gas/doc/c-sh.texi

   1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @page
   6 @node SH-Dependent
   7 @chapter Hitachi SH Dependent Features
   8
   9 @cindex SH support
  10 @menu
  11 * SH Options::              Options
  12 * SH Syntax::               Syntax
  13 * SH Floating Point::       Floating Point
  14 * SH Directives::           SH Machine Directives
  15 * SH Opcodes::              Opcodes
  16 @end menu
  17
  18 @node SH Options
  19 @section Options
  20
  21 @cindex SH options (none)
  22 @cindex options, SH (none)
  23 @code{@value{AS}} has no additional command-line options for the Hitachi
  24 SH family.
  25
  26 @node SH Syntax
  27 @section Syntax
  28
  29 @menu
  30 * SH-Chars::                Special Characters
  31 * SH-Regs::                 Register Names
  32 * SH-Addressing::           Addressing Modes
  33 @end menu
  34
  35 @node SH-Chars
  36 @subsection Special Characters
  37
  38 @cindex line comment character, SH
  39 @cindex SH line comment character
  40 @samp{!} is the line comment character.
  41
  42 @cindex line separator, SH
  43 @cindex statement separator, SH
  44 @cindex SH line separator
  45 You can use @samp{;} instead of a newline to separate statements.
  46
  47 @cindex symbol names, @samp{$} in
  48 @cindex @code{$} in symbol names
  49 Since @samp{$} has no special meaning, you may use it in symbol names.
  50
  51 @node SH-Regs
  52 @subsection Register Names
  53
  54 @cindex SH registers
  55 @cindex registers, SH
  56 You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
  57 @samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
  58 @samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
  59 and @samp{r15} to refer to the SH registers.
  60
  61 The SH also has these control registers:
  62
  63 @table @code
  64 @item pr
  65 procedure register (holds return address)
  66
  67 @item pc
  68 program counter
  69
  70 @item mach
  71 @itemx macl
  72 high and low multiply accumulator registers
  73
  74 @item sr
  75 status register
  76
  77 @item gbr
  78 global base register
  79
  80 @item vbr
  81 vector base register (for interrupt vectors)
  82 @end table
  83
  84 @node SH-Addressing
  85 @subsection Addressing Modes
  86
  87 @cindex addressing modes, SH
  88 @cindex SH addressing modes
  89 @code{@value{AS}} understands the following addressing modes for the SH.
  90 @code{R@var{n}} in the following refers to any of the numbered
  91 registers, but @emph{not} the control registers.
  92
  93 @table @code
  94 @item R@var{n}
  95 Register direct
  96
  97 @item @@R@var{n}
  98 Register indirect
  99
 100 @item @@-R@var{n}
 101 Register indirect with pre-decrement
 102
 103 @item @@R@var{n}+
 104 Register indirect with post-increment
 105
 106 @item @@(@var{disp}, R@var{n})
 107 Register indirect with displacement
 108
 109 @item @@(R0, R@var{n})
 110 Register indexed
 111
 112 @item @@(@var{disp}, GBR)
 113 @code{GBR} offset
 114
 115 @item @@(R0, GBR)
 116 GBR indexed
 117
 118 @item @var{addr}
 119 @itemx @@(@var{disp}, PC)
 120 PC relative address (for branch or for addressing memory).  The
 121 @code{@value{AS}} implementation allows you to use the simpler form
 122 @var{addr} anywhere a PC relative address is called for; the alternate
 123 form is supported for compatibility with other assemblers.
 124
 125 @item #@var{imm}
 126 Immediate data
 127 @end table
 128
 129 @node SH Floating Point
 130 @section Floating Point
 131
 132 @cindex floating point, SH (@sc{ieee})
 133 @cindex SH floating point (@sc{ieee})
 134 The SH family has no hardware floating point, but the @code{.float}
 135 directive generates @sc{ieee} floating-point numbers for compatibility
 136 with other development tools.
 137
 138 @node SH Directives
 139 @section SH Machine Directives
 140
 141 @cindex SH machine directives
 142 @cindex machine directives, SH
 143 @cindex @code{uaword} directive, SH
 144 @cindex @code{ualong} directive, SH
 145
 146 @table @code
 147 @item uaword
 148 @itemx ualong
 149 @code{@value{AS}} will issue a warning when a misaligned @code{.word} or
 150 @code{.long} directive is used.  You may use @code{.uaword} or
 151 @code{.ualong} to indicate that the value is intentionally misaligned.
 152 @end table
 153
 154 @node SH Opcodes
 155 @section Opcodes
 156
 157 @cindex SH opcode summary
 158 @cindex opcode summary, SH
 159 @cindex mnemonics, SH
 160 @cindex instruction summary, SH
 161 For detailed information on the SH machine instruction set, see
 162 @cite{SH-Microcomputer User's Manual} (Hitachi Micro Systems, Inc.).
 163
 164 @code{@value{AS}} implements all the standard SH opcodes.  No additional
 165 pseudo-instructions are needed on this family.  Note, however, that
 166 because @code{@value{AS}} supports a simpler form of PC-relative
 167 addressing, you may simply write (for example)
 168
 169 @example
 170 mov.l  bar,r0
 171 @end example
 172
 173 @noindent
 174 where other assemblers might require an explicit displacement to
 175 @code{bar} from the program counter:
 176
 177 @example
 178 mov.l  @@(@var{disp}, PC)
 179 @end example
 180
 181 @ifset SMALL
 182 @c this table, due to the multi-col faking and hardcoded order, looks silly
 183 @c except in smallbook.  See comments below "@set SMALL" near top of this file.
 184
 185 Here is a summary of SH opcodes:
 186
 187 @page
 188 @smallexample
 189 @i{Legend:}
 190 Rn        @r{a numbered register}
 191 Rm        @r{another numbered register}
 192 #imm      @r{immediate data}
 193 disp      @r{displacement}
 194 disp8     @r{8-bit displacement}
 195 disp12    @r{12-bit displacement}
 196
 197 add #imm,Rn                    lds.l @@Rn+,PR
 198 add Rm,Rn                      mac.w @@Rm+,@@Rn+
 199 addc Rm,Rn                     mov #imm,Rn
 200 addv Rm,Rn                     mov Rm,Rn
 201 and #imm,R0                    mov.b Rm,@@(R0,Rn)
 202 and Rm,Rn                      mov.b Rm,@@-Rn
 203 and.b #imm,@@(R0,GBR)           mov.b Rm,@@Rn
 204 bf disp8                       mov.b @@(disp,Rm),R0
 205 bra disp12                     mov.b @@(disp,GBR),R0
 206 bsr disp12                     mov.b @@(R0,Rm),Rn
 207 bt disp8                       mov.b @@Rm+,Rn
 208 clrmac                         mov.b @@Rm,Rn
 209 clrt                           mov.b R0,@@(disp,Rm)
 210 cmp/eq #imm,R0                 mov.b R0,@@(disp,GBR)
 211 cmp/eq Rm,Rn                   mov.l Rm,@@(disp,Rn)
 212 cmp/ge Rm,Rn                   mov.l Rm,@@(R0,Rn)
 213 cmp/gt Rm,Rn                   mov.l Rm,@@-Rn
 214 cmp/hi Rm,Rn                   mov.l Rm,@@Rn
 215 cmp/hs Rm,Rn                   mov.l @@(disp,Rn),Rm
 216 cmp/pl Rn                      mov.l @@(disp,GBR),R0
 217 cmp/pz Rn                      mov.l @@(disp,PC),Rn
 218 cmp/str Rm,Rn                  mov.l @@(R0,Rm),Rn
 219 div0s Rm,Rn                    mov.l @@Rm+,Rn
 220 div0u                          mov.l @@Rm,Rn
 221 div1 Rm,Rn                     mov.l R0,@@(disp,GBR)
 222 exts.b Rm,Rn                   mov.w Rm,@@(R0,Rn)
 223 exts.w Rm,Rn                   mov.w Rm,@@-Rn
 224 extu.b Rm,Rn                   mov.w Rm,@@Rn
 225 extu.w Rm,Rn                   mov.w @@(disp,Rm),R0
 226 jmp @@Rn                        mov.w @@(disp,GBR),R0
 227 jsr @@Rn                        mov.w @@(disp,PC),Rn
 228 ldc Rn,GBR                     mov.w @@(R0,Rm),Rn
 229 ldc Rn,SR                      mov.w @@Rm+,Rn
 230 ldc Rn,VBR                     mov.w @@Rm,Rn
 231 ldc.l @@Rn+,GBR                 mov.w R0,@@(disp,Rm)
 232 ldc.l @@Rn+,SR                  mov.w R0,@@(disp,GBR)
 233 ldc.l @@Rn+,VBR                 mova @@(disp,PC),R0
 234 lds Rn,MACH                    movt Rn
 235 lds Rn,MACL                    muls Rm,Rn
 236 lds Rn,PR                      mulu Rm,Rn
 237 lds.l @@Rn+,MACH                neg Rm,Rn
 238 lds.l @@Rn+,MACL                negc Rm,Rn
 239 @page
 240 nop                            stc VBR,Rn
 241 not Rm,Rn                      stc.l GBR,@@-Rn
 242 or #imm,R0                     stc.l SR,@@-Rn
 243 or Rm,Rn                       stc.l VBR,@@-Rn
 244 or.b #imm,@@(R0,GBR)            sts MACH,Rn
 245 rotcl Rn                       sts MACL,Rn
 246 rotcr Rn                       sts PR,Rn
 247 rotl Rn                        sts.l MACH,@@-Rn
 248 rotr Rn                        sts.l MACL,@@-Rn
 249 rte                            sts.l PR,@@-Rn
 250 rts                            sub Rm,Rn
 251 sett                           subc Rm,Rn
 252 shal Rn                        subv Rm,Rn
 253 shar Rn                        swap.b Rm,Rn
 254 shll Rn                        swap.w Rm,Rn
 255 shll16 Rn                      tas.b @@Rn
 256 shll2 Rn                       trapa #imm
 257 shll8 Rn                       tst #imm,R0
 258 shlr Rn                        tst Rm,Rn
 259 shlr16 Rn                      tst.b #imm,@@(R0,GBR)
 260 shlr2 Rn                       xor #imm,R0
 261 shlr8 Rn                       xor Rm,Rn
 262 sleep                          xor.b #imm,@@(R0,GBR)
 263 stc GBR,Rn                     xtrct Rm,Rn
 264 stc SR,Rn
 265 @end smallexample
 266 @end ifset
 267
 268 @ifset Hitachi-all
 269 @ifclear GENERIC
 270 @raisesections
 271 @end ifclear
 272 @end ifset
 273