1 @c Copyright (C) 1991-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter SPARC Dependent Features
10 @node Machine Dependencies
11 @chapter SPARC Dependent Features
16 * Sparc-Opts:: Options
17 * Sparc-Aligned-Data:: Option to enforce aligned data
18 * Sparc-Syntax:: Syntax
19 * Sparc-Float:: Floating Point
20 * Sparc-Directives:: Sparc Machine Directives
26 @cindex options for SPARC
28 @cindex architectures, SPARC
29 @cindex SPARC architectures
30 The SPARC chip family includes several successive versions, using the same
31 core instruction set, but including a few additional instructions at
32 each version. There are exceptions to this however. For details on what
33 instructions each variant supports, please see the chip's architecture
36 By default, @code{@value{AS}} assumes the core instruction set (SPARC
37 v6), but ``bumps'' the architecture level as needed: it switches to
38 successively higher architectures as it encounters instructions that
39 only exist in the higher levels.
41 If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
42 past sparclite by default, an option must be passed to enable the
45 GAS treats sparclite as being compatible with v8, unless an architecture
46 is explicitly requested. SPARC v9 is always incompatible with sparclite.
48 @c The order here is the same as the order of enum sparc_opcode_arch_val
49 @c to give the user a sense of the order of the "bumping".
73 @item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
74 @itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
75 @itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m
76 @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
77 @itemx -Asparcvis3 | -Asparcvis3r
78 Use one of the @samp{-A} options to select one of the SPARC
79 architectures explicitly. If you select an architecture explicitly,
80 @code{@value{AS}} reports a fatal error if it encounters an instruction
81 or feature requiring an incompatible or higher level.
83 @samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
84 @samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
86 @samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d},
87 @samp{-Av9e}, @samp{-Av9v} and @samp{-Av9m} select a 64 bit
88 environment and are not available unless GAS is explicitly configured
89 with 64 bit environment support.
91 @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
92 UltraSPARC VIS 1.0 extensions.
94 @samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions,
95 as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}.
97 @samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions,
98 as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
100 @samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused
101 multiply-add, VIS 3.0, and HPC extension instructions, as well as the
102 instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
104 @samp{-Av8pluse} and @samp{-Av9e} enable the cryptographic
105 instructions, as well as the instructions enabled by @samp{-Av8plusd}
108 @samp{-Av8plusv} and @samp{-Av9v} enable floating point unfused
109 multiply-add, and integer multiply-add, as well as the instructions
110 enabled by @samp{-Av8pluse} and @samp{-Av9e}.
112 @samp{-Av8plusm} and @samp{-Av9m} enable the VIS 4.0, subtract extended,
113 xmpmul, xmontmul and xmontsqr instructions, as well as the instructions
114 enabled by @samp{-Av8plusv} and @samp{-Av9v}.
116 @samp{-Asparc} specifies a v9 environment. It is equivalent to
117 @samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
119 @samp{-Asparcvis} specifies a v9a environment. It is equivalent to
120 @samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise.
122 @samp{-Asparcvis2} specifies a v9b environment. It is equivalent to
123 @samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise.
125 @samp{-Asparcfmaf} specifies a v9b environment with the floating point
126 fused multiply-add instructions enabled.
128 @samp{-Asparcima} specifies a v9b environment with the integer
129 multiply-add instructions enabled.
131 @samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
132 HPC , and floating point fused multiply-add instructions enabled.
134 @samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, HPC,
135 and floating point unfused multiply-add instructions enabled.
137 @samp{-Asparc5} is equivalent to @samp{-Av9m}.
139 @item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
140 @itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
141 @itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m
142 @itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
143 @itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
144 @itemx -xarch=sparcvis3r | -xarch=sparc5
145 For compatibility with the SunOS v9 assembler. These options are
146 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
147 -Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m,
148 -Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima,
149 -Asparcvis3, and -Asparcvis3r, respectively.
152 Warn whenever it is necessary to switch to another level.
153 If an architecture level is explicitly requested, GAS will not issue
154 warnings until that level is reached, and will then bump the level
155 as required (except between incompatible levels).
158 Select the word size, either 32 bits or 64 bits.
159 These options are only available with the ELF object file format,
160 and require that the necessary BFD support has been included.
163 @node Sparc-Aligned-Data
164 @section Enforcing aligned data
166 @cindex data alignment on SPARC
167 @cindex SPARC data alignment
168 SPARC GAS normally permits data to be misaligned. For example, it
169 permits the @code{.long} pseudo-op to be used on a byte boundary.
170 However, the native SunOS assemblers issue an error when they see
173 @kindex --enforce-aligned-data
174 You can use the @code{--enforce-aligned-data} option to make SPARC GAS
175 also issue an error about misaligned data, just as the SunOS
178 The @code{--enforce-aligned-data} option is not the default because gcc
179 issues misaligned data pseudo-ops when it initializes certain packed
180 data structures (structures defined using the @code{packed} attribute).
181 You may have to assemble with GAS in order to initialize packed data
182 structures in your own code.
185 @cindex syntax, SPARC
187 @section Sparc Syntax
188 The assembler syntax closely follows The Sparc Architecture Manual,
189 versions 8 and 9, as well as most extensions defined by Sun
190 for their UltraSPARC and Niagara line of processors.
193 * Sparc-Chars:: Special Characters
194 * Sparc-Regs:: Register Names
195 * Sparc-Constants:: Constant Names
196 * Sparc-Relocs:: Relocations
197 * Sparc-Size-Translations:: Size Translations
201 @subsection Special Characters
203 @cindex line comment character, Sparc
204 @cindex Sparc line comment character
205 A @samp{!} character appearing anywhere on a line indicates the start
206 of a comment that extends to the end of that line.
208 If a @samp{#} appears as the first character of a line then the whole
209 line is treated as a comment, but in this case the line could also be
210 a logical line number directive (@pxref{Comments}) or a preprocessor
211 control command (@pxref{Preprocessing}).
213 @cindex line separator, Sparc
214 @cindex statement separator, Sparc
215 @cindex Sparc line separator
216 @samp{;} can be used instead of a newline to separate statements.
219 @subsection Register Names
220 @cindex Sparc registers
221 @cindex register names, Sparc
223 The Sparc integer register file is broken down into global,
224 outgoing, local, and incoming.
228 The 8 global registers are referred to as @samp{%g@var{n}}.
231 The 8 outgoing registers are referred to as @samp{%o@var{n}}.
234 The 8 local registers are referred to as @samp{%l@var{n}}.
237 The 8 incoming registers are referred to as @samp{%i@var{n}}.
240 The frame pointer register @samp{%i6} can be referenced using
241 the alias @samp{%fp}.
244 The stack pointer register @samp{%o6} can be referenced using
245 the alias @samp{%sp}.
248 Floating point registers are simply referred to as @samp{%f@var{n}}.
249 When assembling for pre-V9, only 32 floating point registers
250 are available. For V9 and later there are 64, but there are
251 restrictions when referencing the upper 32 registers. They
252 can only be accessed as double or quad, and thus only even
253 or quad numbered accesses are allowed. For example, @samp{%f34}
254 is a legal floating point register, but @samp{%f35} is not.
256 Certain V9 instructions allow access to ancillary state registers.
257 Most simply they can be referred to as @samp{%asr@var{n}} where
258 @var{n} can be from 16 to 31. However, there are some aliases
259 defined to reference ASR registers defined for various UltraSPARC
264 The tick compare register is referred to as @samp{%tick_cmpr}.
267 The system tick register is referred to as @samp{%stick}. An alias,
268 @samp{%sys_tick}, exists but is deprecated and should not be used
272 The system tick compare register is referred to as @samp{%stick_cmpr}.
273 An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should
274 not be used by new software.
277 The software interrupt register is referred to as @samp{%softint}.
280 The set software interrupt register is referred to as @samp{%set_softint}.
281 The mnemonic @samp{%softint_set} is provided as an alias.
284 The clear software interrupt register is referred to as
285 @samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided
289 The performance instrumentation counters register is referred to as
293 The performance control register is referred to as @samp{%pcr}.
296 The graphics status register is referred to as @samp{%gsr}.
299 The V9 dispatch control register is referred to as @samp{%dcr}.
302 Various V9 branch and conditional move instructions allow
303 specification of which set of integer condition codes to
304 test. These are referred to as @samp{%xcc} and @samp{%icc}.
306 Additionally, GAS supports the so-called ``natural'' condition codes;
307 these are referred to as @samp{%ncc} and reference to @samp{%icc} if
308 the word size is 32, @samp{%xcc} if the word size is 64.
310 In V9, there are 4 sets of floating point condition codes
311 which are referred to as @samp{%fcc@var{n}}.
313 Several special privileged and non-privileged registers
318 The V9 address space identifier register is referred to as @samp{%asi}.
321 The V9 restorable windows register is referred to as @samp{%canrestore}.
324 The V9 savable windows register is referred to as @samp{%cansave}.
327 The V9 clean windows register is referred to as @samp{%cleanwin}.
330 The V9 current window pointer register is referred to as @samp{%cwp}.
333 The floating-point queue register is referred to as @samp{%fq}.
336 The V8 co-processor queue register is referred to as @samp{%cq}.
339 The floating point status register is referred to as @samp{%fsr}.
342 The other windows register is referred to as @samp{%otherwin}.
345 The V9 program counter register is referred to as @samp{%pc}.
348 The V9 next program counter register is referred to as @samp{%npc}.
351 The V9 processor interrupt level register is referred to as @samp{%pil}.
354 The V9 processor state register is referred to as @samp{%pstate}.
357 The trap base address register is referred to as @samp{%tba}.
360 The V9 tick register is referred to as @samp{%tick}.
363 The V9 trap level is referred to as @samp{%tl}.
366 The V9 trap program counter is referred to as @samp{%tpc}.
369 The V9 trap next program counter is referred to as @samp{%tnpc}.
372 The V9 trap state is referred to as @samp{%tstate}.
375 The V9 trap type is referred to as @samp{%tt}.
378 The V9 condition codes is referred to as @samp{%ccr}.
381 The V9 floating-point registers state is referred to as @samp{%fprs}.
384 The V9 version register is referred to as @samp{%ver}.
387 The V9 window state register is referred to as @samp{%wstate}.
390 The Y register is referred to as @samp{%y}.
393 The V8 window invalid mask register is referred to as @samp{%wim}.
396 The V8 processor state register is referred to as @samp{%psr}.
399 The V9 global register level register is referred to as @samp{%gl}.
402 Several special register names exist for hypervisor mode code:
406 The hyperprivileged processor state register is referred to as
410 The hyperprivileged trap state register is referred to as @samp{%htstate}.
413 The hyperprivileged interrupt pending register is referred to as
417 The hyperprivileged trap base address register is referred to as
421 The hyperprivileged implementation version register is referred
425 The hyperprivileged system tick offset register is referred to as
426 @samp{%hstick_offset}. Note that there is no @samp{%hstick} register,
427 the normal @samp{%stick} is used.
430 The hyperprivileged system tick enable register is referred to as
431 @samp{%hstick_enable}.
434 The hyperprivileged system tick compare register is referred
435 to as @samp{%hstick_cmpr}.
438 @node Sparc-Constants
439 @subsection Constants
440 @cindex Sparc constants
441 @cindex constants, Sparc
443 Several Sparc instructions take an immediate operand field for
444 which mnemonic names exist. Two such examples are @samp{membar}
445 and @samp{prefetch}. Another example are the set of V9
446 memory access instruction that allow specification of an
447 address space identifier.
449 The @samp{membar} instruction specifies a memory barrier that is
450 the defined by the operand which is a bitmask. The supported
455 @samp{#Sync} requests that all operations (including nonmemory
456 reference operations) appearing prior to the @code{membar} must have
457 been performed and the effects of any exceptions become visible before
458 any instructions after the @code{membar} may be initiated. This
459 corresponds to @code{membar} cmask field bit 2.
462 @samp{#MemIssue} requests that all memory reference operations
463 appearing prior to the @code{membar} must have been performed before
464 any memory operation after the @code{membar} may be initiated. This
465 corresponds to @code{membar} cmask field bit 1.
468 @samp{#Lookaside} requests that a store appearing prior to the
469 @code{membar} must complete before any load following the
470 @code{membar} referencing the same address can be initiated. This
471 corresponds to @code{membar} cmask field bit 0.
474 @samp{#StoreStore} defines that the effects of all stores appearing
475 prior to the @code{membar} instruction must be visible to all
476 processors before the effect of any stores following the
477 @code{membar}. Equivalent to the deprecated @code{stbar} instruction.
478 This corresponds to @code{membar} mmask field bit 3.
481 @samp{#LoadStore} defines all loads appearing prior to the
482 @code{membar} instruction must have been performed before the effect
483 of any stores following the @code{membar} is visible to any other
484 processor. This corresponds to @code{membar} mmask field bit 2.
487 @samp{#StoreLoad} defines that the effects of all stores appearing
488 prior to the @code{membar} instruction must be visible to all
489 processors before loads following the @code{membar} may be performed.
490 This corresponds to @code{membar} mmask field bit 1.
493 @samp{#LoadLoad} defines that all loads appearing prior to the
494 @code{membar} instruction must have been performed before any loads
495 following the @code{membar} may be performed. This corresponds to
496 @code{membar} mmask field bit 0.
500 These values can be ored together, for example:
504 membar #StoreLoad | #LoadLoad
505 membar #StoreLoad | #StoreStore
508 The @code{prefetch} and @code{prefetcha} instructions take a prefetch
509 function code. The following prefetch function code constant
510 mnemonics are available:
514 @samp{#n_reads} requests a prefetch for several reads, and corresponds
515 to a prefetch function code of 0.
517 @samp{#one_read} requests a prefetch for one read, and corresponds
518 to a prefetch function code of 1.
520 @samp{#n_writes} requests a prefetch for several writes (and possibly
521 reads), and corresponds to a prefetch function code of 2.
523 @samp{#one_write} requests a prefetch for one write, and corresponds
524 to a prefetch function code of 3.
526 @samp{#page} requests a prefetch page, and corresponds to a prefetch
529 @samp{#invalidate} requests a prefetch invalidate, and corresponds to
530 a prefetch function code of 16.
532 @samp{#unified} requests a prefetch to the nearest unified cache, and
533 corresponds to a prefetch function code of 17.
535 @samp{#n_reads_strong} requests a strong prefetch for several reads,
536 and corresponds to a prefetch function code of 20.
538 @samp{#one_read_strong} requests a strong prefetch for one read,
539 and corresponds to a prefetch function code of 21.
541 @samp{#n_writes_strong} requests a strong prefetch for several writes,
542 and corresponds to a prefetch function code of 22.
544 @samp{#one_write_strong} requests a strong prefetch for one write,
545 and corresponds to a prefetch function code of 23.
547 Onle one prefetch code may be specified. Here are some examples:
550 prefetch [%l0 + %l2], #one_read
551 prefetch [%g2 + 8], #n_writes
552 prefetcha [%g1] 0x8, #unified
553 prefetcha [%o0 + 0x10] %asi, #n_reads
556 The actual behavior of a given prefetch function code is processor
557 specific. If a processor does not implement a given prefetch
558 function code, it will treat the prefetch instruction as a nop.
560 For instructions that accept an immediate address space identifier,
561 @code{@value{AS}} provides many mnemonics corresponding to
562 V9 defined as well as UltraSPARC and Niagara extended values.
563 For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}.
564 See the V9 and processor specific manuals for details.
569 @subsection Relocations
570 @cindex Sparc relocations
571 @cindex relocations, Sparc
573 ELF relocations are available as defined in the 32-bit and 64-bit
574 Sparc ELF specifications.
576 @code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10}
577 is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is
578 obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained
579 using @samp{%lox}. For example:
582 sethi %hi(symbol), %g1
583 or %g1, %lo(symbol), %g1
585 sethi %hix(symbol), %g1
586 xor %g1, %lox(symbol), %g1
589 These ``high'' mnemonics extract bits 31:10 of their operand,
590 and the ``low'' mnemonics extract bits 9:0 of their operand.
592 V9 code model relocations can be requested as follows:
596 @code{R_SPARC_HH22} is requested using @samp{%hh}. It can
597 also be generated using @samp{%uhi}.
599 @code{R_SPARC_HM10} is requested using @samp{%hm}. It can
600 also be generated using @samp{%ulo}.
602 @code{R_SPARC_LM22} is requested using @samp{%lm}.
605 @code{R_SPARC_H44} is requested using @samp{%h44}.
607 @code{R_SPARC_M44} is requested using @samp{%m44}.
609 @code{R_SPARC_L44} is requested using @samp{%l44} or @samp{%l34}.
611 @code{R_SPARC_H34} is requested using @samp{%h34}.
614 The @samp{%l34} generates a @code{R_SPARC_L44} relocation because it
615 calculates the necessary value, and therefore no explicit
616 @code{R_SPARC_L34} relocation needed to be created for this purpose.
618 The @samp{%h34} and @samp{%l34} relocations are used for the abs34 code
619 model. Here is an example abs34 address generation sequence:
622 sethi %h34(symbol), %g1
624 or %g1, %l34(symbol), %g1
627 The PC relative relocation @code{R_SPARC_PC22} can be obtained by
628 enclosing an operand inside of @samp{%pc22}. Likewise, the
629 @code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}.
630 These are mostly used when assembling PIC code. For example, the
631 standard PIC sequence on Sparc to get the base of the global offset
632 table, PC relative, into a register, can be performed as:
635 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
636 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
639 Several relocations exist to allow the link editor to potentially
640 optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22}
641 relocation can obtained by enclosing an operand inside of
642 @samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10}
643 relocation can obtained by enclosing an operand inside of
644 @samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be
645 obtained by enclosing an operand inside of @samp{%gdop}.
646 For example, assuming the GOT base is in register @code{%l7}:
649 sethi %gdop_hix22(symbol), %l1
650 xor %l1, %gdop_lox10(symbol), %l1
651 ld [%l7 + %l1], %l2, %gdop(symbol)
654 There are many relocations that can be requested for access to
655 thread local storage variables. All of the Sparc TLS mnemonics
660 @code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}.
662 @code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}.
664 @code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}.
666 @code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}.
669 @code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}.
671 @code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}.
673 @code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}.
675 @code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}.
678 @code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}.
680 @code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}.
682 @code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}.
685 @code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}.
687 @code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}.
689 @code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}.
691 @code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}.
693 @code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}.
696 @code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}.
698 @code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}.
701 Here are some example TLS model sequences.
703 First, General Dynamic:
706 sethi %tgd_hi22(symbol), %l1
707 add %l1, %tgd_lo10(symbol), %l1
708 add %l7, %l1, %o0, %tgd_add(symbol)
709 call __tls_get_addr, %tgd_call(symbol)
716 sethi %tldm_hi22(symbol), %l1
717 add %l1, %tldm_lo10(symbol), %l1
718 add %l7, %l1, %o0, %tldm_add(symbol)
719 call __tls_get_addr, %tldm_call(symbol)
722 sethi %tldo_hix22(symbol), %l1
723 xor %l1, %tldo_lox10(symbol), %l1
724 add %o0, %l1, %l1, %tldo_add(symbol)
730 sethi %tie_hi22(symbol), %l1
731 add %l1, %tie_lo10(symbol), %l1
732 ld [%l7 + %l1], %o0, %tie_ld(symbol)
733 add %g7, %o0, %o0, %tie_add(symbol)
735 sethi %tie_hi22(symbol), %l1
736 add %l1, %tie_lo10(symbol), %l1
737 ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
738 add %g7, %o0, %o0, %tie_add(symbol)
741 And finally, Local Exec:
744 sethi %tle_hix22(symbol), %l1
745 add %l1, %tle_lox10(symbol), %l1
749 When assembling for 64-bit, and a secondary constant addend is
750 specified in an address expression that would normally generate
751 an @code{R_SPARC_LO10} relocation, the assembler will emit an
752 @code{R_SPARC_OLO10} instead.
754 @node Sparc-Size-Translations
755 @subsection Size Translations
756 @cindex Sparc size translations
757 @cindex size, translations, Sparc
759 Often it is desirable to write code in an operand size agnostic
760 manner. @code{@value{AS}} provides support for this via
761 operand size opcode translations. Translations are supported
762 for loads, stores, shifts, compare-and-swap atomics, and the
763 @samp{clr} synthetic instruction.
765 If generating 32-bit code, @code{@value{AS}} will generate the
766 32-bit opcode. Whereas if 64-bit code is being generated,
767 the 64-bit opcode will be emitted. For example @code{ldn}
768 will be transformed into @code{ld} for 32-bit code and
769 @code{ldx} for 64-bit code.
771 Here is an example meant to demonstrate all the supported
783 casna [%o0] %asi, %o1, %o2
787 In 32-bit mode @code{@value{AS}} will emit:
798 casa [%o0] %asi, %o1, %o2
802 And in 64-bit mode @code{@value{AS}} will emit:
813 casxa [%o0] %asi, %o1, %o2
817 Finally, the @samp{.nword} translating directive is supported
818 as well. It is documented in the section on Sparc machine
822 @section Floating Point
824 @cindex floating point, SPARC (@sc{ieee})
825 @cindex SPARC floating point (@sc{ieee})
826 The Sparc uses @sc{ieee} floating-point numbers.
828 @node Sparc-Directives
829 @section Sparc Machine Directives
831 @cindex SPARC machine directives
832 @cindex machine directives, SPARC
833 The Sparc version of @code{@value{AS}} supports the following additional
837 @cindex @code{align} directive, SPARC
839 This must be followed by the desired alignment in bytes.
841 @cindex @code{common} directive, SPARC
843 This must be followed by a symbol name, a positive number, and
844 @code{"bss"}. This behaves somewhat like @code{.comm}, but the
847 @cindex @code{half} directive, SPARC
849 This is functionally identical to @code{.short}.
851 @cindex @code{nword} directive, SPARC
853 On the Sparc, the @code{.nword} directive produces native word sized value,
854 ie. if assembling with -32 it is equivalent to @code{.word}, if assembling
855 with -64 it is equivalent to @code{.xword}.
857 @cindex @code{proc} directive, SPARC
859 This directive is ignored. Any text following it on the same
860 line is also ignored.
862 @cindex @code{register} directive, SPARC
864 This directive declares use of a global application or system register.
865 It must be followed by a register name %g2, %g3, %g6 or %g7, comma and
866 the symbol name for that register. If symbol name is @code{#scratch},
867 it is a scratch register, if it is @code{#ignore}, it just suppresses any
868 errors about using undeclared global register, but does not emit any
869 information about it into the object file. This can be useful e.g. if you
870 save the register before use and restore it after.
872 @cindex @code{reserve} directive, SPARC
874 This must be followed by a symbol name, a positive number, and
875 @code{"bss"}. This behaves somewhat like @code{.lcomm}, but the
878 @cindex @code{seg} directive, SPARC
880 This must be followed by @code{"text"}, @code{"data"}, or
881 @code{"data1"}. It behaves like @code{.text}, @code{.data}, or
884 @cindex @code{skip} directive, SPARC
886 This is functionally identical to the @code{.space} directive.
888 @cindex @code{word} directive, SPARC
890 On the Sparc, the @code{.word} directive produces 32 bit values,
891 instead of the 16 bit values it produces on many other machines.
893 @cindex @code{xword} directive, SPARC
895 On the Sparc V9 processor, the @code{.xword} directive produces