1 # Print a 4 operand instruction
2 .macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w , pw1=, pw2=
4 \op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
7 \op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
9 \op \pm1\m\()\pm2, \pw1\w\()\pw2
14 .macro gen4reg_iter_d_offset op, d, pd1=, pd2=, r
16 \op \pd1\d\()\pd2, [\r, \m]
20 .macro gen4reg_iter_d_n_w op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, pw1=, pw2=
22 print_gen4reg \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \w, \pw1, \pw2
26 .macro gen4reg_iter_d_n op, d, pd1=, pd2=, n, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
28 gen4reg_iter_d_n_w \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \pw1, \pw2
32 .macro gen4reg_iter_d op, d, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
34 gen4reg_iter_d_n \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
38 .macro gen4reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
40 gen4reg_iter_d \op, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
44 # Print a 3 operand instruction
45 .macro gen3reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=
47 gen4reg_iter_d \op,,, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2
51 .macro gen3reg_iter_lane op, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=, x:vararg
53 gen4reg_iter_d \op,,,, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2[\l]
57 # Print a 2 operand instruction
58 .macro gen2reg_iter op, pd1=, pd2=, pn1=, pn2=
60 gen4reg_iter_d_n \op,,,,,, \d, \pd1, \pd2, \pn1, \pn2
64 .macro gen2reg_iter_offset op, pd1=, pd2=, r
66 gen4reg_iter_d_offset \op, \d, \pd1, \pd2, \r,
70 # Print a 1 operand instruction
71 .macro gen1reg_iter op, pd1=, pd2=
79 gen3reg_iter sha512h q,, q,, v,.2d
80 gen3reg_iter sha512h2 q,, q,, v,.2d
81 gen2reg_iter sha512su0 v,.2d, v,.2d
82 gen3reg_iter sha512su1 v,.2d, v,.2d, v,.2d
83 gen4reg_iter eor3 v,.16b, v,.16b, v,.16b, v,.16b
84 gen3reg_iter rax1 v,.2d, v,.2d, v,.2d
85 gen4reg_iter xar v,.2d, v,.2d, v,.2d,,
86 gen4reg_iter bcax v,.16b, v,.16b, v,.16b, v,.16b
88 gen4reg_iter sm3ss1 v,.4s, v,.4s, v,.4s, v,.4s
89 gen3reg_iter_lane sm3tt1a v,.4s, v,.4s, v,.s, 0, 1, 2, 3
90 gen3reg_iter_lane sm3tt1b v,.4s, v,.4s, v,.s, 0, 1, 2, 3
91 gen3reg_iter_lane sm3tt2a v,.4s, v,.4s, v,.s, 0, 1, 2, 3
92 gen3reg_iter_lane sm3tt2b v,.4s, v,.4s, v,.s, 0, 1, 2, 3
93 gen3reg_iter sm3partw1 v,.4s, v,.4s, v,.4s
94 gen3reg_iter sm3partw2 v,.4s, v,.4s, v,.4s
96 gen2reg_iter sm4e v,.4s, v,.4s
97 gen3reg_iter sm4ekey v,.4s, v,.4s, v,.4s
99 gen3reg_iter fmlal v,.2s, v,.2h, v,.2h
100 gen3reg_iter fmlal v,.4s, v,.4h, v,.4h
101 gen3reg_iter fmlsl v,.2s, v,.2h, v,.2h
102 gen3reg_iter fmlsl v,.4s, v,.4h, v,.4h
104 gen3reg_iter fmlal2 v,.2s, v,.2h, v,.2h
105 gen3reg_iter fmlal2 v,.4s, v,.4h, v,.4h
106 gen3reg_iter fmlsl2 v,.2s, v,.2h, v,.2h
107 gen3reg_iter fmlsl2 v,.4s, v,.4h, v,.4h
109 gen3reg_iter_lane fmlal v,.2s, v,.2h, v,.h, 0, 1, 5, 7
110 gen3reg_iter_lane fmlal v,.4s, v,.4h, v,.h, 0, 1, 5, 7
111 gen3reg_iter_lane fmlsl v,.2s, v,.2h, v,.h, 0, 1, 5, 7
112 gen3reg_iter_lane fmlsl v,.4s, v,.4h, v,.h, 0, 1, 5, 7
114 gen3reg_iter_lane fmlal2 v,.2s, v,.2h, v,.h, 0, 1, 5, 7
115 gen3reg_iter_lane fmlal2 v,.4s, v,.4h, v,.h, 0, 1, 5, 7
116 gen3reg_iter_lane fmlsl2 v,.2s, v,.2h, v,.h, 0, 1, 5, 7
117 gen3reg_iter_lane fmlsl2 v,.4s, v,.4h, v,.h, 0, 1, 5, 7