[binutils][aarch64] Bfloat16 enablement [2/X]
[binutils-gdb.git] / gas / testsuite / gas / aarch64 / sysreg-4.d
1 #source: sysreg-4.s
2 #as: -march=armv8.5-a+rng+memtag
3 #objdump: -dr
4
5 .*: file format .*
6
7 Disassembly of section \.text:
8
9 0+ <.*>:
10 .*: d50b7381 cfp rctx, x1
11 .*: d50b73a2 dvp rctx, x2
12 .*: d50b73e3 cpp rctx, x3
13 .*: d50b7d24 dc cvadp, x4
14 .*: d53b2405 mrs x5, rndr
15 .*: d53b2426 mrs x6, rndrrs
16 .*: d53bd0e7 mrs x7, scxtnum_el0
17 .*: d538d0e7 mrs x7, scxtnum_el1
18 .*: d53cd0e7 mrs x7, scxtnum_el2
19 .*: d53ed0e7 mrs x7, scxtnum_el3
20 .*: d53dd0e7 mrs x7, scxtnum_el12
21 .*: d5380388 mrs x8, id_pfr2_el1
22 .*: d53b42e1 mrs x1, tco
23 .*: d53b42e2 mrs x2, tco
24 .*: d5385621 mrs x1, tfsre0_el1
25 .*: d5385601 mrs x1, tfsr_el1
26 .*: d53c5602 mrs x2, tfsr_el2
27 .*: d53e5603 mrs x3, tfsr_el3
28 .*: d53d560c mrs x12, tfsr_el12
29 .*: d53810a1 mrs x1, rgsr_el1
30 .*: d53810c3 mrs x3, gcr_el1
31 .*: d5390084 mrs x4, gmid_el1
32 .*: d51b42e1 msr tco, x1
33 .*: d51b42e2 msr tco, x2
34 .*: d5185621 msr tfsre0_el1, x1
35 .*: d5185601 msr tfsr_el1, x1
36 .*: d51c5602 msr tfsr_el2, x2
37 .*: d51e5603 msr tfsr_el3, x3
38 .*: d51d560c msr tfsr_el12, x12
39 .*: d51810a1 msr rgsr_el1, x1
40 .*: d51810c3 msr gcr_el1, x3
41 .*: d503489f msr tco, #0x8
42 .*: d5087661 dc igvac, x1
43 .*: d5087682 dc igsw, x2
44 .*: d5087a83 dc cgsw, x3
45 .*: d5087e84 dc cigsw, x4
46 .*: d50b7a65 dc cgvac, x5
47 .*: d50b7c66 dc cgvap, x6
48 .*: d50b7d67 dc cgvadp, x7
49 .*: d50b7e68 dc cigvac, x8
50 .*: d50b7469 dc gva, x9
51 .*: d50876aa dc igdvac, x10
52 .*: d50876cb dc igdsw, x11
53 .*: d5087acc dc cgdsw, x12
54 .*: d5087ecd dc cigdsw, x13
55 .*: d50b7aae dc cgdvac, x14
56 .*: d50b7caf dc cgdvap, x15
57 .*: d50b7db0 dc cgdvadp, x16
58 .*: d50b7eb1 dc cigdvac, x17
59 .*: d50b7492 dc gzva, x18