RISC-V: Clarify the behavior of .option arch directive.
[binutils-gdb.git] / gas / testsuite / gas / riscv / k-ext-64.d
1 #as: -march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
2 #source: k-ext-64.s
3 #objdump: -d
4
5 .*:[ ]+file format .*
6
7
8 Disassembly of section .text:
9
10 0+000 <target>:
11 [ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
12 [ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
13 [ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
14 [ ]+.*:[ ]+.*[ ]+rorw[ ]+a0,a1,a2
15 [ ]+.*:[ ]+.*[ ]+rolw[ ]+a0,a1,a2
16 [ ]+.*:[ ]+.*[ ]+roriw[ ]+a0,a1,0x2
17 [ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
18 [ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
19 [ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
20 [ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
21 [ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
22 [ ]+.*:[ ]+.*[ ]+packw[ ]+a0,a1,a2
23 [ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
24 [ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
25 [ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
26 [ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
27 [ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
28 [ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
29 [ ]+.*:[ ]+.*[ ]+aes64ds[ ]+a0,a1,a2
30 [ ]+.*:[ ]+.*[ ]+aes64dsm[ ]+a0,a1,a2
31 [ ]+.*:[ ]+.*[ ]+aes64im[ ]+a0,a0
32 [ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
33 [ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
34 [ ]+.*:[ ]+.*[ ]+aes64es[ ]+a0,a1,a2
35 [ ]+.*:[ ]+.*[ ]+aes64esm[ ]+a0,a1,a2
36 [ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
37 [ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
38 [ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
39 [ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
40 [ ]+.*:[ ]+.*[ ]+sha512sig0[ ]+a0,a0
41 [ ]+.*:[ ]+.*[ ]+sha512sig1[ ]+a0,a0
42 [ ]+.*:[ ]+.*[ ]+sha512sum0[ ]+a0,a0
43 [ ]+.*:[ ]+.*[ ]+sha512sum1[ ]+a0,a0
44 [ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
45 [ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
46 [ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
47 [ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0