RISC-V: Support svinval extension with frozen version 1.0.
[binutils-gdb.git] / gas / testsuite / gas / riscv / priv-reg-pseudo.d
1 #source: priv-reg-pseudo.s
2 #as: -march=rv32if
3 #objdump: -dr
4
5 .*:[ ]+file format .*
6
7
8 Disassembly of section .text:
9
10 0+000 <pseudo_csr_insn>:
11 [ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrr[ ]+t0,ustatus
12 [ ]+[0-9a-f]+:[ ]+00029073[ ]+csrw[ ]+ustatus,t0
13 [ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrs[ ]+ustatus,t0
14 [ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrc[ ]+ustatus,t0
15 [ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrwi[ ]+ustatus,31
16 [ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrsi[ ]+ustatus,31
17 [ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrci[ ]+ustatus,31
18 [ ]+[0-9a-f]+:[ ]+c00022f3[ ]+rdcycle[ ]+t0
19 [ ]+[0-9a-f]+:[ ]+c01022f3[ ]+rdtime[ ]+t0
20 [ ]+[0-9a-f]+:[ ]+c02022f3[ ]+rdinstret[ ]+t0
21 [ ]+[0-9a-f]+:[ ]+c80022f3[ ]+rdcycleh[ ]+t0
22 [ ]+[0-9a-f]+:[ ]+c81022f3[ ]+rdtimeh[ ]+t0
23 [ ]+[0-9a-f]+:[ ]+c82022f3[ ]+rdinstreth[ ]+t0
24 [ ]+[0-9a-f]+:[ ]+003022f3[ ]+frcsr[ ]+t0
25 [ ]+[0-9a-f]+:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
26 [ ]+[0-9a-f]+:[ ]+00339073[ ]+fscsr[ ]+t2
27 [ ]+[0-9a-f]+:[ ]+002022f3[ ]+frrm[ ]+t0
28 [ ]+[0-9a-f]+:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
29 [ ]+[0-9a-f]+:[ ]+00231073[ ]+fsrm[ ]+t1
30 [ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
31 [ ]+[0-9a-f]+:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
32 [ ]+[0-9a-f]+:[ ]+001022f3[ ]+frflags[ ]+t0
33 [ ]+[0-9a-f]+:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
34 [ ]+[0-9a-f]+:[ ]+00131073[ ]+fsflags[ ]+t1
35 [ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
36 [ ]+[0-9a-f]+:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31