1 2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
3 * config/arm/arm.c (thumb1_expand_prologue): Update error message.
5 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
8 * config/i386/sse.md (sse2_cvtpi2pd): Add memory to alternative 1.
10 (floatv2siv2df2): New expander.
11 (floatunsv2siv2df2): New insn pattern.
13 (fix_truncv2dfv2si2): New expander.
14 (fixuns_truncv2dfv2si2): New insn pattern.
16 2020-05-14 Richard Sandiford <richard.sandiford@arm.com>
19 * config/aarch64/aarch64-sve-builtins.cc
20 (handle_arm_sve_vector_bits_attribute): Create a copy of the
21 original type's TYPE_MAIN_VARIANT, then reapply all the differences
22 between the original type and its main variant.
24 2020-05-14 Richard Biener <rguenther@suse.de>
27 * real.c (real_to_decimal_for_mode): Make sure we handle
28 a zero with nonzero exponent.
30 2020-05-14 Jakub Jelinek <jakub@redhat.com>
32 * Makefile.in (GTFILES): Add omp-general.c.
33 * cgraph.h (struct cgraph_node): Add declare_variant_alt and
34 calls_declare_variant_alt members and initialize them in the
36 * ipa.c (symbol_table::remove_unreachable_nodes): Handle direct
37 calls to declare_variant_alt nodes.
38 * lto-cgraph.c (lto_output_node): Write declare_variant_alt
39 and calls_declare_variant_alt.
40 (input_overwrite_node): Read them back.
41 * omp-simd-clone.c (simd_clone_create): Copy calls_declare_variant_alt
43 * tree-inline.c (expand_call_inline): Or in calls_declare_variant_alt
45 (tree_function_versioning): Copy calls_declare_variant_alt bit.
46 * omp-offload.c (execute_omp_device_lower): Call
47 omp_resolve_declare_variant on direct function calls.
48 (pass_omp_device_lower::gate): Also enable for
49 calls_declare_variant_alt functions.
50 * omp-general.c (omp_maybe_offloaded): Return false after inlining.
51 (omp_context_selector_matches): Handle the case when
52 cfun->curr_properties has PROP_gimple_any bit set.
53 (struct omp_declare_variant_entry): New type.
54 (struct omp_declare_variant_base_entry): New type.
55 (struct omp_declare_variant_hasher): New type.
56 (omp_declare_variant_hasher::hash, omp_declare_variant_hasher::equal):
58 (omp_declare_variants): New variable.
59 (struct omp_declare_variant_alt_hasher): New type.
60 (omp_declare_variant_alt_hasher::hash,
61 omp_declare_variant_alt_hasher::equal): New methods.
62 (omp_declare_variant_alt): New variables.
63 (omp_resolve_late_declare_variant): New function.
64 (omp_resolve_declare_variant): Call omp_resolve_late_declare_variant
65 when called late. Create a magic declare_variant_alt fndecl and
66 cgraph node and return that if decision needs to be deferred until
68 * cgraph.c (symbol_table::create_edge): Or in calls_declare_variant_alt
72 * omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member.
73 (ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in
74 entry block if info->after_stmt is NULL, otherwise add after that stmt
75 and update it after adding each stmt.
76 (ipa_simd_modify_function_body): Initialize info.after_stmt.
78 * function.h (struct function): Add has_omp_target bit.
79 * omp-offload.c (omp_discover_declare_target_fn_r): New function,
81 (omp_discover_declare_target_tgt_fn_r): ... this.
82 (omp_discover_declare_target_var_r): Call
83 omp_discover_declare_target_tgt_fn_r instead of
84 omp_discover_declare_target_fn_r.
85 (omp_discover_implicit_declare_target): Also queue functions with
86 has_omp_target bit set, for those walk with
87 omp_discover_declare_target_fn_r, for declare target to functions
88 walk with omp_discover_declare_target_tgt_fn_r.
90 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
93 * config/i386/mmx.md (mmx_fix_truncv2sfv2si2): Rename from mmx_pf2id.
94 Add SSE/AVX alternative. Change operand predicates from
95 nonimmediate_operand to register_mmxmem_operand.
96 Enable instruction pattern for TARGET_MMX_WITH_SSE.
97 (fix_truncv2sfv2si2): New expander.
98 (fixuns_truncv2sfv2si2): New insn pattern.
100 (mmx_floatv2siv2sf2): rename from mmx_floatv2si2.
101 Add SSE/AVX alternative. Change operand predicates from
102 nonimmediate_operand to register_mmxmem_operand.
103 Enable instruction pattern for TARGET_MMX_WITH_SSE.
104 (floatv2siv2sf2): New expander.
105 (floatunsv2siv2sf2): New insn pattern.
107 * config/i386/i386-builtin.def (IX86_BUILTIN_PF2ID):
109 (IX86_BUILTIN_PI2FD): Ditto.
111 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
113 * config/s390/s390.c (s390_emit_stack_probe): Call the probe_stack
115 * config/s390/s390.md ("@probe_stack2<mode>", "probe_stack"): New
118 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
120 * config/s390/s390.c (allocate_stack_space): Add missing updates
121 of last_probe_offset.
123 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
125 * config/s390/s390.md ("allocate_stack"): Call
126 anti_adjust_stack_and_probe_stack_clash when stack clash
127 protection is enabled.
128 * explow.c (anti_adjust_stack_and_probe_stack_clash): Remove
129 prototype. Remove static.
130 * explow.h (anti_adjust_stack_and_probe_stack_clash): Add
133 2020-05-13 Kelvin Nilsen <kelvin@gcc.gnu.org>
135 * config/rs6000/altivec.h (vec_extractl): New #define.
136 (vec_extracth): Likewise.
137 * config/rs6000/altivec.md (UNSPEC_EXTRACTL): New constant.
138 (UNSPEC_EXTRACTR): Likewise.
139 (vextractl<mode>): New expansion.
140 (vextractl<mode>_internal): New insn.
141 (vextractr<mode>): New expansion.
142 (vextractr<mode>_internal): New insn.
143 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vextdubvlx):
144 New built-in function.
145 (__builtin_altivec_vextduhvlx): Likewise.
146 (__builtin_altivec_vextduwvlx): Likewise.
147 (__builtin_altivec_vextddvlx): Likewise.
148 (__builtin_altivec_vextdubvhx): Likewise.
149 (__builtin_altivec_vextduhvhx): Likewise.
150 (__builtin_altivec_vextduwvhx): Likewise.
151 (__builtin_altivec_vextddvhx): Likewise.
152 (__builtin_vec_extractl): New overloaded built-in function.
153 (__builtin_vec_extracth): Likewise.
154 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
155 Define overloaded forms of __builtin_vec_extractl and
156 __builtin_vec_extracth.
157 (builtin_function_type): Add cases to mark arguments of new
158 built-in functions as unsigned.
159 (rs6000_common_init_builtins): Add
160 opaque_ftype_opaque_opaque_opaque_opaque.
161 * config/rs6000/rs6000.md (du_or_d): New mode attribute.
162 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
163 for a Future Architecture): Add description of vec_extractl and
164 vec_extractr built-in functions.
166 2020-05-13 Richard Biener <rguenther@suse.de>
168 * target.def (add_stmt_cost): Add new vectype parameter.
169 * targhooks.c (default_add_stmt_cost): Adjust.
170 * targhooks.h (default_add_stmt_cost): Likewise.
171 * config/aarch64/aarch64.c (aarch64_add_stmt_cost): Take new
173 * config/arm/arm.c (arm_add_stmt_cost): Likewise.
174 * config/i386/i386.c (ix86_add_stmt_cost): Likewise.
175 * config/rs6000/rs6000.c (rs6000_add_stmt_cost): Likewise.
177 * tree-vectorizer.h (stmt_info_for_cost::vectype): Add.
178 (dump_stmt_cost): Add new vectype parameter.
179 (add_stmt_cost): Likewise.
180 (record_stmt_cost): Likewise.
181 (record_stmt_cost): Add overload with old signature.
182 * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost):
184 (vect_get_known_peeling_cost): Likewise.
185 (vect_estimate_min_profitable_iters): Likewise.
186 * tree-vectorizer.c (dump_stmt_cost): Add new vectype parameter.
187 * tree-vect-stmts.c (record_stmt_cost): Likewise.
188 (vect_prologue_cost_for_slp_op): Remove stmt_vec_info parameter
189 and pass down correct vectype and NULL stmt_info.
190 (vect_model_simple_cost): Adjust.
191 (vect_model_store_cost): Likewise.
193 2020-05-13 Richard Biener <rguenther@suse.de>
195 * tree-vectorizer.h (SLP_INSTANCE_GROUP_SIZE): Remove.
196 (_slp_instance::group_size): Likewise.
197 * tree-vect-loop.c (vectorizable_reduction): The group size
198 is the number of lanes in the node.
199 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Likewise.
200 (vect_analyze_slp_instance): Do not set SLP_INSTANCE_GROUP_SIZE,
201 verify it matches the instance trees number of lanes.
202 (vect_slp_analyze_node_operations_1): Use the numer of lanes
203 in the node as group size.
204 (vect_bb_vectorization_profitable_p): Use the instance root
205 number of lanes for the size of life.
206 (vect_schedule_slp_instance): Use the number of lanes as
208 * tree-vect-stmts.c (vectorizable_load): Remove SLP instance
209 parameter. Use the number of lanes of the load for the group
210 size in the gap adjustment code.
211 (vect_analyze_stmt): Adjust.
212 (vect_transform_stmt): Likewise.
214 2020-05-13 Jakub Jelinek <jakub@redhat.com>
217 * cfgrtl.c (purge_dead_edges): Skip over debug and note insns even
218 if the last insn is a note.
220 PR tree-optimization/95060
221 * tree-ssa-math-opts.c (convert_mult_to_fma_1): Fold a NEGATE_EXPR
222 if it is the single use of the FMA internal builtin.
224 2020-05-13 Bin Cheng <bin.cheng@linux.alibaba.com>
226 PR tree-optimization/94969
227 * tree-data-dependence.c (constant_access_functions): Rename to...
228 (invariant_access_functions): ...this. Add parameter. Check for
229 invariant access function, rather than constant.
230 (build_classic_dist_vector): Call above function.
231 * tree-loop-distribution.c (pg_add_dependence_edges): Add comment.
233 2020-05-13 Hongtao Liu <hongtao.liu@intel.com>
236 * doc/extend.texi (x86Operandmodifiers): Document more x86
238 * gcc/config/i386/i386.c: Add comment for operand modifier N and I.
240 2020-05-12 Giuliano Belinassi <giuliano.belinassi@usp.br>
242 * tree-vrp.c (class vrp_insert): New.
243 (insert_range_assertions): Move to class vrp_insert.
244 (dump_all_asserts): Same as above.
245 (dump_asserts_for): Same as above.
246 (live): Same as above.
247 (need_assert_for): Same as above.
248 (live_on_edge): Same as above.
249 (finish_register_edge_assert_for): Same as above.
250 (find_switch_asserts): Same as above.
251 (find_assert_locations): Same as above.
252 (find_assert_locations_1): Same as above.
253 (find_conditional_asserts): Same as above.
254 (process_assert_insertions): Same as above.
255 (register_new_assert_for): Same as above.
256 (vrp_prop): New variable fun.
257 (vrp_initialize): New parameter.
258 (identify_jump_threads): Same as above.
259 (execute_vrp): Same as above.
262 2020-05-12 Keith Packard <keith.packard@sifive.com>
264 * config/riscv/riscv.c (riscv_unique_section): New.
265 (TARGET_ASM_UNIQUE_SECTION): New.
267 2020-05-12 Craig Blackmore <craig.blackmore@embecosm.com>
269 * config.gcc: Add riscv-shorten-memrefs.o to extra_objs for riscv.
270 * config/riscv/riscv-passes.def: New file.
271 * config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare.
272 * config/riscv/riscv-shorten-memrefs.c: New file.
273 * config/riscv/riscv.c (tree-pass.h): New include.
274 (riscv_compressed_reg_p): New Function
275 (riscv_compressed_lw_offset_p): Likewise.
276 (riscv_compressed_lw_address_p): Likewise.
277 (riscv_shorten_lw_offset): Likewise.
278 (riscv_legitimize_address): Attempt to convert base + large_offset
279 to compressible new_base + small_offset.
280 (riscv_address_cost): Make anticipated compressed load/stores
281 cheaper for code size than uncompressed load/stores.
282 (riscv_register_priority): Move compressed register check to
283 riscv_compressed_reg_p.
284 * config/riscv/riscv.h (C_S_BITS): Define.
285 (CSW_MAX_OFFSET): Define.
286 * config/riscv/riscv.opt (mshorten-memefs): New option.
287 * config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule.
288 (PASSES_EXTRA): Add riscv-passes.def.
289 * doc/invoke.texi: Document -mshorten-memrefs.
291 * config/riscv/riscv.c (riscv_new_address_profitable_p): New function.
292 (TARGET_NEW_ADDRESS_PROFITABLE_P): Define.
293 * doc/tm.texi: Regenerate.
294 * doc/tm.texi.in (TARGET_NEW_ADDRESS_PROFITABLE_P): New hook.
295 * sched-deps.c (attempt_change): Use old address if it is cheaper than
297 * target.def (new_address_profitable_p): New hook.
298 * targhooks.c (default_new_address_profitable_p): New function.
299 * targhooks.h (default_new_address_profitable_p): Declare.
301 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
304 * config/i386/mmx.md (copysignv2sf3): New expander.
305 (xorsignv2sf3): Ditto.
306 (signbitv2sf3): Ditto.
308 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
311 * config/i386/mmx.md (fmav2sf4): New insn pattern.
316 2020-05-12 H.J. Lu <hongjiu.lu@intel.com>
318 * Makefile.in (CET_HOST_FLAGS): New.
319 (COMPILER): Add $(CET_HOST_FLAGS).
320 * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and
321 AC_SUBST(CET_HOST_FLAGS). Clear CET_HOST_FLAGS if jit isn't
323 * aclocal.m4: Regenerated.
324 * configure: Likewise.
326 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
329 * config/i386/mmx.md (<code>v2sf2): New insn pattern.
330 (*mmx_<code>v2sf2): New insn_and_split pattern.
331 (*mmx_nabsv2sf2): Ditto.
332 (*mmx_andnotv2sf3): New insn pattern.
333 (*mmx_<code>v2sf3): Ditto.
334 * config/i386/i386.md (absneg_op): New code attribute.
335 * config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode.
336 (ix86_build_signbit_mask): Ditto.
338 2020-05-12 Richard Biener <rguenther@suse.de>
340 * tree-ssa-live.c (remove_unused_locals): Remove dead debug
343 2020-05-12 Jozef Lawrynowicz <jozef.l@mittosystems.com>
345 * config/msp430/msp430-protos.h (msp430_output_aligned_decl_common):
346 Update prototype to include "local" argument.
347 * config/msp430/msp430.c (msp430_output_aligned_decl_common): Add
348 "local" argument. Handle local common decls.
349 * config/msp430/msp430.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Adjust
350 msp430_output_aligned_decl_common call with 0 for "local" argument.
351 (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Define.
353 2020-05-12 Richard Biener <rguenther@suse.de>
355 * cfghooks.c (split_edge): Preserve EDGE_DFS_BACK if set.
357 2020-05-12 Martin Liska <mliska@suse.cz>
361 * sanopt.c (sanitize_rewrite_addressable_params):
362 Clear DECL_NOT_GIMPLE_REG_P for argument.
364 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
366 PR tree-optimization/94980
367 * tree-vect-generic.c (expand_vector_comparison): Use
368 vector_element_bits_tree to get the element size in bits,
369 rather than using TYPE_SIZE.
370 (expand_vector_condition, vector_element): Likewise.
372 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
374 PR tree-optimization/94980
375 * tree-vect-generic.c (build_replicated_const): Take the number
376 of bits as a parameter, instead of the type of the elements.
377 (do_plus_minus): Update accordingly, using vector_element_bits
378 to calculate the correct number of bits.
379 (do_negate): Likewise.
381 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
383 PR tree-optimization/94980
384 * tree.h (vector_element_bits, vector_element_bits_tree): Declare.
385 * tree.c (vector_element_bits, vector_element_bits_tree): New.
386 * match.pd: Use the new functions instead of determining the
387 vector element size directly from TYPE_SIZE(_UNIT).
388 * tree-vect-data-refs.c (vect_gather_scatter_fn_p): Likewise.
389 * tree-vect-patterns.c (vect_recog_mask_conversion_pattern): Likewise.
390 * tree-vect-stmts.c (vect_is_simple_cond): Likewise.
391 * tree-vect-generic.c (expand_vector_piecewise): Likewise.
392 (expand_vector_conversion): Likewise.
393 (expand_vector_addition): Likewise for a TYPE_SIZE_UNIT used as
394 a divisor. Convert the dividend to bits to compensate.
395 * tree-vect-loop.c (vectorizable_live_operation): Call
396 vector_element_bits instead of open-coding it.
398 2020-05-12 Jakub Jelinek <jakub@redhat.com>
400 * omp-offload.h (omp_discover_implicit_declare_target): Declare.
401 * omp-offload.c: Include context.h.
402 (omp_declare_target_fn_p, omp_declare_target_var_p,
403 omp_discover_declare_target_fn_r, omp_discover_declare_target_var_r,
404 omp_discover_implicit_declare_target): New functions.
405 * cgraphunit.c (analyze_functions): Call
406 omp_discover_implicit_declare_target.
408 2020-05-12 Richard Biener <rguenther@suse.de>
410 * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Canonicalize
411 literal constant &MEM[..] to a constant literal.
413 2020-05-12 Richard Biener <rguenther@suse.de>
415 PR tree-optimization/95045
416 * dbgcnt.def (lim): Add debug-counter.
417 * tree-ssa-loop-im.c: Include dbgcnt.h.
418 (find_refs_for_sm): Use lim debug counter for store motion
420 (do_store_motion): Rename form store_motion. Commit edge
422 (store_motion_loop): ... here.
423 (tree_ssa_lim): Adjust.
425 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
427 * config/rs6000/altivec.h (vec_clzm): Rename to vec_cntlzm.
428 (vec_ctzm): Rename to vec_cnttzm.
429 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
430 Change fourth operand for vec_ternarylogic to require
431 compatibility with unsigned SImode rather than unsigned QImode.
432 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
433 Remove overloaded forms of vec_gnb that are no longer needed.
434 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
435 for a Future Architecture): Replace vec_clzm with vec_cntlzm;
436 replace vec_ctzm with vec_cntlzm; remove four unwanted forms of
437 vec_gnb; move vec_ternarylogic documentation into this section
438 and replace const unsigned char with const unsigned int as its
441 2020-05-11 Carl Love <cel@us.ibm.com>
443 * config/rs6000/altivec.h (vec_genpcvm): New #define.
444 * config/rs6000/rs6000-builtin.def (XXGENPCVM_V16QI): New built-in
446 (XXGENPCVM_V8HI): Likewise.
447 (XXGENPCVM_V4SI): Likewise.
448 (XXGENPCVM_V2DI): Likewise.
449 (XXGENPCVM): New overloaded built-in instantiation.
450 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add
451 entries for FUTURE_BUILTIN_VEC_XXGENPCVM.
452 (altivec_expand_builtin): Add special handling for
453 FUTURE_BUILTIN_VEC_XXGENPCVM.
454 (builtin_function_type): Add handling for
455 FUTURE_BUILTIN_XXGENPCVM_{V16QI,V8HI,V4SI,V2DI}.
456 * config/rs6000/vsx.md (VSX_EXTRACT_I4): New mode iterator.
457 (UNSPEC_XXGENPCV): New constant.
458 (xxgenpcvm_<mode>_internal): New insn.
459 (xxgenpcvm_<mode>): New expansion.
460 * doc/extend.texi: Add documentation for vec_genpcvm built-ins.
462 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
464 * config/rs6000/altivec.h (vec_strir): New #define.
465 (vec_stril): Likewise.
466 (vec_strir_p): Likewise.
467 (vec_stril_p): Likewise.
468 * config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
469 (UNSPEC_VSTRIL): Likewise.
470 (vstrir_<mode>): New expansion.
471 (vstrir_code_<mode>): New insn.
472 (vstrir_p_<mode>): New expansion.
473 (vstrir_p_code_<mode>): New insn.
474 (vstril_<mode>): New expansion.
475 (vstril_code_<mode>): New insn.
476 (vstril_p_<mode>): New expansion.
477 (vstril_p_code_<mode>): New insn.
478 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr):
479 New built-in function.
480 (__builtin_altivec_vstrihr): Likewise.
481 (__builtin_altivec_vstribl): Likewise.
482 (__builtin_altivec_vstrihl): Likewise.
483 (__builtin_altivec_vstribr_p): Likewise.
484 (__builtin_altivec_vstrihr_p): Likewise.
485 (__builtin_altivec_vstribl_p): Likewise.
486 (__builtin_altivec_vstrihl_p): Likewise.
487 (__builtin_vec_strir): New overloaded built-in function.
488 (__builtin_vec_stril): Likewise.
489 (__builtin_vec_strir_p): Likewise.
490 (__builtin_vec_stril_p): Likewise.
491 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
492 Define overloaded forms of __builtin_vec_strir,
493 __builtin_vec_stril, __builtin_vec_strir_p, and
494 __builtin_vec_stril_p.
495 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
496 for a Future Architecture): Add description of vec_stril,
497 vec_stril_p, vec_strir, and vec_strir_p built-in functions.
499 2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
501 * config/rs6000/altivec.h (vec_ternarylogic): New #define.
502 * config/rs6000/altivec.md (UNSPEC_XXEVAL): New constant.
504 * config/rs6000/predicates.md (u8bit_cint_operand): New predicate.
505 * config/rs6000/rs6000-builtin.def: Add handling of new macro
507 (BU_FUTURE_V_4): New macro. Use it.
508 (BU_FUTURE_OVERLOAD_4): Likewise.
509 * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Add
510 handling for quaternary built-in functions.
511 (altivec_resolve_overloaded_builtin): Add special-case handling
512 for __builtin_vec_xxeval.
513 * config/rs6000/rs6000-call.c: Add handling of new macro
514 RS6000_BUILTIN_4 in initialization of rs6000_builtin_info,
515 bdesc0_arg, bdesc1_arg, bdesc2_arg, bdesc_3arg,
516 bdesc_altivec_preds, bdesc_abs, and bdesc_htm arrays.
517 (altivec_overloaded_builtins): Add definitions for
518 FUTURE_BUILTIN_VEC_XXEVAL.
519 (bdesc_4arg): New array.
520 (htm_expand_builtin): Add handling for quaternary built-in
522 (rs6000_expand_quaternop_builtin): New function.
523 (rs6000_expand_builtin): Add handling for quaternary built-in
525 (rs6000_init_builtins): Initialize builtin_mode_to_type entries
526 for unsigned QImode and unsigned HImode.
527 (builtin_quaternary_function_type): New function.
528 (rs6000_common_init_builtins): Add handling of quaternary
530 * config/rs6000/rs6000.h (RS6000_BTC_QUATERNARY): New defined
532 (RS6000_BTC_PREDICATE): Change value of constant.
533 (RS6000_BTC_ABS): Likewise.
534 (rs6000_builtins): Add support for new macro RS6000_BUILTIN_4.
535 * doc/extend.texi (PowerPC AltiVec Built-In Functions Available
536 for a Future Architecture): Add description of vec_ternarylogic
539 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
541 * config/rs6000/rs6000-builtin.def (__builtin_pdepd): New built-in
543 (__builtin_pextd): Likewise.
544 * config/rs6000/rs6000.md (UNSPEC_PDEPD): New constant.
545 (UNSPEC_PEXTD): Likewise.
548 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
549 a Future Architecture): Add descriptions of __builtin_pdepd and
550 __builtin_pextd functions.
552 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
554 * config/rs6000/altivec.h (vec_clrl): New #define.
555 (vec_clrr): Likewise.
556 * config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
557 (UNSPEC_VCLRRB): Likewise.
560 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
562 (__builtin_altivec_vclrrb): Likewise.
563 (__builtin_vec_clrl): New overloaded built-in function.
564 (__builtin_vec_clrr): Likewise.
565 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
566 Define overloaded forms of __builtin_vec_clrl and
568 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
569 for a Future Architecture): Add descriptions of vec_clrl and
572 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
574 * config/rs6000/rs6000-builtin.def (__builtin_cntlzdm): New
575 built-in function definition.
576 (__builtin_cnttzdm): Likewise.
577 * config/rs6000/rs6000.md (UNSPEC_CNTLZDM): New constant.
578 (UNSPEC_CNTTZDM): Likewise.
581 * doc/extend.texi (Basic PowerPC Built-in Functions available for
582 a Future Architecture): Add descriptions of __builtin_cntlzdm and
583 __builtin_cnttzdm functions.
585 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
588 * config/i386/mmx.md (sqrtv2sf2): New insn pattern.
590 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
592 * config/rs6000/altivec.h (vec_cfuge): New #define.
593 * config/rs6000/altivec.md (UNSPEC_VCFUGED): New constant.
595 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vcfuged):
596 New built-in function.
597 * config/rs6000/rs6000-call.c (builtin_function_type): Add
598 handling for FUTURE_BUILTIN_VCFUGED case.
599 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
600 for a Future Architecture): Add description of vec_cfuge built-in
603 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
605 * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_0): New
607 (BU_FUTURE_MISC_1): Likewise.
608 (BU_FUTURE_MISC_2): Likewise.
609 (BU_FUTURE_MISC_3): Likewise.
610 (__builtin_cfuged): New built-in function definition.
611 * config/rs6000/rs6000.md (UNSPEC_CFUGED): New constant.
613 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
614 a Future Architecture): New subsubsection.
616 2020-05-11 Richard Biener <rguenther@suse.de>
618 PR tree-optimization/95049
619 * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition
620 between different constants.
622 2020-05-11 Richard Sandiford <richard.sandiford@arm.com>
624 * tree-pretty-print.c (dump_generic_node): Handle BOOLEAN_TYPEs.
626 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
627 Bill Schmidt <wschmidt@linux.ibm.com>
629 * config/rs6000/altivec.h (vec_gnb): New #define.
630 * config/rs6000/altivec.md (UNSPEC_VGNB): New constant.
632 * config/rs6000/rs6000-builtin.def (BU_FUTURE_OVERLOAD_1): New
634 (BU_FUTURE_OVERLOAD_2): Likewise.
635 (BU_FUTURE_OVERLOAD_3): Likewise.
636 (__builtin_altivec_gnb): New built-in function.
637 (__buiiltin_vec_gnb): New overloaded built-in function.
638 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
639 Define overloaded forms of __builtin_vec_gnb.
640 (rs6000_expand_binop_builtin): Add error checking for 2nd argument
641 of __builtin_vec_gnb.
642 (builtin_function_type): Mark return value and arguments unsigned
643 for FUTURE_BUILTIN_VGNB.
644 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
645 for a Future Architecture): Add description of vec_gnb built-in
648 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
649 Bill Schmidt <wschmidt@linux.ibm.com>
651 * config/rs6000/altivec.h (vec_pdep): New macro implementing new
653 (vec_pext): Likewise.
654 * config/rs6000/altivec.md (UNSPEC_VPDEPD): New constant.
655 (UNSPEC_VPEXTD): Likewise.
658 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vpdepd): New
660 (__builtin_altivec_vpextd): Likewise.
661 * config/rs6000/rs6000-call.c (builtin_function_type): Add
662 handling for FUTURE_BUILTIN_VPDEPD and FUTURE_BUILTIN_VPEXTD
664 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
665 for a Future Architecture): Add description of vec_pdep and
666 vec_pext built-in functions.
668 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
669 Bill Schmidt <wschmidt@linux.ibm.com>
671 * config/rs6000/altivec.h (vec_clzm): New macro.
672 (vec_ctzm): Likewise.
673 * config/rs6000/altivec.md (UNSPEC_VCLZDM): New constant.
674 (UNSPEC_VCTZDM): Likewise.
677 * config/rs6000/rs6000-builtin.def (BU_FUTURE_V_0): New macro.
678 (BU_FUTURE_V_1): Likewise.
679 (BU_FUTURE_V_2): Likewise.
680 (BU_FUTURE_V_3): Likewise.
681 (__builtin_altivec_vclzdm): New builtin definition.
682 (__builtin_altivec_vctzdm): Likewise.
683 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Cause
684 _ARCH_PWR_FUTURE macro to be defined if OPTION_MASK_FUTURE flag is
686 * config/rs6000/rs6000-call.c (builtin_function_type): Set return
687 value and parameter types to be unsigned for VCLZDM and VCTZDM.
688 * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
689 support for TARGET_FUTURE flag.
690 * config/rs6000/rs6000.h (RS6000_BTM_FUTURE): New macro constant.
691 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
692 for a Future Architecture): New subsubsection.
694 2020-05-11 Richard Biener <rguenther@suse.de>
696 PR tree-optimization/94988
697 PR tree-optimization/95025
698 * tree-ssa-loop-im.c (seq_entry): Make a struct, add from.
699 (sm_seq_push_down): Take extra parameter denoting where we
701 (execute_sm_exit): Re-issue sm_other stores in the correct
703 (sm_seq_valid_bb): When always executed, allow sm_other to
704 prevail inbetween sm_ord and record their stored value.
705 (hoist_memory_references): Adjust refs_not_supported propagation
706 and prune sm_other from the end of the ordered sequences.
708 2020-05-11 Felix Yang <felix.yang@huawei.com>
711 * config/aarch64/aarch64.md (mov<mode>):
712 Bitcasts to the equivalent integer mode using gen_lowpart
713 instead of doing FAIL for scalar floating point move.
715 2020-05-11 Alex Coplan <alex.coplan@arm.com>
717 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Add case
718 to correctly calculate cost for new pattern (*csinv3_uxtw_insn3).
719 * config/aarch64/aarch64.md (*csinv3_utxw_insn1): New.
720 (*csinv3_uxtw_insn2): New.
721 (*csinv3_uxtw_insn3): New.
722 * config/aarch64/iterators.md (neg_not_cs): New.
724 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
727 * config/i386/mmx.md (mmx_addv2sf3): Use "v" constraint
728 instead of "Yv" for AVX alternatives. Add "prefix" attribute.
729 (*mmx_addv2sf3): Ditto.
730 (*mmx_subv2sf3): Ditto.
731 (*mmx_mulv2sf3): Ditto.
732 (*mmx_<code>v2sf3): Ditto.
733 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
735 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
738 * config/i386/i386.c (ix86_vector_mode_supported_p):
739 Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE.
740 * config/i386/mmx.md (*mov<mode>_internal): Do not set
741 mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE.
743 (mmx_addv2sf3): Change operand predicates from
744 nonimmediate_operand to register_mmxmem_operand.
745 (addv2sf3): New expander.
746 (*mmx_addv2sf3): Add SSE/AVX alternatives. Change operand
747 predicates from nonimmediate_operand to register_mmxmem_operand.
748 Enable instruction pattern for TARGET_MMX_WITH_SSE.
750 (mmx_subv2sf3): Change operand predicate from
751 nonimmediate_operand to register_mmxmem_operand.
752 (mmx_subrv2sf3): Ditto.
753 (subv2sf3): New expander.
754 (*mmx_subv2sf3): Add SSE/AVX alternatives. Change operand
755 predicates from nonimmediate_operand to register_mmxmem_operand.
756 Enable instruction pattern for TARGET_MMX_WITH_SSE.
758 (mmx_mulv2sf3): Change operand predicates from
759 nonimmediate_operand to register_mmxmem_operand.
760 (mulv2sf3): New expander.
761 (*mmx_mulv2sf3): Add SSE/AVX alternatives. Change operand
762 predicates from nonimmediate_operand to register_mmxmem_operand.
763 Enable instruction pattern for TARGET_MMX_WITH_SSE.
765 (mmx_<code>v2sf3): Change operand predicates from
766 nonimmediate_operand to register_mmxmem_operand.
767 (<code>v2sf3): New expander.
768 (*mmx_<code>v2sf3): Add SSE/AVX alternatives. Change operand
769 predicates from nonimmediate_operand to register_mmxmem_operand.
770 Enable instruction pattern for TARGET_MMX_WITH_SSE.
771 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
773 2020-05-11 Martin Liska <mliska@suse.cz>
776 * common.opt: Fix typo in option description.
778 2020-05-11 Martin Liska <mliska@suse.cz>
780 PR gcov-profile/94928
781 * gcov-io.h: Add caveat about coverage format parsing and
782 possible outdated documentation.
784 2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com>
786 PR tree-optimization/83403
787 * tree-affine.c (expr_to_aff_combination): Replace SSA_NAME with
788 determine_value_range, Add fold conversion of MULT_EXPR, fix the
791 2020-05-10 Gerald Pfeifer <gerald@pfeifer.com>
793 * config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and
794 __ILP32__ for 32-bit targets.
796 2020-05-09 Eric Botcazou <ebotcazou@adacore.com>
798 * tree.h (expr_align): Delete.
799 * tree.c (expr_align): Likewise.
801 2020-05-09 Hans-Peter Nilsson <hp@axis.com>
803 * resource.c (init_resource_info): Filter-out TARGET_FLAGS_REGNUM
804 from end_of_function_needs.
806 * config.gcc: Remove support for crisv32-*-* and cris-*-linux*.
807 * config/cris/t-linux, config/cris/linux.h, config/cris/linux.opt:
809 * config/cris/t-elfmulti: Remove crisv32 multilib.
810 * config/cris: Remove shared-library and CRIS v32 support.
812 Move trivially from cc0 to reg:CC model, removing most optimizations.
813 * config/cris/cris.md: Remove all side-effect patterns and their
814 splitters. Remove most peepholes. Add clobbers of CRIS_CC0_REGNUM
815 to all but post-reload control-flow and movem insns. Remove
816 constraints on all modified expanders. Remove obsoleted cc0-related
818 (attr "cc"): Remove alternative "rev".
819 (mode_iterator BWDD, DI_, SI_): New.
820 (mode_attr sCC_destc, cmp_op1c, cmp_op2c): New.
821 ("tst<mode>"): Remove; fold as "M" alternative into compare insn.
822 ("mstep_shift", "mstep_mul"): Remove patterns.
823 ("s<rcond>", "s<ocond>", "s<ncond>"): Anonymize.
824 * config/cris/cris.c: Change all non-condition-code,
825 non-control-flow emitted insns to add a parallel with clobber of
826 CRIS_CC0_REGNUM, mostly by changing from gen_rtx_SET with
827 emit_insn to use of emit_move_insn, gen_add2_insn or
828 cris_emit_insn, as convenient.
829 (cris_reg_overlap_mentioned_p)
830 (cris_normal_notice_update_cc, cris_notice_update_cc): Remove.
831 (cris_movem_load_rest_p): Don't assume all elements in a
833 (cris_store_multiple_op_p): Ditto.
834 (cris_emit_insn): New function.
835 * cris/cris-protos.h (cris_emit_insn): Declare.
838 * config/cris/cris.md (zcond): New code_iterator.
839 ("*cbranch<mode>4_btstq<CC>"): New insn_and_split.
841 * config/cris/cris.c (TARGET_FLAGS_REGNUM): Define.
843 * config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.
845 * config/cris/cris.md ("movsi"): For memory destination
846 post-reload, generate clobberless variant. Similarly for a
847 zero-source post-reload.
848 ("*mov_tomem<mode>_split"): New split.
849 ("*mov_tomem<mode>"): New insn.
850 ("enabled", mov_tomem_enabled): Define and use to exclude "x" ->
851 "Q>m" for less-than-SImode.
852 ("*mov_fromzero<mode>_split"): New split.
853 ("*mov_fromzero<mode>"): New insn.
855 Prepare for cmpelim pass to eliminate redundant compare insns.
856 * config/cris/cris-modes.def: New file.
857 * config/cris/cris-protos.h (cris_select_cc_mode): Declare.
858 (cris_notice_update_cc): Remove left-over declaration.
859 * config/cris/cris.c (TARGET_CC_MODES_COMPATIBLE): Define.
860 (cris_select_cc_mode, cris_cc_modes_compatible): New functions.
861 * config/cris/cris.h (SELECT_CC_MODE): Define.
862 * config/cris/cris.md (NZSET, NZUSE, NZVCSET, NZVCUSE): New
864 (cond): New code_iterator.
865 (nzcond): Replacement for incorrect ncond. All callers changed.
866 (nzvccond): Replacement for ocond. All callers changed.
867 (rnzcond): Replacement for rcond. All callers changed.
868 (xCC): New code_attr.
869 (cmp_op1c, cmp_op0c): Renumber from cmp_op1c and cmp_op2c. All
871 ("*cmpdi<NZVCSET:mode>"): Rename from "*cmpdi". Replace
872 CCmode with iteration over NZVCSET.
873 ("*cmp_ext<BW:mode><NZVCSET:mode>"): Similarly; rename from
875 ("*cmpsi<NZVCSET:mode>"): Similarly, from "*cmpsi".
876 ("*cmp<BW:mode><NZVCSET:mode>"): Similarly from "*cmp<mode>".
877 ("*btst<mode>"): Similarly, from "*btst".
878 ("*cbranch<mode><code>4"): Rename from "*cbranch<mode>4",
879 iterating over cond instead of matching the comparison with
880 ordered_comparison_operator.
881 ("*cbranch<mode>4_btstq<CC>"): Correct label operand number.
882 ("b<zcond:code><mode>"): Rename from "b<ncond:code>", iterating
884 ("b<nzvccond:code><mode>"): Similarly from "b<ocond:code>", over
885 NZVCUSE. Remove FIXME.
886 ("*b<nzcond:code>_reversed<mode>"): Similarly from
887 "*b<ncond:code>_reversed", over NZUSE.
888 ("*b<nzvccond:code>_reversed<mode>"): Similarly from
889 "*b<ocond:code>_reversed", over NZVCUSE. Remove FIXME.
890 ("b<rnzcond:code><mode>"): Similarly from "b<rcond:code>",
891 over NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
892 depending on CC_NZmode vs. CCmode. Remove FIXME.
893 ("*b<rnzcond:code>_reversed<mode>"): Similarly from
894 "*b<rcond:code>_reversed", over NZUSE.
895 ("*cstore<mode><code>4"): Rename from "*cstore<mode>4",
896 iterating over cond instead of matching the comparison with
897 ordered_comparison_operator.
898 ("*s<nzcond:code><mode>"): Rename from "*s<ncond:code>",
899 iterating over NZUSE.
900 ("*s<rnzcond:code><mode>"): Similar from "*s<rcond:code>", over
901 NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
902 depending on CC_NZmode vs. CCmode.
903 ("*s<nzvccond:code><mode>"): Simlar from "*s<ocond:code>", over
904 NZVCUSE. Remove FIXME.
905 ("cc"): Comment on new use.
906 ("cc_enabled"): New attribute.
907 ("enabled"): Make default fall back to cc_enabled.
908 ("setnz", "ccnz", "setnzvc", "ccnzvc", "setcc", "cccc"): New
910 ("setnz_subst", "setnzvc_subst", "setcc_subst"): New default_subst.
911 ("*movsi_internal<setcc><setnz><setnzvc>"): Rename from
912 "*movsi_internal". Correct contents of, and rename attribute
913 "cc" to "cc<cccc><ccnz><ccnzvc>".
914 ("anz", "anzvc", "acc"): New define_subst_attrs.
915 ("<acc><anz><anzvc>movhi<setcc><setnz><setnzvc>"): Rename from
916 "movhi". Rename "cc" attribute to "cc<cccc><ccnz><ccnzvc>".
917 ("<acc><anz><anzvc>movqi<setcc><setnz><setnzvc>"): Similar from
918 "movqi". Correct contents of, and rename "cc" attribute to
919 "cc<cccc><ccnz><ccnzvc>".
920 ("*b<zcond:code><mode>"): Rename from "b<zcond:code><mode>".
921 ("*b<nzvccond:code><mode>"): Rename from "b<nzvccond:code><mode>".
922 ("*b<rnzcond:code><mode>"): Rename from "*b<rnzcond:code><mode>".
923 ("<acc><anz><anzvc>extend<mode>si2<setcc><setnz><setnzvc>"):
924 Rename from "extend<mode>si2".
925 ("<acc><anz><anzvc>zero_extend<mode>si2<setcc><setnz><setnzvc>"):
926 Similar, from "zero_extend<mode>si2".
927 ("*adddi3<setnz>"): Rename from "*adddi3".
928 ("*subdi3<setnz>"): Similarly from "*subdi3".
929 ("*addsi3<setnz>"): Similarly from "*addsi3".
930 ("*subsi3<setnz>"): Similarly from "*subsi3".
931 ("*addhi3<setnz>"): Similarly from "*addhi3" and decorate the
932 "cc" attribute to "cc<ccnz>".
933 ("*addqi3<setnz>"): Similarly from "*addqi3".
934 ("*sub<mode>3<setnz>"): Similarly from "*sub<mode>3".
935 ("*expanded_andsi<setcc><setnz><setnzvc>"): Rename from
937 ("*iorsi3<setcc><setnz><setnzvc>"): Similar from "*iorsi3".
938 Decorate "cc" attribute to make "cc<cccc><ccnz><ccnzvc>".
939 ("*iorhi3<setcc><setnz><setnzvc>"): Similar from "*iorhi3".
940 ("*iorqi3<setcc><setnz><setnzvc>"): Similar from "*iorqi3".
941 ("*expanded_andhi<setcc><setnz><setnzvc>"): Similar from
942 "*expanded_andhi". Add quick cc-setting alternative for 0..31.
943 ("*andqi3<setcc><setnz><setnzvc>"): Similar from "*andqi3".
944 ("<acc><anz><anzvc>xorsi3<setcc><setnz><setnzvc>"): Rename
946 ("<acc><anz><anzvc>one_cmplsi2<setcc><setnz><setnzvc>"): Rename
948 ("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"): Rename
950 ("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"): Rename
952 ("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"): Rename
954 ("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".
956 * config/cris/cris-modes.def (CC_ZnN): New CC_MODE.
957 * config/cris/cris.c (cris_rtx_costs): Handle pre-split bit-test
958 * config/cris/cris.md (ZnNNZSET, ZnNNZUSE): New mode_iterators.
959 (znnCC, rznnCC): New code_attrs.
960 ("*btst<mode>"): Iterator over ZnNNZSET instead of NZVCSET. Remove
961 obseolete comment. Add belt-and-suspenders mode-test to condition.
962 Add fixme regarding remaining matched-but-not-generated case.
963 ("*cbranch<mode>4_btstrq1_<CC>"): New insn_and_split.
964 ("*cbranch<mode>4_btstqb0_<CC>"): Rename from
965 "*cbranch<mode>4_btstq<CC>". Split to CC_NZ instead of CC.
966 ("*b<zcond:code><mode>"): Iterate over ZnNNZUSE instead of NZUSE.
967 Handle output of CC_ZnNmode.
968 ("*b<nzcond:code>_reversed<mode>"): Ditto.
970 * config/cris/cris.c (cris_select_cc_mode): Return CC_NZmode for
971 NEG too. Correct comment.
972 * config/cris/cris.md ("<anz>neg<mode>2<setnz>"): Rename from
975 2020-05-08 Vladimir Makarov <vmakarov@redhat.com>
977 * ira-color.c (update_costs_from_allocno): Remove
978 conflict_cost_update_p argument. Propagate costs only along
979 threads. Always do conflict cost update. Add printing debugging
981 (update_costs_from_copies): Add printing debugging info.
982 (restore_costs_from_copies): Ditto.
983 (assign_hard_reg): Improve debug info.
984 (push_only_colorable): Ditto. Call update_costs_from_prefs.
985 (color_allocnos): Remove update_costs_from_prefs.
987 2020-05-08 Richard Biener <rguenther@suse.de>
989 * tree-vectorizer.h (vec_info::slp_loads): New.
990 (vect_optimize_slp): Declare.
991 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Do
992 nothing when there are no loads.
993 (vect_gather_slp_loads): Gather loads into a vector.
994 (vect_supported_load_permutation_p): Remove.
995 (vect_analyze_slp_instance): Do not verify permutation
997 (vect_analyze_slp): Optimize permutations of reductions
998 after all SLP instances have been gathered and gather
1000 (vect_optimize_slp): New function split out from
1001 vect_supported_load_permutation_p. Elide some permutations.
1002 (vect_slp_analyze_bb_1): Call vect_optimize_slp.
1003 * tree-vect-loop.c (vect_analyze_loop_2): Likewise.
1004 * tree-vect-stmts.c (vectorizable_load): Check whether
1005 the load can be permuted. When generating code assert we can.
1007 2020-05-08 Richard Biener <rguenther@suse.de>
1009 * tree-ssa-sccvn.c (rpo_avail): Change type to
1010 eliminate_dom_walker *.
1011 (eliminate_with_rpo_vn): Adjust rpo_avail to make vn_valueize
1012 use the DOM walker availability.
1013 (vn_reference_fold_indirect): Use get_addr_base_and_unit_offset_1
1014 with vn_valueize as valueization callback.
1015 (vn_reference_maybe_forwprop_address): Likewise.
1016 * tree-dfa.c (get_addr_base_and_unit_offset_1): Also valueize
1017 array_ref_low_bound.
1019 2020-05-08 Jakub Jelinek <jakub@redhat.com>
1021 PR tree-optimization/94786
1022 * match.pd (A ^ ((A ^ B) & -(C cmp D)) -> (C cmp D) ? B : A): New
1026 * config/i386/i386.md (peephole2 after *add<mode>3_cc_overflow_1): New
1030 * tree.c (get_narrower): Reuse the op temporary instead of
1033 PR tree-optimization/94783
1034 * match.pd ((X + (X >> (prec - 1))) ^ (X >> (prec - 1)) to abs (X)):
1037 PR tree-optimization/94956
1038 * match.pd (FFS): Optimize __builtin_ffs* of non-zero argument into
1039 __builtin_ctz* + 1 if direct IFN_CTZ is supported.
1041 PR tree-optimization/94913
1042 * match.pd (A - B + -1 >= A to B >= A): New simplification.
1043 (A - B > A to A < B): Don't test TYPE_OVERFLOW_WRAPS which is always
1044 true for TYPE_UNSIGNED integral types.
1047 PR rtl-optimization/94516
1048 * rtl.h (remove_reg_equal_equiv_notes): Add a bool argument defaulted
1050 * rtlanal.c (remove_reg_equal_equiv_notes): Add no_rescan argument.
1051 Call df_notes_rescan if that argument is not true and returning true.
1052 * combine.c (adjust_for_new_dest): Pass true as second argument to
1053 remove_reg_equal_equiv_notes.
1054 * postreload.c (reload_combine_recognize_pattern): Don't call
1057 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
1059 * config/rs6000/rs6000.md (*setnbc_<un>signed_<GPR:mode>): New
1061 (*setnbcr_<un>signed_<GPR:mode>): New define_insn.
1062 (*neg_eq_<mode>): Avoid for TARGET_FUTURE; add missing && 1.
1063 (*neg_ne_<mode>): Likewise.
1065 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
1067 * config/rs6000/rs6000.md (setbc_<un>signed_<GPR:mode>): New
1069 (*setbcr_<un>signed_<GPR:mode>): Likewise.
1070 (cstore<mode>4): Use setbc[r] if available.
1071 (<code><GPR:mode><GPR2:mode>2_isel): Avoid for TARGET_FUTURE.
1072 (eq<mode>3): Use setbc for TARGET_FUTURE.
1073 (*eq<mode>3): Avoid for TARGET_FUTURE.
1074 (ne<mode>3): Replace :P with :GPR; use setbc for TARGET_FUTURE;
1075 else for non-Pmode, use gen_eq and gen_xor.
1076 (*ne<mode>3): Avoid for TARGET_FUTURE.
1077 (*eqsi3_ext<mode>): Avoid for TARGET_FUTURE; fix missing && 1.
1079 2020-05-07 Jeff Law <law@redhat.com>
1081 * config/h8300/h8300.md: Move expanders and patterns into
1082 files based on functionality.
1083 * config/h8300/addsub.md: New file.
1084 * config/h8300/bitfield.md: New file
1085 * config/h8300/combiner.md: New file
1086 * config/h8300/divmod.md: New file
1087 * config/h8300/extensions.md: New file
1088 * config/h8300/jumpcall.md: New file
1089 * config/h8300/logical.md: New file
1090 * config/h8300/movepush.md: New file
1091 * config/h8300/multiply.md: New file
1092 * config/h8300/other.md: New file
1093 * config/h8300/proepi.md: New file
1094 * config/h8300/shiftrotate.md: New file
1095 * config/h8300/testcompare.md: New file
1097 * config/h8300/h8300.md (adds/subs splitters): Merge into single
1099 (negation expanders and patterns): Simplify and combine using
1101 (one_cmpl expanders and patterns): Likewise.
1102 (tablejump, indirect_jump patterns ): Likewise.
1103 (shift and rotate expanders and patterns): Likewise.
1104 (absolute value expander and pattern): Drop expander, rename pattern
1106 (peephole2 patterns): Move into...
1107 * config/h8300/peepholes.md: New file.
1109 * config/h8300/constraints.md (L and N): Simplify now that we're not
1110 longer supporting the original H8/300 chip.
1111 * config/h8300/elf.h (LINK_SPEC): Likewise. Default to H8/300H.
1112 * config/h8300/h8300.c (shift_alg_qi): Drop H8/300 support.
1113 (shift_alg_hi, shift_alg_si): Similarly.
1114 (h8300_option_overrides): Similarly. Default to H8/300H. If
1115 compiling for H8/S, then turn off H8/300H. Do not update the
1116 shift_alg tables for H8/300 port.
1117 (h8300_emit_stack_adjustment): Remove support for H8/300. Simplify
1119 (push, split_adds_subs, h8300_rtx_costs): Likewise.
1120 (h8300_print_operand, compute_mov_length): Likewise.
1121 (output_plussi, compute_plussi_length): Likewise.
1122 (compute_plussi_cc, output_logical_op): Likewise.
1123 (compute_logical_op_length, compute_logical_op_cc): Likewise.
1124 (get_shift_alg, h8300_shift_needs_scratch): Likewise.
1125 (output_a_shift, compute_a_shift_length): Likewise.
1126 (output_a_rotate, compute_a_rotate_length): Likewise.
1127 (output_simode_bld, h8300_hard_regno_mode_ok): Likewise.
1128 (h8300_modes_tieable_p, h8300_return_in_memory): Likewise.
1129 * config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Likewise.
1130 (attr_cpu, TARGET_H8300): Remove.
1131 (TARGET_DEFAULT): Update.
1132 (UNITS_PER_WORD, PARM_BOUNDARY): Simplify where possible.
1133 (BIGGEST_ALIGNMENT, STACK_BOUNDARY): Likewise.
1134 (CONSTANT_ADDRESS_P, MOVE_MAX, Pmode): Likewise.
1135 (SIZE_TYPE, POINTER_SIZE, ASM_WORD_OP): Likewise.
1136 * config/h8300/h8300.md: Simplify patterns throughout.
1137 * config/h8300/t-h8300: Update multilib configuration.
1139 * config/h8300/h8300.h (LINK_SPEC): Remove.
1140 (USER_LABEL_PREFIX): Likewise.
1142 * config/h8300/h8300.c (h8300_asm_named_section): Remove.
1143 (h8300_option_override): Remove remnants of COFF support.
1145 2020-05-07 Alan Modra <amodra@gmail.com>
1147 * tree-ssa-reassoc.c (optimize_range_tests_to_bit_test): Replace
1148 set_rtx_cost with set_src_cost.
1149 * tree-switch-conversion.c (bit_test_cluster::emit): Likewise.
1151 2020-05-07 Kewen Lin <linkw@gcc.gnu.org>
1153 * tree-vect-stmts.c (vectorizable_load): Check alignment to avoid
1154 redundant half vector handlings for no peeling gaps.
1156 2020-05-07 Giuliano Belinassi <giuliano.belinassi@usp.br>
1158 * tree-ssa-operands.c (operands_scanner): New class.
1159 (operands_bitmap_obstack): Remove.
1160 (n_initialized): Remove.
1161 (build_uses): Move to operands_scanner class.
1162 (build_vuse): Same as above.
1163 (build_vdef): Same as above.
1164 (verify_ssa_operands): Same as above.
1165 (finalize_ssa_uses): Same as above.
1166 (cleanup_build_arrays): Same as above.
1167 (finalize_ssa_stmt_operands): Same as above.
1168 (start_ssa_stmt_operands): Same as above.
1169 (append_use): Same as above.
1170 (append_vdef): Same as above.
1171 (add_virtual_operand): Same as above.
1172 (add_stmt_operand): Same as above.
1173 (get_mem_ref_operands): Same as above.
1174 (get_tmr_operands): Same as above.
1175 (maybe_add_call_vops): Same as above.
1176 (get_asm_stmt_operands): Same as above.
1177 (get_expr_operands): Same as above.
1178 (parse_ssa_operands): Same as above.
1179 (finalize_ssa_defs): Same as above.
1180 (build_ssa_operands): Same as above, plus create a C-like wrapper.
1181 (update_stmt_operands): Create an instance of operands_scanner.
1183 2020-05-07 Richard Biener <rguenther@suse.de>
1186 * tree-ssa-structalias.c (refered_from_nonlocal_fn): Use
1187 DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible.
1188 (refered_from_nonlocal_var): Likewise.
1189 (ipa_pta_execute): Likewise.
1191 2020-05-07 Erick Ochoa <erick.ochoa@theobroma-systems.com>
1193 * gcc/tree-ssa-struct-alias.c: Fix comments
1195 2020-05-07 Martin Liska <mliska@suse.cz>
1197 * doc/invoke.texi: Fix 2 optindex entries.
1199 2020-05-07 Richard Biener <rguenther@suse.de>
1202 * tree-core.h (tree_decl_common::gimple_reg_flag): Rename ...
1203 (tree_decl_common::not_gimple_reg_flag): ... to this.
1204 * tree.h (DECL_GIMPLE_REG_P): Rename ...
1205 (DECL_NOT_GIMPLE_REG_P): ... to this.
1206 * gimple-expr.c (copy_var_decl): Copy DECL_NOT_GIMPLE_REG_P.
1207 (create_tmp_reg): Simplify.
1208 (create_tmp_reg_fn): Likewise.
1209 (is_gimple_reg): Check DECL_NOT_GIMPLE_REG_P for all regs.
1210 * gimplify.c (create_tmp_from_val): Simplify.
1211 (gimplify_bind_expr): Likewise.
1212 (gimplify_compound_literal_expr): Likewise.
1213 (gimplify_function_tree): Likewise.
1214 (prepare_gimple_addressable): Set DECL_NOT_GIMPLE_REG_P.
1215 * asan.c (create_odr_indicator): Do not clear DECL_GIMPLE_REG_P.
1216 (asan_add_global): Copy it.
1217 * cgraphunit.c (cgraph_node::expand_thunk): Force args
1219 * function.c (gimplify_parameters): Copy
1220 DECL_NOT_GIMPLE_REG_P.
1221 * ipa-param-manipulation.c
1222 (ipa_param_body_adjustments::common_initialization): Simplify.
1223 (ipa_param_body_adjustments::reset_debug_stmts): Copy
1224 DECL_NOT_GIMPLE_REG_P.
1225 * omp-low.c (lower_omp_for_scan): Do not set DECL_GIMPLE_REG_P.
1226 * sanopt.c (sanitize_rewrite_addressable_params): Likewise.
1227 * tree-cfg.c (make_blocks_1): Simplify.
1228 (verify_address): Do not verify DECL_GIMPLE_REG_P setting.
1229 * tree-eh.c (lower_eh_constructs_2): Simplify.
1230 * tree-inline.c (declare_return_variable): Adjust and
1232 (copy_decl_to_var): Copy DECL_NOT_GIMPLE_REG_P.
1233 (copy_result_decl_to_var): Likewise.
1234 * tree-into-ssa.c (pass_build_ssa::execute): Adjust comment.
1235 * tree-nested.c (create_tmp_var_for): Simplify.
1236 * tree-parloops.c (separate_decls_in_region_name): Copy
1237 DECL_NOT_GIMPLE_REG_P.
1238 * tree-sra.c (create_access_replacement): Adjust and
1239 generalize partial def support.
1240 * tree-ssa-forwprop.c (pass_forwprop::execute): Set
1241 DECL_NOT_GIMPLE_REG_P on decls we introduce partial defs on.
1242 * tree-ssa.c (maybe_optimize_var): Handle clearing of
1243 TREE_ADDRESSABLE and setting/clearing DECL_NOT_GIMPLE_REG_P
1245 * lto-streamer-out.c (hash_tree): Hash DECL_NOT_GIMPLE_REG_P.
1246 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Stream
1247 DECL_NOT_GIMPLE_REG_P.
1248 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
1249 * cfgexpand.c (avoid_type_punning_on_regs): New.
1250 (discover_nonconstant_array_refs): Call
1251 avoid_type_punning_on_regs to avoid unsupported mode punning.
1253 2020-05-07 Alex Coplan <alex.coplan@arm.com>
1255 * config/arm/arm.c (arm_add_stmt_cost): Fix declaration, remove class
1258 2020-05-07 Richard Biener <rguenther@suse.de>
1260 PR tree-optimization/57359
1261 * tree-ssa-loop-im.c (im_mem_ref::indep_loop): Remove.
1262 (in_mem_ref::dep_loop): Repurpose.
1263 (LOOP_DEP_BIT): Remove.
1264 (enum dep_kind): New.
1265 (enum dep_state): Likewise.
1266 (record_loop_dependence): New function to populate the
1268 (query_loop_dependence): New function to query the dependence
1270 (memory_accesses::refs_in_loop): Rename to ...
1271 (memory_accesses::refs_loaded_in_loop): ... this and change to
1273 (outermost_indep_loop): Adjust.
1274 (mem_ref_alloc): Likewise.
1275 (gather_mem_refs_stmt): Likewise.
1276 (mem_refs_may_alias_p): Add tbaa_p parameter and pass it down.
1277 (struct sm_aux): New.
1278 (execute_sm): Split code generation on exits, record state
1280 (enum sm_kind): New.
1281 (execute_sm_exit): Exit code generation part.
1282 (sm_seq_push_down): Helper for sm_seq_valid_bb performing
1283 dependence checking on stores reached from exits.
1284 (sm_seq_valid_bb): New function gathering SM stores on exits.
1285 (hoist_memory_references): Re-implement.
1286 (refs_independent_p): Add tbaa_p parameter and pass it down.
1287 (record_dep_loop): Remove.
1288 (ref_indep_loop_p_1): Fold into ...
1289 (ref_indep_loop_p): ... this and generalize for three kinds
1290 of dependence queries.
1291 (can_sm_ref_p): Adjust according to hoist_memory_references
1293 (store_motion_loop): Don't do anything if the set of SM
1294 candidates is empty.
1295 (tree_ssa_lim_initialize): Adjust.
1296 (tree_ssa_lim_finalize): Likewise.
1298 2020-05-07 Eric Botcazou <ebotcazou@adacore.com>
1299 Pierre-Marie de Rodat <derodat@adacore.com>
1301 * dwarf2out.c (add_data_member_location_attribute): Take into account
1302 the variant part offset in the computation of the data bit offset.
1303 (add_bit_offset_attribute): Remove CTX parameter. Pass a new context
1304 in the call to field_byte_offset.
1305 (gen_field_die): Adjust call to add_bit_offset_attribute and remove
1306 confusing assertion.
1307 (analyze_variant_discr): Deal with boolean subtypes.
1309 2020-05-07 Martin Liska <mliska@suse.cz>
1311 * lto-wrapper.c: Split arguments of MAKE environment
1314 2020-05-07 Uroš Bizjak <ubizjak@gmail.com>
1316 * config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use
1317 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
1318 fenv_var and new_fenv_var.
1320 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1323 * config/i386/subst.md (store_mask_constraint, store_mask_predicate):
1325 (avx512dq_vextract<shuffletype>64x2_1_maskm,
1326 avx512f_vextract<shuffletype>32x4_1_maskm,
1327 vec_extract_lo_<mode>_maskm, vec_extract_hi_<mode>_maskm): Remove.
1328 (<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>): Split
1330 (*avx512dq_vextract<shuffletype>64x2_1,
1331 avx512dq_vextract<shuffletype>64x2_1_mask): ... these new
1332 define_insns. Even in the masked variant allow memory output but in
1333 that case use 0 rather than 0C constraint on the source of masked-out
1335 (<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>): Split
1337 (*avx512f_vextract<shuffletype>32x4_1,
1338 avx512f_vextract<shuffletype>32x4_1_mask): ... these new define_insns.
1339 Even in the masked variant allow memory output but in that case use
1340 0 rather than 0C constraint on the source of masked-out elts.
1341 (vec_extract_lo_<mode><mask_name>): Split into ...
1342 (vec_extract_lo_<mode>, vec_extract_lo_<mode>_mask): ... these new
1343 define_insns. Even in the masked variant allow memory output but in
1344 that case use 0 rather than 0C constraint on the source of masked-out
1346 (vec_extract_hi_<mode><mask_name>): Split into ...
1347 (vec_extract_hi_<mode>, vec_extract_hi_<mode>_mask): ... these new
1348 define_insns. Even in the masked variant allow memory output but in
1349 that case use 0 rather than 0C constraint on the source of masked-out
1352 2020-05-06 qing zhao <qing.zhao@oracle.com>
1355 * common.opt: Add -flarge-source-files.
1356 * doc/invoke.texi: Document it.
1357 * toplev.c (process_options): set line_table->default_range_bits
1358 to 0 when flag_large_source_files is true.
1360 2020-05-06 Uroš Bizjak <ubizjak@gmail.com>
1363 * config/i386/predicates.md (add_comparison_operator): New predicate.
1364 * config/i386/i386.md (compare->add splitter): New splitters.
1366 2020-05-06 Richard Biener <rguenther@suse.de>
1368 * tree-vectorizer.h (vect_transform_slp_perm_load): Adjust.
1369 * tree-vect-data-refs.c (vect_slp_analyze_node_dependences):
1370 Remove slp_instance parameter, just iterate over all scalar stmts.
1371 (vect_slp_analyze_instance_dependence): Adjust and likewise.
1372 * tree-vect-slp.c (vect_bb_slp_scalar_cost): Remove unused BB
1374 (vect_schedule_slp): Just iterate over all scalar stmts.
1375 (vect_supported_load_permutation_p): Adjust.
1376 (vect_transform_slp_perm_load): Remove slp_instance parameter,
1377 instead use the number of lanes in the node as group size.
1378 * tree-vect-stmts.c (vect_model_load_cost): Get vectorization
1379 factor instead of slp_instance as parameter.
1380 (vectorizable_load): Adjust.
1382 2020-05-06 Andreas Schwab <schwab@suse.de>
1384 * config/aarch64/driver-aarch64.c: Include "aarch64-protos.h".
1385 (aarch64_get_extension_string_for_isa_flags): Don't declare.
1387 2020-05-06 Richard Biener <rguenther@suse.de>
1390 * cfgloopmanip.c (create_preheader): Require non-complex
1391 preheader edge for CP_SIMPLE_PREHEADERS.
1393 2020-05-06 Richard Biener <rguenther@suse.de>
1395 PR tree-optimization/94963
1396 * tree-ssa-loop-im.c (execute_sm_if_changed): Remove
1397 no-warning marking of the conditional store.
1398 (execute_sm): Instead mark the uninitialized state
1399 on loop entry to be not warned about.
1401 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
1403 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET,
1404 OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros.
1405 * config.gcc: Add tsxldtrkintrin.h to extra_headers.
1406 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
1408 * config/i386/i386-builtin.def: Add new builtins.
1409 * config/i386/i386-c.c (ix86_target_macros_internal): Define
1411 * config/i386/i386-options.c (ix86_target_string): Add
1413 (ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk.
1414 * config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P):
1416 * config/i386/i386.md (define_c_enum "unspec"): Add
1417 UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK.
1418 (TSXLDTRK): New define_int_iterator.
1419 ("<tsxldtrk>"): New define_insn.
1420 * config/i386/i386.opt: Add -mtsxldtrk.
1421 * config/i386/immintrin.h: Include tsxldtrkintrin.h.
1422 * config/i386/tsxldtrkintrin.h: New.
1423 * doc/invoke.texi: Document -mtsxldtrk.
1425 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1427 PR tree-optimization/94921
1428 * match.pd (~(~X - Y) -> X + Y, ~(~X + Y) -> X - Y): New
1431 2020-05-06 Richard Biener <rguenther@suse.de>
1433 PR tree-optimization/94965
1434 * tree-vect-stmts.c (vectorizable_load): Fix typo.
1436 2020-05-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1438 * doc/install.texi: Replace Sun with Solaris as appropriate.
1439 (Tools/packages necessary for building GCC, Perl version between
1440 5.6.1 and 5.6.24): Remove Solaris 8 reference.
1441 (Installing GCC: Binaries, Solaris 2 (SPARC, Intel)): Remove
1443 (Specific, i?86-*-solaris2*): Update version references for
1444 Solaris 11.3 and later. Remove gas 2.26 caveat.
1445 (Specific, *-*-solaris2*): Update version references for
1446 Solaris 11.3 and later. Remove boehm-gc reference.
1447 Document GMP, MPFR caveats on Solaris 11.3.
1448 (Specific, sparc-sun-solaris2*): Update Solaris 9 references.
1449 (Specific, sparc64-*-solaris2*): Likewise.
1450 Document --build requirement.
1452 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1455 * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use
1456 TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags.
1458 PR rtl-optimization/94873
1459 * combine.c (combine_instructions): Don't optimize using REG_EQUAL
1460 note if SET_SRC (set) has side-effects.
1462 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
1463 Wei Xiao <wei3.xiao@intel.com>
1465 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
1466 OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
1467 (ix86_handle_option): Handle -mserialize.
1468 * config.gcc (serializeintrin.h): New header file.
1469 * config/i386/cpuid.h (bit_SERIALIZE): New bit.
1470 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
1472 * config/i386/i386-builtin.def: Add new builtin.
1473 * config/i386/i386-c.c (__SERIALIZE__): New macro.
1474 * config/i386/i386-options.c (ix86_target_opts_isa2_opts):
1476 * (ix86_valid_target_attribute_inner_p): Add target attribute
1478 * config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):
1480 * config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.
1481 (serialize): New define_insn.
1482 * config/i386/i386.opt (mserialize): New option
1483 * config/i386/immintrin.h: Include serailizeintrin.h.
1484 * config/i386/serializeintrin.h: New header file.
1485 * doc/invoke.texi: Add documents for -mserialize.
1487 2020-05-06 Richard Biener <rguenther@suse.de>
1489 * tree-cfg.c (verify_gimple_assign_unary): Adjust integer
1490 to/from pointer conversion checking.
1492 2020-05-05 Michael Meissner <meissner@linux.ibm.com>
1494 * config/rs6000/rs6000-builtin.def: Delete changes meant for a
1496 * config/rs6000/rs6000-c.c: Likewise.
1497 * config/rs6000/rs6000-call.c: Likewise.
1498 * config/rs6000/rs6000.c: Likewise.
1500 2020-05-05 Sebastian Huber <sebastian.huber@embedded-brains.de>
1502 * config/rtems.h (RTEMS_STARTFILE_SPEC): Define if undefined.
1503 (RTEMS_ENDFILE_SPEC): Likewise.
1504 (STARTFILE_SPEC): Update comment. Add RTEMS_STARTFILE_SPEC.
1505 (ENDFILE_SPEC): Add RTEMS_ENDFILE_SPEC.
1506 (LIB_SPECS): Support -nodefaultlibs option.
1507 * config/or1k/rtems.h (RTEMS_STARTFILE_SPEC): Define.
1508 (RTEMS_ENDFILE_SPEC): Likewise.
1509 * config/rs6000/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
1510 (RTEMS_ENDFILE_SPEC): Likewise.
1511 * config/v850/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
1512 (RTEMS_ENDFILE_SPEC): Likewise.
1514 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1516 * config/pru/pru.c (pru_hard_regno_call_part_clobbered): Remove.
1517 (TARGET_HARD_REGNO_CALL_PART_CLOBBERED): Remove.
1519 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1521 * config/pru/pru.h: Mark R3.w0 as caller saved.
1523 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1525 * config/pru/pru.c (pru_emit_doloop): Use new gen_doloop_end_internal
1526 and gen_doloop_begin_internal.
1527 (pru_reorg_loop): Use gen_pruloop with mode.
1528 * config/pru/pru.md: Use new @insn syntax.
1530 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1532 * config/pru/pru.c (pru_print_operand): Fix fall through comment.
1534 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
1536 * config/i386/i386.md (fixuns_trunc<mode>si2): Use
1537 "clobber (scratch:M)" instad of "clobber (match_scratch:M N)".
1538 (addqi3_cconly_overflow): Ditto.
1539 (umulv<mode>4): Ditto.
1540 (<s>mul<mode>3_highpart): Ditto.
1541 (tls_global_dynamic_32): Ditto.
1542 (tls_local_dynamic_base_32): Ditto.
1549 (*adddi_4): Remove "m" constraint from scratch operand.
1550 (*add<mode>_4): Ditto.
1552 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1554 PR rtl-optimization/94516
1555 * postreload.c (reload_cse_simplify): When replacing sp = sp + const
1556 with sp = reg, add REG_EQUAL note with sp + const.
1557 * combine-stack-adj.c (try_apply_stack_adjustment): Change return
1558 type from int to bool. Add LIVE and OTHER_INSN arguments. Undo
1559 postreload sp = sp + const to sp = reg optimization if needed and
1561 (combine_stack_adjustments_for_block): Add LIVE argument. Handle
1562 reg = sp insn with sp + const REG_EQUAL note. Adjust
1563 try_apply_stack_adjustment caller, call
1564 df_simulate_initialize_forwards and df_simulate_one_insn_forwards.
1565 (combine_stack_adjustments): Allocate and free LIVE bitmap,
1566 adjust combine_stack_adjustments_for_block caller.
1568 2020-05-05 Martin Liska <mliska@suse.cz>
1570 PR gcov-profile/93623
1571 * tree-cfg.c (stmt_can_terminate_bb_p): Update comment to reflect
1574 2020-05-05 Martin Liska <mliska@suse.cz>
1576 * opt-functions.awk (opt_args_non_empty): New function.
1577 * opt-read.awk: Use the function for various option arguments.
1579 2020-05-05 Martin Liska <mliska@suse.cz>
1582 * lto-wrapper.c (run_gcc): When using -flto=jobserver,
1583 report warning when the jobserver is not detected.
1585 2020-05-05 Martin Liska <mliska@suse.cz>
1587 PR gcov-profile/94636
1588 * gcov.c (main): Print total lines summary at the end.
1589 (generate_results): Expect file_name always being non-null.
1590 Print newline after intermediate file is printed in order to align with
1591 what we do for normal files.
1593 2020-05-05 Martin Liska <mliska@suse.cz>
1595 * dumpfile.c (dump_switch_p): Change return type
1596 and print option suggestion.
1597 * dumpfile.h: Change return type.
1598 * opts-global.c (handle_common_deferred_options):
1599 Move error into dump_switch_p function.
1601 2020-05-05 Martin Liska <mliska@suse.cz>
1604 * alloc-pool.h: Use const for some arguments.
1605 * bitmap.h: Likewise.
1606 * mem-stats.h: Likewise.
1607 * sese.h (get_entry_bb): Likewise.
1608 (get_exit_bb): Likewise.
1610 2020-05-05 Richard Biener <rguenther@suse.de>
1612 * tree-vect-slp.c (struct vdhs_data): New.
1613 (vect_detect_hybrid_slp): New walker.
1614 (vect_detect_hybrid_slp): Rewrite.
1616 2020-05-05 Richard Biener <rguenther@suse.de>
1619 * tree-ssa-structalias.c (ipa_pta_execute): Use
1620 varpool_node::externally_visible_p ().
1621 (refered_from_nonlocal_var): Likewise.
1623 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
1625 * gcc.c (LTO_PLUGIN_SPEC): Define if not already.
1626 (LINK_PLUGIN_SPEC): Execute LTO_PLUGIN_SPEC.
1627 * config/vxworks.h (LTO_PLUGIN_SPEC): Define.
1629 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
1631 * gimplify.c (gimplify_init_constructor): Do not put the constructor
1632 into static memory if it is not complete.
1634 2020-05-05 Richard Biener <rguenther@suse.de>
1636 PR tree-optimization/94949
1637 * tree-ssa-loop-im.c (execute_sm): Check whether we use
1638 the multithreaded model or always compute the stored value
1639 before eliding a load.
1641 2020-05-05 Alex Coplan <alex.coplan@arm.com>
1643 * config/aarch64/aarch64.md (*one_cmpl_zero_extend): New.
1645 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1647 PR tree-optimization/94800
1648 * match.pd (X + (X << C) to X * (1 + (1 << C)),
1649 (X << C1) + (X << C2) to X * ((1 << C1) + (1 << C2))): New
1653 * config/i386/mmx.md (*vec_dupv4hi): Use xYw constraints instead of Yv.
1655 PR tree-optimization/94914
1656 * match.pd ((((type)A * B) >> prec) != 0 to .MUL_OVERFLOW(A, B) != 0):
1659 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
1661 * config/i386/i386.md (*testqi_ext_3): Use
1662 int_nonimmediate_operand instead of manual mode checks.
1663 (*x86_mov<SWI48:mode>cc_0_m1_neg_leu<SWI:mode>):
1664 Use int_nonimmediate_operand predicate. Rewrite
1665 define_insn_and_split pattern to a combine pass splitter.
1667 2020-05-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1669 * configure.ac <i[34567]86-*-*>: Add --32 to tls_as_opt on Solaris.
1670 * configure: Regenerate.
1672 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1675 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
1676 ssse3_ph<plusminus_mnemonic>wv8hi3, ssse3_ph<plusminus_mnemonic>wv4hi3,
1677 avx2_ph<plusminus_mnemonic>dv8si3, ssse3_ph<plusminus_mnemonic>dv4si3,
1678 ssse3_ph<plusminus_mnemonic>dv2si3): Simplify RTL patterns.
1680 2020-05-04 Clement Chigot <clement.chigot@atos.net>
1681 David Edelsohn <dje.gcc@gmail.com>
1683 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Override explicit
1684 for fmodl, frexpl, ldexpl and modfl builtins.
1686 2020-05-04 Richard Sandiford <richard.sandiford@arm.com>
1689 * internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the
1690 chosen lhs is different from the gcall lhs.
1691 (expand_mask_load_optab_fn): Likewise.
1692 (expand_gather_load_optab_fn): Likewise.
1694 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
1697 * config/i386/i386.md (*neg<mode>_ccc): New insn pattern.
1698 (EQ compare->LTU compare splitter): New splitter.
1699 (NE compare->NEG splitter): Ditto.
1701 2020-05-04 Marek Polacek <polacek@redhat.com>
1704 2020-04-30 Marek Polacek <polacek@redhat.com>
1707 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
1708 (check_aligned_type): Check if TYPE_USER_ALIGN match.
1710 2020-05-04 Richard Biener <rguenther@suse.de>
1712 PR tree-optimization/93891
1713 * tree-ssa-sccvn.c (vn_reference_lookup_3): Fall back to
1714 the original reference tree for assessing access alignment.
1716 2020-05-04 Richard Biener <rguenther@suse.de>
1718 PR tree-optimization/39612
1719 * tree-ssa-loop-im.c (im_mem_ref::loaded): New member.
1720 (set_ref_loaded_in_loop): New.
1721 (mark_ref_loaded): Likewise.
1722 (gather_mem_refs_stmt): Call mark_ref_loaded for loads.
1723 (execute_sm): Avoid issueing a load when it was not there.
1724 (execute_sm_if_changed): Avoid issueing warnings for the
1727 2020-05-04 Martin Jambor <mjambor@suse.cz>
1730 * tree-inline.c (tree_function_versioning): Leave any type conversion
1731 of replacements to setup_one_parameter and its friend
1732 force_value_to_type.
1734 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
1737 * config/i386/predicates.md (shr_comparison_operator): New predicate.
1738 * config/i386/i386.md (compare->shr splitter): New splitters.
1740 2020-05-04 Jakub Jelinek <jakub@redhat.com>
1742 PR tree-optimization/94718
1743 * match.pd ((X < 0) != (Y < 0) into (X ^ Y) < 0): New simplification.
1745 PR tree-optimization/94718
1746 * match.pd (bitop (convert @0) (convert? @1)): For GIMPLE, if we can,
1747 replace two nop conversions on bit_{and,ior,xor} argument
1748 and result with just one conversion on the result or another argument.
1750 PR tree-optimization/94718
1751 * fold-const.c (fold_binary_loc): Move (X & C) eqne (Y & C)
1752 -> (X ^ Y) & C eqne 0 optimization to ...
1753 * match.pd ((X & C) op (Y & C) into (X ^ Y) & C op 0): ... here.
1755 * opts.c (get_option_html_page): Instead of hardcoding a list of
1756 options common between C/C++ and Fortran only use gfortran/
1757 documentation for warnings that have CL_Fortran set but not
1760 2020-05-03 Uroš Bizjak <ubizjak@gmail.com>
1762 * config/i386/i386-expand.c (ix86_expand_int_movcc):
1763 Use plus_constant instead of gen_rtx_PLUS with GEN_INT.
1764 (emit_memmov): Ditto.
1765 (emit_memset): Ditto.
1766 (ix86_expand_strlensi_unroll_1): Ditto.
1767 (release_scratch_register_on_entry): Ditto.
1768 (gen_frame_set): Ditto.
1769 (ix86_emit_restore_reg_using_pop): Ditto.
1770 (ix86_emit_outlined_ms2sysv_restore): Ditto.
1771 (ix86_expand_epilogue): Ditto.
1772 (ix86_expand_split_stack_prologue): Ditto.
1773 * config/i386/i386.md (push immediate splitter): Ditto.
1777 2020-05-02 Iain Sandoe <iain@sandoe.co.uk>
1779 PR translation/93861
1780 * config/darwin-driver.c (darwin_driver_init): Adjust spelling in
1783 2020-05-02 Jakub Jelinek <jakub@redhat.com>
1785 * config/tilegx/tilegx.md
1786 (insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>): Use <I124MODE:n>
1787 rather than just <n>.
1789 2020-05-01 H.J. Lu <hongjiu.lu@intel.com>
1792 * cfgexpand.c (pass_expand::execute): Set crtl->patch_area_size
1793 and crtl->patch_area_entry.
1794 * emit-rtl.h (rtl_data): Add patch_area_size and patch_area_entry.
1795 * opts.c (common_handle_option): Limit
1796 function_entry_patch_area_size and function_entry_patch_area_start
1797 to USHRT_MAX. Fix a typo in error message.
1798 * varasm.c (assemble_start_function): Use crtl->patch_area_size
1799 and crtl->patch_area_entry.
1800 * doc/invoke.texi: Document the maximum value for
1801 -fpatchable-function-entry.
1803 2020-05-01 Iain Sandoe <iain@sandoe.co.uk>
1805 * config/i386/darwin.h: Repair SUBTARGET_INIT_BUILTINS.
1806 Override SUBTARGET_SHADOW_OFFSET macro.
1808 2020-05-01 Andreas Tobler <andreast@gcc.gnu.org>
1810 * config/i386/i386.h: Define a new macro: SUBTARGET_SHADOW_OFFSET.
1811 * config/i386/i386.c (ix86_asan_shadow_offset): Use this macro.
1812 * config/i386/darwin.h: Override the SUBTARGET_SHADOW_OFFSET macro.
1813 * config/i386/freebsd.h: Likewise.
1814 * config/freebsd.h (LIBASAN_EARLY_SPEC): Define.
1815 LIBTSAN_EARLY_SPEC): Likewise. (LIBLSAN_EARLY_SPEC): Likewise.
1817 2020-04-30 Alexandre Oliva <oliva@adacore.com>
1819 * doc/sourcebuild.texi (Effective-Target Keywords): Document
1820 the newly-introduced fileio effective target.
1822 2020-04-30 Richard Sandiford <richard.sandiford@arm.com>
1824 PR rtl-optimization/94740
1825 * cse.c (cse_process_notes_1): Replace with...
1826 (cse_process_note_1): ...this new function, acting as a
1827 simplify_replace_fn_rtx callback to process_note. Handle only
1828 REGs and MEMs directly. Validate the MEM if cse_process_note
1829 changes its address.
1830 (cse_process_notes): Replace with...
1831 (cse_process_note): ...this new function.
1832 (cse_extended_basic_block): Update accordingly, iterating over
1833 the register notes and passing individual notes to cse_process_note.
1835 2020-04-30 Carl Love <cel@us.ibm.com>
1837 * config/rs6000/emmintrin.h (_mm_movemask_epi8): Fix comment.
1839 2020-04-30 Martin Jambor <mjambor@suse.cz>
1842 * cgraph.c (clone_of_p): Also consider thunks whih had their bodies
1843 saved by the inliner and thunks which had their call inlined.
1844 * ipa-inline-transform.c (save_inline_function_body): Fill in
1845 former_clone_of of new body holders.
1847 2020-04-30 Jakub Jelinek <jakub@redhat.com>
1849 * BASE-VER: Set to 11.0.0.
1851 2020-04-30 Jonathan Wakely <jwakely@redhat.com>
1853 * pretty-print.c (pp_take_prefix): Fix spelling in comment.
1855 2020-04-30 Marek Polacek <polacek@redhat.com>
1858 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
1859 (check_aligned_type): Check if TYPE_USER_ALIGN match.
1861 2020-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1863 * config/aarch64/aarch64.h (TARGET_OUTLINE_ATOMICS): Define.
1864 * config/aarch64/aarch64.opt (moutline-atomics): Change to Int variable.
1865 * doc/invoke.texi (moutline-atomics): Document as on by default.
1867 2020-04-30 Szabolcs Nagy <szabolcs.nagy@arm.com>
1870 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Remove
1871 the check for NOTE_INSN_DELETED_LABEL.
1873 2020-04-30 Jakub Jelinek <jakub@redhat.com>
1875 * configure.ac (--with-documentation-root-url,
1876 --with-changes-root-url): Diagnose URL not ending with /,
1877 use AC_DEFINE_UNQUOTED instead of AC_SUBST.
1878 * opts.h (get_changes_url): Remove.
1879 * opts.c (get_changes_url): Remove.
1880 * Makefile.in (CFLAGS-opts.o): Don't add -DDOCUMENTATION_ROOT_URL
1881 or -DCHANGES_ROOT_URL.
1882 * doc/install.texi (--with-documentation-root-url,
1883 --with-changes-root-url): Document.
1884 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Don't call
1885 get_changes_url and free, change url variable type to const char * and
1886 set it to CHANGES_ROOT_URL "gcc-10/changes.html#empty_base".
1887 * config/s390/s390.c (s390_function_arg_vector,
1888 s390_function_arg_float): Likewise.
1889 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
1891 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
1893 * config.in: Regenerate.
1894 * configure: Regenerate.
1896 2020-04-30 Christophe Lyon <christophe.lyon@linaro.org>
1899 * config/arm/arm.c (isr_attribute_args): Remove duplicate entries.
1901 2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
1903 * config/s390/constraints.md ("j>f", "jb4"): New constraints.
1904 * config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix
1906 * config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a
1908 ("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst.
1909 Change constraint for vlrl/vstrl to jb4.
1911 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1913 * var-tracking.c (vt_initialize): Move variables pre and post
1914 into inner block and initialize both in order to fix warning
1915 about uninitialized use. Remove unnecessary checks for
1916 frame_pointer_needed.
1918 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1920 * toplev.c (output_stack_usage_1): Ensure that first
1921 argument to fprintf is not null.
1923 2020-04-29 Jakub Jelinek <jakub@redhat.com>
1925 * configure.ac (-with-changes-root-url): New configure option,
1926 defaulting to https://gcc.gnu.org/.
1927 * Makefile.in (CFLAGS-opts.o): Define CHANGES_ROOT_URL for
1929 * pretty-print.c (get_end_url_string): New function.
1930 (pp_format): Handle %{ and %} for URLs.
1931 (pp_begin_url): Use pp_string instead of pp_printf.
1932 (pp_end_url): Use get_end_url_string.
1933 * opts.h (get_changes_url): Declare.
1934 * opts.c (get_changes_url): New function.
1935 * config/rs6000/rs6000-call.c: Include opts.h.
1936 (rs6000_discover_homogeneous_aggregate): Use %{in GCC 10.1%} instead
1937 of just in GCC 10.1 in diagnostics and add URL.
1938 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Likewise.
1939 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
1941 * config/s390/s390.c (s390_function_arg_vector,
1942 s390_function_arg_float): Likewise.
1943 * configure: Regenerated.
1946 * config/s390/s390.c (s390_function_arg_vector,
1947 s390_function_arg_float): Use DECL_FIELD_ABI_IGNORED instead of
1948 cxx17_empty_base_field_p. In -Wpsabi diagnostics use the type
1949 passed to the function rather than the type of the single element.
1950 Rename cxx17_empty_base_seen variable to empty_base_seen, change
1951 type to int, and adjust diagnostics depending on if the field
1952 has [[no_unique_attribute]] or not.
1955 * config/i386/avx512bwintrin.h (_mm512_alignr_epi8,
1956 _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands
1957 used in casts into parens.
1958 * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph,
1959 _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph,
1960 _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph,
1961 _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask,
1962 _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask,
1963 _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask,
1964 _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise.
1965 * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8,
1966 _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8,
1967 _mm256_mask_cmp_epu8_mask): Likewise.
1968 * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph,
1969 _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise.
1970 * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise.
1971 * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise.
1974 * config/i386/avx2intrin.h (_mm_mask_i32gather_pd,
1975 _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd,
1976 _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps,
1977 _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps,
1978 _mm256_mask_i64gather_ps, _mm_i32gather_epi64,
1979 _mm_mask_i32gather_epi64, _mm256_i32gather_epi64,
1980 _mm256_mask_i32gather_epi64, _mm_i64gather_epi64,
1981 _mm_mask_i64gather_epi64, _mm256_i64gather_epi64,
1982 _mm256_mask_i64gather_epi64, _mm_i32gather_epi32,
1983 _mm_mask_i32gather_epi32, _mm256_i32gather_epi32,
1984 _mm256_mask_i32gather_epi32, _mm_i64gather_epi32,
1985 _mm_mask_i64gather_epi32, _mm256_i64gather_epi32,
1986 _mm256_mask_i64gather_epi32): Surround macro parameter uses with
1988 (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd,
1989 _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps,
1990 _mm_i64gather_ps, _mm256_i64gather_ps): Likewise. Don't use
1991 as mask vector containing -1.0 or -1.0f elts, but instead vector
1992 with all bits set using _mm*_cmpeq_p? with zero operands.
1993 * config/i386/avx512fintrin.h (_mm512_i32gather_ps,
1994 _mm512_mask_i32gather_ps, _mm512_i32gather_pd,
1995 _mm512_mask_i32gather_pd, _mm512_i64gather_ps,
1996 _mm512_mask_i64gather_ps, _mm512_i64gather_pd,
1997 _mm512_mask_i64gather_pd, _mm512_i32gather_epi32,
1998 _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64,
1999 _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32,
2000 _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64,
2001 _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps,
2002 _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd,
2003 _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps,
2004 _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd,
2005 _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32,
2006 _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64,
2007 _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32,
2008 _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64,
2009 _mm512_mask_i64scatter_epi64): Surround macro parameter uses with
2011 * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd,
2012 _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd,
2013 _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd,
2014 _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd,
2015 _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd,
2016 _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd,
2017 _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd,
2018 _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd,
2019 _mm512_mask_prefetch_i64scatter_ps): Likewise.
2020 * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps,
2021 _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd,
2022 _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps,
2023 _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd,
2024 _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32,
2025 _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64,
2026 _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32,
2027 _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64,
2028 _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps,
2029 _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps,
2030 _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd,
2031 _mm_mask_i32scatter_pd, _mm256_i64scatter_ps,
2032 _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps,
2033 _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd,
2034 _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32,
2035 _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32,
2036 _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64,
2037 _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64,
2038 _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32,
2039 _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32,
2040 _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64,
2041 _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64,
2042 _mm_mask_i64scatter_epi64): Likewise.
2044 2020-04-29 Jeff Law <law@redhat.com>
2046 * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific
2047 division instructions are 4 bytes long.
2049 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2052 * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use
2053 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
2054 fenv_var, fenv_clear and old_fenv variables. For fenv_addr
2055 take address of TARGET_EXPR of fenv_var with void_node initializer.
2058 2020-04-29 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2060 PR tree-optimization/94774
2061 * gimple-ssa-sprintf.c (try_substitute_return_value): Initialize
2064 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2066 * calls.h (cxx17_empty_base_field_p): Turn into a function declaration.
2067 * calls.c (cxx17_empty_base_field_p): New function. Check
2068 DECL_ARTIFICIAL and RECORD_OR_UNION_TYPE_P in addition to the
2071 2020-04-29 H.J. Lu <hongjiu.lu@intel.com>
2074 * config/i386/i386-options.c (ix86_set_indirect_branch_type):
2075 Allow -fcf-protection with -mindirect-branch=thunk-extern and
2076 -mfunction-return=thunk-extern.
2077 * doc/invoke.texi: Update notes for -fcf-protection=branch with
2078 -mindirect-branch=thunk-extern and -mindirect-return=thunk-extern.
2080 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2082 * doc/sourcebuild.texi: Add missing arm_arch_v8a_hard_ok anchor.
2084 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2086 * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
2087 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
2088 fenv_var and new_fenv_var.
2090 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2092 * doc/sourcebuild.texi (arm_arch_v8a_hard_ok): Document new
2093 effective-target keyword.
2094 (arm_arch_v8a_hard_multilib): Likewise.
2095 (arm_arch_v8a_hard): Document new dg-add-options keyword.
2096 * config/arm/arm.c (arm_return_in_memory): Note that the APCS
2097 code is deprecated and has not been updated to handle
2098 DECL_FIELD_ABI_IGNORED.
2099 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
2100 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
2101 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
2102 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
2103 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
2104 something actually is a HFA or HVA. Record whether we see a
2105 [[no_unique_address]] field that previous GCCs would not have
2106 ignored in this way.
2107 (aapcs_vfp_is_call_or_return_candidate): Update the calls to
2108 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
2109 [[no_unique_address]] case. Use TYPE_MAIN_VARIANT in the
2110 diagnostic messages.
2111 (arm_needs_doubleword_align): Add a comment explaining why we
2112 consider even zero-sized fields.
2114 2020-04-29 Richard Biener <rguenther@suse.de>
2115 Li Zekun <lizekun1@huawei.com>
2118 * tree.c (component_ref_size): Guard against error_mark_node
2119 DECL_INITIAL as it happens with LTO.
2121 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2123 * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add a
2124 comment explaining why we consider even zero-sized fields.
2125 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
2126 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
2127 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
2128 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
2129 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
2130 something actually is a HFA or HVA. Record whether we see a
2131 [[no_unique_address]] field that previous GCCs would not have
2132 ignored in this way.
2133 (aarch64_vfp_is_call_or_return_candidate): Add a parameter to say
2134 whether diagnostics should be suppressed. Update the calls to
2135 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
2136 [[no_unique_address]] case.
2137 (aarch64_return_in_msb): Update call accordingly, never silencing
2139 (aarch64_function_value): Likewise.
2140 (aarch64_return_in_memory_1): Likewise.
2141 (aarch64_init_cumulative_args): Likewise.
2142 (aarch64_gimplify_va_arg_expr): Likewise.
2143 (aarch64_pass_by_reference_1): Take a CUMULATIVE_ARGS pointer and
2144 use it to decide whether arch64_vfp_is_call_or_return_candidate
2146 (aarch64_pass_by_reference): Update calls accordingly.
2147 (aarch64_vfp_is_call_candidate): Use the CUMULATIVE_ARGS argument
2148 to decide whether arch64_vfp_is_call_or_return_candidate should be
2151 2020-04-29 Haijian Zhang <z.zhanghaijian@huawei.com>
2154 * config/aarch64/aarch64-builtins.c
2155 (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of
2156 MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and
2159 2020-04-29 Thomas Schwinge <thomas@codesourcery.com>
2161 * configure.ac <$enable_offload_targets>: Do parsing as done
2163 * configure: Regenerate.
2165 * configure.ac <$enable_offload_targets>: 'amdgcn' is 'gcn'.
2166 * configure: Regenerate.
2169 * rtlanal.c (set_noop_p): Handle non-constant selectors.
2172 * common/config/gcn/gcn-common.c (gcn_except_unwind_info): New
2174 (TARGET_EXCEPT_UNWIND_INFO): Define.
2176 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2179 * config/gcn/gcn.md (*mov<mode>_insn): Use
2180 'reg_overlap_mentioned_p' to check for overlap.
2183 * config/ia64/ia64.c (hfa_element_mode): Use DECL_FIELD_ABI_IGNORED
2184 instead of cxx17_empty_base_field_p.
2187 * tree-core.h (tree_decl_common): Note decl_flag_0 used for
2188 DECL_FIELD_ABI_IGNORED.
2189 * tree.h (DECL_FIELD_ABI_IGNORED): Define.
2190 * calls.h (cxx17_empty_base_field_p): Change into a temporary
2191 macro, check DECL_FIELD_ABI_IGNORED flag with no "no_unique_address"
2193 * calls.c (cxx17_empty_base_field_p): Remove.
2194 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Handle
2195 DECL_FIELD_ABI_IGNORED.
2196 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
2197 * lto-streamer-out.c (hash_tree): Likewise.
2198 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Rename
2199 cxx17_empty_base_seen to empty_base_seen, change type to int *,
2200 adjust recursive calls, use DECL_FIELD_ABI_IGNORED instead of
2201 cxx17_empty_base_field_p, if "no_unique_address" attribute is
2202 present, propagate that to the caller too.
2203 (rs6000_discover_homogeneous_aggregate): Adjust
2204 rs6000_aggregate_candidate caller, emit different diagnostics
2205 when c++17 empty base fields are present and when empty
2206 [[no_unique_address]] fields are present.
2207 * config/rs6000/rs6000.c (rs6000_special_round_type_align,
2208 darwin_rs6000_special_round_type_align): Skip DECL_FIELD_ABI_IGNORED
2211 2020-04-29 Richard Biener <rguenther@suse.de>
2213 * tree-ssa-loop-im.c (ref_always_accessed::operator ()):
2214 Just check whether the stmt stores.
2216 2020-04-28 Alexandre Oliva <oliva@adacore.com>
2219 * config/rs6000/rs6000.md (rs6000_mffsl): Copy result to
2220 output operand in emulation. Don't overwrite pseudos.
2222 2020-04-28 Jeff Law <law@redhat.com>
2224 * config/h8300/h8300.md (H8/SX mult patterns): All H8/SX specific
2225 multiply patterns are 4 bytes long.
2227 2020-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2229 * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option.
2230 * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option.
2232 2020-04-28 Matthew Malcomson <matthew.malcomson@arm.com>
2233 Jakub Jelinek <jakub@redhat.com>
2236 * config/arm/arm.c (aapcs_vfp_sub_candidate): Account for C++17 empty
2237 base class artificial fields.
2238 (aapcs_vfp_is_call_or_return_candidate): Warn when PCS ABI
2239 decision is different after this fix.
2241 2020-04-28 David Malcolm <dmalcolm@redhat.com>
2247 * doc/invoke.texi (Static Analyzer Options): Remove
2248 -Wanalyzer-use-of-uninitialized-value.
2249 (-Wno-analyzer-use-of-uninitialized-value): Remove item.
2251 2020-04-28 Jakub Jelinek <jakub@redhat.com>
2253 PR tree-optimization/94809
2254 * tree.c (build_call_expr_internal_loc_array): Call
2255 process_call_operands.
2257 2020-04-27 Anton Youdkevitch <anton.youdkevitch@bell-sw.com>
2259 * config/aarch64/aarch64-cores.def (thunderx3t110): Add the chip name.
2260 * config/aarch64/aarch64-tune.md: Regenerate.
2261 * config/aarch64/aarch64.c (thunderx3t110_addrcost_table): Define.
2262 (thunderx3t110_regmove_cost): Likewise.
2263 (thunderx3t110_vector_cost): Likewise.
2264 (thunderx3t110_prefetch_tune): Likewise.
2265 (thunderx3t110_tunings): Likewise.
2266 * config/aarch64/aarch64-cost-tables.h (thunderx3t110_extra_costs):
2268 * config/aarch64/thunderx3t110.md: New file.
2269 * config/aarch64/aarch64.md: Include thunderx3t110.md.
2270 * doc/invoke.texi (AArch64 options): Add thunderx3t110.
2272 2020-04-28 Jakub Jelinek <jakub@redhat.com>
2275 * config/s390/s390.c (s390_function_arg_vector,
2276 s390_function_arg_float): Emit -Wpsabi diagnostics if the ABI changed.
2278 2020-04-28 Richard Sandiford <richard.sandiford@arm.com>
2280 PR tree-optimization/94727
2281 * tree-vect-stmts.c (vect_is_simple_cond): If both comparison
2282 operands are invariant booleans, use the mask type associated with the
2283 STMT_VINFO_VECTYPE. Use !slp_node instead of !vectype to exclude SLP.
2284 (vectorizable_condition): Pass vectype unconditionally to
2285 vect_is_simple_cond.
2287 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2290 * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use
2291 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
2292 sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var.
2294 2020-04-27 David Malcolm <dmalcolm@redhat.com>
2297 * configure.ac (DOCUMENTATION_ROOT_URL): Drop trailing "gcc/" from
2298 default value, so that it can by supplied by get_option_html_page.
2299 * configure: Regenerate.
2300 * opts.c: Include "selftest.h".
2301 (get_option_html_page): New function.
2302 (get_option_url): Use it. Reformat to place comments next to the
2303 expressions they refer to.
2304 (selftest::test_get_option_html_page): New.
2305 (selftest::opts_c_tests): New.
2306 * selftest-run-tests.c (selftest::run_tests): Call
2307 selftest::opts_c_tests.
2308 * selftest.h (selftest::opts_c_tests): New decl.
2310 2020-04-27 Richard Sandiford <richard.sandiford@arm.com>
2312 * config/arm/arm-builtins.c (arm_expand_builtin_args): Only apply
2313 UINTVAL to CONST_INTs.
2315 2020-04-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2317 * config/arm/constraints.md (e): Remove constraint.
2318 (Te): Define constraint.
2319 * config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in
2320 operand 0 from "e" to "Te".
2321 (vaddvaq_<supf><mode>): Likewise.
2322 (vaddvq_p_<supf><mode>): Likewise.
2323 (vmladavq_<supf><mode>): Likewise.
2324 (vmladavxq_s<mode>): Likewise.
2325 (vmlsdavq_s<mode>): Likewise.
2326 (vmlsdavxq_s<mode>): Likewise.
2327 (vaddvaq_p_<supf><mode>): Likewise.
2328 (vmladavaq_<supf><mode>): Likewise.
2329 (vmladavq_p_<supf><mode>): Likewise.
2330 (vmladavxq_p_s<mode>): Likewise.
2331 (vmlsdavq_p_s<mode>): Likewise.
2332 (vmlsdavxq_p_s<mode>): Likewise.
2333 (vmlsdavaxq_s<mode>): Likewise.
2334 (vmlsdavaq_s<mode>): Likewise.
2335 (vmladavaxq_s<mode>): Likewise.
2336 (vmladavaq_p_<supf><mode>): Likewise.
2337 (vmladavaxq_p_s<mode>): Likewise.
2338 (vmlsdavaq_p_s<mode>): Likewise.
2339 (vmlsdavaxq_p_s<mode>): Likewise.
2341 2020-04-27 Andre Vieira <andre.simoesdiasvieira@arm.com>
2343 * config/arm/arm.c (output_move_neon): Only get the first operand if
2346 2020-04-27 Felix Yang <felix.yang@huawei.com>
2348 PR tree-optimization/94784
2349 * tree-ssa-forwprop.c (simplify_vector_constructor): Flip the
2350 assert around so that it checks that the two vectors have equal
2351 TYPE_VECTOR_SUBPARTS and that converting the corresponding element
2352 types is a useless_type_conversion_p.
2354 2020-04-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
2357 * dwarf2cfi.c (struct GTY): Add ra_mangled.
2358 (cfi_row_equal_p): Check ra_mangled.
2359 (dwarf2out_frame_debug_cfa_window_save): Remove the argument,
2360 this only handles the sparc logic now.
2361 (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for
2362 the aarch64 specific logic.
2363 (dwarf2out_frame_debug): Update to use the new subroutines.
2364 (change_cfi_row): Check ra_mangled.
2366 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2369 * config/s390/s390.c (s390_function_arg_vector,
2370 s390_function_arg_float): Ignore cxx17_empty_base_field_p fields.
2372 2020-04-27 Jiufu Guo <guojiufu@cn.ibm.com>
2374 * common/config/rs6000/rs6000-common.c
2375 (rs6000_option_optimization_table) [OPT_LEVELS_ALL]: Remove turn off
2377 * config/rs6000/rs6000.c (rs6000_option_override_internal): Avoid to
2380 2020-04-27 Martin Liska <mliska@suse.cz>
2383 * cgraph.h (cgraph_node::can_remove_if_no_direct_calls_and_refs_p):
2384 Do not remove ifunc_resolvers in remove unreachable nodes in LTO.
2386 2020-04-27 Xiong Hu Luo <luoxhu@linux.ibm.com>
2389 * config/rs6000/rs6000-logue.c (frame_pointer_needed_indeed):
2391 (rs6000_emit_prologue_components):
2392 Check with frame_pointer_needed_indeed.
2393 (rs6000_emit_epilogue_components): Likewise.
2394 (rs6000_emit_prologue): Likewise.
2395 (rs6000_emit_epilogue): Set frame_pointer_needed_indeed.
2397 2020-04-25 David Edelsohn <dje.gcc@gmail.com>
2399 * config/rs6000/rs6000-logue.c (rs6000_stack_info): Don't push a
2400 stack frame when debugging and flag_compare_debug is enabled.
2402 2020-04-25 Michael Meissner <meissner@linux.ibm.com>
2404 * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to
2405 enable PC-relative addressing for -mcpu=future.
2406 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move
2407 after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS.
2408 * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined,
2409 suppress PC-relative addressing.
2410 (rs6000_option_override_internal): Split up error messages
2411 checking for -mprefixed and -mpcrel. Enable -mpcrel if the target
2414 2020-04-25 Jakub Jelinek <jakub@redhat.com>
2415 Richard Biener <rguenther@suse.de>
2417 PR tree-optimization/94734
2418 PR tree-optimization/89430
2419 * tree-ssa-phiopt.c: Include tree-eh.h.
2420 (cond_store_replacement): Return false if an automatic variable
2421 access could trap. If -fstore-data-races, don't return false
2422 just because an automatic variable is addressable.
2424 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2426 * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
2428 (add<mode>_sext_dup2_exec): Likewise.
2430 2020-04-24 Segher Boessenkool <segher@kernel.crashing.org>
2433 * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little
2434 endian byteshift_val calculation.
2436 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2438 * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
2440 2020-04-24 Richard Sandiford <richard.sandiford@arm.com>
2442 * config/aarch64/arm_sve.h: Add a comment.
2444 2020-04-24 Haijian Zhang <z.zhanghaijian@huawei.com>
2446 PR rtl-optimization/94708
2447 * combine.c (simplify_if_then_else): Add check for
2448 !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode).
2450 2020-04-23 Martin Sebor <msebor@redhat.com>
2453 * common.opt (-Wno-frame-larger-than): New option.
2454 (-Wno-larger-than, -Wno-stack-usage): Same.
2456 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
2458 * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands
2460 (mov<mode>_exec): Likewise.
2461 (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec.
2462 (<convop><mode><vndi>2_exec): Likewise.
2464 2019-04-23 Eric Botcazou <ebotcazou@adacore.com>
2466 PR tree-optimization/94717
2467 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one
2468 of the stores doesn't have the same landing pad number as the first.
2469 (coalesce_immediate_stores): Do not try to coalesce the store using
2470 bswap if it doesn't have the same landing pad number as the first.
2472 2020-04-23 Bill Schmidt <wschmidt@linux.ibm.com>
2474 * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
2475 Replace outdated link to ELFv2 ABI.
2477 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2480 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx
2484 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs
2485 temporarily with non-final second operand and updating it later,
2486 push COMPOUND_EXPRs into a vector and process it in reverse,
2487 creating COMPOUND_EXPRs with the final operands.
2489 2020-04-23 Szabolcs Nagy <szabolcs.nagy@arm.com>
2492 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap
2493 bti c and bti j handling.
2495 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
2496 Thomas Schwinge <thomas@codesourcery.com>
2500 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on
2501 t_async and the wait arguments.
2503 2020-04-23 Richard Sandiford <richard.sandiford@arm.com>
2505 PR tree-optimization/94727
2506 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when
2507 comparing invariant scalar booleans.
2509 2020-04-23 Matthew Malcomson <matthew.malcomson@arm.com>
2510 Jakub Jelinek <jakub@redhat.com>
2513 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17
2514 empty base class artificial fields.
2515 (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is
2516 different after this fix.
2518 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2521 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
2522 Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check
2523 if the same type has been diagnosed most recently already.
2525 2020-04-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2527 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's
2529 (__arm_vbicq_n_s16): Likewise.
2530 (__arm_vbicq_n_u32): Likewise.
2531 (__arm_vbicq_n_s32): Likewise.
2532 (__arm_vbicq): Likewise.
2533 (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype.
2534 (__arm_vbicq_n_s32): Likewise.
2535 (__arm_vbicq_n_u16): Likewise.
2536 (__arm_vbicq_n_u32): Likewise.
2537 (__arm_vdupq_m_n_s8): Likewise.
2538 (__arm_vdupq_m_n_s16): Likewise.
2539 (__arm_vdupq_m_n_s32): Likewise.
2540 (__arm_vdupq_m_n_u8): Likewise.
2541 (__arm_vdupq_m_n_u16): Likewise.
2542 (__arm_vdupq_m_n_u32): Likewise.
2543 (__arm_vdupq_m_n_f16): Likewise.
2544 (__arm_vdupq_m_n_f32): Likewise.
2545 (__arm_vldrhq_gather_offset_s16): Likewise.
2546 (__arm_vldrhq_gather_offset_s32): Likewise.
2547 (__arm_vldrhq_gather_offset_u16): Likewise.
2548 (__arm_vldrhq_gather_offset_u32): Likewise.
2549 (__arm_vldrhq_gather_offset_f16): Likewise.
2550 (__arm_vldrhq_gather_offset_z_s16): Likewise.
2551 (__arm_vldrhq_gather_offset_z_s32): Likewise.
2552 (__arm_vldrhq_gather_offset_z_u16): Likewise.
2553 (__arm_vldrhq_gather_offset_z_u32): Likewise.
2554 (__arm_vldrhq_gather_offset_z_f16): Likewise.
2555 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
2556 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
2557 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
2558 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
2559 (__arm_vldrhq_gather_shifted_offset_f16): Likewise.
2560 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
2561 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
2562 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
2563 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
2564 (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise.
2565 (__arm_vldrwq_gather_offset_s32): Likewise.
2566 (__arm_vldrwq_gather_offset_u32): Likewise.
2567 (__arm_vldrwq_gather_offset_f32): Likewise.
2568 (__arm_vldrwq_gather_offset_z_s32): Likewise.
2569 (__arm_vldrwq_gather_offset_z_u32): Likewise.
2570 (__arm_vldrwq_gather_offset_z_f32): Likewise.
2571 (__arm_vldrwq_gather_shifted_offset_s32): Likewise.
2572 (__arm_vldrwq_gather_shifted_offset_u32): Likewise.
2573 (__arm_vldrwq_gather_shifted_offset_f32): Likewise.
2574 (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise.
2575 (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise.
2576 (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise.
2577 (__arm_vdwdupq_x_n_u8): Likewise.
2578 (__arm_vdwdupq_x_n_u16): Likewise.
2579 (__arm_vdwdupq_x_n_u32): Likewise.
2580 (__arm_viwdupq_x_n_u8): Likewise.
2581 (__arm_viwdupq_x_n_u16): Likewise.
2582 (__arm_viwdupq_x_n_u32): Likewise.
2583 (__arm_vidupq_x_n_u8): Likewise.
2584 (__arm_vddupq_x_n_u8): Likewise.
2585 (__arm_vidupq_x_n_u16): Likewise.
2586 (__arm_vddupq_x_n_u16): Likewise.
2587 (__arm_vidupq_x_n_u32): Likewise.
2588 (__arm_vddupq_x_n_u32): Likewise.
2589 (__arm_vldrdq_gather_offset_s64): Likewise.
2590 (__arm_vldrdq_gather_offset_u64): Likewise.
2591 (__arm_vldrdq_gather_offset_z_s64): Likewise.
2592 (__arm_vldrdq_gather_offset_z_u64): Likewise.
2593 (__arm_vldrdq_gather_shifted_offset_s64): Likewise.
2594 (__arm_vldrdq_gather_shifted_offset_u64): Likewise.
2595 (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise.
2596 (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise.
2597 (__arm_vidupq_m_n_u8): Likewise.
2598 (__arm_vidupq_m_n_u16): Likewise.
2599 (__arm_vidupq_m_n_u32): Likewise.
2600 (__arm_vddupq_m_n_u8): Likewise.
2601 (__arm_vddupq_m_n_u16): Likewise.
2602 (__arm_vddupq_m_n_u32): Likewise.
2603 (__arm_vidupq_n_u16): Likewise.
2604 (__arm_vidupq_n_u32): Likewise.
2605 (__arm_vidupq_n_u8): Likewise.
2606 (__arm_vddupq_n_u16): Likewise.
2607 (__arm_vddupq_n_u32): Likewise.
2608 (__arm_vddupq_n_u8): Likewise.
2610 2020-04-23 Iain Buclaw <ibuclaw@gdcproject.org>
2612 * doc/install.texi (D-Specific Options): Document
2613 --enable-libphobos-checking and --with-libphobos-druntime-only.
2615 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2618 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add
2619 cxx17_empty_base_seen argument. Pass it to recursive calls.
2620 Ignore cxx17_empty_base_field_p fields after setting
2621 *cxx17_empty_base_seen to true.
2622 (rs6000_discover_homogeneous_aggregate): Adjust
2623 rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous
2624 aggregates with C++17 empty base fields.
2627 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
2628 if last_decl is error_mark_node or has such a TREE_TYPE.
2631 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
2632 if last_decl is error_mark_node or has such a TREE_TYPE.
2634 2020-04-22 Felix Yang <felix.yang@huawei.com>
2637 * config/aarch64/aarch64.h (TARGET_SVE):
2638 Add && !TARGET_GENERAL_REGS_ONLY.
2639 (TARGET_SVE2): Add && TARGET_SVE.
2640 (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3,
2641 TARGET_SVE2_SM4): Add && TARGET_SVE2.
2642 * config/aarch64/aarch64-sve-builtins.h
2643 (sve_switcher::m_old_general_regs_only): New member.
2644 * config/aarch64/aarch64-sve-builtins.cc (check_required_registers):
2646 (reported_missing_registers_p): New variable.
2647 (check_required_extensions): Call check_required_registers before
2648 return if all required extenstions are present.
2649 (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in
2650 m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in
2651 global_options.x_target_flags.
2652 (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in
2653 global_options.x_target_flags if m_old_general_regs_only is true.
2655 2020-04-22 Zackery Spytz <zspytz@gmail.com>
2657 * doc/extend.exi: Add "free" to list of other builtin functions
2660 2020-04-20 Aaron Sawdey <acsawdey@linux.ibm.com>
2663 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed"
2665 (store_quadpti): Ditto.
2666 (atomic_load<mode>): Do not swap doublewords if TARGET_PREFIXED as
2667 plq will be used and doesn't need it.
2668 (atomic_store<mode>): Ditto, for pstq.
2670 2020-04-22 Erick Ochoa <erick.ochoa@theobroma-systems.com>
2672 * doc/invoke.texi: Update flags turned on by -O3.
2674 2020-04-22 Jakub Jelinek <jakub@redhat.com>
2677 * config/ia64/ia64.c (hfa_element_mode): Ignore
2678 cxx17_empty_base_field_p fields.
2681 * calls.h (cxx17_empty_base_field_p): Declare.
2682 * calls.c (cxx17_empty_base_field_p): Define.
2684 2020-04-22 Christophe Lyon <christophe.lyon@linaro.org>
2686 * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document.
2688 2020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2689 Andre Vieira <andre.simoesdiasvieira@arm.com>
2690 Mihail Ionescu <mihail.ionescu@arm.com>
2692 * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
2693 * config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
2694 (ALL_QUIRKS): Add quirk_no_asmcpu.
2695 (cortex-m55): Define new cpu.
2696 * config/arm/arm-tables.opt: Regenerate.
2697 * config/arm/arm-tune.md: Likewise.
2698 * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
2700 2020-04-22 Richard Sandiford <richard.sandiford@arm.com>
2702 PR tree-optimization/94700
2703 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing
2704 an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures
2705 of similarly-structured but distinct vector types.
2707 2020-04-21 Martin Sebor <msebor@redhat.com>
2710 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct
2711 the computation of the lower bound of the source access size.
2712 (builtin_access::generic_overlap): Remove a hack for setting ranges
2715 2020-04-21 John David Anglin <danglin@gcc.gnu.org>
2717 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete.
2718 (ASM_WEAKEN_DECL): New define.
2719 (HAVE_GAS_WEAKREF): Undefine.
2721 2020-04-21 Richard Sandiford <richard.sandiford@arm.com>
2723 PR tree-optimization/94683
2724 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a
2725 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured
2726 but distinct vector types.
2728 2020-04-21 Jakub Jelinek <jakub@redhat.com>
2731 * stor-layout.c (place_field, finalize_record_size): Don't emit
2732 -Wpadded warning on TYPE_ARTIFICIAL rli->t.
2733 * ubsan.c (ubsan_get_type_descriptor_type,
2734 ubsan_get_source_location_type, ubsan_create_data): Set
2736 * asan.c (asan_global_struct): Likewise.
2738 2020-04-21 Duan bo <duanbo3@huawei.com>
2741 * config/aarch64/aarch64.c: Add an error message for option conflict.
2742 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is
2743 incompatible with -fpic, -fPIC and -mabi=ilp32.
2745 2020-04-21 Frederik Harwath <frederik@codesourcery.com>
2748 * omp-low.c (new_omp_context): Remove assignments to
2749 ctx->outer_reduction_clauses and ctx->local_reduction_clauses.
2751 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
2753 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
2754 ("popcountv2di2_vx"): Use simplify_gen_subreg.
2756 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
2759 * config/s390/s390-builtin-types.def: Add 3 new function modes.
2760 * config/s390/s390-builtins.def: Add mode dependent low-level
2761 builtin and map the overloaded builtins to these.
2762 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
2763 ("vsel<V_HW"): ... this and rewrite the pattern with bitops.
2765 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
2767 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo
2768 has a variable VF, prefer new_loop_vinfo if it is cheaper for the
2769 estimated VF and is no worse at double the estimated VF.
2771 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
2774 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix
2775 order of arguments to rtx_vector_builder.
2776 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise.
2777 When extending the trailing constants to a full vector, replace any
2778 variables with zeros.
2780 2020-04-20 Jan Hubicka <hubicka@ucw.cz>
2783 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local
2786 2020-04-20 Martin Liska <mliska@suse.cz>
2788 * symtab.c (symtab_node::dump_references): Add space after
2790 (symtab_node::dump_referring): Likewise.
2792 2020-04-18 Jeff Law <law@redhat.com>
2795 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking
2798 2020-04-18 Iain Buclaw <ibuclaw@gdcproject.org>
2800 * doc/sourcebuild.texi (Effective-Target Keywords, Environment
2801 attributes): Document d_runtime_has_std_library.
2803 2020-04-17 Jeff Law <law@redhat.com>
2805 PR rtl-optimization/90275
2806 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels
2807 when the destination has a REG_UNUSED note.
2809 2020-04-17 Tobias Burnus <tobias@codesourcery.com>
2812 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to
2815 2020-04-17 Richard Sandiford <richard.sandiford@arm.com>
2817 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function.
2818 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the
2819 cost of load and store insns if one loop iteration has enough scalar
2820 elements to use an Advanced SIMD LDP or STP.
2821 (aarch64_add_stmt_cost): Update call accordingly.
2823 2020-04-17 Jakub Jelinek <jakub@redhat.com>
2824 Jeff Law <law@redhat.com>
2827 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than
2828 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision,
2829 or pos + len >= 32, or pos + len is equal to operands[2] precision
2830 and operands[2] is not a register operand. During splitting perform
2831 SImode AND if operands[0] doesn't have CCZmode and pos + len is
2832 equal to mode precision.
2834 2020-04-17 Richard Biener <rguenther@suse.de>
2837 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate
2839 * dwarf2out.c (dw_val_equal_p): Fix pasto in
2840 dw_val_class_vms_delta comparison.
2841 * optabs.c (expand_binop_directly): Fix pasto in commutation
2843 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in
2846 2020-04-17 Jakub Jelinek <jakub@redhat.com>
2848 PR rtl-optimization/94618
2849 * cfgrtl.c (delete_insn_and_edges): Set purge not just when
2850 insn is the BB_END of its block, but also when it is only followed
2851 by DEBUG_INSNs in its block.
2853 PR tree-optimization/94621
2854 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN.
2855 Move id->adjust_array_error_bounds check first in the condition.
2857 2020-04-17 Martin Liska <mliska@suse.cz>
2858 Jonathan Yong <10walls@gmail.com>
2860 PR gcov-profile/94570
2861 * coverage.c (coverage_init): Use separator properly.
2863 2020-04-16 Peter Bergner <bergner@linux.ibm.com>
2865 PR rtl-optimization/93974
2866 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.
2867 (rs6000_cannot_substitute_mem_equiv_p): New function.
2869 2020-04-16 Martin Jambor <mjambor@suse.cz>
2872 * ipa-inline.h (ipa_saved_clone_sources): Declare.
2873 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable.
2874 (save_inline_function_body): Link the new body holder with the
2876 * cgraph.c: Include ipa-inline.h.
2877 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from
2878 the statement in ipa_saved_clone_sources.
2879 * cgraphunit.c: Include ipa-inline.h.
2880 (expand_all_functions): Free ipa_saved_clone_sources.
2882 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
2885 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
2886 the VNx16BI lowpart of the recursively-generated constant.
2888 2020-04-16 Martin Liska <mliska@suse.cz>
2889 Jakub Jelinek <jakub@redhat.com>
2892 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
2893 DECL_IS_REPLACEABLE_OPERATOR during cloning.
2894 * tree-ssa-dce.c (valid_new_delete_pair_p): New function.
2895 (propagate_necessity): Check operator names.
2897 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
2899 PR rtl-optimization/94605
2900 * early-remat.c (early_remat::process_block): Handle insns that
2901 set multiple candidate registers.
2902 2020-04-16 Jan Hubicka <hubicka@ucw.cz>
2904 PR gcov-profile/93401
2905 * common.opt (profile-prefix-path): New option.
2906 * coverae.c: Include diagnostics.h.
2907 (coverage_init): Strip profile prefix path.
2908 * doc/invoke.texi (-fprofile-prefix-path): Document.
2910 2020-04-16 Richard Biener <rguenther@suse.de>
2913 * expr.c (emit_move_multi_word): Do not generate code when
2914 the destination part is undefined_operand_subword_p.
2915 * lower-subreg.c (resolve_clobber): Look through a paradoxica
2918 2020-04-16 Martin Jambor <mjambor@suse.cz>
2920 PR tree-optimization/94598
2921 * tree-sra.c (verify_sra_access_forest): Fix verification of total
2922 scalarization accesses under access to one-element arrays.
2924 2020-04-16 Jakub Jelinek <jakub@redhat.com>
2927 * function.c (assign_parm_find_data_types): Add workaround for
2928 BROKEN_VALUE_INITIALIZATION compilers.
2930 2020-04-16 Richard Biener <rguenther@suse.de>
2932 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME
2935 2020-04-15 Uroš Bizjak <ubizjak@gmail.com>
2938 * config/i386/i386-builtin.def (__builtin_ia32_movq128):
2939 Require OPTION_MASK_ISA_SSE2.
2941 2020-04-15 Gustavo Romero <gromero@linux.ibm.com>
2944 * dumpfile.c (selftest::temp_dump_context::temp_dump_context):
2945 Don't construct a dump_context temporary to call static method.
2947 2020-04-15 Andrea Corallo <andrea.corallo@arm.com>
2949 * config/aarch64/falkor-tag-collision-avoidance.c
2950 (valid_src_p): Check for aarch64_address_info type before
2951 accessing base field.
2953 2020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
2955 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern.
2956 (V_sz_elem2): Remove unused mode attribute.
2958 2020-04-15 Matthew Malcomson <matthew.malcomson@arm.com>
2960 * config/arm/arm.md (arm_movdi): Disallow for MVE.
2962 2020-04-15 Richard Biener <rguenther@suse.de>
2965 * tree-ssa-alias.c (same_type_for_tbaa): Defer to
2966 alias_sets_conflict_p for pointers.
2968 2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
2971 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
2972 (extendhisi2_internal): Add %v1 before the load instructions.
2974 2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com>
2977 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to
2978 use PC-relative addressing for TLS references.
2980 2020-04-14 Martin Jambor <mjambor@suse.cz>
2983 * ipa-sra.c: Include internal-fn.h.
2984 (enum isra_scan_context): Update comment.
2985 (scan_function): Treat calls to internal_functions like loads or stores.
2987 2020-04-14 Yang Yang <yangyang305@huawei.com>
2989 PR tree-optimization/94574
2990 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
2991 whether a vector-insert is rewritable using a BIT_INSERT_EXPR.
2993 2020-04-14 H.J. Lu <hongjiu.lu@intel.com>
2996 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.
2998 2020-04-13 Martin Sebor <msebor@redhat.com>
3000 * doc/extend.texi (-Wall): Mention -Wformat-overflow and
3001 -Wformat-truncation. Move -Wzero-length-bounds last.
3002 (-Wrestrict): Document positive form of option enabled by -Wall.
3004 2020-04-13 Zachary Spytz <zspytz@gmail.com>
3006 * doc/extend.texi: Add realloc to list of built-in functions
3007 are recognized by the compiler.
3009 2020-04-13 H.J. Lu <hongjiu.lu@intel.com>
3012 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame
3013 pointer in word_mode for eh_return epilogues.
3015 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3017 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to
3018 memory references in %B, %C and %D operand selectors when the inner
3019 operand is a post increment address.
3021 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3023 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory
3024 reference by 4 bytes, and %D memory reference by 6 bytes.
3026 2020-04-11 Uroš Bizjak <ubizjak@gmail.com>
3029 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2
3030 condition for V4SI, V8HI and V16QI modes.
3032 2020-04-11 Jakub Jelinek <jakub@redhat.com>
3036 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on
3039 2020-04-10 Thomas Schwinge <thomas@codesourcery.com>
3043 * omp-general.c (oacc_verify_routine_clauses): Diagnose if
3044 "#pragma omp declare target" has also been applied.
3046 2020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3048 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn
3049 when to emit the epilogue_helper insn.
3050 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the
3053 2020-04-09 Jakub Jelinek <jakub@redhat.com>
3056 * cselib.h (cselib_record_sp_cfa_base_equiv,
3057 cselib_sp_derived_value_p): Declare.
3058 * cselib.c (cselib_record_sp_cfa_base_equiv,
3059 cselib_sp_derived_value_p): New functions.
3060 * var-tracking.c (add_stores): Don't record MO_VAL_SET for
3061 cselib_sp_derived_value_p values.
3062 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the
3063 start of extended basic blocks other than the first one
3064 for !frame_pointer_needed functions.
3066 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3068 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw)
3069 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw)
3070 (aarch64_sve2048_hw): Document.
3071 * config/aarch64/aarch64-protos.h
3072 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare.
3073 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
3074 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled.
3075 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New
3077 (find_type_suffix_for_scalar_type): Use it instead of comparing
3079 (function_resolver::infer_vector_or_tuple_type): Likewise.
3080 (function_resolver::require_vector_type): Likewise.
3081 (handle_arm_sve_vector_bits_attribute): New function.
3082 * config/aarch64/aarch64.c (pure_scalable_type_info): New class.
3083 (aarch64_attribute_table): Add arm_sve_vector_bits.
3084 (aarch64_return_in_memory_1):
3085 (pure_scalable_type_info::piece::get_rtx): New function.
3086 (pure_scalable_type_info::num_zr): Likewise.
3087 (pure_scalable_type_info::num_pr): Likewise.
3088 (pure_scalable_type_info::get_rtx): Likewise.
3089 (pure_scalable_type_info::analyze): Likewise.
3090 (pure_scalable_type_info::analyze_registers): Likewise.
3091 (pure_scalable_type_info::analyze_array): Likewise.
3092 (pure_scalable_type_info::analyze_record): Likewise.
3093 (pure_scalable_type_info::add_piece): Likewise.
3094 (aarch64_some_values_include_pst_objects_p): Likewise.
3095 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info
3096 to analyze whether the type is returned in SVE registers.
3097 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type
3098 is passed in SVE registers.
3099 (aarch64_pass_by_reference_1): New function, extracted from...
3100 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info
3101 to analyze whether the type is a pure scalable type and, if so,
3102 whether it should be passed by reference.
3103 (aarch64_return_in_msb): Return false for pure scalable types.
3104 (aarch64_function_value_1): Fold back into...
3105 (aarch64_function_value): ...this function. Use
3106 pure_scalable_type_info to analyze whether the type is a pure
3107 scalable type and, if so, which registers it should use. Handle
3108 types that include pure scalable types but are not themselves
3109 pure scalable types.
3110 (aarch64_return_in_memory_1): New function, split out from...
3111 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info
3112 to analyze whether the type is a pure scalable type and, if so,
3113 whether it should be returned by reference.
3114 (aarch64_layout_arg): Remove orig_mode argument. Use
3115 pure_scalable_type_info to analyze whether the type is a pure
3116 scalable type and, if so, which registers it should use. Handle
3117 types that include pure scalable types but are not themselves
3118 pure scalable types.
3119 (aarch64_function_arg): Update call accordingly.
3120 (aarch64_function_arg_advance): Likewise.
3121 (aarch64_pad_reg_upward): On big-endian targets, return false for
3122 pure scalable types that are smaller than 16 bytes.
3123 (aarch64_member_type_forces_blk): New function.
3124 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types.
3125 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that
3126 correspond to built-in SVE types. Do not rely on a vector mode
3127 if the type includes an pure scalable type. When returning true,
3128 assert that the mode is not an SVE mode.
3129 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE
3130 built-in types here. When returning true, assert that the type
3131 does not have an SVE mode.
3132 (aarch64_can_change_mode_class): Don't allow anything to change
3133 between a predicate mode and a non-predicate mode. Also don't
3134 allow changes between SVE vector modes and other modes that
3135 might be bigger than 128 bits.
3136 (aarch64_invalid_binary_op): Reject binary operations that mix
3137 SVE and GNU vector types.
3138 (TARGET_MEMBER_TYPE_FORCES_BLK): Define.
3140 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3142 * config/aarch64/aarch64.c (aarch64_attribute_table): Add
3143 "SVE sizeless type".
3144 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless)
3145 (sizeless_type_p): New functions.
3146 (register_builtin_types): Apply make_type_sizeless to the type.
3147 (register_tuple_type): Likewise.
3148 (verify_type_context): Use sizeless_type_p instead of builin_type_p.
3150 2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
3152 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for
3155 2020-04-09 Martin Jambor <mjambor@suse.cz>
3156 Richard Biener <rguenther@suse.de>
3158 PR tree-optimization/94482
3159 * tree-sra.c (create_access_replacement): Dump new replacement with
3161 (sra_modify_expr): Fix handling of cases when the original EXPR writes
3162 to only part of the replacement.
3163 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
3164 the first operand of combinations into REAL/IMAGPART_EXPR and
3167 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3169 * doc/sourcebuild.texi (check-function-bodies): Treat the third
3170 parameter as a list of option regexps and require each regexp
3173 2020-04-09 Andrea Corallo <andrea.corallo@arm.com>
3176 * config/aarch64/falkor-tag-collision-avoidance.c
3177 (valid_src_p): Fix missing rtx type check.
3179 2020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com>
3180 Richard Biener <rguenther@suse.de>
3182 PR tree-optimization/93674
3183 * tree-ssa-loop-ivopts.c (langhooks.h): New include.
3184 (add_iv_candidate_for_use): For iv_use of non integer or pointer type,
3185 or non-mode precision type, add candidate in unsigned type with the
3188 2020-04-08 Clement Chigot <clement.chigot@atos.net>
3190 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128.
3191 * config/rs6000/aix71.h (LIB_SPEC): Likewise.
3192 * config/rs6000/aix72.h (LIB_SPEC): Likewise.
3194 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3197 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
3199 * reload1.c (eliminate_regs_1): Avoid creating
3200 (plus (reg) (const_int 0)) in DEBUG_INSNs.
3202 PR tree-optimization/94524
3203 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
3204 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
3205 op1 rather than op1 itself at the end. Punt for signed modulo by
3206 most negative constant.
3207 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
3208 modulo by most negative constant.
3210 2020-04-08 Richard Biener <rguenther@suse.de>
3212 PR rtl-optimization/93946
3213 * cse.c (cse_insn): Record the tabled expression in
3214 src_related. Verify a redundant store removal is valid.
3216 2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
3219 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert
3220 ENDBR at function entry if function will be called indirectly.
3222 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3225 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
3228 2020-04-08 Martin Liska <mliska@suse.cz>
3231 * gimple.c (gimple_call_operator_delete_p): Rename to...
3232 (gimple_call_replaceable_operator_delete_p): ... this.
3233 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
3234 * gimple.h (gimple_call_operator_delete_p): Rename to ...
3235 (gimple_call_replaceable_operator_delete_p): ... this.
3236 * tree-core.h (tree_function_decl): Add replaceable_operator
3238 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1):
3239 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
3240 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p.
3241 (eliminate_unnecessary_stmts): Likewise.
3242 * tree-streamer-in.c (unpack_ts_function_decl_value_fields):
3243 Pack DECL_IS_REPLACEABLE_OPERATOR.
3244 * tree-streamer-out.c (pack_ts_function_decl_value_fields):
3245 Unpack the field here.
3246 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New.
3247 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New.
3248 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New.
3249 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable.
3250 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare
3251 replaceable operator flags.
3253 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
3254 Matthew Malcomson <matthew.malcomson@arm.com>
3256 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
3257 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
3258 (CX_TERNARY_QUALIFIERS): Likewise.
3259 (ARM_BUILTIN_CDE_PATTERN_START): Likewise.
3260 (ARM_BUILTIN_CDE_PATTERN_END): Likewise.
3261 (arm_init_acle_builtins): Initialize CDE builtins.
3262 (arm_expand_acle_builtin): Check CDE constant operands.
3263 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
3264 of CDE constant operand.
3265 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
3267 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
3268 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
3269 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
3270 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
3271 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
3272 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
3273 * config/arm/arm_cde_builtins.def: New file.
3274 * config/arm/iterators.md (V_reg): New attribute of SI.
3275 * config/arm/predicates.md (const_int_coproc_operand): New.
3276 (const_int_vcde1_operand, const_int_vcde2_operand): New.
3277 (const_int_vcde3_operand): New.
3278 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
3279 * config/arm/vfp.md (arm_vcx1<mode>): New entry.
3280 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
3281 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.
3283 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
3285 * config.gcc: Add arm_cde.h.
3286 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
3287 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
3288 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
3289 * config/arm/arm.c (arm_option_reconfigure_globals): Configure
3290 arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
3291 * config/arm/arm.h (TARGET_CDE): New macro.
3292 * config/arm/arm_cde.h: New file.
3293 * doc/invoke.texi: Document CDE options +cdecp[0-7].
3294 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
3296 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
3298 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3300 PR rtl-optimization/94516
3301 * postreload.c: Include rtl-iter.h.
3302 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
3303 looking for all MEMs with RTX_AUTOINC operand.
3304 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.
3306 2020-04-08 Tobias Burnus <tobias@codesourcery.com>
3308 * omp-grid.c (grid_eliminate_combined_simd_part): Use
3309 OMP_CLAUSE_CODE to access the omp clause code.
3311 2020-04-07 Jeff Law <law@redhat.com>
3313 PR rtl-optimization/92264
3314 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when
3315 the destination is the stack pointer.
3317 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3319 PR rtl-optimization/94291
3320 PR rtl-optimization/84169
3321 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST
3322 must be a REG or SUBREG of REG; if it is not one of these, don't
3325 2020-04-07 Richard Biener <rguenther@suse.de>
3328 * gimplify.c (gimplify_addr_expr): Also consider generated
3331 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3333 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.
3335 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3337 * config/arm/arm_mve.h: Cast some pointers to expected types.
3339 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3341 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
3342 same with '__arm_' prefix.
3344 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3346 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.
3348 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3350 * config/arm/arm.c (arm_mve_immediate_check): Removed.
3351 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
3352 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
3353 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
3354 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
3355 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
3356 mve_vqshruntq_m_n_s*): Fixed immediate constraints.
3358 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3360 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
3362 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3364 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
3365 * config/arm/mve/md: Fix v[id]wdup patterns.
3367 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3369 * config/arm/arm.c (output_move_neon): Deal with label + offset cases.
3370 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
3372 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3374 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
3375 and remove const_ptr enums.
3377 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3379 * config/arm/arm_mve.h (vsubq_n): Merge with...
3381 (vmulq_n): Merge with...
3383 (__ARM_mve_typeid): Simplify scalar and constant detection.
3385 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3388 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
3389 for inter-lane permutation for 64-byte modes.
3392 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
3393 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
3394 Assume it is a REG after that instead of testing it and doing FAIL
3395 otherwise. Formatting fix.
3397 2020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
3399 * config/rs6000/t-rtems: Delete mcpu=8540 multilib.
3401 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3404 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
3405 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes.
3407 2020-04-06 Jakub Jelinek <jakub@redhat.com>
3409 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
3410 + const0_rtx return the SP_DERIVED_VALUE_P.
3412 2020-04-06 Richard Sandiford <richard.sandiford@arm.com>
3414 PR rtl-optimization/92989
3415 * lra-lives.c (process_bb_lives): Do not treat eh_return data
3416 registers as being live at the beginning of the EH receiver.
3418 2020-04-05 Zachary Spytz <zspytz@gmail.com>
3420 * extend.texi: Add free to list of ISO C90 functions that
3421 are recognized by the compiler.
3423 2020-04-05 Nagaraju Mekala <nmekala@xilix.com>
3425 * config/microblaze/microblaze.c (microblaze_must_save_register): Check
3428 * config/microblaze/microblaze.md (trap): Update output pattern.
3430 2020-04-04 Hannes Domani <ssbssa@yahoo.de>
3431 Jakub Jelinek <jakub@redhat.com>
3434 * dwarf2out.c (gen_subprogram_die): Look through references, pointers,
3435 arrays, pointer-to-members, function types and qualifiers when
3436 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
3437 to emit type again on definition.
3439 2020-04-04 Jan Hubicka <hubicka@ucw.cz>
3442 * ipa-fnsummary.c (vrp_will_run_p): New function.
3443 (fre_will_run_p): New function.
3444 (evaluate_properties_for_edge): Use it.
3445 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
3446 !optimize_debug to optimize_debug.
3448 2020-04-04 Jakub Jelinek <jakub@redhat.com>
3450 PR rtl-optimization/94468
3451 * cselib.c (references_value_p): Formatting fix.
3452 (cselib_useless_value_p): New function.
3453 (discard_useless_locs, discard_useless_values,
3454 cselib_invalidate_regno_val, cselib_invalidate_mem,
3455 cselib_record_set): Use it instead of
3456 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx).
3459 * tree-iterator.h (expr_single): Declare.
3460 * tree-iterator.c (expr_single): New function.
3461 * tree.h (protected_set_expr_location_if_unset): Declare.
3462 * tree.c (protected_set_expr_location): Use expr_single.
3463 (protected_set_expr_location_if_unset): New function.
3465 2020-04-03 Jeff Law <law@redhat.com>
3467 PR rtl-optimization/92264
3468 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle
3469 reloading of auto-increment addressing modes.
3471 2020-04-03 H.J. Lu <hongjiu.lu@intel.com>
3474 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand
3477 2020-04-03 Jeff Law <law@redhat.com>
3479 PR rtl-optimization/92264
3480 * config/m32r/m32r.c (m32r_output_block_move): Properly account for
3481 post-increment addressing of source operands as well as residuals
3482 when computing any adjustments to the input pointer.
3484 2020-04-03 Jakub Jelinek <jakub@redhat.com>
3487 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
3488 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
3489 second half of first lane from first lane of second operand and
3490 first half of second lane from second lane of first operand.
3492 2020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
3494 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE.
3496 2020-04-03 Tamar Christina <tamar.christina@arm.com>
3499 * common/config/aarch64/aarch64-common.c
3500 (aarch64_get_extension_string_for_isa_flags): Handle default flags.
3502 2020-04-03 Richard Biener <rguenther@suse.de>
3505 * tree.c (array_ref_low_bound): Deal with released SSA names
3508 2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com>
3510 * config/gcn/gcn.c (print_operand): Handle unordered comparison
3512 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered
3513 comparison operators.
3515 2020-04-03 Kewen Lin <linkw@gcc.gnu.org>
3517 PR tree-optimization/94443
3518 * tree-vect-loop.c (vectorizable_live_operation): Use
3519 gsi_insert_seq_before to replace gsi_insert_before.
3521 2020-04-03 Martin Liska <mliska@suse.cz>
3524 * ipa-icf-gimple.c (func_checker::compare_gimple_call):
3525 Compare type attributes for gimple_call_fntypes.
3527 2020-04-02 Sandra Loosemore <sandra@codesourcery.com>
3529 * alias.c (get_alias_set): Fix comment typos.
3531 2020-04-02 Fritz Reese <foreese@gcc.gnu.org>
3534 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
3535 attribute checking used by TYPE.
3537 2020-04-02 Martin Jambor <mjambor@suse.cz>
3540 * ipa-sra.c (struct caller_issues): New fields candidate and
3541 call_from_outside_comdat.
3542 (check_for_caller_issues): Check for calls from outsied of
3543 candidate's same_comdat_group.
3544 (check_all_callers_for_issues): Set up issues.candidate, check result
3546 (mark_callers_calls_comdat_local): New function.
3547 (process_isra_node_results): Set calls_comdat_local of callers if
3550 2020-04-02 Richard Biener <rguenther@suse.de>
3553 * common.opt (ffinite-loops): Initialize to zero.
3554 * opts.c (default_options_table): Remove OPT_ffinite_loops
3556 * cfgloop.h (loop::finite_p): New member.
3557 * cfgloopmanip.c (copy_loop_info): Copy finite_p.
3558 * ipa-icf-gimple.c (func_checker::compare_loops): Compare
3560 * lto-streamer-in.c (input_cfg): Stream finite_p.
3561 * lto-streamer-out.c (output_cfg): Likewise.
3562 * tree-cfg.c (replace_loop_annotate): Initialize finite_p
3563 from flag_finite_loops at CFG build time.
3564 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops
3565 finite_p flag instead of flag_finite_loops.
3566 * doc/invoke.texi (ffinite-loops): Adjust documentation of
3569 2020-04-02 Richard Biener <rguenther@suse.de>
3572 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting
3573 DW_TAG_imported_unit.
3575 2020-04-02 Maciej W. Rozycki <macro@wdc.com>
3577 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
3578 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
3581 2020-04-02 Kewen Lin <linkw@gcc.gnu.org>
3583 PR tree-optimization/94401
3584 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
3585 access type when loading halves of vector to avoid peeling for gaps.
3587 2020-04-02 Jakub Jelinek <jakub@redhat.com>
3589 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
3590 between a string literal and MIPS_SYSVERSION_SPEC macro.
3592 2020-04-02 Martin Jambor <mjambor@suse.cz>
3594 * doc/invoke.texi (Optimize Options): Document sra-max-propagations.
3596 2020-04-02 Jakub Jelinek <jakub@redhat.com>
3598 PR rtl-optimization/92264
3599 * params.opt (-param=max-find-base-term-values=): Decrease default
3602 PR rtl-optimization/92264
3603 * rtl.h (struct rtx_def): Mention that call bit is used as
3604 SP_DERIVED_VALUE_P in cselib.c.
3605 * cselib.c (SP_DERIVED_VALUE_P): Define.
3606 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
3607 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
3608 val_rtx and sp based expression where offsets cancel each other.
3609 (preserve_constants_and_equivs): Formatting fix.
3610 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
3611 locs list for cfa_base_preserved_val if needed. Formatting fix.
3612 (autoinc_split): If the to be returned value is a REG, MEM or
3613 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
3614 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
3615 (rtx_equal_for_cselib_1): Call autoinc_split even if both
3616 expressions are PLUS in Pmode with CONST_INT second operands.
3617 Handle SP_DERIVED_VALUE_P cases.
3618 (cselib_hash_plus_const_int): New function.
3619 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
3620 second operand, as well as for PRE_DEC etc. that ought to be
3621 hashed the same way.
3622 (cselib_subst_to_values): Substitute PLUS with Pmode and
3623 CONST_INT operand if the first operand is a VALUE which has
3624 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
3625 SP_DERIVED_VALUE_P + adjusted offset.
3626 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
3627 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding
3628 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
3629 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
3630 on the sp value before calling cselib_add_permanent_equiv on the
3632 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
3633 in the insn without REG_INC note.
3634 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
3635 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes.
3638 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
3639 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
3641 2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3644 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
3645 (LDRGBWBXU_Z_QUALIFIERS): Likewise.
3646 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
3647 intrinsic defintion by adding a new builtin call to writeback into base
3649 (__arm_vldrdq_gather_base_wb_u64): Likewise.
3650 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
3651 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
3652 (__arm_vldrwq_gather_base_wb_s32): Likewise.
3653 (__arm_vldrwq_gather_base_wb_u32): Likewise.
3654 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
3655 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
3656 (__arm_vldrwq_gather_base_wb_f32): Likewise.
3657 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
3658 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
3659 builtin's qualifier.
3660 (vldrdq_gather_base_wb_z_u): Likewise.
3661 (vldrwq_gather_base_wb_u): Likewise.
3662 (vldrdq_gather_base_wb_u): Likewise.
3663 (vldrwq_gather_base_wb_z_s): Likewise.
3664 (vldrwq_gather_base_wb_z_f): Likewise.
3665 (vldrdq_gather_base_wb_z_s): Likewise.
3666 (vldrwq_gather_base_wb_s): Likewise.
3667 (vldrwq_gather_base_wb_f): Likewise.
3668 (vldrdq_gather_base_wb_s): Likewise.
3669 (vldrwq_gather_base_nowb_z_u): Define builtin.
3670 (vldrdq_gather_base_nowb_z_u): Likewise.
3671 (vldrwq_gather_base_nowb_u): Likewise.
3672 (vldrdq_gather_base_nowb_u): Likewise.
3673 (vldrwq_gather_base_nowb_z_s): Likewise.
3674 (vldrwq_gather_base_nowb_z_f): Likewise.
3675 (vldrdq_gather_base_nowb_z_s): Likewise.
3676 (vldrwq_gather_base_nowb_s): Likewise.
3677 (vldrwq_gather_base_nowb_f): Likewise.
3678 (vldrdq_gather_base_nowb_s): Likewise.
3679 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
3681 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
3682 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
3683 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
3684 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
3685 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
3686 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
3687 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
3688 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
3689 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
3690 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
3691 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
3693 2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
3695 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
3696 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
3697 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
3698 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
3699 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
3700 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
3701 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
3702 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
3703 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
3705 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
3706 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
3707 Remove constraints from expander.
3708 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
3709 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
3710 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
3711 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
3712 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
3713 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
3715 2020-04-01 Peter Bergner <bergner@linux.ibm.com>
3717 PR rtl-optimization/94123
3718 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for
3719 flag_split_wide_types_early.
3721 2020-04-01 Joerg Sonnenberger <joerg@bec.de>
3723 * doc/extend.texi (Common Function Attributes): Fix typo.
3725 2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>
3728 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
3731 2020-04-01 Zackery Spytz <zspytz@gmail.com>
3733 * doc/extend.texi: Fix a typo in the documentation of the
3734 copy function attribute.
3736 2020-04-01 Jakub Jelinek <jakub@redhat.com>
3739 * tree-object-size.c (pass_object_sizes::execute): Don't call
3740 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
3741 call replace_call_with_value.
3743 2020-04-01 Kewen Lin <linkw@gcc.gnu.org>
3745 PR tree-optimization/94043
3746 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
3747 phi for vec_lhs and use it for lane extraction.
3749 2020-03-31 Felix Yang <felix.yang@huawei.com>
3751 PR tree-optimization/94398
3752 * tree-vect-stmts.c (vectorizable_store): Instead of calling
3753 vect_supportable_dr_alignment, set alignment_support_scheme to
3754 dr_unaligned_supported for gather-scatter accesses.
3755 (vectorizable_load): Likewise.
3757 2020-03-31 Andrew Stubbs <ams@codesourcery.com>
3759 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
3761 (vnsi, VnSI, vndi, VnDI): New mode attributes.
3762 (mov<mode>): Use <VnDI> in place of V64DI.
3763 (mov<mode>_exec): Likewise.
3764 (mov<mode>_sgprbase): Likewise.
3765 (reload_out<mode>): Likewise.
3766 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
3767 (gather_load<mode>v64si): Rename to ...
3768 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
3769 and <VnDI> in place of V64DI.
3770 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
3771 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
3772 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
3773 (scatter_store<mode>v64si): Rename to ...
3774 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
3775 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
3776 (scatter<mode>_insn_1offset<exec_scatter>): Likewise.
3777 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
3778 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
3779 (ds_bpermute<mode>): Use <VnSI>.
3780 (addv64si3_vcc<exec_vcc>): Rename to ...
3781 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
3782 (addv64si3_vcc_dup<exec_vcc>): Rename to ...
3783 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
3784 (addcv64si3<exec_vcc>): Rename to ...
3785 (addc<mode>3<exec_vcc>): ... this, and use V_SI.
3786 (subv64si3_vcc<exec_vcc>): Rename to ...
3787 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
3788 (subcv64si3<exec_vcc>): Rename to ...
3789 (subc<mode>3<exec_vcc>): ... this, and use V_SI.
3790 (addv64di3): Rename to ...
3791 (add<mode>3): ... this, and use V_DI.
3792 (addv64di3_exec): Rename to ...
3793 (add<mode>3_exec): ... this, and use V_DI.
3794 (subv64di3): Rename to ...
3795 (sub<mode>3): ... this, and use V_DI.
3796 (subv64di3_exec): Rename to ...
3797 (sub<mode>3_exec): ... this, and use V_DI.
3798 (addv64di3_zext): Rename to ...
3799 (add<mode>3_zext): ... this, and use V_DI and <VnSI>.
3800 (addv64di3_zext_exec): Rename to ...
3801 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
3802 (addv64di3_zext_dup): Rename to ...
3803 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
3804 (addv64di3_zext_dup_exec): Rename to ...
3805 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
3806 (addv64di3_zext_dup2): Rename to ...
3807 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
3808 (addv64di3_zext_dup2_exec): Rename to ...
3809 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
3810 (addv64di3_sext_dup2): Rename to ...
3811 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
3812 (addv64di3_sext_dup2_exec): Rename to ...
3813 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
3814 (<su>mulv64si3_highpart<exec>): Rename to ...
3815 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
3816 (mulv64di3): Rename to ...
3817 (mul<mode>3): ... this, and use V_DI and <VnSI>.
3818 (mulv64di3_exec): Rename to ...
3819 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
3820 (mulv64di3_zext): Rename to ...
3821 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
3822 (mulv64di3_zext_exec): Rename to ...
3823 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
3824 (mulv64di3_zext_dup2): Rename to ...
3825 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
3826 (mulv64di3_zext_dup2_exec): Rename to ...
3827 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
3828 (<expander>v64di3): Rename to ...
3829 (<expander><mode>3): ... this, and use V_DI and <VnSI>.
3830 (<expander>v64di3_exec): Rename to ...
3831 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
3832 (<expander>v64si3<exec>): Rename to ...
3833 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
3834 (v<expander>v64si3<exec>): Rename to ...
3835 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
3836 (<expander>v64si3<exec>): Rename to ...
3837 (<expander><vnsi>3<exec>): ... this, and use V_SI.
3838 (subv64df3<exec>): Rename to ...
3839 (sub<mode>3<exec>): ... this, and use V_DF.
3840 (truncv64di<mode>2): Rename to ...
3841 (trunc<vndi><mode>2): ... this, and use <VnDI>.
3842 (truncv64di<mode>2_exec): Rename to ...
3843 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
3844 (<convop><mode>v64di2): Rename to ...
3845 (<convop><mode><vndi>2): ... this, and use <VnDI>.
3846 (<convop><mode>v64di2_exec): Rename to ...
3847 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
3848 (vec_cmp<u>v64qidi): Rename to ...
3849 (vec_cmp<u><mode>di): ... this, and use <VnSI>.
3850 (vec_cmp<u>v64qidi_exec): Rename to ...
3851 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
3852 (vcond_mask_<mode>di): Use <VnDI>.
3853 (maskload<mode>di): Likewise.
3854 (maskstore<mode>di): Likewise.
3855 (mask_gather_load<mode>v64si): Rename to ...
3856 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
3857 (mask_scatter_store<mode>v64si): Rename to ...
3858 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
3859 (*<reduc_op>_dpp_shr_v64di): Rename to ...
3860 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
3861 (*plus_carry_in_dpp_shr_v64si): Rename to ...
3862 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
3863 (*plus_carry_dpp_shr_v64di): Rename to ...
3864 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
3865 (vec_seriesv64si): Rename to ...
3866 (vec_series<mode>): ... this, and use V_SI.
3867 (vec_seriesv64di): Rename to ...
3868 (vec_series<mode>): ... this, and use V_DI.
3870 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
3872 * config/arc/arc.c (arc_print_operand): Use
3873 HOST_WIDE_INT_PRINT_DEC macro.
3875 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
3877 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
3879 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3881 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
3883 (__arm_vbicq): Likewise.
3885 2020-03-31 Vineet Gupta <vgupta@synopsys.com>
3887 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
3889 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3891 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
3892 common section of both MVE Integer and MVE Floating Point.
3894 (vaddlvq_p): Likewise.
3895 (vaddvaq): Likewise.
3896 (vaddvq_p): Likewise.
3897 (vcmpcsq): Likewise.
3898 (vmlsdavxq): Likewise.
3899 (vmlsdavq): Likewise.
3900 (vmladavxq): Likewise.
3901 (vmladavq): Likewise.
3903 (vminavq): Likewise.
3905 (vmaxavq): Likewise.
3906 (vmlaldavq): Likewise.
3907 (vcmphiq): Likewise.
3908 (vaddlvaq): Likewise.
3909 (vrmlaldavhq): Likewise.
3910 (vrmlaldavhxq): Likewise.
3911 (vrmlsldavhq): Likewise.
3912 (vrmlsldavhxq): Likewise.
3913 (vmlsldavxq): Likewise.
3914 (vmlsldavq): Likewise.
3916 (vrmlaldavhaq): Likewise.
3917 (vcmpgeq_m_n): Likewise.
3918 (vmlsdavxq_p): Likewise.
3919 (vmlsdavq_p): Likewise.
3920 (vmlsdavaxq): Likewise.
3921 (vmlsdavaq): Likewise.
3922 (vaddvaq_p): Likewise.
3923 (vcmpcsq_m_n): Likewise.
3924 (vcmpcsq_m): Likewise.
3925 (vmladavxq_p): Likewise.
3926 (vmladavq_p): Likewise.
3927 (vmladavaxq): Likewise.
3928 (vmladavaq): Likewise.
3929 (vminvq_p): Likewise.
3930 (vminavq_p): Likewise.
3931 (vmaxvq_p): Likewise.
3932 (vmaxavq_p): Likewise.
3933 (vcmphiq_m): Likewise.
3934 (vaddlvaq_p): Likewise.
3935 (vmlaldavaq): Likewise.
3936 (vmlaldavaxq): Likewise.
3937 (vmlaldavq_p): Likewise.
3938 (vmlaldavxq_p): Likewise.
3939 (vmlsldavaq): Likewise.
3940 (vmlsldavaxq): Likewise.
3941 (vmlsldavq_p): Likewise.
3942 (vmlsldavxq_p): Likewise.
3943 (vrmlaldavhaxq): Likewise.
3944 (vrmlaldavhq_p): Likewise.
3945 (vrmlaldavhxq_p): Likewise.
3946 (vrmlsldavhaq): Likewise.
3947 (vrmlsldavhaxq): Likewise.
3948 (vrmlsldavhq_p): Likewise.
3949 (vrmlsldavhxq_p): Likewise.
3950 (vabavq_p): Likewise.
3951 (vmladavaq_p): Likewise.
3952 (vstrbq_scatter_offset): Likewise.
3953 (vstrbq_p): Likewise.
3954 (vstrbq_scatter_offset_p): Likewise.
3955 (vstrdq_scatter_base_p): Likewise.
3956 (vstrdq_scatter_base): Likewise.
3957 (vstrdq_scatter_offset_p): Likewise.
3958 (vstrdq_scatter_offset): Likewise.
3959 (vstrdq_scatter_shifted_offset_p): Likewise.
3960 (vstrdq_scatter_shifted_offset): Likewise.
3961 (vmaxq_x): Likewise.
3962 (vminq_x): Likewise.
3963 (vmovlbq_x): Likewise.
3964 (vmovltq_x): Likewise.
3965 (vmulhq_x): Likewise.
3966 (vmullbq_int_x): Likewise.
3967 (vmullbq_poly_x): Likewise.
3968 (vmulltq_int_x): Likewise.
3969 (vmulltq_poly_x): Likewise.
3972 2020-03-31 Jakub Jelinek <jakub@redhat.com>
3975 * config/aarch64/constraints.md (Uph): New constraint.
3976 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
3977 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
3980 2020-03-31 Marc Glisse <marc.glisse@inria.fr>
3981 Jakub Jelinek <jakub@redhat.com>
3984 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
3985 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
3987 2020-03-31 Jakub Jelinek <jakub@redhat.com>
3989 PR tree-optimization/94403
3990 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
3991 ENUMERAL_TYPE lhs_type.
3993 PR rtl-optimization/94344
3994 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
3995 conversions, either on both operands of |^+ or just one. Handle
3996 also extra same precision conversion on RSHIFT_EXPR first operand
3997 provided RSHIFT_EXPR is performed in unsigned type.
3999 2020-03-30 David Malcolm <dmalcolm@redhat.com>
4001 * lra.c (finish_insn_code_data_once): Set the array elements
4002 to NULL after freeing them.
4004 2020-03-30 Andreas Schwab <schwab@suse.de>
4006 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
4009 2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com>
4011 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
4012 to skip defining builtins based on builtin_mask.
4014 2020-03-30 Jakub Jelinek <jakub@redhat.com>
4017 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
4018 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
4019 operand is a register. Don't enable masked variants for V*[QH]Imode.
4022 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
4023 <store_mask_constraint> instead of m in output operand constraint.
4024 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
4027 2020-03-30 Alan Modra <amodra@gmail.com>
4029 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
4030 (rs6000_indirect_call_template_1): Adjust to suit.
4031 * config/rs6000/rs6000.md (call_local): Merge call_local32,
4032 call_local64, and call_local_aix.
4033 (call_value_local): Simlarly.
4034 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
4035 and disable pattern when CALL_LONG.
4036 (call_indirect_aix, call_value_indirect_aix): Adjust rtl.
4037 (call_indirect_elfv2, call_indirect_pcrel): Likewise.
4038 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
4040 2020-03-29 H.J. Lu <hongjiu.lu@intel.com>
4043 * doc/invoke.texi: Update -falign-functions, -falign-loops and
4044 -falign-jumps documentation.
4046 2020-03-29 Martin Liska <mliska@suse.cz>
4049 * cgraphunit.c (process_function_and_variable_attributes): Remove
4050 double 'attribute' words.
4052 2020-03-29 John David Anglin <dave.anglin@bell.net>
4054 * config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
4057 2020-03-28 Jakub Jelinek <jakub@redhat.com>
4060 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const
4061 to true after setting size to integer_one_node.
4063 PR tree-optimization/94329
4064 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
4065 on the last stmt in a bb, make sure gsi_prev isn't done immediately
4068 2020-03-27 Alan Modra <amodra@gmail.com>
4071 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
4072 for PLT16_LO and PLT_PCREL.
4073 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
4074 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
4075 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
4077 2020-03-27 Martin Sebor <msebor@redhat.com>
4080 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes.
4082 2020-03-27 Andrew Stubbs <ams@codesourcery.com>
4084 * config/gcn/gcn-valu.md:
4085 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout.
4086 (VEC_1REG_MODE): Delete.
4087 (VEC_1REG_ALT): Delete.
4088 (VEC_ALL1REG_MODE): Rename to V_1REG throughout.
4089 (VEC_1REG_INT_MODE): Delete.
4090 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout.
4091 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout.
4092 (VEC_2REG_MODE): Rename to V_2REG throughout.
4093 (VEC_REG_MODE): Rename to V_noHI throughout.
4094 (VEC_ALLREG_MODE): Rename to V_ALL throughout.
4095 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout.
4096 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout.
4097 (VEC_INT_MODE): Delete.
4098 (VEC_FP_MODE): Rename to V_FP throughout and move to top.
4099 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top.
4100 (FP_MODE): Delete and replace with FP throughout.
4101 (FP_1REG_MODE): Delete and replace with FP_1REG throughout.
4102 (VCMP_MODE): Rename to V_noQI throughout and move to top.
4103 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top.
4104 * config/gcn/gcn.md (FP): New mode iterator.
4105 (FP_1REG): New mode iterator.
4107 2020-03-27 David Malcolm <dmalcolm@redhat.com>
4109 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this
4110 now emits two .dot files.
4111 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD.
4112 (graphviz_out::end_tr): Only close a TR, not a TD.
4113 (graphviz_out::begin_td): New.
4114 (graphviz_out::end_td): New.
4115 (graphviz_out::begin_trtd): New, replacing the old implementation
4116 of graphviz_out::begin_tr.
4117 (graphviz_out::end_tdtr): New, replacing the old implementation
4118 of graphviz_out::end_tr.
4119 * graphviz.h (graphviz_out::begin_td): New decl.
4120 (graphviz_out::end_td): New decl.
4121 (graphviz_out::begin_trtd): New decl.
4122 (graphviz_out::end_tdtr): New decl.
4124 2020-03-27 Richard Biener <rguenther@suse.de>
4127 * dwarf2out.c (should_emit_struct_debug): Return false for
4130 2020-03-27 Richard Biener <rguenther@suse.de>
4132 PR tree-optimization/94352
4133 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the
4135 (ssa_propagation_engine::ssa_propagate): ... here after
4136 initializing curr_order.
4138 2020-03-27 Kewen Lin <linkw@gcc.gnu.org>
4140 PR tree-optimization/90332
4141 * tree-vect-stmts.c (vector_vector_composition_type): New function.
4142 (get_group_load_store_type): Adjust to call
4143 vector_vector_composition_type, extend it to construct with scalar
4145 (vectorizable_load): Likewise.
4147 2020-03-27 Roman Zhuykov <zhroma@ispras.ru>
4149 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions.
4150 (create_ddg_dep_no_link): Likewise.
4151 (add_cross_iteration_register_deps): Move debug instruction check.
4152 Other minor refactoring.
4153 (add_intra_loop_mem_dep): Do not check for debug instructions.
4154 (add_inter_loop_mem_dep): Likewise.
4155 (build_intra_loop_deps): Likewise.
4156 (create_ddg): Do not include debug insns into the graph.
4157 * ddg.h (struct ddg): Remove num_debug field.
4158 * modulo-sched.c (doloop_register_get): Adjust condition.
4159 (res_MII): Remove DDG num_debug field usage.
4160 (sms_schedule_by_order): Use assertion against debug insns.
4161 (ps_has_conflicts): Drop debug insn check.
4163 2020-03-26 Jakub Jelinek <jakub@redhat.com>
4166 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST
4167 that contains exactly one non-DEBUG_BEGIN_STMT statement.
4170 * gimple.h (gimple_seq_first_nondebug_stmt): New function.
4171 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains
4172 a single non-debug stmt followed by one or more debug stmts.
4173 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt
4174 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt
4175 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and
4176 gimple_seq_last to check if outer_stmt gbind could be reused and
4177 if yes and it is surrounded by any debug stmts, move them into the
4180 PR rtl-optimization/92264
4181 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even
4182 for sp based values in !frame_pointer_needed
4183 && !ACCUMULATE_OUTGOING_ARGS functions.
4185 2020-03-26 Felix Yang <felix.yang@huawei.com>
4187 PR tree-optimization/94269
4188 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict
4190 operation to single basic block.
4192 2020-03-25 Jeff Law <law@redhat.com>
4194 PR rtl-optimization/90275
4195 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the
4198 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4201 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to
4202 mode rather than VOIDmode.
4204 2020-03-25 Martin Sebor <msebor@redhat.com>
4207 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings
4208 even for alloca calls resulting from system macro expansion.
4209 Include inlining context in all warnings.
4211 2020-03-25 Richard Sandiford <richard.sandiford@arm.com>
4214 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
4215 FPRs to change between SDmode and DDmode.
4217 2020-03-25 Martin Sebor <msebor@redhat.com>
4219 PR tree-optimization/94131
4220 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length
4222 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming
4223 types have constant sizes.
4225 2020-03-25 Martin Liska <mliska@suse.cz>
4228 * configure.ac: Report error only when --with-zstd
4230 * configure: Regenerate.
4232 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4235 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
4236 INSN_CODE (insn) to -1 when changing the pattern.
4238 2020-03-25 Martin Liska <mliska@suse.cz>
4242 * config/i386/i386-features.c (make_resolver_func): Drop
4243 public flag for resolver.
4244 * config/rs6000/rs6000.c (make_resolver_func): Add comdat
4245 group for resolver and drop public flag if possible.
4246 * multiple_target.c (create_dispatcher_calls): Drop unique_name
4247 and resolution as we want to enable LTO privatization of the default
4250 2020-03-25 Martin Liska <mliska@suse.cz>
4253 * configure.ac: Respect --without-zstd and report
4254 error when we can't find header file with --with-zstd.
4255 * configure: Regenerate.
4257 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4260 * varasm.c (output_constructor_array_range): If local->index
4261 RANGE_EXPR doesn't start at the current location in the constructor,
4262 skip needed number of bytes using assemble_zeros or assert we don't
4266 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong
4267 counter instead of DECL_UID.
4269 PR tree-optimization/94300
4270 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset
4271 is positive, make sure that off + size isn't larger than needed_len.
4273 2020-03-25 Richard Biener <rguenther@suse.de>
4274 Jakub Jelinek <jakub@redhat.com>
4277 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
4279 2020-03-24 Christophe Lyon <christophe.lyon@linaro.org>
4281 * doc/sourcebuild.texi (ARM-specific attributes): Add
4283 (Features for dg-add-options): Add arm_fp_dp.
4285 2020-03-24 John David Anglin <danglin@gcc.gnu.org>
4288 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.
4290 2020-03-24 Tobias Burnus <tobias@codesourcery.com>
4293 * omp-offload.c (omp_finish_file): Fix target-link handling if
4294 targetm_common.have_named_sections is false.
4296 2020-03-24 Jakub Jelinek <jakub@redhat.com>
4299 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
4303 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to
4304 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts.
4305 If not after and at *incr_pos is a debug stmt, set stmt location to
4306 location of next non-debug stmt after it if any.
4309 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
4310 GF_PLF_2, but don't add them to worklist. Don't add an assigment to
4311 worklist or set GF_PLF_2 just because it is used in a debug stmt in
4312 another bb. Formatting improvements.
4315 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and
4316 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC
4317 regardless of whether TREE_NO_WARNING is set on it or whether
4318 warn_unused_function is true or not.
4320 2020-03-23 Jeff Law <law@redhat.com>
4322 PR rtl-optimization/90275
4325 * simplify-rtx.c (comparison_code_valid_for_mode): New function.
4326 (simplify_logical_relational_operation): Use it.
4328 2020-03-23 Jakub Jelinek <jakub@redhat.com>
4331 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on
4332 ultimate rhs and if returned something different, reconstructing
4335 2020-03-23 Lewis Hyatt <lhyatt@gmail.com>
4337 * opts.c (print_filtered_help): Improve the help text for alias options.
4339 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4340 Andre Vieira <andre.simoesdiasvieira@arm.com>
4341 Mihail Ionescu <mihail.ionescu@arm.com>
4343 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro.
4344 (vshlcq_m_u8): Likewise.
4345 (vshlcq_m_s16): Likewise.
4346 (vshlcq_m_u16): Likewise.
4347 (vshlcq_m_s32): Likewise.
4348 (vshlcq_m_u32): Likewise.
4349 (__arm_vshlcq_m_s8): Define intrinsic.
4350 (__arm_vshlcq_m_u8): Likewise.
4351 (__arm_vshlcq_m_s16): Likewise.
4352 (__arm_vshlcq_m_u16): Likewise.
4353 (__arm_vshlcq_m_s32): Likewise.
4354 (__arm_vshlcq_m_u32): Likewise.
4355 (vshlcq_m): Define polymorphic variant.
4356 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE):
4357 Use builtin qualifier.
4358 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
4359 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern.
4360 (mve_vshlcq_m_carry_<supf><mode>): Likewise.
4361 (mve_vshlcq_m_<supf><mode>): Likewise.
4363 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4365 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier.
4366 (UQSHL_QUALIFIERS): Likewise.
4367 (ASRL_QUALIFIERS): Likewise.
4368 (SQSHL_QUALIFIERS): Likewise.
4369 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in
4371 (sqrshr): Define macro.
4372 (sqrshrl): Likewise.
4373 (sqrshrl_sat48): Likewise.
4379 (uqrshll): Likewise.
4380 (uqrshll_sat48): Likewise.
4387 (__arm_lsll): Define intrinsic.
4388 (__arm_asrl): Likewise.
4389 (__arm_uqrshll): Likewise.
4390 (__arm_uqrshll_sat48): Likewise.
4391 (__arm_sqrshrl): Likewise.
4392 (__arm_sqrshrl_sat48): Likewise.
4393 (__arm_uqshll): Likewise.
4394 (__arm_urshrl): Likewise.
4395 (__arm_srshrl): Likewise.
4396 (__arm_sqshll): Likewise.
4397 (__arm_uqrshl): Likewise.
4398 (__arm_sqrshr): Likewise.
4399 (__arm_uqshl): Likewise.
4400 (__arm_urshr): Likewise.
4401 (__arm_sqshl): Likewise.
4402 (__arm_srshr): Likewise.
4403 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin
4405 (UQSHL_QUALIFIERS): Likewise.
4406 (ASRL_QUALIFIERS): Likewise.
4407 (SQSHL_QUALIFIERS): Likewise.
4408 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern.
4409 (mve_sqrshrl_sat<supf>_di): Likewise.
4410 (mve_uqrshl_si): Likewise.
4411 (mve_sqrshr_si): Likewise.
4412 (mve_uqshll_di): Likewise.
4413 (mve_urshrl_di): Likewise.
4414 (mve_uqshl_si): Likewise.
4415 (mve_urshr_si): Likewise.
4416 (mve_sqshl_si): Likewise.
4417 (mve_srshr_si): Likewise.
4418 (mve_srshrl_di): Likewise.
4419 (mve_sqshll_di): Likewise.
4421 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4422 Andre Vieira <andre.simoesdiasvieira@arm.com>
4423 Mihail Ionescu <mihail.ionescu@arm.com>
4425 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro.
4426 (vsetq_lane_f32): Likewise.
4427 (vsetq_lane_s16): Likewise.
4428 (vsetq_lane_s32): Likewise.
4429 (vsetq_lane_s8): Likewise.
4430 (vsetq_lane_s64): Likewise.
4431 (vsetq_lane_u8): Likewise.
4432 (vsetq_lane_u16): Likewise.
4433 (vsetq_lane_u32): Likewise.
4434 (vsetq_lane_u64): Likewise.
4435 (vgetq_lane_f16): Likewise.
4436 (vgetq_lane_f32): Likewise.
4437 (vgetq_lane_s16): Likewise.
4438 (vgetq_lane_s32): Likewise.
4439 (vgetq_lane_s8): Likewise.
4440 (vgetq_lane_s64): Likewise.
4441 (vgetq_lane_u8): Likewise.
4442 (vgetq_lane_u16): Likewise.
4443 (vgetq_lane_u32): Likewise.
4444 (vgetq_lane_u64): Likewise.
4445 (__ARM_NUM_LANES): Likewise.
4446 (__ARM_LANEQ): Likewise.
4447 (__ARM_CHECK_LANEQ): Likewise.
4448 (__arm_vsetq_lane_s16): Define intrinsic.
4449 (__arm_vsetq_lane_s32): Likewise.
4450 (__arm_vsetq_lane_s8): Likewise.
4451 (__arm_vsetq_lane_s64): Likewise.
4452 (__arm_vsetq_lane_u8): Likewise.
4453 (__arm_vsetq_lane_u16): Likewise.
4454 (__arm_vsetq_lane_u32): Likewise.
4455 (__arm_vsetq_lane_u64): Likewise.
4456 (__arm_vgetq_lane_s16): Likewise.
4457 (__arm_vgetq_lane_s32): Likewise.
4458 (__arm_vgetq_lane_s8): Likewise.
4459 (__arm_vgetq_lane_s64): Likewise.
4460 (__arm_vgetq_lane_u8): Likewise.
4461 (__arm_vgetq_lane_u16): Likewise.
4462 (__arm_vgetq_lane_u32): Likewise.
4463 (__arm_vgetq_lane_u64): Likewise.
4464 (__arm_vsetq_lane_f16): Likewise.
4465 (__arm_vsetq_lane_f32): Likewise.
4466 (__arm_vgetq_lane_f16): Likewise.
4467 (__arm_vgetq_lane_f32): Likewise.
4468 (vgetq_lane): Define polymorphic variant.
4469 (vsetq_lane): Likewise.
4470 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL
4472 (mve_vec_extractv2didi): Likewise.
4473 (mve_vec_extract_sext_internal<mode>): Likewise.
4474 (mve_vec_extract_zext_internal<mode>): Likewise.
4475 (mve_vec_set<mode>_internal): Likewise.
4476 (mve_vec_setv2di_internal): Likewise.
4477 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md
4479 (vec_extract<mode><V_elem_l>): Rename to
4480 "neon_vec_extract<mode><V_elem_l>".
4481 (vec_extractv2didi): Rename to "neon_vec_extractv2didi".
4482 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL
4483 pattern common for MVE and NEON.
4484 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both
4487 2020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com>
4489 * config/arm/mve.md (earlyclobber_32): New mode attribute.
4490 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
4491 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.
4493 2020-03-23 Richard Biener <rguenther@suse.de>
4495 PR tree-optimization/94261
4496 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove
4497 IL operand swapping code.
4498 (vect_slp_rearrange_stmts): Do not arrange isomorphic
4499 nodes that would need operation code adjustments.
4501 2020-03-23 Tobias Burnus <tobias@codesourcery.com>
4503 * doc/install.texi (amdgcn-*-amdhsa): Renamed
4504 from amdgcn-unknown-amdhsa; change
4505 amdgcn-unknown-amdhsa to amdgcn-amdhsa.
4507 2020-03-23 Richard Biener <rguenther@suse.de>
4510 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP
4511 directly rather than also folding it via build_fold_addr_expr.
4513 2020-03-23 Richard Biener <rguenther@suse.de>
4515 PR tree-optimization/94266
4516 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate
4517 addresses of TARGET_MEM_REFs.
4519 2020-03-23 Martin Liska <mliska@suse.cz>
4522 * symtab.c (symtab_node::clone_references): Save speculative_id
4523 as ref may be overwritten by create_reference.
4524 (symtab_node::clone_referring): Likewise.
4525 (symtab_node::clone_reference): Likewise.
4527 2020-03-22 Iain Sandoe <iain@sandoe.co.uk>
4529 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
4530 references to Darwin.
4531 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
4532 unconditionally and comment on why.
4534 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
4536 * config/darwin.c (darwin_mergeable_constant_section): Collect
4537 section anchor checks into the caller.
4538 (machopic_select_section): Collect section anchor checks into
4539 the determination of 'effective zero-size' objects. When the
4540 size is unknown, assume it is non-zero, and thus return the
4541 'generic' section for the DECL.
4543 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
4546 * config/darwin.opt: Amend options descriptions.
4548 2020-03-21 Richard Sandiford <richard.sandiford@arm.com>
4550 PR rtl-optimization/94052
4551 * lra-constraints.c (simplify_operand_subreg): Reload the inner
4552 register of a paradoxical subreg if simplify_subreg_regno fails
4553 to give a valid hard register for the outer mode.
4555 2020-03-20 Martin Jambor <mjambor@suse.cz>
4557 PR tree-optimization/93435
4558 * params.opt (sra-max-propagations): New parameter.
4559 * tree-sra.c (propagation_budget): New variable.
4560 (budget_for_propagation_access): New function.
4561 (propagate_subaccesses_from_rhs): Use it.
4562 (propagate_subaccesses_from_lhs): Likewise.
4563 (propagate_all_subaccesses): Set up and destroy propagation_budget.
4565 2020-03-20 Carl Love <cel@us.ibm.com>
4568 * config/rs6000/rs6000.c (rs6000_option_override_internal):
4569 Add check for TARGET_FPRND for Power 7 or newer.
4571 2020-03-20 Jan Hubicka <hubicka@ucw.cz>
4574 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag.
4575 (cgraph_edge::redirect_callee): Move here; likewise.
4576 (cgraph_node::remove_callees): Update calls_comdat_local flag.
4577 (cgraph_node::verify_node): Verify that calls_comdat_local flag match
4579 (cgraph_node::check_calls_comdat_local_p): New member function.
4580 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare.
4581 (cgraph_edge::redirect_callee): Move offline.
4582 * ipa-fnsummary.c (compute_fn_summary): Do not compute
4583 calls_comdat_local flag here.
4584 * ipa-inline-transform.c (inline_call): Fix updating of
4585 calls_comdat_local flag.
4586 * ipa-split.c (split_function): Use true instead of 1 to set the flag.
4587 * symtab.c (symtab_node::add_to_same_comdat_group): Update
4588 calls_comdat_local flag.
4590 2020-03-20 Richard Biener <rguenther@suse.de>
4592 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree
4593 from the possibly modified root.
4595 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4596 Andre Vieira <andre.simoesdiasvieira@arm.com>
4597 Mihail Ionescu <mihail.ionescu@arm.com>
4599 * config/arm/arm_mve.h (vst1q_p_u8): Define macro.
4600 (vst1q_p_s8): Likewise.
4601 (vst2q_s8): Likewise.
4602 (vst2q_u8): Likewise.
4603 (vld1q_z_u8): Likewise.
4604 (vld1q_z_s8): Likewise.
4605 (vld2q_s8): Likewise.
4606 (vld2q_u8): Likewise.
4607 (vld4q_s8): Likewise.
4608 (vld4q_u8): Likewise.
4609 (vst1q_p_u16): Likewise.
4610 (vst1q_p_s16): Likewise.
4611 (vst2q_s16): Likewise.
4612 (vst2q_u16): Likewise.
4613 (vld1q_z_u16): Likewise.
4614 (vld1q_z_s16): Likewise.
4615 (vld2q_s16): Likewise.
4616 (vld2q_u16): Likewise.
4617 (vld4q_s16): Likewise.
4618 (vld4q_u16): Likewise.
4619 (vst1q_p_u32): Likewise.
4620 (vst1q_p_s32): Likewise.
4621 (vst2q_s32): Likewise.
4622 (vst2q_u32): Likewise.
4623 (vld1q_z_u32): Likewise.
4624 (vld1q_z_s32): Likewise.
4625 (vld2q_s32): Likewise.
4626 (vld2q_u32): Likewise.
4627 (vld4q_s32): Likewise.
4628 (vld4q_u32): Likewise.
4629 (vld4q_f16): Likewise.
4630 (vld2q_f16): Likewise.
4631 (vld1q_z_f16): Likewise.
4632 (vst2q_f16): Likewise.
4633 (vst1q_p_f16): Likewise.
4634 (vld4q_f32): Likewise.
4635 (vld2q_f32): Likewise.
4636 (vld1q_z_f32): Likewise.
4637 (vst2q_f32): Likewise.
4638 (vst1q_p_f32): Likewise.
4639 (__arm_vst1q_p_u8): Define intrinsic.
4640 (__arm_vst1q_p_s8): Likewise.
4641 (__arm_vst2q_s8): Likewise.
4642 (__arm_vst2q_u8): Likewise.
4643 (__arm_vld1q_z_u8): Likewise.
4644 (__arm_vld1q_z_s8): Likewise.
4645 (__arm_vld2q_s8): Likewise.
4646 (__arm_vld2q_u8): Likewise.
4647 (__arm_vld4q_s8): Likewise.
4648 (__arm_vld4q_u8): Likewise.
4649 (__arm_vst1q_p_u16): Likewise.
4650 (__arm_vst1q_p_s16): Likewise.
4651 (__arm_vst2q_s16): Likewise.
4652 (__arm_vst2q_u16): Likewise.
4653 (__arm_vld1q_z_u16): Likewise.
4654 (__arm_vld1q_z_s16): Likewise.
4655 (__arm_vld2q_s16): Likewise.
4656 (__arm_vld2q_u16): Likewise.
4657 (__arm_vld4q_s16): Likewise.
4658 (__arm_vld4q_u16): Likewise.
4659 (__arm_vst1q_p_u32): Likewise.
4660 (__arm_vst1q_p_s32): Likewise.
4661 (__arm_vst2q_s32): Likewise.
4662 (__arm_vst2q_u32): Likewise.
4663 (__arm_vld1q_z_u32): Likewise.
4664 (__arm_vld1q_z_s32): Likewise.
4665 (__arm_vld2q_s32): Likewise.
4666 (__arm_vld2q_u32): Likewise.
4667 (__arm_vld4q_s32): Likewise.
4668 (__arm_vld4q_u32): Likewise.
4669 (__arm_vld4q_f16): Likewise.
4670 (__arm_vld2q_f16): Likewise.
4671 (__arm_vld1q_z_f16): Likewise.
4672 (__arm_vst2q_f16): Likewise.
4673 (__arm_vst1q_p_f16): Likewise.
4674 (__arm_vld4q_f32): Likewise.
4675 (__arm_vld2q_f32): Likewise.
4676 (__arm_vld1q_z_f32): Likewise.
4677 (__arm_vst2q_f32): Likewise.
4678 (__arm_vst1q_p_f32): Likewise.
4679 (vld1q_z): Define polymorphic variant.
4682 (vst1q_p): Likewise.
4684 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier.
4686 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern.
4687 (mve_vld2q<mode>): Likewise.
4688 (mve_vld4q<mode>): Likewise.
4690 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4691 Andre Vieira <andre.simoesdiasvieira@arm.com>
4692 Mihail Ionescu <mihail.ionescu@arm.com>
4694 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define.
4695 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise.
4696 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and
4697 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array.
4698 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC
4699 and ARM_BUILTIN_SET_FPSCR_NZCVQC.
4700 * config/arm/arm_mve.h (vadciq_s32): Define macro.
4701 (vadciq_u32): Likewise.
4702 (vadciq_m_s32): Likewise.
4703 (vadciq_m_u32): Likewise.
4704 (vadcq_s32): Likewise.
4705 (vadcq_u32): Likewise.
4706 (vadcq_m_s32): Likewise.
4707 (vadcq_m_u32): Likewise.
4708 (vsbciq_s32): Likewise.
4709 (vsbciq_u32): Likewise.
4710 (vsbciq_m_s32): Likewise.
4711 (vsbciq_m_u32): Likewise.
4712 (vsbcq_s32): Likewise.
4713 (vsbcq_u32): Likewise.
4714 (vsbcq_m_s32): Likewise.
4715 (vsbcq_m_u32): Likewise.
4716 (__arm_vadciq_s32): Define intrinsic.
4717 (__arm_vadciq_u32): Likewise.
4718 (__arm_vadciq_m_s32): Likewise.
4719 (__arm_vadciq_m_u32): Likewise.
4720 (__arm_vadcq_s32): Likewise.
4721 (__arm_vadcq_u32): Likewise.
4722 (__arm_vadcq_m_s32): Likewise.
4723 (__arm_vadcq_m_u32): Likewise.
4724 (__arm_vsbciq_s32): Likewise.
4725 (__arm_vsbciq_u32): Likewise.
4726 (__arm_vsbciq_m_s32): Likewise.
4727 (__arm_vsbciq_m_u32): Likewise.
4728 (__arm_vsbcq_s32): Likewise.
4729 (__arm_vsbcq_u32): Likewise.
4730 (__arm_vsbcq_m_s32): Likewise.
4731 (__arm_vsbcq_m_u32): Likewise.
4732 (vadciq_m): Define polymorphic variant.
4734 (vadcq_m): Likewise.
4736 (vsbciq_m): Likewise.
4738 (vsbcq_m): Likewise.
4740 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin
4742 (BINOP_UNONE_UNONE_UNONE): Likewise.
4743 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
4744 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
4745 * config/arm/mve.md (VADCIQ): Define iterator.
4746 (VADCIQ_M): Likewise.
4748 (VSBCQ_M): Likewise.
4750 (VSBCIQ_M): Likewise.
4752 (VADCQ_M): Likewise.
4753 (mve_vadciq_m_<supf>v4si): Define RTL pattern.
4754 (mve_vadciq_<supf>v4si): Likewise.
4755 (mve_vadcq_m_<supf>v4si): Likewise.
4756 (mve_vadcq_<supf>v4si): Likewise.
4757 (mve_vsbciq_m_<supf>v4si): Likewise.
4758 (mve_vsbciq_<supf>v4si): Likewise.
4759 (mve_vsbcq_m_<supf>v4si): Likewise.
4760 (mve_vsbcq_<supf>v4si): Likewise.
4761 (get_fpscr_nzcvqc): Define isns.
4762 (set_fpscr_nzcvqc): Define isns.
4763 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define.
4764 (UNSPEC_SET_FPSCR_NZCVQC): Define.
4766 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4768 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
4769 (vddupq_x_n_u16): Likewise.
4770 (vddupq_x_n_u32): Likewise.
4771 (vddupq_x_wb_u8): Likewise.
4772 (vddupq_x_wb_u16): Likewise.
4773 (vddupq_x_wb_u32): Likewise.
4774 (vdwdupq_x_n_u8): Likewise.
4775 (vdwdupq_x_n_u16): Likewise.
4776 (vdwdupq_x_n_u32): Likewise.
4777 (vdwdupq_x_wb_u8): Likewise.
4778 (vdwdupq_x_wb_u16): Likewise.
4779 (vdwdupq_x_wb_u32): Likewise.
4780 (vidupq_x_n_u8): Likewise.
4781 (vidupq_x_n_u16): Likewise.
4782 (vidupq_x_n_u32): Likewise.
4783 (vidupq_x_wb_u8): Likewise.
4784 (vidupq_x_wb_u16): Likewise.
4785 (vidupq_x_wb_u32): Likewise.
4786 (viwdupq_x_n_u8): Likewise.
4787 (viwdupq_x_n_u16): Likewise.
4788 (viwdupq_x_n_u32): Likewise.
4789 (viwdupq_x_wb_u8): Likewise.
4790 (viwdupq_x_wb_u16): Likewise.
4791 (viwdupq_x_wb_u32): Likewise.
4792 (vdupq_x_n_s8): Likewise.
4793 (vdupq_x_n_s16): Likewise.
4794 (vdupq_x_n_s32): Likewise.
4795 (vdupq_x_n_u8): Likewise.
4796 (vdupq_x_n_u16): Likewise.
4797 (vdupq_x_n_u32): Likewise.
4798 (vminq_x_s8): Likewise.
4799 (vminq_x_s16): Likewise.
4800 (vminq_x_s32): Likewise.
4801 (vminq_x_u8): Likewise.
4802 (vminq_x_u16): Likewise.
4803 (vminq_x_u32): Likewise.
4804 (vmaxq_x_s8): Likewise.
4805 (vmaxq_x_s16): Likewise.
4806 (vmaxq_x_s32): Likewise.
4807 (vmaxq_x_u8): Likewise.
4808 (vmaxq_x_u16): Likewise.
4809 (vmaxq_x_u32): Likewise.
4810 (vabdq_x_s8): Likewise.
4811 (vabdq_x_s16): Likewise.
4812 (vabdq_x_s32): Likewise.
4813 (vabdq_x_u8): Likewise.
4814 (vabdq_x_u16): Likewise.
4815 (vabdq_x_u32): Likewise.
4816 (vabsq_x_s8): Likewise.
4817 (vabsq_x_s16): Likewise.
4818 (vabsq_x_s32): Likewise.
4819 (vaddq_x_s8): Likewise.
4820 (vaddq_x_s16): Likewise.
4821 (vaddq_x_s32): Likewise.
4822 (vaddq_x_n_s8): Likewise.
4823 (vaddq_x_n_s16): Likewise.
4824 (vaddq_x_n_s32): Likewise.
4825 (vaddq_x_u8): Likewise.
4826 (vaddq_x_u16): Likewise.
4827 (vaddq_x_u32): Likewise.
4828 (vaddq_x_n_u8): Likewise.
4829 (vaddq_x_n_u16): Likewise.
4830 (vaddq_x_n_u32): Likewise.
4831 (vclsq_x_s8): Likewise.
4832 (vclsq_x_s16): Likewise.
4833 (vclsq_x_s32): Likewise.
4834 (vclzq_x_s8): Likewise.
4835 (vclzq_x_s16): Likewise.
4836 (vclzq_x_s32): Likewise.
4837 (vclzq_x_u8): Likewise.
4838 (vclzq_x_u16): Likewise.
4839 (vclzq_x_u32): Likewise.
4840 (vnegq_x_s8): Likewise.
4841 (vnegq_x_s16): Likewise.
4842 (vnegq_x_s32): Likewise.
4843 (vmulhq_x_s8): Likewise.
4844 (vmulhq_x_s16): Likewise.
4845 (vmulhq_x_s32): Likewise.
4846 (vmulhq_x_u8): Likewise.
4847 (vmulhq_x_u16): Likewise.
4848 (vmulhq_x_u32): Likewise.
4849 (vmullbq_poly_x_p8): Likewise.
4850 (vmullbq_poly_x_p16): Likewise.
4851 (vmullbq_int_x_s8): Likewise.
4852 (vmullbq_int_x_s16): Likewise.
4853 (vmullbq_int_x_s32): Likewise.
4854 (vmullbq_int_x_u8): Likewise.
4855 (vmullbq_int_x_u16): Likewise.
4856 (vmullbq_int_x_u32): Likewise.
4857 (vmulltq_poly_x_p8): Likewise.
4858 (vmulltq_poly_x_p16): Likewise.
4859 (vmulltq_int_x_s8): Likewise.
4860 (vmulltq_int_x_s16): Likewise.
4861 (vmulltq_int_x_s32): Likewise.
4862 (vmulltq_int_x_u8): Likewise.
4863 (vmulltq_int_x_u16): Likewise.
4864 (vmulltq_int_x_u32): Likewise.
4865 (vmulq_x_s8): Likewise.
4866 (vmulq_x_s16): Likewise.
4867 (vmulq_x_s32): Likewise.
4868 (vmulq_x_n_s8): Likewise.
4869 (vmulq_x_n_s16): Likewise.
4870 (vmulq_x_n_s32): Likewise.
4871 (vmulq_x_u8): Likewise.
4872 (vmulq_x_u16): Likewise.
4873 (vmulq_x_u32): Likewise.
4874 (vmulq_x_n_u8): Likewise.
4875 (vmulq_x_n_u16): Likewise.
4876 (vmulq_x_n_u32): Likewise.
4877 (vsubq_x_s8): Likewise.
4878 (vsubq_x_s16): Likewise.
4879 (vsubq_x_s32): Likewise.
4880 (vsubq_x_n_s8): Likewise.
4881 (vsubq_x_n_s16): Likewise.
4882 (vsubq_x_n_s32): Likewise.
4883 (vsubq_x_u8): Likewise.
4884 (vsubq_x_u16): Likewise.
4885 (vsubq_x_u32): Likewise.
4886 (vsubq_x_n_u8): Likewise.
4887 (vsubq_x_n_u16): Likewise.
4888 (vsubq_x_n_u32): Likewise.
4889 (vcaddq_rot90_x_s8): Likewise.
4890 (vcaddq_rot90_x_s16): Likewise.
4891 (vcaddq_rot90_x_s32): Likewise.
4892 (vcaddq_rot90_x_u8): Likewise.
4893 (vcaddq_rot90_x_u16): Likewise.
4894 (vcaddq_rot90_x_u32): Likewise.
4895 (vcaddq_rot270_x_s8): Likewise.
4896 (vcaddq_rot270_x_s16): Likewise.
4897 (vcaddq_rot270_x_s32): Likewise.
4898 (vcaddq_rot270_x_u8): Likewise.
4899 (vcaddq_rot270_x_u16): Likewise.
4900 (vcaddq_rot270_x_u32): Likewise.
4901 (vhaddq_x_n_s8): Likewise.
4902 (vhaddq_x_n_s16): Likewise.
4903 (vhaddq_x_n_s32): Likewise.
4904 (vhaddq_x_n_u8): Likewise.
4905 (vhaddq_x_n_u16): Likewise.
4906 (vhaddq_x_n_u32): Likewise.
4907 (vhaddq_x_s8): Likewise.
4908 (vhaddq_x_s16): Likewise.
4909 (vhaddq_x_s32): Likewise.
4910 (vhaddq_x_u8): Likewise.
4911 (vhaddq_x_u16): Likewise.
4912 (vhaddq_x_u32): Likewise.
4913 (vhcaddq_rot90_x_s8): Likewise.
4914 (vhcaddq_rot90_x_s16): Likewise.
4915 (vhcaddq_rot90_x_s32): Likewise.
4916 (vhcaddq_rot270_x_s8): Likewise.
4917 (vhcaddq_rot270_x_s16): Likewise.
4918 (vhcaddq_rot270_x_s32): Likewise.
4919 (vhsubq_x_n_s8): Likewise.
4920 (vhsubq_x_n_s16): Likewise.
4921 (vhsubq_x_n_s32): Likewise.
4922 (vhsubq_x_n_u8): Likewise.
4923 (vhsubq_x_n_u16): Likewise.
4924 (vhsubq_x_n_u32): Likewise.
4925 (vhsubq_x_s8): Likewise.
4926 (vhsubq_x_s16): Likewise.
4927 (vhsubq_x_s32): Likewise.
4928 (vhsubq_x_u8): Likewise.
4929 (vhsubq_x_u16): Likewise.
4930 (vhsubq_x_u32): Likewise.
4931 (vrhaddq_x_s8): Likewise.
4932 (vrhaddq_x_s16): Likewise.
4933 (vrhaddq_x_s32): Likewise.
4934 (vrhaddq_x_u8): Likewise.
4935 (vrhaddq_x_u16): Likewise.
4936 (vrhaddq_x_u32): Likewise.
4937 (vrmulhq_x_s8): Likewise.
4938 (vrmulhq_x_s16): Likewise.
4939 (vrmulhq_x_s32): Likewise.
4940 (vrmulhq_x_u8): Likewise.
4941 (vrmulhq_x_u16): Likewise.
4942 (vrmulhq_x_u32): Likewise.
4943 (vandq_x_s8): Likewise.
4944 (vandq_x_s16): Likewise.
4945 (vandq_x_s32): Likewise.
4946 (vandq_x_u8): Likewise.
4947 (vandq_x_u16): Likewise.
4948 (vandq_x_u32): Likewise.
4949 (vbicq_x_s8): Likewise.
4950 (vbicq_x_s16): Likewise.
4951 (vbicq_x_s32): Likewise.
4952 (vbicq_x_u8): Likewise.
4953 (vbicq_x_u16): Likewise.
4954 (vbicq_x_u32): Likewise.
4955 (vbrsrq_x_n_s8): Likewise.
4956 (vbrsrq_x_n_s16): Likewise.
4957 (vbrsrq_x_n_s32): Likewise.
4958 (vbrsrq_x_n_u8): Likewise.
4959 (vbrsrq_x_n_u16): Likewise.
4960 (vbrsrq_x_n_u32): Likewise.
4961 (veorq_x_s8): Likewise.
4962 (veorq_x_s16): Likewise.
4963 (veorq_x_s32): Likewise.
4964 (veorq_x_u8): Likewise.
4965 (veorq_x_u16): Likewise.
4966 (veorq_x_u32): Likewise.
4967 (vmovlbq_x_s8): Likewise.
4968 (vmovlbq_x_s16): Likewise.
4969 (vmovlbq_x_u8): Likewise.
4970 (vmovlbq_x_u16): Likewise.
4971 (vmovltq_x_s8): Likewise.
4972 (vmovltq_x_s16): Likewise.
4973 (vmovltq_x_u8): Likewise.
4974 (vmovltq_x_u16): Likewise.
4975 (vmvnq_x_s8): Likewise.
4976 (vmvnq_x_s16): Likewise.
4977 (vmvnq_x_s32): Likewise.
4978 (vmvnq_x_u8): Likewise.
4979 (vmvnq_x_u16): Likewise.
4980 (vmvnq_x_u32): Likewise.
4981 (vmvnq_x_n_s16): Likewise.
4982 (vmvnq_x_n_s32): Likewise.
4983 (vmvnq_x_n_u16): Likewise.
4984 (vmvnq_x_n_u32): Likewise.
4985 (vornq_x_s8): Likewise.
4986 (vornq_x_s16): Likewise.
4987 (vornq_x_s32): Likewise.
4988 (vornq_x_u8): Likewise.
4989 (vornq_x_u16): Likewise.
4990 (vornq_x_u32): Likewise.
4991 (vorrq_x_s8): Likewise.
4992 (vorrq_x_s16): Likewise.
4993 (vorrq_x_s32): Likewise.
4994 (vorrq_x_u8): Likewise.
4995 (vorrq_x_u16): Likewise.
4996 (vorrq_x_u32): Likewise.
4997 (vrev16q_x_s8): Likewise.
4998 (vrev16q_x_u8): Likewise.
4999 (vrev32q_x_s8): Likewise.
5000 (vrev32q_x_s16): Likewise.
5001 (vrev32q_x_u8): Likewise.
5002 (vrev32q_x_u16): Likewise.
5003 (vrev64q_x_s8): Likewise.
5004 (vrev64q_x_s16): Likewise.
5005 (vrev64q_x_s32): Likewise.
5006 (vrev64q_x_u8): Likewise.
5007 (vrev64q_x_u16): Likewise.
5008 (vrev64q_x_u32): Likewise.
5009 (vrshlq_x_s8): Likewise.
5010 (vrshlq_x_s16): Likewise.
5011 (vrshlq_x_s32): Likewise.
5012 (vrshlq_x_u8): Likewise.
5013 (vrshlq_x_u16): Likewise.
5014 (vrshlq_x_u32): Likewise.
5015 (vshllbq_x_n_s8): Likewise.
5016 (vshllbq_x_n_s16): Likewise.
5017 (vshllbq_x_n_u8): Likewise.
5018 (vshllbq_x_n_u16): Likewise.
5019 (vshlltq_x_n_s8): Likewise.
5020 (vshlltq_x_n_s16): Likewise.
5021 (vshlltq_x_n_u8): Likewise.
5022 (vshlltq_x_n_u16): Likewise.
5023 (vshlq_x_s8): Likewise.
5024 (vshlq_x_s16): Likewise.
5025 (vshlq_x_s32): Likewise.
5026 (vshlq_x_u8): Likewise.
5027 (vshlq_x_u16): Likewise.
5028 (vshlq_x_u32): Likewise.
5029 (vshlq_x_n_s8): Likewise.
5030 (vshlq_x_n_s16): Likewise.
5031 (vshlq_x_n_s32): Likewise.
5032 (vshlq_x_n_u8): Likewise.
5033 (vshlq_x_n_u16): Likewise.
5034 (vshlq_x_n_u32): Likewise.
5035 (vrshrq_x_n_s8): Likewise.
5036 (vrshrq_x_n_s16): Likewise.
5037 (vrshrq_x_n_s32): Likewise.
5038 (vrshrq_x_n_u8): Likewise.
5039 (vrshrq_x_n_u16): Likewise.
5040 (vrshrq_x_n_u32): Likewise.
5041 (vshrq_x_n_s8): Likewise.
5042 (vshrq_x_n_s16): Likewise.
5043 (vshrq_x_n_s32): Likewise.
5044 (vshrq_x_n_u8): Likewise.
5045 (vshrq_x_n_u16): Likewise.
5046 (vshrq_x_n_u32): Likewise.
5047 (vdupq_x_n_f16): Likewise.
5048 (vdupq_x_n_f32): Likewise.
5049 (vminnmq_x_f16): Likewise.
5050 (vminnmq_x_f32): Likewise.
5051 (vmaxnmq_x_f16): Likewise.
5052 (vmaxnmq_x_f32): Likewise.
5053 (vabdq_x_f16): Likewise.
5054 (vabdq_x_f32): Likewise.
5055 (vabsq_x_f16): Likewise.
5056 (vabsq_x_f32): Likewise.
5057 (vaddq_x_f16): Likewise.
5058 (vaddq_x_f32): Likewise.
5059 (vaddq_x_n_f16): Likewise.
5060 (vaddq_x_n_f32): Likewise.
5061 (vnegq_x_f16): Likewise.
5062 (vnegq_x_f32): Likewise.
5063 (vmulq_x_f16): Likewise.
5064 (vmulq_x_f32): Likewise.
5065 (vmulq_x_n_f16): Likewise.
5066 (vmulq_x_n_f32): Likewise.
5067 (vsubq_x_f16): Likewise.
5068 (vsubq_x_f32): Likewise.
5069 (vsubq_x_n_f16): Likewise.
5070 (vsubq_x_n_f32): Likewise.
5071 (vcaddq_rot90_x_f16): Likewise.
5072 (vcaddq_rot90_x_f32): Likewise.
5073 (vcaddq_rot270_x_f16): Likewise.
5074 (vcaddq_rot270_x_f32): Likewise.
5075 (vcmulq_x_f16): Likewise.
5076 (vcmulq_x_f32): Likewise.
5077 (vcmulq_rot90_x_f16): Likewise.
5078 (vcmulq_rot90_x_f32): Likewise.
5079 (vcmulq_rot180_x_f16): Likewise.
5080 (vcmulq_rot180_x_f32): Likewise.
5081 (vcmulq_rot270_x_f16): Likewise.
5082 (vcmulq_rot270_x_f32): Likewise.
5083 (vcvtaq_x_s16_f16): Likewise.
5084 (vcvtaq_x_s32_f32): Likewise.
5085 (vcvtaq_x_u16_f16): Likewise.
5086 (vcvtaq_x_u32_f32): Likewise.
5087 (vcvtnq_x_s16_f16): Likewise.
5088 (vcvtnq_x_s32_f32): Likewise.
5089 (vcvtnq_x_u16_f16): Likewise.
5090 (vcvtnq_x_u32_f32): Likewise.
5091 (vcvtpq_x_s16_f16): Likewise.
5092 (vcvtpq_x_s32_f32): Likewise.
5093 (vcvtpq_x_u16_f16): Likewise.
5094 (vcvtpq_x_u32_f32): Likewise.
5095 (vcvtmq_x_s16_f16): Likewise.
5096 (vcvtmq_x_s32_f32): Likewise.
5097 (vcvtmq_x_u16_f16): Likewise.
5098 (vcvtmq_x_u32_f32): Likewise.
5099 (vcvtbq_x_f32_f16): Likewise.
5100 (vcvttq_x_f32_f16): Likewise.
5101 (vcvtq_x_f16_u16): Likewise.
5102 (vcvtq_x_f16_s16): Likewise.
5103 (vcvtq_x_f32_s32): Likewise.
5104 (vcvtq_x_f32_u32): Likewise.
5105 (vcvtq_x_n_f16_s16): Likewise.
5106 (vcvtq_x_n_f16_u16): Likewise.
5107 (vcvtq_x_n_f32_s32): Likewise.
5108 (vcvtq_x_n_f32_u32): Likewise.
5109 (vcvtq_x_s16_f16): Likewise.
5110 (vcvtq_x_s32_f32): Likewise.
5111 (vcvtq_x_u16_f16): Likewise.
5112 (vcvtq_x_u32_f32): Likewise.
5113 (vcvtq_x_n_s16_f16): Likewise.
5114 (vcvtq_x_n_s32_f32): Likewise.
5115 (vcvtq_x_n_u16_f16): Likewise.
5116 (vcvtq_x_n_u32_f32): Likewise.
5117 (vrndq_x_f16): Likewise.
5118 (vrndq_x_f32): Likewise.
5119 (vrndnq_x_f16): Likewise.
5120 (vrndnq_x_f32): Likewise.
5121 (vrndmq_x_f16): Likewise.
5122 (vrndmq_x_f32): Likewise.
5123 (vrndpq_x_f16): Likewise.
5124 (vrndpq_x_f32): Likewise.
5125 (vrndaq_x_f16): Likewise.
5126 (vrndaq_x_f32): Likewise.
5127 (vrndxq_x_f16): Likewise.
5128 (vrndxq_x_f32): Likewise.
5129 (vandq_x_f16): Likewise.
5130 (vandq_x_f32): Likewise.
5131 (vbicq_x_f16): Likewise.
5132 (vbicq_x_f32): Likewise.
5133 (vbrsrq_x_n_f16): Likewise.
5134 (vbrsrq_x_n_f32): Likewise.
5135 (veorq_x_f16): Likewise.
5136 (veorq_x_f32): Likewise.
5137 (vornq_x_f16): Likewise.
5138 (vornq_x_f32): Likewise.
5139 (vorrq_x_f16): Likewise.
5140 (vorrq_x_f32): Likewise.
5141 (vrev32q_x_f16): Likewise.
5142 (vrev64q_x_f16): Likewise.
5143 (vrev64q_x_f32): Likewise.
5144 (__arm_vddupq_x_n_u8): Define intrinsic.
5145 (__arm_vddupq_x_n_u16): Likewise.
5146 (__arm_vddupq_x_n_u32): Likewise.
5147 (__arm_vddupq_x_wb_u8): Likewise.
5148 (__arm_vddupq_x_wb_u16): Likewise.
5149 (__arm_vddupq_x_wb_u32): Likewise.
5150 (__arm_vdwdupq_x_n_u8): Likewise.
5151 (__arm_vdwdupq_x_n_u16): Likewise.
5152 (__arm_vdwdupq_x_n_u32): Likewise.
5153 (__arm_vdwdupq_x_wb_u8): Likewise.
5154 (__arm_vdwdupq_x_wb_u16): Likewise.
5155 (__arm_vdwdupq_x_wb_u32): Likewise.
5156 (__arm_vidupq_x_n_u8): Likewise.
5157 (__arm_vidupq_x_n_u16): Likewise.
5158 (__arm_vidupq_x_n_u32): Likewise.
5159 (__arm_vidupq_x_wb_u8): Likewise.
5160 (__arm_vidupq_x_wb_u16): Likewise.
5161 (__arm_vidupq_x_wb_u32): Likewise.
5162 (__arm_viwdupq_x_n_u8): Likewise.
5163 (__arm_viwdupq_x_n_u16): Likewise.
5164 (__arm_viwdupq_x_n_u32): Likewise.
5165 (__arm_viwdupq_x_wb_u8): Likewise.
5166 (__arm_viwdupq_x_wb_u16): Likewise.
5167 (__arm_viwdupq_x_wb_u32): Likewise.
5168 (__arm_vdupq_x_n_s8): Likewise.
5169 (__arm_vdupq_x_n_s16): Likewise.
5170 (__arm_vdupq_x_n_s32): Likewise.
5171 (__arm_vdupq_x_n_u8): Likewise.
5172 (__arm_vdupq_x_n_u16): Likewise.
5173 (__arm_vdupq_x_n_u32): Likewise.
5174 (__arm_vminq_x_s8): Likewise.
5175 (__arm_vminq_x_s16): Likewise.
5176 (__arm_vminq_x_s32): Likewise.
5177 (__arm_vminq_x_u8): Likewise.
5178 (__arm_vminq_x_u16): Likewise.
5179 (__arm_vminq_x_u32): Likewise.
5180 (__arm_vmaxq_x_s8): Likewise.
5181 (__arm_vmaxq_x_s16): Likewise.
5182 (__arm_vmaxq_x_s32): Likewise.
5183 (__arm_vmaxq_x_u8): Likewise.
5184 (__arm_vmaxq_x_u16): Likewise.
5185 (__arm_vmaxq_x_u32): Likewise.
5186 (__arm_vabdq_x_s8): Likewise.
5187 (__arm_vabdq_x_s16): Likewise.
5188 (__arm_vabdq_x_s32): Likewise.
5189 (__arm_vabdq_x_u8): Likewise.
5190 (__arm_vabdq_x_u16): Likewise.
5191 (__arm_vabdq_x_u32): Likewise.
5192 (__arm_vabsq_x_s8): Likewise.
5193 (__arm_vabsq_x_s16): Likewise.
5194 (__arm_vabsq_x_s32): Likewise.
5195 (__arm_vaddq_x_s8): Likewise.
5196 (__arm_vaddq_x_s16): Likewise.
5197 (__arm_vaddq_x_s32): Likewise.
5198 (__arm_vaddq_x_n_s8): Likewise.
5199 (__arm_vaddq_x_n_s16): Likewise.
5200 (__arm_vaddq_x_n_s32): Likewise.
5201 (__arm_vaddq_x_u8): Likewise.
5202 (__arm_vaddq_x_u16): Likewise.
5203 (__arm_vaddq_x_u32): Likewise.
5204 (__arm_vaddq_x_n_u8): Likewise.
5205 (__arm_vaddq_x_n_u16): Likewise.
5206 (__arm_vaddq_x_n_u32): Likewise.
5207 (__arm_vclsq_x_s8): Likewise.
5208 (__arm_vclsq_x_s16): Likewise.
5209 (__arm_vclsq_x_s32): Likewise.
5210 (__arm_vclzq_x_s8): Likewise.
5211 (__arm_vclzq_x_s16): Likewise.
5212 (__arm_vclzq_x_s32): Likewise.
5213 (__arm_vclzq_x_u8): Likewise.
5214 (__arm_vclzq_x_u16): Likewise.
5215 (__arm_vclzq_x_u32): Likewise.
5216 (__arm_vnegq_x_s8): Likewise.
5217 (__arm_vnegq_x_s16): Likewise.
5218 (__arm_vnegq_x_s32): Likewise.
5219 (__arm_vmulhq_x_s8): Likewise.
5220 (__arm_vmulhq_x_s16): Likewise.
5221 (__arm_vmulhq_x_s32): Likewise.
5222 (__arm_vmulhq_x_u8): Likewise.
5223 (__arm_vmulhq_x_u16): Likewise.
5224 (__arm_vmulhq_x_u32): Likewise.
5225 (__arm_vmullbq_poly_x_p8): Likewise.
5226 (__arm_vmullbq_poly_x_p16): Likewise.
5227 (__arm_vmullbq_int_x_s8): Likewise.
5228 (__arm_vmullbq_int_x_s16): Likewise.
5229 (__arm_vmullbq_int_x_s32): Likewise.
5230 (__arm_vmullbq_int_x_u8): Likewise.
5231 (__arm_vmullbq_int_x_u16): Likewise.
5232 (__arm_vmullbq_int_x_u32): Likewise.
5233 (__arm_vmulltq_poly_x_p8): Likewise.
5234 (__arm_vmulltq_poly_x_p16): Likewise.
5235 (__arm_vmulltq_int_x_s8): Likewise.
5236 (__arm_vmulltq_int_x_s16): Likewise.
5237 (__arm_vmulltq_int_x_s32): Likewise.
5238 (__arm_vmulltq_int_x_u8): Likewise.
5239 (__arm_vmulltq_int_x_u16): Likewise.
5240 (__arm_vmulltq_int_x_u32): Likewise.
5241 (__arm_vmulq_x_s8): Likewise.
5242 (__arm_vmulq_x_s16): Likewise.
5243 (__arm_vmulq_x_s32): Likewise.
5244 (__arm_vmulq_x_n_s8): Likewise.
5245 (__arm_vmulq_x_n_s16): Likewise.
5246 (__arm_vmulq_x_n_s32): Likewise.
5247 (__arm_vmulq_x_u8): Likewise.
5248 (__arm_vmulq_x_u16): Likewise.
5249 (__arm_vmulq_x_u32): Likewise.
5250 (__arm_vmulq_x_n_u8): Likewise.
5251 (__arm_vmulq_x_n_u16): Likewise.
5252 (__arm_vmulq_x_n_u32): Likewise.
5253 (__arm_vsubq_x_s8): Likewise.
5254 (__arm_vsubq_x_s16): Likewise.
5255 (__arm_vsubq_x_s32): Likewise.
5256 (__arm_vsubq_x_n_s8): Likewise.
5257 (__arm_vsubq_x_n_s16): Likewise.
5258 (__arm_vsubq_x_n_s32): Likewise.
5259 (__arm_vsubq_x_u8): Likewise.
5260 (__arm_vsubq_x_u16): Likewise.
5261 (__arm_vsubq_x_u32): Likewise.
5262 (__arm_vsubq_x_n_u8): Likewise.
5263 (__arm_vsubq_x_n_u16): Likewise.
5264 (__arm_vsubq_x_n_u32): Likewise.
5265 (__arm_vcaddq_rot90_x_s8): Likewise.
5266 (__arm_vcaddq_rot90_x_s16): Likewise.
5267 (__arm_vcaddq_rot90_x_s32): Likewise.
5268 (__arm_vcaddq_rot90_x_u8): Likewise.
5269 (__arm_vcaddq_rot90_x_u16): Likewise.
5270 (__arm_vcaddq_rot90_x_u32): Likewise.
5271 (__arm_vcaddq_rot270_x_s8): Likewise.
5272 (__arm_vcaddq_rot270_x_s16): Likewise.
5273 (__arm_vcaddq_rot270_x_s32): Likewise.
5274 (__arm_vcaddq_rot270_x_u8): Likewise.
5275 (__arm_vcaddq_rot270_x_u16): Likewise.
5276 (__arm_vcaddq_rot270_x_u32): Likewise.
5277 (__arm_vhaddq_x_n_s8): Likewise.
5278 (__arm_vhaddq_x_n_s16): Likewise.
5279 (__arm_vhaddq_x_n_s32): Likewise.
5280 (__arm_vhaddq_x_n_u8): Likewise.
5281 (__arm_vhaddq_x_n_u16): Likewise.
5282 (__arm_vhaddq_x_n_u32): Likewise.
5283 (__arm_vhaddq_x_s8): Likewise.
5284 (__arm_vhaddq_x_s16): Likewise.
5285 (__arm_vhaddq_x_s32): Likewise.
5286 (__arm_vhaddq_x_u8): Likewise.
5287 (__arm_vhaddq_x_u16): Likewise.
5288 (__arm_vhaddq_x_u32): Likewise.
5289 (__arm_vhcaddq_rot90_x_s8): Likewise.
5290 (__arm_vhcaddq_rot90_x_s16): Likewise.
5291 (__arm_vhcaddq_rot90_x_s32): Likewise.
5292 (__arm_vhcaddq_rot270_x_s8): Likewise.
5293 (__arm_vhcaddq_rot270_x_s16): Likewise.
5294 (__arm_vhcaddq_rot270_x_s32): Likewise.
5295 (__arm_vhsubq_x_n_s8): Likewise.
5296 (__arm_vhsubq_x_n_s16): Likewise.
5297 (__arm_vhsubq_x_n_s32): Likewise.
5298 (__arm_vhsubq_x_n_u8): Likewise.
5299 (__arm_vhsubq_x_n_u16): Likewise.
5300 (__arm_vhsubq_x_n_u32): Likewise.
5301 (__arm_vhsubq_x_s8): Likewise.
5302 (__arm_vhsubq_x_s16): Likewise.
5303 (__arm_vhsubq_x_s32): Likewise.
5304 (__arm_vhsubq_x_u8): Likewise.
5305 (__arm_vhsubq_x_u16): Likewise.
5306 (__arm_vhsubq_x_u32): Likewise.
5307 (__arm_vrhaddq_x_s8): Likewise.
5308 (__arm_vrhaddq_x_s16): Likewise.
5309 (__arm_vrhaddq_x_s32): Likewise.
5310 (__arm_vrhaddq_x_u8): Likewise.
5311 (__arm_vrhaddq_x_u16): Likewise.
5312 (__arm_vrhaddq_x_u32): Likewise.
5313 (__arm_vrmulhq_x_s8): Likewise.
5314 (__arm_vrmulhq_x_s16): Likewise.
5315 (__arm_vrmulhq_x_s32): Likewise.
5316 (__arm_vrmulhq_x_u8): Likewise.
5317 (__arm_vrmulhq_x_u16): Likewise.
5318 (__arm_vrmulhq_x_u32): Likewise.
5319 (__arm_vandq_x_s8): Likewise.
5320 (__arm_vandq_x_s16): Likewise.
5321 (__arm_vandq_x_s32): Likewise.
5322 (__arm_vandq_x_u8): Likewise.
5323 (__arm_vandq_x_u16): Likewise.
5324 (__arm_vandq_x_u32): Likewise.
5325 (__arm_vbicq_x_s8): Likewise.
5326 (__arm_vbicq_x_s16): Likewise.
5327 (__arm_vbicq_x_s32): Likewise.
5328 (__arm_vbicq_x_u8): Likewise.
5329 (__arm_vbicq_x_u16): Likewise.
5330 (__arm_vbicq_x_u32): Likewise.
5331 (__arm_vbrsrq_x_n_s8): Likewise.
5332 (__arm_vbrsrq_x_n_s16): Likewise.
5333 (__arm_vbrsrq_x_n_s32): Likewise.
5334 (__arm_vbrsrq_x_n_u8): Likewise.
5335 (__arm_vbrsrq_x_n_u16): Likewise.
5336 (__arm_vbrsrq_x_n_u32): Likewise.
5337 (__arm_veorq_x_s8): Likewise.
5338 (__arm_veorq_x_s16): Likewise.
5339 (__arm_veorq_x_s32): Likewise.
5340 (__arm_veorq_x_u8): Likewise.
5341 (__arm_veorq_x_u16): Likewise.
5342 (__arm_veorq_x_u32): Likewise.
5343 (__arm_vmovlbq_x_s8): Likewise.
5344 (__arm_vmovlbq_x_s16): Likewise.
5345 (__arm_vmovlbq_x_u8): Likewise.
5346 (__arm_vmovlbq_x_u16): Likewise.
5347 (__arm_vmovltq_x_s8): Likewise.
5348 (__arm_vmovltq_x_s16): Likewise.
5349 (__arm_vmovltq_x_u8): Likewise.
5350 (__arm_vmovltq_x_u16): Likewise.
5351 (__arm_vmvnq_x_s8): Likewise.
5352 (__arm_vmvnq_x_s16): Likewise.
5353 (__arm_vmvnq_x_s32): Likewise.
5354 (__arm_vmvnq_x_u8): Likewise.
5355 (__arm_vmvnq_x_u16): Likewise.
5356 (__arm_vmvnq_x_u32): Likewise.
5357 (__arm_vmvnq_x_n_s16): Likewise.
5358 (__arm_vmvnq_x_n_s32): Likewise.
5359 (__arm_vmvnq_x_n_u16): Likewise.
5360 (__arm_vmvnq_x_n_u32): Likewise.
5361 (__arm_vornq_x_s8): Likewise.
5362 (__arm_vornq_x_s16): Likewise.
5363 (__arm_vornq_x_s32): Likewise.
5364 (__arm_vornq_x_u8): Likewise.
5365 (__arm_vornq_x_u16): Likewise.
5366 (__arm_vornq_x_u32): Likewise.
5367 (__arm_vorrq_x_s8): Likewise.
5368 (__arm_vorrq_x_s16): Likewise.
5369 (__arm_vorrq_x_s32): Likewise.
5370 (__arm_vorrq_x_u8): Likewise.
5371 (__arm_vorrq_x_u16): Likewise.
5372 (__arm_vorrq_x_u32): Likewise.
5373 (__arm_vrev16q_x_s8): Likewise.
5374 (__arm_vrev16q_x_u8): Likewise.
5375 (__arm_vrev32q_x_s8): Likewise.
5376 (__arm_vrev32q_x_s16): Likewise.
5377 (__arm_vrev32q_x_u8): Likewise.
5378 (__arm_vrev32q_x_u16): Likewise.
5379 (__arm_vrev64q_x_s8): Likewise.
5380 (__arm_vrev64q_x_s16): Likewise.
5381 (__arm_vrev64q_x_s32): Likewise.
5382 (__arm_vrev64q_x_u8): Likewise.
5383 (__arm_vrev64q_x_u16): Likewise.
5384 (__arm_vrev64q_x_u32): Likewise.
5385 (__arm_vrshlq_x_s8): Likewise.
5386 (__arm_vrshlq_x_s16): Likewise.
5387 (__arm_vrshlq_x_s32): Likewise.
5388 (__arm_vrshlq_x_u8): Likewise.
5389 (__arm_vrshlq_x_u16): Likewise.
5390 (__arm_vrshlq_x_u32): Likewise.
5391 (__arm_vshllbq_x_n_s8): Likewise.
5392 (__arm_vshllbq_x_n_s16): Likewise.
5393 (__arm_vshllbq_x_n_u8): Likewise.
5394 (__arm_vshllbq_x_n_u16): Likewise.
5395 (__arm_vshlltq_x_n_s8): Likewise.
5396 (__arm_vshlltq_x_n_s16): Likewise.
5397 (__arm_vshlltq_x_n_u8): Likewise.
5398 (__arm_vshlltq_x_n_u16): Likewise.
5399 (__arm_vshlq_x_s8): Likewise.
5400 (__arm_vshlq_x_s16): Likewise.
5401 (__arm_vshlq_x_s32): Likewise.
5402 (__arm_vshlq_x_u8): Likewise.
5403 (__arm_vshlq_x_u16): Likewise.
5404 (__arm_vshlq_x_u32): Likewise.
5405 (__arm_vshlq_x_n_s8): Likewise.
5406 (__arm_vshlq_x_n_s16): Likewise.
5407 (__arm_vshlq_x_n_s32): Likewise.
5408 (__arm_vshlq_x_n_u8): Likewise.
5409 (__arm_vshlq_x_n_u16): Likewise.
5410 (__arm_vshlq_x_n_u32): Likewise.
5411 (__arm_vrshrq_x_n_s8): Likewise.
5412 (__arm_vrshrq_x_n_s16): Likewise.
5413 (__arm_vrshrq_x_n_s32): Likewise.
5414 (__arm_vrshrq_x_n_u8): Likewise.
5415 (__arm_vrshrq_x_n_u16): Likewise.
5416 (__arm_vrshrq_x_n_u32): Likewise.
5417 (__arm_vshrq_x_n_s8): Likewise.
5418 (__arm_vshrq_x_n_s16): Likewise.
5419 (__arm_vshrq_x_n_s32): Likewise.
5420 (__arm_vshrq_x_n_u8): Likewise.
5421 (__arm_vshrq_x_n_u16): Likewise.
5422 (__arm_vshrq_x_n_u32): Likewise.
5423 (__arm_vdupq_x_n_f16): Likewise.
5424 (__arm_vdupq_x_n_f32): Likewise.
5425 (__arm_vminnmq_x_f16): Likewise.
5426 (__arm_vminnmq_x_f32): Likewise.
5427 (__arm_vmaxnmq_x_f16): Likewise.
5428 (__arm_vmaxnmq_x_f32): Likewise.
5429 (__arm_vabdq_x_f16): Likewise.
5430 (__arm_vabdq_x_f32): Likewise.
5431 (__arm_vabsq_x_f16): Likewise.
5432 (__arm_vabsq_x_f32): Likewise.
5433 (__arm_vaddq_x_f16): Likewise.
5434 (__arm_vaddq_x_f32): Likewise.
5435 (__arm_vaddq_x_n_f16): Likewise.
5436 (__arm_vaddq_x_n_f32): Likewise.
5437 (__arm_vnegq_x_f16): Likewise.
5438 (__arm_vnegq_x_f32): Likewise.
5439 (__arm_vmulq_x_f16): Likewise.
5440 (__arm_vmulq_x_f32): Likewise.
5441 (__arm_vmulq_x_n_f16): Likewise.
5442 (__arm_vmulq_x_n_f32): Likewise.
5443 (__arm_vsubq_x_f16): Likewise.
5444 (__arm_vsubq_x_f32): Likewise.
5445 (__arm_vsubq_x_n_f16): Likewise.
5446 (__arm_vsubq_x_n_f32): Likewise.
5447 (__arm_vcaddq_rot90_x_f16): Likewise.
5448 (__arm_vcaddq_rot90_x_f32): Likewise.
5449 (__arm_vcaddq_rot270_x_f16): Likewise.
5450 (__arm_vcaddq_rot270_x_f32): Likewise.
5451 (__arm_vcmulq_x_f16): Likewise.
5452 (__arm_vcmulq_x_f32): Likewise.
5453 (__arm_vcmulq_rot90_x_f16): Likewise.
5454 (__arm_vcmulq_rot90_x_f32): Likewise.
5455 (__arm_vcmulq_rot180_x_f16): Likewise.
5456 (__arm_vcmulq_rot180_x_f32): Likewise.
5457 (__arm_vcmulq_rot270_x_f16): Likewise.
5458 (__arm_vcmulq_rot270_x_f32): Likewise.
5459 (__arm_vcvtaq_x_s16_f16): Likewise.
5460 (__arm_vcvtaq_x_s32_f32): Likewise.
5461 (__arm_vcvtaq_x_u16_f16): Likewise.
5462 (__arm_vcvtaq_x_u32_f32): Likewise.
5463 (__arm_vcvtnq_x_s16_f16): Likewise.
5464 (__arm_vcvtnq_x_s32_f32): Likewise.
5465 (__arm_vcvtnq_x_u16_f16): Likewise.
5466 (__arm_vcvtnq_x_u32_f32): Likewise.
5467 (__arm_vcvtpq_x_s16_f16): Likewise.
5468 (__arm_vcvtpq_x_s32_f32): Likewise.
5469 (__arm_vcvtpq_x_u16_f16): Likewise.
5470 (__arm_vcvtpq_x_u32_f32): Likewise.
5471 (__arm_vcvtmq_x_s16_f16): Likewise.
5472 (__arm_vcvtmq_x_s32_f32): Likewise.
5473 (__arm_vcvtmq_x_u16_f16): Likewise.
5474 (__arm_vcvtmq_x_u32_f32): Likewise.
5475 (__arm_vcvtbq_x_f32_f16): Likewise.
5476 (__arm_vcvttq_x_f32_f16): Likewise.
5477 (__arm_vcvtq_x_f16_u16): Likewise.
5478 (__arm_vcvtq_x_f16_s16): Likewise.
5479 (__arm_vcvtq_x_f32_s32): Likewise.
5480 (__arm_vcvtq_x_f32_u32): Likewise.
5481 (__arm_vcvtq_x_n_f16_s16): Likewise.
5482 (__arm_vcvtq_x_n_f16_u16): Likewise.
5483 (__arm_vcvtq_x_n_f32_s32): Likewise.
5484 (__arm_vcvtq_x_n_f32_u32): Likewise.
5485 (__arm_vcvtq_x_s16_f16): Likewise.
5486 (__arm_vcvtq_x_s32_f32): Likewise.
5487 (__arm_vcvtq_x_u16_f16): Likewise.
5488 (__arm_vcvtq_x_u32_f32): Likewise.
5489 (__arm_vcvtq_x_n_s16_f16): Likewise.
5490 (__arm_vcvtq_x_n_s32_f32): Likewise.
5491 (__arm_vcvtq_x_n_u16_f16): Likewise.
5492 (__arm_vcvtq_x_n_u32_f32): Likewise.
5493 (__arm_vrndq_x_f16): Likewise.
5494 (__arm_vrndq_x_f32): Likewise.
5495 (__arm_vrndnq_x_f16): Likewise.
5496 (__arm_vrndnq_x_f32): Likewise.
5497 (__arm_vrndmq_x_f16): Likewise.
5498 (__arm_vrndmq_x_f32): Likewise.
5499 (__arm_vrndpq_x_f16): Likewise.
5500 (__arm_vrndpq_x_f32): Likewise.
5501 (__arm_vrndaq_x_f16): Likewise.
5502 (__arm_vrndaq_x_f32): Likewise.
5503 (__arm_vrndxq_x_f16): Likewise.
5504 (__arm_vrndxq_x_f32): Likewise.
5505 (__arm_vandq_x_f16): Likewise.
5506 (__arm_vandq_x_f32): Likewise.
5507 (__arm_vbicq_x_f16): Likewise.
5508 (__arm_vbicq_x_f32): Likewise.
5509 (__arm_vbrsrq_x_n_f16): Likewise.
5510 (__arm_vbrsrq_x_n_f32): Likewise.
5511 (__arm_veorq_x_f16): Likewise.
5512 (__arm_veorq_x_f32): Likewise.
5513 (__arm_vornq_x_f16): Likewise.
5514 (__arm_vornq_x_f32): Likewise.
5515 (__arm_vorrq_x_f16): Likewise.
5516 (__arm_vorrq_x_f32): Likewise.
5517 (__arm_vrev32q_x_f16): Likewise.
5518 (__arm_vrev64q_x_f16): Likewise.
5519 (__arm_vrev64q_x_f32): Likewise.
5520 (vabdq_x): Define polymorphic variant.
5521 (vabsq_x): Likewise.
5522 (vaddq_x): Likewise.
5523 (vandq_x): Likewise.
5524 (vbicq_x): Likewise.
5525 (vbrsrq_x): Likewise.
5526 (vcaddq_rot270_x): Likewise.
5527 (vcaddq_rot90_x): Likewise.
5528 (vcmulq_rot180_x): Likewise.
5529 (vcmulq_rot270_x): Likewise.
5530 (vcmulq_x): Likewise.
5531 (vcvtq_x): Likewise.
5532 (vcvtq_x_n): Likewise.
5533 (vcvtnq_m): Likewise.
5534 (veorq_x): Likewise.
5535 (vmaxnmq_x): Likewise.
5536 (vminnmq_x): Likewise.
5537 (vmulq_x): Likewise.
5538 (vnegq_x): Likewise.
5539 (vornq_x): Likewise.
5540 (vorrq_x): Likewise.
5541 (vrev32q_x): Likewise.
5542 (vrev64q_x): Likewise.
5543 (vrndaq_x): Likewise.
5544 (vrndmq_x): Likewise.
5545 (vrndnq_x): Likewise.
5546 (vrndpq_x): Likewise.
5547 (vrndq_x): Likewise.
5548 (vrndxq_x): Likewise.
5549 (vsubq_x): Likewise.
5550 (vcmulq_rot90_x): Likewise.
5552 (vclsq_x): Likewise.
5553 (vclzq_x): Likewise.
5554 (vhaddq_x): Likewise.
5555 (vhcaddq_rot270_x): Likewise.
5556 (vhcaddq_rot90_x): Likewise.
5557 (vhsubq_x): Likewise.
5558 (vmaxq_x): Likewise.
5559 (vminq_x): Likewise.
5560 (vmovlbq_x): Likewise.
5561 (vmovltq_x): Likewise.
5562 (vmulhq_x): Likewise.
5563 (vmullbq_int_x): Likewise.
5564 (vmullbq_poly_x): Likewise.
5565 (vmulltq_int_x): Likewise.
5566 (vmulltq_poly_x): Likewise.
5567 (vmvnq_x): Likewise.
5568 (vrev16q_x): Likewise.
5569 (vrhaddq_x): Likewise.
5570 (vrmulhq_x): Likewise.
5571 (vrshlq_x): Likewise.
5572 (vrshrq_x): Likewise.
5573 (vshllbq_x): Likewise.
5574 (vshlltq_x): Likewise.
5575 (vshlq_x_n): Likewise.
5576 (vshlq_x): Likewise.
5577 (vdwdupq_x_u8): Likewise.
5578 (vdwdupq_x_u16): Likewise.
5579 (vdwdupq_x_u32): Likewise.
5580 (viwdupq_x_u8): Likewise.
5581 (viwdupq_x_u16): Likewise.
5582 (viwdupq_x_u32): Likewise.
5583 (vidupq_x_u8): Likewise.
5584 (vddupq_x_u8): Likewise.
5585 (vidupq_x_u16): Likewise.
5586 (vddupq_x_u16): Likewise.
5587 (vidupq_x_u32): Likewise.
5588 (vddupq_x_u32): Likewise.
5589 (vshrq_x): Likewise.
5591 2020-03-20 Richard Biener <rguenther@suse.de>
5593 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts
5594 to vectorize for CTOR defs.
5596 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5597 Andre Vieira <andre.simoesdiasvieira@arm.com>
5598 Mihail Ionescu <mihail.ionescu@arm.com>
5600 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin
5602 (LDRGBWBU_QUALIFIERS): Likewise.
5603 (LDRGBWBS_Z_QUALIFIERS): Likewise.
5604 (LDRGBWBU_Z_QUALIFIERS): Likewise.
5605 (STRSBWBS_QUALIFIERS): Likewise.
5606 (STRSBWBU_QUALIFIERS): Likewise.
5607 (STRSBWBS_P_QUALIFIERS): Likewise.
5608 (STRSBWBU_P_QUALIFIERS): Likewise.
5609 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro.
5610 (vldrdq_gather_base_wb_u64): Likewise.
5611 (vldrdq_gather_base_wb_z_s64): Likewise.
5612 (vldrdq_gather_base_wb_z_u64): Likewise.
5613 (vldrwq_gather_base_wb_f32): Likewise.
5614 (vldrwq_gather_base_wb_s32): Likewise.
5615 (vldrwq_gather_base_wb_u32): Likewise.
5616 (vldrwq_gather_base_wb_z_f32): Likewise.
5617 (vldrwq_gather_base_wb_z_s32): Likewise.
5618 (vldrwq_gather_base_wb_z_u32): Likewise.
5619 (vstrdq_scatter_base_wb_p_s64): Likewise.
5620 (vstrdq_scatter_base_wb_p_u64): Likewise.
5621 (vstrdq_scatter_base_wb_s64): Likewise.
5622 (vstrdq_scatter_base_wb_u64): Likewise.
5623 (vstrwq_scatter_base_wb_p_s32): Likewise.
5624 (vstrwq_scatter_base_wb_p_f32): Likewise.
5625 (vstrwq_scatter_base_wb_p_u32): Likewise.
5626 (vstrwq_scatter_base_wb_s32): Likewise.
5627 (vstrwq_scatter_base_wb_u32): Likewise.
5628 (vstrwq_scatter_base_wb_f32): Likewise.
5629 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic.
5630 (__arm_vldrdq_gather_base_wb_u64): Likewise.
5631 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
5632 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
5633 (__arm_vldrwq_gather_base_wb_s32): Likewise.
5634 (__arm_vldrwq_gather_base_wb_u32): Likewise.
5635 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
5636 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
5637 (__arm_vstrdq_scatter_base_wb_s64): Likewise.
5638 (__arm_vstrdq_scatter_base_wb_u64): Likewise.
5639 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
5640 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
5641 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
5642 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
5643 (__arm_vstrwq_scatter_base_wb_s32): Likewise.
5644 (__arm_vstrwq_scatter_base_wb_u32): Likewise.
5645 (__arm_vldrwq_gather_base_wb_f32): Likewise.
5646 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
5647 (__arm_vstrwq_scatter_base_wb_f32): Likewise.
5648 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
5649 (vstrwq_scatter_base_wb): Define polymorphic variant.
5650 (vstrwq_scatter_base_wb_p): Likewise.
5651 (vstrdq_scatter_base_wb_p): Likewise.
5652 (vstrdq_scatter_base_wb): Likewise.
5653 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin
5655 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL
5657 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise.
5658 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise.
5659 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
5660 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise.
5661 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise.
5662 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
5663 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
5664 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise.
5665 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
5666 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
5667 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise.
5668 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
5669 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise.
5670 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise.
5671 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
5672 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise.
5673 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise.
5674 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise.
5675 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
5676 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise.
5677 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
5678 (mve_vldrwq_gather_base_wb_fv4sf): Likewise.
5679 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
5680 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise.
5681 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
5682 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise.
5683 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
5684 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise.
5685 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
5687 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5688 Andre Vieira <andre.simoesdiasvieira@arm.com>
5689 Mihail Ionescu <mihail.ionescu@arm.com>
5691 * config/arm/arm-builtins.c
5692 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary
5694 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro.
5695 (vddupq_m_n_u32): Likewise.
5696 (vddupq_m_n_u16): Likewise.
5697 (vddupq_m_wb_u8): Likewise.
5698 (vddupq_m_wb_u16): Likewise.
5699 (vddupq_m_wb_u32): Likewise.
5700 (vddupq_n_u8): Likewise.
5701 (vddupq_n_u32): Likewise.
5702 (vddupq_n_u16): Likewise.
5703 (vddupq_wb_u8): Likewise.
5704 (vddupq_wb_u16): Likewise.
5705 (vddupq_wb_u32): Likewise.
5706 (vdwdupq_m_n_u8): Likewise.
5707 (vdwdupq_m_n_u32): Likewise.
5708 (vdwdupq_m_n_u16): Likewise.
5709 (vdwdupq_m_wb_u8): Likewise.
5710 (vdwdupq_m_wb_u32): Likewise.
5711 (vdwdupq_m_wb_u16): Likewise.
5712 (vdwdupq_n_u8): Likewise.
5713 (vdwdupq_n_u32): Likewise.
5714 (vdwdupq_n_u16): Likewise.
5715 (vdwdupq_wb_u8): Likewise.
5716 (vdwdupq_wb_u32): Likewise.
5717 (vdwdupq_wb_u16): Likewise.
5718 (vidupq_m_n_u8): Likewise.
5719 (vidupq_m_n_u32): Likewise.
5720 (vidupq_m_n_u16): Likewise.
5721 (vidupq_m_wb_u8): Likewise.
5722 (vidupq_m_wb_u16): Likewise.
5723 (vidupq_m_wb_u32): Likewise.
5724 (vidupq_n_u8): Likewise.
5725 (vidupq_n_u32): Likewise.
5726 (vidupq_n_u16): Likewise.
5727 (vidupq_wb_u8): Likewise.
5728 (vidupq_wb_u16): Likewise.
5729 (vidupq_wb_u32): Likewise.
5730 (viwdupq_m_n_u8): Likewise.
5731 (viwdupq_m_n_u32): Likewise.
5732 (viwdupq_m_n_u16): Likewise.
5733 (viwdupq_m_wb_u8): Likewise.
5734 (viwdupq_m_wb_u32): Likewise.
5735 (viwdupq_m_wb_u16): Likewise.
5736 (viwdupq_n_u8): Likewise.
5737 (viwdupq_n_u32): Likewise.
5738 (viwdupq_n_u16): Likewise.
5739 (viwdupq_wb_u8): Likewise.
5740 (viwdupq_wb_u32): Likewise.
5741 (viwdupq_wb_u16): Likewise.
5742 (__arm_vddupq_m_n_u8): Define intrinsic.
5743 (__arm_vddupq_m_n_u32): Likewise.
5744 (__arm_vddupq_m_n_u16): Likewise.
5745 (__arm_vddupq_m_wb_u8): Likewise.
5746 (__arm_vddupq_m_wb_u16): Likewise.
5747 (__arm_vddupq_m_wb_u32): Likewise.
5748 (__arm_vddupq_n_u8): Likewise.
5749 (__arm_vddupq_n_u32): Likewise.
5750 (__arm_vddupq_n_u16): Likewise.
5751 (__arm_vdwdupq_m_n_u8): Likewise.
5752 (__arm_vdwdupq_m_n_u32): Likewise.
5753 (__arm_vdwdupq_m_n_u16): Likewise.
5754 (__arm_vdwdupq_m_wb_u8): Likewise.
5755 (__arm_vdwdupq_m_wb_u32): Likewise.
5756 (__arm_vdwdupq_m_wb_u16): Likewise.
5757 (__arm_vdwdupq_n_u8): Likewise.
5758 (__arm_vdwdupq_n_u32): Likewise.
5759 (__arm_vdwdupq_n_u16): Likewise.
5760 (__arm_vdwdupq_wb_u8): Likewise.
5761 (__arm_vdwdupq_wb_u32): Likewise.
5762 (__arm_vdwdupq_wb_u16): Likewise.
5763 (__arm_vidupq_m_n_u8): Likewise.
5764 (__arm_vidupq_m_n_u32): Likewise.
5765 (__arm_vidupq_m_n_u16): Likewise.
5766 (__arm_vidupq_n_u8): Likewise.
5767 (__arm_vidupq_m_wb_u8): Likewise.
5768 (__arm_vidupq_m_wb_u16): Likewise.
5769 (__arm_vidupq_m_wb_u32): Likewise.
5770 (__arm_vidupq_n_u32): Likewise.
5771 (__arm_vidupq_n_u16): Likewise.
5772 (__arm_vidupq_wb_u8): Likewise.
5773 (__arm_vidupq_wb_u16): Likewise.
5774 (__arm_vidupq_wb_u32): Likewise.
5775 (__arm_vddupq_wb_u8): Likewise.
5776 (__arm_vddupq_wb_u16): Likewise.
5777 (__arm_vddupq_wb_u32): Likewise.
5778 (__arm_viwdupq_m_n_u8): Likewise.
5779 (__arm_viwdupq_m_n_u32): Likewise.
5780 (__arm_viwdupq_m_n_u16): Likewise.
5781 (__arm_viwdupq_m_wb_u8): Likewise.
5782 (__arm_viwdupq_m_wb_u32): Likewise.
5783 (__arm_viwdupq_m_wb_u16): Likewise.
5784 (__arm_viwdupq_n_u8): Likewise.
5785 (__arm_viwdupq_n_u32): Likewise.
5786 (__arm_viwdupq_n_u16): Likewise.
5787 (__arm_viwdupq_wb_u8): Likewise.
5788 (__arm_viwdupq_wb_u32): Likewise.
5789 (__arm_viwdupq_wb_u16): Likewise.
5790 (vidupq_m): Define polymorphic variant.
5791 (vddupq_m): Likewise.
5792 (vidupq_u16): Likewise.
5793 (vidupq_u32): Likewise.
5794 (vidupq_u8): Likewise.
5795 (vddupq_u16): Likewise.
5796 (vddupq_u32): Likewise.
5797 (vddupq_u8): Likewise.
5798 (viwdupq_m): Likewise.
5799 (viwdupq_u16): Likewise.
5800 (viwdupq_u32): Likewise.
5801 (viwdupq_u8): Likewise.
5802 (vdwdupq_m): Likewise.
5803 (vdwdupq_u16): Likewise.
5804 (vdwdupq_u32): Likewise.
5805 (vdwdupq_u8): Likewise.
5806 * config/arm/arm_mve_builtins.def
5807 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin
5809 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern.
5810 (mve_vidupq_u<mode>_insn): Likewise.
5811 (mve_vidupq_m_n_u<mode>): Likewise.
5812 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
5813 (mve_vddupq_n_u<mode>): Likewise.
5814 (mve_vddupq_u<mode>_insn): Likewise.
5815 (mve_vddupq_m_n_u<mode>): Likewise.
5816 (mve_vddupq_m_wb_u<mode>_insn): Likewise.
5817 (mve_vdwdupq_n_u<mode>): Likewise.
5818 (mve_vdwdupq_wb_u<mode>): Likewise.
5819 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
5820 (mve_vdwdupq_m_n_u<mode>): Likewise.
5821 (mve_vdwdupq_m_wb_u<mode>): Likewise.
5822 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
5823 (mve_viwdupq_n_u<mode>): Likewise.
5824 (mve_viwdupq_wb_u<mode>): Likewise.
5825 (mve_viwdupq_wb_u<mode>_insn): Likewise.
5826 (mve_viwdupq_m_n_u<mode>): Likewise.
5827 (mve_viwdupq_m_wb_u<mode>): Likewise.
5828 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
5830 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5832 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro.
5833 (vreinterpretq_s16_s64): Likewise.
5834 (vreinterpretq_s16_s8): Likewise.
5835 (vreinterpretq_s16_u16): Likewise.
5836 (vreinterpretq_s16_u32): Likewise.
5837 (vreinterpretq_s16_u64): Likewise.
5838 (vreinterpretq_s16_u8): Likewise.
5839 (vreinterpretq_s32_s16): Likewise.
5840 (vreinterpretq_s32_s64): Likewise.
5841 (vreinterpretq_s32_s8): Likewise.
5842 (vreinterpretq_s32_u16): Likewise.
5843 (vreinterpretq_s32_u32): Likewise.
5844 (vreinterpretq_s32_u64): Likewise.
5845 (vreinterpretq_s32_u8): Likewise.
5846 (vreinterpretq_s64_s16): Likewise.
5847 (vreinterpretq_s64_s32): Likewise.
5848 (vreinterpretq_s64_s8): Likewise.
5849 (vreinterpretq_s64_u16): Likewise.
5850 (vreinterpretq_s64_u32): Likewise.
5851 (vreinterpretq_s64_u64): Likewise.
5852 (vreinterpretq_s64_u8): Likewise.
5853 (vreinterpretq_s8_s16): Likewise.
5854 (vreinterpretq_s8_s32): Likewise.
5855 (vreinterpretq_s8_s64): Likewise.
5856 (vreinterpretq_s8_u16): Likewise.
5857 (vreinterpretq_s8_u32): Likewise.
5858 (vreinterpretq_s8_u64): Likewise.
5859 (vreinterpretq_s8_u8): Likewise.
5860 (vreinterpretq_u16_s16): Likewise.
5861 (vreinterpretq_u16_s32): Likewise.
5862 (vreinterpretq_u16_s64): Likewise.
5863 (vreinterpretq_u16_s8): Likewise.
5864 (vreinterpretq_u16_u32): Likewise.
5865 (vreinterpretq_u16_u64): Likewise.
5866 (vreinterpretq_u16_u8): Likewise.
5867 (vreinterpretq_u32_s16): Likewise.
5868 (vreinterpretq_u32_s32): Likewise.
5869 (vreinterpretq_u32_s64): Likewise.
5870 (vreinterpretq_u32_s8): Likewise.
5871 (vreinterpretq_u32_u16): Likewise.
5872 (vreinterpretq_u32_u64): Likewise.
5873 (vreinterpretq_u32_u8): Likewise.
5874 (vreinterpretq_u64_s16): Likewise.
5875 (vreinterpretq_u64_s32): Likewise.
5876 (vreinterpretq_u64_s64): Likewise.
5877 (vreinterpretq_u64_s8): Likewise.
5878 (vreinterpretq_u64_u16): Likewise.
5879 (vreinterpretq_u64_u32): Likewise.
5880 (vreinterpretq_u64_u8): Likewise.
5881 (vreinterpretq_u8_s16): Likewise.
5882 (vreinterpretq_u8_s32): Likewise.
5883 (vreinterpretq_u8_s64): Likewise.
5884 (vreinterpretq_u8_s8): Likewise.
5885 (vreinterpretq_u8_u16): Likewise.
5886 (vreinterpretq_u8_u32): Likewise.
5887 (vreinterpretq_u8_u64): Likewise.
5888 (vreinterpretq_s32_f16): Likewise.
5889 (vreinterpretq_s32_f32): Likewise.
5890 (vreinterpretq_u16_f16): Likewise.
5891 (vreinterpretq_u16_f32): Likewise.
5892 (vreinterpretq_u32_f16): Likewise.
5893 (vreinterpretq_u32_f32): Likewise.
5894 (vreinterpretq_u64_f16): Likewise.
5895 (vreinterpretq_u64_f32): Likewise.
5896 (vreinterpretq_u8_f16): Likewise.
5897 (vreinterpretq_u8_f32): Likewise.
5898 (vreinterpretq_f16_f32): Likewise.
5899 (vreinterpretq_f16_s16): Likewise.
5900 (vreinterpretq_f16_s32): Likewise.
5901 (vreinterpretq_f16_s64): Likewise.
5902 (vreinterpretq_f16_s8): Likewise.
5903 (vreinterpretq_f16_u16): Likewise.
5904 (vreinterpretq_f16_u32): Likewise.
5905 (vreinterpretq_f16_u64): Likewise.
5906 (vreinterpretq_f16_u8): Likewise.
5907 (vreinterpretq_f32_f16): Likewise.
5908 (vreinterpretq_f32_s16): Likewise.
5909 (vreinterpretq_f32_s32): Likewise.
5910 (vreinterpretq_f32_s64): Likewise.
5911 (vreinterpretq_f32_s8): Likewise.
5912 (vreinterpretq_f32_u16): Likewise.
5913 (vreinterpretq_f32_u32): Likewise.
5914 (vreinterpretq_f32_u64): Likewise.
5915 (vreinterpretq_f32_u8): Likewise.
5916 (vreinterpretq_s16_f16): Likewise.
5917 (vreinterpretq_s16_f32): Likewise.
5918 (vreinterpretq_s64_f16): Likewise.
5919 (vreinterpretq_s64_f32): Likewise.
5920 (vreinterpretq_s8_f16): Likewise.
5921 (vreinterpretq_s8_f32): Likewise.
5922 (vuninitializedq_u8): Likewise.
5923 (vuninitializedq_u16): Likewise.
5924 (vuninitializedq_u32): Likewise.
5925 (vuninitializedq_u64): Likewise.
5926 (vuninitializedq_s8): Likewise.
5927 (vuninitializedq_s16): Likewise.
5928 (vuninitializedq_s32): Likewise.
5929 (vuninitializedq_s64): Likewise.
5930 (vuninitializedq_f16): Likewise.
5931 (vuninitializedq_f32): Likewise.
5932 (__arm_vuninitializedq_u8): Define intrinsic.
5933 (__arm_vuninitializedq_u16): Likewise.
5934 (__arm_vuninitializedq_u32): Likewise.
5935 (__arm_vuninitializedq_u64): Likewise.
5936 (__arm_vuninitializedq_s8): Likewise.
5937 (__arm_vuninitializedq_s16): Likewise.
5938 (__arm_vuninitializedq_s32): Likewise.
5939 (__arm_vuninitializedq_s64): Likewise.
5940 (__arm_vreinterpretq_s16_s32): Likewise.
5941 (__arm_vreinterpretq_s16_s64): Likewise.
5942 (__arm_vreinterpretq_s16_s8): Likewise.
5943 (__arm_vreinterpretq_s16_u16): Likewise.
5944 (__arm_vreinterpretq_s16_u32): Likewise.
5945 (__arm_vreinterpretq_s16_u64): Likewise.
5946 (__arm_vreinterpretq_s16_u8): Likewise.
5947 (__arm_vreinterpretq_s32_s16): Likewise.
5948 (__arm_vreinterpretq_s32_s64): Likewise.
5949 (__arm_vreinterpretq_s32_s8): Likewise.
5950 (__arm_vreinterpretq_s32_u16): Likewise.
5951 (__arm_vreinterpretq_s32_u32): Likewise.
5952 (__arm_vreinterpretq_s32_u64): Likewise.
5953 (__arm_vreinterpretq_s32_u8): Likewise.
5954 (__arm_vreinterpretq_s64_s16): Likewise.
5955 (__arm_vreinterpretq_s64_s32): Likewise.
5956 (__arm_vreinterpretq_s64_s8): Likewise.
5957 (__arm_vreinterpretq_s64_u16): Likewise.
5958 (__arm_vreinterpretq_s64_u32): Likewise.
5959 (__arm_vreinterpretq_s64_u64): Likewise.
5960 (__arm_vreinterpretq_s64_u8): Likewise.
5961 (__arm_vreinterpretq_s8_s16): Likewise.
5962 (__arm_vreinterpretq_s8_s32): Likewise.
5963 (__arm_vreinterpretq_s8_s64): Likewise.
5964 (__arm_vreinterpretq_s8_u16): Likewise.
5965 (__arm_vreinterpretq_s8_u32): Likewise.
5966 (__arm_vreinterpretq_s8_u64): Likewise.
5967 (__arm_vreinterpretq_s8_u8): Likewise.
5968 (__arm_vreinterpretq_u16_s16): Likewise.
5969 (__arm_vreinterpretq_u16_s32): Likewise.
5970 (__arm_vreinterpretq_u16_s64): Likewise.
5971 (__arm_vreinterpretq_u16_s8): Likewise.
5972 (__arm_vreinterpretq_u16_u32): Likewise.
5973 (__arm_vreinterpretq_u16_u64): Likewise.
5974 (__arm_vreinterpretq_u16_u8): Likewise.
5975 (__arm_vreinterpretq_u32_s16): Likewise.
5976 (__arm_vreinterpretq_u32_s32): Likewise.
5977 (__arm_vreinterpretq_u32_s64): Likewise.
5978 (__arm_vreinterpretq_u32_s8): Likewise.
5979 (__arm_vreinterpretq_u32_u16): Likewise.
5980 (__arm_vreinterpretq_u32_u64): Likewise.
5981 (__arm_vreinterpretq_u32_u8): Likewise.
5982 (__arm_vreinterpretq_u64_s16): Likewise.
5983 (__arm_vreinterpretq_u64_s32): Likewise.
5984 (__arm_vreinterpretq_u64_s64): Likewise.
5985 (__arm_vreinterpretq_u64_s8): Likewise.
5986 (__arm_vreinterpretq_u64_u16): Likewise.
5987 (__arm_vreinterpretq_u64_u32): Likewise.
5988 (__arm_vreinterpretq_u64_u8): Likewise.
5989 (__arm_vreinterpretq_u8_s16): Likewise.
5990 (__arm_vreinterpretq_u8_s32): Likewise.
5991 (__arm_vreinterpretq_u8_s64): Likewise.
5992 (__arm_vreinterpretq_u8_s8): Likewise.
5993 (__arm_vreinterpretq_u8_u16): Likewise.
5994 (__arm_vreinterpretq_u8_u32): Likewise.
5995 (__arm_vreinterpretq_u8_u64): Likewise.
5996 (__arm_vuninitializedq_f16): Likewise.
5997 (__arm_vuninitializedq_f32): Likewise.
5998 (__arm_vreinterpretq_s32_f16): Likewise.
5999 (__arm_vreinterpretq_s32_f32): Likewise.
6000 (__arm_vreinterpretq_s16_f16): Likewise.
6001 (__arm_vreinterpretq_s16_f32): Likewise.
6002 (__arm_vreinterpretq_s64_f16): Likewise.
6003 (__arm_vreinterpretq_s64_f32): Likewise.
6004 (__arm_vreinterpretq_s8_f16): Likewise.
6005 (__arm_vreinterpretq_s8_f32): Likewise.
6006 (__arm_vreinterpretq_u16_f16): Likewise.
6007 (__arm_vreinterpretq_u16_f32): Likewise.
6008 (__arm_vreinterpretq_u32_f16): Likewise.
6009 (__arm_vreinterpretq_u32_f32): Likewise.
6010 (__arm_vreinterpretq_u64_f16): Likewise.
6011 (__arm_vreinterpretq_u64_f32): Likewise.
6012 (__arm_vreinterpretq_u8_f16): Likewise.
6013 (__arm_vreinterpretq_u8_f32): Likewise.
6014 (__arm_vreinterpretq_f16_f32): Likewise.
6015 (__arm_vreinterpretq_f16_s16): Likewise.
6016 (__arm_vreinterpretq_f16_s32): Likewise.
6017 (__arm_vreinterpretq_f16_s64): Likewise.
6018 (__arm_vreinterpretq_f16_s8): Likewise.
6019 (__arm_vreinterpretq_f16_u16): Likewise.
6020 (__arm_vreinterpretq_f16_u32): Likewise.
6021 (__arm_vreinterpretq_f16_u64): Likewise.
6022 (__arm_vreinterpretq_f16_u8): Likewise.
6023 (__arm_vreinterpretq_f32_f16): Likewise.
6024 (__arm_vreinterpretq_f32_s16): Likewise.
6025 (__arm_vreinterpretq_f32_s32): Likewise.
6026 (__arm_vreinterpretq_f32_s64): Likewise.
6027 (__arm_vreinterpretq_f32_s8): Likewise.
6028 (__arm_vreinterpretq_f32_u16): Likewise.
6029 (__arm_vreinterpretq_f32_u32): Likewise.
6030 (__arm_vreinterpretq_f32_u64): Likewise.
6031 (__arm_vreinterpretq_f32_u8): Likewise.
6032 (vuninitializedq): Define polymorphic variant.
6033 (vreinterpretq_f16): Likewise.
6034 (vreinterpretq_f32): Likewise.
6035 (vreinterpretq_s16): Likewise.
6036 (vreinterpretq_s32): Likewise.
6037 (vreinterpretq_s64): Likewise.
6038 (vreinterpretq_s8): Likewise.
6039 (vreinterpretq_u16): Likewise.
6040 (vreinterpretq_u32): Likewise.
6041 (vreinterpretq_u64): Likewise.
6042 (vreinterpretq_u8): Likewise.
6044 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6045 Andre Vieira <andre.simoesdiasvieira@arm.com>
6046 Mihail Ionescu <mihail.ionescu@arm.com>
6048 * config/arm/arm_mve.h (vaddq_s8): Define macro.
6049 (vaddq_s16): Likewise.
6050 (vaddq_s32): Likewise.
6051 (vaddq_u8): Likewise.
6052 (vaddq_u16): Likewise.
6053 (vaddq_u32): Likewise.
6054 (vaddq_f16): Likewise.
6055 (vaddq_f32): Likewise.
6056 (__arm_vaddq_s8): Define intrinsic.
6057 (__arm_vaddq_s16): Likewise.
6058 (__arm_vaddq_s32): Likewise.
6059 (__arm_vaddq_u8): Likewise.
6060 (__arm_vaddq_u16): Likewise.
6061 (__arm_vaddq_u32): Likewise.
6062 (__arm_vaddq_f16): Likewise.
6063 (__arm_vaddq_f32): Likewise.
6064 (vaddq): Define polymorphic variant.
6065 * config/arm/iterators.md (VNIM): Define mode iterator for common types
6066 Neon, IWMMXT and MVE.
6067 (VNINOTM): Likewise.
6068 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern.
6069 (mve_vaddq_f<mode>): Define RTL pattern.
6070 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern.
6071 (addv8hf3_neon): Define RTL pattern.
6072 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern
6074 (addv8hf3): Define standard RTL pattern for MVE and Neon.
6075 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT.
6077 2020-03-20 Martin Liska <mliska@suse.cz>
6080 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously
6081 build_ref_for_offset function was used and it transforms off to bytes
6084 2020-03-20 Richard Biener <rguenther@suse.de>
6086 PR tree-optimization/94266
6087 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the
6088 type of the underlying object to adjust for the containing
6091 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6093 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
6094 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
6095 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
6097 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6099 * config/arm/mve.md (mve_mov<mode>): Fix R->R case.
6101 2020-03-20 Jakub Jelinek <jakub@redhat.com>
6103 PR tree-optimization/94224
6104 * gimple-ssa-store-merging.c
6105 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping
6106 or adjacent INTEGER_CST rhs_code stores as mergeable if they have
6109 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6111 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve.
6113 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
6116 * cgraph.c (cgraph_node::function_symbol): Fix availability computation.
6117 (cgraph_node::function_or_virtual_thunk_symbol): Likewise.
6119 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
6122 * cgraphunit.c (process_function_and_variable_attributes): warn
6123 for flatten attribute on alias.
6124 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias.
6126 2020-03-19 Martin Liska <mliska@suse.cz>
6128 * lto-section-in.c: Add ext_symtab.
6129 * lto-streamer-out.c (write_symbol_extension_info): New.
6130 (produce_symtab_extension): New.
6131 (produce_asm_for_decls): Stream also produce_symtab_extension.
6132 * lto-streamer.h (enum lto_section_type): New section.
6134 2020-03-19 Jakub Jelinek <jakub@redhat.com>
6136 PR tree-optimization/94211
6137 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
6138 instead of estimate_num_insns for bb_seq (middle_bb). Rename
6139 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
6142 2020-03-19 Richard Biener <rguenther@suse.de>
6145 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr
6146 and build_ref_for_offset.
6148 2020-03-19 Richard Biener <rguenther@suse.de>
6151 * fold-const.c (fold_binary_loc): Avoid using
6152 build_fold_addr_expr when we really want an ADDR_EXPR.
6154 2020-03-18 Segher Boessenkool <segher@kernel.crashing.org>
6156 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented
6159 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
6161 PR rtl-optimization/90275
6162 * cse.c (cse_insn): Delete no-op register moves too.
6164 2020-03-18 Martin Sebor <msebor@redhat.com>
6167 * cgraphunit.c (process_function_and_variable_attributes): Also
6168 complain about weakref function definitions and drop all effects
6171 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6172 Mihail Ionescu <mihail.ionescu@arm.com>
6173 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6175 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
6176 (vstrdq_scatter_base_p_u64): Likewise.
6177 (vstrdq_scatter_base_s64): Likewise.
6178 (vstrdq_scatter_base_u64): Likewise.
6179 (vstrdq_scatter_offset_p_s64): Likewise.
6180 (vstrdq_scatter_offset_p_u64): Likewise.
6181 (vstrdq_scatter_offset_s64): Likewise.
6182 (vstrdq_scatter_offset_u64): Likewise.
6183 (vstrdq_scatter_shifted_offset_p_s64): Likewise.
6184 (vstrdq_scatter_shifted_offset_p_u64): Likewise.
6185 (vstrdq_scatter_shifted_offset_s64): Likewise.
6186 (vstrdq_scatter_shifted_offset_u64): Likewise.
6187 (vstrhq_scatter_offset_f16): Likewise.
6188 (vstrhq_scatter_offset_p_f16): Likewise.
6189 (vstrhq_scatter_shifted_offset_f16): Likewise.
6190 (vstrhq_scatter_shifted_offset_p_f16): Likewise.
6191 (vstrwq_scatter_base_f32): Likewise.
6192 (vstrwq_scatter_base_p_f32): Likewise.
6193 (vstrwq_scatter_offset_f32): Likewise.
6194 (vstrwq_scatter_offset_p_f32): Likewise.
6195 (vstrwq_scatter_offset_p_s32): Likewise.
6196 (vstrwq_scatter_offset_p_u32): Likewise.
6197 (vstrwq_scatter_offset_s32): Likewise.
6198 (vstrwq_scatter_offset_u32): Likewise.
6199 (vstrwq_scatter_shifted_offset_f32): Likewise.
6200 (vstrwq_scatter_shifted_offset_p_f32): Likewise.
6201 (vstrwq_scatter_shifted_offset_p_s32): Likewise.
6202 (vstrwq_scatter_shifted_offset_p_u32): Likewise.
6203 (vstrwq_scatter_shifted_offset_s32): Likewise.
6204 (vstrwq_scatter_shifted_offset_u32): Likewise.
6205 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
6206 (__arm_vstrdq_scatter_base_p_u64): Likewise.
6207 (__arm_vstrdq_scatter_base_s64): Likewise.
6208 (__arm_vstrdq_scatter_base_u64): Likewise.
6209 (__arm_vstrdq_scatter_offset_p_s64): Likewise.
6210 (__arm_vstrdq_scatter_offset_p_u64): Likewise.
6211 (__arm_vstrdq_scatter_offset_s64): Likewise.
6212 (__arm_vstrdq_scatter_offset_u64): Likewise.
6213 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
6214 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
6215 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
6216 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
6217 (__arm_vstrwq_scatter_offset_p_s32): Likewise.
6218 (__arm_vstrwq_scatter_offset_p_u32): Likewise.
6219 (__arm_vstrwq_scatter_offset_s32): Likewise.
6220 (__arm_vstrwq_scatter_offset_u32): Likewise.
6221 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
6222 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
6223 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
6224 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
6225 (__arm_vstrhq_scatter_offset_f16): Likewise.
6226 (__arm_vstrhq_scatter_offset_p_f16): Likewise.
6227 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
6228 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
6229 (__arm_vstrwq_scatter_base_f32): Likewise.
6230 (__arm_vstrwq_scatter_base_p_f32): Likewise.
6231 (__arm_vstrwq_scatter_offset_f32): Likewise.
6232 (__arm_vstrwq_scatter_offset_p_f32): Likewise.
6233 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
6234 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
6235 (vstrhq_scatter_offset): Define polymorphic variant.
6236 (vstrhq_scatter_offset_p): Likewise.
6237 (vstrhq_scatter_shifted_offset): Likewise.
6238 (vstrhq_scatter_shifted_offset_p): Likewise.
6239 (vstrwq_scatter_base): Likewise.
6240 (vstrwq_scatter_base_p): Likewise.
6241 (vstrwq_scatter_offset): Likewise.
6242 (vstrwq_scatter_offset_p): Likewise.
6243 (vstrwq_scatter_shifted_offset): Likewise.
6244 (vstrwq_scatter_shifted_offset_p): Likewise.
6245 (vstrdq_scatter_base_p): Likewise.
6246 (vstrdq_scatter_base): Likewise.
6247 (vstrdq_scatter_offset_p): Likewise.
6248 (vstrdq_scatter_offset): Likewise.
6249 (vstrdq_scatter_shifted_offset_p): Likewise.
6250 (vstrdq_scatter_shifted_offset): Likewise.
6251 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
6252 (STRSBS_P): Likewise.
6254 (STRSBU_P): Likewise.
6256 (STRSS_P): Likewise.
6258 (STRSU_P): Likewise.
6259 * config/arm/constraints.md (Ri): Define.
6260 * config/arm/mve.md (VSTRDSBQ): Define iterator.
6261 (VSTRDSOQ): Likewise.
6262 (VSTRDSSOQ): Likewise.
6263 (VSTRWSOQ): Likewise.
6264 (VSTRWSSOQ): Likewise.
6265 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
6266 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
6267 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
6268 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
6269 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
6270 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
6271 (mve_vstrhq_scatter_offset_fv8hf): Likewise.
6272 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
6273 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
6274 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
6275 (mve_vstrwq_scatter_base_fv4sf): Likewise.
6276 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
6277 (mve_vstrwq_scatter_offset_fv4sf): Likewise.
6278 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
6279 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
6280 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
6281 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
6282 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
6283 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
6284 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
6285 * config/arm/predicates.md (Ri): Define predicate to check immediate
6286 is the range +/-1016 and multiple of 8.
6288 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6289 Mihail Ionescu <mihail.ionescu@arm.com>
6290 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6292 * config/arm/arm_mve.h (vst1q_f32): Define macro.
6293 (vst1q_f16): Likewise.
6294 (vst1q_s8): Likewise.
6295 (vst1q_s32): Likewise.
6296 (vst1q_s16): Likewise.
6297 (vst1q_u8): Likewise.
6298 (vst1q_u32): Likewise.
6299 (vst1q_u16): Likewise.
6300 (vstrhq_f16): Likewise.
6301 (vstrhq_scatter_offset_s32): Likewise.
6302 (vstrhq_scatter_offset_s16): Likewise.
6303 (vstrhq_scatter_offset_u32): Likewise.
6304 (vstrhq_scatter_offset_u16): Likewise.
6305 (vstrhq_scatter_offset_p_s32): Likewise.
6306 (vstrhq_scatter_offset_p_s16): Likewise.
6307 (vstrhq_scatter_offset_p_u32): Likewise.
6308 (vstrhq_scatter_offset_p_u16): Likewise.
6309 (vstrhq_scatter_shifted_offset_s32): Likewise.
6310 (vstrhq_scatter_shifted_offset_s16): Likewise.
6311 (vstrhq_scatter_shifted_offset_u32): Likewise.
6312 (vstrhq_scatter_shifted_offset_u16): Likewise.
6313 (vstrhq_scatter_shifted_offset_p_s32): Likewise.
6314 (vstrhq_scatter_shifted_offset_p_s16): Likewise.
6315 (vstrhq_scatter_shifted_offset_p_u32): Likewise.
6316 (vstrhq_scatter_shifted_offset_p_u16): Likewise.
6317 (vstrhq_s32): Likewise.
6318 (vstrhq_s16): Likewise.
6319 (vstrhq_u32): Likewise.
6320 (vstrhq_u16): Likewise.
6321 (vstrhq_p_f16): Likewise.
6322 (vstrhq_p_s32): Likewise.
6323 (vstrhq_p_s16): Likewise.
6324 (vstrhq_p_u32): Likewise.
6325 (vstrhq_p_u16): Likewise.
6326 (vstrwq_f32): Likewise.
6327 (vstrwq_s32): Likewise.
6328 (vstrwq_u32): Likewise.
6329 (vstrwq_p_f32): Likewise.
6330 (vstrwq_p_s32): Likewise.
6331 (vstrwq_p_u32): Likewise.
6332 (__arm_vst1q_s8): Define intrinsic.
6333 (__arm_vst1q_s32): Likewise.
6334 (__arm_vst1q_s16): Likewise.
6335 (__arm_vst1q_u8): Likewise.
6336 (__arm_vst1q_u32): Likewise.
6337 (__arm_vst1q_u16): Likewise.
6338 (__arm_vstrhq_scatter_offset_s32): Likewise.
6339 (__arm_vstrhq_scatter_offset_s16): Likewise.
6340 (__arm_vstrhq_scatter_offset_u32): Likewise.
6341 (__arm_vstrhq_scatter_offset_u16): Likewise.
6342 (__arm_vstrhq_scatter_offset_p_s32): Likewise.
6343 (__arm_vstrhq_scatter_offset_p_s16): Likewise.
6344 (__arm_vstrhq_scatter_offset_p_u32): Likewise.
6345 (__arm_vstrhq_scatter_offset_p_u16): Likewise.
6346 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
6347 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
6348 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
6349 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
6350 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
6351 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
6352 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
6353 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
6354 (__arm_vstrhq_s32): Likewise.
6355 (__arm_vstrhq_s16): Likewise.
6356 (__arm_vstrhq_u32): Likewise.
6357 (__arm_vstrhq_u16): Likewise.
6358 (__arm_vstrhq_p_s32): Likewise.
6359 (__arm_vstrhq_p_s16): Likewise.
6360 (__arm_vstrhq_p_u32): Likewise.
6361 (__arm_vstrhq_p_u16): Likewise.
6362 (__arm_vstrwq_s32): Likewise.
6363 (__arm_vstrwq_u32): Likewise.
6364 (__arm_vstrwq_p_s32): Likewise.
6365 (__arm_vstrwq_p_u32): Likewise.
6366 (__arm_vstrwq_p_f32): Likewise.
6367 (__arm_vstrwq_f32): Likewise.
6368 (__arm_vst1q_f32): Likewise.
6369 (__arm_vst1q_f16): Likewise.
6370 (__arm_vstrhq_f16): Likewise.
6371 (__arm_vstrhq_p_f16): Likewise.
6372 (vst1q): Define polymorphic variant.
6374 (vstrhq_p): Likewise.
6375 (vstrhq_scatter_offset_p): Likewise.
6376 (vstrhq_scatter_offset): Likewise.
6377 (vstrhq_scatter_shifted_offset_p): Likewise.
6378 (vstrhq_scatter_shifted_offset): Likewise.
6379 (vstrwq_p): Likewise.
6381 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
6384 (STRSS_P): Likewise.
6386 (STRSU_P): Likewise.
6389 * config/arm/mve.md (VST1Q): Define iterator.
6390 (VSTRHSOQ): Likewise.
6391 (VSTRHSSOQ): Likewise.
6394 (mve_vstrhq_fv8hf): Define RTL pattern.
6395 (mve_vstrhq_p_fv8hf): Likewise.
6396 (mve_vstrhq_p_<supf><mode>): Likewise.
6397 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
6398 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
6399 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
6400 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
6401 (mve_vstrhq_<supf><mode>): Likewise.
6402 (mve_vstrwq_fv4sf): Likewise.
6403 (mve_vstrwq_p_fv4sf): Likewise.
6404 (mve_vstrwq_p_<supf>v4si): Likewise.
6405 (mve_vstrwq_<supf>v4si): Likewise.
6406 (mve_vst1q_f<mode>): Define expand.
6407 (mve_vst1q_<supf><mode>): Likewise.
6409 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6410 Mihail Ionescu <mihail.ionescu@arm.com>
6411 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6413 * config/arm/arm_mve.h (vld1q_s8): Define macro.
6414 (vld1q_s32): Likewise.
6415 (vld1q_s16): Likewise.
6416 (vld1q_u8): Likewise.
6417 (vld1q_u32): Likewise.
6418 (vld1q_u16): Likewise.
6419 (vldrhq_gather_offset_s32): Likewise.
6420 (vldrhq_gather_offset_s16): Likewise.
6421 (vldrhq_gather_offset_u32): Likewise.
6422 (vldrhq_gather_offset_u16): Likewise.
6423 (vldrhq_gather_offset_z_s32): Likewise.
6424 (vldrhq_gather_offset_z_s16): Likewise.
6425 (vldrhq_gather_offset_z_u32): Likewise.
6426 (vldrhq_gather_offset_z_u16): Likewise.
6427 (vldrhq_gather_shifted_offset_s32): Likewise.
6428 (vldrhq_gather_shifted_offset_s16): Likewise.
6429 (vldrhq_gather_shifted_offset_u32): Likewise.
6430 (vldrhq_gather_shifted_offset_u16): Likewise.
6431 (vldrhq_gather_shifted_offset_z_s32): Likewise.
6432 (vldrhq_gather_shifted_offset_z_s16): Likewise.
6433 (vldrhq_gather_shifted_offset_z_u32): Likewise.
6434 (vldrhq_gather_shifted_offset_z_u16): Likewise.
6435 (vldrhq_s32): Likewise.
6436 (vldrhq_s16): Likewise.
6437 (vldrhq_u32): Likewise.
6438 (vldrhq_u16): Likewise.
6439 (vldrhq_z_s32): Likewise.
6440 (vldrhq_z_s16): Likewise.
6441 (vldrhq_z_u32): Likewise.
6442 (vldrhq_z_u16): Likewise.
6443 (vldrwq_s32): Likewise.
6444 (vldrwq_u32): Likewise.
6445 (vldrwq_z_s32): Likewise.
6446 (vldrwq_z_u32): Likewise.
6447 (vld1q_f32): Likewise.
6448 (vld1q_f16): Likewise.
6449 (vldrhq_f16): Likewise.
6450 (vldrhq_z_f16): Likewise.
6451 (vldrwq_f32): Likewise.
6452 (vldrwq_z_f32): Likewise.
6453 (__arm_vld1q_s8): Define intrinsic.
6454 (__arm_vld1q_s32): Likewise.
6455 (__arm_vld1q_s16): Likewise.
6456 (__arm_vld1q_u8): Likewise.
6457 (__arm_vld1q_u32): Likewise.
6458 (__arm_vld1q_u16): Likewise.
6459 (__arm_vldrhq_gather_offset_s32): Likewise.
6460 (__arm_vldrhq_gather_offset_s16): Likewise.
6461 (__arm_vldrhq_gather_offset_u32): Likewise.
6462 (__arm_vldrhq_gather_offset_u16): Likewise.
6463 (__arm_vldrhq_gather_offset_z_s32): Likewise.
6464 (__arm_vldrhq_gather_offset_z_s16): Likewise.
6465 (__arm_vldrhq_gather_offset_z_u32): Likewise.
6466 (__arm_vldrhq_gather_offset_z_u16): Likewise.
6467 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
6468 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
6469 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
6470 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
6471 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
6472 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
6473 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
6474 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
6475 (__arm_vldrhq_s32): Likewise.
6476 (__arm_vldrhq_s16): Likewise.
6477 (__arm_vldrhq_u32): Likewise.
6478 (__arm_vldrhq_u16): Likewise.
6479 (__arm_vldrhq_z_s32): Likewise.
6480 (__arm_vldrhq_z_s16): Likewise.
6481 (__arm_vldrhq_z_u32): Likewise.
6482 (__arm_vldrhq_z_u16): Likewise.
6483 (__arm_vldrwq_s32): Likewise.
6484 (__arm_vldrwq_u32): Likewise.
6485 (__arm_vldrwq_z_s32): Likewise.
6486 (__arm_vldrwq_z_u32): Likewise.
6487 (__arm_vld1q_f32): Likewise.
6488 (__arm_vld1q_f16): Likewise.
6489 (__arm_vldrwq_f32): Likewise.
6490 (__arm_vldrwq_z_f32): Likewise.
6491 (__arm_vldrhq_z_f16): Likewise.
6492 (__arm_vldrhq_f16): Likewise.
6493 (vld1q): Define polymorphic variant.
6494 (vldrhq_gather_offset): Likewise.
6495 (vldrhq_gather_offset_z): Likewise.
6496 (vldrhq_gather_shifted_offset): Likewise.
6497 (vldrhq_gather_shifted_offset_z): Likewise.
6498 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
6502 (LDRGU_Z): Likewise.
6504 (LDRGS_Z): Likewise.
6506 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
6507 (V_sz_elem1): Likewise.
6508 (VLD1Q): Define iterator.
6509 (VLDRHGOQ): Likewise.
6510 (VLDRHGSOQ): Likewise.
6513 (mve_vldrhq_fv8hf): Define RTL pattern.
6514 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
6515 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
6516 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
6517 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
6518 (mve_vldrhq_<supf><mode>): Likewise.
6519 (mve_vldrhq_z_fv8hf): Likewise.
6520 (mve_vldrhq_z_<supf><mode>): Likewise.
6521 (mve_vldrwq_fv4sf): Likewise.
6522 (mve_vldrwq_<supf>v4si): Likewise.
6523 (mve_vldrwq_z_fv4sf): Likewise.
6524 (mve_vldrwq_z_<supf>v4si): Likewise.
6525 (mve_vld1q_f<mode>): Define RTL expand pattern.
6526 (mve_vld1q_<supf><mode>): Likewise.
6528 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6529 Mihail Ionescu <mihail.ionescu@arm.com>
6530 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6532 * config/arm/arm_mve.h (vld1q_s8): Define macro.
6533 (vld1q_s32): Likewise.
6534 (vld1q_s16): Likewise.
6535 (vld1q_u8): Likewise.
6536 (vld1q_u32): Likewise.
6537 (vld1q_u16): Likewise.
6538 (vldrhq_gather_offset_s32): Likewise.
6539 (vldrhq_gather_offset_s16): Likewise.
6540 (vldrhq_gather_offset_u32): Likewise.
6541 (vldrhq_gather_offset_u16): Likewise.
6542 (vldrhq_gather_offset_z_s32): Likewise.
6543 (vldrhq_gather_offset_z_s16): Likewise.
6544 (vldrhq_gather_offset_z_u32): Likewise.
6545 (vldrhq_gather_offset_z_u16): Likewise.
6546 (vldrhq_gather_shifted_offset_s32): Likewise.
6547 (vldrhq_gather_shifted_offset_s16): Likewise.
6548 (vldrhq_gather_shifted_offset_u32): Likewise.
6549 (vldrhq_gather_shifted_offset_u16): Likewise.
6550 (vldrhq_gather_shifted_offset_z_s32): Likewise.
6551 (vldrhq_gather_shifted_offset_z_s16): Likewise.
6552 (vldrhq_gather_shifted_offset_z_u32): Likewise.
6553 (vldrhq_gather_shifted_offset_z_u16): Likewise.
6554 (vldrhq_s32): Likewise.
6555 (vldrhq_s16): Likewise.
6556 (vldrhq_u32): Likewise.
6557 (vldrhq_u16): Likewise.
6558 (vldrhq_z_s32): Likewise.
6559 (vldrhq_z_s16): Likewise.
6560 (vldrhq_z_u32): Likewise.
6561 (vldrhq_z_u16): Likewise.
6562 (vldrwq_s32): Likewise.
6563 (vldrwq_u32): Likewise.
6564 (vldrwq_z_s32): Likewise.
6565 (vldrwq_z_u32): Likewise.
6566 (vld1q_f32): Likewise.
6567 (vld1q_f16): Likewise.
6568 (vldrhq_f16): Likewise.
6569 (vldrhq_z_f16): Likewise.
6570 (vldrwq_f32): Likewise.
6571 (vldrwq_z_f32): Likewise.
6572 (__arm_vld1q_s8): Define intrinsic.
6573 (__arm_vld1q_s32): Likewise.
6574 (__arm_vld1q_s16): Likewise.
6575 (__arm_vld1q_u8): Likewise.
6576 (__arm_vld1q_u32): Likewise.
6577 (__arm_vld1q_u16): Likewise.
6578 (__arm_vldrhq_gather_offset_s32): Likewise.
6579 (__arm_vldrhq_gather_offset_s16): Likewise.
6580 (__arm_vldrhq_gather_offset_u32): Likewise.
6581 (__arm_vldrhq_gather_offset_u16): Likewise.
6582 (__arm_vldrhq_gather_offset_z_s32): Likewise.
6583 (__arm_vldrhq_gather_offset_z_s16): Likewise.
6584 (__arm_vldrhq_gather_offset_z_u32): Likewise.
6585 (__arm_vldrhq_gather_offset_z_u16): Likewise.
6586 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
6587 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
6588 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
6589 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
6590 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
6591 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
6592 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
6593 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
6594 (__arm_vldrhq_s32): Likewise.
6595 (__arm_vldrhq_s16): Likewise.
6596 (__arm_vldrhq_u32): Likewise.
6597 (__arm_vldrhq_u16): Likewise.
6598 (__arm_vldrhq_z_s32): Likewise.
6599 (__arm_vldrhq_z_s16): Likewise.
6600 (__arm_vldrhq_z_u32): Likewise.
6601 (__arm_vldrhq_z_u16): Likewise.
6602 (__arm_vldrwq_s32): Likewise.
6603 (__arm_vldrwq_u32): Likewise.
6604 (__arm_vldrwq_z_s32): Likewise.
6605 (__arm_vldrwq_z_u32): Likewise.
6606 (__arm_vld1q_f32): Likewise.
6607 (__arm_vld1q_f16): Likewise.
6608 (__arm_vldrwq_f32): Likewise.
6609 (__arm_vldrwq_z_f32): Likewise.
6610 (__arm_vldrhq_z_f16): Likewise.
6611 (__arm_vldrhq_f16): Likewise.
6612 (vld1q): Define polymorphic variant.
6613 (vldrhq_gather_offset): Likewise.
6614 (vldrhq_gather_offset_z): Likewise.
6615 (vldrhq_gather_shifted_offset): Likewise.
6616 (vldrhq_gather_shifted_offset_z): Likewise.
6617 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
6621 (LDRGU_Z): Likewise.
6623 (LDRGS_Z): Likewise.
6625 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
6626 (V_sz_elem1): Likewise.
6627 (VLD1Q): Define iterator.
6628 (VLDRHGOQ): Likewise.
6629 (VLDRHGSOQ): Likewise.
6632 (mve_vldrhq_fv8hf): Define RTL pattern.
6633 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
6634 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
6635 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
6636 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
6637 (mve_vldrhq_<supf><mode>): Likewise.
6638 (mve_vldrhq_z_fv8hf): Likewise.
6639 (mve_vldrhq_z_<supf><mode>): Likewise.
6640 (mve_vldrwq_fv4sf): Likewise.
6641 (mve_vldrwq_<supf>v4si): Likewise.
6642 (mve_vldrwq_z_fv4sf): Likewise.
6643 (mve_vldrwq_z_<supf>v4si): Likewise.
6644 (mve_vld1q_f<mode>): Define RTL expand pattern.
6645 (mve_vld1q_<supf><mode>): Likewise.
6647 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6648 Mihail Ionescu <mihail.ionescu@arm.com>
6649 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6651 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
6653 (LDRGBU_Z_QUALIFIERS): Likewise.
6654 (LDRGS_Z_QUALIFIERS): Likewise.
6655 (LDRGU_Z_QUALIFIERS): Likewise.
6656 (LDRS_Z_QUALIFIERS): Likewise.
6657 (LDRU_Z_QUALIFIERS): Likewise.
6658 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro.
6659 (vldrbq_gather_offset_z_u8): Likewise.
6660 (vldrbq_gather_offset_z_s32): Likewise.
6661 (vldrbq_gather_offset_z_u16): Likewise.
6662 (vldrbq_gather_offset_z_u32): Likewise.
6663 (vldrbq_gather_offset_z_s8): Likewise.
6664 (vldrbq_z_s16): Likewise.
6665 (vldrbq_z_u8): Likewise.
6666 (vldrbq_z_s8): Likewise.
6667 (vldrbq_z_s32): Likewise.
6668 (vldrbq_z_u16): Likewise.
6669 (vldrbq_z_u32): Likewise.
6670 (vldrwq_gather_base_z_u32): Likewise.
6671 (vldrwq_gather_base_z_s32): Likewise.
6672 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic.
6673 (__arm_vldrbq_gather_offset_z_s32): Likewise.
6674 (__arm_vldrbq_gather_offset_z_s16): Likewise.
6675 (__arm_vldrbq_gather_offset_z_u8): Likewise.
6676 (__arm_vldrbq_gather_offset_z_u32): Likewise.
6677 (__arm_vldrbq_gather_offset_z_u16): Likewise.
6678 (__arm_vldrbq_z_s8): Likewise.
6679 (__arm_vldrbq_z_s32): Likewise.
6680 (__arm_vldrbq_z_s16): Likewise.
6681 (__arm_vldrbq_z_u8): Likewise.
6682 (__arm_vldrbq_z_u32): Likewise.
6683 (__arm_vldrbq_z_u16): Likewise.
6684 (__arm_vldrwq_gather_base_z_s32): Likewise.
6685 (__arm_vldrwq_gather_base_z_u32): Likewise.
6686 (vldrbq_gather_offset_z): Define polymorphic variant.
6687 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin
6689 (LDRGBU_Z_QUALIFIERS): Likewise.
6690 (LDRGS_Z_QUALIFIERS): Likewise.
6691 (LDRGU_Z_QUALIFIERS): Likewise.
6692 (LDRS_Z_QUALIFIERS): Likewise.
6693 (LDRU_Z_QUALIFIERS): Likewise.
6694 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define
6696 (mve_vldrbq_z_<supf><mode>): Likewise.
6697 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
6699 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6700 Mihail Ionescu <mihail.ionescu@arm.com>
6701 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6703 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin
6705 (STRU_P_QUALIFIERS): Likewise.
6706 (STRSU_P_QUALIFIERS): Likewise.
6707 (STRSS_P_QUALIFIERS): Likewise.
6708 (STRSBS_P_QUALIFIERS): Likewise.
6709 (STRSBU_P_QUALIFIERS): Likewise.
6710 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro.
6711 (vstrbq_p_s32): Likewise.
6712 (vstrbq_p_s16): Likewise.
6713 (vstrbq_p_u8): Likewise.
6714 (vstrbq_p_u32): Likewise.
6715 (vstrbq_p_u16): Likewise.
6716 (vstrbq_scatter_offset_p_s8): Likewise.
6717 (vstrbq_scatter_offset_p_s32): Likewise.
6718 (vstrbq_scatter_offset_p_s16): Likewise.
6719 (vstrbq_scatter_offset_p_u8): Likewise.
6720 (vstrbq_scatter_offset_p_u32): Likewise.
6721 (vstrbq_scatter_offset_p_u16): Likewise.
6722 (vstrwq_scatter_base_p_s32): Likewise.
6723 (vstrwq_scatter_base_p_u32): Likewise.
6724 (__arm_vstrbq_p_s8): Define intrinsic.
6725 (__arm_vstrbq_p_s32): Likewise.
6726 (__arm_vstrbq_p_s16): Likewise.
6727 (__arm_vstrbq_p_u8): Likewise.
6728 (__arm_vstrbq_p_u32): Likewise.
6729 (__arm_vstrbq_p_u16): Likewise.
6730 (__arm_vstrbq_scatter_offset_p_s8): Likewise.
6731 (__arm_vstrbq_scatter_offset_p_s32): Likewise.
6732 (__arm_vstrbq_scatter_offset_p_s16): Likewise.
6733 (__arm_vstrbq_scatter_offset_p_u8): Likewise.
6734 (__arm_vstrbq_scatter_offset_p_u32): Likewise.
6735 (__arm_vstrbq_scatter_offset_p_u16): Likewise.
6736 (__arm_vstrwq_scatter_base_p_s32): Likewise.
6737 (__arm_vstrwq_scatter_base_p_u32): Likewise.
6738 (vstrbq_p): Define polymorphic variant.
6739 (vstrbq_scatter_offset_p): Likewise.
6740 (vstrwq_scatter_base_p): Likewise.
6741 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin
6743 (STRU_P_QUALIFIERS): Likewise.
6744 (STRSU_P_QUALIFIERS): Likewise.
6745 (STRSS_P_QUALIFIERS): Likewise.
6746 (STRSBS_P_QUALIFIERS): Likewise.
6747 (STRSBU_P_QUALIFIERS): Likewise.
6748 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define
6750 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
6751 (mve_vstrbq_p_<supf><mode>): Likewise.
6753 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6754 Mihail Ionescu <mihail.ionescu@arm.com>
6755 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6757 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin
6759 (LDRGS_QUALIFIERS): Likewise.
6760 (LDRS_QUALIFIERS): Likewise.
6761 (LDRU_QUALIFIERS): Likewise.
6762 (LDRGBS_QUALIFIERS): Likewise.
6763 (LDRGBU_QUALIFIERS): Likewise.
6764 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro.
6765 (vldrbq_gather_offset_s8): Likewise.
6766 (vldrbq_s8): Likewise.
6767 (vldrbq_u8): Likewise.
6768 (vldrbq_gather_offset_u16): Likewise.
6769 (vldrbq_gather_offset_s16): Likewise.
6770 (vldrbq_s16): Likewise.
6771 (vldrbq_u16): Likewise.
6772 (vldrbq_gather_offset_u32): Likewise.
6773 (vldrbq_gather_offset_s32): Likewise.
6774 (vldrbq_s32): Likewise.
6775 (vldrbq_u32): Likewise.
6776 (vldrwq_gather_base_s32): Likewise.
6777 (vldrwq_gather_base_u32): Likewise.
6778 (__arm_vldrbq_gather_offset_u8): Define intrinsic.
6779 (__arm_vldrbq_gather_offset_s8): Likewise.
6780 (__arm_vldrbq_s8): Likewise.
6781 (__arm_vldrbq_u8): Likewise.
6782 (__arm_vldrbq_gather_offset_u16): Likewise.
6783 (__arm_vldrbq_gather_offset_s16): Likewise.
6784 (__arm_vldrbq_s16): Likewise.
6785 (__arm_vldrbq_u16): Likewise.
6786 (__arm_vldrbq_gather_offset_u32): Likewise.
6787 (__arm_vldrbq_gather_offset_s32): Likewise.
6788 (__arm_vldrbq_s32): Likewise.
6789 (__arm_vldrbq_u32): Likewise.
6790 (__arm_vldrwq_gather_base_s32): Likewise.
6791 (__arm_vldrwq_gather_base_u32): Likewise.
6792 (vldrbq_gather_offset): Define polymorphic variant.
6793 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin
6795 (LDRGS_QUALIFIERS): Likewise.
6796 (LDRS_QUALIFIERS): Likewise.
6797 (LDRU_QUALIFIERS): Likewise.
6798 (LDRGBS_QUALIFIERS): Likewise.
6799 (LDRGBU_QUALIFIERS): Likewise.
6800 * config/arm/mve.md (VLDRBGOQ): Define iterator.
6802 (VLDRWGBQ): Likewise.
6803 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern.
6804 (mve_vldrbq_<supf><mode>): Likewise.
6805 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
6807 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6808 Mihail Ionescu <mihail.ionescu@arm.com>
6809 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6811 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier.
6812 (STRU_QUALIFIERS): Likewise.
6813 (STRSS_QUALIFIERS): Likewise.
6814 (STRSU_QUALIFIERS): Likewise.
6815 (STRSBS_QUALIFIERS): Likewise.
6816 (STRSBU_QUALIFIERS): Likewise.
6817 * config/arm/arm_mve.h (vstrbq_s8): Define macro.
6818 (vstrbq_u8): Likewise.
6819 (vstrbq_u16): Likewise.
6820 (vstrbq_scatter_offset_s8): Likewise.
6821 (vstrbq_scatter_offset_u8): Likewise.
6822 (vstrbq_scatter_offset_u16): Likewise.
6823 (vstrbq_s16): Likewise.
6824 (vstrbq_u32): Likewise.
6825 (vstrbq_scatter_offset_s16): Likewise.
6826 (vstrbq_scatter_offset_u32): Likewise.
6827 (vstrbq_s32): Likewise.
6828 (vstrbq_scatter_offset_s32): Likewise.
6829 (vstrwq_scatter_base_s32): Likewise.
6830 (vstrwq_scatter_base_u32): Likewise.
6831 (__arm_vstrbq_scatter_offset_s8): Define intrinsic.
6832 (__arm_vstrbq_scatter_offset_s32): Likewise.
6833 (__arm_vstrbq_scatter_offset_s16): Likewise.
6834 (__arm_vstrbq_scatter_offset_u8): Likewise.
6835 (__arm_vstrbq_scatter_offset_u32): Likewise.
6836 (__arm_vstrbq_scatter_offset_u16): Likewise.
6837 (__arm_vstrbq_s8): Likewise.
6838 (__arm_vstrbq_s32): Likewise.
6839 (__arm_vstrbq_s16): Likewise.
6840 (__arm_vstrbq_u8): Likewise.
6841 (__arm_vstrbq_u32): Likewise.
6842 (__arm_vstrbq_u16): Likewise.
6843 (__arm_vstrwq_scatter_base_s32): Likewise.
6844 (__arm_vstrwq_scatter_base_u32): Likewise.
6845 (vstrbq): Define polymorphic variant.
6846 (vstrbq_scatter_offset): Likewise.
6847 (vstrwq_scatter_base): Likewise.
6848 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin
6850 (STRU_QUALIFIERS): Likewise.
6851 (STRSS_QUALIFIERS): Likewise.
6852 (STRSU_QUALIFIERS): Likewise.
6853 (STRSBS_QUALIFIERS): Likewise.
6854 (STRSBU_QUALIFIERS): Likewise.
6855 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator.
6856 (VSTRWSBQ): Define iterators.
6857 (VSTRBSOQ): Likewise.
6859 (mve_vstrbq_<supf><mode>): Define RTL pattern.
6860 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise.
6861 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
6863 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6864 Mihail Ionescu <mihail.ionescu@arm.com>
6865 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6867 * config/arm/arm_mve.h (vabdq_m_f32): Define macro.
6868 (vabdq_m_f16): Likewise.
6869 (vaddq_m_f32): Likewise.
6870 (vaddq_m_f16): Likewise.
6871 (vaddq_m_n_f32): Likewise.
6872 (vaddq_m_n_f16): Likewise.
6873 (vandq_m_f32): Likewise.
6874 (vandq_m_f16): Likewise.
6875 (vbicq_m_f32): Likewise.
6876 (vbicq_m_f16): Likewise.
6877 (vbrsrq_m_n_f32): Likewise.
6878 (vbrsrq_m_n_f16): Likewise.
6879 (vcaddq_rot270_m_f32): Likewise.
6880 (vcaddq_rot270_m_f16): Likewise.
6881 (vcaddq_rot90_m_f32): Likewise.
6882 (vcaddq_rot90_m_f16): Likewise.
6883 (vcmlaq_m_f32): Likewise.
6884 (vcmlaq_m_f16): Likewise.
6885 (vcmlaq_rot180_m_f32): Likewise.
6886 (vcmlaq_rot180_m_f16): Likewise.
6887 (vcmlaq_rot270_m_f32): Likewise.
6888 (vcmlaq_rot270_m_f16): Likewise.
6889 (vcmlaq_rot90_m_f32): Likewise.
6890 (vcmlaq_rot90_m_f16): Likewise.
6891 (vcmulq_m_f32): Likewise.
6892 (vcmulq_m_f16): Likewise.
6893 (vcmulq_rot180_m_f32): Likewise.
6894 (vcmulq_rot180_m_f16): Likewise.
6895 (vcmulq_rot270_m_f32): Likewise.
6896 (vcmulq_rot270_m_f16): Likewise.
6897 (vcmulq_rot90_m_f32): Likewise.
6898 (vcmulq_rot90_m_f16): Likewise.
6899 (vcvtq_m_n_s32_f32): Likewise.
6900 (vcvtq_m_n_s16_f16): Likewise.
6901 (vcvtq_m_n_u32_f32): Likewise.
6902 (vcvtq_m_n_u16_f16): Likewise.
6903 (veorq_m_f32): Likewise.
6904 (veorq_m_f16): Likewise.
6905 (vfmaq_m_f32): Likewise.
6906 (vfmaq_m_f16): Likewise.
6907 (vfmaq_m_n_f32): Likewise.
6908 (vfmaq_m_n_f16): Likewise.
6909 (vfmasq_m_n_f32): Likewise.
6910 (vfmasq_m_n_f16): Likewise.
6911 (vfmsq_m_f32): Likewise.
6912 (vfmsq_m_f16): Likewise.
6913 (vmaxnmq_m_f32): Likewise.
6914 (vmaxnmq_m_f16): Likewise.
6915 (vminnmq_m_f32): Likewise.
6916 (vminnmq_m_f16): Likewise.
6917 (vmulq_m_f32): Likewise.
6918 (vmulq_m_f16): Likewise.
6919 (vmulq_m_n_f32): Likewise.
6920 (vmulq_m_n_f16): Likewise.
6921 (vornq_m_f32): Likewise.
6922 (vornq_m_f16): Likewise.
6923 (vorrq_m_f32): Likewise.
6924 (vorrq_m_f16): Likewise.
6925 (vsubq_m_f32): Likewise.
6926 (vsubq_m_f16): Likewise.
6927 (vsubq_m_n_f32): Likewise.
6928 (vsubq_m_n_f16): Likewise.
6929 (__attribute__): Likewise.
6930 (__arm_vabdq_m_f32): Likewise.
6931 (__arm_vabdq_m_f16): Likewise.
6932 (__arm_vaddq_m_f32): Likewise.
6933 (__arm_vaddq_m_f16): Likewise.
6934 (__arm_vaddq_m_n_f32): Likewise.
6935 (__arm_vaddq_m_n_f16): Likewise.
6936 (__arm_vandq_m_f32): Likewise.
6937 (__arm_vandq_m_f16): Likewise.
6938 (__arm_vbicq_m_f32): Likewise.
6939 (__arm_vbicq_m_f16): Likewise.
6940 (__arm_vbrsrq_m_n_f32): Likewise.
6941 (__arm_vbrsrq_m_n_f16): Likewise.
6942 (__arm_vcaddq_rot270_m_f32): Likewise.
6943 (__arm_vcaddq_rot270_m_f16): Likewise.
6944 (__arm_vcaddq_rot90_m_f32): Likewise.
6945 (__arm_vcaddq_rot90_m_f16): Likewise.
6946 (__arm_vcmlaq_m_f32): Likewise.
6947 (__arm_vcmlaq_m_f16): Likewise.
6948 (__arm_vcmlaq_rot180_m_f32): Likewise.
6949 (__arm_vcmlaq_rot180_m_f16): Likewise.
6950 (__arm_vcmlaq_rot270_m_f32): Likewise.
6951 (__arm_vcmlaq_rot270_m_f16): Likewise.
6952 (__arm_vcmlaq_rot90_m_f32): Likewise.
6953 (__arm_vcmlaq_rot90_m_f16): Likewise.
6954 (__arm_vcmulq_m_f32): Likewise.
6955 (__arm_vcmulq_m_f16): Likewise.
6956 (__arm_vcmulq_rot180_m_f32): Define intrinsic.
6957 (__arm_vcmulq_rot180_m_f16): Likewise.
6958 (__arm_vcmulq_rot270_m_f32): Likewise.
6959 (__arm_vcmulq_rot270_m_f16): Likewise.
6960 (__arm_vcmulq_rot90_m_f32): Likewise.
6961 (__arm_vcmulq_rot90_m_f16): Likewise.
6962 (__arm_vcvtq_m_n_s32_f32): Likewise.
6963 (__arm_vcvtq_m_n_s16_f16): Likewise.
6964 (__arm_vcvtq_m_n_u32_f32): Likewise.
6965 (__arm_vcvtq_m_n_u16_f16): Likewise.
6966 (__arm_veorq_m_f32): Likewise.
6967 (__arm_veorq_m_f16): Likewise.
6968 (__arm_vfmaq_m_f32): Likewise.
6969 (__arm_vfmaq_m_f16): Likewise.
6970 (__arm_vfmaq_m_n_f32): Likewise.
6971 (__arm_vfmaq_m_n_f16): Likewise.
6972 (__arm_vfmasq_m_n_f32): Likewise.
6973 (__arm_vfmasq_m_n_f16): Likewise.
6974 (__arm_vfmsq_m_f32): Likewise.
6975 (__arm_vfmsq_m_f16): Likewise.
6976 (__arm_vmaxnmq_m_f32): Likewise.
6977 (__arm_vmaxnmq_m_f16): Likewise.
6978 (__arm_vminnmq_m_f32): Likewise.
6979 (__arm_vminnmq_m_f16): Likewise.
6980 (__arm_vmulq_m_f32): Likewise.
6981 (__arm_vmulq_m_f16): Likewise.
6982 (__arm_vmulq_m_n_f32): Likewise.
6983 (__arm_vmulq_m_n_f16): Likewise.
6984 (__arm_vornq_m_f32): Likewise.
6985 (__arm_vornq_m_f16): Likewise.
6986 (__arm_vorrq_m_f32): Likewise.
6987 (__arm_vorrq_m_f16): Likewise.
6988 (__arm_vsubq_m_f32): Likewise.
6989 (__arm_vsubq_m_f16): Likewise.
6990 (__arm_vsubq_m_n_f32): Likewise.
6991 (__arm_vsubq_m_n_f16): Likewise.
6992 (vabdq_m): Define polymorphic variant.
6993 (vaddq_m): Likewise.
6994 (vaddq_m_n): Likewise.
6995 (vandq_m): Likewise.
6996 (vbicq_m): Likewise.
6997 (vbrsrq_m_n): Likewise.
6998 (vcaddq_rot270_m): Likewise.
6999 (vcaddq_rot90_m): Likewise.
7000 (vcmlaq_m): Likewise.
7001 (vcmlaq_rot180_m): Likewise.
7002 (vcmlaq_rot270_m): Likewise.
7003 (vcmlaq_rot90_m): Likewise.
7004 (vcmulq_m): Likewise.
7005 (vcmulq_rot180_m): Likewise.
7006 (vcmulq_rot270_m): Likewise.
7007 (vcmulq_rot90_m): Likewise.
7008 (veorq_m): Likewise.
7009 (vfmaq_m): Likewise.
7010 (vfmaq_m_n): Likewise.
7011 (vfmasq_m_n): Likewise.
7012 (vfmsq_m): Likewise.
7013 (vmaxnmq_m): Likewise.
7014 (vminnmq_m): Likewise.
7015 (vmulq_m): Likewise.
7016 (vmulq_m_n): Likewise.
7017 (vornq_m): Likewise.
7018 (vsubq_m): Likewise.
7019 (vsubq_m_n): Likewise.
7020 (vorrq_m): Likewise.
7021 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7023 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7024 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
7025 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern.
7026 (mve_vaddq_m_f<mode>): Likewise.
7027 (mve_vaddq_m_n_f<mode>): Likewise.
7028 (mve_vandq_m_f<mode>): Likewise.
7029 (mve_vbicq_m_f<mode>): Likewise.
7030 (mve_vbrsrq_m_n_f<mode>): Likewise.
7031 (mve_vcaddq_rot270_m_f<mode>): Likewise.
7032 (mve_vcaddq_rot90_m_f<mode>): Likewise.
7033 (mve_vcmlaq_m_f<mode>): Likewise.
7034 (mve_vcmlaq_rot180_m_f<mode>): Likewise.
7035 (mve_vcmlaq_rot270_m_f<mode>): Likewise.
7036 (mve_vcmlaq_rot90_m_f<mode>): Likewise.
7037 (mve_vcmulq_m_f<mode>): Likewise.
7038 (mve_vcmulq_rot180_m_f<mode>): Likewise.
7039 (mve_vcmulq_rot270_m_f<mode>): Likewise.
7040 (mve_vcmulq_rot90_m_f<mode>): Likewise.
7041 (mve_veorq_m_f<mode>): Likewise.
7042 (mve_vfmaq_m_f<mode>): Likewise.
7043 (mve_vfmaq_m_n_f<mode>): Likewise.
7044 (mve_vfmasq_m_n_f<mode>): Likewise.
7045 (mve_vfmsq_m_f<mode>): Likewise.
7046 (mve_vmaxnmq_m_f<mode>): Likewise.
7047 (mve_vminnmq_m_f<mode>): Likewise.
7048 (mve_vmulq_m_f<mode>): Likewise.
7049 (mve_vmulq_m_n_f<mode>): Likewise.
7050 (mve_vornq_m_f<mode>): Likewise.
7051 (mve_vorrq_m_f<mode>): Likewise.
7052 (mve_vsubq_m_f<mode>): Likewise.
7053 (mve_vsubq_m_n_f<mode>): Likewise.
7055 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7056 Mihail Ionescu <mihail.ionescu@arm.com>
7057 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7059 * config/arm/arm-protos.h (arm_mve_immediate_check):
7060 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check
7061 mode and interger value.
7062 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
7063 (vmlaldavaq_p_s16): Likewise.
7064 (vmlaldavaq_p_u32): Likewise.
7065 (vmlaldavaq_p_u16): Likewise.
7066 (vmlaldavaxq_p_s32): Likewise.
7067 (vmlaldavaxq_p_s16): Likewise.
7068 (vmlaldavaxq_p_u32): Likewise.
7069 (vmlaldavaxq_p_u16): Likewise.
7070 (vmlsldavaq_p_s32): Likewise.
7071 (vmlsldavaq_p_s16): Likewise.
7072 (vmlsldavaxq_p_s32): Likewise.
7073 (vmlsldavaxq_p_s16): Likewise.
7074 (vmullbq_poly_m_p8): Likewise.
7075 (vmullbq_poly_m_p16): Likewise.
7076 (vmulltq_poly_m_p8): Likewise.
7077 (vmulltq_poly_m_p16): Likewise.
7078 (vqdmullbq_m_n_s32): Likewise.
7079 (vqdmullbq_m_n_s16): Likewise.
7080 (vqdmullbq_m_s32): Likewise.
7081 (vqdmullbq_m_s16): Likewise.
7082 (vqdmulltq_m_n_s32): Likewise.
7083 (vqdmulltq_m_n_s16): Likewise.
7084 (vqdmulltq_m_s32): Likewise.
7085 (vqdmulltq_m_s16): Likewise.
7086 (vqrshrnbq_m_n_s32): Likewise.
7087 (vqrshrnbq_m_n_s16): Likewise.
7088 (vqrshrnbq_m_n_u32): Likewise.
7089 (vqrshrnbq_m_n_u16): Likewise.
7090 (vqrshrntq_m_n_s32): Likewise.
7091 (vqrshrntq_m_n_s16): Likewise.
7092 (vqrshrntq_m_n_u32): Likewise.
7093 (vqrshrntq_m_n_u16): Likewise.
7094 (vqrshrunbq_m_n_s32): Likewise.
7095 (vqrshrunbq_m_n_s16): Likewise.
7096 (vqrshruntq_m_n_s32): Likewise.
7097 (vqrshruntq_m_n_s16): Likewise.
7098 (vqshrnbq_m_n_s32): Likewise.
7099 (vqshrnbq_m_n_s16): Likewise.
7100 (vqshrnbq_m_n_u32): Likewise.
7101 (vqshrnbq_m_n_u16): Likewise.
7102 (vqshrntq_m_n_s32): Likewise.
7103 (vqshrntq_m_n_s16): Likewise.
7104 (vqshrntq_m_n_u32): Likewise.
7105 (vqshrntq_m_n_u16): Likewise.
7106 (vqshrunbq_m_n_s32): Likewise.
7107 (vqshrunbq_m_n_s16): Likewise.
7108 (vqshruntq_m_n_s32): Likewise.
7109 (vqshruntq_m_n_s16): Likewise.
7110 (vrmlaldavhaq_p_s32): Likewise.
7111 (vrmlaldavhaq_p_u32): Likewise.
7112 (vrmlaldavhaxq_p_s32): Likewise.
7113 (vrmlsldavhaq_p_s32): Likewise.
7114 (vrmlsldavhaxq_p_s32): Likewise.
7115 (vrshrnbq_m_n_s32): Likewise.
7116 (vrshrnbq_m_n_s16): Likewise.
7117 (vrshrnbq_m_n_u32): Likewise.
7118 (vrshrnbq_m_n_u16): Likewise.
7119 (vrshrntq_m_n_s32): Likewise.
7120 (vrshrntq_m_n_s16): Likewise.
7121 (vrshrntq_m_n_u32): Likewise.
7122 (vrshrntq_m_n_u16): Likewise.
7123 (vshllbq_m_n_s8): Likewise.
7124 (vshllbq_m_n_s16): Likewise.
7125 (vshllbq_m_n_u8): Likewise.
7126 (vshllbq_m_n_u16): Likewise.
7127 (vshlltq_m_n_s8): Likewise.
7128 (vshlltq_m_n_s16): Likewise.
7129 (vshlltq_m_n_u8): Likewise.
7130 (vshlltq_m_n_u16): Likewise.
7131 (vshrnbq_m_n_s32): Likewise.
7132 (vshrnbq_m_n_s16): Likewise.
7133 (vshrnbq_m_n_u32): Likewise.
7134 (vshrnbq_m_n_u16): Likewise.
7135 (vshrntq_m_n_s32): Likewise.
7136 (vshrntq_m_n_s16): Likewise.
7137 (vshrntq_m_n_u32): Likewise.
7138 (vshrntq_m_n_u16): Likewise.
7139 (__arm_vmlaldavaq_p_s32): Define intrinsic.
7140 (__arm_vmlaldavaq_p_s16): Likewise.
7141 (__arm_vmlaldavaq_p_u32): Likewise.
7142 (__arm_vmlaldavaq_p_u16): Likewise.
7143 (__arm_vmlaldavaxq_p_s32): Likewise.
7144 (__arm_vmlaldavaxq_p_s16): Likewise.
7145 (__arm_vmlaldavaxq_p_u32): Likewise.
7146 (__arm_vmlaldavaxq_p_u16): Likewise.
7147 (__arm_vmlsldavaq_p_s32): Likewise.
7148 (__arm_vmlsldavaq_p_s16): Likewise.
7149 (__arm_vmlsldavaxq_p_s32): Likewise.
7150 (__arm_vmlsldavaxq_p_s16): Likewise.
7151 (__arm_vmullbq_poly_m_p8): Likewise.
7152 (__arm_vmullbq_poly_m_p16): Likewise.
7153 (__arm_vmulltq_poly_m_p8): Likewise.
7154 (__arm_vmulltq_poly_m_p16): Likewise.
7155 (__arm_vqdmullbq_m_n_s32): Likewise.
7156 (__arm_vqdmullbq_m_n_s16): Likewise.
7157 (__arm_vqdmullbq_m_s32): Likewise.
7158 (__arm_vqdmullbq_m_s16): Likewise.
7159 (__arm_vqdmulltq_m_n_s32): Likewise.
7160 (__arm_vqdmulltq_m_n_s16): Likewise.
7161 (__arm_vqdmulltq_m_s32): Likewise.
7162 (__arm_vqdmulltq_m_s16): Likewise.
7163 (__arm_vqrshrnbq_m_n_s32): Likewise.
7164 (__arm_vqrshrnbq_m_n_s16): Likewise.
7165 (__arm_vqrshrnbq_m_n_u32): Likewise.
7166 (__arm_vqrshrnbq_m_n_u16): Likewise.
7167 (__arm_vqrshrntq_m_n_s32): Likewise.
7168 (__arm_vqrshrntq_m_n_s16): Likewise.
7169 (__arm_vqrshrntq_m_n_u32): Likewise.
7170 (__arm_vqrshrntq_m_n_u16): Likewise.
7171 (__arm_vqrshrunbq_m_n_s32): Likewise.
7172 (__arm_vqrshrunbq_m_n_s16): Likewise.
7173 (__arm_vqrshruntq_m_n_s32): Likewise.
7174 (__arm_vqrshruntq_m_n_s16): Likewise.
7175 (__arm_vqshrnbq_m_n_s32): Likewise.
7176 (__arm_vqshrnbq_m_n_s16): Likewise.
7177 (__arm_vqshrnbq_m_n_u32): Likewise.
7178 (__arm_vqshrnbq_m_n_u16): Likewise.
7179 (__arm_vqshrntq_m_n_s32): Likewise.
7180 (__arm_vqshrntq_m_n_s16): Likewise.
7181 (__arm_vqshrntq_m_n_u32): Likewise.
7182 (__arm_vqshrntq_m_n_u16): Likewise.
7183 (__arm_vqshrunbq_m_n_s32): Likewise.
7184 (__arm_vqshrunbq_m_n_s16): Likewise.
7185 (__arm_vqshruntq_m_n_s32): Likewise.
7186 (__arm_vqshruntq_m_n_s16): Likewise.
7187 (__arm_vrmlaldavhaq_p_s32): Likewise.
7188 (__arm_vrmlaldavhaq_p_u32): Likewise.
7189 (__arm_vrmlaldavhaxq_p_s32): Likewise.
7190 (__arm_vrmlsldavhaq_p_s32): Likewise.
7191 (__arm_vrmlsldavhaxq_p_s32): Likewise.
7192 (__arm_vrshrnbq_m_n_s32): Likewise.
7193 (__arm_vrshrnbq_m_n_s16): Likewise.
7194 (__arm_vrshrnbq_m_n_u32): Likewise.
7195 (__arm_vrshrnbq_m_n_u16): Likewise.
7196 (__arm_vrshrntq_m_n_s32): Likewise.
7197 (__arm_vrshrntq_m_n_s16): Likewise.
7198 (__arm_vrshrntq_m_n_u32): Likewise.
7199 (__arm_vrshrntq_m_n_u16): Likewise.
7200 (__arm_vshllbq_m_n_s8): Likewise.
7201 (__arm_vshllbq_m_n_s16): Likewise.
7202 (__arm_vshllbq_m_n_u8): Likewise.
7203 (__arm_vshllbq_m_n_u16): Likewise.
7204 (__arm_vshlltq_m_n_s8): Likewise.
7205 (__arm_vshlltq_m_n_s16): Likewise.
7206 (__arm_vshlltq_m_n_u8): Likewise.
7207 (__arm_vshlltq_m_n_u16): Likewise.
7208 (__arm_vshrnbq_m_n_s32): Likewise.
7209 (__arm_vshrnbq_m_n_s16): Likewise.
7210 (__arm_vshrnbq_m_n_u32): Likewise.
7211 (__arm_vshrnbq_m_n_u16): Likewise.
7212 (__arm_vshrntq_m_n_s32): Likewise.
7213 (__arm_vshrntq_m_n_s16): Likewise.
7214 (__arm_vshrntq_m_n_u32): Likewise.
7215 (__arm_vshrntq_m_n_u16): Likewise.
7216 (vmullbq_poly_m): Define polymorphic variant.
7217 (vmulltq_poly_m): Likewise.
7218 (vshllbq_m): Likewise.
7219 (vshrntq_m_n): Likewise.
7220 (vshrnbq_m_n): Likewise.
7221 (vshlltq_m_n): Likewise.
7222 (vshllbq_m_n): Likewise.
7223 (vrshrntq_m_n): Likewise.
7224 (vrshrnbq_m_n): Likewise.
7225 (vqshruntq_m_n): Likewise.
7226 (vqshrunbq_m_n): Likewise.
7227 (vqdmullbq_m_n): Likewise.
7228 (vqdmullbq_m): Likewise.
7229 (vqdmulltq_m_n): Likewise.
7230 (vqdmulltq_m): Likewise.
7231 (vqrshrnbq_m_n): Likewise.
7232 (vqrshrntq_m_n): Likewise.
7233 (vqrshrunbq_m_n): Likewise.
7234 (vqrshruntq_m_n): Likewise.
7235 (vqshrnbq_m_n): Likewise.
7236 (vqshrntq_m_n): Likewise.
7237 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7239 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7240 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
7241 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
7242 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
7243 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
7244 (VMLALDAVAXQ_P): Likewise.
7245 (VQRSHRNBQ_M_N): Likewise.
7246 (VQRSHRNTQ_M_N): Likewise.
7247 (VQSHRNBQ_M_N): Likewise.
7248 (VQSHRNTQ_M_N): Likewise.
7249 (VRSHRNBQ_M_N): Likewise.
7250 (VRSHRNTQ_M_N): Likewise.
7251 (VSHLLBQ_M_N): Likewise.
7252 (VSHLLTQ_M_N): Likewise.
7253 (VSHRNBQ_M_N): Likewise.
7254 (VSHRNTQ_M_N): Likewise.
7255 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
7256 (mve_vmlaldavaxq_p_<supf><mode>): Likewise.
7257 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
7258 (mve_vqrshrntq_m_n_<supf><mode>): Likewise.
7259 (mve_vqshrnbq_m_n_<supf><mode>): Likewise.
7260 (mve_vqshrntq_m_n_<supf><mode>): Likewise.
7261 (mve_vrmlaldavhaq_p_sv4si): Likewise.
7262 (mve_vrshrnbq_m_n_<supf><mode>): Likewise.
7263 (mve_vrshrntq_m_n_<supf><mode>): Likewise.
7264 (mve_vshllbq_m_n_<supf><mode>): Likewise.
7265 (mve_vshlltq_m_n_<supf><mode>): Likewise.
7266 (mve_vshrnbq_m_n_<supf><mode>): Likewise.
7267 (mve_vshrntq_m_n_<supf><mode>): Likewise.
7268 (mve_vmlsldavaq_p_s<mode>): Likewise.
7269 (mve_vmlsldavaxq_p_s<mode>): Likewise.
7270 (mve_vmullbq_poly_m_p<mode>): Likewise.
7271 (mve_vmulltq_poly_m_p<mode>): Likewise.
7272 (mve_vqdmullbq_m_n_s<mode>): Likewise.
7273 (mve_vqdmullbq_m_s<mode>): Likewise.
7274 (mve_vqdmulltq_m_n_s<mode>): Likewise.
7275 (mve_vqdmulltq_m_s<mode>): Likewise.
7276 (mve_vqrshrunbq_m_n_s<mode>): Likewise.
7277 (mve_vqrshruntq_m_n_s<mode>): Likewise.
7278 (mve_vqshrunbq_m_n_s<mode>): Likewise.
7279 (mve_vqshruntq_m_n_s<mode>): Likewise.
7280 (mve_vrmlaldavhaq_p_uv4si): Likewise.
7281 (mve_vrmlaldavhaxq_p_sv4si): Likewise.
7282 (mve_vrmlsldavhaq_p_sv4si): Likewise.
7283 (mve_vrmlsldavhaxq_p_sv4si): Likewise.
7285 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7286 Mihail Ionescu <mihail.ionescu@arm.com>
7287 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7289 * config/arm/arm_mve.h (vabdq_m_s8): Define macro.
7290 (vabdq_m_s32): Likewise.
7291 (vabdq_m_s16): Likewise.
7292 (vabdq_m_u8): Likewise.
7293 (vabdq_m_u32): Likewise.
7294 (vabdq_m_u16): Likewise.
7295 (vaddq_m_n_s8): Likewise.
7296 (vaddq_m_n_s32): Likewise.
7297 (vaddq_m_n_s16): Likewise.
7298 (vaddq_m_n_u8): Likewise.
7299 (vaddq_m_n_u32): Likewise.
7300 (vaddq_m_n_u16): Likewise.
7301 (vaddq_m_s8): Likewise.
7302 (vaddq_m_s32): Likewise.
7303 (vaddq_m_s16): Likewise.
7304 (vaddq_m_u8): Likewise.
7305 (vaddq_m_u32): Likewise.
7306 (vaddq_m_u16): Likewise.
7307 (vandq_m_s8): Likewise.
7308 (vandq_m_s32): Likewise.
7309 (vandq_m_s16): Likewise.
7310 (vandq_m_u8): Likewise.
7311 (vandq_m_u32): Likewise.
7312 (vandq_m_u16): Likewise.
7313 (vbicq_m_s8): Likewise.
7314 (vbicq_m_s32): Likewise.
7315 (vbicq_m_s16): Likewise.
7316 (vbicq_m_u8): Likewise.
7317 (vbicq_m_u32): Likewise.
7318 (vbicq_m_u16): Likewise.
7319 (vbrsrq_m_n_s8): Likewise.
7320 (vbrsrq_m_n_s32): Likewise.
7321 (vbrsrq_m_n_s16): Likewise.
7322 (vbrsrq_m_n_u8): Likewise.
7323 (vbrsrq_m_n_u32): Likewise.
7324 (vbrsrq_m_n_u16): Likewise.
7325 (vcaddq_rot270_m_s8): Likewise.
7326 (vcaddq_rot270_m_s32): Likewise.
7327 (vcaddq_rot270_m_s16): Likewise.
7328 (vcaddq_rot270_m_u8): Likewise.
7329 (vcaddq_rot270_m_u32): Likewise.
7330 (vcaddq_rot270_m_u16): Likewise.
7331 (vcaddq_rot90_m_s8): Likewise.
7332 (vcaddq_rot90_m_s32): Likewise.
7333 (vcaddq_rot90_m_s16): Likewise.
7334 (vcaddq_rot90_m_u8): Likewise.
7335 (vcaddq_rot90_m_u32): Likewise.
7336 (vcaddq_rot90_m_u16): Likewise.
7337 (veorq_m_s8): Likewise.
7338 (veorq_m_s32): Likewise.
7339 (veorq_m_s16): Likewise.
7340 (veorq_m_u8): Likewise.
7341 (veorq_m_u32): Likewise.
7342 (veorq_m_u16): Likewise.
7343 (vhaddq_m_n_s8): Likewise.
7344 (vhaddq_m_n_s32): Likewise.
7345 (vhaddq_m_n_s16): Likewise.
7346 (vhaddq_m_n_u8): Likewise.
7347 (vhaddq_m_n_u32): Likewise.
7348 (vhaddq_m_n_u16): Likewise.
7349 (vhaddq_m_s8): Likewise.
7350 (vhaddq_m_s32): Likewise.
7351 (vhaddq_m_s16): Likewise.
7352 (vhaddq_m_u8): Likewise.
7353 (vhaddq_m_u32): Likewise.
7354 (vhaddq_m_u16): Likewise.
7355 (vhcaddq_rot270_m_s8): Likewise.
7356 (vhcaddq_rot270_m_s32): Likewise.
7357 (vhcaddq_rot270_m_s16): Likewise.
7358 (vhcaddq_rot90_m_s8): Likewise.
7359 (vhcaddq_rot90_m_s32): Likewise.
7360 (vhcaddq_rot90_m_s16): Likewise.
7361 (vhsubq_m_n_s8): Likewise.
7362 (vhsubq_m_n_s32): Likewise.
7363 (vhsubq_m_n_s16): Likewise.
7364 (vhsubq_m_n_u8): Likewise.
7365 (vhsubq_m_n_u32): Likewise.
7366 (vhsubq_m_n_u16): Likewise.
7367 (vhsubq_m_s8): Likewise.
7368 (vhsubq_m_s32): Likewise.
7369 (vhsubq_m_s16): Likewise.
7370 (vhsubq_m_u8): Likewise.
7371 (vhsubq_m_u32): Likewise.
7372 (vhsubq_m_u16): Likewise.
7373 (vmaxq_m_s8): Likewise.
7374 (vmaxq_m_s32): Likewise.
7375 (vmaxq_m_s16): Likewise.
7376 (vmaxq_m_u8): Likewise.
7377 (vmaxq_m_u32): Likewise.
7378 (vmaxq_m_u16): Likewise.
7379 (vminq_m_s8): Likewise.
7380 (vminq_m_s32): Likewise.
7381 (vminq_m_s16): Likewise.
7382 (vminq_m_u8): Likewise.
7383 (vminq_m_u32): Likewise.
7384 (vminq_m_u16): Likewise.
7385 (vmladavaq_p_s8): Likewise.
7386 (vmladavaq_p_s32): Likewise.
7387 (vmladavaq_p_s16): Likewise.
7388 (vmladavaq_p_u8): Likewise.
7389 (vmladavaq_p_u32): Likewise.
7390 (vmladavaq_p_u16): Likewise.
7391 (vmladavaxq_p_s8): Likewise.
7392 (vmladavaxq_p_s32): Likewise.
7393 (vmladavaxq_p_s16): Likewise.
7394 (vmlaq_m_n_s8): Likewise.
7395 (vmlaq_m_n_s32): Likewise.
7396 (vmlaq_m_n_s16): Likewise.
7397 (vmlaq_m_n_u8): Likewise.
7398 (vmlaq_m_n_u32): Likewise.
7399 (vmlaq_m_n_u16): Likewise.
7400 (vmlasq_m_n_s8): Likewise.
7401 (vmlasq_m_n_s32): Likewise.
7402 (vmlasq_m_n_s16): Likewise.
7403 (vmlasq_m_n_u8): Likewise.
7404 (vmlasq_m_n_u32): Likewise.
7405 (vmlasq_m_n_u16): Likewise.
7406 (vmlsdavaq_p_s8): Likewise.
7407 (vmlsdavaq_p_s32): Likewise.
7408 (vmlsdavaq_p_s16): Likewise.
7409 (vmlsdavaxq_p_s8): Likewise.
7410 (vmlsdavaxq_p_s32): Likewise.
7411 (vmlsdavaxq_p_s16): Likewise.
7412 (vmulhq_m_s8): Likewise.
7413 (vmulhq_m_s32): Likewise.
7414 (vmulhq_m_s16): Likewise.
7415 (vmulhq_m_u8): Likewise.
7416 (vmulhq_m_u32): Likewise.
7417 (vmulhq_m_u16): Likewise.
7418 (vmullbq_int_m_s8): Likewise.
7419 (vmullbq_int_m_s32): Likewise.
7420 (vmullbq_int_m_s16): Likewise.
7421 (vmullbq_int_m_u8): Likewise.
7422 (vmullbq_int_m_u32): Likewise.
7423 (vmullbq_int_m_u16): Likewise.
7424 (vmulltq_int_m_s8): Likewise.
7425 (vmulltq_int_m_s32): Likewise.
7426 (vmulltq_int_m_s16): Likewise.
7427 (vmulltq_int_m_u8): Likewise.
7428 (vmulltq_int_m_u32): Likewise.
7429 (vmulltq_int_m_u16): Likewise.
7430 (vmulq_m_n_s8): Likewise.
7431 (vmulq_m_n_s32): Likewise.
7432 (vmulq_m_n_s16): Likewise.
7433 (vmulq_m_n_u8): Likewise.
7434 (vmulq_m_n_u32): Likewise.
7435 (vmulq_m_n_u16): Likewise.
7436 (vmulq_m_s8): Likewise.
7437 (vmulq_m_s32): Likewise.
7438 (vmulq_m_s16): Likewise.
7439 (vmulq_m_u8): Likewise.
7440 (vmulq_m_u32): Likewise.
7441 (vmulq_m_u16): Likewise.
7442 (vornq_m_s8): Likewise.
7443 (vornq_m_s32): Likewise.
7444 (vornq_m_s16): Likewise.
7445 (vornq_m_u8): Likewise.
7446 (vornq_m_u32): Likewise.
7447 (vornq_m_u16): Likewise.
7448 (vorrq_m_s8): Likewise.
7449 (vorrq_m_s32): Likewise.
7450 (vorrq_m_s16): Likewise.
7451 (vorrq_m_u8): Likewise.
7452 (vorrq_m_u32): Likewise.
7453 (vorrq_m_u16): Likewise.
7454 (vqaddq_m_n_s8): Likewise.
7455 (vqaddq_m_n_s32): Likewise.
7456 (vqaddq_m_n_s16): Likewise.
7457 (vqaddq_m_n_u8): Likewise.
7458 (vqaddq_m_n_u32): Likewise.
7459 (vqaddq_m_n_u16): Likewise.
7460 (vqaddq_m_s8): Likewise.
7461 (vqaddq_m_s32): Likewise.
7462 (vqaddq_m_s16): Likewise.
7463 (vqaddq_m_u8): Likewise.
7464 (vqaddq_m_u32): Likewise.
7465 (vqaddq_m_u16): Likewise.
7466 (vqdmladhq_m_s8): Likewise.
7467 (vqdmladhq_m_s32): Likewise.
7468 (vqdmladhq_m_s16): Likewise.
7469 (vqdmladhxq_m_s8): Likewise.
7470 (vqdmladhxq_m_s32): Likewise.
7471 (vqdmladhxq_m_s16): Likewise.
7472 (vqdmlahq_m_n_s8): Likewise.
7473 (vqdmlahq_m_n_s32): Likewise.
7474 (vqdmlahq_m_n_s16): Likewise.
7475 (vqdmlahq_m_n_u8): Likewise.
7476 (vqdmlahq_m_n_u32): Likewise.
7477 (vqdmlahq_m_n_u16): Likewise.
7478 (vqdmlsdhq_m_s8): Likewise.
7479 (vqdmlsdhq_m_s32): Likewise.
7480 (vqdmlsdhq_m_s16): Likewise.
7481 (vqdmlsdhxq_m_s8): Likewise.
7482 (vqdmlsdhxq_m_s32): Likewise.
7483 (vqdmlsdhxq_m_s16): Likewise.
7484 (vqdmulhq_m_n_s8): Likewise.
7485 (vqdmulhq_m_n_s32): Likewise.
7486 (vqdmulhq_m_n_s16): Likewise.
7487 (vqdmulhq_m_s8): Likewise.
7488 (vqdmulhq_m_s32): Likewise.
7489 (vqdmulhq_m_s16): Likewise.
7490 (vqrdmladhq_m_s8): Likewise.
7491 (vqrdmladhq_m_s32): Likewise.
7492 (vqrdmladhq_m_s16): Likewise.
7493 (vqrdmladhxq_m_s8): Likewise.
7494 (vqrdmladhxq_m_s32): Likewise.
7495 (vqrdmladhxq_m_s16): Likewise.
7496 (vqrdmlahq_m_n_s8): Likewise.
7497 (vqrdmlahq_m_n_s32): Likewise.
7498 (vqrdmlahq_m_n_s16): Likewise.
7499 (vqrdmlahq_m_n_u8): Likewise.
7500 (vqrdmlahq_m_n_u32): Likewise.
7501 (vqrdmlahq_m_n_u16): Likewise.
7502 (vqrdmlashq_m_n_s8): Likewise.
7503 (vqrdmlashq_m_n_s32): Likewise.
7504 (vqrdmlashq_m_n_s16): Likewise.
7505 (vqrdmlashq_m_n_u8): Likewise.
7506 (vqrdmlashq_m_n_u32): Likewise.
7507 (vqrdmlashq_m_n_u16): Likewise.
7508 (vqrdmlsdhq_m_s8): Likewise.
7509 (vqrdmlsdhq_m_s32): Likewise.
7510 (vqrdmlsdhq_m_s16): Likewise.
7511 (vqrdmlsdhxq_m_s8): Likewise.
7512 (vqrdmlsdhxq_m_s32): Likewise.
7513 (vqrdmlsdhxq_m_s16): Likewise.
7514 (vqrdmulhq_m_n_s8): Likewise.
7515 (vqrdmulhq_m_n_s32): Likewise.
7516 (vqrdmulhq_m_n_s16): Likewise.
7517 (vqrdmulhq_m_s8): Likewise.
7518 (vqrdmulhq_m_s32): Likewise.
7519 (vqrdmulhq_m_s16): Likewise.
7520 (vqrshlq_m_s8): Likewise.
7521 (vqrshlq_m_s32): Likewise.
7522 (vqrshlq_m_s16): Likewise.
7523 (vqrshlq_m_u8): Likewise.
7524 (vqrshlq_m_u32): Likewise.
7525 (vqrshlq_m_u16): Likewise.
7526 (vqshlq_m_n_s8): Likewise.
7527 (vqshlq_m_n_s32): Likewise.
7528 (vqshlq_m_n_s16): Likewise.
7529 (vqshlq_m_n_u8): Likewise.
7530 (vqshlq_m_n_u32): Likewise.
7531 (vqshlq_m_n_u16): Likewise.
7532 (vqshlq_m_s8): Likewise.
7533 (vqshlq_m_s32): Likewise.
7534 (vqshlq_m_s16): Likewise.
7535 (vqshlq_m_u8): Likewise.
7536 (vqshlq_m_u32): Likewise.
7537 (vqshlq_m_u16): Likewise.
7538 (vqsubq_m_n_s8): Likewise.
7539 (vqsubq_m_n_s32): Likewise.
7540 (vqsubq_m_n_s16): Likewise.
7541 (vqsubq_m_n_u8): Likewise.
7542 (vqsubq_m_n_u32): Likewise.
7543 (vqsubq_m_n_u16): Likewise.
7544 (vqsubq_m_s8): Likewise.
7545 (vqsubq_m_s32): Likewise.
7546 (vqsubq_m_s16): Likewise.
7547 (vqsubq_m_u8): Likewise.
7548 (vqsubq_m_u32): Likewise.
7549 (vqsubq_m_u16): Likewise.
7550 (vrhaddq_m_s8): Likewise.
7551 (vrhaddq_m_s32): Likewise.
7552 (vrhaddq_m_s16): Likewise.
7553 (vrhaddq_m_u8): Likewise.
7554 (vrhaddq_m_u32): Likewise.
7555 (vrhaddq_m_u16): Likewise.
7556 (vrmulhq_m_s8): Likewise.
7557 (vrmulhq_m_s32): Likewise.
7558 (vrmulhq_m_s16): Likewise.
7559 (vrmulhq_m_u8): Likewise.
7560 (vrmulhq_m_u32): Likewise.
7561 (vrmulhq_m_u16): Likewise.
7562 (vrshlq_m_s8): Likewise.
7563 (vrshlq_m_s32): Likewise.
7564 (vrshlq_m_s16): Likewise.
7565 (vrshlq_m_u8): Likewise.
7566 (vrshlq_m_u32): Likewise.
7567 (vrshlq_m_u16): Likewise.
7568 (vrshrq_m_n_s8): Likewise.
7569 (vrshrq_m_n_s32): Likewise.
7570 (vrshrq_m_n_s16): Likewise.
7571 (vrshrq_m_n_u8): Likewise.
7572 (vrshrq_m_n_u32): Likewise.
7573 (vrshrq_m_n_u16): Likewise.
7574 (vshlq_m_n_s8): Likewise.
7575 (vshlq_m_n_s32): Likewise.
7576 (vshlq_m_n_s16): Likewise.
7577 (vshlq_m_n_u8): Likewise.
7578 (vshlq_m_n_u32): Likewise.
7579 (vshlq_m_n_u16): Likewise.
7580 (vshrq_m_n_s8): Likewise.
7581 (vshrq_m_n_s32): Likewise.
7582 (vshrq_m_n_s16): Likewise.
7583 (vshrq_m_n_u8): Likewise.
7584 (vshrq_m_n_u32): Likewise.
7585 (vshrq_m_n_u16): Likewise.
7586 (vsliq_m_n_s8): Likewise.
7587 (vsliq_m_n_s32): Likewise.
7588 (vsliq_m_n_s16): Likewise.
7589 (vsliq_m_n_u8): Likewise.
7590 (vsliq_m_n_u32): Likewise.
7591 (vsliq_m_n_u16): Likewise.
7592 (vsubq_m_n_s8): Likewise.
7593 (vsubq_m_n_s32): Likewise.
7594 (vsubq_m_n_s16): Likewise.
7595 (vsubq_m_n_u8): Likewise.
7596 (vsubq_m_n_u32): Likewise.
7597 (vsubq_m_n_u16): Likewise.
7598 (__arm_vabdq_m_s8): Define intrinsic.
7599 (__arm_vabdq_m_s32): Likewise.
7600 (__arm_vabdq_m_s16): Likewise.
7601 (__arm_vabdq_m_u8): Likewise.
7602 (__arm_vabdq_m_u32): Likewise.
7603 (__arm_vabdq_m_u16): Likewise.
7604 (__arm_vaddq_m_n_s8): Likewise.
7605 (__arm_vaddq_m_n_s32): Likewise.
7606 (__arm_vaddq_m_n_s16): Likewise.
7607 (__arm_vaddq_m_n_u8): Likewise.
7608 (__arm_vaddq_m_n_u32): Likewise.
7609 (__arm_vaddq_m_n_u16): Likewise.
7610 (__arm_vaddq_m_s8): Likewise.
7611 (__arm_vaddq_m_s32): Likewise.
7612 (__arm_vaddq_m_s16): Likewise.
7613 (__arm_vaddq_m_u8): Likewise.
7614 (__arm_vaddq_m_u32): Likewise.
7615 (__arm_vaddq_m_u16): Likewise.
7616 (__arm_vandq_m_s8): Likewise.
7617 (__arm_vandq_m_s32): Likewise.
7618 (__arm_vandq_m_s16): Likewise.
7619 (__arm_vandq_m_u8): Likewise.
7620 (__arm_vandq_m_u32): Likewise.
7621 (__arm_vandq_m_u16): Likewise.
7622 (__arm_vbicq_m_s8): Likewise.
7623 (__arm_vbicq_m_s32): Likewise.
7624 (__arm_vbicq_m_s16): Likewise.
7625 (__arm_vbicq_m_u8): Likewise.
7626 (__arm_vbicq_m_u32): Likewise.
7627 (__arm_vbicq_m_u16): Likewise.
7628 (__arm_vbrsrq_m_n_s8): Likewise.
7629 (__arm_vbrsrq_m_n_s32): Likewise.
7630 (__arm_vbrsrq_m_n_s16): Likewise.
7631 (__arm_vbrsrq_m_n_u8): Likewise.
7632 (__arm_vbrsrq_m_n_u32): Likewise.
7633 (__arm_vbrsrq_m_n_u16): Likewise.
7634 (__arm_vcaddq_rot270_m_s8): Likewise.
7635 (__arm_vcaddq_rot270_m_s32): Likewise.
7636 (__arm_vcaddq_rot270_m_s16): Likewise.
7637 (__arm_vcaddq_rot270_m_u8): Likewise.
7638 (__arm_vcaddq_rot270_m_u32): Likewise.
7639 (__arm_vcaddq_rot270_m_u16): Likewise.
7640 (__arm_vcaddq_rot90_m_s8): Likewise.
7641 (__arm_vcaddq_rot90_m_s32): Likewise.
7642 (__arm_vcaddq_rot90_m_s16): Likewise.
7643 (__arm_vcaddq_rot90_m_u8): Likewise.
7644 (__arm_vcaddq_rot90_m_u32): Likewise.
7645 (__arm_vcaddq_rot90_m_u16): Likewise.
7646 (__arm_veorq_m_s8): Likewise.
7647 (__arm_veorq_m_s32): Likewise.
7648 (__arm_veorq_m_s16): Likewise.
7649 (__arm_veorq_m_u8): Likewise.
7650 (__arm_veorq_m_u32): Likewise.
7651 (__arm_veorq_m_u16): Likewise.
7652 (__arm_vhaddq_m_n_s8): Likewise.
7653 (__arm_vhaddq_m_n_s32): Likewise.
7654 (__arm_vhaddq_m_n_s16): Likewise.
7655 (__arm_vhaddq_m_n_u8): Likewise.
7656 (__arm_vhaddq_m_n_u32): Likewise.
7657 (__arm_vhaddq_m_n_u16): Likewise.
7658 (__arm_vhaddq_m_s8): Likewise.
7659 (__arm_vhaddq_m_s32): Likewise.
7660 (__arm_vhaddq_m_s16): Likewise.
7661 (__arm_vhaddq_m_u8): Likewise.
7662 (__arm_vhaddq_m_u32): Likewise.
7663 (__arm_vhaddq_m_u16): Likewise.
7664 (__arm_vhcaddq_rot270_m_s8): Likewise.
7665 (__arm_vhcaddq_rot270_m_s32): Likewise.
7666 (__arm_vhcaddq_rot270_m_s16): Likewise.
7667 (__arm_vhcaddq_rot90_m_s8): Likewise.
7668 (__arm_vhcaddq_rot90_m_s32): Likewise.
7669 (__arm_vhcaddq_rot90_m_s16): Likewise.
7670 (__arm_vhsubq_m_n_s8): Likewise.
7671 (__arm_vhsubq_m_n_s32): Likewise.
7672 (__arm_vhsubq_m_n_s16): Likewise.
7673 (__arm_vhsubq_m_n_u8): Likewise.
7674 (__arm_vhsubq_m_n_u32): Likewise.
7675 (__arm_vhsubq_m_n_u16): Likewise.
7676 (__arm_vhsubq_m_s8): Likewise.
7677 (__arm_vhsubq_m_s32): Likewise.
7678 (__arm_vhsubq_m_s16): Likewise.
7679 (__arm_vhsubq_m_u8): Likewise.
7680 (__arm_vhsubq_m_u32): Likewise.
7681 (__arm_vhsubq_m_u16): Likewise.
7682 (__arm_vmaxq_m_s8): Likewise.
7683 (__arm_vmaxq_m_s32): Likewise.
7684 (__arm_vmaxq_m_s16): Likewise.
7685 (__arm_vmaxq_m_u8): Likewise.
7686 (__arm_vmaxq_m_u32): Likewise.
7687 (__arm_vmaxq_m_u16): Likewise.
7688 (__arm_vminq_m_s8): Likewise.
7689 (__arm_vminq_m_s32): Likewise.
7690 (__arm_vminq_m_s16): Likewise.
7691 (__arm_vminq_m_u8): Likewise.
7692 (__arm_vminq_m_u32): Likewise.
7693 (__arm_vminq_m_u16): Likewise.
7694 (__arm_vmladavaq_p_s8): Likewise.
7695 (__arm_vmladavaq_p_s32): Likewise.
7696 (__arm_vmladavaq_p_s16): Likewise.
7697 (__arm_vmladavaq_p_u8): Likewise.
7698 (__arm_vmladavaq_p_u32): Likewise.
7699 (__arm_vmladavaq_p_u16): Likewise.
7700 (__arm_vmladavaxq_p_s8): Likewise.
7701 (__arm_vmladavaxq_p_s32): Likewise.
7702 (__arm_vmladavaxq_p_s16): Likewise.
7703 (__arm_vmlaq_m_n_s8): Likewise.
7704 (__arm_vmlaq_m_n_s32): Likewise.
7705 (__arm_vmlaq_m_n_s16): Likewise.
7706 (__arm_vmlaq_m_n_u8): Likewise.
7707 (__arm_vmlaq_m_n_u32): Likewise.
7708 (__arm_vmlaq_m_n_u16): Likewise.
7709 (__arm_vmlasq_m_n_s8): Likewise.
7710 (__arm_vmlasq_m_n_s32): Likewise.
7711 (__arm_vmlasq_m_n_s16): Likewise.
7712 (__arm_vmlasq_m_n_u8): Likewise.
7713 (__arm_vmlasq_m_n_u32): Likewise.
7714 (__arm_vmlasq_m_n_u16): Likewise.
7715 (__arm_vmlsdavaq_p_s8): Likewise.
7716 (__arm_vmlsdavaq_p_s32): Likewise.
7717 (__arm_vmlsdavaq_p_s16): Likewise.
7718 (__arm_vmlsdavaxq_p_s8): Likewise.
7719 (__arm_vmlsdavaxq_p_s32): Likewise.
7720 (__arm_vmlsdavaxq_p_s16): Likewise.
7721 (__arm_vmulhq_m_s8): Likewise.
7722 (__arm_vmulhq_m_s32): Likewise.
7723 (__arm_vmulhq_m_s16): Likewise.
7724 (__arm_vmulhq_m_u8): Likewise.
7725 (__arm_vmulhq_m_u32): Likewise.
7726 (__arm_vmulhq_m_u16): Likewise.
7727 (__arm_vmullbq_int_m_s8): Likewise.
7728 (__arm_vmullbq_int_m_s32): Likewise.
7729 (__arm_vmullbq_int_m_s16): Likewise.
7730 (__arm_vmullbq_int_m_u8): Likewise.
7731 (__arm_vmullbq_int_m_u32): Likewise.
7732 (__arm_vmullbq_int_m_u16): Likewise.
7733 (__arm_vmulltq_int_m_s8): Likewise.
7734 (__arm_vmulltq_int_m_s32): Likewise.
7735 (__arm_vmulltq_int_m_s16): Likewise.
7736 (__arm_vmulltq_int_m_u8): Likewise.
7737 (__arm_vmulltq_int_m_u32): Likewise.
7738 (__arm_vmulltq_int_m_u16): Likewise.
7739 (__arm_vmulq_m_n_s8): Likewise.
7740 (__arm_vmulq_m_n_s32): Likewise.
7741 (__arm_vmulq_m_n_s16): Likewise.
7742 (__arm_vmulq_m_n_u8): Likewise.
7743 (__arm_vmulq_m_n_u32): Likewise.
7744 (__arm_vmulq_m_n_u16): Likewise.
7745 (__arm_vmulq_m_s8): Likewise.
7746 (__arm_vmulq_m_s32): Likewise.
7747 (__arm_vmulq_m_s16): Likewise.
7748 (__arm_vmulq_m_u8): Likewise.
7749 (__arm_vmulq_m_u32): Likewise.
7750 (__arm_vmulq_m_u16): Likewise.
7751 (__arm_vornq_m_s8): Likewise.
7752 (__arm_vornq_m_s32): Likewise.
7753 (__arm_vornq_m_s16): Likewise.
7754 (__arm_vornq_m_u8): Likewise.
7755 (__arm_vornq_m_u32): Likewise.
7756 (__arm_vornq_m_u16): Likewise.
7757 (__arm_vorrq_m_s8): Likewise.
7758 (__arm_vorrq_m_s32): Likewise.
7759 (__arm_vorrq_m_s16): Likewise.
7760 (__arm_vorrq_m_u8): Likewise.
7761 (__arm_vorrq_m_u32): Likewise.
7762 (__arm_vorrq_m_u16): Likewise.
7763 (__arm_vqaddq_m_n_s8): Likewise.
7764 (__arm_vqaddq_m_n_s32): Likewise.
7765 (__arm_vqaddq_m_n_s16): Likewise.
7766 (__arm_vqaddq_m_n_u8): Likewise.
7767 (__arm_vqaddq_m_n_u32): Likewise.
7768 (__arm_vqaddq_m_n_u16): Likewise.
7769 (__arm_vqaddq_m_s8): Likewise.
7770 (__arm_vqaddq_m_s32): Likewise.
7771 (__arm_vqaddq_m_s16): Likewise.
7772 (__arm_vqaddq_m_u8): Likewise.
7773 (__arm_vqaddq_m_u32): Likewise.
7774 (__arm_vqaddq_m_u16): Likewise.
7775 (__arm_vqdmladhq_m_s8): Likewise.
7776 (__arm_vqdmladhq_m_s32): Likewise.
7777 (__arm_vqdmladhq_m_s16): Likewise.
7778 (__arm_vqdmladhxq_m_s8): Likewise.
7779 (__arm_vqdmladhxq_m_s32): Likewise.
7780 (__arm_vqdmladhxq_m_s16): Likewise.
7781 (__arm_vqdmlahq_m_n_s8): Likewise.
7782 (__arm_vqdmlahq_m_n_s32): Likewise.
7783 (__arm_vqdmlahq_m_n_s16): Likewise.
7784 (__arm_vqdmlahq_m_n_u8): Likewise.
7785 (__arm_vqdmlahq_m_n_u32): Likewise.
7786 (__arm_vqdmlahq_m_n_u16): Likewise.
7787 (__arm_vqdmlsdhq_m_s8): Likewise.
7788 (__arm_vqdmlsdhq_m_s32): Likewise.
7789 (__arm_vqdmlsdhq_m_s16): Likewise.
7790 (__arm_vqdmlsdhxq_m_s8): Likewise.
7791 (__arm_vqdmlsdhxq_m_s32): Likewise.
7792 (__arm_vqdmlsdhxq_m_s16): Likewise.
7793 (__arm_vqdmulhq_m_n_s8): Likewise.
7794 (__arm_vqdmulhq_m_n_s32): Likewise.
7795 (__arm_vqdmulhq_m_n_s16): Likewise.
7796 (__arm_vqdmulhq_m_s8): Likewise.
7797 (__arm_vqdmulhq_m_s32): Likewise.
7798 (__arm_vqdmulhq_m_s16): Likewise.
7799 (__arm_vqrdmladhq_m_s8): Likewise.
7800 (__arm_vqrdmladhq_m_s32): Likewise.
7801 (__arm_vqrdmladhq_m_s16): Likewise.
7802 (__arm_vqrdmladhxq_m_s8): Likewise.
7803 (__arm_vqrdmladhxq_m_s32): Likewise.
7804 (__arm_vqrdmladhxq_m_s16): Likewise.
7805 (__arm_vqrdmlahq_m_n_s8): Likewise.
7806 (__arm_vqrdmlahq_m_n_s32): Likewise.
7807 (__arm_vqrdmlahq_m_n_s16): Likewise.
7808 (__arm_vqrdmlahq_m_n_u8): Likewise.
7809 (__arm_vqrdmlahq_m_n_u32): Likewise.
7810 (__arm_vqrdmlahq_m_n_u16): Likewise.
7811 (__arm_vqrdmlashq_m_n_s8): Likewise.
7812 (__arm_vqrdmlashq_m_n_s32): Likewise.
7813 (__arm_vqrdmlashq_m_n_s16): Likewise.
7814 (__arm_vqrdmlashq_m_n_u8): Likewise.
7815 (__arm_vqrdmlashq_m_n_u32): Likewise.
7816 (__arm_vqrdmlashq_m_n_u16): Likewise.
7817 (__arm_vqrdmlsdhq_m_s8): Likewise.
7818 (__arm_vqrdmlsdhq_m_s32): Likewise.
7819 (__arm_vqrdmlsdhq_m_s16): Likewise.
7820 (__arm_vqrdmlsdhxq_m_s8): Likewise.
7821 (__arm_vqrdmlsdhxq_m_s32): Likewise.
7822 (__arm_vqrdmlsdhxq_m_s16): Likewise.
7823 (__arm_vqrdmulhq_m_n_s8): Likewise.
7824 (__arm_vqrdmulhq_m_n_s32): Likewise.
7825 (__arm_vqrdmulhq_m_n_s16): Likewise.
7826 (__arm_vqrdmulhq_m_s8): Likewise.
7827 (__arm_vqrdmulhq_m_s32): Likewise.
7828 (__arm_vqrdmulhq_m_s16): Likewise.
7829 (__arm_vqrshlq_m_s8): Likewise.
7830 (__arm_vqrshlq_m_s32): Likewise.
7831 (__arm_vqrshlq_m_s16): Likewise.
7832 (__arm_vqrshlq_m_u8): Likewise.
7833 (__arm_vqrshlq_m_u32): Likewise.
7834 (__arm_vqrshlq_m_u16): Likewise.
7835 (__arm_vqshlq_m_n_s8): Likewise.
7836 (__arm_vqshlq_m_n_s32): Likewise.
7837 (__arm_vqshlq_m_n_s16): Likewise.
7838 (__arm_vqshlq_m_n_u8): Likewise.
7839 (__arm_vqshlq_m_n_u32): Likewise.
7840 (__arm_vqshlq_m_n_u16): Likewise.
7841 (__arm_vqshlq_m_s8): Likewise.
7842 (__arm_vqshlq_m_s32): Likewise.
7843 (__arm_vqshlq_m_s16): Likewise.
7844 (__arm_vqshlq_m_u8): Likewise.
7845 (__arm_vqshlq_m_u32): Likewise.
7846 (__arm_vqshlq_m_u16): Likewise.
7847 (__arm_vqsubq_m_n_s8): Likewise.
7848 (__arm_vqsubq_m_n_s32): Likewise.
7849 (__arm_vqsubq_m_n_s16): Likewise.
7850 (__arm_vqsubq_m_n_u8): Likewise.
7851 (__arm_vqsubq_m_n_u32): Likewise.
7852 (__arm_vqsubq_m_n_u16): Likewise.
7853 (__arm_vqsubq_m_s8): Likewise.
7854 (__arm_vqsubq_m_s32): Likewise.
7855 (__arm_vqsubq_m_s16): Likewise.
7856 (__arm_vqsubq_m_u8): Likewise.
7857 (__arm_vqsubq_m_u32): Likewise.
7858 (__arm_vqsubq_m_u16): Likewise.
7859 (__arm_vrhaddq_m_s8): Likewise.
7860 (__arm_vrhaddq_m_s32): Likewise.
7861 (__arm_vrhaddq_m_s16): Likewise.
7862 (__arm_vrhaddq_m_u8): Likewise.
7863 (__arm_vrhaddq_m_u32): Likewise.
7864 (__arm_vrhaddq_m_u16): Likewise.
7865 (__arm_vrmulhq_m_s8): Likewise.
7866 (__arm_vrmulhq_m_s32): Likewise.
7867 (__arm_vrmulhq_m_s16): Likewise.
7868 (__arm_vrmulhq_m_u8): Likewise.
7869 (__arm_vrmulhq_m_u32): Likewise.
7870 (__arm_vrmulhq_m_u16): Likewise.
7871 (__arm_vrshlq_m_s8): Likewise.
7872 (__arm_vrshlq_m_s32): Likewise.
7873 (__arm_vrshlq_m_s16): Likewise.
7874 (__arm_vrshlq_m_u8): Likewise.
7875 (__arm_vrshlq_m_u32): Likewise.
7876 (__arm_vrshlq_m_u16): Likewise.
7877 (__arm_vrshrq_m_n_s8): Likewise.
7878 (__arm_vrshrq_m_n_s32): Likewise.
7879 (__arm_vrshrq_m_n_s16): Likewise.
7880 (__arm_vrshrq_m_n_u8): Likewise.
7881 (__arm_vrshrq_m_n_u32): Likewise.
7882 (__arm_vrshrq_m_n_u16): Likewise.
7883 (__arm_vshlq_m_n_s8): Likewise.
7884 (__arm_vshlq_m_n_s32): Likewise.
7885 (__arm_vshlq_m_n_s16): Likewise.
7886 (__arm_vshlq_m_n_u8): Likewise.
7887 (__arm_vshlq_m_n_u32): Likewise.
7888 (__arm_vshlq_m_n_u16): Likewise.
7889 (__arm_vshrq_m_n_s8): Likewise.
7890 (__arm_vshrq_m_n_s32): Likewise.
7891 (__arm_vshrq_m_n_s16): Likewise.
7892 (__arm_vshrq_m_n_u8): Likewise.
7893 (__arm_vshrq_m_n_u32): Likewise.
7894 (__arm_vshrq_m_n_u16): Likewise.
7895 (__arm_vsliq_m_n_s8): Likewise.
7896 (__arm_vsliq_m_n_s32): Likewise.
7897 (__arm_vsliq_m_n_s16): Likewise.
7898 (__arm_vsliq_m_n_u8): Likewise.
7899 (__arm_vsliq_m_n_u32): Likewise.
7900 (__arm_vsliq_m_n_u16): Likewise.
7901 (__arm_vsubq_m_n_s8): Likewise.
7902 (__arm_vsubq_m_n_s32): Likewise.
7903 (__arm_vsubq_m_n_s16): Likewise.
7904 (__arm_vsubq_m_n_u8): Likewise.
7905 (__arm_vsubq_m_n_u32): Likewise.
7906 (__arm_vsubq_m_n_u16): Likewise.
7907 (vqdmladhq_m): Define polymorphic variant.
7908 (vqdmladhxq_m): Likewise.
7909 (vqdmlsdhq_m): Likewise.
7910 (vqdmlsdhxq_m): Likewise.
7911 (vabdq_m): Likewise.
7912 (vandq_m): Likewise.
7913 (vbicq_m): Likewise.
7914 (vbrsrq_m_n): Likewise.
7915 (vcaddq_rot270_m): Likewise.
7916 (vcaddq_rot90_m): Likewise.
7917 (veorq_m): Likewise.
7918 (vmaxq_m): Likewise.
7919 (vminq_m): Likewise.
7920 (vmladavaq_p): Likewise.
7921 (vmlaq_m_n): Likewise.
7922 (vmlasq_m_n): Likewise.
7923 (vmulhq_m): Likewise.
7924 (vmullbq_int_m): Likewise.
7925 (vmulltq_int_m): Likewise.
7926 (vornq_m): Likewise.
7927 (vorrq_m): Likewise.
7928 (vqdmlahq_m_n): Likewise.
7929 (vqrdmlahq_m_n): Likewise.
7930 (vqrdmlashq_m_n): Likewise.
7931 (vqrshlq_m): Likewise.
7932 (vqshlq_m_n): Likewise.
7933 (vqshlq_m): Likewise.
7934 (vrhaddq_m): Likewise.
7935 (vrmulhq_m): Likewise.
7936 (vrshlq_m): Likewise.
7937 (vrshrq_m_n): Likewise.
7938 (vshlq_m_n): Likewise.
7939 (vshrq_m_n): Likewise.
7940 (vsliq_m): Likewise.
7941 (vaddq_m_n): Likewise.
7942 (vaddq_m): Likewise.
7943 (vhaddq_m_n): Likewise.
7944 (vhaddq_m): Likewise.
7945 (vhcaddq_rot270_m): Likewise.
7946 (vhcaddq_rot90_m): Likewise.
7947 (vhsubq_m): Likewise.
7948 (vhsubq_m_n): Likewise.
7949 (vmulq_m_n): Likewise.
7950 (vmulq_m): Likewise.
7951 (vqaddq_m_n): Likewise.
7952 (vqaddq_m): Likewise.
7953 (vqdmulhq_m_n): Likewise.
7954 (vqdmulhq_m): Likewise.
7955 (vsubq_m_n): Likewise.
7956 (vsliq_m_n): Likewise.
7957 (vqsubq_m_n): Likewise.
7958 (vqsubq_m): Likewise.
7959 (vqrdmulhq_m): Likewise.
7960 (vqrdmulhq_m_n): Likewise.
7961 (vqrdmlsdhxq_m): Likewise.
7962 (vqrdmlsdhq_m): Likewise.
7963 (vqrdmladhq_m): Likewise.
7964 (vqrdmladhxq_m): Likewise.
7965 (vmlsdavaxq_p): Likewise.
7966 (vmlsdavaq_p): Likewise.
7967 (vmladavaxq_p): Likewise.
7968 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7970 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7971 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
7972 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
7973 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
7974 * config/arm/mve.md (VHSUBQ_M): Define iterators.
7975 (VSLIQ_M_N): Likewise.
7976 (VQRDMLAHQ_M_N): Likewise.
7977 (VRSHLQ_M): Likewise.
7978 (VMINQ_M): Likewise.
7979 (VMULLBQ_INT_M): Likewise.
7980 (VMULHQ_M): Likewise.
7981 (VMULQ_M): Likewise.
7982 (VHSUBQ_M_N): Likewise.
7983 (VHADDQ_M_N): Likewise.
7984 (VORRQ_M): Likewise.
7985 (VRMULHQ_M): Likewise.
7986 (VQADDQ_M): Likewise.
7987 (VRSHRQ_M_N): Likewise.
7988 (VQSUBQ_M_N): Likewise.
7989 (VADDQ_M): Likewise.
7990 (VORNQ_M): Likewise.
7991 (VQDMLAHQ_M_N): Likewise.
7992 (VRHADDQ_M): Likewise.
7993 (VQSHLQ_M): Likewise.
7994 (VANDQ_M): Likewise.
7995 (VBICQ_M): Likewise.
7996 (VSHLQ_M_N): Likewise.
7997 (VCADDQ_ROT270_M): Likewise.
7998 (VQRSHLQ_M): Likewise.
7999 (VQADDQ_M_N): Likewise.
8000 (VADDQ_M_N): Likewise.
8001 (VMAXQ_M): Likewise.
8002 (VQSUBQ_M): Likewise.
8003 (VMLASQ_M_N): Likewise.
8004 (VMLADAVAQ_P): Likewise.
8005 (VBRSRQ_M_N): Likewise.
8006 (VMULQ_M_N): Likewise.
8007 (VCADDQ_ROT90_M): Likewise.
8008 (VMULLTQ_INT_M): Likewise.
8009 (VEORQ_M): Likewise.
8010 (VSHRQ_M_N): Likewise.
8011 (VSUBQ_M_N): Likewise.
8012 (VHADDQ_M): Likewise.
8013 (VABDQ_M): Likewise.
8014 (VQRDMLASHQ_M_N): Likewise.
8015 (VMLAQ_M_N): Likewise.
8016 (VQSHLQ_M_N): Likewise.
8017 (mve_vabdq_m_<supf><mode>): Define RTL pattern.
8018 (mve_vaddq_m_n_<supf><mode>): Likewise.
8019 (mve_vaddq_m_<supf><mode>): Likewise.
8020 (mve_vandq_m_<supf><mode>): Likewise.
8021 (mve_vbicq_m_<supf><mode>): Likewise.
8022 (mve_vbrsrq_m_n_<supf><mode>): Likewise.
8023 (mve_vcaddq_rot270_m_<supf><mode>): Likewise.
8024 (mve_vcaddq_rot90_m_<supf><mode>): Likewise.
8025 (mve_veorq_m_<supf><mode>): Likewise.
8026 (mve_vhaddq_m_n_<supf><mode>): Likewise.
8027 (mve_vhaddq_m_<supf><mode>): Likewise.
8028 (mve_vhsubq_m_n_<supf><mode>): Likewise.
8029 (mve_vhsubq_m_<supf><mode>): Likewise.
8030 (mve_vmaxq_m_<supf><mode>): Likewise.
8031 (mve_vminq_m_<supf><mode>): Likewise.
8032 (mve_vmladavaq_p_<supf><mode>): Likewise.
8033 (mve_vmlaq_m_n_<supf><mode>): Likewise.
8034 (mve_vmlasq_m_n_<supf><mode>): Likewise.
8035 (mve_vmulhq_m_<supf><mode>): Likewise.
8036 (mve_vmullbq_int_m_<supf><mode>): Likewise.
8037 (mve_vmulltq_int_m_<supf><mode>): Likewise.
8038 (mve_vmulq_m_n_<supf><mode>): Likewise.
8039 (mve_vmulq_m_<supf><mode>): Likewise.
8040 (mve_vornq_m_<supf><mode>): Likewise.
8041 (mve_vorrq_m_<supf><mode>): Likewise.
8042 (mve_vqaddq_m_n_<supf><mode>): Likewise.
8043 (mve_vqaddq_m_<supf><mode>): Likewise.
8044 (mve_vqdmlahq_m_n_<supf><mode>): Likewise.
8045 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
8046 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
8047 (mve_vqrshlq_m_<supf><mode>): Likewise.
8048 (mve_vqshlq_m_n_<supf><mode>): Likewise.
8049 (mve_vqshlq_m_<supf><mode>): Likewise.
8050 (mve_vqsubq_m_n_<supf><mode>): Likewise.
8051 (mve_vqsubq_m_<supf><mode>): Likewise.
8052 (mve_vrhaddq_m_<supf><mode>): Likewise.
8053 (mve_vrmulhq_m_<supf><mode>): Likewise.
8054 (mve_vrshlq_m_<supf><mode>): Likewise.
8055 (mve_vrshrq_m_n_<supf><mode>): Likewise.
8056 (mve_vshlq_m_n_<supf><mode>): Likewise.
8057 (mve_vshrq_m_n_<supf><mode>): Likewise.
8058 (mve_vsliq_m_n_<supf><mode>): Likewise.
8059 (mve_vsubq_m_n_<supf><mode>): Likewise.
8060 (mve_vhcaddq_rot270_m_s<mode>): Likewise.
8061 (mve_vhcaddq_rot90_m_s<mode>): Likewise.
8062 (mve_vmladavaxq_p_s<mode>): Likewise.
8063 (mve_vmlsdavaq_p_s<mode>): Likewise.
8064 (mve_vmlsdavaxq_p_s<mode>): Likewise.
8065 (mve_vqdmladhq_m_s<mode>): Likewise.
8066 (mve_vqdmladhxq_m_s<mode>): Likewise.
8067 (mve_vqdmlsdhq_m_s<mode>): Likewise.
8068 (mve_vqdmlsdhxq_m_s<mode>): Likewise.
8069 (mve_vqdmulhq_m_n_s<mode>): Likewise.
8070 (mve_vqdmulhq_m_s<mode>): Likewise.
8071 (mve_vqrdmladhq_m_s<mode>): Likewise.
8072 (mve_vqrdmladhxq_m_s<mode>): Likewise.
8073 (mve_vqrdmlsdhq_m_s<mode>): Likewise.
8074 (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
8075 (mve_vqrdmulhq_m_n_s<mode>): Likewise.
8076 (mve_vqrdmulhq_m_s<mode>): Likewise.
8078 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8079 Mihail Ionescu <mihail.ionescu@arm.com>
8080 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8082 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
8083 Define builtin qualifier.
8084 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
8085 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8086 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8087 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8088 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8089 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8090 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
8091 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
8092 (vsubq_m_s8): Likewise.
8093 (vcvtq_m_n_f16_u16): Likewise.
8094 (vqshluq_m_n_s8): Likewise.
8095 (vabavq_p_s8): Likewise.
8096 (vsriq_m_n_u8): Likewise.
8097 (vshlq_m_u8): Likewise.
8098 (vsubq_m_u8): Likewise.
8099 (vabavq_p_u8): Likewise.
8100 (vshlq_m_s8): Likewise.
8101 (vcvtq_m_n_f16_s16): Likewise.
8102 (vsriq_m_n_s16): Likewise.
8103 (vsubq_m_s16): Likewise.
8104 (vcvtq_m_n_f32_u32): Likewise.
8105 (vqshluq_m_n_s16): Likewise.
8106 (vabavq_p_s16): Likewise.
8107 (vsriq_m_n_u16): Likewise.
8108 (vshlq_m_u16): Likewise.
8109 (vsubq_m_u16): Likewise.
8110 (vabavq_p_u16): Likewise.
8111 (vshlq_m_s16): Likewise.
8112 (vcvtq_m_n_f32_s32): Likewise.
8113 (vsriq_m_n_s32): Likewise.
8114 (vsubq_m_s32): Likewise.
8115 (vqshluq_m_n_s32): Likewise.
8116 (vabavq_p_s32): Likewise.
8117 (vsriq_m_n_u32): Likewise.
8118 (vshlq_m_u32): Likewise.
8119 (vsubq_m_u32): Likewise.
8120 (vabavq_p_u32): Likewise.
8121 (vshlq_m_s32): Likewise.
8122 (__arm_vsriq_m_n_s8): Define intrinsic.
8123 (__arm_vsubq_m_s8): Likewise.
8124 (__arm_vqshluq_m_n_s8): Likewise.
8125 (__arm_vabavq_p_s8): Likewise.
8126 (__arm_vsriq_m_n_u8): Likewise.
8127 (__arm_vshlq_m_u8): Likewise.
8128 (__arm_vsubq_m_u8): Likewise.
8129 (__arm_vabavq_p_u8): Likewise.
8130 (__arm_vshlq_m_s8): Likewise.
8131 (__arm_vsriq_m_n_s16): Likewise.
8132 (__arm_vsubq_m_s16): Likewise.
8133 (__arm_vqshluq_m_n_s16): Likewise.
8134 (__arm_vabavq_p_s16): Likewise.
8135 (__arm_vsriq_m_n_u16): Likewise.
8136 (__arm_vshlq_m_u16): Likewise.
8137 (__arm_vsubq_m_u16): Likewise.
8138 (__arm_vabavq_p_u16): Likewise.
8139 (__arm_vshlq_m_s16): Likewise.
8140 (__arm_vsriq_m_n_s32): Likewise.
8141 (__arm_vsubq_m_s32): Likewise.
8142 (__arm_vqshluq_m_n_s32): Likewise.
8143 (__arm_vabavq_p_s32): Likewise.
8144 (__arm_vsriq_m_n_u32): Likewise.
8145 (__arm_vshlq_m_u32): Likewise.
8146 (__arm_vsubq_m_u32): Likewise.
8147 (__arm_vabavq_p_u32): Likewise.
8148 (__arm_vshlq_m_s32): Likewise.
8149 (__arm_vcvtq_m_n_f16_u16): Likewise.
8150 (__arm_vcvtq_m_n_f16_s16): Likewise.
8151 (__arm_vcvtq_m_n_f32_u32): Likewise.
8152 (__arm_vcvtq_m_n_f32_s32): Likewise.
8153 (vcvtq_m_n): Define polymorphic variant.
8154 (vqshluq_m_n): Likewise.
8155 (vshlq_m): Likewise.
8156 (vsriq_m_n): Likewise.
8157 (vsubq_m): Likewise.
8158 (vabavq_p): Likewise.
8159 * config/arm/arm_mve_builtins.def
8160 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
8161 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
8162 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8163 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8164 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8165 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8166 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8167 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
8168 * config/arm/mve.md (VABAVQ_P): Define iterator.
8169 (VSHLQ_M): Likewise.
8170 (VSRIQ_M_N): Likewise.
8171 (VSUBQ_M): Likewise.
8172 (VCVTQ_M_N_TO_F): Likewise.
8173 (mve_vabavq_p_<supf><mode>): Define RTL pattern.
8174 (mve_vqshluq_m_n_s<mode>): Likewise.
8175 (mve_vshlq_m_<supf><mode>): Likewise.
8176 (mve_vsriq_m_n_<supf><mode>): Likewise.
8177 (mve_vsubq_m_<supf><mode>): Likewise.
8178 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
8180 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8181 Mihail Ionescu <mihail.ionescu@arm.com>
8182 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8184 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
8185 (vrmlsldavhaq_s32): Likewise.
8186 (vrmlsldavhaxq_s32): Likewise.
8187 (vaddlvaq_p_s32): Likewise.
8188 (vcvtbq_m_f16_f32): Likewise.
8189 (vcvtbq_m_f32_f16): Likewise.
8190 (vcvttq_m_f16_f32): Likewise.
8191 (vcvttq_m_f32_f16): Likewise.
8192 (vrev16q_m_s8): Likewise.
8193 (vrev32q_m_f16): Likewise.
8194 (vrmlaldavhq_p_s32): Likewise.
8195 (vrmlaldavhxq_p_s32): Likewise.
8196 (vrmlsldavhq_p_s32): Likewise.
8197 (vrmlsldavhxq_p_s32): Likewise.
8198 (vaddlvaq_p_u32): Likewise.
8199 (vrev16q_m_u8): Likewise.
8200 (vrmlaldavhq_p_u32): Likewise.
8201 (vmvnq_m_n_s16): Likewise.
8202 (vorrq_m_n_s16): Likewise.
8203 (vqrshrntq_n_s16): Likewise.
8204 (vqshrnbq_n_s16): Likewise.
8205 (vqshrntq_n_s16): Likewise.
8206 (vrshrnbq_n_s16): Likewise.
8207 (vrshrntq_n_s16): Likewise.
8208 (vshrnbq_n_s16): Likewise.
8209 (vshrntq_n_s16): Likewise.
8210 (vcmlaq_f16): Likewise.
8211 (vcmlaq_rot180_f16): Likewise.
8212 (vcmlaq_rot270_f16): Likewise.
8213 (vcmlaq_rot90_f16): Likewise.
8214 (vfmaq_f16): Likewise.
8215 (vfmaq_n_f16): Likewise.
8216 (vfmasq_n_f16): Likewise.
8217 (vfmsq_f16): Likewise.
8218 (vmlaldavaq_s16): Likewise.
8219 (vmlaldavaxq_s16): Likewise.
8220 (vmlsldavaq_s16): Likewise.
8221 (vmlsldavaxq_s16): Likewise.
8222 (vabsq_m_f16): Likewise.
8223 (vcvtmq_m_s16_f16): Likewise.
8224 (vcvtnq_m_s16_f16): Likewise.
8225 (vcvtpq_m_s16_f16): Likewise.
8226 (vcvtq_m_s16_f16): Likewise.
8227 (vdupq_m_n_f16): Likewise.
8228 (vmaxnmaq_m_f16): Likewise.
8229 (vmaxnmavq_p_f16): Likewise.
8230 (vmaxnmvq_p_f16): Likewise.
8231 (vminnmaq_m_f16): Likewise.
8232 (vminnmavq_p_f16): Likewise.
8233 (vminnmvq_p_f16): Likewise.
8234 (vmlaldavq_p_s16): Likewise.
8235 (vmlaldavxq_p_s16): Likewise.
8236 (vmlsldavq_p_s16): Likewise.
8237 (vmlsldavxq_p_s16): Likewise.
8238 (vmovlbq_m_s8): Likewise.
8239 (vmovltq_m_s8): Likewise.
8240 (vmovnbq_m_s16): Likewise.
8241 (vmovntq_m_s16): Likewise.
8242 (vnegq_m_f16): Likewise.
8243 (vpselq_f16): Likewise.
8244 (vqmovnbq_m_s16): Likewise.
8245 (vqmovntq_m_s16): Likewise.
8246 (vrev32q_m_s8): Likewise.
8247 (vrev64q_m_f16): Likewise.
8248 (vrndaq_m_f16): Likewise.
8249 (vrndmq_m_f16): Likewise.
8250 (vrndnq_m_f16): Likewise.
8251 (vrndpq_m_f16): Likewise.
8252 (vrndq_m_f16): Likewise.
8253 (vrndxq_m_f16): Likewise.
8254 (vcmpeqq_m_n_f16): Likewise.
8255 (vcmpgeq_m_f16): Likewise.
8256 (vcmpgeq_m_n_f16): Likewise.
8257 (vcmpgtq_m_f16): Likewise.
8258 (vcmpgtq_m_n_f16): Likewise.
8259 (vcmpleq_m_f16): Likewise.
8260 (vcmpleq_m_n_f16): Likewise.
8261 (vcmpltq_m_f16): Likewise.
8262 (vcmpltq_m_n_f16): Likewise.
8263 (vcmpneq_m_f16): Likewise.
8264 (vcmpneq_m_n_f16): Likewise.
8265 (vmvnq_m_n_u16): Likewise.
8266 (vorrq_m_n_u16): Likewise.
8267 (vqrshruntq_n_s16): Likewise.
8268 (vqshrunbq_n_s16): Likewise.
8269 (vqshruntq_n_s16): Likewise.
8270 (vcvtmq_m_u16_f16): Likewise.
8271 (vcvtnq_m_u16_f16): Likewise.
8272 (vcvtpq_m_u16_f16): Likewise.
8273 (vcvtq_m_u16_f16): Likewise.
8274 (vqmovunbq_m_s16): Likewise.
8275 (vqmovuntq_m_s16): Likewise.
8276 (vqrshrntq_n_u16): Likewise.
8277 (vqshrnbq_n_u16): Likewise.
8278 (vqshrntq_n_u16): Likewise.
8279 (vrshrnbq_n_u16): Likewise.
8280 (vrshrntq_n_u16): Likewise.
8281 (vshrnbq_n_u16): Likewise.
8282 (vshrntq_n_u16): Likewise.
8283 (vmlaldavaq_u16): Likewise.
8284 (vmlaldavaxq_u16): Likewise.
8285 (vmlaldavq_p_u16): Likewise.
8286 (vmlaldavxq_p_u16): Likewise.
8287 (vmovlbq_m_u8): Likewise.
8288 (vmovltq_m_u8): Likewise.
8289 (vmovnbq_m_u16): Likewise.
8290 (vmovntq_m_u16): Likewise.
8291 (vqmovnbq_m_u16): Likewise.
8292 (vqmovntq_m_u16): Likewise.
8293 (vrev32q_m_u8): Likewise.
8294 (vmvnq_m_n_s32): Likewise.
8295 (vorrq_m_n_s32): Likewise.
8296 (vqrshrntq_n_s32): Likewise.
8297 (vqshrnbq_n_s32): Likewise.
8298 (vqshrntq_n_s32): Likewise.
8299 (vrshrnbq_n_s32): Likewise.
8300 (vrshrntq_n_s32): Likewise.
8301 (vshrnbq_n_s32): Likewise.
8302 (vshrntq_n_s32): Likewise.
8303 (vcmlaq_f32): Likewise.
8304 (vcmlaq_rot180_f32): Likewise.
8305 (vcmlaq_rot270_f32): Likewise.
8306 (vcmlaq_rot90_f32): Likewise.
8307 (vfmaq_f32): Likewise.
8308 (vfmaq_n_f32): Likewise.
8309 (vfmasq_n_f32): Likewise.
8310 (vfmsq_f32): Likewise.
8311 (vmlaldavaq_s32): Likewise.
8312 (vmlaldavaxq_s32): Likewise.
8313 (vmlsldavaq_s32): Likewise.
8314 (vmlsldavaxq_s32): Likewise.
8315 (vabsq_m_f32): Likewise.
8316 (vcvtmq_m_s32_f32): Likewise.
8317 (vcvtnq_m_s32_f32): Likewise.
8318 (vcvtpq_m_s32_f32): Likewise.
8319 (vcvtq_m_s32_f32): Likewise.
8320 (vdupq_m_n_f32): Likewise.
8321 (vmaxnmaq_m_f32): Likewise.
8322 (vmaxnmavq_p_f32): Likewise.
8323 (vmaxnmvq_p_f32): Likewise.
8324 (vminnmaq_m_f32): Likewise.
8325 (vminnmavq_p_f32): Likewise.
8326 (vminnmvq_p_f32): Likewise.
8327 (vmlaldavq_p_s32): Likewise.
8328 (vmlaldavxq_p_s32): Likewise.
8329 (vmlsldavq_p_s32): Likewise.
8330 (vmlsldavxq_p_s32): Likewise.
8331 (vmovlbq_m_s16): Likewise.
8332 (vmovltq_m_s16): Likewise.
8333 (vmovnbq_m_s32): Likewise.
8334 (vmovntq_m_s32): Likewise.
8335 (vnegq_m_f32): Likewise.
8336 (vpselq_f32): Likewise.
8337 (vqmovnbq_m_s32): Likewise.
8338 (vqmovntq_m_s32): Likewise.
8339 (vrev32q_m_s16): Likewise.
8340 (vrev64q_m_f32): Likewise.
8341 (vrndaq_m_f32): Likewise.
8342 (vrndmq_m_f32): Likewise.
8343 (vrndnq_m_f32): Likewise.
8344 (vrndpq_m_f32): Likewise.
8345 (vrndq_m_f32): Likewise.
8346 (vrndxq_m_f32): Likewise.
8347 (vcmpeqq_m_n_f32): Likewise.
8348 (vcmpgeq_m_f32): Likewise.
8349 (vcmpgeq_m_n_f32): Likewise.
8350 (vcmpgtq_m_f32): Likewise.
8351 (vcmpgtq_m_n_f32): Likewise.
8352 (vcmpleq_m_f32): Likewise.
8353 (vcmpleq_m_n_f32): Likewise.
8354 (vcmpltq_m_f32): Likewise.
8355 (vcmpltq_m_n_f32): Likewise.
8356 (vcmpneq_m_f32): Likewise.
8357 (vcmpneq_m_n_f32): Likewise.
8358 (vmvnq_m_n_u32): Likewise.
8359 (vorrq_m_n_u32): Likewise.
8360 (vqrshruntq_n_s32): Likewise.
8361 (vqshrunbq_n_s32): Likewise.
8362 (vqshruntq_n_s32): Likewise.
8363 (vcvtmq_m_u32_f32): Likewise.
8364 (vcvtnq_m_u32_f32): Likewise.
8365 (vcvtpq_m_u32_f32): Likewise.
8366 (vcvtq_m_u32_f32): Likewise.
8367 (vqmovunbq_m_s32): Likewise.
8368 (vqmovuntq_m_s32): Likewise.
8369 (vqrshrntq_n_u32): Likewise.
8370 (vqshrnbq_n_u32): Likewise.
8371 (vqshrntq_n_u32): Likewise.
8372 (vrshrnbq_n_u32): Likewise.
8373 (vrshrntq_n_u32): Likewise.
8374 (vshrnbq_n_u32): Likewise.
8375 (vshrntq_n_u32): Likewise.
8376 (vmlaldavaq_u32): Likewise.
8377 (vmlaldavaxq_u32): Likewise.
8378 (vmlaldavq_p_u32): Likewise.
8379 (vmlaldavxq_p_u32): Likewise.
8380 (vmovlbq_m_u16): Likewise.
8381 (vmovltq_m_u16): Likewise.
8382 (vmovnbq_m_u32): Likewise.
8383 (vmovntq_m_u32): Likewise.
8384 (vqmovnbq_m_u32): Likewise.
8385 (vqmovntq_m_u32): Likewise.
8386 (vrev32q_m_u16): Likewise.
8387 (__arm_vrmlaldavhaxq_s32): Define intrinsic.
8388 (__arm_vrmlsldavhaq_s32): Likewise.
8389 (__arm_vrmlsldavhaxq_s32): Likewise.
8390 (__arm_vaddlvaq_p_s32): Likewise.
8391 (__arm_vrev16q_m_s8): Likewise.
8392 (__arm_vrmlaldavhq_p_s32): Likewise.
8393 (__arm_vrmlaldavhxq_p_s32): Likewise.
8394 (__arm_vrmlsldavhq_p_s32): Likewise.
8395 (__arm_vrmlsldavhxq_p_s32): Likewise.
8396 (__arm_vaddlvaq_p_u32): Likewise.
8397 (__arm_vrev16q_m_u8): Likewise.
8398 (__arm_vrmlaldavhq_p_u32): Likewise.
8399 (__arm_vmvnq_m_n_s16): Likewise.
8400 (__arm_vorrq_m_n_s16): Likewise.
8401 (__arm_vqrshrntq_n_s16): Likewise.
8402 (__arm_vqshrnbq_n_s16): Likewise.
8403 (__arm_vqshrntq_n_s16): Likewise.
8404 (__arm_vrshrnbq_n_s16): Likewise.
8405 (__arm_vrshrntq_n_s16): Likewise.
8406 (__arm_vshrnbq_n_s16): Likewise.
8407 (__arm_vshrntq_n_s16): Likewise.
8408 (__arm_vmlaldavaq_s16): Likewise.
8409 (__arm_vmlaldavaxq_s16): Likewise.
8410 (__arm_vmlsldavaq_s16): Likewise.
8411 (__arm_vmlsldavaxq_s16): Likewise.
8412 (__arm_vmlaldavq_p_s16): Likewise.
8413 (__arm_vmlaldavxq_p_s16): Likewise.
8414 (__arm_vmlsldavq_p_s16): Likewise.
8415 (__arm_vmlsldavxq_p_s16): Likewise.
8416 (__arm_vmovlbq_m_s8): Likewise.
8417 (__arm_vmovltq_m_s8): Likewise.
8418 (__arm_vmovnbq_m_s16): Likewise.
8419 (__arm_vmovntq_m_s16): Likewise.
8420 (__arm_vqmovnbq_m_s16): Likewise.
8421 (__arm_vqmovntq_m_s16): Likewise.
8422 (__arm_vrev32q_m_s8): Likewise.
8423 (__arm_vmvnq_m_n_u16): Likewise.
8424 (__arm_vorrq_m_n_u16): Likewise.
8425 (__arm_vqrshruntq_n_s16): Likewise.
8426 (__arm_vqshrunbq_n_s16): Likewise.
8427 (__arm_vqshruntq_n_s16): Likewise.
8428 (__arm_vqmovunbq_m_s16): Likewise.
8429 (__arm_vqmovuntq_m_s16): Likewise.
8430 (__arm_vqrshrntq_n_u16): Likewise.
8431 (__arm_vqshrnbq_n_u16): Likewise.
8432 (__arm_vqshrntq_n_u16): Likewise.
8433 (__arm_vrshrnbq_n_u16): Likewise.
8434 (__arm_vrshrntq_n_u16): Likewise.
8435 (__arm_vshrnbq_n_u16): Likewise.
8436 (__arm_vshrntq_n_u16): Likewise.
8437 (__arm_vmlaldavaq_u16): Likewise.
8438 (__arm_vmlaldavaxq_u16): Likewise.
8439 (__arm_vmlaldavq_p_u16): Likewise.
8440 (__arm_vmlaldavxq_p_u16): Likewise.
8441 (__arm_vmovlbq_m_u8): Likewise.
8442 (__arm_vmovltq_m_u8): Likewise.
8443 (__arm_vmovnbq_m_u16): Likewise.
8444 (__arm_vmovntq_m_u16): Likewise.
8445 (__arm_vqmovnbq_m_u16): Likewise.
8446 (__arm_vqmovntq_m_u16): Likewise.
8447 (__arm_vrev32q_m_u8): Likewise.
8448 (__arm_vmvnq_m_n_s32): Likewise.
8449 (__arm_vorrq_m_n_s32): Likewise.
8450 (__arm_vqrshrntq_n_s32): Likewise.
8451 (__arm_vqshrnbq_n_s32): Likewise.
8452 (__arm_vqshrntq_n_s32): Likewise.
8453 (__arm_vrshrnbq_n_s32): Likewise.
8454 (__arm_vrshrntq_n_s32): Likewise.
8455 (__arm_vshrnbq_n_s32): Likewise.
8456 (__arm_vshrntq_n_s32): Likewise.
8457 (__arm_vmlaldavaq_s32): Likewise.
8458 (__arm_vmlaldavaxq_s32): Likewise.
8459 (__arm_vmlsldavaq_s32): Likewise.
8460 (__arm_vmlsldavaxq_s32): Likewise.
8461 (__arm_vmlaldavq_p_s32): Likewise.
8462 (__arm_vmlaldavxq_p_s32): Likewise.
8463 (__arm_vmlsldavq_p_s32): Likewise.
8464 (__arm_vmlsldavxq_p_s32): Likewise.
8465 (__arm_vmovlbq_m_s16): Likewise.
8466 (__arm_vmovltq_m_s16): Likewise.
8467 (__arm_vmovnbq_m_s32): Likewise.
8468 (__arm_vmovntq_m_s32): Likewise.
8469 (__arm_vqmovnbq_m_s32): Likewise.
8470 (__arm_vqmovntq_m_s32): Likewise.
8471 (__arm_vrev32q_m_s16): Likewise.
8472 (__arm_vmvnq_m_n_u32): Likewise.
8473 (__arm_vorrq_m_n_u32): Likewise.
8474 (__arm_vqrshruntq_n_s32): Likewise.
8475 (__arm_vqshrunbq_n_s32): Likewise.
8476 (__arm_vqshruntq_n_s32): Likewise.
8477 (__arm_vqmovunbq_m_s32): Likewise.
8478 (__arm_vqmovuntq_m_s32): Likewise.
8479 (__arm_vqrshrntq_n_u32): Likewise.
8480 (__arm_vqshrnbq_n_u32): Likewise.
8481 (__arm_vqshrntq_n_u32): Likewise.
8482 (__arm_vrshrnbq_n_u32): Likewise.
8483 (__arm_vrshrntq_n_u32): Likewise.
8484 (__arm_vshrnbq_n_u32): Likewise.
8485 (__arm_vshrntq_n_u32): Likewise.
8486 (__arm_vmlaldavaq_u32): Likewise.
8487 (__arm_vmlaldavaxq_u32): Likewise.
8488 (__arm_vmlaldavq_p_u32): Likewise.
8489 (__arm_vmlaldavxq_p_u32): Likewise.
8490 (__arm_vmovlbq_m_u16): Likewise.
8491 (__arm_vmovltq_m_u16): Likewise.
8492 (__arm_vmovnbq_m_u32): Likewise.
8493 (__arm_vmovntq_m_u32): Likewise.
8494 (__arm_vqmovnbq_m_u32): Likewise.
8495 (__arm_vqmovntq_m_u32): Likewise.
8496 (__arm_vrev32q_m_u16): Likewise.
8497 (__arm_vcvtbq_m_f16_f32): Likewise.
8498 (__arm_vcvtbq_m_f32_f16): Likewise.
8499 (__arm_vcvttq_m_f16_f32): Likewise.
8500 (__arm_vcvttq_m_f32_f16): Likewise.
8501 (__arm_vrev32q_m_f16): Likewise.
8502 (__arm_vcmlaq_f16): Likewise.
8503 (__arm_vcmlaq_rot180_f16): Likewise.
8504 (__arm_vcmlaq_rot270_f16): Likewise.
8505 (__arm_vcmlaq_rot90_f16): Likewise.
8506 (__arm_vfmaq_f16): Likewise.
8507 (__arm_vfmaq_n_f16): Likewise.
8508 (__arm_vfmasq_n_f16): Likewise.
8509 (__arm_vfmsq_f16): Likewise.
8510 (__arm_vabsq_m_f16): Likewise.
8511 (__arm_vcvtmq_m_s16_f16): Likewise.
8512 (__arm_vcvtnq_m_s16_f16): Likewise.
8513 (__arm_vcvtpq_m_s16_f16): Likewise.
8514 (__arm_vcvtq_m_s16_f16): Likewise.
8515 (__arm_vdupq_m_n_f16): Likewise.
8516 (__arm_vmaxnmaq_m_f16): Likewise.
8517 (__arm_vmaxnmavq_p_f16): Likewise.
8518 (__arm_vmaxnmvq_p_f16): Likewise.
8519 (__arm_vminnmaq_m_f16): Likewise.
8520 (__arm_vminnmavq_p_f16): Likewise.
8521 (__arm_vminnmvq_p_f16): Likewise.
8522 (__arm_vnegq_m_f16): Likewise.
8523 (__arm_vpselq_f16): Likewise.
8524 (__arm_vrev64q_m_f16): Likewise.
8525 (__arm_vrndaq_m_f16): Likewise.
8526 (__arm_vrndmq_m_f16): Likewise.
8527 (__arm_vrndnq_m_f16): Likewise.
8528 (__arm_vrndpq_m_f16): Likewise.
8529 (__arm_vrndq_m_f16): Likewise.
8530 (__arm_vrndxq_m_f16): Likewise.
8531 (__arm_vcmpeqq_m_n_f16): Likewise.
8532 (__arm_vcmpgeq_m_f16): Likewise.
8533 (__arm_vcmpgeq_m_n_f16): Likewise.
8534 (__arm_vcmpgtq_m_f16): Likewise.
8535 (__arm_vcmpgtq_m_n_f16): Likewise.
8536 (__arm_vcmpleq_m_f16): Likewise.
8537 (__arm_vcmpleq_m_n_f16): Likewise.
8538 (__arm_vcmpltq_m_f16): Likewise.
8539 (__arm_vcmpltq_m_n_f16): Likewise.
8540 (__arm_vcmpneq_m_f16): Likewise.
8541 (__arm_vcmpneq_m_n_f16): Likewise.
8542 (__arm_vcvtmq_m_u16_f16): Likewise.
8543 (__arm_vcvtnq_m_u16_f16): Likewise.
8544 (__arm_vcvtpq_m_u16_f16): Likewise.
8545 (__arm_vcvtq_m_u16_f16): Likewise.
8546 (__arm_vcmlaq_f32): Likewise.
8547 (__arm_vcmlaq_rot180_f32): Likewise.
8548 (__arm_vcmlaq_rot270_f32): Likewise.
8549 (__arm_vcmlaq_rot90_f32): Likewise.
8550 (__arm_vfmaq_f32): Likewise.
8551 (__arm_vfmaq_n_f32): Likewise.
8552 (__arm_vfmasq_n_f32): Likewise.
8553 (__arm_vfmsq_f32): Likewise.
8554 (__arm_vabsq_m_f32): Likewise.
8555 (__arm_vcvtmq_m_s32_f32): Likewise.
8556 (__arm_vcvtnq_m_s32_f32): Likewise.
8557 (__arm_vcvtpq_m_s32_f32): Likewise.
8558 (__arm_vcvtq_m_s32_f32): Likewise.
8559 (__arm_vdupq_m_n_f32): Likewise.
8560 (__arm_vmaxnmaq_m_f32): Likewise.
8561 (__arm_vmaxnmavq_p_f32): Likewise.
8562 (__arm_vmaxnmvq_p_f32): Likewise.
8563 (__arm_vminnmaq_m_f32): Likewise.
8564 (__arm_vminnmavq_p_f32): Likewise.
8565 (__arm_vminnmvq_p_f32): Likewise.
8566 (__arm_vnegq_m_f32): Likewise.
8567 (__arm_vpselq_f32): Likewise.
8568 (__arm_vrev64q_m_f32): Likewise.
8569 (__arm_vrndaq_m_f32): Likewise.
8570 (__arm_vrndmq_m_f32): Likewise.
8571 (__arm_vrndnq_m_f32): Likewise.
8572 (__arm_vrndpq_m_f32): Likewise.
8573 (__arm_vrndq_m_f32): Likewise.
8574 (__arm_vrndxq_m_f32): Likewise.
8575 (__arm_vcmpeqq_m_n_f32): Likewise.
8576 (__arm_vcmpgeq_m_f32): Likewise.
8577 (__arm_vcmpgeq_m_n_f32): Likewise.
8578 (__arm_vcmpgtq_m_f32): Likewise.
8579 (__arm_vcmpgtq_m_n_f32): Likewise.
8580 (__arm_vcmpleq_m_f32): Likewise.
8581 (__arm_vcmpleq_m_n_f32): Likewise.
8582 (__arm_vcmpltq_m_f32): Likewise.
8583 (__arm_vcmpltq_m_n_f32): Likewise.
8584 (__arm_vcmpneq_m_f32): Likewise.
8585 (__arm_vcmpneq_m_n_f32): Likewise.
8586 (__arm_vcvtmq_m_u32_f32): Likewise.
8587 (__arm_vcvtnq_m_u32_f32): Likewise.
8588 (__arm_vcvtpq_m_u32_f32): Likewise.
8589 (__arm_vcvtq_m_u32_f32): Likewise.
8590 (vcvtq_m): Define polymorphic variant.
8591 (vabsq_m): Likewise.
8593 (vcmlaq_rot180): Likewise.
8594 (vcmlaq_rot270): Likewise.
8595 (vcmlaq_rot90): Likewise.
8596 (vcmpeqq_m_n): Likewise.
8597 (vcmpgeq_m_n): Likewise.
8598 (vrndxq_m): Likewise.
8599 (vrndq_m): Likewise.
8600 (vrndpq_m): Likewise.
8601 (vcmpgtq_m_n): Likewise.
8602 (vcmpgtq_m): Likewise.
8603 (vcmpleq_m): Likewise.
8604 (vcmpleq_m_n): Likewise.
8605 (vcmpltq_m_n): Likewise.
8606 (vcmpltq_m): Likewise.
8607 (vcmpneq_m): Likewise.
8608 (vcmpneq_m_n): Likewise.
8609 (vcvtbq_m): Likewise.
8610 (vcvttq_m): Likewise.
8611 (vcvtmq_m): Likewise.
8612 (vcvtnq_m): Likewise.
8613 (vcvtpq_m): Likewise.
8614 (vdupq_m_n): Likewise.
8615 (vfmaq_n): Likewise.
8617 (vfmasq_n): Likewise.
8619 (vmaxnmaq_m): Likewise.
8620 (vmaxnmavq_m): Likewise.
8621 (vmaxnmvq_m): Likewise.
8622 (vmaxnmavq_p): Likewise.
8623 (vmaxnmvq_p): Likewise.
8624 (vminnmaq_m): Likewise.
8625 (vminnmavq_p): Likewise.
8626 (vminnmvq_p): Likewise.
8627 (vrndnq_m): Likewise.
8628 (vrndaq_m): Likewise.
8629 (vrndmq_m): Likewise.
8630 (vrev64q_m): Likewise.
8631 (vrev32q_m): Likewise.
8633 (vnegq_m): Likewise.
8634 (vcmpgeq_m): Likewise.
8635 (vshrntq_n): Likewise.
8636 (vrshrntq_n): Likewise.
8637 (vmovlbq_m): Likewise.
8638 (vmovnbq_m): Likewise.
8639 (vmovntq_m): Likewise.
8640 (vmvnq_m_n): Likewise.
8641 (vmvnq_m): Likewise.
8642 (vshrnbq_n): Likewise.
8643 (vrshrnbq_n): Likewise.
8644 (vqshruntq_n): Likewise.
8645 (vrev16q_m): Likewise.
8646 (vqshrunbq_n): Likewise.
8647 (vqshrntq_n): Likewise.
8648 (vqrshruntq_n): Likewise.
8649 (vqrshrntq_n): Likewise.
8650 (vqshrnbq_n): Likewise.
8651 (vqmovuntq_m): Likewise.
8652 (vqmovntq_m): Likewise.
8653 (vqmovnbq_m): Likewise.
8654 (vorrq_m_n): Likewise.
8655 (vmovltq_m): Likewise.
8656 (vqmovunbq_m): Likewise.
8657 (vaddlvaq_p): Likewise.
8658 (vmlaldavaq): Likewise.
8659 (vmlaldavaxq): Likewise.
8660 (vmlaldavq_p): Likewise.
8661 (vmlaldavxq_p): Likewise.
8662 (vmlsldavaq): Likewise.
8663 (vmlsldavaxq): Likewise.
8664 (vmlsldavq_p): Likewise.
8665 (vmlsldavxq_p): Likewise.
8666 (vrmlaldavhaxq): Likewise.
8667 (vrmlaldavhq_p): Likewise.
8668 (vrmlaldavhxq_p): Likewise.
8669 (vrmlsldavhaq): Likewise.
8670 (vrmlsldavhaxq): Likewise.
8671 (vrmlsldavhq_p): Likewise.
8672 (vrmlsldavhxq_p): Likewise.
8673 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use
8675 (TERNOP_NONE_NONE_NONE_IMM): Likewise.
8676 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
8677 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
8678 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
8679 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise.
8680 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise.
8681 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
8682 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
8683 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
8684 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator.
8685 (MVE_pred3): Likewise.
8686 (MVE_constraint1): Likewise.
8687 (MVE_pred1): Likewise.
8688 (VMLALDAVQ_P): Define iterator.
8689 (VQMOVNBQ_M): Likewise.
8690 (VMOVLTQ_M): Likewise.
8691 (VMOVNBQ_M): Likewise.
8692 (VRSHRNTQ_N): Likewise.
8693 (VORRQ_M_N): Likewise.
8694 (VREV32Q_M): Likewise.
8695 (VREV16Q_M): Likewise.
8696 (VQRSHRNTQ_N): Likewise.
8697 (VMOVNTQ_M): Likewise.
8698 (VMOVLBQ_M): Likewise.
8699 (VMLALDAVAQ): Likewise.
8700 (VQSHRNBQ_N): Likewise.
8701 (VSHRNBQ_N): Likewise.
8702 (VRSHRNBQ_N): Likewise.
8703 (VMLALDAVXQ_P): Likewise.
8704 (VQMOVNTQ_M): Likewise.
8705 (VMVNQ_M_N): Likewise.
8706 (VQSHRNTQ_N): Likewise.
8707 (VMLALDAVAXQ): Likewise.
8708 (VSHRNTQ_N): Likewise.
8709 (VCVTMQ_M): Likewise.
8710 (VCVTNQ_M): Likewise.
8711 (VCVTPQ_M): Likewise.
8712 (VCVTQ_M_N_FROM_F): Likewise.
8713 (VCVTQ_M_FROM_F): Likewise.
8714 (VRMLALDAVHQ_P): Likewise.
8715 (VADDLVAQ_P): Likewise.
8716 (mve_vrndq_m_f<mode>): Define RTL pattern.
8717 (mve_vabsq_m_f<mode>): Likewise.
8718 (mve_vaddlvaq_p_<supf>v4si): Likewise.
8719 (mve_vcmlaq_f<mode>): Likewise.
8720 (mve_vcmlaq_rot180_f<mode>): Likewise.
8721 (mve_vcmlaq_rot270_f<mode>): Likewise.
8722 (mve_vcmlaq_rot90_f<mode>): Likewise.
8723 (mve_vcmpeqq_m_n_f<mode>): Likewise.
8724 (mve_vcmpgeq_m_f<mode>): Likewise.
8725 (mve_vcmpgeq_m_n_f<mode>): Likewise.
8726 (mve_vcmpgtq_m_f<mode>): Likewise.
8727 (mve_vcmpgtq_m_n_f<mode>): Likewise.
8728 (mve_vcmpleq_m_f<mode>): Likewise.
8729 (mve_vcmpleq_m_n_f<mode>): Likewise.
8730 (mve_vcmpltq_m_f<mode>): Likewise.
8731 (mve_vcmpltq_m_n_f<mode>): Likewise.
8732 (mve_vcmpneq_m_f<mode>): Likewise.
8733 (mve_vcmpneq_m_n_f<mode>): Likewise.
8734 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
8735 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
8736 (mve_vcvttq_m_f16_f32v8hf): Likewise.
8737 (mve_vcvttq_m_f32_f16v4sf): Likewise.
8738 (mve_vdupq_m_n_f<mode>): Likewise.
8739 (mve_vfmaq_f<mode>): Likewise.
8740 (mve_vfmaq_n_f<mode>): Likewise.
8741 (mve_vfmasq_n_f<mode>): Likewise.
8742 (mve_vfmsq_f<mode>): Likewise.
8743 (mve_vmaxnmaq_m_f<mode>): Likewise.
8744 (mve_vmaxnmavq_p_f<mode>): Likewise.
8745 (mve_vmaxnmvq_p_f<mode>): Likewise.
8746 (mve_vminnmaq_m_f<mode>): Likewise.
8747 (mve_vminnmavq_p_f<mode>): Likewise.
8748 (mve_vminnmvq_p_f<mode>): Likewise.
8749 (mve_vmlaldavaq_<supf><mode>): Likewise.
8750 (mve_vmlaldavaxq_<supf><mode>): Likewise.
8751 (mve_vmlaldavq_p_<supf><mode>): Likewise.
8752 (mve_vmlaldavxq_p_<supf><mode>): Likewise.
8753 (mve_vmlsldavaq_s<mode>): Likewise.
8754 (mve_vmlsldavaxq_s<mode>): Likewise.
8755 (mve_vmlsldavq_p_s<mode>): Likewise.
8756 (mve_vmlsldavxq_p_s<mode>): Likewise.
8757 (mve_vmovlbq_m_<supf><mode>): Likewise.
8758 (mve_vmovltq_m_<supf><mode>): Likewise.
8759 (mve_vmovnbq_m_<supf><mode>): Likewise.
8760 (mve_vmovntq_m_<supf><mode>): Likewise.
8761 (mve_vmvnq_m_n_<supf><mode>): Likewise.
8762 (mve_vnegq_m_f<mode>): Likewise.
8763 (mve_vorrq_m_n_<supf><mode>): Likewise.
8764 (mve_vpselq_f<mode>): Likewise.
8765 (mve_vqmovnbq_m_<supf><mode>): Likewise.
8766 (mve_vqmovntq_m_<supf><mode>): Likewise.
8767 (mve_vqmovunbq_m_s<mode>): Likewise.
8768 (mve_vqmovuntq_m_s<mode>): Likewise.
8769 (mve_vqrshrntq_n_<supf><mode>): Likewise.
8770 (mve_vqrshruntq_n_s<mode>): Likewise.
8771 (mve_vqshrnbq_n_<supf><mode>): Likewise.
8772 (mve_vqshrntq_n_<supf><mode>): Likewise.
8773 (mve_vqshrunbq_n_s<mode>): Likewise.
8774 (mve_vqshruntq_n_s<mode>): Likewise.
8775 (mve_vrev32q_m_fv8hf): Likewise.
8776 (mve_vrev32q_m_<supf><mode>): Likewise.
8777 (mve_vrev64q_m_f<mode>): Likewise.
8778 (mve_vrmlaldavhaxq_sv4si): Likewise.
8779 (mve_vrmlaldavhxq_p_sv4si): Likewise.
8780 (mve_vrmlsldavhaxq_sv4si): Likewise.
8781 (mve_vrmlsldavhq_p_sv4si): Likewise.
8782 (mve_vrmlsldavhxq_p_sv4si): Likewise.
8783 (mve_vrndaq_m_f<mode>): Likewise.
8784 (mve_vrndmq_m_f<mode>): Likewise.
8785 (mve_vrndnq_m_f<mode>): Likewise.
8786 (mve_vrndpq_m_f<mode>): Likewise.
8787 (mve_vrndxq_m_f<mode>): Likewise.
8788 (mve_vrshrnbq_n_<supf><mode>): Likewise.
8789 (mve_vrshrntq_n_<supf><mode>): Likewise.
8790 (mve_vshrnbq_n_<supf><mode>): Likewise.
8791 (mve_vshrntq_n_<supf><mode>): Likewise.
8792 (mve_vcvtmq_m_<supf><mode>): Likewise.
8793 (mve_vcvtpq_m_<supf><mode>): Likewise.
8794 (mve_vcvtnq_m_<supf><mode>): Likewise.
8795 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
8796 (mve_vrev16q_m_<supf>v16qi): Likewise.
8797 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
8798 (mve_vrmlaldavhq_p_<supf>v4si): Likewise.
8799 (mve_vrmlsldavhaq_sv4si): Likewise.
8801 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8802 Mihail Ionescu <mihail.ionescu@arm.com>
8803 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8805 * config/arm/arm_mve.h (vpselq_u8): Define macro.
8806 (vpselq_s8): Likewise.
8807 (vrev64q_m_u8): Likewise.
8808 (vqrdmlashq_n_u8): Likewise.
8809 (vqrdmlahq_n_u8): Likewise.
8810 (vqdmlahq_n_u8): Likewise.
8811 (vmvnq_m_u8): Likewise.
8812 (vmlasq_n_u8): Likewise.
8813 (vmlaq_n_u8): Likewise.
8814 (vmladavq_p_u8): Likewise.
8815 (vmladavaq_u8): Likewise.
8816 (vminvq_p_u8): Likewise.
8817 (vmaxvq_p_u8): Likewise.
8818 (vdupq_m_n_u8): Likewise.
8819 (vcmpneq_m_u8): Likewise.
8820 (vcmpneq_m_n_u8): Likewise.
8821 (vcmphiq_m_u8): Likewise.
8822 (vcmphiq_m_n_u8): Likewise.
8823 (vcmpeqq_m_u8): Likewise.
8824 (vcmpeqq_m_n_u8): Likewise.
8825 (vcmpcsq_m_u8): Likewise.
8826 (vcmpcsq_m_n_u8): Likewise.
8827 (vclzq_m_u8): Likewise.
8828 (vaddvaq_p_u8): Likewise.
8829 (vsriq_n_u8): Likewise.
8830 (vsliq_n_u8): Likewise.
8831 (vshlq_m_r_u8): Likewise.
8832 (vrshlq_m_n_u8): Likewise.
8833 (vqshlq_m_r_u8): Likewise.
8834 (vqrshlq_m_n_u8): Likewise.
8835 (vminavq_p_s8): Likewise.
8836 (vminaq_m_s8): Likewise.
8837 (vmaxavq_p_s8): Likewise.
8838 (vmaxaq_m_s8): Likewise.
8839 (vcmpneq_m_s8): Likewise.
8840 (vcmpneq_m_n_s8): Likewise.
8841 (vcmpltq_m_s8): Likewise.
8842 (vcmpltq_m_n_s8): Likewise.
8843 (vcmpleq_m_s8): Likewise.
8844 (vcmpleq_m_n_s8): Likewise.
8845 (vcmpgtq_m_s8): Likewise.
8846 (vcmpgtq_m_n_s8): Likewise.
8847 (vcmpgeq_m_s8): Likewise.
8848 (vcmpgeq_m_n_s8): Likewise.
8849 (vcmpeqq_m_s8): Likewise.
8850 (vcmpeqq_m_n_s8): Likewise.
8851 (vshlq_m_r_s8): Likewise.
8852 (vrshlq_m_n_s8): Likewise.
8853 (vrev64q_m_s8): Likewise.
8854 (vqshlq_m_r_s8): Likewise.
8855 (vqrshlq_m_n_s8): Likewise.
8856 (vqnegq_m_s8): Likewise.
8857 (vqabsq_m_s8): Likewise.
8858 (vnegq_m_s8): Likewise.
8859 (vmvnq_m_s8): Likewise.
8860 (vmlsdavxq_p_s8): Likewise.
8861 (vmlsdavq_p_s8): Likewise.
8862 (vmladavxq_p_s8): Likewise.
8863 (vmladavq_p_s8): Likewise.
8864 (vminvq_p_s8): Likewise.
8865 (vmaxvq_p_s8): Likewise.
8866 (vdupq_m_n_s8): Likewise.
8867 (vclzq_m_s8): Likewise.
8868 (vclsq_m_s8): Likewise.
8869 (vaddvaq_p_s8): Likewise.
8870 (vabsq_m_s8): Likewise.
8871 (vqrdmlsdhxq_s8): Likewise.
8872 (vqrdmlsdhq_s8): Likewise.
8873 (vqrdmlashq_n_s8): Likewise.
8874 (vqrdmlahq_n_s8): Likewise.
8875 (vqrdmladhxq_s8): Likewise.
8876 (vqrdmladhq_s8): Likewise.
8877 (vqdmlsdhxq_s8): Likewise.
8878 (vqdmlsdhq_s8): Likewise.
8879 (vqdmlahq_n_s8): Likewise.
8880 (vqdmladhxq_s8): Likewise.
8881 (vqdmladhq_s8): Likewise.
8882 (vmlsdavaxq_s8): Likewise.
8883 (vmlsdavaq_s8): Likewise.
8884 (vmlasq_n_s8): Likewise.
8885 (vmlaq_n_s8): Likewise.
8886 (vmladavaxq_s8): Likewise.
8887 (vmladavaq_s8): Likewise.
8888 (vsriq_n_s8): Likewise.
8889 (vsliq_n_s8): Likewise.
8890 (vpselq_u16): Likewise.
8891 (vpselq_s16): Likewise.
8892 (vrev64q_m_u16): Likewise.
8893 (vqrdmlashq_n_u16): Likewise.
8894 (vqrdmlahq_n_u16): Likewise.
8895 (vqdmlahq_n_u16): Likewise.
8896 (vmvnq_m_u16): Likewise.
8897 (vmlasq_n_u16): Likewise.
8898 (vmlaq_n_u16): Likewise.
8899 (vmladavq_p_u16): Likewise.
8900 (vmladavaq_u16): Likewise.
8901 (vminvq_p_u16): Likewise.
8902 (vmaxvq_p_u16): Likewise.
8903 (vdupq_m_n_u16): Likewise.
8904 (vcmpneq_m_u16): Likewise.
8905 (vcmpneq_m_n_u16): Likewise.
8906 (vcmphiq_m_u16): Likewise.
8907 (vcmphiq_m_n_u16): Likewise.
8908 (vcmpeqq_m_u16): Likewise.
8909 (vcmpeqq_m_n_u16): Likewise.
8910 (vcmpcsq_m_u16): Likewise.
8911 (vcmpcsq_m_n_u16): Likewise.
8912 (vclzq_m_u16): Likewise.
8913 (vaddvaq_p_u16): Likewise.
8914 (vsriq_n_u16): Likewise.
8915 (vsliq_n_u16): Likewise.
8916 (vshlq_m_r_u16): Likewise.
8917 (vrshlq_m_n_u16): Likewise.
8918 (vqshlq_m_r_u16): Likewise.
8919 (vqrshlq_m_n_u16): Likewise.
8920 (vminavq_p_s16): Likewise.
8921 (vminaq_m_s16): Likewise.
8922 (vmaxavq_p_s16): Likewise.
8923 (vmaxaq_m_s16): Likewise.
8924 (vcmpneq_m_s16): Likewise.
8925 (vcmpneq_m_n_s16): Likewise.
8926 (vcmpltq_m_s16): Likewise.
8927 (vcmpltq_m_n_s16): Likewise.
8928 (vcmpleq_m_s16): Likewise.
8929 (vcmpleq_m_n_s16): Likewise.
8930 (vcmpgtq_m_s16): Likewise.
8931 (vcmpgtq_m_n_s16): Likewise.
8932 (vcmpgeq_m_s16): Likewise.
8933 (vcmpgeq_m_n_s16): Likewise.
8934 (vcmpeqq_m_s16): Likewise.
8935 (vcmpeqq_m_n_s16): Likewise.
8936 (vshlq_m_r_s16): Likewise.
8937 (vrshlq_m_n_s16): Likewise.
8938 (vrev64q_m_s16): Likewise.
8939 (vqshlq_m_r_s16): Likewise.
8940 (vqrshlq_m_n_s16): Likewise.
8941 (vqnegq_m_s16): Likewise.
8942 (vqabsq_m_s16): Likewise.
8943 (vnegq_m_s16): Likewise.
8944 (vmvnq_m_s16): Likewise.
8945 (vmlsdavxq_p_s16): Likewise.
8946 (vmlsdavq_p_s16): Likewise.
8947 (vmladavxq_p_s16): Likewise.
8948 (vmladavq_p_s16): Likewise.
8949 (vminvq_p_s16): Likewise.
8950 (vmaxvq_p_s16): Likewise.
8951 (vdupq_m_n_s16): Likewise.
8952 (vclzq_m_s16): Likewise.
8953 (vclsq_m_s16): Likewise.
8954 (vaddvaq_p_s16): Likewise.
8955 (vabsq_m_s16): Likewise.
8956 (vqrdmlsdhxq_s16): Likewise.
8957 (vqrdmlsdhq_s16): Likewise.
8958 (vqrdmlashq_n_s16): Likewise.
8959 (vqrdmlahq_n_s16): Likewise.
8960 (vqrdmladhxq_s16): Likewise.
8961 (vqrdmladhq_s16): Likewise.
8962 (vqdmlsdhxq_s16): Likewise.
8963 (vqdmlsdhq_s16): Likewise.
8964 (vqdmlahq_n_s16): Likewise.
8965 (vqdmladhxq_s16): Likewise.
8966 (vqdmladhq_s16): Likewise.
8967 (vmlsdavaxq_s16): Likewise.
8968 (vmlsdavaq_s16): Likewise.
8969 (vmlasq_n_s16): Likewise.
8970 (vmlaq_n_s16): Likewise.
8971 (vmladavaxq_s16): Likewise.
8972 (vmladavaq_s16): Likewise.
8973 (vsriq_n_s16): Likewise.
8974 (vsliq_n_s16): Likewise.
8975 (vpselq_u32): Likewise.
8976 (vpselq_s32): Likewise.
8977 (vrev64q_m_u32): Likewise.
8978 (vqrdmlashq_n_u32): Likewise.
8979 (vqrdmlahq_n_u32): Likewise.
8980 (vqdmlahq_n_u32): Likewise.
8981 (vmvnq_m_u32): Likewise.
8982 (vmlasq_n_u32): Likewise.
8983 (vmlaq_n_u32): Likewise.
8984 (vmladavq_p_u32): Likewise.
8985 (vmladavaq_u32): Likewise.
8986 (vminvq_p_u32): Likewise.
8987 (vmaxvq_p_u32): Likewise.
8988 (vdupq_m_n_u32): Likewise.
8989 (vcmpneq_m_u32): Likewise.
8990 (vcmpneq_m_n_u32): Likewise.
8991 (vcmphiq_m_u32): Likewise.
8992 (vcmphiq_m_n_u32): Likewise.
8993 (vcmpeqq_m_u32): Likewise.
8994 (vcmpeqq_m_n_u32): Likewise.
8995 (vcmpcsq_m_u32): Likewise.
8996 (vcmpcsq_m_n_u32): Likewise.
8997 (vclzq_m_u32): Likewise.
8998 (vaddvaq_p_u32): Likewise.
8999 (vsriq_n_u32): Likewise.
9000 (vsliq_n_u32): Likewise.
9001 (vshlq_m_r_u32): Likewise.
9002 (vrshlq_m_n_u32): Likewise.
9003 (vqshlq_m_r_u32): Likewise.
9004 (vqrshlq_m_n_u32): Likewise.
9005 (vminavq_p_s32): Likewise.
9006 (vminaq_m_s32): Likewise.
9007 (vmaxavq_p_s32): Likewise.
9008 (vmaxaq_m_s32): Likewise.
9009 (vcmpneq_m_s32): Likewise.
9010 (vcmpneq_m_n_s32): Likewise.
9011 (vcmpltq_m_s32): Likewise.
9012 (vcmpltq_m_n_s32): Likewise.
9013 (vcmpleq_m_s32): Likewise.
9014 (vcmpleq_m_n_s32): Likewise.
9015 (vcmpgtq_m_s32): Likewise.
9016 (vcmpgtq_m_n_s32): Likewise.
9017 (vcmpgeq_m_s32): Likewise.
9018 (vcmpgeq_m_n_s32): Likewise.
9019 (vcmpeqq_m_s32): Likewise.
9020 (vcmpeqq_m_n_s32): Likewise.
9021 (vshlq_m_r_s32): Likewise.
9022 (vrshlq_m_n_s32): Likewise.
9023 (vrev64q_m_s32): Likewise.
9024 (vqshlq_m_r_s32): Likewise.
9025 (vqrshlq_m_n_s32): Likewise.
9026 (vqnegq_m_s32): Likewise.
9027 (vqabsq_m_s32): Likewise.
9028 (vnegq_m_s32): Likewise.
9029 (vmvnq_m_s32): Likewise.
9030 (vmlsdavxq_p_s32): Likewise.
9031 (vmlsdavq_p_s32): Likewise.
9032 (vmladavxq_p_s32): Likewise.
9033 (vmladavq_p_s32): Likewise.
9034 (vminvq_p_s32): Likewise.
9035 (vmaxvq_p_s32): Likewise.
9036 (vdupq_m_n_s32): Likewise.
9037 (vclzq_m_s32): Likewise.
9038 (vclsq_m_s32): Likewise.
9039 (vaddvaq_p_s32): Likewise.
9040 (vabsq_m_s32): Likewise.
9041 (vqrdmlsdhxq_s32): Likewise.
9042 (vqrdmlsdhq_s32): Likewise.
9043 (vqrdmlashq_n_s32): Likewise.
9044 (vqrdmlahq_n_s32): Likewise.
9045 (vqrdmladhxq_s32): Likewise.
9046 (vqrdmladhq_s32): Likewise.
9047 (vqdmlsdhxq_s32): Likewise.
9048 (vqdmlsdhq_s32): Likewise.
9049 (vqdmlahq_n_s32): Likewise.
9050 (vqdmladhxq_s32): Likewise.
9051 (vqdmladhq_s32): Likewise.
9052 (vmlsdavaxq_s32): Likewise.
9053 (vmlsdavaq_s32): Likewise.
9054 (vmlasq_n_s32): Likewise.
9055 (vmlaq_n_s32): Likewise.
9056 (vmladavaxq_s32): Likewise.
9057 (vmladavaq_s32): Likewise.
9058 (vsriq_n_s32): Likewise.
9059 (vsliq_n_s32): Likewise.
9060 (vpselq_u64): Likewise.
9061 (vpselq_s64): Likewise.
9062 (__arm_vpselq_u8): Define intrinsic.
9063 (__arm_vpselq_s8): Likewise.
9064 (__arm_vrev64q_m_u8): Likewise.
9065 (__arm_vqrdmlashq_n_u8): Likewise.
9066 (__arm_vqrdmlahq_n_u8): Likewise.
9067 (__arm_vqdmlahq_n_u8): Likewise.
9068 (__arm_vmvnq_m_u8): Likewise.
9069 (__arm_vmlasq_n_u8): Likewise.
9070 (__arm_vmlaq_n_u8): Likewise.
9071 (__arm_vmladavq_p_u8): Likewise.
9072 (__arm_vmladavaq_u8): Likewise.
9073 (__arm_vminvq_p_u8): Likewise.
9074 (__arm_vmaxvq_p_u8): Likewise.
9075 (__arm_vdupq_m_n_u8): Likewise.
9076 (__arm_vcmpneq_m_u8): Likewise.
9077 (__arm_vcmpneq_m_n_u8): Likewise.
9078 (__arm_vcmphiq_m_u8): Likewise.
9079 (__arm_vcmphiq_m_n_u8): Likewise.
9080 (__arm_vcmpeqq_m_u8): Likewise.
9081 (__arm_vcmpeqq_m_n_u8): Likewise.
9082 (__arm_vcmpcsq_m_u8): Likewise.
9083 (__arm_vcmpcsq_m_n_u8): Likewise.
9084 (__arm_vclzq_m_u8): Likewise.
9085 (__arm_vaddvaq_p_u8): Likewise.
9086 (__arm_vsriq_n_u8): Likewise.
9087 (__arm_vsliq_n_u8): Likewise.
9088 (__arm_vshlq_m_r_u8): Likewise.
9089 (__arm_vrshlq_m_n_u8): Likewise.
9090 (__arm_vqshlq_m_r_u8): Likewise.
9091 (__arm_vqrshlq_m_n_u8): Likewise.
9092 (__arm_vminavq_p_s8): Likewise.
9093 (__arm_vminaq_m_s8): Likewise.
9094 (__arm_vmaxavq_p_s8): Likewise.
9095 (__arm_vmaxaq_m_s8): Likewise.
9096 (__arm_vcmpneq_m_s8): Likewise.
9097 (__arm_vcmpneq_m_n_s8): Likewise.
9098 (__arm_vcmpltq_m_s8): Likewise.
9099 (__arm_vcmpltq_m_n_s8): Likewise.
9100 (__arm_vcmpleq_m_s8): Likewise.
9101 (__arm_vcmpleq_m_n_s8): Likewise.
9102 (__arm_vcmpgtq_m_s8): Likewise.
9103 (__arm_vcmpgtq_m_n_s8): Likewise.
9104 (__arm_vcmpgeq_m_s8): Likewise.
9105 (__arm_vcmpgeq_m_n_s8): Likewise.
9106 (__arm_vcmpeqq_m_s8): Likewise.
9107 (__arm_vcmpeqq_m_n_s8): Likewise.
9108 (__arm_vshlq_m_r_s8): Likewise.
9109 (__arm_vrshlq_m_n_s8): Likewise.
9110 (__arm_vrev64q_m_s8): Likewise.
9111 (__arm_vqshlq_m_r_s8): Likewise.
9112 (__arm_vqrshlq_m_n_s8): Likewise.
9113 (__arm_vqnegq_m_s8): Likewise.
9114 (__arm_vqabsq_m_s8): Likewise.
9115 (__arm_vnegq_m_s8): Likewise.
9116 (__arm_vmvnq_m_s8): Likewise.
9117 (__arm_vmlsdavxq_p_s8): Likewise.
9118 (__arm_vmlsdavq_p_s8): Likewise.
9119 (__arm_vmladavxq_p_s8): Likewise.
9120 (__arm_vmladavq_p_s8): Likewise.
9121 (__arm_vminvq_p_s8): Likewise.
9122 (__arm_vmaxvq_p_s8): Likewise.
9123 (__arm_vdupq_m_n_s8): Likewise.
9124 (__arm_vclzq_m_s8): Likewise.
9125 (__arm_vclsq_m_s8): Likewise.
9126 (__arm_vaddvaq_p_s8): Likewise.
9127 (__arm_vabsq_m_s8): Likewise.
9128 (__arm_vqrdmlsdhxq_s8): Likewise.
9129 (__arm_vqrdmlsdhq_s8): Likewise.
9130 (__arm_vqrdmlashq_n_s8): Likewise.
9131 (__arm_vqrdmlahq_n_s8): Likewise.
9132 (__arm_vqrdmladhxq_s8): Likewise.
9133 (__arm_vqrdmladhq_s8): Likewise.
9134 (__arm_vqdmlsdhxq_s8): Likewise.
9135 (__arm_vqdmlsdhq_s8): Likewise.
9136 (__arm_vqdmlahq_n_s8): Likewise.
9137 (__arm_vqdmladhxq_s8): Likewise.
9138 (__arm_vqdmladhq_s8): Likewise.
9139 (__arm_vmlsdavaxq_s8): Likewise.
9140 (__arm_vmlsdavaq_s8): Likewise.
9141 (__arm_vmlasq_n_s8): Likewise.
9142 (__arm_vmlaq_n_s8): Likewise.
9143 (__arm_vmladavaxq_s8): Likewise.
9144 (__arm_vmladavaq_s8): Likewise.
9145 (__arm_vsriq_n_s8): Likewise.
9146 (__arm_vsliq_n_s8): Likewise.
9147 (__arm_vpselq_u16): Likewise.
9148 (__arm_vpselq_s16): Likewise.
9149 (__arm_vrev64q_m_u16): Likewise.
9150 (__arm_vqrdmlashq_n_u16): Likewise.
9151 (__arm_vqrdmlahq_n_u16): Likewise.
9152 (__arm_vqdmlahq_n_u16): Likewise.
9153 (__arm_vmvnq_m_u16): Likewise.
9154 (__arm_vmlasq_n_u16): Likewise.
9155 (__arm_vmlaq_n_u16): Likewise.
9156 (__arm_vmladavq_p_u16): Likewise.
9157 (__arm_vmladavaq_u16): Likewise.
9158 (__arm_vminvq_p_u16): Likewise.
9159 (__arm_vmaxvq_p_u16): Likewise.
9160 (__arm_vdupq_m_n_u16): Likewise.
9161 (__arm_vcmpneq_m_u16): Likewise.
9162 (__arm_vcmpneq_m_n_u16): Likewise.
9163 (__arm_vcmphiq_m_u16): Likewise.
9164 (__arm_vcmphiq_m_n_u16): Likewise.
9165 (__arm_vcmpeqq_m_u16): Likewise.
9166 (__arm_vcmpeqq_m_n_u16): Likewise.
9167 (__arm_vcmpcsq_m_u16): Likewise.
9168 (__arm_vcmpcsq_m_n_u16): Likewise.
9169 (__arm_vclzq_m_u16): Likewise.
9170 (__arm_vaddvaq_p_u16): Likewise.
9171 (__arm_vsriq_n_u16): Likewise.
9172 (__arm_vsliq_n_u16): Likewise.
9173 (__arm_vshlq_m_r_u16): Likewise.
9174 (__arm_vrshlq_m_n_u16): Likewise.
9175 (__arm_vqshlq_m_r_u16): Likewise.
9176 (__arm_vqrshlq_m_n_u16): Likewise.
9177 (__arm_vminavq_p_s16): Likewise.
9178 (__arm_vminaq_m_s16): Likewise.
9179 (__arm_vmaxavq_p_s16): Likewise.
9180 (__arm_vmaxaq_m_s16): Likewise.
9181 (__arm_vcmpneq_m_s16): Likewise.
9182 (__arm_vcmpneq_m_n_s16): Likewise.
9183 (__arm_vcmpltq_m_s16): Likewise.
9184 (__arm_vcmpltq_m_n_s16): Likewise.
9185 (__arm_vcmpleq_m_s16): Likewise.
9186 (__arm_vcmpleq_m_n_s16): Likewise.
9187 (__arm_vcmpgtq_m_s16): Likewise.
9188 (__arm_vcmpgtq_m_n_s16): Likewise.
9189 (__arm_vcmpgeq_m_s16): Likewise.
9190 (__arm_vcmpgeq_m_n_s16): Likewise.
9191 (__arm_vcmpeqq_m_s16): Likewise.
9192 (__arm_vcmpeqq_m_n_s16): Likewise.
9193 (__arm_vshlq_m_r_s16): Likewise.
9194 (__arm_vrshlq_m_n_s16): Likewise.
9195 (__arm_vrev64q_m_s16): Likewise.
9196 (__arm_vqshlq_m_r_s16): Likewise.
9197 (__arm_vqrshlq_m_n_s16): Likewise.
9198 (__arm_vqnegq_m_s16): Likewise.
9199 (__arm_vqabsq_m_s16): Likewise.
9200 (__arm_vnegq_m_s16): Likewise.
9201 (__arm_vmvnq_m_s16): Likewise.
9202 (__arm_vmlsdavxq_p_s16): Likewise.
9203 (__arm_vmlsdavq_p_s16): Likewise.
9204 (__arm_vmladavxq_p_s16): Likewise.
9205 (__arm_vmladavq_p_s16): Likewise.
9206 (__arm_vminvq_p_s16): Likewise.
9207 (__arm_vmaxvq_p_s16): Likewise.
9208 (__arm_vdupq_m_n_s16): Likewise.
9209 (__arm_vclzq_m_s16): Likewise.
9210 (__arm_vclsq_m_s16): Likewise.
9211 (__arm_vaddvaq_p_s16): Likewise.
9212 (__arm_vabsq_m_s16): Likewise.
9213 (__arm_vqrdmlsdhxq_s16): Likewise.
9214 (__arm_vqrdmlsdhq_s16): Likewise.
9215 (__arm_vqrdmlashq_n_s16): Likewise.
9216 (__arm_vqrdmlahq_n_s16): Likewise.
9217 (__arm_vqrdmladhxq_s16): Likewise.
9218 (__arm_vqrdmladhq_s16): Likewise.
9219 (__arm_vqdmlsdhxq_s16): Likewise.
9220 (__arm_vqdmlsdhq_s16): Likewise.
9221 (__arm_vqdmlahq_n_s16): Likewise.
9222 (__arm_vqdmladhxq_s16): Likewise.
9223 (__arm_vqdmladhq_s16): Likewise.
9224 (__arm_vmlsdavaxq_s16): Likewise.
9225 (__arm_vmlsdavaq_s16): Likewise.
9226 (__arm_vmlasq_n_s16): Likewise.
9227 (__arm_vmlaq_n_s16): Likewise.
9228 (__arm_vmladavaxq_s16): Likewise.
9229 (__arm_vmladavaq_s16): Likewise.
9230 (__arm_vsriq_n_s16): Likewise.
9231 (__arm_vsliq_n_s16): Likewise.
9232 (__arm_vpselq_u32): Likewise.
9233 (__arm_vpselq_s32): Likewise.
9234 (__arm_vrev64q_m_u32): Likewise.
9235 (__arm_vqrdmlashq_n_u32): Likewise.
9236 (__arm_vqrdmlahq_n_u32): Likewise.
9237 (__arm_vqdmlahq_n_u32): Likewise.
9238 (__arm_vmvnq_m_u32): Likewise.
9239 (__arm_vmlasq_n_u32): Likewise.
9240 (__arm_vmlaq_n_u32): Likewise.
9241 (__arm_vmladavq_p_u32): Likewise.
9242 (__arm_vmladavaq_u32): Likewise.
9243 (__arm_vminvq_p_u32): Likewise.
9244 (__arm_vmaxvq_p_u32): Likewise.
9245 (__arm_vdupq_m_n_u32): Likewise.
9246 (__arm_vcmpneq_m_u32): Likewise.
9247 (__arm_vcmpneq_m_n_u32): Likewise.
9248 (__arm_vcmphiq_m_u32): Likewise.
9249 (__arm_vcmphiq_m_n_u32): Likewise.
9250 (__arm_vcmpeqq_m_u32): Likewise.
9251 (__arm_vcmpeqq_m_n_u32): Likewise.
9252 (__arm_vcmpcsq_m_u32): Likewise.
9253 (__arm_vcmpcsq_m_n_u32): Likewise.
9254 (__arm_vclzq_m_u32): Likewise.
9255 (__arm_vaddvaq_p_u32): Likewise.
9256 (__arm_vsriq_n_u32): Likewise.
9257 (__arm_vsliq_n_u32): Likewise.
9258 (__arm_vshlq_m_r_u32): Likewise.
9259 (__arm_vrshlq_m_n_u32): Likewise.
9260 (__arm_vqshlq_m_r_u32): Likewise.
9261 (__arm_vqrshlq_m_n_u32): Likewise.
9262 (__arm_vminavq_p_s32): Likewise.
9263 (__arm_vminaq_m_s32): Likewise.
9264 (__arm_vmaxavq_p_s32): Likewise.
9265 (__arm_vmaxaq_m_s32): Likewise.
9266 (__arm_vcmpneq_m_s32): Likewise.
9267 (__arm_vcmpneq_m_n_s32): Likewise.
9268 (__arm_vcmpltq_m_s32): Likewise.
9269 (__arm_vcmpltq_m_n_s32): Likewise.
9270 (__arm_vcmpleq_m_s32): Likewise.
9271 (__arm_vcmpleq_m_n_s32): Likewise.
9272 (__arm_vcmpgtq_m_s32): Likewise.
9273 (__arm_vcmpgtq_m_n_s32): Likewise.
9274 (__arm_vcmpgeq_m_s32): Likewise.
9275 (__arm_vcmpgeq_m_n_s32): Likewise.
9276 (__arm_vcmpeqq_m_s32): Likewise.
9277 (__arm_vcmpeqq_m_n_s32): Likewise.
9278 (__arm_vshlq_m_r_s32): Likewise.
9279 (__arm_vrshlq_m_n_s32): Likewise.
9280 (__arm_vrev64q_m_s32): Likewise.
9281 (__arm_vqshlq_m_r_s32): Likewise.
9282 (__arm_vqrshlq_m_n_s32): Likewise.
9283 (__arm_vqnegq_m_s32): Likewise.
9284 (__arm_vqabsq_m_s32): Likewise.
9285 (__arm_vnegq_m_s32): Likewise.
9286 (__arm_vmvnq_m_s32): Likewise.
9287 (__arm_vmlsdavxq_p_s32): Likewise.
9288 (__arm_vmlsdavq_p_s32): Likewise.
9289 (__arm_vmladavxq_p_s32): Likewise.
9290 (__arm_vmladavq_p_s32): Likewise.
9291 (__arm_vminvq_p_s32): Likewise.
9292 (__arm_vmaxvq_p_s32): Likewise.
9293 (__arm_vdupq_m_n_s32): Likewise.
9294 (__arm_vclzq_m_s32): Likewise.
9295 (__arm_vclsq_m_s32): Likewise.
9296 (__arm_vaddvaq_p_s32): Likewise.
9297 (__arm_vabsq_m_s32): Likewise.
9298 (__arm_vqrdmlsdhxq_s32): Likewise.
9299 (__arm_vqrdmlsdhq_s32): Likewise.
9300 (__arm_vqrdmlashq_n_s32): Likewise.
9301 (__arm_vqrdmlahq_n_s32): Likewise.
9302 (__arm_vqrdmladhxq_s32): Likewise.
9303 (__arm_vqrdmladhq_s32): Likewise.
9304 (__arm_vqdmlsdhxq_s32): Likewise.
9305 (__arm_vqdmlsdhq_s32): Likewise.
9306 (__arm_vqdmlahq_n_s32): Likewise.
9307 (__arm_vqdmladhxq_s32): Likewise.
9308 (__arm_vqdmladhq_s32): Likewise.
9309 (__arm_vmlsdavaxq_s32): Likewise.
9310 (__arm_vmlsdavaq_s32): Likewise.
9311 (__arm_vmlasq_n_s32): Likewise.
9312 (__arm_vmlaq_n_s32): Likewise.
9313 (__arm_vmladavaxq_s32): Likewise.
9314 (__arm_vmladavaq_s32): Likewise.
9315 (__arm_vsriq_n_s32): Likewise.
9316 (__arm_vsliq_n_s32): Likewise.
9317 (__arm_vpselq_u64): Likewise.
9318 (__arm_vpselq_s64): Likewise.
9319 (vcmpneq_m_n): Define polymorphic variant.
9320 (vcmpneq_m): Likewise.
9321 (vqrdmlsdhq): Likewise.
9322 (vqrdmlsdhxq): Likewise.
9323 (vqrshlq_m_n): Likewise.
9324 (vqshlq_m_r): Likewise.
9325 (vrev64q_m): Likewise.
9326 (vrshlq_m_n): Likewise.
9327 (vshlq_m_r): Likewise.
9328 (vsliq_n): Likewise.
9329 (vsriq_n): Likewise.
9330 (vqrdmlashq_n): Likewise.
9331 (vqrdmlahq): Likewise.
9332 (vqrdmladhxq): Likewise.
9333 (vqrdmladhq): Likewise.
9334 (vqnegq_m): Likewise.
9335 (vqdmlsdhxq): Likewise.
9336 (vabsq_m): Likewise.
9337 (vclsq_m): Likewise.
9338 (vclzq_m): Likewise.
9339 (vcmpgeq_m): Likewise.
9340 (vcmpgeq_m_n): Likewise.
9341 (vdupq_m_n): Likewise.
9342 (vmaxaq_m): Likewise.
9343 (vmlaq_n): Likewise.
9344 (vmlasq_n): Likewise.
9345 (vmvnq_m): Likewise.
9346 (vnegq_m): Likewise.
9348 (vqdmlahq_n): Likewise.
9349 (vqrdmlahq_n): Likewise.
9350 (vqdmlsdhq): Likewise.
9351 (vqdmladhq): Likewise.
9352 (vqabsq_m): Likewise.
9353 (vminaq_m): Likewise.
9354 (vrmlaldavhaq): Likewise.
9355 (vmlsdavxq_p): Likewise.
9356 (vmlsdavq_p): Likewise.
9357 (vmlsdavaxq): Likewise.
9358 (vmlsdavaq): Likewise.
9359 (vaddvaq_p): Likewise.
9360 (vcmpcsq_m_n): Likewise.
9361 (vcmpcsq_m): Likewise.
9362 (vcmpeqq_m_n): Likewise.
9363 (vcmpeqq_m): Likewise.
9364 (vmladavxq_p): Likewise.
9365 (vmladavq_p): Likewise.
9366 (vmladavaxq): Likewise.
9367 (vmladavaq): Likewise.
9368 (vminvq_p): Likewise.
9369 (vminavq_p): Likewise.
9370 (vmaxvq_p): Likewise.
9371 (vmaxavq_p): Likewise.
9372 (vcmpltq_m_n): Likewise.
9373 (vcmpltq_m): Likewise.
9374 (vcmpleq_m): Likewise.
9375 (vcmpleq_m_n): Likewise.
9376 (vcmphiq_m_n): Likewise.
9377 (vcmphiq_m): Likewise.
9378 (vcmpgtq_m_n): Likewise.
9379 (vcmpgtq_m): Likewise.
9380 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use
9382 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
9383 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
9384 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
9385 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
9386 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
9387 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
9388 * config/arm/constraints.md (Rc): Define constraint to check constant is
9389 in the range of 0 to 15.
9390 (Re): Define constraint to check constant is in the range of 0 to 31.
9391 * config/arm/mve.md (VADDVAQ_P): Define iterator.
9392 (VCLZQ_M): Likewise.
9393 (VCMPEQQ_M_N): Likewise.
9394 (VCMPEQQ_M): Likewise.
9395 (VCMPNEQ_M_N): Likewise.
9396 (VCMPNEQ_M): Likewise.
9397 (VDUPQ_M_N): Likewise.
9398 (VMAXVQ_P): Likewise.
9399 (VMINVQ_P): Likewise.
9400 (VMLADAVAQ): Likewise.
9401 (VMLADAVQ_P): Likewise.
9402 (VMLAQ_N): Likewise.
9403 (VMLASQ_N): Likewise.
9404 (VMVNQ_M): Likewise.
9406 (VQDMLAHQ_N): Likewise.
9407 (VQRDMLAHQ_N): Likewise.
9408 (VQRDMLASHQ_N): Likewise.
9409 (VQRSHLQ_M_N): Likewise.
9410 (VQSHLQ_M_R): Likewise.
9411 (VREV64Q_M): Likewise.
9412 (VRSHLQ_M_N): Likewise.
9413 (VSHLQ_M_R): Likewise.
9414 (VSLIQ_N): Likewise.
9415 (VSRIQ_N): Likewise.
9416 (mve_vabsq_m_s<mode>): Define RTL pattern.
9417 (mve_vaddvaq_p_<supf><mode>): Likewise.
9418 (mve_vclsq_m_s<mode>): Likewise.
9419 (mve_vclzq_m_<supf><mode>): Likewise.
9420 (mve_vcmpcsq_m_n_u<mode>): Likewise.
9421 (mve_vcmpcsq_m_u<mode>): Likewise.
9422 (mve_vcmpeqq_m_n_<supf><mode>): Likewise.
9423 (mve_vcmpeqq_m_<supf><mode>): Likewise.
9424 (mve_vcmpgeq_m_n_s<mode>): Likewise.
9425 (mve_vcmpgeq_m_s<mode>): Likewise.
9426 (mve_vcmpgtq_m_n_s<mode>): Likewise.
9427 (mve_vcmpgtq_m_s<mode>): Likewise.
9428 (mve_vcmphiq_m_n_u<mode>): Likewise.
9429 (mve_vcmphiq_m_u<mode>): Likewise.
9430 (mve_vcmpleq_m_n_s<mode>): Likewise.
9431 (mve_vcmpleq_m_s<mode>): Likewise.
9432 (mve_vcmpltq_m_n_s<mode>): Likewise.
9433 (mve_vcmpltq_m_s<mode>): Likewise.
9434 (mve_vcmpneq_m_n_<supf><mode>): Likewise.
9435 (mve_vcmpneq_m_<supf><mode>): Likewise.
9436 (mve_vdupq_m_n_<supf><mode>): Likewise.
9437 (mve_vmaxaq_m_s<mode>): Likewise.
9438 (mve_vmaxavq_p_s<mode>): Likewise.
9439 (mve_vmaxvq_p_<supf><mode>): Likewise.
9440 (mve_vminaq_m_s<mode>): Likewise.
9441 (mve_vminavq_p_s<mode>): Likewise.
9442 (mve_vminvq_p_<supf><mode>): Likewise.
9443 (mve_vmladavaq_<supf><mode>): Likewise.
9444 (mve_vmladavq_p_<supf><mode>): Likewise.
9445 (mve_vmladavxq_p_s<mode>): Likewise.
9446 (mve_vmlaq_n_<supf><mode>): Likewise.
9447 (mve_vmlasq_n_<supf><mode>): Likewise.
9448 (mve_vmlsdavq_p_s<mode>): Likewise.
9449 (mve_vmlsdavxq_p_s<mode>): Likewise.
9450 (mve_vmvnq_m_<supf><mode>): Likewise.
9451 (mve_vnegq_m_s<mode>): Likewise.
9452 (mve_vpselq_<supf><mode>): Likewise.
9453 (mve_vqabsq_m_s<mode>): Likewise.
9454 (mve_vqdmlahq_n_<supf><mode>): Likewise.
9455 (mve_vqnegq_m_s<mode>): Likewise.
9456 (mve_vqrdmladhq_s<mode>): Likewise.
9457 (mve_vqrdmladhxq_s<mode>): Likewise.
9458 (mve_vqrdmlahq_n_<supf><mode>): Likewise.
9459 (mve_vqrdmlashq_n_<supf><mode>): Likewise.
9460 (mve_vqrdmlsdhq_s<mode>): Likewise.
9461 (mve_vqrdmlsdhxq_s<mode>): Likewise.
9462 (mve_vqrshlq_m_n_<supf><mode>): Likewise.
9463 (mve_vqshlq_m_r_<supf><mode>): Likewise.
9464 (mve_vrev64q_m_<supf><mode>): Likewise.
9465 (mve_vrshlq_m_n_<supf><mode>): Likewise.
9466 (mve_vshlq_m_r_<supf><mode>): Likewise.
9467 (mve_vsliq_n_<supf><mode>): Likewise.
9468 (mve_vsriq_n_<supf><mode>): Likewise.
9469 (mve_vqdmlsdhxq_s<mode>): Likewise.
9470 (mve_vqdmlsdhq_s<mode>): Likewise.
9471 (mve_vqdmladhxq_s<mode>): Likewise.
9472 (mve_vqdmladhq_s<mode>): Likewise.
9473 (mve_vmlsdavaxq_s<mode>): Likewise.
9474 (mve_vmlsdavaq_s<mode>): Likewise.
9475 (mve_vmladavaxq_s<mode>): Likewise.
9476 * config/arm/predicates.md (mve_imm_15):Define predicate to check the
9477 matching constraint Rc.
9478 (mve_imm_31): Define predicate to check the matching constraint Re.
9480 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
9482 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
9483 (vec_cmp<mode>di_dup): Likewise.
9484 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
9486 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
9488 * config/gcn/gcn-valu.md (COND_MODE): Delete.
9489 (COND_INT_MODE): Delete.
9490 (cond_op): Add "mult".
9491 (cond_<expander><mode>): Use VEC_ALLREG_MODE.
9492 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
9494 2020-03-18 Richard Biener <rguenther@suse.de>
9497 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using
9498 partial int modes or not mode-precision integer types for
9501 2020-03-18 Jakub Jelinek <jakub@redhat.com>
9503 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue
9505 * config/arc/arc.c (frame_stack_add): Likewise.
9506 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term):
9508 * ipa-predicate.c (predicate::remap_after_inlining): Likewise.
9509 * tree-ssa-strlen.h (handle_printf_call): Likewise.
9510 * tree-ssa-strlen.c (is_strlen_related_p): Likewise.
9511 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise.
9513 2020-03-18 Duan bo <duanbo3@huawei.com>
9516 * config/aarch64/aarch64.md (ldr_got_tiny): Delete.
9517 (@ldr_got_tiny_<mode>): New pattern.
9518 (ldr_got_tiny_sidi): Likewise.
9519 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
9520 them to handle SYMBOL_TINY_GOT for ILP32.
9522 2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
9524 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
9525 call-preserved for SVE PCS functions.
9526 (aarch64_layout_frame): Cope with up to 12 predicate save slots.
9527 Optimize the case in which there are no following vector save slots.
9529 2020-03-18 Richard Biener <rguenther@suse.de>
9532 * fold-const.c (build_fold_addr_expr): Convert address to
9534 * asan.c (maybe_create_ssa_name): Strip useless type conversions.
9535 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1
9536 to build the ADDR_EXPR which we don't really want to simplify.
9537 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
9538 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise.
9539 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
9540 (simplify_builtin_call): Strip useless type conversions.
9541 * tree-ssa-strlen.c (new_strinfo): Likewise.
9543 2020-03-17 Alexey Neyman <stilor@att.net>
9546 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if
9547 the debug level is terse and the declaration is public. Do not
9549 (dwarf2out_decl): Same.
9550 (add_type_attribute): Return immediately if debug level is
9553 2020-03-17 Richard Sandiford <richard.sandiford@arm.com>
9555 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF.
9557 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9558 Mihail Ionescu <mihail.ionescu@arm.com>
9559 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9561 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
9562 Define qualifier for ternary operands.
9563 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
9564 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9565 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9566 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
9567 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
9568 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
9569 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9570 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
9571 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9572 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
9573 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
9574 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
9575 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
9576 * config/arm/arm_mve.h (vabavq_s8): Define macro.
9577 (vabavq_s16): Likewise.
9578 (vabavq_s32): Likewise.
9579 (vbicq_m_n_s16): Likewise.
9580 (vbicq_m_n_s32): Likewise.
9581 (vbicq_m_n_u16): Likewise.
9582 (vbicq_m_n_u32): Likewise.
9583 (vcmpeqq_m_f16): Likewise.
9584 (vcmpeqq_m_f32): Likewise.
9585 (vcvtaq_m_s16_f16): Likewise.
9586 (vcvtaq_m_u16_f16): Likewise.
9587 (vcvtaq_m_s32_f32): Likewise.
9588 (vcvtaq_m_u32_f32): Likewise.
9589 (vcvtq_m_f16_s16): Likewise.
9590 (vcvtq_m_f16_u16): Likewise.
9591 (vcvtq_m_f32_s32): Likewise.
9592 (vcvtq_m_f32_u32): Likewise.
9593 (vqrshrnbq_n_s16): Likewise.
9594 (vqrshrnbq_n_u16): Likewise.
9595 (vqrshrnbq_n_s32): Likewise.
9596 (vqrshrnbq_n_u32): Likewise.
9597 (vqrshrunbq_n_s16): Likewise.
9598 (vqrshrunbq_n_s32): Likewise.
9599 (vrmlaldavhaq_s32): Likewise.
9600 (vrmlaldavhaq_u32): Likewise.
9601 (vshlcq_s8): Likewise.
9602 (vshlcq_u8): Likewise.
9603 (vshlcq_s16): Likewise.
9604 (vshlcq_u16): Likewise.
9605 (vshlcq_s32): Likewise.
9606 (vshlcq_u32): Likewise.
9607 (vabavq_u8): Likewise.
9608 (vabavq_u16): Likewise.
9609 (vabavq_u32): Likewise.
9610 (__arm_vabavq_s8): Define intrinsic.
9611 (__arm_vabavq_s16): Likewise.
9612 (__arm_vabavq_s32): Likewise.
9613 (__arm_vabavq_u8): Likewise.
9614 (__arm_vabavq_u16): Likewise.
9615 (__arm_vabavq_u32): Likewise.
9616 (__arm_vbicq_m_n_s16): Likewise.
9617 (__arm_vbicq_m_n_s32): Likewise.
9618 (__arm_vbicq_m_n_u16): Likewise.
9619 (__arm_vbicq_m_n_u32): Likewise.
9620 (__arm_vqrshrnbq_n_s16): Likewise.
9621 (__arm_vqrshrnbq_n_u16): Likewise.
9622 (__arm_vqrshrnbq_n_s32): Likewise.
9623 (__arm_vqrshrnbq_n_u32): Likewise.
9624 (__arm_vqrshrunbq_n_s16): Likewise.
9625 (__arm_vqrshrunbq_n_s32): Likewise.
9626 (__arm_vrmlaldavhaq_s32): Likewise.
9627 (__arm_vrmlaldavhaq_u32): Likewise.
9628 (__arm_vshlcq_s8): Likewise.
9629 (__arm_vshlcq_u8): Likewise.
9630 (__arm_vshlcq_s16): Likewise.
9631 (__arm_vshlcq_u16): Likewise.
9632 (__arm_vshlcq_s32): Likewise.
9633 (__arm_vshlcq_u32): Likewise.
9634 (__arm_vcmpeqq_m_f16): Likewise.
9635 (__arm_vcmpeqq_m_f32): Likewise.
9636 (__arm_vcvtaq_m_s16_f16): Likewise.
9637 (__arm_vcvtaq_m_u16_f16): Likewise.
9638 (__arm_vcvtaq_m_s32_f32): Likewise.
9639 (__arm_vcvtaq_m_u32_f32): Likewise.
9640 (__arm_vcvtq_m_f16_s16): Likewise.
9641 (__arm_vcvtq_m_f16_u16): Likewise.
9642 (__arm_vcvtq_m_f32_s32): Likewise.
9643 (__arm_vcvtq_m_f32_u32): Likewise.
9644 (vcvtaq_m): Define polymorphic variant.
9645 (vcvtq_m): Likewise.
9648 (vbicq_m_n): Likewise.
9649 (vqrshrnbq_n): Likewise.
9650 (vqrshrunbq_n): Likewise.
9651 * config/arm/arm_mve_builtins.def
9652 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
9653 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
9654 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9655 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9656 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
9657 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
9658 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
9659 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9660 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
9661 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9662 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
9663 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
9664 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
9665 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
9666 * config/arm/mve.md (VBICQ_M_N): Define iterator.
9667 (VCVTAQ_M): Likewise.
9668 (VCVTQ_M_TO_F): Likewise.
9669 (VQRSHRNBQ_N): Likewise.
9672 (VRMLALDAVHAQ): Likewise.
9673 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
9674 (mve_vcmpeqq_m_f<mode>): Likewise.
9675 (mve_vcvtaq_m_<supf><mode>): Likewise.
9676 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
9677 (mve_vqrshrnbq_n_<supf><mode>): Likewise.
9678 (mve_vqrshrunbq_n_s<mode>): Likewise.
9679 (mve_vrmlaldavhaq_<supf>v4si): Likewise.
9680 (mve_vabavq_<supf><mode>): Likewise.
9681 (mve_vshlcq_<supf><mode>): Likewise.
9682 (mve_vshlcq_<supf><mode>): Likewise.
9683 (mve_vshlcq_vec_<supf><mode>): Define RTL expand.
9684 (mve_vshlcq_carry_<supf><mode>): Likewise.
9686 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9687 Mihail Ionescu <mihail.ionescu@arm.com>
9688 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9690 * config/arm/arm_mve.h (vqmovntq_u16): Define macro.
9691 (vqmovnbq_u16): Likewise.
9692 (vmulltq_poly_p8): Likewise.
9693 (vmullbq_poly_p8): Likewise.
9694 (vmovntq_u16): Likewise.
9695 (vmovnbq_u16): Likewise.
9696 (vmlaldavxq_u16): Likewise.
9697 (vmlaldavq_u16): Likewise.
9698 (vqmovuntq_s16): Likewise.
9699 (vqmovunbq_s16): Likewise.
9700 (vshlltq_n_u8): Likewise.
9701 (vshllbq_n_u8): Likewise.
9702 (vorrq_n_u16): Likewise.
9703 (vbicq_n_u16): Likewise.
9704 (vcmpneq_n_f16): Likewise.
9705 (vcmpneq_f16): Likewise.
9706 (vcmpltq_n_f16): Likewise.
9707 (vcmpltq_f16): Likewise.
9708 (vcmpleq_n_f16): Likewise.
9709 (vcmpleq_f16): Likewise.
9710 (vcmpgtq_n_f16): Likewise.
9711 (vcmpgtq_f16): Likewise.
9712 (vcmpgeq_n_f16): Likewise.
9713 (vcmpgeq_f16): Likewise.
9714 (vcmpeqq_n_f16): Likewise.
9715 (vcmpeqq_f16): Likewise.
9716 (vsubq_f16): Likewise.
9717 (vqmovntq_s16): Likewise.
9718 (vqmovnbq_s16): Likewise.
9719 (vqdmulltq_s16): Likewise.
9720 (vqdmulltq_n_s16): Likewise.
9721 (vqdmullbq_s16): Likewise.
9722 (vqdmullbq_n_s16): Likewise.
9723 (vorrq_f16): Likewise.
9724 (vornq_f16): Likewise.
9725 (vmulq_n_f16): Likewise.
9726 (vmulq_f16): Likewise.
9727 (vmovntq_s16): Likewise.
9728 (vmovnbq_s16): Likewise.
9729 (vmlsldavxq_s16): Likewise.
9730 (vmlsldavq_s16): Likewise.
9731 (vmlaldavxq_s16): Likewise.
9732 (vmlaldavq_s16): Likewise.
9733 (vminnmvq_f16): Likewise.
9734 (vminnmq_f16): Likewise.
9735 (vminnmavq_f16): Likewise.
9736 (vminnmaq_f16): Likewise.
9737 (vmaxnmvq_f16): Likewise.
9738 (vmaxnmq_f16): Likewise.
9739 (vmaxnmavq_f16): Likewise.
9740 (vmaxnmaq_f16): Likewise.
9741 (veorq_f16): Likewise.
9742 (vcmulq_rot90_f16): Likewise.
9743 (vcmulq_rot270_f16): Likewise.
9744 (vcmulq_rot180_f16): Likewise.
9745 (vcmulq_f16): Likewise.
9746 (vcaddq_rot90_f16): Likewise.
9747 (vcaddq_rot270_f16): Likewise.
9748 (vbicq_f16): Likewise.
9749 (vandq_f16): Likewise.
9750 (vaddq_n_f16): Likewise.
9751 (vabdq_f16): Likewise.
9752 (vshlltq_n_s8): Likewise.
9753 (vshllbq_n_s8): Likewise.
9754 (vorrq_n_s16): Likewise.
9755 (vbicq_n_s16): Likewise.
9756 (vqmovntq_u32): Likewise.
9757 (vqmovnbq_u32): Likewise.
9758 (vmulltq_poly_p16): Likewise.
9759 (vmullbq_poly_p16): Likewise.
9760 (vmovntq_u32): Likewise.
9761 (vmovnbq_u32): Likewise.
9762 (vmlaldavxq_u32): Likewise.
9763 (vmlaldavq_u32): Likewise.
9764 (vqmovuntq_s32): Likewise.
9765 (vqmovunbq_s32): Likewise.
9766 (vshlltq_n_u16): Likewise.
9767 (vshllbq_n_u16): Likewise.
9768 (vorrq_n_u32): Likewise.
9769 (vbicq_n_u32): Likewise.
9770 (vcmpneq_n_f32): Likewise.
9771 (vcmpneq_f32): Likewise.
9772 (vcmpltq_n_f32): Likewise.
9773 (vcmpltq_f32): Likewise.
9774 (vcmpleq_n_f32): Likewise.
9775 (vcmpleq_f32): Likewise.
9776 (vcmpgtq_n_f32): Likewise.
9777 (vcmpgtq_f32): Likewise.
9778 (vcmpgeq_n_f32): Likewise.
9779 (vcmpgeq_f32): Likewise.
9780 (vcmpeqq_n_f32): Likewise.
9781 (vcmpeqq_f32): Likewise.
9782 (vsubq_f32): Likewise.
9783 (vqmovntq_s32): Likewise.
9784 (vqmovnbq_s32): Likewise.
9785 (vqdmulltq_s32): Likewise.
9786 (vqdmulltq_n_s32): Likewise.
9787 (vqdmullbq_s32): Likewise.
9788 (vqdmullbq_n_s32): Likewise.
9789 (vorrq_f32): Likewise.
9790 (vornq_f32): Likewise.
9791 (vmulq_n_f32): Likewise.
9792 (vmulq_f32): Likewise.
9793 (vmovntq_s32): Likewise.
9794 (vmovnbq_s32): Likewise.
9795 (vmlsldavxq_s32): Likewise.
9796 (vmlsldavq_s32): Likewise.
9797 (vmlaldavxq_s32): Likewise.
9798 (vmlaldavq_s32): Likewise.
9799 (vminnmvq_f32): Likewise.
9800 (vminnmq_f32): Likewise.
9801 (vminnmavq_f32): Likewise.
9802 (vminnmaq_f32): Likewise.
9803 (vmaxnmvq_f32): Likewise.
9804 (vmaxnmq_f32): Likewise.
9805 (vmaxnmavq_f32): Likewise.
9806 (vmaxnmaq_f32): Likewise.
9807 (veorq_f32): Likewise.
9808 (vcmulq_rot90_f32): Likewise.
9809 (vcmulq_rot270_f32): Likewise.
9810 (vcmulq_rot180_f32): Likewise.
9811 (vcmulq_f32): Likewise.
9812 (vcaddq_rot90_f32): Likewise.
9813 (vcaddq_rot270_f32): Likewise.
9814 (vbicq_f32): Likewise.
9815 (vandq_f32): Likewise.
9816 (vaddq_n_f32): Likewise.
9817 (vabdq_f32): Likewise.
9818 (vshlltq_n_s16): Likewise.
9819 (vshllbq_n_s16): Likewise.
9820 (vorrq_n_s32): Likewise.
9821 (vbicq_n_s32): Likewise.
9822 (vrmlaldavhq_u32): Likewise.
9823 (vctp8q_m): Likewise.
9824 (vctp64q_m): Likewise.
9825 (vctp32q_m): Likewise.
9826 (vctp16q_m): Likewise.
9827 (vaddlvaq_u32): Likewise.
9828 (vrmlsldavhxq_s32): Likewise.
9829 (vrmlsldavhq_s32): Likewise.
9830 (vrmlaldavhxq_s32): Likewise.
9831 (vrmlaldavhq_s32): Likewise.
9832 (vcvttq_f16_f32): Likewise.
9833 (vcvtbq_f16_f32): Likewise.
9834 (vaddlvaq_s32): Likewise.
9835 (__arm_vqmovntq_u16): Define intrinsic.
9836 (__arm_vqmovnbq_u16): Likewise.
9837 (__arm_vmulltq_poly_p8): Likewise.
9838 (__arm_vmullbq_poly_p8): Likewise.
9839 (__arm_vmovntq_u16): Likewise.
9840 (__arm_vmovnbq_u16): Likewise.
9841 (__arm_vmlaldavxq_u16): Likewise.
9842 (__arm_vmlaldavq_u16): Likewise.
9843 (__arm_vqmovuntq_s16): Likewise.
9844 (__arm_vqmovunbq_s16): Likewise.
9845 (__arm_vshlltq_n_u8): Likewise.
9846 (__arm_vshllbq_n_u8): Likewise.
9847 (__arm_vorrq_n_u16): Likewise.
9848 (__arm_vbicq_n_u16): Likewise.
9849 (__arm_vcmpneq_n_f16): Likewise.
9850 (__arm_vcmpneq_f16): Likewise.
9851 (__arm_vcmpltq_n_f16): Likewise.
9852 (__arm_vcmpltq_f16): Likewise.
9853 (__arm_vcmpleq_n_f16): Likewise.
9854 (__arm_vcmpleq_f16): Likewise.
9855 (__arm_vcmpgtq_n_f16): Likewise.
9856 (__arm_vcmpgtq_f16): Likewise.
9857 (__arm_vcmpgeq_n_f16): Likewise.
9858 (__arm_vcmpgeq_f16): Likewise.
9859 (__arm_vcmpeqq_n_f16): Likewise.
9860 (__arm_vcmpeqq_f16): Likewise.
9861 (__arm_vsubq_f16): Likewise.
9862 (__arm_vqmovntq_s16): Likewise.
9863 (__arm_vqmovnbq_s16): Likewise.
9864 (__arm_vqdmulltq_s16): Likewise.
9865 (__arm_vqdmulltq_n_s16): Likewise.
9866 (__arm_vqdmullbq_s16): Likewise.
9867 (__arm_vqdmullbq_n_s16): Likewise.
9868 (__arm_vorrq_f16): Likewise.
9869 (__arm_vornq_f16): Likewise.
9870 (__arm_vmulq_n_f16): Likewise.
9871 (__arm_vmulq_f16): Likewise.
9872 (__arm_vmovntq_s16): Likewise.
9873 (__arm_vmovnbq_s16): Likewise.
9874 (__arm_vmlsldavxq_s16): Likewise.
9875 (__arm_vmlsldavq_s16): Likewise.
9876 (__arm_vmlaldavxq_s16): Likewise.
9877 (__arm_vmlaldavq_s16): Likewise.
9878 (__arm_vminnmvq_f16): Likewise.
9879 (__arm_vminnmq_f16): Likewise.
9880 (__arm_vminnmavq_f16): Likewise.
9881 (__arm_vminnmaq_f16): Likewise.
9882 (__arm_vmaxnmvq_f16): Likewise.
9883 (__arm_vmaxnmq_f16): Likewise.
9884 (__arm_vmaxnmavq_f16): Likewise.
9885 (__arm_vmaxnmaq_f16): Likewise.
9886 (__arm_veorq_f16): Likewise.
9887 (__arm_vcmulq_rot90_f16): Likewise.
9888 (__arm_vcmulq_rot270_f16): Likewise.
9889 (__arm_vcmulq_rot180_f16): Likewise.
9890 (__arm_vcmulq_f16): Likewise.
9891 (__arm_vcaddq_rot90_f16): Likewise.
9892 (__arm_vcaddq_rot270_f16): Likewise.
9893 (__arm_vbicq_f16): Likewise.
9894 (__arm_vandq_f16): Likewise.
9895 (__arm_vaddq_n_f16): Likewise.
9896 (__arm_vabdq_f16): Likewise.
9897 (__arm_vshlltq_n_s8): Likewise.
9898 (__arm_vshllbq_n_s8): Likewise.
9899 (__arm_vorrq_n_s16): Likewise.
9900 (__arm_vbicq_n_s16): Likewise.
9901 (__arm_vqmovntq_u32): Likewise.
9902 (__arm_vqmovnbq_u32): Likewise.
9903 (__arm_vmulltq_poly_p16): Likewise.
9904 (__arm_vmullbq_poly_p16): Likewise.
9905 (__arm_vmovntq_u32): Likewise.
9906 (__arm_vmovnbq_u32): Likewise.
9907 (__arm_vmlaldavxq_u32): Likewise.
9908 (__arm_vmlaldavq_u32): Likewise.
9909 (__arm_vqmovuntq_s32): Likewise.
9910 (__arm_vqmovunbq_s32): Likewise.
9911 (__arm_vshlltq_n_u16): Likewise.
9912 (__arm_vshllbq_n_u16): Likewise.
9913 (__arm_vorrq_n_u32): Likewise.
9914 (__arm_vbicq_n_u32): Likewise.
9915 (__arm_vcmpneq_n_f32): Likewise.
9916 (__arm_vcmpneq_f32): Likewise.
9917 (__arm_vcmpltq_n_f32): Likewise.
9918 (__arm_vcmpltq_f32): Likewise.
9919 (__arm_vcmpleq_n_f32): Likewise.
9920 (__arm_vcmpleq_f32): Likewise.
9921 (__arm_vcmpgtq_n_f32): Likewise.
9922 (__arm_vcmpgtq_f32): Likewise.
9923 (__arm_vcmpgeq_n_f32): Likewise.
9924 (__arm_vcmpgeq_f32): Likewise.
9925 (__arm_vcmpeqq_n_f32): Likewise.
9926 (__arm_vcmpeqq_f32): Likewise.
9927 (__arm_vsubq_f32): Likewise.
9928 (__arm_vqmovntq_s32): Likewise.
9929 (__arm_vqmovnbq_s32): Likewise.
9930 (__arm_vqdmulltq_s32): Likewise.
9931 (__arm_vqdmulltq_n_s32): Likewise.
9932 (__arm_vqdmullbq_s32): Likewise.
9933 (__arm_vqdmullbq_n_s32): Likewise.
9934 (__arm_vorrq_f32): Likewise.
9935 (__arm_vornq_f32): Likewise.
9936 (__arm_vmulq_n_f32): Likewise.
9937 (__arm_vmulq_f32): Likewise.
9938 (__arm_vmovntq_s32): Likewise.
9939 (__arm_vmovnbq_s32): Likewise.
9940 (__arm_vmlsldavxq_s32): Likewise.
9941 (__arm_vmlsldavq_s32): Likewise.
9942 (__arm_vmlaldavxq_s32): Likewise.
9943 (__arm_vmlaldavq_s32): Likewise.
9944 (__arm_vminnmvq_f32): Likewise.
9945 (__arm_vminnmq_f32): Likewise.
9946 (__arm_vminnmavq_f32): Likewise.
9947 (__arm_vminnmaq_f32): Likewise.
9948 (__arm_vmaxnmvq_f32): Likewise.
9949 (__arm_vmaxnmq_f32): Likewise.
9950 (__arm_vmaxnmavq_f32): Likewise.
9951 (__arm_vmaxnmaq_f32): Likewise.
9952 (__arm_veorq_f32): Likewise.
9953 (__arm_vcmulq_rot90_f32): Likewise.
9954 (__arm_vcmulq_rot270_f32): Likewise.
9955 (__arm_vcmulq_rot180_f32): Likewise.
9956 (__arm_vcmulq_f32): Likewise.
9957 (__arm_vcaddq_rot90_f32): Likewise.
9958 (__arm_vcaddq_rot270_f32): Likewise.
9959 (__arm_vbicq_f32): Likewise.
9960 (__arm_vandq_f32): Likewise.
9961 (__arm_vaddq_n_f32): Likewise.
9962 (__arm_vabdq_f32): Likewise.
9963 (__arm_vshlltq_n_s16): Likewise.
9964 (__arm_vshllbq_n_s16): Likewise.
9965 (__arm_vorrq_n_s32): Likewise.
9966 (__arm_vbicq_n_s32): Likewise.
9967 (__arm_vrmlaldavhq_u32): Likewise.
9968 (__arm_vctp8q_m): Likewise.
9969 (__arm_vctp64q_m): Likewise.
9970 (__arm_vctp32q_m): Likewise.
9971 (__arm_vctp16q_m): Likewise.
9972 (__arm_vaddlvaq_u32): Likewise.
9973 (__arm_vrmlsldavhxq_s32): Likewise.
9974 (__arm_vrmlsldavhq_s32): Likewise.
9975 (__arm_vrmlaldavhxq_s32): Likewise.
9976 (__arm_vrmlaldavhq_s32): Likewise.
9977 (__arm_vcvttq_f16_f32): Likewise.
9978 (__arm_vcvtbq_f16_f32): Likewise.
9979 (__arm_vaddlvaq_s32): Likewise.
9980 (vst4q): Define polymorphic variant.
9987 (vrev64q): Likewise.
9989 (vdupq_n): Likewise.
9991 (vrev32q): Likewise.
9992 (vcvtbq_f32): Likewise.
9993 (vcvttq_f32): Likewise.
9995 (vsubq_n): Likewise.
9996 (vbrsrq_n): Likewise.
9997 (vcvtq_n): Likewise.
10001 (vaddq_n): Likewise.
10005 (vmulq_n): Likewise.
10007 (vcaddq_rot270): Likewise.
10008 (vcmpeqq_n): Likewise.
10009 (vcmpeqq): Likewise.
10010 (vcaddq_rot90): Likewise.
10011 (vcmpgeq_n): Likewise.
10012 (vcmpgeq): Likewise.
10013 (vcmpgtq_n): Likewise.
10014 (vcmpgtq): Likewise.
10015 (vcmpgtq): Likewise.
10016 (vcmpleq_n): Likewise.
10017 (vcmpleq_n): Likewise.
10018 (vcmpleq): Likewise.
10019 (vcmpleq): Likewise.
10020 (vcmpltq_n): Likewise.
10021 (vcmpltq_n): Likewise.
10022 (vcmpltq): Likewise.
10023 (vcmpltq): Likewise.
10024 (vcmpneq_n): Likewise.
10025 (vcmpneq_n): Likewise.
10026 (vcmpneq): Likewise.
10027 (vcmpneq): Likewise.
10028 (vcmulq): Likewise.
10029 (vcmulq): Likewise.
10030 (vcmulq_rot180): Likewise.
10031 (vcmulq_rot180): Likewise.
10032 (vcmulq_rot270): Likewise.
10033 (vcmulq_rot270): Likewise.
10034 (vcmulq_rot90): Likewise.
10035 (vcmulq_rot90): Likewise.
10038 (vmaxnmaq): Likewise.
10039 (vmaxnmaq): Likewise.
10040 (vmaxnmavq): Likewise.
10041 (vmaxnmavq): Likewise.
10042 (vmaxnmq): Likewise.
10043 (vmaxnmq): Likewise.
10044 (vmaxnmvq): Likewise.
10045 (vmaxnmvq): Likewise.
10046 (vminnmaq): Likewise.
10047 (vminnmaq): Likewise.
10048 (vminnmavq): Likewise.
10049 (vminnmavq): Likewise.
10050 (vminnmq): Likewise.
10051 (vminnmq): Likewise.
10052 (vminnmvq): Likewise.
10053 (vminnmvq): Likewise.
10054 (vbicq_n): Likewise.
10055 (vqmovntq): Likewise.
10056 (vqmovntq): Likewise.
10057 (vqmovnbq): Likewise.
10058 (vqmovnbq): Likewise.
10059 (vmulltq_poly): Likewise.
10060 (vmulltq_poly): Likewise.
10061 (vmullbq_poly): Likewise.
10062 (vmullbq_poly): Likewise.
10063 (vmovntq): Likewise.
10064 (vmovntq): Likewise.
10065 (vmovnbq): Likewise.
10066 (vmovnbq): Likewise.
10067 (vmlaldavxq): Likewise.
10068 (vmlaldavxq): Likewise.
10069 (vqmovuntq): Likewise.
10070 (vqmovuntq): Likewise.
10071 (vshlltq_n): Likewise.
10072 (vshlltq_n): Likewise.
10073 (vshllbq_n): Likewise.
10074 (vshllbq_n): Likewise.
10075 (vorrq_n): Likewise.
10076 (vorrq_n): Likewise.
10077 (vmlaldavq): Likewise.
10078 (vmlaldavq): Likewise.
10079 (vqmovunbq): Likewise.
10080 (vqmovunbq): Likewise.
10081 (vqdmulltq_n): Likewise.
10082 (vqdmulltq_n): Likewise.
10083 (vqdmulltq): Likewise.
10084 (vqdmulltq): Likewise.
10085 (vqdmullbq_n): Likewise.
10086 (vqdmullbq_n): Likewise.
10087 (vqdmullbq): Likewise.
10088 (vqdmullbq): Likewise.
10089 (vaddlvaq): Likewise.
10090 (vaddlvaq): Likewise.
10091 (vrmlaldavhq): Likewise.
10092 (vrmlaldavhq): Likewise.
10093 (vrmlaldavhxq): Likewise.
10094 (vrmlaldavhxq): Likewise.
10095 (vrmlsldavhq): Likewise.
10096 (vrmlsldavhq): Likewise.
10097 (vrmlsldavhxq): Likewise.
10098 (vrmlsldavhxq): Likewise.
10099 (vmlsldavxq): Likewise.
10100 (vmlsldavxq): Likewise.
10101 (vmlsldavq): Likewise.
10102 (vmlsldavq): Likewise.
10103 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
10104 (BINOP_NONE_NONE_NONE): Likewise.
10105 (BINOP_UNONE_NONE_NONE): Likewise.
10106 (BINOP_UNONE_UNONE_IMM): Likewise.
10107 (BINOP_UNONE_UNONE_NONE): Likewise.
10108 (BINOP_UNONE_UNONE_UNONE): Likewise.
10109 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
10110 (mve_vaddlvaq_<supf>v4si): Likewise.
10111 (mve_vaddq_n_f<mode>): Likewise.
10112 (mve_vandq_f<mode>): Likewise.
10113 (mve_vbicq_f<mode>): Likewise.
10114 (mve_vbicq_n_<supf><mode>): Likewise.
10115 (mve_vcaddq_rot270_f<mode>): Likewise.
10116 (mve_vcaddq_rot90_f<mode>): Likewise.
10117 (mve_vcmpeqq_f<mode>): Likewise.
10118 (mve_vcmpeqq_n_f<mode>): Likewise.
10119 (mve_vcmpgeq_f<mode>): Likewise.
10120 (mve_vcmpgeq_n_f<mode>): Likewise.
10121 (mve_vcmpgtq_f<mode>): Likewise.
10122 (mve_vcmpgtq_n_f<mode>): Likewise.
10123 (mve_vcmpleq_f<mode>): Likewise.
10124 (mve_vcmpleq_n_f<mode>): Likewise.
10125 (mve_vcmpltq_f<mode>): Likewise.
10126 (mve_vcmpltq_n_f<mode>): Likewise.
10127 (mve_vcmpneq_f<mode>): Likewise.
10128 (mve_vcmpneq_n_f<mode>): Likewise.
10129 (mve_vcmulq_f<mode>): Likewise.
10130 (mve_vcmulq_rot180_f<mode>): Likewise.
10131 (mve_vcmulq_rot270_f<mode>): Likewise.
10132 (mve_vcmulq_rot90_f<mode>): Likewise.
10133 (mve_vctp<mode1>q_mhi): Likewise.
10134 (mve_vcvtbq_f16_f32v8hf): Likewise.
10135 (mve_vcvttq_f16_f32v8hf): Likewise.
10136 (mve_veorq_f<mode>): Likewise.
10137 (mve_vmaxnmaq_f<mode>): Likewise.
10138 (mve_vmaxnmavq_f<mode>): Likewise.
10139 (mve_vmaxnmq_f<mode>): Likewise.
10140 (mve_vmaxnmvq_f<mode>): Likewise.
10141 (mve_vminnmaq_f<mode>): Likewise.
10142 (mve_vminnmavq_f<mode>): Likewise.
10143 (mve_vminnmq_f<mode>): Likewise.
10144 (mve_vminnmvq_f<mode>): Likewise.
10145 (mve_vmlaldavq_<supf><mode>): Likewise.
10146 (mve_vmlaldavxq_<supf><mode>): Likewise.
10147 (mve_vmlsldavq_s<mode>): Likewise.
10148 (mve_vmlsldavxq_s<mode>): Likewise.
10149 (mve_vmovnbq_<supf><mode>): Likewise.
10150 (mve_vmovntq_<supf><mode>): Likewise.
10151 (mve_vmulq_f<mode>): Likewise.
10152 (mve_vmulq_n_f<mode>): Likewise.
10153 (mve_vornq_f<mode>): Likewise.
10154 (mve_vorrq_f<mode>): Likewise.
10155 (mve_vorrq_n_<supf><mode>): Likewise.
10156 (mve_vqdmullbq_n_s<mode>): Likewise.
10157 (mve_vqdmullbq_s<mode>): Likewise.
10158 (mve_vqdmulltq_n_s<mode>): Likewise.
10159 (mve_vqdmulltq_s<mode>): Likewise.
10160 (mve_vqmovnbq_<supf><mode>): Likewise.
10161 (mve_vqmovntq_<supf><mode>): Likewise.
10162 (mve_vqmovunbq_s<mode>): Likewise.
10163 (mve_vqmovuntq_s<mode>): Likewise.
10164 (mve_vrmlaldavhxq_sv4si): Likewise.
10165 (mve_vrmlsldavhq_sv4si): Likewise.
10166 (mve_vrmlsldavhxq_sv4si): Likewise.
10167 (mve_vshllbq_n_<supf><mode>): Likewise.
10168 (mve_vshlltq_n_<supf><mode>): Likewise.
10169 (mve_vsubq_f<mode>): Likewise.
10170 (mve_vmulltq_poly_p<mode>): Likewise.
10171 (mve_vmullbq_poly_p<mode>): Likewise.
10172 (mve_vrmlaldavhq_<supf>v4si): Likewise.
10174 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10175 Mihail Ionescu <mihail.ionescu@arm.com>
10176 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10178 * config/arm/arm_mve.h (vsubq_u8): Define macro.
10179 (vsubq_n_u8): Likewise.
10180 (vrmulhq_u8): Likewise.
10181 (vrhaddq_u8): Likewise.
10182 (vqsubq_u8): Likewise.
10183 (vqsubq_n_u8): Likewise.
10184 (vqaddq_u8): Likewise.
10185 (vqaddq_n_u8): Likewise.
10186 (vorrq_u8): Likewise.
10187 (vornq_u8): Likewise.
10188 (vmulq_u8): Likewise.
10189 (vmulq_n_u8): Likewise.
10190 (vmulltq_int_u8): Likewise.
10191 (vmullbq_int_u8): Likewise.
10192 (vmulhq_u8): Likewise.
10193 (vmladavq_u8): Likewise.
10194 (vminvq_u8): Likewise.
10195 (vminq_u8): Likewise.
10196 (vmaxvq_u8): Likewise.
10197 (vmaxq_u8): Likewise.
10198 (vhsubq_u8): Likewise.
10199 (vhsubq_n_u8): Likewise.
10200 (vhaddq_u8): Likewise.
10201 (vhaddq_n_u8): Likewise.
10202 (veorq_u8): Likewise.
10203 (vcmpneq_n_u8): Likewise.
10204 (vcmphiq_u8): Likewise.
10205 (vcmphiq_n_u8): Likewise.
10206 (vcmpeqq_u8): Likewise.
10207 (vcmpeqq_n_u8): Likewise.
10208 (vcmpcsq_u8): Likewise.
10209 (vcmpcsq_n_u8): Likewise.
10210 (vcaddq_rot90_u8): Likewise.
10211 (vcaddq_rot270_u8): Likewise.
10212 (vbicq_u8): Likewise.
10213 (vandq_u8): Likewise.
10214 (vaddvq_p_u8): Likewise.
10215 (vaddvaq_u8): Likewise.
10216 (vaddq_n_u8): Likewise.
10217 (vabdq_u8): Likewise.
10218 (vshlq_r_u8): Likewise.
10219 (vrshlq_u8): Likewise.
10220 (vrshlq_n_u8): Likewise.
10221 (vqshlq_u8): Likewise.
10222 (vqshlq_r_u8): Likewise.
10223 (vqrshlq_u8): Likewise.
10224 (vqrshlq_n_u8): Likewise.
10225 (vminavq_s8): Likewise.
10226 (vminaq_s8): Likewise.
10227 (vmaxavq_s8): Likewise.
10228 (vmaxaq_s8): Likewise.
10229 (vbrsrq_n_u8): Likewise.
10230 (vshlq_n_u8): Likewise.
10231 (vrshrq_n_u8): Likewise.
10232 (vqshlq_n_u8): Likewise.
10233 (vcmpneq_n_s8): Likewise.
10234 (vcmpltq_s8): Likewise.
10235 (vcmpltq_n_s8): Likewise.
10236 (vcmpleq_s8): Likewise.
10237 (vcmpleq_n_s8): Likewise.
10238 (vcmpgtq_s8): Likewise.
10239 (vcmpgtq_n_s8): Likewise.
10240 (vcmpgeq_s8): Likewise.
10241 (vcmpgeq_n_s8): Likewise.
10242 (vcmpeqq_s8): Likewise.
10243 (vcmpeqq_n_s8): Likewise.
10244 (vqshluq_n_s8): Likewise.
10245 (vaddvq_p_s8): Likewise.
10246 (vsubq_s8): Likewise.
10247 (vsubq_n_s8): Likewise.
10248 (vshlq_r_s8): Likewise.
10249 (vrshlq_s8): Likewise.
10250 (vrshlq_n_s8): Likewise.
10251 (vrmulhq_s8): Likewise.
10252 (vrhaddq_s8): Likewise.
10253 (vqsubq_s8): Likewise.
10254 (vqsubq_n_s8): Likewise.
10255 (vqshlq_s8): Likewise.
10256 (vqshlq_r_s8): Likewise.
10257 (vqrshlq_s8): Likewise.
10258 (vqrshlq_n_s8): Likewise.
10259 (vqrdmulhq_s8): Likewise.
10260 (vqrdmulhq_n_s8): Likewise.
10261 (vqdmulhq_s8): Likewise.
10262 (vqdmulhq_n_s8): Likewise.
10263 (vqaddq_s8): Likewise.
10264 (vqaddq_n_s8): Likewise.
10265 (vorrq_s8): Likewise.
10266 (vornq_s8): Likewise.
10267 (vmulq_s8): Likewise.
10268 (vmulq_n_s8): Likewise.
10269 (vmulltq_int_s8): Likewise.
10270 (vmullbq_int_s8): Likewise.
10271 (vmulhq_s8): Likewise.
10272 (vmlsdavxq_s8): Likewise.
10273 (vmlsdavq_s8): Likewise.
10274 (vmladavxq_s8): Likewise.
10275 (vmladavq_s8): Likewise.
10276 (vminvq_s8): Likewise.
10277 (vminq_s8): Likewise.
10278 (vmaxvq_s8): Likewise.
10279 (vmaxq_s8): Likewise.
10280 (vhsubq_s8): Likewise.
10281 (vhsubq_n_s8): Likewise.
10282 (vhcaddq_rot90_s8): Likewise.
10283 (vhcaddq_rot270_s8): Likewise.
10284 (vhaddq_s8): Likewise.
10285 (vhaddq_n_s8): Likewise.
10286 (veorq_s8): Likewise.
10287 (vcaddq_rot90_s8): Likewise.
10288 (vcaddq_rot270_s8): Likewise.
10289 (vbrsrq_n_s8): Likewise.
10290 (vbicq_s8): Likewise.
10291 (vandq_s8): Likewise.
10292 (vaddvaq_s8): Likewise.
10293 (vaddq_n_s8): Likewise.
10294 (vabdq_s8): Likewise.
10295 (vshlq_n_s8): Likewise.
10296 (vrshrq_n_s8): Likewise.
10297 (vqshlq_n_s8): Likewise.
10298 (vsubq_u16): Likewise.
10299 (vsubq_n_u16): Likewise.
10300 (vrmulhq_u16): Likewise.
10301 (vrhaddq_u16): Likewise.
10302 (vqsubq_u16): Likewise.
10303 (vqsubq_n_u16): Likewise.
10304 (vqaddq_u16): Likewise.
10305 (vqaddq_n_u16): Likewise.
10306 (vorrq_u16): Likewise.
10307 (vornq_u16): Likewise.
10308 (vmulq_u16): Likewise.
10309 (vmulq_n_u16): Likewise.
10310 (vmulltq_int_u16): Likewise.
10311 (vmullbq_int_u16): Likewise.
10312 (vmulhq_u16): Likewise.
10313 (vmladavq_u16): Likewise.
10314 (vminvq_u16): Likewise.
10315 (vminq_u16): Likewise.
10316 (vmaxvq_u16): Likewise.
10317 (vmaxq_u16): Likewise.
10318 (vhsubq_u16): Likewise.
10319 (vhsubq_n_u16): Likewise.
10320 (vhaddq_u16): Likewise.
10321 (vhaddq_n_u16): Likewise.
10322 (veorq_u16): Likewise.
10323 (vcmpneq_n_u16): Likewise.
10324 (vcmphiq_u16): Likewise.
10325 (vcmphiq_n_u16): Likewise.
10326 (vcmpeqq_u16): Likewise.
10327 (vcmpeqq_n_u16): Likewise.
10328 (vcmpcsq_u16): Likewise.
10329 (vcmpcsq_n_u16): Likewise.
10330 (vcaddq_rot90_u16): Likewise.
10331 (vcaddq_rot270_u16): Likewise.
10332 (vbicq_u16): Likewise.
10333 (vandq_u16): Likewise.
10334 (vaddvq_p_u16): Likewise.
10335 (vaddvaq_u16): Likewise.
10336 (vaddq_n_u16): Likewise.
10337 (vabdq_u16): Likewise.
10338 (vshlq_r_u16): Likewise.
10339 (vrshlq_u16): Likewise.
10340 (vrshlq_n_u16): Likewise.
10341 (vqshlq_u16): Likewise.
10342 (vqshlq_r_u16): Likewise.
10343 (vqrshlq_u16): Likewise.
10344 (vqrshlq_n_u16): Likewise.
10345 (vminavq_s16): Likewise.
10346 (vminaq_s16): Likewise.
10347 (vmaxavq_s16): Likewise.
10348 (vmaxaq_s16): Likewise.
10349 (vbrsrq_n_u16): Likewise.
10350 (vshlq_n_u16): Likewise.
10351 (vrshrq_n_u16): Likewise.
10352 (vqshlq_n_u16): Likewise.
10353 (vcmpneq_n_s16): Likewise.
10354 (vcmpltq_s16): Likewise.
10355 (vcmpltq_n_s16): Likewise.
10356 (vcmpleq_s16): Likewise.
10357 (vcmpleq_n_s16): Likewise.
10358 (vcmpgtq_s16): Likewise.
10359 (vcmpgtq_n_s16): Likewise.
10360 (vcmpgeq_s16): Likewise.
10361 (vcmpgeq_n_s16): Likewise.
10362 (vcmpeqq_s16): Likewise.
10363 (vcmpeqq_n_s16): Likewise.
10364 (vqshluq_n_s16): Likewise.
10365 (vaddvq_p_s16): Likewise.
10366 (vsubq_s16): Likewise.
10367 (vsubq_n_s16): Likewise.
10368 (vshlq_r_s16): Likewise.
10369 (vrshlq_s16): Likewise.
10370 (vrshlq_n_s16): Likewise.
10371 (vrmulhq_s16): Likewise.
10372 (vrhaddq_s16): Likewise.
10373 (vqsubq_s16): Likewise.
10374 (vqsubq_n_s16): Likewise.
10375 (vqshlq_s16): Likewise.
10376 (vqshlq_r_s16): Likewise.
10377 (vqrshlq_s16): Likewise.
10378 (vqrshlq_n_s16): Likewise.
10379 (vqrdmulhq_s16): Likewise.
10380 (vqrdmulhq_n_s16): Likewise.
10381 (vqdmulhq_s16): Likewise.
10382 (vqdmulhq_n_s16): Likewise.
10383 (vqaddq_s16): Likewise.
10384 (vqaddq_n_s16): Likewise.
10385 (vorrq_s16): Likewise.
10386 (vornq_s16): Likewise.
10387 (vmulq_s16): Likewise.
10388 (vmulq_n_s16): Likewise.
10389 (vmulltq_int_s16): Likewise.
10390 (vmullbq_int_s16): Likewise.
10391 (vmulhq_s16): Likewise.
10392 (vmlsdavxq_s16): Likewise.
10393 (vmlsdavq_s16): Likewise.
10394 (vmladavxq_s16): Likewise.
10395 (vmladavq_s16): Likewise.
10396 (vminvq_s16): Likewise.
10397 (vminq_s16): Likewise.
10398 (vmaxvq_s16): Likewise.
10399 (vmaxq_s16): Likewise.
10400 (vhsubq_s16): Likewise.
10401 (vhsubq_n_s16): Likewise.
10402 (vhcaddq_rot90_s16): Likewise.
10403 (vhcaddq_rot270_s16): Likewise.
10404 (vhaddq_s16): Likewise.
10405 (vhaddq_n_s16): Likewise.
10406 (veorq_s16): Likewise.
10407 (vcaddq_rot90_s16): Likewise.
10408 (vcaddq_rot270_s16): Likewise.
10409 (vbrsrq_n_s16): Likewise.
10410 (vbicq_s16): Likewise.
10411 (vandq_s16): Likewise.
10412 (vaddvaq_s16): Likewise.
10413 (vaddq_n_s16): Likewise.
10414 (vabdq_s16): Likewise.
10415 (vshlq_n_s16): Likewise.
10416 (vrshrq_n_s16): Likewise.
10417 (vqshlq_n_s16): Likewise.
10418 (vsubq_u32): Likewise.
10419 (vsubq_n_u32): Likewise.
10420 (vrmulhq_u32): Likewise.
10421 (vrhaddq_u32): Likewise.
10422 (vqsubq_u32): Likewise.
10423 (vqsubq_n_u32): Likewise.
10424 (vqaddq_u32): Likewise.
10425 (vqaddq_n_u32): Likewise.
10426 (vorrq_u32): Likewise.
10427 (vornq_u32): Likewise.
10428 (vmulq_u32): Likewise.
10429 (vmulq_n_u32): Likewise.
10430 (vmulltq_int_u32): Likewise.
10431 (vmullbq_int_u32): Likewise.
10432 (vmulhq_u32): Likewise.
10433 (vmladavq_u32): Likewise.
10434 (vminvq_u32): Likewise.
10435 (vminq_u32): Likewise.
10436 (vmaxvq_u32): Likewise.
10437 (vmaxq_u32): Likewise.
10438 (vhsubq_u32): Likewise.
10439 (vhsubq_n_u32): Likewise.
10440 (vhaddq_u32): Likewise.
10441 (vhaddq_n_u32): Likewise.
10442 (veorq_u32): Likewise.
10443 (vcmpneq_n_u32): Likewise.
10444 (vcmphiq_u32): Likewise.
10445 (vcmphiq_n_u32): Likewise.
10446 (vcmpeqq_u32): Likewise.
10447 (vcmpeqq_n_u32): Likewise.
10448 (vcmpcsq_u32): Likewise.
10449 (vcmpcsq_n_u32): Likewise.
10450 (vcaddq_rot90_u32): Likewise.
10451 (vcaddq_rot270_u32): Likewise.
10452 (vbicq_u32): Likewise.
10453 (vandq_u32): Likewise.
10454 (vaddvq_p_u32): Likewise.
10455 (vaddvaq_u32): Likewise.
10456 (vaddq_n_u32): Likewise.
10457 (vabdq_u32): Likewise.
10458 (vshlq_r_u32): Likewise.
10459 (vrshlq_u32): Likewise.
10460 (vrshlq_n_u32): Likewise.
10461 (vqshlq_u32): Likewise.
10462 (vqshlq_r_u32): Likewise.
10463 (vqrshlq_u32): Likewise.
10464 (vqrshlq_n_u32): Likewise.
10465 (vminavq_s32): Likewise.
10466 (vminaq_s32): Likewise.
10467 (vmaxavq_s32): Likewise.
10468 (vmaxaq_s32): Likewise.
10469 (vbrsrq_n_u32): Likewise.
10470 (vshlq_n_u32): Likewise.
10471 (vrshrq_n_u32): Likewise.
10472 (vqshlq_n_u32): Likewise.
10473 (vcmpneq_n_s32): Likewise.
10474 (vcmpltq_s32): Likewise.
10475 (vcmpltq_n_s32): Likewise.
10476 (vcmpleq_s32): Likewise.
10477 (vcmpleq_n_s32): Likewise.
10478 (vcmpgtq_s32): Likewise.
10479 (vcmpgtq_n_s32): Likewise.
10480 (vcmpgeq_s32): Likewise.
10481 (vcmpgeq_n_s32): Likewise.
10482 (vcmpeqq_s32): Likewise.
10483 (vcmpeqq_n_s32): Likewise.
10484 (vqshluq_n_s32): Likewise.
10485 (vaddvq_p_s32): Likewise.
10486 (vsubq_s32): Likewise.
10487 (vsubq_n_s32): Likewise.
10488 (vshlq_r_s32): Likewise.
10489 (vrshlq_s32): Likewise.
10490 (vrshlq_n_s32): Likewise.
10491 (vrmulhq_s32): Likewise.
10492 (vrhaddq_s32): Likewise.
10493 (vqsubq_s32): Likewise.
10494 (vqsubq_n_s32): Likewise.
10495 (vqshlq_s32): Likewise.
10496 (vqshlq_r_s32): Likewise.
10497 (vqrshlq_s32): Likewise.
10498 (vqrshlq_n_s32): Likewise.
10499 (vqrdmulhq_s32): Likewise.
10500 (vqrdmulhq_n_s32): Likewise.
10501 (vqdmulhq_s32): Likewise.
10502 (vqdmulhq_n_s32): Likewise.
10503 (vqaddq_s32): Likewise.
10504 (vqaddq_n_s32): Likewise.
10505 (vorrq_s32): Likewise.
10506 (vornq_s32): Likewise.
10507 (vmulq_s32): Likewise.
10508 (vmulq_n_s32): Likewise.
10509 (vmulltq_int_s32): Likewise.
10510 (vmullbq_int_s32): Likewise.
10511 (vmulhq_s32): Likewise.
10512 (vmlsdavxq_s32): Likewise.
10513 (vmlsdavq_s32): Likewise.
10514 (vmladavxq_s32): Likewise.
10515 (vmladavq_s32): Likewise.
10516 (vminvq_s32): Likewise.
10517 (vminq_s32): Likewise.
10518 (vmaxvq_s32): Likewise.
10519 (vmaxq_s32): Likewise.
10520 (vhsubq_s32): Likewise.
10521 (vhsubq_n_s32): Likewise.
10522 (vhcaddq_rot90_s32): Likewise.
10523 (vhcaddq_rot270_s32): Likewise.
10524 (vhaddq_s32): Likewise.
10525 (vhaddq_n_s32): Likewise.
10526 (veorq_s32): Likewise.
10527 (vcaddq_rot90_s32): Likewise.
10528 (vcaddq_rot270_s32): Likewise.
10529 (vbrsrq_n_s32): Likewise.
10530 (vbicq_s32): Likewise.
10531 (vandq_s32): Likewise.
10532 (vaddvaq_s32): Likewise.
10533 (vaddq_n_s32): Likewise.
10534 (vabdq_s32): Likewise.
10535 (vshlq_n_s32): Likewise.
10536 (vrshrq_n_s32): Likewise.
10537 (vqshlq_n_s32): Likewise.
10538 (__arm_vsubq_u8): Define intrinsic.
10539 (__arm_vsubq_n_u8): Likewise.
10540 (__arm_vrmulhq_u8): Likewise.
10541 (__arm_vrhaddq_u8): Likewise.
10542 (__arm_vqsubq_u8): Likewise.
10543 (__arm_vqsubq_n_u8): Likewise.
10544 (__arm_vqaddq_u8): Likewise.
10545 (__arm_vqaddq_n_u8): Likewise.
10546 (__arm_vorrq_u8): Likewise.
10547 (__arm_vornq_u8): Likewise.
10548 (__arm_vmulq_u8): Likewise.
10549 (__arm_vmulq_n_u8): Likewise.
10550 (__arm_vmulltq_int_u8): Likewise.
10551 (__arm_vmullbq_int_u8): Likewise.
10552 (__arm_vmulhq_u8): Likewise.
10553 (__arm_vmladavq_u8): Likewise.
10554 (__arm_vminvq_u8): Likewise.
10555 (__arm_vminq_u8): Likewise.
10556 (__arm_vmaxvq_u8): Likewise.
10557 (__arm_vmaxq_u8): Likewise.
10558 (__arm_vhsubq_u8): Likewise.
10559 (__arm_vhsubq_n_u8): Likewise.
10560 (__arm_vhaddq_u8): Likewise.
10561 (__arm_vhaddq_n_u8): Likewise.
10562 (__arm_veorq_u8): Likewise.
10563 (__arm_vcmpneq_n_u8): Likewise.
10564 (__arm_vcmphiq_u8): Likewise.
10565 (__arm_vcmphiq_n_u8): Likewise.
10566 (__arm_vcmpeqq_u8): Likewise.
10567 (__arm_vcmpeqq_n_u8): Likewise.
10568 (__arm_vcmpcsq_u8): Likewise.
10569 (__arm_vcmpcsq_n_u8): Likewise.
10570 (__arm_vcaddq_rot90_u8): Likewise.
10571 (__arm_vcaddq_rot270_u8): Likewise.
10572 (__arm_vbicq_u8): Likewise.
10573 (__arm_vandq_u8): Likewise.
10574 (__arm_vaddvq_p_u8): Likewise.
10575 (__arm_vaddvaq_u8): Likewise.
10576 (__arm_vaddq_n_u8): Likewise.
10577 (__arm_vabdq_u8): Likewise.
10578 (__arm_vshlq_r_u8): Likewise.
10579 (__arm_vrshlq_u8): Likewise.
10580 (__arm_vrshlq_n_u8): Likewise.
10581 (__arm_vqshlq_u8): Likewise.
10582 (__arm_vqshlq_r_u8): Likewise.
10583 (__arm_vqrshlq_u8): Likewise.
10584 (__arm_vqrshlq_n_u8): Likewise.
10585 (__arm_vminavq_s8): Likewise.
10586 (__arm_vminaq_s8): Likewise.
10587 (__arm_vmaxavq_s8): Likewise.
10588 (__arm_vmaxaq_s8): Likewise.
10589 (__arm_vbrsrq_n_u8): Likewise.
10590 (__arm_vshlq_n_u8): Likewise.
10591 (__arm_vrshrq_n_u8): Likewise.
10592 (__arm_vqshlq_n_u8): Likewise.
10593 (__arm_vcmpneq_n_s8): Likewise.
10594 (__arm_vcmpltq_s8): Likewise.
10595 (__arm_vcmpltq_n_s8): Likewise.
10596 (__arm_vcmpleq_s8): Likewise.
10597 (__arm_vcmpleq_n_s8): Likewise.
10598 (__arm_vcmpgtq_s8): Likewise.
10599 (__arm_vcmpgtq_n_s8): Likewise.
10600 (__arm_vcmpgeq_s8): Likewise.
10601 (__arm_vcmpgeq_n_s8): Likewise.
10602 (__arm_vcmpeqq_s8): Likewise.
10603 (__arm_vcmpeqq_n_s8): Likewise.
10604 (__arm_vqshluq_n_s8): Likewise.
10605 (__arm_vaddvq_p_s8): Likewise.
10606 (__arm_vsubq_s8): Likewise.
10607 (__arm_vsubq_n_s8): Likewise.
10608 (__arm_vshlq_r_s8): Likewise.
10609 (__arm_vrshlq_s8): Likewise.
10610 (__arm_vrshlq_n_s8): Likewise.
10611 (__arm_vrmulhq_s8): Likewise.
10612 (__arm_vrhaddq_s8): Likewise.
10613 (__arm_vqsubq_s8): Likewise.
10614 (__arm_vqsubq_n_s8): Likewise.
10615 (__arm_vqshlq_s8): Likewise.
10616 (__arm_vqshlq_r_s8): Likewise.
10617 (__arm_vqrshlq_s8): Likewise.
10618 (__arm_vqrshlq_n_s8): Likewise.
10619 (__arm_vqrdmulhq_s8): Likewise.
10620 (__arm_vqrdmulhq_n_s8): Likewise.
10621 (__arm_vqdmulhq_s8): Likewise.
10622 (__arm_vqdmulhq_n_s8): Likewise.
10623 (__arm_vqaddq_s8): Likewise.
10624 (__arm_vqaddq_n_s8): Likewise.
10625 (__arm_vorrq_s8): Likewise.
10626 (__arm_vornq_s8): Likewise.
10627 (__arm_vmulq_s8): Likewise.
10628 (__arm_vmulq_n_s8): Likewise.
10629 (__arm_vmulltq_int_s8): Likewise.
10630 (__arm_vmullbq_int_s8): Likewise.
10631 (__arm_vmulhq_s8): Likewise.
10632 (__arm_vmlsdavxq_s8): Likewise.
10633 (__arm_vmlsdavq_s8): Likewise.
10634 (__arm_vmladavxq_s8): Likewise.
10635 (__arm_vmladavq_s8): Likewise.
10636 (__arm_vminvq_s8): Likewise.
10637 (__arm_vminq_s8): Likewise.
10638 (__arm_vmaxvq_s8): Likewise.
10639 (__arm_vmaxq_s8): Likewise.
10640 (__arm_vhsubq_s8): Likewise.
10641 (__arm_vhsubq_n_s8): Likewise.
10642 (__arm_vhcaddq_rot90_s8): Likewise.
10643 (__arm_vhcaddq_rot270_s8): Likewise.
10644 (__arm_vhaddq_s8): Likewise.
10645 (__arm_vhaddq_n_s8): Likewise.
10646 (__arm_veorq_s8): Likewise.
10647 (__arm_vcaddq_rot90_s8): Likewise.
10648 (__arm_vcaddq_rot270_s8): Likewise.
10649 (__arm_vbrsrq_n_s8): Likewise.
10650 (__arm_vbicq_s8): Likewise.
10651 (__arm_vandq_s8): Likewise.
10652 (__arm_vaddvaq_s8): Likewise.
10653 (__arm_vaddq_n_s8): Likewise.
10654 (__arm_vabdq_s8): Likewise.
10655 (__arm_vshlq_n_s8): Likewise.
10656 (__arm_vrshrq_n_s8): Likewise.
10657 (__arm_vqshlq_n_s8): Likewise.
10658 (__arm_vsubq_u16): Likewise.
10659 (__arm_vsubq_n_u16): Likewise.
10660 (__arm_vrmulhq_u16): Likewise.
10661 (__arm_vrhaddq_u16): Likewise.
10662 (__arm_vqsubq_u16): Likewise.
10663 (__arm_vqsubq_n_u16): Likewise.
10664 (__arm_vqaddq_u16): Likewise.
10665 (__arm_vqaddq_n_u16): Likewise.
10666 (__arm_vorrq_u16): Likewise.
10667 (__arm_vornq_u16): Likewise.
10668 (__arm_vmulq_u16): Likewise.
10669 (__arm_vmulq_n_u16): Likewise.
10670 (__arm_vmulltq_int_u16): Likewise.
10671 (__arm_vmullbq_int_u16): Likewise.
10672 (__arm_vmulhq_u16): Likewise.
10673 (__arm_vmladavq_u16): Likewise.
10674 (__arm_vminvq_u16): Likewise.
10675 (__arm_vminq_u16): Likewise.
10676 (__arm_vmaxvq_u16): Likewise.
10677 (__arm_vmaxq_u16): Likewise.
10678 (__arm_vhsubq_u16): Likewise.
10679 (__arm_vhsubq_n_u16): Likewise.
10680 (__arm_vhaddq_u16): Likewise.
10681 (__arm_vhaddq_n_u16): Likewise.
10682 (__arm_veorq_u16): Likewise.
10683 (__arm_vcmpneq_n_u16): Likewise.
10684 (__arm_vcmphiq_u16): Likewise.
10685 (__arm_vcmphiq_n_u16): Likewise.
10686 (__arm_vcmpeqq_u16): Likewise.
10687 (__arm_vcmpeqq_n_u16): Likewise.
10688 (__arm_vcmpcsq_u16): Likewise.
10689 (__arm_vcmpcsq_n_u16): Likewise.
10690 (__arm_vcaddq_rot90_u16): Likewise.
10691 (__arm_vcaddq_rot270_u16): Likewise.
10692 (__arm_vbicq_u16): Likewise.
10693 (__arm_vandq_u16): Likewise.
10694 (__arm_vaddvq_p_u16): Likewise.
10695 (__arm_vaddvaq_u16): Likewise.
10696 (__arm_vaddq_n_u16): Likewise.
10697 (__arm_vabdq_u16): Likewise.
10698 (__arm_vshlq_r_u16): Likewise.
10699 (__arm_vrshlq_u16): Likewise.
10700 (__arm_vrshlq_n_u16): Likewise.
10701 (__arm_vqshlq_u16): Likewise.
10702 (__arm_vqshlq_r_u16): Likewise.
10703 (__arm_vqrshlq_u16): Likewise.
10704 (__arm_vqrshlq_n_u16): Likewise.
10705 (__arm_vminavq_s16): Likewise.
10706 (__arm_vminaq_s16): Likewise.
10707 (__arm_vmaxavq_s16): Likewise.
10708 (__arm_vmaxaq_s16): Likewise.
10709 (__arm_vbrsrq_n_u16): Likewise.
10710 (__arm_vshlq_n_u16): Likewise.
10711 (__arm_vrshrq_n_u16): Likewise.
10712 (__arm_vqshlq_n_u16): Likewise.
10713 (__arm_vcmpneq_n_s16): Likewise.
10714 (__arm_vcmpltq_s16): Likewise.
10715 (__arm_vcmpltq_n_s16): Likewise.
10716 (__arm_vcmpleq_s16): Likewise.
10717 (__arm_vcmpleq_n_s16): Likewise.
10718 (__arm_vcmpgtq_s16): Likewise.
10719 (__arm_vcmpgtq_n_s16): Likewise.
10720 (__arm_vcmpgeq_s16): Likewise.
10721 (__arm_vcmpgeq_n_s16): Likewise.
10722 (__arm_vcmpeqq_s16): Likewise.
10723 (__arm_vcmpeqq_n_s16): Likewise.
10724 (__arm_vqshluq_n_s16): Likewise.
10725 (__arm_vaddvq_p_s16): Likewise.
10726 (__arm_vsubq_s16): Likewise.
10727 (__arm_vsubq_n_s16): Likewise.
10728 (__arm_vshlq_r_s16): Likewise.
10729 (__arm_vrshlq_s16): Likewise.
10730 (__arm_vrshlq_n_s16): Likewise.
10731 (__arm_vrmulhq_s16): Likewise.
10732 (__arm_vrhaddq_s16): Likewise.
10733 (__arm_vqsubq_s16): Likewise.
10734 (__arm_vqsubq_n_s16): Likewise.
10735 (__arm_vqshlq_s16): Likewise.
10736 (__arm_vqshlq_r_s16): Likewise.
10737 (__arm_vqrshlq_s16): Likewise.
10738 (__arm_vqrshlq_n_s16): Likewise.
10739 (__arm_vqrdmulhq_s16): Likewise.
10740 (__arm_vqrdmulhq_n_s16): Likewise.
10741 (__arm_vqdmulhq_s16): Likewise.
10742 (__arm_vqdmulhq_n_s16): Likewise.
10743 (__arm_vqaddq_s16): Likewise.
10744 (__arm_vqaddq_n_s16): Likewise.
10745 (__arm_vorrq_s16): Likewise.
10746 (__arm_vornq_s16): Likewise.
10747 (__arm_vmulq_s16): Likewise.
10748 (__arm_vmulq_n_s16): Likewise.
10749 (__arm_vmulltq_int_s16): Likewise.
10750 (__arm_vmullbq_int_s16): Likewise.
10751 (__arm_vmulhq_s16): Likewise.
10752 (__arm_vmlsdavxq_s16): Likewise.
10753 (__arm_vmlsdavq_s16): Likewise.
10754 (__arm_vmladavxq_s16): Likewise.
10755 (__arm_vmladavq_s16): Likewise.
10756 (__arm_vminvq_s16): Likewise.
10757 (__arm_vminq_s16): Likewise.
10758 (__arm_vmaxvq_s16): Likewise.
10759 (__arm_vmaxq_s16): Likewise.
10760 (__arm_vhsubq_s16): Likewise.
10761 (__arm_vhsubq_n_s16): Likewise.
10762 (__arm_vhcaddq_rot90_s16): Likewise.
10763 (__arm_vhcaddq_rot270_s16): Likewise.
10764 (__arm_vhaddq_s16): Likewise.
10765 (__arm_vhaddq_n_s16): Likewise.
10766 (__arm_veorq_s16): Likewise.
10767 (__arm_vcaddq_rot90_s16): Likewise.
10768 (__arm_vcaddq_rot270_s16): Likewise.
10769 (__arm_vbrsrq_n_s16): Likewise.
10770 (__arm_vbicq_s16): Likewise.
10771 (__arm_vandq_s16): Likewise.
10772 (__arm_vaddvaq_s16): Likewise.
10773 (__arm_vaddq_n_s16): Likewise.
10774 (__arm_vabdq_s16): Likewise.
10775 (__arm_vshlq_n_s16): Likewise.
10776 (__arm_vrshrq_n_s16): Likewise.
10777 (__arm_vqshlq_n_s16): Likewise.
10778 (__arm_vsubq_u32): Likewise.
10779 (__arm_vsubq_n_u32): Likewise.
10780 (__arm_vrmulhq_u32): Likewise.
10781 (__arm_vrhaddq_u32): Likewise.
10782 (__arm_vqsubq_u32): Likewise.
10783 (__arm_vqsubq_n_u32): Likewise.
10784 (__arm_vqaddq_u32): Likewise.
10785 (__arm_vqaddq_n_u32): Likewise.
10786 (__arm_vorrq_u32): Likewise.
10787 (__arm_vornq_u32): Likewise.
10788 (__arm_vmulq_u32): Likewise.
10789 (__arm_vmulq_n_u32): Likewise.
10790 (__arm_vmulltq_int_u32): Likewise.
10791 (__arm_vmullbq_int_u32): Likewise.
10792 (__arm_vmulhq_u32): Likewise.
10793 (__arm_vmladavq_u32): Likewise.
10794 (__arm_vminvq_u32): Likewise.
10795 (__arm_vminq_u32): Likewise.
10796 (__arm_vmaxvq_u32): Likewise.
10797 (__arm_vmaxq_u32): Likewise.
10798 (__arm_vhsubq_u32): Likewise.
10799 (__arm_vhsubq_n_u32): Likewise.
10800 (__arm_vhaddq_u32): Likewise.
10801 (__arm_vhaddq_n_u32): Likewise.
10802 (__arm_veorq_u32): Likewise.
10803 (__arm_vcmpneq_n_u32): Likewise.
10804 (__arm_vcmphiq_u32): Likewise.
10805 (__arm_vcmphiq_n_u32): Likewise.
10806 (__arm_vcmpeqq_u32): Likewise.
10807 (__arm_vcmpeqq_n_u32): Likewise.
10808 (__arm_vcmpcsq_u32): Likewise.
10809 (__arm_vcmpcsq_n_u32): Likewise.
10810 (__arm_vcaddq_rot90_u32): Likewise.
10811 (__arm_vcaddq_rot270_u32): Likewise.
10812 (__arm_vbicq_u32): Likewise.
10813 (__arm_vandq_u32): Likewise.
10814 (__arm_vaddvq_p_u32): Likewise.
10815 (__arm_vaddvaq_u32): Likewise.
10816 (__arm_vaddq_n_u32): Likewise.
10817 (__arm_vabdq_u32): Likewise.
10818 (__arm_vshlq_r_u32): Likewise.
10819 (__arm_vrshlq_u32): Likewise.
10820 (__arm_vrshlq_n_u32): Likewise.
10821 (__arm_vqshlq_u32): Likewise.
10822 (__arm_vqshlq_r_u32): Likewise.
10823 (__arm_vqrshlq_u32): Likewise.
10824 (__arm_vqrshlq_n_u32): Likewise.
10825 (__arm_vminavq_s32): Likewise.
10826 (__arm_vminaq_s32): Likewise.
10827 (__arm_vmaxavq_s32): Likewise.
10828 (__arm_vmaxaq_s32): Likewise.
10829 (__arm_vbrsrq_n_u32): Likewise.
10830 (__arm_vshlq_n_u32): Likewise.
10831 (__arm_vrshrq_n_u32): Likewise.
10832 (__arm_vqshlq_n_u32): Likewise.
10833 (__arm_vcmpneq_n_s32): Likewise.
10834 (__arm_vcmpltq_s32): Likewise.
10835 (__arm_vcmpltq_n_s32): Likewise.
10836 (__arm_vcmpleq_s32): Likewise.
10837 (__arm_vcmpleq_n_s32): Likewise.
10838 (__arm_vcmpgtq_s32): Likewise.
10839 (__arm_vcmpgtq_n_s32): Likewise.
10840 (__arm_vcmpgeq_s32): Likewise.
10841 (__arm_vcmpgeq_n_s32): Likewise.
10842 (__arm_vcmpeqq_s32): Likewise.
10843 (__arm_vcmpeqq_n_s32): Likewise.
10844 (__arm_vqshluq_n_s32): Likewise.
10845 (__arm_vaddvq_p_s32): Likewise.
10846 (__arm_vsubq_s32): Likewise.
10847 (__arm_vsubq_n_s32): Likewise.
10848 (__arm_vshlq_r_s32): Likewise.
10849 (__arm_vrshlq_s32): Likewise.
10850 (__arm_vrshlq_n_s32): Likewise.
10851 (__arm_vrmulhq_s32): Likewise.
10852 (__arm_vrhaddq_s32): Likewise.
10853 (__arm_vqsubq_s32): Likewise.
10854 (__arm_vqsubq_n_s32): Likewise.
10855 (__arm_vqshlq_s32): Likewise.
10856 (__arm_vqshlq_r_s32): Likewise.
10857 (__arm_vqrshlq_s32): Likewise.
10858 (__arm_vqrshlq_n_s32): Likewise.
10859 (__arm_vqrdmulhq_s32): Likewise.
10860 (__arm_vqrdmulhq_n_s32): Likewise.
10861 (__arm_vqdmulhq_s32): Likewise.
10862 (__arm_vqdmulhq_n_s32): Likewise.
10863 (__arm_vqaddq_s32): Likewise.
10864 (__arm_vqaddq_n_s32): Likewise.
10865 (__arm_vorrq_s32): Likewise.
10866 (__arm_vornq_s32): Likewise.
10867 (__arm_vmulq_s32): Likewise.
10868 (__arm_vmulq_n_s32): Likewise.
10869 (__arm_vmulltq_int_s32): Likewise.
10870 (__arm_vmullbq_int_s32): Likewise.
10871 (__arm_vmulhq_s32): Likewise.
10872 (__arm_vmlsdavxq_s32): Likewise.
10873 (__arm_vmlsdavq_s32): Likewise.
10874 (__arm_vmladavxq_s32): Likewise.
10875 (__arm_vmladavq_s32): Likewise.
10876 (__arm_vminvq_s32): Likewise.
10877 (__arm_vminq_s32): Likewise.
10878 (__arm_vmaxvq_s32): Likewise.
10879 (__arm_vmaxq_s32): Likewise.
10880 (__arm_vhsubq_s32): Likewise.
10881 (__arm_vhsubq_n_s32): Likewise.
10882 (__arm_vhcaddq_rot90_s32): Likewise.
10883 (__arm_vhcaddq_rot270_s32): Likewise.
10884 (__arm_vhaddq_s32): Likewise.
10885 (__arm_vhaddq_n_s32): Likewise.
10886 (__arm_veorq_s32): Likewise.
10887 (__arm_vcaddq_rot90_s32): Likewise.
10888 (__arm_vcaddq_rot270_s32): Likewise.
10889 (__arm_vbrsrq_n_s32): Likewise.
10890 (__arm_vbicq_s32): Likewise.
10891 (__arm_vandq_s32): Likewise.
10892 (__arm_vaddvaq_s32): Likewise.
10893 (__arm_vaddq_n_s32): Likewise.
10894 (__arm_vabdq_s32): Likewise.
10895 (__arm_vshlq_n_s32): Likewise.
10896 (__arm_vrshrq_n_s32): Likewise.
10897 (__arm_vqshlq_n_s32): Likewise.
10898 (vsubq): Define polymorphic variant.
10899 (vsubq_n): Likewise.
10900 (vshlq_r): Likewise.
10901 (vrshlq_n): Likewise.
10902 (vrshlq): Likewise.
10903 (vrmulhq): Likewise.
10904 (vrhaddq): Likewise.
10905 (vqsubq_n): Likewise.
10906 (vqsubq): Likewise.
10907 (vqshlq): Likewise.
10908 (vqshlq_r): Likewise.
10909 (vqshluq): Likewise.
10910 (vrshrq_n): Likewise.
10911 (vshlq_n): Likewise.
10912 (vqshluq_n): Likewise.
10913 (vqshlq_n): Likewise.
10914 (vqrshlq_n): Likewise.
10915 (vqrshlq): Likewise.
10916 (vqrdmulhq_n): Likewise.
10917 (vqrdmulhq): Likewise.
10918 (vqdmulhq_n): Likewise.
10919 (vqdmulhq): Likewise.
10920 (vqaddq_n): Likewise.
10921 (vqaddq): Likewise.
10922 (vorrq_n): Likewise.
10925 (vmulq_n): Likewise.
10927 (vmulltq_int): Likewise.
10928 (vmullbq_int): Likewise.
10929 (vmulhq): Likewise.
10931 (vminaq): Likewise.
10933 (vmaxaq): Likewise.
10934 (vhsubq_n): Likewise.
10935 (vhsubq): Likewise.
10936 (vhcaddq_rot90): Likewise.
10937 (vhcaddq_rot270): Likewise.
10938 (vhaddq_n): Likewise.
10939 (vhaddq): Likewise.
10941 (vcaddq_rot90): Likewise.
10942 (vcaddq_rot270): Likewise.
10943 (vbrsrq_n): Likewise.
10944 (vbicq_n): Likewise.
10947 (vaddq_n): Likewise.
10950 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
10951 (BINOP_NONE_NONE_NONE): Likewise.
10952 (BINOP_NONE_NONE_UNONE): Likewise.
10953 (BINOP_UNONE_NONE_IMM): Likewise.
10954 (BINOP_UNONE_NONE_NONE): Likewise.
10955 (BINOP_UNONE_UNONE_IMM): Likewise.
10956 (BINOP_UNONE_UNONE_NONE): Likewise.
10957 (BINOP_UNONE_UNONE_UNONE): Likewise.
10958 * config/arm/constraints.md (Ra): Define constraint to check constant is
10959 in the range of 0 to 7.
10960 (Rg): Define constriant to check the constant is one among 1, 2, 4
10962 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern.
10963 (mve_vaddq_n_<supf>): Likewise.
10964 (mve_vaddvaq_<supf>): Likewise.
10965 (mve_vaddvq_p_<supf>): Likewise.
10966 (mve_vandq_<supf>): Likewise.
10967 (mve_vbicq_<supf>): Likewise.
10968 (mve_vbrsrq_n_<supf>): Likewise.
10969 (mve_vcaddq_rot270_<supf>): Likewise.
10970 (mve_vcaddq_rot90_<supf>): Likewise.
10971 (mve_vcmpcsq_n_u): Likewise.
10972 (mve_vcmpcsq_u): Likewise.
10973 (mve_vcmpeqq_n_<supf>): Likewise.
10974 (mve_vcmpeqq_<supf>): Likewise.
10975 (mve_vcmpgeq_n_s): Likewise.
10976 (mve_vcmpgeq_s): Likewise.
10977 (mve_vcmpgtq_n_s): Likewise.
10978 (mve_vcmpgtq_s): Likewise.
10979 (mve_vcmphiq_n_u): Likewise.
10980 (mve_vcmphiq_u): Likewise.
10981 (mve_vcmpleq_n_s): Likewise.
10982 (mve_vcmpleq_s): Likewise.
10983 (mve_vcmpltq_n_s): Likewise.
10984 (mve_vcmpltq_s): Likewise.
10985 (mve_vcmpneq_n_<supf>): Likewise.
10986 (mve_vddupq_n_u): Likewise.
10987 (mve_veorq_<supf>): Likewise.
10988 (mve_vhaddq_n_<supf>): Likewise.
10989 (mve_vhaddq_<supf>): Likewise.
10990 (mve_vhcaddq_rot270_s): Likewise.
10991 (mve_vhcaddq_rot90_s): Likewise.
10992 (mve_vhsubq_n_<supf>): Likewise.
10993 (mve_vhsubq_<supf>): Likewise.
10994 (mve_vidupq_n_u): Likewise.
10995 (mve_vmaxaq_s): Likewise.
10996 (mve_vmaxavq_s): Likewise.
10997 (mve_vmaxq_<supf>): Likewise.
10998 (mve_vmaxvq_<supf>): Likewise.
10999 (mve_vminaq_s): Likewise.
11000 (mve_vminavq_s): Likewise.
11001 (mve_vminq_<supf>): Likewise.
11002 (mve_vminvq_<supf>): Likewise.
11003 (mve_vmladavq_<supf>): Likewise.
11004 (mve_vmladavxq_s): Likewise.
11005 (mve_vmlsdavq_s): Likewise.
11006 (mve_vmlsdavxq_s): Likewise.
11007 (mve_vmulhq_<supf>): Likewise.
11008 (mve_vmullbq_int_<supf>): Likewise.
11009 (mve_vmulltq_int_<supf>): Likewise.
11010 (mve_vmulq_n_<supf>): Likewise.
11011 (mve_vmulq_<supf>): Likewise.
11012 (mve_vornq_<supf>): Likewise.
11013 (mve_vorrq_<supf>): Likewise.
11014 (mve_vqaddq_n_<supf>): Likewise.
11015 (mve_vqaddq_<supf>): Likewise.
11016 (mve_vqdmulhq_n_s): Likewise.
11017 (mve_vqdmulhq_s): Likewise.
11018 (mve_vqrdmulhq_n_s): Likewise.
11019 (mve_vqrdmulhq_s): Likewise.
11020 (mve_vqrshlq_n_<supf>): Likewise.
11021 (mve_vqrshlq_<supf>): Likewise.
11022 (mve_vqshlq_n_<supf>): Likewise.
11023 (mve_vqshlq_r_<supf>): Likewise.
11024 (mve_vqshlq_<supf>): Likewise.
11025 (mve_vqshluq_n_s): Likewise.
11026 (mve_vqsubq_n_<supf>): Likewise.
11027 (mve_vqsubq_<supf>): Likewise.
11028 (mve_vrhaddq_<supf>): Likewise.
11029 (mve_vrmulhq_<supf>): Likewise.
11030 (mve_vrshlq_n_<supf>): Likewise.
11031 (mve_vrshlq_<supf>): Likewise.
11032 (mve_vrshrq_n_<supf>): Likewise.
11033 (mve_vshlq_n_<supf>): Likewise.
11034 (mve_vshlq_r_<supf>): Likewise.
11035 (mve_vsubq_n_<supf>): Likewise.
11036 (mve_vsubq_<supf>): Likewise.
11037 * config/arm/predicates.md (mve_imm_7): Define predicate to check
11038 the matching constraint Ra.
11039 (mve_imm_selective_upto_8): Define predicate to check the matching
11042 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11043 Mihail Ionescu <mihail.ionescu@arm.com>
11044 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11046 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define
11047 qualifier for binary operands.
11048 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
11049 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
11050 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro.
11051 (vaddlvq_p_u32): Likewise.
11052 (vcmpneq_s8): Likewise.
11053 (vcmpneq_s16): Likewise.
11054 (vcmpneq_s32): Likewise.
11055 (vcmpneq_u8): Likewise.
11056 (vcmpneq_u16): Likewise.
11057 (vcmpneq_u32): Likewise.
11058 (vshlq_s8): Likewise.
11059 (vshlq_s16): Likewise.
11060 (vshlq_s32): Likewise.
11061 (vshlq_u8): Likewise.
11062 (vshlq_u16): Likewise.
11063 (vshlq_u32): Likewise.
11064 (__arm_vaddlvq_p_s32): Define intrinsic.
11065 (__arm_vaddlvq_p_u32): Likewise.
11066 (__arm_vcmpneq_s8): Likewise.
11067 (__arm_vcmpneq_s16): Likewise.
11068 (__arm_vcmpneq_s32): Likewise.
11069 (__arm_vcmpneq_u8): Likewise.
11070 (__arm_vcmpneq_u16): Likewise.
11071 (__arm_vcmpneq_u32): Likewise.
11072 (__arm_vshlq_s8): Likewise.
11073 (__arm_vshlq_s16): Likewise.
11074 (__arm_vshlq_s32): Likewise.
11075 (__arm_vshlq_u8): Likewise.
11076 (__arm_vshlq_u16): Likewise.
11077 (__arm_vshlq_u32): Likewise.
11078 (vaddlvq_p): Define polymorphic variant.
11079 (vcmpneq): Likewise.
11081 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS):
11083 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
11084 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
11085 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern.
11086 (mve_vcmpneq_<supf><mode>): Likewise.
11087 (mve_vshlq_<supf><mode>): Likewise.
11089 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11090 Mihail Ionescu <mihail.ionescu@arm.com>
11091 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11093 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
11094 qualifier for binary operands.
11095 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
11096 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
11097 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
11098 (vcvtq_n_s32_f32): Likewise.
11099 (vcvtq_n_u16_f16): Likewise.
11100 (vcvtq_n_u32_f32): Likewise.
11101 (vcreateq_u8): Likewise.
11102 (vcreateq_u16): Likewise.
11103 (vcreateq_u32): Likewise.
11104 (vcreateq_u64): Likewise.
11105 (vcreateq_s8): Likewise.
11106 (vcreateq_s16): Likewise.
11107 (vcreateq_s32): Likewise.
11108 (vcreateq_s64): Likewise.
11109 (vshrq_n_s8): Likewise.
11110 (vshrq_n_s16): Likewise.
11111 (vshrq_n_s32): Likewise.
11112 (vshrq_n_u8): Likewise.
11113 (vshrq_n_u16): Likewise.
11114 (vshrq_n_u32): Likewise.
11115 (__arm_vcreateq_u8): Define intrinsic.
11116 (__arm_vcreateq_u16): Likewise.
11117 (__arm_vcreateq_u32): Likewise.
11118 (__arm_vcreateq_u64): Likewise.
11119 (__arm_vcreateq_s8): Likewise.
11120 (__arm_vcreateq_s16): Likewise.
11121 (__arm_vcreateq_s32): Likewise.
11122 (__arm_vcreateq_s64): Likewise.
11123 (__arm_vshrq_n_s8): Likewise.
11124 (__arm_vshrq_n_s16): Likewise.
11125 (__arm_vshrq_n_s32): Likewise.
11126 (__arm_vshrq_n_u8): Likewise.
11127 (__arm_vshrq_n_u16): Likewise.
11128 (__arm_vshrq_n_u32): Likewise.
11129 (__arm_vcvtq_n_s16_f16): Likewise.
11130 (__arm_vcvtq_n_s32_f32): Likewise.
11131 (__arm_vcvtq_n_u16_f16): Likewise.
11132 (__arm_vcvtq_n_u32_f32): Likewise.
11133 (vshrq_n): Define polymorphic variant.
11134 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
11136 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
11137 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
11138 * config/arm/constraints.md (Rb): Define constraint to check constant is
11139 in the range of 1 to 8.
11140 (Rf): Define constraint to check constant is in the range of 1 to 32.
11141 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
11142 (mve_vshrq_n_<supf><mode>): Likewise.
11143 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
11144 * config/arm/predicates.md (mve_imm_8): Define predicate to check
11145 the matching constraint Rb.
11146 (mve_imm_32): Define predicate to check the matching constraint Rf.
11148 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11149 Mihail Ionescu <mihail.ionescu@arm.com>
11150 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11152 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
11153 qualifier for binary operands.
11154 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
11155 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
11156 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
11157 * config/arm/arm_mve.h (vsubq_n_f16): Define macro.
11158 (vsubq_n_f32): Likewise.
11159 (vbrsrq_n_f16): Likewise.
11160 (vbrsrq_n_f32): Likewise.
11161 (vcvtq_n_f16_s16): Likewise.
11162 (vcvtq_n_f32_s32): Likewise.
11163 (vcvtq_n_f16_u16): Likewise.
11164 (vcvtq_n_f32_u32): Likewise.
11165 (vcreateq_f16): Likewise.
11166 (vcreateq_f32): Likewise.
11167 (__arm_vsubq_n_f16): Define intrinsic.
11168 (__arm_vsubq_n_f32): Likewise.
11169 (__arm_vbrsrq_n_f16): Likewise.
11170 (__arm_vbrsrq_n_f32): Likewise.
11171 (__arm_vcvtq_n_f16_s16): Likewise.
11172 (__arm_vcvtq_n_f32_s32): Likewise.
11173 (__arm_vcvtq_n_f16_u16): Likewise.
11174 (__arm_vcvtq_n_f32_u32): Likewise.
11175 (__arm_vcreateq_f16): Likewise.
11176 (__arm_vcreateq_f32): Likewise.
11177 (vsubq): Define polymorphic variant.
11178 (vbrsrq): Likewise.
11179 (vcvtq_n): Likewise.
11180 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use
11182 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
11183 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
11184 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
11185 * config/arm/constraints.md (Rd): Define constraint to check constant is
11186 in the range of 1 to 16.
11187 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern.
11188 mve_vbrsrq_n_f<mode>: Likewise.
11189 mve_vcvtq_n_to_f_<supf><mode>: Likewise.
11190 mve_vcreateq_f<mode>: Likewise.
11191 * config/arm/predicates.md (mve_imm_16): Define predicate to check
11192 the matching constraint Rd.
11194 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11195 Mihail Ionescu <mihail.ionescu@arm.com>
11196 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11198 * config/arm/arm-builtins.c (hi_UP): Define mode.
11199 * config/arm/arm.h (IS_VPR_REGNUM): Move.
11200 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
11201 (APSRQ_REGNUM): Modify.
11202 (APSRGE_REGNUM): Modify.
11203 * config/arm/arm_mve.h (vctp16q): Define macro.
11204 (vctp32q): Likewise.
11205 (vctp64q): Likewise.
11206 (vctp8q): Likewise.
11208 (__arm_vctp16q): Define intrinsic.
11209 (__arm_vctp32q): Likewise.
11210 (__arm_vctp64q): Likewise.
11211 (__arm_vctp8q): Likewise.
11212 (__arm_vpnot): Likewise.
11213 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
11215 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
11216 (mve_vpnothi): Likewise.
11218 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11219 Mihail Ionescu <mihail.ionescu@arm.com>
11220 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11222 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
11223 * config/arm/arm_mve.h (vdupq_n_s8): Define macro.
11224 (vdupq_n_s16): Likewise.
11225 (vdupq_n_s32): Likewise.
11226 (vabsq_s8): Likewise.
11227 (vabsq_s16): Likewise.
11228 (vabsq_s32): Likewise.
11229 (vclsq_s8): Likewise.
11230 (vclsq_s16): Likewise.
11231 (vclsq_s32): Likewise.
11232 (vclzq_s8): Likewise.
11233 (vclzq_s16): Likewise.
11234 (vclzq_s32): Likewise.
11235 (vnegq_s8): Likewise.
11236 (vnegq_s16): Likewise.
11237 (vnegq_s32): Likewise.
11238 (vaddlvq_s32): Likewise.
11239 (vaddvq_s8): Likewise.
11240 (vaddvq_s16): Likewise.
11241 (vaddvq_s32): Likewise.
11242 (vmovlbq_s8): Likewise.
11243 (vmovlbq_s16): Likewise.
11244 (vmovltq_s8): Likewise.
11245 (vmovltq_s16): Likewise.
11246 (vmvnq_s8): Likewise.
11247 (vmvnq_s16): Likewise.
11248 (vmvnq_s32): Likewise.
11249 (vrev16q_s8): Likewise.
11250 (vrev32q_s8): Likewise.
11251 (vrev32q_s16): Likewise.
11252 (vqabsq_s8): Likewise.
11253 (vqabsq_s16): Likewise.
11254 (vqabsq_s32): Likewise.
11255 (vqnegq_s8): Likewise.
11256 (vqnegq_s16): Likewise.
11257 (vqnegq_s32): Likewise.
11258 (vcvtaq_s16_f16): Likewise.
11259 (vcvtaq_s32_f32): Likewise.
11260 (vcvtnq_s16_f16): Likewise.
11261 (vcvtnq_s32_f32): Likewise.
11262 (vcvtpq_s16_f16): Likewise.
11263 (vcvtpq_s32_f32): Likewise.
11264 (vcvtmq_s16_f16): Likewise.
11265 (vcvtmq_s32_f32): Likewise.
11266 (vmvnq_u8): Likewise.
11267 (vmvnq_u16): Likewise.
11268 (vmvnq_u32): Likewise.
11269 (vdupq_n_u8): Likewise.
11270 (vdupq_n_u16): Likewise.
11271 (vdupq_n_u32): Likewise.
11272 (vclzq_u8): Likewise.
11273 (vclzq_u16): Likewise.
11274 (vclzq_u32): Likewise.
11275 (vaddvq_u8): Likewise.
11276 (vaddvq_u16): Likewise.
11277 (vaddvq_u32): Likewise.
11278 (vrev32q_u8): Likewise.
11279 (vrev32q_u16): Likewise.
11280 (vmovltq_u8): Likewise.
11281 (vmovltq_u16): Likewise.
11282 (vmovlbq_u8): Likewise.
11283 (vmovlbq_u16): Likewise.
11284 (vrev16q_u8): Likewise.
11285 (vaddlvq_u32): Likewise.
11286 (vcvtpq_u16_f16): Likewise.
11287 (vcvtpq_u32_f32): Likewise.
11288 (vcvtnq_u16_f16): Likewise.
11289 (vcvtmq_u16_f16): Likewise.
11290 (vcvtmq_u32_f32): Likewise.
11291 (vcvtaq_u16_f16): Likewise.
11292 (vcvtaq_u32_f32): Likewise.
11293 (__arm_vdupq_n_s8): Define intrinsic.
11294 (__arm_vdupq_n_s16): Likewise.
11295 (__arm_vdupq_n_s32): Likewise.
11296 (__arm_vabsq_s8): Likewise.
11297 (__arm_vabsq_s16): Likewise.
11298 (__arm_vabsq_s32): Likewise.
11299 (__arm_vclsq_s8): Likewise.
11300 (__arm_vclsq_s16): Likewise.
11301 (__arm_vclsq_s32): Likewise.
11302 (__arm_vclzq_s8): Likewise.
11303 (__arm_vclzq_s16): Likewise.
11304 (__arm_vclzq_s32): Likewise.
11305 (__arm_vnegq_s8): Likewise.
11306 (__arm_vnegq_s16): Likewise.
11307 (__arm_vnegq_s32): Likewise.
11308 (__arm_vaddlvq_s32): Likewise.
11309 (__arm_vaddvq_s8): Likewise.
11310 (__arm_vaddvq_s16): Likewise.
11311 (__arm_vaddvq_s32): Likewise.
11312 (__arm_vmovlbq_s8): Likewise.
11313 (__arm_vmovlbq_s16): Likewise.
11314 (__arm_vmovltq_s8): Likewise.
11315 (__arm_vmovltq_s16): Likewise.
11316 (__arm_vmvnq_s8): Likewise.
11317 (__arm_vmvnq_s16): Likewise.
11318 (__arm_vmvnq_s32): Likewise.
11319 (__arm_vrev16q_s8): Likewise.
11320 (__arm_vrev32q_s8): Likewise.
11321 (__arm_vrev32q_s16): Likewise.
11322 (__arm_vqabsq_s8): Likewise.
11323 (__arm_vqabsq_s16): Likewise.
11324 (__arm_vqabsq_s32): Likewise.
11325 (__arm_vqnegq_s8): Likewise.
11326 (__arm_vqnegq_s16): Likewise.
11327 (__arm_vqnegq_s32): Likewise.
11328 (__arm_vmvnq_u8): Likewise.
11329 (__arm_vmvnq_u16): Likewise.
11330 (__arm_vmvnq_u32): Likewise.
11331 (__arm_vdupq_n_u8): Likewise.
11332 (__arm_vdupq_n_u16): Likewise.
11333 (__arm_vdupq_n_u32): Likewise.
11334 (__arm_vclzq_u8): Likewise.
11335 (__arm_vclzq_u16): Likewise.
11336 (__arm_vclzq_u32): Likewise.
11337 (__arm_vaddvq_u8): Likewise.
11338 (__arm_vaddvq_u16): Likewise.
11339 (__arm_vaddvq_u32): Likewise.
11340 (__arm_vrev32q_u8): Likewise.
11341 (__arm_vrev32q_u16): Likewise.
11342 (__arm_vmovltq_u8): Likewise.
11343 (__arm_vmovltq_u16): Likewise.
11344 (__arm_vmovlbq_u8): Likewise.
11345 (__arm_vmovlbq_u16): Likewise.
11346 (__arm_vrev16q_u8): Likewise.
11347 (__arm_vaddlvq_u32): Likewise.
11348 (__arm_vcvtpq_u16_f16): Likewise.
11349 (__arm_vcvtpq_u32_f32): Likewise.
11350 (__arm_vcvtnq_u16_f16): Likewise.
11351 (__arm_vcvtmq_u16_f16): Likewise.
11352 (__arm_vcvtmq_u32_f32): Likewise.
11353 (__arm_vcvtaq_u16_f16): Likewise.
11354 (__arm_vcvtaq_u32_f32): Likewise.
11355 (__arm_vcvtaq_s16_f16): Likewise.
11356 (__arm_vcvtaq_s32_f32): Likewise.
11357 (__arm_vcvtnq_s16_f16): Likewise.
11358 (__arm_vcvtnq_s32_f32): Likewise.
11359 (__arm_vcvtpq_s16_f16): Likewise.
11360 (__arm_vcvtpq_s32_f32): Likewise.
11361 (__arm_vcvtmq_s16_f16): Likewise.
11362 (__arm_vcvtmq_s32_f32): Likewise.
11363 (vdupq_n): Define polymorphic variant.
11368 (vaddlvq): Likewise.
11369 (vaddvq): Likewise.
11370 (vmovlbq): Likewise.
11371 (vmovltq): Likewise.
11373 (vrev16q): Likewise.
11374 (vrev32q): Likewise.
11375 (vqabsq): Likewise.
11376 (vqnegq): Likewise.
11377 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
11378 (UNOP_SNONE_NONE): Likewise.
11379 (UNOP_UNONE_UNONE): Likewise.
11380 (UNOP_UNONE_NONE): Likewise.
11381 * config/arm/constraints.md (e): Define new constriant to allow only
11383 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
11384 (mve_vnegq_s<mode>): Likewise.
11385 (mve_vmvnq_<supf><mode>): Likewise.
11386 (mve_vdupq_n_<supf><mode>): Likewise.
11387 (mve_vclzq_<supf><mode>): Likewise.
11388 (mve_vclsq_s<mode>): Likewise.
11389 (mve_vaddvq_<supf><mode>): Likewise.
11390 (mve_vabsq_s<mode>): Likewise.
11391 (mve_vrev32q_<supf><mode>): Likewise.
11392 (mve_vmovltq_<supf><mode>): Likewise.
11393 (mve_vmovlbq_<supf><mode>): Likewise.
11394 (mve_vcvtpq_<supf><mode>): Likewise.
11395 (mve_vcvtnq_<supf><mode>): Likewise.
11396 (mve_vcvtmq_<supf><mode>): Likewise.
11397 (mve_vcvtaq_<supf><mode>): Likewise.
11398 (mve_vrev16q_<supf>v16qi): Likewise.
11399 (mve_vaddlvq_<supf>v4si): Likewise.
11401 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11403 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in
11405 * tree-sra.c (create_access_replacement): Fix up duplicated word issue
11407 * read-rtl-function.c (find_param_by_name,
11408 function_reader::parse_enum_value, function_reader::get_insn_by_uid):
11410 * spellcheck.c (get_edit_distance_cutoff): Likewise.
11411 * tree-data-ref.c (create_ifn_alias_checks): Likewise.
11412 * tree.def (SWITCH_EXPR): Likewise.
11413 * selftest.c (assert_str_contains): Likewise.
11414 * ipa-param-manipulation.h (class ipa_param_body_adjustments):
11416 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise.
11417 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise.
11418 * langhooks.h (struct lang_hooks_for_decls): Likewise.
11419 * ipa-prop.h (struct ipa_param_descriptor): Likewise.
11420 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store):
11422 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise.
11423 * tree-ssa-reassoc.c (reassociate_bb): Likewise.
11424 * tree.c (component_ref_size): Likewise.
11425 * hsa-common.c (hsa_init_compilation_unit_data): Likewise.
11426 * gimple-ssa-sprintf.c (get_string_length, format_string,
11427 format_directive): Likewise.
11428 * omp-grid.c (grid_process_kernel_body_copy): Likewise.
11429 * input.c (string_concat_db::get_string_concatenation,
11430 test_lexer_string_locations_ucn4): Likewise.
11431 * cfgexpand.c (pass_expand::execute): Likewise.
11432 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds,
11433 maybe_diag_overlap): Likewise.
11434 * rtl.c (RTX_CODE_HWINT_P_1): Likewise.
11435 * shrink-wrap.c (spread_components): Likewise.
11436 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse):
11438 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
11440 * dwarf2out.c (dwarf2out_early_finish): Likewise.
11441 * gimple-ssa-store-merging.c: Likewise.
11442 * ira-costs.c (record_operand_costs): Likewise.
11443 * tree-vect-loop.c (vectorizable_reduction): Likewise.
11444 * target.def (dispatch): Likewise.
11445 (validate_dims, gen_ccmp_first): Fix up duplicated word issue
11446 in documentation text.
11447 * doc/tm.texi: Regenerated.
11448 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up
11449 duplicated word issue in a comment.
11450 * config/i386/i386.c (ix86_test_loading_unspec): Likewise.
11451 * config/i386/i386-features.c (remove_partial_avx_dependency):
11453 * config/msp430/msp430.c (msp430_select_section): Likewise.
11454 * config/gcn/gcn-run.c (load_image): Likewise.
11455 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise.
11456 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise.
11457 * config/aarch64/falkor-tag-collision-avoidance.c
11458 (single_dest_per_chain): Likewise.
11459 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise.
11460 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise.
11461 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise.
11462 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant):
11464 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise.
11465 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise.
11466 * config/rs6000/rs6000-logue.c
11467 (rs6000_emit_probe_stack_range_stack_clash): Likewise.
11468 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise.
11469 Fix various other issues in the comment.
11471 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
11473 * config/arm/t-rmprofile: create new multilib for
11474 armv8.1-m.main+mve hard float and reuse v8-m.main ones for
11477 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11479 PR tree-optimization/94015
11480 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the
11481 function where EXP is address of the bytes being stored rather than
11482 the bytes themselves into count_nonzero_bytes_addr. Punt on zero
11483 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs.
11484 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before
11485 calling native_encode_expr if host or target doesn't have 8-bit
11486 chars. Formatting fixes.
11487 (count_nonzero_bytes_addr): New function.
11489 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11490 Mihail Ionescu <mihail.ionescu@arm.com>
11491 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11493 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define.
11494 (UNOP_SNONE_NONE_QUALIFIERS): Likewise.
11495 (UNOP_SNONE_IMM_QUALIFIERS): Likewise.
11496 (UNOP_UNONE_NONE_QUALIFIERS): Likewise.
11497 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise.
11498 (UNOP_UNONE_IMM_QUALIFIERS): Likewise.
11499 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro.
11500 (vmvnq_n_s32): Likewise.
11501 (vrev64q_s8): Likewise.
11502 (vrev64q_s16): Likewise.
11503 (vrev64q_s32): Likewise.
11504 (vcvtq_s16_f16): Likewise.
11505 (vcvtq_s32_f32): Likewise.
11506 (vrev64q_u8): Likewise.
11507 (vrev64q_u16): Likewise.
11508 (vrev64q_u32): Likewise.
11509 (vmvnq_n_u16): Likewise.
11510 (vmvnq_n_u32): Likewise.
11511 (vcvtq_u16_f16): Likewise.
11512 (vcvtq_u32_f32): Likewise.
11513 (__arm_vmvnq_n_s16): Define intrinsic.
11514 (__arm_vmvnq_n_s32): Likewise.
11515 (__arm_vrev64q_s8): Likewise.
11516 (__arm_vrev64q_s16): Likewise.
11517 (__arm_vrev64q_s32): Likewise.
11518 (__arm_vrev64q_u8): Likewise.
11519 (__arm_vrev64q_u16): Likewise.
11520 (__arm_vrev64q_u32): Likewise.
11521 (__arm_vmvnq_n_u16): Likewise.
11522 (__arm_vmvnq_n_u32): Likewise.
11523 (__arm_vcvtq_s16_f16): Likewise.
11524 (__arm_vcvtq_s32_f32): Likewise.
11525 (__arm_vcvtq_u16_f16): Likewise.
11526 (__arm_vcvtq_u32_f32): Likewise.
11527 (vrev64q): Define polymorphic variant.
11528 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
11529 (UNOP_SNONE_NONE): Likewise.
11530 (UNOP_SNONE_IMM): Likewise.
11531 (UNOP_UNONE_UNONE): Likewise.
11532 (UNOP_UNONE_NONE): Likewise.
11533 (UNOP_UNONE_IMM): Likewise.
11534 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern.
11535 (mve_vcvtq_from_f_<supf><mode>): Likewise.
11536 (mve_vmvnq_n_<supf><mode>): Likewise.
11538 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11539 Mihail Ionescu <mihail.ionescu@arm.com>
11540 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11542 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
11543 (UNOP_NONE_SNONE_QUALIFIERS): Likewise.
11544 (UNOP_NONE_UNONE_QUALIFIERS): Likewise.
11545 * config/arm/arm_mve.h (vrndxq_f16): Define macro.
11546 (vrndxq_f32): Likewise.
11547 (vrndq_f16) Likewise.
11548 (vrndq_f32): Likewise.
11549 (vrndpq_f16): Likewise.
11550 (vrndpq_f32): Likewise.
11551 (vrndnq_f16): Likewise.
11552 (vrndnq_f32): Likewise.
11553 (vrndmq_f16): Likewise.
11554 (vrndmq_f32): Likewise.
11555 (vrndaq_f16): Likewise.
11556 (vrndaq_f32): Likewise.
11557 (vrev64q_f16): Likewise.
11558 (vrev64q_f32): Likewise.
11559 (vnegq_f16): Likewise.
11560 (vnegq_f32): Likewise.
11561 (vdupq_n_f16): Likewise.
11562 (vdupq_n_f32): Likewise.
11563 (vabsq_f16): Likewise.
11564 (vabsq_f32): Likewise.
11565 (vrev32q_f16): Likewise.
11566 (vcvttq_f32_f16): Likewise.
11567 (vcvtbq_f32_f16): Likewise.
11568 (vcvtq_f16_s16): Likewise.
11569 (vcvtq_f32_s32): Likewise.
11570 (vcvtq_f16_u16): Likewise.
11571 (vcvtq_f32_u32): Likewise.
11572 (__arm_vrndxq_f16): Define intrinsic.
11573 (__arm_vrndxq_f32): Likewise.
11574 (__arm_vrndq_f16): Likewise.
11575 (__arm_vrndq_f32): Likewise.
11576 (__arm_vrndpq_f16): Likewise.
11577 (__arm_vrndpq_f32): Likewise.
11578 (__arm_vrndnq_f16): Likewise.
11579 (__arm_vrndnq_f32): Likewise.
11580 (__arm_vrndmq_f16): Likewise.
11581 (__arm_vrndmq_f32): Likewise.
11582 (__arm_vrndaq_f16): Likewise.
11583 (__arm_vrndaq_f32): Likewise.
11584 (__arm_vrev64q_f16): Likewise.
11585 (__arm_vrev64q_f32): Likewise.
11586 (__arm_vnegq_f16): Likewise.
11587 (__arm_vnegq_f32): Likewise.
11588 (__arm_vdupq_n_f16): Likewise.
11589 (__arm_vdupq_n_f32): Likewise.
11590 (__arm_vabsq_f16): Likewise.
11591 (__arm_vabsq_f32): Likewise.
11592 (__arm_vrev32q_f16): Likewise.
11593 (__arm_vcvttq_f32_f16): Likewise.
11594 (__arm_vcvtbq_f32_f16): Likewise.
11595 (__arm_vcvtq_f16_s16): Likewise.
11596 (__arm_vcvtq_f32_s32): Likewise.
11597 (__arm_vcvtq_f16_u16): Likewise.
11598 (__arm_vcvtq_f32_u32): Likewise.
11599 (vrndxq): Define polymorphic variants.
11601 (vrndpq): Likewise.
11602 (vrndnq): Likewise.
11603 (vrndmq): Likewise.
11604 (vrndaq): Likewise.
11605 (vrev64q): Likewise.
11608 (vrev32q): Likewise.
11609 (vcvtbq_f32): Likewise.
11610 (vcvttq_f32): Likewise.
11612 * config/arm/arm_mve_builtins.def (VAR2): Define.
11614 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
11615 (mve_vrndq_f<mode>): Likewise.
11616 (mve_vrndpq_f<mode>): Likewise.
11617 (mve_vrndnq_f<mode>): Likewise.
11618 (mve_vrndmq_f<mode>): Likewise.
11619 (mve_vrndaq_f<mode>): Likewise.
11620 (mve_vrev64q_f<mode>): Likewise.
11621 (mve_vnegq_f<mode>): Likewise.
11622 (mve_vdupq_n_f<mode>): Likewise.
11623 (mve_vabsq_f<mode>): Likewise.
11624 (mve_vrev32q_fv8hf): Likewise.
11625 (mve_vcvttq_f32_f16v4sf): Likewise.
11626 (mve_vcvtbq_f32_f16v4sf): Likewise.
11627 (mve_vcvtq_to_f_<supf><mode>): Likewise.
11629 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11630 Mihail Ionescu <mihail.ionescu@arm.com>
11631 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11633 * config/arm/arm-builtins.c (CF): Define mve_builtin_data.
11635 (ARM_BUILTIN_MVE_PATTERN_START): Define.
11636 (arm_init_mve_builtins): Define function.
11637 (arm_init_builtins): Add TARGET_HAVE_MVE check.
11638 (arm_expand_builtin_1): Check the range of fcode.
11639 (arm_expand_mve_builtin): Define function to expand MVE builtins.
11640 (arm_expand_builtin): Check the range of fcode.
11641 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point
11643 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace.
11644 (vst4q_s8): Define macro.
11645 (vst4q_s16): Likewise.
11646 (vst4q_s32): Likewise.
11647 (vst4q_u8): Likewise.
11648 (vst4q_u16): Likewise.
11649 (vst4q_u32): Likewise.
11650 (vst4q_f16): Likewise.
11651 (vst4q_f32): Likewise.
11652 (__arm_vst4q_s8): Define inline builtin.
11653 (__arm_vst4q_s16): Likewise.
11654 (__arm_vst4q_s32): Likewise.
11655 (__arm_vst4q_u8): Likewise.
11656 (__arm_vst4q_u16): Likewise.
11657 (__arm_vst4q_u32): Likewise.
11658 (__arm_vst4q_f16): Likewise.
11659 (__arm_vst4q_f32): Likewise.
11660 (__ARM_mve_typeid): Define macro with MVE types.
11661 (__ARM_mve_coerce): Define macro with _Generic feature.
11662 (vst4q): Define polymorphic variant for different vst4q builtins.
11663 * config/arm/arm_mve_builtins.def: New file.
11664 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI
11666 * config/arm/mve.md (MVE_VLD_ST): Define iterator.
11667 (unspec): Define unspec.
11668 (mve_vst4q<mode>): Define RTL pattern.
11669 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI
11671 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes
11673 (define_split): Allow OI mode split for MVE after reload.
11674 (define_split): Allow XI mode split for MVE after reload.
11675 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def.
11676 (arm-builtins.o): Likewise.
11678 2020-03-17 Christophe Lyon <christophe.lyon@linaro.org>
11680 * c-typeck.c (process_init_element): Handle constructor_type with
11681 type size represented by POLY_INT_CST.
11683 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11685 PR tree-optimization/94187
11686 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if
11687 nchars - offset < nbytes.
11689 PR middle-end/94189
11690 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would
11691 emit a warning if it was enabled and don't depend on TREE_NO_WARNING
11692 for code-generation.
11694 2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
11697 * lra-spills.c (remove_pseudos): Do not reuse insn alternative
11698 after changing memory subreg.
11700 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11701 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11703 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
11704 emulator calls for dobule precision arithmetic operations for MVE.
11706 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11707 Mihail Ionescu <mihail.ionescu@arm.com>
11708 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11710 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
11711 feature bit is on and -mfpu=auto is passed as compiler option, do not
11712 generate error on not finding any matching fpu. Because in this case
11713 fpu is not required.
11714 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
11715 enabled for MVE and also for all VFP extensions.
11716 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
11718 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
11719 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
11720 along with feature bits mve_float.
11721 (mve): Modify add options in armv8.1-m.main arch for MVE.
11722 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with
11724 * config/arm/arm.c (use_return_insn): Replace the
11725 check with TARGET_VFP_BASE.
11726 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
11728 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
11729 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
11731 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
11732 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
11734 (arm_compute_frame_layout): Likewise.
11735 (arm_save_coproc_regs): Likewise.
11736 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
11738 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
11739 with equivalent macro TARGET_VFP_BASE.
11740 (arm_expand_epilogue_apcs_frame): Likewise.
11741 (arm_expand_epilogue): Likewise.
11742 (arm_conditional_register_usage): Likewise.
11743 (arm_declare_function_name): Add check to skip printing .fpu directive
11744 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
11746 * config/arm/arm.h (TARGET_VFP_BASE): Define.
11747 * config/arm/arm.md (arch): Add "mve" to arch.
11748 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
11749 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
11750 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
11751 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR
11753 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
11754 to not allow for MVE.
11755 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
11757 (VUNSPEC_GET_FPSCR): Define.
11758 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
11759 instructions which move to general-purpose Register from Floating-point
11760 Special register and vice-versa.
11761 (thumb2_movhi_fp16): Likewise.
11762 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
11763 with MCR and MRC instructions which set and get Floating-point Status
11764 and Control Register (FPSCR).
11765 (movdi_vfp): Modify pattern to enable Single-precision scalar float move
11767 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
11768 float move patterns in MVE.
11769 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
11770 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
11771 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
11772 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
11773 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
11774 TARGET_VFP_BASE check.
11775 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
11776 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
11778 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
11779 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
11783 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11784 Mihail Ionescu <mihail.ionescu@arm.com>
11785 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11787 * config.gcc (arm_mve.h): Include mve intrinsics header file.
11788 * config/arm/aout.h (p0): Add new register name for MVE predicated
11790 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
11791 common to Neon and MVE.
11792 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
11793 (arm_init_simd_builtin_types): Disable poly types for MVE.
11794 (arm_init_neon_builtins): Move a check to arm_init_builtins function.
11795 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
11796 ARM_BUILTIN_NEON_LANE_CHECK.
11797 (mve_dereference_pointer): Add function.
11798 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
11800 (arm_expand_neon_builtin): Moved to arm_expand_builtin function.
11801 (arm_expand_builtin): Moved from arm_expand_neon_builtin function.
11802 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
11803 with floating point enabled.
11804 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
11805 simd_immediate_valid_for_move.
11806 (simd_immediate_valid_for_move): Renamed from
11807 neon_immediate_valid_for_move function.
11808 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
11809 error if vfpv2 feature bit is disabled and mve feature bit is also
11810 disabled for HARD_FLOAT_ABI.
11811 (use_return_insn): Check to not push VFP regs for MVE.
11812 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
11814 (aapcs_vfp_allocate_return_reg): Likewise.
11815 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
11816 address operand for MVE.
11817 (arm_rtx_costs_internal): MVE check to determine cost of rtx.
11818 (neon_valid_immediate): Rename to simd_valid_immediate.
11819 (simd_valid_immediate): Rename from neon_valid_immediate.
11820 (simd_valid_immediate): MVE check on size of vector is 128 bits.
11821 (neon_immediate_valid_for_move): Rename to
11822 simd_immediate_valid_for_move.
11823 (simd_immediate_valid_for_move): Rename from
11824 neon_immediate_valid_for_move.
11825 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
11827 (neon_make_constant): Modify call to neon_valid_immediate function.
11828 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
11830 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
11831 (arm_compute_frame_layout): Calculate space for saved VFP registers for
11833 (arm_save_coproc_regs): Save coproc registers for MVE.
11834 (arm_print_operand): Add case 'E' to print memory operands for MVE.
11835 (arm_print_operand_address): Check to print register number for MVE.
11836 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
11837 (arm_modes_tieable_p): Check to allow structure mode for MVE.
11838 (arm_regno_class): Add VPR_REGNUM check.
11839 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
11841 (arm_expand_epilogue): MVE check for enabling pop instructions in
11843 (arm_print_asm_arch_directives): Modify function to disable print of
11844 .arch_extension "mve" and "fp" for cases where MVE is enabled with
11846 (arm_vector_mode_supported_p): Check for modes available in MVE interger
11847 and MVE floating point.
11848 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
11850 (arm_conditional_register_usage): Enable usage of conditional regsiter
11852 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
11853 (arm_declare_function_name): Modify function to disable print of
11854 .arch_extension "mve" and "fp" for cases where MVE is enabled with
11856 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
11857 when target general registers are required.
11858 (TARGET_HAVE_MVE_FLOAT): Likewise.
11859 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
11861 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
11862 which indicate this is not available for across function calls.
11863 (FIRST_PSEUDO_REGISTER): Modify.
11864 (VALID_MVE_MODE): Define valid MVE mode.
11865 (VALID_MVE_SI_MODE): Define valid MVE SI mode.
11866 (VALID_MVE_SF_MODE): Define valid MVE SF mode.
11867 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
11868 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
11870 (IS_VPR_REGNUM): Macro to check for VPR_REG register.
11871 (REG_ALLOC_ORDER): Add VPR_REGNUM entry.
11872 (enum reg_class): Add VPR_REG entry.
11873 (REG_CLASS_NAMES): Add VPR_REG entry.
11874 * config/arm/arm.md (VPR_REGNUM): Define.
11875 (conds): Check is_mve_type attrbiute to differentiate "conditional" and
11876 "unconditional" instructions.
11877 (arm_movsf_soft_insn): Modify RTL to not allow for MVE.
11878 (movdf_soft_insn): Modify RTL to not allow for MVE.
11879 (vfp_pop_multiple_with_writeback): Enable for MVE.
11880 (include "mve.md"): Include mve.md file.
11881 * config/arm/arm_mve.h: Add MVE intrinsics head file.
11882 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
11883 for vector predicated operands.
11884 * config/arm/iterators.md (VNIM1): Define.
11885 (VNINOTM1): Define.
11886 (VHFBF_split): Define
11887 * config/arm/mve.md: New file.
11888 (mve_mov<mode>): Define RTL for move, store and load in MVE.
11889 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
11891 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with
11892 simd_immediate_valid_for_move.
11893 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
11894 is common to MVE and NEON to vec-common.md file.
11895 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
11896 * config/arm/predicates.md (vpr_register_operand): Define.
11897 * config/arm/t-arm: Add mve.md file.
11898 * config/arm/types.md (mve_move): Add MVE instructions mve_move to
11900 (mve_store): Add MVE instructions mve_store to attribute "type".
11901 (mve_load): Add MVE instructions mve_load to attribute "type".
11902 (is_mve_type): Define attribute.
11903 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
11904 standard move patterns in MVE along with NEON and IWMMXT with mode
11906 (mov<mode>): Modify RTL expand to support standard move patterns in NEON
11907 and IWMMXT with mode iterator V8HF.
11908 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in
11910 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
11911 simd_immediate_valid_for_move.
11914 2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
11917 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
11918 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
11920 * config/i386/predicates.md (ext_sse_reg_operand): Removed.
11922 2020-03-16 Jakub Jelinek <jakub@redhat.com>
11925 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
11928 PR tree-optimization/94166
11929 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
11930 as secondary comparison key.
11932 2020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com>
11934 PR tree-optimization/94125
11935 * tree-loop-distribution.c
11936 (loop_distribution::break_alias_scc_partitions): Update post order
11937 number for merged scc.
11939 2020-03-15 H.J. Lu <hongjiu.lu@intel.com>
11942 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
11944 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
11945 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
11946 and ext_sse_reg_operand check.
11948 2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
11950 * common.opt: Avoid redundancy in the help text.
11951 * config/arc/arc.opt: Likewise.
11952 * config/cr16/cr16.opt: Likewise.
11954 2020-03-14 Jakub Jelinek <jakub@redhat.com>
11956 PR middle-end/93566
11957 * tree-nested.c (convert_nonlocal_omp_clauses,
11958 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
11959 with C/C++ array sections.
11961 2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
11964 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
11965 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
11968 2020-03-14 Jakub Jelinek <jakub@redhat.com>
11970 * gimple-fold.c (gimple_fold_builtin_strncpy): Change
11971 "a an" to "an" in a comment.
11972 * hsa-common.h (is_a_helper): Likewise.
11973 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
11974 * config/arc/arc.c (arc600_corereg_hazard): Likewise.
11975 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.
11977 2020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com>
11980 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a
11981 64-bit value by 64 bits (UB).
11983 2020-03-13 Vladimir Makarov <vmakarov@redhat.com>
11985 PR rtl-optimization/92303
11986 * lra-spills.c (remove_pseudos): Try to simplify memory subreg.
11988 2020-03-13 Segher Boessenkool <segher@kernel.crashing.org>
11990 PR rtl-optimization/94148
11991 PR rtl-optimization/94042
11992 * df-core.c (BB_LAST_CHANGE_AGE): Delete.
11993 (df_worklist_propagate_forward): New parameter last_change_age, use
11994 that instead of bb->aux.
11995 (df_worklist_propagate_backward): Ditto.
11996 (df_worklist_dataflow_doublequeue): Use a local array last_change_age.
11998 2020-03-13 Richard Biener <rguenther@suse.de>
12000 PR tree-optimization/94163
12001 * tree-ssa-pre.c (create_expression_by_pieces): Check
12002 whether alignment would be zero.
12004 2020-03-13 Martin Liska <mliska@suse.cz>
12007 * lto-wrapper.c (run_gcc): Use concat for appending
12008 to collect_gcc_options.
12010 2020-03-13 Jakub Jelinek <jakub@redhat.com>
12013 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
12014 instead of GEN_INT.
12016 2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
12019 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
12020 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
12021 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
12022 TARGET_AVX512VL and ext_sse_reg_operand check.
12024 2020-03-13 Bu Le <bule1@huawei.com>
12027 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=)
12028 (-param=aarch64-double-recp-precision=): New options.
12029 * doc/invoke.texi: Document them.
12030 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them
12031 instead of hard-coding the choice of 1 for float and 2 for double.
12033 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
12035 PR rtl-optimization/94119
12036 * resource.h (clear_hashed_info_until_next_barrier): Declare.
12037 * resource.c (clear_hashed_info_until_next_barrier): New function.
12038 * reorg.c (add_to_delay_list): Fix formatting.
12039 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on
12040 the next instruction after removing a BARRIER.
12042 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
12044 PR middle-end/92071
12045 * expmed.c (store_integral_bit_field): For fields larger than a word,
12046 call extract_bit_field on the value if the mode is BLKmode. Remove
12047 specific path for big-endian targets and tidy things up a little bit.
12049 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
12051 PR rtl-optimization/90275
12052 * cse.c (cse_insn): Delete no-op register moves too.
12054 2020-03-12 Darius Galis <darius.galis@cyberthorstudios.com>
12056 * config/rx/rx.md (CTRLREG_CPEN): Remove.
12057 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support.
12059 2020-03-12 Richard Biener <rguenther@suse.de>
12061 PR tree-optimization/94103
12062 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type
12063 punning when the mode precision is not sufficient.
12065 2020-03-12 H.J. Lu <hongjiu.lu@intel.com>
12068 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
12069 MODE_V1DF and MODE_V2SF.
12070 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
12071 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
12074 2020-03-12 Jakub Jelinek <jakub@redhat.com>
12076 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
12077 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
12078 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
12079 * doc/tm.texi: Regenerated.
12081 PR tree-optimization/94130
12082 * tree-ssa-dse.c: Include gimplify.h.
12083 (increment_start_addr): If stmt has lhs, drop the lhs from call and
12084 set it after the call to the original value of the first argument.
12086 (decrement_count): Formatting fix.
12088 2020-03-11 Delia Burduv <delia.burduv@arm.com>
12090 * config/arm/arm-builtins.c
12091 (arm_init_simd_builtin_scalar_types): New.
12092 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type.
12093 (vld2q_bf16): Used new builtin type.
12094 (vld3_bf16): Used new builtin type.
12095 (vld3q_bf16): Used new builtin type.
12096 (vld4_bf16): Used new builtin type.
12097 (vld4q_bf16): Used new builtin type.
12098 (vld2_dup_bf16): Used new builtin type.
12099 (vld2q_dup_bf16): Used new builtin type.
12100 (vld3_dup_bf16): Used new builtin type.
12101 (vld3q_dup_bf16): Used new builtin type.
12102 (vld4_dup_bf16): Used new builtin type.
12103 (vld4q_dup_bf16): Used new builtin type.
12105 2020-03-11 Jakub Jelinek <jakub@redhat.com>
12108 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
12109 at the start to switch to data section. Don't print extra newline if
12110 .globl directive has not been emitted.
12112 2020-03-11 Richard Biener <rguenther@suse.de>
12114 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]):
12117 2020-03-11 Eric Botcazou <ebotcazou@adacore.com>
12119 PR middle-end/93961
12120 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields
12121 whose type is a qualified union.
12123 2020-03-11 Jakub Jelinek <jakub@redhat.com>
12126 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
12127 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
12130 * value-prof.c (dump_histogram_value): Use abs_hwi instead of
12132 (get_nth_most_common_value): Use abs_hwi instead of abs.
12134 PR middle-end/94111
12135 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
12136 is rvc_normal, otherwise use real_to_decimal to print the number to
12139 PR tree-optimization/94114
12140 * tree-loop-distribution.c (generate_memset_builtin): Call
12141 rewrite_to_non_trapping_overflow even on mem.
12142 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
12145 2020-03-10 Jeff Law <law@redhat.com>
12147 * config/bfin/bfin.md (movsi_insv): Add length attribute.
12149 2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
12152 * config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check
12153 NAN and SIGNED_ZEROR for smax/smin.
12155 2020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
12158 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
12159 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments.
12161 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
12163 * loop-iv.c (find_simple_exit): Make it static.
12164 * cfgloop.h: Remove the corresponding prototype.
12166 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
12168 * ddg.c (create_ddg): Fix intendation.
12169 (set_recurrence_length): Likewise.
12170 (create_ddg_all_sccs): Likewise.
12172 2020-03-10 Jakub Jelinek <jakub@redhat.com>
12175 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with
12176 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len
12179 2020-03-09 Jason Merrill <jason@redhat.com>
12181 * gdbinit.in (pgs): Fix typo in documentation.
12183 2020-03-09 Vladimir Makarov <vmakarov@redhat.com>
12187 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
12189 PR rtl-optimization/93564
12190 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
12191 do not honor reg alloc order.
12193 2020-03-09 Andrew Pinski <apinski@marvell.com>
12195 PR inline-asm/94095
12196 * doc/extend.texi (x86 Operand Modifiers): Fix column
12199 2020-03-09 Martin Liska <mliska@suse.cz>
12202 * config/rs6000/rs6000.c (rs6000_option_override_internal):
12203 Remove set of str_align_loops and str_align_jumps as these
12204 should be set in previous 2 conditions in the function.
12206 2020-03-09 Jakub Jelinek <jakub@redhat.com>
12208 PR rtl-optimization/94045
12209 * params.opt (-param=max-find-base-term-values=): New option.
12210 * alias.c (find_base_term): Add cut-off for number of visited VALUEs
12211 in a single toplevel find_base_term call.
12213 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
12216 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define.
12217 * config/aarch64/aarch64-simd.md
12218 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul.
12219 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise.
12220 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics.
12221 * config/aarch64/arm_neon.h:
12222 (vmlal_lane_s16): Expand using intrinsics rather than inline asm.
12223 (vmlal_lane_u16): Likewise.
12224 (vmlal_lane_s32): Likewise.
12225 (vmlal_lane_u32): Likewise.
12226 (vmlal_laneq_s16): Likewise.
12227 (vmlal_laneq_u16): Likewise.
12228 (vmlal_laneq_s32): Likewise.
12229 (vmlal_laneq_u32): Likewise.
12230 (vmull_lane_s16): Likewise.
12231 (vmull_lane_u16): Likewise.
12232 (vmull_lane_s32): Likewise.
12233 (vmull_lane_u32): Likewise.
12234 (vmull_laneq_s16): Likewise.
12235 (vmull_laneq_u16): Likewise.
12236 (vmull_laneq_s32): Likewise.
12237 (vmull_laneq_u32): Likewise.
12238 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul.
12241 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
12243 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
12244 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
12245 (aarch64_mls_elt<mode>): Likewise.
12246 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
12247 (aarch64_fma4_elt<mode>): Likewise.
12248 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
12249 (aarch64_fma4_elt_to_64v2df): Likewise.
12250 (aarch64_fnma4_elt<mode>): Likewise.
12251 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
12252 (aarch64_fnma4_elt_to_64v2df): Likewise.
12254 2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
12256 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
12257 Specify movprfx attribute.
12258 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
12260 2020-03-06 David Edelsohn <dje.gcc@gmail.com>
12263 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for
12265 (TARGET_NO_FP_IN_TOC): Same.
12266 * config/rs6000/aix71.h: Same.
12267 * config/rs6000/aix72.h: Same.
12269 2020-03-06 Andrew Pinski <apinski@marvell.com>
12270 Jeff Law <law@redhat.com>
12272 PR rtl-optimization/93996
12273 * haifa-sched.c (remove_notes): Be more careful when adding
12276 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12278 * config/arm/arm_neon.h (vld2_bf16): New.
12284 (vld2_dup_bf16): New.
12285 (vld2q_dup_bf16): New.
12286 (vld3_dup_bf16): New.
12287 (vld3q_dup_bf16): New.
12288 (vld4_dup_bf16): New.
12289 (vld4q_dup_bf16): New.
12290 * config/arm/arm_neon_builtins.def
12291 (vld2): Changed to VAR13 and added v4bf, v8bf
12292 (vld2_dup): Changed to VAR8 and added v4bf, v8bf
12293 (vld3): Changed to VAR13 and added v4bf, v8bf
12294 (vld3_dup): Changed to VAR8 and added v4bf, v8bf
12295 (vld4): Changed to VAR13 and added v4bf, v8bf
12296 (vld4_dup): Changed to VAR8 and added v4bf, v8bf
12297 * config/arm/iterators.md (VDXBF2): New iterator.
12298 *config/arm/neon.md (neon_vld2): Use new iterators.
12299 (neon_vld2_dup<mode): Use new iterators.
12300 (neon_vld3<mode>): Likewise.
12301 (neon_vld3qa<mode>): Likewise.
12302 (neon_vld3qb<mode>): Likewise.
12303 (neon_vld3_dup<mode>): Likewise.
12304 (neon_vld4<mode>): Likewise.
12305 (neon_vld4qa<mode>): Likewise.
12306 (neon_vld4qb<mode>): Likewise.
12307 (neon_vld4_dup<mode>): Likewise.
12308 (neon_vld2_dupv8bf): New.
12309 (neon_vld3_dupv8bf): Likewise.
12310 (neon_vld4_dupv8bf): Likewise.
12312 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12314 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef.
12315 (bfloat16x8x2_t): New typedef.
12316 (bfloat16x4x3_t): New typedef.
12317 (bfloat16x8x3_t): New typedef.
12318 (bfloat16x4x4_t): New typedef.
12319 (bfloat16x8x4_t): New typedef.
12326 * config/arm/arm-builtins.c (v2bf_UP): Define.
12328 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype.
12329 * config/arm/arm-modes.def (V2BF): New mode.
12330 * config/arm/arm-simd-builtin-types.def
12331 (Bfloat16x2_t): New entry.
12332 * config/arm/arm_neon_builtins.def
12333 (vst2): Changed to VAR13 and added v4bf, v8bf
12334 (vst3): Changed to VAR13 and added v4bf, v8bf
12335 (vst4): Changed to VAR13 and added v4bf, v8bf
12336 * config/arm/iterators.md (VDXBF): New iterator.
12337 (VQ2BF): New iterator.
12338 *config/arm/neon.md (neon_vst2<mode>): Used new iterators.
12339 (neon_vst2<mode>): Used new iterators.
12340 (neon_vst3<mode>): Used new iterators.
12341 (neon_vst3<mode>): Used new iterators.
12342 (neon_vst3qa<mode>): Used new iterators.
12343 (neon_vst3qb<mode>): Used new iterators.
12344 (neon_vst4<mode>): Used new iterators.
12345 (neon_vst4<mode>): Used new iterators.
12346 (neon_vst4qa<mode>): Used new iterators.
12347 (neon_vst4qb<mode>): Used new iterators.
12349 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12351 * config/aarch64/aarch64-simd-builtins.def
12352 (bfcvtn): New built-in function.
12353 (bfcvtn_q): New built-in function.
12354 (bfcvtn2): New built-in function.
12355 (bfcvt): New built-in function.
12356 * config/aarch64/aarch64-simd.md
12357 (aarch64_bfcvtn<q><mode>): New pattern.
12358 (aarch64_bfcvtn2v8bf): New pattern.
12359 (aarch64_bfcvtbf): New pattern.
12360 * config/aarch64/arm_bf16.h (float32_t): New typedef.
12361 (vcvth_bf16_f32): New intrinsic.
12362 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic.
12363 (vcvtq_low_bf16_f32): New intrinsic.
12364 (vcvtq_high_bf16_f32): New intrinsic.
12365 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator.
12366 (UNSPEC_BFCVTN): New UNSPEC.
12367 (UNSPEC_BFCVTN2): New UNSPEC.
12368 (UNSPEC_BFCVT): New UNSPEC.
12369 * config/arm/types.md (bf_cvt): New type.
12371 2020-03-06 Andreas Krebbel <krebbel@linux.ibm.com>
12373 * config/s390/s390.md ("tabort"): Get rid of two consecutive
12374 blanks in format string.
12376 2020-03-05 H.J. Lu <hongjiu.lu@intel.com>
12380 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype.
12381 * config/i386/i386.c (ix86_get_ssemov): New function.
12382 (ix86_output_ssemov): Likewise.
12383 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call
12384 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL
12386 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV.
12387 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV.
12388 Remove ext_sse_reg_operand and TARGET_AVX512VL check.
12389 (*movti_internal): Likewise.
12390 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV.
12392 2020-03-05 Jeff Law <law@redhat.com>
12394 PR tree-optimization/91890
12395 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument.
12396 Use gimple_or_expr_nonartificial_location.
12397 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds.
12398 Use gimple_or_expr_nonartificial_location.
12399 * gimple.c (gimple_or_expr_nonartificial_location): New function.
12400 * gimple.h (gimple_or_expr_nonartificial_location): Declare it.
12401 * tree-ssa-strlen.c (maybe_warn_overflow): Use
12402 gimple_or_expr_nonartificial_location.
12403 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise.
12404 (maybe_warn_pointless_strcmp): Likewise.
12406 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12409 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
12410 SRC and MASK arguments to __m128 from __m128d.
12411 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
12413 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
12415 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
12416 argument to __m128i from __m128d.
12417 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from
12419 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
12420 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from
12423 2020-03-05 Delia Burduv <delia.burduv@arm.com>
12425 * config/arm/arm_neon.h (vbfmmlaq_f32): New.
12426 (vbfmlalbq_f32): New.
12427 (vbfmlaltq_f32): New.
12428 (vbfmlalbq_lane_f32): New.
12429 (vbfmlaltq_lane_f32): New.
12430 (vbfmlalbq_laneq_f32): New.
12431 (vbfmlaltq_laneq_f32): New.
12432 * config/arm/arm_neon_builtins.def (vmmla): New.
12437 (vfmab_laneq): New.
12438 (vfmat_laneq): New.
12439 * config/arm/iterators.md (BF_MA): New int iterator.
12440 (bt): New int attribute.
12441 (VQXBF): Copy of VQX with V8BF.
12442 * config/arm/neon.md (neon_vmmlav8bf): New insn.
12443 (neon_vfma<bt>v8bf): New insn.
12444 (neon_vfma<bt>_lanev8bf): New insn.
12445 (neon_vfma<bt>_laneqv8bf): New expand.
12446 (neon_vget_high<mode>): Changed iterator to VQXBF.
12447 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC.
12448 (UNSPEC_BFMAB): New UNSPEC.
12449 (UNSPEC_BFMAT): New UNSPEC.
12451 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12453 PR middle-end/93399
12454 * tree-pretty-print.h (pretty_print_string): Declare.
12455 * tree-pretty-print.c (pretty_print_string): Remove forward
12456 declaration, no longer static. Change nbytes parameter type
12457 from unsigned to size_t.
12458 * print-rtl.c (print_value) <case CONST_STRING>: Use
12459 pretty_print_string and for shrink way too long strings.
12461 2020-03-05 Richard Biener <rguenther@suse.de>
12462 Jakub Jelinek <jakub@redhat.com>
12464 PR tree-optimization/93582
12465 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR
12466 last operand as signed when looking for memset offset. Formatting
12469 2020-03-04 Andrew Pinski <apinski@marvell.com>
12472 * value-prof.c (dump_histogram_value): Use std::abs.
12474 2020-03-04 Martin Sebor <msebor@redhat.com>
12476 PR tree-optimization/93986
12477 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int
12478 operands to the same precision widest_int to avoid ICEs.
12480 2020-03-04 Bill Schmidt <wschmidt@linux.ibm.com>
12483 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define.
12484 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry
12485 for OPTION_MASK_ALTIVEC.
12487 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12489 * config.gcc: Include the glibc-stdint.h header for zTPF.
12491 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12493 * config/s390/s390.c (s390_secondary_memory_needed): Disallow
12494 direct FPR-GPR copies.
12495 (s390_register_info_gprtofpr): Disallow GPR content to be saved in
12498 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12500 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new
12501 operands to the prologue_tpf expander.
12502 (s390_emit_epilogue): Likewise.
12503 (s390_option_override_internal): Do error checking and setup for
12505 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK)
12506 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET)
12507 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET)
12508 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions.
12509 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new
12510 operands for the check flag and the branch target.
12511 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check")
12512 ("mtpf-trace-hook-prologue-target")
12513 ("mtpf-trace-hook-epilogue-check")
12514 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New
12516 * doc/invoke.texi: Document -mtpf-trace-skip option. The other
12517 options are for debugging purposes and will not be documented
12520 2020-03-04 Jakub Jelinek <jakub@redhat.com>
12523 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
12525 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti
12526 argument. Change pd argument so that it can be modified. Turn
12527 constant non-CONSTRUCTOR store into non-constant if it is too large.
12528 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid
12530 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust
12533 2020-02-04 Richard Biener <rguenther@suse.de>
12535 PR tree-optimization/93964
12536 * graphite-isl-ast-to-gimple.c
12537 (gcc_expression_from_isl_ast_expr_id): Add intermediate
12538 conversion for pointer to integer converts.
12539 * graphite-scop-detection.c (assign_parameter_index_in_region):
12542 2020-03-04 Martin Liska <mliska@suse.cz>
12546 * doc/invoke.texi: Clarify --help=language and --help=common
12549 2020-03-04 Jakub Jelinek <jakub@redhat.com>
12551 PR tree-optimization/94001
12552 * tree-tailcall.c (process_assignment): Before comparing op1 to
12553 *ass_var, verify *ass_var is non-NULL.
12555 2020-03-04 Kito Cheng <kito.cheng@sifive.com>
12558 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
12561 2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
12563 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
12564 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
12565 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
12566 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
12567 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
12568 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
12569 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
12570 (V_bf_low, V_bf_cvt_m): New mode attributes.
12571 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
12572 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
12573 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
12574 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
12575 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
12577 2020-03-03 Jakub Jelinek <jakub@redhat.com>
12579 PR tree-optimization/93582
12580 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument.
12581 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result
12582 members, initialize them in the constructor and if mask is non-NULL,
12583 artificially push_partial_def {} for the portions of the mask that
12585 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to
12586 val and return (void *)-1. Formatting fix.
12587 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization.
12589 (vn_reference_lookup): Add mask argument. If non-NULL, don't call
12590 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return
12592 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST
12594 (visit_stmt): Formatting fix.
12596 2020-03-03 Richard Biener <rguenther@suse.de>
12598 PR tree-optimization/93946
12599 * alias.h (refs_same_for_tbaa_p): Declare.
12600 * alias.c (refs_same_for_tbaa_p): New function.
12601 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return
12603 * tree-ssa-scopedtables.h
12604 (avail_exprs_stack::lookup_avail_expr): Add output argument
12605 giving access to the hashtable entry.
12606 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
12608 * tree-ssa-dom.c: Include alias.h.
12609 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before
12610 removing redundant store.
12611 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member.
12612 (ao_ref_init_from_vn_reference): Adjust prototype.
12613 (vn_reference_lookup_pieces): Likewise.
12614 (vn_reference_insert_pieces): Likewise.
12615 * tree-ssa-sccvn.c: Track base alias set in addition to alias
12617 (eliminate_dom_walker::eliminate_stmt): Also check base alias
12618 set when removing redundant stores.
12619 (visit_reference_op_store): Likewise.
12620 * dse.c (record_store): Adjust valdity check for redundant
12623 2020-03-03 Jakub Jelinek <jakub@redhat.com>
12626 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder.
12628 PR rtl-optimization/94002
12629 * explow.c (plus_constant): Punt if cst has VOIDmode and
12630 get_pool_mode is different from mode.
12632 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12634 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an
12635 address has an offset which fits the scalling constraint for a
12636 load/store operation.
12637 (legitimate_scaled_address_p): Update use
12638 leigitimate_small_data_address_p.
12639 (arc_print_operand): Likewise.
12640 (arc_legitimate_address_p): Likewise.
12641 (legitimate_small_data_address_p): Likewise.
12643 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12645 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate.
12646 (fnmasf4_fpu): Likewise.
12648 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12650 * config/arc/arc.md (adddi3): Early expand the 64bit operation into
12652 (subdi3): Likewise.
12653 (adddi3_i): Remove pattern.
12654 (subdi3_i): Likewise.
12656 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12658 * config/arc/arc.md (eh_return): Add length info.
12660 2020-03-02 David Malcolm <dmalcolm@redhat.com>
12662 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New.
12664 2020-03-02 David Malcolm <dmalcolm@redhat.com>
12666 * doc/invoke.texi (Static Analyzer Options): Add
12667 -Wanalyzer-stale-setjmp-buffer to the list of options enabled
12670 2020-03-02 Uroš Bizjak <ubizjak@gmail.com>
12673 * config/i386/i386.md (movstrict<mode>): Allow only
12674 registers with VALID_INT_MODE_P modes.
12676 2020-03-02 Andrew Stubbs <ams@codesourcery.com>
12678 * config/gcn/gcn-valu.md (dpp_move<mode>): New.
12679 (reduc_insn): Use 'U' and 'B' operand codes.
12680 (reduc_<reduc_op>_scal_<mode>): Allow all types.
12681 (reduc_<reduc_op>_scal_v64di): Delete.
12682 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types.
12683 (*plus_carry_dpp_shr_v64si): Change to ...
12684 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types.
12685 (mov_from_lane63_v64di): Change to ...
12686 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes.
12687 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size.
12688 Support UNSPEC_MOV_DPP_SHR output formats.
12689 (gcn_expand_reduc_scalar): Add "use_moves" reductions.
12690 Add "use_extends" reductions.
12691 (print_operand_address): Add 'I' and 'U' codes.
12692 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
12694 2020-03-02 Martin Liska <mliska@suse.cz>
12696 * lto-wrapper.c: Fix typo in comment about
12697 C++ standard version.
12699 2020-03-01 Martin Sebor <msebor@redhat.com>
12702 * calls.c (init_attr_rdwr_indices): Correctly handle attribute.
12704 2020-03-01 Martin Sebor <msebor@redhat.com>
12706 PR middle-end/93829
12707 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that
12708 of a pointer in the outermost ADDR_EXPRs.
12710 2020-02-28 Jeff Law <law@redhat.com>
12712 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19.
12713 * config/v850/v850.c (v850_asm_trampoline_template): Update
12716 2020-02-28 Michael Meissner <meissner@linux.ibm.com>
12719 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var):
12722 2020-02-28 Martin Liska <mliska@suse.cz>
12725 * configure.ac: Improve detection of ld_date by requiring
12726 either two dashes or none.
12727 * configure: Regenerate.
12729 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
12731 PR rtl-optimization/93564
12732 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
12733 do not honor reg alloc order.
12735 2020-02-27 Joel Hutton <Joel.Hutton@arm.com>
12738 * config/aarch64/aarch64.c (aarch64_override_options): Fix
12739 misleading warning string.
12741 2020-02-27 Martin Sebor <msebor@redhat.com>
12743 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo.
12745 2020-02-27 Michael Meissner <meissner@linux.ibm.com>
12748 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
12749 Split the insn into two parts. This insn only does variable
12750 extract from a register.
12751 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
12752 variable extract from memory.
12753 (vsx_extract_v4sf_var): Split the insn into two parts. This insn
12754 only does variable extract from a register.
12755 (vsx_extract_v4sf_var_load): New insn, do variable extract from
12757 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
12758 into two parts. This insn only does variable extract from a
12760 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
12761 do variable extract from memory.
12763 2020-02-27 Martin Jambor <mjambor@suse.cz>
12764 Feng Xue <fxue@os.amperecomputing.com>
12767 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with
12768 new function calls_same_node_or_its_all_contexts_clone_p.
12769 (cgraph_edge_brings_value_p): Use it.
12770 (cgraph_edge_brings_value_p): Likewise.
12771 (self_recursive_pass_through_p): Return false if caller is a clone.
12772 (self_recursive_agg_pass_through_p): Likewise.
12774 2020-02-27 Jan Hubicka <hubicka@ucw.cz>
12776 PR middle-end/92152
12777 * alias.c (ends_tbaa_access_path_p): Break out from ...
12778 (component_uses_parent_alias_set_from): ... here.
12779 * alias.h (ends_tbaa_access_path_p): Declare.
12780 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...;
12781 handle trailing arrays past end of tbaa access path.
12782 (aliasing_component_refs_p): ... here; likewise.
12783 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access
12784 path; disambiguate also past end of it.
12785 (nonoverlapping_component_refs_p): Use only TBAA segment of the access
12788 2020-02-27 Mihail Ionescu <mihail.ionescu@arm.com>
12790 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the
12791 beginning of the file.
12792 (vcreate_bf16, vcombine_bf16): New.
12793 (vdup_n_bf16, vdupq_n_bf16): New.
12794 (vdup_lane_bf16, vdup_laneq_bf16): New.
12795 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
12796 (vduph_lane_bf16, vduph_laneq_bf16): New.
12797 (vset_lane_bf16, vsetq_lane_bf16): New.
12798 (vget_lane_bf16, vgetq_lane_bf16): New.
12799 (vget_high_bf16, vget_low_bf16): New.
12800 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
12801 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
12802 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
12803 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
12804 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
12805 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
12806 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
12807 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
12808 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
12809 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
12810 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New.
12811 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
12812 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
12813 (vreinterpretq_bf16_p128): New.
12814 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
12815 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
12816 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
12817 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
12818 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
12819 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
12820 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
12821 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
12822 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
12823 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
12824 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
12825 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
12826 (vreinterpretq_p128_bf16): New.
12827 * config/arm/arm_neon_builtins.def (VDX): Add V4BF.
12828 (V_elem): Likewise.
12829 (V_elem_l): Likewise.
12830 (VD_LANE): Likewise.
12832 (V_DOUBLE): Likewise.
12833 (VDQX): Add V4BF and V8BF.
12834 (V_two_elem, V_three_elem, V_four_elem): Likewise.
12836 (V_HALF): Likewise.
12837 (V_double_vector_mode): Likewise.
12838 (V_cmp_result): Likewise.
12839 (V_uf_sclr): Likewise.
12840 (V_sz_elem): Likewise.
12841 (Is_d_reg): Likewise.
12842 (V_mode_nunits): Likewise.
12843 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16.
12845 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
12847 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator.
12848 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE.
12849 (<expander><mode>3<exec>): Likewise.
12850 (<expander><mode>3): New.
12851 (v<expander><mode>3): New.
12852 (<expander><mode>3): New.
12853 (<expander><mode>3<exec>): Rename to ...
12854 (<expander>v64si3<exec>): ... this, and change modes to V64SI.
12855 * config/gcn/gcn.md (mnemonic): Use '%B' for not.
12857 2020-02-27 Alexandre Oliva <oliva@adacore.com>
12859 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave
12862 2020-02-27 Richard Biener <rguenther@suse.de>
12864 PR tree-optimization/93508
12865 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like
12866 non-_CHK variants. Valueize their length arguments.
12868 2020-02-27 Richard Biener <rguenther@suse.de>
12870 PR tree-optimization/93953
12871 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference
12872 to the hash-map entry.
12874 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
12876 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
12878 2020-02-27 Mark Williams <mwilliams@fb.com>
12880 * dwarf2out.c (file_name_acquire): Call remap_debug_filename.
12881 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map,
12882 -ffile-prefix-map and -fmacro-prefix-map.
12883 * lto-streamer-out.c: Include file-prefix-map.h.
12884 (lto_output_location): Remap the file part of locations.
12886 2020-02-27 Jakub Jelinek <jakub@redhat.com>
12889 * gimplify.c (gimplify_init_constructor): Don't promote readonly
12890 DECL_REGISTER variables to TREE_STATIC.
12892 PR tree-optimization/93582
12893 PR tree-optimization/93945
12894 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with
12895 non-zero INTEGER_CST second argument and ref->offset or ref->size
12896 not a multiple of BITS_PER_UNIT.
12898 2020-02-27 Jonathan Wakely <jwakely@redhat.com>
12900 * doc/install.texi (Binaries): Update description of BullFreeware.
12902 2020-02-26 Sandra Loosemore <sandra@codesourcery.com>
12906 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in
12907 C++ Language Options, Warning Options, and Static Analyzer
12908 Options lists. Document negative form of options enabled by
12909 default. Move some things around to more accurately sort
12910 warnings by category.
12911 (C++ Dialect Options, Warning Options, Static Analyzer
12912 Options): Document negative form of options when enabled by
12913 default. Move some things around to more accurately sort
12914 warnings by category. Add some missing index entries.
12915 Light copy-editing.
12917 2020-02-26 Carl Love <cel@us.ibm.com>
12920 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on
12921 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only
12922 for the vector unsigned short arguments. It is also listed as the
12923 name of the built-in for arguments vector unsigned short,
12924 vector unsigned int and vector unsigned long long built-ins. The
12925 name of the builtins for these arguments should be:
12926 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and
12927 __builtin_crypto_vpmsumd respectively.
12929 2020-02-26 Richard Biener <rguenther@suse.de>
12931 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count
12932 and load permutation.
12934 2020-02-26 Richard Sandiford <richard.sandiford@arm.com>
12936 PR middle-end/93843
12937 * optabs-tree.c (supportable_convert_operation): Reject types with
12940 2020-02-26 David Malcolm <dmalcolm@redhat.com>
12942 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o.
12944 2020-02-26 Jakub Jelinek <jakub@redhat.com>
12946 PR tree-optimization/93820
12947 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE
12948 argument to ALL_INTEGER_CST_P boolean.
12949 (imm_store_chain_info::try_coalesce_bswap): Adjust caller.
12950 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle
12951 adjacent INTEGER_CST store into merged_store->only_constants like
12954 2020-02-25 Jakub Jelinek <jakub@redhat.com>
12957 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity
12959 * cfghooks.c (verify_flow_info): Likewise.
12960 * predict.c (combine_predictions_for_bb): Likewise.
12961 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo,
12962 sucessor -> successor.
12963 (find_traces_1_round): Fix comment typo, destinarion -> destination.
12964 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors ->
12966 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump
12967 message typo, sucessors -> successors.
12969 2020-02-25 Martin Sebor <msebor@redhat.com>
12971 * doc/extend.texi (attribute access): Correct an example.
12973 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
12975 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
12977 (aarch64_init_simd_builtin_scalar_types): Register simd_bf.
12978 (VAR15, VAR16): New.
12979 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
12980 (VD): Enable for V4BF.
12982 (VQ): Enable for V8BF.
12984 (VQ_NO2E): Likewise.
12985 (VDBL, Vdbl): Add V4BF.
12986 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
12987 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
12988 (bfloat16x8x2_t): Likewise.
12989 (bfloat16x4x3_t): Likewise.
12990 (bfloat16x8x3_t): Likewise.
12991 (bfloat16x4x4_t): Likewise.
12992 (bfloat16x8x4_t): Likewise.
12993 (vcombine_bf16): New.
12994 (vld1_bf16, vld1_bf16_x2): New.
12995 (vld1_bf16_x3, vld1_bf16_x4): New.
12996 (vld1q_bf16, vld1q_bf16_x2): New.
12997 (vld1q_bf16_x3, vld1q_bf16_x4): New.
12998 (vld1_lane_bf16): New.
12999 (vld1q_lane_bf16): New.
13000 (vld1_dup_bf16): New.
13001 (vld1q_dup_bf16): New.
13004 (vld2_dup_bf16): New.
13005 (vld2q_dup_bf16): New.
13008 (vld3_dup_bf16): New.
13009 (vld3q_dup_bf16): New.
13012 (vld4_dup_bf16): New.
13013 (vld4q_dup_bf16): New.
13014 (vst1_bf16, vst1_bf16_x2): New.
13015 (vst1_bf16_x3, vst1_bf16_x4): New.
13016 (vst1q_bf16, vst1q_bf16_x2): New.
13017 (vst1q_bf16_x3, vst1q_bf16_x4): New.
13018 (vst1_lane_bf16): New.
13019 (vst1q_lane_bf16): New.
13027 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
13029 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
13030 (VALL_F16): Likewise.
13031 (VALLDI_F16): Likewise.
13033 (Vetype): Likewise.
13034 (vswap_width_name): Likewise.
13035 (VSWAP_WIDTH): Likewise.
13039 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New.
13040 (vget_lane_bf16, vgetq_lane_bf16): New.
13041 (vcreate_bf16): New.
13042 (vdup_n_bf16, vdupq_n_bf16): New.
13043 (vdup_lane_bf16, vdup_laneq_bf16): New.
13044 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
13045 (vduph_lane_bf16, vduph_laneq_bf16): New.
13046 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
13047 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
13048 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
13049 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
13050 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
13051 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
13052 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
13053 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
13054 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
13055 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
13056 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New
13057 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New
13058 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
13059 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
13060 (vreinterpretq_bf16_p128): New.
13061 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
13062 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
13063 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
13064 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
13065 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
13066 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
13067 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
13068 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
13069 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
13070 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
13071 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
13072 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
13073 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New.
13074 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New.
13075 (vreinterpretq_p128_bf16): New.
13077 2020-02-25 Dennis Zhang <dennis.zhang@arm.com>
13079 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New
13080 (vbfdot_lane_f32, vbfdotq_laneq_f32): New.
13081 (vbfdot_laneq_f32, vbfdotq_lane_f32): New.
13082 * config/arm/arm_neon_builtins.def (vbfdot): New entry.
13083 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise.
13084 * config/arm/iterators.md (VSF2BF): New attribute.
13085 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry.
13086 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise.
13087 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise.
13089 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org>
13091 * config/arm/arm.md (required_for_purecode): New attribute.
13092 (enabled): Handle required_for_purecode.
13093 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to
13094 work with -mpure-code.
13096 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13098 PR rtl-optimization/93908
13099 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src
13102 2019-02-25 Eric Botcazou <ebotcazou@adacore.com>
13104 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode.
13106 2020-02-25 Roman Zhuykov <zhroma@ispras.ru>
13108 * doc/install.texi (--enable-checking): Adjust wording.
13110 2020-02-25 Richard Biener <rguenther@suse.de>
13112 PR tree-optimization/93868
13113 * tree-vect-slp.c (slp_copy_subtree): New function.
13114 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before
13115 re-arranging stmts in it.
13117 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13119 PR middle-end/93874
13120 * passes.c (pass_manager::dump_passes): Create a cgraph node for the
13121 dummy function and remove it at the end.
13123 PR translation/93864
13124 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo
13125 paramter -> parameter.
13126 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise.
13127 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise.
13129 2020-02-24 Roman Zhuykov <zhroma@ispras.ru>
13131 * doc/install.texi (--enable-checking): Properly document current
13133 (--enable-stage1-checking): Minor clarification about bootstrap.
13135 2020-02-24 David Malcolm <dmalcolm@redhat.com>
13138 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that
13139 -fanalyzer-checker=taint is also required.
13140 (-fanalyzer-checker=): Note that providing this option enables the
13141 given checker, and doing so may be required for checkers that are
13142 disabled by default.
13144 2020-02-24 David Malcolm <dmalcolm@redhat.com>
13146 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows
13147 significant control flow events; add a "3" which shows all
13148 control flow events; the old "3" becomes "4".
13150 2020-02-24 Jakub Jelinek <jakub@redhat.com>
13152 PR tree-optimization/93582
13153 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider
13154 pd.offset and pd.size to be counted in bits rather than bytes, add
13155 support for maxsizei that is not a multiple of BITS_PER_UNIT and
13156 handle bitfield stores and loads.
13157 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with
13158 uncomparable quantities - bytes vs. bits. Allow push_partial_def
13159 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust
13160 pd.offset/pd.size to be counted in bits rather than bytes.
13161 Formatting fix. Rename shadowed len variable to buflen.
13163 2020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
13164 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org>
13167 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function.
13168 (driver::main): Call putenv_COLLECT_AS_OPTIONS.
13169 * opts-common.c (parse_options_from_collect_gcc_options): New function.
13170 (prepend_xassembler_to_collect_as_options): Likewise.
13171 * opts.h (parse_options_from_collect_gcc_options): Declare prototype.
13172 (prepend_xassembler_to_collect_as_options): Likewise.
13173 * lto-opts.c (lto_write_options): Stream assembler options
13174 in COLLECT_AS_OPTIONS.
13175 * lto-wrapper.c (xassembler_options_error): New static variable.
13176 (get_options_from_collect_gcc_options): Move parsing options code to
13177 parse_options_from_collect_gcc_options and call it.
13178 (merge_and_complain): Validate -Xassembler options.
13179 (append_compiler_options): Handle OPT_Xassembler.
13180 (run_gcc): Append command line -Xassembler options to
13181 collect_gcc_options.
13182 * doc/invoke.texi: Add documentation about using Xassembler
13185 2020-02-24 Kito Cheng <kito.cheng@sifive.com>
13187 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen
13189 (riscv_rtx_costs): Update cost model for LTGT.
13191 2020-02-23 Vladimir Makarov <vmakarov@redhat.com>
13193 PR rtl-optimization/93564
13194 * ira-color.c (struct update_cost_queue_elem): New member start.
13195 (queue_update_cost, get_next_update_cost): Add new arg start.
13196 (allocnos_conflict_p): New function.
13197 (update_costs_from_allocno): Add new arg conflict_cost_update_p.
13198 Add checking conflicts with allocnos_conflict_p.
13199 (update_costs_from_prefs, restore_costs_from_copies): Adjust
13200 update_costs_from_allocno calls.
13201 (update_conflict_hard_regno_costs): Add checking conflicts with
13202 allocnos_conflict_p. Adjust calls of queue_update_cost and
13203 get_next_update_cost.
13204 (assign_hard_reg): Adjust calls of queue_update_cost. Add
13206 (bucket_allocno_compare_func): Restore previous version.
13208 2020-02-21 John David Anglin <danglin@gcc.gnu.org>
13210 * config/pa/pa.c (pa_function_value): Fix check for word and
13211 double-word size when handling aggregate return values.
13212 * config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate
13213 that homogeneous SFmode and DFmode aggregates are passed and returned
13214 in general registers.
13216 2020-02-21 Jakub Jelinek <jakub@redhat.com>
13218 PR translation/93759
13219 * opts.c (print_filtered_help): Translate help before appending
13220 messages to it rather than after that.
13222 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13224 PR rtl-optimization/PR92989
13225 * lra-lives.c (process_bb_lives): Restore the original order
13226 of the bb liveness update. Call make_hard_regno_dead for each
13227 register clobbered at the start of an EH receiver.
13229 2020-02-18 Feng Xue <fxue@os.amperecomputing.com>
13232 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as
13233 self-recursively generated.
13235 2020-02-21 Iain Sandoe <iain@sandoe.co.uk>
13238 * config/darwin-c.c (pop_field_alignment): Adjust quoting of
13241 2020-02-21 Mihail Ionescu <mihail.ionescu@arm.com>
13243 * doc/sourcebuild.texi (arm_v8_1m_mve_ok):
13244 Document new target supports option.
13246 2020-02-21 Dennis Zhang <dennis.zhang@arm.com>
13248 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New.
13249 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New.
13250 * config/arm/iterators.md (MATMUL): New iterator.
13251 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US.
13252 (mmla_sfx): New attribute.
13253 * config/arm/neon.md (neon_<sup>mmlav16qi): New.
13254 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New.
13255 (UNSPEC_MATMUL_US): New.
13257 2020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13259 * config/arm/arm.md: Prevent scalar shifts from being used when big
13262 2020-02-21 Jan Hubicka <hubicka@ucw.cz>
13263 Richard Biener <rguenther@suse.de>
13265 PR tree-optimization/93586
13266 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk
13267 after mismatched array refs; do not sure type size information to
13268 recover from unmatched referneces with !flag_strict_aliasing_p.
13270 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13272 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ...
13273 (gather_load<mode>v64si): ... this and set operand 2 to V64SI.
13274 (scatter_store<mode>): Rename to ...
13275 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI.
13276 (scatter<mode>_exec): Delete. Move contents ...
13277 (mask_scatter_store<mode>): ... here, and rename that to ...
13278 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI.
13279 Remove mode conversion.
13280 (mask_gather_load<mode>): Rename to ...
13281 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI.
13282 Remove mode conversion.
13283 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
13285 2020-02-21 Martin Jambor <mjambor@suse.cz>
13287 PR tree-optimization/93845
13288 * tree-sra.c (verify_sra_access_forest): Only test access size of
13291 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13293 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
13294 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
13295 (addv64di3_exec): Likewise.
13296 (subv64di3): Likewise.
13297 (subv64di3_exec): Likewise.
13298 (addv64di3_zext): Likewise.
13299 (addv64di3_zext_exec): Likewise.
13300 (addv64di3_zext_dup): Likewise.
13301 (addv64di3_zext_dup_exec): Likewise.
13302 (addv64di3_zext_dup2): Likewise.
13303 (addv64di3_zext_dup2_exec): Likewise.
13304 (addv64di3_sext_dup2): Likewise.
13305 (addv64di3_sext_dup2_exec): Likewise.
13306 (<expander>v64di3): Likewise.
13307 (<expander>v64di3_exec): Likewise.
13308 (*<reduc_op>_dpp_shr_v64di): Likewise.
13309 (*plus_carry_dpp_shr_v64di): Likewise.
13310 * config/gcn/gcn.md (adddi3): Likewise.
13311 (addptrdi3): Likewise.
13312 (<expander>di3): Likewise.
13314 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13316 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
13318 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13320 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE
13321 support. Use aarch64_emit_mult instead of emitting multiplication
13322 instructions directly.
13323 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2)
13324 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders.
13326 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13328 * config/aarch64/aarch64.c (aarch64_emit_mult): New function.
13329 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult
13330 instead of emitting multiplication instructions directly.
13331 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator.
13332 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>)
13333 (@aarch64_frecps<mode>): New expanders.
13335 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13337 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate
13338 on and produce uint64_ts rather than ints.
13339 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts.
13340 (cpu_approx_modes): Change the fields from unsigned int to uint64_t.
13342 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13344 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create
13345 an unused xmsk register when handling approximate rsqrt.
13347 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13349 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted
13350 flag_finite_math_only condition.
13352 2020-02-20 Uroš Bizjak <ubizjak@gmail.com>
13355 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand
13356 to destination operand for shufps alternative.
13357 (*vec_extractv2si_1): Ditto.
13359 2020-02-20 Peter Bergner <bergner@linux.ibm.com>
13362 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
13365 2020-02-20 Martin Liska <mliska@suse.cz>
13367 PR translation/93831
13368 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode.
13370 2020-02-20 Martin Liska <mliska@suse.cz>
13372 PR translation/93830
13373 * common/config/avr/avr-common.c: Remote trailing "|".
13375 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13377 * collect2.c (maybe_run_lto_and_relink): Fix typo in
13380 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13382 PR tree-optimization/93767
13383 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the
13384 access-size bias from the offset calculations for negative strides.
13386 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13388 * collect2.c (c_file, o_file): Make const again.
13389 (ldout,lderrout, dump_ld_file): Remove.
13390 (tool_cleanup): Avoid calling not signal-safe functions.
13391 (maybe_run_lto_and_relink): Avoid possible signal handler
13392 access to unintialzed memory (lto_o_files).
13393 (main): Avoid leaking temp files in $TMPDIR.
13394 Initialize c_file/o_file with concat, which avoids exposing
13395 uninitialized memory to signal handler, which calls unlink(!).
13396 Avoid calling maybe_unlink when the main function returns,
13397 since the atexit handler is already doing this.
13398 * collect2.h (dump_ld_file, ldout, lderrout): Remove.
13400 2020-02-19 Martin Jambor <mjambor@suse.cz>
13402 PR tree-optimization/93776
13403 * tree-sra.c (create_access): Do not create zero size accesses.
13404 (get_access_for_expr): Do not search for zero sized accesses.
13406 2020-02-19 Martin Jambor <mjambor@suse.cz>
13408 PR tree-optimization/93667
13409 * tree-sra.c (scalarizable_type_p): Return false if record fields
13410 do not follow wach other.
13412 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
13414 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
13415 rather than fmv.x.s/fmv.s.x.
13417 2020-02-18 James Greenhalgh <james.greenhalgh@arm.com>
13419 * config/aarch64/aarch64-simd-builtins.def
13420 (intrinsic_vec_smult_lo_): New.
13421 (intrinsic_vec_umult_lo_): Likewise.
13422 (vec_widen_smult_hi_): Likewise.
13423 (vec_widen_umult_hi_): Likewise.
13424 * config/aarch64/aarch64-simd.md
13425 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New.
13426 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics.
13427 (vmull_high_s16): Likewise.
13428 (vmull_high_s32): Likewise.
13429 (vmull_high_u8): Likewise.
13430 (vmull_high_u16): Likewise.
13431 (vmull_high_u32): Likewise.
13432 (vmull_s8): Likewise.
13433 (vmull_s16): Likewise.
13434 (vmull_s32): Likewise.
13435 (vmull_u8): Likewise.
13436 (vmull_u16): Likewise.
13437 (vmull_u32): Likewise.
13439 2020-02-18 Martin Liska <mliska@suse.cz>
13441 * value-prof.c (stream_out_histogram_value): Restore LTO PGO
13442 bootstrap by missing removal of invalid sanity check.
13444 2020-02-18 Martin Liska <mliska@suse.cz>
13447 * ipa-icf-gimple.c (func_checker::compare_gimple_assign):
13448 Always compare LHS of gimple_assign.
13450 2020-02-18 Martin Liska <mliska@suse.cz>
13453 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute
13454 and return type of functions.
13455 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl):
13456 Drop MALLOC attribute for void functions.
13457 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop
13458 malloc_state for a new VOID clone.
13460 2020-02-18 Martin Liska <mliska@suse.cz>
13463 * common.opt: Add -fprofile-reproducibility.
13464 * doc/invoke.texi: Document it.
13465 * value-prof.c (dump_histogram_value):
13466 Document and support behavior for counters[0]
13467 being a negative value.
13468 (get_nth_most_common_value): Handle negative
13469 counters[0] in respect to flag_profile_reproducible.
13471 2020-02-18 Jakub Jelinek <jakub@redhat.com>
13474 * cgraph.c (verify_speculative_call): Use speculative_id instead of
13475 speculative_uid in messages. Remove trailing whitespace from error
13476 message. Use num_speculative_call_targets instead of
13477 num_speculative_targets in a message.
13478 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in
13479 edge messages and stmt instead of cal_stmt in reference message.
13481 PR tree-optimization/93780
13482 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p
13483 before calling build_vector_type.
13484 (execute_update_addresses_taken): Likewise.
13487 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help
13488 typo, functoin -> function.
13489 * tree.c (free_lang_data_in_decl): Fix comment typo,
13490 functoin -> function.
13491 * ipa-visibility.c (cgraph_externally_visible_p): Likewise.
13493 2020-02-17 David Malcolm <dmalcolm@redhat.com>
13495 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs
13497 (print_option_information): Don't call get_option_url if URLs
13500 2020-02-17 Alexandre Oliva <oliva@adacore.com>
13502 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete
13503 handling of register_common-less targets.
13505 2020-02-17 Martin Liska <mliska@suse.cz>
13508 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar.
13510 2020-02-17 Martin Liska <mliska@suse.cz>
13512 PR translation/93755
13513 * config/rs6000/rs6000.c (rs6000_option_override_internal):
13516 2020-02-17 Martin Liska <mliska@suse.cz>
13519 * config/rx/elf.opt: Fix typo.
13521 2020-02-17 Richard Biener <rguenther@suse.de>
13524 * opts-global.c (print_ignored_options): Use inform and
13527 2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
13530 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber.
13532 2020-02-16 Uroš Bizjak <ubizjak@gmail.com>
13535 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2.
13536 (atan2<mode>3): Update operand order in the call to gen_atan2xf3.
13538 2020-02-15 Jason Merrill <jason@redhat.com>
13540 * doc/invoke.texi (C Dialect Options): Add -std=c++20.
13542 2020-02-15 Jakub Jelinek <jakub@redhat.com>
13544 PR tree-optimization/93744
13545 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0,
13546 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A,
13547 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make
13548 sure @2 in the first and @1 in the other patterns has no side-effects.
13550 2020-02-15 David Malcolm <dmalcolm@redhat.com>
13551 Bernd Edlinger <bernd.edlinger@hotmail.de>
13555 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
13556 * configure.ac (--with-diagnostics-urls): New configuration
13557 option, based on --with-diagnostics-color.
13558 (DIAGNOSTICS_URLS_DEFAULT): New define.
13559 * config.h: Regenerate.
13560 * configure: Regenerate.
13561 * diagnostic.c (diagnostic_urls_init): Handle -1 for
13562 DIAGNOSTICS_URLS_DEFAULT from configure-time
13563 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
13564 and TERM_URLS environment variable.
13565 * diagnostic-url.h (diagnostic_url_format): New enum type.
13566 (diagnostic_urls_enabled_p): rename to...
13567 (determine_url_format): ... this, and change return type.
13568 * diagnostic-color.c (parse_env_vars_for_urls): New helper function.
13569 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
13570 the linux console, and mingw.
13571 (diagnostic_urls_enabled_p): rename to...
13572 (determine_url_format): ... this, and adjust.
13573 * pretty-print.h (pretty_printer::show_urls): rename to...
13574 (pretty_printer::url_format): ... this, and change to enum.
13575 * pretty-print.c (pretty_printer::pretty_printer,
13576 pp_begin_url, pp_end_url, test_urls): Adjust.
13577 * doc/install.texi (--with-diagnostics-urls): Document the new
13578 configuration option.
13579 (--with-diagnostics-color): Document the existing interaction
13580 with GCC_COLORS better.
13581 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
13582 vindex reference. Update description of defaults based on the above.
13583 (-fdiagnostics-color): Update description of how -fdiagnostics-color
13584 interacts with GCC_COLORS.
13586 2020-02-14 Eric Botcazou <ebotcazou@adacore.com>
13589 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in
13590 conjunction with TARGET_GNU_TLS in early return.
13592 2020-02-14 Alexander Monakov <amonakov@ispras.ru>
13594 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if
13595 the mode is not wider than UNITS_PER_WORD.
13597 2020-02-14 Martin Jambor <mjambor@suse.cz>
13599 PR tree-optimization/93516
13600 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create
13601 access of the same type as the parent.
13602 (propagate_subaccesses_from_lhs): Likewise.
13604 2020-02-14 Hongtao Liu <hongtao.liu@intel.com>
13607 * config/i386/avx512vbmi2intrin.h
13608 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16,
13609 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32,
13610 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
13611 _m512_shrdi_epi64, _m512_mask_shrdi_epi64,
13612 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16,
13613 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16,
13614 _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
13615 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64,
13616 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo
13617 of lacking a closing parenthesis.
13618 * config/i386/avx512vbmi2vlintrin.h
13619 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16,
13620 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32,
13621 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32,
13622 _m256_shrdi_epi64, _m256_mask_shrdi_epi64,
13623 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16,
13624 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16,
13625 _mm256_shldi_epi32, _mm256_mask_shldi_epi32,
13626 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64,
13627 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64,
13628 _mm_shrdi_epi16, _mm_mask_shrdi_epi16,
13629 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32,
13630 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32,
13631 _mm_shrdi_epi64, _mm_mask_shrdi_epi64,
13632 _m_maskz_shrdi_epi64, _mm_shldi_epi16,
13633 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16,
13634 _mm_shldi_epi32, _mm_mask_shldi_epi32,
13635 _mm_maskz_shldi_epi32, _mm_shldi_epi64,
13636 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto.
13638 2020-02-13 H.J. Lu <hongjiu.lu@intel.com>
13641 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
13642 the target function entry.
13644 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13646 * common/config/arc/arc-common.c (arc_option_optimization_table):
13647 Disable if-conversion step when optimized for size.
13649 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13651 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
13652 R12-R15 are always in ARCOMPACT16_REGS register class.
13653 * config/arc/arc.opt (mq-class): Deprecate.
13654 * config/arc/constraint.md ("q"): Remove dependency on mq-class
13656 * doc/invoke.texi (mq-class): Update text.
13657 * common/config/arc/arc-common.c (arc_option_optimization_table):
13660 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13662 * config/arc/arc.c (arc_insn_cost): New function.
13663 (TARGET_INSN_COST): Define.
13664 * config/arc/arc.md (cost): New attribute.
13665 (add_n): Use arc_nonmemory_operand.
13666 (ashlsi3_insn): Likewise, also update constraints.
13667 (ashrsi3_insn): Likewise.
13668 (rotrsi3): Likewise.
13669 (add_shift): Likewise.
13670 * config/arc/predicates.md (arc_nonmemory_operand): New predicate.
13672 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13674 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
13676 (umulsidi_600): Likewise.
13678 2020-02-13 Jakub Jelinek <jakub@redhat.com>
13681 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8,
13682 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8,
13683 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8,
13684 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W,
13685 pass __A to the builtin followed by __W instead of __A followed by
13687 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32,
13688 _mm512_mask_popcnt_epi64): Likewise.
13689 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32,
13690 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64,
13691 _mm256_mask_popcnt_epi64): Likewise.
13693 PR tree-optimization/93582
13694 * fold-const.h (shift_bytes_in_array_left,
13695 shift_bytes_in_array_right): Declare.
13696 * fold-const.c (shift_bytes_in_array_left,
13697 shift_bytes_in_array_right): New function, moved from
13698 gimple-ssa-store-merging.c, no longer static.
13699 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move
13700 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left.
13701 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c.
13702 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of
13703 shift_bytes_in_array.
13704 (verify_shift_bytes_in_array): Rename to ...
13705 (verify_shift_bytes_in_array_left): ... this. Use
13706 shift_bytes_in_array_left instead of shift_bytes_in_array.
13707 (store_merging_c_tests): Call verify_shift_bytes_in_array_left
13708 instead of verify_shift_bytes_in_array.
13709 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr
13710 / native_interpret_expr where the store covers all needed bits,
13711 punt on PDP-endian, otherwise allow all involved offsets and sizes
13712 not to be byte-aligned.
13715 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and
13716 use const_0_to_255_operand predicate instead of immediate_operand.
13717 (avx512dq_fpclass<mode><mask_scalar_merge_name>,
13718 avx512dq_vmfpclass<mode><mask_scalar_merge_name>,
13719 vgf2p8affineinvqb_<mode><mask_name>,
13720 vgf2p8affineqb_<mode><mask_name>): Drop mode from
13721 const_0_to_255_operand predicated operands.
13723 2020-02-12 Jeff Law <law@redhat.com>
13725 * config/h8300/h8300.md (comparison shortening peepholes): Use
13726 a mode iterator to merge the HImode and SImode peepholes.
13728 2020-02-12 Jakub Jelinek <jakub@redhat.com>
13730 PR middle-end/93663
13731 * real.c (is_even): Make static. Function comment fix.
13732 (is_halfway_below): Make static, don't assert R is not inf/nan,
13733 instead return false for those. Small formatting fixes.
13735 2020-02-12 Martin Sebor <msebor@redhat.com>
13737 PR middle-end/93646
13738 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename...
13739 (handle_builtin_stxncpy_strncat): ...to this. Change first argument.
13740 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation.
13741 (strlen_check_and_optimize_call): Adjust callee name.
13743 2020-02-12 Jeff Law <law@redhat.com>
13745 * config/h8300/h8300.md (comparison shortening peepholes): Drop
13746 (and (xor)) variant. Combine other two into single peephole.
13748 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
13750 PR rtl-optimization/93565
13751 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs.
13753 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
13755 * config/aarch64/aarch64-simd.md
13756 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
13757 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
13758 generating separate ADDV and zero_extend patterns.
13759 * config/aarch64/iterators.md (VDQV_E): New iterator.
13761 2020-02-12 Jeff Law <law@redhat.com>
13763 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns,
13764 expanders, splits, etc.
13765 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise.
13766 (stpcpy_internal_<mode>, stpcpy splitter): Likewise.
13767 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise.
13768 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function.
13769 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise
13770 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused
13771 function prototype.
13772 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise.
13774 2020-02-12 Jakub Jelinek <jakub@redhat.com>
13777 * config/i386/sse.md (VI48F_256_DQ): New mode iterator.
13778 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove
13779 TARGET_AVX512DQ from condition.
13780 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition>
13781 instead of <mask_mode512bit_condition> in condition. If
13782 TARGET_AVX512DQ is false, emit vextract*64x4 instead of
13784 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition>
13787 2020-02-12 Kewen Lin <linkw@gcc.gnu.org>
13790 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn.
13792 2020-02-12 Segher Boessenkool <segher@kernel.crashing.org>
13794 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof
13795 where strlen is more legible.
13796 (rs6000_builtin_vectorized_libmass): Ditto.
13797 (rs6000_print_options_internal): Ditto.
13799 2020-02-11 Martin Sebor <msebor@redhat.com>
13801 PR tree-optimization/93683
13802 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set.
13804 2020-02-11 Michael Meissner <meissner@linux.ibm.com>
13806 * config/rs6000/predicates.md (cint34_operand): Rename the
13807 -mprefixed-addr option to be -mprefixed.
13808 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename
13809 the -mprefixed-addr option to be -mprefixed.
13810 (OTHER_FUTURE_MASKS): Likewise.
13811 (POWERPC_MASKS): Likewise.
13812 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
13813 the -mprefixed-addr option to be -mprefixed. Change error
13814 messages to refer to -mprefixed.
13815 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be
13817 (rs6000_legitimate_offset_address_p): Likewise.
13818 (rs6000_mode_dependent_address): Likewise.
13819 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be
13820 "-mprefixed" for target attributes and pragmas.
13821 (address_to_insn_form): Rename the -mprefixed-addr option to be
13823 (rs6000_adjust_insn_length): Likewise.
13824 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the
13825 -mprefixed-addr option to be -mprefixed.
13826 (ASM_OUTPUT_OPCODE): Likewise.
13827 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the
13828 -mprefixed-addr option to be -mprefixed.
13829 * config/rs6000/rs6000.opt (-mprefixed): Rename the
13830 -mprefixed-addr option to be prefixed. Change the option from
13831 being undocumented to being documented.
13832 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the
13833 -mprefixed option. Update the -mpcrel documentation to mention
13836 2020-02-11 Hans-Peter Nilsson <hp@axis.com>
13838 * ira-conflicts.c (print_hard_reg_set): Correct output for sets
13839 including FIRST_PSEUDO_REGISTER - 1.
13840 * ira-color.c (print_hard_reg_set): Ditto.
13842 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13844 * config/arm/arm-builtins.c (enum arm_type_qualifiers):
13845 (USTERNOP_QUALIFIERS): New define.
13846 (USMAC_LANE_QUADTUP_QUALIFIERS): New define.
13847 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define.
13848 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX.
13849 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index.
13850 * config/arm/arm_neon.h (vusdot_s32): New.
13851 (vusdot_lane_s32): New.
13852 (vusdotq_lane_s32): New.
13853 (vsudot_lane_s32): New.
13854 (vsudotq_lane_s32): New.
13855 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New.
13856 * config/arm/iterators.md (DOTPROD_I8MM): New.
13857 (sup, opsuffix): Add <us/su>.
13858 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New.
13859 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New.
13861 2020-02-11 Richard Biener <rguenther@suse.de>
13863 PR tree-optimization/93661
13864 PR tree-optimization/93662
13865 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard
13866 tree_to_poly_int64.
13867 * tree-sra.c (get_access_for_expr): Likewise.
13869 2020-02-10 Jakub Jelinek <jakub@redhat.com>
13872 * config/i386/sse.md (VI_256_AVX2): New mode iterator.
13873 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256.
13874 Change condition from TARGET_AVX2 to TARGET_AVX.
13876 2020-02-10 Iain Sandoe <iain@sandoe.co.uk>
13879 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last
13880 argument of strncmp.
13882 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
13884 Try to generate zero-based comparisons.
13885 * config/cris/cris.c (cris_reduce_compare): New function.
13886 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype.
13887 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4")
13888 (cstore<mode>4"): Apply cris_reduce_compare in expanders.
13890 2020-02-10 Richard Earnshaw <rearnsha@arm.com>
13893 * config/arm/arm.md (movsi_compare0): Allow SP as a source register
13894 in Thumb state and also as a destination in Arm state. Add T16
13897 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
13899 * md.texi (Define Subst): Match closing paren in example.
13901 2020-02-10 Jakub Jelinek <jakub@redhat.com>
13905 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last
13906 arguments of strncmp.
13908 2020-02-10 Feng Xue <fxue@os.amperecomputing.com>
13911 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge
13912 but different source value.
13913 (adjust_callers_for_value_intersection): New function.
13914 (gather_edges_for_value): Adjust order of callers to let a
13915 non-self-recursive caller be the first element.
13916 (self_recursive_pass_through_p): Add a new parameter "simple", and
13917 check generalized self-recursive pass-through jump function.
13918 (self_recursive_agg_pass_through_p): Likewise.
13919 (find_more_scalar_values_for_callers_subset): Compute value from
13920 pass-through jump function for self-recursive.
13921 (intersect_with_plats): Cleanup previous implementation code for value
13922 itersection with self-recursive call edge.
13923 (intersect_with_agg_replacements): Likewise.
13924 (intersect_aggregates_with_edge): Deduce value from pass-through jump
13925 function for self-recursive call edge. Cleanup previous implementation
13926 code for value intersection with self-recursive call edge.
13927 (decide_whether_version_node): Remove dead callers and adjust order
13928 to let a non-self-recursive caller be the first element.
13930 2020-02-09 Uroš Bizjak <ubizjak@gmail.com>
13932 * recog.c: Move pass_split_before_sched2 code in front of
13933 pass_split_before_regstack.
13934 (pass_data_split_before_sched2): Rename pass to split3 from split4.
13935 (pass_data_split_before_regstack): Rename pass to split4 from split3.
13936 (rest_of_handle_split_before_sched2): Remove.
13937 (pass_split_before_sched2::execute): Unconditionally call
13939 (enable_split_before_sched2): New function.
13940 (pass_split_before_sched2::gate): Use enable_split_before_sched2.
13941 (pass_split_before_regstack::gate): Ditto.
13942 * config/nds32/nds32.c (nds32_split_double_word_load_store_p):
13943 Update name check for renamed split4 pass.
13944 * config/sh/sh.c (register_sh_passes): Update pass insertion
13945 point for renamed split4 pass.
13947 2020-02-09 Jakub Jelinek <jakub@redhat.com>
13949 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote
13950 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid
13951 copying them around between host and target.
13953 2020-02-08 Andrew Pinski <apinski@marvell.com>
13956 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
13957 STRICT_ALIGNMENT also.
13959 2020-02-08 Jim Wilson <jimw@sifive.com>
13962 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
13964 2020-02-08 Uroš Bizjak <ubizjak@gmail.com>
13965 Jakub Jelinek <jakub@redhat.com>
13968 * config/i386/i386.h (CALL_USED_REGISTERS): Make
13969 xmm16-xmm31 call-used even in 64-bit ms-abi.
13971 2020-02-07 Dennis Zhang <dennis.zhang@arm.com>
13973 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry.
13974 (simd_ummla, simd_usmmla): Likewise.
13975 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New.
13976 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New.
13977 (vusmmlaq_s32): New.
13979 2020-02-07 Richard Biener <rguenther@suse.de>
13981 PR middle-end/93519
13982 * tree-inline.c (fold_marked_statements): Do a PRE walk,
13983 skipping unreachable regions.
13984 (optimize_inline_calls): Skip folding stmts when we didn't
13987 2020-02-07 H.J. Lu <hongjiu.lu@intel.com>
13990 * config/i386/i386.c (function_arg_ms_64): Add a type argument.
13991 Don't return aggregates with only SFmode and DFmode in SSE
13993 (ix86_function_arg): Pass arg.type to function_arg_ms_64.
13995 2020-02-07 Jakub Jelinek <jakub@redhat.com>
13998 * config/rs6000/rs6000-logue.c
13999 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn,
14000 if it fails, move rs into end_addr and retry. Add
14001 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or
14002 the insn pattern doesn't describe well what exactly happens to
14006 * config/i386/predicates.md (avx_identity_operand): Remove.
14007 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove.
14008 (avx_<castmode><avxsizesuffix>_<castmode>,
14009 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to
14010 a VEC_CONCAT of the operand and UNSPEC_CAST.
14011 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to
14012 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with
14016 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear
14017 recog_data.insn if distance_non_agu_define changed it.
14019 2020-02-06 Michael Meissner <meissner@linux.ibm.com>
14022 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
14023 we only had X-FORM (reg+reg) addressing for vectors. Also before
14024 ISA 3.0, we only had X-FORM addressing for scalars in the
14025 traditional Altivec registers.
14027 2020-02-06 <zhongyunde@huawei.com>
14028 Vladimir Makarov <vmakarov@redhat.com>
14030 PR rtl-optimization/93561
14031 * lra-assigns.c (spill_for): Check that tested hard regno is not out of
14032 hard register range.
14034 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14036 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type
14039 2020-02-06 Segher Boessenkool <segher@kernel.crashing.org>
14041 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case
14042 where the low and the high 32 bits are equal to each other specially,
14043 with an rldimi instruction.
14045 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
14047 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main.
14049 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
14051 * config/arm/arm-tables.opt: Regenerate.
14053 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14056 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare.
14057 * config/aarch64/aarch64.c (aarch64_movk_shift): New function.
14058 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern.
14060 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14062 PR rtl-optimization/87763
14063 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern.
14065 2020-02-06 Delia Burduv <delia.burduv@arm.com>
14067 * config/aarch64/aarch64-simd-builtins.def
14068 (bfmlaq): New built-in function.
14069 (bfmlalb): New built-in function.
14070 (bfmlalt): New built-in function.
14071 (bfmlalb_lane): New built-in function.
14072 (bfmlalt_lane): New built-in function.
14073 * config/aarch64/aarch64-simd.md
14074 (aarch64_bfmmlaqv4sf): New pattern.
14075 (aarch64_bfmlal<bt>v4sf): New pattern.
14076 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern.
14077 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic.
14078 (vbfmlalbq_f32): New intrinsic.
14079 (vbfmlaltq_f32): New intrinsic.
14080 (vbfmlalbq_lane_f32): New intrinsic.
14081 (vbfmlaltq_lane_f32): New intrinsic.
14082 (vbfmlalbq_laneq_f32): New intrinsic.
14083 (vbfmlaltq_laneq_f32): New intrinsic.
14084 * config/aarch64/iterators.md (BF_MLA): New int iterator.
14085 (bt): New int attribute.
14087 2020-02-06 Uroš Bizjak <ubizjak@gmail.com>
14089 * config/i386/i386.md (*pushtf): Emit "#" instead of
14090 calling gcc_unreachable in insn output.
14093 (*pushsf_rex64): Ditto for alternatives other than 1.
14094 (*pushsf): Ditto for alternatives other than 1.
14096 2020-02-06 Martin Liska <mliska@suse.cz>
14098 PR gcov-profile/91971
14099 PR gcov-profile/93466
14100 * coverage.c (coverage_init): Revert mangling of
14101 path into filename. It can lead to huge filename length.
14102 Creation of subfolders seem more natural.
14104 2020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14107 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New.
14108 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs.
14109 Use arm_block_arith_comp_libfuncs_for_mode for HFmode.
14111 2020-02-06 Jakub Jelinek <jakub@redhat.com>
14114 * config/i386/predicates.md (avx_identity_operand): New predicate.
14115 * config/i386/sse.md (*avx_vec_concat<mode>_1): New
14116 define_insn_and_split.
14119 * omp-low.c (use_pointer_for_field): For nested constructs, also
14120 look for map clauses on target construct.
14121 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily
14122 taskreg_nesting_level.
14125 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding
14126 shared clause, call omp_notice_variable on outer context if any.
14128 2020-02-05 Jason Merrill <jason@redhat.com>
14131 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has
14132 non-zero address even if weak and not yet defined.
14134 2020-02-05 Martin Sebor <msebor@redhat.com>
14136 PR tree-optimization/92765
14137 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL.
14138 * tree-ssa-strlen.c (compute_string_length): Remove.
14139 (determine_min_objsize): Remove.
14140 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic.
14141 Avoid using type size as the upper bound on string length.
14142 (handle_builtin_string_cmp): Add an argument. Adjust.
14143 (strlen_check_and_optimize_call): Pass additional argument to
14144 handle_builtin_string_cmp.
14146 2020-02-05 Uroš Bizjak <ubizjak@gmail.com>
14148 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove.
14149 (*pushdi2_rex64 peephole2): Unconditionally split after
14150 epilogue_completed.
14151 (*ashl<mode>3_doubleword): Ditto.
14152 (*<shift_insn><mode>3_doubleword): Ditto.
14154 2020-02-05 Michael Meissner <meissner@linux.ibm.com>
14157 * config/rs6000/rs6000.c (get_vector_offset): Fix
14159 2020-02-05 Andrew Stubbs <ams@codesourcery.com>
14161 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space.
14163 2020-02-05 David Malcolm <dmalcolm@redhat.com>
14165 * doc/analyzer.texi
14166 (Special Functions for Debugging the Analyzer): Update description
14167 of __analyzer_dump_exploded_nodes.
14169 2020-02-05 Jakub Jelinek <jakub@redhat.com>
14172 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only
14173 include sets and not clobbers in the vzeroupper pattern.
14174 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that
14175 the parallel has 17 (64-bit) or 9 (32-bit) elts.
14176 (*avx_vzeroupper_1): New define_insn_and_split.
14179 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets,
14180 don't run when !optimize.
14181 (pass_split_before_regstack::gate): For STACK_REGS targets, run even
14184 2020-02-05 Richard Biener <rguenther@suse.de>
14186 PR middle-end/90648
14187 * genmatch.c (dt_node::gen_kids_1): Emit number of argument
14188 checks before matching calls.
14190 2020-02-05 Jakub Jelinek <jakub@redhat.com>
14192 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up
14193 function comment typo.
14195 PR middle-end/93555
14196 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or
14197 simd_clone_create failed when i == 0, adjust clone->nargs by
14200 2020-02-05 Martin Liska <mliska@suse.cz>
14203 * doc/invoke.texi: Document that one should
14204 not combine ASLR and -fpch.
14206 2020-02-04 Richard Biener <rguenther@suse.de>
14208 PR tree-optimization/93538
14209 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr.
14211 2020-02-04 Richard Biener <rguenther@suse.de>
14213 PR tree-optimization/91123
14214 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method.
14215 (vn_walk_cb_data::last_vuse): New member.
14216 (vn_walk_cb_data::saved_operands): Likewsie.
14217 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands.
14218 (vn_walk_cb_data::push_partial_def): Use finish.
14219 (vn_reference_lookup_2): Update last_vuse and use finish if
14220 we've saved operands.
14221 (vn_reference_lookup_3): Use finish and update calls to
14222 push_partial_defs everywhere. When translating through
14223 memcpy or aggregate copies save off operands and alias-set.
14224 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE
14225 operation for redundant store removal.
14227 2020-02-04 Richard Biener <rguenther@suse.de>
14229 PR tree-optimization/92819
14230 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid
14231 generating more stmts than before.
14233 2020-02-04 Martin Liska <mliska@suse.cz>
14235 * config/arm/arm.c (arm_gen_far_branch): Move the function
14236 outside of selftests.
14238 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14240 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
14241 function to adjust PC-relative vector addresses.
14242 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
14243 handle vectors with PC-relative addresses.
14245 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14247 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
14249 (hard_reg_and_mode_to_addr_mask): Delete.
14250 (rs6000_adjust_vec_address): If the original vector address
14251 was REG+REG or REG+OFFSET and the element is not zero, do the add
14252 of the elements in the original address before adding the offset
14253 for the vector element. Use address_to_insn_form to validate the
14254 address using the register being loaded, rather than guessing
14255 whether the address is a DS-FORM or DQ-FORM address.
14257 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14259 * config/rs6000/rs6000.c (get_vector_offset): New helper function
14260 to calculate the offset in memory from the start of a vector of a
14261 particular element. Add code to keep the element number in
14262 bounds if the element number is variable.
14263 (rs6000_adjust_vec_address): Move calculation of offset of the
14264 vector element to get_vector_offset.
14265 (rs6000_split_vec_extract_var): Do not do the initial AND of
14266 element here, move the code to get_vector_offset.
14268 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14270 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
14273 2020-02-03 Segher Boessenkool <segher@kernel.crashing.org>
14275 * config/rs6000/constraints.md: Improve documentation.
14277 2020-02-03 Richard Earnshaw <rearnsha@arm.com>
14280 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md)
14281 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change.
14283 2020-02-03 Andrew Stubbs <ams@codesourcery.com>
14285 * config.gcc: Remove "carrizo" support.
14286 * config/gcn/gcn-opts.h (processor_type): Likewise.
14287 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
14288 * config/gcn/gcn.opt (gpu_type): Likewise.
14289 * config/gcn/t-omp-device: Likewise.
14291 2020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14294 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
14295 * config/arm/arm.c (arm_gen_far_branch): New function
14296 arm_gen_far_branch.
14297 * config/arm/arm.md: Update b<cond> for Thumb2 range checks.
14299 2020-02-03 Julian Brown <julian@codesourcery.com>
14300 Tobias Burnus <tobias@codesourcery.com>
14302 * doc/invoke.texi: Update mention of OpenACC version to 2.6.
14304 2020-02-03 Jakub Jelinek <jakub@redhat.com>
14307 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit
14308 valid RTL to sum up the lowest and second lowest bytes of the popcnt
14311 2020-02-02 Vladimir Makarov <vmakarov@redhat.com>
14313 PR rtl-optimization/91333
14314 * ira-color.c (struct allocno_color_data): Add member
14316 (init_allocno_threads): Set the member up.
14317 (bucket_allocno_compare_func): Add compare hard reg
14320 2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
14322 nios2: Support for GOT-relative DW_EH_PE_datarel encoding.
14324 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION.
14325 * config.in: Regenerated.
14326 * configure: Regenerated.
14327 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling
14328 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION.
14329 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New.
14331 2020-02-01 Andrew Burgess <andrew.burgess@embecosm.com>
14333 * configure: Regenerate.
14335 2020-01-31 Vladimir Makarov <vmakarov@redhat.com>
14337 PR rtl-optimization/91333
14338 * ira-color.c (bucket_allocno_compare_func): Move conflict hard
14339 reg preferences comparison up.
14341 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14343 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro.
14344 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to
14345 aarch64-sve-builtins-base.h.
14346 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to
14347 aarch64-sve-builtins-base.cc.
14348 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane)
14349 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14350 (svcvtnt): Declare.
14351 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane)
14352 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14353 (svcvtnt): New functions.
14354 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane)
14355 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14356 (svcvtnt): New functions.
14357 (svcvt): Add a form that converts f32 to bf16.
14358 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat)
14359 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n):
14361 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type):
14362 Treat B as bfloat16_t.
14363 (ternary_bfloat_lane_base): New class.
14364 (ternary_bfloat_def): Likewise.
14365 (ternary_bfloat): New shape.
14366 (ternary_bfloat_lane_def): New class.
14367 (ternary_bfloat_lane): New shape.
14368 (ternary_bfloat_lanex2_def): New class.
14369 (ternary_bfloat_lanex2): New shape.
14370 (ternary_bfloat_opt_n_def): New class.
14371 (ternary_bfloat_opt_n): New shape.
14372 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro.
14373 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf)
14374 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns.
14375 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
14376 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14377 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14378 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise.
14379 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key
14380 the pattern off the narrow mode instead of the wider one.
14381 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator.
14382 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs.
14383 (sve_fp_op): Handle them.
14384 (SVE_BFLOAT_TERNARY_LONG): New int itertor.
14385 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
14387 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14389 * config/aarch64/arm_sve.h: Include arm_bf16.h.
14390 * config/aarch64/aarch64-modes.def (BF): Move definition before
14391 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF.
14392 (SVE_MODES): Handle BF modes.
14393 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
14395 (aarch64_full_sve_mode): Likewise.
14396 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF
14398 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF.
14399 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
14400 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count)
14401 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the
14403 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New
14405 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro.
14406 (TYPES_all_data): Add bf16.
14407 (TYPES_reinterpret1, TYPES_reinterpret): Likewise.
14408 (register_tuple_type): Increase buffer size.
14409 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type.
14410 (bf16): New type suffix.
14411 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv)
14412 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax)
14413 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr):
14414 Change type from all_data to all_arith.
14415 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp)
14416 (svminp): Likewise.
14418 2020-01-31 Dennis Zhang <dennis.zhang@arm.com>
14419 Matthew Malcomson <matthew.malcomson@arm.com>
14420 Richard Sandiford <richard.sandiford@arm.com>
14422 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension.
14423 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
14424 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
14425 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define
14426 __ARM_FEATURE_MATMUL_FP64.
14427 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16)
14428 (sve): Add AARCH64_FL_F32MM to the list of extensions that should
14429 be disabled at the same time.
14430 (f32mm): New extension.
14431 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro.
14432 (AARCH64_FL_F64MM): Bump to the next bit up.
14433 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM)
14434 (TARGET_SVE_F64MM): New macros.
14435 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator.
14436 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL)
14437 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q)
14438 (UNSPEC_ZIP2Q): New unspeccs.
14439 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators.
14440 (optab, sur, perm_insn): Handle the new unspecs.
14441 (sve_fp_op): Handle UNSPEC_FMMLA. Resort.
14442 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
14443 TARGET_SVE_F64MM instead of separate tests.
14444 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern.
14445 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise.
14446 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise.
14447 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise.
14448 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise.
14449 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro.
14450 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it.
14451 (TYPES_s_signed): New macro.
14452 (TYPES_s_integer): Use it.
14453 (TYPES_d_float): New macro.
14454 (TYPES_d_data): Use it.
14455 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare.
14456 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq)
14457 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise.
14458 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class.
14459 (svmmla): New shape.
14460 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3
14461 template parameters.
14462 (ternary_resize2_lane_base): Likewise.
14463 (ternary_resize2_base): New class.
14464 (ternary_qq_lane_base): Likewise.
14465 (ternary_intq_uintq_lane_def): Likewise.
14466 (ternary_intq_uintq_lane): New shape.
14467 (ternary_intq_uintq_opt_n_def): New class
14468 (ternary_intq_uintq_opt_n): New shape.
14469 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base.
14470 (ternary_uintq_intq_def): New class.
14471 (ternary_uintq_intq): New shape.
14472 (ternary_uintq_intq_lane_def): New class.
14473 (ternary_uintq_intq_lane): New shape.
14474 (ternary_uintq_intq_opt_n_def): New class.
14475 (ternary_uintq_intq_opt_n): New shape.
14476 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot)
14477 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla)
14478 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare.
14479 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl):
14481 (svdotprod_lane_impl): ...this new class.
14482 (svmmla_impl, svusdot_impl): New classes.
14483 (svdot_lane): Update to use svdotprod_lane_impl.
14484 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot)
14485 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New
14487 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base
14488 function, with no types defined.
14489 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New
14490 AARCH64_FL_I8MM functions.
14491 (svmmla): New AARCH64_FL_F32MM function.
14492 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6.
14493 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New
14494 AARCH64_FL_F64MM function.
14495 (REQUIRED_EXTENSIONS):
14497 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
14499 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
14502 2020-01-31 Uroš Bizjak <ubizjak@gmail.com>
14504 * config/i386/i386.md (*movoi_internal_avx): Do not check for
14505 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling.
14506 (*movti_internal): Do not check for
14507 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
14508 (*movtf_internal): Move check for TARGET_SSE2 and size optimization
14509 just after check for TARGET_AVX.
14510 (*movdf_internal): Ditto.
14511 * config/i386/mmx.md (*mov<mode>_internal): Do not check for
14512 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
14513 * config/i386/sse.md (mov<mode>_internal): Only check
14514 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check
14515 for TARGET_SSE2 and size optimization just after check for TARGET_AVX.
14516 (<sse>_andnot<mode>3<mask_name>): Move check for
14517 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX.
14518 (<code><mode>3<mask_name>): Ditto.
14519 (*andnot<mode>3): Ditto.
14520 (*andnottf3): Ditto.
14521 (*<code><mode>3): Ditto.
14522 (*<code>tf3): Ditto.
14523 (*andnot<VI:mode>3): Remove
14524 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling.
14525 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto.
14526 (*<code><VI12_AVX_AVX512F:mode>3): Ditto.
14527 (sse4_1_blendv<ssemodesuffix>): Ditto.
14528 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL):
14529 Explain that tune applies to 128bit instructions only.
14531 2020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com>
14533 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count
14534 to definition of hsa_kernel_description. Parse assembly to find SGPR
14535 and VGPR count of kernel and store in hsa_kernel_description.
14537 2020-01-31 Tamar Christina <tamar.christina@arm.com>
14539 PR rtl-optimization/91838
14540 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case
14541 to truncate if allowed or reject combination.
14543 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
14545 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step.
14546 (find_inv_vars_cb): Likewise.
14548 2020-01-31 David Malcolm <dmalcolm@redhat.com>
14550 * calls.c (special_function_p): Split out the check for DECL_NAME
14551 being non-NULL and fndecl being extern at file scope into a
14552 new maybe_special_function_p and call it. Drop check for fndecl
14553 being non-NULL that was after a usage of DECL_NAME (fndecl).
14554 * tree.h (maybe_special_function_p): New inline function.
14556 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
14558 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ...
14559 (mask_gather_load<mode>): ... here, and zero-initialize the
14561 (maskload<mode>di): Zero-initialize the destination.
14562 * config/gcn/gcn.c:
14564 2020-01-30 David Malcolm <dmalcolm@redhat.com>
14567 * doc/analyzer.texi (Limitations): Note that constraints on
14568 floating-point values are currently ignored.
14570 2020-01-30 Jakub Jelinek <jakub@redhat.com>
14573 * symtab.c (symtab_node::noninterposable_alias): If localalias
14574 already exists, but is not usable, append numbers after it until
14575 a unique name is found. Formatting fix.
14577 PR middle-end/93505
14578 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range
14581 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
14583 * config/gcn/gcn.c (print_operand): Handle LTGT.
14584 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt.
14586 2020-01-30 Richard Biener <rguenther@suse.de>
14588 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST
14589 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE.
14591 2020-01-30 John David Anglin <danglin@gcc.gnu.org>
14593 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers
14594 without a DECL in .data.rel.ro.local.
14596 2020-01-30 Jakub Jelinek <jakub@redhat.com>
14599 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4
14603 * config/i386/sse.md
14604 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ...
14605 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use
14606 any_extend code iterator instead of always zero_extend.
14607 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ...
14608 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this.
14609 Use any_extend code iterator instead of always zero_extend.
14610 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ...
14611 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this.
14612 Use any_extend code iterator instead of always zero_extend.
14613 (*sse2_pmovmskb_ext): New define_insn.
14614 (*sse2_pmovmskb_ext_lt): New define_insn_and_split.
14617 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split.
14618 (*popcountsi2_zext_falsedep): New define_insn.
14620 2020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
14622 * config.in: Regenerated.
14623 * configure: Regenerated.
14625 2020-01-29 Tobias Burnus <tobias@codesourcery.com>
14628 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as
14629 LLVM's assembler changed the default in version 9.
14631 2020-01-24 Jeff Law <law@redhat.com>
14633 PR tree-optimization/89689
14634 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure.
14636 2020-01-29 Richard Sandiford <richard.sandiford@arm.com>
14640 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14642 PR rtl-optimization/87763
14643 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
14644 simplification to handle subregs as well as bare regs.
14645 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
14647 2020-01-29 Joel Hutton <Joel.Hutton@arm.com>
14650 * ira.c (ira): Revert use of simplified LRA algorithm.
14652 2020-01-29 Martin Jambor <mjambor@suse.cz>
14654 PR tree-optimization/92706
14655 * tree-sra.c (struct access): Fields first_link, last_link,
14656 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link,
14657 next_rhs_queued and grp_rhs_queued respectively, new fields
14658 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued.
14659 (struct assign_link): Field next renamed to next_rhs, new field
14660 next_lhs. Updated comment.
14661 (work_queue_head): Renamed to rhs_work_queue_head.
14662 (lhs_work_queue_head): New variable.
14663 (add_link_to_lhs): New function.
14664 (relink_to_new_repr): Also relink LHS lists.
14665 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue.
14666 (add_access_to_lhs_work_queue): New function.
14667 (pop_access_from_work_queue): Renamed to
14668 pop_access_from_rhs_work_queue.
14669 (pop_access_from_lhs_work_queue): New function.
14670 (build_accesses_from_assign): Also add links to LHS lists and to LHS
14672 (child_would_conflict_in_lacc): Renamed to
14673 child_would_conflict_in_acc. Adjusted parameter names.
14674 (create_artificial_child_access): New parameter set_grp_read, use it.
14675 (subtree_mark_written_and_enqueue): Renamed to
14676 subtree_mark_written_and_rhs_enqueue.
14677 (propagate_subaccesses_across_link): Renamed to
14678 propagate_subaccesses_from_rhs.
14679 (propagate_subaccesses_from_lhs): New function.
14680 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to
14683 2020-01-29 Martin Jambor <mjambor@suse.cz>
14685 PR tree-optimization/92706
14686 * tree-sra.c (struct access): Adjust comment of
14687 grp_total_scalarization.
14688 (find_access_in_subtree): Look for single children spanning an entire
14690 (scalarizable_type_p): Allow register accesses, adjust callers.
14691 (completely_scalarize): Remove function.
14692 (scalarize_elem): Likewise.
14693 (create_total_scalarization_access): Likewise.
14694 (sort_and_splice_var_accesses): Do not track total scalarization
14696 (analyze_access_subtree): New parameter totally, adjust to new meaning
14697 of grp_total_scalarization.
14698 (analyze_access_trees): Pass new parameter to analyze_access_subtree.
14699 (can_totally_scalarize_forest_p): New function.
14700 (create_total_scalarization_access): Likewise.
14701 (create_total_access_and_reshape): Likewise.
14702 (total_should_skip_creating_access): Likewise.
14703 (totally_scalarize_subtree): Likewise.
14704 (analyze_all_variable_accesses): Perform total scalarization after
14705 subaccess propagation using the new functions above.
14706 (initialize_constant_pool_replacements): Output initializers by
14707 traversing the access tree.
14709 2020-01-29 Martin Jambor <mjambor@suse.cz>
14711 * tree-sra.c (verify_sra_access_forest): New function.
14712 (verify_all_sra_access_forests): Likewise.
14713 (create_artificial_child_access): Set parent.
14714 (analyze_all_variable_accesses): Call the verifier.
14716 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14718 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge
14719 if called on indirect edge.
14720 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of
14721 speculative call if needed.
14723 2020-01-29 Richard Biener <rguenther@suse.de>
14725 PR tree-optimization/93428
14726 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load
14727 permutation when the load node is created.
14728 (vect_analyze_slp_instance): Re-use it here.
14730 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14732 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning.
14734 2020-01-28 Vladimir Makarov <vmakarov@redhat.com>
14736 PR rtl-optimization/93272
14737 * ira-lives.c (process_out_of_region_eh_regs): New function.
14738 (process_bb_node_lives): Call it.
14740 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14742 * coverage.c (read_counts_file): Make error message lowercase.
14744 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14746 * profile-count.c (profile_quality_display_names): Fix ordering.
14748 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14751 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site
14752 hash only when edge is first within the sequence.
14753 (cgraph_edge::set_call_stmt): Update handling of speculative calls.
14754 (symbol_table::create_edge): Do not set target_prob.
14755 (cgraph_edge::remove_caller): Watch for speculative calls when updating
14756 the call site hash.
14757 (cgraph_edge::make_speculative): Drop target_prob parameter.
14758 (cgraph_edge::speculative_call_info): Remove.
14759 (cgraph_edge::first_speculative_call_target): New member function.
14760 (update_call_stmt_hash_for_removing_direct_edge): New function.
14761 (cgraph_edge::resolve_speculation): Rewrite to new API.
14762 (cgraph_edge::speculative_call_for_target): New member function.
14763 (cgraph_edge::make_direct): Rewrite to new API; fix handling of
14764 multiple speculation targets.
14765 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating
14767 (verify_speculative_call): Verify that targets form an interval.
14768 * cgraph.h (cgraph_edge::speculative_call_info): Remove.
14769 (cgraph_edge::first_speculative_call_target): New member function.
14770 (cgraph_edge::next_speculative_call_target): New member function.
14771 (cgraph_edge::speculative_call_target_ref): New member function.
14772 (cgraph_edge;:speculative_call_indirect_edge): New member funtion.
14773 (cgraph_edge): Remove target_prob.
14774 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
14775 Fix handling of speculative calls.
14776 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals.
14777 * ipa-fnsummary.c (analyze_function_body): Likewise.
14778 * ipa-inline.c (speculation_useful_p): Use new speculative call API.
14779 * ipa-profile.c (dump_histogram): Fix formating.
14780 (ipa_profile_generate_summary): Watch for overflows.
14781 (ipa_profile): Do not require probablity to be 1/2; update to new API.
14782 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API.
14783 (update_indirect_edges_after_inlining): Update to new API.
14784 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call
14786 * profile-count.h: (profile_probability::adjusted): New.
14787 * tree-inline.c (copy_bb): Update to new speculative call API; fix
14788 updating of profile.
14789 * value-prof.c (gimple_ic_transform): Rename to ...
14790 (dump_ic_profile): ... this one; update dumping.
14791 (stream_in_histogram_value): Fix formating.
14792 (gimple_value_profile_transformations): Update.
14794 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
14797 * config/i386/i386.md (*movoi_internal_avx): Remove
14798 TARGET_SSE_TYPELESS_STORES check.
14799 (*movti_internal): Prefer TARGET_AVX over
14800 TARGET_SSE_TYPELESS_STORES.
14801 (*movtf_internal): Likewise.
14802 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over
14803 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check
14804 from TARGET_SSE_TYPELESS_STORES.
14806 2020-01-28 David Malcolm <dmalcolm@redhat.com>
14808 * diagnostic-core.h (warning_at): Rename overload to...
14809 (warning_meta): ...this.
14810 (emit_diagnostic_valist): Delete decl of overload taking
14811 diagnostic_metadata.
14812 * diagnostic.c (emit_diagnostic_valist): Likewise for defn.
14813 (warning_at): Rename overload taking diagnostic_metadata to...
14814 (warning_meta): ...this.
14816 2020-01-28 Richard Biener <rguenther@suse.de>
14818 PR tree-optimization/93439
14819 * tree-parloops.c (create_loop_fn): Move clique bookkeeping...
14820 * tree-cfg.c (move_sese_region_to_fn): ... here.
14821 (verify_types_in_gimple_reference): Verify used cliques are
14824 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
14827 * config/i386/i386-options.c (set_ix86_tune_features): Add an
14828 argument of a pointer to struct gcc_options and pass it to
14829 parse_mtune_ctrl_str.
14830 (ix86_function_specific_restore): Pass opts to
14831 set_ix86_tune_features.
14832 (ix86_option_override_internal): Likewise.
14833 (parse_mtune_ctrl_str): Add an argument of a pointer to struct
14834 gcc_options and use it for x_ix86_tune_ctrl_string.
14836 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14838 PR rtl-optimization/87763
14839 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
14840 simplification to handle subregs as well as bare regs.
14841 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
14843 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14845 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully
14846 for reduction chains that (now) include a call.
14848 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14850 PR tree-optimization/92822
14851 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling
14852 out the don't-care elements of a vector whose significant elements
14853 are duplicates, make the don't-care elements duplicates too.
14855 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14857 PR tree-optimization/93434
14858 * tree-predcom.c (split_data_refs_to_components): Record which
14859 components have had aliasing loads removed. Prevent store-store
14860 commoning for all such components.
14862 2020-01-28 Jakub Jelinek <jakub@redhat.com>
14865 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not
14866 -1 or is_vshift is true, use new_vector with number of elts npatterns
14867 rather than new_unary_operation.
14869 PR tree-optimization/93454
14870 * gimple-fold.c (fold_array_ctor_reference): Perform
14871 elt_size.to_uhwi () just once, instead of calling it in every
14872 iteration. Punt if that value is above size of the temporary
14873 buffer. Decrease third native_encode_expr argument when
14874 bufoff + elt_sz is above size of buf.
14876 2020-01-27 Joseph Myers <joseph@codesourcery.com>
14878 * config/mips/mips.c (mips_declare_object_name)
14879 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object.
14881 2020-01-27 Martin Liska <mliska@suse.cz>
14883 PR gcov-profile/93403
14884 * tree-profile.c (gimple_init_gcov_profiler): Generate
14885 both __gcov_indirect_call_profiler_v4 and
14886 __gcov_indirect_call_profiler_v4_atomic.
14888 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
14891 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
14893 (@aarch64_split_simd_mov<mode>): Use it.
14894 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
14895 Leave the vec_extract patterns to handle 2-element vectors.
14896 (aarch64_simd_mov_from_<mode>high): Likewise.
14897 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
14898 (vec_extractv2dfv1df): Likewise.
14900 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
14902 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match
14903 jump conditions for *compare_condjump<GPI:mode>.
14905 2020-01-27 David Malcolm <dmalcolm@redhat.com>
14908 * digraph.cc (test_edge::test_edge): Specify template for base
14911 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
14913 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost.
14915 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
14917 * config/arc/arc-protos.h (gen_mlo): Remove.
14918 (gen_mhi): Likewise.
14919 * config/arc/arc.c (AUX_MULHI): Define.
14920 (arc_must_save_reister): Special handling for r58/59.
14921 (arc_compute_frame_size): Consider mlo/mhi registers.
14922 (arc_save_callee_saves): Emit fp/sp move only when emit_move
14924 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from
14925 mlo/mhi name selection.
14926 (arc_restore_callee_saves): Don't early restore blink when ISR.
14927 (arc_expand_prologue): Add mlo/mhi saving.
14928 (arc_expand_epilogue): Add mlo/mhi restoring.
14931 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register
14932 numbering when MUL64 option is used.
14933 (DWARF2_FRAME_REG_OUT): Define.
14934 * config/arc/arc.md (arc600_stall): New pattern.
14935 (VUNSPEC_ARC_ARC600_STALL): Define.
14936 (mulsi64): Use correct mlo/mhi registers.
14937 (mulsi_600): Clean it up.
14938 * config/arc/predicates.md (mlo_operand): Remove any dependency on
14940 (mhi_operand): Likewise.
14942 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
14943 Petro Karashchenko <petro.karashchenko@ring.com>
14945 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct
14946 attributes if needed.
14947 (prepare_move_operands): Generate special unspec instruction for
14949 (arc_isuncached_mem_p): Propagate uncached attribute to each
14951 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
14952 (VUNSPEC_ARC_STDI): Likewise.
14953 (ALLI): New mode iterator.
14954 (mALLI): New mode attribute.
14955 (lddi): New instruction pattern.
14957 (stdidi_split): Split instruction for architectures which are not
14958 supporting ll64 option.
14959 (lddidi_split): Likewise.
14961 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
14963 PR rtl-optimization/92989
14964 * lra-lives.c (process_bb_lives): Update the live-in set before
14965 processing additional clobbers.
14967 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
14969 PR rtl-optimization/93170
14970 * cselib.c (cselib_invalidate_regno_val): New function, split out
14972 (cselib_invalidate_regno): ...here.
14973 (cselib_invalidated_by_call_p): New function.
14974 (cselib_process_insn): Iterate over all the hard-register entries in
14975 REG_VALUES and invalidate any that cross call-clobbered registers.
14977 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
14979 * dojump.c (split_comparison): Use HONOR_NANS rather than
14980 HONOR_SNANS when splitting LTGT.
14982 2020-01-27 Martin Liska <mliska@suse.cz>
14985 * opts.c (print_filtered_help): Exclude language-specific
14986 options from --help=common unless enabled in all FEs.
14988 2020-01-27 Martin Liska <mliska@suse.cz>
14990 * opts.c (print_help): Exclude params from
14991 all except --help=param.
14993 2020-01-27 Martin Liska <mliska@suse.cz>
14996 * config/i386/i386-features.c (make_resolver_func):
14997 Align the code with ppc64 target implementation.
14998 Do not generate a unique name for resolver function.
15000 2020-01-27 Richard Biener <rguenther@suse.de>
15002 PR tree-optimization/93397
15003 * tree-vect-slp.c (vect_analyze_slp_instance): Delay
15004 converted reduction chain SLP graph adjustment.
15006 2020-01-26 Marek Polacek <polacek@redhat.com>
15009 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on
15012 2020-01-26 Jason Merrill <jason@redhat.com>
15015 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING
15018 2020-01-26 Darius Galis <darius.galis@cyberthorstudios.com>
15020 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint
15021 (rx_setmem): Likewise.
15023 2020-01-26 Jakub Jelinek <jakub@redhat.com>
15026 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword):
15027 Use nonimmediate_operand instead of x86_64_hilo_general_operand and
15028 drop <di> from constraint of last operand.
15031 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for
15032 TARGET_AVX2 and V4DFmode not in the split condition, but in the
15033 pattern condition, though allow { 0, 0, 0, 0 } broadcast always.
15035 2020-01-25 Feng Xue <fxue@os.amperecomputing.com>
15038 * ipa-cp.c (get_info_about_necessary_edges): Remove value
15041 2020-01-24 Jeff Law <law@redhat.com>
15043 PR tree-optimization/92788
15044 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX
15047 2020-01-24 Jakub Jelinek <jakub@redhat.com>
15050 * config/i386/sse.md (*avx_vperm_broadcast_v4sf,
15051 *avx_vperm_broadcast_<mode>,
15052 <sse2_avx_avx512f>_vpermil<mode><mask_name>,
15053 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>):
15054 Move before avx2_perm<mode>/avx512f_perm<mode>.
15057 * simplify-rtx.c (simplify_const_unary_operation,
15058 simplify_const_binary_operation): Punt for mode precision above
15059 MAX_BITSIZE_MODE_ANY_INT.
15061 2020-01-24 Andrew Pinski <apinski@marvell.com>
15063 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change
15064 alu.shift_reg to 0.
15066 2020-01-24 Jeff Law <law@redhat.com>
15069 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg
15070 for REGs. Call output_operand_lossage to get more reasonable
15073 2020-01-24 Andrew Stubbs <ams@codesourcery.com>
15075 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use
15076 gcn_fp_compare_operator.
15077 (vec_cmpu<mode>di): Use gcn_compare_operator.
15078 (vec_cmp<u>v64qidi): Use gcn_compare_operator.
15079 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator.
15080 (vec_cmpu<mode>di_exec): Use gcn_compare_operator.
15081 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator.
15082 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator.
15083 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator.
15084 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use
15085 gcn_fp_compare_operator.
15086 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use
15087 gcn_fp_compare_operator.
15088 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use
15089 gcn_fp_compare_operator.
15090 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use
15091 gcn_fp_compare_operator.
15093 2020-01-24 Maciej W. Rozycki <macro@wdc.com>
15095 * doc/install.texi (Cross-Compiler-Specific Options): Document
15096 `--with-toolexeclibdir' option.
15098 2020-01-24 Hans-Peter Nilsson <hp@axis.com>
15100 * target.def (flags_regnum): Also mention effect on delay slot filling.
15101 * doc/tm.texi: Regenerate.
15103 2020-01-23 Jeff Law <law@redhat.com>
15105 PR translation/90162
15106 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text.
15108 2020-01-23 Mikael Tillenius <mti-1@tillenius.com>
15111 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of
15114 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15116 PR rtl-optimization/93402
15117 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust
15120 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15122 * config.in: Regenerated.
15123 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
15124 for TARGET_LIBC_GNUSTACK.
15125 * configure: Regenerated.
15126 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
15127 found to be 2.31 or greater.
15129 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15131 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
15133 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
15134 (mips_asm_file_end): New function. Delegate to
15135 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
15136 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.
15138 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15141 * config/i386/i386-modes.def (POImode): New mode.
15142 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160.
15143 * config/i386/i386.md (DPWI): New mode attribute.
15144 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>.
15145 (QWI): Rename to...
15146 (QPWI): ... this. Use POI instead of OI for TImode.
15147 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1,
15148 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI>
15151 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15154 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New
15156 (speculation_tracker_rev): New pattern.
15157 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation):
15158 Use speculation_tracker_rev to track the inverse condition.
15160 2020-01-23 Richard Biener <rguenther@suse.de>
15162 PR tree-optimization/93381
15163 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take
15164 alias-set of the def as argument and record the first one.
15165 (vn_walk_cb_data::first_set): New member.
15166 (vn_reference_lookup_3): Pass the alias-set of the current def
15167 to push_partial_def. Fix alias-set used in the aggregate copy
15169 (vn_reference_lookup): Consistently set *last_vuse_ptr.
15170 * real.c (clear_significand_below): Fix out-of-bound access.
15172 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15175 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3):
15176 New define_insn patterns.
15178 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15180 * doc/sourcebuild.texi (check-function-bodies): Add an
15181 optional target/xfail selector.
15183 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15185 PR rtl-optimization/93124
15186 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to
15187 bare USE and CLOBBER insns.
15189 2020-01-22 Andrew Pinski <apinski@marvell.com>
15191 * config/arc/arc.c (output_short_suffix): Check insn for nullness.
15193 2020-01-22 David Malcolm <dmalcolm@redhat.com>
15196 * gdbinit.in (break-on-saved-diagnostic): Update for move of
15197 diagnostic_manager into "ana" namespace.
15198 * selftest-run-tests.c (selftest::run_tests): Update for move of
15199 selftest::run_analyzer_selftests to
15200 ana::selftest::run_analyzer_selftests.
15202 2020-01-22 Richard Sandiford <richard.sandiford@arm.com>
15204 * cfgexpand.c (union_stack_vars): Update the size.
15206 2020-01-22 Richard Biener <rguenther@suse.de>
15208 PR tree-optimization/93381
15209 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting
15210 throughout, handle all conversions the same.
15212 2020-01-22 Jakub Jelinek <jakub@redhat.com>
15215 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use
15216 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate
15217 predicate, not whenever it is CONST_INT. Otherwise, force_reg it.
15218 Call force_reg on high_in2 unconditionally.
15220 2020-01-22 Martin Liska <mliska@suse.cz>
15222 PR tree-optimization/92924
15223 * profile.c (compute_value_histograms): Divide
15224 all counter values.
15226 2020-01-22 Jakub Jelinek <jakub@redhat.com>
15229 * output.h (assemble_name_resolve): Declare.
15230 * varasm.c (assemble_name_resolve): New function.
15231 (assemble_name): Use it.
15232 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define.
15234 2020-01-22 Joseph Myers <joseph@codesourcery.com>
15236 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to
15237 update_web_docs_git instead of update_web_docs_svn.
15239 2020-01-21 Andrew Pinski <apinski@marvell.com>
15242 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
15243 as PTR mode. Have operand 1 as being modeless, it can be P mode.
15244 (*tlsgd_small_<mode>): Likewise.
15245 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
15246 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
15247 register. Convert that register back to dest using convert_mode.
15249 2020-01-21 Jim Wilson <jimw@sifive.com>
15251 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
15254 2020-01-21 H.J. Lu <hongjiu.lu@intel.com>
15255 Uros Bizjak <ubizjak@gmail.com>
15258 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode
15260 (legitimize_tls_address): Do GNU2 TLS address computation in
15261 ptr_mode and zero-extend result to Pmode.
15262 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace
15263 :P with :PTR and Pmode with ptr_mode.
15264 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise.
15265 (*tls_dynamic_gnu2_call_64_<mode>): Likewise.
15266 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise.
15268 2020-01-21 Jakub Jelinek <jakub@redhat.com>
15271 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify
15272 the last two operands are CONST_INT_P before using them as such.
15274 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
15276 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name
15277 to get the integer element types.
15279 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
15281 * config/aarch64/aarch64-sve-builtins.h
15282 (function_expander::convert_to_pmode): Declare.
15283 * config/aarch64/aarch64-sve-builtins.cc
15284 (function_expander::convert_to_pmode): New function.
15285 (function_expander::get_contiguous_base): Use it.
15286 (function_expander::prepare_gather_address_operands): Likewise.
15287 * config/aarch64/aarch64-sve-builtins-sve2.cc
15288 (svwhilerw_svwhilewr_impl::expand): Likewise.
15290 2020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com>
15293 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set
15294 cfun->machine->label_is_assembled.
15295 (aarch64_print_patchable_function_entry): New.
15296 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define.
15297 * config/aarch64/aarch64.h (struct machine_function): New field,
15298 label_is_assembled.
15300 2020-01-21 David Malcolm <dmalcolm@redhat.com>
15303 * ipa-profile.c (ipa_profile): Delete call_sums and set it to
15306 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15309 * cgraph.c (cgraph_edge::resolve_speculation,
15310 cgraph_edge::redirect_call_stmt_to_callee): Fix update of
15311 call_stmt_site_hash.
15313 2020-01-21 Martin Liska <mliska@suse.cz>
15315 * config/rs6000/rs6000.c (common_mode_defined): Remove
15318 2020-01-21 Richard Biener <rguenther@suse.de>
15320 PR tree-optimization/92328
15321 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve
15322 type when value-numbering same-sized store by inserting a
15324 (eliminate_dom_walker::eliminate_stmt): When eliminating
15325 a redundant store handle bit-reinterpretation of the same value.
15327 2020-01-21 Andrew Pinski <apinski@marvel.com>
15330 * tree-into-ssa.c (prepare_block_for_update_1): Split out
15332 (prepare_block_for_update): This. Use a worklist instead of
15335 2020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15337 * config/arm/arm.c (clear_operation_p):
15338 Initialise last_regno, skip first iteration
15339 based on the first_set value and use ints instead
15340 of the unnecessary HOST_WIDE_INTs.
15342 2020-01-21 Jakub Jelinek <jakub@redhat.com>
15345 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for
15346 compare_mode other than SFmode or DFmode.
15348 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
15351 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
15352 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
15353 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
15355 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15357 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
15359 2020-01-20 Andrew Pinski <apinski@marvell.com>
15361 PR middle-end/93242
15362 * targhooks.c (default_print_patchable_function_entry): Use
15363 output_asm_insn to emit the nop instruction.
15365 2020-01-20 Fangrui Song <maskray@google.com>
15367 PR middle-end/93194
15368 * targhooks.c (default_print_patchable_function_entry): Align to
15371 2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
15374 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to
15375 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode.
15376 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ...
15377 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P.
15378 (*tls_dynamic_gnu2_lea_64): Renamed to ...
15379 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P.
15380 Remove the {q} suffix from lea.
15381 (*tls_dynamic_gnu2_call_64): Renamed to ...
15382 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P.
15383 (*tls_dynamic_gnu2_combine_64): Renamed to ...
15384 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P.
15385 Pass Pmode to gen_tls_dynamic_gnu2_64.
15387 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15389 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1.
15391 2020-01-20 Richard Sandiford <richard.sandiford@arm.com>
15393 * config/aarch64/aarch64-sve-builtins-base.cc
15394 (svld1ro_impl::memory_vector_mode): Remove parameter name.
15396 2020-01-20 Richard Biener <rguenther@suse.de>
15399 * dwarf2out.c (prune_unused_types): Unconditionally mark
15400 called function DIEs.
15402 2020-01-20 Martin Liska <mliska@suse.cz>
15404 PR tree-optimization/93199
15405 * tree-eh.c (struct leh_state): Add
15406 new field outer_non_cleanup.
15407 (cleanup_is_dead_in): Pass leh_state instead
15408 of eh_region. Add a checking that state->outer_non_cleanup
15409 points to outer non-clean up region.
15410 (lower_try_finally): Record outer_non_cleanup
15412 (lower_catch): Likewise.
15413 (lower_eh_filter): Likewise.
15414 (lower_eh_must_not_throw): Likewise.
15415 (lower_cleanup): Likewise.
15417 2020-01-20 Richard Biener <rguenther@suse.de>
15419 PR tree-optimization/93094
15420 * tree-vectorizer.h (vect_loop_versioning): Adjust.
15421 (vect_transform_loop): Likewise.
15422 * tree-vectorizer.c (try_vectorize_loop_1): Pass down
15423 loop_vectorized_call to vect_transform_loop.
15424 * tree-vect-loop.c (vect_transform_loop): Pass down
15425 loop_vectorized_call to vect_loop_versioning.
15426 * tree-vect-loop-manip.c (vect_loop_versioning): Use
15427 the earlier discovered loop_vectorized_call.
15429 2020-01-19 Eric S. Raymond <esr@thyrsus.com>
15431 * doc/contribute.texi: Update for SVN -> Git transition.
15432 * doc/install.texi: Likewise.
15434 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15437 * cgraph.c (cgraph_edge::make_speculative): Increase number of
15438 speculative targets.
15439 (verify_speculative_call): New function
15440 (cgraph_node::verify_node): Use it.
15441 * ipa-profile.c (ipa_profile): Fix formating; do not set number of
15444 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15447 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting.
15448 (cgraph_edge::make_direct): Remove all indirect targets.
15449 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct..
15450 (cgraph_node::verify_node): Verify that only one call_stmt or
15451 lto_stmt_uid is set.
15452 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or
15454 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt.
15455 (lto_output_ref): Simplify streaming of stmt.
15456 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid.
15458 2020-01-18 Tamar Christina <tamar.christina@arm.com>
15460 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode):
15461 Mark parameter unused.
15463 2020-01-18 Hans-Peter Nilsson <hp@axis.com>
15465 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux*
15467 2019-01-18 Gerald Pfeifer <gerald@pfeifer.com>
15469 * varpool.c (ctor_useable_for_folding_p): Fix grammar.
15471 2020-01-18 Iain Sandoe <iain@sandoe.co.uk>
15473 * Makefile.in: Add coroutine-passes.o.
15474 * builtin-types.def (BT_CONST_SIZE): New.
15475 (BT_FN_BOOL_PTR): New.
15476 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New.
15477 * builtins.def (DEF_COROUTINE_BUILTIN): New.
15478 * coroutine-builtins.def: New file.
15479 * coroutine-passes.cc: New file.
15480 * function.h (struct GTY function): Add a bit to indicate that the
15481 function is a coroutine component.
15482 * internal-fn.c (expand_CO_FRAME): New.
15483 (expand_CO_YIELD): New.
15484 (expand_CO_SUSPN): New.
15485 (expand_CO_ACTOR): New.
15486 * internal-fn.def (CO_ACTOR): New.
15490 * passes.def: Add pass_coroutine_lower_builtins,
15491 pass_coroutine_early_expand_ifns.
15492 * tree-pass.h (make_pass_coroutine_lower_builtins): New.
15493 (make_pass_coroutine_early_expand_ifns): New.
15494 * doc/invoke.texi: Document the fcoroutines command line
15497 2020-01-18 Jakub Jelinek <jakub@redhat.com>
15499 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable.
15502 * config/arm/arm.c (clear_operation_p): Don't use REGNO until
15503 after checking the argument is a REG. Don't use REGNO (reg)
15504 again to set last_regno, reuse regno variable instead.
15506 2020-01-17 David Malcolm <dmalcolm@redhat.com>
15508 * doc/analyzer.texi (Limitations): Add note about NaN.
15510 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15511 Sudakshina Das <sudi.das@arm.com>
15513 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
15514 and valid immediate.
15515 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
15516 (lshrdi3): Generate thumb2_lsrl for valid immediates.
15517 * config/arm/constraints.md (Pg): New.
15518 * config/arm/predicates.md (long_shift_imm): New.
15519 (arm_reg_or_long_shift_imm): Likewise.
15520 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
15521 (thumb2_lsll): Likewise.
15522 (thumb2_lsrl): New.
15524 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15525 Sudakshina Das <sudi.das@arm.com>
15527 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
15528 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
15529 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
15530 register pairs for doubleword quantities for ARMv8.1M-Mainline.
15531 * config/arm/thumb2.md (thumb2_asrl): New.
15532 (thumb2_lsll): Likewise.
15534 2020-01-17 Jakub Jelinek <jakub@redhat.com>
15536 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
15539 2020-01-17 Alexander Monakov <amonakov@ispras.ru>
15541 * gdbinit.in (help-gcc-hooks): New command.
15542 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
15543 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
15546 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15548 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the
15549 correct target macro.
15551 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15553 * config/aarch64/aarch64-protos.h
15554 (aarch64_sve_ld1ro_operand_p): New.
15555 * config/aarch64/aarch64-sve-builtins-base.cc
15556 (class load_replicate): New.
15557 (class svld1ro_impl): New.
15558 (class svld1rq_impl): Change to inherit from load_replicate.
15559 (svld1ro): New sve intrinsic function base.
15560 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
15561 New DEF_SVE_FUNCTION.
15562 * config/aarch64/aarch64-sve-builtins-base.h
15563 (svld1ro): New decl.
15564 * config/aarch64/aarch64-sve-builtins.cc
15565 (function_expander::add_mem_operand): Modify assert to allow
15567 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
15569 * config/aarch64/aarch64.c
15570 (aarch64_sve_ld1rq_operand_p): Implement in terms of ...
15571 (aarch64_sve_ld1rq_ld1ro_operand_p): This.
15572 (aarch64_sve_ld1ro_operand_p): New.
15573 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
15574 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
15575 * config/aarch64/predicates.md
15576 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New.
15578 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15580 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
15581 Introduce this ACLE specified predefined macro.
15582 * config/aarch64/aarch64-option-extensions.def (f64mm): New.
15583 (fp): Disabling this disables f64mm.
15584 (simd): Disabling this disables f64mm.
15585 (fp16): Disabling this disables f64mm.
15586 (sve): Disabling this disables f64mm.
15587 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
15588 (AARCH64_ISA_F64MM): New.
15589 (TARGET_F64MM): New.
15590 * doc/invoke.texi (f64mm): Document new option.
15592 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
15594 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
15595 (neoversen1_tunings): Likewise.
15597 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
15600 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
15601 Add assert to ensure prolog has been emitted.
15602 (aarch64_split_atomic_op): Likewise.
15603 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
15604 Use epilogue_completed rather than reload_completed.
15605 (aarch64_atomic_exchange<mode>): Likewise.
15606 (aarch64_atomic_<atomic_optab><mode>): Likewise.
15607 (atomic_nand<mode>): Likewise.
15608 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
15609 (atomic_fetch_nand<mode>): Likewise.
15610 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
15611 (atomic_nand_fetch<mode>): Likewise.
15613 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
15616 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
15618 (REVERSE_CONDITION): Delete.
15619 * config/aarch64/iterators.md (CC_ONLY): New mode iterator.
15620 (CCFP_CCFPE): Likewise.
15621 (e): New mode attribute.
15622 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
15623 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
15624 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
15625 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
15626 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
15627 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
15628 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
15629 name of generator from gen_ccmpdi to gen_ccmpccdi.
15630 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse
15631 the previous comparison but aren't able to, use the new ccmp_rev
15634 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
15636 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
15637 than testing directly for INTEGER_CST.
15638 (gimplify_target_expr, gimplify_omp_depend): Likewise.
15640 2020-01-17 Jakub Jelinek <jakub@redhat.com>
15642 PR tree-optimization/93292
15643 * tree-vect-stmts.c (vectorizable_comparison): Punt also if
15644 get_vectype_for_scalar_type returns NULL.
15646 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
15648 * params.opt (-param=max-predicted-iterations): Increase range from 0.
15649 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.
15651 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
15653 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
15655 * params.opt: (max-predicted-iterations): Set bounds.
15656 * predict.c (real_almost_one, real_br_prob_base,
15657 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
15658 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic
15659 probabilities; do not truncate to reg_br_prob_bases.
15660 (estimate_loops_at_level): Pass max_cyclic_prob.
15661 (estimate_loops): Compute max_cyclic_prob.
15662 (estimate_bb_frequencies): Do not initialize real_*; update calculation
15664 * profile-count.c (profile_probability::to_sreal): New.
15665 * profile-count.h (class sreal): Move up in file.
15666 (profile_probability::to_sreal): Declare.
15668 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15671 (arm_invalid_conversion): New function for target hook.
15672 (arm_invalid_unary_op): New function for target hook.
15673 (arm_invalid_binary_op): New function for target hook.
15675 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15677 * config.gcc: Add arm_bf16.h.
15678 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
15679 (arm_simd_builtin_std_type): Add BFmode.
15680 (arm_init_simd_builtin_types): Define element types for vector types.
15681 (arm_init_bf16_types): New function.
15682 (arm_init_builtins): Add arm_init_bf16_types function call.
15683 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
15684 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
15685 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode.
15686 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
15687 (arm_vector_mode_supported_p): Add V4BF, V8BF.
15688 (arm_mangle_type): Add __bf16.
15689 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
15690 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
15691 arm_bf16_ptr_type_node.
15692 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
15693 define_split between ARM registers.
15694 * config/arm/arm_bf16.h: New file.
15695 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
15696 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
15697 (VQXMOV): Add V8BF.
15698 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
15699 * config/arm/vfp.md: Add BFmode to movhf patterns.
15701 2020-01-16 Mihail Ionescu <mihail.ionescu@arm.com>
15702 Andre Vieira <andre.simoesdiasvieira@arm.com>
15704 * config/arm/arm-cpus.in (mve, mve_float): New features.
15705 (dsp, mve, mve.fp): New options.
15706 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
15707 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
15708 * doc/invoke.texi: Document the armv8.1-m mve and dps options.
15710 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15711 Thomas Preud'homme <thomas.preudhomme@arm.com>
15713 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
15715 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
15716 error for using -mcmse when targeting Armv8.1-M Mainline.
15718 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15719 Thomas Preud'homme <thomas.preudhomme@arm.com>
15721 * config/arm/arm.md (nonsecure_call_internal): Do not force memory
15722 address in r4 when targeting Armv8.1-M Mainline.
15723 (nonsecure_call_value_internal): Likewise.
15724 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
15725 a register match_operand again. Emit BLXNS when targeting
15726 Armv8.1-M Mainline.
15727 (nonsecure_call_value_reg_thumb2): Likewise.
15729 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15730 Thomas Preud'homme <thomas.preudhomme@arm.com>
15732 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
15733 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
15734 variable as true when floating-point ABI is not hard. Replace
15735 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
15736 Generate VLSTM and VLLDM instruction respectively before and
15737 after a function call to cmse_nonsecure_call function.
15738 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
15739 (VUNSPEC_VLLDM): Likewise.
15740 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
15741 (lazy_load_multiple_insn): Likewise.
15743 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15744 Thomas Preud'homme <thomas.preudhomme@arm.com>
15746 * config/arm/arm.c (vfp_emit_fstmd): Declare early.
15747 (arm_emit_vfp_multi_reg_pop): Likewise.
15748 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
15749 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and
15750 restore callee-saved VFP registers.
15752 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15753 Thomas Preud'homme <thomas.preudhomme@arm.com>
15755 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
15756 (cmse_nonsecure_call_clear_caller_saved): Rename into ...
15757 (cmse_nonsecure_call_inline_register_clear): This. Save and clear
15758 callee-saved GPRs as well as clear ip register before doing a nonsecure
15759 call then restore callee-saved GPRs after it when targeting
15760 Armv8.1-M Mainline.
15761 (arm_reorg): Adapt to function rename.
15763 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15764 Thomas Preud'homme <thomas.preudhomme@arm.com>
15766 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
15767 * config/arm/arm.c (clear_operation_p): Extend to be able to check a
15768 clear_vfp_multiple pattern based on a new vfp parameter.
15769 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
15770 targeting Armv8.1-M Mainline.
15771 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers
15772 unconditionally when targeting Armv8.1-M Mainline architecture. Check
15773 whether VFP registers are available before looking call_used_regs for a
15775 * config/arm/predicates.md (clear_multiple_operation): Adapt to change
15776 of prototype of clear_operation_p.
15777 (clear_vfp_multiple_operation): New predicate.
15778 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
15779 * config/arm/vfp.md (clear_vfp_multiple): New define_insn.
15781 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15782 Thomas Preud'homme <thomas.preudhomme@arm.com>
15784 * config/arm/arm-protos.h (clear_operation_p): Declare.
15785 * config/arm/arm.c (clear_operation_p): New function.
15786 (cmse_clear_registers): Generate clear_multiple instruction pattern if
15787 targeting Armv8.1-M Mainline or successor.
15788 (output_return_instruction): Only output APSR register clearing if
15789 Armv8.1-M Mainline instructions not available.
15790 (thumb_exit): Likewise.
15791 * config/arm/predicates.md (clear_multiple_operation): New predicate.
15792 * config/arm/thumb2.md (clear_apsr): New define_insn.
15793 (clear_multiple): Likewise.
15794 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.
15796 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15797 Thomas Preud'homme <thomas.preudhomme@arm.com>
15799 * config/arm/arm.c (fp_sysreg_names): Declare and define.
15800 (use_return_insn): Also return false for Armv8.1-M Mainline.
15801 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M
15802 Mainline instructions are available.
15803 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS
15804 when targeting Armv8.1-M Mainline Security Extensions.
15805 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
15806 Mainline entry function.
15807 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
15808 targeting Armv8.1-M Mainline or successor.
15809 (arm_expand_epilogue): Fix indentation of caller-saved register
15810 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline
15812 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
15813 (FP_SYSREGS): Likewise.
15814 (enum vfp_sysregs_encoding): Define enum.
15815 (fp_sysreg_names): Declare.
15816 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
15817 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
15818 (pop_fpsysreg_insn): Likewise.
15820 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15821 Thomas Preud'homme <thomas.preudhomme@arm.com>
15823 * config/arm/arm-cpus.in (armv8_1m_main): New feature.
15824 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
15825 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
15826 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
15827 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
15828 (ARMv8_1m_main): New feature group.
15829 (armv8.1-m.main): New architecture.
15830 * config/arm/arm-tables.opt: Regenerate.
15831 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
15832 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
15833 (arm_options_perform_arch_sanity_checks): Error out when targeting
15834 Armv8.1-M Mainline Security Extensions.
15835 * config/arm/arm.h (arm_arch8_1m_main): Declare.
15837 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15839 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
15840 aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
15841 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
15842 aarch64_bfdot_laneq): New.
15843 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
15844 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
15845 vbfdotq_laneq_f32): New.
15846 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
15847 VBFMLA_W, VBF): New.
15848 (isquadop): Add V4BF, V8BF.
15850 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15852 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
15853 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
15854 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
15855 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
15856 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
15857 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
15858 usdot_laneq, sudot_lane,sudot_laneq): New.
15859 * config/aarch64/aarch64-simd.md (aarch64_usdot): New.
15860 (aarch64_<sur>dot_lane): New.
15861 * config/aarch64/arm_neon.h (vusdot_s32): New.
15862 (vusdotq_s32): New.
15863 (vusdot_lane_s32): New.
15864 (vsudot_lane_s32): New.
15865 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
15866 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.
15868 2020-01-16 Martin Liska <mliska@suse.cz>
15870 * value-prof.c (dump_histogram_value): Fix
15871 obvious spacing issue.
15873 2020-01-16 Andrew Pinski <apinski@marvell.com>
15875 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
15876 !storage_order_barrier_p.
15878 2020-01-16 Andrew Pinski <apinski@marvell.com>
15880 * sched-int.h (_dep): Add unused bit-field field for the padding.
15881 * sched-deps.c (init_dep_1): Init unused field.
15883 2020-01-16 Andrew Pinski <apinski@marvell.com>
15885 * optabs.h (create_expand_operand): Initialize target field also.
15887 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
15889 PR tree-optimization/92429
15890 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
15891 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
15893 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
15896 2020-01-16 Richard Sandiford <richard.sandiford@arm.com>
15898 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
15899 aarch64_sve_int_mode to each mode.
15901 2020-01-15 David Malcolm <dmalcolm@redhat.com>
15903 * doc/analyzer.texi (Overview): Add note about
15904 -fdump-ipa-analyzer.
15906 2020-01-15 Wilco Dijkstra <wdijkstr@arm.com>
15908 PR tree-optimization/93231
15909 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
15910 input_type is unsigned. Use tree_to_shwi for shift constant.
15911 Check CST_STRING element size is CHAR_TYPE_SIZE bits.
15912 (simplify_count_trailing_zeroes): Add test to handle known non-zero
15913 inputs more efficiently.
15915 2020-01-15 Uroš Bizjak <ubizjak@gmail.com>
15917 * config/i386/i386.md (*movsf_internal): Do not require
15918 SSE2 ISA for alternatives 14 and 15.
15920 2020-01-15 Richard Biener <rguenther@suse.de>
15922 PR middle-end/93273
15923 * tree-eh.c (sink_clobbers): If we already visited the destination
15924 block do not defer insertion.
15925 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for
15926 the purpose of defered insertion.
15928 2020-01-15 Jakub Jelinek <jakub@redhat.com>
15930 * BASE-VER: Bump to 10.0.1.
15932 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
15934 PR tree-optimization/93247
15935 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access
15936 type of the stmt that we're going to vectorize.
15938 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
15940 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a
15941 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent
15944 2020-01-15 Martin Liska <mliska@suse.cz>
15946 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow
15947 2 calls of streamer_read_hwi in a function call.
15949 2020-01-15 Richard Biener <rguenther@suse.de>
15951 * alias.c (record_alias_subset): Avoid redundant work when
15952 subset is already recorded.
15954 2020-01-14 David Malcolm <dmalcolm@redhat.com>
15956 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of
15957 the analyzer options provide CWE identifiers.
15959 2020-01-14 David Malcolm <dmalcolm@redhat.com>
15961 * tree-diagnostic-path.cc (path_summary::event_range::print):
15962 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers
15963 using get_pure_location.
15965 2020-01-15 Jakub Jelinek <jakub@redhat.com>
15967 PR tree-optimization/93262
15968 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins,
15969 perform head trimming only if the last argument is constant,
15970 either all ones, or larger or equal to head trim, in the latter
15971 case decrease the last argument by head_trim.
15973 PR tree-optimization/93249
15974 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h.
15975 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to
15976 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't
15977 perform head trim unless we can prove there are no '\0' chars
15978 from the source among the first head_trim chars.
15980 2020-01-14 David Malcolm <dmalcolm@redhat.com>
15982 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o.
15984 2020-01-15 Jakub Jelinek <jakub@redhat.com>
15987 * config/i386/sse.md
15988 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1,
15989 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1,
15990 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1,
15991 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use
15992 just a single alternative instead of two, make operands 1 and 2
15995 2020-01-14 Jan Hubicka <hubicka@ucw.cz>
15998 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and
16001 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16003 * Makefile.in (lang_opt_files): Add analyzer.opt.
16004 (ANALYZER_OBJS): New.
16005 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o,
16006 tristate.o and ANALYZER_OBJS.
16007 (TEXI_GCCINT_FILES): Add analyzer.texi.
16008 * common.opt (-fanalyzer): New driver option.
16009 * config.in: Regenerate.
16010 * configure: Regenerate.
16011 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option.
16012 (gccdepdir): Also create depdir for "analyzer" subdir.
16013 * digraph.cc: New file.
16014 * digraph.h: New file.
16015 * doc/analyzer.texi: New file.
16016 * doc/gccint.texi ("Static Analyzer") New menu item.
16017 (analyzer.texi): Include it.
16018 * doc/invoke.texi ("Static Analyzer Options"): New list and new section.
16019 ("Warning Options"): Add static analysis warnings to the list.
16020 (-Wno-analyzer-double-fclose): New option.
16021 (-Wno-analyzer-double-free): New option.
16022 (-Wno-analyzer-exposure-through-output-file): New option.
16023 (-Wno-analyzer-file-leak): New option.
16024 (-Wno-analyzer-free-of-non-heap): New option.
16025 (-Wno-analyzer-malloc-leak): New option.
16026 (-Wno-analyzer-possible-null-argument): New option.
16027 (-Wno-analyzer-possible-null-dereference): New option.
16028 (-Wno-analyzer-null-argument): New option.
16029 (-Wno-analyzer-null-dereference): New option.
16030 (-Wno-analyzer-stale-setjmp-buffer): New option.
16031 (-Wno-analyzer-tainted-array-index): New option.
16032 (-Wno-analyzer-use-after-free): New option.
16033 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option.
16034 (-Wno-analyzer-use-of-uninitialized-value): New option.
16035 (-Wanalyzer-too-complex): New option.
16036 (-fanalyzer-call-summaries): New warning.
16037 (-fanalyzer-checker=): New warning.
16038 (-fanalyzer-fine-grained): New warning.
16039 (-fno-analyzer-state-merge): New warning.
16040 (-fno-analyzer-state-purge): New warning.
16041 (-fanalyzer-transitivity): New warning.
16042 (-fanalyzer-verbose-edges): New warning.
16043 (-fanalyzer-verbose-state-changes): New warning.
16044 (-fanalyzer-verbosity=): New warning.
16045 (-fdump-analyzer): New warning.
16046 (-fdump-analyzer-callgraph): New warning.
16047 (-fdump-analyzer-exploded-graph): New warning.
16048 (-fdump-analyzer-exploded-nodes): New warning.
16049 (-fdump-analyzer-exploded-nodes-2): New warning.
16050 (-fdump-analyzer-exploded-nodes-3): New warning.
16051 (-fdump-analyzer-supergraph): New warning.
16052 * doc/sourcebuild.texi (dg-require-dot): New.
16053 (dg-check-dot): New.
16054 * gdbinit.in (break-on-saved-diagnostic): New command.
16055 * graphviz.cc: New file.
16056 * graphviz.h: New file.
16057 * ordered-hash-map-tests.cc: New file.
16058 * ordered-hash-map.h: New file.
16059 * passes.def (pass_analyzer): Add before
16060 pass_ipa_whole_program_visibility.
16061 * selftest-run-tests.c (selftest::run_tests): Call
16062 selftest::ordered_hash_map_tests_cc_tests.
16063 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New
16065 * shortest-paths.h: New file.
16066 * timevar.def (TV_ANALYZER): New timevar.
16067 (TV_ANALYZER_SUPERGRAPH): Likewise.
16068 (TV_ANALYZER_STATE_PURGE): Likewise.
16069 (TV_ANALYZER_PLAN): Likewise.
16070 (TV_ANALYZER_SCC): Likewise.
16071 (TV_ANALYZER_WORKLIST): Likewise.
16072 (TV_ANALYZER_DUMP): Likewise.
16073 (TV_ANALYZER_DIAGNOSTICS): Likewise.
16074 (TV_ANALYZER_SHORTEST_PATHS): Likewise.
16075 * tree-pass.h (make_pass_analyzer): New decl.
16076 * tristate.cc: New file.
16077 * tristate.h: New file.
16079 2020-01-14 Uroš Bizjak <ubizjak@gmail.com>
16082 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for
16083 alternatives 9 and 10.
16085 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16087 * attribs.c (excl_hash_traits::empty_zero_p): New static constant.
16088 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise.
16089 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise.
16090 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
16091 (selftest::hash_map_tests_c_tests): Call it.
16092 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p):
16093 New static constant, using the value of = H::empty_zero_p.
16094 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value
16095 from default_hash_traits <Value>.
16096 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value
16098 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise.
16099 * hash-table.h (hash_table::alloc_entries): Guard the loop of
16100 calls to mark_empty with !Descriptor::empty_zero_p.
16101 (hash_table::empty_slow): Conditionalize the memset call with a
16102 check that Descriptor::empty_zero_p; otherwise, loop through the
16103 entries calling mark_empty on them.
16104 * hash-traits.h (int_hash::empty_zero_p): New static constant.
16105 (pointer_hash::empty_zero_p): Likewise.
16106 (pair_hash::empty_zero_p): Likewise.
16107 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p):
16109 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise.
16110 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise.
16111 * profile.c (location_triplet_hash::empty_zero_p): Likewise.
16112 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise.
16113 (sanopt_tree_couple_hash::empty_zero_p): Likewise.
16114 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise.
16115 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise.
16116 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise.
16117 * tree-vectorizer.h
16118 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p):
16121 2020-01-14 Kewen Lin <linkw@gcc.gnu.org>
16123 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return,
16124 fix typo on return value.
16126 2020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
16129 * cgraph.c (symbol_table::create_edge): Init speculative_id and
16131 (cgraph_edge::make_speculative): Add param for setting speculative_id
16133 (cgraph_edge::speculative_call_info): Update comments and find reference
16134 by speculative_id for multiple indirect targets.
16135 (cgraph_edge::resolve_speculation): Decrease the speculations
16136 for indirect edge, drop it's speculative if not direct target
16137 left. Update comments.
16138 (cgraph_edge::redirect_call_stmt_to_callee): Likewise.
16139 (cgraph_node::dump): Print num_speculative_call_targets.
16140 (cgraph_node::verify_node): Don't report error if speculative
16141 edge not include statement.
16142 (cgraph_edge::num_speculative_call_targets_p): New function.
16143 * cgraph.h (int common_target_id): Remove.
16144 (int common_target_probability): Remove.
16145 (num_speculative_call_targets): New variable.
16146 (make_speculative): Add param for setting speculative_id.
16147 (cgraph_edge::num_speculative_call_targets_p): New declare.
16148 (target_prob): New variable.
16149 (speculative_id): New variable.
16150 * ipa-fnsummary.c (analyze_function_body): Create and duplicate
16151 call summaries for multiple speculative call targets.
16152 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id.
16153 * ipa-profile.c (struct speculative_call_target): New struct.
16154 (class speculative_call_summary): New class.
16155 (class speculative_call_summaries): New class.
16156 (call_sums): New variable.
16157 (ipa_profile_generate_summary): Generate indirect multiple targets summaries.
16158 (ipa_profile_write_edge_summary): New function.
16159 (ipa_profile_write_summary): Stream out indirect multiple targets summaries.
16160 (ipa_profile_dump_all_summaries): New function.
16161 (ipa_profile_read_edge_summary): New function.
16162 (ipa_profile_read_summary_section): New function.
16163 (ipa_profile_read_summary): Stream in indirect multiple targets summaries.
16164 (ipa_profile): Generate num_speculative_call_targets from
16166 * ipa-ref.h (speculative_id): New variable.
16167 * ipa-utils.c (ipa_merge_profiles): Update with target_prob.
16168 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and
16169 common_target_probability. Stream out speculative_id and
16170 num_speculative_call_targets.
16171 (input_edge): Likewise.
16172 * predict.c (dump_prediction): Remove edges count assert to be
16174 * symtab.c (symtab_node::create_reference): Init speculative_id.
16175 (symtab_node::clone_references): Clone speculative_id.
16176 (symtab_node::clone_referring): Clone speculative_id.
16177 (symtab_node::clone_reference): Clone speculative_id.
16178 (symtab_node::clear_stmts_in_references): Clear speculative_id.
16179 * tree-inline.c (copy_bb): Duplicate all the speculative edges
16180 if indirect call contains multiple speculative targets.
16181 * value-prof.h (check_ic_target): Remove.
16182 * value-prof.c (gimple_value_profile_transformations):
16183 Use void function gimple_ic_transform.
16184 * value-prof.c (gimple_ic_transform): Handle topn case.
16185 Fix comment typos. Change it to a void function.
16187 2020-01-13 Andrew Pinski <apinski@marvell.com>
16189 * config/aarch64/aarch64-cores.def (octeontx2): New define.
16190 (octeontx2t98): New define.
16191 (octeontx2t96): New define.
16192 (octeontx2t93): New define.
16193 (octeontx2f95): New define.
16194 (octeontx2f95n): New define.
16195 (octeontx2f95mm): New define.
16196 * config/aarch64/aarch64-tune.md: Regenerate.
16197 * doc/invoke.texi (-mcpu=): Document the new cpu types.
16199 2020-01-13 Jason Merrill <jason@redhat.com>
16201 PR c++/33799 - destroy return value if local cleanup throws.
16202 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR.
16204 2020-01-13 Martin Liska <mliska@suse.cz>
16206 * ipa-cp.c (get_max_overall_size): Use newly
16207 renamed param param_ipa_cp_unit_growth.
16208 * params.opt: Remove legacy param name.
16210 2020-01-13 Martin Sebor <msebor@redhat.com>
16212 PR tree-optimization/93213
16213 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul
16214 stores to be eliminated.
16216 2020-01-13 Martin Liska <mliska@suse.cz>
16218 * opts.c (print_help): Do not print CL_PARAM
16219 and CL_WARNING for CL_OPTIMIZATION.
16221 2020-01-13 Jonathan Wakely <jwakely@redhat.com>
16224 * doc/invoke.texi (Warning Options): Add caveat about some warnings
16225 depending on optimization settings.
16227 2020-01-13 Jakub Jelinek <jakub@redhat.com>
16229 PR tree-optimization/90838
16230 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
16231 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro
16232 argument rather than to initialize temporary for targets that
16233 don't use the mode argument at all. Initialize ctzval to avoid
16236 2020-01-10 Thomas Schwinge <thomas@codesourcery.com>
16238 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition.
16239 * tree-core.h: Document it.
16240 * gimplify.c (gimplify_omp_workshare): Set it.
16241 * omp-low.c (lower_omp_target): Use it.
16242 * tree-pretty-print.c (dump_omp_clause): Print it.
16244 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>:
16245 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'.
16247 2020-01-10 David Malcolm <dmalcolm@redhat.com>
16249 * Makefile.in (OBJS): Add tree-diagnostic-path.o.
16250 * common.opt (fdiagnostics-path-format=): New option.
16251 (diagnostic_path_format): New enum.
16252 (fdiagnostics-show-path-depths): New option.
16253 * coretypes.h (diagnostic_event_id_t): New forward decl.
16254 * diagnostic-color.c (color_dict): Add "path".
16255 * diagnostic-event-id.h: New file.
16256 * diagnostic-format-json.cc (json_from_expanded_location): Make
16258 (json_end_diagnostic): Call context->make_json_for_path if it
16259 exists and the diagnostic has a path.
16260 (diagnostic_output_format_init): Clear context->print_path.
16261 * diagnostic-path.h: New file.
16262 * diagnostic-show-locus.c (colorizer::set_range): Special-case
16263 when printing a run of events in a diagnostic_path so that they
16264 all get the same color.
16265 (layout::m_diagnostic_path_p): New field.
16266 (layout::layout): Initialize it.
16267 (layout::print_any_labels): Don't colorize the label text for an
16268 event in a diagnostic_path.
16269 (gcc_rich_location::add_location_if_nearby): Add
16270 "restrict_to_current_line_spans" and "label" params. Pass the
16271 former to layout.maybe_add_location_range; pass the latter
16272 when calling add_range.
16273 * diagnostic.c: Include "diagnostic-path.h".
16274 (diagnostic_initialize): Initialize context->path_format and
16275 context->show_path_depths.
16276 (diagnostic_show_any_path): New function.
16277 (diagnostic_path::interprocedural_p): New function.
16278 (diagnostic_report_diagnostic): Call diagnostic_show_any_path.
16279 (simple_diagnostic_path::num_events): New function.
16280 (simple_diagnostic_path::get_event): New function.
16281 (simple_diagnostic_path::add_event): New function.
16282 (simple_diagnostic_event::simple_diagnostic_event): New ctor.
16283 (simple_diagnostic_event::~simple_diagnostic_event): New dtor.
16284 (debug): New overload taking a diagnostic_path *.
16285 * diagnostic.def (DK_DIAGNOSTIC_PATH): New.
16286 * diagnostic.h (enum diagnostic_path_format): New enum.
16287 (json::value): New forward decl.
16288 (diagnostic_context::path_format): New field.
16289 (diagnostic_context::show_path_depths): New field.
16290 (diagnostic_context::print_path): New callback field.
16291 (diagnostic_context::make_json_for_path): New callback field.
16292 (diagnostic_show_any_path): New decl.
16293 (json_from_expanded_location): New decl.
16294 * doc/invoke.texi (-fdiagnostics-path-format=): New option.
16295 (-fdiagnostics-show-path-depths): New option.
16296 (-fdiagnostics-color): Add "path" to description of default
16297 GCC_COLORS; describe it.
16298 (-fdiagnostics-format=json): Document how diagnostic paths are
16299 represented in the JSON output format.
16300 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
16301 Add optional params "restrict_to_current_line_spans" and "label".
16302 * opts.c (common_handle_option): Handle
16303 OPT_fdiagnostics_path_format_ and
16304 OPT_fdiagnostics_show_path_depths.
16305 * pretty-print.c: Include "diagnostic-event-id.h".
16306 (pp_format): Implement "%@" format code for printing
16307 diagnostic_event_id_t *.
16308 (selftest::test_pp_format): Add tests for "%@".
16309 * selftest-run-tests.c (selftest::run_tests): Call
16310 selftest::tree_diagnostic_path_cc_tests.
16311 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl.
16312 * toplev.c (general_init): Initialize global_dc->path_format and
16313 global_dc->show_path_depths.
16314 * tree-diagnostic-path.cc: New file.
16315 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make
16316 non-static. Drop "diagnostic" param in favor of storing the
16317 original value of "where" and re-using it.
16318 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of
16319 maybe_unwind_expanded_macro_loc.
16320 (tree_diagnostics_defaults): Initialize context->print_path and
16321 context->make_json_for_path.
16322 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New
16324 (default_tree_make_json_for_path): New decl.
16325 (maybe_unwind_expanded_macro_loc): New decl.
16327 2020-01-10 Jakub Jelinek <jakub@redhat.com>
16329 PR tree-optimization/93210
16330 * fold-const.h (native_encode_initializer,
16331 can_native_interpret_type_p): Declare.
16332 * fold-const.c (native_encode_string): Fix up handling with off != -1,
16334 (native_encode_initializer): New function, moved from dwarf2out.c.
16335 Adjust to native_encode_expr compatible arguments, including dry-run
16336 and partial extraction modes. Don't handle STRING_CST.
16337 (can_native_interpret_type_p): No longer static.
16338 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify
16339 offset / BITS_PER_UNIT fits into int and don't call it if
16340 can_native_interpret_type_p fails. If suboff is NULL and for
16341 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with
16342 native_encode_initializer.
16343 (fold_const_aggregate_ref_1): Formatting fix.
16344 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c.
16345 (tree_add_const_value_attribute): Adjust caller.
16347 PR tree-optimization/90838
16348 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
16349 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of
16350 CTZ_DEFINED_VALUE_AT_ZERO.
16352 2020-01-10 Vladimir Makarov <vmakarov@redhat.com>
16354 PR inline-asm/93027
16355 * lra-constraints.c (match_reload): Permit input operands have the
16356 same mode as output while other input operands have a different
16359 2020-01-10 Wilco Dijkstra <wdijkstr@arm.com>
16361 PR tree-optimization/90838
16362 * tree-ssa-forwprop.c (check_ctz_array): Add new function.
16363 (check_ctz_string): Likewise.
16364 (optimize_count_trailing_zeroes): Likewise.
16365 (simplify_count_trailing_zeroes): Likewise.
16366 (pass_forwprop::execute): Try ctz simplification.
16367 * match.pd: Add matching for ctz idioms.
16369 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16371 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function
16373 (aarch64_invalid_unary_op): New function for target hook.
16374 (aarch64_invalid_binary_op): New function for target hook.
16376 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16378 * config.gcc: Add arm_bf16.h.
16379 * config/aarch64/aarch64-builtins.c
16380 (aarch64_simd_builtin_std_type): Add BFmode.
16381 (aarch64_init_simd_builtin_types): Define element types for vector
16383 (aarch64_init_bf16_types): New function.
16384 (aarch64_general_init_builtins): Add arm_init_bf16_types function call.
16385 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
16387 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
16388 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
16390 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
16391 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
16392 * config/aarch64/aarch64.c
16393 (aarch64_classify_vector_mode): Add support for BF types.
16394 (aarch64_gimplify_va_arg_expr): Add support for BF types.
16395 (aarch64_vq_mode): Add support for BF types.
16396 (aarch64_simd_container_mode): Add support for BF types.
16397 (aarch64_mangle_type): Add support for BF scalar type.
16398 * config/aarch64/aarch64.md: Add BFmode to movhf pattern.
16399 * config/aarch64/arm_bf16.h: New file.
16400 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
16401 * config/aarch64/iterators.md: Add BF types to mode attributes.
16402 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.
16404 2020-01-10 Jason Merrill <jason@redhat.com>
16406 PR c++/93173 - incorrect tree sharing.
16407 * gimplify.c (copy_if_shared): No longer static.
16408 * gimplify.h: Declare it.
16410 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16412 * doc/invoke.texi (-msve-vector-bits=): Document that
16413 -msve-vector-bits=128 now generates VL-specific code for
16414 little-endian targets.
16415 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use
16416 build_vector_type_for_mode to construct the data vector types.
16417 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate
16418 VL-specific code for -msve-vector-bits=128 on little-endian targets.
16419 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes
16420 for 128-bit vectors.
16422 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16424 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask
16427 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16429 * config/aarch64/aarch64-builtins.c
16430 (aarch64_builtin_vectorized_function): Check for specific vector modes,
16431 rather than checking the number of elements and the element mode.
16433 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16435 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use
16436 get_related_vectype_for_scalar_type rather than build_vector_type
16437 to create the index type for a conditional reduction.
16439 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16441 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF
16442 for any type of gather or scatter, including strided accesses.
16444 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16446 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function
16449 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16451 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use
16452 get_dr_vinfo_offset
16453 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init
16454 parameter and its use to reset DR_OFFSET's.
16455 (vect_transform_loop): Remove orig_drs_init argument.
16456 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset
16457 member of dr_vec_info rather than the offset of the associated
16458 data_reference's innermost_loop_behavior.
16459 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference.
16460 (vect_do_peeling): Remove orig_drs_init parameter and its construction.
16461 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with
16462 get_dr_vinfo_offset.
16463 (vectorizable_store): Likewise.
16464 (vectorizable_load): Likewise.
16466 2020-01-10 Richard Biener <rguenther@suse.de>
16468 * gimple-ssa-store-merging
16469 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info.
16471 2020-01-10 Martin Liska <mliska@suse.cz>
16474 * ipa-inline-analysis.c (offline_size): Make proper parenthesis
16475 encapsulation that was there before r280040.
16477 2020-01-10 Richard Biener <rguenther@suse.de>
16479 PR middle-end/93199
16480 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL
16481 sequences to avoid walking them again for secondary opportunities.
16482 (pass_lower_eh_dispatch::execute): Instead actually insert
16485 2020-01-10 Richard Biener <rguenther@suse.de>
16487 PR middle-end/93199
16488 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible.
16489 (cleanup_all_empty_eh): Walk landing pads in reverse order to
16490 avoid quadraticness.
16492 2020-01-10 Martin Jambor <mjambor@suse.cz>
16494 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization.
16495 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it
16496 to get param_ipa_sra_max_replacements.
16497 (param_splitting_across_edge): Pass the caller to
16498 pull_accesses_from_callee.
16500 2020-01-10 Martin Jambor <mjambor@suse.cz>
16502 * params.opt (param_ipcp_unit_growth): Mark as Optimization.
16503 * ipa-cp.c (max_new_size): Removed.
16504 (orig_overall_size): New variable.
16505 (get_max_overall_size): New function.
16506 (estimate_local_effects): Use it. Adjust dump.
16507 (decide_about_value): Likewise.
16508 (ipcp_propagate_stage): Do not calculate max_new_size, just store
16509 orig_overall_size. Adjust dump.
16510 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size.
16512 2020-01-10 Martin Jambor <mjambor@suse.cz>
16514 * params.opt (param_ipa_max_agg_items): Mark as Optimization
16515 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use
16516 instead of param_ipa_max_agg_items.
16517 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from
16518 optimization info for the callee.
16520 2020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com>
16522 * lto-streamer-in.c (input_function): Remove streamed-in inline debug
16523 markers if debug_inline_points is false.
16525 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16527 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
16529 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
16530 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
16531 aarch64-sve-builtins-sve2.h.
16532 (aarch64-sve-builtins-sve2.o): New rule.
16533 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
16534 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
16535 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
16536 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
16537 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
16538 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
16540 * config/aarch64/aarch64-sve.md: Update comments with SVE2
16541 instructions that are handled here.
16542 (@cond_asrd<mode>): Generalize to...
16543 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
16544 (*cond_asrd<mode>_2): Generalize to...
16545 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
16546 (*cond_asrd<mode>_z): Generalize to...
16547 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
16548 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
16549 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
16550 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
16551 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
16553 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
16554 (@aarch64_scatter_stnt<mode>): Likewise.
16555 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
16556 (@aarch64_mul_lane_<mode>): Likewise.
16557 (@aarch64_sve_suqadd<mode>_const): Likewise.
16558 (*<sur>h<addsub><mode>): Generalize to...
16559 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
16561 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
16562 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
16563 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
16564 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
16565 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
16566 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
16567 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
16568 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
16569 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
16570 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
16571 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
16572 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
16573 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
16574 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
16575 (@aarch64_sve_add_mul_lane_<mode>): Likewise.
16576 (@aarch64_sve_sub_mul_lane_<mode>): Likewise.
16577 (@aarch64_sve2_xar<mode>): Likewise.
16578 (@aarch64_sve2_bcax<mode>): Likewise.
16579 (*aarch64_sve2_eor3<mode>): Rename to...
16580 (@aarch64_sve2_eor3<mode>): ...this.
16581 (@aarch64_sve2_bsl<mode>): New expander.
16582 (@aarch64_sve2_nbsl<mode>): Likewise.
16583 (@aarch64_sve2_bsl1n<mode>): Likewise.
16584 (@aarch64_sve2_bsl2n<mode>): Likewise.
16585 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
16586 (*aarch64_sve2_sra<mode>): Add MOVPRFX support.
16587 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
16588 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
16589 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
16590 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
16591 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
16592 (<su>mull<bt><Vwide>): Generalize to...
16593 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
16595 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
16596 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
16597 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
16598 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16599 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
16600 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16601 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
16602 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16603 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
16604 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16605 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
16606 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
16607 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
16608 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
16609 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
16610 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
16611 (<SHRNB:r>shrnb<mode>): Generalize to...
16612 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
16614 (<SHRNT:r>shrnt<mode>): Generalize to...
16615 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
16617 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
16618 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
16619 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
16620 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
16621 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
16622 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
16623 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
16624 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
16625 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
16626 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
16627 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
16628 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
16629 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
16630 (@aarch64_sve2_cvtnt<mode>): Likewise.
16631 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
16632 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
16633 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
16634 (@aarch64_sve2_cvtxnt<mode>): Likewise.
16635 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
16636 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
16637 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
16638 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
16639 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
16640 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
16641 (@aarch64_sve2_pmul<mode>): Likewise.
16642 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
16643 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
16644 (@aarch64_sve2_tbl2<mode>): Likewise.
16645 (@aarch64_sve2_tbx<mode>): Likewise.
16646 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
16647 (@aarch64_sve2_histcnt<mode>): Likewise.
16648 (@aarch64_sve2_histseg<mode>): Likewise.
16649 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
16650 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
16651 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
16652 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
16653 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
16654 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
16655 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
16656 (<su>mulh<r>s<mode>3): Update after above pattern name changes.
16657 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
16658 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
16659 (SVE2_PMULL_PAIR_I): New mode iterators.
16660 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
16661 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
16662 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
16663 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
16664 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
16665 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
16666 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
16667 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
16668 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
16669 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
16670 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
16671 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
16672 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
16673 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
16674 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
16675 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
16676 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
16677 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
16678 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
16679 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
16680 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
16681 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
16682 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
16683 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
16684 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
16685 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
16686 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
16687 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
16688 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
16689 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
16690 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
16692 (VNARROW, Ventype): New mode attributes.
16693 (Vewtype): Handle VNx2DI. Fix typo in comment.
16694 (VDOUBLE): New mode attribute.
16695 (sve_lane_con): Handle VNx8HI.
16696 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
16697 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
16698 (sve_int_op, sve_int_op_rev): Handle the above codes.
16699 (sve_pred_int_rhs2_operand): Likewise.
16700 (MULLBT, SHRNB, SHRNT): Delete.
16701 (SVE_INT_SHIFT_IMM): New int iterator.
16702 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
16703 and UNSPEC_WHILEHS for TARGET_SVE2.
16704 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
16705 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
16706 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
16707 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
16708 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
16709 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
16710 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
16711 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
16712 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
16713 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
16714 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
16715 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
16716 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
16717 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
16718 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
16719 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
16720 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
16721 (optab): Handle the new unspecs.
16722 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
16724 (lr): Handle the new unspecs.
16726 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
16727 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
16728 (sve_int_qsub_op): New int attributes.
16729 (sve_fp_op, rot): Handle the new unspecs.
16730 * config/aarch64/aarch64-sve-builtins.h
16731 (function_resolver::require_matching_pointer_type): Declare.
16732 (function_resolver::resolve_unary): Add an optional boolean argument.
16733 (function_resolver::finish_opt_n_resolution): Add an optional
16734 type_suffix_index argument.
16735 (gimple_folder::redirect_call): Declare.
16736 (gimple_expander::prepare_gather_address_operands): Add an optional
16738 * config/aarch64/aarch64-sve-builtins.cc: Include
16739 aarch64-sve-builtins-sve2.h.
16740 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
16741 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
16742 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
16743 (TYPES_hsd_integer): Use TYPES_hsd_signed.
16744 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
16745 (TYPES_s_unsigned): Likewise.
16746 (TYPES_s_integer): Use TYPES_s_unsigned.
16747 (TYPES_sd_signed, TYPES_sd_unsigned): New macros.
16748 (TYPES_sd_integer): Use them.
16749 (TYPES_d_unsigned): New macro.
16750 (TYPES_d_integer): Use it.
16751 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
16752 (TYPES_cvt_narrow): Likewise.
16753 (DEF_SVE_TYPES_ARRAY): Include the new types macros above.
16754 (preds_mx): New variable.
16755 (function_builder::add_overloaded_function): Allow the new feature
16756 set to be more restrictive than the original one.
16757 (function_resolver::infer_pointer_type): Remove qualifiers from
16758 the pointer type before printing it.
16759 (function_resolver::require_matching_pointer_type): New function.
16760 (function_resolver::resolve_sv_displacement): Handle functions
16761 that don't support 32-bit vector indices or svint32_t vector offsets.
16762 (function_resolver::finish_opt_n_resolution): Take the inferred type
16763 as a separate argument.
16764 (function_resolver::resolve_unary): Optionally treat all forms in
16765 the same way as normal merging functions.
16766 (gimple_folder::redirect_call): New function.
16767 (function_expander::prepare_gather_address_operands): Add an argument
16768 that says whether scaled forms are available. If they aren't,
16769 handle scaling of vector indices and don't add the extension and
16771 (function_expander::map_to_unspecs): If aarch64_sve isn't available,
16772 fall back to using cond_* instead.
16773 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
16774 Split out the member variables into...
16775 (rtx_code_function_base): ...this new base class.
16776 (rtx_code_function_rotated): Inherit rtx_code_function_base.
16777 (unspec_based_function): Split out the member variables into...
16778 (unspec_based_function_base): ...this new base class.
16779 (unspec_based_function_rotated): Inherit unspec_based_function_base.
16780 (unspec_based_function_exact_insn): New class.
16781 (unspec_based_add_function, unspec_based_add_lane_function)
16782 (unspec_based_lane_function, unspec_based_pred_function)
16783 (unspec_based_qadd_function, unspec_based_qadd_lane_function)
16784 (unspec_based_qsub_function, unspec_based_qsub_lane_function)
16785 (unspec_based_sub_function, unspec_based_sub_lane_function): New
16787 (unspec_based_fused_function): New class.
16788 (unspec_based_mla_function, unspec_based_mls_function): New typedefs.
16789 (unspec_based_fused_lane_function): New class.
16790 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
16792 (CODE_FOR_MODE1): New macro.
16793 (fixed_insn_function): New class.
16794 (while_comparison): Likewise.
16795 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
16796 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
16797 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
16798 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
16799 (load_gather_sv_restricted, shift_left_imm_long): Declare.
16800 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
16801 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
16802 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
16803 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
16804 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
16805 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
16806 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
16807 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
16808 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
16809 Also add an initial argument for unary_convert_narrowt, regardless
16810 of the predication type.
16811 (build_32_64): Allow loads and stores to specify MODE_none.
16812 (build_sv_index64, build_sv_uint_offset): New functions.
16813 (long_type_suffix): New function.
16814 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
16815 (binary_imm_long_base, load_gather_sv_base): Likewise.
16816 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
16817 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
16818 (unary_narrowb_base, unary_narrowt_base): Likewise.
16819 (binary_long_lane_def, binary_long_lane): New shape.
16820 (binary_long_opt_n_def, binary_long_opt_n): Likewise.
16821 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
16822 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
16823 (binary_to_uint_def, binary_to_uint): Likewise.
16824 (binary_wide_def, binary_wide): Likewise.
16825 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
16826 (compare_def, compare): Likewise.
16827 (compare_ptr_def, compare_ptr): Likewise.
16828 (load_ext_gather_index_restricted_def,
16829 load_ext_gather_index_restricted): Likewise.
16830 (load_ext_gather_offset_restricted_def,
16831 load_ext_gather_offset_restricted): Likewise.
16832 (load_gather_sv_def): Inherit from load_gather_sv_base.
16833 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
16834 (shift_left_imm_def, shift_left_imm): Likewise.
16835 (shift_left_imm_long_def, shift_left_imm_long): Likewise.
16836 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
16837 (store_scatter_index_restricted_def,
16838 store_scatter_index_restricted): Likewise.
16839 (store_scatter_offset_restricted_def,
16840 store_scatter_offset_restricted): Likewise.
16841 (tbl_tuple_def, tbl_tuple): Likewise.
16842 (ternary_long_lane_def, ternary_long_lane): Likewise.
16843 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
16844 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
16845 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
16846 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
16847 (ternary_qq_rotate_def, ternary_qq_rotate): New shape.
16848 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
16849 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
16850 (ternary_uint_def, ternary_uint): Likewise.
16851 (unary_convert): Fix typo in comment.
16852 (unary_convert_narrowt_def, unary_convert_narrowt): New shape.
16853 (unary_long_def, unary_long): Likewise.
16854 (unary_narrowb_def, unary_narrowb): Likewise.
16855 (unary_narrowt_def, unary_narrowt): Likewise.
16856 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
16857 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
16858 (unary_to_int_def, unary_to_int): Likewise.
16859 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
16860 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
16861 (svasrd_impl): Delete.
16862 (svcadd_impl::expand): Handle integer operations too.
16863 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
16864 new functions to derive the unspec numbers.
16865 (svmla_svmls_lane_impl): Replace with...
16866 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle
16867 integer operations too.
16868 (svwhile_impl): Rename to...
16869 (svwhilelx_impl): ...this and inherit from while_comparison.
16870 (svasrd): Use unspec_based_function.
16871 (svmla_lane): Use svmla_lane_impl.
16872 (svmls_lane): Use svmls_lane_impl.
16873 (svrecpe, svrsqrte): Handle unsigned integer operations too.
16874 (svwhilele, svwhilelt): Use svwhilelx_impl.
16875 * config/aarch64/aarch64-sve-builtins-sve2.h: New file.
16876 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
16877 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
16878 * config/aarch64/aarch64-sve-builtins.def: Include
16879 aarch64-sve-builtins-sve2.def.
16881 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16883 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
16884 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
16885 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
16886 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar
16887 immediates as well as vector ones.
16888 * config/aarch64/predicates.md (aarch64_sve_arith_immediate)
16889 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
16890 (aarch64_sve_qsub_immediate): Update calls accordingly.
16892 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16894 * config/aarch64/aarch64-sve2.md: Add banner comments.
16895 (<su>mulh<r>s<mode>3): Move further up file.
16896 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
16897 (*aarch64_sve2_sra<mode>): Move further down file.
16898 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.
16900 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16902 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW
16903 and UNSPEC_WHILEWR.
16904 (while_optab_cmp): Handle them.
16905 * config/aarch64/aarch64-sve.md
16906 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public
16907 and add a "@" marker.
16908 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it
16909 instead of gen_aarch64_sve2_while_ptest.
16910 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete.
16912 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16914 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to...
16915 (UNSPEC_WHILELE): ...this.
16916 (UNSPEC_WHILE_LO): Rename to...
16917 (UNSPEC_WHILELO): ...this.
16918 (UNSPEC_WHILE_LS): Rename to...
16919 (UNSPEC_WHILELS): ...this.
16920 (UNSPEC_WHILE_LT): Rename to...
16921 (UNSPEC_WHILELT): ...this.
16922 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly.
16923 (cmp_op, while_optab_cmp): Likewise.
16924 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise.
16925 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise.
16926 (svwhilelt): Likewise.
16928 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16930 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete.
16931 (unary_to_uint): Define.
16932 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def)
16933 (unary_count): Rename to...
16934 (unary_to_uint_def, unary_to_uint): ...this.
16935 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly.
16937 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16939 * config/aarch64/aarch64-sve-builtins-functions.h
16940 (code_for_mode_function): New class.
16941 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros.
16942 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl)
16943 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete.
16944 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0.
16945 (svmul_lane, svtmad): Use CODE_FOR_MODE0.
16947 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16949 * config/aarch64/iterators.md (addsub): New code attribute.
16950 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>):
16952 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change
16953 in the asm string and attributes. Fix indentation.
16954 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>):
16956 (@aarch64_sve_<optab><mode>): ...this.
16957 * config/aarch64/aarch64-sve-builtins.h
16958 (function_expander::expand_signed_unpred_op): Delete.
16959 * config/aarch64/aarch64-sve-builtins.cc
16960 (function_expander::expand_signed_unpred_op): Likewise.
16961 (function_expander::map_to_rtx_codes): If the optab isn't defined,
16962 try using code_for_aarch64_sve instead.
16963 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete.
16964 (svqsub_impl): Likewise.
16965 (svqadd, svqsub): Use rtx_code_function instead.
16967 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16969 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete.
16970 (HADDSUB, sur, addsub): Remove them.
16972 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16974 * tree-nrv.c (pass_return_slot::execute): Handle all internal
16975 functions the same way, rather than singling out those that
16976 aren't mapped directly to optabs.
16978 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16980 * target.def (compatible_vector_types_p): New target hook.
16981 * hooks.h (hook_bool_const_tree_const_tree_true): Declare.
16982 * hooks.c (hook_bool_const_tree_const_tree_true): New function.
16983 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook.
16984 * doc/tm.texi: Regenerate.
16985 * gimple-expr.c: Include target.h.
16986 (useless_type_conversion_p): Use targetm.compatible_vector_types_p.
16987 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New
16989 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define.
16990 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred):
16991 Use the original predicate if it already has a suitable type.
16993 2020-01-09 Martin Jambor <mjambor@suse.cz>
16995 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct,
16996 resolve_speculation and redirect_call_stmt_to_callee static. Change
16997 return type of set_call_stmt to cgraph_edge *.
16998 * auto-profile.c (afdo_indirect_call): Adjust call to
16999 redirect_call_stmt_to_callee.
17000 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *,
17001 make the this pointer explicit, adjust self-recursive calls and the
17002 call top make_direct. Return the resulting edge.
17003 (cgraph_edge::remove): Make this pointer explicit.
17004 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove.
17005 (cgraph_edge::make_direct): Likewise, adjust call to
17006 resolve_speculation.
17007 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust
17008 call to set_call_stmt.
17009 (cgraph_update_edges_for_call_stmt_node): Update call to
17010 set_call_stmt and remove.
17011 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
17012 Renamed edge to master_edge. Adjusted calls to set_call_stmt.
17013 (cgraph_node::create_edge_including_clones): Moved "first" definition
17014 of edge to the block where it was used. Adjusted calls to
17016 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to
17017 cgraph_edge::remove.
17018 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to
17019 make_direct and redirect_call_stmt_to_callee.
17020 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to
17021 resolve_speculation and make_direct.
17022 * ipa-inline-transform.c (inline_transform): Adjust call to
17023 redirect_call_stmt_to_callee.
17024 (check_speculations_1):: Adjust call to resolve_speculation.
17025 * ipa-inline.c (resolve_noninline_speculation): Adjust call to
17026 resolve-speculation.
17027 (inline_small_functions): Adjust call to resolve_speculation.
17028 (ipa_inline): Likewise.
17029 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to
17031 * ipa-visibility.c (function_and_variable_visibility): Make iteration
17032 safe with regards to edge removal, adjust calls to
17033 redirect_call_stmt_to_callee.
17034 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct
17035 and redirect_call_stmt_to_callee.
17036 * multiple_target.c (create_dispatcher_calls): Adjust call to
17037 redirect_call_stmt_to_callee
17038 (redirect_to_specific_clone): Likewise.
17039 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph):
17040 Adjust calls to cgraph_edge::remove.
17041 * tree-inline.c (copy_bb): Adjust call to set_call_stmt.
17042 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee.
17043 (expand_call_inline): Adjust call to cgraph_edge::remove.
17045 2020-01-09 Martin Liska <mliska@suse.cz>
17047 * params.opt: Set Optimization for
17048 param_max_speculative_devirt_maydefs.
17050 2020-01-09 Martin Sebor <msebor@redhat.com>
17052 PR middle-end/93200
17054 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type.
17056 2020-01-09 Martin Liska <mliska@suse.cz>
17058 * auto-profile.c (auto_profile): Use opt_for_fn
17060 * ipa-cp.c (ipcp_lattice::add_value): Likewise.
17061 (propagate_vals_across_arith_jfunc): Likewise.
17062 (hint_time_bonus): Likewise.
17063 (incorporate_penalties): Likewise.
17064 (good_cloning_opportunity_p): Likewise.
17065 (perform_estimation_of_a_value): Likewise.
17066 (estimate_local_effects): Likewise.
17067 (ipcp_propagate_stage): Likewise.
17068 * ipa-fnsummary.c (decompose_param_expr): Likewise.
17069 (set_switch_stmt_execution_predicate): Likewise.
17070 (analyze_function_body): Likewise.
17071 * ipa-inline-analysis.c (offline_size): Likewise.
17072 * ipa-inline.c (early_inliner): Likewise.
17073 * ipa-prop.c (ipa_analyze_node): Likewise.
17074 (ipcp_transform_function): Likewise.
17075 * ipa-sra.c (process_scan_results): Likewise.
17076 (ipa_sra_summarize_function): Likewise.
17077 * params.opt: Rename ipcp-unit-growth to
17078 ipa-cp-unit-growth. Add Optimization for various
17079 IPA-related parameters.
17081 2020-01-09 Richard Biener <rguenther@suse.de>
17083 PR middle-end/93054
17084 * gimplify.c (gimplify_expr): Deal with NOP definitions.
17086 2020-01-09 Richard Biener <rguenther@suse.de>
17088 PR tree-optimization/93040
17089 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit.
17091 2020-01-09 Georg-Johann Lay <avr@gjlay.de>
17093 * common/config/avr/avr-common.c (avr_option_optimization_table)
17094 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early.
17096 2020-01-09 Martin Liska <mliska@suse.cz>
17098 * cgraphclones.c (symbol_table::materialize_all_clones):
17099 Use cgraph_node::dump_name.
17101 2020-01-09 Jakub Jelinek <jakub@redhat.com>
17103 PR inline-asm/93202
17104 * config/riscv/riscv.c (riscv_print_operand_reloc): Use
17105 output_operand_lossage instead of gcc_unreachable.
17106 * doc/md.texi (riscv f constraint): Fix typo.
17109 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of
17110 SWI. Use <general_hilo_operand> instead of <general_operand>. Use
17111 CONST_SCALAR_INT_P instead of CONST_INT_P.
17112 (*subv<mode>4_1): Rename to ...
17113 (subv<mode>4_1): ... this.
17114 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
17115 define_insn_and_split patterns.
17116 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
17119 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17121 * vec.c (class selftest::count_dtor): New class.
17122 (selftest::test_auto_delete_vec): New test.
17123 (selftest::vec_c_tests): Call it.
17124 * vec.h (class auto_delete_vec): New class template.
17125 (auto_delete_vec<T>::~auto_delete_vec): New dtor.
17127 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17129 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap.
17131 2020-01-08 Jim Wilson <jimw@sifive.com>
17133 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out
17134 use of TLS_MODEL_LOCAL_EXEC when not pic.
17136 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17138 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix
17141 2020-01-08 Jakub Jelinek <jakub@redhat.com>
17144 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2,
17145 *stack_protect_set_3 peephole2): Also check that the second
17146 insns source is general_operand.
17149 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand
17150 predicate for output operand instead of register_operand.
17151 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with
17152 memory destination and non-memory operands[2].
17154 2020-01-08 Martin Liska <mliska@suse.cz>
17156 * cgraph.c (cgraph_node::dump): Use ::dump_name or
17157 ::dump_asm_name instead of (::name or ::asm_name).
17158 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise.
17159 * cgraphunit.c (walk_polymorphic_call_targets): Likewise.
17160 (analyze_functions): Likewise.
17161 (expand_all_functions): Likewise.
17162 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise.
17163 (propagate_bits_across_jump_function): Likewise.
17164 (dump_profile_updates): Likewise.
17165 (ipcp_store_bits_results): Likewise.
17166 (ipcp_store_vr_results): Likewise.
17167 * ipa-devirt.c (dump_targets): Likewise.
17168 * ipa-fnsummary.c (analyze_function_body): Likewise.
17169 * ipa-hsa.c (check_warn_node_versionable): Likewise.
17170 (process_hsa_functions): Likewise.
17171 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise.
17172 (set_alias_uids): Likewise.
17173 * ipa-inline-transform.c (save_inline_function_body): Likewise.
17174 * ipa-inline.c (recursive_inlining): Likewise.
17175 (inline_to_all_callers_1): Likewise.
17176 (ipa_inline): Likewise.
17177 * ipa-profile.c (ipa_propagate_frequency_1): Likewise.
17178 (ipa_propagate_frequency): Likewise.
17179 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.
17180 (remove_described_reference): Likewise.
17181 * ipa-pure-const.c (worse_state): Likewise.
17182 (check_retval_uses): Likewise.
17183 (analyze_function): Likewise.
17184 (propagate_pure_const): Likewise.
17185 (propagate_nothrow): Likewise.
17186 (dump_malloc_lattice): Likewise.
17187 (propagate_malloc): Likewise.
17188 (pass_local_pure_const::execute): Likewise.
17189 * ipa-visibility.c (optimize_weakref): Likewise.
17190 (function_and_variable_visibility): Likewise.
17191 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise.
17192 (ipa_discover_variable_flags): Likewise.
17193 * lto-streamer-out.c (output_function): Likewise.
17194 (output_constructor): Likewise.
17195 * tree-inline.c (copy_bb): Likewise.
17196 * tree-ssa-structalias.c (ipa_pta_execute): Likewise.
17197 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise.
17199 2020-01-08 Richard Biener <rguenther@suse.de>
17201 PR middle-end/93199
17202 * tree-eh.c (sink_clobbers): Update virtual operands for
17203 the first and last stmt only. Add a dry-run capability.
17204 (pass_lower_eh_dispatch::execute): Perform clobber sinking
17205 after CFG manipulations and in RPO order to catch all
17206 secondary opportunities reliably.
17208 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17211 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
17213 2019-01-08 Richard Biener <rguenther@suse.de>
17215 PR middle-end/93199
17216 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified.
17217 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust
17218 virtual operand, also updating SSA use.
17219 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction):
17220 Update stmt after resetting virtual operand.
17221 (tree_loop_interchange::move_code_to_inner_loop): Likewise.
17222 * gimple-iterator.c (gsi_remove): When not removing the stmt
17223 permanently do not delink immediate uses or mark the stmt modified.
17225 2020-01-08 Martin Liska <mliska@suse.cz>
17227 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name.
17228 (ipa_call_context::estimate_size_and_time): Likewise.
17229 (inline_analyze_function): Likewise.
17231 2020-01-08 Martin Liska <mliska@suse.cz>
17233 * cgraph.c (cgraph_node::dump): Use systematically
17236 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17238 Add -nodevicespecs option for avr.
17241 * config/avr/avr.opt (-nodevicespecs): New driver option.
17242 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue
17243 "-specs=device-specs/..." if that option is not set.
17244 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
17246 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17248 Implement 64-bit double functions for avr.
17251 * config.gcc (tm_defines) [target=avr]: Support --with-libf7,
17252 --with-double-comparison.
17253 * doc/install.texi: Document them.
17254 * config/avr/avr-c.c (avr_cpu_cpp_builtins)
17255 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
17256 <WITH_DOUBLE_COMPARISON>: New built-in defines.
17257 * doc/invoke.texi (AVR Built-in Macros): Document them.
17258 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
17259 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
17260 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
17262 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
17265 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
17266 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
17267 when only building rm-profile multilibs.
17269 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
17272 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
17273 lattice for a value to check.
17274 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
17275 finite propagation in self-recursive scc.
17277 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
17279 * ipa-inline.c (caller_growth_limits): Restore the AND.
17281 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
17283 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
17284 (VEC_ALLREG_ALT): New iterator.
17285 (VEC_ALLREG_INT_MODE): New iterator.
17286 (VCMP_MODE): New iterator.
17287 (VCMP_MODE_INT): New iterator.
17288 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
17289 (vec_cmp<u>v64qidi): New define_expand.
17290 (vec_cmp<mode>di_exec): Use VCMP_MODE.
17291 (vec_cmpu<mode>di_exec): New define_expand.
17292 (vec_cmp<u>v64qidi_exec): New define_expand.
17293 (vec_cmp<mode>di_dup): Use VCMP_MODE.
17294 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
17295 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
17296 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
17297 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
17298 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
17299 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
17300 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
17301 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
17302 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
17304 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
17305 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
17307 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
17309 * config/gcn/constraints.md (DA): Update description and match.
17311 (Db): New constraint.
17312 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
17314 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
17315 Implement 'Db' mixed immediate type.
17316 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
17317 (addcv64si3_dup<exec_vcc>): Delete.
17318 (subcv64si3<exec_vcc>): Rework constraints.
17319 (addv64di3): Rework constraints.
17320 (addv64di3_exec): Rework constraints.
17321 (subv64di3): Rework constraints.
17322 (addv64di3_dup): Delete.
17323 (addv64di3_dup_exec): Delete.
17324 (addv64di3_zext): Rework constraints.
17325 (addv64di3_zext_exec): Rework constraints.
17326 (addv64di3_zext_dup): Rework constraints.
17327 (addv64di3_zext_dup_exec): Rework constraints.
17328 (addv64di3_zext_dup2): Rework constraints.
17329 (addv64di3_zext_dup2_exec): Rework constraints.
17330 (addv64di3_sext_dup2): Rework constraints.
17331 (addv64di3_sext_dup2_exec): Rework constraints.
17333 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
17335 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
17336 existing target checks.
17338 2020-01-07 Richard Biener <rguenther@suse.de>
17340 * doc/install.texi: Bump minimal supported MPC version.
17342 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17344 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
17345 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
17346 * langhooks.c: Include stor-layout.h.
17347 (lhd_simulate_enum_decl): New function.
17348 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
17349 handle_arm_sve_h for the LTO frontend.
17350 (register_vector_type): Cope with null returns from pushdecl.
17352 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17354 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
17355 (aarch64_sve::nvectors_if_data_type): Replace with...
17356 (aarch64_sve::builtin_type_p): ...this.
17357 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
17358 (find_vector_type): Delete.
17359 (add_sve_type_attribute): New function.
17360 (lookup_sve_type_attribute): Likewise.
17361 (register_builtin_types): Add an "SVE type" attribute to each type.
17362 (register_tuple_type): Likewise.
17363 (svbool_type_p, nvectors_if_data_type): Delete.
17364 (mangle_builtin_type): Use lookup_sve_type_attribute.
17365 (builtin_type_p): Likewise. Add an overload that returns the
17366 number of constituent vector and predicate registers.
17367 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
17368 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
17369 instead of aarch64_sve_argument_p.
17370 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
17371 (aarch64_pass_by_reference): Likewise.
17372 (aarch64_function_value_1): Likewise.
17373 (aarch64_return_in_memory): Likewise.
17374 (aarch64_layout_arg): Likewise.
17376 2020-01-07 Jakub Jelinek <jakub@redhat.com>
17378 PR tree-optimization/93156
17379 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
17380 least significant bit is always clear.
17382 PR tree-optimization/93118
17383 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
17384 simplifier with two intermediate conversions.
17386 2020-01-07 Martin Liska <mliska@suse.cz>
17388 * params.opt: Add Optimization for various parameters.
17390 2020-01-07 Martin Liska <mliska@suse.cz>
17393 * doc/extend.texi: Explain cloning for target_clone
17396 2020-01-07 Martin Liska <mliska@suse.cz>
17398 PR tree-optimization/92860
17399 * common.opt: Make in Optimization option
17400 as it is affected by -O0, which is an Optimization
17402 * tree-inline.c (tree_inlinable_function_p):
17403 Use opt_for_fn for warn_inline.
17404 (expand_call_inline): Likewise.
17406 2020-01-07 Martin Liska <mliska@suse.cz>
17408 PR tree-optimization/92860
17409 * common.opt: Make flag_ree as optimization
17412 2020-01-07 Martin Liska <mliska@suse.cz>
17414 PR optimization/92860
17415 * params.opt: Mark param_min_crossjump_insns with Optimization
17418 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
17420 * ipa-inline-analysis.c (estimate_growth): Fix typo.
17421 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
17423 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
17425 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
17426 helper function to return the valid addressing formats for a given
17427 hard register and mode.
17428 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
17430 * config/rs6000/constraints.md (Q constraint): Update
17432 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
17435 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
17436 Use 'Q' for doing vector extract from memory.
17437 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
17439 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
17440 doing vector extract from memory.
17441 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
17442 extract from memory.
17444 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
17445 for the offset being 34-bits when -mcpu=future is used.
17447 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
17449 * config/pa/pa.md: Revert change to use ordered_comparison_operator
17450 instead of cmpib_comparison_operator in cmpib patterns.
17451 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
17452 of cmpib_comparison_operator. Revise comment.
17454 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17456 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
17457 in an IFN_DIV_POW2 node to be equal.
17459 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17461 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
17462 (vect_check_scalar_mask): ...this.
17463 (vectorizable_store, vectorizable_load): Update call accordingly.
17464 (vectorizable_call): Use vect_check_scalar_mask to check the mask
17465 argument in calls to conditional internal functions.
17467 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17469 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
17470 '0' matching inputs.
17471 (subv64di3_exec): Likewise.
17473 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
17475 * config/mips/mips.c (vr4130_align_insns): Fix typo.
17476 * doc/md.texi (movstr): Likewise.
17478 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17480 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
17483 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17485 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
17487 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
17488 to a temporary file and use move-if-change to update the real
17489 file where necessary.
17491 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17493 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
17494 rather than Upa for CPY /M.
17496 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17498 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
17501 2020-01-06 Martin Liska <mliska@suse.cz>
17503 PR tree-optimization/92860
17504 * params.opt: Mark param_max_combine_insns with Optimization
17507 2020-01-05 Jakub Jelinek <jakub@redhat.com>
17510 * config/i386/i386.md (SWIDWI): New mode iterator.
17511 (DWI, dwi): Add TImode variants.
17512 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
17513 <general_hilo_operand> instead of <general_operand>. Use
17514 CONST_SCALAR_INT_P instead of CONST_INT_P.
17515 (*addv<mode>4_1): Rename to ...
17516 (addv<mode>4_1): ... this.
17517 (QWI): New mode attribute.
17518 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
17519 define_insn_and_split patterns.
17520 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
17522 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
17523 <general_hilo_operand> instead of <general_operand>.
17524 (*addcarry<mode>_1): New define_insn.
17525 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
17527 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
17529 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
17530 Use "call" instead of "set".
17532 2020-01-03 Martin Jambor <mjambor@suse.cz>
17535 * ipa-cp.c (print_all_lattices): Skip functions without info.
17537 2020-01-03 Jakub Jelinek <jakub@redhat.com>
17540 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
17541 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
17542 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
17543 for 'e' simd clones.
17546 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
17548 (mprefer-vector-width=): Add Save.
17549 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
17550 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
17551 (ix86_debug_options, ix86_function_specific_print): Adjust
17552 ix86_target_string callers.
17553 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
17554 (ix86_valid_target_attribute_tree): Likewise.
17555 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
17556 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
17557 ix86_target_string caller.
17560 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
17561 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
17562 instead of gen_int_shift_amount + convert_modes.
17564 PR rtl-optimization/93088
17565 * loop-iv.c (find_single_def_src): Punt after looking through
17566 128 reg copies for regs with single definitions. Move definitions
17569 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
17571 * config/arm/arm-c.c (arm_cpu_builtins): Define
17572 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
17573 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
17574 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
17575 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
17576 * config/arm/arm-tables.opt: Regenerated.
17577 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
17578 arm_arch_i8mm and arm_arch_bf16 when enabled.
17579 * config/arm/arm.h (TARGET_I8MM): New macro.
17580 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
17581 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
17582 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
17583 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
17584 (v8_6_a_simd_variants): New.
17585 (v8_*_a_simd_variants): Add i8mm and bf16.
17586 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
17588 2020-01-02 Jakub Jelinek <jakub@redhat.com>
17591 * predict.c (compute_function_frequency): Don't call
17592 warn_function_cold on functions that already have cold attribute.
17594 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
17597 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
17598 COMDAT group function labels in .data.rel.ro.local section.
17599 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
17602 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
17603 comparison_operator in B and S integer comparisons. Likewise, use
17604 ordered_comparison_operator instead of cmpib_comparison_operator in
17606 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
17608 2020-01-01 Jakub Jelinek <jakub@redhat.com>
17610 Update copyright years.
17612 * gcc.c (process_command): Update copyright notice dates.
17613 * gcov-dump.c (print_version): Ditto.
17614 * gcov.c (print_version): Ditto.
17615 * gcov-tool.c (print_version): Ditto.
17616 * gengtype.c (create_file): Ditto.
17617 * doc/cpp.texi: Bump @copying's copyright year.
17618 * doc/cppinternals.texi: Ditto.
17619 * doc/gcc.texi: Ditto.
17620 * doc/gccint.texi: Ditto.
17621 * doc/gcov.texi: Ditto.
17622 * doc/install.texi: Ditto.
17623 * doc/invoke.texi: Ditto.
17625 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
17627 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
17630 2020-01-01 Jakub Jelinek <jakub@redhat.com>
17632 PR tree-optimization/93098
17633 * match.pd (popcount): For shift amounts, use integer_onep
17634 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
17635 tests. Make sure that precision is power of two larger than or equal
17636 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
17637 instead of ULL suffixed constants. Formatting fixes.
17639 Copyright (C) 2020 Free Software Foundation, Inc.
17641 Copying and distribution of this file, with or without modification,
17642 are permitted in any medium without royalty provided the copyright
17643 notice and this notice are preserved.