1 2020-05-21 H.J. Lu <hongjiu.lu@intel.com>
4 * config/i386/i386-builtins.c (processor_features): Move
5 F_AVX512VP2INTERSECT after F_AVX512BF16.
6 (isa_names_table): Likewise.
8 2020-05-21 Martin Liska <mliska@suse.cz>
10 * common/config/aarch64/aarch64-common.c (aarch64_handle_option):
11 Handle OPT_moutline_atomics.
12 * config/aarch64/aarch64.c: Add outline-atomics to
14 * doc/extend.texi: Document the newly added target attribute.
16 2020-05-21 Uroš Bizjak <ubizjak@gmail.com>
20 * config/i386/mmx.md (*mmx_<code>v2sf): Do not mark
21 operands 1 and 2 commutative. Manually swap operands.
22 (*mmx_nabsv2sf2): Ditto.
25 2020-05-18 Uroš Bizjak <ubizjak@gmail.com>
27 * config/i386/i386.md (*<code>tf2_1):
28 Mark operands 1 and 2 commutative.
30 * config/i386/sse.md (*<code><mode>2): Mark operands 1 and 2
31 commutative. Do not swap operands.
32 (*nabs<mode>2): Ditto.
34 2020-05-20 Uroš Bizjak <ubizjak@gmail.com>
37 * config/i386/sse.md (<code>v8qiv8hi2): Use
38 simplify_gen_subreg instead of simplify_subreg.
39 (<code>v8qiv8si2): Ditto.
40 (<code>v4qiv4si2): Ditto.
41 (<code>v4hiv4si2): Ditto.
42 (<code>v8qiv8di2): Ditto.
43 (<code>v4qiv4di2): Ditto.
44 (<code>v2qiv2di2): Ditto.
45 (<code>v4hiv4di2): Ditto.
46 (<code>v2hiv2di2): Ditto.
47 (<code>v2siv2di2): Ditto.
49 2020-05-20 Uroš Bizjak <ubizjak@gmail.com>
52 * config/i386/i386.md (*pushsi2_rex64):
53 Use "e" constraint instead of "i".
55 2020-05-20 Jan Hubicka <hubicka@ucw.cz>
57 * lto-streamer-in.c (lto_input_scc): Add SHARED_SCC parameter.
58 (lto_input_tree_1): Strenghten sanity check.
59 (lto_input_tree): Update call of lto_input_scc.
60 * lto-streamer-out.c: Include ipa-utils.h
61 (create_output_block): Initialize local_trees if merigng is going
63 (destroy_output_block): Destroy local_trees.
64 (DFS): Add max_local_entry.
65 (local_tree_p): New function.
66 (DFS::DFS): Initialize and maintain it.
67 (DFS::DFS_write_tree): Decide on streaming format.
68 (lto_output_tree): Stream inline singleton SCCs
69 * lto-streamer.h (enum LTO_tags): Add LTO_trees.
70 (struct output_block): Add local_trees.
71 (lto_input_scc): Update prototype.
73 2020-05-20 Patrick Palka <ppalka@redhat.com>
76 * hash-table.h (hash_table::find_with_hash): Move up the call to
79 2020-05-20 Martin Liska <mliska@suse.cz>
81 * lto-compress.c (lto_compression_zstd): Fill up
82 num_compressed_il_bytes.
83 (lto_uncompression_zstd): Likewise for num_uncompressed_il_bytes here.
85 2020-05-20 Richard Biener <rguenther@suse.de>
87 PR tree-optimization/95219
88 * tree-vect-loop.c (vectorizable_induction): Reduce
89 group_size before computing the number of required IVs.
91 2020-05-20 Richard Biener <rguenther@suse.de>
94 * tree-inline.c (remap_gimple_stmt): Revert adjusting
95 COND_EXPR and VEC_COND_EXPR for a -fnon-call-exception boundary.
97 2020-05-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
98 Andre Vieira <andre.simoesdiasvieira@arm.com>
101 * config/arm/arm-protos.h (arm_mode_base_reg_class): Function
103 (mve_vector_mem_operand): Likewise.
104 * config/arm/arm.c (thumb2_legitimate_address_p): For MVE target check
105 the load from memory to a core register is legitimate for give mode.
106 (mve_vector_mem_operand): Define function.
107 (arm_print_operand): Modify comment.
108 (arm_mode_base_reg_class): Define.
109 * config/arm/arm.h (MODE_BASE_REG_CLASS): Modify to add check for
110 TARGET_HAVE_MVE and expand to arm_mode_base_reg_class on TRUE.
111 * config/arm/constraints.md (Ux): Likewise.
113 * config/arm/mve.md (mve_mov): Replace constraint Us with Ux and also
114 add support for missing Vector Store Register and Vector Load Register.
115 Add a new alternative to support load from memory to PC (or label) in
117 (mve_vstrbq_<supf><mode>): Modify constraint Us to Ux.
118 (mve_vldrbq_<supf><mode>): Modify constriant Us to Ux, predicate to
119 mve_memory_operand and also modify the MVE instructions to emit.
120 (mve_vldrbq_z_<supf><mode>): Modify constraint Us to Ux.
121 (mve_vldrhq_fv8hf): Modify constriant Us to Ux, predicate to
122 mve_memory_operand and also modify the MVE instructions to emit.
123 (mve_vldrhq_<supf><mode>): Modify constriant Us to Ux, predicate to
124 mve_memory_operand and also modify the MVE instructions to emit.
125 (mve_vldrhq_z_fv8hf): Likewise.
126 (mve_vldrhq_z_<supf><mode>): Likewise.
127 (mve_vldrwq_fv4sf): Likewise.
128 (mve_vldrwq_<supf>v4si): Likewise.
129 (mve_vldrwq_z_fv4sf): Likewise.
130 (mve_vldrwq_z_<supf>v4si): Likewise.
131 (mve_vld1q_f<mode>): Modify constriant Us to Ux.
132 (mve_vld1q_<supf><mode>): Likewise.
133 (mve_vstrhq_fv8hf): Modify constriant Us to Ux, predicate to
135 (mve_vstrhq_p_fv8hf): Modify constriant Us to Ux, predicate to
136 mve_memory_operand and also modify the MVE instructions to emit.
137 (mve_vstrhq_p_<supf><mode>): Likewise.
138 (mve_vstrhq_<supf><mode>): Modify constriant Us to Ux, predicate to
140 (mve_vstrwq_fv4sf): Modify constriant Us to Ux.
141 (mve_vstrwq_p_fv4sf): Modify constriant Us to Ux and also modify the MVE
142 instructions to emit.
143 (mve_vstrwq_p_<supf>v4si): Likewise.
144 (mve_vstrwq_<supf>v4si): Likewise.Modify constriant Us to Ux.
145 * config/arm/predicates.md (mve_memory_operand): Define.
147 2020-05-30 Richard Biener <rguenther@suse.de>
150 * c-fold.c (c_fully_fold_internal): Enhance guard on
153 2020-05-20 Kito Cheng <kito.cheng@sifive.com>
156 * Makefile.in (OBJS): Add adjust-alignment.o.
157 * adjust-alignment.c (pass_data_adjust_alignment): New.
158 (pass_adjust_alignment): New.
159 (pass_adjust_alignment::execute): New.
160 (make_pass_adjust_alignment): New.
161 * tree-pass.h (make_pass_adjust_alignment): New.
162 * passes.def: Add pass_adjust_alignment.
164 2020-05-19 Alex Coplan <alex.coplan@arm.com>
167 * config/aarch64/aarch64.c (aarch64_evpc_rev_local): Don't match
168 identity permutation.
170 2020-05-19 Jozef Lawrynowicz <jozef.l@mittosystems.com>
172 * doc/sourcebuild.texi: Document new short_eq_int, ptr_eq_short,
173 msp430_small, msp430_large and size24plus DejaGNU effective
175 Improve grammar in descriptions for size20plus and size32plus effective
178 2020-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
180 * config/bpf/bpf.c (bpf_compute_frame_layout): Include space for
181 callee saved registers only in xBPF.
182 (bpf_expand_prologue): Save callee saved registers only in xBPF.
183 (bpf_expand_epilogue): Likewise for restoring.
184 * doc/invoke.texi (eBPF Options): Document this is activated by
187 2020-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
189 * config/bpf/bpf.opt (mxbpf): New option.
190 * doc/invoke.texi (Option Summary): Add -mxbpf.
191 (eBPF Options): Document -mxbbpf.
193 2020-05-19 Uroš Bizjak <ubizjak@gmail.com>
196 * config/i386/sse.md (<code>v16qiv16hi2): New expander.
197 (<code>v32qiv32hi2): Ditto.
198 (<code>v8qiv8hi2): Ditto.
199 (<code>v16qiv16si2): Ditto.
200 (<code>v8qiv8si2): Ditto.
201 (<code>v4qiv4si2): Ditto.
202 (<code>v16hiv16si2): Ditto.
203 (<code>v8hiv8si2): Ditto.
204 (<code>v4hiv4si2): Ditto.
205 (<code>v8qiv8di2): Ditto.
206 (<code>v4qiv4di2): Ditto.
207 (<code>v2qiv2di2): Ditto.
208 (<code>v8hiv8di2): Ditto.
209 (<code>v4hiv4di2): Ditto.
210 (<code>v2hiv2di2): Ditto.
211 (<code>v8siv8di2): Ditto.
212 (<code>v4siv4di2): Ditto.
213 (<code>v2siv2di2): Ditto.
215 2020-05-19 Kito Cheng <kito.cheng@sifive.com>
217 * common/config/riscv/riscv-common.c (riscv_implied_info_t): New.
218 (riscv_implied_info): New.
219 (riscv_subset_list): Add handle_implied_ext.
220 (riscv_subset_list::to_string): New parameter version_p to
221 control output format.
222 (riscv_subset_list::handle_implied_ext): New.
223 (riscv_subset_list::parse_std_ext): Call handle_implied_ext.
224 (riscv_arch_str): New parameter version_p to control output format.
225 (riscv_expand_arch): New.
226 * config/riscv/riscv-protos.h (riscv_arch_str): New parameter,
228 * config/riscv/riscv.h (riscv_expand_arch): New,
229 (EXTRA_SPEC_FUNCTIONS): Define.
230 (ASM_SPEC): Transform -march= via riscv_expand_arch.
232 2020-05-19 Kito Cheng <kito.cheng@sifive.com>
234 * riscv-common.c (parse_sv_or_non_std_ext): Rename to
235 parse_multiletter_ext.
236 (parse_multiletter_ext): Add parsing `h` and `z`, drop `sx`,
237 adjust parsing order for 's' and 'x'.
239 2020-05-19 Richard Biener <rguenther@suse.de>
241 * tree-vectorizer.h (_slp_tree::vectype): Add field.
242 (SLP_TREE_VECTYPE): New.
243 * tree-vect-slp.c (vect_create_new_slp_node): Initialize
245 (vect_create_new_slp_node): Likewise.
246 (vect_prologue_cost_for_slp): Move here from tree-vect-stmts.c
248 (vect_slp_analyze_node_operations): Walk nodes children for
250 (vect_get_constant_vectors): Use local scope op variable.
251 * tree-vect-stmts.c (vect_prologue_cost_for_slp_op): Remove here.
252 (vect_model_simple_cost): Adjust.
253 (vect_model_store_cost): Likewise.
254 (vectorizable_store): Likewise.
256 2020-05-18 Martin Sebor <msebor@redhat.com>
259 * tree-object-size.c (decl_init_size): New function.
260 (addr_object_size): Call it.
261 * tree.h (last_field): Declare.
262 (first_field): Add attribute nonnull.
264 2020-05-18 Martin Sebor <msebor@redhat.com>
267 * tree-vrp.c (vrp_prop::check_mem_ref): Remove unreachable code.
268 * tree.c (component_ref_size): Correct the handling or array members
270 Drop a pointless test.
271 Rename a local variable.
273 2020-05-18 Jason Merrill <jason@redhat.com>
275 * aclocal.m4: Add ax_cxx_compile_stdcxx.m4.
276 * configure.ac: Use AX_CXX_COMPILE_STDCXX(11).
278 2020-05-14 Jason Merrill <jason@redhat.com>
280 * doc/install.texi (Prerequisites): Update boostrap compiler
281 requirement to C++11/GCC 4.8.
283 2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
285 PR tree-optimization/94952
286 * gimple-ssa-store-merging.c (pass_store_merging::process_store):
287 Initialize variables bitpos, bitregion_start, and bitregion_end in
288 order to silence warnings about use of uninitialized variables.
290 2020-05-18 Carl Love <cel@us.ibm.com>
293 * config/rs6000/vsx.md (define_expand): Fix instruction generation for
294 first_match_index_<mode>.
295 * testsuite/gcc.target/powerpc/builtins-8-p9-runnable.c (main): Add
296 additional test cases with zero vector elements.
298 2020-05-18 Uroš Bizjak <ubizjak@gmail.com>
301 * config/i386/i386-expand.c (ix86_expand_int_movcc):
302 Avoid reversing a non-trapping comparison to a trapping one.
304 2020-05-18 Alex Coplan <alex.coplan@arm.com>
306 * config/arm/arm.c (output_move_double): Fix codegen when loading into
307 a register pair with an odd base register.
309 2020-05-18 Uroš Bizjak <ubizjak@gmail.com>
311 * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator):
312 Do not emit FLAGS_REG clobber for TFmode.
313 * config/i386/i386.md (*<code>tf2_1): Rewrite as
314 define_insn_and_split. Mark operands 1 and 2 commutative.
316 (absneg SSE splitter): Use MODEF mode iterator instead of SSEMODEF.
317 Do not swap memory operands. Simplify RTX generation.
318 (neg abs SSE splitter): Ditto.
319 * config/i386/sse.md (*<code><mode>2): Mark operands 1 and 2
320 commutative. Do not swap operands. Simplify RTX generation.
321 (*nabs<mode>2): Ditto.
323 2020-05-18 Richard Biener <rguenther@suse.de>
325 * tree-vect-slp.c (vect_slp_bb): Start after labels.
326 (vect_get_constant_vectors): Really place init stmt after scalar defs.
327 * tree-vect-stmts.c (vect_init_vector_1): Insert before
330 2020-05-18 H.J. Lu <hongjiu.lu@intel.com>
332 * config/i386/driver-i386.c (host_detect_local_cpu): Support
333 Intel Airmont, Tremont, Comet Lake, Ice Lake and Tiger Lake
336 2020-05-18 Richard Biener <rguenther@suse.de>
339 * tree-inline.c (remap_gimple_stmt): Split out trapping compares
340 when inlining into a non-call EH function.
342 2020-05-18 Richard Biener <rguenther@suse.de>
344 PR tree-optimization/95172
345 * tree-ssa-loop-im.c (execute_sm): Get flag whether we
346 eventually need the conditional processing.
347 (execute_sm_exit): When processing an orderd sequence
348 avoid doing any conditional processing.
349 (hoist_memory_references): Pass down whether all edges
350 have ordered processing for a ref to execute_sm.
352 2020-05-17 Jeff Law <law@redhat.com>
354 * config/h8300/predicates.md (pc_or_label_operand): New predicate.
355 * config/h8300/jumpcall.md (branch_true, branch_false): Consolidate
356 into a single pattern using pc_or_label_operand.
357 * config/h8300/combiner.md (bit branch patterns): Likewise.
358 * config/h8300/peepholes.md (HImode and SImode branches): Likewise.
360 2020-05-17 H.J. Lu <hongjiu.lu@intel.com>
363 * config/i386/i386-features.c (has_non_address_hard_reg):
365 (pseudo_reg_set): This. Return the SET expression. Ignore
366 pseudo register push.
367 (general_scalar_to_vector_candidate_p): Combine single_set and
368 has_non_address_hard_reg calls to pseudo_reg_set.
369 (timode_scalar_to_vector_candidate_p): Likewise.
370 * config/i386/i386.md (*pushv1ti2): New pattern.
372 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
375 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
377 * tree-vrp.c (operand_less_p): Move to...
378 * vr-values.c (operand_less_p): ...here.
379 * tree-vrp.h (operand_less_p): Remove.
381 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
383 * tree-vrp.c (operand_less_p): Move to...
384 * vr-values.c (operand_less_p): ...here.
385 * tree-vrp.h (operand_less_p): Remove.
387 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
389 * tree-vrp.c (class vrp_insert): Remove prototype for
392 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
394 * tree-vrp.c (class live_names): New.
395 (live_on_edge): Move into live_names.
396 (build_assert_expr_for): Move into vrp_insert.
397 (find_assert_locations_in_bb): Rename from
398 find_assert_locations_1.
399 (process_assert_insertions_for): Move into vrp_insert.
400 (compare_assert_loc): Same.
401 (remove_range_assertions): Same.
402 (dump_asserts_for): Rename to vrp_insert::dump.
403 (debug_asserts_for): Rename to vrp_insert::debug.
404 (dump_all_asserts): Rename to vrp_insert::dump.
405 (debug_all_asserts): Rename to vrp_insert::debug.
407 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
409 * tree-vrp.c (class vrp_prop): Move check_all_array_refs,
410 check_array_ref, check_mem_ref, and search_for_addr_array
412 (class array_bounds_checker): ...here.
413 (class check_array_bounds_dom_walker): Adjust to use
414 array_bounds_checker.
415 (check_all_array_refs): Move into array_bounds_checker and rename
417 (class vrp_folder): Make fold_predicate_in private.
419 2020-05-15 Jeff Law <law@redhat.com>
421 * config/h8300/h8300.md (SFI iterator): New iterator for
423 * config/h8300/peepholes.md (memory comparison): Use mode
424 iterator to consolidate 3 patterns into one.
425 (stack allocation and stack store): Handle SFmode. Handle
428 2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
430 * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_2): Also require
431 RS6000_BTM_POWERPC64.
433 2020-05-15 Uroš Bizjak <ubizjak@gmail.com>
435 * config/i386/i386.md (SWI48DWI): New mode iterator.
436 (*push<mode>2): Allow XMM registers.
437 (*pushdi2_rex64): Ditto.
438 (*pushsi2_rex64): Ditto.
440 (push XMM reg splitter): New splitter
442 (*pushdf) Change "x" operand constraint to "v".
443 (*pushsf_rex64): Ditto.
446 2020-05-15 Richard Biener <rguenther@suse.de>
448 PR tree-optimization/92260
449 * tree-vect-slp.c (vect_get_constant_vectors): Compute
450 the number of vector stmts in a canonical way.
452 2020-05-15 Martin Liska <mliska@suse.cz>
454 * hsa-gen.c (get_symbol_for_decl): Fix misleading indentation
457 2020-05-15 Andrew Stubbs <ams@codesourcery.com>
459 * config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.
461 2020-05-15 Richard Biener <rguenther@suse.de>
463 PR tree-optimization/95133
464 * gimple-ssa-split-paths.c
465 (find_block_to_duplicate_for_splitting_paths): Check for
468 2020-05-15 Christophe Lyon <christophe.lyon@linaro.org>
470 * config/arm/arm.c (reg_needs_saving_p): Add support for interrupt
472 (arm_compute_save_reg0_reg12_mask): Use reg_needs_saving_p.
474 2020-05-15 Tobias Burnus <tobias@codesourcery.com>
477 * gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with
478 OMP_TARGET_EXIT_DATA, use 'release:' unless the associated
481 2020-05-15 Uroš Bizjak <ubizjak@gmail.com>
484 * config/i386/i386.md (isa): Add sse3_noavx.
485 (enabled): Handle sse3_noavx.
487 * config/i386/mmx.md (mmx_haddv2sf3): New expander.
488 (*mmx_haddv2sf3): Rename from mmx_haddv2sf3. Add SSE/AVX
489 alternatives. Match commutative vec_select selector operands.
490 (*mmx_haddv2sf3_low): New insn pattern.
492 (*mmx_hsubv2sf3): Add SSE/AVX alternatives.
493 (*mmx_hsubv2sf3_low): New insn pattern.
495 2020-05-15 Richard Biener <rguenther@suse.de>
497 PR tree-optimization/33315
498 * tree-ssa-sink.c: Include tree-eh.h.
499 (sink_stats): Add commoned member.
500 (sink_common_stores_to_bb): New function implementing store
501 commoning by sinking to the successor.
502 (sink_code_in_bb): Call it, pass down TODO_cleanup_cfg returned.
503 (pass_sink_code::execute): Likewise. Record commoned stores
506 2020-05-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
508 PR rtl-optimization/37451, part of PR target/61837
509 * loop-doloop.c (doloop_simplify_count): New function. Simplify
510 (add -1; zero_ext; add +1) to zero_ext when not wrapping.
511 (doloop_modify): Call doloop_simplify_count.
513 2020-05-14 H.J. Lu <hongjiu.lu@intel.com>
516 * doc/sourcebuild.texi: Document effective target lgccjit.
518 2020-05-14 Andrew Stubbs <ams@codesourcery.com>
520 * config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a
521 define_expand, and rename the original to ...
522 (add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand.
523 (add<mode>3_zext_dup_exec): Likewise, with ...
524 (add<mode>3_vcc_zext_dup_exec): ... this.
525 (add<mode>3_zext_dup2): Likewise, with ...
526 (add<mode>3_zext_dup_exec): ... this.
527 (add<mode>3_zext_dup2_exec): Likewise, with ...
528 (add<mode>3_zext_dup2): ... this.
529 * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch
530 addv64di3_zext* calls to use addv64di3_vcc_zext*.
532 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
535 * config/i386/sse.md (truncv2dfv2df2): New insn pattern.
536 (extendv2sfv2df2): Ditto.
538 2020-05-14 H.J. Lu <hongjiu.lu@intel.com>
540 * configure: Regenerated.
542 2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
544 * config/arm/arm.c (reg_needs_saving_p): New function.
545 (use_return_insn): Use reg_needs_saving_p.
546 (arm_get_vfp_saved_size): Likewise.
547 (arm_compute_frame_layout): Likewise.
548 (arm_save_coproc_regs): Likewise.
549 (thumb1_expand_epilogue): Likewise.
550 (arm_expand_epilogue_apcs_frame): Likewise.
551 (arm_expand_epilogue): Likewise.
553 2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
555 * config/arm/arm.c (thumb1_expand_prologue): Update error message.
557 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
560 * config/i386/sse.md (sse2_cvtpi2pd): Add memory to alternative 1.
562 (floatv2siv2df2): New expander.
563 (floatunsv2siv2df2): New insn pattern.
565 (fix_truncv2dfv2si2): New expander.
566 (fixuns_truncv2dfv2si2): New insn pattern.
568 2020-05-14 Richard Sandiford <richard.sandiford@arm.com>
571 * config/aarch64/aarch64-sve-builtins.cc
572 (handle_arm_sve_vector_bits_attribute): Create a copy of the
573 original type's TYPE_MAIN_VARIANT, then reapply all the differences
574 between the original type and its main variant.
576 2020-05-14 Richard Biener <rguenther@suse.de>
579 * real.c (real_to_decimal_for_mode): Make sure we handle
580 a zero with nonzero exponent.
582 2020-05-14 Jakub Jelinek <jakub@redhat.com>
584 * Makefile.in (GTFILES): Add omp-general.c.
585 * cgraph.h (struct cgraph_node): Add declare_variant_alt and
586 calls_declare_variant_alt members and initialize them in the
588 * ipa.c (symbol_table::remove_unreachable_nodes): Handle direct
589 calls to declare_variant_alt nodes.
590 * lto-cgraph.c (lto_output_node): Write declare_variant_alt
591 and calls_declare_variant_alt.
592 (input_overwrite_node): Read them back.
593 * omp-simd-clone.c (simd_clone_create): Copy calls_declare_variant_alt
595 * tree-inline.c (expand_call_inline): Or in calls_declare_variant_alt
597 (tree_function_versioning): Copy calls_declare_variant_alt bit.
598 * omp-offload.c (execute_omp_device_lower): Call
599 omp_resolve_declare_variant on direct function calls.
600 (pass_omp_device_lower::gate): Also enable for
601 calls_declare_variant_alt functions.
602 * omp-general.c (omp_maybe_offloaded): Return false after inlining.
603 (omp_context_selector_matches): Handle the case when
604 cfun->curr_properties has PROP_gimple_any bit set.
605 (struct omp_declare_variant_entry): New type.
606 (struct omp_declare_variant_base_entry): New type.
607 (struct omp_declare_variant_hasher): New type.
608 (omp_declare_variant_hasher::hash, omp_declare_variant_hasher::equal):
610 (omp_declare_variants): New variable.
611 (struct omp_declare_variant_alt_hasher): New type.
612 (omp_declare_variant_alt_hasher::hash,
613 omp_declare_variant_alt_hasher::equal): New methods.
614 (omp_declare_variant_alt): New variables.
615 (omp_resolve_late_declare_variant): New function.
616 (omp_resolve_declare_variant): Call omp_resolve_late_declare_variant
617 when called late. Create a magic declare_variant_alt fndecl and
618 cgraph node and return that if decision needs to be deferred until
619 after gimplification.
620 * cgraph.c (symbol_table::create_edge): Or in calls_declare_variant_alt
624 * omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member.
625 (ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in
626 entry block if info->after_stmt is NULL, otherwise add after that stmt
627 and update it after adding each stmt.
628 (ipa_simd_modify_function_body): Initialize info.after_stmt.
630 * function.h (struct function): Add has_omp_target bit.
631 * omp-offload.c (omp_discover_declare_target_fn_r): New function,
633 (omp_discover_declare_target_tgt_fn_r): ... this.
634 (omp_discover_declare_target_var_r): Call
635 omp_discover_declare_target_tgt_fn_r instead of
636 omp_discover_declare_target_fn_r.
637 (omp_discover_implicit_declare_target): Also queue functions with
638 has_omp_target bit set, for those walk with
639 omp_discover_declare_target_fn_r, for declare target to functions
640 walk with omp_discover_declare_target_tgt_fn_r.
642 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
645 * config/i386/mmx.md (mmx_fix_truncv2sfv2si2): Rename from mmx_pf2id.
646 Add SSE/AVX alternative. Change operand predicates from
647 nonimmediate_operand to register_mmxmem_operand.
648 Enable instruction pattern for TARGET_MMX_WITH_SSE.
649 (fix_truncv2sfv2si2): New expander.
650 (fixuns_truncv2sfv2si2): New insn pattern.
652 (mmx_floatv2siv2sf2): rename from mmx_floatv2si2.
653 Add SSE/AVX alternative. Change operand predicates from
654 nonimmediate_operand to register_mmxmem_operand.
655 Enable instruction pattern for TARGET_MMX_WITH_SSE.
656 (floatv2siv2sf2): New expander.
657 (floatunsv2siv2sf2): New insn pattern.
659 * config/i386/i386-builtin.def (IX86_BUILTIN_PF2ID):
661 (IX86_BUILTIN_PI2FD): Ditto.
663 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
665 * config/s390/s390.c (s390_emit_stack_probe): Call the probe_stack
667 * config/s390/s390.md ("@probe_stack2<mode>", "probe_stack"): New
670 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
672 * config/s390/s390.c (allocate_stack_space): Add missing updates
673 of last_probe_offset.
675 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
677 * config/s390/s390.md ("allocate_stack"): Call
678 anti_adjust_stack_and_probe_stack_clash when stack clash
679 protection is enabled.
680 * explow.c (anti_adjust_stack_and_probe_stack_clash): Remove
681 prototype. Remove static.
682 * explow.h (anti_adjust_stack_and_probe_stack_clash): Add
685 2020-05-13 Kelvin Nilsen <kelvin@gcc.gnu.org>
687 * config/rs6000/altivec.h (vec_extractl): New #define.
688 (vec_extracth): Likewise.
689 * config/rs6000/altivec.md (UNSPEC_EXTRACTL): New constant.
690 (UNSPEC_EXTRACTR): Likewise.
691 (vextractl<mode>): New expansion.
692 (vextractl<mode>_internal): New insn.
693 (vextractr<mode>): New expansion.
694 (vextractr<mode>_internal): New insn.
695 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vextdubvlx):
696 New built-in function.
697 (__builtin_altivec_vextduhvlx): Likewise.
698 (__builtin_altivec_vextduwvlx): Likewise.
699 (__builtin_altivec_vextddvlx): Likewise.
700 (__builtin_altivec_vextdubvhx): Likewise.
701 (__builtin_altivec_vextduhvhx): Likewise.
702 (__builtin_altivec_vextduwvhx): Likewise.
703 (__builtin_altivec_vextddvhx): Likewise.
704 (__builtin_vec_extractl): New overloaded built-in function.
705 (__builtin_vec_extracth): Likewise.
706 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
707 Define overloaded forms of __builtin_vec_extractl and
708 __builtin_vec_extracth.
709 (builtin_function_type): Add cases to mark arguments of new
710 built-in functions as unsigned.
711 (rs6000_common_init_builtins): Add
712 opaque_ftype_opaque_opaque_opaque_opaque.
713 * config/rs6000/rs6000.md (du_or_d): New mode attribute.
714 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
715 for a Future Architecture): Add description of vec_extractl and
716 vec_extractr built-in functions.
718 2020-05-13 Richard Biener <rguenther@suse.de>
720 * target.def (add_stmt_cost): Add new vectype parameter.
721 * targhooks.c (default_add_stmt_cost): Adjust.
722 * targhooks.h (default_add_stmt_cost): Likewise.
723 * config/aarch64/aarch64.c (aarch64_add_stmt_cost): Take new
725 * config/arm/arm.c (arm_add_stmt_cost): Likewise.
726 * config/i386/i386.c (ix86_add_stmt_cost): Likewise.
727 * config/rs6000/rs6000.c (rs6000_add_stmt_cost): Likewise.
729 * tree-vectorizer.h (stmt_info_for_cost::vectype): Add.
730 (dump_stmt_cost): Add new vectype parameter.
731 (add_stmt_cost): Likewise.
732 (record_stmt_cost): Likewise.
733 (record_stmt_cost): Add overload with old signature.
734 * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost):
736 (vect_get_known_peeling_cost): Likewise.
737 (vect_estimate_min_profitable_iters): Likewise.
738 * tree-vectorizer.c (dump_stmt_cost): Add new vectype parameter.
739 * tree-vect-stmts.c (record_stmt_cost): Likewise.
740 (vect_prologue_cost_for_slp_op): Remove stmt_vec_info parameter
741 and pass down correct vectype and NULL stmt_info.
742 (vect_model_simple_cost): Adjust.
743 (vect_model_store_cost): Likewise.
745 2020-05-13 Richard Biener <rguenther@suse.de>
747 * tree-vectorizer.h (SLP_INSTANCE_GROUP_SIZE): Remove.
748 (_slp_instance::group_size): Likewise.
749 * tree-vect-loop.c (vectorizable_reduction): The group size
750 is the number of lanes in the node.
751 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Likewise.
752 (vect_analyze_slp_instance): Do not set SLP_INSTANCE_GROUP_SIZE,
753 verify it matches the instance trees number of lanes.
754 (vect_slp_analyze_node_operations_1): Use the numer of lanes
755 in the node as group size.
756 (vect_bb_vectorization_profitable_p): Use the instance root
757 number of lanes for the size of life.
758 (vect_schedule_slp_instance): Use the number of lanes as
760 * tree-vect-stmts.c (vectorizable_load): Remove SLP instance
761 parameter. Use the number of lanes of the load for the group
762 size in the gap adjustment code.
763 (vect_analyze_stmt): Adjust.
764 (vect_transform_stmt): Likewise.
766 2020-05-13 Jakub Jelinek <jakub@redhat.com>
769 * cfgrtl.c (purge_dead_edges): Skip over debug and note insns even
770 if the last insn is a note.
772 PR tree-optimization/95060
773 * tree-ssa-math-opts.c (convert_mult_to_fma_1): Fold a NEGATE_EXPR
774 if it is the single use of the FMA internal builtin.
776 2020-05-13 Bin Cheng <bin.cheng@linux.alibaba.com>
778 PR tree-optimization/94969
779 * tree-data-dependence.c (constant_access_functions): Rename to...
780 (invariant_access_functions): ...this. Add parameter. Check for
781 invariant access function, rather than constant.
782 (build_classic_dist_vector): Call above function.
783 * tree-loop-distribution.c (pg_add_dependence_edges): Add comment.
785 2020-05-13 Hongtao Liu <hongtao.liu@intel.com>
788 * doc/extend.texi (x86Operandmodifiers): Document more x86
790 * gcc/config/i386/i386.c: Add comment for operand modifier N and I.
792 2020-05-12 Giuliano Belinassi <giuliano.belinassi@usp.br>
794 * tree-vrp.c (class vrp_insert): New.
795 (insert_range_assertions): Move to class vrp_insert.
796 (dump_all_asserts): Same as above.
797 (dump_asserts_for): Same as above.
798 (live): Same as above.
799 (need_assert_for): Same as above.
800 (live_on_edge): Same as above.
801 (finish_register_edge_assert_for): Same as above.
802 (find_switch_asserts): Same as above.
803 (find_assert_locations): Same as above.
804 (find_assert_locations_1): Same as above.
805 (find_conditional_asserts): Same as above.
806 (process_assert_insertions): Same as above.
807 (register_new_assert_for): Same as above.
808 (vrp_prop): New variable fun.
809 (vrp_initialize): New parameter.
810 (identify_jump_threads): Same as above.
811 (execute_vrp): Same as above.
814 2020-05-12 Keith Packard <keith.packard@sifive.com>
816 * config/riscv/riscv.c (riscv_unique_section): New.
817 (TARGET_ASM_UNIQUE_SECTION): New.
819 2020-05-12 Craig Blackmore <craig.blackmore@embecosm.com>
821 * config.gcc: Add riscv-shorten-memrefs.o to extra_objs for riscv.
822 * config/riscv/riscv-passes.def: New file.
823 * config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare.
824 * config/riscv/riscv-shorten-memrefs.c: New file.
825 * config/riscv/riscv.c (tree-pass.h): New include.
826 (riscv_compressed_reg_p): New Function
827 (riscv_compressed_lw_offset_p): Likewise.
828 (riscv_compressed_lw_address_p): Likewise.
829 (riscv_shorten_lw_offset): Likewise.
830 (riscv_legitimize_address): Attempt to convert base + large_offset
831 to compressible new_base + small_offset.
832 (riscv_address_cost): Make anticipated compressed load/stores
833 cheaper for code size than uncompressed load/stores.
834 (riscv_register_priority): Move compressed register check to
835 riscv_compressed_reg_p.
836 * config/riscv/riscv.h (C_S_BITS): Define.
837 (CSW_MAX_OFFSET): Define.
838 * config/riscv/riscv.opt (mshorten-memefs): New option.
839 * config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule.
840 (PASSES_EXTRA): Add riscv-passes.def.
841 * doc/invoke.texi: Document -mshorten-memrefs.
843 * config/riscv/riscv.c (riscv_new_address_profitable_p): New function.
844 (TARGET_NEW_ADDRESS_PROFITABLE_P): Define.
845 * doc/tm.texi: Regenerate.
846 * doc/tm.texi.in (TARGET_NEW_ADDRESS_PROFITABLE_P): New hook.
847 * sched-deps.c (attempt_change): Use old address if it is cheaper than
849 * target.def (new_address_profitable_p): New hook.
850 * targhooks.c (default_new_address_profitable_p): New function.
851 * targhooks.h (default_new_address_profitable_p): Declare.
853 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
856 * config/i386/mmx.md (copysignv2sf3): New expander.
857 (xorsignv2sf3): Ditto.
858 (signbitv2sf3): Ditto.
860 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
863 * config/i386/mmx.md (fmav2sf4): New insn pattern.
868 2020-05-12 H.J. Lu <hongjiu.lu@intel.com>
870 * Makefile.in (CET_HOST_FLAGS): New.
871 (COMPILER): Add $(CET_HOST_FLAGS).
872 * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and
873 AC_SUBST(CET_HOST_FLAGS). Clear CET_HOST_FLAGS if jit isn't
875 * aclocal.m4: Regenerated.
876 * configure: Likewise.
878 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
881 * config/i386/mmx.md (<code>v2sf2): New insn pattern.
882 (*mmx_<code>v2sf2): New insn_and_split pattern.
883 (*mmx_nabsv2sf2): Ditto.
884 (*mmx_andnotv2sf3): New insn pattern.
885 (*mmx_<code>v2sf3): Ditto.
886 * config/i386/i386.md (absneg_op): New code attribute.
887 * config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode.
888 (ix86_build_signbit_mask): Ditto.
890 2020-05-12 Richard Biener <rguenther@suse.de>
892 * tree-ssa-live.c (remove_unused_locals): Remove dead debug
895 2020-05-12 Jozef Lawrynowicz <jozef.l@mittosystems.com>
897 * config/msp430/msp430-protos.h (msp430_output_aligned_decl_common):
898 Update prototype to include "local" argument.
899 * config/msp430/msp430.c (msp430_output_aligned_decl_common): Add
900 "local" argument. Handle local common decls.
901 * config/msp430/msp430.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Adjust
902 msp430_output_aligned_decl_common call with 0 for "local" argument.
903 (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Define.
905 2020-05-12 Richard Biener <rguenther@suse.de>
907 * cfghooks.c (split_edge): Preserve EDGE_DFS_BACK if set.
909 2020-05-12 Martin Liska <mliska@suse.cz>
913 * sanopt.c (sanitize_rewrite_addressable_params):
914 Clear DECL_NOT_GIMPLE_REG_P for argument.
916 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
918 PR tree-optimization/94980
919 * tree-vect-generic.c (expand_vector_comparison): Use
920 vector_element_bits_tree to get the element size in bits,
921 rather than using TYPE_SIZE.
922 (expand_vector_condition, vector_element): Likewise.
924 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
926 PR tree-optimization/94980
927 * tree-vect-generic.c (build_replicated_const): Take the number
928 of bits as a parameter, instead of the type of the elements.
929 (do_plus_minus): Update accordingly, using vector_element_bits
930 to calculate the correct number of bits.
931 (do_negate): Likewise.
933 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
935 PR tree-optimization/94980
936 * tree.h (vector_element_bits, vector_element_bits_tree): Declare.
937 * tree.c (vector_element_bits, vector_element_bits_tree): New.
938 * match.pd: Use the new functions instead of determining the
939 vector element size directly from TYPE_SIZE(_UNIT).
940 * tree-vect-data-refs.c (vect_gather_scatter_fn_p): Likewise.
941 * tree-vect-patterns.c (vect_recog_mask_conversion_pattern): Likewise.
942 * tree-vect-stmts.c (vect_is_simple_cond): Likewise.
943 * tree-vect-generic.c (expand_vector_piecewise): Likewise.
944 (expand_vector_conversion): Likewise.
945 (expand_vector_addition): Likewise for a TYPE_SIZE_UNIT used as
946 a divisor. Convert the dividend to bits to compensate.
947 * tree-vect-loop.c (vectorizable_live_operation): Call
948 vector_element_bits instead of open-coding it.
950 2020-05-12 Jakub Jelinek <jakub@redhat.com>
952 * omp-offload.h (omp_discover_implicit_declare_target): Declare.
953 * omp-offload.c: Include context.h.
954 (omp_declare_target_fn_p, omp_declare_target_var_p,
955 omp_discover_declare_target_fn_r, omp_discover_declare_target_var_r,
956 omp_discover_implicit_declare_target): New functions.
957 * cgraphunit.c (analyze_functions): Call
958 omp_discover_implicit_declare_target.
960 2020-05-12 Richard Biener <rguenther@suse.de>
962 * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Canonicalize
963 literal constant &MEM[..] to a constant literal.
965 2020-05-12 Richard Biener <rguenther@suse.de>
967 PR tree-optimization/95045
968 * dbgcnt.def (lim): Add debug-counter.
969 * tree-ssa-loop-im.c: Include dbgcnt.h.
970 (find_refs_for_sm): Use lim debug counter for store motion
972 (do_store_motion): Rename form store_motion. Commit edge
974 (store_motion_loop): ... here.
975 (tree_ssa_lim): Adjust.
977 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
979 * config/rs6000/altivec.h (vec_clzm): Rename to vec_cntlzm.
980 (vec_ctzm): Rename to vec_cnttzm.
981 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
982 Change fourth operand for vec_ternarylogic to require
983 compatibility with unsigned SImode rather than unsigned QImode.
984 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
985 Remove overloaded forms of vec_gnb that are no longer needed.
986 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
987 for a Future Architecture): Replace vec_clzm with vec_cntlzm;
988 replace vec_ctzm with vec_cntlzm; remove four unwanted forms of
989 vec_gnb; move vec_ternarylogic documentation into this section
990 and replace const unsigned char with const unsigned int as its
993 2020-05-11 Carl Love <cel@us.ibm.com>
995 * config/rs6000/altivec.h (vec_genpcvm): New #define.
996 * config/rs6000/rs6000-builtin.def (XXGENPCVM_V16QI): New built-in
998 (XXGENPCVM_V8HI): Likewise.
999 (XXGENPCVM_V4SI): Likewise.
1000 (XXGENPCVM_V2DI): Likewise.
1001 (XXGENPCVM): New overloaded built-in instantiation.
1002 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add
1003 entries for FUTURE_BUILTIN_VEC_XXGENPCVM.
1004 (altivec_expand_builtin): Add special handling for
1005 FUTURE_BUILTIN_VEC_XXGENPCVM.
1006 (builtin_function_type): Add handling for
1007 FUTURE_BUILTIN_XXGENPCVM_{V16QI,V8HI,V4SI,V2DI}.
1008 * config/rs6000/vsx.md (VSX_EXTRACT_I4): New mode iterator.
1009 (UNSPEC_XXGENPCV): New constant.
1010 (xxgenpcvm_<mode>_internal): New insn.
1011 (xxgenpcvm_<mode>): New expansion.
1012 * doc/extend.texi: Add documentation for vec_genpcvm built-ins.
1014 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1016 * config/rs6000/altivec.h (vec_strir): New #define.
1017 (vec_stril): Likewise.
1018 (vec_strir_p): Likewise.
1019 (vec_stril_p): Likewise.
1020 * config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
1021 (UNSPEC_VSTRIL): Likewise.
1022 (vstrir_<mode>): New expansion.
1023 (vstrir_code_<mode>): New insn.
1024 (vstrir_p_<mode>): New expansion.
1025 (vstrir_p_code_<mode>): New insn.
1026 (vstril_<mode>): New expansion.
1027 (vstril_code_<mode>): New insn.
1028 (vstril_p_<mode>): New expansion.
1029 (vstril_p_code_<mode>): New insn.
1030 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr):
1031 New built-in function.
1032 (__builtin_altivec_vstrihr): Likewise.
1033 (__builtin_altivec_vstribl): Likewise.
1034 (__builtin_altivec_vstrihl): Likewise.
1035 (__builtin_altivec_vstribr_p): Likewise.
1036 (__builtin_altivec_vstrihr_p): Likewise.
1037 (__builtin_altivec_vstribl_p): Likewise.
1038 (__builtin_altivec_vstrihl_p): Likewise.
1039 (__builtin_vec_strir): New overloaded built-in function.
1040 (__builtin_vec_stril): Likewise.
1041 (__builtin_vec_strir_p): Likewise.
1042 (__builtin_vec_stril_p): Likewise.
1043 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
1044 Define overloaded forms of __builtin_vec_strir,
1045 __builtin_vec_stril, __builtin_vec_strir_p, and
1046 __builtin_vec_stril_p.
1047 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
1048 for a Future Architecture): Add description of vec_stril,
1049 vec_stril_p, vec_strir, and vec_strir_p built-in functions.
1051 2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
1053 * config/rs6000/altivec.h (vec_ternarylogic): New #define.
1054 * config/rs6000/altivec.md (UNSPEC_XXEVAL): New constant.
1056 * config/rs6000/predicates.md (u8bit_cint_operand): New predicate.
1057 * config/rs6000/rs6000-builtin.def: Add handling of new macro
1059 (BU_FUTURE_V_4): New macro. Use it.
1060 (BU_FUTURE_OVERLOAD_4): Likewise.
1061 * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Add
1062 handling for quaternary built-in functions.
1063 (altivec_resolve_overloaded_builtin): Add special-case handling
1064 for __builtin_vec_xxeval.
1065 * config/rs6000/rs6000-call.c: Add handling of new macro
1066 RS6000_BUILTIN_4 in initialization of rs6000_builtin_info,
1067 bdesc0_arg, bdesc1_arg, bdesc2_arg, bdesc_3arg,
1068 bdesc_altivec_preds, bdesc_abs, and bdesc_htm arrays.
1069 (altivec_overloaded_builtins): Add definitions for
1070 FUTURE_BUILTIN_VEC_XXEVAL.
1071 (bdesc_4arg): New array.
1072 (htm_expand_builtin): Add handling for quaternary built-in
1074 (rs6000_expand_quaternop_builtin): New function.
1075 (rs6000_expand_builtin): Add handling for quaternary built-in
1077 (rs6000_init_builtins): Initialize builtin_mode_to_type entries
1078 for unsigned QImode and unsigned HImode.
1079 (builtin_quaternary_function_type): New function.
1080 (rs6000_common_init_builtins): Add handling of quaternary
1082 * config/rs6000/rs6000.h (RS6000_BTC_QUATERNARY): New defined
1084 (RS6000_BTC_PREDICATE): Change value of constant.
1085 (RS6000_BTC_ABS): Likewise.
1086 (rs6000_builtins): Add support for new macro RS6000_BUILTIN_4.
1087 * doc/extend.texi (PowerPC AltiVec Built-In Functions Available
1088 for a Future Architecture): Add description of vec_ternarylogic
1091 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1093 * config/rs6000/rs6000-builtin.def (__builtin_pdepd): New built-in
1095 (__builtin_pextd): Likewise.
1096 * config/rs6000/rs6000.md (UNSPEC_PDEPD): New constant.
1097 (UNSPEC_PEXTD): Likewise.
1100 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
1101 a Future Architecture): Add descriptions of __builtin_pdepd and
1102 __builtin_pextd functions.
1104 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1106 * config/rs6000/altivec.h (vec_clrl): New #define.
1107 (vec_clrr): Likewise.
1108 * config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
1109 (UNSPEC_VCLRRB): Likewise.
1112 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
1114 (__builtin_altivec_vclrrb): Likewise.
1115 (__builtin_vec_clrl): New overloaded built-in function.
1116 (__builtin_vec_clrr): Likewise.
1117 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
1118 Define overloaded forms of __builtin_vec_clrl and
1120 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
1121 for a Future Architecture): Add descriptions of vec_clrl and
1124 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1126 * config/rs6000/rs6000-builtin.def (__builtin_cntlzdm): New
1127 built-in function definition.
1128 (__builtin_cnttzdm): Likewise.
1129 * config/rs6000/rs6000.md (UNSPEC_CNTLZDM): New constant.
1130 (UNSPEC_CNTTZDM): Likewise.
1131 (cntlzdm): New insn.
1132 (cnttzdm): Likewise.
1133 * doc/extend.texi (Basic PowerPC Built-in Functions available for
1134 a Future Architecture): Add descriptions of __builtin_cntlzdm and
1135 __builtin_cnttzdm functions.
1137 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
1140 * config/i386/mmx.md (sqrtv2sf2): New insn pattern.
1142 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1144 * config/rs6000/altivec.h (vec_cfuge): New #define.
1145 * config/rs6000/altivec.md (UNSPEC_VCFUGED): New constant.
1146 (vcfuged): New insn.
1147 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vcfuged):
1148 New built-in function.
1149 * config/rs6000/rs6000-call.c (builtin_function_type): Add
1150 handling for FUTURE_BUILTIN_VCFUGED case.
1151 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
1152 for a Future Architecture): Add description of vec_cfuge built-in
1155 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1157 * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_0): New
1159 (BU_FUTURE_MISC_1): Likewise.
1160 (BU_FUTURE_MISC_2): Likewise.
1161 (BU_FUTURE_MISC_3): Likewise.
1162 (__builtin_cfuged): New built-in function definition.
1163 * config/rs6000/rs6000.md (UNSPEC_CFUGED): New constant.
1165 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
1166 a Future Architecture): New subsubsection.
1168 2020-05-11 Richard Biener <rguenther@suse.de>
1170 PR tree-optimization/95049
1171 * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition
1172 between different constants.
1174 2020-05-11 Richard Sandiford <richard.sandiford@arm.com>
1176 * tree-pretty-print.c (dump_generic_node): Handle BOOLEAN_TYPEs.
1178 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1179 Bill Schmidt <wschmidt@linux.ibm.com>
1181 * config/rs6000/altivec.h (vec_gnb): New #define.
1182 * config/rs6000/altivec.md (UNSPEC_VGNB): New constant.
1184 * config/rs6000/rs6000-builtin.def (BU_FUTURE_OVERLOAD_1): New
1186 (BU_FUTURE_OVERLOAD_2): Likewise.
1187 (BU_FUTURE_OVERLOAD_3): Likewise.
1188 (__builtin_altivec_gnb): New built-in function.
1189 (__buiiltin_vec_gnb): New overloaded built-in function.
1190 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
1191 Define overloaded forms of __builtin_vec_gnb.
1192 (rs6000_expand_binop_builtin): Add error checking for 2nd argument
1193 of __builtin_vec_gnb.
1194 (builtin_function_type): Mark return value and arguments unsigned
1195 for FUTURE_BUILTIN_VGNB.
1196 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
1197 for a Future Architecture): Add description of vec_gnb built-in
1200 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1201 Bill Schmidt <wschmidt@linux.ibm.com>
1203 * config/rs6000/altivec.h (vec_pdep): New macro implementing new
1205 (vec_pext): Likewise.
1206 * config/rs6000/altivec.md (UNSPEC_VPDEPD): New constant.
1207 (UNSPEC_VPEXTD): Likewise.
1210 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vpdepd): New
1212 (__builtin_altivec_vpextd): Likewise.
1213 * config/rs6000/rs6000-call.c (builtin_function_type): Add
1214 handling for FUTURE_BUILTIN_VPDEPD and FUTURE_BUILTIN_VPEXTD
1216 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
1217 for a Future Architecture): Add description of vec_pdep and
1218 vec_pext built-in functions.
1220 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1221 Bill Schmidt <wschmidt@linux.ibm.com>
1223 * config/rs6000/altivec.h (vec_clzm): New macro.
1224 (vec_ctzm): Likewise.
1225 * config/rs6000/altivec.md (UNSPEC_VCLZDM): New constant.
1226 (UNSPEC_VCTZDM): Likewise.
1229 * config/rs6000/rs6000-builtin.def (BU_FUTURE_V_0): New macro.
1230 (BU_FUTURE_V_1): Likewise.
1231 (BU_FUTURE_V_2): Likewise.
1232 (BU_FUTURE_V_3): Likewise.
1233 (__builtin_altivec_vclzdm): New builtin definition.
1234 (__builtin_altivec_vctzdm): Likewise.
1235 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Cause
1236 _ARCH_PWR_FUTURE macro to be defined if OPTION_MASK_FUTURE flag is
1238 * config/rs6000/rs6000-call.c (builtin_function_type): Set return
1239 value and parameter types to be unsigned for VCLZDM and VCTZDM.
1240 * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
1241 support for TARGET_FUTURE flag.
1242 * config/rs6000/rs6000.h (RS6000_BTM_FUTURE): New macro constant.
1243 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
1244 for a Future Architecture): New subsubsection.
1246 2020-05-11 Richard Biener <rguenther@suse.de>
1248 PR tree-optimization/94988
1249 PR tree-optimization/95025
1250 * tree-ssa-loop-im.c (seq_entry): Make a struct, add from.
1251 (sm_seq_push_down): Take extra parameter denoting where we
1253 (execute_sm_exit): Re-issue sm_other stores in the correct
1255 (sm_seq_valid_bb): When always executed, allow sm_other to
1256 prevail inbetween sm_ord and record their stored value.
1257 (hoist_memory_references): Adjust refs_not_supported propagation
1258 and prune sm_other from the end of the ordered sequences.
1260 2020-05-11 Felix Yang <felix.yang@huawei.com>
1263 * config/aarch64/aarch64.md (mov<mode>):
1264 Bitcasts to the equivalent integer mode using gen_lowpart
1265 instead of doing FAIL for scalar floating point move.
1267 2020-05-11 Alex Coplan <alex.coplan@arm.com>
1269 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Add case
1270 to correctly calculate cost for new pattern (*csinv3_uxtw_insn3).
1271 * config/aarch64/aarch64.md (*csinv3_utxw_insn1): New.
1272 (*csinv3_uxtw_insn2): New.
1273 (*csinv3_uxtw_insn3): New.
1274 * config/aarch64/iterators.md (neg_not_cs): New.
1276 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
1279 * config/i386/mmx.md (mmx_addv2sf3): Use "v" constraint
1280 instead of "Yv" for AVX alternatives. Add "prefix" attribute.
1281 (*mmx_addv2sf3): Ditto.
1282 (*mmx_subv2sf3): Ditto.
1283 (*mmx_mulv2sf3): Ditto.
1284 (*mmx_<code>v2sf3): Ditto.
1285 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
1287 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
1290 * config/i386/i386.c (ix86_vector_mode_supported_p):
1291 Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE.
1292 * config/i386/mmx.md (*mov<mode>_internal): Do not set
1293 mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE.
1295 (mmx_addv2sf3): Change operand predicates from
1296 nonimmediate_operand to register_mmxmem_operand.
1297 (addv2sf3): New expander.
1298 (*mmx_addv2sf3): Add SSE/AVX alternatives. Change operand
1299 predicates from nonimmediate_operand to register_mmxmem_operand.
1300 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1302 (mmx_subv2sf3): Change operand predicate from
1303 nonimmediate_operand to register_mmxmem_operand.
1304 (mmx_subrv2sf3): Ditto.
1305 (subv2sf3): New expander.
1306 (*mmx_subv2sf3): Add SSE/AVX alternatives. Change operand
1307 predicates from nonimmediate_operand to register_mmxmem_operand.
1308 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1310 (mmx_mulv2sf3): Change operand predicates from
1311 nonimmediate_operand to register_mmxmem_operand.
1312 (mulv2sf3): New expander.
1313 (*mmx_mulv2sf3): Add SSE/AVX alternatives. Change operand
1314 predicates from nonimmediate_operand to register_mmxmem_operand.
1315 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1317 (mmx_<code>v2sf3): Change operand predicates from
1318 nonimmediate_operand to register_mmxmem_operand.
1319 (<code>v2sf3): New expander.
1320 (*mmx_<code>v2sf3): Add SSE/AVX alternatives. Change operand
1321 predicates from nonimmediate_operand to register_mmxmem_operand.
1322 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1323 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
1325 2020-05-11 Martin Liska <mliska@suse.cz>
1328 * common.opt: Fix typo in option description.
1330 2020-05-11 Martin Liska <mliska@suse.cz>
1332 PR gcov-profile/94928
1333 * gcov-io.h: Add caveat about coverage format parsing and
1334 possible outdated documentation.
1336 2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com>
1338 PR tree-optimization/83403
1339 * tree-affine.c (expr_to_aff_combination): Replace SSA_NAME with
1340 determine_value_range, Add fold conversion of MULT_EXPR, fix the
1343 2020-05-10 Gerald Pfeifer <gerald@pfeifer.com>
1345 * config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and
1346 __ILP32__ for 32-bit targets.
1348 2020-05-09 Eric Botcazou <ebotcazou@adacore.com>
1350 * tree.h (expr_align): Delete.
1351 * tree.c (expr_align): Likewise.
1353 2020-05-09 Hans-Peter Nilsson <hp@axis.com>
1355 * resource.c (init_resource_info): Filter-out TARGET_FLAGS_REGNUM
1356 from end_of_function_needs.
1358 * config.gcc: Remove support for crisv32-*-* and cris-*-linux*.
1359 * config/cris/t-linux, config/cris/linux.h, config/cris/linux.opt:
1361 * config/cris/t-elfmulti: Remove crisv32 multilib.
1362 * config/cris: Remove shared-library and CRIS v32 support.
1364 Move trivially from cc0 to reg:CC model, removing most optimizations.
1365 * config/cris/cris.md: Remove all side-effect patterns and their
1366 splitters. Remove most peepholes. Add clobbers of CRIS_CC0_REGNUM
1367 to all but post-reload control-flow and movem insns. Remove
1368 constraints on all modified expanders. Remove obsoleted cc0-related
1370 (attr "cc"): Remove alternative "rev".
1371 (mode_iterator BWDD, DI_, SI_): New.
1372 (mode_attr sCC_destc, cmp_op1c, cmp_op2c): New.
1373 ("tst<mode>"): Remove; fold as "M" alternative into compare insn.
1374 ("mstep_shift", "mstep_mul"): Remove patterns.
1375 ("s<rcond>", "s<ocond>", "s<ncond>"): Anonymize.
1376 * config/cris/cris.c: Change all non-condition-code,
1377 non-control-flow emitted insns to add a parallel with clobber of
1378 CRIS_CC0_REGNUM, mostly by changing from gen_rtx_SET with
1379 emit_insn to use of emit_move_insn, gen_add2_insn or
1380 cris_emit_insn, as convenient.
1381 (cris_reg_overlap_mentioned_p)
1382 (cris_normal_notice_update_cc, cris_notice_update_cc): Remove.
1383 (cris_movem_load_rest_p): Don't assume all elements in a
1385 (cris_store_multiple_op_p): Ditto.
1386 (cris_emit_insn): New function.
1387 * cris/cris-protos.h (cris_emit_insn): Declare.
1390 * config/cris/cris.md (zcond): New code_iterator.
1391 ("*cbranch<mode>4_btstq<CC>"): New insn_and_split.
1393 * config/cris/cris.c (TARGET_FLAGS_REGNUM): Define.
1395 * config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.
1397 * config/cris/cris.md ("movsi"): For memory destination
1398 post-reload, generate clobberless variant. Similarly for a
1399 zero-source post-reload.
1400 ("*mov_tomem<mode>_split"): New split.
1401 ("*mov_tomem<mode>"): New insn.
1402 ("enabled", mov_tomem_enabled): Define and use to exclude "x" ->
1403 "Q>m" for less-than-SImode.
1404 ("*mov_fromzero<mode>_split"): New split.
1405 ("*mov_fromzero<mode>"): New insn.
1407 Prepare for cmpelim pass to eliminate redundant compare insns.
1408 * config/cris/cris-modes.def: New file.
1409 * config/cris/cris-protos.h (cris_select_cc_mode): Declare.
1410 (cris_notice_update_cc): Remove left-over declaration.
1411 * config/cris/cris.c (TARGET_CC_MODES_COMPATIBLE): Define.
1412 (cris_select_cc_mode, cris_cc_modes_compatible): New functions.
1413 * config/cris/cris.h (SELECT_CC_MODE): Define.
1414 * config/cris/cris.md (NZSET, NZUSE, NZVCSET, NZVCUSE): New
1416 (cond): New code_iterator.
1417 (nzcond): Replacement for incorrect ncond. All callers changed.
1418 (nzvccond): Replacement for ocond. All callers changed.
1419 (rnzcond): Replacement for rcond. All callers changed.
1420 (xCC): New code_attr.
1421 (cmp_op1c, cmp_op0c): Renumber from cmp_op1c and cmp_op2c. All
1423 ("*cmpdi<NZVCSET:mode>"): Rename from "*cmpdi". Replace
1424 CCmode with iteration over NZVCSET.
1425 ("*cmp_ext<BW:mode><NZVCSET:mode>"): Similarly; rename from
1427 ("*cmpsi<NZVCSET:mode>"): Similarly, from "*cmpsi".
1428 ("*cmp<BW:mode><NZVCSET:mode>"): Similarly from "*cmp<mode>".
1429 ("*btst<mode>"): Similarly, from "*btst".
1430 ("*cbranch<mode><code>4"): Rename from "*cbranch<mode>4",
1431 iterating over cond instead of matching the comparison with
1432 ordered_comparison_operator.
1433 ("*cbranch<mode>4_btstq<CC>"): Correct label operand number.
1434 ("b<zcond:code><mode>"): Rename from "b<ncond:code>", iterating
1436 ("b<nzvccond:code><mode>"): Similarly from "b<ocond:code>", over
1437 NZVCUSE. Remove FIXME.
1438 ("*b<nzcond:code>_reversed<mode>"): Similarly from
1439 "*b<ncond:code>_reversed", over NZUSE.
1440 ("*b<nzvccond:code>_reversed<mode>"): Similarly from
1441 "*b<ocond:code>_reversed", over NZVCUSE. Remove FIXME.
1442 ("b<rnzcond:code><mode>"): Similarly from "b<rcond:code>",
1443 over NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
1444 depending on CC_NZmode vs. CCmode. Remove FIXME.
1445 ("*b<rnzcond:code>_reversed<mode>"): Similarly from
1446 "*b<rcond:code>_reversed", over NZUSE.
1447 ("*cstore<mode><code>4"): Rename from "*cstore<mode>4",
1448 iterating over cond instead of matching the comparison with
1449 ordered_comparison_operator.
1450 ("*s<nzcond:code><mode>"): Rename from "*s<ncond:code>",
1451 iterating over NZUSE.
1452 ("*s<rnzcond:code><mode>"): Similar from "*s<rcond:code>", over
1453 NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
1454 depending on CC_NZmode vs. CCmode.
1455 ("*s<nzvccond:code><mode>"): Simlar from "*s<ocond:code>", over
1456 NZVCUSE. Remove FIXME.
1457 ("cc"): Comment on new use.
1458 ("cc_enabled"): New attribute.
1459 ("enabled"): Make default fall back to cc_enabled.
1460 ("setnz", "ccnz", "setnzvc", "ccnzvc", "setcc", "cccc"): New
1461 default_subst_attrs.
1462 ("setnz_subst", "setnzvc_subst", "setcc_subst"): New default_subst.
1463 ("*movsi_internal<setcc><setnz><setnzvc>"): Rename from
1464 "*movsi_internal". Correct contents of, and rename attribute
1465 "cc" to "cc<cccc><ccnz><ccnzvc>".
1466 ("anz", "anzvc", "acc"): New define_subst_attrs.
1467 ("<acc><anz><anzvc>movhi<setcc><setnz><setnzvc>"): Rename from
1468 "movhi". Rename "cc" attribute to "cc<cccc><ccnz><ccnzvc>".
1469 ("<acc><anz><anzvc>movqi<setcc><setnz><setnzvc>"): Similar from
1470 "movqi". Correct contents of, and rename "cc" attribute to
1471 "cc<cccc><ccnz><ccnzvc>".
1472 ("*b<zcond:code><mode>"): Rename from "b<zcond:code><mode>".
1473 ("*b<nzvccond:code><mode>"): Rename from "b<nzvccond:code><mode>".
1474 ("*b<rnzcond:code><mode>"): Rename from "*b<rnzcond:code><mode>".
1475 ("<acc><anz><anzvc>extend<mode>si2<setcc><setnz><setnzvc>"):
1476 Rename from "extend<mode>si2".
1477 ("<acc><anz><anzvc>zero_extend<mode>si2<setcc><setnz><setnzvc>"):
1478 Similar, from "zero_extend<mode>si2".
1479 ("*adddi3<setnz>"): Rename from "*adddi3".
1480 ("*subdi3<setnz>"): Similarly from "*subdi3".
1481 ("*addsi3<setnz>"): Similarly from "*addsi3".
1482 ("*subsi3<setnz>"): Similarly from "*subsi3".
1483 ("*addhi3<setnz>"): Similarly from "*addhi3" and decorate the
1484 "cc" attribute to "cc<ccnz>".
1485 ("*addqi3<setnz>"): Similarly from "*addqi3".
1486 ("*sub<mode>3<setnz>"): Similarly from "*sub<mode>3".
1487 ("*expanded_andsi<setcc><setnz><setnzvc>"): Rename from
1489 ("*iorsi3<setcc><setnz><setnzvc>"): Similar from "*iorsi3".
1490 Decorate "cc" attribute to make "cc<cccc><ccnz><ccnzvc>".
1491 ("*iorhi3<setcc><setnz><setnzvc>"): Similar from "*iorhi3".
1492 ("*iorqi3<setcc><setnz><setnzvc>"): Similar from "*iorqi3".
1493 ("*expanded_andhi<setcc><setnz><setnzvc>"): Similar from
1494 "*expanded_andhi". Add quick cc-setting alternative for 0..31.
1495 ("*andqi3<setcc><setnz><setnzvc>"): Similar from "*andqi3".
1496 ("<acc><anz><anzvc>xorsi3<setcc><setnz><setnzvc>"): Rename
1498 ("<acc><anz><anzvc>one_cmplsi2<setcc><setnz><setnzvc>"): Rename
1500 ("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"): Rename
1502 ("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"): Rename
1504 ("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"): Rename
1506 ("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".
1508 * config/cris/cris-modes.def (CC_ZnN): New CC_MODE.
1509 * config/cris/cris.c (cris_rtx_costs): Handle pre-split bit-test
1510 * config/cris/cris.md (ZnNNZSET, ZnNNZUSE): New mode_iterators.
1511 (znnCC, rznnCC): New code_attrs.
1512 ("*btst<mode>"): Iterator over ZnNNZSET instead of NZVCSET. Remove
1513 obseolete comment. Add belt-and-suspenders mode-test to condition.
1514 Add fixme regarding remaining matched-but-not-generated case.
1515 ("*cbranch<mode>4_btstrq1_<CC>"): New insn_and_split.
1516 ("*cbranch<mode>4_btstqb0_<CC>"): Rename from
1517 "*cbranch<mode>4_btstq<CC>". Split to CC_NZ instead of CC.
1518 ("*b<zcond:code><mode>"): Iterate over ZnNNZUSE instead of NZUSE.
1519 Handle output of CC_ZnNmode.
1520 ("*b<nzcond:code>_reversed<mode>"): Ditto.
1522 * config/cris/cris.c (cris_select_cc_mode): Return CC_NZmode for
1523 NEG too. Correct comment.
1524 * config/cris/cris.md ("<anz>neg<mode>2<setnz>"): Rename from
1527 2020-05-08 Vladimir Makarov <vmakarov@redhat.com>
1529 * ira-color.c (update_costs_from_allocno): Remove
1530 conflict_cost_update_p argument. Propagate costs only along
1531 threads. Always do conflict cost update. Add printing debugging
1533 (update_costs_from_copies): Add printing debugging info.
1534 (restore_costs_from_copies): Ditto.
1535 (assign_hard_reg): Improve debug info.
1536 (push_only_colorable): Ditto. Call update_costs_from_prefs.
1537 (color_allocnos): Remove update_costs_from_prefs.
1539 2020-05-08 Richard Biener <rguenther@suse.de>
1541 * tree-vectorizer.h (vec_info::slp_loads): New.
1542 (vect_optimize_slp): Declare.
1543 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Do
1544 nothing when there are no loads.
1545 (vect_gather_slp_loads): Gather loads into a vector.
1546 (vect_supported_load_permutation_p): Remove.
1547 (vect_analyze_slp_instance): Do not verify permutation
1549 (vect_analyze_slp): Optimize permutations of reductions
1550 after all SLP instances have been gathered and gather
1552 (vect_optimize_slp): New function split out from
1553 vect_supported_load_permutation_p. Elide some permutations.
1554 (vect_slp_analyze_bb_1): Call vect_optimize_slp.
1555 * tree-vect-loop.c (vect_analyze_loop_2): Likewise.
1556 * tree-vect-stmts.c (vectorizable_load): Check whether
1557 the load can be permuted. When generating code assert we can.
1559 2020-05-08 Richard Biener <rguenther@suse.de>
1561 * tree-ssa-sccvn.c (rpo_avail): Change type to
1562 eliminate_dom_walker *.
1563 (eliminate_with_rpo_vn): Adjust rpo_avail to make vn_valueize
1564 use the DOM walker availability.
1565 (vn_reference_fold_indirect): Use get_addr_base_and_unit_offset_1
1566 with vn_valueize as valueization callback.
1567 (vn_reference_maybe_forwprop_address): Likewise.
1568 * tree-dfa.c (get_addr_base_and_unit_offset_1): Also valueize
1569 array_ref_low_bound.
1571 2020-05-08 Jakub Jelinek <jakub@redhat.com>
1573 PR tree-optimization/94786
1574 * match.pd (A ^ ((A ^ B) & -(C cmp D)) -> (C cmp D) ? B : A): New
1578 * config/i386/i386.md (peephole2 after *add<mode>3_cc_overflow_1): New
1582 * tree.c (get_narrower): Reuse the op temporary instead of
1585 PR tree-optimization/94783
1586 * match.pd ((X + (X >> (prec - 1))) ^ (X >> (prec - 1)) to abs (X)):
1589 PR tree-optimization/94956
1590 * match.pd (FFS): Optimize __builtin_ffs* of non-zero argument into
1591 __builtin_ctz* + 1 if direct IFN_CTZ is supported.
1593 PR tree-optimization/94913
1594 * match.pd (A - B + -1 >= A to B >= A): New simplification.
1595 (A - B > A to A < B): Don't test TYPE_OVERFLOW_WRAPS which is always
1596 true for TYPE_UNSIGNED integral types.
1599 PR rtl-optimization/94516
1600 * rtl.h (remove_reg_equal_equiv_notes): Add a bool argument defaulted
1602 * rtlanal.c (remove_reg_equal_equiv_notes): Add no_rescan argument.
1603 Call df_notes_rescan if that argument is not true and returning true.
1604 * combine.c (adjust_for_new_dest): Pass true as second argument to
1605 remove_reg_equal_equiv_notes.
1606 * postreload.c (reload_combine_recognize_pattern): Don't call
1609 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
1611 * config/rs6000/rs6000.md (*setnbc_<un>signed_<GPR:mode>): New
1613 (*setnbcr_<un>signed_<GPR:mode>): New define_insn.
1614 (*neg_eq_<mode>): Avoid for TARGET_FUTURE; add missing && 1.
1615 (*neg_ne_<mode>): Likewise.
1617 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
1619 * config/rs6000/rs6000.md (setbc_<un>signed_<GPR:mode>): New
1621 (*setbcr_<un>signed_<GPR:mode>): Likewise.
1622 (cstore<mode>4): Use setbc[r] if available.
1623 (<code><GPR:mode><GPR2:mode>2_isel): Avoid for TARGET_FUTURE.
1624 (eq<mode>3): Use setbc for TARGET_FUTURE.
1625 (*eq<mode>3): Avoid for TARGET_FUTURE.
1626 (ne<mode>3): Replace :P with :GPR; use setbc for TARGET_FUTURE;
1627 else for non-Pmode, use gen_eq and gen_xor.
1628 (*ne<mode>3): Avoid for TARGET_FUTURE.
1629 (*eqsi3_ext<mode>): Avoid for TARGET_FUTURE; fix missing && 1.
1631 2020-05-07 Jeff Law <law@redhat.com>
1633 * config/h8300/h8300.md: Move expanders and patterns into
1634 files based on functionality.
1635 * config/h8300/addsub.md: New file.
1636 * config/h8300/bitfield.md: New file
1637 * config/h8300/combiner.md: New file
1638 * config/h8300/divmod.md: New file
1639 * config/h8300/extensions.md: New file
1640 * config/h8300/jumpcall.md: New file
1641 * config/h8300/logical.md: New file
1642 * config/h8300/movepush.md: New file
1643 * config/h8300/multiply.md: New file
1644 * config/h8300/other.md: New file
1645 * config/h8300/proepi.md: New file
1646 * config/h8300/shiftrotate.md: New file
1647 * config/h8300/testcompare.md: New file
1649 * config/h8300/h8300.md (adds/subs splitters): Merge into single
1651 (negation expanders and patterns): Simplify and combine using
1653 (one_cmpl expanders and patterns): Likewise.
1654 (tablejump, indirect_jump patterns ): Likewise.
1655 (shift and rotate expanders and patterns): Likewise.
1656 (absolute value expander and pattern): Drop expander, rename pattern
1658 (peephole2 patterns): Move into...
1659 * config/h8300/peepholes.md: New file.
1661 * config/h8300/constraints.md (L and N): Simplify now that we're not
1662 longer supporting the original H8/300 chip.
1663 * config/h8300/elf.h (LINK_SPEC): Likewise. Default to H8/300H.
1664 * config/h8300/h8300.c (shift_alg_qi): Drop H8/300 support.
1665 (shift_alg_hi, shift_alg_si): Similarly.
1666 (h8300_option_overrides): Similarly. Default to H8/300H. If
1667 compiling for H8/S, then turn off H8/300H. Do not update the
1668 shift_alg tables for H8/300 port.
1669 (h8300_emit_stack_adjustment): Remove support for H8/300. Simplify
1671 (push, split_adds_subs, h8300_rtx_costs): Likewise.
1672 (h8300_print_operand, compute_mov_length): Likewise.
1673 (output_plussi, compute_plussi_length): Likewise.
1674 (compute_plussi_cc, output_logical_op): Likewise.
1675 (compute_logical_op_length, compute_logical_op_cc): Likewise.
1676 (get_shift_alg, h8300_shift_needs_scratch): Likewise.
1677 (output_a_shift, compute_a_shift_length): Likewise.
1678 (output_a_rotate, compute_a_rotate_length): Likewise.
1679 (output_simode_bld, h8300_hard_regno_mode_ok): Likewise.
1680 (h8300_modes_tieable_p, h8300_return_in_memory): Likewise.
1681 * config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Likewise.
1682 (attr_cpu, TARGET_H8300): Remove.
1683 (TARGET_DEFAULT): Update.
1684 (UNITS_PER_WORD, PARM_BOUNDARY): Simplify where possible.
1685 (BIGGEST_ALIGNMENT, STACK_BOUNDARY): Likewise.
1686 (CONSTANT_ADDRESS_P, MOVE_MAX, Pmode): Likewise.
1687 (SIZE_TYPE, POINTER_SIZE, ASM_WORD_OP): Likewise.
1688 * config/h8300/h8300.md: Simplify patterns throughout.
1689 * config/h8300/t-h8300: Update multilib configuration.
1691 * config/h8300/h8300.h (LINK_SPEC): Remove.
1692 (USER_LABEL_PREFIX): Likewise.
1694 * config/h8300/h8300.c (h8300_asm_named_section): Remove.
1695 (h8300_option_override): Remove remnants of COFF support.
1697 2020-05-07 Alan Modra <amodra@gmail.com>
1699 * tree-ssa-reassoc.c (optimize_range_tests_to_bit_test): Replace
1700 set_rtx_cost with set_src_cost.
1701 * tree-switch-conversion.c (bit_test_cluster::emit): Likewise.
1703 2020-05-07 Kewen Lin <linkw@gcc.gnu.org>
1705 * tree-vect-stmts.c (vectorizable_load): Check alignment to avoid
1706 redundant half vector handlings for no peeling gaps.
1708 2020-05-07 Giuliano Belinassi <giuliano.belinassi@usp.br>
1710 * tree-ssa-operands.c (operands_scanner): New class.
1711 (operands_bitmap_obstack): Remove.
1712 (n_initialized): Remove.
1713 (build_uses): Move to operands_scanner class.
1714 (build_vuse): Same as above.
1715 (build_vdef): Same as above.
1716 (verify_ssa_operands): Same as above.
1717 (finalize_ssa_uses): Same as above.
1718 (cleanup_build_arrays): Same as above.
1719 (finalize_ssa_stmt_operands): Same as above.
1720 (start_ssa_stmt_operands): Same as above.
1721 (append_use): Same as above.
1722 (append_vdef): Same as above.
1723 (add_virtual_operand): Same as above.
1724 (add_stmt_operand): Same as above.
1725 (get_mem_ref_operands): Same as above.
1726 (get_tmr_operands): Same as above.
1727 (maybe_add_call_vops): Same as above.
1728 (get_asm_stmt_operands): Same as above.
1729 (get_expr_operands): Same as above.
1730 (parse_ssa_operands): Same as above.
1731 (finalize_ssa_defs): Same as above.
1732 (build_ssa_operands): Same as above, plus create a C-like wrapper.
1733 (update_stmt_operands): Create an instance of operands_scanner.
1735 2020-05-07 Richard Biener <rguenther@suse.de>
1738 * tree-ssa-structalias.c (refered_from_nonlocal_fn): Use
1739 DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible.
1740 (refered_from_nonlocal_var): Likewise.
1741 (ipa_pta_execute): Likewise.
1743 2020-05-07 Erick Ochoa <erick.ochoa@theobroma-systems.com>
1745 * gcc/tree-ssa-struct-alias.c: Fix comments
1747 2020-05-07 Martin Liska <mliska@suse.cz>
1749 * doc/invoke.texi: Fix 2 optindex entries.
1751 2020-05-07 Richard Biener <rguenther@suse.de>
1754 * tree-core.h (tree_decl_common::gimple_reg_flag): Rename ...
1755 (tree_decl_common::not_gimple_reg_flag): ... to this.
1756 * tree.h (DECL_GIMPLE_REG_P): Rename ...
1757 (DECL_NOT_GIMPLE_REG_P): ... to this.
1758 * gimple-expr.c (copy_var_decl): Copy DECL_NOT_GIMPLE_REG_P.
1759 (create_tmp_reg): Simplify.
1760 (create_tmp_reg_fn): Likewise.
1761 (is_gimple_reg): Check DECL_NOT_GIMPLE_REG_P for all regs.
1762 * gimplify.c (create_tmp_from_val): Simplify.
1763 (gimplify_bind_expr): Likewise.
1764 (gimplify_compound_literal_expr): Likewise.
1765 (gimplify_function_tree): Likewise.
1766 (prepare_gimple_addressable): Set DECL_NOT_GIMPLE_REG_P.
1767 * asan.c (create_odr_indicator): Do not clear DECL_GIMPLE_REG_P.
1768 (asan_add_global): Copy it.
1769 * cgraphunit.c (cgraph_node::expand_thunk): Force args
1771 * function.c (gimplify_parameters): Copy
1772 DECL_NOT_GIMPLE_REG_P.
1773 * ipa-param-manipulation.c
1774 (ipa_param_body_adjustments::common_initialization): Simplify.
1775 (ipa_param_body_adjustments::reset_debug_stmts): Copy
1776 DECL_NOT_GIMPLE_REG_P.
1777 * omp-low.c (lower_omp_for_scan): Do not set DECL_GIMPLE_REG_P.
1778 * sanopt.c (sanitize_rewrite_addressable_params): Likewise.
1779 * tree-cfg.c (make_blocks_1): Simplify.
1780 (verify_address): Do not verify DECL_GIMPLE_REG_P setting.
1781 * tree-eh.c (lower_eh_constructs_2): Simplify.
1782 * tree-inline.c (declare_return_variable): Adjust and
1784 (copy_decl_to_var): Copy DECL_NOT_GIMPLE_REG_P.
1785 (copy_result_decl_to_var): Likewise.
1786 * tree-into-ssa.c (pass_build_ssa::execute): Adjust comment.
1787 * tree-nested.c (create_tmp_var_for): Simplify.
1788 * tree-parloops.c (separate_decls_in_region_name): Copy
1789 DECL_NOT_GIMPLE_REG_P.
1790 * tree-sra.c (create_access_replacement): Adjust and
1791 generalize partial def support.
1792 * tree-ssa-forwprop.c (pass_forwprop::execute): Set
1793 DECL_NOT_GIMPLE_REG_P on decls we introduce partial defs on.
1794 * tree-ssa.c (maybe_optimize_var): Handle clearing of
1795 TREE_ADDRESSABLE and setting/clearing DECL_NOT_GIMPLE_REG_P
1797 * lto-streamer-out.c (hash_tree): Hash DECL_NOT_GIMPLE_REG_P.
1798 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Stream
1799 DECL_NOT_GIMPLE_REG_P.
1800 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
1801 * cfgexpand.c (avoid_type_punning_on_regs): New.
1802 (discover_nonconstant_array_refs): Call
1803 avoid_type_punning_on_regs to avoid unsupported mode punning.
1805 2020-05-07 Alex Coplan <alex.coplan@arm.com>
1807 * config/arm/arm.c (arm_add_stmt_cost): Fix declaration, remove class
1810 2020-05-07 Richard Biener <rguenther@suse.de>
1812 PR tree-optimization/57359
1813 * tree-ssa-loop-im.c (im_mem_ref::indep_loop): Remove.
1814 (in_mem_ref::dep_loop): Repurpose.
1815 (LOOP_DEP_BIT): Remove.
1816 (enum dep_kind): New.
1817 (enum dep_state): Likewise.
1818 (record_loop_dependence): New function to populate the
1820 (query_loop_dependence): New function to query the dependence
1822 (memory_accesses::refs_in_loop): Rename to ...
1823 (memory_accesses::refs_loaded_in_loop): ... this and change to
1825 (outermost_indep_loop): Adjust.
1826 (mem_ref_alloc): Likewise.
1827 (gather_mem_refs_stmt): Likewise.
1828 (mem_refs_may_alias_p): Add tbaa_p parameter and pass it down.
1829 (struct sm_aux): New.
1830 (execute_sm): Split code generation on exits, record state
1832 (enum sm_kind): New.
1833 (execute_sm_exit): Exit code generation part.
1834 (sm_seq_push_down): Helper for sm_seq_valid_bb performing
1835 dependence checking on stores reached from exits.
1836 (sm_seq_valid_bb): New function gathering SM stores on exits.
1837 (hoist_memory_references): Re-implement.
1838 (refs_independent_p): Add tbaa_p parameter and pass it down.
1839 (record_dep_loop): Remove.
1840 (ref_indep_loop_p_1): Fold into ...
1841 (ref_indep_loop_p): ... this and generalize for three kinds
1842 of dependence queries.
1843 (can_sm_ref_p): Adjust according to hoist_memory_references
1845 (store_motion_loop): Don't do anything if the set of SM
1846 candidates is empty.
1847 (tree_ssa_lim_initialize): Adjust.
1848 (tree_ssa_lim_finalize): Likewise.
1850 2020-05-07 Eric Botcazou <ebotcazou@adacore.com>
1851 Pierre-Marie de Rodat <derodat@adacore.com>
1853 * dwarf2out.c (add_data_member_location_attribute): Take into account
1854 the variant part offset in the computation of the data bit offset.
1855 (add_bit_offset_attribute): Remove CTX parameter. Pass a new context
1856 in the call to field_byte_offset.
1857 (gen_field_die): Adjust call to add_bit_offset_attribute and remove
1858 confusing assertion.
1859 (analyze_variant_discr): Deal with boolean subtypes.
1861 2020-05-07 Martin Liska <mliska@suse.cz>
1863 * lto-wrapper.c: Split arguments of MAKE environment
1866 2020-05-07 Uroš Bizjak <ubizjak@gmail.com>
1868 * config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use
1869 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
1870 fenv_var and new_fenv_var.
1872 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1875 * config/i386/subst.md (store_mask_constraint, store_mask_predicate):
1877 (avx512dq_vextract<shuffletype>64x2_1_maskm,
1878 avx512f_vextract<shuffletype>32x4_1_maskm,
1879 vec_extract_lo_<mode>_maskm, vec_extract_hi_<mode>_maskm): Remove.
1880 (<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>): Split
1882 (*avx512dq_vextract<shuffletype>64x2_1,
1883 avx512dq_vextract<shuffletype>64x2_1_mask): ... these new
1884 define_insns. Even in the masked variant allow memory output but in
1885 that case use 0 rather than 0C constraint on the source of masked-out
1887 (<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>): Split
1889 (*avx512f_vextract<shuffletype>32x4_1,
1890 avx512f_vextract<shuffletype>32x4_1_mask): ... these new define_insns.
1891 Even in the masked variant allow memory output but in that case use
1892 0 rather than 0C constraint on the source of masked-out elts.
1893 (vec_extract_lo_<mode><mask_name>): Split into ...
1894 (vec_extract_lo_<mode>, vec_extract_lo_<mode>_mask): ... these new
1895 define_insns. Even in the masked variant allow memory output but in
1896 that case use 0 rather than 0C constraint on the source of masked-out
1898 (vec_extract_hi_<mode><mask_name>): Split into ...
1899 (vec_extract_hi_<mode>, vec_extract_hi_<mode>_mask): ... these new
1900 define_insns. Even in the masked variant allow memory output but in
1901 that case use 0 rather than 0C constraint on the source of masked-out
1904 2020-05-06 qing zhao <qing.zhao@oracle.com>
1907 * common.opt: Add -flarge-source-files.
1908 * doc/invoke.texi: Document it.
1909 * toplev.c (process_options): set line_table->default_range_bits
1910 to 0 when flag_large_source_files is true.
1912 2020-05-06 Uroš Bizjak <ubizjak@gmail.com>
1915 * config/i386/predicates.md (add_comparison_operator): New predicate.
1916 * config/i386/i386.md (compare->add splitter): New splitters.
1918 2020-05-06 Richard Biener <rguenther@suse.de>
1920 * tree-vectorizer.h (vect_transform_slp_perm_load): Adjust.
1921 * tree-vect-data-refs.c (vect_slp_analyze_node_dependences):
1922 Remove slp_instance parameter, just iterate over all scalar stmts.
1923 (vect_slp_analyze_instance_dependence): Adjust and likewise.
1924 * tree-vect-slp.c (vect_bb_slp_scalar_cost): Remove unused BB
1926 (vect_schedule_slp): Just iterate over all scalar stmts.
1927 (vect_supported_load_permutation_p): Adjust.
1928 (vect_transform_slp_perm_load): Remove slp_instance parameter,
1929 instead use the number of lanes in the node as group size.
1930 * tree-vect-stmts.c (vect_model_load_cost): Get vectorization
1931 factor instead of slp_instance as parameter.
1932 (vectorizable_load): Adjust.
1934 2020-05-06 Andreas Schwab <schwab@suse.de>
1936 * config/aarch64/driver-aarch64.c: Include "aarch64-protos.h".
1937 (aarch64_get_extension_string_for_isa_flags): Don't declare.
1939 2020-05-06 Richard Biener <rguenther@suse.de>
1942 * cfgloopmanip.c (create_preheader): Require non-complex
1943 preheader edge for CP_SIMPLE_PREHEADERS.
1945 2020-05-06 Richard Biener <rguenther@suse.de>
1947 PR tree-optimization/94963
1948 * tree-ssa-loop-im.c (execute_sm_if_changed): Remove
1949 no-warning marking of the conditional store.
1950 (execute_sm): Instead mark the uninitialized state
1951 on loop entry to be not warned about.
1953 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
1955 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET,
1956 OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros.
1957 * config.gcc: Add tsxldtrkintrin.h to extra_headers.
1958 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
1960 * config/i386/i386-builtin.def: Add new builtins.
1961 * config/i386/i386-c.c (ix86_target_macros_internal): Define
1963 * config/i386/i386-options.c (ix86_target_string): Add
1965 (ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk.
1966 * config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P):
1968 * config/i386/i386.md (define_c_enum "unspec"): Add
1969 UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK.
1970 (TSXLDTRK): New define_int_iterator.
1971 ("<tsxldtrk>"): New define_insn.
1972 * config/i386/i386.opt: Add -mtsxldtrk.
1973 * config/i386/immintrin.h: Include tsxldtrkintrin.h.
1974 * config/i386/tsxldtrkintrin.h: New.
1975 * doc/invoke.texi: Document -mtsxldtrk.
1977 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1979 PR tree-optimization/94921
1980 * match.pd (~(~X - Y) -> X + Y, ~(~X + Y) -> X - Y): New
1983 2020-05-06 Richard Biener <rguenther@suse.de>
1985 PR tree-optimization/94965
1986 * tree-vect-stmts.c (vectorizable_load): Fix typo.
1988 2020-05-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1990 * doc/install.texi: Replace Sun with Solaris as appropriate.
1991 (Tools/packages necessary for building GCC, Perl version between
1992 5.6.1 and 5.6.24): Remove Solaris 8 reference.
1993 (Installing GCC: Binaries, Solaris 2 (SPARC, Intel)): Remove
1995 (Specific, i?86-*-solaris2*): Update version references for
1996 Solaris 11.3 and later. Remove gas 2.26 caveat.
1997 (Specific, *-*-solaris2*): Update version references for
1998 Solaris 11.3 and later. Remove boehm-gc reference.
1999 Document GMP, MPFR caveats on Solaris 11.3.
2000 (Specific, sparc-sun-solaris2*): Update Solaris 9 references.
2001 (Specific, sparc64-*-solaris2*): Likewise.
2002 Document --build requirement.
2004 2020-05-06 Jakub Jelinek <jakub@redhat.com>
2007 * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use
2008 TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags.
2010 PR rtl-optimization/94873
2011 * combine.c (combine_instructions): Don't optimize using REG_EQUAL
2012 note if SET_SRC (set) has side-effects.
2014 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
2015 Wei Xiao <wei3.xiao@intel.com>
2017 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
2018 OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
2019 (ix86_handle_option): Handle -mserialize.
2020 * config.gcc (serializeintrin.h): New header file.
2021 * config/i386/cpuid.h (bit_SERIALIZE): New bit.
2022 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
2024 * config/i386/i386-builtin.def: Add new builtin.
2025 * config/i386/i386-c.c (__SERIALIZE__): New macro.
2026 * config/i386/i386-options.c (ix86_target_opts_isa2_opts):
2028 * (ix86_valid_target_attribute_inner_p): Add target attribute
2030 * config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):
2032 * config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.
2033 (serialize): New define_insn.
2034 * config/i386/i386.opt (mserialize): New option
2035 * config/i386/immintrin.h: Include serailizeintrin.h.
2036 * config/i386/serializeintrin.h: New header file.
2037 * doc/invoke.texi: Add documents for -mserialize.
2039 2020-05-06 Richard Biener <rguenther@suse.de>
2041 * tree-cfg.c (verify_gimple_assign_unary): Adjust integer
2042 to/from pointer conversion checking.
2044 2020-05-05 Michael Meissner <meissner@linux.ibm.com>
2046 * config/rs6000/rs6000-builtin.def: Delete changes meant for a
2048 * config/rs6000/rs6000-c.c: Likewise.
2049 * config/rs6000/rs6000-call.c: Likewise.
2050 * config/rs6000/rs6000.c: Likewise.
2052 2020-05-05 Sebastian Huber <sebastian.huber@embedded-brains.de>
2054 * config/rtems.h (RTEMS_STARTFILE_SPEC): Define if undefined.
2055 (RTEMS_ENDFILE_SPEC): Likewise.
2056 (STARTFILE_SPEC): Update comment. Add RTEMS_STARTFILE_SPEC.
2057 (ENDFILE_SPEC): Add RTEMS_ENDFILE_SPEC.
2058 (LIB_SPECS): Support -nodefaultlibs option.
2059 * config/or1k/rtems.h (RTEMS_STARTFILE_SPEC): Define.
2060 (RTEMS_ENDFILE_SPEC): Likewise.
2061 * config/rs6000/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
2062 (RTEMS_ENDFILE_SPEC): Likewise.
2063 * config/v850/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
2064 (RTEMS_ENDFILE_SPEC): Likewise.
2066 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
2068 * config/pru/pru.c (pru_hard_regno_call_part_clobbered): Remove.
2069 (TARGET_HARD_REGNO_CALL_PART_CLOBBERED): Remove.
2071 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
2073 * config/pru/pru.h: Mark R3.w0 as caller saved.
2075 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
2077 * config/pru/pru.c (pru_emit_doloop): Use new gen_doloop_end_internal
2078 and gen_doloop_begin_internal.
2079 (pru_reorg_loop): Use gen_pruloop with mode.
2080 * config/pru/pru.md: Use new @insn syntax.
2082 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
2084 * config/pru/pru.c (pru_print_operand): Fix fall through comment.
2086 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
2088 * config/i386/i386.md (fixuns_trunc<mode>si2): Use
2089 "clobber (scratch:M)" instad of "clobber (match_scratch:M N)".
2090 (addqi3_cconly_overflow): Ditto.
2091 (umulv<mode>4): Ditto.
2092 (<s>mul<mode>3_highpart): Ditto.
2093 (tls_global_dynamic_32): Ditto.
2094 (tls_local_dynamic_base_32): Ditto.
2101 (*adddi_4): Remove "m" constraint from scratch operand.
2102 (*add<mode>_4): Ditto.
2104 2020-05-05 Jakub Jelinek <jakub@redhat.com>
2106 PR rtl-optimization/94516
2107 * postreload.c (reload_cse_simplify): When replacing sp = sp + const
2108 with sp = reg, add REG_EQUAL note with sp + const.
2109 * combine-stack-adj.c (try_apply_stack_adjustment): Change return
2110 type from int to bool. Add LIVE and OTHER_INSN arguments. Undo
2111 postreload sp = sp + const to sp = reg optimization if needed and
2113 (combine_stack_adjustments_for_block): Add LIVE argument. Handle
2114 reg = sp insn with sp + const REG_EQUAL note. Adjust
2115 try_apply_stack_adjustment caller, call
2116 df_simulate_initialize_forwards and df_simulate_one_insn_forwards.
2117 (combine_stack_adjustments): Allocate and free LIVE bitmap,
2118 adjust combine_stack_adjustments_for_block caller.
2120 2020-05-05 Martin Liska <mliska@suse.cz>
2122 PR gcov-profile/93623
2123 * tree-cfg.c (stmt_can_terminate_bb_p): Update comment to reflect
2126 2020-05-05 Martin Liska <mliska@suse.cz>
2128 * opt-functions.awk (opt_args_non_empty): New function.
2129 * opt-read.awk: Use the function for various option arguments.
2131 2020-05-05 Martin Liska <mliska@suse.cz>
2134 * lto-wrapper.c (run_gcc): When using -flto=jobserver,
2135 report warning when the jobserver is not detected.
2137 2020-05-05 Martin Liska <mliska@suse.cz>
2139 PR gcov-profile/94636
2140 * gcov.c (main): Print total lines summary at the end.
2141 (generate_results): Expect file_name always being non-null.
2142 Print newline after intermediate file is printed in order to align with
2143 what we do for normal files.
2145 2020-05-05 Martin Liska <mliska@suse.cz>
2147 * dumpfile.c (dump_switch_p): Change return type
2148 and print option suggestion.
2149 * dumpfile.h: Change return type.
2150 * opts-global.c (handle_common_deferred_options):
2151 Move error into dump_switch_p function.
2153 2020-05-05 Martin Liska <mliska@suse.cz>
2156 * alloc-pool.h: Use const for some arguments.
2157 * bitmap.h: Likewise.
2158 * mem-stats.h: Likewise.
2159 * sese.h (get_entry_bb): Likewise.
2160 (get_exit_bb): Likewise.
2162 2020-05-05 Richard Biener <rguenther@suse.de>
2164 * tree-vect-slp.c (struct vdhs_data): New.
2165 (vect_detect_hybrid_slp): New walker.
2166 (vect_detect_hybrid_slp): Rewrite.
2168 2020-05-05 Richard Biener <rguenther@suse.de>
2171 * tree-ssa-structalias.c (ipa_pta_execute): Use
2172 varpool_node::externally_visible_p ().
2173 (refered_from_nonlocal_var): Likewise.
2175 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
2177 * gcc.c (LTO_PLUGIN_SPEC): Define if not already.
2178 (LINK_PLUGIN_SPEC): Execute LTO_PLUGIN_SPEC.
2179 * config/vxworks.h (LTO_PLUGIN_SPEC): Define.
2181 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
2183 * gimplify.c (gimplify_init_constructor): Do not put the constructor
2184 into static memory if it is not complete.
2186 2020-05-05 Richard Biener <rguenther@suse.de>
2188 PR tree-optimization/94949
2189 * tree-ssa-loop-im.c (execute_sm): Check whether we use
2190 the multithreaded model or always compute the stored value
2191 before eliding a load.
2193 2020-05-05 Alex Coplan <alex.coplan@arm.com>
2195 * config/aarch64/aarch64.md (*one_cmpl_zero_extend): New.
2197 2020-05-05 Jakub Jelinek <jakub@redhat.com>
2199 PR tree-optimization/94800
2200 * match.pd (X + (X << C) to X * (1 + (1 << C)),
2201 (X << C1) + (X << C2) to X * ((1 << C1) + (1 << C2))): New
2205 * config/i386/mmx.md (*vec_dupv4hi): Use xYw constraints instead of Yv.
2207 PR tree-optimization/94914
2208 * match.pd ((((type)A * B) >> prec) != 0 to .MUL_OVERFLOW(A, B) != 0):
2211 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
2213 * config/i386/i386.md (*testqi_ext_3): Use
2214 int_nonimmediate_operand instead of manual mode checks.
2215 (*x86_mov<SWI48:mode>cc_0_m1_neg_leu<SWI:mode>):
2216 Use int_nonimmediate_operand predicate. Rewrite
2217 define_insn_and_split pattern to a combine pass splitter.
2219 2020-05-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2221 * configure.ac <i[34567]86-*-*>: Add --32 to tls_as_opt on Solaris.
2222 * configure: Regenerate.
2224 2020-05-05 Jakub Jelinek <jakub@redhat.com>
2227 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
2228 ssse3_ph<plusminus_mnemonic>wv8hi3, ssse3_ph<plusminus_mnemonic>wv4hi3,
2229 avx2_ph<plusminus_mnemonic>dv8si3, ssse3_ph<plusminus_mnemonic>dv4si3,
2230 ssse3_ph<plusminus_mnemonic>dv2si3): Simplify RTL patterns.
2232 2020-05-04 Clement Chigot <clement.chigot@atos.net>
2233 David Edelsohn <dje.gcc@gmail.com>
2235 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Override explicit
2236 for fmodl, frexpl, ldexpl and modfl builtins.
2238 2020-05-04 Richard Sandiford <richard.sandiford@arm.com>
2241 * internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the
2242 chosen lhs is different from the gcall lhs.
2243 (expand_mask_load_optab_fn): Likewise.
2244 (expand_gather_load_optab_fn): Likewise.
2246 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
2249 * config/i386/i386.md (*neg<mode>_ccc): New insn pattern.
2250 (EQ compare->LTU compare splitter): New splitter.
2251 (NE compare->NEG splitter): Ditto.
2253 2020-05-04 Marek Polacek <polacek@redhat.com>
2256 2020-04-30 Marek Polacek <polacek@redhat.com>
2259 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
2260 (check_aligned_type): Check if TYPE_USER_ALIGN match.
2262 2020-05-04 Richard Biener <rguenther@suse.de>
2264 PR tree-optimization/93891
2265 * tree-ssa-sccvn.c (vn_reference_lookup_3): Fall back to
2266 the original reference tree for assessing access alignment.
2268 2020-05-04 Richard Biener <rguenther@suse.de>
2270 PR tree-optimization/39612
2271 * tree-ssa-loop-im.c (im_mem_ref::loaded): New member.
2272 (set_ref_loaded_in_loop): New.
2273 (mark_ref_loaded): Likewise.
2274 (gather_mem_refs_stmt): Call mark_ref_loaded for loads.
2275 (execute_sm): Avoid issueing a load when it was not there.
2276 (execute_sm_if_changed): Avoid issueing warnings for the
2279 2020-05-04 Martin Jambor <mjambor@suse.cz>
2282 * tree-inline.c (tree_function_versioning): Leave any type conversion
2283 of replacements to setup_one_parameter and its friend
2284 force_value_to_type.
2286 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
2289 * config/i386/predicates.md (shr_comparison_operator): New predicate.
2290 * config/i386/i386.md (compare->shr splitter): New splitters.
2292 2020-05-04 Jakub Jelinek <jakub@redhat.com>
2294 PR tree-optimization/94718
2295 * match.pd ((X < 0) != (Y < 0) into (X ^ Y) < 0): New simplification.
2297 PR tree-optimization/94718
2298 * match.pd (bitop (convert @0) (convert? @1)): For GIMPLE, if we can,
2299 replace two nop conversions on bit_{and,ior,xor} argument
2300 and result with just one conversion on the result or another argument.
2302 PR tree-optimization/94718
2303 * fold-const.c (fold_binary_loc): Move (X & C) eqne (Y & C)
2304 -> (X ^ Y) & C eqne 0 optimization to ...
2305 * match.pd ((X & C) op (Y & C) into (X ^ Y) & C op 0): ... here.
2307 * opts.c (get_option_html_page): Instead of hardcoding a list of
2308 options common between C/C++ and Fortran only use gfortran/
2309 documentation for warnings that have CL_Fortran set but not
2312 2020-05-03 Uroš Bizjak <ubizjak@gmail.com>
2314 * config/i386/i386-expand.c (ix86_expand_int_movcc):
2315 Use plus_constant instead of gen_rtx_PLUS with GEN_INT.
2316 (emit_memmov): Ditto.
2317 (emit_memset): Ditto.
2318 (ix86_expand_strlensi_unroll_1): Ditto.
2319 (release_scratch_register_on_entry): Ditto.
2320 (gen_frame_set): Ditto.
2321 (ix86_emit_restore_reg_using_pop): Ditto.
2322 (ix86_emit_outlined_ms2sysv_restore): Ditto.
2323 (ix86_expand_epilogue): Ditto.
2324 (ix86_expand_split_stack_prologue): Ditto.
2325 * config/i386/i386.md (push immediate splitter): Ditto.
2329 2020-05-02 Iain Sandoe <iain@sandoe.co.uk>
2331 PR translation/93861
2332 * config/darwin-driver.c (darwin_driver_init): Adjust spelling in
2335 2020-05-02 Jakub Jelinek <jakub@redhat.com>
2337 * config/tilegx/tilegx.md
2338 (insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>): Use <I124MODE:n>
2339 rather than just <n>.
2341 2020-05-01 H.J. Lu <hongjiu.lu@intel.com>
2344 * cfgexpand.c (pass_expand::execute): Set crtl->patch_area_size
2345 and crtl->patch_area_entry.
2346 * emit-rtl.h (rtl_data): Add patch_area_size and patch_area_entry.
2347 * opts.c (common_handle_option): Limit
2348 function_entry_patch_area_size and function_entry_patch_area_start
2349 to USHRT_MAX. Fix a typo in error message.
2350 * varasm.c (assemble_start_function): Use crtl->patch_area_size
2351 and crtl->patch_area_entry.
2352 * doc/invoke.texi: Document the maximum value for
2353 -fpatchable-function-entry.
2355 2020-05-01 Iain Sandoe <iain@sandoe.co.uk>
2357 * config/i386/darwin.h: Repair SUBTARGET_INIT_BUILTINS.
2358 Override SUBTARGET_SHADOW_OFFSET macro.
2360 2020-05-01 Andreas Tobler <andreast@gcc.gnu.org>
2362 * config/i386/i386.h: Define a new macro: SUBTARGET_SHADOW_OFFSET.
2363 * config/i386/i386.c (ix86_asan_shadow_offset): Use this macro.
2364 * config/i386/darwin.h: Override the SUBTARGET_SHADOW_OFFSET macro.
2365 * config/i386/freebsd.h: Likewise.
2366 * config/freebsd.h (LIBASAN_EARLY_SPEC): Define.
2367 LIBTSAN_EARLY_SPEC): Likewise. (LIBLSAN_EARLY_SPEC): Likewise.
2369 2020-04-30 Alexandre Oliva <oliva@adacore.com>
2371 * doc/sourcebuild.texi (Effective-Target Keywords): Document
2372 the newly-introduced fileio effective target.
2374 2020-04-30 Richard Sandiford <richard.sandiford@arm.com>
2376 PR rtl-optimization/94740
2377 * cse.c (cse_process_notes_1): Replace with...
2378 (cse_process_note_1): ...this new function, acting as a
2379 simplify_replace_fn_rtx callback to process_note. Handle only
2380 REGs and MEMs directly. Validate the MEM if cse_process_note
2381 changes its address.
2382 (cse_process_notes): Replace with...
2383 (cse_process_note): ...this new function.
2384 (cse_extended_basic_block): Update accordingly, iterating over
2385 the register notes and passing individual notes to cse_process_note.
2387 2020-04-30 Carl Love <cel@us.ibm.com>
2389 * config/rs6000/emmintrin.h (_mm_movemask_epi8): Fix comment.
2391 2020-04-30 Martin Jambor <mjambor@suse.cz>
2394 * cgraph.c (clone_of_p): Also consider thunks whih had their bodies
2395 saved by the inliner and thunks which had their call inlined.
2396 * ipa-inline-transform.c (save_inline_function_body): Fill in
2397 former_clone_of of new body holders.
2399 2020-04-30 Jakub Jelinek <jakub@redhat.com>
2401 * BASE-VER: Set to 11.0.0.
2403 2020-04-30 Jonathan Wakely <jwakely@redhat.com>
2405 * pretty-print.c (pp_take_prefix): Fix spelling in comment.
2407 2020-04-30 Marek Polacek <polacek@redhat.com>
2410 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
2411 (check_aligned_type): Check if TYPE_USER_ALIGN match.
2413 2020-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2415 * config/aarch64/aarch64.h (TARGET_OUTLINE_ATOMICS): Define.
2416 * config/aarch64/aarch64.opt (moutline-atomics): Change to Int variable.
2417 * doc/invoke.texi (moutline-atomics): Document as on by default.
2419 2020-04-30 Szabolcs Nagy <szabolcs.nagy@arm.com>
2422 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Remove
2423 the check for NOTE_INSN_DELETED_LABEL.
2425 2020-04-30 Jakub Jelinek <jakub@redhat.com>
2427 * configure.ac (--with-documentation-root-url,
2428 --with-changes-root-url): Diagnose URL not ending with /,
2429 use AC_DEFINE_UNQUOTED instead of AC_SUBST.
2430 * opts.h (get_changes_url): Remove.
2431 * opts.c (get_changes_url): Remove.
2432 * Makefile.in (CFLAGS-opts.o): Don't add -DDOCUMENTATION_ROOT_URL
2433 or -DCHANGES_ROOT_URL.
2434 * doc/install.texi (--with-documentation-root-url,
2435 --with-changes-root-url): Document.
2436 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Don't call
2437 get_changes_url and free, change url variable type to const char * and
2438 set it to CHANGES_ROOT_URL "gcc-10/changes.html#empty_base".
2439 * config/s390/s390.c (s390_function_arg_vector,
2440 s390_function_arg_float): Likewise.
2441 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
2443 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
2445 * config.in: Regenerate.
2446 * configure: Regenerate.
2448 2020-04-30 Christophe Lyon <christophe.lyon@linaro.org>
2451 * config/arm/arm.c (isr_attribute_args): Remove duplicate entries.
2453 2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
2455 * config/s390/constraints.md ("j>f", "jb4"): New constraints.
2456 * config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix
2458 * config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a
2460 ("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst.
2461 Change constraint for vlrl/vstrl to jb4.
2463 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2465 * var-tracking.c (vt_initialize): Move variables pre and post
2466 into inner block and initialize both in order to fix warning
2467 about uninitialized use. Remove unnecessary checks for
2468 frame_pointer_needed.
2470 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2472 * toplev.c (output_stack_usage_1): Ensure that first
2473 argument to fprintf is not null.
2475 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2477 * configure.ac (-with-changes-root-url): New configure option,
2478 defaulting to https://gcc.gnu.org/.
2479 * Makefile.in (CFLAGS-opts.o): Define CHANGES_ROOT_URL for
2481 * pretty-print.c (get_end_url_string): New function.
2482 (pp_format): Handle %{ and %} for URLs.
2483 (pp_begin_url): Use pp_string instead of pp_printf.
2484 (pp_end_url): Use get_end_url_string.
2485 * opts.h (get_changes_url): Declare.
2486 * opts.c (get_changes_url): New function.
2487 * config/rs6000/rs6000-call.c: Include opts.h.
2488 (rs6000_discover_homogeneous_aggregate): Use %{in GCC 10.1%} instead
2489 of just in GCC 10.1 in diagnostics and add URL.
2490 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Likewise.
2491 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
2493 * config/s390/s390.c (s390_function_arg_vector,
2494 s390_function_arg_float): Likewise.
2495 * configure: Regenerated.
2498 * config/s390/s390.c (s390_function_arg_vector,
2499 s390_function_arg_float): Use DECL_FIELD_ABI_IGNORED instead of
2500 cxx17_empty_base_field_p. In -Wpsabi diagnostics use the type
2501 passed to the function rather than the type of the single element.
2502 Rename cxx17_empty_base_seen variable to empty_base_seen, change
2503 type to int, and adjust diagnostics depending on if the field
2504 has [[no_unique_attribute]] or not.
2507 * config/i386/avx512bwintrin.h (_mm512_alignr_epi8,
2508 _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands
2509 used in casts into parens.
2510 * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph,
2511 _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph,
2512 _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph,
2513 _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask,
2514 _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask,
2515 _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask,
2516 _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise.
2517 * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8,
2518 _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8,
2519 _mm256_mask_cmp_epu8_mask): Likewise.
2520 * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph,
2521 _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise.
2522 * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise.
2523 * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise.
2526 * config/i386/avx2intrin.h (_mm_mask_i32gather_pd,
2527 _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd,
2528 _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps,
2529 _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps,
2530 _mm256_mask_i64gather_ps, _mm_i32gather_epi64,
2531 _mm_mask_i32gather_epi64, _mm256_i32gather_epi64,
2532 _mm256_mask_i32gather_epi64, _mm_i64gather_epi64,
2533 _mm_mask_i64gather_epi64, _mm256_i64gather_epi64,
2534 _mm256_mask_i64gather_epi64, _mm_i32gather_epi32,
2535 _mm_mask_i32gather_epi32, _mm256_i32gather_epi32,
2536 _mm256_mask_i32gather_epi32, _mm_i64gather_epi32,
2537 _mm_mask_i64gather_epi32, _mm256_i64gather_epi32,
2538 _mm256_mask_i64gather_epi32): Surround macro parameter uses with
2540 (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd,
2541 _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps,
2542 _mm_i64gather_ps, _mm256_i64gather_ps): Likewise. Don't use
2543 as mask vector containing -1.0 or -1.0f elts, but instead vector
2544 with all bits set using _mm*_cmpeq_p? with zero operands.
2545 * config/i386/avx512fintrin.h (_mm512_i32gather_ps,
2546 _mm512_mask_i32gather_ps, _mm512_i32gather_pd,
2547 _mm512_mask_i32gather_pd, _mm512_i64gather_ps,
2548 _mm512_mask_i64gather_ps, _mm512_i64gather_pd,
2549 _mm512_mask_i64gather_pd, _mm512_i32gather_epi32,
2550 _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64,
2551 _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32,
2552 _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64,
2553 _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps,
2554 _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd,
2555 _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps,
2556 _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd,
2557 _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32,
2558 _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64,
2559 _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32,
2560 _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64,
2561 _mm512_mask_i64scatter_epi64): Surround macro parameter uses with
2563 * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd,
2564 _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd,
2565 _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd,
2566 _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd,
2567 _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd,
2568 _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd,
2569 _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd,
2570 _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd,
2571 _mm512_mask_prefetch_i64scatter_ps): Likewise.
2572 * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps,
2573 _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd,
2574 _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps,
2575 _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd,
2576 _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32,
2577 _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64,
2578 _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32,
2579 _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64,
2580 _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps,
2581 _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps,
2582 _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd,
2583 _mm_mask_i32scatter_pd, _mm256_i64scatter_ps,
2584 _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps,
2585 _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd,
2586 _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32,
2587 _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32,
2588 _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64,
2589 _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64,
2590 _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32,
2591 _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32,
2592 _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64,
2593 _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64,
2594 _mm_mask_i64scatter_epi64): Likewise.
2596 2020-04-29 Jeff Law <law@redhat.com>
2598 * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific
2599 division instructions are 4 bytes long.
2601 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2604 * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use
2605 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
2606 fenv_var, fenv_clear and old_fenv variables. For fenv_addr
2607 take address of TARGET_EXPR of fenv_var with void_node initializer.
2610 2020-04-29 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2612 PR tree-optimization/94774
2613 * gimple-ssa-sprintf.c (try_substitute_return_value): Initialize
2616 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2618 * calls.h (cxx17_empty_base_field_p): Turn into a function declaration.
2619 * calls.c (cxx17_empty_base_field_p): New function. Check
2620 DECL_ARTIFICIAL and RECORD_OR_UNION_TYPE_P in addition to the
2623 2020-04-29 H.J. Lu <hongjiu.lu@intel.com>
2626 * config/i386/i386-options.c (ix86_set_indirect_branch_type):
2627 Allow -fcf-protection with -mindirect-branch=thunk-extern and
2628 -mfunction-return=thunk-extern.
2629 * doc/invoke.texi: Update notes for -fcf-protection=branch with
2630 -mindirect-branch=thunk-extern and -mindirect-return=thunk-extern.
2632 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2634 * doc/sourcebuild.texi: Add missing arm_arch_v8a_hard_ok anchor.
2636 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2638 * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
2639 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
2640 fenv_var and new_fenv_var.
2642 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2644 * doc/sourcebuild.texi (arm_arch_v8a_hard_ok): Document new
2645 effective-target keyword.
2646 (arm_arch_v8a_hard_multilib): Likewise.
2647 (arm_arch_v8a_hard): Document new dg-add-options keyword.
2648 * config/arm/arm.c (arm_return_in_memory): Note that the APCS
2649 code is deprecated and has not been updated to handle
2650 DECL_FIELD_ABI_IGNORED.
2651 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
2652 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
2653 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
2654 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
2655 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
2656 something actually is a HFA or HVA. Record whether we see a
2657 [[no_unique_address]] field that previous GCCs would not have
2658 ignored in this way.
2659 (aapcs_vfp_is_call_or_return_candidate): Update the calls to
2660 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
2661 [[no_unique_address]] case. Use TYPE_MAIN_VARIANT in the
2662 diagnostic messages.
2663 (arm_needs_doubleword_align): Add a comment explaining why we
2664 consider even zero-sized fields.
2666 2020-04-29 Richard Biener <rguenther@suse.de>
2667 Li Zekun <lizekun1@huawei.com>
2670 * tree.c (component_ref_size): Guard against error_mark_node
2671 DECL_INITIAL as it happens with LTO.
2673 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2675 * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add a
2676 comment explaining why we consider even zero-sized fields.
2677 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
2678 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
2679 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
2680 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
2681 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
2682 something actually is a HFA or HVA. Record whether we see a
2683 [[no_unique_address]] field that previous GCCs would not have
2684 ignored in this way.
2685 (aarch64_vfp_is_call_or_return_candidate): Add a parameter to say
2686 whether diagnostics should be suppressed. Update the calls to
2687 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
2688 [[no_unique_address]] case.
2689 (aarch64_return_in_msb): Update call accordingly, never silencing
2691 (aarch64_function_value): Likewise.
2692 (aarch64_return_in_memory_1): Likewise.
2693 (aarch64_init_cumulative_args): Likewise.
2694 (aarch64_gimplify_va_arg_expr): Likewise.
2695 (aarch64_pass_by_reference_1): Take a CUMULATIVE_ARGS pointer and
2696 use it to decide whether arch64_vfp_is_call_or_return_candidate
2698 (aarch64_pass_by_reference): Update calls accordingly.
2699 (aarch64_vfp_is_call_candidate): Use the CUMULATIVE_ARGS argument
2700 to decide whether arch64_vfp_is_call_or_return_candidate should be
2703 2020-04-29 Haijian Zhang <z.zhanghaijian@huawei.com>
2706 * config/aarch64/aarch64-builtins.c
2707 (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of
2708 MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and
2711 2020-04-29 Thomas Schwinge <thomas@codesourcery.com>
2713 * configure.ac <$enable_offload_targets>: Do parsing as done
2715 * configure: Regenerate.
2717 * configure.ac <$enable_offload_targets>: 'amdgcn' is 'gcn'.
2718 * configure: Regenerate.
2721 * rtlanal.c (set_noop_p): Handle non-constant selectors.
2724 * common/config/gcn/gcn-common.c (gcn_except_unwind_info): New
2726 (TARGET_EXCEPT_UNWIND_INFO): Define.
2728 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2731 * config/gcn/gcn.md (*mov<mode>_insn): Use
2732 'reg_overlap_mentioned_p' to check for overlap.
2735 * config/ia64/ia64.c (hfa_element_mode): Use DECL_FIELD_ABI_IGNORED
2736 instead of cxx17_empty_base_field_p.
2739 * tree-core.h (tree_decl_common): Note decl_flag_0 used for
2740 DECL_FIELD_ABI_IGNORED.
2741 * tree.h (DECL_FIELD_ABI_IGNORED): Define.
2742 * calls.h (cxx17_empty_base_field_p): Change into a temporary
2743 macro, check DECL_FIELD_ABI_IGNORED flag with no "no_unique_address"
2745 * calls.c (cxx17_empty_base_field_p): Remove.
2746 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Handle
2747 DECL_FIELD_ABI_IGNORED.
2748 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
2749 * lto-streamer-out.c (hash_tree): Likewise.
2750 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Rename
2751 cxx17_empty_base_seen to empty_base_seen, change type to int *,
2752 adjust recursive calls, use DECL_FIELD_ABI_IGNORED instead of
2753 cxx17_empty_base_field_p, if "no_unique_address" attribute is
2754 present, propagate that to the caller too.
2755 (rs6000_discover_homogeneous_aggregate): Adjust
2756 rs6000_aggregate_candidate caller, emit different diagnostics
2757 when c++17 empty base fields are present and when empty
2758 [[no_unique_address]] fields are present.
2759 * config/rs6000/rs6000.c (rs6000_special_round_type_align,
2760 darwin_rs6000_special_round_type_align): Skip DECL_FIELD_ABI_IGNORED
2763 2020-04-29 Richard Biener <rguenther@suse.de>
2765 * tree-ssa-loop-im.c (ref_always_accessed::operator ()):
2766 Just check whether the stmt stores.
2768 2020-04-28 Alexandre Oliva <oliva@adacore.com>
2771 * config/rs6000/rs6000.md (rs6000_mffsl): Copy result to
2772 output operand in emulation. Don't overwrite pseudos.
2774 2020-04-28 Jeff Law <law@redhat.com>
2776 * config/h8300/h8300.md (H8/SX mult patterns): All H8/SX specific
2777 multiply patterns are 4 bytes long.
2779 2020-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2781 * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option.
2782 * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option.
2784 2020-04-28 Matthew Malcomson <matthew.malcomson@arm.com>
2785 Jakub Jelinek <jakub@redhat.com>
2788 * config/arm/arm.c (aapcs_vfp_sub_candidate): Account for C++17 empty
2789 base class artificial fields.
2790 (aapcs_vfp_is_call_or_return_candidate): Warn when PCS ABI
2791 decision is different after this fix.
2793 2020-04-28 David Malcolm <dmalcolm@redhat.com>
2799 * doc/invoke.texi (Static Analyzer Options): Remove
2800 -Wanalyzer-use-of-uninitialized-value.
2801 (-Wno-analyzer-use-of-uninitialized-value): Remove item.
2803 2020-04-28 Jakub Jelinek <jakub@redhat.com>
2805 PR tree-optimization/94809
2806 * tree.c (build_call_expr_internal_loc_array): Call
2807 process_call_operands.
2809 2020-04-27 Anton Youdkevitch <anton.youdkevitch@bell-sw.com>
2811 * config/aarch64/aarch64-cores.def (thunderx3t110): Add the chip name.
2812 * config/aarch64/aarch64-tune.md: Regenerate.
2813 * config/aarch64/aarch64.c (thunderx3t110_addrcost_table): Define.
2814 (thunderx3t110_regmove_cost): Likewise.
2815 (thunderx3t110_vector_cost): Likewise.
2816 (thunderx3t110_prefetch_tune): Likewise.
2817 (thunderx3t110_tunings): Likewise.
2818 * config/aarch64/aarch64-cost-tables.h (thunderx3t110_extra_costs):
2820 * config/aarch64/thunderx3t110.md: New file.
2821 * config/aarch64/aarch64.md: Include thunderx3t110.md.
2822 * doc/invoke.texi (AArch64 options): Add thunderx3t110.
2824 2020-04-28 Jakub Jelinek <jakub@redhat.com>
2827 * config/s390/s390.c (s390_function_arg_vector,
2828 s390_function_arg_float): Emit -Wpsabi diagnostics if the ABI changed.
2830 2020-04-28 Richard Sandiford <richard.sandiford@arm.com>
2832 PR tree-optimization/94727
2833 * tree-vect-stmts.c (vect_is_simple_cond): If both comparison
2834 operands are invariant booleans, use the mask type associated with the
2835 STMT_VINFO_VECTYPE. Use !slp_node instead of !vectype to exclude SLP.
2836 (vectorizable_condition): Pass vectype unconditionally to
2837 vect_is_simple_cond.
2839 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2842 * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use
2843 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
2844 sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var.
2846 2020-04-27 David Malcolm <dmalcolm@redhat.com>
2849 * configure.ac (DOCUMENTATION_ROOT_URL): Drop trailing "gcc/" from
2850 default value, so that it can by supplied by get_option_html_page.
2851 * configure: Regenerate.
2852 * opts.c: Include "selftest.h".
2853 (get_option_html_page): New function.
2854 (get_option_url): Use it. Reformat to place comments next to the
2855 expressions they refer to.
2856 (selftest::test_get_option_html_page): New.
2857 (selftest::opts_c_tests): New.
2858 * selftest-run-tests.c (selftest::run_tests): Call
2859 selftest::opts_c_tests.
2860 * selftest.h (selftest::opts_c_tests): New decl.
2862 2020-04-27 Richard Sandiford <richard.sandiford@arm.com>
2864 * config/arm/arm-builtins.c (arm_expand_builtin_args): Only apply
2865 UINTVAL to CONST_INTs.
2867 2020-04-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2869 * config/arm/constraints.md (e): Remove constraint.
2870 (Te): Define constraint.
2871 * config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in
2872 operand 0 from "e" to "Te".
2873 (vaddvaq_<supf><mode>): Likewise.
2874 (vaddvq_p_<supf><mode>): Likewise.
2875 (vmladavq_<supf><mode>): Likewise.
2876 (vmladavxq_s<mode>): Likewise.
2877 (vmlsdavq_s<mode>): Likewise.
2878 (vmlsdavxq_s<mode>): Likewise.
2879 (vaddvaq_p_<supf><mode>): Likewise.
2880 (vmladavaq_<supf><mode>): Likewise.
2881 (vmladavq_p_<supf><mode>): Likewise.
2882 (vmladavxq_p_s<mode>): Likewise.
2883 (vmlsdavq_p_s<mode>): Likewise.
2884 (vmlsdavxq_p_s<mode>): Likewise.
2885 (vmlsdavaxq_s<mode>): Likewise.
2886 (vmlsdavaq_s<mode>): Likewise.
2887 (vmladavaxq_s<mode>): Likewise.
2888 (vmladavaq_p_<supf><mode>): Likewise.
2889 (vmladavaxq_p_s<mode>): Likewise.
2890 (vmlsdavaq_p_s<mode>): Likewise.
2891 (vmlsdavaxq_p_s<mode>): Likewise.
2893 2020-04-27 Andre Vieira <andre.simoesdiasvieira@arm.com>
2895 * config/arm/arm.c (output_move_neon): Only get the first operand if
2898 2020-04-27 Felix Yang <felix.yang@huawei.com>
2900 PR tree-optimization/94784
2901 * tree-ssa-forwprop.c (simplify_vector_constructor): Flip the
2902 assert around so that it checks that the two vectors have equal
2903 TYPE_VECTOR_SUBPARTS and that converting the corresponding element
2904 types is a useless_type_conversion_p.
2906 2020-04-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
2909 * dwarf2cfi.c (struct GTY): Add ra_mangled.
2910 (cfi_row_equal_p): Check ra_mangled.
2911 (dwarf2out_frame_debug_cfa_window_save): Remove the argument,
2912 this only handles the sparc logic now.
2913 (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for
2914 the aarch64 specific logic.
2915 (dwarf2out_frame_debug): Update to use the new subroutines.
2916 (change_cfi_row): Check ra_mangled.
2918 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2921 * config/s390/s390.c (s390_function_arg_vector,
2922 s390_function_arg_float): Ignore cxx17_empty_base_field_p fields.
2924 2020-04-27 Jiufu Guo <guojiufu@cn.ibm.com>
2926 * common/config/rs6000/rs6000-common.c
2927 (rs6000_option_optimization_table) [OPT_LEVELS_ALL]: Remove turn off
2929 * config/rs6000/rs6000.c (rs6000_option_override_internal): Avoid to
2932 2020-04-27 Martin Liska <mliska@suse.cz>
2935 * cgraph.h (cgraph_node::can_remove_if_no_direct_calls_and_refs_p):
2936 Do not remove ifunc_resolvers in remove unreachable nodes in LTO.
2938 2020-04-27 Xiong Hu Luo <luoxhu@linux.ibm.com>
2941 * config/rs6000/rs6000-logue.c (frame_pointer_needed_indeed):
2943 (rs6000_emit_prologue_components):
2944 Check with frame_pointer_needed_indeed.
2945 (rs6000_emit_epilogue_components): Likewise.
2946 (rs6000_emit_prologue): Likewise.
2947 (rs6000_emit_epilogue): Set frame_pointer_needed_indeed.
2949 2020-04-25 David Edelsohn <dje.gcc@gmail.com>
2951 * config/rs6000/rs6000-logue.c (rs6000_stack_info): Don't push a
2952 stack frame when debugging and flag_compare_debug is enabled.
2954 2020-04-25 Michael Meissner <meissner@linux.ibm.com>
2956 * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to
2957 enable PC-relative addressing for -mcpu=future.
2958 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move
2959 after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS.
2960 * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined,
2961 suppress PC-relative addressing.
2962 (rs6000_option_override_internal): Split up error messages
2963 checking for -mprefixed and -mpcrel. Enable -mpcrel if the target
2966 2020-04-25 Jakub Jelinek <jakub@redhat.com>
2967 Richard Biener <rguenther@suse.de>
2969 PR tree-optimization/94734
2970 PR tree-optimization/89430
2971 * tree-ssa-phiopt.c: Include tree-eh.h.
2972 (cond_store_replacement): Return false if an automatic variable
2973 access could trap. If -fstore-data-races, don't return false
2974 just because an automatic variable is addressable.
2976 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2978 * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
2980 (add<mode>_sext_dup2_exec): Likewise.
2982 2020-04-24 Segher Boessenkool <segher@kernel.crashing.org>
2985 * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little
2986 endian byteshift_val calculation.
2988 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2990 * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
2992 2020-04-24 Richard Sandiford <richard.sandiford@arm.com>
2994 * config/aarch64/arm_sve.h: Add a comment.
2996 2020-04-24 Haijian Zhang <z.zhanghaijian@huawei.com>
2998 PR rtl-optimization/94708
2999 * combine.c (simplify_if_then_else): Add check for
3000 !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode).
3002 2020-04-23 Martin Sebor <msebor@redhat.com>
3005 * common.opt (-Wno-frame-larger-than): New option.
3006 (-Wno-larger-than, -Wno-stack-usage): Same.
3008 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
3010 * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands
3012 (mov<mode>_exec): Likewise.
3013 (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec.
3014 (<convop><mode><vndi>2_exec): Likewise.
3016 2019-04-23 Eric Botcazou <ebotcazou@adacore.com>
3018 PR tree-optimization/94717
3019 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one
3020 of the stores doesn't have the same landing pad number as the first.
3021 (coalesce_immediate_stores): Do not try to coalesce the store using
3022 bswap if it doesn't have the same landing pad number as the first.
3024 2020-04-23 Bill Schmidt <wschmidt@linux.ibm.com>
3026 * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
3027 Replace outdated link to ELFv2 ABI.
3029 2020-04-23 Jakub Jelinek <jakub@redhat.com>
3032 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx
3036 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs
3037 temporarily with non-final second operand and updating it later,
3038 push COMPOUND_EXPRs into a vector and process it in reverse,
3039 creating COMPOUND_EXPRs with the final operands.
3041 2020-04-23 Szabolcs Nagy <szabolcs.nagy@arm.com>
3044 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap
3045 bti c and bti j handling.
3047 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
3048 Thomas Schwinge <thomas@codesourcery.com>
3052 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on
3053 t_async and the wait arguments.
3055 2020-04-23 Richard Sandiford <richard.sandiford@arm.com>
3057 PR tree-optimization/94727
3058 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when
3059 comparing invariant scalar booleans.
3061 2020-04-23 Matthew Malcomson <matthew.malcomson@arm.com>
3062 Jakub Jelinek <jakub@redhat.com>
3065 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17
3066 empty base class artificial fields.
3067 (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is
3068 different after this fix.
3070 2020-04-23 Jakub Jelinek <jakub@redhat.com>
3073 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
3074 Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check
3075 if the same type has been diagnosed most recently already.
3077 2020-04-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3079 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's
3081 (__arm_vbicq_n_s16): Likewise.
3082 (__arm_vbicq_n_u32): Likewise.
3083 (__arm_vbicq_n_s32): Likewise.
3084 (__arm_vbicq): Likewise.
3085 (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype.
3086 (__arm_vbicq_n_s32): Likewise.
3087 (__arm_vbicq_n_u16): Likewise.
3088 (__arm_vbicq_n_u32): Likewise.
3089 (__arm_vdupq_m_n_s8): Likewise.
3090 (__arm_vdupq_m_n_s16): Likewise.
3091 (__arm_vdupq_m_n_s32): Likewise.
3092 (__arm_vdupq_m_n_u8): Likewise.
3093 (__arm_vdupq_m_n_u16): Likewise.
3094 (__arm_vdupq_m_n_u32): Likewise.
3095 (__arm_vdupq_m_n_f16): Likewise.
3096 (__arm_vdupq_m_n_f32): Likewise.
3097 (__arm_vldrhq_gather_offset_s16): Likewise.
3098 (__arm_vldrhq_gather_offset_s32): Likewise.
3099 (__arm_vldrhq_gather_offset_u16): Likewise.
3100 (__arm_vldrhq_gather_offset_u32): Likewise.
3101 (__arm_vldrhq_gather_offset_f16): Likewise.
3102 (__arm_vldrhq_gather_offset_z_s16): Likewise.
3103 (__arm_vldrhq_gather_offset_z_s32): Likewise.
3104 (__arm_vldrhq_gather_offset_z_u16): Likewise.
3105 (__arm_vldrhq_gather_offset_z_u32): Likewise.
3106 (__arm_vldrhq_gather_offset_z_f16): Likewise.
3107 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
3108 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
3109 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
3110 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
3111 (__arm_vldrhq_gather_shifted_offset_f16): Likewise.
3112 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
3113 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
3114 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
3115 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
3116 (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise.
3117 (__arm_vldrwq_gather_offset_s32): Likewise.
3118 (__arm_vldrwq_gather_offset_u32): Likewise.
3119 (__arm_vldrwq_gather_offset_f32): Likewise.
3120 (__arm_vldrwq_gather_offset_z_s32): Likewise.
3121 (__arm_vldrwq_gather_offset_z_u32): Likewise.
3122 (__arm_vldrwq_gather_offset_z_f32): Likewise.
3123 (__arm_vldrwq_gather_shifted_offset_s32): Likewise.
3124 (__arm_vldrwq_gather_shifted_offset_u32): Likewise.
3125 (__arm_vldrwq_gather_shifted_offset_f32): Likewise.
3126 (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise.
3127 (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise.
3128 (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise.
3129 (__arm_vdwdupq_x_n_u8): Likewise.
3130 (__arm_vdwdupq_x_n_u16): Likewise.
3131 (__arm_vdwdupq_x_n_u32): Likewise.
3132 (__arm_viwdupq_x_n_u8): Likewise.
3133 (__arm_viwdupq_x_n_u16): Likewise.
3134 (__arm_viwdupq_x_n_u32): Likewise.
3135 (__arm_vidupq_x_n_u8): Likewise.
3136 (__arm_vddupq_x_n_u8): Likewise.
3137 (__arm_vidupq_x_n_u16): Likewise.
3138 (__arm_vddupq_x_n_u16): Likewise.
3139 (__arm_vidupq_x_n_u32): Likewise.
3140 (__arm_vddupq_x_n_u32): Likewise.
3141 (__arm_vldrdq_gather_offset_s64): Likewise.
3142 (__arm_vldrdq_gather_offset_u64): Likewise.
3143 (__arm_vldrdq_gather_offset_z_s64): Likewise.
3144 (__arm_vldrdq_gather_offset_z_u64): Likewise.
3145 (__arm_vldrdq_gather_shifted_offset_s64): Likewise.
3146 (__arm_vldrdq_gather_shifted_offset_u64): Likewise.
3147 (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise.
3148 (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise.
3149 (__arm_vidupq_m_n_u8): Likewise.
3150 (__arm_vidupq_m_n_u16): Likewise.
3151 (__arm_vidupq_m_n_u32): Likewise.
3152 (__arm_vddupq_m_n_u8): Likewise.
3153 (__arm_vddupq_m_n_u16): Likewise.
3154 (__arm_vddupq_m_n_u32): Likewise.
3155 (__arm_vidupq_n_u16): Likewise.
3156 (__arm_vidupq_n_u32): Likewise.
3157 (__arm_vidupq_n_u8): Likewise.
3158 (__arm_vddupq_n_u16): Likewise.
3159 (__arm_vddupq_n_u32): Likewise.
3160 (__arm_vddupq_n_u8): Likewise.
3162 2020-04-23 Iain Buclaw <ibuclaw@gdcproject.org>
3164 * doc/install.texi (D-Specific Options): Document
3165 --enable-libphobos-checking and --with-libphobos-druntime-only.
3167 2020-04-23 Jakub Jelinek <jakub@redhat.com>
3170 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add
3171 cxx17_empty_base_seen argument. Pass it to recursive calls.
3172 Ignore cxx17_empty_base_field_p fields after setting
3173 *cxx17_empty_base_seen to true.
3174 (rs6000_discover_homogeneous_aggregate): Adjust
3175 rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous
3176 aggregates with C++17 empty base fields.
3179 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
3180 if last_decl is error_mark_node or has such a TREE_TYPE.
3183 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
3184 if last_decl is error_mark_node or has such a TREE_TYPE.
3186 2020-04-22 Felix Yang <felix.yang@huawei.com>
3189 * config/aarch64/aarch64.h (TARGET_SVE):
3190 Add && !TARGET_GENERAL_REGS_ONLY.
3191 (TARGET_SVE2): Add && TARGET_SVE.
3192 (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3,
3193 TARGET_SVE2_SM4): Add && TARGET_SVE2.
3194 * config/aarch64/aarch64-sve-builtins.h
3195 (sve_switcher::m_old_general_regs_only): New member.
3196 * config/aarch64/aarch64-sve-builtins.cc (check_required_registers):
3198 (reported_missing_registers_p): New variable.
3199 (check_required_extensions): Call check_required_registers before
3200 return if all required extenstions are present.
3201 (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in
3202 m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in
3203 global_options.x_target_flags.
3204 (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in
3205 global_options.x_target_flags if m_old_general_regs_only is true.
3207 2020-04-22 Zackery Spytz <zspytz@gmail.com>
3209 * doc/extend.exi: Add "free" to list of other builtin functions
3212 2020-04-20 Aaron Sawdey <acsawdey@linux.ibm.com>
3215 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed"
3217 (store_quadpti): Ditto.
3218 (atomic_load<mode>): Do not swap doublewords if TARGET_PREFIXED as
3219 plq will be used and doesn't need it.
3220 (atomic_store<mode>): Ditto, for pstq.
3222 2020-04-22 Erick Ochoa <erick.ochoa@theobroma-systems.com>
3224 * doc/invoke.texi: Update flags turned on by -O3.
3226 2020-04-22 Jakub Jelinek <jakub@redhat.com>
3229 * config/ia64/ia64.c (hfa_element_mode): Ignore
3230 cxx17_empty_base_field_p fields.
3233 * calls.h (cxx17_empty_base_field_p): Declare.
3234 * calls.c (cxx17_empty_base_field_p): Define.
3236 2020-04-22 Christophe Lyon <christophe.lyon@linaro.org>
3238 * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document.
3240 2020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
3241 Andre Vieira <andre.simoesdiasvieira@arm.com>
3242 Mihail Ionescu <mihail.ionescu@arm.com>
3244 * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
3245 * config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
3246 (ALL_QUIRKS): Add quirk_no_asmcpu.
3247 (cortex-m55): Define new cpu.
3248 * config/arm/arm-tables.opt: Regenerate.
3249 * config/arm/arm-tune.md: Likewise.
3250 * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
3252 2020-04-22 Richard Sandiford <richard.sandiford@arm.com>
3254 PR tree-optimization/94700
3255 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing
3256 an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures
3257 of similarly-structured but distinct vector types.
3259 2020-04-21 Martin Sebor <msebor@redhat.com>
3262 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct
3263 the computation of the lower bound of the source access size.
3264 (builtin_access::generic_overlap): Remove a hack for setting ranges
3267 2020-04-21 John David Anglin <danglin@gcc.gnu.org>
3269 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete.
3270 (ASM_WEAKEN_DECL): New define.
3271 (HAVE_GAS_WEAKREF): Undefine.
3273 2020-04-21 Richard Sandiford <richard.sandiford@arm.com>
3275 PR tree-optimization/94683
3276 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a
3277 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured
3278 but distinct vector types.
3280 2020-04-21 Jakub Jelinek <jakub@redhat.com>
3283 * stor-layout.c (place_field, finalize_record_size): Don't emit
3284 -Wpadded warning on TYPE_ARTIFICIAL rli->t.
3285 * ubsan.c (ubsan_get_type_descriptor_type,
3286 ubsan_get_source_location_type, ubsan_create_data): Set
3288 * asan.c (asan_global_struct): Likewise.
3290 2020-04-21 Duan bo <duanbo3@huawei.com>
3293 * config/aarch64/aarch64.c: Add an error message for option conflict.
3294 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is
3295 incompatible with -fpic, -fPIC and -mabi=ilp32.
3297 2020-04-21 Frederik Harwath <frederik@codesourcery.com>
3300 * omp-low.c (new_omp_context): Remove assignments to
3301 ctx->outer_reduction_clauses and ctx->local_reduction_clauses.
3303 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
3305 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
3306 ("popcountv2di2_vx"): Use simplify_gen_subreg.
3308 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
3311 * config/s390/s390-builtin-types.def: Add 3 new function modes.
3312 * config/s390/s390-builtins.def: Add mode dependent low-level
3313 builtin and map the overloaded builtins to these.
3314 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
3315 ("vsel<V_HW"): ... this and rewrite the pattern with bitops.
3317 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
3319 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo
3320 has a variable VF, prefer new_loop_vinfo if it is cheaper for the
3321 estimated VF and is no worse at double the estimated VF.
3323 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
3326 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix
3327 order of arguments to rtx_vector_builder.
3328 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise.
3329 When extending the trailing constants to a full vector, replace any
3330 variables with zeros.
3332 2020-04-20 Jan Hubicka <hubicka@ucw.cz>
3335 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local
3338 2020-04-20 Martin Liska <mliska@suse.cz>
3340 * symtab.c (symtab_node::dump_references): Add space after
3342 (symtab_node::dump_referring): Likewise.
3344 2020-04-18 Jeff Law <law@redhat.com>
3347 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking
3350 2020-04-18 Iain Buclaw <ibuclaw@gdcproject.org>
3352 * doc/sourcebuild.texi (Effective-Target Keywords, Environment
3353 attributes): Document d_runtime_has_std_library.
3355 2020-04-17 Jeff Law <law@redhat.com>
3357 PR rtl-optimization/90275
3358 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels
3359 when the destination has a REG_UNUSED note.
3361 2020-04-17 Tobias Burnus <tobias@codesourcery.com>
3364 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to
3367 2020-04-17 Richard Sandiford <richard.sandiford@arm.com>
3369 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function.
3370 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the
3371 cost of load and store insns if one loop iteration has enough scalar
3372 elements to use an Advanced SIMD LDP or STP.
3373 (aarch64_add_stmt_cost): Update call accordingly.
3375 2020-04-17 Jakub Jelinek <jakub@redhat.com>
3376 Jeff Law <law@redhat.com>
3379 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than
3380 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision,
3381 or pos + len >= 32, or pos + len is equal to operands[2] precision
3382 and operands[2] is not a register operand. During splitting perform
3383 SImode AND if operands[0] doesn't have CCZmode and pos + len is
3384 equal to mode precision.
3386 2020-04-17 Richard Biener <rguenther@suse.de>
3389 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate
3391 * dwarf2out.c (dw_val_equal_p): Fix pasto in
3392 dw_val_class_vms_delta comparison.
3393 * optabs.c (expand_binop_directly): Fix pasto in commutation
3395 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in
3398 2020-04-17 Jakub Jelinek <jakub@redhat.com>
3400 PR rtl-optimization/94618
3401 * cfgrtl.c (delete_insn_and_edges): Set purge not just when
3402 insn is the BB_END of its block, but also when it is only followed
3403 by DEBUG_INSNs in its block.
3405 PR tree-optimization/94621
3406 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN.
3407 Move id->adjust_array_error_bounds check first in the condition.
3409 2020-04-17 Martin Liska <mliska@suse.cz>
3410 Jonathan Yong <10walls@gmail.com>
3412 PR gcov-profile/94570
3413 * coverage.c (coverage_init): Use separator properly.
3415 2020-04-16 Peter Bergner <bergner@linux.ibm.com>
3417 PR rtl-optimization/93974
3418 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.
3419 (rs6000_cannot_substitute_mem_equiv_p): New function.
3421 2020-04-16 Martin Jambor <mjambor@suse.cz>
3424 * ipa-inline.h (ipa_saved_clone_sources): Declare.
3425 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable.
3426 (save_inline_function_body): Link the new body holder with the
3428 * cgraph.c: Include ipa-inline.h.
3429 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from
3430 the statement in ipa_saved_clone_sources.
3431 * cgraphunit.c: Include ipa-inline.h.
3432 (expand_all_functions): Free ipa_saved_clone_sources.
3434 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
3437 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
3438 the VNx16BI lowpart of the recursively-generated constant.
3440 2020-04-16 Martin Liska <mliska@suse.cz>
3441 Jakub Jelinek <jakub@redhat.com>
3444 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
3445 DECL_IS_REPLACEABLE_OPERATOR during cloning.
3446 * tree-ssa-dce.c (valid_new_delete_pair_p): New function.
3447 (propagate_necessity): Check operator names.
3449 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
3451 PR rtl-optimization/94605
3452 * early-remat.c (early_remat::process_block): Handle insns that
3453 set multiple candidate registers.
3454 2020-04-16 Jan Hubicka <hubicka@ucw.cz>
3456 PR gcov-profile/93401
3457 * common.opt (profile-prefix-path): New option.
3458 * coverae.c: Include diagnostics.h.
3459 (coverage_init): Strip profile prefix path.
3460 * doc/invoke.texi (-fprofile-prefix-path): Document.
3462 2020-04-16 Richard Biener <rguenther@suse.de>
3465 * expr.c (emit_move_multi_word): Do not generate code when
3466 the destination part is undefined_operand_subword_p.
3467 * lower-subreg.c (resolve_clobber): Look through a paradoxica
3470 2020-04-16 Martin Jambor <mjambor@suse.cz>
3472 PR tree-optimization/94598
3473 * tree-sra.c (verify_sra_access_forest): Fix verification of total
3474 scalarization accesses under access to one-element arrays.
3476 2020-04-16 Jakub Jelinek <jakub@redhat.com>
3479 * function.c (assign_parm_find_data_types): Add workaround for
3480 BROKEN_VALUE_INITIALIZATION compilers.
3482 2020-04-16 Richard Biener <rguenther@suse.de>
3484 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME
3487 2020-04-15 Uroš Bizjak <ubizjak@gmail.com>
3490 * config/i386/i386-builtin.def (__builtin_ia32_movq128):
3491 Require OPTION_MASK_ISA_SSE2.
3493 2020-04-15 Gustavo Romero <gromero@linux.ibm.com>
3496 * dumpfile.c (selftest::temp_dump_context::temp_dump_context):
3497 Don't construct a dump_context temporary to call static method.
3499 2020-04-15 Andrea Corallo <andrea.corallo@arm.com>
3501 * config/aarch64/falkor-tag-collision-avoidance.c
3502 (valid_src_p): Check for aarch64_address_info type before
3503 accessing base field.
3505 2020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
3507 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern.
3508 (V_sz_elem2): Remove unused mode attribute.
3510 2020-04-15 Matthew Malcomson <matthew.malcomson@arm.com>
3512 * config/arm/arm.md (arm_movdi): Disallow for MVE.
3514 2020-04-15 Richard Biener <rguenther@suse.de>
3517 * tree-ssa-alias.c (same_type_for_tbaa): Defer to
3518 alias_sets_conflict_p for pointers.
3520 2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
3523 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
3524 (extendhisi2_internal): Add %v1 before the load instructions.
3526 2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com>
3529 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to
3530 use PC-relative addressing for TLS references.
3532 2020-04-14 Martin Jambor <mjambor@suse.cz>
3535 * ipa-sra.c: Include internal-fn.h.
3536 (enum isra_scan_context): Update comment.
3537 (scan_function): Treat calls to internal_functions like loads or stores.
3539 2020-04-14 Yang Yang <yangyang305@huawei.com>
3541 PR tree-optimization/94574
3542 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
3543 whether a vector-insert is rewritable using a BIT_INSERT_EXPR.
3545 2020-04-14 H.J. Lu <hongjiu.lu@intel.com>
3548 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.
3550 2020-04-13 Martin Sebor <msebor@redhat.com>
3552 * doc/extend.texi (-Wall): Mention -Wformat-overflow and
3553 -Wformat-truncation. Move -Wzero-length-bounds last.
3554 (-Wrestrict): Document positive form of option enabled by -Wall.
3556 2020-04-13 Zachary Spytz <zspytz@gmail.com>
3558 * doc/extend.texi: Add realloc to list of built-in functions
3559 are recognized by the compiler.
3561 2020-04-13 H.J. Lu <hongjiu.lu@intel.com>
3564 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame
3565 pointer in word_mode for eh_return epilogues.
3567 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3569 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to
3570 memory references in %B, %C and %D operand selectors when the inner
3571 operand is a post increment address.
3573 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3575 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory
3576 reference by 4 bytes, and %D memory reference by 6 bytes.
3578 2020-04-11 Uroš Bizjak <ubizjak@gmail.com>
3581 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2
3582 condition for V4SI, V8HI and V16QI modes.
3584 2020-04-11 Jakub Jelinek <jakub@redhat.com>
3588 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on
3591 2020-04-10 Thomas Schwinge <thomas@codesourcery.com>
3595 * omp-general.c (oacc_verify_routine_clauses): Diagnose if
3596 "#pragma omp declare target" has also been applied.
3598 2020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3600 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn
3601 when to emit the epilogue_helper insn.
3602 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the
3605 2020-04-09 Jakub Jelinek <jakub@redhat.com>
3608 * cselib.h (cselib_record_sp_cfa_base_equiv,
3609 cselib_sp_derived_value_p): Declare.
3610 * cselib.c (cselib_record_sp_cfa_base_equiv,
3611 cselib_sp_derived_value_p): New functions.
3612 * var-tracking.c (add_stores): Don't record MO_VAL_SET for
3613 cselib_sp_derived_value_p values.
3614 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the
3615 start of extended basic blocks other than the first one
3616 for !frame_pointer_needed functions.
3618 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3620 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw)
3621 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw)
3622 (aarch64_sve2048_hw): Document.
3623 * config/aarch64/aarch64-protos.h
3624 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare.
3625 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
3626 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled.
3627 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New
3629 (find_type_suffix_for_scalar_type): Use it instead of comparing
3631 (function_resolver::infer_vector_or_tuple_type): Likewise.
3632 (function_resolver::require_vector_type): Likewise.
3633 (handle_arm_sve_vector_bits_attribute): New function.
3634 * config/aarch64/aarch64.c (pure_scalable_type_info): New class.
3635 (aarch64_attribute_table): Add arm_sve_vector_bits.
3636 (aarch64_return_in_memory_1):
3637 (pure_scalable_type_info::piece::get_rtx): New function.
3638 (pure_scalable_type_info::num_zr): Likewise.
3639 (pure_scalable_type_info::num_pr): Likewise.
3640 (pure_scalable_type_info::get_rtx): Likewise.
3641 (pure_scalable_type_info::analyze): Likewise.
3642 (pure_scalable_type_info::analyze_registers): Likewise.
3643 (pure_scalable_type_info::analyze_array): Likewise.
3644 (pure_scalable_type_info::analyze_record): Likewise.
3645 (pure_scalable_type_info::add_piece): Likewise.
3646 (aarch64_some_values_include_pst_objects_p): Likewise.
3647 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info
3648 to analyze whether the type is returned in SVE registers.
3649 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type
3650 is passed in SVE registers.
3651 (aarch64_pass_by_reference_1): New function, extracted from...
3652 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info
3653 to analyze whether the type is a pure scalable type and, if so,
3654 whether it should be passed by reference.
3655 (aarch64_return_in_msb): Return false for pure scalable types.
3656 (aarch64_function_value_1): Fold back into...
3657 (aarch64_function_value): ...this function. Use
3658 pure_scalable_type_info to analyze whether the type is a pure
3659 scalable type and, if so, which registers it should use. Handle
3660 types that include pure scalable types but are not themselves
3661 pure scalable types.
3662 (aarch64_return_in_memory_1): New function, split out from...
3663 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info
3664 to analyze whether the type is a pure scalable type and, if so,
3665 whether it should be returned by reference.
3666 (aarch64_layout_arg): Remove orig_mode argument. Use
3667 pure_scalable_type_info to analyze whether the type is a pure
3668 scalable type and, if so, which registers it should use. Handle
3669 types that include pure scalable types but are not themselves
3670 pure scalable types.
3671 (aarch64_function_arg): Update call accordingly.
3672 (aarch64_function_arg_advance): Likewise.
3673 (aarch64_pad_reg_upward): On big-endian targets, return false for
3674 pure scalable types that are smaller than 16 bytes.
3675 (aarch64_member_type_forces_blk): New function.
3676 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types.
3677 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that
3678 correspond to built-in SVE types. Do not rely on a vector mode
3679 if the type includes an pure scalable type. When returning true,
3680 assert that the mode is not an SVE mode.
3681 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE
3682 built-in types here. When returning true, assert that the type
3683 does not have an SVE mode.
3684 (aarch64_can_change_mode_class): Don't allow anything to change
3685 between a predicate mode and a non-predicate mode. Also don't
3686 allow changes between SVE vector modes and other modes that
3687 might be bigger than 128 bits.
3688 (aarch64_invalid_binary_op): Reject binary operations that mix
3689 SVE and GNU vector types.
3690 (TARGET_MEMBER_TYPE_FORCES_BLK): Define.
3692 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3694 * config/aarch64/aarch64.c (aarch64_attribute_table): Add
3695 "SVE sizeless type".
3696 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless)
3697 (sizeless_type_p): New functions.
3698 (register_builtin_types): Apply make_type_sizeless to the type.
3699 (register_tuple_type): Likewise.
3700 (verify_type_context): Use sizeless_type_p instead of builin_type_p.
3702 2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
3704 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for
3707 2020-04-09 Martin Jambor <mjambor@suse.cz>
3708 Richard Biener <rguenther@suse.de>
3710 PR tree-optimization/94482
3711 * tree-sra.c (create_access_replacement): Dump new replacement with
3713 (sra_modify_expr): Fix handling of cases when the original EXPR writes
3714 to only part of the replacement.
3715 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
3716 the first operand of combinations into REAL/IMAGPART_EXPR and
3719 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3721 * doc/sourcebuild.texi (check-function-bodies): Treat the third
3722 parameter as a list of option regexps and require each regexp
3725 2020-04-09 Andrea Corallo <andrea.corallo@arm.com>
3728 * config/aarch64/falkor-tag-collision-avoidance.c
3729 (valid_src_p): Fix missing rtx type check.
3731 2020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com>
3732 Richard Biener <rguenther@suse.de>
3734 PR tree-optimization/93674
3735 * tree-ssa-loop-ivopts.c (langhooks.h): New include.
3736 (add_iv_candidate_for_use): For iv_use of non integer or pointer type,
3737 or non-mode precision type, add candidate in unsigned type with the
3740 2020-04-08 Clement Chigot <clement.chigot@atos.net>
3742 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128.
3743 * config/rs6000/aix71.h (LIB_SPEC): Likewise.
3744 * config/rs6000/aix72.h (LIB_SPEC): Likewise.
3746 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3749 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
3751 * reload1.c (eliminate_regs_1): Avoid creating
3752 (plus (reg) (const_int 0)) in DEBUG_INSNs.
3754 PR tree-optimization/94524
3755 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
3756 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
3757 op1 rather than op1 itself at the end. Punt for signed modulo by
3758 most negative constant.
3759 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
3760 modulo by most negative constant.
3762 2020-04-08 Richard Biener <rguenther@suse.de>
3764 PR rtl-optimization/93946
3765 * cse.c (cse_insn): Record the tabled expression in
3766 src_related. Verify a redundant store removal is valid.
3768 2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
3771 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert
3772 ENDBR at function entry if function will be called indirectly.
3774 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3777 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
3780 2020-04-08 Martin Liska <mliska@suse.cz>
3783 * gimple.c (gimple_call_operator_delete_p): Rename to...
3784 (gimple_call_replaceable_operator_delete_p): ... this.
3785 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
3786 * gimple.h (gimple_call_operator_delete_p): Rename to ...
3787 (gimple_call_replaceable_operator_delete_p): ... this.
3788 * tree-core.h (tree_function_decl): Add replaceable_operator
3790 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1):
3791 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
3792 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p.
3793 (eliminate_unnecessary_stmts): Likewise.
3794 * tree-streamer-in.c (unpack_ts_function_decl_value_fields):
3795 Pack DECL_IS_REPLACEABLE_OPERATOR.
3796 * tree-streamer-out.c (pack_ts_function_decl_value_fields):
3797 Unpack the field here.
3798 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New.
3799 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New.
3800 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New.
3801 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable.
3802 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare
3803 replaceable operator flags.
3805 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
3806 Matthew Malcomson <matthew.malcomson@arm.com>
3808 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
3809 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
3810 (CX_TERNARY_QUALIFIERS): Likewise.
3811 (ARM_BUILTIN_CDE_PATTERN_START): Likewise.
3812 (ARM_BUILTIN_CDE_PATTERN_END): Likewise.
3813 (arm_init_acle_builtins): Initialize CDE builtins.
3814 (arm_expand_acle_builtin): Check CDE constant operands.
3815 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
3816 of CDE constant operand.
3817 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
3819 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
3820 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
3821 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
3822 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
3823 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
3824 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
3825 * config/arm/arm_cde_builtins.def: New file.
3826 * config/arm/iterators.md (V_reg): New attribute of SI.
3827 * config/arm/predicates.md (const_int_coproc_operand): New.
3828 (const_int_vcde1_operand, const_int_vcde2_operand): New.
3829 (const_int_vcde3_operand): New.
3830 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
3831 * config/arm/vfp.md (arm_vcx1<mode>): New entry.
3832 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
3833 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.
3835 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
3837 * config.gcc: Add arm_cde.h.
3838 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
3839 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
3840 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
3841 * config/arm/arm.c (arm_option_reconfigure_globals): Configure
3842 arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
3843 * config/arm/arm.h (TARGET_CDE): New macro.
3844 * config/arm/arm_cde.h: New file.
3845 * doc/invoke.texi: Document CDE options +cdecp[0-7].
3846 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
3848 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
3850 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3852 PR rtl-optimization/94516
3853 * postreload.c: Include rtl-iter.h.
3854 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
3855 looking for all MEMs with RTX_AUTOINC operand.
3856 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.
3858 2020-04-08 Tobias Burnus <tobias@codesourcery.com>
3860 * omp-grid.c (grid_eliminate_combined_simd_part): Use
3861 OMP_CLAUSE_CODE to access the omp clause code.
3863 2020-04-07 Jeff Law <law@redhat.com>
3865 PR rtl-optimization/92264
3866 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when
3867 the destination is the stack pointer.
3869 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3871 PR rtl-optimization/94291
3872 PR rtl-optimization/84169
3873 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST
3874 must be a REG or SUBREG of REG; if it is not one of these, don't
3877 2020-04-07 Richard Biener <rguenther@suse.de>
3880 * gimplify.c (gimplify_addr_expr): Also consider generated
3883 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3885 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.
3887 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3889 * config/arm/arm_mve.h: Cast some pointers to expected types.
3891 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3893 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
3894 same with '__arm_' prefix.
3896 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3898 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.
3900 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3902 * config/arm/arm.c (arm_mve_immediate_check): Removed.
3903 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
3904 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
3905 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
3906 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
3907 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
3908 mve_vqshruntq_m_n_s*): Fixed immediate constraints.
3910 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3912 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
3914 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3916 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
3917 * config/arm/mve/md: Fix v[id]wdup patterns.
3919 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3921 * config/arm/arm.c (output_move_neon): Deal with label + offset cases.
3922 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
3924 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3926 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
3927 and remove const_ptr enums.
3929 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3931 * config/arm/arm_mve.h (vsubq_n): Merge with...
3933 (vmulq_n): Merge with...
3935 (__ARM_mve_typeid): Simplify scalar and constant detection.
3937 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3940 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
3941 for inter-lane permutation for 64-byte modes.
3944 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
3945 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
3946 Assume it is a REG after that instead of testing it and doing FAIL
3947 otherwise. Formatting fix.
3949 2020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
3951 * config/rs6000/t-rtems: Delete mcpu=8540 multilib.
3953 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3956 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
3957 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes.
3959 2020-04-06 Jakub Jelinek <jakub@redhat.com>
3961 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
3962 + const0_rtx return the SP_DERIVED_VALUE_P.
3964 2020-04-06 Richard Sandiford <richard.sandiford@arm.com>
3966 PR rtl-optimization/92989
3967 * lra-lives.c (process_bb_lives): Do not treat eh_return data
3968 registers as being live at the beginning of the EH receiver.
3970 2020-04-05 Zachary Spytz <zspytz@gmail.com>
3972 * extend.texi: Add free to list of ISO C90 functions that
3973 are recognized by the compiler.
3975 2020-04-05 Nagaraju Mekala <nmekala@xilix.com>
3977 * config/microblaze/microblaze.c (microblaze_must_save_register): Check
3980 * config/microblaze/microblaze.md (trap): Update output pattern.
3982 2020-04-04 Hannes Domani <ssbssa@yahoo.de>
3983 Jakub Jelinek <jakub@redhat.com>
3986 * dwarf2out.c (gen_subprogram_die): Look through references, pointers,
3987 arrays, pointer-to-members, function types and qualifiers when
3988 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
3989 to emit type again on definition.
3991 2020-04-04 Jan Hubicka <hubicka@ucw.cz>
3994 * ipa-fnsummary.c (vrp_will_run_p): New function.
3995 (fre_will_run_p): New function.
3996 (evaluate_properties_for_edge): Use it.
3997 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
3998 !optimize_debug to optimize_debug.
4000 2020-04-04 Jakub Jelinek <jakub@redhat.com>
4002 PR rtl-optimization/94468
4003 * cselib.c (references_value_p): Formatting fix.
4004 (cselib_useless_value_p): New function.
4005 (discard_useless_locs, discard_useless_values,
4006 cselib_invalidate_regno_val, cselib_invalidate_mem,
4007 cselib_record_set): Use it instead of
4008 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx).
4011 * tree-iterator.h (expr_single): Declare.
4012 * tree-iterator.c (expr_single): New function.
4013 * tree.h (protected_set_expr_location_if_unset): Declare.
4014 * tree.c (protected_set_expr_location): Use expr_single.
4015 (protected_set_expr_location_if_unset): New function.
4017 2020-04-03 Jeff Law <law@redhat.com>
4019 PR rtl-optimization/92264
4020 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle
4021 reloading of auto-increment addressing modes.
4023 2020-04-03 H.J. Lu <hongjiu.lu@intel.com>
4026 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand
4029 2020-04-03 Jeff Law <law@redhat.com>
4031 PR rtl-optimization/92264
4032 * config/m32r/m32r.c (m32r_output_block_move): Properly account for
4033 post-increment addressing of source operands as well as residuals
4034 when computing any adjustments to the input pointer.
4036 2020-04-03 Jakub Jelinek <jakub@redhat.com>
4039 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
4040 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
4041 second half of first lane from first lane of second operand and
4042 first half of second lane from second lane of first operand.
4044 2020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
4046 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE.
4048 2020-04-03 Tamar Christina <tamar.christina@arm.com>
4051 * common/config/aarch64/aarch64-common.c
4052 (aarch64_get_extension_string_for_isa_flags): Handle default flags.
4054 2020-04-03 Richard Biener <rguenther@suse.de>
4057 * tree.c (array_ref_low_bound): Deal with released SSA names
4060 2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com>
4062 * config/gcn/gcn.c (print_operand): Handle unordered comparison
4064 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered
4065 comparison operators.
4067 2020-04-03 Kewen Lin <linkw@gcc.gnu.org>
4069 PR tree-optimization/94443
4070 * tree-vect-loop.c (vectorizable_live_operation): Use
4071 gsi_insert_seq_before to replace gsi_insert_before.
4073 2020-04-03 Martin Liska <mliska@suse.cz>
4076 * ipa-icf-gimple.c (func_checker::compare_gimple_call):
4077 Compare type attributes for gimple_call_fntypes.
4079 2020-04-02 Sandra Loosemore <sandra@codesourcery.com>
4081 * alias.c (get_alias_set): Fix comment typos.
4083 2020-04-02 Fritz Reese <foreese@gcc.gnu.org>
4086 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
4087 attribute checking used by TYPE.
4089 2020-04-02 Martin Jambor <mjambor@suse.cz>
4092 * ipa-sra.c (struct caller_issues): New fields candidate and
4093 call_from_outside_comdat.
4094 (check_for_caller_issues): Check for calls from outsied of
4095 candidate's same_comdat_group.
4096 (check_all_callers_for_issues): Set up issues.candidate, check result
4098 (mark_callers_calls_comdat_local): New function.
4099 (process_isra_node_results): Set calls_comdat_local of callers if
4102 2020-04-02 Richard Biener <rguenther@suse.de>
4105 * common.opt (ffinite-loops): Initialize to zero.
4106 * opts.c (default_options_table): Remove OPT_ffinite_loops
4108 * cfgloop.h (loop::finite_p): New member.
4109 * cfgloopmanip.c (copy_loop_info): Copy finite_p.
4110 * ipa-icf-gimple.c (func_checker::compare_loops): Compare
4112 * lto-streamer-in.c (input_cfg): Stream finite_p.
4113 * lto-streamer-out.c (output_cfg): Likewise.
4114 * tree-cfg.c (replace_loop_annotate): Initialize finite_p
4115 from flag_finite_loops at CFG build time.
4116 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops
4117 finite_p flag instead of flag_finite_loops.
4118 * doc/invoke.texi (ffinite-loops): Adjust documentation of
4121 2020-04-02 Richard Biener <rguenther@suse.de>
4124 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting
4125 DW_TAG_imported_unit.
4127 2020-04-02 Maciej W. Rozycki <macro@wdc.com>
4129 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
4130 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
4133 2020-04-02 Kewen Lin <linkw@gcc.gnu.org>
4135 PR tree-optimization/94401
4136 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
4137 access type when loading halves of vector to avoid peeling for gaps.
4139 2020-04-02 Jakub Jelinek <jakub@redhat.com>
4141 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
4142 between a string literal and MIPS_SYSVERSION_SPEC macro.
4144 2020-04-02 Martin Jambor <mjambor@suse.cz>
4146 * doc/invoke.texi (Optimize Options): Document sra-max-propagations.
4148 2020-04-02 Jakub Jelinek <jakub@redhat.com>
4150 PR rtl-optimization/92264
4151 * params.opt (-param=max-find-base-term-values=): Decrease default
4154 PR rtl-optimization/92264
4155 * rtl.h (struct rtx_def): Mention that call bit is used as
4156 SP_DERIVED_VALUE_P in cselib.c.
4157 * cselib.c (SP_DERIVED_VALUE_P): Define.
4158 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
4159 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
4160 val_rtx and sp based expression where offsets cancel each other.
4161 (preserve_constants_and_equivs): Formatting fix.
4162 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
4163 locs list for cfa_base_preserved_val if needed. Formatting fix.
4164 (autoinc_split): If the to be returned value is a REG, MEM or
4165 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
4166 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
4167 (rtx_equal_for_cselib_1): Call autoinc_split even if both
4168 expressions are PLUS in Pmode with CONST_INT second operands.
4169 Handle SP_DERIVED_VALUE_P cases.
4170 (cselib_hash_plus_const_int): New function.
4171 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
4172 second operand, as well as for PRE_DEC etc. that ought to be
4173 hashed the same way.
4174 (cselib_subst_to_values): Substitute PLUS with Pmode and
4175 CONST_INT operand if the first operand is a VALUE which has
4176 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
4177 SP_DERIVED_VALUE_P + adjusted offset.
4178 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
4179 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding
4180 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
4181 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
4182 on the sp value before calling cselib_add_permanent_equiv on the
4184 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
4185 in the insn without REG_INC note.
4186 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
4187 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes.
4190 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
4191 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
4193 2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4196 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
4197 (LDRGBWBXU_Z_QUALIFIERS): Likewise.
4198 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
4199 intrinsic defintion by adding a new builtin call to writeback into base
4201 (__arm_vldrdq_gather_base_wb_u64): Likewise.
4202 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
4203 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
4204 (__arm_vldrwq_gather_base_wb_s32): Likewise.
4205 (__arm_vldrwq_gather_base_wb_u32): Likewise.
4206 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
4207 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
4208 (__arm_vldrwq_gather_base_wb_f32): Likewise.
4209 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
4210 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
4211 builtin's qualifier.
4212 (vldrdq_gather_base_wb_z_u): Likewise.
4213 (vldrwq_gather_base_wb_u): Likewise.
4214 (vldrdq_gather_base_wb_u): Likewise.
4215 (vldrwq_gather_base_wb_z_s): Likewise.
4216 (vldrwq_gather_base_wb_z_f): Likewise.
4217 (vldrdq_gather_base_wb_z_s): Likewise.
4218 (vldrwq_gather_base_wb_s): Likewise.
4219 (vldrwq_gather_base_wb_f): Likewise.
4220 (vldrdq_gather_base_wb_s): Likewise.
4221 (vldrwq_gather_base_nowb_z_u): Define builtin.
4222 (vldrdq_gather_base_nowb_z_u): Likewise.
4223 (vldrwq_gather_base_nowb_u): Likewise.
4224 (vldrdq_gather_base_nowb_u): Likewise.
4225 (vldrwq_gather_base_nowb_z_s): Likewise.
4226 (vldrwq_gather_base_nowb_z_f): Likewise.
4227 (vldrdq_gather_base_nowb_z_s): Likewise.
4228 (vldrwq_gather_base_nowb_s): Likewise.
4229 (vldrwq_gather_base_nowb_f): Likewise.
4230 (vldrdq_gather_base_nowb_s): Likewise.
4231 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
4233 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
4234 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
4235 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
4236 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
4237 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
4238 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
4239 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
4240 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
4241 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
4242 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
4243 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
4245 2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
4247 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
4248 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
4249 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
4250 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
4251 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
4252 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
4253 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
4254 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
4255 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
4257 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
4258 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
4259 Remove constraints from expander.
4260 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
4261 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
4262 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
4263 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
4264 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
4265 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
4267 2020-04-01 Peter Bergner <bergner@linux.ibm.com>
4269 PR rtl-optimization/94123
4270 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for
4271 flag_split_wide_types_early.
4273 2020-04-01 Joerg Sonnenberger <joerg@bec.de>
4275 * doc/extend.texi (Common Function Attributes): Fix typo.
4277 2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>
4280 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
4283 2020-04-01 Zackery Spytz <zspytz@gmail.com>
4285 * doc/extend.texi: Fix a typo in the documentation of the
4286 copy function attribute.
4288 2020-04-01 Jakub Jelinek <jakub@redhat.com>
4291 * tree-object-size.c (pass_object_sizes::execute): Don't call
4292 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
4293 call replace_call_with_value.
4295 2020-04-01 Kewen Lin <linkw@gcc.gnu.org>
4297 PR tree-optimization/94043
4298 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
4299 phi for vec_lhs and use it for lane extraction.
4301 2020-03-31 Felix Yang <felix.yang@huawei.com>
4303 PR tree-optimization/94398
4304 * tree-vect-stmts.c (vectorizable_store): Instead of calling
4305 vect_supportable_dr_alignment, set alignment_support_scheme to
4306 dr_unaligned_supported for gather-scatter accesses.
4307 (vectorizable_load): Likewise.
4309 2020-03-31 Andrew Stubbs <ams@codesourcery.com>
4311 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
4313 (vnsi, VnSI, vndi, VnDI): New mode attributes.
4314 (mov<mode>): Use <VnDI> in place of V64DI.
4315 (mov<mode>_exec): Likewise.
4316 (mov<mode>_sgprbase): Likewise.
4317 (reload_out<mode>): Likewise.
4318 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
4319 (gather_load<mode>v64si): Rename to ...
4320 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
4321 and <VnDI> in place of V64DI.
4322 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
4323 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
4324 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
4325 (scatter_store<mode>v64si): Rename to ...
4326 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4327 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
4328 (scatter<mode>_insn_1offset<exec_scatter>): Likewise.
4329 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
4330 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
4331 (ds_bpermute<mode>): Use <VnSI>.
4332 (addv64si3_vcc<exec_vcc>): Rename to ...
4333 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
4334 (addv64si3_vcc_dup<exec_vcc>): Rename to ...
4335 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
4336 (addcv64si3<exec_vcc>): Rename to ...
4337 (addc<mode>3<exec_vcc>): ... this, and use V_SI.
4338 (subv64si3_vcc<exec_vcc>): Rename to ...
4339 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
4340 (subcv64si3<exec_vcc>): Rename to ...
4341 (subc<mode>3<exec_vcc>): ... this, and use V_SI.
4342 (addv64di3): Rename to ...
4343 (add<mode>3): ... this, and use V_DI.
4344 (addv64di3_exec): Rename to ...
4345 (add<mode>3_exec): ... this, and use V_DI.
4346 (subv64di3): Rename to ...
4347 (sub<mode>3): ... this, and use V_DI.
4348 (subv64di3_exec): Rename to ...
4349 (sub<mode>3_exec): ... this, and use V_DI.
4350 (addv64di3_zext): Rename to ...
4351 (add<mode>3_zext): ... this, and use V_DI and <VnSI>.
4352 (addv64di3_zext_exec): Rename to ...
4353 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
4354 (addv64di3_zext_dup): Rename to ...
4355 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
4356 (addv64di3_zext_dup_exec): Rename to ...
4357 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
4358 (addv64di3_zext_dup2): Rename to ...
4359 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
4360 (addv64di3_zext_dup2_exec): Rename to ...
4361 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
4362 (addv64di3_sext_dup2): Rename to ...
4363 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
4364 (addv64di3_sext_dup2_exec): Rename to ...
4365 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
4366 (<su>mulv64si3_highpart<exec>): Rename to ...
4367 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
4368 (mulv64di3): Rename to ...
4369 (mul<mode>3): ... this, and use V_DI and <VnSI>.
4370 (mulv64di3_exec): Rename to ...
4371 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
4372 (mulv64di3_zext): Rename to ...
4373 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
4374 (mulv64di3_zext_exec): Rename to ...
4375 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
4376 (mulv64di3_zext_dup2): Rename to ...
4377 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
4378 (mulv64di3_zext_dup2_exec): Rename to ...
4379 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
4380 (<expander>v64di3): Rename to ...
4381 (<expander><mode>3): ... this, and use V_DI and <VnSI>.
4382 (<expander>v64di3_exec): Rename to ...
4383 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
4384 (<expander>v64si3<exec>): Rename to ...
4385 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
4386 (v<expander>v64si3<exec>): Rename to ...
4387 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
4388 (<expander>v64si3<exec>): Rename to ...
4389 (<expander><vnsi>3<exec>): ... this, and use V_SI.
4390 (subv64df3<exec>): Rename to ...
4391 (sub<mode>3<exec>): ... this, and use V_DF.
4392 (truncv64di<mode>2): Rename to ...
4393 (trunc<vndi><mode>2): ... this, and use <VnDI>.
4394 (truncv64di<mode>2_exec): Rename to ...
4395 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
4396 (<convop><mode>v64di2): Rename to ...
4397 (<convop><mode><vndi>2): ... this, and use <VnDI>.
4398 (<convop><mode>v64di2_exec): Rename to ...
4399 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
4400 (vec_cmp<u>v64qidi): Rename to ...
4401 (vec_cmp<u><mode>di): ... this, and use <VnSI>.
4402 (vec_cmp<u>v64qidi_exec): Rename to ...
4403 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
4404 (vcond_mask_<mode>di): Use <VnDI>.
4405 (maskload<mode>di): Likewise.
4406 (maskstore<mode>di): Likewise.
4407 (mask_gather_load<mode>v64si): Rename to ...
4408 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4409 (mask_scatter_store<mode>v64si): Rename to ...
4410 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4411 (*<reduc_op>_dpp_shr_v64di): Rename to ...
4412 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
4413 (*plus_carry_in_dpp_shr_v64si): Rename to ...
4414 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
4415 (*plus_carry_dpp_shr_v64di): Rename to ...
4416 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
4417 (vec_seriesv64si): Rename to ...
4418 (vec_series<mode>): ... this, and use V_SI.
4419 (vec_seriesv64di): Rename to ...
4420 (vec_series<mode>): ... this, and use V_DI.
4422 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
4424 * config/arc/arc.c (arc_print_operand): Use
4425 HOST_WIDE_INT_PRINT_DEC macro.
4427 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
4429 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
4431 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4433 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
4435 (__arm_vbicq): Likewise.
4437 2020-03-31 Vineet Gupta <vgupta@synopsys.com>
4439 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
4441 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4443 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
4444 common section of both MVE Integer and MVE Floating Point.
4446 (vaddlvq_p): Likewise.
4447 (vaddvaq): Likewise.
4448 (vaddvq_p): Likewise.
4449 (vcmpcsq): Likewise.
4450 (vmlsdavxq): Likewise.
4451 (vmlsdavq): Likewise.
4452 (vmladavxq): Likewise.
4453 (vmladavq): Likewise.
4455 (vminavq): Likewise.
4457 (vmaxavq): Likewise.
4458 (vmlaldavq): Likewise.
4459 (vcmphiq): Likewise.
4460 (vaddlvaq): Likewise.
4461 (vrmlaldavhq): Likewise.
4462 (vrmlaldavhxq): Likewise.
4463 (vrmlsldavhq): Likewise.
4464 (vrmlsldavhxq): Likewise.
4465 (vmlsldavxq): Likewise.
4466 (vmlsldavq): Likewise.
4468 (vrmlaldavhaq): Likewise.
4469 (vcmpgeq_m_n): Likewise.
4470 (vmlsdavxq_p): Likewise.
4471 (vmlsdavq_p): Likewise.
4472 (vmlsdavaxq): Likewise.
4473 (vmlsdavaq): Likewise.
4474 (vaddvaq_p): Likewise.
4475 (vcmpcsq_m_n): Likewise.
4476 (vcmpcsq_m): Likewise.
4477 (vmladavxq_p): Likewise.
4478 (vmladavq_p): Likewise.
4479 (vmladavaxq): Likewise.
4480 (vmladavaq): Likewise.
4481 (vminvq_p): Likewise.
4482 (vminavq_p): Likewise.
4483 (vmaxvq_p): Likewise.
4484 (vmaxavq_p): Likewise.
4485 (vcmphiq_m): Likewise.
4486 (vaddlvaq_p): Likewise.
4487 (vmlaldavaq): Likewise.
4488 (vmlaldavaxq): Likewise.
4489 (vmlaldavq_p): Likewise.
4490 (vmlaldavxq_p): Likewise.
4491 (vmlsldavaq): Likewise.
4492 (vmlsldavaxq): Likewise.
4493 (vmlsldavq_p): Likewise.
4494 (vmlsldavxq_p): Likewise.
4495 (vrmlaldavhaxq): Likewise.
4496 (vrmlaldavhq_p): Likewise.
4497 (vrmlaldavhxq_p): Likewise.
4498 (vrmlsldavhaq): Likewise.
4499 (vrmlsldavhaxq): Likewise.
4500 (vrmlsldavhq_p): Likewise.
4501 (vrmlsldavhxq_p): Likewise.
4502 (vabavq_p): Likewise.
4503 (vmladavaq_p): Likewise.
4504 (vstrbq_scatter_offset): Likewise.
4505 (vstrbq_p): Likewise.
4506 (vstrbq_scatter_offset_p): Likewise.
4507 (vstrdq_scatter_base_p): Likewise.
4508 (vstrdq_scatter_base): Likewise.
4509 (vstrdq_scatter_offset_p): Likewise.
4510 (vstrdq_scatter_offset): Likewise.
4511 (vstrdq_scatter_shifted_offset_p): Likewise.
4512 (vstrdq_scatter_shifted_offset): Likewise.
4513 (vmaxq_x): Likewise.
4514 (vminq_x): Likewise.
4515 (vmovlbq_x): Likewise.
4516 (vmovltq_x): Likewise.
4517 (vmulhq_x): Likewise.
4518 (vmullbq_int_x): Likewise.
4519 (vmullbq_poly_x): Likewise.
4520 (vmulltq_int_x): Likewise.
4521 (vmulltq_poly_x): Likewise.
4524 2020-03-31 Jakub Jelinek <jakub@redhat.com>
4527 * config/aarch64/constraints.md (Uph): New constraint.
4528 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
4529 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
4532 2020-03-31 Marc Glisse <marc.glisse@inria.fr>
4533 Jakub Jelinek <jakub@redhat.com>
4536 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
4537 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
4539 2020-03-31 Jakub Jelinek <jakub@redhat.com>
4541 PR tree-optimization/94403
4542 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
4543 ENUMERAL_TYPE lhs_type.
4545 PR rtl-optimization/94344
4546 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
4547 conversions, either on both operands of |^+ or just one. Handle
4548 also extra same precision conversion on RSHIFT_EXPR first operand
4549 provided RSHIFT_EXPR is performed in unsigned type.
4551 2020-03-30 David Malcolm <dmalcolm@redhat.com>
4553 * lra.c (finish_insn_code_data_once): Set the array elements
4554 to NULL after freeing them.
4556 2020-03-30 Andreas Schwab <schwab@suse.de>
4558 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
4561 2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com>
4563 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
4564 to skip defining builtins based on builtin_mask.
4566 2020-03-30 Jakub Jelinek <jakub@redhat.com>
4569 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
4570 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
4571 operand is a register. Don't enable masked variants for V*[QH]Imode.
4574 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
4575 <store_mask_constraint> instead of m in output operand constraint.
4576 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
4579 2020-03-30 Alan Modra <amodra@gmail.com>
4581 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
4582 (rs6000_indirect_call_template_1): Adjust to suit.
4583 * config/rs6000/rs6000.md (call_local): Merge call_local32,
4584 call_local64, and call_local_aix.
4585 (call_value_local): Simlarly.
4586 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
4587 and disable pattern when CALL_LONG.
4588 (call_indirect_aix, call_value_indirect_aix): Adjust rtl.
4589 (call_indirect_elfv2, call_indirect_pcrel): Likewise.
4590 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
4592 2020-03-29 H.J. Lu <hongjiu.lu@intel.com>
4595 * doc/invoke.texi: Update -falign-functions, -falign-loops and
4596 -falign-jumps documentation.
4598 2020-03-29 Martin Liska <mliska@suse.cz>
4601 * cgraphunit.c (process_function_and_variable_attributes): Remove
4602 double 'attribute' words.
4604 2020-03-29 John David Anglin <dave.anglin@bell.net>
4606 * config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
4609 2020-03-28 Jakub Jelinek <jakub@redhat.com>
4612 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const
4613 to true after setting size to integer_one_node.
4615 PR tree-optimization/94329
4616 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
4617 on the last stmt in a bb, make sure gsi_prev isn't done immediately
4620 2020-03-27 Alan Modra <amodra@gmail.com>
4623 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
4624 for PLT16_LO and PLT_PCREL.
4625 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
4626 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
4627 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
4629 2020-03-27 Martin Sebor <msebor@redhat.com>
4632 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes.
4634 2020-03-27 Andrew Stubbs <ams@codesourcery.com>
4636 * config/gcn/gcn-valu.md:
4637 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout.
4638 (VEC_1REG_MODE): Delete.
4639 (VEC_1REG_ALT): Delete.
4640 (VEC_ALL1REG_MODE): Rename to V_1REG throughout.
4641 (VEC_1REG_INT_MODE): Delete.
4642 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout.
4643 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout.
4644 (VEC_2REG_MODE): Rename to V_2REG throughout.
4645 (VEC_REG_MODE): Rename to V_noHI throughout.
4646 (VEC_ALLREG_MODE): Rename to V_ALL throughout.
4647 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout.
4648 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout.
4649 (VEC_INT_MODE): Delete.
4650 (VEC_FP_MODE): Rename to V_FP throughout and move to top.
4651 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top.
4652 (FP_MODE): Delete and replace with FP throughout.
4653 (FP_1REG_MODE): Delete and replace with FP_1REG throughout.
4654 (VCMP_MODE): Rename to V_noQI throughout and move to top.
4655 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top.
4656 * config/gcn/gcn.md (FP): New mode iterator.
4657 (FP_1REG): New mode iterator.
4659 2020-03-27 David Malcolm <dmalcolm@redhat.com>
4661 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this
4662 now emits two .dot files.
4663 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD.
4664 (graphviz_out::end_tr): Only close a TR, not a TD.
4665 (graphviz_out::begin_td): New.
4666 (graphviz_out::end_td): New.
4667 (graphviz_out::begin_trtd): New, replacing the old implementation
4668 of graphviz_out::begin_tr.
4669 (graphviz_out::end_tdtr): New, replacing the old implementation
4670 of graphviz_out::end_tr.
4671 * graphviz.h (graphviz_out::begin_td): New decl.
4672 (graphviz_out::end_td): New decl.
4673 (graphviz_out::begin_trtd): New decl.
4674 (graphviz_out::end_tdtr): New decl.
4676 2020-03-27 Richard Biener <rguenther@suse.de>
4679 * dwarf2out.c (should_emit_struct_debug): Return false for
4682 2020-03-27 Richard Biener <rguenther@suse.de>
4684 PR tree-optimization/94352
4685 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the
4687 (ssa_propagation_engine::ssa_propagate): ... here after
4688 initializing curr_order.
4690 2020-03-27 Kewen Lin <linkw@gcc.gnu.org>
4692 PR tree-optimization/90332
4693 * tree-vect-stmts.c (vector_vector_composition_type): New function.
4694 (get_group_load_store_type): Adjust to call
4695 vector_vector_composition_type, extend it to construct with scalar
4697 (vectorizable_load): Likewise.
4699 2020-03-27 Roman Zhuykov <zhroma@ispras.ru>
4701 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions.
4702 (create_ddg_dep_no_link): Likewise.
4703 (add_cross_iteration_register_deps): Move debug instruction check.
4704 Other minor refactoring.
4705 (add_intra_loop_mem_dep): Do not check for debug instructions.
4706 (add_inter_loop_mem_dep): Likewise.
4707 (build_intra_loop_deps): Likewise.
4708 (create_ddg): Do not include debug insns into the graph.
4709 * ddg.h (struct ddg): Remove num_debug field.
4710 * modulo-sched.c (doloop_register_get): Adjust condition.
4711 (res_MII): Remove DDG num_debug field usage.
4712 (sms_schedule_by_order): Use assertion against debug insns.
4713 (ps_has_conflicts): Drop debug insn check.
4715 2020-03-26 Jakub Jelinek <jakub@redhat.com>
4718 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST
4719 that contains exactly one non-DEBUG_BEGIN_STMT statement.
4722 * gimple.h (gimple_seq_first_nondebug_stmt): New function.
4723 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains
4724 a single non-debug stmt followed by one or more debug stmts.
4725 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt
4726 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt
4727 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and
4728 gimple_seq_last to check if outer_stmt gbind could be reused and
4729 if yes and it is surrounded by any debug stmts, move them into the
4732 PR rtl-optimization/92264
4733 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even
4734 for sp based values in !frame_pointer_needed
4735 && !ACCUMULATE_OUTGOING_ARGS functions.
4737 2020-03-26 Felix Yang <felix.yang@huawei.com>
4739 PR tree-optimization/94269
4740 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict
4742 operation to single basic block.
4744 2020-03-25 Jeff Law <law@redhat.com>
4746 PR rtl-optimization/90275
4747 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the
4750 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4753 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to
4754 mode rather than VOIDmode.
4756 2020-03-25 Martin Sebor <msebor@redhat.com>
4759 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings
4760 even for alloca calls resulting from system macro expansion.
4761 Include inlining context in all warnings.
4763 2020-03-25 Richard Sandiford <richard.sandiford@arm.com>
4766 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
4767 FPRs to change between SDmode and DDmode.
4769 2020-03-25 Martin Sebor <msebor@redhat.com>
4771 PR tree-optimization/94131
4772 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length
4774 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming
4775 types have constant sizes.
4777 2020-03-25 Martin Liska <mliska@suse.cz>
4780 * configure.ac: Report error only when --with-zstd
4782 * configure: Regenerate.
4784 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4787 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
4788 INSN_CODE (insn) to -1 when changing the pattern.
4790 2020-03-25 Martin Liska <mliska@suse.cz>
4794 * config/i386/i386-features.c (make_resolver_func): Drop
4795 public flag for resolver.
4796 * config/rs6000/rs6000.c (make_resolver_func): Add comdat
4797 group for resolver and drop public flag if possible.
4798 * multiple_target.c (create_dispatcher_calls): Drop unique_name
4799 and resolution as we want to enable LTO privatization of the default
4802 2020-03-25 Martin Liska <mliska@suse.cz>
4805 * configure.ac: Respect --without-zstd and report
4806 error when we can't find header file with --with-zstd.
4807 * configure: Regenerate.
4809 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4812 * varasm.c (output_constructor_array_range): If local->index
4813 RANGE_EXPR doesn't start at the current location in the constructor,
4814 skip needed number of bytes using assemble_zeros or assert we don't
4818 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong
4819 counter instead of DECL_UID.
4821 PR tree-optimization/94300
4822 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset
4823 is positive, make sure that off + size isn't larger than needed_len.
4825 2020-03-25 Richard Biener <rguenther@suse.de>
4826 Jakub Jelinek <jakub@redhat.com>
4829 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
4831 2020-03-24 Christophe Lyon <christophe.lyon@linaro.org>
4833 * doc/sourcebuild.texi (ARM-specific attributes): Add
4835 (Features for dg-add-options): Add arm_fp_dp.
4837 2020-03-24 John David Anglin <danglin@gcc.gnu.org>
4840 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.
4842 2020-03-24 Tobias Burnus <tobias@codesourcery.com>
4845 * omp-offload.c (omp_finish_file): Fix target-link handling if
4846 targetm_common.have_named_sections is false.
4848 2020-03-24 Jakub Jelinek <jakub@redhat.com>
4851 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
4855 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to
4856 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts.
4857 If not after and at *incr_pos is a debug stmt, set stmt location to
4858 location of next non-debug stmt after it if any.
4861 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
4862 GF_PLF_2, but don't add them to worklist. Don't add an assigment to
4863 worklist or set GF_PLF_2 just because it is used in a debug stmt in
4864 another bb. Formatting improvements.
4867 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and
4868 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC
4869 regardless of whether TREE_NO_WARNING is set on it or whether
4870 warn_unused_function is true or not.
4872 2020-03-23 Jeff Law <law@redhat.com>
4874 PR rtl-optimization/90275
4877 * simplify-rtx.c (comparison_code_valid_for_mode): New function.
4878 (simplify_logical_relational_operation): Use it.
4880 2020-03-23 Jakub Jelinek <jakub@redhat.com>
4883 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on
4884 ultimate rhs and if returned something different, reconstructing
4887 2020-03-23 Lewis Hyatt <lhyatt@gmail.com>
4889 * opts.c (print_filtered_help): Improve the help text for alias options.
4891 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4892 Andre Vieira <andre.simoesdiasvieira@arm.com>
4893 Mihail Ionescu <mihail.ionescu@arm.com>
4895 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro.
4896 (vshlcq_m_u8): Likewise.
4897 (vshlcq_m_s16): Likewise.
4898 (vshlcq_m_u16): Likewise.
4899 (vshlcq_m_s32): Likewise.
4900 (vshlcq_m_u32): Likewise.
4901 (__arm_vshlcq_m_s8): Define intrinsic.
4902 (__arm_vshlcq_m_u8): Likewise.
4903 (__arm_vshlcq_m_s16): Likewise.
4904 (__arm_vshlcq_m_u16): Likewise.
4905 (__arm_vshlcq_m_s32): Likewise.
4906 (__arm_vshlcq_m_u32): Likewise.
4907 (vshlcq_m): Define polymorphic variant.
4908 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE):
4909 Use builtin qualifier.
4910 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
4911 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern.
4912 (mve_vshlcq_m_carry_<supf><mode>): Likewise.
4913 (mve_vshlcq_m_<supf><mode>): Likewise.
4915 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4917 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier.
4918 (UQSHL_QUALIFIERS): Likewise.
4919 (ASRL_QUALIFIERS): Likewise.
4920 (SQSHL_QUALIFIERS): Likewise.
4921 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in
4923 (sqrshr): Define macro.
4924 (sqrshrl): Likewise.
4925 (sqrshrl_sat48): Likewise.
4931 (uqrshll): Likewise.
4932 (uqrshll_sat48): Likewise.
4939 (__arm_lsll): Define intrinsic.
4940 (__arm_asrl): Likewise.
4941 (__arm_uqrshll): Likewise.
4942 (__arm_uqrshll_sat48): Likewise.
4943 (__arm_sqrshrl): Likewise.
4944 (__arm_sqrshrl_sat48): Likewise.
4945 (__arm_uqshll): Likewise.
4946 (__arm_urshrl): Likewise.
4947 (__arm_srshrl): Likewise.
4948 (__arm_sqshll): Likewise.
4949 (__arm_uqrshl): Likewise.
4950 (__arm_sqrshr): Likewise.
4951 (__arm_uqshl): Likewise.
4952 (__arm_urshr): Likewise.
4953 (__arm_sqshl): Likewise.
4954 (__arm_srshr): Likewise.
4955 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin
4957 (UQSHL_QUALIFIERS): Likewise.
4958 (ASRL_QUALIFIERS): Likewise.
4959 (SQSHL_QUALIFIERS): Likewise.
4960 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern.
4961 (mve_sqrshrl_sat<supf>_di): Likewise.
4962 (mve_uqrshl_si): Likewise.
4963 (mve_sqrshr_si): Likewise.
4964 (mve_uqshll_di): Likewise.
4965 (mve_urshrl_di): Likewise.
4966 (mve_uqshl_si): Likewise.
4967 (mve_urshr_si): Likewise.
4968 (mve_sqshl_si): Likewise.
4969 (mve_srshr_si): Likewise.
4970 (mve_srshrl_di): Likewise.
4971 (mve_sqshll_di): Likewise.
4973 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4974 Andre Vieira <andre.simoesdiasvieira@arm.com>
4975 Mihail Ionescu <mihail.ionescu@arm.com>
4977 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro.
4978 (vsetq_lane_f32): Likewise.
4979 (vsetq_lane_s16): Likewise.
4980 (vsetq_lane_s32): Likewise.
4981 (vsetq_lane_s8): Likewise.
4982 (vsetq_lane_s64): Likewise.
4983 (vsetq_lane_u8): Likewise.
4984 (vsetq_lane_u16): Likewise.
4985 (vsetq_lane_u32): Likewise.
4986 (vsetq_lane_u64): Likewise.
4987 (vgetq_lane_f16): Likewise.
4988 (vgetq_lane_f32): Likewise.
4989 (vgetq_lane_s16): Likewise.
4990 (vgetq_lane_s32): Likewise.
4991 (vgetq_lane_s8): Likewise.
4992 (vgetq_lane_s64): Likewise.
4993 (vgetq_lane_u8): Likewise.
4994 (vgetq_lane_u16): Likewise.
4995 (vgetq_lane_u32): Likewise.
4996 (vgetq_lane_u64): Likewise.
4997 (__ARM_NUM_LANES): Likewise.
4998 (__ARM_LANEQ): Likewise.
4999 (__ARM_CHECK_LANEQ): Likewise.
5000 (__arm_vsetq_lane_s16): Define intrinsic.
5001 (__arm_vsetq_lane_s32): Likewise.
5002 (__arm_vsetq_lane_s8): Likewise.
5003 (__arm_vsetq_lane_s64): Likewise.
5004 (__arm_vsetq_lane_u8): Likewise.
5005 (__arm_vsetq_lane_u16): Likewise.
5006 (__arm_vsetq_lane_u32): Likewise.
5007 (__arm_vsetq_lane_u64): Likewise.
5008 (__arm_vgetq_lane_s16): Likewise.
5009 (__arm_vgetq_lane_s32): Likewise.
5010 (__arm_vgetq_lane_s8): Likewise.
5011 (__arm_vgetq_lane_s64): Likewise.
5012 (__arm_vgetq_lane_u8): Likewise.
5013 (__arm_vgetq_lane_u16): Likewise.
5014 (__arm_vgetq_lane_u32): Likewise.
5015 (__arm_vgetq_lane_u64): Likewise.
5016 (__arm_vsetq_lane_f16): Likewise.
5017 (__arm_vsetq_lane_f32): Likewise.
5018 (__arm_vgetq_lane_f16): Likewise.
5019 (__arm_vgetq_lane_f32): Likewise.
5020 (vgetq_lane): Define polymorphic variant.
5021 (vsetq_lane): Likewise.
5022 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL
5024 (mve_vec_extractv2didi): Likewise.
5025 (mve_vec_extract_sext_internal<mode>): Likewise.
5026 (mve_vec_extract_zext_internal<mode>): Likewise.
5027 (mve_vec_set<mode>_internal): Likewise.
5028 (mve_vec_setv2di_internal): Likewise.
5029 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md
5031 (vec_extract<mode><V_elem_l>): Rename to
5032 "neon_vec_extract<mode><V_elem_l>".
5033 (vec_extractv2didi): Rename to "neon_vec_extractv2didi".
5034 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL
5035 pattern common for MVE and NEON.
5036 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both
5039 2020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com>
5041 * config/arm/mve.md (earlyclobber_32): New mode attribute.
5042 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
5043 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.
5045 2020-03-23 Richard Biener <rguenther@suse.de>
5047 PR tree-optimization/94261
5048 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove
5049 IL operand swapping code.
5050 (vect_slp_rearrange_stmts): Do not arrange isomorphic
5051 nodes that would need operation code adjustments.
5053 2020-03-23 Tobias Burnus <tobias@codesourcery.com>
5055 * doc/install.texi (amdgcn-*-amdhsa): Renamed
5056 from amdgcn-unknown-amdhsa; change
5057 amdgcn-unknown-amdhsa to amdgcn-amdhsa.
5059 2020-03-23 Richard Biener <rguenther@suse.de>
5062 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP
5063 directly rather than also folding it via build_fold_addr_expr.
5065 2020-03-23 Richard Biener <rguenther@suse.de>
5067 PR tree-optimization/94266
5068 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate
5069 addresses of TARGET_MEM_REFs.
5071 2020-03-23 Martin Liska <mliska@suse.cz>
5074 * symtab.c (symtab_node::clone_references): Save speculative_id
5075 as ref may be overwritten by create_reference.
5076 (symtab_node::clone_referring): Likewise.
5077 (symtab_node::clone_reference): Likewise.
5079 2020-03-22 Iain Sandoe <iain@sandoe.co.uk>
5081 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
5082 references to Darwin.
5083 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
5084 unconditionally and comment on why.
5086 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
5088 * config/darwin.c (darwin_mergeable_constant_section): Collect
5089 section anchor checks into the caller.
5090 (machopic_select_section): Collect section anchor checks into
5091 the determination of 'effective zero-size' objects. When the
5092 size is unknown, assume it is non-zero, and thus return the
5093 'generic' section for the DECL.
5095 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
5098 * config/darwin.opt: Amend options descriptions.
5100 2020-03-21 Richard Sandiford <richard.sandiford@arm.com>
5102 PR rtl-optimization/94052
5103 * lra-constraints.c (simplify_operand_subreg): Reload the inner
5104 register of a paradoxical subreg if simplify_subreg_regno fails
5105 to give a valid hard register for the outer mode.
5107 2020-03-20 Martin Jambor <mjambor@suse.cz>
5109 PR tree-optimization/93435
5110 * params.opt (sra-max-propagations): New parameter.
5111 * tree-sra.c (propagation_budget): New variable.
5112 (budget_for_propagation_access): New function.
5113 (propagate_subaccesses_from_rhs): Use it.
5114 (propagate_subaccesses_from_lhs): Likewise.
5115 (propagate_all_subaccesses): Set up and destroy propagation_budget.
5117 2020-03-20 Carl Love <cel@us.ibm.com>
5120 * config/rs6000/rs6000.c (rs6000_option_override_internal):
5121 Add check for TARGET_FPRND for Power 7 or newer.
5123 2020-03-20 Jan Hubicka <hubicka@ucw.cz>
5126 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag.
5127 (cgraph_edge::redirect_callee): Move here; likewise.
5128 (cgraph_node::remove_callees): Update calls_comdat_local flag.
5129 (cgraph_node::verify_node): Verify that calls_comdat_local flag match
5131 (cgraph_node::check_calls_comdat_local_p): New member function.
5132 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare.
5133 (cgraph_edge::redirect_callee): Move offline.
5134 * ipa-fnsummary.c (compute_fn_summary): Do not compute
5135 calls_comdat_local flag here.
5136 * ipa-inline-transform.c (inline_call): Fix updating of
5137 calls_comdat_local flag.
5138 * ipa-split.c (split_function): Use true instead of 1 to set the flag.
5139 * symtab.c (symtab_node::add_to_same_comdat_group): Update
5140 calls_comdat_local flag.
5142 2020-03-20 Richard Biener <rguenther@suse.de>
5144 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree
5145 from the possibly modified root.
5147 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5148 Andre Vieira <andre.simoesdiasvieira@arm.com>
5149 Mihail Ionescu <mihail.ionescu@arm.com>
5151 * config/arm/arm_mve.h (vst1q_p_u8): Define macro.
5152 (vst1q_p_s8): Likewise.
5153 (vst2q_s8): Likewise.
5154 (vst2q_u8): Likewise.
5155 (vld1q_z_u8): Likewise.
5156 (vld1q_z_s8): Likewise.
5157 (vld2q_s8): Likewise.
5158 (vld2q_u8): Likewise.
5159 (vld4q_s8): Likewise.
5160 (vld4q_u8): Likewise.
5161 (vst1q_p_u16): Likewise.
5162 (vst1q_p_s16): Likewise.
5163 (vst2q_s16): Likewise.
5164 (vst2q_u16): Likewise.
5165 (vld1q_z_u16): Likewise.
5166 (vld1q_z_s16): Likewise.
5167 (vld2q_s16): Likewise.
5168 (vld2q_u16): Likewise.
5169 (vld4q_s16): Likewise.
5170 (vld4q_u16): Likewise.
5171 (vst1q_p_u32): Likewise.
5172 (vst1q_p_s32): Likewise.
5173 (vst2q_s32): Likewise.
5174 (vst2q_u32): Likewise.
5175 (vld1q_z_u32): Likewise.
5176 (vld1q_z_s32): Likewise.
5177 (vld2q_s32): Likewise.
5178 (vld2q_u32): Likewise.
5179 (vld4q_s32): Likewise.
5180 (vld4q_u32): Likewise.
5181 (vld4q_f16): Likewise.
5182 (vld2q_f16): Likewise.
5183 (vld1q_z_f16): Likewise.
5184 (vst2q_f16): Likewise.
5185 (vst1q_p_f16): Likewise.
5186 (vld4q_f32): Likewise.
5187 (vld2q_f32): Likewise.
5188 (vld1q_z_f32): Likewise.
5189 (vst2q_f32): Likewise.
5190 (vst1q_p_f32): Likewise.
5191 (__arm_vst1q_p_u8): Define intrinsic.
5192 (__arm_vst1q_p_s8): Likewise.
5193 (__arm_vst2q_s8): Likewise.
5194 (__arm_vst2q_u8): Likewise.
5195 (__arm_vld1q_z_u8): Likewise.
5196 (__arm_vld1q_z_s8): Likewise.
5197 (__arm_vld2q_s8): Likewise.
5198 (__arm_vld2q_u8): Likewise.
5199 (__arm_vld4q_s8): Likewise.
5200 (__arm_vld4q_u8): Likewise.
5201 (__arm_vst1q_p_u16): Likewise.
5202 (__arm_vst1q_p_s16): Likewise.
5203 (__arm_vst2q_s16): Likewise.
5204 (__arm_vst2q_u16): Likewise.
5205 (__arm_vld1q_z_u16): Likewise.
5206 (__arm_vld1q_z_s16): Likewise.
5207 (__arm_vld2q_s16): Likewise.
5208 (__arm_vld2q_u16): Likewise.
5209 (__arm_vld4q_s16): Likewise.
5210 (__arm_vld4q_u16): Likewise.
5211 (__arm_vst1q_p_u32): Likewise.
5212 (__arm_vst1q_p_s32): Likewise.
5213 (__arm_vst2q_s32): Likewise.
5214 (__arm_vst2q_u32): Likewise.
5215 (__arm_vld1q_z_u32): Likewise.
5216 (__arm_vld1q_z_s32): Likewise.
5217 (__arm_vld2q_s32): Likewise.
5218 (__arm_vld2q_u32): Likewise.
5219 (__arm_vld4q_s32): Likewise.
5220 (__arm_vld4q_u32): Likewise.
5221 (__arm_vld4q_f16): Likewise.
5222 (__arm_vld2q_f16): Likewise.
5223 (__arm_vld1q_z_f16): Likewise.
5224 (__arm_vst2q_f16): Likewise.
5225 (__arm_vst1q_p_f16): Likewise.
5226 (__arm_vld4q_f32): Likewise.
5227 (__arm_vld2q_f32): Likewise.
5228 (__arm_vld1q_z_f32): Likewise.
5229 (__arm_vst2q_f32): Likewise.
5230 (__arm_vst1q_p_f32): Likewise.
5231 (vld1q_z): Define polymorphic variant.
5234 (vst1q_p): Likewise.
5236 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier.
5238 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern.
5239 (mve_vld2q<mode>): Likewise.
5240 (mve_vld4q<mode>): Likewise.
5242 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5243 Andre Vieira <andre.simoesdiasvieira@arm.com>
5244 Mihail Ionescu <mihail.ionescu@arm.com>
5246 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define.
5247 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise.
5248 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and
5249 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array.
5250 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC
5251 and ARM_BUILTIN_SET_FPSCR_NZCVQC.
5252 * config/arm/arm_mve.h (vadciq_s32): Define macro.
5253 (vadciq_u32): Likewise.
5254 (vadciq_m_s32): Likewise.
5255 (vadciq_m_u32): Likewise.
5256 (vadcq_s32): Likewise.
5257 (vadcq_u32): Likewise.
5258 (vadcq_m_s32): Likewise.
5259 (vadcq_m_u32): Likewise.
5260 (vsbciq_s32): Likewise.
5261 (vsbciq_u32): Likewise.
5262 (vsbciq_m_s32): Likewise.
5263 (vsbciq_m_u32): Likewise.
5264 (vsbcq_s32): Likewise.
5265 (vsbcq_u32): Likewise.
5266 (vsbcq_m_s32): Likewise.
5267 (vsbcq_m_u32): Likewise.
5268 (__arm_vadciq_s32): Define intrinsic.
5269 (__arm_vadciq_u32): Likewise.
5270 (__arm_vadciq_m_s32): Likewise.
5271 (__arm_vadciq_m_u32): Likewise.
5272 (__arm_vadcq_s32): Likewise.
5273 (__arm_vadcq_u32): Likewise.
5274 (__arm_vadcq_m_s32): Likewise.
5275 (__arm_vadcq_m_u32): Likewise.
5276 (__arm_vsbciq_s32): Likewise.
5277 (__arm_vsbciq_u32): Likewise.
5278 (__arm_vsbciq_m_s32): Likewise.
5279 (__arm_vsbciq_m_u32): Likewise.
5280 (__arm_vsbcq_s32): Likewise.
5281 (__arm_vsbcq_u32): Likewise.
5282 (__arm_vsbcq_m_s32): Likewise.
5283 (__arm_vsbcq_m_u32): Likewise.
5284 (vadciq_m): Define polymorphic variant.
5286 (vadcq_m): Likewise.
5288 (vsbciq_m): Likewise.
5290 (vsbcq_m): Likewise.
5292 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin
5294 (BINOP_UNONE_UNONE_UNONE): Likewise.
5295 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
5296 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
5297 * config/arm/mve.md (VADCIQ): Define iterator.
5298 (VADCIQ_M): Likewise.
5300 (VSBCQ_M): Likewise.
5302 (VSBCIQ_M): Likewise.
5304 (VADCQ_M): Likewise.
5305 (mve_vadciq_m_<supf>v4si): Define RTL pattern.
5306 (mve_vadciq_<supf>v4si): Likewise.
5307 (mve_vadcq_m_<supf>v4si): Likewise.
5308 (mve_vadcq_<supf>v4si): Likewise.
5309 (mve_vsbciq_m_<supf>v4si): Likewise.
5310 (mve_vsbciq_<supf>v4si): Likewise.
5311 (mve_vsbcq_m_<supf>v4si): Likewise.
5312 (mve_vsbcq_<supf>v4si): Likewise.
5313 (get_fpscr_nzcvqc): Define isns.
5314 (set_fpscr_nzcvqc): Define isns.
5315 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define.
5316 (UNSPEC_SET_FPSCR_NZCVQC): Define.
5318 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5320 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
5321 (vddupq_x_n_u16): Likewise.
5322 (vddupq_x_n_u32): Likewise.
5323 (vddupq_x_wb_u8): Likewise.
5324 (vddupq_x_wb_u16): Likewise.
5325 (vddupq_x_wb_u32): Likewise.
5326 (vdwdupq_x_n_u8): Likewise.
5327 (vdwdupq_x_n_u16): Likewise.
5328 (vdwdupq_x_n_u32): Likewise.
5329 (vdwdupq_x_wb_u8): Likewise.
5330 (vdwdupq_x_wb_u16): Likewise.
5331 (vdwdupq_x_wb_u32): Likewise.
5332 (vidupq_x_n_u8): Likewise.
5333 (vidupq_x_n_u16): Likewise.
5334 (vidupq_x_n_u32): Likewise.
5335 (vidupq_x_wb_u8): Likewise.
5336 (vidupq_x_wb_u16): Likewise.
5337 (vidupq_x_wb_u32): Likewise.
5338 (viwdupq_x_n_u8): Likewise.
5339 (viwdupq_x_n_u16): Likewise.
5340 (viwdupq_x_n_u32): Likewise.
5341 (viwdupq_x_wb_u8): Likewise.
5342 (viwdupq_x_wb_u16): Likewise.
5343 (viwdupq_x_wb_u32): Likewise.
5344 (vdupq_x_n_s8): Likewise.
5345 (vdupq_x_n_s16): Likewise.
5346 (vdupq_x_n_s32): Likewise.
5347 (vdupq_x_n_u8): Likewise.
5348 (vdupq_x_n_u16): Likewise.
5349 (vdupq_x_n_u32): Likewise.
5350 (vminq_x_s8): Likewise.
5351 (vminq_x_s16): Likewise.
5352 (vminq_x_s32): Likewise.
5353 (vminq_x_u8): Likewise.
5354 (vminq_x_u16): Likewise.
5355 (vminq_x_u32): Likewise.
5356 (vmaxq_x_s8): Likewise.
5357 (vmaxq_x_s16): Likewise.
5358 (vmaxq_x_s32): Likewise.
5359 (vmaxq_x_u8): Likewise.
5360 (vmaxq_x_u16): Likewise.
5361 (vmaxq_x_u32): Likewise.
5362 (vabdq_x_s8): Likewise.
5363 (vabdq_x_s16): Likewise.
5364 (vabdq_x_s32): Likewise.
5365 (vabdq_x_u8): Likewise.
5366 (vabdq_x_u16): Likewise.
5367 (vabdq_x_u32): Likewise.
5368 (vabsq_x_s8): Likewise.
5369 (vabsq_x_s16): Likewise.
5370 (vabsq_x_s32): Likewise.
5371 (vaddq_x_s8): Likewise.
5372 (vaddq_x_s16): Likewise.
5373 (vaddq_x_s32): Likewise.
5374 (vaddq_x_n_s8): Likewise.
5375 (vaddq_x_n_s16): Likewise.
5376 (vaddq_x_n_s32): Likewise.
5377 (vaddq_x_u8): Likewise.
5378 (vaddq_x_u16): Likewise.
5379 (vaddq_x_u32): Likewise.
5380 (vaddq_x_n_u8): Likewise.
5381 (vaddq_x_n_u16): Likewise.
5382 (vaddq_x_n_u32): Likewise.
5383 (vclsq_x_s8): Likewise.
5384 (vclsq_x_s16): Likewise.
5385 (vclsq_x_s32): Likewise.
5386 (vclzq_x_s8): Likewise.
5387 (vclzq_x_s16): Likewise.
5388 (vclzq_x_s32): Likewise.
5389 (vclzq_x_u8): Likewise.
5390 (vclzq_x_u16): Likewise.
5391 (vclzq_x_u32): Likewise.
5392 (vnegq_x_s8): Likewise.
5393 (vnegq_x_s16): Likewise.
5394 (vnegq_x_s32): Likewise.
5395 (vmulhq_x_s8): Likewise.
5396 (vmulhq_x_s16): Likewise.
5397 (vmulhq_x_s32): Likewise.
5398 (vmulhq_x_u8): Likewise.
5399 (vmulhq_x_u16): Likewise.
5400 (vmulhq_x_u32): Likewise.
5401 (vmullbq_poly_x_p8): Likewise.
5402 (vmullbq_poly_x_p16): Likewise.
5403 (vmullbq_int_x_s8): Likewise.
5404 (vmullbq_int_x_s16): Likewise.
5405 (vmullbq_int_x_s32): Likewise.
5406 (vmullbq_int_x_u8): Likewise.
5407 (vmullbq_int_x_u16): Likewise.
5408 (vmullbq_int_x_u32): Likewise.
5409 (vmulltq_poly_x_p8): Likewise.
5410 (vmulltq_poly_x_p16): Likewise.
5411 (vmulltq_int_x_s8): Likewise.
5412 (vmulltq_int_x_s16): Likewise.
5413 (vmulltq_int_x_s32): Likewise.
5414 (vmulltq_int_x_u8): Likewise.
5415 (vmulltq_int_x_u16): Likewise.
5416 (vmulltq_int_x_u32): Likewise.
5417 (vmulq_x_s8): Likewise.
5418 (vmulq_x_s16): Likewise.
5419 (vmulq_x_s32): Likewise.
5420 (vmulq_x_n_s8): Likewise.
5421 (vmulq_x_n_s16): Likewise.
5422 (vmulq_x_n_s32): Likewise.
5423 (vmulq_x_u8): Likewise.
5424 (vmulq_x_u16): Likewise.
5425 (vmulq_x_u32): Likewise.
5426 (vmulq_x_n_u8): Likewise.
5427 (vmulq_x_n_u16): Likewise.
5428 (vmulq_x_n_u32): Likewise.
5429 (vsubq_x_s8): Likewise.
5430 (vsubq_x_s16): Likewise.
5431 (vsubq_x_s32): Likewise.
5432 (vsubq_x_n_s8): Likewise.
5433 (vsubq_x_n_s16): Likewise.
5434 (vsubq_x_n_s32): Likewise.
5435 (vsubq_x_u8): Likewise.
5436 (vsubq_x_u16): Likewise.
5437 (vsubq_x_u32): Likewise.
5438 (vsubq_x_n_u8): Likewise.
5439 (vsubq_x_n_u16): Likewise.
5440 (vsubq_x_n_u32): Likewise.
5441 (vcaddq_rot90_x_s8): Likewise.
5442 (vcaddq_rot90_x_s16): Likewise.
5443 (vcaddq_rot90_x_s32): Likewise.
5444 (vcaddq_rot90_x_u8): Likewise.
5445 (vcaddq_rot90_x_u16): Likewise.
5446 (vcaddq_rot90_x_u32): Likewise.
5447 (vcaddq_rot270_x_s8): Likewise.
5448 (vcaddq_rot270_x_s16): Likewise.
5449 (vcaddq_rot270_x_s32): Likewise.
5450 (vcaddq_rot270_x_u8): Likewise.
5451 (vcaddq_rot270_x_u16): Likewise.
5452 (vcaddq_rot270_x_u32): Likewise.
5453 (vhaddq_x_n_s8): Likewise.
5454 (vhaddq_x_n_s16): Likewise.
5455 (vhaddq_x_n_s32): Likewise.
5456 (vhaddq_x_n_u8): Likewise.
5457 (vhaddq_x_n_u16): Likewise.
5458 (vhaddq_x_n_u32): Likewise.
5459 (vhaddq_x_s8): Likewise.
5460 (vhaddq_x_s16): Likewise.
5461 (vhaddq_x_s32): Likewise.
5462 (vhaddq_x_u8): Likewise.
5463 (vhaddq_x_u16): Likewise.
5464 (vhaddq_x_u32): Likewise.
5465 (vhcaddq_rot90_x_s8): Likewise.
5466 (vhcaddq_rot90_x_s16): Likewise.
5467 (vhcaddq_rot90_x_s32): Likewise.
5468 (vhcaddq_rot270_x_s8): Likewise.
5469 (vhcaddq_rot270_x_s16): Likewise.
5470 (vhcaddq_rot270_x_s32): Likewise.
5471 (vhsubq_x_n_s8): Likewise.
5472 (vhsubq_x_n_s16): Likewise.
5473 (vhsubq_x_n_s32): Likewise.
5474 (vhsubq_x_n_u8): Likewise.
5475 (vhsubq_x_n_u16): Likewise.
5476 (vhsubq_x_n_u32): Likewise.
5477 (vhsubq_x_s8): Likewise.
5478 (vhsubq_x_s16): Likewise.
5479 (vhsubq_x_s32): Likewise.
5480 (vhsubq_x_u8): Likewise.
5481 (vhsubq_x_u16): Likewise.
5482 (vhsubq_x_u32): Likewise.
5483 (vrhaddq_x_s8): Likewise.
5484 (vrhaddq_x_s16): Likewise.
5485 (vrhaddq_x_s32): Likewise.
5486 (vrhaddq_x_u8): Likewise.
5487 (vrhaddq_x_u16): Likewise.
5488 (vrhaddq_x_u32): Likewise.
5489 (vrmulhq_x_s8): Likewise.
5490 (vrmulhq_x_s16): Likewise.
5491 (vrmulhq_x_s32): Likewise.
5492 (vrmulhq_x_u8): Likewise.
5493 (vrmulhq_x_u16): Likewise.
5494 (vrmulhq_x_u32): Likewise.
5495 (vandq_x_s8): Likewise.
5496 (vandq_x_s16): Likewise.
5497 (vandq_x_s32): Likewise.
5498 (vandq_x_u8): Likewise.
5499 (vandq_x_u16): Likewise.
5500 (vandq_x_u32): Likewise.
5501 (vbicq_x_s8): Likewise.
5502 (vbicq_x_s16): Likewise.
5503 (vbicq_x_s32): Likewise.
5504 (vbicq_x_u8): Likewise.
5505 (vbicq_x_u16): Likewise.
5506 (vbicq_x_u32): Likewise.
5507 (vbrsrq_x_n_s8): Likewise.
5508 (vbrsrq_x_n_s16): Likewise.
5509 (vbrsrq_x_n_s32): Likewise.
5510 (vbrsrq_x_n_u8): Likewise.
5511 (vbrsrq_x_n_u16): Likewise.
5512 (vbrsrq_x_n_u32): Likewise.
5513 (veorq_x_s8): Likewise.
5514 (veorq_x_s16): Likewise.
5515 (veorq_x_s32): Likewise.
5516 (veorq_x_u8): Likewise.
5517 (veorq_x_u16): Likewise.
5518 (veorq_x_u32): Likewise.
5519 (vmovlbq_x_s8): Likewise.
5520 (vmovlbq_x_s16): Likewise.
5521 (vmovlbq_x_u8): Likewise.
5522 (vmovlbq_x_u16): Likewise.
5523 (vmovltq_x_s8): Likewise.
5524 (vmovltq_x_s16): Likewise.
5525 (vmovltq_x_u8): Likewise.
5526 (vmovltq_x_u16): Likewise.
5527 (vmvnq_x_s8): Likewise.
5528 (vmvnq_x_s16): Likewise.
5529 (vmvnq_x_s32): Likewise.
5530 (vmvnq_x_u8): Likewise.
5531 (vmvnq_x_u16): Likewise.
5532 (vmvnq_x_u32): Likewise.
5533 (vmvnq_x_n_s16): Likewise.
5534 (vmvnq_x_n_s32): Likewise.
5535 (vmvnq_x_n_u16): Likewise.
5536 (vmvnq_x_n_u32): Likewise.
5537 (vornq_x_s8): Likewise.
5538 (vornq_x_s16): Likewise.
5539 (vornq_x_s32): Likewise.
5540 (vornq_x_u8): Likewise.
5541 (vornq_x_u16): Likewise.
5542 (vornq_x_u32): Likewise.
5543 (vorrq_x_s8): Likewise.
5544 (vorrq_x_s16): Likewise.
5545 (vorrq_x_s32): Likewise.
5546 (vorrq_x_u8): Likewise.
5547 (vorrq_x_u16): Likewise.
5548 (vorrq_x_u32): Likewise.
5549 (vrev16q_x_s8): Likewise.
5550 (vrev16q_x_u8): Likewise.
5551 (vrev32q_x_s8): Likewise.
5552 (vrev32q_x_s16): Likewise.
5553 (vrev32q_x_u8): Likewise.
5554 (vrev32q_x_u16): Likewise.
5555 (vrev64q_x_s8): Likewise.
5556 (vrev64q_x_s16): Likewise.
5557 (vrev64q_x_s32): Likewise.
5558 (vrev64q_x_u8): Likewise.
5559 (vrev64q_x_u16): Likewise.
5560 (vrev64q_x_u32): Likewise.
5561 (vrshlq_x_s8): Likewise.
5562 (vrshlq_x_s16): Likewise.
5563 (vrshlq_x_s32): Likewise.
5564 (vrshlq_x_u8): Likewise.
5565 (vrshlq_x_u16): Likewise.
5566 (vrshlq_x_u32): Likewise.
5567 (vshllbq_x_n_s8): Likewise.
5568 (vshllbq_x_n_s16): Likewise.
5569 (vshllbq_x_n_u8): Likewise.
5570 (vshllbq_x_n_u16): Likewise.
5571 (vshlltq_x_n_s8): Likewise.
5572 (vshlltq_x_n_s16): Likewise.
5573 (vshlltq_x_n_u8): Likewise.
5574 (vshlltq_x_n_u16): Likewise.
5575 (vshlq_x_s8): Likewise.
5576 (vshlq_x_s16): Likewise.
5577 (vshlq_x_s32): Likewise.
5578 (vshlq_x_u8): Likewise.
5579 (vshlq_x_u16): Likewise.
5580 (vshlq_x_u32): Likewise.
5581 (vshlq_x_n_s8): Likewise.
5582 (vshlq_x_n_s16): Likewise.
5583 (vshlq_x_n_s32): Likewise.
5584 (vshlq_x_n_u8): Likewise.
5585 (vshlq_x_n_u16): Likewise.
5586 (vshlq_x_n_u32): Likewise.
5587 (vrshrq_x_n_s8): Likewise.
5588 (vrshrq_x_n_s16): Likewise.
5589 (vrshrq_x_n_s32): Likewise.
5590 (vrshrq_x_n_u8): Likewise.
5591 (vrshrq_x_n_u16): Likewise.
5592 (vrshrq_x_n_u32): Likewise.
5593 (vshrq_x_n_s8): Likewise.
5594 (vshrq_x_n_s16): Likewise.
5595 (vshrq_x_n_s32): Likewise.
5596 (vshrq_x_n_u8): Likewise.
5597 (vshrq_x_n_u16): Likewise.
5598 (vshrq_x_n_u32): Likewise.
5599 (vdupq_x_n_f16): Likewise.
5600 (vdupq_x_n_f32): Likewise.
5601 (vminnmq_x_f16): Likewise.
5602 (vminnmq_x_f32): Likewise.
5603 (vmaxnmq_x_f16): Likewise.
5604 (vmaxnmq_x_f32): Likewise.
5605 (vabdq_x_f16): Likewise.
5606 (vabdq_x_f32): Likewise.
5607 (vabsq_x_f16): Likewise.
5608 (vabsq_x_f32): Likewise.
5609 (vaddq_x_f16): Likewise.
5610 (vaddq_x_f32): Likewise.
5611 (vaddq_x_n_f16): Likewise.
5612 (vaddq_x_n_f32): Likewise.
5613 (vnegq_x_f16): Likewise.
5614 (vnegq_x_f32): Likewise.
5615 (vmulq_x_f16): Likewise.
5616 (vmulq_x_f32): Likewise.
5617 (vmulq_x_n_f16): Likewise.
5618 (vmulq_x_n_f32): Likewise.
5619 (vsubq_x_f16): Likewise.
5620 (vsubq_x_f32): Likewise.
5621 (vsubq_x_n_f16): Likewise.
5622 (vsubq_x_n_f32): Likewise.
5623 (vcaddq_rot90_x_f16): Likewise.
5624 (vcaddq_rot90_x_f32): Likewise.
5625 (vcaddq_rot270_x_f16): Likewise.
5626 (vcaddq_rot270_x_f32): Likewise.
5627 (vcmulq_x_f16): Likewise.
5628 (vcmulq_x_f32): Likewise.
5629 (vcmulq_rot90_x_f16): Likewise.
5630 (vcmulq_rot90_x_f32): Likewise.
5631 (vcmulq_rot180_x_f16): Likewise.
5632 (vcmulq_rot180_x_f32): Likewise.
5633 (vcmulq_rot270_x_f16): Likewise.
5634 (vcmulq_rot270_x_f32): Likewise.
5635 (vcvtaq_x_s16_f16): Likewise.
5636 (vcvtaq_x_s32_f32): Likewise.
5637 (vcvtaq_x_u16_f16): Likewise.
5638 (vcvtaq_x_u32_f32): Likewise.
5639 (vcvtnq_x_s16_f16): Likewise.
5640 (vcvtnq_x_s32_f32): Likewise.
5641 (vcvtnq_x_u16_f16): Likewise.
5642 (vcvtnq_x_u32_f32): Likewise.
5643 (vcvtpq_x_s16_f16): Likewise.
5644 (vcvtpq_x_s32_f32): Likewise.
5645 (vcvtpq_x_u16_f16): Likewise.
5646 (vcvtpq_x_u32_f32): Likewise.
5647 (vcvtmq_x_s16_f16): Likewise.
5648 (vcvtmq_x_s32_f32): Likewise.
5649 (vcvtmq_x_u16_f16): Likewise.
5650 (vcvtmq_x_u32_f32): Likewise.
5651 (vcvtbq_x_f32_f16): Likewise.
5652 (vcvttq_x_f32_f16): Likewise.
5653 (vcvtq_x_f16_u16): Likewise.
5654 (vcvtq_x_f16_s16): Likewise.
5655 (vcvtq_x_f32_s32): Likewise.
5656 (vcvtq_x_f32_u32): Likewise.
5657 (vcvtq_x_n_f16_s16): Likewise.
5658 (vcvtq_x_n_f16_u16): Likewise.
5659 (vcvtq_x_n_f32_s32): Likewise.
5660 (vcvtq_x_n_f32_u32): Likewise.
5661 (vcvtq_x_s16_f16): Likewise.
5662 (vcvtq_x_s32_f32): Likewise.
5663 (vcvtq_x_u16_f16): Likewise.
5664 (vcvtq_x_u32_f32): Likewise.
5665 (vcvtq_x_n_s16_f16): Likewise.
5666 (vcvtq_x_n_s32_f32): Likewise.
5667 (vcvtq_x_n_u16_f16): Likewise.
5668 (vcvtq_x_n_u32_f32): Likewise.
5669 (vrndq_x_f16): Likewise.
5670 (vrndq_x_f32): Likewise.
5671 (vrndnq_x_f16): Likewise.
5672 (vrndnq_x_f32): Likewise.
5673 (vrndmq_x_f16): Likewise.
5674 (vrndmq_x_f32): Likewise.
5675 (vrndpq_x_f16): Likewise.
5676 (vrndpq_x_f32): Likewise.
5677 (vrndaq_x_f16): Likewise.
5678 (vrndaq_x_f32): Likewise.
5679 (vrndxq_x_f16): Likewise.
5680 (vrndxq_x_f32): Likewise.
5681 (vandq_x_f16): Likewise.
5682 (vandq_x_f32): Likewise.
5683 (vbicq_x_f16): Likewise.
5684 (vbicq_x_f32): Likewise.
5685 (vbrsrq_x_n_f16): Likewise.
5686 (vbrsrq_x_n_f32): Likewise.
5687 (veorq_x_f16): Likewise.
5688 (veorq_x_f32): Likewise.
5689 (vornq_x_f16): Likewise.
5690 (vornq_x_f32): Likewise.
5691 (vorrq_x_f16): Likewise.
5692 (vorrq_x_f32): Likewise.
5693 (vrev32q_x_f16): Likewise.
5694 (vrev64q_x_f16): Likewise.
5695 (vrev64q_x_f32): Likewise.
5696 (__arm_vddupq_x_n_u8): Define intrinsic.
5697 (__arm_vddupq_x_n_u16): Likewise.
5698 (__arm_vddupq_x_n_u32): Likewise.
5699 (__arm_vddupq_x_wb_u8): Likewise.
5700 (__arm_vddupq_x_wb_u16): Likewise.
5701 (__arm_vddupq_x_wb_u32): Likewise.
5702 (__arm_vdwdupq_x_n_u8): Likewise.
5703 (__arm_vdwdupq_x_n_u16): Likewise.
5704 (__arm_vdwdupq_x_n_u32): Likewise.
5705 (__arm_vdwdupq_x_wb_u8): Likewise.
5706 (__arm_vdwdupq_x_wb_u16): Likewise.
5707 (__arm_vdwdupq_x_wb_u32): Likewise.
5708 (__arm_vidupq_x_n_u8): Likewise.
5709 (__arm_vidupq_x_n_u16): Likewise.
5710 (__arm_vidupq_x_n_u32): Likewise.
5711 (__arm_vidupq_x_wb_u8): Likewise.
5712 (__arm_vidupq_x_wb_u16): Likewise.
5713 (__arm_vidupq_x_wb_u32): Likewise.
5714 (__arm_viwdupq_x_n_u8): Likewise.
5715 (__arm_viwdupq_x_n_u16): Likewise.
5716 (__arm_viwdupq_x_n_u32): Likewise.
5717 (__arm_viwdupq_x_wb_u8): Likewise.
5718 (__arm_viwdupq_x_wb_u16): Likewise.
5719 (__arm_viwdupq_x_wb_u32): Likewise.
5720 (__arm_vdupq_x_n_s8): Likewise.
5721 (__arm_vdupq_x_n_s16): Likewise.
5722 (__arm_vdupq_x_n_s32): Likewise.
5723 (__arm_vdupq_x_n_u8): Likewise.
5724 (__arm_vdupq_x_n_u16): Likewise.
5725 (__arm_vdupq_x_n_u32): Likewise.
5726 (__arm_vminq_x_s8): Likewise.
5727 (__arm_vminq_x_s16): Likewise.
5728 (__arm_vminq_x_s32): Likewise.
5729 (__arm_vminq_x_u8): Likewise.
5730 (__arm_vminq_x_u16): Likewise.
5731 (__arm_vminq_x_u32): Likewise.
5732 (__arm_vmaxq_x_s8): Likewise.
5733 (__arm_vmaxq_x_s16): Likewise.
5734 (__arm_vmaxq_x_s32): Likewise.
5735 (__arm_vmaxq_x_u8): Likewise.
5736 (__arm_vmaxq_x_u16): Likewise.
5737 (__arm_vmaxq_x_u32): Likewise.
5738 (__arm_vabdq_x_s8): Likewise.
5739 (__arm_vabdq_x_s16): Likewise.
5740 (__arm_vabdq_x_s32): Likewise.
5741 (__arm_vabdq_x_u8): Likewise.
5742 (__arm_vabdq_x_u16): Likewise.
5743 (__arm_vabdq_x_u32): Likewise.
5744 (__arm_vabsq_x_s8): Likewise.
5745 (__arm_vabsq_x_s16): Likewise.
5746 (__arm_vabsq_x_s32): Likewise.
5747 (__arm_vaddq_x_s8): Likewise.
5748 (__arm_vaddq_x_s16): Likewise.
5749 (__arm_vaddq_x_s32): Likewise.
5750 (__arm_vaddq_x_n_s8): Likewise.
5751 (__arm_vaddq_x_n_s16): Likewise.
5752 (__arm_vaddq_x_n_s32): Likewise.
5753 (__arm_vaddq_x_u8): Likewise.
5754 (__arm_vaddq_x_u16): Likewise.
5755 (__arm_vaddq_x_u32): Likewise.
5756 (__arm_vaddq_x_n_u8): Likewise.
5757 (__arm_vaddq_x_n_u16): Likewise.
5758 (__arm_vaddq_x_n_u32): Likewise.
5759 (__arm_vclsq_x_s8): Likewise.
5760 (__arm_vclsq_x_s16): Likewise.
5761 (__arm_vclsq_x_s32): Likewise.
5762 (__arm_vclzq_x_s8): Likewise.
5763 (__arm_vclzq_x_s16): Likewise.
5764 (__arm_vclzq_x_s32): Likewise.
5765 (__arm_vclzq_x_u8): Likewise.
5766 (__arm_vclzq_x_u16): Likewise.
5767 (__arm_vclzq_x_u32): Likewise.
5768 (__arm_vnegq_x_s8): Likewise.
5769 (__arm_vnegq_x_s16): Likewise.
5770 (__arm_vnegq_x_s32): Likewise.
5771 (__arm_vmulhq_x_s8): Likewise.
5772 (__arm_vmulhq_x_s16): Likewise.
5773 (__arm_vmulhq_x_s32): Likewise.
5774 (__arm_vmulhq_x_u8): Likewise.
5775 (__arm_vmulhq_x_u16): Likewise.
5776 (__arm_vmulhq_x_u32): Likewise.
5777 (__arm_vmullbq_poly_x_p8): Likewise.
5778 (__arm_vmullbq_poly_x_p16): Likewise.
5779 (__arm_vmullbq_int_x_s8): Likewise.
5780 (__arm_vmullbq_int_x_s16): Likewise.
5781 (__arm_vmullbq_int_x_s32): Likewise.
5782 (__arm_vmullbq_int_x_u8): Likewise.
5783 (__arm_vmullbq_int_x_u16): Likewise.
5784 (__arm_vmullbq_int_x_u32): Likewise.
5785 (__arm_vmulltq_poly_x_p8): Likewise.
5786 (__arm_vmulltq_poly_x_p16): Likewise.
5787 (__arm_vmulltq_int_x_s8): Likewise.
5788 (__arm_vmulltq_int_x_s16): Likewise.
5789 (__arm_vmulltq_int_x_s32): Likewise.
5790 (__arm_vmulltq_int_x_u8): Likewise.
5791 (__arm_vmulltq_int_x_u16): Likewise.
5792 (__arm_vmulltq_int_x_u32): Likewise.
5793 (__arm_vmulq_x_s8): Likewise.
5794 (__arm_vmulq_x_s16): Likewise.
5795 (__arm_vmulq_x_s32): Likewise.
5796 (__arm_vmulq_x_n_s8): Likewise.
5797 (__arm_vmulq_x_n_s16): Likewise.
5798 (__arm_vmulq_x_n_s32): Likewise.
5799 (__arm_vmulq_x_u8): Likewise.
5800 (__arm_vmulq_x_u16): Likewise.
5801 (__arm_vmulq_x_u32): Likewise.
5802 (__arm_vmulq_x_n_u8): Likewise.
5803 (__arm_vmulq_x_n_u16): Likewise.
5804 (__arm_vmulq_x_n_u32): Likewise.
5805 (__arm_vsubq_x_s8): Likewise.
5806 (__arm_vsubq_x_s16): Likewise.
5807 (__arm_vsubq_x_s32): Likewise.
5808 (__arm_vsubq_x_n_s8): Likewise.
5809 (__arm_vsubq_x_n_s16): Likewise.
5810 (__arm_vsubq_x_n_s32): Likewise.
5811 (__arm_vsubq_x_u8): Likewise.
5812 (__arm_vsubq_x_u16): Likewise.
5813 (__arm_vsubq_x_u32): Likewise.
5814 (__arm_vsubq_x_n_u8): Likewise.
5815 (__arm_vsubq_x_n_u16): Likewise.
5816 (__arm_vsubq_x_n_u32): Likewise.
5817 (__arm_vcaddq_rot90_x_s8): Likewise.
5818 (__arm_vcaddq_rot90_x_s16): Likewise.
5819 (__arm_vcaddq_rot90_x_s32): Likewise.
5820 (__arm_vcaddq_rot90_x_u8): Likewise.
5821 (__arm_vcaddq_rot90_x_u16): Likewise.
5822 (__arm_vcaddq_rot90_x_u32): Likewise.
5823 (__arm_vcaddq_rot270_x_s8): Likewise.
5824 (__arm_vcaddq_rot270_x_s16): Likewise.
5825 (__arm_vcaddq_rot270_x_s32): Likewise.
5826 (__arm_vcaddq_rot270_x_u8): Likewise.
5827 (__arm_vcaddq_rot270_x_u16): Likewise.
5828 (__arm_vcaddq_rot270_x_u32): Likewise.
5829 (__arm_vhaddq_x_n_s8): Likewise.
5830 (__arm_vhaddq_x_n_s16): Likewise.
5831 (__arm_vhaddq_x_n_s32): Likewise.
5832 (__arm_vhaddq_x_n_u8): Likewise.
5833 (__arm_vhaddq_x_n_u16): Likewise.
5834 (__arm_vhaddq_x_n_u32): Likewise.
5835 (__arm_vhaddq_x_s8): Likewise.
5836 (__arm_vhaddq_x_s16): Likewise.
5837 (__arm_vhaddq_x_s32): Likewise.
5838 (__arm_vhaddq_x_u8): Likewise.
5839 (__arm_vhaddq_x_u16): Likewise.
5840 (__arm_vhaddq_x_u32): Likewise.
5841 (__arm_vhcaddq_rot90_x_s8): Likewise.
5842 (__arm_vhcaddq_rot90_x_s16): Likewise.
5843 (__arm_vhcaddq_rot90_x_s32): Likewise.
5844 (__arm_vhcaddq_rot270_x_s8): Likewise.
5845 (__arm_vhcaddq_rot270_x_s16): Likewise.
5846 (__arm_vhcaddq_rot270_x_s32): Likewise.
5847 (__arm_vhsubq_x_n_s8): Likewise.
5848 (__arm_vhsubq_x_n_s16): Likewise.
5849 (__arm_vhsubq_x_n_s32): Likewise.
5850 (__arm_vhsubq_x_n_u8): Likewise.
5851 (__arm_vhsubq_x_n_u16): Likewise.
5852 (__arm_vhsubq_x_n_u32): Likewise.
5853 (__arm_vhsubq_x_s8): Likewise.
5854 (__arm_vhsubq_x_s16): Likewise.
5855 (__arm_vhsubq_x_s32): Likewise.
5856 (__arm_vhsubq_x_u8): Likewise.
5857 (__arm_vhsubq_x_u16): Likewise.
5858 (__arm_vhsubq_x_u32): Likewise.
5859 (__arm_vrhaddq_x_s8): Likewise.
5860 (__arm_vrhaddq_x_s16): Likewise.
5861 (__arm_vrhaddq_x_s32): Likewise.
5862 (__arm_vrhaddq_x_u8): Likewise.
5863 (__arm_vrhaddq_x_u16): Likewise.
5864 (__arm_vrhaddq_x_u32): Likewise.
5865 (__arm_vrmulhq_x_s8): Likewise.
5866 (__arm_vrmulhq_x_s16): Likewise.
5867 (__arm_vrmulhq_x_s32): Likewise.
5868 (__arm_vrmulhq_x_u8): Likewise.
5869 (__arm_vrmulhq_x_u16): Likewise.
5870 (__arm_vrmulhq_x_u32): Likewise.
5871 (__arm_vandq_x_s8): Likewise.
5872 (__arm_vandq_x_s16): Likewise.
5873 (__arm_vandq_x_s32): Likewise.
5874 (__arm_vandq_x_u8): Likewise.
5875 (__arm_vandq_x_u16): Likewise.
5876 (__arm_vandq_x_u32): Likewise.
5877 (__arm_vbicq_x_s8): Likewise.
5878 (__arm_vbicq_x_s16): Likewise.
5879 (__arm_vbicq_x_s32): Likewise.
5880 (__arm_vbicq_x_u8): Likewise.
5881 (__arm_vbicq_x_u16): Likewise.
5882 (__arm_vbicq_x_u32): Likewise.
5883 (__arm_vbrsrq_x_n_s8): Likewise.
5884 (__arm_vbrsrq_x_n_s16): Likewise.
5885 (__arm_vbrsrq_x_n_s32): Likewise.
5886 (__arm_vbrsrq_x_n_u8): Likewise.
5887 (__arm_vbrsrq_x_n_u16): Likewise.
5888 (__arm_vbrsrq_x_n_u32): Likewise.
5889 (__arm_veorq_x_s8): Likewise.
5890 (__arm_veorq_x_s16): Likewise.
5891 (__arm_veorq_x_s32): Likewise.
5892 (__arm_veorq_x_u8): Likewise.
5893 (__arm_veorq_x_u16): Likewise.
5894 (__arm_veorq_x_u32): Likewise.
5895 (__arm_vmovlbq_x_s8): Likewise.
5896 (__arm_vmovlbq_x_s16): Likewise.
5897 (__arm_vmovlbq_x_u8): Likewise.
5898 (__arm_vmovlbq_x_u16): Likewise.
5899 (__arm_vmovltq_x_s8): Likewise.
5900 (__arm_vmovltq_x_s16): Likewise.
5901 (__arm_vmovltq_x_u8): Likewise.
5902 (__arm_vmovltq_x_u16): Likewise.
5903 (__arm_vmvnq_x_s8): Likewise.
5904 (__arm_vmvnq_x_s16): Likewise.
5905 (__arm_vmvnq_x_s32): Likewise.
5906 (__arm_vmvnq_x_u8): Likewise.
5907 (__arm_vmvnq_x_u16): Likewise.
5908 (__arm_vmvnq_x_u32): Likewise.
5909 (__arm_vmvnq_x_n_s16): Likewise.
5910 (__arm_vmvnq_x_n_s32): Likewise.
5911 (__arm_vmvnq_x_n_u16): Likewise.
5912 (__arm_vmvnq_x_n_u32): Likewise.
5913 (__arm_vornq_x_s8): Likewise.
5914 (__arm_vornq_x_s16): Likewise.
5915 (__arm_vornq_x_s32): Likewise.
5916 (__arm_vornq_x_u8): Likewise.
5917 (__arm_vornq_x_u16): Likewise.
5918 (__arm_vornq_x_u32): Likewise.
5919 (__arm_vorrq_x_s8): Likewise.
5920 (__arm_vorrq_x_s16): Likewise.
5921 (__arm_vorrq_x_s32): Likewise.
5922 (__arm_vorrq_x_u8): Likewise.
5923 (__arm_vorrq_x_u16): Likewise.
5924 (__arm_vorrq_x_u32): Likewise.
5925 (__arm_vrev16q_x_s8): Likewise.
5926 (__arm_vrev16q_x_u8): Likewise.
5927 (__arm_vrev32q_x_s8): Likewise.
5928 (__arm_vrev32q_x_s16): Likewise.
5929 (__arm_vrev32q_x_u8): Likewise.
5930 (__arm_vrev32q_x_u16): Likewise.
5931 (__arm_vrev64q_x_s8): Likewise.
5932 (__arm_vrev64q_x_s16): Likewise.
5933 (__arm_vrev64q_x_s32): Likewise.
5934 (__arm_vrev64q_x_u8): Likewise.
5935 (__arm_vrev64q_x_u16): Likewise.
5936 (__arm_vrev64q_x_u32): Likewise.
5937 (__arm_vrshlq_x_s8): Likewise.
5938 (__arm_vrshlq_x_s16): Likewise.
5939 (__arm_vrshlq_x_s32): Likewise.
5940 (__arm_vrshlq_x_u8): Likewise.
5941 (__arm_vrshlq_x_u16): Likewise.
5942 (__arm_vrshlq_x_u32): Likewise.
5943 (__arm_vshllbq_x_n_s8): Likewise.
5944 (__arm_vshllbq_x_n_s16): Likewise.
5945 (__arm_vshllbq_x_n_u8): Likewise.
5946 (__arm_vshllbq_x_n_u16): Likewise.
5947 (__arm_vshlltq_x_n_s8): Likewise.
5948 (__arm_vshlltq_x_n_s16): Likewise.
5949 (__arm_vshlltq_x_n_u8): Likewise.
5950 (__arm_vshlltq_x_n_u16): Likewise.
5951 (__arm_vshlq_x_s8): Likewise.
5952 (__arm_vshlq_x_s16): Likewise.
5953 (__arm_vshlq_x_s32): Likewise.
5954 (__arm_vshlq_x_u8): Likewise.
5955 (__arm_vshlq_x_u16): Likewise.
5956 (__arm_vshlq_x_u32): Likewise.
5957 (__arm_vshlq_x_n_s8): Likewise.
5958 (__arm_vshlq_x_n_s16): Likewise.
5959 (__arm_vshlq_x_n_s32): Likewise.
5960 (__arm_vshlq_x_n_u8): Likewise.
5961 (__arm_vshlq_x_n_u16): Likewise.
5962 (__arm_vshlq_x_n_u32): Likewise.
5963 (__arm_vrshrq_x_n_s8): Likewise.
5964 (__arm_vrshrq_x_n_s16): Likewise.
5965 (__arm_vrshrq_x_n_s32): Likewise.
5966 (__arm_vrshrq_x_n_u8): Likewise.
5967 (__arm_vrshrq_x_n_u16): Likewise.
5968 (__arm_vrshrq_x_n_u32): Likewise.
5969 (__arm_vshrq_x_n_s8): Likewise.
5970 (__arm_vshrq_x_n_s16): Likewise.
5971 (__arm_vshrq_x_n_s32): Likewise.
5972 (__arm_vshrq_x_n_u8): Likewise.
5973 (__arm_vshrq_x_n_u16): Likewise.
5974 (__arm_vshrq_x_n_u32): Likewise.
5975 (__arm_vdupq_x_n_f16): Likewise.
5976 (__arm_vdupq_x_n_f32): Likewise.
5977 (__arm_vminnmq_x_f16): Likewise.
5978 (__arm_vminnmq_x_f32): Likewise.
5979 (__arm_vmaxnmq_x_f16): Likewise.
5980 (__arm_vmaxnmq_x_f32): Likewise.
5981 (__arm_vabdq_x_f16): Likewise.
5982 (__arm_vabdq_x_f32): Likewise.
5983 (__arm_vabsq_x_f16): Likewise.
5984 (__arm_vabsq_x_f32): Likewise.
5985 (__arm_vaddq_x_f16): Likewise.
5986 (__arm_vaddq_x_f32): Likewise.
5987 (__arm_vaddq_x_n_f16): Likewise.
5988 (__arm_vaddq_x_n_f32): Likewise.
5989 (__arm_vnegq_x_f16): Likewise.
5990 (__arm_vnegq_x_f32): Likewise.
5991 (__arm_vmulq_x_f16): Likewise.
5992 (__arm_vmulq_x_f32): Likewise.
5993 (__arm_vmulq_x_n_f16): Likewise.
5994 (__arm_vmulq_x_n_f32): Likewise.
5995 (__arm_vsubq_x_f16): Likewise.
5996 (__arm_vsubq_x_f32): Likewise.
5997 (__arm_vsubq_x_n_f16): Likewise.
5998 (__arm_vsubq_x_n_f32): Likewise.
5999 (__arm_vcaddq_rot90_x_f16): Likewise.
6000 (__arm_vcaddq_rot90_x_f32): Likewise.
6001 (__arm_vcaddq_rot270_x_f16): Likewise.
6002 (__arm_vcaddq_rot270_x_f32): Likewise.
6003 (__arm_vcmulq_x_f16): Likewise.
6004 (__arm_vcmulq_x_f32): Likewise.
6005 (__arm_vcmulq_rot90_x_f16): Likewise.
6006 (__arm_vcmulq_rot90_x_f32): Likewise.
6007 (__arm_vcmulq_rot180_x_f16): Likewise.
6008 (__arm_vcmulq_rot180_x_f32): Likewise.
6009 (__arm_vcmulq_rot270_x_f16): Likewise.
6010 (__arm_vcmulq_rot270_x_f32): Likewise.
6011 (__arm_vcvtaq_x_s16_f16): Likewise.
6012 (__arm_vcvtaq_x_s32_f32): Likewise.
6013 (__arm_vcvtaq_x_u16_f16): Likewise.
6014 (__arm_vcvtaq_x_u32_f32): Likewise.
6015 (__arm_vcvtnq_x_s16_f16): Likewise.
6016 (__arm_vcvtnq_x_s32_f32): Likewise.
6017 (__arm_vcvtnq_x_u16_f16): Likewise.
6018 (__arm_vcvtnq_x_u32_f32): Likewise.
6019 (__arm_vcvtpq_x_s16_f16): Likewise.
6020 (__arm_vcvtpq_x_s32_f32): Likewise.
6021 (__arm_vcvtpq_x_u16_f16): Likewise.
6022 (__arm_vcvtpq_x_u32_f32): Likewise.
6023 (__arm_vcvtmq_x_s16_f16): Likewise.
6024 (__arm_vcvtmq_x_s32_f32): Likewise.
6025 (__arm_vcvtmq_x_u16_f16): Likewise.
6026 (__arm_vcvtmq_x_u32_f32): Likewise.
6027 (__arm_vcvtbq_x_f32_f16): Likewise.
6028 (__arm_vcvttq_x_f32_f16): Likewise.
6029 (__arm_vcvtq_x_f16_u16): Likewise.
6030 (__arm_vcvtq_x_f16_s16): Likewise.
6031 (__arm_vcvtq_x_f32_s32): Likewise.
6032 (__arm_vcvtq_x_f32_u32): Likewise.
6033 (__arm_vcvtq_x_n_f16_s16): Likewise.
6034 (__arm_vcvtq_x_n_f16_u16): Likewise.
6035 (__arm_vcvtq_x_n_f32_s32): Likewise.
6036 (__arm_vcvtq_x_n_f32_u32): Likewise.
6037 (__arm_vcvtq_x_s16_f16): Likewise.
6038 (__arm_vcvtq_x_s32_f32): Likewise.
6039 (__arm_vcvtq_x_u16_f16): Likewise.
6040 (__arm_vcvtq_x_u32_f32): Likewise.
6041 (__arm_vcvtq_x_n_s16_f16): Likewise.
6042 (__arm_vcvtq_x_n_s32_f32): Likewise.
6043 (__arm_vcvtq_x_n_u16_f16): Likewise.
6044 (__arm_vcvtq_x_n_u32_f32): Likewise.
6045 (__arm_vrndq_x_f16): Likewise.
6046 (__arm_vrndq_x_f32): Likewise.
6047 (__arm_vrndnq_x_f16): Likewise.
6048 (__arm_vrndnq_x_f32): Likewise.
6049 (__arm_vrndmq_x_f16): Likewise.
6050 (__arm_vrndmq_x_f32): Likewise.
6051 (__arm_vrndpq_x_f16): Likewise.
6052 (__arm_vrndpq_x_f32): Likewise.
6053 (__arm_vrndaq_x_f16): Likewise.
6054 (__arm_vrndaq_x_f32): Likewise.
6055 (__arm_vrndxq_x_f16): Likewise.
6056 (__arm_vrndxq_x_f32): Likewise.
6057 (__arm_vandq_x_f16): Likewise.
6058 (__arm_vandq_x_f32): Likewise.
6059 (__arm_vbicq_x_f16): Likewise.
6060 (__arm_vbicq_x_f32): Likewise.
6061 (__arm_vbrsrq_x_n_f16): Likewise.
6062 (__arm_vbrsrq_x_n_f32): Likewise.
6063 (__arm_veorq_x_f16): Likewise.
6064 (__arm_veorq_x_f32): Likewise.
6065 (__arm_vornq_x_f16): Likewise.
6066 (__arm_vornq_x_f32): Likewise.
6067 (__arm_vorrq_x_f16): Likewise.
6068 (__arm_vorrq_x_f32): Likewise.
6069 (__arm_vrev32q_x_f16): Likewise.
6070 (__arm_vrev64q_x_f16): Likewise.
6071 (__arm_vrev64q_x_f32): Likewise.
6072 (vabdq_x): Define polymorphic variant.
6073 (vabsq_x): Likewise.
6074 (vaddq_x): Likewise.
6075 (vandq_x): Likewise.
6076 (vbicq_x): Likewise.
6077 (vbrsrq_x): Likewise.
6078 (vcaddq_rot270_x): Likewise.
6079 (vcaddq_rot90_x): Likewise.
6080 (vcmulq_rot180_x): Likewise.
6081 (vcmulq_rot270_x): Likewise.
6082 (vcmulq_x): Likewise.
6083 (vcvtq_x): Likewise.
6084 (vcvtq_x_n): Likewise.
6085 (vcvtnq_m): Likewise.
6086 (veorq_x): Likewise.
6087 (vmaxnmq_x): Likewise.
6088 (vminnmq_x): Likewise.
6089 (vmulq_x): Likewise.
6090 (vnegq_x): Likewise.
6091 (vornq_x): Likewise.
6092 (vorrq_x): Likewise.
6093 (vrev32q_x): Likewise.
6094 (vrev64q_x): Likewise.
6095 (vrndaq_x): Likewise.
6096 (vrndmq_x): Likewise.
6097 (vrndnq_x): Likewise.
6098 (vrndpq_x): Likewise.
6099 (vrndq_x): Likewise.
6100 (vrndxq_x): Likewise.
6101 (vsubq_x): Likewise.
6102 (vcmulq_rot90_x): Likewise.
6104 (vclsq_x): Likewise.
6105 (vclzq_x): Likewise.
6106 (vhaddq_x): Likewise.
6107 (vhcaddq_rot270_x): Likewise.
6108 (vhcaddq_rot90_x): Likewise.
6109 (vhsubq_x): Likewise.
6110 (vmaxq_x): Likewise.
6111 (vminq_x): Likewise.
6112 (vmovlbq_x): Likewise.
6113 (vmovltq_x): Likewise.
6114 (vmulhq_x): Likewise.
6115 (vmullbq_int_x): Likewise.
6116 (vmullbq_poly_x): Likewise.
6117 (vmulltq_int_x): Likewise.
6118 (vmulltq_poly_x): Likewise.
6119 (vmvnq_x): Likewise.
6120 (vrev16q_x): Likewise.
6121 (vrhaddq_x): Likewise.
6122 (vrmulhq_x): Likewise.
6123 (vrshlq_x): Likewise.
6124 (vrshrq_x): Likewise.
6125 (vshllbq_x): Likewise.
6126 (vshlltq_x): Likewise.
6127 (vshlq_x_n): Likewise.
6128 (vshlq_x): Likewise.
6129 (vdwdupq_x_u8): Likewise.
6130 (vdwdupq_x_u16): Likewise.
6131 (vdwdupq_x_u32): Likewise.
6132 (viwdupq_x_u8): Likewise.
6133 (viwdupq_x_u16): Likewise.
6134 (viwdupq_x_u32): Likewise.
6135 (vidupq_x_u8): Likewise.
6136 (vddupq_x_u8): Likewise.
6137 (vidupq_x_u16): Likewise.
6138 (vddupq_x_u16): Likewise.
6139 (vidupq_x_u32): Likewise.
6140 (vddupq_x_u32): Likewise.
6141 (vshrq_x): Likewise.
6143 2020-03-20 Richard Biener <rguenther@suse.de>
6145 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts
6146 to vectorize for CTOR defs.
6148 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6149 Andre Vieira <andre.simoesdiasvieira@arm.com>
6150 Mihail Ionescu <mihail.ionescu@arm.com>
6152 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin
6154 (LDRGBWBU_QUALIFIERS): Likewise.
6155 (LDRGBWBS_Z_QUALIFIERS): Likewise.
6156 (LDRGBWBU_Z_QUALIFIERS): Likewise.
6157 (STRSBWBS_QUALIFIERS): Likewise.
6158 (STRSBWBU_QUALIFIERS): Likewise.
6159 (STRSBWBS_P_QUALIFIERS): Likewise.
6160 (STRSBWBU_P_QUALIFIERS): Likewise.
6161 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro.
6162 (vldrdq_gather_base_wb_u64): Likewise.
6163 (vldrdq_gather_base_wb_z_s64): Likewise.
6164 (vldrdq_gather_base_wb_z_u64): Likewise.
6165 (vldrwq_gather_base_wb_f32): Likewise.
6166 (vldrwq_gather_base_wb_s32): Likewise.
6167 (vldrwq_gather_base_wb_u32): Likewise.
6168 (vldrwq_gather_base_wb_z_f32): Likewise.
6169 (vldrwq_gather_base_wb_z_s32): Likewise.
6170 (vldrwq_gather_base_wb_z_u32): Likewise.
6171 (vstrdq_scatter_base_wb_p_s64): Likewise.
6172 (vstrdq_scatter_base_wb_p_u64): Likewise.
6173 (vstrdq_scatter_base_wb_s64): Likewise.
6174 (vstrdq_scatter_base_wb_u64): Likewise.
6175 (vstrwq_scatter_base_wb_p_s32): Likewise.
6176 (vstrwq_scatter_base_wb_p_f32): Likewise.
6177 (vstrwq_scatter_base_wb_p_u32): Likewise.
6178 (vstrwq_scatter_base_wb_s32): Likewise.
6179 (vstrwq_scatter_base_wb_u32): Likewise.
6180 (vstrwq_scatter_base_wb_f32): Likewise.
6181 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic.
6182 (__arm_vldrdq_gather_base_wb_u64): Likewise.
6183 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
6184 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
6185 (__arm_vldrwq_gather_base_wb_s32): Likewise.
6186 (__arm_vldrwq_gather_base_wb_u32): Likewise.
6187 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
6188 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
6189 (__arm_vstrdq_scatter_base_wb_s64): Likewise.
6190 (__arm_vstrdq_scatter_base_wb_u64): Likewise.
6191 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
6192 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
6193 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
6194 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
6195 (__arm_vstrwq_scatter_base_wb_s32): Likewise.
6196 (__arm_vstrwq_scatter_base_wb_u32): Likewise.
6197 (__arm_vldrwq_gather_base_wb_f32): Likewise.
6198 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
6199 (__arm_vstrwq_scatter_base_wb_f32): Likewise.
6200 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
6201 (vstrwq_scatter_base_wb): Define polymorphic variant.
6202 (vstrwq_scatter_base_wb_p): Likewise.
6203 (vstrdq_scatter_base_wb_p): Likewise.
6204 (vstrdq_scatter_base_wb): Likewise.
6205 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin
6207 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL
6209 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise.
6210 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise.
6211 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
6212 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise.
6213 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise.
6214 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
6215 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
6216 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise.
6217 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
6218 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
6219 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise.
6220 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
6221 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise.
6222 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise.
6223 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
6224 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise.
6225 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise.
6226 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise.
6227 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
6228 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise.
6229 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
6230 (mve_vldrwq_gather_base_wb_fv4sf): Likewise.
6231 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
6232 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise.
6233 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
6234 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise.
6235 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
6236 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise.
6237 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
6239 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6240 Andre Vieira <andre.simoesdiasvieira@arm.com>
6241 Mihail Ionescu <mihail.ionescu@arm.com>
6243 * config/arm/arm-builtins.c
6244 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary
6246 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro.
6247 (vddupq_m_n_u32): Likewise.
6248 (vddupq_m_n_u16): Likewise.
6249 (vddupq_m_wb_u8): Likewise.
6250 (vddupq_m_wb_u16): Likewise.
6251 (vddupq_m_wb_u32): Likewise.
6252 (vddupq_n_u8): Likewise.
6253 (vddupq_n_u32): Likewise.
6254 (vddupq_n_u16): Likewise.
6255 (vddupq_wb_u8): Likewise.
6256 (vddupq_wb_u16): Likewise.
6257 (vddupq_wb_u32): Likewise.
6258 (vdwdupq_m_n_u8): Likewise.
6259 (vdwdupq_m_n_u32): Likewise.
6260 (vdwdupq_m_n_u16): Likewise.
6261 (vdwdupq_m_wb_u8): Likewise.
6262 (vdwdupq_m_wb_u32): Likewise.
6263 (vdwdupq_m_wb_u16): Likewise.
6264 (vdwdupq_n_u8): Likewise.
6265 (vdwdupq_n_u32): Likewise.
6266 (vdwdupq_n_u16): Likewise.
6267 (vdwdupq_wb_u8): Likewise.
6268 (vdwdupq_wb_u32): Likewise.
6269 (vdwdupq_wb_u16): Likewise.
6270 (vidupq_m_n_u8): Likewise.
6271 (vidupq_m_n_u32): Likewise.
6272 (vidupq_m_n_u16): Likewise.
6273 (vidupq_m_wb_u8): Likewise.
6274 (vidupq_m_wb_u16): Likewise.
6275 (vidupq_m_wb_u32): Likewise.
6276 (vidupq_n_u8): Likewise.
6277 (vidupq_n_u32): Likewise.
6278 (vidupq_n_u16): Likewise.
6279 (vidupq_wb_u8): Likewise.
6280 (vidupq_wb_u16): Likewise.
6281 (vidupq_wb_u32): Likewise.
6282 (viwdupq_m_n_u8): Likewise.
6283 (viwdupq_m_n_u32): Likewise.
6284 (viwdupq_m_n_u16): Likewise.
6285 (viwdupq_m_wb_u8): Likewise.
6286 (viwdupq_m_wb_u32): Likewise.
6287 (viwdupq_m_wb_u16): Likewise.
6288 (viwdupq_n_u8): Likewise.
6289 (viwdupq_n_u32): Likewise.
6290 (viwdupq_n_u16): Likewise.
6291 (viwdupq_wb_u8): Likewise.
6292 (viwdupq_wb_u32): Likewise.
6293 (viwdupq_wb_u16): Likewise.
6294 (__arm_vddupq_m_n_u8): Define intrinsic.
6295 (__arm_vddupq_m_n_u32): Likewise.
6296 (__arm_vddupq_m_n_u16): Likewise.
6297 (__arm_vddupq_m_wb_u8): Likewise.
6298 (__arm_vddupq_m_wb_u16): Likewise.
6299 (__arm_vddupq_m_wb_u32): Likewise.
6300 (__arm_vddupq_n_u8): Likewise.
6301 (__arm_vddupq_n_u32): Likewise.
6302 (__arm_vddupq_n_u16): Likewise.
6303 (__arm_vdwdupq_m_n_u8): Likewise.
6304 (__arm_vdwdupq_m_n_u32): Likewise.
6305 (__arm_vdwdupq_m_n_u16): Likewise.
6306 (__arm_vdwdupq_m_wb_u8): Likewise.
6307 (__arm_vdwdupq_m_wb_u32): Likewise.
6308 (__arm_vdwdupq_m_wb_u16): Likewise.
6309 (__arm_vdwdupq_n_u8): Likewise.
6310 (__arm_vdwdupq_n_u32): Likewise.
6311 (__arm_vdwdupq_n_u16): Likewise.
6312 (__arm_vdwdupq_wb_u8): Likewise.
6313 (__arm_vdwdupq_wb_u32): Likewise.
6314 (__arm_vdwdupq_wb_u16): Likewise.
6315 (__arm_vidupq_m_n_u8): Likewise.
6316 (__arm_vidupq_m_n_u32): Likewise.
6317 (__arm_vidupq_m_n_u16): Likewise.
6318 (__arm_vidupq_n_u8): Likewise.
6319 (__arm_vidupq_m_wb_u8): Likewise.
6320 (__arm_vidupq_m_wb_u16): Likewise.
6321 (__arm_vidupq_m_wb_u32): Likewise.
6322 (__arm_vidupq_n_u32): Likewise.
6323 (__arm_vidupq_n_u16): Likewise.
6324 (__arm_vidupq_wb_u8): Likewise.
6325 (__arm_vidupq_wb_u16): Likewise.
6326 (__arm_vidupq_wb_u32): Likewise.
6327 (__arm_vddupq_wb_u8): Likewise.
6328 (__arm_vddupq_wb_u16): Likewise.
6329 (__arm_vddupq_wb_u32): Likewise.
6330 (__arm_viwdupq_m_n_u8): Likewise.
6331 (__arm_viwdupq_m_n_u32): Likewise.
6332 (__arm_viwdupq_m_n_u16): Likewise.
6333 (__arm_viwdupq_m_wb_u8): Likewise.
6334 (__arm_viwdupq_m_wb_u32): Likewise.
6335 (__arm_viwdupq_m_wb_u16): Likewise.
6336 (__arm_viwdupq_n_u8): Likewise.
6337 (__arm_viwdupq_n_u32): Likewise.
6338 (__arm_viwdupq_n_u16): Likewise.
6339 (__arm_viwdupq_wb_u8): Likewise.
6340 (__arm_viwdupq_wb_u32): Likewise.
6341 (__arm_viwdupq_wb_u16): Likewise.
6342 (vidupq_m): Define polymorphic variant.
6343 (vddupq_m): Likewise.
6344 (vidupq_u16): Likewise.
6345 (vidupq_u32): Likewise.
6346 (vidupq_u8): Likewise.
6347 (vddupq_u16): Likewise.
6348 (vddupq_u32): Likewise.
6349 (vddupq_u8): Likewise.
6350 (viwdupq_m): Likewise.
6351 (viwdupq_u16): Likewise.
6352 (viwdupq_u32): Likewise.
6353 (viwdupq_u8): Likewise.
6354 (vdwdupq_m): Likewise.
6355 (vdwdupq_u16): Likewise.
6356 (vdwdupq_u32): Likewise.
6357 (vdwdupq_u8): Likewise.
6358 * config/arm/arm_mve_builtins.def
6359 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin
6361 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern.
6362 (mve_vidupq_u<mode>_insn): Likewise.
6363 (mve_vidupq_m_n_u<mode>): Likewise.
6364 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
6365 (mve_vddupq_n_u<mode>): Likewise.
6366 (mve_vddupq_u<mode>_insn): Likewise.
6367 (mve_vddupq_m_n_u<mode>): Likewise.
6368 (mve_vddupq_m_wb_u<mode>_insn): Likewise.
6369 (mve_vdwdupq_n_u<mode>): Likewise.
6370 (mve_vdwdupq_wb_u<mode>): Likewise.
6371 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
6372 (mve_vdwdupq_m_n_u<mode>): Likewise.
6373 (mve_vdwdupq_m_wb_u<mode>): Likewise.
6374 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
6375 (mve_viwdupq_n_u<mode>): Likewise.
6376 (mve_viwdupq_wb_u<mode>): Likewise.
6377 (mve_viwdupq_wb_u<mode>_insn): Likewise.
6378 (mve_viwdupq_m_n_u<mode>): Likewise.
6379 (mve_viwdupq_m_wb_u<mode>): Likewise.
6380 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
6382 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6384 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro.
6385 (vreinterpretq_s16_s64): Likewise.
6386 (vreinterpretq_s16_s8): Likewise.
6387 (vreinterpretq_s16_u16): Likewise.
6388 (vreinterpretq_s16_u32): Likewise.
6389 (vreinterpretq_s16_u64): Likewise.
6390 (vreinterpretq_s16_u8): Likewise.
6391 (vreinterpretq_s32_s16): Likewise.
6392 (vreinterpretq_s32_s64): Likewise.
6393 (vreinterpretq_s32_s8): Likewise.
6394 (vreinterpretq_s32_u16): Likewise.
6395 (vreinterpretq_s32_u32): Likewise.
6396 (vreinterpretq_s32_u64): Likewise.
6397 (vreinterpretq_s32_u8): Likewise.
6398 (vreinterpretq_s64_s16): Likewise.
6399 (vreinterpretq_s64_s32): Likewise.
6400 (vreinterpretq_s64_s8): Likewise.
6401 (vreinterpretq_s64_u16): Likewise.
6402 (vreinterpretq_s64_u32): Likewise.
6403 (vreinterpretq_s64_u64): Likewise.
6404 (vreinterpretq_s64_u8): Likewise.
6405 (vreinterpretq_s8_s16): Likewise.
6406 (vreinterpretq_s8_s32): Likewise.
6407 (vreinterpretq_s8_s64): Likewise.
6408 (vreinterpretq_s8_u16): Likewise.
6409 (vreinterpretq_s8_u32): Likewise.
6410 (vreinterpretq_s8_u64): Likewise.
6411 (vreinterpretq_s8_u8): Likewise.
6412 (vreinterpretq_u16_s16): Likewise.
6413 (vreinterpretq_u16_s32): Likewise.
6414 (vreinterpretq_u16_s64): Likewise.
6415 (vreinterpretq_u16_s8): Likewise.
6416 (vreinterpretq_u16_u32): Likewise.
6417 (vreinterpretq_u16_u64): Likewise.
6418 (vreinterpretq_u16_u8): Likewise.
6419 (vreinterpretq_u32_s16): Likewise.
6420 (vreinterpretq_u32_s32): Likewise.
6421 (vreinterpretq_u32_s64): Likewise.
6422 (vreinterpretq_u32_s8): Likewise.
6423 (vreinterpretq_u32_u16): Likewise.
6424 (vreinterpretq_u32_u64): Likewise.
6425 (vreinterpretq_u32_u8): Likewise.
6426 (vreinterpretq_u64_s16): Likewise.
6427 (vreinterpretq_u64_s32): Likewise.
6428 (vreinterpretq_u64_s64): Likewise.
6429 (vreinterpretq_u64_s8): Likewise.
6430 (vreinterpretq_u64_u16): Likewise.
6431 (vreinterpretq_u64_u32): Likewise.
6432 (vreinterpretq_u64_u8): Likewise.
6433 (vreinterpretq_u8_s16): Likewise.
6434 (vreinterpretq_u8_s32): Likewise.
6435 (vreinterpretq_u8_s64): Likewise.
6436 (vreinterpretq_u8_s8): Likewise.
6437 (vreinterpretq_u8_u16): Likewise.
6438 (vreinterpretq_u8_u32): Likewise.
6439 (vreinterpretq_u8_u64): Likewise.
6440 (vreinterpretq_s32_f16): Likewise.
6441 (vreinterpretq_s32_f32): Likewise.
6442 (vreinterpretq_u16_f16): Likewise.
6443 (vreinterpretq_u16_f32): Likewise.
6444 (vreinterpretq_u32_f16): Likewise.
6445 (vreinterpretq_u32_f32): Likewise.
6446 (vreinterpretq_u64_f16): Likewise.
6447 (vreinterpretq_u64_f32): Likewise.
6448 (vreinterpretq_u8_f16): Likewise.
6449 (vreinterpretq_u8_f32): Likewise.
6450 (vreinterpretq_f16_f32): Likewise.
6451 (vreinterpretq_f16_s16): Likewise.
6452 (vreinterpretq_f16_s32): Likewise.
6453 (vreinterpretq_f16_s64): Likewise.
6454 (vreinterpretq_f16_s8): Likewise.
6455 (vreinterpretq_f16_u16): Likewise.
6456 (vreinterpretq_f16_u32): Likewise.
6457 (vreinterpretq_f16_u64): Likewise.
6458 (vreinterpretq_f16_u8): Likewise.
6459 (vreinterpretq_f32_f16): Likewise.
6460 (vreinterpretq_f32_s16): Likewise.
6461 (vreinterpretq_f32_s32): Likewise.
6462 (vreinterpretq_f32_s64): Likewise.
6463 (vreinterpretq_f32_s8): Likewise.
6464 (vreinterpretq_f32_u16): Likewise.
6465 (vreinterpretq_f32_u32): Likewise.
6466 (vreinterpretq_f32_u64): Likewise.
6467 (vreinterpretq_f32_u8): Likewise.
6468 (vreinterpretq_s16_f16): Likewise.
6469 (vreinterpretq_s16_f32): Likewise.
6470 (vreinterpretq_s64_f16): Likewise.
6471 (vreinterpretq_s64_f32): Likewise.
6472 (vreinterpretq_s8_f16): Likewise.
6473 (vreinterpretq_s8_f32): Likewise.
6474 (vuninitializedq_u8): Likewise.
6475 (vuninitializedq_u16): Likewise.
6476 (vuninitializedq_u32): Likewise.
6477 (vuninitializedq_u64): Likewise.
6478 (vuninitializedq_s8): Likewise.
6479 (vuninitializedq_s16): Likewise.
6480 (vuninitializedq_s32): Likewise.
6481 (vuninitializedq_s64): Likewise.
6482 (vuninitializedq_f16): Likewise.
6483 (vuninitializedq_f32): Likewise.
6484 (__arm_vuninitializedq_u8): Define intrinsic.
6485 (__arm_vuninitializedq_u16): Likewise.
6486 (__arm_vuninitializedq_u32): Likewise.
6487 (__arm_vuninitializedq_u64): Likewise.
6488 (__arm_vuninitializedq_s8): Likewise.
6489 (__arm_vuninitializedq_s16): Likewise.
6490 (__arm_vuninitializedq_s32): Likewise.
6491 (__arm_vuninitializedq_s64): Likewise.
6492 (__arm_vreinterpretq_s16_s32): Likewise.
6493 (__arm_vreinterpretq_s16_s64): Likewise.
6494 (__arm_vreinterpretq_s16_s8): Likewise.
6495 (__arm_vreinterpretq_s16_u16): Likewise.
6496 (__arm_vreinterpretq_s16_u32): Likewise.
6497 (__arm_vreinterpretq_s16_u64): Likewise.
6498 (__arm_vreinterpretq_s16_u8): Likewise.
6499 (__arm_vreinterpretq_s32_s16): Likewise.
6500 (__arm_vreinterpretq_s32_s64): Likewise.
6501 (__arm_vreinterpretq_s32_s8): Likewise.
6502 (__arm_vreinterpretq_s32_u16): Likewise.
6503 (__arm_vreinterpretq_s32_u32): Likewise.
6504 (__arm_vreinterpretq_s32_u64): Likewise.
6505 (__arm_vreinterpretq_s32_u8): Likewise.
6506 (__arm_vreinterpretq_s64_s16): Likewise.
6507 (__arm_vreinterpretq_s64_s32): Likewise.
6508 (__arm_vreinterpretq_s64_s8): Likewise.
6509 (__arm_vreinterpretq_s64_u16): Likewise.
6510 (__arm_vreinterpretq_s64_u32): Likewise.
6511 (__arm_vreinterpretq_s64_u64): Likewise.
6512 (__arm_vreinterpretq_s64_u8): Likewise.
6513 (__arm_vreinterpretq_s8_s16): Likewise.
6514 (__arm_vreinterpretq_s8_s32): Likewise.
6515 (__arm_vreinterpretq_s8_s64): Likewise.
6516 (__arm_vreinterpretq_s8_u16): Likewise.
6517 (__arm_vreinterpretq_s8_u32): Likewise.
6518 (__arm_vreinterpretq_s8_u64): Likewise.
6519 (__arm_vreinterpretq_s8_u8): Likewise.
6520 (__arm_vreinterpretq_u16_s16): Likewise.
6521 (__arm_vreinterpretq_u16_s32): Likewise.
6522 (__arm_vreinterpretq_u16_s64): Likewise.
6523 (__arm_vreinterpretq_u16_s8): Likewise.
6524 (__arm_vreinterpretq_u16_u32): Likewise.
6525 (__arm_vreinterpretq_u16_u64): Likewise.
6526 (__arm_vreinterpretq_u16_u8): Likewise.
6527 (__arm_vreinterpretq_u32_s16): Likewise.
6528 (__arm_vreinterpretq_u32_s32): Likewise.
6529 (__arm_vreinterpretq_u32_s64): Likewise.
6530 (__arm_vreinterpretq_u32_s8): Likewise.
6531 (__arm_vreinterpretq_u32_u16): Likewise.
6532 (__arm_vreinterpretq_u32_u64): Likewise.
6533 (__arm_vreinterpretq_u32_u8): Likewise.
6534 (__arm_vreinterpretq_u64_s16): Likewise.
6535 (__arm_vreinterpretq_u64_s32): Likewise.
6536 (__arm_vreinterpretq_u64_s64): Likewise.
6537 (__arm_vreinterpretq_u64_s8): Likewise.
6538 (__arm_vreinterpretq_u64_u16): Likewise.
6539 (__arm_vreinterpretq_u64_u32): Likewise.
6540 (__arm_vreinterpretq_u64_u8): Likewise.
6541 (__arm_vreinterpretq_u8_s16): Likewise.
6542 (__arm_vreinterpretq_u8_s32): Likewise.
6543 (__arm_vreinterpretq_u8_s64): Likewise.
6544 (__arm_vreinterpretq_u8_s8): Likewise.
6545 (__arm_vreinterpretq_u8_u16): Likewise.
6546 (__arm_vreinterpretq_u8_u32): Likewise.
6547 (__arm_vreinterpretq_u8_u64): Likewise.
6548 (__arm_vuninitializedq_f16): Likewise.
6549 (__arm_vuninitializedq_f32): Likewise.
6550 (__arm_vreinterpretq_s32_f16): Likewise.
6551 (__arm_vreinterpretq_s32_f32): Likewise.
6552 (__arm_vreinterpretq_s16_f16): Likewise.
6553 (__arm_vreinterpretq_s16_f32): Likewise.
6554 (__arm_vreinterpretq_s64_f16): Likewise.
6555 (__arm_vreinterpretq_s64_f32): Likewise.
6556 (__arm_vreinterpretq_s8_f16): Likewise.
6557 (__arm_vreinterpretq_s8_f32): Likewise.
6558 (__arm_vreinterpretq_u16_f16): Likewise.
6559 (__arm_vreinterpretq_u16_f32): Likewise.
6560 (__arm_vreinterpretq_u32_f16): Likewise.
6561 (__arm_vreinterpretq_u32_f32): Likewise.
6562 (__arm_vreinterpretq_u64_f16): Likewise.
6563 (__arm_vreinterpretq_u64_f32): Likewise.
6564 (__arm_vreinterpretq_u8_f16): Likewise.
6565 (__arm_vreinterpretq_u8_f32): Likewise.
6566 (__arm_vreinterpretq_f16_f32): Likewise.
6567 (__arm_vreinterpretq_f16_s16): Likewise.
6568 (__arm_vreinterpretq_f16_s32): Likewise.
6569 (__arm_vreinterpretq_f16_s64): Likewise.
6570 (__arm_vreinterpretq_f16_s8): Likewise.
6571 (__arm_vreinterpretq_f16_u16): Likewise.
6572 (__arm_vreinterpretq_f16_u32): Likewise.
6573 (__arm_vreinterpretq_f16_u64): Likewise.
6574 (__arm_vreinterpretq_f16_u8): Likewise.
6575 (__arm_vreinterpretq_f32_f16): Likewise.
6576 (__arm_vreinterpretq_f32_s16): Likewise.
6577 (__arm_vreinterpretq_f32_s32): Likewise.
6578 (__arm_vreinterpretq_f32_s64): Likewise.
6579 (__arm_vreinterpretq_f32_s8): Likewise.
6580 (__arm_vreinterpretq_f32_u16): Likewise.
6581 (__arm_vreinterpretq_f32_u32): Likewise.
6582 (__arm_vreinterpretq_f32_u64): Likewise.
6583 (__arm_vreinterpretq_f32_u8): Likewise.
6584 (vuninitializedq): Define polymorphic variant.
6585 (vreinterpretq_f16): Likewise.
6586 (vreinterpretq_f32): Likewise.
6587 (vreinterpretq_s16): Likewise.
6588 (vreinterpretq_s32): Likewise.
6589 (vreinterpretq_s64): Likewise.
6590 (vreinterpretq_s8): Likewise.
6591 (vreinterpretq_u16): Likewise.
6592 (vreinterpretq_u32): Likewise.
6593 (vreinterpretq_u64): Likewise.
6594 (vreinterpretq_u8): Likewise.
6596 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6597 Andre Vieira <andre.simoesdiasvieira@arm.com>
6598 Mihail Ionescu <mihail.ionescu@arm.com>
6600 * config/arm/arm_mve.h (vaddq_s8): Define macro.
6601 (vaddq_s16): Likewise.
6602 (vaddq_s32): Likewise.
6603 (vaddq_u8): Likewise.
6604 (vaddq_u16): Likewise.
6605 (vaddq_u32): Likewise.
6606 (vaddq_f16): Likewise.
6607 (vaddq_f32): Likewise.
6608 (__arm_vaddq_s8): Define intrinsic.
6609 (__arm_vaddq_s16): Likewise.
6610 (__arm_vaddq_s32): Likewise.
6611 (__arm_vaddq_u8): Likewise.
6612 (__arm_vaddq_u16): Likewise.
6613 (__arm_vaddq_u32): Likewise.
6614 (__arm_vaddq_f16): Likewise.
6615 (__arm_vaddq_f32): Likewise.
6616 (vaddq): Define polymorphic variant.
6617 * config/arm/iterators.md (VNIM): Define mode iterator for common types
6618 Neon, IWMMXT and MVE.
6619 (VNINOTM): Likewise.
6620 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern.
6621 (mve_vaddq_f<mode>): Define RTL pattern.
6622 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern.
6623 (addv8hf3_neon): Define RTL pattern.
6624 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern
6626 (addv8hf3): Define standard RTL pattern for MVE and Neon.
6627 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT.
6629 2020-03-20 Martin Liska <mliska@suse.cz>
6632 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously
6633 build_ref_for_offset function was used and it transforms off to bytes
6636 2020-03-20 Richard Biener <rguenther@suse.de>
6638 PR tree-optimization/94266
6639 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the
6640 type of the underlying object to adjust for the containing
6643 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6645 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
6646 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
6647 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
6649 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6651 * config/arm/mve.md (mve_mov<mode>): Fix R->R case.
6653 2020-03-20 Jakub Jelinek <jakub@redhat.com>
6655 PR tree-optimization/94224
6656 * gimple-ssa-store-merging.c
6657 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping
6658 or adjacent INTEGER_CST rhs_code stores as mergeable if they have
6661 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6663 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve.
6665 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
6668 * cgraph.c (cgraph_node::function_symbol): Fix availability computation.
6669 (cgraph_node::function_or_virtual_thunk_symbol): Likewise.
6671 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
6674 * cgraphunit.c (process_function_and_variable_attributes): warn
6675 for flatten attribute on alias.
6676 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias.
6678 2020-03-19 Martin Liska <mliska@suse.cz>
6680 * lto-section-in.c: Add ext_symtab.
6681 * lto-streamer-out.c (write_symbol_extension_info): New.
6682 (produce_symtab_extension): New.
6683 (produce_asm_for_decls): Stream also produce_symtab_extension.
6684 * lto-streamer.h (enum lto_section_type): New section.
6686 2020-03-19 Jakub Jelinek <jakub@redhat.com>
6688 PR tree-optimization/94211
6689 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
6690 instead of estimate_num_insns for bb_seq (middle_bb). Rename
6691 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
6694 2020-03-19 Richard Biener <rguenther@suse.de>
6697 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr
6698 and build_ref_for_offset.
6700 2020-03-19 Richard Biener <rguenther@suse.de>
6703 * fold-const.c (fold_binary_loc): Avoid using
6704 build_fold_addr_expr when we really want an ADDR_EXPR.
6706 2020-03-18 Segher Boessenkool <segher@kernel.crashing.org>
6708 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented
6711 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
6713 PR rtl-optimization/90275
6714 * cse.c (cse_insn): Delete no-op register moves too.
6716 2020-03-18 Martin Sebor <msebor@redhat.com>
6719 * cgraphunit.c (process_function_and_variable_attributes): Also
6720 complain about weakref function definitions and drop all effects
6723 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6724 Mihail Ionescu <mihail.ionescu@arm.com>
6725 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6727 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
6728 (vstrdq_scatter_base_p_u64): Likewise.
6729 (vstrdq_scatter_base_s64): Likewise.
6730 (vstrdq_scatter_base_u64): Likewise.
6731 (vstrdq_scatter_offset_p_s64): Likewise.
6732 (vstrdq_scatter_offset_p_u64): Likewise.
6733 (vstrdq_scatter_offset_s64): Likewise.
6734 (vstrdq_scatter_offset_u64): Likewise.
6735 (vstrdq_scatter_shifted_offset_p_s64): Likewise.
6736 (vstrdq_scatter_shifted_offset_p_u64): Likewise.
6737 (vstrdq_scatter_shifted_offset_s64): Likewise.
6738 (vstrdq_scatter_shifted_offset_u64): Likewise.
6739 (vstrhq_scatter_offset_f16): Likewise.
6740 (vstrhq_scatter_offset_p_f16): Likewise.
6741 (vstrhq_scatter_shifted_offset_f16): Likewise.
6742 (vstrhq_scatter_shifted_offset_p_f16): Likewise.
6743 (vstrwq_scatter_base_f32): Likewise.
6744 (vstrwq_scatter_base_p_f32): Likewise.
6745 (vstrwq_scatter_offset_f32): Likewise.
6746 (vstrwq_scatter_offset_p_f32): Likewise.
6747 (vstrwq_scatter_offset_p_s32): Likewise.
6748 (vstrwq_scatter_offset_p_u32): Likewise.
6749 (vstrwq_scatter_offset_s32): Likewise.
6750 (vstrwq_scatter_offset_u32): Likewise.
6751 (vstrwq_scatter_shifted_offset_f32): Likewise.
6752 (vstrwq_scatter_shifted_offset_p_f32): Likewise.
6753 (vstrwq_scatter_shifted_offset_p_s32): Likewise.
6754 (vstrwq_scatter_shifted_offset_p_u32): Likewise.
6755 (vstrwq_scatter_shifted_offset_s32): Likewise.
6756 (vstrwq_scatter_shifted_offset_u32): Likewise.
6757 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
6758 (__arm_vstrdq_scatter_base_p_u64): Likewise.
6759 (__arm_vstrdq_scatter_base_s64): Likewise.
6760 (__arm_vstrdq_scatter_base_u64): Likewise.
6761 (__arm_vstrdq_scatter_offset_p_s64): Likewise.
6762 (__arm_vstrdq_scatter_offset_p_u64): Likewise.
6763 (__arm_vstrdq_scatter_offset_s64): Likewise.
6764 (__arm_vstrdq_scatter_offset_u64): Likewise.
6765 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
6766 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
6767 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
6768 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
6769 (__arm_vstrwq_scatter_offset_p_s32): Likewise.
6770 (__arm_vstrwq_scatter_offset_p_u32): Likewise.
6771 (__arm_vstrwq_scatter_offset_s32): Likewise.
6772 (__arm_vstrwq_scatter_offset_u32): Likewise.
6773 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
6774 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
6775 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
6776 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
6777 (__arm_vstrhq_scatter_offset_f16): Likewise.
6778 (__arm_vstrhq_scatter_offset_p_f16): Likewise.
6779 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
6780 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
6781 (__arm_vstrwq_scatter_base_f32): Likewise.
6782 (__arm_vstrwq_scatter_base_p_f32): Likewise.
6783 (__arm_vstrwq_scatter_offset_f32): Likewise.
6784 (__arm_vstrwq_scatter_offset_p_f32): Likewise.
6785 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
6786 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
6787 (vstrhq_scatter_offset): Define polymorphic variant.
6788 (vstrhq_scatter_offset_p): Likewise.
6789 (vstrhq_scatter_shifted_offset): Likewise.
6790 (vstrhq_scatter_shifted_offset_p): Likewise.
6791 (vstrwq_scatter_base): Likewise.
6792 (vstrwq_scatter_base_p): Likewise.
6793 (vstrwq_scatter_offset): Likewise.
6794 (vstrwq_scatter_offset_p): Likewise.
6795 (vstrwq_scatter_shifted_offset): Likewise.
6796 (vstrwq_scatter_shifted_offset_p): Likewise.
6797 (vstrdq_scatter_base_p): Likewise.
6798 (vstrdq_scatter_base): Likewise.
6799 (vstrdq_scatter_offset_p): Likewise.
6800 (vstrdq_scatter_offset): Likewise.
6801 (vstrdq_scatter_shifted_offset_p): Likewise.
6802 (vstrdq_scatter_shifted_offset): Likewise.
6803 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
6804 (STRSBS_P): Likewise.
6806 (STRSBU_P): Likewise.
6808 (STRSS_P): Likewise.
6810 (STRSU_P): Likewise.
6811 * config/arm/constraints.md (Ri): Define.
6812 * config/arm/mve.md (VSTRDSBQ): Define iterator.
6813 (VSTRDSOQ): Likewise.
6814 (VSTRDSSOQ): Likewise.
6815 (VSTRWSOQ): Likewise.
6816 (VSTRWSSOQ): Likewise.
6817 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
6818 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
6819 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
6820 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
6821 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
6822 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
6823 (mve_vstrhq_scatter_offset_fv8hf): Likewise.
6824 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
6825 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
6826 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
6827 (mve_vstrwq_scatter_base_fv4sf): Likewise.
6828 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
6829 (mve_vstrwq_scatter_offset_fv4sf): Likewise.
6830 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
6831 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
6832 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
6833 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
6834 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
6835 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
6836 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
6837 * config/arm/predicates.md (Ri): Define predicate to check immediate
6838 is the range +/-1016 and multiple of 8.
6840 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6841 Mihail Ionescu <mihail.ionescu@arm.com>
6842 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6844 * config/arm/arm_mve.h (vst1q_f32): Define macro.
6845 (vst1q_f16): Likewise.
6846 (vst1q_s8): Likewise.
6847 (vst1q_s32): Likewise.
6848 (vst1q_s16): Likewise.
6849 (vst1q_u8): Likewise.
6850 (vst1q_u32): Likewise.
6851 (vst1q_u16): Likewise.
6852 (vstrhq_f16): Likewise.
6853 (vstrhq_scatter_offset_s32): Likewise.
6854 (vstrhq_scatter_offset_s16): Likewise.
6855 (vstrhq_scatter_offset_u32): Likewise.
6856 (vstrhq_scatter_offset_u16): Likewise.
6857 (vstrhq_scatter_offset_p_s32): Likewise.
6858 (vstrhq_scatter_offset_p_s16): Likewise.
6859 (vstrhq_scatter_offset_p_u32): Likewise.
6860 (vstrhq_scatter_offset_p_u16): Likewise.
6861 (vstrhq_scatter_shifted_offset_s32): Likewise.
6862 (vstrhq_scatter_shifted_offset_s16): Likewise.
6863 (vstrhq_scatter_shifted_offset_u32): Likewise.
6864 (vstrhq_scatter_shifted_offset_u16): Likewise.
6865 (vstrhq_scatter_shifted_offset_p_s32): Likewise.
6866 (vstrhq_scatter_shifted_offset_p_s16): Likewise.
6867 (vstrhq_scatter_shifted_offset_p_u32): Likewise.
6868 (vstrhq_scatter_shifted_offset_p_u16): Likewise.
6869 (vstrhq_s32): Likewise.
6870 (vstrhq_s16): Likewise.
6871 (vstrhq_u32): Likewise.
6872 (vstrhq_u16): Likewise.
6873 (vstrhq_p_f16): Likewise.
6874 (vstrhq_p_s32): Likewise.
6875 (vstrhq_p_s16): Likewise.
6876 (vstrhq_p_u32): Likewise.
6877 (vstrhq_p_u16): Likewise.
6878 (vstrwq_f32): Likewise.
6879 (vstrwq_s32): Likewise.
6880 (vstrwq_u32): Likewise.
6881 (vstrwq_p_f32): Likewise.
6882 (vstrwq_p_s32): Likewise.
6883 (vstrwq_p_u32): Likewise.
6884 (__arm_vst1q_s8): Define intrinsic.
6885 (__arm_vst1q_s32): Likewise.
6886 (__arm_vst1q_s16): Likewise.
6887 (__arm_vst1q_u8): Likewise.
6888 (__arm_vst1q_u32): Likewise.
6889 (__arm_vst1q_u16): Likewise.
6890 (__arm_vstrhq_scatter_offset_s32): Likewise.
6891 (__arm_vstrhq_scatter_offset_s16): Likewise.
6892 (__arm_vstrhq_scatter_offset_u32): Likewise.
6893 (__arm_vstrhq_scatter_offset_u16): Likewise.
6894 (__arm_vstrhq_scatter_offset_p_s32): Likewise.
6895 (__arm_vstrhq_scatter_offset_p_s16): Likewise.
6896 (__arm_vstrhq_scatter_offset_p_u32): Likewise.
6897 (__arm_vstrhq_scatter_offset_p_u16): Likewise.
6898 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
6899 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
6900 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
6901 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
6902 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
6903 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
6904 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
6905 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
6906 (__arm_vstrhq_s32): Likewise.
6907 (__arm_vstrhq_s16): Likewise.
6908 (__arm_vstrhq_u32): Likewise.
6909 (__arm_vstrhq_u16): Likewise.
6910 (__arm_vstrhq_p_s32): Likewise.
6911 (__arm_vstrhq_p_s16): Likewise.
6912 (__arm_vstrhq_p_u32): Likewise.
6913 (__arm_vstrhq_p_u16): Likewise.
6914 (__arm_vstrwq_s32): Likewise.
6915 (__arm_vstrwq_u32): Likewise.
6916 (__arm_vstrwq_p_s32): Likewise.
6917 (__arm_vstrwq_p_u32): Likewise.
6918 (__arm_vstrwq_p_f32): Likewise.
6919 (__arm_vstrwq_f32): Likewise.
6920 (__arm_vst1q_f32): Likewise.
6921 (__arm_vst1q_f16): Likewise.
6922 (__arm_vstrhq_f16): Likewise.
6923 (__arm_vstrhq_p_f16): Likewise.
6924 (vst1q): Define polymorphic variant.
6926 (vstrhq_p): Likewise.
6927 (vstrhq_scatter_offset_p): Likewise.
6928 (vstrhq_scatter_offset): Likewise.
6929 (vstrhq_scatter_shifted_offset_p): Likewise.
6930 (vstrhq_scatter_shifted_offset): Likewise.
6931 (vstrwq_p): Likewise.
6933 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
6936 (STRSS_P): Likewise.
6938 (STRSU_P): Likewise.
6941 * config/arm/mve.md (VST1Q): Define iterator.
6942 (VSTRHSOQ): Likewise.
6943 (VSTRHSSOQ): Likewise.
6946 (mve_vstrhq_fv8hf): Define RTL pattern.
6947 (mve_vstrhq_p_fv8hf): Likewise.
6948 (mve_vstrhq_p_<supf><mode>): Likewise.
6949 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
6950 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
6951 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
6952 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
6953 (mve_vstrhq_<supf><mode>): Likewise.
6954 (mve_vstrwq_fv4sf): Likewise.
6955 (mve_vstrwq_p_fv4sf): Likewise.
6956 (mve_vstrwq_p_<supf>v4si): Likewise.
6957 (mve_vstrwq_<supf>v4si): Likewise.
6958 (mve_vst1q_f<mode>): Define expand.
6959 (mve_vst1q_<supf><mode>): Likewise.
6961 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6962 Mihail Ionescu <mihail.ionescu@arm.com>
6963 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6965 * config/arm/arm_mve.h (vld1q_s8): Define macro.
6966 (vld1q_s32): Likewise.
6967 (vld1q_s16): Likewise.
6968 (vld1q_u8): Likewise.
6969 (vld1q_u32): Likewise.
6970 (vld1q_u16): Likewise.
6971 (vldrhq_gather_offset_s32): Likewise.
6972 (vldrhq_gather_offset_s16): Likewise.
6973 (vldrhq_gather_offset_u32): Likewise.
6974 (vldrhq_gather_offset_u16): Likewise.
6975 (vldrhq_gather_offset_z_s32): Likewise.
6976 (vldrhq_gather_offset_z_s16): Likewise.
6977 (vldrhq_gather_offset_z_u32): Likewise.
6978 (vldrhq_gather_offset_z_u16): Likewise.
6979 (vldrhq_gather_shifted_offset_s32): Likewise.
6980 (vldrhq_gather_shifted_offset_s16): Likewise.
6981 (vldrhq_gather_shifted_offset_u32): Likewise.
6982 (vldrhq_gather_shifted_offset_u16): Likewise.
6983 (vldrhq_gather_shifted_offset_z_s32): Likewise.
6984 (vldrhq_gather_shifted_offset_z_s16): Likewise.
6985 (vldrhq_gather_shifted_offset_z_u32): Likewise.
6986 (vldrhq_gather_shifted_offset_z_u16): Likewise.
6987 (vldrhq_s32): Likewise.
6988 (vldrhq_s16): Likewise.
6989 (vldrhq_u32): Likewise.
6990 (vldrhq_u16): Likewise.
6991 (vldrhq_z_s32): Likewise.
6992 (vldrhq_z_s16): Likewise.
6993 (vldrhq_z_u32): Likewise.
6994 (vldrhq_z_u16): Likewise.
6995 (vldrwq_s32): Likewise.
6996 (vldrwq_u32): Likewise.
6997 (vldrwq_z_s32): Likewise.
6998 (vldrwq_z_u32): Likewise.
6999 (vld1q_f32): Likewise.
7000 (vld1q_f16): Likewise.
7001 (vldrhq_f16): Likewise.
7002 (vldrhq_z_f16): Likewise.
7003 (vldrwq_f32): Likewise.
7004 (vldrwq_z_f32): Likewise.
7005 (__arm_vld1q_s8): Define intrinsic.
7006 (__arm_vld1q_s32): Likewise.
7007 (__arm_vld1q_s16): Likewise.
7008 (__arm_vld1q_u8): Likewise.
7009 (__arm_vld1q_u32): Likewise.
7010 (__arm_vld1q_u16): Likewise.
7011 (__arm_vldrhq_gather_offset_s32): Likewise.
7012 (__arm_vldrhq_gather_offset_s16): Likewise.
7013 (__arm_vldrhq_gather_offset_u32): Likewise.
7014 (__arm_vldrhq_gather_offset_u16): Likewise.
7015 (__arm_vldrhq_gather_offset_z_s32): Likewise.
7016 (__arm_vldrhq_gather_offset_z_s16): Likewise.
7017 (__arm_vldrhq_gather_offset_z_u32): Likewise.
7018 (__arm_vldrhq_gather_offset_z_u16): Likewise.
7019 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
7020 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
7021 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
7022 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
7023 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
7024 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
7025 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
7026 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
7027 (__arm_vldrhq_s32): Likewise.
7028 (__arm_vldrhq_s16): Likewise.
7029 (__arm_vldrhq_u32): Likewise.
7030 (__arm_vldrhq_u16): Likewise.
7031 (__arm_vldrhq_z_s32): Likewise.
7032 (__arm_vldrhq_z_s16): Likewise.
7033 (__arm_vldrhq_z_u32): Likewise.
7034 (__arm_vldrhq_z_u16): Likewise.
7035 (__arm_vldrwq_s32): Likewise.
7036 (__arm_vldrwq_u32): Likewise.
7037 (__arm_vldrwq_z_s32): Likewise.
7038 (__arm_vldrwq_z_u32): Likewise.
7039 (__arm_vld1q_f32): Likewise.
7040 (__arm_vld1q_f16): Likewise.
7041 (__arm_vldrwq_f32): Likewise.
7042 (__arm_vldrwq_z_f32): Likewise.
7043 (__arm_vldrhq_z_f16): Likewise.
7044 (__arm_vldrhq_f16): Likewise.
7045 (vld1q): Define polymorphic variant.
7046 (vldrhq_gather_offset): Likewise.
7047 (vldrhq_gather_offset_z): Likewise.
7048 (vldrhq_gather_shifted_offset): Likewise.
7049 (vldrhq_gather_shifted_offset_z): Likewise.
7050 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
7054 (LDRGU_Z): Likewise.
7056 (LDRGS_Z): Likewise.
7058 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
7059 (V_sz_elem1): Likewise.
7060 (VLD1Q): Define iterator.
7061 (VLDRHGOQ): Likewise.
7062 (VLDRHGSOQ): Likewise.
7065 (mve_vldrhq_fv8hf): Define RTL pattern.
7066 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
7067 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
7068 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
7069 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
7070 (mve_vldrhq_<supf><mode>): Likewise.
7071 (mve_vldrhq_z_fv8hf): Likewise.
7072 (mve_vldrhq_z_<supf><mode>): Likewise.
7073 (mve_vldrwq_fv4sf): Likewise.
7074 (mve_vldrwq_<supf>v4si): Likewise.
7075 (mve_vldrwq_z_fv4sf): Likewise.
7076 (mve_vldrwq_z_<supf>v4si): Likewise.
7077 (mve_vld1q_f<mode>): Define RTL expand pattern.
7078 (mve_vld1q_<supf><mode>): Likewise.
7080 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7081 Mihail Ionescu <mihail.ionescu@arm.com>
7082 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7084 * config/arm/arm_mve.h (vld1q_s8): Define macro.
7085 (vld1q_s32): Likewise.
7086 (vld1q_s16): Likewise.
7087 (vld1q_u8): Likewise.
7088 (vld1q_u32): Likewise.
7089 (vld1q_u16): Likewise.
7090 (vldrhq_gather_offset_s32): Likewise.
7091 (vldrhq_gather_offset_s16): Likewise.
7092 (vldrhq_gather_offset_u32): Likewise.
7093 (vldrhq_gather_offset_u16): Likewise.
7094 (vldrhq_gather_offset_z_s32): Likewise.
7095 (vldrhq_gather_offset_z_s16): Likewise.
7096 (vldrhq_gather_offset_z_u32): Likewise.
7097 (vldrhq_gather_offset_z_u16): Likewise.
7098 (vldrhq_gather_shifted_offset_s32): Likewise.
7099 (vldrhq_gather_shifted_offset_s16): Likewise.
7100 (vldrhq_gather_shifted_offset_u32): Likewise.
7101 (vldrhq_gather_shifted_offset_u16): Likewise.
7102 (vldrhq_gather_shifted_offset_z_s32): Likewise.
7103 (vldrhq_gather_shifted_offset_z_s16): Likewise.
7104 (vldrhq_gather_shifted_offset_z_u32): Likewise.
7105 (vldrhq_gather_shifted_offset_z_u16): Likewise.
7106 (vldrhq_s32): Likewise.
7107 (vldrhq_s16): Likewise.
7108 (vldrhq_u32): Likewise.
7109 (vldrhq_u16): Likewise.
7110 (vldrhq_z_s32): Likewise.
7111 (vldrhq_z_s16): Likewise.
7112 (vldrhq_z_u32): Likewise.
7113 (vldrhq_z_u16): Likewise.
7114 (vldrwq_s32): Likewise.
7115 (vldrwq_u32): Likewise.
7116 (vldrwq_z_s32): Likewise.
7117 (vldrwq_z_u32): Likewise.
7118 (vld1q_f32): Likewise.
7119 (vld1q_f16): Likewise.
7120 (vldrhq_f16): Likewise.
7121 (vldrhq_z_f16): Likewise.
7122 (vldrwq_f32): Likewise.
7123 (vldrwq_z_f32): Likewise.
7124 (__arm_vld1q_s8): Define intrinsic.
7125 (__arm_vld1q_s32): Likewise.
7126 (__arm_vld1q_s16): Likewise.
7127 (__arm_vld1q_u8): Likewise.
7128 (__arm_vld1q_u32): Likewise.
7129 (__arm_vld1q_u16): Likewise.
7130 (__arm_vldrhq_gather_offset_s32): Likewise.
7131 (__arm_vldrhq_gather_offset_s16): Likewise.
7132 (__arm_vldrhq_gather_offset_u32): Likewise.
7133 (__arm_vldrhq_gather_offset_u16): Likewise.
7134 (__arm_vldrhq_gather_offset_z_s32): Likewise.
7135 (__arm_vldrhq_gather_offset_z_s16): Likewise.
7136 (__arm_vldrhq_gather_offset_z_u32): Likewise.
7137 (__arm_vldrhq_gather_offset_z_u16): Likewise.
7138 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
7139 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
7140 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
7141 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
7142 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
7143 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
7144 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
7145 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
7146 (__arm_vldrhq_s32): Likewise.
7147 (__arm_vldrhq_s16): Likewise.
7148 (__arm_vldrhq_u32): Likewise.
7149 (__arm_vldrhq_u16): Likewise.
7150 (__arm_vldrhq_z_s32): Likewise.
7151 (__arm_vldrhq_z_s16): Likewise.
7152 (__arm_vldrhq_z_u32): Likewise.
7153 (__arm_vldrhq_z_u16): Likewise.
7154 (__arm_vldrwq_s32): Likewise.
7155 (__arm_vldrwq_u32): Likewise.
7156 (__arm_vldrwq_z_s32): Likewise.
7157 (__arm_vldrwq_z_u32): Likewise.
7158 (__arm_vld1q_f32): Likewise.
7159 (__arm_vld1q_f16): Likewise.
7160 (__arm_vldrwq_f32): Likewise.
7161 (__arm_vldrwq_z_f32): Likewise.
7162 (__arm_vldrhq_z_f16): Likewise.
7163 (__arm_vldrhq_f16): Likewise.
7164 (vld1q): Define polymorphic variant.
7165 (vldrhq_gather_offset): Likewise.
7166 (vldrhq_gather_offset_z): Likewise.
7167 (vldrhq_gather_shifted_offset): Likewise.
7168 (vldrhq_gather_shifted_offset_z): Likewise.
7169 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
7173 (LDRGU_Z): Likewise.
7175 (LDRGS_Z): Likewise.
7177 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
7178 (V_sz_elem1): Likewise.
7179 (VLD1Q): Define iterator.
7180 (VLDRHGOQ): Likewise.
7181 (VLDRHGSOQ): Likewise.
7184 (mve_vldrhq_fv8hf): Define RTL pattern.
7185 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
7186 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
7187 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
7188 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
7189 (mve_vldrhq_<supf><mode>): Likewise.
7190 (mve_vldrhq_z_fv8hf): Likewise.
7191 (mve_vldrhq_z_<supf><mode>): Likewise.
7192 (mve_vldrwq_fv4sf): Likewise.
7193 (mve_vldrwq_<supf>v4si): Likewise.
7194 (mve_vldrwq_z_fv4sf): Likewise.
7195 (mve_vldrwq_z_<supf>v4si): Likewise.
7196 (mve_vld1q_f<mode>): Define RTL expand pattern.
7197 (mve_vld1q_<supf><mode>): Likewise.
7199 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7200 Mihail Ionescu <mihail.ionescu@arm.com>
7201 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7203 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
7205 (LDRGBU_Z_QUALIFIERS): Likewise.
7206 (LDRGS_Z_QUALIFIERS): Likewise.
7207 (LDRGU_Z_QUALIFIERS): Likewise.
7208 (LDRS_Z_QUALIFIERS): Likewise.
7209 (LDRU_Z_QUALIFIERS): Likewise.
7210 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro.
7211 (vldrbq_gather_offset_z_u8): Likewise.
7212 (vldrbq_gather_offset_z_s32): Likewise.
7213 (vldrbq_gather_offset_z_u16): Likewise.
7214 (vldrbq_gather_offset_z_u32): Likewise.
7215 (vldrbq_gather_offset_z_s8): Likewise.
7216 (vldrbq_z_s16): Likewise.
7217 (vldrbq_z_u8): Likewise.
7218 (vldrbq_z_s8): Likewise.
7219 (vldrbq_z_s32): Likewise.
7220 (vldrbq_z_u16): Likewise.
7221 (vldrbq_z_u32): Likewise.
7222 (vldrwq_gather_base_z_u32): Likewise.
7223 (vldrwq_gather_base_z_s32): Likewise.
7224 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic.
7225 (__arm_vldrbq_gather_offset_z_s32): Likewise.
7226 (__arm_vldrbq_gather_offset_z_s16): Likewise.
7227 (__arm_vldrbq_gather_offset_z_u8): Likewise.
7228 (__arm_vldrbq_gather_offset_z_u32): Likewise.
7229 (__arm_vldrbq_gather_offset_z_u16): Likewise.
7230 (__arm_vldrbq_z_s8): Likewise.
7231 (__arm_vldrbq_z_s32): Likewise.
7232 (__arm_vldrbq_z_s16): Likewise.
7233 (__arm_vldrbq_z_u8): Likewise.
7234 (__arm_vldrbq_z_u32): Likewise.
7235 (__arm_vldrbq_z_u16): Likewise.
7236 (__arm_vldrwq_gather_base_z_s32): Likewise.
7237 (__arm_vldrwq_gather_base_z_u32): Likewise.
7238 (vldrbq_gather_offset_z): Define polymorphic variant.
7239 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin
7241 (LDRGBU_Z_QUALIFIERS): Likewise.
7242 (LDRGS_Z_QUALIFIERS): Likewise.
7243 (LDRGU_Z_QUALIFIERS): Likewise.
7244 (LDRS_Z_QUALIFIERS): Likewise.
7245 (LDRU_Z_QUALIFIERS): Likewise.
7246 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define
7248 (mve_vldrbq_z_<supf><mode>): Likewise.
7249 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
7251 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7252 Mihail Ionescu <mihail.ionescu@arm.com>
7253 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7255 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin
7257 (STRU_P_QUALIFIERS): Likewise.
7258 (STRSU_P_QUALIFIERS): Likewise.
7259 (STRSS_P_QUALIFIERS): Likewise.
7260 (STRSBS_P_QUALIFIERS): Likewise.
7261 (STRSBU_P_QUALIFIERS): Likewise.
7262 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro.
7263 (vstrbq_p_s32): Likewise.
7264 (vstrbq_p_s16): Likewise.
7265 (vstrbq_p_u8): Likewise.
7266 (vstrbq_p_u32): Likewise.
7267 (vstrbq_p_u16): Likewise.
7268 (vstrbq_scatter_offset_p_s8): Likewise.
7269 (vstrbq_scatter_offset_p_s32): Likewise.
7270 (vstrbq_scatter_offset_p_s16): Likewise.
7271 (vstrbq_scatter_offset_p_u8): Likewise.
7272 (vstrbq_scatter_offset_p_u32): Likewise.
7273 (vstrbq_scatter_offset_p_u16): Likewise.
7274 (vstrwq_scatter_base_p_s32): Likewise.
7275 (vstrwq_scatter_base_p_u32): Likewise.
7276 (__arm_vstrbq_p_s8): Define intrinsic.
7277 (__arm_vstrbq_p_s32): Likewise.
7278 (__arm_vstrbq_p_s16): Likewise.
7279 (__arm_vstrbq_p_u8): Likewise.
7280 (__arm_vstrbq_p_u32): Likewise.
7281 (__arm_vstrbq_p_u16): Likewise.
7282 (__arm_vstrbq_scatter_offset_p_s8): Likewise.
7283 (__arm_vstrbq_scatter_offset_p_s32): Likewise.
7284 (__arm_vstrbq_scatter_offset_p_s16): Likewise.
7285 (__arm_vstrbq_scatter_offset_p_u8): Likewise.
7286 (__arm_vstrbq_scatter_offset_p_u32): Likewise.
7287 (__arm_vstrbq_scatter_offset_p_u16): Likewise.
7288 (__arm_vstrwq_scatter_base_p_s32): Likewise.
7289 (__arm_vstrwq_scatter_base_p_u32): Likewise.
7290 (vstrbq_p): Define polymorphic variant.
7291 (vstrbq_scatter_offset_p): Likewise.
7292 (vstrwq_scatter_base_p): Likewise.
7293 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin
7295 (STRU_P_QUALIFIERS): Likewise.
7296 (STRSU_P_QUALIFIERS): Likewise.
7297 (STRSS_P_QUALIFIERS): Likewise.
7298 (STRSBS_P_QUALIFIERS): Likewise.
7299 (STRSBU_P_QUALIFIERS): Likewise.
7300 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define
7302 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
7303 (mve_vstrbq_p_<supf><mode>): Likewise.
7305 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7306 Mihail Ionescu <mihail.ionescu@arm.com>
7307 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7309 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin
7311 (LDRGS_QUALIFIERS): Likewise.
7312 (LDRS_QUALIFIERS): Likewise.
7313 (LDRU_QUALIFIERS): Likewise.
7314 (LDRGBS_QUALIFIERS): Likewise.
7315 (LDRGBU_QUALIFIERS): Likewise.
7316 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro.
7317 (vldrbq_gather_offset_s8): Likewise.
7318 (vldrbq_s8): Likewise.
7319 (vldrbq_u8): Likewise.
7320 (vldrbq_gather_offset_u16): Likewise.
7321 (vldrbq_gather_offset_s16): Likewise.
7322 (vldrbq_s16): Likewise.
7323 (vldrbq_u16): Likewise.
7324 (vldrbq_gather_offset_u32): Likewise.
7325 (vldrbq_gather_offset_s32): Likewise.
7326 (vldrbq_s32): Likewise.
7327 (vldrbq_u32): Likewise.
7328 (vldrwq_gather_base_s32): Likewise.
7329 (vldrwq_gather_base_u32): Likewise.
7330 (__arm_vldrbq_gather_offset_u8): Define intrinsic.
7331 (__arm_vldrbq_gather_offset_s8): Likewise.
7332 (__arm_vldrbq_s8): Likewise.
7333 (__arm_vldrbq_u8): Likewise.
7334 (__arm_vldrbq_gather_offset_u16): Likewise.
7335 (__arm_vldrbq_gather_offset_s16): Likewise.
7336 (__arm_vldrbq_s16): Likewise.
7337 (__arm_vldrbq_u16): Likewise.
7338 (__arm_vldrbq_gather_offset_u32): Likewise.
7339 (__arm_vldrbq_gather_offset_s32): Likewise.
7340 (__arm_vldrbq_s32): Likewise.
7341 (__arm_vldrbq_u32): Likewise.
7342 (__arm_vldrwq_gather_base_s32): Likewise.
7343 (__arm_vldrwq_gather_base_u32): Likewise.
7344 (vldrbq_gather_offset): Define polymorphic variant.
7345 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin
7347 (LDRGS_QUALIFIERS): Likewise.
7348 (LDRS_QUALIFIERS): Likewise.
7349 (LDRU_QUALIFIERS): Likewise.
7350 (LDRGBS_QUALIFIERS): Likewise.
7351 (LDRGBU_QUALIFIERS): Likewise.
7352 * config/arm/mve.md (VLDRBGOQ): Define iterator.
7354 (VLDRWGBQ): Likewise.
7355 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern.
7356 (mve_vldrbq_<supf><mode>): Likewise.
7357 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
7359 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7360 Mihail Ionescu <mihail.ionescu@arm.com>
7361 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7363 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier.
7364 (STRU_QUALIFIERS): Likewise.
7365 (STRSS_QUALIFIERS): Likewise.
7366 (STRSU_QUALIFIERS): Likewise.
7367 (STRSBS_QUALIFIERS): Likewise.
7368 (STRSBU_QUALIFIERS): Likewise.
7369 * config/arm/arm_mve.h (vstrbq_s8): Define macro.
7370 (vstrbq_u8): Likewise.
7371 (vstrbq_u16): Likewise.
7372 (vstrbq_scatter_offset_s8): Likewise.
7373 (vstrbq_scatter_offset_u8): Likewise.
7374 (vstrbq_scatter_offset_u16): Likewise.
7375 (vstrbq_s16): Likewise.
7376 (vstrbq_u32): Likewise.
7377 (vstrbq_scatter_offset_s16): Likewise.
7378 (vstrbq_scatter_offset_u32): Likewise.
7379 (vstrbq_s32): Likewise.
7380 (vstrbq_scatter_offset_s32): Likewise.
7381 (vstrwq_scatter_base_s32): Likewise.
7382 (vstrwq_scatter_base_u32): Likewise.
7383 (__arm_vstrbq_scatter_offset_s8): Define intrinsic.
7384 (__arm_vstrbq_scatter_offset_s32): Likewise.
7385 (__arm_vstrbq_scatter_offset_s16): Likewise.
7386 (__arm_vstrbq_scatter_offset_u8): Likewise.
7387 (__arm_vstrbq_scatter_offset_u32): Likewise.
7388 (__arm_vstrbq_scatter_offset_u16): Likewise.
7389 (__arm_vstrbq_s8): Likewise.
7390 (__arm_vstrbq_s32): Likewise.
7391 (__arm_vstrbq_s16): Likewise.
7392 (__arm_vstrbq_u8): Likewise.
7393 (__arm_vstrbq_u32): Likewise.
7394 (__arm_vstrbq_u16): Likewise.
7395 (__arm_vstrwq_scatter_base_s32): Likewise.
7396 (__arm_vstrwq_scatter_base_u32): Likewise.
7397 (vstrbq): Define polymorphic variant.
7398 (vstrbq_scatter_offset): Likewise.
7399 (vstrwq_scatter_base): Likewise.
7400 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin
7402 (STRU_QUALIFIERS): Likewise.
7403 (STRSS_QUALIFIERS): Likewise.
7404 (STRSU_QUALIFIERS): Likewise.
7405 (STRSBS_QUALIFIERS): Likewise.
7406 (STRSBU_QUALIFIERS): Likewise.
7407 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator.
7408 (VSTRWSBQ): Define iterators.
7409 (VSTRBSOQ): Likewise.
7411 (mve_vstrbq_<supf><mode>): Define RTL pattern.
7412 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise.
7413 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
7415 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7416 Mihail Ionescu <mihail.ionescu@arm.com>
7417 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7419 * config/arm/arm_mve.h (vabdq_m_f32): Define macro.
7420 (vabdq_m_f16): Likewise.
7421 (vaddq_m_f32): Likewise.
7422 (vaddq_m_f16): Likewise.
7423 (vaddq_m_n_f32): Likewise.
7424 (vaddq_m_n_f16): Likewise.
7425 (vandq_m_f32): Likewise.
7426 (vandq_m_f16): Likewise.
7427 (vbicq_m_f32): Likewise.
7428 (vbicq_m_f16): Likewise.
7429 (vbrsrq_m_n_f32): Likewise.
7430 (vbrsrq_m_n_f16): Likewise.
7431 (vcaddq_rot270_m_f32): Likewise.
7432 (vcaddq_rot270_m_f16): Likewise.
7433 (vcaddq_rot90_m_f32): Likewise.
7434 (vcaddq_rot90_m_f16): Likewise.
7435 (vcmlaq_m_f32): Likewise.
7436 (vcmlaq_m_f16): Likewise.
7437 (vcmlaq_rot180_m_f32): Likewise.
7438 (vcmlaq_rot180_m_f16): Likewise.
7439 (vcmlaq_rot270_m_f32): Likewise.
7440 (vcmlaq_rot270_m_f16): Likewise.
7441 (vcmlaq_rot90_m_f32): Likewise.
7442 (vcmlaq_rot90_m_f16): Likewise.
7443 (vcmulq_m_f32): Likewise.
7444 (vcmulq_m_f16): Likewise.
7445 (vcmulq_rot180_m_f32): Likewise.
7446 (vcmulq_rot180_m_f16): Likewise.
7447 (vcmulq_rot270_m_f32): Likewise.
7448 (vcmulq_rot270_m_f16): Likewise.
7449 (vcmulq_rot90_m_f32): Likewise.
7450 (vcmulq_rot90_m_f16): Likewise.
7451 (vcvtq_m_n_s32_f32): Likewise.
7452 (vcvtq_m_n_s16_f16): Likewise.
7453 (vcvtq_m_n_u32_f32): Likewise.
7454 (vcvtq_m_n_u16_f16): Likewise.
7455 (veorq_m_f32): Likewise.
7456 (veorq_m_f16): Likewise.
7457 (vfmaq_m_f32): Likewise.
7458 (vfmaq_m_f16): Likewise.
7459 (vfmaq_m_n_f32): Likewise.
7460 (vfmaq_m_n_f16): Likewise.
7461 (vfmasq_m_n_f32): Likewise.
7462 (vfmasq_m_n_f16): Likewise.
7463 (vfmsq_m_f32): Likewise.
7464 (vfmsq_m_f16): Likewise.
7465 (vmaxnmq_m_f32): Likewise.
7466 (vmaxnmq_m_f16): Likewise.
7467 (vminnmq_m_f32): Likewise.
7468 (vminnmq_m_f16): Likewise.
7469 (vmulq_m_f32): Likewise.
7470 (vmulq_m_f16): Likewise.
7471 (vmulq_m_n_f32): Likewise.
7472 (vmulq_m_n_f16): Likewise.
7473 (vornq_m_f32): Likewise.
7474 (vornq_m_f16): Likewise.
7475 (vorrq_m_f32): Likewise.
7476 (vorrq_m_f16): Likewise.
7477 (vsubq_m_f32): Likewise.
7478 (vsubq_m_f16): Likewise.
7479 (vsubq_m_n_f32): Likewise.
7480 (vsubq_m_n_f16): Likewise.
7481 (__attribute__): Likewise.
7482 (__arm_vabdq_m_f32): Likewise.
7483 (__arm_vabdq_m_f16): Likewise.
7484 (__arm_vaddq_m_f32): Likewise.
7485 (__arm_vaddq_m_f16): Likewise.
7486 (__arm_vaddq_m_n_f32): Likewise.
7487 (__arm_vaddq_m_n_f16): Likewise.
7488 (__arm_vandq_m_f32): Likewise.
7489 (__arm_vandq_m_f16): Likewise.
7490 (__arm_vbicq_m_f32): Likewise.
7491 (__arm_vbicq_m_f16): Likewise.
7492 (__arm_vbrsrq_m_n_f32): Likewise.
7493 (__arm_vbrsrq_m_n_f16): Likewise.
7494 (__arm_vcaddq_rot270_m_f32): Likewise.
7495 (__arm_vcaddq_rot270_m_f16): Likewise.
7496 (__arm_vcaddq_rot90_m_f32): Likewise.
7497 (__arm_vcaddq_rot90_m_f16): Likewise.
7498 (__arm_vcmlaq_m_f32): Likewise.
7499 (__arm_vcmlaq_m_f16): Likewise.
7500 (__arm_vcmlaq_rot180_m_f32): Likewise.
7501 (__arm_vcmlaq_rot180_m_f16): Likewise.
7502 (__arm_vcmlaq_rot270_m_f32): Likewise.
7503 (__arm_vcmlaq_rot270_m_f16): Likewise.
7504 (__arm_vcmlaq_rot90_m_f32): Likewise.
7505 (__arm_vcmlaq_rot90_m_f16): Likewise.
7506 (__arm_vcmulq_m_f32): Likewise.
7507 (__arm_vcmulq_m_f16): Likewise.
7508 (__arm_vcmulq_rot180_m_f32): Define intrinsic.
7509 (__arm_vcmulq_rot180_m_f16): Likewise.
7510 (__arm_vcmulq_rot270_m_f32): Likewise.
7511 (__arm_vcmulq_rot270_m_f16): Likewise.
7512 (__arm_vcmulq_rot90_m_f32): Likewise.
7513 (__arm_vcmulq_rot90_m_f16): Likewise.
7514 (__arm_vcvtq_m_n_s32_f32): Likewise.
7515 (__arm_vcvtq_m_n_s16_f16): Likewise.
7516 (__arm_vcvtq_m_n_u32_f32): Likewise.
7517 (__arm_vcvtq_m_n_u16_f16): Likewise.
7518 (__arm_veorq_m_f32): Likewise.
7519 (__arm_veorq_m_f16): Likewise.
7520 (__arm_vfmaq_m_f32): Likewise.
7521 (__arm_vfmaq_m_f16): Likewise.
7522 (__arm_vfmaq_m_n_f32): Likewise.
7523 (__arm_vfmaq_m_n_f16): Likewise.
7524 (__arm_vfmasq_m_n_f32): Likewise.
7525 (__arm_vfmasq_m_n_f16): Likewise.
7526 (__arm_vfmsq_m_f32): Likewise.
7527 (__arm_vfmsq_m_f16): Likewise.
7528 (__arm_vmaxnmq_m_f32): Likewise.
7529 (__arm_vmaxnmq_m_f16): Likewise.
7530 (__arm_vminnmq_m_f32): Likewise.
7531 (__arm_vminnmq_m_f16): Likewise.
7532 (__arm_vmulq_m_f32): Likewise.
7533 (__arm_vmulq_m_f16): Likewise.
7534 (__arm_vmulq_m_n_f32): Likewise.
7535 (__arm_vmulq_m_n_f16): Likewise.
7536 (__arm_vornq_m_f32): Likewise.
7537 (__arm_vornq_m_f16): Likewise.
7538 (__arm_vorrq_m_f32): Likewise.
7539 (__arm_vorrq_m_f16): Likewise.
7540 (__arm_vsubq_m_f32): Likewise.
7541 (__arm_vsubq_m_f16): Likewise.
7542 (__arm_vsubq_m_n_f32): Likewise.
7543 (__arm_vsubq_m_n_f16): Likewise.
7544 (vabdq_m): Define polymorphic variant.
7545 (vaddq_m): Likewise.
7546 (vaddq_m_n): Likewise.
7547 (vandq_m): Likewise.
7548 (vbicq_m): Likewise.
7549 (vbrsrq_m_n): Likewise.
7550 (vcaddq_rot270_m): Likewise.
7551 (vcaddq_rot90_m): Likewise.
7552 (vcmlaq_m): Likewise.
7553 (vcmlaq_rot180_m): Likewise.
7554 (vcmlaq_rot270_m): Likewise.
7555 (vcmlaq_rot90_m): Likewise.
7556 (vcmulq_m): Likewise.
7557 (vcmulq_rot180_m): Likewise.
7558 (vcmulq_rot270_m): Likewise.
7559 (vcmulq_rot90_m): Likewise.
7560 (veorq_m): Likewise.
7561 (vfmaq_m): Likewise.
7562 (vfmaq_m_n): Likewise.
7563 (vfmasq_m_n): Likewise.
7564 (vfmsq_m): Likewise.
7565 (vmaxnmq_m): Likewise.
7566 (vminnmq_m): Likewise.
7567 (vmulq_m): Likewise.
7568 (vmulq_m_n): Likewise.
7569 (vornq_m): Likewise.
7570 (vsubq_m): Likewise.
7571 (vsubq_m_n): Likewise.
7572 (vorrq_m): Likewise.
7573 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7575 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7576 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
7577 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern.
7578 (mve_vaddq_m_f<mode>): Likewise.
7579 (mve_vaddq_m_n_f<mode>): Likewise.
7580 (mve_vandq_m_f<mode>): Likewise.
7581 (mve_vbicq_m_f<mode>): Likewise.
7582 (mve_vbrsrq_m_n_f<mode>): Likewise.
7583 (mve_vcaddq_rot270_m_f<mode>): Likewise.
7584 (mve_vcaddq_rot90_m_f<mode>): Likewise.
7585 (mve_vcmlaq_m_f<mode>): Likewise.
7586 (mve_vcmlaq_rot180_m_f<mode>): Likewise.
7587 (mve_vcmlaq_rot270_m_f<mode>): Likewise.
7588 (mve_vcmlaq_rot90_m_f<mode>): Likewise.
7589 (mve_vcmulq_m_f<mode>): Likewise.
7590 (mve_vcmulq_rot180_m_f<mode>): Likewise.
7591 (mve_vcmulq_rot270_m_f<mode>): Likewise.
7592 (mve_vcmulq_rot90_m_f<mode>): Likewise.
7593 (mve_veorq_m_f<mode>): Likewise.
7594 (mve_vfmaq_m_f<mode>): Likewise.
7595 (mve_vfmaq_m_n_f<mode>): Likewise.
7596 (mve_vfmasq_m_n_f<mode>): Likewise.
7597 (mve_vfmsq_m_f<mode>): Likewise.
7598 (mve_vmaxnmq_m_f<mode>): Likewise.
7599 (mve_vminnmq_m_f<mode>): Likewise.
7600 (mve_vmulq_m_f<mode>): Likewise.
7601 (mve_vmulq_m_n_f<mode>): Likewise.
7602 (mve_vornq_m_f<mode>): Likewise.
7603 (mve_vorrq_m_f<mode>): Likewise.
7604 (mve_vsubq_m_f<mode>): Likewise.
7605 (mve_vsubq_m_n_f<mode>): Likewise.
7607 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7608 Mihail Ionescu <mihail.ionescu@arm.com>
7609 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7611 * config/arm/arm-protos.h (arm_mve_immediate_check):
7612 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check
7613 mode and interger value.
7614 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
7615 (vmlaldavaq_p_s16): Likewise.
7616 (vmlaldavaq_p_u32): Likewise.
7617 (vmlaldavaq_p_u16): Likewise.
7618 (vmlaldavaxq_p_s32): Likewise.
7619 (vmlaldavaxq_p_s16): Likewise.
7620 (vmlaldavaxq_p_u32): Likewise.
7621 (vmlaldavaxq_p_u16): Likewise.
7622 (vmlsldavaq_p_s32): Likewise.
7623 (vmlsldavaq_p_s16): Likewise.
7624 (vmlsldavaxq_p_s32): Likewise.
7625 (vmlsldavaxq_p_s16): Likewise.
7626 (vmullbq_poly_m_p8): Likewise.
7627 (vmullbq_poly_m_p16): Likewise.
7628 (vmulltq_poly_m_p8): Likewise.
7629 (vmulltq_poly_m_p16): Likewise.
7630 (vqdmullbq_m_n_s32): Likewise.
7631 (vqdmullbq_m_n_s16): Likewise.
7632 (vqdmullbq_m_s32): Likewise.
7633 (vqdmullbq_m_s16): Likewise.
7634 (vqdmulltq_m_n_s32): Likewise.
7635 (vqdmulltq_m_n_s16): Likewise.
7636 (vqdmulltq_m_s32): Likewise.
7637 (vqdmulltq_m_s16): Likewise.
7638 (vqrshrnbq_m_n_s32): Likewise.
7639 (vqrshrnbq_m_n_s16): Likewise.
7640 (vqrshrnbq_m_n_u32): Likewise.
7641 (vqrshrnbq_m_n_u16): Likewise.
7642 (vqrshrntq_m_n_s32): Likewise.
7643 (vqrshrntq_m_n_s16): Likewise.
7644 (vqrshrntq_m_n_u32): Likewise.
7645 (vqrshrntq_m_n_u16): Likewise.
7646 (vqrshrunbq_m_n_s32): Likewise.
7647 (vqrshrunbq_m_n_s16): Likewise.
7648 (vqrshruntq_m_n_s32): Likewise.
7649 (vqrshruntq_m_n_s16): Likewise.
7650 (vqshrnbq_m_n_s32): Likewise.
7651 (vqshrnbq_m_n_s16): Likewise.
7652 (vqshrnbq_m_n_u32): Likewise.
7653 (vqshrnbq_m_n_u16): Likewise.
7654 (vqshrntq_m_n_s32): Likewise.
7655 (vqshrntq_m_n_s16): Likewise.
7656 (vqshrntq_m_n_u32): Likewise.
7657 (vqshrntq_m_n_u16): Likewise.
7658 (vqshrunbq_m_n_s32): Likewise.
7659 (vqshrunbq_m_n_s16): Likewise.
7660 (vqshruntq_m_n_s32): Likewise.
7661 (vqshruntq_m_n_s16): Likewise.
7662 (vrmlaldavhaq_p_s32): Likewise.
7663 (vrmlaldavhaq_p_u32): Likewise.
7664 (vrmlaldavhaxq_p_s32): Likewise.
7665 (vrmlsldavhaq_p_s32): Likewise.
7666 (vrmlsldavhaxq_p_s32): Likewise.
7667 (vrshrnbq_m_n_s32): Likewise.
7668 (vrshrnbq_m_n_s16): Likewise.
7669 (vrshrnbq_m_n_u32): Likewise.
7670 (vrshrnbq_m_n_u16): Likewise.
7671 (vrshrntq_m_n_s32): Likewise.
7672 (vrshrntq_m_n_s16): Likewise.
7673 (vrshrntq_m_n_u32): Likewise.
7674 (vrshrntq_m_n_u16): Likewise.
7675 (vshllbq_m_n_s8): Likewise.
7676 (vshllbq_m_n_s16): Likewise.
7677 (vshllbq_m_n_u8): Likewise.
7678 (vshllbq_m_n_u16): Likewise.
7679 (vshlltq_m_n_s8): Likewise.
7680 (vshlltq_m_n_s16): Likewise.
7681 (vshlltq_m_n_u8): Likewise.
7682 (vshlltq_m_n_u16): Likewise.
7683 (vshrnbq_m_n_s32): Likewise.
7684 (vshrnbq_m_n_s16): Likewise.
7685 (vshrnbq_m_n_u32): Likewise.
7686 (vshrnbq_m_n_u16): Likewise.
7687 (vshrntq_m_n_s32): Likewise.
7688 (vshrntq_m_n_s16): Likewise.
7689 (vshrntq_m_n_u32): Likewise.
7690 (vshrntq_m_n_u16): Likewise.
7691 (__arm_vmlaldavaq_p_s32): Define intrinsic.
7692 (__arm_vmlaldavaq_p_s16): Likewise.
7693 (__arm_vmlaldavaq_p_u32): Likewise.
7694 (__arm_vmlaldavaq_p_u16): Likewise.
7695 (__arm_vmlaldavaxq_p_s32): Likewise.
7696 (__arm_vmlaldavaxq_p_s16): Likewise.
7697 (__arm_vmlaldavaxq_p_u32): Likewise.
7698 (__arm_vmlaldavaxq_p_u16): Likewise.
7699 (__arm_vmlsldavaq_p_s32): Likewise.
7700 (__arm_vmlsldavaq_p_s16): Likewise.
7701 (__arm_vmlsldavaxq_p_s32): Likewise.
7702 (__arm_vmlsldavaxq_p_s16): Likewise.
7703 (__arm_vmullbq_poly_m_p8): Likewise.
7704 (__arm_vmullbq_poly_m_p16): Likewise.
7705 (__arm_vmulltq_poly_m_p8): Likewise.
7706 (__arm_vmulltq_poly_m_p16): Likewise.
7707 (__arm_vqdmullbq_m_n_s32): Likewise.
7708 (__arm_vqdmullbq_m_n_s16): Likewise.
7709 (__arm_vqdmullbq_m_s32): Likewise.
7710 (__arm_vqdmullbq_m_s16): Likewise.
7711 (__arm_vqdmulltq_m_n_s32): Likewise.
7712 (__arm_vqdmulltq_m_n_s16): Likewise.
7713 (__arm_vqdmulltq_m_s32): Likewise.
7714 (__arm_vqdmulltq_m_s16): Likewise.
7715 (__arm_vqrshrnbq_m_n_s32): Likewise.
7716 (__arm_vqrshrnbq_m_n_s16): Likewise.
7717 (__arm_vqrshrnbq_m_n_u32): Likewise.
7718 (__arm_vqrshrnbq_m_n_u16): Likewise.
7719 (__arm_vqrshrntq_m_n_s32): Likewise.
7720 (__arm_vqrshrntq_m_n_s16): Likewise.
7721 (__arm_vqrshrntq_m_n_u32): Likewise.
7722 (__arm_vqrshrntq_m_n_u16): Likewise.
7723 (__arm_vqrshrunbq_m_n_s32): Likewise.
7724 (__arm_vqrshrunbq_m_n_s16): Likewise.
7725 (__arm_vqrshruntq_m_n_s32): Likewise.
7726 (__arm_vqrshruntq_m_n_s16): Likewise.
7727 (__arm_vqshrnbq_m_n_s32): Likewise.
7728 (__arm_vqshrnbq_m_n_s16): Likewise.
7729 (__arm_vqshrnbq_m_n_u32): Likewise.
7730 (__arm_vqshrnbq_m_n_u16): Likewise.
7731 (__arm_vqshrntq_m_n_s32): Likewise.
7732 (__arm_vqshrntq_m_n_s16): Likewise.
7733 (__arm_vqshrntq_m_n_u32): Likewise.
7734 (__arm_vqshrntq_m_n_u16): Likewise.
7735 (__arm_vqshrunbq_m_n_s32): Likewise.
7736 (__arm_vqshrunbq_m_n_s16): Likewise.
7737 (__arm_vqshruntq_m_n_s32): Likewise.
7738 (__arm_vqshruntq_m_n_s16): Likewise.
7739 (__arm_vrmlaldavhaq_p_s32): Likewise.
7740 (__arm_vrmlaldavhaq_p_u32): Likewise.
7741 (__arm_vrmlaldavhaxq_p_s32): Likewise.
7742 (__arm_vrmlsldavhaq_p_s32): Likewise.
7743 (__arm_vrmlsldavhaxq_p_s32): Likewise.
7744 (__arm_vrshrnbq_m_n_s32): Likewise.
7745 (__arm_vrshrnbq_m_n_s16): Likewise.
7746 (__arm_vrshrnbq_m_n_u32): Likewise.
7747 (__arm_vrshrnbq_m_n_u16): Likewise.
7748 (__arm_vrshrntq_m_n_s32): Likewise.
7749 (__arm_vrshrntq_m_n_s16): Likewise.
7750 (__arm_vrshrntq_m_n_u32): Likewise.
7751 (__arm_vrshrntq_m_n_u16): Likewise.
7752 (__arm_vshllbq_m_n_s8): Likewise.
7753 (__arm_vshllbq_m_n_s16): Likewise.
7754 (__arm_vshllbq_m_n_u8): Likewise.
7755 (__arm_vshllbq_m_n_u16): Likewise.
7756 (__arm_vshlltq_m_n_s8): Likewise.
7757 (__arm_vshlltq_m_n_s16): Likewise.
7758 (__arm_vshlltq_m_n_u8): Likewise.
7759 (__arm_vshlltq_m_n_u16): Likewise.
7760 (__arm_vshrnbq_m_n_s32): Likewise.
7761 (__arm_vshrnbq_m_n_s16): Likewise.
7762 (__arm_vshrnbq_m_n_u32): Likewise.
7763 (__arm_vshrnbq_m_n_u16): Likewise.
7764 (__arm_vshrntq_m_n_s32): Likewise.
7765 (__arm_vshrntq_m_n_s16): Likewise.
7766 (__arm_vshrntq_m_n_u32): Likewise.
7767 (__arm_vshrntq_m_n_u16): Likewise.
7768 (vmullbq_poly_m): Define polymorphic variant.
7769 (vmulltq_poly_m): Likewise.
7770 (vshllbq_m): Likewise.
7771 (vshrntq_m_n): Likewise.
7772 (vshrnbq_m_n): Likewise.
7773 (vshlltq_m_n): Likewise.
7774 (vshllbq_m_n): Likewise.
7775 (vrshrntq_m_n): Likewise.
7776 (vrshrnbq_m_n): Likewise.
7777 (vqshruntq_m_n): Likewise.
7778 (vqshrunbq_m_n): Likewise.
7779 (vqdmullbq_m_n): Likewise.
7780 (vqdmullbq_m): Likewise.
7781 (vqdmulltq_m_n): Likewise.
7782 (vqdmulltq_m): Likewise.
7783 (vqrshrnbq_m_n): Likewise.
7784 (vqrshrntq_m_n): Likewise.
7785 (vqrshrunbq_m_n): Likewise.
7786 (vqrshruntq_m_n): Likewise.
7787 (vqshrnbq_m_n): Likewise.
7788 (vqshrntq_m_n): Likewise.
7789 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7791 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7792 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
7793 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
7794 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
7795 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
7796 (VMLALDAVAXQ_P): Likewise.
7797 (VQRSHRNBQ_M_N): Likewise.
7798 (VQRSHRNTQ_M_N): Likewise.
7799 (VQSHRNBQ_M_N): Likewise.
7800 (VQSHRNTQ_M_N): Likewise.
7801 (VRSHRNBQ_M_N): Likewise.
7802 (VRSHRNTQ_M_N): Likewise.
7803 (VSHLLBQ_M_N): Likewise.
7804 (VSHLLTQ_M_N): Likewise.
7805 (VSHRNBQ_M_N): Likewise.
7806 (VSHRNTQ_M_N): Likewise.
7807 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
7808 (mve_vmlaldavaxq_p_<supf><mode>): Likewise.
7809 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
7810 (mve_vqrshrntq_m_n_<supf><mode>): Likewise.
7811 (mve_vqshrnbq_m_n_<supf><mode>): Likewise.
7812 (mve_vqshrntq_m_n_<supf><mode>): Likewise.
7813 (mve_vrmlaldavhaq_p_sv4si): Likewise.
7814 (mve_vrshrnbq_m_n_<supf><mode>): Likewise.
7815 (mve_vrshrntq_m_n_<supf><mode>): Likewise.
7816 (mve_vshllbq_m_n_<supf><mode>): Likewise.
7817 (mve_vshlltq_m_n_<supf><mode>): Likewise.
7818 (mve_vshrnbq_m_n_<supf><mode>): Likewise.
7819 (mve_vshrntq_m_n_<supf><mode>): Likewise.
7820 (mve_vmlsldavaq_p_s<mode>): Likewise.
7821 (mve_vmlsldavaxq_p_s<mode>): Likewise.
7822 (mve_vmullbq_poly_m_p<mode>): Likewise.
7823 (mve_vmulltq_poly_m_p<mode>): Likewise.
7824 (mve_vqdmullbq_m_n_s<mode>): Likewise.
7825 (mve_vqdmullbq_m_s<mode>): Likewise.
7826 (mve_vqdmulltq_m_n_s<mode>): Likewise.
7827 (mve_vqdmulltq_m_s<mode>): Likewise.
7828 (mve_vqrshrunbq_m_n_s<mode>): Likewise.
7829 (mve_vqrshruntq_m_n_s<mode>): Likewise.
7830 (mve_vqshrunbq_m_n_s<mode>): Likewise.
7831 (mve_vqshruntq_m_n_s<mode>): Likewise.
7832 (mve_vrmlaldavhaq_p_uv4si): Likewise.
7833 (mve_vrmlaldavhaxq_p_sv4si): Likewise.
7834 (mve_vrmlsldavhaq_p_sv4si): Likewise.
7835 (mve_vrmlsldavhaxq_p_sv4si): Likewise.
7837 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7838 Mihail Ionescu <mihail.ionescu@arm.com>
7839 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7841 * config/arm/arm_mve.h (vabdq_m_s8): Define macro.
7842 (vabdq_m_s32): Likewise.
7843 (vabdq_m_s16): Likewise.
7844 (vabdq_m_u8): Likewise.
7845 (vabdq_m_u32): Likewise.
7846 (vabdq_m_u16): Likewise.
7847 (vaddq_m_n_s8): Likewise.
7848 (vaddq_m_n_s32): Likewise.
7849 (vaddq_m_n_s16): Likewise.
7850 (vaddq_m_n_u8): Likewise.
7851 (vaddq_m_n_u32): Likewise.
7852 (vaddq_m_n_u16): Likewise.
7853 (vaddq_m_s8): Likewise.
7854 (vaddq_m_s32): Likewise.
7855 (vaddq_m_s16): Likewise.
7856 (vaddq_m_u8): Likewise.
7857 (vaddq_m_u32): Likewise.
7858 (vaddq_m_u16): Likewise.
7859 (vandq_m_s8): Likewise.
7860 (vandq_m_s32): Likewise.
7861 (vandq_m_s16): Likewise.
7862 (vandq_m_u8): Likewise.
7863 (vandq_m_u32): Likewise.
7864 (vandq_m_u16): Likewise.
7865 (vbicq_m_s8): Likewise.
7866 (vbicq_m_s32): Likewise.
7867 (vbicq_m_s16): Likewise.
7868 (vbicq_m_u8): Likewise.
7869 (vbicq_m_u32): Likewise.
7870 (vbicq_m_u16): Likewise.
7871 (vbrsrq_m_n_s8): Likewise.
7872 (vbrsrq_m_n_s32): Likewise.
7873 (vbrsrq_m_n_s16): Likewise.
7874 (vbrsrq_m_n_u8): Likewise.
7875 (vbrsrq_m_n_u32): Likewise.
7876 (vbrsrq_m_n_u16): Likewise.
7877 (vcaddq_rot270_m_s8): Likewise.
7878 (vcaddq_rot270_m_s32): Likewise.
7879 (vcaddq_rot270_m_s16): Likewise.
7880 (vcaddq_rot270_m_u8): Likewise.
7881 (vcaddq_rot270_m_u32): Likewise.
7882 (vcaddq_rot270_m_u16): Likewise.
7883 (vcaddq_rot90_m_s8): Likewise.
7884 (vcaddq_rot90_m_s32): Likewise.
7885 (vcaddq_rot90_m_s16): Likewise.
7886 (vcaddq_rot90_m_u8): Likewise.
7887 (vcaddq_rot90_m_u32): Likewise.
7888 (vcaddq_rot90_m_u16): Likewise.
7889 (veorq_m_s8): Likewise.
7890 (veorq_m_s32): Likewise.
7891 (veorq_m_s16): Likewise.
7892 (veorq_m_u8): Likewise.
7893 (veorq_m_u32): Likewise.
7894 (veorq_m_u16): Likewise.
7895 (vhaddq_m_n_s8): Likewise.
7896 (vhaddq_m_n_s32): Likewise.
7897 (vhaddq_m_n_s16): Likewise.
7898 (vhaddq_m_n_u8): Likewise.
7899 (vhaddq_m_n_u32): Likewise.
7900 (vhaddq_m_n_u16): Likewise.
7901 (vhaddq_m_s8): Likewise.
7902 (vhaddq_m_s32): Likewise.
7903 (vhaddq_m_s16): Likewise.
7904 (vhaddq_m_u8): Likewise.
7905 (vhaddq_m_u32): Likewise.
7906 (vhaddq_m_u16): Likewise.
7907 (vhcaddq_rot270_m_s8): Likewise.
7908 (vhcaddq_rot270_m_s32): Likewise.
7909 (vhcaddq_rot270_m_s16): Likewise.
7910 (vhcaddq_rot90_m_s8): Likewise.
7911 (vhcaddq_rot90_m_s32): Likewise.
7912 (vhcaddq_rot90_m_s16): Likewise.
7913 (vhsubq_m_n_s8): Likewise.
7914 (vhsubq_m_n_s32): Likewise.
7915 (vhsubq_m_n_s16): Likewise.
7916 (vhsubq_m_n_u8): Likewise.
7917 (vhsubq_m_n_u32): Likewise.
7918 (vhsubq_m_n_u16): Likewise.
7919 (vhsubq_m_s8): Likewise.
7920 (vhsubq_m_s32): Likewise.
7921 (vhsubq_m_s16): Likewise.
7922 (vhsubq_m_u8): Likewise.
7923 (vhsubq_m_u32): Likewise.
7924 (vhsubq_m_u16): Likewise.
7925 (vmaxq_m_s8): Likewise.
7926 (vmaxq_m_s32): Likewise.
7927 (vmaxq_m_s16): Likewise.
7928 (vmaxq_m_u8): Likewise.
7929 (vmaxq_m_u32): Likewise.
7930 (vmaxq_m_u16): Likewise.
7931 (vminq_m_s8): Likewise.
7932 (vminq_m_s32): Likewise.
7933 (vminq_m_s16): Likewise.
7934 (vminq_m_u8): Likewise.
7935 (vminq_m_u32): Likewise.
7936 (vminq_m_u16): Likewise.
7937 (vmladavaq_p_s8): Likewise.
7938 (vmladavaq_p_s32): Likewise.
7939 (vmladavaq_p_s16): Likewise.
7940 (vmladavaq_p_u8): Likewise.
7941 (vmladavaq_p_u32): Likewise.
7942 (vmladavaq_p_u16): Likewise.
7943 (vmladavaxq_p_s8): Likewise.
7944 (vmladavaxq_p_s32): Likewise.
7945 (vmladavaxq_p_s16): Likewise.
7946 (vmlaq_m_n_s8): Likewise.
7947 (vmlaq_m_n_s32): Likewise.
7948 (vmlaq_m_n_s16): Likewise.
7949 (vmlaq_m_n_u8): Likewise.
7950 (vmlaq_m_n_u32): Likewise.
7951 (vmlaq_m_n_u16): Likewise.
7952 (vmlasq_m_n_s8): Likewise.
7953 (vmlasq_m_n_s32): Likewise.
7954 (vmlasq_m_n_s16): Likewise.
7955 (vmlasq_m_n_u8): Likewise.
7956 (vmlasq_m_n_u32): Likewise.
7957 (vmlasq_m_n_u16): Likewise.
7958 (vmlsdavaq_p_s8): Likewise.
7959 (vmlsdavaq_p_s32): Likewise.
7960 (vmlsdavaq_p_s16): Likewise.
7961 (vmlsdavaxq_p_s8): Likewise.
7962 (vmlsdavaxq_p_s32): Likewise.
7963 (vmlsdavaxq_p_s16): Likewise.
7964 (vmulhq_m_s8): Likewise.
7965 (vmulhq_m_s32): Likewise.
7966 (vmulhq_m_s16): Likewise.
7967 (vmulhq_m_u8): Likewise.
7968 (vmulhq_m_u32): Likewise.
7969 (vmulhq_m_u16): Likewise.
7970 (vmullbq_int_m_s8): Likewise.
7971 (vmullbq_int_m_s32): Likewise.
7972 (vmullbq_int_m_s16): Likewise.
7973 (vmullbq_int_m_u8): Likewise.
7974 (vmullbq_int_m_u32): Likewise.
7975 (vmullbq_int_m_u16): Likewise.
7976 (vmulltq_int_m_s8): Likewise.
7977 (vmulltq_int_m_s32): Likewise.
7978 (vmulltq_int_m_s16): Likewise.
7979 (vmulltq_int_m_u8): Likewise.
7980 (vmulltq_int_m_u32): Likewise.
7981 (vmulltq_int_m_u16): Likewise.
7982 (vmulq_m_n_s8): Likewise.
7983 (vmulq_m_n_s32): Likewise.
7984 (vmulq_m_n_s16): Likewise.
7985 (vmulq_m_n_u8): Likewise.
7986 (vmulq_m_n_u32): Likewise.
7987 (vmulq_m_n_u16): Likewise.
7988 (vmulq_m_s8): Likewise.
7989 (vmulq_m_s32): Likewise.
7990 (vmulq_m_s16): Likewise.
7991 (vmulq_m_u8): Likewise.
7992 (vmulq_m_u32): Likewise.
7993 (vmulq_m_u16): Likewise.
7994 (vornq_m_s8): Likewise.
7995 (vornq_m_s32): Likewise.
7996 (vornq_m_s16): Likewise.
7997 (vornq_m_u8): Likewise.
7998 (vornq_m_u32): Likewise.
7999 (vornq_m_u16): Likewise.
8000 (vorrq_m_s8): Likewise.
8001 (vorrq_m_s32): Likewise.
8002 (vorrq_m_s16): Likewise.
8003 (vorrq_m_u8): Likewise.
8004 (vorrq_m_u32): Likewise.
8005 (vorrq_m_u16): Likewise.
8006 (vqaddq_m_n_s8): Likewise.
8007 (vqaddq_m_n_s32): Likewise.
8008 (vqaddq_m_n_s16): Likewise.
8009 (vqaddq_m_n_u8): Likewise.
8010 (vqaddq_m_n_u32): Likewise.
8011 (vqaddq_m_n_u16): Likewise.
8012 (vqaddq_m_s8): Likewise.
8013 (vqaddq_m_s32): Likewise.
8014 (vqaddq_m_s16): Likewise.
8015 (vqaddq_m_u8): Likewise.
8016 (vqaddq_m_u32): Likewise.
8017 (vqaddq_m_u16): Likewise.
8018 (vqdmladhq_m_s8): Likewise.
8019 (vqdmladhq_m_s32): Likewise.
8020 (vqdmladhq_m_s16): Likewise.
8021 (vqdmladhxq_m_s8): Likewise.
8022 (vqdmladhxq_m_s32): Likewise.
8023 (vqdmladhxq_m_s16): Likewise.
8024 (vqdmlahq_m_n_s8): Likewise.
8025 (vqdmlahq_m_n_s32): Likewise.
8026 (vqdmlahq_m_n_s16): Likewise.
8027 (vqdmlahq_m_n_u8): Likewise.
8028 (vqdmlahq_m_n_u32): Likewise.
8029 (vqdmlahq_m_n_u16): Likewise.
8030 (vqdmlsdhq_m_s8): Likewise.
8031 (vqdmlsdhq_m_s32): Likewise.
8032 (vqdmlsdhq_m_s16): Likewise.
8033 (vqdmlsdhxq_m_s8): Likewise.
8034 (vqdmlsdhxq_m_s32): Likewise.
8035 (vqdmlsdhxq_m_s16): Likewise.
8036 (vqdmulhq_m_n_s8): Likewise.
8037 (vqdmulhq_m_n_s32): Likewise.
8038 (vqdmulhq_m_n_s16): Likewise.
8039 (vqdmulhq_m_s8): Likewise.
8040 (vqdmulhq_m_s32): Likewise.
8041 (vqdmulhq_m_s16): Likewise.
8042 (vqrdmladhq_m_s8): Likewise.
8043 (vqrdmladhq_m_s32): Likewise.
8044 (vqrdmladhq_m_s16): Likewise.
8045 (vqrdmladhxq_m_s8): Likewise.
8046 (vqrdmladhxq_m_s32): Likewise.
8047 (vqrdmladhxq_m_s16): Likewise.
8048 (vqrdmlahq_m_n_s8): Likewise.
8049 (vqrdmlahq_m_n_s32): Likewise.
8050 (vqrdmlahq_m_n_s16): Likewise.
8051 (vqrdmlahq_m_n_u8): Likewise.
8052 (vqrdmlahq_m_n_u32): Likewise.
8053 (vqrdmlahq_m_n_u16): Likewise.
8054 (vqrdmlashq_m_n_s8): Likewise.
8055 (vqrdmlashq_m_n_s32): Likewise.
8056 (vqrdmlashq_m_n_s16): Likewise.
8057 (vqrdmlashq_m_n_u8): Likewise.
8058 (vqrdmlashq_m_n_u32): Likewise.
8059 (vqrdmlashq_m_n_u16): Likewise.
8060 (vqrdmlsdhq_m_s8): Likewise.
8061 (vqrdmlsdhq_m_s32): Likewise.
8062 (vqrdmlsdhq_m_s16): Likewise.
8063 (vqrdmlsdhxq_m_s8): Likewise.
8064 (vqrdmlsdhxq_m_s32): Likewise.
8065 (vqrdmlsdhxq_m_s16): Likewise.
8066 (vqrdmulhq_m_n_s8): Likewise.
8067 (vqrdmulhq_m_n_s32): Likewise.
8068 (vqrdmulhq_m_n_s16): Likewise.
8069 (vqrdmulhq_m_s8): Likewise.
8070 (vqrdmulhq_m_s32): Likewise.
8071 (vqrdmulhq_m_s16): Likewise.
8072 (vqrshlq_m_s8): Likewise.
8073 (vqrshlq_m_s32): Likewise.
8074 (vqrshlq_m_s16): Likewise.
8075 (vqrshlq_m_u8): Likewise.
8076 (vqrshlq_m_u32): Likewise.
8077 (vqrshlq_m_u16): Likewise.
8078 (vqshlq_m_n_s8): Likewise.
8079 (vqshlq_m_n_s32): Likewise.
8080 (vqshlq_m_n_s16): Likewise.
8081 (vqshlq_m_n_u8): Likewise.
8082 (vqshlq_m_n_u32): Likewise.
8083 (vqshlq_m_n_u16): Likewise.
8084 (vqshlq_m_s8): Likewise.
8085 (vqshlq_m_s32): Likewise.
8086 (vqshlq_m_s16): Likewise.
8087 (vqshlq_m_u8): Likewise.
8088 (vqshlq_m_u32): Likewise.
8089 (vqshlq_m_u16): Likewise.
8090 (vqsubq_m_n_s8): Likewise.
8091 (vqsubq_m_n_s32): Likewise.
8092 (vqsubq_m_n_s16): Likewise.
8093 (vqsubq_m_n_u8): Likewise.
8094 (vqsubq_m_n_u32): Likewise.
8095 (vqsubq_m_n_u16): Likewise.
8096 (vqsubq_m_s8): Likewise.
8097 (vqsubq_m_s32): Likewise.
8098 (vqsubq_m_s16): Likewise.
8099 (vqsubq_m_u8): Likewise.
8100 (vqsubq_m_u32): Likewise.
8101 (vqsubq_m_u16): Likewise.
8102 (vrhaddq_m_s8): Likewise.
8103 (vrhaddq_m_s32): Likewise.
8104 (vrhaddq_m_s16): Likewise.
8105 (vrhaddq_m_u8): Likewise.
8106 (vrhaddq_m_u32): Likewise.
8107 (vrhaddq_m_u16): Likewise.
8108 (vrmulhq_m_s8): Likewise.
8109 (vrmulhq_m_s32): Likewise.
8110 (vrmulhq_m_s16): Likewise.
8111 (vrmulhq_m_u8): Likewise.
8112 (vrmulhq_m_u32): Likewise.
8113 (vrmulhq_m_u16): Likewise.
8114 (vrshlq_m_s8): Likewise.
8115 (vrshlq_m_s32): Likewise.
8116 (vrshlq_m_s16): Likewise.
8117 (vrshlq_m_u8): Likewise.
8118 (vrshlq_m_u32): Likewise.
8119 (vrshlq_m_u16): Likewise.
8120 (vrshrq_m_n_s8): Likewise.
8121 (vrshrq_m_n_s32): Likewise.
8122 (vrshrq_m_n_s16): Likewise.
8123 (vrshrq_m_n_u8): Likewise.
8124 (vrshrq_m_n_u32): Likewise.
8125 (vrshrq_m_n_u16): Likewise.
8126 (vshlq_m_n_s8): Likewise.
8127 (vshlq_m_n_s32): Likewise.
8128 (vshlq_m_n_s16): Likewise.
8129 (vshlq_m_n_u8): Likewise.
8130 (vshlq_m_n_u32): Likewise.
8131 (vshlq_m_n_u16): Likewise.
8132 (vshrq_m_n_s8): Likewise.
8133 (vshrq_m_n_s32): Likewise.
8134 (vshrq_m_n_s16): Likewise.
8135 (vshrq_m_n_u8): Likewise.
8136 (vshrq_m_n_u32): Likewise.
8137 (vshrq_m_n_u16): Likewise.
8138 (vsliq_m_n_s8): Likewise.
8139 (vsliq_m_n_s32): Likewise.
8140 (vsliq_m_n_s16): Likewise.
8141 (vsliq_m_n_u8): Likewise.
8142 (vsliq_m_n_u32): Likewise.
8143 (vsliq_m_n_u16): Likewise.
8144 (vsubq_m_n_s8): Likewise.
8145 (vsubq_m_n_s32): Likewise.
8146 (vsubq_m_n_s16): Likewise.
8147 (vsubq_m_n_u8): Likewise.
8148 (vsubq_m_n_u32): Likewise.
8149 (vsubq_m_n_u16): Likewise.
8150 (__arm_vabdq_m_s8): Define intrinsic.
8151 (__arm_vabdq_m_s32): Likewise.
8152 (__arm_vabdq_m_s16): Likewise.
8153 (__arm_vabdq_m_u8): Likewise.
8154 (__arm_vabdq_m_u32): Likewise.
8155 (__arm_vabdq_m_u16): Likewise.
8156 (__arm_vaddq_m_n_s8): Likewise.
8157 (__arm_vaddq_m_n_s32): Likewise.
8158 (__arm_vaddq_m_n_s16): Likewise.
8159 (__arm_vaddq_m_n_u8): Likewise.
8160 (__arm_vaddq_m_n_u32): Likewise.
8161 (__arm_vaddq_m_n_u16): Likewise.
8162 (__arm_vaddq_m_s8): Likewise.
8163 (__arm_vaddq_m_s32): Likewise.
8164 (__arm_vaddq_m_s16): Likewise.
8165 (__arm_vaddq_m_u8): Likewise.
8166 (__arm_vaddq_m_u32): Likewise.
8167 (__arm_vaddq_m_u16): Likewise.
8168 (__arm_vandq_m_s8): Likewise.
8169 (__arm_vandq_m_s32): Likewise.
8170 (__arm_vandq_m_s16): Likewise.
8171 (__arm_vandq_m_u8): Likewise.
8172 (__arm_vandq_m_u32): Likewise.
8173 (__arm_vandq_m_u16): Likewise.
8174 (__arm_vbicq_m_s8): Likewise.
8175 (__arm_vbicq_m_s32): Likewise.
8176 (__arm_vbicq_m_s16): Likewise.
8177 (__arm_vbicq_m_u8): Likewise.
8178 (__arm_vbicq_m_u32): Likewise.
8179 (__arm_vbicq_m_u16): Likewise.
8180 (__arm_vbrsrq_m_n_s8): Likewise.
8181 (__arm_vbrsrq_m_n_s32): Likewise.
8182 (__arm_vbrsrq_m_n_s16): Likewise.
8183 (__arm_vbrsrq_m_n_u8): Likewise.
8184 (__arm_vbrsrq_m_n_u32): Likewise.
8185 (__arm_vbrsrq_m_n_u16): Likewise.
8186 (__arm_vcaddq_rot270_m_s8): Likewise.
8187 (__arm_vcaddq_rot270_m_s32): Likewise.
8188 (__arm_vcaddq_rot270_m_s16): Likewise.
8189 (__arm_vcaddq_rot270_m_u8): Likewise.
8190 (__arm_vcaddq_rot270_m_u32): Likewise.
8191 (__arm_vcaddq_rot270_m_u16): Likewise.
8192 (__arm_vcaddq_rot90_m_s8): Likewise.
8193 (__arm_vcaddq_rot90_m_s32): Likewise.
8194 (__arm_vcaddq_rot90_m_s16): Likewise.
8195 (__arm_vcaddq_rot90_m_u8): Likewise.
8196 (__arm_vcaddq_rot90_m_u32): Likewise.
8197 (__arm_vcaddq_rot90_m_u16): Likewise.
8198 (__arm_veorq_m_s8): Likewise.
8199 (__arm_veorq_m_s32): Likewise.
8200 (__arm_veorq_m_s16): Likewise.
8201 (__arm_veorq_m_u8): Likewise.
8202 (__arm_veorq_m_u32): Likewise.
8203 (__arm_veorq_m_u16): Likewise.
8204 (__arm_vhaddq_m_n_s8): Likewise.
8205 (__arm_vhaddq_m_n_s32): Likewise.
8206 (__arm_vhaddq_m_n_s16): Likewise.
8207 (__arm_vhaddq_m_n_u8): Likewise.
8208 (__arm_vhaddq_m_n_u32): Likewise.
8209 (__arm_vhaddq_m_n_u16): Likewise.
8210 (__arm_vhaddq_m_s8): Likewise.
8211 (__arm_vhaddq_m_s32): Likewise.
8212 (__arm_vhaddq_m_s16): Likewise.
8213 (__arm_vhaddq_m_u8): Likewise.
8214 (__arm_vhaddq_m_u32): Likewise.
8215 (__arm_vhaddq_m_u16): Likewise.
8216 (__arm_vhcaddq_rot270_m_s8): Likewise.
8217 (__arm_vhcaddq_rot270_m_s32): Likewise.
8218 (__arm_vhcaddq_rot270_m_s16): Likewise.
8219 (__arm_vhcaddq_rot90_m_s8): Likewise.
8220 (__arm_vhcaddq_rot90_m_s32): Likewise.
8221 (__arm_vhcaddq_rot90_m_s16): Likewise.
8222 (__arm_vhsubq_m_n_s8): Likewise.
8223 (__arm_vhsubq_m_n_s32): Likewise.
8224 (__arm_vhsubq_m_n_s16): Likewise.
8225 (__arm_vhsubq_m_n_u8): Likewise.
8226 (__arm_vhsubq_m_n_u32): Likewise.
8227 (__arm_vhsubq_m_n_u16): Likewise.
8228 (__arm_vhsubq_m_s8): Likewise.
8229 (__arm_vhsubq_m_s32): Likewise.
8230 (__arm_vhsubq_m_s16): Likewise.
8231 (__arm_vhsubq_m_u8): Likewise.
8232 (__arm_vhsubq_m_u32): Likewise.
8233 (__arm_vhsubq_m_u16): Likewise.
8234 (__arm_vmaxq_m_s8): Likewise.
8235 (__arm_vmaxq_m_s32): Likewise.
8236 (__arm_vmaxq_m_s16): Likewise.
8237 (__arm_vmaxq_m_u8): Likewise.
8238 (__arm_vmaxq_m_u32): Likewise.
8239 (__arm_vmaxq_m_u16): Likewise.
8240 (__arm_vminq_m_s8): Likewise.
8241 (__arm_vminq_m_s32): Likewise.
8242 (__arm_vminq_m_s16): Likewise.
8243 (__arm_vminq_m_u8): Likewise.
8244 (__arm_vminq_m_u32): Likewise.
8245 (__arm_vminq_m_u16): Likewise.
8246 (__arm_vmladavaq_p_s8): Likewise.
8247 (__arm_vmladavaq_p_s32): Likewise.
8248 (__arm_vmladavaq_p_s16): Likewise.
8249 (__arm_vmladavaq_p_u8): Likewise.
8250 (__arm_vmladavaq_p_u32): Likewise.
8251 (__arm_vmladavaq_p_u16): Likewise.
8252 (__arm_vmladavaxq_p_s8): Likewise.
8253 (__arm_vmladavaxq_p_s32): Likewise.
8254 (__arm_vmladavaxq_p_s16): Likewise.
8255 (__arm_vmlaq_m_n_s8): Likewise.
8256 (__arm_vmlaq_m_n_s32): Likewise.
8257 (__arm_vmlaq_m_n_s16): Likewise.
8258 (__arm_vmlaq_m_n_u8): Likewise.
8259 (__arm_vmlaq_m_n_u32): Likewise.
8260 (__arm_vmlaq_m_n_u16): Likewise.
8261 (__arm_vmlasq_m_n_s8): Likewise.
8262 (__arm_vmlasq_m_n_s32): Likewise.
8263 (__arm_vmlasq_m_n_s16): Likewise.
8264 (__arm_vmlasq_m_n_u8): Likewise.
8265 (__arm_vmlasq_m_n_u32): Likewise.
8266 (__arm_vmlasq_m_n_u16): Likewise.
8267 (__arm_vmlsdavaq_p_s8): Likewise.
8268 (__arm_vmlsdavaq_p_s32): Likewise.
8269 (__arm_vmlsdavaq_p_s16): Likewise.
8270 (__arm_vmlsdavaxq_p_s8): Likewise.
8271 (__arm_vmlsdavaxq_p_s32): Likewise.
8272 (__arm_vmlsdavaxq_p_s16): Likewise.
8273 (__arm_vmulhq_m_s8): Likewise.
8274 (__arm_vmulhq_m_s32): Likewise.
8275 (__arm_vmulhq_m_s16): Likewise.
8276 (__arm_vmulhq_m_u8): Likewise.
8277 (__arm_vmulhq_m_u32): Likewise.
8278 (__arm_vmulhq_m_u16): Likewise.
8279 (__arm_vmullbq_int_m_s8): Likewise.
8280 (__arm_vmullbq_int_m_s32): Likewise.
8281 (__arm_vmullbq_int_m_s16): Likewise.
8282 (__arm_vmullbq_int_m_u8): Likewise.
8283 (__arm_vmullbq_int_m_u32): Likewise.
8284 (__arm_vmullbq_int_m_u16): Likewise.
8285 (__arm_vmulltq_int_m_s8): Likewise.
8286 (__arm_vmulltq_int_m_s32): Likewise.
8287 (__arm_vmulltq_int_m_s16): Likewise.
8288 (__arm_vmulltq_int_m_u8): Likewise.
8289 (__arm_vmulltq_int_m_u32): Likewise.
8290 (__arm_vmulltq_int_m_u16): Likewise.
8291 (__arm_vmulq_m_n_s8): Likewise.
8292 (__arm_vmulq_m_n_s32): Likewise.
8293 (__arm_vmulq_m_n_s16): Likewise.
8294 (__arm_vmulq_m_n_u8): Likewise.
8295 (__arm_vmulq_m_n_u32): Likewise.
8296 (__arm_vmulq_m_n_u16): Likewise.
8297 (__arm_vmulq_m_s8): Likewise.
8298 (__arm_vmulq_m_s32): Likewise.
8299 (__arm_vmulq_m_s16): Likewise.
8300 (__arm_vmulq_m_u8): Likewise.
8301 (__arm_vmulq_m_u32): Likewise.
8302 (__arm_vmulq_m_u16): Likewise.
8303 (__arm_vornq_m_s8): Likewise.
8304 (__arm_vornq_m_s32): Likewise.
8305 (__arm_vornq_m_s16): Likewise.
8306 (__arm_vornq_m_u8): Likewise.
8307 (__arm_vornq_m_u32): Likewise.
8308 (__arm_vornq_m_u16): Likewise.
8309 (__arm_vorrq_m_s8): Likewise.
8310 (__arm_vorrq_m_s32): Likewise.
8311 (__arm_vorrq_m_s16): Likewise.
8312 (__arm_vorrq_m_u8): Likewise.
8313 (__arm_vorrq_m_u32): Likewise.
8314 (__arm_vorrq_m_u16): Likewise.
8315 (__arm_vqaddq_m_n_s8): Likewise.
8316 (__arm_vqaddq_m_n_s32): Likewise.
8317 (__arm_vqaddq_m_n_s16): Likewise.
8318 (__arm_vqaddq_m_n_u8): Likewise.
8319 (__arm_vqaddq_m_n_u32): Likewise.
8320 (__arm_vqaddq_m_n_u16): Likewise.
8321 (__arm_vqaddq_m_s8): Likewise.
8322 (__arm_vqaddq_m_s32): Likewise.
8323 (__arm_vqaddq_m_s16): Likewise.
8324 (__arm_vqaddq_m_u8): Likewise.
8325 (__arm_vqaddq_m_u32): Likewise.
8326 (__arm_vqaddq_m_u16): Likewise.
8327 (__arm_vqdmladhq_m_s8): Likewise.
8328 (__arm_vqdmladhq_m_s32): Likewise.
8329 (__arm_vqdmladhq_m_s16): Likewise.
8330 (__arm_vqdmladhxq_m_s8): Likewise.
8331 (__arm_vqdmladhxq_m_s32): Likewise.
8332 (__arm_vqdmladhxq_m_s16): Likewise.
8333 (__arm_vqdmlahq_m_n_s8): Likewise.
8334 (__arm_vqdmlahq_m_n_s32): Likewise.
8335 (__arm_vqdmlahq_m_n_s16): Likewise.
8336 (__arm_vqdmlahq_m_n_u8): Likewise.
8337 (__arm_vqdmlahq_m_n_u32): Likewise.
8338 (__arm_vqdmlahq_m_n_u16): Likewise.
8339 (__arm_vqdmlsdhq_m_s8): Likewise.
8340 (__arm_vqdmlsdhq_m_s32): Likewise.
8341 (__arm_vqdmlsdhq_m_s16): Likewise.
8342 (__arm_vqdmlsdhxq_m_s8): Likewise.
8343 (__arm_vqdmlsdhxq_m_s32): Likewise.
8344 (__arm_vqdmlsdhxq_m_s16): Likewise.
8345 (__arm_vqdmulhq_m_n_s8): Likewise.
8346 (__arm_vqdmulhq_m_n_s32): Likewise.
8347 (__arm_vqdmulhq_m_n_s16): Likewise.
8348 (__arm_vqdmulhq_m_s8): Likewise.
8349 (__arm_vqdmulhq_m_s32): Likewise.
8350 (__arm_vqdmulhq_m_s16): Likewise.
8351 (__arm_vqrdmladhq_m_s8): Likewise.
8352 (__arm_vqrdmladhq_m_s32): Likewise.
8353 (__arm_vqrdmladhq_m_s16): Likewise.
8354 (__arm_vqrdmladhxq_m_s8): Likewise.
8355 (__arm_vqrdmladhxq_m_s32): Likewise.
8356 (__arm_vqrdmladhxq_m_s16): Likewise.
8357 (__arm_vqrdmlahq_m_n_s8): Likewise.
8358 (__arm_vqrdmlahq_m_n_s32): Likewise.
8359 (__arm_vqrdmlahq_m_n_s16): Likewise.
8360 (__arm_vqrdmlahq_m_n_u8): Likewise.
8361 (__arm_vqrdmlahq_m_n_u32): Likewise.
8362 (__arm_vqrdmlahq_m_n_u16): Likewise.
8363 (__arm_vqrdmlashq_m_n_s8): Likewise.
8364 (__arm_vqrdmlashq_m_n_s32): Likewise.
8365 (__arm_vqrdmlashq_m_n_s16): Likewise.
8366 (__arm_vqrdmlashq_m_n_u8): Likewise.
8367 (__arm_vqrdmlashq_m_n_u32): Likewise.
8368 (__arm_vqrdmlashq_m_n_u16): Likewise.
8369 (__arm_vqrdmlsdhq_m_s8): Likewise.
8370 (__arm_vqrdmlsdhq_m_s32): Likewise.
8371 (__arm_vqrdmlsdhq_m_s16): Likewise.
8372 (__arm_vqrdmlsdhxq_m_s8): Likewise.
8373 (__arm_vqrdmlsdhxq_m_s32): Likewise.
8374 (__arm_vqrdmlsdhxq_m_s16): Likewise.
8375 (__arm_vqrdmulhq_m_n_s8): Likewise.
8376 (__arm_vqrdmulhq_m_n_s32): Likewise.
8377 (__arm_vqrdmulhq_m_n_s16): Likewise.
8378 (__arm_vqrdmulhq_m_s8): Likewise.
8379 (__arm_vqrdmulhq_m_s32): Likewise.
8380 (__arm_vqrdmulhq_m_s16): Likewise.
8381 (__arm_vqrshlq_m_s8): Likewise.
8382 (__arm_vqrshlq_m_s32): Likewise.
8383 (__arm_vqrshlq_m_s16): Likewise.
8384 (__arm_vqrshlq_m_u8): Likewise.
8385 (__arm_vqrshlq_m_u32): Likewise.
8386 (__arm_vqrshlq_m_u16): Likewise.
8387 (__arm_vqshlq_m_n_s8): Likewise.
8388 (__arm_vqshlq_m_n_s32): Likewise.
8389 (__arm_vqshlq_m_n_s16): Likewise.
8390 (__arm_vqshlq_m_n_u8): Likewise.
8391 (__arm_vqshlq_m_n_u32): Likewise.
8392 (__arm_vqshlq_m_n_u16): Likewise.
8393 (__arm_vqshlq_m_s8): Likewise.
8394 (__arm_vqshlq_m_s32): Likewise.
8395 (__arm_vqshlq_m_s16): Likewise.
8396 (__arm_vqshlq_m_u8): Likewise.
8397 (__arm_vqshlq_m_u32): Likewise.
8398 (__arm_vqshlq_m_u16): Likewise.
8399 (__arm_vqsubq_m_n_s8): Likewise.
8400 (__arm_vqsubq_m_n_s32): Likewise.
8401 (__arm_vqsubq_m_n_s16): Likewise.
8402 (__arm_vqsubq_m_n_u8): Likewise.
8403 (__arm_vqsubq_m_n_u32): Likewise.
8404 (__arm_vqsubq_m_n_u16): Likewise.
8405 (__arm_vqsubq_m_s8): Likewise.
8406 (__arm_vqsubq_m_s32): Likewise.
8407 (__arm_vqsubq_m_s16): Likewise.
8408 (__arm_vqsubq_m_u8): Likewise.
8409 (__arm_vqsubq_m_u32): Likewise.
8410 (__arm_vqsubq_m_u16): Likewise.
8411 (__arm_vrhaddq_m_s8): Likewise.
8412 (__arm_vrhaddq_m_s32): Likewise.
8413 (__arm_vrhaddq_m_s16): Likewise.
8414 (__arm_vrhaddq_m_u8): Likewise.
8415 (__arm_vrhaddq_m_u32): Likewise.
8416 (__arm_vrhaddq_m_u16): Likewise.
8417 (__arm_vrmulhq_m_s8): Likewise.
8418 (__arm_vrmulhq_m_s32): Likewise.
8419 (__arm_vrmulhq_m_s16): Likewise.
8420 (__arm_vrmulhq_m_u8): Likewise.
8421 (__arm_vrmulhq_m_u32): Likewise.
8422 (__arm_vrmulhq_m_u16): Likewise.
8423 (__arm_vrshlq_m_s8): Likewise.
8424 (__arm_vrshlq_m_s32): Likewise.
8425 (__arm_vrshlq_m_s16): Likewise.
8426 (__arm_vrshlq_m_u8): Likewise.
8427 (__arm_vrshlq_m_u32): Likewise.
8428 (__arm_vrshlq_m_u16): Likewise.
8429 (__arm_vrshrq_m_n_s8): Likewise.
8430 (__arm_vrshrq_m_n_s32): Likewise.
8431 (__arm_vrshrq_m_n_s16): Likewise.
8432 (__arm_vrshrq_m_n_u8): Likewise.
8433 (__arm_vrshrq_m_n_u32): Likewise.
8434 (__arm_vrshrq_m_n_u16): Likewise.
8435 (__arm_vshlq_m_n_s8): Likewise.
8436 (__arm_vshlq_m_n_s32): Likewise.
8437 (__arm_vshlq_m_n_s16): Likewise.
8438 (__arm_vshlq_m_n_u8): Likewise.
8439 (__arm_vshlq_m_n_u32): Likewise.
8440 (__arm_vshlq_m_n_u16): Likewise.
8441 (__arm_vshrq_m_n_s8): Likewise.
8442 (__arm_vshrq_m_n_s32): Likewise.
8443 (__arm_vshrq_m_n_s16): Likewise.
8444 (__arm_vshrq_m_n_u8): Likewise.
8445 (__arm_vshrq_m_n_u32): Likewise.
8446 (__arm_vshrq_m_n_u16): Likewise.
8447 (__arm_vsliq_m_n_s8): Likewise.
8448 (__arm_vsliq_m_n_s32): Likewise.
8449 (__arm_vsliq_m_n_s16): Likewise.
8450 (__arm_vsliq_m_n_u8): Likewise.
8451 (__arm_vsliq_m_n_u32): Likewise.
8452 (__arm_vsliq_m_n_u16): Likewise.
8453 (__arm_vsubq_m_n_s8): Likewise.
8454 (__arm_vsubq_m_n_s32): Likewise.
8455 (__arm_vsubq_m_n_s16): Likewise.
8456 (__arm_vsubq_m_n_u8): Likewise.
8457 (__arm_vsubq_m_n_u32): Likewise.
8458 (__arm_vsubq_m_n_u16): Likewise.
8459 (vqdmladhq_m): Define polymorphic variant.
8460 (vqdmladhxq_m): Likewise.
8461 (vqdmlsdhq_m): Likewise.
8462 (vqdmlsdhxq_m): Likewise.
8463 (vabdq_m): Likewise.
8464 (vandq_m): Likewise.
8465 (vbicq_m): Likewise.
8466 (vbrsrq_m_n): Likewise.
8467 (vcaddq_rot270_m): Likewise.
8468 (vcaddq_rot90_m): Likewise.
8469 (veorq_m): Likewise.
8470 (vmaxq_m): Likewise.
8471 (vminq_m): Likewise.
8472 (vmladavaq_p): Likewise.
8473 (vmlaq_m_n): Likewise.
8474 (vmlasq_m_n): Likewise.
8475 (vmulhq_m): Likewise.
8476 (vmullbq_int_m): Likewise.
8477 (vmulltq_int_m): Likewise.
8478 (vornq_m): Likewise.
8479 (vorrq_m): Likewise.
8480 (vqdmlahq_m_n): Likewise.
8481 (vqrdmlahq_m_n): Likewise.
8482 (vqrdmlashq_m_n): Likewise.
8483 (vqrshlq_m): Likewise.
8484 (vqshlq_m_n): Likewise.
8485 (vqshlq_m): Likewise.
8486 (vrhaddq_m): Likewise.
8487 (vrmulhq_m): Likewise.
8488 (vrshlq_m): Likewise.
8489 (vrshrq_m_n): Likewise.
8490 (vshlq_m_n): Likewise.
8491 (vshrq_m_n): Likewise.
8492 (vsliq_m): Likewise.
8493 (vaddq_m_n): Likewise.
8494 (vaddq_m): Likewise.
8495 (vhaddq_m_n): Likewise.
8496 (vhaddq_m): Likewise.
8497 (vhcaddq_rot270_m): Likewise.
8498 (vhcaddq_rot90_m): Likewise.
8499 (vhsubq_m): Likewise.
8500 (vhsubq_m_n): Likewise.
8501 (vmulq_m_n): Likewise.
8502 (vmulq_m): Likewise.
8503 (vqaddq_m_n): Likewise.
8504 (vqaddq_m): Likewise.
8505 (vqdmulhq_m_n): Likewise.
8506 (vqdmulhq_m): Likewise.
8507 (vsubq_m_n): Likewise.
8508 (vsliq_m_n): Likewise.
8509 (vqsubq_m_n): Likewise.
8510 (vqsubq_m): Likewise.
8511 (vqrdmulhq_m): Likewise.
8512 (vqrdmulhq_m_n): Likewise.
8513 (vqrdmlsdhxq_m): Likewise.
8514 (vqrdmlsdhq_m): Likewise.
8515 (vqrdmladhq_m): Likewise.
8516 (vqrdmladhxq_m): Likewise.
8517 (vmlsdavaxq_p): Likewise.
8518 (vmlsdavaq_p): Likewise.
8519 (vmladavaxq_p): Likewise.
8520 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
8522 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
8523 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
8524 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
8525 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
8526 * config/arm/mve.md (VHSUBQ_M): Define iterators.
8527 (VSLIQ_M_N): Likewise.
8528 (VQRDMLAHQ_M_N): Likewise.
8529 (VRSHLQ_M): Likewise.
8530 (VMINQ_M): Likewise.
8531 (VMULLBQ_INT_M): Likewise.
8532 (VMULHQ_M): Likewise.
8533 (VMULQ_M): Likewise.
8534 (VHSUBQ_M_N): Likewise.
8535 (VHADDQ_M_N): Likewise.
8536 (VORRQ_M): Likewise.
8537 (VRMULHQ_M): Likewise.
8538 (VQADDQ_M): Likewise.
8539 (VRSHRQ_M_N): Likewise.
8540 (VQSUBQ_M_N): Likewise.
8541 (VADDQ_M): Likewise.
8542 (VORNQ_M): Likewise.
8543 (VQDMLAHQ_M_N): Likewise.
8544 (VRHADDQ_M): Likewise.
8545 (VQSHLQ_M): Likewise.
8546 (VANDQ_M): Likewise.
8547 (VBICQ_M): Likewise.
8548 (VSHLQ_M_N): Likewise.
8549 (VCADDQ_ROT270_M): Likewise.
8550 (VQRSHLQ_M): Likewise.
8551 (VQADDQ_M_N): Likewise.
8552 (VADDQ_M_N): Likewise.
8553 (VMAXQ_M): Likewise.
8554 (VQSUBQ_M): Likewise.
8555 (VMLASQ_M_N): Likewise.
8556 (VMLADAVAQ_P): Likewise.
8557 (VBRSRQ_M_N): Likewise.
8558 (VMULQ_M_N): Likewise.
8559 (VCADDQ_ROT90_M): Likewise.
8560 (VMULLTQ_INT_M): Likewise.
8561 (VEORQ_M): Likewise.
8562 (VSHRQ_M_N): Likewise.
8563 (VSUBQ_M_N): Likewise.
8564 (VHADDQ_M): Likewise.
8565 (VABDQ_M): Likewise.
8566 (VQRDMLASHQ_M_N): Likewise.
8567 (VMLAQ_M_N): Likewise.
8568 (VQSHLQ_M_N): Likewise.
8569 (mve_vabdq_m_<supf><mode>): Define RTL pattern.
8570 (mve_vaddq_m_n_<supf><mode>): Likewise.
8571 (mve_vaddq_m_<supf><mode>): Likewise.
8572 (mve_vandq_m_<supf><mode>): Likewise.
8573 (mve_vbicq_m_<supf><mode>): Likewise.
8574 (mve_vbrsrq_m_n_<supf><mode>): Likewise.
8575 (mve_vcaddq_rot270_m_<supf><mode>): Likewise.
8576 (mve_vcaddq_rot90_m_<supf><mode>): Likewise.
8577 (mve_veorq_m_<supf><mode>): Likewise.
8578 (mve_vhaddq_m_n_<supf><mode>): Likewise.
8579 (mve_vhaddq_m_<supf><mode>): Likewise.
8580 (mve_vhsubq_m_n_<supf><mode>): Likewise.
8581 (mve_vhsubq_m_<supf><mode>): Likewise.
8582 (mve_vmaxq_m_<supf><mode>): Likewise.
8583 (mve_vminq_m_<supf><mode>): Likewise.
8584 (mve_vmladavaq_p_<supf><mode>): Likewise.
8585 (mve_vmlaq_m_n_<supf><mode>): Likewise.
8586 (mve_vmlasq_m_n_<supf><mode>): Likewise.
8587 (mve_vmulhq_m_<supf><mode>): Likewise.
8588 (mve_vmullbq_int_m_<supf><mode>): Likewise.
8589 (mve_vmulltq_int_m_<supf><mode>): Likewise.
8590 (mve_vmulq_m_n_<supf><mode>): Likewise.
8591 (mve_vmulq_m_<supf><mode>): Likewise.
8592 (mve_vornq_m_<supf><mode>): Likewise.
8593 (mve_vorrq_m_<supf><mode>): Likewise.
8594 (mve_vqaddq_m_n_<supf><mode>): Likewise.
8595 (mve_vqaddq_m_<supf><mode>): Likewise.
8596 (mve_vqdmlahq_m_n_<supf><mode>): Likewise.
8597 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
8598 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
8599 (mve_vqrshlq_m_<supf><mode>): Likewise.
8600 (mve_vqshlq_m_n_<supf><mode>): Likewise.
8601 (mve_vqshlq_m_<supf><mode>): Likewise.
8602 (mve_vqsubq_m_n_<supf><mode>): Likewise.
8603 (mve_vqsubq_m_<supf><mode>): Likewise.
8604 (mve_vrhaddq_m_<supf><mode>): Likewise.
8605 (mve_vrmulhq_m_<supf><mode>): Likewise.
8606 (mve_vrshlq_m_<supf><mode>): Likewise.
8607 (mve_vrshrq_m_n_<supf><mode>): Likewise.
8608 (mve_vshlq_m_n_<supf><mode>): Likewise.
8609 (mve_vshrq_m_n_<supf><mode>): Likewise.
8610 (mve_vsliq_m_n_<supf><mode>): Likewise.
8611 (mve_vsubq_m_n_<supf><mode>): Likewise.
8612 (mve_vhcaddq_rot270_m_s<mode>): Likewise.
8613 (mve_vhcaddq_rot90_m_s<mode>): Likewise.
8614 (mve_vmladavaxq_p_s<mode>): Likewise.
8615 (mve_vmlsdavaq_p_s<mode>): Likewise.
8616 (mve_vmlsdavaxq_p_s<mode>): Likewise.
8617 (mve_vqdmladhq_m_s<mode>): Likewise.
8618 (mve_vqdmladhxq_m_s<mode>): Likewise.
8619 (mve_vqdmlsdhq_m_s<mode>): Likewise.
8620 (mve_vqdmlsdhxq_m_s<mode>): Likewise.
8621 (mve_vqdmulhq_m_n_s<mode>): Likewise.
8622 (mve_vqdmulhq_m_s<mode>): Likewise.
8623 (mve_vqrdmladhq_m_s<mode>): Likewise.
8624 (mve_vqrdmladhxq_m_s<mode>): Likewise.
8625 (mve_vqrdmlsdhq_m_s<mode>): Likewise.
8626 (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
8627 (mve_vqrdmulhq_m_n_s<mode>): Likewise.
8628 (mve_vqrdmulhq_m_s<mode>): Likewise.
8630 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8631 Mihail Ionescu <mihail.ionescu@arm.com>
8632 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8634 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
8635 Define builtin qualifier.
8636 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
8637 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8638 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8639 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8640 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8641 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8642 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
8643 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
8644 (vsubq_m_s8): Likewise.
8645 (vcvtq_m_n_f16_u16): Likewise.
8646 (vqshluq_m_n_s8): Likewise.
8647 (vabavq_p_s8): Likewise.
8648 (vsriq_m_n_u8): Likewise.
8649 (vshlq_m_u8): Likewise.
8650 (vsubq_m_u8): Likewise.
8651 (vabavq_p_u8): Likewise.
8652 (vshlq_m_s8): Likewise.
8653 (vcvtq_m_n_f16_s16): Likewise.
8654 (vsriq_m_n_s16): Likewise.
8655 (vsubq_m_s16): Likewise.
8656 (vcvtq_m_n_f32_u32): Likewise.
8657 (vqshluq_m_n_s16): Likewise.
8658 (vabavq_p_s16): Likewise.
8659 (vsriq_m_n_u16): Likewise.
8660 (vshlq_m_u16): Likewise.
8661 (vsubq_m_u16): Likewise.
8662 (vabavq_p_u16): Likewise.
8663 (vshlq_m_s16): Likewise.
8664 (vcvtq_m_n_f32_s32): Likewise.
8665 (vsriq_m_n_s32): Likewise.
8666 (vsubq_m_s32): Likewise.
8667 (vqshluq_m_n_s32): Likewise.
8668 (vabavq_p_s32): Likewise.
8669 (vsriq_m_n_u32): Likewise.
8670 (vshlq_m_u32): Likewise.
8671 (vsubq_m_u32): Likewise.
8672 (vabavq_p_u32): Likewise.
8673 (vshlq_m_s32): Likewise.
8674 (__arm_vsriq_m_n_s8): Define intrinsic.
8675 (__arm_vsubq_m_s8): Likewise.
8676 (__arm_vqshluq_m_n_s8): Likewise.
8677 (__arm_vabavq_p_s8): Likewise.
8678 (__arm_vsriq_m_n_u8): Likewise.
8679 (__arm_vshlq_m_u8): Likewise.
8680 (__arm_vsubq_m_u8): Likewise.
8681 (__arm_vabavq_p_u8): Likewise.
8682 (__arm_vshlq_m_s8): Likewise.
8683 (__arm_vsriq_m_n_s16): Likewise.
8684 (__arm_vsubq_m_s16): Likewise.
8685 (__arm_vqshluq_m_n_s16): Likewise.
8686 (__arm_vabavq_p_s16): Likewise.
8687 (__arm_vsriq_m_n_u16): Likewise.
8688 (__arm_vshlq_m_u16): Likewise.
8689 (__arm_vsubq_m_u16): Likewise.
8690 (__arm_vabavq_p_u16): Likewise.
8691 (__arm_vshlq_m_s16): Likewise.
8692 (__arm_vsriq_m_n_s32): Likewise.
8693 (__arm_vsubq_m_s32): Likewise.
8694 (__arm_vqshluq_m_n_s32): Likewise.
8695 (__arm_vabavq_p_s32): Likewise.
8696 (__arm_vsriq_m_n_u32): Likewise.
8697 (__arm_vshlq_m_u32): Likewise.
8698 (__arm_vsubq_m_u32): Likewise.
8699 (__arm_vabavq_p_u32): Likewise.
8700 (__arm_vshlq_m_s32): Likewise.
8701 (__arm_vcvtq_m_n_f16_u16): Likewise.
8702 (__arm_vcvtq_m_n_f16_s16): Likewise.
8703 (__arm_vcvtq_m_n_f32_u32): Likewise.
8704 (__arm_vcvtq_m_n_f32_s32): Likewise.
8705 (vcvtq_m_n): Define polymorphic variant.
8706 (vqshluq_m_n): Likewise.
8707 (vshlq_m): Likewise.
8708 (vsriq_m_n): Likewise.
8709 (vsubq_m): Likewise.
8710 (vabavq_p): Likewise.
8711 * config/arm/arm_mve_builtins.def
8712 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
8713 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
8714 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8715 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8716 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8717 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8718 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8719 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
8720 * config/arm/mve.md (VABAVQ_P): Define iterator.
8721 (VSHLQ_M): Likewise.
8722 (VSRIQ_M_N): Likewise.
8723 (VSUBQ_M): Likewise.
8724 (VCVTQ_M_N_TO_F): Likewise.
8725 (mve_vabavq_p_<supf><mode>): Define RTL pattern.
8726 (mve_vqshluq_m_n_s<mode>): Likewise.
8727 (mve_vshlq_m_<supf><mode>): Likewise.
8728 (mve_vsriq_m_n_<supf><mode>): Likewise.
8729 (mve_vsubq_m_<supf><mode>): Likewise.
8730 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
8732 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8733 Mihail Ionescu <mihail.ionescu@arm.com>
8734 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8736 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
8737 (vrmlsldavhaq_s32): Likewise.
8738 (vrmlsldavhaxq_s32): Likewise.
8739 (vaddlvaq_p_s32): Likewise.
8740 (vcvtbq_m_f16_f32): Likewise.
8741 (vcvtbq_m_f32_f16): Likewise.
8742 (vcvttq_m_f16_f32): Likewise.
8743 (vcvttq_m_f32_f16): Likewise.
8744 (vrev16q_m_s8): Likewise.
8745 (vrev32q_m_f16): Likewise.
8746 (vrmlaldavhq_p_s32): Likewise.
8747 (vrmlaldavhxq_p_s32): Likewise.
8748 (vrmlsldavhq_p_s32): Likewise.
8749 (vrmlsldavhxq_p_s32): Likewise.
8750 (vaddlvaq_p_u32): Likewise.
8751 (vrev16q_m_u8): Likewise.
8752 (vrmlaldavhq_p_u32): Likewise.
8753 (vmvnq_m_n_s16): Likewise.
8754 (vorrq_m_n_s16): Likewise.
8755 (vqrshrntq_n_s16): Likewise.
8756 (vqshrnbq_n_s16): Likewise.
8757 (vqshrntq_n_s16): Likewise.
8758 (vrshrnbq_n_s16): Likewise.
8759 (vrshrntq_n_s16): Likewise.
8760 (vshrnbq_n_s16): Likewise.
8761 (vshrntq_n_s16): Likewise.
8762 (vcmlaq_f16): Likewise.
8763 (vcmlaq_rot180_f16): Likewise.
8764 (vcmlaq_rot270_f16): Likewise.
8765 (vcmlaq_rot90_f16): Likewise.
8766 (vfmaq_f16): Likewise.
8767 (vfmaq_n_f16): Likewise.
8768 (vfmasq_n_f16): Likewise.
8769 (vfmsq_f16): Likewise.
8770 (vmlaldavaq_s16): Likewise.
8771 (vmlaldavaxq_s16): Likewise.
8772 (vmlsldavaq_s16): Likewise.
8773 (vmlsldavaxq_s16): Likewise.
8774 (vabsq_m_f16): Likewise.
8775 (vcvtmq_m_s16_f16): Likewise.
8776 (vcvtnq_m_s16_f16): Likewise.
8777 (vcvtpq_m_s16_f16): Likewise.
8778 (vcvtq_m_s16_f16): Likewise.
8779 (vdupq_m_n_f16): Likewise.
8780 (vmaxnmaq_m_f16): Likewise.
8781 (vmaxnmavq_p_f16): Likewise.
8782 (vmaxnmvq_p_f16): Likewise.
8783 (vminnmaq_m_f16): Likewise.
8784 (vminnmavq_p_f16): Likewise.
8785 (vminnmvq_p_f16): Likewise.
8786 (vmlaldavq_p_s16): Likewise.
8787 (vmlaldavxq_p_s16): Likewise.
8788 (vmlsldavq_p_s16): Likewise.
8789 (vmlsldavxq_p_s16): Likewise.
8790 (vmovlbq_m_s8): Likewise.
8791 (vmovltq_m_s8): Likewise.
8792 (vmovnbq_m_s16): Likewise.
8793 (vmovntq_m_s16): Likewise.
8794 (vnegq_m_f16): Likewise.
8795 (vpselq_f16): Likewise.
8796 (vqmovnbq_m_s16): Likewise.
8797 (vqmovntq_m_s16): Likewise.
8798 (vrev32q_m_s8): Likewise.
8799 (vrev64q_m_f16): Likewise.
8800 (vrndaq_m_f16): Likewise.
8801 (vrndmq_m_f16): Likewise.
8802 (vrndnq_m_f16): Likewise.
8803 (vrndpq_m_f16): Likewise.
8804 (vrndq_m_f16): Likewise.
8805 (vrndxq_m_f16): Likewise.
8806 (vcmpeqq_m_n_f16): Likewise.
8807 (vcmpgeq_m_f16): Likewise.
8808 (vcmpgeq_m_n_f16): Likewise.
8809 (vcmpgtq_m_f16): Likewise.
8810 (vcmpgtq_m_n_f16): Likewise.
8811 (vcmpleq_m_f16): Likewise.
8812 (vcmpleq_m_n_f16): Likewise.
8813 (vcmpltq_m_f16): Likewise.
8814 (vcmpltq_m_n_f16): Likewise.
8815 (vcmpneq_m_f16): Likewise.
8816 (vcmpneq_m_n_f16): Likewise.
8817 (vmvnq_m_n_u16): Likewise.
8818 (vorrq_m_n_u16): Likewise.
8819 (vqrshruntq_n_s16): Likewise.
8820 (vqshrunbq_n_s16): Likewise.
8821 (vqshruntq_n_s16): Likewise.
8822 (vcvtmq_m_u16_f16): Likewise.
8823 (vcvtnq_m_u16_f16): Likewise.
8824 (vcvtpq_m_u16_f16): Likewise.
8825 (vcvtq_m_u16_f16): Likewise.
8826 (vqmovunbq_m_s16): Likewise.
8827 (vqmovuntq_m_s16): Likewise.
8828 (vqrshrntq_n_u16): Likewise.
8829 (vqshrnbq_n_u16): Likewise.
8830 (vqshrntq_n_u16): Likewise.
8831 (vrshrnbq_n_u16): Likewise.
8832 (vrshrntq_n_u16): Likewise.
8833 (vshrnbq_n_u16): Likewise.
8834 (vshrntq_n_u16): Likewise.
8835 (vmlaldavaq_u16): Likewise.
8836 (vmlaldavaxq_u16): Likewise.
8837 (vmlaldavq_p_u16): Likewise.
8838 (vmlaldavxq_p_u16): Likewise.
8839 (vmovlbq_m_u8): Likewise.
8840 (vmovltq_m_u8): Likewise.
8841 (vmovnbq_m_u16): Likewise.
8842 (vmovntq_m_u16): Likewise.
8843 (vqmovnbq_m_u16): Likewise.
8844 (vqmovntq_m_u16): Likewise.
8845 (vrev32q_m_u8): Likewise.
8846 (vmvnq_m_n_s32): Likewise.
8847 (vorrq_m_n_s32): Likewise.
8848 (vqrshrntq_n_s32): Likewise.
8849 (vqshrnbq_n_s32): Likewise.
8850 (vqshrntq_n_s32): Likewise.
8851 (vrshrnbq_n_s32): Likewise.
8852 (vrshrntq_n_s32): Likewise.
8853 (vshrnbq_n_s32): Likewise.
8854 (vshrntq_n_s32): Likewise.
8855 (vcmlaq_f32): Likewise.
8856 (vcmlaq_rot180_f32): Likewise.
8857 (vcmlaq_rot270_f32): Likewise.
8858 (vcmlaq_rot90_f32): Likewise.
8859 (vfmaq_f32): Likewise.
8860 (vfmaq_n_f32): Likewise.
8861 (vfmasq_n_f32): Likewise.
8862 (vfmsq_f32): Likewise.
8863 (vmlaldavaq_s32): Likewise.
8864 (vmlaldavaxq_s32): Likewise.
8865 (vmlsldavaq_s32): Likewise.
8866 (vmlsldavaxq_s32): Likewise.
8867 (vabsq_m_f32): Likewise.
8868 (vcvtmq_m_s32_f32): Likewise.
8869 (vcvtnq_m_s32_f32): Likewise.
8870 (vcvtpq_m_s32_f32): Likewise.
8871 (vcvtq_m_s32_f32): Likewise.
8872 (vdupq_m_n_f32): Likewise.
8873 (vmaxnmaq_m_f32): Likewise.
8874 (vmaxnmavq_p_f32): Likewise.
8875 (vmaxnmvq_p_f32): Likewise.
8876 (vminnmaq_m_f32): Likewise.
8877 (vminnmavq_p_f32): Likewise.
8878 (vminnmvq_p_f32): Likewise.
8879 (vmlaldavq_p_s32): Likewise.
8880 (vmlaldavxq_p_s32): Likewise.
8881 (vmlsldavq_p_s32): Likewise.
8882 (vmlsldavxq_p_s32): Likewise.
8883 (vmovlbq_m_s16): Likewise.
8884 (vmovltq_m_s16): Likewise.
8885 (vmovnbq_m_s32): Likewise.
8886 (vmovntq_m_s32): Likewise.
8887 (vnegq_m_f32): Likewise.
8888 (vpselq_f32): Likewise.
8889 (vqmovnbq_m_s32): Likewise.
8890 (vqmovntq_m_s32): Likewise.
8891 (vrev32q_m_s16): Likewise.
8892 (vrev64q_m_f32): Likewise.
8893 (vrndaq_m_f32): Likewise.
8894 (vrndmq_m_f32): Likewise.
8895 (vrndnq_m_f32): Likewise.
8896 (vrndpq_m_f32): Likewise.
8897 (vrndq_m_f32): Likewise.
8898 (vrndxq_m_f32): Likewise.
8899 (vcmpeqq_m_n_f32): Likewise.
8900 (vcmpgeq_m_f32): Likewise.
8901 (vcmpgeq_m_n_f32): Likewise.
8902 (vcmpgtq_m_f32): Likewise.
8903 (vcmpgtq_m_n_f32): Likewise.
8904 (vcmpleq_m_f32): Likewise.
8905 (vcmpleq_m_n_f32): Likewise.
8906 (vcmpltq_m_f32): Likewise.
8907 (vcmpltq_m_n_f32): Likewise.
8908 (vcmpneq_m_f32): Likewise.
8909 (vcmpneq_m_n_f32): Likewise.
8910 (vmvnq_m_n_u32): Likewise.
8911 (vorrq_m_n_u32): Likewise.
8912 (vqrshruntq_n_s32): Likewise.
8913 (vqshrunbq_n_s32): Likewise.
8914 (vqshruntq_n_s32): Likewise.
8915 (vcvtmq_m_u32_f32): Likewise.
8916 (vcvtnq_m_u32_f32): Likewise.
8917 (vcvtpq_m_u32_f32): Likewise.
8918 (vcvtq_m_u32_f32): Likewise.
8919 (vqmovunbq_m_s32): Likewise.
8920 (vqmovuntq_m_s32): Likewise.
8921 (vqrshrntq_n_u32): Likewise.
8922 (vqshrnbq_n_u32): Likewise.
8923 (vqshrntq_n_u32): Likewise.
8924 (vrshrnbq_n_u32): Likewise.
8925 (vrshrntq_n_u32): Likewise.
8926 (vshrnbq_n_u32): Likewise.
8927 (vshrntq_n_u32): Likewise.
8928 (vmlaldavaq_u32): Likewise.
8929 (vmlaldavaxq_u32): Likewise.
8930 (vmlaldavq_p_u32): Likewise.
8931 (vmlaldavxq_p_u32): Likewise.
8932 (vmovlbq_m_u16): Likewise.
8933 (vmovltq_m_u16): Likewise.
8934 (vmovnbq_m_u32): Likewise.
8935 (vmovntq_m_u32): Likewise.
8936 (vqmovnbq_m_u32): Likewise.
8937 (vqmovntq_m_u32): Likewise.
8938 (vrev32q_m_u16): Likewise.
8939 (__arm_vrmlaldavhaxq_s32): Define intrinsic.
8940 (__arm_vrmlsldavhaq_s32): Likewise.
8941 (__arm_vrmlsldavhaxq_s32): Likewise.
8942 (__arm_vaddlvaq_p_s32): Likewise.
8943 (__arm_vrev16q_m_s8): Likewise.
8944 (__arm_vrmlaldavhq_p_s32): Likewise.
8945 (__arm_vrmlaldavhxq_p_s32): Likewise.
8946 (__arm_vrmlsldavhq_p_s32): Likewise.
8947 (__arm_vrmlsldavhxq_p_s32): Likewise.
8948 (__arm_vaddlvaq_p_u32): Likewise.
8949 (__arm_vrev16q_m_u8): Likewise.
8950 (__arm_vrmlaldavhq_p_u32): Likewise.
8951 (__arm_vmvnq_m_n_s16): Likewise.
8952 (__arm_vorrq_m_n_s16): Likewise.
8953 (__arm_vqrshrntq_n_s16): Likewise.
8954 (__arm_vqshrnbq_n_s16): Likewise.
8955 (__arm_vqshrntq_n_s16): Likewise.
8956 (__arm_vrshrnbq_n_s16): Likewise.
8957 (__arm_vrshrntq_n_s16): Likewise.
8958 (__arm_vshrnbq_n_s16): Likewise.
8959 (__arm_vshrntq_n_s16): Likewise.
8960 (__arm_vmlaldavaq_s16): Likewise.
8961 (__arm_vmlaldavaxq_s16): Likewise.
8962 (__arm_vmlsldavaq_s16): Likewise.
8963 (__arm_vmlsldavaxq_s16): Likewise.
8964 (__arm_vmlaldavq_p_s16): Likewise.
8965 (__arm_vmlaldavxq_p_s16): Likewise.
8966 (__arm_vmlsldavq_p_s16): Likewise.
8967 (__arm_vmlsldavxq_p_s16): Likewise.
8968 (__arm_vmovlbq_m_s8): Likewise.
8969 (__arm_vmovltq_m_s8): Likewise.
8970 (__arm_vmovnbq_m_s16): Likewise.
8971 (__arm_vmovntq_m_s16): Likewise.
8972 (__arm_vqmovnbq_m_s16): Likewise.
8973 (__arm_vqmovntq_m_s16): Likewise.
8974 (__arm_vrev32q_m_s8): Likewise.
8975 (__arm_vmvnq_m_n_u16): Likewise.
8976 (__arm_vorrq_m_n_u16): Likewise.
8977 (__arm_vqrshruntq_n_s16): Likewise.
8978 (__arm_vqshrunbq_n_s16): Likewise.
8979 (__arm_vqshruntq_n_s16): Likewise.
8980 (__arm_vqmovunbq_m_s16): Likewise.
8981 (__arm_vqmovuntq_m_s16): Likewise.
8982 (__arm_vqrshrntq_n_u16): Likewise.
8983 (__arm_vqshrnbq_n_u16): Likewise.
8984 (__arm_vqshrntq_n_u16): Likewise.
8985 (__arm_vrshrnbq_n_u16): Likewise.
8986 (__arm_vrshrntq_n_u16): Likewise.
8987 (__arm_vshrnbq_n_u16): Likewise.
8988 (__arm_vshrntq_n_u16): Likewise.
8989 (__arm_vmlaldavaq_u16): Likewise.
8990 (__arm_vmlaldavaxq_u16): Likewise.
8991 (__arm_vmlaldavq_p_u16): Likewise.
8992 (__arm_vmlaldavxq_p_u16): Likewise.
8993 (__arm_vmovlbq_m_u8): Likewise.
8994 (__arm_vmovltq_m_u8): Likewise.
8995 (__arm_vmovnbq_m_u16): Likewise.
8996 (__arm_vmovntq_m_u16): Likewise.
8997 (__arm_vqmovnbq_m_u16): Likewise.
8998 (__arm_vqmovntq_m_u16): Likewise.
8999 (__arm_vrev32q_m_u8): Likewise.
9000 (__arm_vmvnq_m_n_s32): Likewise.
9001 (__arm_vorrq_m_n_s32): Likewise.
9002 (__arm_vqrshrntq_n_s32): Likewise.
9003 (__arm_vqshrnbq_n_s32): Likewise.
9004 (__arm_vqshrntq_n_s32): Likewise.
9005 (__arm_vrshrnbq_n_s32): Likewise.
9006 (__arm_vrshrntq_n_s32): Likewise.
9007 (__arm_vshrnbq_n_s32): Likewise.
9008 (__arm_vshrntq_n_s32): Likewise.
9009 (__arm_vmlaldavaq_s32): Likewise.
9010 (__arm_vmlaldavaxq_s32): Likewise.
9011 (__arm_vmlsldavaq_s32): Likewise.
9012 (__arm_vmlsldavaxq_s32): Likewise.
9013 (__arm_vmlaldavq_p_s32): Likewise.
9014 (__arm_vmlaldavxq_p_s32): Likewise.
9015 (__arm_vmlsldavq_p_s32): Likewise.
9016 (__arm_vmlsldavxq_p_s32): Likewise.
9017 (__arm_vmovlbq_m_s16): Likewise.
9018 (__arm_vmovltq_m_s16): Likewise.
9019 (__arm_vmovnbq_m_s32): Likewise.
9020 (__arm_vmovntq_m_s32): Likewise.
9021 (__arm_vqmovnbq_m_s32): Likewise.
9022 (__arm_vqmovntq_m_s32): Likewise.
9023 (__arm_vrev32q_m_s16): Likewise.
9024 (__arm_vmvnq_m_n_u32): Likewise.
9025 (__arm_vorrq_m_n_u32): Likewise.
9026 (__arm_vqrshruntq_n_s32): Likewise.
9027 (__arm_vqshrunbq_n_s32): Likewise.
9028 (__arm_vqshruntq_n_s32): Likewise.
9029 (__arm_vqmovunbq_m_s32): Likewise.
9030 (__arm_vqmovuntq_m_s32): Likewise.
9031 (__arm_vqrshrntq_n_u32): Likewise.
9032 (__arm_vqshrnbq_n_u32): Likewise.
9033 (__arm_vqshrntq_n_u32): Likewise.
9034 (__arm_vrshrnbq_n_u32): Likewise.
9035 (__arm_vrshrntq_n_u32): Likewise.
9036 (__arm_vshrnbq_n_u32): Likewise.
9037 (__arm_vshrntq_n_u32): Likewise.
9038 (__arm_vmlaldavaq_u32): Likewise.
9039 (__arm_vmlaldavaxq_u32): Likewise.
9040 (__arm_vmlaldavq_p_u32): Likewise.
9041 (__arm_vmlaldavxq_p_u32): Likewise.
9042 (__arm_vmovlbq_m_u16): Likewise.
9043 (__arm_vmovltq_m_u16): Likewise.
9044 (__arm_vmovnbq_m_u32): Likewise.
9045 (__arm_vmovntq_m_u32): Likewise.
9046 (__arm_vqmovnbq_m_u32): Likewise.
9047 (__arm_vqmovntq_m_u32): Likewise.
9048 (__arm_vrev32q_m_u16): Likewise.
9049 (__arm_vcvtbq_m_f16_f32): Likewise.
9050 (__arm_vcvtbq_m_f32_f16): Likewise.
9051 (__arm_vcvttq_m_f16_f32): Likewise.
9052 (__arm_vcvttq_m_f32_f16): Likewise.
9053 (__arm_vrev32q_m_f16): Likewise.
9054 (__arm_vcmlaq_f16): Likewise.
9055 (__arm_vcmlaq_rot180_f16): Likewise.
9056 (__arm_vcmlaq_rot270_f16): Likewise.
9057 (__arm_vcmlaq_rot90_f16): Likewise.
9058 (__arm_vfmaq_f16): Likewise.
9059 (__arm_vfmaq_n_f16): Likewise.
9060 (__arm_vfmasq_n_f16): Likewise.
9061 (__arm_vfmsq_f16): Likewise.
9062 (__arm_vabsq_m_f16): Likewise.
9063 (__arm_vcvtmq_m_s16_f16): Likewise.
9064 (__arm_vcvtnq_m_s16_f16): Likewise.
9065 (__arm_vcvtpq_m_s16_f16): Likewise.
9066 (__arm_vcvtq_m_s16_f16): Likewise.
9067 (__arm_vdupq_m_n_f16): Likewise.
9068 (__arm_vmaxnmaq_m_f16): Likewise.
9069 (__arm_vmaxnmavq_p_f16): Likewise.
9070 (__arm_vmaxnmvq_p_f16): Likewise.
9071 (__arm_vminnmaq_m_f16): Likewise.
9072 (__arm_vminnmavq_p_f16): Likewise.
9073 (__arm_vminnmvq_p_f16): Likewise.
9074 (__arm_vnegq_m_f16): Likewise.
9075 (__arm_vpselq_f16): Likewise.
9076 (__arm_vrev64q_m_f16): Likewise.
9077 (__arm_vrndaq_m_f16): Likewise.
9078 (__arm_vrndmq_m_f16): Likewise.
9079 (__arm_vrndnq_m_f16): Likewise.
9080 (__arm_vrndpq_m_f16): Likewise.
9081 (__arm_vrndq_m_f16): Likewise.
9082 (__arm_vrndxq_m_f16): Likewise.
9083 (__arm_vcmpeqq_m_n_f16): Likewise.
9084 (__arm_vcmpgeq_m_f16): Likewise.
9085 (__arm_vcmpgeq_m_n_f16): Likewise.
9086 (__arm_vcmpgtq_m_f16): Likewise.
9087 (__arm_vcmpgtq_m_n_f16): Likewise.
9088 (__arm_vcmpleq_m_f16): Likewise.
9089 (__arm_vcmpleq_m_n_f16): Likewise.
9090 (__arm_vcmpltq_m_f16): Likewise.
9091 (__arm_vcmpltq_m_n_f16): Likewise.
9092 (__arm_vcmpneq_m_f16): Likewise.
9093 (__arm_vcmpneq_m_n_f16): Likewise.
9094 (__arm_vcvtmq_m_u16_f16): Likewise.
9095 (__arm_vcvtnq_m_u16_f16): Likewise.
9096 (__arm_vcvtpq_m_u16_f16): Likewise.
9097 (__arm_vcvtq_m_u16_f16): Likewise.
9098 (__arm_vcmlaq_f32): Likewise.
9099 (__arm_vcmlaq_rot180_f32): Likewise.
9100 (__arm_vcmlaq_rot270_f32): Likewise.
9101 (__arm_vcmlaq_rot90_f32): Likewise.
9102 (__arm_vfmaq_f32): Likewise.
9103 (__arm_vfmaq_n_f32): Likewise.
9104 (__arm_vfmasq_n_f32): Likewise.
9105 (__arm_vfmsq_f32): Likewise.
9106 (__arm_vabsq_m_f32): Likewise.
9107 (__arm_vcvtmq_m_s32_f32): Likewise.
9108 (__arm_vcvtnq_m_s32_f32): Likewise.
9109 (__arm_vcvtpq_m_s32_f32): Likewise.
9110 (__arm_vcvtq_m_s32_f32): Likewise.
9111 (__arm_vdupq_m_n_f32): Likewise.
9112 (__arm_vmaxnmaq_m_f32): Likewise.
9113 (__arm_vmaxnmavq_p_f32): Likewise.
9114 (__arm_vmaxnmvq_p_f32): Likewise.
9115 (__arm_vminnmaq_m_f32): Likewise.
9116 (__arm_vminnmavq_p_f32): Likewise.
9117 (__arm_vminnmvq_p_f32): Likewise.
9118 (__arm_vnegq_m_f32): Likewise.
9119 (__arm_vpselq_f32): Likewise.
9120 (__arm_vrev64q_m_f32): Likewise.
9121 (__arm_vrndaq_m_f32): Likewise.
9122 (__arm_vrndmq_m_f32): Likewise.
9123 (__arm_vrndnq_m_f32): Likewise.
9124 (__arm_vrndpq_m_f32): Likewise.
9125 (__arm_vrndq_m_f32): Likewise.
9126 (__arm_vrndxq_m_f32): Likewise.
9127 (__arm_vcmpeqq_m_n_f32): Likewise.
9128 (__arm_vcmpgeq_m_f32): Likewise.
9129 (__arm_vcmpgeq_m_n_f32): Likewise.
9130 (__arm_vcmpgtq_m_f32): Likewise.
9131 (__arm_vcmpgtq_m_n_f32): Likewise.
9132 (__arm_vcmpleq_m_f32): Likewise.
9133 (__arm_vcmpleq_m_n_f32): Likewise.
9134 (__arm_vcmpltq_m_f32): Likewise.
9135 (__arm_vcmpltq_m_n_f32): Likewise.
9136 (__arm_vcmpneq_m_f32): Likewise.
9137 (__arm_vcmpneq_m_n_f32): Likewise.
9138 (__arm_vcvtmq_m_u32_f32): Likewise.
9139 (__arm_vcvtnq_m_u32_f32): Likewise.
9140 (__arm_vcvtpq_m_u32_f32): Likewise.
9141 (__arm_vcvtq_m_u32_f32): Likewise.
9142 (vcvtq_m): Define polymorphic variant.
9143 (vabsq_m): Likewise.
9145 (vcmlaq_rot180): Likewise.
9146 (vcmlaq_rot270): Likewise.
9147 (vcmlaq_rot90): Likewise.
9148 (vcmpeqq_m_n): Likewise.
9149 (vcmpgeq_m_n): Likewise.
9150 (vrndxq_m): Likewise.
9151 (vrndq_m): Likewise.
9152 (vrndpq_m): Likewise.
9153 (vcmpgtq_m_n): Likewise.
9154 (vcmpgtq_m): Likewise.
9155 (vcmpleq_m): Likewise.
9156 (vcmpleq_m_n): Likewise.
9157 (vcmpltq_m_n): Likewise.
9158 (vcmpltq_m): Likewise.
9159 (vcmpneq_m): Likewise.
9160 (vcmpneq_m_n): Likewise.
9161 (vcvtbq_m): Likewise.
9162 (vcvttq_m): Likewise.
9163 (vcvtmq_m): Likewise.
9164 (vcvtnq_m): Likewise.
9165 (vcvtpq_m): Likewise.
9166 (vdupq_m_n): Likewise.
9167 (vfmaq_n): Likewise.
9169 (vfmasq_n): Likewise.
9171 (vmaxnmaq_m): Likewise.
9172 (vmaxnmavq_m): Likewise.
9173 (vmaxnmvq_m): Likewise.
9174 (vmaxnmavq_p): Likewise.
9175 (vmaxnmvq_p): Likewise.
9176 (vminnmaq_m): Likewise.
9177 (vminnmavq_p): Likewise.
9178 (vminnmvq_p): Likewise.
9179 (vrndnq_m): Likewise.
9180 (vrndaq_m): Likewise.
9181 (vrndmq_m): Likewise.
9182 (vrev64q_m): Likewise.
9183 (vrev32q_m): Likewise.
9185 (vnegq_m): Likewise.
9186 (vcmpgeq_m): Likewise.
9187 (vshrntq_n): Likewise.
9188 (vrshrntq_n): Likewise.
9189 (vmovlbq_m): Likewise.
9190 (vmovnbq_m): Likewise.
9191 (vmovntq_m): Likewise.
9192 (vmvnq_m_n): Likewise.
9193 (vmvnq_m): Likewise.
9194 (vshrnbq_n): Likewise.
9195 (vrshrnbq_n): Likewise.
9196 (vqshruntq_n): Likewise.
9197 (vrev16q_m): Likewise.
9198 (vqshrunbq_n): Likewise.
9199 (vqshrntq_n): Likewise.
9200 (vqrshruntq_n): Likewise.
9201 (vqrshrntq_n): Likewise.
9202 (vqshrnbq_n): Likewise.
9203 (vqmovuntq_m): Likewise.
9204 (vqmovntq_m): Likewise.
9205 (vqmovnbq_m): Likewise.
9206 (vorrq_m_n): Likewise.
9207 (vmovltq_m): Likewise.
9208 (vqmovunbq_m): Likewise.
9209 (vaddlvaq_p): Likewise.
9210 (vmlaldavaq): Likewise.
9211 (vmlaldavaxq): Likewise.
9212 (vmlaldavq_p): Likewise.
9213 (vmlaldavxq_p): Likewise.
9214 (vmlsldavaq): Likewise.
9215 (vmlsldavaxq): Likewise.
9216 (vmlsldavq_p): Likewise.
9217 (vmlsldavxq_p): Likewise.
9218 (vrmlaldavhaxq): Likewise.
9219 (vrmlaldavhq_p): Likewise.
9220 (vrmlaldavhxq_p): Likewise.
9221 (vrmlsldavhaq): Likewise.
9222 (vrmlsldavhaxq): Likewise.
9223 (vrmlsldavhq_p): Likewise.
9224 (vrmlsldavhxq_p): Likewise.
9225 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use
9227 (TERNOP_NONE_NONE_NONE_IMM): Likewise.
9228 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
9229 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
9230 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
9231 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise.
9232 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise.
9233 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
9234 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
9235 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
9236 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator.
9237 (MVE_pred3): Likewise.
9238 (MVE_constraint1): Likewise.
9239 (MVE_pred1): Likewise.
9240 (VMLALDAVQ_P): Define iterator.
9241 (VQMOVNBQ_M): Likewise.
9242 (VMOVLTQ_M): Likewise.
9243 (VMOVNBQ_M): Likewise.
9244 (VRSHRNTQ_N): Likewise.
9245 (VORRQ_M_N): Likewise.
9246 (VREV32Q_M): Likewise.
9247 (VREV16Q_M): Likewise.
9248 (VQRSHRNTQ_N): Likewise.
9249 (VMOVNTQ_M): Likewise.
9250 (VMOVLBQ_M): Likewise.
9251 (VMLALDAVAQ): Likewise.
9252 (VQSHRNBQ_N): Likewise.
9253 (VSHRNBQ_N): Likewise.
9254 (VRSHRNBQ_N): Likewise.
9255 (VMLALDAVXQ_P): Likewise.
9256 (VQMOVNTQ_M): Likewise.
9257 (VMVNQ_M_N): Likewise.
9258 (VQSHRNTQ_N): Likewise.
9259 (VMLALDAVAXQ): Likewise.
9260 (VSHRNTQ_N): Likewise.
9261 (VCVTMQ_M): Likewise.
9262 (VCVTNQ_M): Likewise.
9263 (VCVTPQ_M): Likewise.
9264 (VCVTQ_M_N_FROM_F): Likewise.
9265 (VCVTQ_M_FROM_F): Likewise.
9266 (VRMLALDAVHQ_P): Likewise.
9267 (VADDLVAQ_P): Likewise.
9268 (mve_vrndq_m_f<mode>): Define RTL pattern.
9269 (mve_vabsq_m_f<mode>): Likewise.
9270 (mve_vaddlvaq_p_<supf>v4si): Likewise.
9271 (mve_vcmlaq_f<mode>): Likewise.
9272 (mve_vcmlaq_rot180_f<mode>): Likewise.
9273 (mve_vcmlaq_rot270_f<mode>): Likewise.
9274 (mve_vcmlaq_rot90_f<mode>): Likewise.
9275 (mve_vcmpeqq_m_n_f<mode>): Likewise.
9276 (mve_vcmpgeq_m_f<mode>): Likewise.
9277 (mve_vcmpgeq_m_n_f<mode>): Likewise.
9278 (mve_vcmpgtq_m_f<mode>): Likewise.
9279 (mve_vcmpgtq_m_n_f<mode>): Likewise.
9280 (mve_vcmpleq_m_f<mode>): Likewise.
9281 (mve_vcmpleq_m_n_f<mode>): Likewise.
9282 (mve_vcmpltq_m_f<mode>): Likewise.
9283 (mve_vcmpltq_m_n_f<mode>): Likewise.
9284 (mve_vcmpneq_m_f<mode>): Likewise.
9285 (mve_vcmpneq_m_n_f<mode>): Likewise.
9286 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
9287 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
9288 (mve_vcvttq_m_f16_f32v8hf): Likewise.
9289 (mve_vcvttq_m_f32_f16v4sf): Likewise.
9290 (mve_vdupq_m_n_f<mode>): Likewise.
9291 (mve_vfmaq_f<mode>): Likewise.
9292 (mve_vfmaq_n_f<mode>): Likewise.
9293 (mve_vfmasq_n_f<mode>): Likewise.
9294 (mve_vfmsq_f<mode>): Likewise.
9295 (mve_vmaxnmaq_m_f<mode>): Likewise.
9296 (mve_vmaxnmavq_p_f<mode>): Likewise.
9297 (mve_vmaxnmvq_p_f<mode>): Likewise.
9298 (mve_vminnmaq_m_f<mode>): Likewise.
9299 (mve_vminnmavq_p_f<mode>): Likewise.
9300 (mve_vminnmvq_p_f<mode>): Likewise.
9301 (mve_vmlaldavaq_<supf><mode>): Likewise.
9302 (mve_vmlaldavaxq_<supf><mode>): Likewise.
9303 (mve_vmlaldavq_p_<supf><mode>): Likewise.
9304 (mve_vmlaldavxq_p_<supf><mode>): Likewise.
9305 (mve_vmlsldavaq_s<mode>): Likewise.
9306 (mve_vmlsldavaxq_s<mode>): Likewise.
9307 (mve_vmlsldavq_p_s<mode>): Likewise.
9308 (mve_vmlsldavxq_p_s<mode>): Likewise.
9309 (mve_vmovlbq_m_<supf><mode>): Likewise.
9310 (mve_vmovltq_m_<supf><mode>): Likewise.
9311 (mve_vmovnbq_m_<supf><mode>): Likewise.
9312 (mve_vmovntq_m_<supf><mode>): Likewise.
9313 (mve_vmvnq_m_n_<supf><mode>): Likewise.
9314 (mve_vnegq_m_f<mode>): Likewise.
9315 (mve_vorrq_m_n_<supf><mode>): Likewise.
9316 (mve_vpselq_f<mode>): Likewise.
9317 (mve_vqmovnbq_m_<supf><mode>): Likewise.
9318 (mve_vqmovntq_m_<supf><mode>): Likewise.
9319 (mve_vqmovunbq_m_s<mode>): Likewise.
9320 (mve_vqmovuntq_m_s<mode>): Likewise.
9321 (mve_vqrshrntq_n_<supf><mode>): Likewise.
9322 (mve_vqrshruntq_n_s<mode>): Likewise.
9323 (mve_vqshrnbq_n_<supf><mode>): Likewise.
9324 (mve_vqshrntq_n_<supf><mode>): Likewise.
9325 (mve_vqshrunbq_n_s<mode>): Likewise.
9326 (mve_vqshruntq_n_s<mode>): Likewise.
9327 (mve_vrev32q_m_fv8hf): Likewise.
9328 (mve_vrev32q_m_<supf><mode>): Likewise.
9329 (mve_vrev64q_m_f<mode>): Likewise.
9330 (mve_vrmlaldavhaxq_sv4si): Likewise.
9331 (mve_vrmlaldavhxq_p_sv4si): Likewise.
9332 (mve_vrmlsldavhaxq_sv4si): Likewise.
9333 (mve_vrmlsldavhq_p_sv4si): Likewise.
9334 (mve_vrmlsldavhxq_p_sv4si): Likewise.
9335 (mve_vrndaq_m_f<mode>): Likewise.
9336 (mve_vrndmq_m_f<mode>): Likewise.
9337 (mve_vrndnq_m_f<mode>): Likewise.
9338 (mve_vrndpq_m_f<mode>): Likewise.
9339 (mve_vrndxq_m_f<mode>): Likewise.
9340 (mve_vrshrnbq_n_<supf><mode>): Likewise.
9341 (mve_vrshrntq_n_<supf><mode>): Likewise.
9342 (mve_vshrnbq_n_<supf><mode>): Likewise.
9343 (mve_vshrntq_n_<supf><mode>): Likewise.
9344 (mve_vcvtmq_m_<supf><mode>): Likewise.
9345 (mve_vcvtpq_m_<supf><mode>): Likewise.
9346 (mve_vcvtnq_m_<supf><mode>): Likewise.
9347 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
9348 (mve_vrev16q_m_<supf>v16qi): Likewise.
9349 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
9350 (mve_vrmlaldavhq_p_<supf>v4si): Likewise.
9351 (mve_vrmlsldavhaq_sv4si): Likewise.
9353 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
9354 Mihail Ionescu <mihail.ionescu@arm.com>
9355 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9357 * config/arm/arm_mve.h (vpselq_u8): Define macro.
9358 (vpselq_s8): Likewise.
9359 (vrev64q_m_u8): Likewise.
9360 (vqrdmlashq_n_u8): Likewise.
9361 (vqrdmlahq_n_u8): Likewise.
9362 (vqdmlahq_n_u8): Likewise.
9363 (vmvnq_m_u8): Likewise.
9364 (vmlasq_n_u8): Likewise.
9365 (vmlaq_n_u8): Likewise.
9366 (vmladavq_p_u8): Likewise.
9367 (vmladavaq_u8): Likewise.
9368 (vminvq_p_u8): Likewise.
9369 (vmaxvq_p_u8): Likewise.
9370 (vdupq_m_n_u8): Likewise.
9371 (vcmpneq_m_u8): Likewise.
9372 (vcmpneq_m_n_u8): Likewise.
9373 (vcmphiq_m_u8): Likewise.
9374 (vcmphiq_m_n_u8): Likewise.
9375 (vcmpeqq_m_u8): Likewise.
9376 (vcmpeqq_m_n_u8): Likewise.
9377 (vcmpcsq_m_u8): Likewise.
9378 (vcmpcsq_m_n_u8): Likewise.
9379 (vclzq_m_u8): Likewise.
9380 (vaddvaq_p_u8): Likewise.
9381 (vsriq_n_u8): Likewise.
9382 (vsliq_n_u8): Likewise.
9383 (vshlq_m_r_u8): Likewise.
9384 (vrshlq_m_n_u8): Likewise.
9385 (vqshlq_m_r_u8): Likewise.
9386 (vqrshlq_m_n_u8): Likewise.
9387 (vminavq_p_s8): Likewise.
9388 (vminaq_m_s8): Likewise.
9389 (vmaxavq_p_s8): Likewise.
9390 (vmaxaq_m_s8): Likewise.
9391 (vcmpneq_m_s8): Likewise.
9392 (vcmpneq_m_n_s8): Likewise.
9393 (vcmpltq_m_s8): Likewise.
9394 (vcmpltq_m_n_s8): Likewise.
9395 (vcmpleq_m_s8): Likewise.
9396 (vcmpleq_m_n_s8): Likewise.
9397 (vcmpgtq_m_s8): Likewise.
9398 (vcmpgtq_m_n_s8): Likewise.
9399 (vcmpgeq_m_s8): Likewise.
9400 (vcmpgeq_m_n_s8): Likewise.
9401 (vcmpeqq_m_s8): Likewise.
9402 (vcmpeqq_m_n_s8): Likewise.
9403 (vshlq_m_r_s8): Likewise.
9404 (vrshlq_m_n_s8): Likewise.
9405 (vrev64q_m_s8): Likewise.
9406 (vqshlq_m_r_s8): Likewise.
9407 (vqrshlq_m_n_s8): Likewise.
9408 (vqnegq_m_s8): Likewise.
9409 (vqabsq_m_s8): Likewise.
9410 (vnegq_m_s8): Likewise.
9411 (vmvnq_m_s8): Likewise.
9412 (vmlsdavxq_p_s8): Likewise.
9413 (vmlsdavq_p_s8): Likewise.
9414 (vmladavxq_p_s8): Likewise.
9415 (vmladavq_p_s8): Likewise.
9416 (vminvq_p_s8): Likewise.
9417 (vmaxvq_p_s8): Likewise.
9418 (vdupq_m_n_s8): Likewise.
9419 (vclzq_m_s8): Likewise.
9420 (vclsq_m_s8): Likewise.
9421 (vaddvaq_p_s8): Likewise.
9422 (vabsq_m_s8): Likewise.
9423 (vqrdmlsdhxq_s8): Likewise.
9424 (vqrdmlsdhq_s8): Likewise.
9425 (vqrdmlashq_n_s8): Likewise.
9426 (vqrdmlahq_n_s8): Likewise.
9427 (vqrdmladhxq_s8): Likewise.
9428 (vqrdmladhq_s8): Likewise.
9429 (vqdmlsdhxq_s8): Likewise.
9430 (vqdmlsdhq_s8): Likewise.
9431 (vqdmlahq_n_s8): Likewise.
9432 (vqdmladhxq_s8): Likewise.
9433 (vqdmladhq_s8): Likewise.
9434 (vmlsdavaxq_s8): Likewise.
9435 (vmlsdavaq_s8): Likewise.
9436 (vmlasq_n_s8): Likewise.
9437 (vmlaq_n_s8): Likewise.
9438 (vmladavaxq_s8): Likewise.
9439 (vmladavaq_s8): Likewise.
9440 (vsriq_n_s8): Likewise.
9441 (vsliq_n_s8): Likewise.
9442 (vpselq_u16): Likewise.
9443 (vpselq_s16): Likewise.
9444 (vrev64q_m_u16): Likewise.
9445 (vqrdmlashq_n_u16): Likewise.
9446 (vqrdmlahq_n_u16): Likewise.
9447 (vqdmlahq_n_u16): Likewise.
9448 (vmvnq_m_u16): Likewise.
9449 (vmlasq_n_u16): Likewise.
9450 (vmlaq_n_u16): Likewise.
9451 (vmladavq_p_u16): Likewise.
9452 (vmladavaq_u16): Likewise.
9453 (vminvq_p_u16): Likewise.
9454 (vmaxvq_p_u16): Likewise.
9455 (vdupq_m_n_u16): Likewise.
9456 (vcmpneq_m_u16): Likewise.
9457 (vcmpneq_m_n_u16): Likewise.
9458 (vcmphiq_m_u16): Likewise.
9459 (vcmphiq_m_n_u16): Likewise.
9460 (vcmpeqq_m_u16): Likewise.
9461 (vcmpeqq_m_n_u16): Likewise.
9462 (vcmpcsq_m_u16): Likewise.
9463 (vcmpcsq_m_n_u16): Likewise.
9464 (vclzq_m_u16): Likewise.
9465 (vaddvaq_p_u16): Likewise.
9466 (vsriq_n_u16): Likewise.
9467 (vsliq_n_u16): Likewise.
9468 (vshlq_m_r_u16): Likewise.
9469 (vrshlq_m_n_u16): Likewise.
9470 (vqshlq_m_r_u16): Likewise.
9471 (vqrshlq_m_n_u16): Likewise.
9472 (vminavq_p_s16): Likewise.
9473 (vminaq_m_s16): Likewise.
9474 (vmaxavq_p_s16): Likewise.
9475 (vmaxaq_m_s16): Likewise.
9476 (vcmpneq_m_s16): Likewise.
9477 (vcmpneq_m_n_s16): Likewise.
9478 (vcmpltq_m_s16): Likewise.
9479 (vcmpltq_m_n_s16): Likewise.
9480 (vcmpleq_m_s16): Likewise.
9481 (vcmpleq_m_n_s16): Likewise.
9482 (vcmpgtq_m_s16): Likewise.
9483 (vcmpgtq_m_n_s16): Likewise.
9484 (vcmpgeq_m_s16): Likewise.
9485 (vcmpgeq_m_n_s16): Likewise.
9486 (vcmpeqq_m_s16): Likewise.
9487 (vcmpeqq_m_n_s16): Likewise.
9488 (vshlq_m_r_s16): Likewise.
9489 (vrshlq_m_n_s16): Likewise.
9490 (vrev64q_m_s16): Likewise.
9491 (vqshlq_m_r_s16): Likewise.
9492 (vqrshlq_m_n_s16): Likewise.
9493 (vqnegq_m_s16): Likewise.
9494 (vqabsq_m_s16): Likewise.
9495 (vnegq_m_s16): Likewise.
9496 (vmvnq_m_s16): Likewise.
9497 (vmlsdavxq_p_s16): Likewise.
9498 (vmlsdavq_p_s16): Likewise.
9499 (vmladavxq_p_s16): Likewise.
9500 (vmladavq_p_s16): Likewise.
9501 (vminvq_p_s16): Likewise.
9502 (vmaxvq_p_s16): Likewise.
9503 (vdupq_m_n_s16): Likewise.
9504 (vclzq_m_s16): Likewise.
9505 (vclsq_m_s16): Likewise.
9506 (vaddvaq_p_s16): Likewise.
9507 (vabsq_m_s16): Likewise.
9508 (vqrdmlsdhxq_s16): Likewise.
9509 (vqrdmlsdhq_s16): Likewise.
9510 (vqrdmlashq_n_s16): Likewise.
9511 (vqrdmlahq_n_s16): Likewise.
9512 (vqrdmladhxq_s16): Likewise.
9513 (vqrdmladhq_s16): Likewise.
9514 (vqdmlsdhxq_s16): Likewise.
9515 (vqdmlsdhq_s16): Likewise.
9516 (vqdmlahq_n_s16): Likewise.
9517 (vqdmladhxq_s16): Likewise.
9518 (vqdmladhq_s16): Likewise.
9519 (vmlsdavaxq_s16): Likewise.
9520 (vmlsdavaq_s16): Likewise.
9521 (vmlasq_n_s16): Likewise.
9522 (vmlaq_n_s16): Likewise.
9523 (vmladavaxq_s16): Likewise.
9524 (vmladavaq_s16): Likewise.
9525 (vsriq_n_s16): Likewise.
9526 (vsliq_n_s16): Likewise.
9527 (vpselq_u32): Likewise.
9528 (vpselq_s32): Likewise.
9529 (vrev64q_m_u32): Likewise.
9530 (vqrdmlashq_n_u32): Likewise.
9531 (vqrdmlahq_n_u32): Likewise.
9532 (vqdmlahq_n_u32): Likewise.
9533 (vmvnq_m_u32): Likewise.
9534 (vmlasq_n_u32): Likewise.
9535 (vmlaq_n_u32): Likewise.
9536 (vmladavq_p_u32): Likewise.
9537 (vmladavaq_u32): Likewise.
9538 (vminvq_p_u32): Likewise.
9539 (vmaxvq_p_u32): Likewise.
9540 (vdupq_m_n_u32): Likewise.
9541 (vcmpneq_m_u32): Likewise.
9542 (vcmpneq_m_n_u32): Likewise.
9543 (vcmphiq_m_u32): Likewise.
9544 (vcmphiq_m_n_u32): Likewise.
9545 (vcmpeqq_m_u32): Likewise.
9546 (vcmpeqq_m_n_u32): Likewise.
9547 (vcmpcsq_m_u32): Likewise.
9548 (vcmpcsq_m_n_u32): Likewise.
9549 (vclzq_m_u32): Likewise.
9550 (vaddvaq_p_u32): Likewise.
9551 (vsriq_n_u32): Likewise.
9552 (vsliq_n_u32): Likewise.
9553 (vshlq_m_r_u32): Likewise.
9554 (vrshlq_m_n_u32): Likewise.
9555 (vqshlq_m_r_u32): Likewise.
9556 (vqrshlq_m_n_u32): Likewise.
9557 (vminavq_p_s32): Likewise.
9558 (vminaq_m_s32): Likewise.
9559 (vmaxavq_p_s32): Likewise.
9560 (vmaxaq_m_s32): Likewise.
9561 (vcmpneq_m_s32): Likewise.
9562 (vcmpneq_m_n_s32): Likewise.
9563 (vcmpltq_m_s32): Likewise.
9564 (vcmpltq_m_n_s32): Likewise.
9565 (vcmpleq_m_s32): Likewise.
9566 (vcmpleq_m_n_s32): Likewise.
9567 (vcmpgtq_m_s32): Likewise.
9568 (vcmpgtq_m_n_s32): Likewise.
9569 (vcmpgeq_m_s32): Likewise.
9570 (vcmpgeq_m_n_s32): Likewise.
9571 (vcmpeqq_m_s32): Likewise.
9572 (vcmpeqq_m_n_s32): Likewise.
9573 (vshlq_m_r_s32): Likewise.
9574 (vrshlq_m_n_s32): Likewise.
9575 (vrev64q_m_s32): Likewise.
9576 (vqshlq_m_r_s32): Likewise.
9577 (vqrshlq_m_n_s32): Likewise.
9578 (vqnegq_m_s32): Likewise.
9579 (vqabsq_m_s32): Likewise.
9580 (vnegq_m_s32): Likewise.
9581 (vmvnq_m_s32): Likewise.
9582 (vmlsdavxq_p_s32): Likewise.
9583 (vmlsdavq_p_s32): Likewise.
9584 (vmladavxq_p_s32): Likewise.
9585 (vmladavq_p_s32): Likewise.
9586 (vminvq_p_s32): Likewise.
9587 (vmaxvq_p_s32): Likewise.
9588 (vdupq_m_n_s32): Likewise.
9589 (vclzq_m_s32): Likewise.
9590 (vclsq_m_s32): Likewise.
9591 (vaddvaq_p_s32): Likewise.
9592 (vabsq_m_s32): Likewise.
9593 (vqrdmlsdhxq_s32): Likewise.
9594 (vqrdmlsdhq_s32): Likewise.
9595 (vqrdmlashq_n_s32): Likewise.
9596 (vqrdmlahq_n_s32): Likewise.
9597 (vqrdmladhxq_s32): Likewise.
9598 (vqrdmladhq_s32): Likewise.
9599 (vqdmlsdhxq_s32): Likewise.
9600 (vqdmlsdhq_s32): Likewise.
9601 (vqdmlahq_n_s32): Likewise.
9602 (vqdmladhxq_s32): Likewise.
9603 (vqdmladhq_s32): Likewise.
9604 (vmlsdavaxq_s32): Likewise.
9605 (vmlsdavaq_s32): Likewise.
9606 (vmlasq_n_s32): Likewise.
9607 (vmlaq_n_s32): Likewise.
9608 (vmladavaxq_s32): Likewise.
9609 (vmladavaq_s32): Likewise.
9610 (vsriq_n_s32): Likewise.
9611 (vsliq_n_s32): Likewise.
9612 (vpselq_u64): Likewise.
9613 (vpselq_s64): Likewise.
9614 (__arm_vpselq_u8): Define intrinsic.
9615 (__arm_vpselq_s8): Likewise.
9616 (__arm_vrev64q_m_u8): Likewise.
9617 (__arm_vqrdmlashq_n_u8): Likewise.
9618 (__arm_vqrdmlahq_n_u8): Likewise.
9619 (__arm_vqdmlahq_n_u8): Likewise.
9620 (__arm_vmvnq_m_u8): Likewise.
9621 (__arm_vmlasq_n_u8): Likewise.
9622 (__arm_vmlaq_n_u8): Likewise.
9623 (__arm_vmladavq_p_u8): Likewise.
9624 (__arm_vmladavaq_u8): Likewise.
9625 (__arm_vminvq_p_u8): Likewise.
9626 (__arm_vmaxvq_p_u8): Likewise.
9627 (__arm_vdupq_m_n_u8): Likewise.
9628 (__arm_vcmpneq_m_u8): Likewise.
9629 (__arm_vcmpneq_m_n_u8): Likewise.
9630 (__arm_vcmphiq_m_u8): Likewise.
9631 (__arm_vcmphiq_m_n_u8): Likewise.
9632 (__arm_vcmpeqq_m_u8): Likewise.
9633 (__arm_vcmpeqq_m_n_u8): Likewise.
9634 (__arm_vcmpcsq_m_u8): Likewise.
9635 (__arm_vcmpcsq_m_n_u8): Likewise.
9636 (__arm_vclzq_m_u8): Likewise.
9637 (__arm_vaddvaq_p_u8): Likewise.
9638 (__arm_vsriq_n_u8): Likewise.
9639 (__arm_vsliq_n_u8): Likewise.
9640 (__arm_vshlq_m_r_u8): Likewise.
9641 (__arm_vrshlq_m_n_u8): Likewise.
9642 (__arm_vqshlq_m_r_u8): Likewise.
9643 (__arm_vqrshlq_m_n_u8): Likewise.
9644 (__arm_vminavq_p_s8): Likewise.
9645 (__arm_vminaq_m_s8): Likewise.
9646 (__arm_vmaxavq_p_s8): Likewise.
9647 (__arm_vmaxaq_m_s8): Likewise.
9648 (__arm_vcmpneq_m_s8): Likewise.
9649 (__arm_vcmpneq_m_n_s8): Likewise.
9650 (__arm_vcmpltq_m_s8): Likewise.
9651 (__arm_vcmpltq_m_n_s8): Likewise.
9652 (__arm_vcmpleq_m_s8): Likewise.
9653 (__arm_vcmpleq_m_n_s8): Likewise.
9654 (__arm_vcmpgtq_m_s8): Likewise.
9655 (__arm_vcmpgtq_m_n_s8): Likewise.
9656 (__arm_vcmpgeq_m_s8): Likewise.
9657 (__arm_vcmpgeq_m_n_s8): Likewise.
9658 (__arm_vcmpeqq_m_s8): Likewise.
9659 (__arm_vcmpeqq_m_n_s8): Likewise.
9660 (__arm_vshlq_m_r_s8): Likewise.
9661 (__arm_vrshlq_m_n_s8): Likewise.
9662 (__arm_vrev64q_m_s8): Likewise.
9663 (__arm_vqshlq_m_r_s8): Likewise.
9664 (__arm_vqrshlq_m_n_s8): Likewise.
9665 (__arm_vqnegq_m_s8): Likewise.
9666 (__arm_vqabsq_m_s8): Likewise.
9667 (__arm_vnegq_m_s8): Likewise.
9668 (__arm_vmvnq_m_s8): Likewise.
9669 (__arm_vmlsdavxq_p_s8): Likewise.
9670 (__arm_vmlsdavq_p_s8): Likewise.
9671 (__arm_vmladavxq_p_s8): Likewise.
9672 (__arm_vmladavq_p_s8): Likewise.
9673 (__arm_vminvq_p_s8): Likewise.
9674 (__arm_vmaxvq_p_s8): Likewise.
9675 (__arm_vdupq_m_n_s8): Likewise.
9676 (__arm_vclzq_m_s8): Likewise.
9677 (__arm_vclsq_m_s8): Likewise.
9678 (__arm_vaddvaq_p_s8): Likewise.
9679 (__arm_vabsq_m_s8): Likewise.
9680 (__arm_vqrdmlsdhxq_s8): Likewise.
9681 (__arm_vqrdmlsdhq_s8): Likewise.
9682 (__arm_vqrdmlashq_n_s8): Likewise.
9683 (__arm_vqrdmlahq_n_s8): Likewise.
9684 (__arm_vqrdmladhxq_s8): Likewise.
9685 (__arm_vqrdmladhq_s8): Likewise.
9686 (__arm_vqdmlsdhxq_s8): Likewise.
9687 (__arm_vqdmlsdhq_s8): Likewise.
9688 (__arm_vqdmlahq_n_s8): Likewise.
9689 (__arm_vqdmladhxq_s8): Likewise.
9690 (__arm_vqdmladhq_s8): Likewise.
9691 (__arm_vmlsdavaxq_s8): Likewise.
9692 (__arm_vmlsdavaq_s8): Likewise.
9693 (__arm_vmlasq_n_s8): Likewise.
9694 (__arm_vmlaq_n_s8): Likewise.
9695 (__arm_vmladavaxq_s8): Likewise.
9696 (__arm_vmladavaq_s8): Likewise.
9697 (__arm_vsriq_n_s8): Likewise.
9698 (__arm_vsliq_n_s8): Likewise.
9699 (__arm_vpselq_u16): Likewise.
9700 (__arm_vpselq_s16): Likewise.
9701 (__arm_vrev64q_m_u16): Likewise.
9702 (__arm_vqrdmlashq_n_u16): Likewise.
9703 (__arm_vqrdmlahq_n_u16): Likewise.
9704 (__arm_vqdmlahq_n_u16): Likewise.
9705 (__arm_vmvnq_m_u16): Likewise.
9706 (__arm_vmlasq_n_u16): Likewise.
9707 (__arm_vmlaq_n_u16): Likewise.
9708 (__arm_vmladavq_p_u16): Likewise.
9709 (__arm_vmladavaq_u16): Likewise.
9710 (__arm_vminvq_p_u16): Likewise.
9711 (__arm_vmaxvq_p_u16): Likewise.
9712 (__arm_vdupq_m_n_u16): Likewise.
9713 (__arm_vcmpneq_m_u16): Likewise.
9714 (__arm_vcmpneq_m_n_u16): Likewise.
9715 (__arm_vcmphiq_m_u16): Likewise.
9716 (__arm_vcmphiq_m_n_u16): Likewise.
9717 (__arm_vcmpeqq_m_u16): Likewise.
9718 (__arm_vcmpeqq_m_n_u16): Likewise.
9719 (__arm_vcmpcsq_m_u16): Likewise.
9720 (__arm_vcmpcsq_m_n_u16): Likewise.
9721 (__arm_vclzq_m_u16): Likewise.
9722 (__arm_vaddvaq_p_u16): Likewise.
9723 (__arm_vsriq_n_u16): Likewise.
9724 (__arm_vsliq_n_u16): Likewise.
9725 (__arm_vshlq_m_r_u16): Likewise.
9726 (__arm_vrshlq_m_n_u16): Likewise.
9727 (__arm_vqshlq_m_r_u16): Likewise.
9728 (__arm_vqrshlq_m_n_u16): Likewise.
9729 (__arm_vminavq_p_s16): Likewise.
9730 (__arm_vminaq_m_s16): Likewise.
9731 (__arm_vmaxavq_p_s16): Likewise.
9732 (__arm_vmaxaq_m_s16): Likewise.
9733 (__arm_vcmpneq_m_s16): Likewise.
9734 (__arm_vcmpneq_m_n_s16): Likewise.
9735 (__arm_vcmpltq_m_s16): Likewise.
9736 (__arm_vcmpltq_m_n_s16): Likewise.
9737 (__arm_vcmpleq_m_s16): Likewise.
9738 (__arm_vcmpleq_m_n_s16): Likewise.
9739 (__arm_vcmpgtq_m_s16): Likewise.
9740 (__arm_vcmpgtq_m_n_s16): Likewise.
9741 (__arm_vcmpgeq_m_s16): Likewise.
9742 (__arm_vcmpgeq_m_n_s16): Likewise.
9743 (__arm_vcmpeqq_m_s16): Likewise.
9744 (__arm_vcmpeqq_m_n_s16): Likewise.
9745 (__arm_vshlq_m_r_s16): Likewise.
9746 (__arm_vrshlq_m_n_s16): Likewise.
9747 (__arm_vrev64q_m_s16): Likewise.
9748 (__arm_vqshlq_m_r_s16): Likewise.
9749 (__arm_vqrshlq_m_n_s16): Likewise.
9750 (__arm_vqnegq_m_s16): Likewise.
9751 (__arm_vqabsq_m_s16): Likewise.
9752 (__arm_vnegq_m_s16): Likewise.
9753 (__arm_vmvnq_m_s16): Likewise.
9754 (__arm_vmlsdavxq_p_s16): Likewise.
9755 (__arm_vmlsdavq_p_s16): Likewise.
9756 (__arm_vmladavxq_p_s16): Likewise.
9757 (__arm_vmladavq_p_s16): Likewise.
9758 (__arm_vminvq_p_s16): Likewise.
9759 (__arm_vmaxvq_p_s16): Likewise.
9760 (__arm_vdupq_m_n_s16): Likewise.
9761 (__arm_vclzq_m_s16): Likewise.
9762 (__arm_vclsq_m_s16): Likewise.
9763 (__arm_vaddvaq_p_s16): Likewise.
9764 (__arm_vabsq_m_s16): Likewise.
9765 (__arm_vqrdmlsdhxq_s16): Likewise.
9766 (__arm_vqrdmlsdhq_s16): Likewise.
9767 (__arm_vqrdmlashq_n_s16): Likewise.
9768 (__arm_vqrdmlahq_n_s16): Likewise.
9769 (__arm_vqrdmladhxq_s16): Likewise.
9770 (__arm_vqrdmladhq_s16): Likewise.
9771 (__arm_vqdmlsdhxq_s16): Likewise.
9772 (__arm_vqdmlsdhq_s16): Likewise.
9773 (__arm_vqdmlahq_n_s16): Likewise.
9774 (__arm_vqdmladhxq_s16): Likewise.
9775 (__arm_vqdmladhq_s16): Likewise.
9776 (__arm_vmlsdavaxq_s16): Likewise.
9777 (__arm_vmlsdavaq_s16): Likewise.
9778 (__arm_vmlasq_n_s16): Likewise.
9779 (__arm_vmlaq_n_s16): Likewise.
9780 (__arm_vmladavaxq_s16): Likewise.
9781 (__arm_vmladavaq_s16): Likewise.
9782 (__arm_vsriq_n_s16): Likewise.
9783 (__arm_vsliq_n_s16): Likewise.
9784 (__arm_vpselq_u32): Likewise.
9785 (__arm_vpselq_s32): Likewise.
9786 (__arm_vrev64q_m_u32): Likewise.
9787 (__arm_vqrdmlashq_n_u32): Likewise.
9788 (__arm_vqrdmlahq_n_u32): Likewise.
9789 (__arm_vqdmlahq_n_u32): Likewise.
9790 (__arm_vmvnq_m_u32): Likewise.
9791 (__arm_vmlasq_n_u32): Likewise.
9792 (__arm_vmlaq_n_u32): Likewise.
9793 (__arm_vmladavq_p_u32): Likewise.
9794 (__arm_vmladavaq_u32): Likewise.
9795 (__arm_vminvq_p_u32): Likewise.
9796 (__arm_vmaxvq_p_u32): Likewise.
9797 (__arm_vdupq_m_n_u32): Likewise.
9798 (__arm_vcmpneq_m_u32): Likewise.
9799 (__arm_vcmpneq_m_n_u32): Likewise.
9800 (__arm_vcmphiq_m_u32): Likewise.
9801 (__arm_vcmphiq_m_n_u32): Likewise.
9802 (__arm_vcmpeqq_m_u32): Likewise.
9803 (__arm_vcmpeqq_m_n_u32): Likewise.
9804 (__arm_vcmpcsq_m_u32): Likewise.
9805 (__arm_vcmpcsq_m_n_u32): Likewise.
9806 (__arm_vclzq_m_u32): Likewise.
9807 (__arm_vaddvaq_p_u32): Likewise.
9808 (__arm_vsriq_n_u32): Likewise.
9809 (__arm_vsliq_n_u32): Likewise.
9810 (__arm_vshlq_m_r_u32): Likewise.
9811 (__arm_vrshlq_m_n_u32): Likewise.
9812 (__arm_vqshlq_m_r_u32): Likewise.
9813 (__arm_vqrshlq_m_n_u32): Likewise.
9814 (__arm_vminavq_p_s32): Likewise.
9815 (__arm_vminaq_m_s32): Likewise.
9816 (__arm_vmaxavq_p_s32): Likewise.
9817 (__arm_vmaxaq_m_s32): Likewise.
9818 (__arm_vcmpneq_m_s32): Likewise.
9819 (__arm_vcmpneq_m_n_s32): Likewise.
9820 (__arm_vcmpltq_m_s32): Likewise.
9821 (__arm_vcmpltq_m_n_s32): Likewise.
9822 (__arm_vcmpleq_m_s32): Likewise.
9823 (__arm_vcmpleq_m_n_s32): Likewise.
9824 (__arm_vcmpgtq_m_s32): Likewise.
9825 (__arm_vcmpgtq_m_n_s32): Likewise.
9826 (__arm_vcmpgeq_m_s32): Likewise.
9827 (__arm_vcmpgeq_m_n_s32): Likewise.
9828 (__arm_vcmpeqq_m_s32): Likewise.
9829 (__arm_vcmpeqq_m_n_s32): Likewise.
9830 (__arm_vshlq_m_r_s32): Likewise.
9831 (__arm_vrshlq_m_n_s32): Likewise.
9832 (__arm_vrev64q_m_s32): Likewise.
9833 (__arm_vqshlq_m_r_s32): Likewise.
9834 (__arm_vqrshlq_m_n_s32): Likewise.
9835 (__arm_vqnegq_m_s32): Likewise.
9836 (__arm_vqabsq_m_s32): Likewise.
9837 (__arm_vnegq_m_s32): Likewise.
9838 (__arm_vmvnq_m_s32): Likewise.
9839 (__arm_vmlsdavxq_p_s32): Likewise.
9840 (__arm_vmlsdavq_p_s32): Likewise.
9841 (__arm_vmladavxq_p_s32): Likewise.
9842 (__arm_vmladavq_p_s32): Likewise.
9843 (__arm_vminvq_p_s32): Likewise.
9844 (__arm_vmaxvq_p_s32): Likewise.
9845 (__arm_vdupq_m_n_s32): Likewise.
9846 (__arm_vclzq_m_s32): Likewise.
9847 (__arm_vclsq_m_s32): Likewise.
9848 (__arm_vaddvaq_p_s32): Likewise.
9849 (__arm_vabsq_m_s32): Likewise.
9850 (__arm_vqrdmlsdhxq_s32): Likewise.
9851 (__arm_vqrdmlsdhq_s32): Likewise.
9852 (__arm_vqrdmlashq_n_s32): Likewise.
9853 (__arm_vqrdmlahq_n_s32): Likewise.
9854 (__arm_vqrdmladhxq_s32): Likewise.
9855 (__arm_vqrdmladhq_s32): Likewise.
9856 (__arm_vqdmlsdhxq_s32): Likewise.
9857 (__arm_vqdmlsdhq_s32): Likewise.
9858 (__arm_vqdmlahq_n_s32): Likewise.
9859 (__arm_vqdmladhxq_s32): Likewise.
9860 (__arm_vqdmladhq_s32): Likewise.
9861 (__arm_vmlsdavaxq_s32): Likewise.
9862 (__arm_vmlsdavaq_s32): Likewise.
9863 (__arm_vmlasq_n_s32): Likewise.
9864 (__arm_vmlaq_n_s32): Likewise.
9865 (__arm_vmladavaxq_s32): Likewise.
9866 (__arm_vmladavaq_s32): Likewise.
9867 (__arm_vsriq_n_s32): Likewise.
9868 (__arm_vsliq_n_s32): Likewise.
9869 (__arm_vpselq_u64): Likewise.
9870 (__arm_vpselq_s64): Likewise.
9871 (vcmpneq_m_n): Define polymorphic variant.
9872 (vcmpneq_m): Likewise.
9873 (vqrdmlsdhq): Likewise.
9874 (vqrdmlsdhxq): Likewise.
9875 (vqrshlq_m_n): Likewise.
9876 (vqshlq_m_r): Likewise.
9877 (vrev64q_m): Likewise.
9878 (vrshlq_m_n): Likewise.
9879 (vshlq_m_r): Likewise.
9880 (vsliq_n): Likewise.
9881 (vsriq_n): Likewise.
9882 (vqrdmlashq_n): Likewise.
9883 (vqrdmlahq): Likewise.
9884 (vqrdmladhxq): Likewise.
9885 (vqrdmladhq): Likewise.
9886 (vqnegq_m): Likewise.
9887 (vqdmlsdhxq): Likewise.
9888 (vabsq_m): Likewise.
9889 (vclsq_m): Likewise.
9890 (vclzq_m): Likewise.
9891 (vcmpgeq_m): Likewise.
9892 (vcmpgeq_m_n): Likewise.
9893 (vdupq_m_n): Likewise.
9894 (vmaxaq_m): Likewise.
9895 (vmlaq_n): Likewise.
9896 (vmlasq_n): Likewise.
9897 (vmvnq_m): Likewise.
9898 (vnegq_m): Likewise.
9900 (vqdmlahq_n): Likewise.
9901 (vqrdmlahq_n): Likewise.
9902 (vqdmlsdhq): Likewise.
9903 (vqdmladhq): Likewise.
9904 (vqabsq_m): Likewise.
9905 (vminaq_m): Likewise.
9906 (vrmlaldavhaq): Likewise.
9907 (vmlsdavxq_p): Likewise.
9908 (vmlsdavq_p): Likewise.
9909 (vmlsdavaxq): Likewise.
9910 (vmlsdavaq): Likewise.
9911 (vaddvaq_p): Likewise.
9912 (vcmpcsq_m_n): Likewise.
9913 (vcmpcsq_m): Likewise.
9914 (vcmpeqq_m_n): Likewise.
9915 (vcmpeqq_m): Likewise.
9916 (vmladavxq_p): Likewise.
9917 (vmladavq_p): Likewise.
9918 (vmladavaxq): Likewise.
9919 (vmladavaq): Likewise.
9920 (vminvq_p): Likewise.
9921 (vminavq_p): Likewise.
9922 (vmaxvq_p): Likewise.
9923 (vmaxavq_p): Likewise.
9924 (vcmpltq_m_n): Likewise.
9925 (vcmpltq_m): Likewise.
9926 (vcmpleq_m): Likewise.
9927 (vcmpleq_m_n): Likewise.
9928 (vcmphiq_m_n): Likewise.
9929 (vcmphiq_m): Likewise.
9930 (vcmpgtq_m_n): Likewise.
9931 (vcmpgtq_m): Likewise.
9932 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use
9934 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
9935 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
9936 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
9937 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
9938 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
9939 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
9940 * config/arm/constraints.md (Rc): Define constraint to check constant is
9941 in the range of 0 to 15.
9942 (Re): Define constraint to check constant is in the range of 0 to 31.
9943 * config/arm/mve.md (VADDVAQ_P): Define iterator.
9944 (VCLZQ_M): Likewise.
9945 (VCMPEQQ_M_N): Likewise.
9946 (VCMPEQQ_M): Likewise.
9947 (VCMPNEQ_M_N): Likewise.
9948 (VCMPNEQ_M): Likewise.
9949 (VDUPQ_M_N): Likewise.
9950 (VMAXVQ_P): Likewise.
9951 (VMINVQ_P): Likewise.
9952 (VMLADAVAQ): Likewise.
9953 (VMLADAVQ_P): Likewise.
9954 (VMLAQ_N): Likewise.
9955 (VMLASQ_N): Likewise.
9956 (VMVNQ_M): Likewise.
9958 (VQDMLAHQ_N): Likewise.
9959 (VQRDMLAHQ_N): Likewise.
9960 (VQRDMLASHQ_N): Likewise.
9961 (VQRSHLQ_M_N): Likewise.
9962 (VQSHLQ_M_R): Likewise.
9963 (VREV64Q_M): Likewise.
9964 (VRSHLQ_M_N): Likewise.
9965 (VSHLQ_M_R): Likewise.
9966 (VSLIQ_N): Likewise.
9967 (VSRIQ_N): Likewise.
9968 (mve_vabsq_m_s<mode>): Define RTL pattern.
9969 (mve_vaddvaq_p_<supf><mode>): Likewise.
9970 (mve_vclsq_m_s<mode>): Likewise.
9971 (mve_vclzq_m_<supf><mode>): Likewise.
9972 (mve_vcmpcsq_m_n_u<mode>): Likewise.
9973 (mve_vcmpcsq_m_u<mode>): Likewise.
9974 (mve_vcmpeqq_m_n_<supf><mode>): Likewise.
9975 (mve_vcmpeqq_m_<supf><mode>): Likewise.
9976 (mve_vcmpgeq_m_n_s<mode>): Likewise.
9977 (mve_vcmpgeq_m_s<mode>): Likewise.
9978 (mve_vcmpgtq_m_n_s<mode>): Likewise.
9979 (mve_vcmpgtq_m_s<mode>): Likewise.
9980 (mve_vcmphiq_m_n_u<mode>): Likewise.
9981 (mve_vcmphiq_m_u<mode>): Likewise.
9982 (mve_vcmpleq_m_n_s<mode>): Likewise.
9983 (mve_vcmpleq_m_s<mode>): Likewise.
9984 (mve_vcmpltq_m_n_s<mode>): Likewise.
9985 (mve_vcmpltq_m_s<mode>): Likewise.
9986 (mve_vcmpneq_m_n_<supf><mode>): Likewise.
9987 (mve_vcmpneq_m_<supf><mode>): Likewise.
9988 (mve_vdupq_m_n_<supf><mode>): Likewise.
9989 (mve_vmaxaq_m_s<mode>): Likewise.
9990 (mve_vmaxavq_p_s<mode>): Likewise.
9991 (mve_vmaxvq_p_<supf><mode>): Likewise.
9992 (mve_vminaq_m_s<mode>): Likewise.
9993 (mve_vminavq_p_s<mode>): Likewise.
9994 (mve_vminvq_p_<supf><mode>): Likewise.
9995 (mve_vmladavaq_<supf><mode>): Likewise.
9996 (mve_vmladavq_p_<supf><mode>): Likewise.
9997 (mve_vmladavxq_p_s<mode>): Likewise.
9998 (mve_vmlaq_n_<supf><mode>): Likewise.
9999 (mve_vmlasq_n_<supf><mode>): Likewise.
10000 (mve_vmlsdavq_p_s<mode>): Likewise.
10001 (mve_vmlsdavxq_p_s<mode>): Likewise.
10002 (mve_vmvnq_m_<supf><mode>): Likewise.
10003 (mve_vnegq_m_s<mode>): Likewise.
10004 (mve_vpselq_<supf><mode>): Likewise.
10005 (mve_vqabsq_m_s<mode>): Likewise.
10006 (mve_vqdmlahq_n_<supf><mode>): Likewise.
10007 (mve_vqnegq_m_s<mode>): Likewise.
10008 (mve_vqrdmladhq_s<mode>): Likewise.
10009 (mve_vqrdmladhxq_s<mode>): Likewise.
10010 (mve_vqrdmlahq_n_<supf><mode>): Likewise.
10011 (mve_vqrdmlashq_n_<supf><mode>): Likewise.
10012 (mve_vqrdmlsdhq_s<mode>): Likewise.
10013 (mve_vqrdmlsdhxq_s<mode>): Likewise.
10014 (mve_vqrshlq_m_n_<supf><mode>): Likewise.
10015 (mve_vqshlq_m_r_<supf><mode>): Likewise.
10016 (mve_vrev64q_m_<supf><mode>): Likewise.
10017 (mve_vrshlq_m_n_<supf><mode>): Likewise.
10018 (mve_vshlq_m_r_<supf><mode>): Likewise.
10019 (mve_vsliq_n_<supf><mode>): Likewise.
10020 (mve_vsriq_n_<supf><mode>): Likewise.
10021 (mve_vqdmlsdhxq_s<mode>): Likewise.
10022 (mve_vqdmlsdhq_s<mode>): Likewise.
10023 (mve_vqdmladhxq_s<mode>): Likewise.
10024 (mve_vqdmladhq_s<mode>): Likewise.
10025 (mve_vmlsdavaxq_s<mode>): Likewise.
10026 (mve_vmlsdavaq_s<mode>): Likewise.
10027 (mve_vmladavaxq_s<mode>): Likewise.
10028 * config/arm/predicates.md (mve_imm_15):Define predicate to check the
10029 matching constraint Rc.
10030 (mve_imm_31): Define predicate to check the matching constraint Re.
10032 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
10034 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
10035 (vec_cmp<mode>di_dup): Likewise.
10036 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
10038 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
10040 * config/gcn/gcn-valu.md (COND_MODE): Delete.
10041 (COND_INT_MODE): Delete.
10042 (cond_op): Add "mult".
10043 (cond_<expander><mode>): Use VEC_ALLREG_MODE.
10044 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
10046 2020-03-18 Richard Biener <rguenther@suse.de>
10048 PR middle-end/94206
10049 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using
10050 partial int modes or not mode-precision integer types for
10053 2020-03-18 Jakub Jelinek <jakub@redhat.com>
10055 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue
10057 * config/arc/arc.c (frame_stack_add): Likewise.
10058 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term):
10060 * ipa-predicate.c (predicate::remap_after_inlining): Likewise.
10061 * tree-ssa-strlen.h (handle_printf_call): Likewise.
10062 * tree-ssa-strlen.c (is_strlen_related_p): Likewise.
10063 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise.
10065 2020-03-18 Duan bo <duanbo3@huawei.com>
10068 * config/aarch64/aarch64.md (ldr_got_tiny): Delete.
10069 (@ldr_got_tiny_<mode>): New pattern.
10070 (ldr_got_tiny_sidi): Likewise.
10071 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
10072 them to handle SYMBOL_TINY_GOT for ILP32.
10074 2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
10076 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
10077 call-preserved for SVE PCS functions.
10078 (aarch64_layout_frame): Cope with up to 12 predicate save slots.
10079 Optimize the case in which there are no following vector save slots.
10081 2020-03-18 Richard Biener <rguenther@suse.de>
10083 PR middle-end/94188
10084 * fold-const.c (build_fold_addr_expr): Convert address to
10086 * asan.c (maybe_create_ssa_name): Strip useless type conversions.
10087 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1
10088 to build the ADDR_EXPR which we don't really want to simplify.
10089 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
10090 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise.
10091 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
10092 (simplify_builtin_call): Strip useless type conversions.
10093 * tree-ssa-strlen.c (new_strinfo): Likewise.
10095 2020-03-17 Alexey Neyman <stilor@att.net>
10098 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if
10099 the debug level is terse and the declaration is public. Do not
10100 generate type info.
10101 (dwarf2out_decl): Same.
10102 (add_type_attribute): Return immediately if debug level is
10105 2020-03-17 Richard Sandiford <richard.sandiford@arm.com>
10107 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF.
10109 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10110 Mihail Ionescu <mihail.ionescu@arm.com>
10111 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10113 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
10114 Define qualifier for ternary operands.
10115 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
10116 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
10117 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
10118 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
10119 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
10120 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
10121 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
10122 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
10123 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
10124 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
10125 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
10126 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
10127 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
10128 * config/arm/arm_mve.h (vabavq_s8): Define macro.
10129 (vabavq_s16): Likewise.
10130 (vabavq_s32): Likewise.
10131 (vbicq_m_n_s16): Likewise.
10132 (vbicq_m_n_s32): Likewise.
10133 (vbicq_m_n_u16): Likewise.
10134 (vbicq_m_n_u32): Likewise.
10135 (vcmpeqq_m_f16): Likewise.
10136 (vcmpeqq_m_f32): Likewise.
10137 (vcvtaq_m_s16_f16): Likewise.
10138 (vcvtaq_m_u16_f16): Likewise.
10139 (vcvtaq_m_s32_f32): Likewise.
10140 (vcvtaq_m_u32_f32): Likewise.
10141 (vcvtq_m_f16_s16): Likewise.
10142 (vcvtq_m_f16_u16): Likewise.
10143 (vcvtq_m_f32_s32): Likewise.
10144 (vcvtq_m_f32_u32): Likewise.
10145 (vqrshrnbq_n_s16): Likewise.
10146 (vqrshrnbq_n_u16): Likewise.
10147 (vqrshrnbq_n_s32): Likewise.
10148 (vqrshrnbq_n_u32): Likewise.
10149 (vqrshrunbq_n_s16): Likewise.
10150 (vqrshrunbq_n_s32): Likewise.
10151 (vrmlaldavhaq_s32): Likewise.
10152 (vrmlaldavhaq_u32): Likewise.
10153 (vshlcq_s8): Likewise.
10154 (vshlcq_u8): Likewise.
10155 (vshlcq_s16): Likewise.
10156 (vshlcq_u16): Likewise.
10157 (vshlcq_s32): Likewise.
10158 (vshlcq_u32): Likewise.
10159 (vabavq_u8): Likewise.
10160 (vabavq_u16): Likewise.
10161 (vabavq_u32): Likewise.
10162 (__arm_vabavq_s8): Define intrinsic.
10163 (__arm_vabavq_s16): Likewise.
10164 (__arm_vabavq_s32): Likewise.
10165 (__arm_vabavq_u8): Likewise.
10166 (__arm_vabavq_u16): Likewise.
10167 (__arm_vabavq_u32): Likewise.
10168 (__arm_vbicq_m_n_s16): Likewise.
10169 (__arm_vbicq_m_n_s32): Likewise.
10170 (__arm_vbicq_m_n_u16): Likewise.
10171 (__arm_vbicq_m_n_u32): Likewise.
10172 (__arm_vqrshrnbq_n_s16): Likewise.
10173 (__arm_vqrshrnbq_n_u16): Likewise.
10174 (__arm_vqrshrnbq_n_s32): Likewise.
10175 (__arm_vqrshrnbq_n_u32): Likewise.
10176 (__arm_vqrshrunbq_n_s16): Likewise.
10177 (__arm_vqrshrunbq_n_s32): Likewise.
10178 (__arm_vrmlaldavhaq_s32): Likewise.
10179 (__arm_vrmlaldavhaq_u32): Likewise.
10180 (__arm_vshlcq_s8): Likewise.
10181 (__arm_vshlcq_u8): Likewise.
10182 (__arm_vshlcq_s16): Likewise.
10183 (__arm_vshlcq_u16): Likewise.
10184 (__arm_vshlcq_s32): Likewise.
10185 (__arm_vshlcq_u32): Likewise.
10186 (__arm_vcmpeqq_m_f16): Likewise.
10187 (__arm_vcmpeqq_m_f32): Likewise.
10188 (__arm_vcvtaq_m_s16_f16): Likewise.
10189 (__arm_vcvtaq_m_u16_f16): Likewise.
10190 (__arm_vcvtaq_m_s32_f32): Likewise.
10191 (__arm_vcvtaq_m_u32_f32): Likewise.
10192 (__arm_vcvtq_m_f16_s16): Likewise.
10193 (__arm_vcvtq_m_f16_u16): Likewise.
10194 (__arm_vcvtq_m_f32_s32): Likewise.
10195 (__arm_vcvtq_m_f32_u32): Likewise.
10196 (vcvtaq_m): Define polymorphic variant.
10197 (vcvtq_m): Likewise.
10198 (vabavq): Likewise.
10199 (vshlcq): Likewise.
10200 (vbicq_m_n): Likewise.
10201 (vqrshrnbq_n): Likewise.
10202 (vqrshrunbq_n): Likewise.
10203 * config/arm/arm_mve_builtins.def
10204 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
10205 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
10206 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
10207 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
10208 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
10209 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
10210 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
10211 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
10212 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
10213 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
10214 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
10215 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
10216 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
10217 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
10218 * config/arm/mve.md (VBICQ_M_N): Define iterator.
10219 (VCVTAQ_M): Likewise.
10220 (VCVTQ_M_TO_F): Likewise.
10221 (VQRSHRNBQ_N): Likewise.
10222 (VABAVQ): Likewise.
10223 (VSHLCQ): Likewise.
10224 (VRMLALDAVHAQ): Likewise.
10225 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
10226 (mve_vcmpeqq_m_f<mode>): Likewise.
10227 (mve_vcvtaq_m_<supf><mode>): Likewise.
10228 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
10229 (mve_vqrshrnbq_n_<supf><mode>): Likewise.
10230 (mve_vqrshrunbq_n_s<mode>): Likewise.
10231 (mve_vrmlaldavhaq_<supf>v4si): Likewise.
10232 (mve_vabavq_<supf><mode>): Likewise.
10233 (mve_vshlcq_<supf><mode>): Likewise.
10234 (mve_vshlcq_<supf><mode>): Likewise.
10235 (mve_vshlcq_vec_<supf><mode>): Define RTL expand.
10236 (mve_vshlcq_carry_<supf><mode>): Likewise.
10238 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10239 Mihail Ionescu <mihail.ionescu@arm.com>
10240 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10242 * config/arm/arm_mve.h (vqmovntq_u16): Define macro.
10243 (vqmovnbq_u16): Likewise.
10244 (vmulltq_poly_p8): Likewise.
10245 (vmullbq_poly_p8): Likewise.
10246 (vmovntq_u16): Likewise.
10247 (vmovnbq_u16): Likewise.
10248 (vmlaldavxq_u16): Likewise.
10249 (vmlaldavq_u16): Likewise.
10250 (vqmovuntq_s16): Likewise.
10251 (vqmovunbq_s16): Likewise.
10252 (vshlltq_n_u8): Likewise.
10253 (vshllbq_n_u8): Likewise.
10254 (vorrq_n_u16): Likewise.
10255 (vbicq_n_u16): Likewise.
10256 (vcmpneq_n_f16): Likewise.
10257 (vcmpneq_f16): Likewise.
10258 (vcmpltq_n_f16): Likewise.
10259 (vcmpltq_f16): Likewise.
10260 (vcmpleq_n_f16): Likewise.
10261 (vcmpleq_f16): Likewise.
10262 (vcmpgtq_n_f16): Likewise.
10263 (vcmpgtq_f16): Likewise.
10264 (vcmpgeq_n_f16): Likewise.
10265 (vcmpgeq_f16): Likewise.
10266 (vcmpeqq_n_f16): Likewise.
10267 (vcmpeqq_f16): Likewise.
10268 (vsubq_f16): Likewise.
10269 (vqmovntq_s16): Likewise.
10270 (vqmovnbq_s16): Likewise.
10271 (vqdmulltq_s16): Likewise.
10272 (vqdmulltq_n_s16): Likewise.
10273 (vqdmullbq_s16): Likewise.
10274 (vqdmullbq_n_s16): Likewise.
10275 (vorrq_f16): Likewise.
10276 (vornq_f16): Likewise.
10277 (vmulq_n_f16): Likewise.
10278 (vmulq_f16): Likewise.
10279 (vmovntq_s16): Likewise.
10280 (vmovnbq_s16): Likewise.
10281 (vmlsldavxq_s16): Likewise.
10282 (vmlsldavq_s16): Likewise.
10283 (vmlaldavxq_s16): Likewise.
10284 (vmlaldavq_s16): Likewise.
10285 (vminnmvq_f16): Likewise.
10286 (vminnmq_f16): Likewise.
10287 (vminnmavq_f16): Likewise.
10288 (vminnmaq_f16): Likewise.
10289 (vmaxnmvq_f16): Likewise.
10290 (vmaxnmq_f16): Likewise.
10291 (vmaxnmavq_f16): Likewise.
10292 (vmaxnmaq_f16): Likewise.
10293 (veorq_f16): Likewise.
10294 (vcmulq_rot90_f16): Likewise.
10295 (vcmulq_rot270_f16): Likewise.
10296 (vcmulq_rot180_f16): Likewise.
10297 (vcmulq_f16): Likewise.
10298 (vcaddq_rot90_f16): Likewise.
10299 (vcaddq_rot270_f16): Likewise.
10300 (vbicq_f16): Likewise.
10301 (vandq_f16): Likewise.
10302 (vaddq_n_f16): Likewise.
10303 (vabdq_f16): Likewise.
10304 (vshlltq_n_s8): Likewise.
10305 (vshllbq_n_s8): Likewise.
10306 (vorrq_n_s16): Likewise.
10307 (vbicq_n_s16): Likewise.
10308 (vqmovntq_u32): Likewise.
10309 (vqmovnbq_u32): Likewise.
10310 (vmulltq_poly_p16): Likewise.
10311 (vmullbq_poly_p16): Likewise.
10312 (vmovntq_u32): Likewise.
10313 (vmovnbq_u32): Likewise.
10314 (vmlaldavxq_u32): Likewise.
10315 (vmlaldavq_u32): Likewise.
10316 (vqmovuntq_s32): Likewise.
10317 (vqmovunbq_s32): Likewise.
10318 (vshlltq_n_u16): Likewise.
10319 (vshllbq_n_u16): Likewise.
10320 (vorrq_n_u32): Likewise.
10321 (vbicq_n_u32): Likewise.
10322 (vcmpneq_n_f32): Likewise.
10323 (vcmpneq_f32): Likewise.
10324 (vcmpltq_n_f32): Likewise.
10325 (vcmpltq_f32): Likewise.
10326 (vcmpleq_n_f32): Likewise.
10327 (vcmpleq_f32): Likewise.
10328 (vcmpgtq_n_f32): Likewise.
10329 (vcmpgtq_f32): Likewise.
10330 (vcmpgeq_n_f32): Likewise.
10331 (vcmpgeq_f32): Likewise.
10332 (vcmpeqq_n_f32): Likewise.
10333 (vcmpeqq_f32): Likewise.
10334 (vsubq_f32): Likewise.
10335 (vqmovntq_s32): Likewise.
10336 (vqmovnbq_s32): Likewise.
10337 (vqdmulltq_s32): Likewise.
10338 (vqdmulltq_n_s32): Likewise.
10339 (vqdmullbq_s32): Likewise.
10340 (vqdmullbq_n_s32): Likewise.
10341 (vorrq_f32): Likewise.
10342 (vornq_f32): Likewise.
10343 (vmulq_n_f32): Likewise.
10344 (vmulq_f32): Likewise.
10345 (vmovntq_s32): Likewise.
10346 (vmovnbq_s32): Likewise.
10347 (vmlsldavxq_s32): Likewise.
10348 (vmlsldavq_s32): Likewise.
10349 (vmlaldavxq_s32): Likewise.
10350 (vmlaldavq_s32): Likewise.
10351 (vminnmvq_f32): Likewise.
10352 (vminnmq_f32): Likewise.
10353 (vminnmavq_f32): Likewise.
10354 (vminnmaq_f32): Likewise.
10355 (vmaxnmvq_f32): Likewise.
10356 (vmaxnmq_f32): Likewise.
10357 (vmaxnmavq_f32): Likewise.
10358 (vmaxnmaq_f32): Likewise.
10359 (veorq_f32): Likewise.
10360 (vcmulq_rot90_f32): Likewise.
10361 (vcmulq_rot270_f32): Likewise.
10362 (vcmulq_rot180_f32): Likewise.
10363 (vcmulq_f32): Likewise.
10364 (vcaddq_rot90_f32): Likewise.
10365 (vcaddq_rot270_f32): Likewise.
10366 (vbicq_f32): Likewise.
10367 (vandq_f32): Likewise.
10368 (vaddq_n_f32): Likewise.
10369 (vabdq_f32): Likewise.
10370 (vshlltq_n_s16): Likewise.
10371 (vshllbq_n_s16): Likewise.
10372 (vorrq_n_s32): Likewise.
10373 (vbicq_n_s32): Likewise.
10374 (vrmlaldavhq_u32): Likewise.
10375 (vctp8q_m): Likewise.
10376 (vctp64q_m): Likewise.
10377 (vctp32q_m): Likewise.
10378 (vctp16q_m): Likewise.
10379 (vaddlvaq_u32): Likewise.
10380 (vrmlsldavhxq_s32): Likewise.
10381 (vrmlsldavhq_s32): Likewise.
10382 (vrmlaldavhxq_s32): Likewise.
10383 (vrmlaldavhq_s32): Likewise.
10384 (vcvttq_f16_f32): Likewise.
10385 (vcvtbq_f16_f32): Likewise.
10386 (vaddlvaq_s32): Likewise.
10387 (__arm_vqmovntq_u16): Define intrinsic.
10388 (__arm_vqmovnbq_u16): Likewise.
10389 (__arm_vmulltq_poly_p8): Likewise.
10390 (__arm_vmullbq_poly_p8): Likewise.
10391 (__arm_vmovntq_u16): Likewise.
10392 (__arm_vmovnbq_u16): Likewise.
10393 (__arm_vmlaldavxq_u16): Likewise.
10394 (__arm_vmlaldavq_u16): Likewise.
10395 (__arm_vqmovuntq_s16): Likewise.
10396 (__arm_vqmovunbq_s16): Likewise.
10397 (__arm_vshlltq_n_u8): Likewise.
10398 (__arm_vshllbq_n_u8): Likewise.
10399 (__arm_vorrq_n_u16): Likewise.
10400 (__arm_vbicq_n_u16): Likewise.
10401 (__arm_vcmpneq_n_f16): Likewise.
10402 (__arm_vcmpneq_f16): Likewise.
10403 (__arm_vcmpltq_n_f16): Likewise.
10404 (__arm_vcmpltq_f16): Likewise.
10405 (__arm_vcmpleq_n_f16): Likewise.
10406 (__arm_vcmpleq_f16): Likewise.
10407 (__arm_vcmpgtq_n_f16): Likewise.
10408 (__arm_vcmpgtq_f16): Likewise.
10409 (__arm_vcmpgeq_n_f16): Likewise.
10410 (__arm_vcmpgeq_f16): Likewise.
10411 (__arm_vcmpeqq_n_f16): Likewise.
10412 (__arm_vcmpeqq_f16): Likewise.
10413 (__arm_vsubq_f16): Likewise.
10414 (__arm_vqmovntq_s16): Likewise.
10415 (__arm_vqmovnbq_s16): Likewise.
10416 (__arm_vqdmulltq_s16): Likewise.
10417 (__arm_vqdmulltq_n_s16): Likewise.
10418 (__arm_vqdmullbq_s16): Likewise.
10419 (__arm_vqdmullbq_n_s16): Likewise.
10420 (__arm_vorrq_f16): Likewise.
10421 (__arm_vornq_f16): Likewise.
10422 (__arm_vmulq_n_f16): Likewise.
10423 (__arm_vmulq_f16): Likewise.
10424 (__arm_vmovntq_s16): Likewise.
10425 (__arm_vmovnbq_s16): Likewise.
10426 (__arm_vmlsldavxq_s16): Likewise.
10427 (__arm_vmlsldavq_s16): Likewise.
10428 (__arm_vmlaldavxq_s16): Likewise.
10429 (__arm_vmlaldavq_s16): Likewise.
10430 (__arm_vminnmvq_f16): Likewise.
10431 (__arm_vminnmq_f16): Likewise.
10432 (__arm_vminnmavq_f16): Likewise.
10433 (__arm_vminnmaq_f16): Likewise.
10434 (__arm_vmaxnmvq_f16): Likewise.
10435 (__arm_vmaxnmq_f16): Likewise.
10436 (__arm_vmaxnmavq_f16): Likewise.
10437 (__arm_vmaxnmaq_f16): Likewise.
10438 (__arm_veorq_f16): Likewise.
10439 (__arm_vcmulq_rot90_f16): Likewise.
10440 (__arm_vcmulq_rot270_f16): Likewise.
10441 (__arm_vcmulq_rot180_f16): Likewise.
10442 (__arm_vcmulq_f16): Likewise.
10443 (__arm_vcaddq_rot90_f16): Likewise.
10444 (__arm_vcaddq_rot270_f16): Likewise.
10445 (__arm_vbicq_f16): Likewise.
10446 (__arm_vandq_f16): Likewise.
10447 (__arm_vaddq_n_f16): Likewise.
10448 (__arm_vabdq_f16): Likewise.
10449 (__arm_vshlltq_n_s8): Likewise.
10450 (__arm_vshllbq_n_s8): Likewise.
10451 (__arm_vorrq_n_s16): Likewise.
10452 (__arm_vbicq_n_s16): Likewise.
10453 (__arm_vqmovntq_u32): Likewise.
10454 (__arm_vqmovnbq_u32): Likewise.
10455 (__arm_vmulltq_poly_p16): Likewise.
10456 (__arm_vmullbq_poly_p16): Likewise.
10457 (__arm_vmovntq_u32): Likewise.
10458 (__arm_vmovnbq_u32): Likewise.
10459 (__arm_vmlaldavxq_u32): Likewise.
10460 (__arm_vmlaldavq_u32): Likewise.
10461 (__arm_vqmovuntq_s32): Likewise.
10462 (__arm_vqmovunbq_s32): Likewise.
10463 (__arm_vshlltq_n_u16): Likewise.
10464 (__arm_vshllbq_n_u16): Likewise.
10465 (__arm_vorrq_n_u32): Likewise.
10466 (__arm_vbicq_n_u32): Likewise.
10467 (__arm_vcmpneq_n_f32): Likewise.
10468 (__arm_vcmpneq_f32): Likewise.
10469 (__arm_vcmpltq_n_f32): Likewise.
10470 (__arm_vcmpltq_f32): Likewise.
10471 (__arm_vcmpleq_n_f32): Likewise.
10472 (__arm_vcmpleq_f32): Likewise.
10473 (__arm_vcmpgtq_n_f32): Likewise.
10474 (__arm_vcmpgtq_f32): Likewise.
10475 (__arm_vcmpgeq_n_f32): Likewise.
10476 (__arm_vcmpgeq_f32): Likewise.
10477 (__arm_vcmpeqq_n_f32): Likewise.
10478 (__arm_vcmpeqq_f32): Likewise.
10479 (__arm_vsubq_f32): Likewise.
10480 (__arm_vqmovntq_s32): Likewise.
10481 (__arm_vqmovnbq_s32): Likewise.
10482 (__arm_vqdmulltq_s32): Likewise.
10483 (__arm_vqdmulltq_n_s32): Likewise.
10484 (__arm_vqdmullbq_s32): Likewise.
10485 (__arm_vqdmullbq_n_s32): Likewise.
10486 (__arm_vorrq_f32): Likewise.
10487 (__arm_vornq_f32): Likewise.
10488 (__arm_vmulq_n_f32): Likewise.
10489 (__arm_vmulq_f32): Likewise.
10490 (__arm_vmovntq_s32): Likewise.
10491 (__arm_vmovnbq_s32): Likewise.
10492 (__arm_vmlsldavxq_s32): Likewise.
10493 (__arm_vmlsldavq_s32): Likewise.
10494 (__arm_vmlaldavxq_s32): Likewise.
10495 (__arm_vmlaldavq_s32): Likewise.
10496 (__arm_vminnmvq_f32): Likewise.
10497 (__arm_vminnmq_f32): Likewise.
10498 (__arm_vminnmavq_f32): Likewise.
10499 (__arm_vminnmaq_f32): Likewise.
10500 (__arm_vmaxnmvq_f32): Likewise.
10501 (__arm_vmaxnmq_f32): Likewise.
10502 (__arm_vmaxnmavq_f32): Likewise.
10503 (__arm_vmaxnmaq_f32): Likewise.
10504 (__arm_veorq_f32): Likewise.
10505 (__arm_vcmulq_rot90_f32): Likewise.
10506 (__arm_vcmulq_rot270_f32): Likewise.
10507 (__arm_vcmulq_rot180_f32): Likewise.
10508 (__arm_vcmulq_f32): Likewise.
10509 (__arm_vcaddq_rot90_f32): Likewise.
10510 (__arm_vcaddq_rot270_f32): Likewise.
10511 (__arm_vbicq_f32): Likewise.
10512 (__arm_vandq_f32): Likewise.
10513 (__arm_vaddq_n_f32): Likewise.
10514 (__arm_vabdq_f32): Likewise.
10515 (__arm_vshlltq_n_s16): Likewise.
10516 (__arm_vshllbq_n_s16): Likewise.
10517 (__arm_vorrq_n_s32): Likewise.
10518 (__arm_vbicq_n_s32): Likewise.
10519 (__arm_vrmlaldavhq_u32): Likewise.
10520 (__arm_vctp8q_m): Likewise.
10521 (__arm_vctp64q_m): Likewise.
10522 (__arm_vctp32q_m): Likewise.
10523 (__arm_vctp16q_m): Likewise.
10524 (__arm_vaddlvaq_u32): Likewise.
10525 (__arm_vrmlsldavhxq_s32): Likewise.
10526 (__arm_vrmlsldavhq_s32): Likewise.
10527 (__arm_vrmlaldavhxq_s32): Likewise.
10528 (__arm_vrmlaldavhq_s32): Likewise.
10529 (__arm_vcvttq_f16_f32): Likewise.
10530 (__arm_vcvtbq_f16_f32): Likewise.
10531 (__arm_vaddlvaq_s32): Likewise.
10532 (vst4q): Define polymorphic variant.
10533 (vrndxq): Likewise.
10535 (vrndpq): Likewise.
10536 (vrndnq): Likewise.
10537 (vrndmq): Likewise.
10538 (vrndaq): Likewise.
10539 (vrev64q): Likewise.
10541 (vdupq_n): Likewise.
10543 (vrev32q): Likewise.
10544 (vcvtbq_f32): Likewise.
10545 (vcvttq_f32): Likewise.
10547 (vsubq_n): Likewise.
10548 (vbrsrq_n): Likewise.
10549 (vcvtq_n): Likewise.
10553 (vaddq_n): Likewise.
10557 (vmulq_n): Likewise.
10559 (vcaddq_rot270): Likewise.
10560 (vcmpeqq_n): Likewise.
10561 (vcmpeqq): Likewise.
10562 (vcaddq_rot90): Likewise.
10563 (vcmpgeq_n): Likewise.
10564 (vcmpgeq): Likewise.
10565 (vcmpgtq_n): Likewise.
10566 (vcmpgtq): Likewise.
10567 (vcmpgtq): Likewise.
10568 (vcmpleq_n): Likewise.
10569 (vcmpleq_n): Likewise.
10570 (vcmpleq): Likewise.
10571 (vcmpleq): Likewise.
10572 (vcmpltq_n): Likewise.
10573 (vcmpltq_n): Likewise.
10574 (vcmpltq): Likewise.
10575 (vcmpltq): Likewise.
10576 (vcmpneq_n): Likewise.
10577 (vcmpneq_n): Likewise.
10578 (vcmpneq): Likewise.
10579 (vcmpneq): Likewise.
10580 (vcmulq): Likewise.
10581 (vcmulq): Likewise.
10582 (vcmulq_rot180): Likewise.
10583 (vcmulq_rot180): Likewise.
10584 (vcmulq_rot270): Likewise.
10585 (vcmulq_rot270): Likewise.
10586 (vcmulq_rot90): Likewise.
10587 (vcmulq_rot90): Likewise.
10590 (vmaxnmaq): Likewise.
10591 (vmaxnmaq): Likewise.
10592 (vmaxnmavq): Likewise.
10593 (vmaxnmavq): Likewise.
10594 (vmaxnmq): Likewise.
10595 (vmaxnmq): Likewise.
10596 (vmaxnmvq): Likewise.
10597 (vmaxnmvq): Likewise.
10598 (vminnmaq): Likewise.
10599 (vminnmaq): Likewise.
10600 (vminnmavq): Likewise.
10601 (vminnmavq): Likewise.
10602 (vminnmq): Likewise.
10603 (vminnmq): Likewise.
10604 (vminnmvq): Likewise.
10605 (vminnmvq): Likewise.
10606 (vbicq_n): Likewise.
10607 (vqmovntq): Likewise.
10608 (vqmovntq): Likewise.
10609 (vqmovnbq): Likewise.
10610 (vqmovnbq): Likewise.
10611 (vmulltq_poly): Likewise.
10612 (vmulltq_poly): Likewise.
10613 (vmullbq_poly): Likewise.
10614 (vmullbq_poly): Likewise.
10615 (vmovntq): Likewise.
10616 (vmovntq): Likewise.
10617 (vmovnbq): Likewise.
10618 (vmovnbq): Likewise.
10619 (vmlaldavxq): Likewise.
10620 (vmlaldavxq): Likewise.
10621 (vqmovuntq): Likewise.
10622 (vqmovuntq): Likewise.
10623 (vshlltq_n): Likewise.
10624 (vshlltq_n): Likewise.
10625 (vshllbq_n): Likewise.
10626 (vshllbq_n): Likewise.
10627 (vorrq_n): Likewise.
10628 (vorrq_n): Likewise.
10629 (vmlaldavq): Likewise.
10630 (vmlaldavq): Likewise.
10631 (vqmovunbq): Likewise.
10632 (vqmovunbq): Likewise.
10633 (vqdmulltq_n): Likewise.
10634 (vqdmulltq_n): Likewise.
10635 (vqdmulltq): Likewise.
10636 (vqdmulltq): Likewise.
10637 (vqdmullbq_n): Likewise.
10638 (vqdmullbq_n): Likewise.
10639 (vqdmullbq): Likewise.
10640 (vqdmullbq): Likewise.
10641 (vaddlvaq): Likewise.
10642 (vaddlvaq): Likewise.
10643 (vrmlaldavhq): Likewise.
10644 (vrmlaldavhq): Likewise.
10645 (vrmlaldavhxq): Likewise.
10646 (vrmlaldavhxq): Likewise.
10647 (vrmlsldavhq): Likewise.
10648 (vrmlsldavhq): Likewise.
10649 (vrmlsldavhxq): Likewise.
10650 (vrmlsldavhxq): Likewise.
10651 (vmlsldavxq): Likewise.
10652 (vmlsldavxq): Likewise.
10653 (vmlsldavq): Likewise.
10654 (vmlsldavq): Likewise.
10655 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
10656 (BINOP_NONE_NONE_NONE): Likewise.
10657 (BINOP_UNONE_NONE_NONE): Likewise.
10658 (BINOP_UNONE_UNONE_IMM): Likewise.
10659 (BINOP_UNONE_UNONE_NONE): Likewise.
10660 (BINOP_UNONE_UNONE_UNONE): Likewise.
10661 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
10662 (mve_vaddlvaq_<supf>v4si): Likewise.
10663 (mve_vaddq_n_f<mode>): Likewise.
10664 (mve_vandq_f<mode>): Likewise.
10665 (mve_vbicq_f<mode>): Likewise.
10666 (mve_vbicq_n_<supf><mode>): Likewise.
10667 (mve_vcaddq_rot270_f<mode>): Likewise.
10668 (mve_vcaddq_rot90_f<mode>): Likewise.
10669 (mve_vcmpeqq_f<mode>): Likewise.
10670 (mve_vcmpeqq_n_f<mode>): Likewise.
10671 (mve_vcmpgeq_f<mode>): Likewise.
10672 (mve_vcmpgeq_n_f<mode>): Likewise.
10673 (mve_vcmpgtq_f<mode>): Likewise.
10674 (mve_vcmpgtq_n_f<mode>): Likewise.
10675 (mve_vcmpleq_f<mode>): Likewise.
10676 (mve_vcmpleq_n_f<mode>): Likewise.
10677 (mve_vcmpltq_f<mode>): Likewise.
10678 (mve_vcmpltq_n_f<mode>): Likewise.
10679 (mve_vcmpneq_f<mode>): Likewise.
10680 (mve_vcmpneq_n_f<mode>): Likewise.
10681 (mve_vcmulq_f<mode>): Likewise.
10682 (mve_vcmulq_rot180_f<mode>): Likewise.
10683 (mve_vcmulq_rot270_f<mode>): Likewise.
10684 (mve_vcmulq_rot90_f<mode>): Likewise.
10685 (mve_vctp<mode1>q_mhi): Likewise.
10686 (mve_vcvtbq_f16_f32v8hf): Likewise.
10687 (mve_vcvttq_f16_f32v8hf): Likewise.
10688 (mve_veorq_f<mode>): Likewise.
10689 (mve_vmaxnmaq_f<mode>): Likewise.
10690 (mve_vmaxnmavq_f<mode>): Likewise.
10691 (mve_vmaxnmq_f<mode>): Likewise.
10692 (mve_vmaxnmvq_f<mode>): Likewise.
10693 (mve_vminnmaq_f<mode>): Likewise.
10694 (mve_vminnmavq_f<mode>): Likewise.
10695 (mve_vminnmq_f<mode>): Likewise.
10696 (mve_vminnmvq_f<mode>): Likewise.
10697 (mve_vmlaldavq_<supf><mode>): Likewise.
10698 (mve_vmlaldavxq_<supf><mode>): Likewise.
10699 (mve_vmlsldavq_s<mode>): Likewise.
10700 (mve_vmlsldavxq_s<mode>): Likewise.
10701 (mve_vmovnbq_<supf><mode>): Likewise.
10702 (mve_vmovntq_<supf><mode>): Likewise.
10703 (mve_vmulq_f<mode>): Likewise.
10704 (mve_vmulq_n_f<mode>): Likewise.
10705 (mve_vornq_f<mode>): Likewise.
10706 (mve_vorrq_f<mode>): Likewise.
10707 (mve_vorrq_n_<supf><mode>): Likewise.
10708 (mve_vqdmullbq_n_s<mode>): Likewise.
10709 (mve_vqdmullbq_s<mode>): Likewise.
10710 (mve_vqdmulltq_n_s<mode>): Likewise.
10711 (mve_vqdmulltq_s<mode>): Likewise.
10712 (mve_vqmovnbq_<supf><mode>): Likewise.
10713 (mve_vqmovntq_<supf><mode>): Likewise.
10714 (mve_vqmovunbq_s<mode>): Likewise.
10715 (mve_vqmovuntq_s<mode>): Likewise.
10716 (mve_vrmlaldavhxq_sv4si): Likewise.
10717 (mve_vrmlsldavhq_sv4si): Likewise.
10718 (mve_vrmlsldavhxq_sv4si): Likewise.
10719 (mve_vshllbq_n_<supf><mode>): Likewise.
10720 (mve_vshlltq_n_<supf><mode>): Likewise.
10721 (mve_vsubq_f<mode>): Likewise.
10722 (mve_vmulltq_poly_p<mode>): Likewise.
10723 (mve_vmullbq_poly_p<mode>): Likewise.
10724 (mve_vrmlaldavhq_<supf>v4si): Likewise.
10726 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10727 Mihail Ionescu <mihail.ionescu@arm.com>
10728 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10730 * config/arm/arm_mve.h (vsubq_u8): Define macro.
10731 (vsubq_n_u8): Likewise.
10732 (vrmulhq_u8): Likewise.
10733 (vrhaddq_u8): Likewise.
10734 (vqsubq_u8): Likewise.
10735 (vqsubq_n_u8): Likewise.
10736 (vqaddq_u8): Likewise.
10737 (vqaddq_n_u8): Likewise.
10738 (vorrq_u8): Likewise.
10739 (vornq_u8): Likewise.
10740 (vmulq_u8): Likewise.
10741 (vmulq_n_u8): Likewise.
10742 (vmulltq_int_u8): Likewise.
10743 (vmullbq_int_u8): Likewise.
10744 (vmulhq_u8): Likewise.
10745 (vmladavq_u8): Likewise.
10746 (vminvq_u8): Likewise.
10747 (vminq_u8): Likewise.
10748 (vmaxvq_u8): Likewise.
10749 (vmaxq_u8): Likewise.
10750 (vhsubq_u8): Likewise.
10751 (vhsubq_n_u8): Likewise.
10752 (vhaddq_u8): Likewise.
10753 (vhaddq_n_u8): Likewise.
10754 (veorq_u8): Likewise.
10755 (vcmpneq_n_u8): Likewise.
10756 (vcmphiq_u8): Likewise.
10757 (vcmphiq_n_u8): Likewise.
10758 (vcmpeqq_u8): Likewise.
10759 (vcmpeqq_n_u8): Likewise.
10760 (vcmpcsq_u8): Likewise.
10761 (vcmpcsq_n_u8): Likewise.
10762 (vcaddq_rot90_u8): Likewise.
10763 (vcaddq_rot270_u8): Likewise.
10764 (vbicq_u8): Likewise.
10765 (vandq_u8): Likewise.
10766 (vaddvq_p_u8): Likewise.
10767 (vaddvaq_u8): Likewise.
10768 (vaddq_n_u8): Likewise.
10769 (vabdq_u8): Likewise.
10770 (vshlq_r_u8): Likewise.
10771 (vrshlq_u8): Likewise.
10772 (vrshlq_n_u8): Likewise.
10773 (vqshlq_u8): Likewise.
10774 (vqshlq_r_u8): Likewise.
10775 (vqrshlq_u8): Likewise.
10776 (vqrshlq_n_u8): Likewise.
10777 (vminavq_s8): Likewise.
10778 (vminaq_s8): Likewise.
10779 (vmaxavq_s8): Likewise.
10780 (vmaxaq_s8): Likewise.
10781 (vbrsrq_n_u8): Likewise.
10782 (vshlq_n_u8): Likewise.
10783 (vrshrq_n_u8): Likewise.
10784 (vqshlq_n_u8): Likewise.
10785 (vcmpneq_n_s8): Likewise.
10786 (vcmpltq_s8): Likewise.
10787 (vcmpltq_n_s8): Likewise.
10788 (vcmpleq_s8): Likewise.
10789 (vcmpleq_n_s8): Likewise.
10790 (vcmpgtq_s8): Likewise.
10791 (vcmpgtq_n_s8): Likewise.
10792 (vcmpgeq_s8): Likewise.
10793 (vcmpgeq_n_s8): Likewise.
10794 (vcmpeqq_s8): Likewise.
10795 (vcmpeqq_n_s8): Likewise.
10796 (vqshluq_n_s8): Likewise.
10797 (vaddvq_p_s8): Likewise.
10798 (vsubq_s8): Likewise.
10799 (vsubq_n_s8): Likewise.
10800 (vshlq_r_s8): Likewise.
10801 (vrshlq_s8): Likewise.
10802 (vrshlq_n_s8): Likewise.
10803 (vrmulhq_s8): Likewise.
10804 (vrhaddq_s8): Likewise.
10805 (vqsubq_s8): Likewise.
10806 (vqsubq_n_s8): Likewise.
10807 (vqshlq_s8): Likewise.
10808 (vqshlq_r_s8): Likewise.
10809 (vqrshlq_s8): Likewise.
10810 (vqrshlq_n_s8): Likewise.
10811 (vqrdmulhq_s8): Likewise.
10812 (vqrdmulhq_n_s8): Likewise.
10813 (vqdmulhq_s8): Likewise.
10814 (vqdmulhq_n_s8): Likewise.
10815 (vqaddq_s8): Likewise.
10816 (vqaddq_n_s8): Likewise.
10817 (vorrq_s8): Likewise.
10818 (vornq_s8): Likewise.
10819 (vmulq_s8): Likewise.
10820 (vmulq_n_s8): Likewise.
10821 (vmulltq_int_s8): Likewise.
10822 (vmullbq_int_s8): Likewise.
10823 (vmulhq_s8): Likewise.
10824 (vmlsdavxq_s8): Likewise.
10825 (vmlsdavq_s8): Likewise.
10826 (vmladavxq_s8): Likewise.
10827 (vmladavq_s8): Likewise.
10828 (vminvq_s8): Likewise.
10829 (vminq_s8): Likewise.
10830 (vmaxvq_s8): Likewise.
10831 (vmaxq_s8): Likewise.
10832 (vhsubq_s8): Likewise.
10833 (vhsubq_n_s8): Likewise.
10834 (vhcaddq_rot90_s8): Likewise.
10835 (vhcaddq_rot270_s8): Likewise.
10836 (vhaddq_s8): Likewise.
10837 (vhaddq_n_s8): Likewise.
10838 (veorq_s8): Likewise.
10839 (vcaddq_rot90_s8): Likewise.
10840 (vcaddq_rot270_s8): Likewise.
10841 (vbrsrq_n_s8): Likewise.
10842 (vbicq_s8): Likewise.
10843 (vandq_s8): Likewise.
10844 (vaddvaq_s8): Likewise.
10845 (vaddq_n_s8): Likewise.
10846 (vabdq_s8): Likewise.
10847 (vshlq_n_s8): Likewise.
10848 (vrshrq_n_s8): Likewise.
10849 (vqshlq_n_s8): Likewise.
10850 (vsubq_u16): Likewise.
10851 (vsubq_n_u16): Likewise.
10852 (vrmulhq_u16): Likewise.
10853 (vrhaddq_u16): Likewise.
10854 (vqsubq_u16): Likewise.
10855 (vqsubq_n_u16): Likewise.
10856 (vqaddq_u16): Likewise.
10857 (vqaddq_n_u16): Likewise.
10858 (vorrq_u16): Likewise.
10859 (vornq_u16): Likewise.
10860 (vmulq_u16): Likewise.
10861 (vmulq_n_u16): Likewise.
10862 (vmulltq_int_u16): Likewise.
10863 (vmullbq_int_u16): Likewise.
10864 (vmulhq_u16): Likewise.
10865 (vmladavq_u16): Likewise.
10866 (vminvq_u16): Likewise.
10867 (vminq_u16): Likewise.
10868 (vmaxvq_u16): Likewise.
10869 (vmaxq_u16): Likewise.
10870 (vhsubq_u16): Likewise.
10871 (vhsubq_n_u16): Likewise.
10872 (vhaddq_u16): Likewise.
10873 (vhaddq_n_u16): Likewise.
10874 (veorq_u16): Likewise.
10875 (vcmpneq_n_u16): Likewise.
10876 (vcmphiq_u16): Likewise.
10877 (vcmphiq_n_u16): Likewise.
10878 (vcmpeqq_u16): Likewise.
10879 (vcmpeqq_n_u16): Likewise.
10880 (vcmpcsq_u16): Likewise.
10881 (vcmpcsq_n_u16): Likewise.
10882 (vcaddq_rot90_u16): Likewise.
10883 (vcaddq_rot270_u16): Likewise.
10884 (vbicq_u16): Likewise.
10885 (vandq_u16): Likewise.
10886 (vaddvq_p_u16): Likewise.
10887 (vaddvaq_u16): Likewise.
10888 (vaddq_n_u16): Likewise.
10889 (vabdq_u16): Likewise.
10890 (vshlq_r_u16): Likewise.
10891 (vrshlq_u16): Likewise.
10892 (vrshlq_n_u16): Likewise.
10893 (vqshlq_u16): Likewise.
10894 (vqshlq_r_u16): Likewise.
10895 (vqrshlq_u16): Likewise.
10896 (vqrshlq_n_u16): Likewise.
10897 (vminavq_s16): Likewise.
10898 (vminaq_s16): Likewise.
10899 (vmaxavq_s16): Likewise.
10900 (vmaxaq_s16): Likewise.
10901 (vbrsrq_n_u16): Likewise.
10902 (vshlq_n_u16): Likewise.
10903 (vrshrq_n_u16): Likewise.
10904 (vqshlq_n_u16): Likewise.
10905 (vcmpneq_n_s16): Likewise.
10906 (vcmpltq_s16): Likewise.
10907 (vcmpltq_n_s16): Likewise.
10908 (vcmpleq_s16): Likewise.
10909 (vcmpleq_n_s16): Likewise.
10910 (vcmpgtq_s16): Likewise.
10911 (vcmpgtq_n_s16): Likewise.
10912 (vcmpgeq_s16): Likewise.
10913 (vcmpgeq_n_s16): Likewise.
10914 (vcmpeqq_s16): Likewise.
10915 (vcmpeqq_n_s16): Likewise.
10916 (vqshluq_n_s16): Likewise.
10917 (vaddvq_p_s16): Likewise.
10918 (vsubq_s16): Likewise.
10919 (vsubq_n_s16): Likewise.
10920 (vshlq_r_s16): Likewise.
10921 (vrshlq_s16): Likewise.
10922 (vrshlq_n_s16): Likewise.
10923 (vrmulhq_s16): Likewise.
10924 (vrhaddq_s16): Likewise.
10925 (vqsubq_s16): Likewise.
10926 (vqsubq_n_s16): Likewise.
10927 (vqshlq_s16): Likewise.
10928 (vqshlq_r_s16): Likewise.
10929 (vqrshlq_s16): Likewise.
10930 (vqrshlq_n_s16): Likewise.
10931 (vqrdmulhq_s16): Likewise.
10932 (vqrdmulhq_n_s16): Likewise.
10933 (vqdmulhq_s16): Likewise.
10934 (vqdmulhq_n_s16): Likewise.
10935 (vqaddq_s16): Likewise.
10936 (vqaddq_n_s16): Likewise.
10937 (vorrq_s16): Likewise.
10938 (vornq_s16): Likewise.
10939 (vmulq_s16): Likewise.
10940 (vmulq_n_s16): Likewise.
10941 (vmulltq_int_s16): Likewise.
10942 (vmullbq_int_s16): Likewise.
10943 (vmulhq_s16): Likewise.
10944 (vmlsdavxq_s16): Likewise.
10945 (vmlsdavq_s16): Likewise.
10946 (vmladavxq_s16): Likewise.
10947 (vmladavq_s16): Likewise.
10948 (vminvq_s16): Likewise.
10949 (vminq_s16): Likewise.
10950 (vmaxvq_s16): Likewise.
10951 (vmaxq_s16): Likewise.
10952 (vhsubq_s16): Likewise.
10953 (vhsubq_n_s16): Likewise.
10954 (vhcaddq_rot90_s16): Likewise.
10955 (vhcaddq_rot270_s16): Likewise.
10956 (vhaddq_s16): Likewise.
10957 (vhaddq_n_s16): Likewise.
10958 (veorq_s16): Likewise.
10959 (vcaddq_rot90_s16): Likewise.
10960 (vcaddq_rot270_s16): Likewise.
10961 (vbrsrq_n_s16): Likewise.
10962 (vbicq_s16): Likewise.
10963 (vandq_s16): Likewise.
10964 (vaddvaq_s16): Likewise.
10965 (vaddq_n_s16): Likewise.
10966 (vabdq_s16): Likewise.
10967 (vshlq_n_s16): Likewise.
10968 (vrshrq_n_s16): Likewise.
10969 (vqshlq_n_s16): Likewise.
10970 (vsubq_u32): Likewise.
10971 (vsubq_n_u32): Likewise.
10972 (vrmulhq_u32): Likewise.
10973 (vrhaddq_u32): Likewise.
10974 (vqsubq_u32): Likewise.
10975 (vqsubq_n_u32): Likewise.
10976 (vqaddq_u32): Likewise.
10977 (vqaddq_n_u32): Likewise.
10978 (vorrq_u32): Likewise.
10979 (vornq_u32): Likewise.
10980 (vmulq_u32): Likewise.
10981 (vmulq_n_u32): Likewise.
10982 (vmulltq_int_u32): Likewise.
10983 (vmullbq_int_u32): Likewise.
10984 (vmulhq_u32): Likewise.
10985 (vmladavq_u32): Likewise.
10986 (vminvq_u32): Likewise.
10987 (vminq_u32): Likewise.
10988 (vmaxvq_u32): Likewise.
10989 (vmaxq_u32): Likewise.
10990 (vhsubq_u32): Likewise.
10991 (vhsubq_n_u32): Likewise.
10992 (vhaddq_u32): Likewise.
10993 (vhaddq_n_u32): Likewise.
10994 (veorq_u32): Likewise.
10995 (vcmpneq_n_u32): Likewise.
10996 (vcmphiq_u32): Likewise.
10997 (vcmphiq_n_u32): Likewise.
10998 (vcmpeqq_u32): Likewise.
10999 (vcmpeqq_n_u32): Likewise.
11000 (vcmpcsq_u32): Likewise.
11001 (vcmpcsq_n_u32): Likewise.
11002 (vcaddq_rot90_u32): Likewise.
11003 (vcaddq_rot270_u32): Likewise.
11004 (vbicq_u32): Likewise.
11005 (vandq_u32): Likewise.
11006 (vaddvq_p_u32): Likewise.
11007 (vaddvaq_u32): Likewise.
11008 (vaddq_n_u32): Likewise.
11009 (vabdq_u32): Likewise.
11010 (vshlq_r_u32): Likewise.
11011 (vrshlq_u32): Likewise.
11012 (vrshlq_n_u32): Likewise.
11013 (vqshlq_u32): Likewise.
11014 (vqshlq_r_u32): Likewise.
11015 (vqrshlq_u32): Likewise.
11016 (vqrshlq_n_u32): Likewise.
11017 (vminavq_s32): Likewise.
11018 (vminaq_s32): Likewise.
11019 (vmaxavq_s32): Likewise.
11020 (vmaxaq_s32): Likewise.
11021 (vbrsrq_n_u32): Likewise.
11022 (vshlq_n_u32): Likewise.
11023 (vrshrq_n_u32): Likewise.
11024 (vqshlq_n_u32): Likewise.
11025 (vcmpneq_n_s32): Likewise.
11026 (vcmpltq_s32): Likewise.
11027 (vcmpltq_n_s32): Likewise.
11028 (vcmpleq_s32): Likewise.
11029 (vcmpleq_n_s32): Likewise.
11030 (vcmpgtq_s32): Likewise.
11031 (vcmpgtq_n_s32): Likewise.
11032 (vcmpgeq_s32): Likewise.
11033 (vcmpgeq_n_s32): Likewise.
11034 (vcmpeqq_s32): Likewise.
11035 (vcmpeqq_n_s32): Likewise.
11036 (vqshluq_n_s32): Likewise.
11037 (vaddvq_p_s32): Likewise.
11038 (vsubq_s32): Likewise.
11039 (vsubq_n_s32): Likewise.
11040 (vshlq_r_s32): Likewise.
11041 (vrshlq_s32): Likewise.
11042 (vrshlq_n_s32): Likewise.
11043 (vrmulhq_s32): Likewise.
11044 (vrhaddq_s32): Likewise.
11045 (vqsubq_s32): Likewise.
11046 (vqsubq_n_s32): Likewise.
11047 (vqshlq_s32): Likewise.
11048 (vqshlq_r_s32): Likewise.
11049 (vqrshlq_s32): Likewise.
11050 (vqrshlq_n_s32): Likewise.
11051 (vqrdmulhq_s32): Likewise.
11052 (vqrdmulhq_n_s32): Likewise.
11053 (vqdmulhq_s32): Likewise.
11054 (vqdmulhq_n_s32): Likewise.
11055 (vqaddq_s32): Likewise.
11056 (vqaddq_n_s32): Likewise.
11057 (vorrq_s32): Likewise.
11058 (vornq_s32): Likewise.
11059 (vmulq_s32): Likewise.
11060 (vmulq_n_s32): Likewise.
11061 (vmulltq_int_s32): Likewise.
11062 (vmullbq_int_s32): Likewise.
11063 (vmulhq_s32): Likewise.
11064 (vmlsdavxq_s32): Likewise.
11065 (vmlsdavq_s32): Likewise.
11066 (vmladavxq_s32): Likewise.
11067 (vmladavq_s32): Likewise.
11068 (vminvq_s32): Likewise.
11069 (vminq_s32): Likewise.
11070 (vmaxvq_s32): Likewise.
11071 (vmaxq_s32): Likewise.
11072 (vhsubq_s32): Likewise.
11073 (vhsubq_n_s32): Likewise.
11074 (vhcaddq_rot90_s32): Likewise.
11075 (vhcaddq_rot270_s32): Likewise.
11076 (vhaddq_s32): Likewise.
11077 (vhaddq_n_s32): Likewise.
11078 (veorq_s32): Likewise.
11079 (vcaddq_rot90_s32): Likewise.
11080 (vcaddq_rot270_s32): Likewise.
11081 (vbrsrq_n_s32): Likewise.
11082 (vbicq_s32): Likewise.
11083 (vandq_s32): Likewise.
11084 (vaddvaq_s32): Likewise.
11085 (vaddq_n_s32): Likewise.
11086 (vabdq_s32): Likewise.
11087 (vshlq_n_s32): Likewise.
11088 (vrshrq_n_s32): Likewise.
11089 (vqshlq_n_s32): Likewise.
11090 (__arm_vsubq_u8): Define intrinsic.
11091 (__arm_vsubq_n_u8): Likewise.
11092 (__arm_vrmulhq_u8): Likewise.
11093 (__arm_vrhaddq_u8): Likewise.
11094 (__arm_vqsubq_u8): Likewise.
11095 (__arm_vqsubq_n_u8): Likewise.
11096 (__arm_vqaddq_u8): Likewise.
11097 (__arm_vqaddq_n_u8): Likewise.
11098 (__arm_vorrq_u8): Likewise.
11099 (__arm_vornq_u8): Likewise.
11100 (__arm_vmulq_u8): Likewise.
11101 (__arm_vmulq_n_u8): Likewise.
11102 (__arm_vmulltq_int_u8): Likewise.
11103 (__arm_vmullbq_int_u8): Likewise.
11104 (__arm_vmulhq_u8): Likewise.
11105 (__arm_vmladavq_u8): Likewise.
11106 (__arm_vminvq_u8): Likewise.
11107 (__arm_vminq_u8): Likewise.
11108 (__arm_vmaxvq_u8): Likewise.
11109 (__arm_vmaxq_u8): Likewise.
11110 (__arm_vhsubq_u8): Likewise.
11111 (__arm_vhsubq_n_u8): Likewise.
11112 (__arm_vhaddq_u8): Likewise.
11113 (__arm_vhaddq_n_u8): Likewise.
11114 (__arm_veorq_u8): Likewise.
11115 (__arm_vcmpneq_n_u8): Likewise.
11116 (__arm_vcmphiq_u8): Likewise.
11117 (__arm_vcmphiq_n_u8): Likewise.
11118 (__arm_vcmpeqq_u8): Likewise.
11119 (__arm_vcmpeqq_n_u8): Likewise.
11120 (__arm_vcmpcsq_u8): Likewise.
11121 (__arm_vcmpcsq_n_u8): Likewise.
11122 (__arm_vcaddq_rot90_u8): Likewise.
11123 (__arm_vcaddq_rot270_u8): Likewise.
11124 (__arm_vbicq_u8): Likewise.
11125 (__arm_vandq_u8): Likewise.
11126 (__arm_vaddvq_p_u8): Likewise.
11127 (__arm_vaddvaq_u8): Likewise.
11128 (__arm_vaddq_n_u8): Likewise.
11129 (__arm_vabdq_u8): Likewise.
11130 (__arm_vshlq_r_u8): Likewise.
11131 (__arm_vrshlq_u8): Likewise.
11132 (__arm_vrshlq_n_u8): Likewise.
11133 (__arm_vqshlq_u8): Likewise.
11134 (__arm_vqshlq_r_u8): Likewise.
11135 (__arm_vqrshlq_u8): Likewise.
11136 (__arm_vqrshlq_n_u8): Likewise.
11137 (__arm_vminavq_s8): Likewise.
11138 (__arm_vminaq_s8): Likewise.
11139 (__arm_vmaxavq_s8): Likewise.
11140 (__arm_vmaxaq_s8): Likewise.
11141 (__arm_vbrsrq_n_u8): Likewise.
11142 (__arm_vshlq_n_u8): Likewise.
11143 (__arm_vrshrq_n_u8): Likewise.
11144 (__arm_vqshlq_n_u8): Likewise.
11145 (__arm_vcmpneq_n_s8): Likewise.
11146 (__arm_vcmpltq_s8): Likewise.
11147 (__arm_vcmpltq_n_s8): Likewise.
11148 (__arm_vcmpleq_s8): Likewise.
11149 (__arm_vcmpleq_n_s8): Likewise.
11150 (__arm_vcmpgtq_s8): Likewise.
11151 (__arm_vcmpgtq_n_s8): Likewise.
11152 (__arm_vcmpgeq_s8): Likewise.
11153 (__arm_vcmpgeq_n_s8): Likewise.
11154 (__arm_vcmpeqq_s8): Likewise.
11155 (__arm_vcmpeqq_n_s8): Likewise.
11156 (__arm_vqshluq_n_s8): Likewise.
11157 (__arm_vaddvq_p_s8): Likewise.
11158 (__arm_vsubq_s8): Likewise.
11159 (__arm_vsubq_n_s8): Likewise.
11160 (__arm_vshlq_r_s8): Likewise.
11161 (__arm_vrshlq_s8): Likewise.
11162 (__arm_vrshlq_n_s8): Likewise.
11163 (__arm_vrmulhq_s8): Likewise.
11164 (__arm_vrhaddq_s8): Likewise.
11165 (__arm_vqsubq_s8): Likewise.
11166 (__arm_vqsubq_n_s8): Likewise.
11167 (__arm_vqshlq_s8): Likewise.
11168 (__arm_vqshlq_r_s8): Likewise.
11169 (__arm_vqrshlq_s8): Likewise.
11170 (__arm_vqrshlq_n_s8): Likewise.
11171 (__arm_vqrdmulhq_s8): Likewise.
11172 (__arm_vqrdmulhq_n_s8): Likewise.
11173 (__arm_vqdmulhq_s8): Likewise.
11174 (__arm_vqdmulhq_n_s8): Likewise.
11175 (__arm_vqaddq_s8): Likewise.
11176 (__arm_vqaddq_n_s8): Likewise.
11177 (__arm_vorrq_s8): Likewise.
11178 (__arm_vornq_s8): Likewise.
11179 (__arm_vmulq_s8): Likewise.
11180 (__arm_vmulq_n_s8): Likewise.
11181 (__arm_vmulltq_int_s8): Likewise.
11182 (__arm_vmullbq_int_s8): Likewise.
11183 (__arm_vmulhq_s8): Likewise.
11184 (__arm_vmlsdavxq_s8): Likewise.
11185 (__arm_vmlsdavq_s8): Likewise.
11186 (__arm_vmladavxq_s8): Likewise.
11187 (__arm_vmladavq_s8): Likewise.
11188 (__arm_vminvq_s8): Likewise.
11189 (__arm_vminq_s8): Likewise.
11190 (__arm_vmaxvq_s8): Likewise.
11191 (__arm_vmaxq_s8): Likewise.
11192 (__arm_vhsubq_s8): Likewise.
11193 (__arm_vhsubq_n_s8): Likewise.
11194 (__arm_vhcaddq_rot90_s8): Likewise.
11195 (__arm_vhcaddq_rot270_s8): Likewise.
11196 (__arm_vhaddq_s8): Likewise.
11197 (__arm_vhaddq_n_s8): Likewise.
11198 (__arm_veorq_s8): Likewise.
11199 (__arm_vcaddq_rot90_s8): Likewise.
11200 (__arm_vcaddq_rot270_s8): Likewise.
11201 (__arm_vbrsrq_n_s8): Likewise.
11202 (__arm_vbicq_s8): Likewise.
11203 (__arm_vandq_s8): Likewise.
11204 (__arm_vaddvaq_s8): Likewise.
11205 (__arm_vaddq_n_s8): Likewise.
11206 (__arm_vabdq_s8): Likewise.
11207 (__arm_vshlq_n_s8): Likewise.
11208 (__arm_vrshrq_n_s8): Likewise.
11209 (__arm_vqshlq_n_s8): Likewise.
11210 (__arm_vsubq_u16): Likewise.
11211 (__arm_vsubq_n_u16): Likewise.
11212 (__arm_vrmulhq_u16): Likewise.
11213 (__arm_vrhaddq_u16): Likewise.
11214 (__arm_vqsubq_u16): Likewise.
11215 (__arm_vqsubq_n_u16): Likewise.
11216 (__arm_vqaddq_u16): Likewise.
11217 (__arm_vqaddq_n_u16): Likewise.
11218 (__arm_vorrq_u16): Likewise.
11219 (__arm_vornq_u16): Likewise.
11220 (__arm_vmulq_u16): Likewise.
11221 (__arm_vmulq_n_u16): Likewise.
11222 (__arm_vmulltq_int_u16): Likewise.
11223 (__arm_vmullbq_int_u16): Likewise.
11224 (__arm_vmulhq_u16): Likewise.
11225 (__arm_vmladavq_u16): Likewise.
11226 (__arm_vminvq_u16): Likewise.
11227 (__arm_vminq_u16): Likewise.
11228 (__arm_vmaxvq_u16): Likewise.
11229 (__arm_vmaxq_u16): Likewise.
11230 (__arm_vhsubq_u16): Likewise.
11231 (__arm_vhsubq_n_u16): Likewise.
11232 (__arm_vhaddq_u16): Likewise.
11233 (__arm_vhaddq_n_u16): Likewise.
11234 (__arm_veorq_u16): Likewise.
11235 (__arm_vcmpneq_n_u16): Likewise.
11236 (__arm_vcmphiq_u16): Likewise.
11237 (__arm_vcmphiq_n_u16): Likewise.
11238 (__arm_vcmpeqq_u16): Likewise.
11239 (__arm_vcmpeqq_n_u16): Likewise.
11240 (__arm_vcmpcsq_u16): Likewise.
11241 (__arm_vcmpcsq_n_u16): Likewise.
11242 (__arm_vcaddq_rot90_u16): Likewise.
11243 (__arm_vcaddq_rot270_u16): Likewise.
11244 (__arm_vbicq_u16): Likewise.
11245 (__arm_vandq_u16): Likewise.
11246 (__arm_vaddvq_p_u16): Likewise.
11247 (__arm_vaddvaq_u16): Likewise.
11248 (__arm_vaddq_n_u16): Likewise.
11249 (__arm_vabdq_u16): Likewise.
11250 (__arm_vshlq_r_u16): Likewise.
11251 (__arm_vrshlq_u16): Likewise.
11252 (__arm_vrshlq_n_u16): Likewise.
11253 (__arm_vqshlq_u16): Likewise.
11254 (__arm_vqshlq_r_u16): Likewise.
11255 (__arm_vqrshlq_u16): Likewise.
11256 (__arm_vqrshlq_n_u16): Likewise.
11257 (__arm_vminavq_s16): Likewise.
11258 (__arm_vminaq_s16): Likewise.
11259 (__arm_vmaxavq_s16): Likewise.
11260 (__arm_vmaxaq_s16): Likewise.
11261 (__arm_vbrsrq_n_u16): Likewise.
11262 (__arm_vshlq_n_u16): Likewise.
11263 (__arm_vrshrq_n_u16): Likewise.
11264 (__arm_vqshlq_n_u16): Likewise.
11265 (__arm_vcmpneq_n_s16): Likewise.
11266 (__arm_vcmpltq_s16): Likewise.
11267 (__arm_vcmpltq_n_s16): Likewise.
11268 (__arm_vcmpleq_s16): Likewise.
11269 (__arm_vcmpleq_n_s16): Likewise.
11270 (__arm_vcmpgtq_s16): Likewise.
11271 (__arm_vcmpgtq_n_s16): Likewise.
11272 (__arm_vcmpgeq_s16): Likewise.
11273 (__arm_vcmpgeq_n_s16): Likewise.
11274 (__arm_vcmpeqq_s16): Likewise.
11275 (__arm_vcmpeqq_n_s16): Likewise.
11276 (__arm_vqshluq_n_s16): Likewise.
11277 (__arm_vaddvq_p_s16): Likewise.
11278 (__arm_vsubq_s16): Likewise.
11279 (__arm_vsubq_n_s16): Likewise.
11280 (__arm_vshlq_r_s16): Likewise.
11281 (__arm_vrshlq_s16): Likewise.
11282 (__arm_vrshlq_n_s16): Likewise.
11283 (__arm_vrmulhq_s16): Likewise.
11284 (__arm_vrhaddq_s16): Likewise.
11285 (__arm_vqsubq_s16): Likewise.
11286 (__arm_vqsubq_n_s16): Likewise.
11287 (__arm_vqshlq_s16): Likewise.
11288 (__arm_vqshlq_r_s16): Likewise.
11289 (__arm_vqrshlq_s16): Likewise.
11290 (__arm_vqrshlq_n_s16): Likewise.
11291 (__arm_vqrdmulhq_s16): Likewise.
11292 (__arm_vqrdmulhq_n_s16): Likewise.
11293 (__arm_vqdmulhq_s16): Likewise.
11294 (__arm_vqdmulhq_n_s16): Likewise.
11295 (__arm_vqaddq_s16): Likewise.
11296 (__arm_vqaddq_n_s16): Likewise.
11297 (__arm_vorrq_s16): Likewise.
11298 (__arm_vornq_s16): Likewise.
11299 (__arm_vmulq_s16): Likewise.
11300 (__arm_vmulq_n_s16): Likewise.
11301 (__arm_vmulltq_int_s16): Likewise.
11302 (__arm_vmullbq_int_s16): Likewise.
11303 (__arm_vmulhq_s16): Likewise.
11304 (__arm_vmlsdavxq_s16): Likewise.
11305 (__arm_vmlsdavq_s16): Likewise.
11306 (__arm_vmladavxq_s16): Likewise.
11307 (__arm_vmladavq_s16): Likewise.
11308 (__arm_vminvq_s16): Likewise.
11309 (__arm_vminq_s16): Likewise.
11310 (__arm_vmaxvq_s16): Likewise.
11311 (__arm_vmaxq_s16): Likewise.
11312 (__arm_vhsubq_s16): Likewise.
11313 (__arm_vhsubq_n_s16): Likewise.
11314 (__arm_vhcaddq_rot90_s16): Likewise.
11315 (__arm_vhcaddq_rot270_s16): Likewise.
11316 (__arm_vhaddq_s16): Likewise.
11317 (__arm_vhaddq_n_s16): Likewise.
11318 (__arm_veorq_s16): Likewise.
11319 (__arm_vcaddq_rot90_s16): Likewise.
11320 (__arm_vcaddq_rot270_s16): Likewise.
11321 (__arm_vbrsrq_n_s16): Likewise.
11322 (__arm_vbicq_s16): Likewise.
11323 (__arm_vandq_s16): Likewise.
11324 (__arm_vaddvaq_s16): Likewise.
11325 (__arm_vaddq_n_s16): Likewise.
11326 (__arm_vabdq_s16): Likewise.
11327 (__arm_vshlq_n_s16): Likewise.
11328 (__arm_vrshrq_n_s16): Likewise.
11329 (__arm_vqshlq_n_s16): Likewise.
11330 (__arm_vsubq_u32): Likewise.
11331 (__arm_vsubq_n_u32): Likewise.
11332 (__arm_vrmulhq_u32): Likewise.
11333 (__arm_vrhaddq_u32): Likewise.
11334 (__arm_vqsubq_u32): Likewise.
11335 (__arm_vqsubq_n_u32): Likewise.
11336 (__arm_vqaddq_u32): Likewise.
11337 (__arm_vqaddq_n_u32): Likewise.
11338 (__arm_vorrq_u32): Likewise.
11339 (__arm_vornq_u32): Likewise.
11340 (__arm_vmulq_u32): Likewise.
11341 (__arm_vmulq_n_u32): Likewise.
11342 (__arm_vmulltq_int_u32): Likewise.
11343 (__arm_vmullbq_int_u32): Likewise.
11344 (__arm_vmulhq_u32): Likewise.
11345 (__arm_vmladavq_u32): Likewise.
11346 (__arm_vminvq_u32): Likewise.
11347 (__arm_vminq_u32): Likewise.
11348 (__arm_vmaxvq_u32): Likewise.
11349 (__arm_vmaxq_u32): Likewise.
11350 (__arm_vhsubq_u32): Likewise.
11351 (__arm_vhsubq_n_u32): Likewise.
11352 (__arm_vhaddq_u32): Likewise.
11353 (__arm_vhaddq_n_u32): Likewise.
11354 (__arm_veorq_u32): Likewise.
11355 (__arm_vcmpneq_n_u32): Likewise.
11356 (__arm_vcmphiq_u32): Likewise.
11357 (__arm_vcmphiq_n_u32): Likewise.
11358 (__arm_vcmpeqq_u32): Likewise.
11359 (__arm_vcmpeqq_n_u32): Likewise.
11360 (__arm_vcmpcsq_u32): Likewise.
11361 (__arm_vcmpcsq_n_u32): Likewise.
11362 (__arm_vcaddq_rot90_u32): Likewise.
11363 (__arm_vcaddq_rot270_u32): Likewise.
11364 (__arm_vbicq_u32): Likewise.
11365 (__arm_vandq_u32): Likewise.
11366 (__arm_vaddvq_p_u32): Likewise.
11367 (__arm_vaddvaq_u32): Likewise.
11368 (__arm_vaddq_n_u32): Likewise.
11369 (__arm_vabdq_u32): Likewise.
11370 (__arm_vshlq_r_u32): Likewise.
11371 (__arm_vrshlq_u32): Likewise.
11372 (__arm_vrshlq_n_u32): Likewise.
11373 (__arm_vqshlq_u32): Likewise.
11374 (__arm_vqshlq_r_u32): Likewise.
11375 (__arm_vqrshlq_u32): Likewise.
11376 (__arm_vqrshlq_n_u32): Likewise.
11377 (__arm_vminavq_s32): Likewise.
11378 (__arm_vminaq_s32): Likewise.
11379 (__arm_vmaxavq_s32): Likewise.
11380 (__arm_vmaxaq_s32): Likewise.
11381 (__arm_vbrsrq_n_u32): Likewise.
11382 (__arm_vshlq_n_u32): Likewise.
11383 (__arm_vrshrq_n_u32): Likewise.
11384 (__arm_vqshlq_n_u32): Likewise.
11385 (__arm_vcmpneq_n_s32): Likewise.
11386 (__arm_vcmpltq_s32): Likewise.
11387 (__arm_vcmpltq_n_s32): Likewise.
11388 (__arm_vcmpleq_s32): Likewise.
11389 (__arm_vcmpleq_n_s32): Likewise.
11390 (__arm_vcmpgtq_s32): Likewise.
11391 (__arm_vcmpgtq_n_s32): Likewise.
11392 (__arm_vcmpgeq_s32): Likewise.
11393 (__arm_vcmpgeq_n_s32): Likewise.
11394 (__arm_vcmpeqq_s32): Likewise.
11395 (__arm_vcmpeqq_n_s32): Likewise.
11396 (__arm_vqshluq_n_s32): Likewise.
11397 (__arm_vaddvq_p_s32): Likewise.
11398 (__arm_vsubq_s32): Likewise.
11399 (__arm_vsubq_n_s32): Likewise.
11400 (__arm_vshlq_r_s32): Likewise.
11401 (__arm_vrshlq_s32): Likewise.
11402 (__arm_vrshlq_n_s32): Likewise.
11403 (__arm_vrmulhq_s32): Likewise.
11404 (__arm_vrhaddq_s32): Likewise.
11405 (__arm_vqsubq_s32): Likewise.
11406 (__arm_vqsubq_n_s32): Likewise.
11407 (__arm_vqshlq_s32): Likewise.
11408 (__arm_vqshlq_r_s32): Likewise.
11409 (__arm_vqrshlq_s32): Likewise.
11410 (__arm_vqrshlq_n_s32): Likewise.
11411 (__arm_vqrdmulhq_s32): Likewise.
11412 (__arm_vqrdmulhq_n_s32): Likewise.
11413 (__arm_vqdmulhq_s32): Likewise.
11414 (__arm_vqdmulhq_n_s32): Likewise.
11415 (__arm_vqaddq_s32): Likewise.
11416 (__arm_vqaddq_n_s32): Likewise.
11417 (__arm_vorrq_s32): Likewise.
11418 (__arm_vornq_s32): Likewise.
11419 (__arm_vmulq_s32): Likewise.
11420 (__arm_vmulq_n_s32): Likewise.
11421 (__arm_vmulltq_int_s32): Likewise.
11422 (__arm_vmullbq_int_s32): Likewise.
11423 (__arm_vmulhq_s32): Likewise.
11424 (__arm_vmlsdavxq_s32): Likewise.
11425 (__arm_vmlsdavq_s32): Likewise.
11426 (__arm_vmladavxq_s32): Likewise.
11427 (__arm_vmladavq_s32): Likewise.
11428 (__arm_vminvq_s32): Likewise.
11429 (__arm_vminq_s32): Likewise.
11430 (__arm_vmaxvq_s32): Likewise.
11431 (__arm_vmaxq_s32): Likewise.
11432 (__arm_vhsubq_s32): Likewise.
11433 (__arm_vhsubq_n_s32): Likewise.
11434 (__arm_vhcaddq_rot90_s32): Likewise.
11435 (__arm_vhcaddq_rot270_s32): Likewise.
11436 (__arm_vhaddq_s32): Likewise.
11437 (__arm_vhaddq_n_s32): Likewise.
11438 (__arm_veorq_s32): Likewise.
11439 (__arm_vcaddq_rot90_s32): Likewise.
11440 (__arm_vcaddq_rot270_s32): Likewise.
11441 (__arm_vbrsrq_n_s32): Likewise.
11442 (__arm_vbicq_s32): Likewise.
11443 (__arm_vandq_s32): Likewise.
11444 (__arm_vaddvaq_s32): Likewise.
11445 (__arm_vaddq_n_s32): Likewise.
11446 (__arm_vabdq_s32): Likewise.
11447 (__arm_vshlq_n_s32): Likewise.
11448 (__arm_vrshrq_n_s32): Likewise.
11449 (__arm_vqshlq_n_s32): Likewise.
11450 (vsubq): Define polymorphic variant.
11451 (vsubq_n): Likewise.
11452 (vshlq_r): Likewise.
11453 (vrshlq_n): Likewise.
11454 (vrshlq): Likewise.
11455 (vrmulhq): Likewise.
11456 (vrhaddq): Likewise.
11457 (vqsubq_n): Likewise.
11458 (vqsubq): Likewise.
11459 (vqshlq): Likewise.
11460 (vqshlq_r): Likewise.
11461 (vqshluq): Likewise.
11462 (vrshrq_n): Likewise.
11463 (vshlq_n): Likewise.
11464 (vqshluq_n): Likewise.
11465 (vqshlq_n): Likewise.
11466 (vqrshlq_n): Likewise.
11467 (vqrshlq): Likewise.
11468 (vqrdmulhq_n): Likewise.
11469 (vqrdmulhq): Likewise.
11470 (vqdmulhq_n): Likewise.
11471 (vqdmulhq): Likewise.
11472 (vqaddq_n): Likewise.
11473 (vqaddq): Likewise.
11474 (vorrq_n): Likewise.
11477 (vmulq_n): Likewise.
11479 (vmulltq_int): Likewise.
11480 (vmullbq_int): Likewise.
11481 (vmulhq): Likewise.
11483 (vminaq): Likewise.
11485 (vmaxaq): Likewise.
11486 (vhsubq_n): Likewise.
11487 (vhsubq): Likewise.
11488 (vhcaddq_rot90): Likewise.
11489 (vhcaddq_rot270): Likewise.
11490 (vhaddq_n): Likewise.
11491 (vhaddq): Likewise.
11493 (vcaddq_rot90): Likewise.
11494 (vcaddq_rot270): Likewise.
11495 (vbrsrq_n): Likewise.
11496 (vbicq_n): Likewise.
11499 (vaddq_n): Likewise.
11502 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
11503 (BINOP_NONE_NONE_NONE): Likewise.
11504 (BINOP_NONE_NONE_UNONE): Likewise.
11505 (BINOP_UNONE_NONE_IMM): Likewise.
11506 (BINOP_UNONE_NONE_NONE): Likewise.
11507 (BINOP_UNONE_UNONE_IMM): Likewise.
11508 (BINOP_UNONE_UNONE_NONE): Likewise.
11509 (BINOP_UNONE_UNONE_UNONE): Likewise.
11510 * config/arm/constraints.md (Ra): Define constraint to check constant is
11511 in the range of 0 to 7.
11512 (Rg): Define constriant to check the constant is one among 1, 2, 4
11514 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern.
11515 (mve_vaddq_n_<supf>): Likewise.
11516 (mve_vaddvaq_<supf>): Likewise.
11517 (mve_vaddvq_p_<supf>): Likewise.
11518 (mve_vandq_<supf>): Likewise.
11519 (mve_vbicq_<supf>): Likewise.
11520 (mve_vbrsrq_n_<supf>): Likewise.
11521 (mve_vcaddq_rot270_<supf>): Likewise.
11522 (mve_vcaddq_rot90_<supf>): Likewise.
11523 (mve_vcmpcsq_n_u): Likewise.
11524 (mve_vcmpcsq_u): Likewise.
11525 (mve_vcmpeqq_n_<supf>): Likewise.
11526 (mve_vcmpeqq_<supf>): Likewise.
11527 (mve_vcmpgeq_n_s): Likewise.
11528 (mve_vcmpgeq_s): Likewise.
11529 (mve_vcmpgtq_n_s): Likewise.
11530 (mve_vcmpgtq_s): Likewise.
11531 (mve_vcmphiq_n_u): Likewise.
11532 (mve_vcmphiq_u): Likewise.
11533 (mve_vcmpleq_n_s): Likewise.
11534 (mve_vcmpleq_s): Likewise.
11535 (mve_vcmpltq_n_s): Likewise.
11536 (mve_vcmpltq_s): Likewise.
11537 (mve_vcmpneq_n_<supf>): Likewise.
11538 (mve_vddupq_n_u): Likewise.
11539 (mve_veorq_<supf>): Likewise.
11540 (mve_vhaddq_n_<supf>): Likewise.
11541 (mve_vhaddq_<supf>): Likewise.
11542 (mve_vhcaddq_rot270_s): Likewise.
11543 (mve_vhcaddq_rot90_s): Likewise.
11544 (mve_vhsubq_n_<supf>): Likewise.
11545 (mve_vhsubq_<supf>): Likewise.
11546 (mve_vidupq_n_u): Likewise.
11547 (mve_vmaxaq_s): Likewise.
11548 (mve_vmaxavq_s): Likewise.
11549 (mve_vmaxq_<supf>): Likewise.
11550 (mve_vmaxvq_<supf>): Likewise.
11551 (mve_vminaq_s): Likewise.
11552 (mve_vminavq_s): Likewise.
11553 (mve_vminq_<supf>): Likewise.
11554 (mve_vminvq_<supf>): Likewise.
11555 (mve_vmladavq_<supf>): Likewise.
11556 (mve_vmladavxq_s): Likewise.
11557 (mve_vmlsdavq_s): Likewise.
11558 (mve_vmlsdavxq_s): Likewise.
11559 (mve_vmulhq_<supf>): Likewise.
11560 (mve_vmullbq_int_<supf>): Likewise.
11561 (mve_vmulltq_int_<supf>): Likewise.
11562 (mve_vmulq_n_<supf>): Likewise.
11563 (mve_vmulq_<supf>): Likewise.
11564 (mve_vornq_<supf>): Likewise.
11565 (mve_vorrq_<supf>): Likewise.
11566 (mve_vqaddq_n_<supf>): Likewise.
11567 (mve_vqaddq_<supf>): Likewise.
11568 (mve_vqdmulhq_n_s): Likewise.
11569 (mve_vqdmulhq_s): Likewise.
11570 (mve_vqrdmulhq_n_s): Likewise.
11571 (mve_vqrdmulhq_s): Likewise.
11572 (mve_vqrshlq_n_<supf>): Likewise.
11573 (mve_vqrshlq_<supf>): Likewise.
11574 (mve_vqshlq_n_<supf>): Likewise.
11575 (mve_vqshlq_r_<supf>): Likewise.
11576 (mve_vqshlq_<supf>): Likewise.
11577 (mve_vqshluq_n_s): Likewise.
11578 (mve_vqsubq_n_<supf>): Likewise.
11579 (mve_vqsubq_<supf>): Likewise.
11580 (mve_vrhaddq_<supf>): Likewise.
11581 (mve_vrmulhq_<supf>): Likewise.
11582 (mve_vrshlq_n_<supf>): Likewise.
11583 (mve_vrshlq_<supf>): Likewise.
11584 (mve_vrshrq_n_<supf>): Likewise.
11585 (mve_vshlq_n_<supf>): Likewise.
11586 (mve_vshlq_r_<supf>): Likewise.
11587 (mve_vsubq_n_<supf>): Likewise.
11588 (mve_vsubq_<supf>): Likewise.
11589 * config/arm/predicates.md (mve_imm_7): Define predicate to check
11590 the matching constraint Ra.
11591 (mve_imm_selective_upto_8): Define predicate to check the matching
11594 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11595 Mihail Ionescu <mihail.ionescu@arm.com>
11596 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11598 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define
11599 qualifier for binary operands.
11600 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
11601 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
11602 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro.
11603 (vaddlvq_p_u32): Likewise.
11604 (vcmpneq_s8): Likewise.
11605 (vcmpneq_s16): Likewise.
11606 (vcmpneq_s32): Likewise.
11607 (vcmpneq_u8): Likewise.
11608 (vcmpneq_u16): Likewise.
11609 (vcmpneq_u32): Likewise.
11610 (vshlq_s8): Likewise.
11611 (vshlq_s16): Likewise.
11612 (vshlq_s32): Likewise.
11613 (vshlq_u8): Likewise.
11614 (vshlq_u16): Likewise.
11615 (vshlq_u32): Likewise.
11616 (__arm_vaddlvq_p_s32): Define intrinsic.
11617 (__arm_vaddlvq_p_u32): Likewise.
11618 (__arm_vcmpneq_s8): Likewise.
11619 (__arm_vcmpneq_s16): Likewise.
11620 (__arm_vcmpneq_s32): Likewise.
11621 (__arm_vcmpneq_u8): Likewise.
11622 (__arm_vcmpneq_u16): Likewise.
11623 (__arm_vcmpneq_u32): Likewise.
11624 (__arm_vshlq_s8): Likewise.
11625 (__arm_vshlq_s16): Likewise.
11626 (__arm_vshlq_s32): Likewise.
11627 (__arm_vshlq_u8): Likewise.
11628 (__arm_vshlq_u16): Likewise.
11629 (__arm_vshlq_u32): Likewise.
11630 (vaddlvq_p): Define polymorphic variant.
11631 (vcmpneq): Likewise.
11633 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS):
11635 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
11636 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
11637 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern.
11638 (mve_vcmpneq_<supf><mode>): Likewise.
11639 (mve_vshlq_<supf><mode>): Likewise.
11641 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11642 Mihail Ionescu <mihail.ionescu@arm.com>
11643 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11645 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
11646 qualifier for binary operands.
11647 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
11648 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
11649 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
11650 (vcvtq_n_s32_f32): Likewise.
11651 (vcvtq_n_u16_f16): Likewise.
11652 (vcvtq_n_u32_f32): Likewise.
11653 (vcreateq_u8): Likewise.
11654 (vcreateq_u16): Likewise.
11655 (vcreateq_u32): Likewise.
11656 (vcreateq_u64): Likewise.
11657 (vcreateq_s8): Likewise.
11658 (vcreateq_s16): Likewise.
11659 (vcreateq_s32): Likewise.
11660 (vcreateq_s64): Likewise.
11661 (vshrq_n_s8): Likewise.
11662 (vshrq_n_s16): Likewise.
11663 (vshrq_n_s32): Likewise.
11664 (vshrq_n_u8): Likewise.
11665 (vshrq_n_u16): Likewise.
11666 (vshrq_n_u32): Likewise.
11667 (__arm_vcreateq_u8): Define intrinsic.
11668 (__arm_vcreateq_u16): Likewise.
11669 (__arm_vcreateq_u32): Likewise.
11670 (__arm_vcreateq_u64): Likewise.
11671 (__arm_vcreateq_s8): Likewise.
11672 (__arm_vcreateq_s16): Likewise.
11673 (__arm_vcreateq_s32): Likewise.
11674 (__arm_vcreateq_s64): Likewise.
11675 (__arm_vshrq_n_s8): Likewise.
11676 (__arm_vshrq_n_s16): Likewise.
11677 (__arm_vshrq_n_s32): Likewise.
11678 (__arm_vshrq_n_u8): Likewise.
11679 (__arm_vshrq_n_u16): Likewise.
11680 (__arm_vshrq_n_u32): Likewise.
11681 (__arm_vcvtq_n_s16_f16): Likewise.
11682 (__arm_vcvtq_n_s32_f32): Likewise.
11683 (__arm_vcvtq_n_u16_f16): Likewise.
11684 (__arm_vcvtq_n_u32_f32): Likewise.
11685 (vshrq_n): Define polymorphic variant.
11686 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
11688 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
11689 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
11690 * config/arm/constraints.md (Rb): Define constraint to check constant is
11691 in the range of 1 to 8.
11692 (Rf): Define constraint to check constant is in the range of 1 to 32.
11693 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
11694 (mve_vshrq_n_<supf><mode>): Likewise.
11695 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
11696 * config/arm/predicates.md (mve_imm_8): Define predicate to check
11697 the matching constraint Rb.
11698 (mve_imm_32): Define predicate to check the matching constraint Rf.
11700 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11701 Mihail Ionescu <mihail.ionescu@arm.com>
11702 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11704 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
11705 qualifier for binary operands.
11706 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
11707 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
11708 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
11709 * config/arm/arm_mve.h (vsubq_n_f16): Define macro.
11710 (vsubq_n_f32): Likewise.
11711 (vbrsrq_n_f16): Likewise.
11712 (vbrsrq_n_f32): Likewise.
11713 (vcvtq_n_f16_s16): Likewise.
11714 (vcvtq_n_f32_s32): Likewise.
11715 (vcvtq_n_f16_u16): Likewise.
11716 (vcvtq_n_f32_u32): Likewise.
11717 (vcreateq_f16): Likewise.
11718 (vcreateq_f32): Likewise.
11719 (__arm_vsubq_n_f16): Define intrinsic.
11720 (__arm_vsubq_n_f32): Likewise.
11721 (__arm_vbrsrq_n_f16): Likewise.
11722 (__arm_vbrsrq_n_f32): Likewise.
11723 (__arm_vcvtq_n_f16_s16): Likewise.
11724 (__arm_vcvtq_n_f32_s32): Likewise.
11725 (__arm_vcvtq_n_f16_u16): Likewise.
11726 (__arm_vcvtq_n_f32_u32): Likewise.
11727 (__arm_vcreateq_f16): Likewise.
11728 (__arm_vcreateq_f32): Likewise.
11729 (vsubq): Define polymorphic variant.
11730 (vbrsrq): Likewise.
11731 (vcvtq_n): Likewise.
11732 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use
11734 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
11735 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
11736 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
11737 * config/arm/constraints.md (Rd): Define constraint to check constant is
11738 in the range of 1 to 16.
11739 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern.
11740 mve_vbrsrq_n_f<mode>: Likewise.
11741 mve_vcvtq_n_to_f_<supf><mode>: Likewise.
11742 mve_vcreateq_f<mode>: Likewise.
11743 * config/arm/predicates.md (mve_imm_16): Define predicate to check
11744 the matching constraint Rd.
11746 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11747 Mihail Ionescu <mihail.ionescu@arm.com>
11748 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11750 * config/arm/arm-builtins.c (hi_UP): Define mode.
11751 * config/arm/arm.h (IS_VPR_REGNUM): Move.
11752 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
11753 (APSRQ_REGNUM): Modify.
11754 (APSRGE_REGNUM): Modify.
11755 * config/arm/arm_mve.h (vctp16q): Define macro.
11756 (vctp32q): Likewise.
11757 (vctp64q): Likewise.
11758 (vctp8q): Likewise.
11760 (__arm_vctp16q): Define intrinsic.
11761 (__arm_vctp32q): Likewise.
11762 (__arm_vctp64q): Likewise.
11763 (__arm_vctp8q): Likewise.
11764 (__arm_vpnot): Likewise.
11765 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
11767 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
11768 (mve_vpnothi): Likewise.
11770 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11771 Mihail Ionescu <mihail.ionescu@arm.com>
11772 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11774 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
11775 * config/arm/arm_mve.h (vdupq_n_s8): Define macro.
11776 (vdupq_n_s16): Likewise.
11777 (vdupq_n_s32): Likewise.
11778 (vabsq_s8): Likewise.
11779 (vabsq_s16): Likewise.
11780 (vabsq_s32): Likewise.
11781 (vclsq_s8): Likewise.
11782 (vclsq_s16): Likewise.
11783 (vclsq_s32): Likewise.
11784 (vclzq_s8): Likewise.
11785 (vclzq_s16): Likewise.
11786 (vclzq_s32): Likewise.
11787 (vnegq_s8): Likewise.
11788 (vnegq_s16): Likewise.
11789 (vnegq_s32): Likewise.
11790 (vaddlvq_s32): Likewise.
11791 (vaddvq_s8): Likewise.
11792 (vaddvq_s16): Likewise.
11793 (vaddvq_s32): Likewise.
11794 (vmovlbq_s8): Likewise.
11795 (vmovlbq_s16): Likewise.
11796 (vmovltq_s8): Likewise.
11797 (vmovltq_s16): Likewise.
11798 (vmvnq_s8): Likewise.
11799 (vmvnq_s16): Likewise.
11800 (vmvnq_s32): Likewise.
11801 (vrev16q_s8): Likewise.
11802 (vrev32q_s8): Likewise.
11803 (vrev32q_s16): Likewise.
11804 (vqabsq_s8): Likewise.
11805 (vqabsq_s16): Likewise.
11806 (vqabsq_s32): Likewise.
11807 (vqnegq_s8): Likewise.
11808 (vqnegq_s16): Likewise.
11809 (vqnegq_s32): Likewise.
11810 (vcvtaq_s16_f16): Likewise.
11811 (vcvtaq_s32_f32): Likewise.
11812 (vcvtnq_s16_f16): Likewise.
11813 (vcvtnq_s32_f32): Likewise.
11814 (vcvtpq_s16_f16): Likewise.
11815 (vcvtpq_s32_f32): Likewise.
11816 (vcvtmq_s16_f16): Likewise.
11817 (vcvtmq_s32_f32): Likewise.
11818 (vmvnq_u8): Likewise.
11819 (vmvnq_u16): Likewise.
11820 (vmvnq_u32): Likewise.
11821 (vdupq_n_u8): Likewise.
11822 (vdupq_n_u16): Likewise.
11823 (vdupq_n_u32): Likewise.
11824 (vclzq_u8): Likewise.
11825 (vclzq_u16): Likewise.
11826 (vclzq_u32): Likewise.
11827 (vaddvq_u8): Likewise.
11828 (vaddvq_u16): Likewise.
11829 (vaddvq_u32): Likewise.
11830 (vrev32q_u8): Likewise.
11831 (vrev32q_u16): Likewise.
11832 (vmovltq_u8): Likewise.
11833 (vmovltq_u16): Likewise.
11834 (vmovlbq_u8): Likewise.
11835 (vmovlbq_u16): Likewise.
11836 (vrev16q_u8): Likewise.
11837 (vaddlvq_u32): Likewise.
11838 (vcvtpq_u16_f16): Likewise.
11839 (vcvtpq_u32_f32): Likewise.
11840 (vcvtnq_u16_f16): Likewise.
11841 (vcvtmq_u16_f16): Likewise.
11842 (vcvtmq_u32_f32): Likewise.
11843 (vcvtaq_u16_f16): Likewise.
11844 (vcvtaq_u32_f32): Likewise.
11845 (__arm_vdupq_n_s8): Define intrinsic.
11846 (__arm_vdupq_n_s16): Likewise.
11847 (__arm_vdupq_n_s32): Likewise.
11848 (__arm_vabsq_s8): Likewise.
11849 (__arm_vabsq_s16): Likewise.
11850 (__arm_vabsq_s32): Likewise.
11851 (__arm_vclsq_s8): Likewise.
11852 (__arm_vclsq_s16): Likewise.
11853 (__arm_vclsq_s32): Likewise.
11854 (__arm_vclzq_s8): Likewise.
11855 (__arm_vclzq_s16): Likewise.
11856 (__arm_vclzq_s32): Likewise.
11857 (__arm_vnegq_s8): Likewise.
11858 (__arm_vnegq_s16): Likewise.
11859 (__arm_vnegq_s32): Likewise.
11860 (__arm_vaddlvq_s32): Likewise.
11861 (__arm_vaddvq_s8): Likewise.
11862 (__arm_vaddvq_s16): Likewise.
11863 (__arm_vaddvq_s32): Likewise.
11864 (__arm_vmovlbq_s8): Likewise.
11865 (__arm_vmovlbq_s16): Likewise.
11866 (__arm_vmovltq_s8): Likewise.
11867 (__arm_vmovltq_s16): Likewise.
11868 (__arm_vmvnq_s8): Likewise.
11869 (__arm_vmvnq_s16): Likewise.
11870 (__arm_vmvnq_s32): Likewise.
11871 (__arm_vrev16q_s8): Likewise.
11872 (__arm_vrev32q_s8): Likewise.
11873 (__arm_vrev32q_s16): Likewise.
11874 (__arm_vqabsq_s8): Likewise.
11875 (__arm_vqabsq_s16): Likewise.
11876 (__arm_vqabsq_s32): Likewise.
11877 (__arm_vqnegq_s8): Likewise.
11878 (__arm_vqnegq_s16): Likewise.
11879 (__arm_vqnegq_s32): Likewise.
11880 (__arm_vmvnq_u8): Likewise.
11881 (__arm_vmvnq_u16): Likewise.
11882 (__arm_vmvnq_u32): Likewise.
11883 (__arm_vdupq_n_u8): Likewise.
11884 (__arm_vdupq_n_u16): Likewise.
11885 (__arm_vdupq_n_u32): Likewise.
11886 (__arm_vclzq_u8): Likewise.
11887 (__arm_vclzq_u16): Likewise.
11888 (__arm_vclzq_u32): Likewise.
11889 (__arm_vaddvq_u8): Likewise.
11890 (__arm_vaddvq_u16): Likewise.
11891 (__arm_vaddvq_u32): Likewise.
11892 (__arm_vrev32q_u8): Likewise.
11893 (__arm_vrev32q_u16): Likewise.
11894 (__arm_vmovltq_u8): Likewise.
11895 (__arm_vmovltq_u16): Likewise.
11896 (__arm_vmovlbq_u8): Likewise.
11897 (__arm_vmovlbq_u16): Likewise.
11898 (__arm_vrev16q_u8): Likewise.
11899 (__arm_vaddlvq_u32): Likewise.
11900 (__arm_vcvtpq_u16_f16): Likewise.
11901 (__arm_vcvtpq_u32_f32): Likewise.
11902 (__arm_vcvtnq_u16_f16): Likewise.
11903 (__arm_vcvtmq_u16_f16): Likewise.
11904 (__arm_vcvtmq_u32_f32): Likewise.
11905 (__arm_vcvtaq_u16_f16): Likewise.
11906 (__arm_vcvtaq_u32_f32): Likewise.
11907 (__arm_vcvtaq_s16_f16): Likewise.
11908 (__arm_vcvtaq_s32_f32): Likewise.
11909 (__arm_vcvtnq_s16_f16): Likewise.
11910 (__arm_vcvtnq_s32_f32): Likewise.
11911 (__arm_vcvtpq_s16_f16): Likewise.
11912 (__arm_vcvtpq_s32_f32): Likewise.
11913 (__arm_vcvtmq_s16_f16): Likewise.
11914 (__arm_vcvtmq_s32_f32): Likewise.
11915 (vdupq_n): Define polymorphic variant.
11920 (vaddlvq): Likewise.
11921 (vaddvq): Likewise.
11922 (vmovlbq): Likewise.
11923 (vmovltq): Likewise.
11925 (vrev16q): Likewise.
11926 (vrev32q): Likewise.
11927 (vqabsq): Likewise.
11928 (vqnegq): Likewise.
11929 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
11930 (UNOP_SNONE_NONE): Likewise.
11931 (UNOP_UNONE_UNONE): Likewise.
11932 (UNOP_UNONE_NONE): Likewise.
11933 * config/arm/constraints.md (e): Define new constriant to allow only
11935 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
11936 (mve_vnegq_s<mode>): Likewise.
11937 (mve_vmvnq_<supf><mode>): Likewise.
11938 (mve_vdupq_n_<supf><mode>): Likewise.
11939 (mve_vclzq_<supf><mode>): Likewise.
11940 (mve_vclsq_s<mode>): Likewise.
11941 (mve_vaddvq_<supf><mode>): Likewise.
11942 (mve_vabsq_s<mode>): Likewise.
11943 (mve_vrev32q_<supf><mode>): Likewise.
11944 (mve_vmovltq_<supf><mode>): Likewise.
11945 (mve_vmovlbq_<supf><mode>): Likewise.
11946 (mve_vcvtpq_<supf><mode>): Likewise.
11947 (mve_vcvtnq_<supf><mode>): Likewise.
11948 (mve_vcvtmq_<supf><mode>): Likewise.
11949 (mve_vcvtaq_<supf><mode>): Likewise.
11950 (mve_vrev16q_<supf>v16qi): Likewise.
11951 (mve_vaddlvq_<supf>v4si): Likewise.
11953 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11955 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in
11957 * tree-sra.c (create_access_replacement): Fix up duplicated word issue
11959 * read-rtl-function.c (find_param_by_name,
11960 function_reader::parse_enum_value, function_reader::get_insn_by_uid):
11962 * spellcheck.c (get_edit_distance_cutoff): Likewise.
11963 * tree-data-ref.c (create_ifn_alias_checks): Likewise.
11964 * tree.def (SWITCH_EXPR): Likewise.
11965 * selftest.c (assert_str_contains): Likewise.
11966 * ipa-param-manipulation.h (class ipa_param_body_adjustments):
11968 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise.
11969 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise.
11970 * langhooks.h (struct lang_hooks_for_decls): Likewise.
11971 * ipa-prop.h (struct ipa_param_descriptor): Likewise.
11972 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store):
11974 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise.
11975 * tree-ssa-reassoc.c (reassociate_bb): Likewise.
11976 * tree.c (component_ref_size): Likewise.
11977 * hsa-common.c (hsa_init_compilation_unit_data): Likewise.
11978 * gimple-ssa-sprintf.c (get_string_length, format_string,
11979 format_directive): Likewise.
11980 * omp-grid.c (grid_process_kernel_body_copy): Likewise.
11981 * input.c (string_concat_db::get_string_concatenation,
11982 test_lexer_string_locations_ucn4): Likewise.
11983 * cfgexpand.c (pass_expand::execute): Likewise.
11984 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds,
11985 maybe_diag_overlap): Likewise.
11986 * rtl.c (RTX_CODE_HWINT_P_1): Likewise.
11987 * shrink-wrap.c (spread_components): Likewise.
11988 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse):
11990 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
11992 * dwarf2out.c (dwarf2out_early_finish): Likewise.
11993 * gimple-ssa-store-merging.c: Likewise.
11994 * ira-costs.c (record_operand_costs): Likewise.
11995 * tree-vect-loop.c (vectorizable_reduction): Likewise.
11996 * target.def (dispatch): Likewise.
11997 (validate_dims, gen_ccmp_first): Fix up duplicated word issue
11998 in documentation text.
11999 * doc/tm.texi: Regenerated.
12000 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up
12001 duplicated word issue in a comment.
12002 * config/i386/i386.c (ix86_test_loading_unspec): Likewise.
12003 * config/i386/i386-features.c (remove_partial_avx_dependency):
12005 * config/msp430/msp430.c (msp430_select_section): Likewise.
12006 * config/gcn/gcn-run.c (load_image): Likewise.
12007 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise.
12008 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise.
12009 * config/aarch64/falkor-tag-collision-avoidance.c
12010 (single_dest_per_chain): Likewise.
12011 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise.
12012 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise.
12013 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise.
12014 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant):
12016 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise.
12017 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise.
12018 * config/rs6000/rs6000-logue.c
12019 (rs6000_emit_probe_stack_range_stack_clash): Likewise.
12020 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise.
12021 Fix various other issues in the comment.
12023 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
12025 * config/arm/t-rmprofile: create new multilib for
12026 armv8.1-m.main+mve hard float and reuse v8-m.main ones for
12029 2020-03-17 Jakub Jelinek <jakub@redhat.com>
12031 PR tree-optimization/94015
12032 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the
12033 function where EXP is address of the bytes being stored rather than
12034 the bytes themselves into count_nonzero_bytes_addr. Punt on zero
12035 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs.
12036 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before
12037 calling native_encode_expr if host or target doesn't have 8-bit
12038 chars. Formatting fixes.
12039 (count_nonzero_bytes_addr): New function.
12041 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
12042 Mihail Ionescu <mihail.ionescu@arm.com>
12043 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12045 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define.
12046 (UNOP_SNONE_NONE_QUALIFIERS): Likewise.
12047 (UNOP_SNONE_IMM_QUALIFIERS): Likewise.
12048 (UNOP_UNONE_NONE_QUALIFIERS): Likewise.
12049 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise.
12050 (UNOP_UNONE_IMM_QUALIFIERS): Likewise.
12051 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro.
12052 (vmvnq_n_s32): Likewise.
12053 (vrev64q_s8): Likewise.
12054 (vrev64q_s16): Likewise.
12055 (vrev64q_s32): Likewise.
12056 (vcvtq_s16_f16): Likewise.
12057 (vcvtq_s32_f32): Likewise.
12058 (vrev64q_u8): Likewise.
12059 (vrev64q_u16): Likewise.
12060 (vrev64q_u32): Likewise.
12061 (vmvnq_n_u16): Likewise.
12062 (vmvnq_n_u32): Likewise.
12063 (vcvtq_u16_f16): Likewise.
12064 (vcvtq_u32_f32): Likewise.
12065 (__arm_vmvnq_n_s16): Define intrinsic.
12066 (__arm_vmvnq_n_s32): Likewise.
12067 (__arm_vrev64q_s8): Likewise.
12068 (__arm_vrev64q_s16): Likewise.
12069 (__arm_vrev64q_s32): Likewise.
12070 (__arm_vrev64q_u8): Likewise.
12071 (__arm_vrev64q_u16): Likewise.
12072 (__arm_vrev64q_u32): Likewise.
12073 (__arm_vmvnq_n_u16): Likewise.
12074 (__arm_vmvnq_n_u32): Likewise.
12075 (__arm_vcvtq_s16_f16): Likewise.
12076 (__arm_vcvtq_s32_f32): Likewise.
12077 (__arm_vcvtq_u16_f16): Likewise.
12078 (__arm_vcvtq_u32_f32): Likewise.
12079 (vrev64q): Define polymorphic variant.
12080 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
12081 (UNOP_SNONE_NONE): Likewise.
12082 (UNOP_SNONE_IMM): Likewise.
12083 (UNOP_UNONE_UNONE): Likewise.
12084 (UNOP_UNONE_NONE): Likewise.
12085 (UNOP_UNONE_IMM): Likewise.
12086 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern.
12087 (mve_vcvtq_from_f_<supf><mode>): Likewise.
12088 (mve_vmvnq_n_<supf><mode>): Likewise.
12090 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
12091 Mihail Ionescu <mihail.ionescu@arm.com>
12092 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12094 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
12095 (UNOP_NONE_SNONE_QUALIFIERS): Likewise.
12096 (UNOP_NONE_UNONE_QUALIFIERS): Likewise.
12097 * config/arm/arm_mve.h (vrndxq_f16): Define macro.
12098 (vrndxq_f32): Likewise.
12099 (vrndq_f16) Likewise.
12100 (vrndq_f32): Likewise.
12101 (vrndpq_f16): Likewise.
12102 (vrndpq_f32): Likewise.
12103 (vrndnq_f16): Likewise.
12104 (vrndnq_f32): Likewise.
12105 (vrndmq_f16): Likewise.
12106 (vrndmq_f32): Likewise.
12107 (vrndaq_f16): Likewise.
12108 (vrndaq_f32): Likewise.
12109 (vrev64q_f16): Likewise.
12110 (vrev64q_f32): Likewise.
12111 (vnegq_f16): Likewise.
12112 (vnegq_f32): Likewise.
12113 (vdupq_n_f16): Likewise.
12114 (vdupq_n_f32): Likewise.
12115 (vabsq_f16): Likewise.
12116 (vabsq_f32): Likewise.
12117 (vrev32q_f16): Likewise.
12118 (vcvttq_f32_f16): Likewise.
12119 (vcvtbq_f32_f16): Likewise.
12120 (vcvtq_f16_s16): Likewise.
12121 (vcvtq_f32_s32): Likewise.
12122 (vcvtq_f16_u16): Likewise.
12123 (vcvtq_f32_u32): Likewise.
12124 (__arm_vrndxq_f16): Define intrinsic.
12125 (__arm_vrndxq_f32): Likewise.
12126 (__arm_vrndq_f16): Likewise.
12127 (__arm_vrndq_f32): Likewise.
12128 (__arm_vrndpq_f16): Likewise.
12129 (__arm_vrndpq_f32): Likewise.
12130 (__arm_vrndnq_f16): Likewise.
12131 (__arm_vrndnq_f32): Likewise.
12132 (__arm_vrndmq_f16): Likewise.
12133 (__arm_vrndmq_f32): Likewise.
12134 (__arm_vrndaq_f16): Likewise.
12135 (__arm_vrndaq_f32): Likewise.
12136 (__arm_vrev64q_f16): Likewise.
12137 (__arm_vrev64q_f32): Likewise.
12138 (__arm_vnegq_f16): Likewise.
12139 (__arm_vnegq_f32): Likewise.
12140 (__arm_vdupq_n_f16): Likewise.
12141 (__arm_vdupq_n_f32): Likewise.
12142 (__arm_vabsq_f16): Likewise.
12143 (__arm_vabsq_f32): Likewise.
12144 (__arm_vrev32q_f16): Likewise.
12145 (__arm_vcvttq_f32_f16): Likewise.
12146 (__arm_vcvtbq_f32_f16): Likewise.
12147 (__arm_vcvtq_f16_s16): Likewise.
12148 (__arm_vcvtq_f32_s32): Likewise.
12149 (__arm_vcvtq_f16_u16): Likewise.
12150 (__arm_vcvtq_f32_u32): Likewise.
12151 (vrndxq): Define polymorphic variants.
12153 (vrndpq): Likewise.
12154 (vrndnq): Likewise.
12155 (vrndmq): Likewise.
12156 (vrndaq): Likewise.
12157 (vrev64q): Likewise.
12160 (vrev32q): Likewise.
12161 (vcvtbq_f32): Likewise.
12162 (vcvttq_f32): Likewise.
12164 * config/arm/arm_mve_builtins.def (VAR2): Define.
12166 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
12167 (mve_vrndq_f<mode>): Likewise.
12168 (mve_vrndpq_f<mode>): Likewise.
12169 (mve_vrndnq_f<mode>): Likewise.
12170 (mve_vrndmq_f<mode>): Likewise.
12171 (mve_vrndaq_f<mode>): Likewise.
12172 (mve_vrev64q_f<mode>): Likewise.
12173 (mve_vnegq_f<mode>): Likewise.
12174 (mve_vdupq_n_f<mode>): Likewise.
12175 (mve_vabsq_f<mode>): Likewise.
12176 (mve_vrev32q_fv8hf): Likewise.
12177 (mve_vcvttq_f32_f16v4sf): Likewise.
12178 (mve_vcvtbq_f32_f16v4sf): Likewise.
12179 (mve_vcvtq_to_f_<supf><mode>): Likewise.
12181 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12182 Mihail Ionescu <mihail.ionescu@arm.com>
12183 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12185 * config/arm/arm-builtins.c (CF): Define mve_builtin_data.
12187 (ARM_BUILTIN_MVE_PATTERN_START): Define.
12188 (arm_init_mve_builtins): Define function.
12189 (arm_init_builtins): Add TARGET_HAVE_MVE check.
12190 (arm_expand_builtin_1): Check the range of fcode.
12191 (arm_expand_mve_builtin): Define function to expand MVE builtins.
12192 (arm_expand_builtin): Check the range of fcode.
12193 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point
12195 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace.
12196 (vst4q_s8): Define macro.
12197 (vst4q_s16): Likewise.
12198 (vst4q_s32): Likewise.
12199 (vst4q_u8): Likewise.
12200 (vst4q_u16): Likewise.
12201 (vst4q_u32): Likewise.
12202 (vst4q_f16): Likewise.
12203 (vst4q_f32): Likewise.
12204 (__arm_vst4q_s8): Define inline builtin.
12205 (__arm_vst4q_s16): Likewise.
12206 (__arm_vst4q_s32): Likewise.
12207 (__arm_vst4q_u8): Likewise.
12208 (__arm_vst4q_u16): Likewise.
12209 (__arm_vst4q_u32): Likewise.
12210 (__arm_vst4q_f16): Likewise.
12211 (__arm_vst4q_f32): Likewise.
12212 (__ARM_mve_typeid): Define macro with MVE types.
12213 (__ARM_mve_coerce): Define macro with _Generic feature.
12214 (vst4q): Define polymorphic variant for different vst4q builtins.
12215 * config/arm/arm_mve_builtins.def: New file.
12216 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI
12218 * config/arm/mve.md (MVE_VLD_ST): Define iterator.
12219 (unspec): Define unspec.
12220 (mve_vst4q<mode>): Define RTL pattern.
12221 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI
12223 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes
12225 (define_split): Allow OI mode split for MVE after reload.
12226 (define_split): Allow XI mode split for MVE after reload.
12227 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def.
12228 (arm-builtins.o): Likewise.
12230 2020-03-17 Christophe Lyon <christophe.lyon@linaro.org>
12232 * c-typeck.c (process_init_element): Handle constructor_type with
12233 type size represented by POLY_INT_CST.
12235 2020-03-17 Jakub Jelinek <jakub@redhat.com>
12237 PR tree-optimization/94187
12238 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if
12239 nchars - offset < nbytes.
12241 PR middle-end/94189
12242 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would
12243 emit a warning if it was enabled and don't depend on TREE_NO_WARNING
12244 for code-generation.
12246 2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
12249 * lra-spills.c (remove_pseudos): Do not reuse insn alternative
12250 after changing memory subreg.
12252 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12253 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12255 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
12256 emulator calls for dobule precision arithmetic operations for MVE.
12258 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12259 Mihail Ionescu <mihail.ionescu@arm.com>
12260 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12262 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
12263 feature bit is on and -mfpu=auto is passed as compiler option, do not
12264 generate error on not finding any matching fpu. Because in this case
12265 fpu is not required.
12266 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
12267 enabled for MVE and also for all VFP extensions.
12268 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
12270 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
12271 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
12272 along with feature bits mve_float.
12273 (mve): Modify add options in armv8.1-m.main arch for MVE.
12274 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with
12276 * config/arm/arm.c (use_return_insn): Replace the
12277 check with TARGET_VFP_BASE.
12278 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
12280 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
12281 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
12283 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
12284 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
12286 (arm_compute_frame_layout): Likewise.
12287 (arm_save_coproc_regs): Likewise.
12288 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
12290 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
12291 with equivalent macro TARGET_VFP_BASE.
12292 (arm_expand_epilogue_apcs_frame): Likewise.
12293 (arm_expand_epilogue): Likewise.
12294 (arm_conditional_register_usage): Likewise.
12295 (arm_declare_function_name): Add check to skip printing .fpu directive
12296 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
12298 * config/arm/arm.h (TARGET_VFP_BASE): Define.
12299 * config/arm/arm.md (arch): Add "mve" to arch.
12300 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
12301 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
12302 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
12303 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR
12305 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
12306 to not allow for MVE.
12307 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
12309 (VUNSPEC_GET_FPSCR): Define.
12310 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
12311 instructions which move to general-purpose Register from Floating-point
12312 Special register and vice-versa.
12313 (thumb2_movhi_fp16): Likewise.
12314 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
12315 with MCR and MRC instructions which set and get Floating-point Status
12316 and Control Register (FPSCR).
12317 (movdi_vfp): Modify pattern to enable Single-precision scalar float move
12319 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
12320 float move patterns in MVE.
12321 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
12322 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
12323 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
12324 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
12325 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
12326 TARGET_VFP_BASE check.
12327 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
12328 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
12330 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
12331 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
12335 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12336 Mihail Ionescu <mihail.ionescu@arm.com>
12337 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12339 * config.gcc (arm_mve.h): Include mve intrinsics header file.
12340 * config/arm/aout.h (p0): Add new register name for MVE predicated
12342 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
12343 common to Neon and MVE.
12344 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
12345 (arm_init_simd_builtin_types): Disable poly types for MVE.
12346 (arm_init_neon_builtins): Move a check to arm_init_builtins function.
12347 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
12348 ARM_BUILTIN_NEON_LANE_CHECK.
12349 (mve_dereference_pointer): Add function.
12350 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
12352 (arm_expand_neon_builtin): Moved to arm_expand_builtin function.
12353 (arm_expand_builtin): Moved from arm_expand_neon_builtin function.
12354 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
12355 with floating point enabled.
12356 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
12357 simd_immediate_valid_for_move.
12358 (simd_immediate_valid_for_move): Renamed from
12359 neon_immediate_valid_for_move function.
12360 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
12361 error if vfpv2 feature bit is disabled and mve feature bit is also
12362 disabled for HARD_FLOAT_ABI.
12363 (use_return_insn): Check to not push VFP regs for MVE.
12364 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
12366 (aapcs_vfp_allocate_return_reg): Likewise.
12367 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
12368 address operand for MVE.
12369 (arm_rtx_costs_internal): MVE check to determine cost of rtx.
12370 (neon_valid_immediate): Rename to simd_valid_immediate.
12371 (simd_valid_immediate): Rename from neon_valid_immediate.
12372 (simd_valid_immediate): MVE check on size of vector is 128 bits.
12373 (neon_immediate_valid_for_move): Rename to
12374 simd_immediate_valid_for_move.
12375 (simd_immediate_valid_for_move): Rename from
12376 neon_immediate_valid_for_move.
12377 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
12379 (neon_make_constant): Modify call to neon_valid_immediate function.
12380 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
12382 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
12383 (arm_compute_frame_layout): Calculate space for saved VFP registers for
12385 (arm_save_coproc_regs): Save coproc registers for MVE.
12386 (arm_print_operand): Add case 'E' to print memory operands for MVE.
12387 (arm_print_operand_address): Check to print register number for MVE.
12388 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
12389 (arm_modes_tieable_p): Check to allow structure mode for MVE.
12390 (arm_regno_class): Add VPR_REGNUM check.
12391 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
12393 (arm_expand_epilogue): MVE check for enabling pop instructions in
12395 (arm_print_asm_arch_directives): Modify function to disable print of
12396 .arch_extension "mve" and "fp" for cases where MVE is enabled with
12398 (arm_vector_mode_supported_p): Check for modes available in MVE interger
12399 and MVE floating point.
12400 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
12402 (arm_conditional_register_usage): Enable usage of conditional regsiter
12404 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
12405 (arm_declare_function_name): Modify function to disable print of
12406 .arch_extension "mve" and "fp" for cases where MVE is enabled with
12408 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
12409 when target general registers are required.
12410 (TARGET_HAVE_MVE_FLOAT): Likewise.
12411 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
12413 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
12414 which indicate this is not available for across function calls.
12415 (FIRST_PSEUDO_REGISTER): Modify.
12416 (VALID_MVE_MODE): Define valid MVE mode.
12417 (VALID_MVE_SI_MODE): Define valid MVE SI mode.
12418 (VALID_MVE_SF_MODE): Define valid MVE SF mode.
12419 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
12420 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
12422 (IS_VPR_REGNUM): Macro to check for VPR_REG register.
12423 (REG_ALLOC_ORDER): Add VPR_REGNUM entry.
12424 (enum reg_class): Add VPR_REG entry.
12425 (REG_CLASS_NAMES): Add VPR_REG entry.
12426 * config/arm/arm.md (VPR_REGNUM): Define.
12427 (conds): Check is_mve_type attrbiute to differentiate "conditional" and
12428 "unconditional" instructions.
12429 (arm_movsf_soft_insn): Modify RTL to not allow for MVE.
12430 (movdf_soft_insn): Modify RTL to not allow for MVE.
12431 (vfp_pop_multiple_with_writeback): Enable for MVE.
12432 (include "mve.md"): Include mve.md file.
12433 * config/arm/arm_mve.h: Add MVE intrinsics head file.
12434 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
12435 for vector predicated operands.
12436 * config/arm/iterators.md (VNIM1): Define.
12437 (VNINOTM1): Define.
12438 (VHFBF_split): Define
12439 * config/arm/mve.md: New file.
12440 (mve_mov<mode>): Define RTL for move, store and load in MVE.
12441 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
12443 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with
12444 simd_immediate_valid_for_move.
12445 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
12446 is common to MVE and NEON to vec-common.md file.
12447 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
12448 * config/arm/predicates.md (vpr_register_operand): Define.
12449 * config/arm/t-arm: Add mve.md file.
12450 * config/arm/types.md (mve_move): Add MVE instructions mve_move to
12452 (mve_store): Add MVE instructions mve_store to attribute "type".
12453 (mve_load): Add MVE instructions mve_load to attribute "type".
12454 (is_mve_type): Define attribute.
12455 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
12456 standard move patterns in MVE along with NEON and IWMMXT with mode
12458 (mov<mode>): Modify RTL expand to support standard move patterns in NEON
12459 and IWMMXT with mode iterator V8HF.
12460 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in
12462 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
12463 simd_immediate_valid_for_move.
12466 2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
12469 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
12470 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
12472 * config/i386/predicates.md (ext_sse_reg_operand): Removed.
12474 2020-03-16 Jakub Jelinek <jakub@redhat.com>
12477 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
12480 PR tree-optimization/94166
12481 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
12482 as secondary comparison key.
12484 2020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com>
12486 PR tree-optimization/94125
12487 * tree-loop-distribution.c
12488 (loop_distribution::break_alias_scc_partitions): Update post order
12489 number for merged scc.
12491 2020-03-15 H.J. Lu <hongjiu.lu@intel.com>
12494 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
12496 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
12497 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
12498 and ext_sse_reg_operand check.
12500 2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
12502 * common.opt: Avoid redundancy in the help text.
12503 * config/arc/arc.opt: Likewise.
12504 * config/cr16/cr16.opt: Likewise.
12506 2020-03-14 Jakub Jelinek <jakub@redhat.com>
12508 PR middle-end/93566
12509 * tree-nested.c (convert_nonlocal_omp_clauses,
12510 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
12511 with C/C++ array sections.
12513 2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
12516 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
12517 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
12520 2020-03-14 Jakub Jelinek <jakub@redhat.com>
12522 * gimple-fold.c (gimple_fold_builtin_strncpy): Change
12523 "a an" to "an" in a comment.
12524 * hsa-common.h (is_a_helper): Likewise.
12525 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
12526 * config/arc/arc.c (arc600_corereg_hazard): Likewise.
12527 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.
12529 2020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com>
12532 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a
12533 64-bit value by 64 bits (UB).
12535 2020-03-13 Vladimir Makarov <vmakarov@redhat.com>
12537 PR rtl-optimization/92303
12538 * lra-spills.c (remove_pseudos): Try to simplify memory subreg.
12540 2020-03-13 Segher Boessenkool <segher@kernel.crashing.org>
12542 PR rtl-optimization/94148
12543 PR rtl-optimization/94042
12544 * df-core.c (BB_LAST_CHANGE_AGE): Delete.
12545 (df_worklist_propagate_forward): New parameter last_change_age, use
12546 that instead of bb->aux.
12547 (df_worklist_propagate_backward): Ditto.
12548 (df_worklist_dataflow_doublequeue): Use a local array last_change_age.
12550 2020-03-13 Richard Biener <rguenther@suse.de>
12552 PR tree-optimization/94163
12553 * tree-ssa-pre.c (create_expression_by_pieces): Check
12554 whether alignment would be zero.
12556 2020-03-13 Martin Liska <mliska@suse.cz>
12559 * lto-wrapper.c (run_gcc): Use concat for appending
12560 to collect_gcc_options.
12562 2020-03-13 Jakub Jelinek <jakub@redhat.com>
12565 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
12566 instead of GEN_INT.
12568 2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
12571 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
12572 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
12573 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
12574 TARGET_AVX512VL and ext_sse_reg_operand check.
12576 2020-03-13 Bu Le <bule1@huawei.com>
12579 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=)
12580 (-param=aarch64-double-recp-precision=): New options.
12581 * doc/invoke.texi: Document them.
12582 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them
12583 instead of hard-coding the choice of 1 for float and 2 for double.
12585 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
12587 PR rtl-optimization/94119
12588 * resource.h (clear_hashed_info_until_next_barrier): Declare.
12589 * resource.c (clear_hashed_info_until_next_barrier): New function.
12590 * reorg.c (add_to_delay_list): Fix formatting.
12591 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on
12592 the next instruction after removing a BARRIER.
12594 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
12596 PR middle-end/92071
12597 * expmed.c (store_integral_bit_field): For fields larger than a word,
12598 call extract_bit_field on the value if the mode is BLKmode. Remove
12599 specific path for big-endian targets and tidy things up a little bit.
12601 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
12603 PR rtl-optimization/90275
12604 * cse.c (cse_insn): Delete no-op register moves too.
12606 2020-03-12 Darius Galis <darius.galis@cyberthorstudios.com>
12608 * config/rx/rx.md (CTRLREG_CPEN): Remove.
12609 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support.
12611 2020-03-12 Richard Biener <rguenther@suse.de>
12613 PR tree-optimization/94103
12614 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type
12615 punning when the mode precision is not sufficient.
12617 2020-03-12 H.J. Lu <hongjiu.lu@intel.com>
12620 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
12621 MODE_V1DF and MODE_V2SF.
12622 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
12623 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
12626 2020-03-12 Jakub Jelinek <jakub@redhat.com>
12628 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
12629 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
12630 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
12631 * doc/tm.texi: Regenerated.
12633 PR tree-optimization/94130
12634 * tree-ssa-dse.c: Include gimplify.h.
12635 (increment_start_addr): If stmt has lhs, drop the lhs from call and
12636 set it after the call to the original value of the first argument.
12638 (decrement_count): Formatting fix.
12640 2020-03-11 Delia Burduv <delia.burduv@arm.com>
12642 * config/arm/arm-builtins.c
12643 (arm_init_simd_builtin_scalar_types): New.
12644 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type.
12645 (vld2q_bf16): Used new builtin type.
12646 (vld3_bf16): Used new builtin type.
12647 (vld3q_bf16): Used new builtin type.
12648 (vld4_bf16): Used new builtin type.
12649 (vld4q_bf16): Used new builtin type.
12650 (vld2_dup_bf16): Used new builtin type.
12651 (vld2q_dup_bf16): Used new builtin type.
12652 (vld3_dup_bf16): Used new builtin type.
12653 (vld3q_dup_bf16): Used new builtin type.
12654 (vld4_dup_bf16): Used new builtin type.
12655 (vld4q_dup_bf16): Used new builtin type.
12657 2020-03-11 Jakub Jelinek <jakub@redhat.com>
12660 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
12661 at the start to switch to data section. Don't print extra newline if
12662 .globl directive has not been emitted.
12664 2020-03-11 Richard Biener <rguenther@suse.de>
12666 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]):
12669 2020-03-11 Eric Botcazou <ebotcazou@adacore.com>
12671 PR middle-end/93961
12672 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields
12673 whose type is a qualified union.
12675 2020-03-11 Jakub Jelinek <jakub@redhat.com>
12678 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
12679 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
12682 * value-prof.c (dump_histogram_value): Use abs_hwi instead of
12684 (get_nth_most_common_value): Use abs_hwi instead of abs.
12686 PR middle-end/94111
12687 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
12688 is rvc_normal, otherwise use real_to_decimal to print the number to
12691 PR tree-optimization/94114
12692 * tree-loop-distribution.c (generate_memset_builtin): Call
12693 rewrite_to_non_trapping_overflow even on mem.
12694 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
12697 2020-03-10 Jeff Law <law@redhat.com>
12699 * config/bfin/bfin.md (movsi_insv): Add length attribute.
12701 2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
12704 * config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check
12705 NAN and SIGNED_ZEROR for smax/smin.
12707 2020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
12710 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
12711 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments.
12713 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
12715 * loop-iv.c (find_simple_exit): Make it static.
12716 * cfgloop.h: Remove the corresponding prototype.
12718 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
12720 * ddg.c (create_ddg): Fix intendation.
12721 (set_recurrence_length): Likewise.
12722 (create_ddg_all_sccs): Likewise.
12724 2020-03-10 Jakub Jelinek <jakub@redhat.com>
12727 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with
12728 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len
12731 2020-03-09 Jason Merrill <jason@redhat.com>
12733 * gdbinit.in (pgs): Fix typo in documentation.
12735 2020-03-09 Vladimir Makarov <vmakarov@redhat.com>
12739 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
12741 PR rtl-optimization/93564
12742 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
12743 do not honor reg alloc order.
12745 2020-03-09 Andrew Pinski <apinski@marvell.com>
12747 PR inline-asm/94095
12748 * doc/extend.texi (x86 Operand Modifiers): Fix column
12751 2020-03-09 Martin Liska <mliska@suse.cz>
12754 * config/rs6000/rs6000.c (rs6000_option_override_internal):
12755 Remove set of str_align_loops and str_align_jumps as these
12756 should be set in previous 2 conditions in the function.
12758 2020-03-09 Jakub Jelinek <jakub@redhat.com>
12760 PR rtl-optimization/94045
12761 * params.opt (-param=max-find-base-term-values=): New option.
12762 * alias.c (find_base_term): Add cut-off for number of visited VALUEs
12763 in a single toplevel find_base_term call.
12765 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
12768 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define.
12769 * config/aarch64/aarch64-simd.md
12770 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul.
12771 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise.
12772 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics.
12773 * config/aarch64/arm_neon.h:
12774 (vmlal_lane_s16): Expand using intrinsics rather than inline asm.
12775 (vmlal_lane_u16): Likewise.
12776 (vmlal_lane_s32): Likewise.
12777 (vmlal_lane_u32): Likewise.
12778 (vmlal_laneq_s16): Likewise.
12779 (vmlal_laneq_u16): Likewise.
12780 (vmlal_laneq_s32): Likewise.
12781 (vmlal_laneq_u32): Likewise.
12782 (vmull_lane_s16): Likewise.
12783 (vmull_lane_u16): Likewise.
12784 (vmull_lane_s32): Likewise.
12785 (vmull_lane_u32): Likewise.
12786 (vmull_laneq_s16): Likewise.
12787 (vmull_laneq_u16): Likewise.
12788 (vmull_laneq_s32): Likewise.
12789 (vmull_laneq_u32): Likewise.
12790 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul.
12793 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
12795 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
12796 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
12797 (aarch64_mls_elt<mode>): Likewise.
12798 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
12799 (aarch64_fma4_elt<mode>): Likewise.
12800 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
12801 (aarch64_fma4_elt_to_64v2df): Likewise.
12802 (aarch64_fnma4_elt<mode>): Likewise.
12803 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
12804 (aarch64_fnma4_elt_to_64v2df): Likewise.
12806 2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
12808 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
12809 Specify movprfx attribute.
12810 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
12812 2020-03-06 David Edelsohn <dje.gcc@gmail.com>
12815 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for
12817 (TARGET_NO_FP_IN_TOC): Same.
12818 * config/rs6000/aix71.h: Same.
12819 * config/rs6000/aix72.h: Same.
12821 2020-03-06 Andrew Pinski <apinski@marvell.com>
12822 Jeff Law <law@redhat.com>
12824 PR rtl-optimization/93996
12825 * haifa-sched.c (remove_notes): Be more careful when adding
12828 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12830 * config/arm/arm_neon.h (vld2_bf16): New.
12836 (vld2_dup_bf16): New.
12837 (vld2q_dup_bf16): New.
12838 (vld3_dup_bf16): New.
12839 (vld3q_dup_bf16): New.
12840 (vld4_dup_bf16): New.
12841 (vld4q_dup_bf16): New.
12842 * config/arm/arm_neon_builtins.def
12843 (vld2): Changed to VAR13 and added v4bf, v8bf
12844 (vld2_dup): Changed to VAR8 and added v4bf, v8bf
12845 (vld3): Changed to VAR13 and added v4bf, v8bf
12846 (vld3_dup): Changed to VAR8 and added v4bf, v8bf
12847 (vld4): Changed to VAR13 and added v4bf, v8bf
12848 (vld4_dup): Changed to VAR8 and added v4bf, v8bf
12849 * config/arm/iterators.md (VDXBF2): New iterator.
12850 *config/arm/neon.md (neon_vld2): Use new iterators.
12851 (neon_vld2_dup<mode): Use new iterators.
12852 (neon_vld3<mode>): Likewise.
12853 (neon_vld3qa<mode>): Likewise.
12854 (neon_vld3qb<mode>): Likewise.
12855 (neon_vld3_dup<mode>): Likewise.
12856 (neon_vld4<mode>): Likewise.
12857 (neon_vld4qa<mode>): Likewise.
12858 (neon_vld4qb<mode>): Likewise.
12859 (neon_vld4_dup<mode>): Likewise.
12860 (neon_vld2_dupv8bf): New.
12861 (neon_vld3_dupv8bf): Likewise.
12862 (neon_vld4_dupv8bf): Likewise.
12864 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12866 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef.
12867 (bfloat16x8x2_t): New typedef.
12868 (bfloat16x4x3_t): New typedef.
12869 (bfloat16x8x3_t): New typedef.
12870 (bfloat16x4x4_t): New typedef.
12871 (bfloat16x8x4_t): New typedef.
12878 * config/arm/arm-builtins.c (v2bf_UP): Define.
12880 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype.
12881 * config/arm/arm-modes.def (V2BF): New mode.
12882 * config/arm/arm-simd-builtin-types.def
12883 (Bfloat16x2_t): New entry.
12884 * config/arm/arm_neon_builtins.def
12885 (vst2): Changed to VAR13 and added v4bf, v8bf
12886 (vst3): Changed to VAR13 and added v4bf, v8bf
12887 (vst4): Changed to VAR13 and added v4bf, v8bf
12888 * config/arm/iterators.md (VDXBF): New iterator.
12889 (VQ2BF): New iterator.
12890 *config/arm/neon.md (neon_vst2<mode>): Used new iterators.
12891 (neon_vst2<mode>): Used new iterators.
12892 (neon_vst3<mode>): Used new iterators.
12893 (neon_vst3<mode>): Used new iterators.
12894 (neon_vst3qa<mode>): Used new iterators.
12895 (neon_vst3qb<mode>): Used new iterators.
12896 (neon_vst4<mode>): Used new iterators.
12897 (neon_vst4<mode>): Used new iterators.
12898 (neon_vst4qa<mode>): Used new iterators.
12899 (neon_vst4qb<mode>): Used new iterators.
12901 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12903 * config/aarch64/aarch64-simd-builtins.def
12904 (bfcvtn): New built-in function.
12905 (bfcvtn_q): New built-in function.
12906 (bfcvtn2): New built-in function.
12907 (bfcvt): New built-in function.
12908 * config/aarch64/aarch64-simd.md
12909 (aarch64_bfcvtn<q><mode>): New pattern.
12910 (aarch64_bfcvtn2v8bf): New pattern.
12911 (aarch64_bfcvtbf): New pattern.
12912 * config/aarch64/arm_bf16.h (float32_t): New typedef.
12913 (vcvth_bf16_f32): New intrinsic.
12914 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic.
12915 (vcvtq_low_bf16_f32): New intrinsic.
12916 (vcvtq_high_bf16_f32): New intrinsic.
12917 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator.
12918 (UNSPEC_BFCVTN): New UNSPEC.
12919 (UNSPEC_BFCVTN2): New UNSPEC.
12920 (UNSPEC_BFCVT): New UNSPEC.
12921 * config/arm/types.md (bf_cvt): New type.
12923 2020-03-06 Andreas Krebbel <krebbel@linux.ibm.com>
12925 * config/s390/s390.md ("tabort"): Get rid of two consecutive
12926 blanks in format string.
12928 2020-03-05 H.J. Lu <hongjiu.lu@intel.com>
12932 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype.
12933 * config/i386/i386.c (ix86_get_ssemov): New function.
12934 (ix86_output_ssemov): Likewise.
12935 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call
12936 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL
12938 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV.
12939 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV.
12940 Remove ext_sse_reg_operand and TARGET_AVX512VL check.
12941 (*movti_internal): Likewise.
12942 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV.
12944 2020-03-05 Jeff Law <law@redhat.com>
12946 PR tree-optimization/91890
12947 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument.
12948 Use gimple_or_expr_nonartificial_location.
12949 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds.
12950 Use gimple_or_expr_nonartificial_location.
12951 * gimple.c (gimple_or_expr_nonartificial_location): New function.
12952 * gimple.h (gimple_or_expr_nonartificial_location): Declare it.
12953 * tree-ssa-strlen.c (maybe_warn_overflow): Use
12954 gimple_or_expr_nonartificial_location.
12955 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise.
12956 (maybe_warn_pointless_strcmp): Likewise.
12958 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12961 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
12962 SRC and MASK arguments to __m128 from __m128d.
12963 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
12965 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
12967 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
12968 argument to __m128i from __m128d.
12969 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from
12971 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
12972 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from
12975 2020-03-05 Delia Burduv <delia.burduv@arm.com>
12977 * config/arm/arm_neon.h (vbfmmlaq_f32): New.
12978 (vbfmlalbq_f32): New.
12979 (vbfmlaltq_f32): New.
12980 (vbfmlalbq_lane_f32): New.
12981 (vbfmlaltq_lane_f32): New.
12982 (vbfmlalbq_laneq_f32): New.
12983 (vbfmlaltq_laneq_f32): New.
12984 * config/arm/arm_neon_builtins.def (vmmla): New.
12989 (vfmab_laneq): New.
12990 (vfmat_laneq): New.
12991 * config/arm/iterators.md (BF_MA): New int iterator.
12992 (bt): New int attribute.
12993 (VQXBF): Copy of VQX with V8BF.
12994 * config/arm/neon.md (neon_vmmlav8bf): New insn.
12995 (neon_vfma<bt>v8bf): New insn.
12996 (neon_vfma<bt>_lanev8bf): New insn.
12997 (neon_vfma<bt>_laneqv8bf): New expand.
12998 (neon_vget_high<mode>): Changed iterator to VQXBF.
12999 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC.
13000 (UNSPEC_BFMAB): New UNSPEC.
13001 (UNSPEC_BFMAT): New UNSPEC.
13003 2020-03-05 Jakub Jelinek <jakub@redhat.com>
13005 PR middle-end/93399
13006 * tree-pretty-print.h (pretty_print_string): Declare.
13007 * tree-pretty-print.c (pretty_print_string): Remove forward
13008 declaration, no longer static. Change nbytes parameter type
13009 from unsigned to size_t.
13010 * print-rtl.c (print_value) <case CONST_STRING>: Use
13011 pretty_print_string and for shrink way too long strings.
13013 2020-03-05 Richard Biener <rguenther@suse.de>
13014 Jakub Jelinek <jakub@redhat.com>
13016 PR tree-optimization/93582
13017 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR
13018 last operand as signed when looking for memset offset. Formatting
13021 2020-03-04 Andrew Pinski <apinski@marvell.com>
13024 * value-prof.c (dump_histogram_value): Use std::abs.
13026 2020-03-04 Martin Sebor <msebor@redhat.com>
13028 PR tree-optimization/93986
13029 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int
13030 operands to the same precision widest_int to avoid ICEs.
13032 2020-03-04 Bill Schmidt <wschmidt@linux.ibm.com>
13035 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define.
13036 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry
13037 for OPTION_MASK_ALTIVEC.
13039 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
13041 * config.gcc: Include the glibc-stdint.h header for zTPF.
13043 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
13045 * config/s390/s390.c (s390_secondary_memory_needed): Disallow
13046 direct FPR-GPR copies.
13047 (s390_register_info_gprtofpr): Disallow GPR content to be saved in
13050 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
13052 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new
13053 operands to the prologue_tpf expander.
13054 (s390_emit_epilogue): Likewise.
13055 (s390_option_override_internal): Do error checking and setup for
13057 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK)
13058 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET)
13059 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET)
13060 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions.
13061 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new
13062 operands for the check flag and the branch target.
13063 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check")
13064 ("mtpf-trace-hook-prologue-target")
13065 ("mtpf-trace-hook-epilogue-check")
13066 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New
13068 * doc/invoke.texi: Document -mtpf-trace-skip option. The other
13069 options are for debugging purposes and will not be documented
13072 2020-03-04 Jakub Jelinek <jakub@redhat.com>
13075 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
13077 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti
13078 argument. Change pd argument so that it can be modified. Turn
13079 constant non-CONSTRUCTOR store into non-constant if it is too large.
13080 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid
13082 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust
13085 2020-02-04 Richard Biener <rguenther@suse.de>
13087 PR tree-optimization/93964
13088 * graphite-isl-ast-to-gimple.c
13089 (gcc_expression_from_isl_ast_expr_id): Add intermediate
13090 conversion for pointer to integer converts.
13091 * graphite-scop-detection.c (assign_parameter_index_in_region):
13094 2020-03-04 Martin Liska <mliska@suse.cz>
13098 * doc/invoke.texi: Clarify --help=language and --help=common
13101 2020-03-04 Jakub Jelinek <jakub@redhat.com>
13103 PR tree-optimization/94001
13104 * tree-tailcall.c (process_assignment): Before comparing op1 to
13105 *ass_var, verify *ass_var is non-NULL.
13107 2020-03-04 Kito Cheng <kito.cheng@sifive.com>
13110 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
13113 2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
13115 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
13116 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
13117 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
13118 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
13119 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
13120 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
13121 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
13122 (V_bf_low, V_bf_cvt_m): New mode attributes.
13123 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
13124 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
13125 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
13126 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
13127 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
13129 2020-03-03 Jakub Jelinek <jakub@redhat.com>
13131 PR tree-optimization/93582
13132 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument.
13133 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result
13134 members, initialize them in the constructor and if mask is non-NULL,
13135 artificially push_partial_def {} for the portions of the mask that
13137 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to
13138 val and return (void *)-1. Formatting fix.
13139 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization.
13141 (vn_reference_lookup): Add mask argument. If non-NULL, don't call
13142 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return
13144 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST
13146 (visit_stmt): Formatting fix.
13148 2020-03-03 Richard Biener <rguenther@suse.de>
13150 PR tree-optimization/93946
13151 * alias.h (refs_same_for_tbaa_p): Declare.
13152 * alias.c (refs_same_for_tbaa_p): New function.
13153 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return
13155 * tree-ssa-scopedtables.h
13156 (avail_exprs_stack::lookup_avail_expr): Add output argument
13157 giving access to the hashtable entry.
13158 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
13160 * tree-ssa-dom.c: Include alias.h.
13161 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before
13162 removing redundant store.
13163 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member.
13164 (ao_ref_init_from_vn_reference): Adjust prototype.
13165 (vn_reference_lookup_pieces): Likewise.
13166 (vn_reference_insert_pieces): Likewise.
13167 * tree-ssa-sccvn.c: Track base alias set in addition to alias
13169 (eliminate_dom_walker::eliminate_stmt): Also check base alias
13170 set when removing redundant stores.
13171 (visit_reference_op_store): Likewise.
13172 * dse.c (record_store): Adjust valdity check for redundant
13175 2020-03-03 Jakub Jelinek <jakub@redhat.com>
13178 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder.
13180 PR rtl-optimization/94002
13181 * explow.c (plus_constant): Punt if cst has VOIDmode and
13182 get_pool_mode is different from mode.
13184 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
13186 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an
13187 address has an offset which fits the scalling constraint for a
13188 load/store operation.
13189 (legitimate_scaled_address_p): Update use
13190 leigitimate_small_data_address_p.
13191 (arc_print_operand): Likewise.
13192 (arc_legitimate_address_p): Likewise.
13193 (legitimate_small_data_address_p): Likewise.
13195 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
13197 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate.
13198 (fnmasf4_fpu): Likewise.
13200 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
13202 * config/arc/arc.md (adddi3): Early expand the 64bit operation into
13204 (subdi3): Likewise.
13205 (adddi3_i): Remove pattern.
13206 (subdi3_i): Likewise.
13208 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
13210 * config/arc/arc.md (eh_return): Add length info.
13212 2020-03-02 David Malcolm <dmalcolm@redhat.com>
13214 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New.
13216 2020-03-02 David Malcolm <dmalcolm@redhat.com>
13218 * doc/invoke.texi (Static Analyzer Options): Add
13219 -Wanalyzer-stale-setjmp-buffer to the list of options enabled
13222 2020-03-02 Uroš Bizjak <ubizjak@gmail.com>
13225 * config/i386/i386.md (movstrict<mode>): Allow only
13226 registers with VALID_INT_MODE_P modes.
13228 2020-03-02 Andrew Stubbs <ams@codesourcery.com>
13230 * config/gcn/gcn-valu.md (dpp_move<mode>): New.
13231 (reduc_insn): Use 'U' and 'B' operand codes.
13232 (reduc_<reduc_op>_scal_<mode>): Allow all types.
13233 (reduc_<reduc_op>_scal_v64di): Delete.
13234 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types.
13235 (*plus_carry_dpp_shr_v64si): Change to ...
13236 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types.
13237 (mov_from_lane63_v64di): Change to ...
13238 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes.
13239 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size.
13240 Support UNSPEC_MOV_DPP_SHR output formats.
13241 (gcn_expand_reduc_scalar): Add "use_moves" reductions.
13242 Add "use_extends" reductions.
13243 (print_operand_address): Add 'I' and 'U' codes.
13244 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
13246 2020-03-02 Martin Liska <mliska@suse.cz>
13248 * lto-wrapper.c: Fix typo in comment about
13249 C++ standard version.
13251 2020-03-01 Martin Sebor <msebor@redhat.com>
13254 * calls.c (init_attr_rdwr_indices): Correctly handle attribute.
13256 2020-03-01 Martin Sebor <msebor@redhat.com>
13258 PR middle-end/93829
13259 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that
13260 of a pointer in the outermost ADDR_EXPRs.
13262 2020-02-28 Jeff Law <law@redhat.com>
13264 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19.
13265 * config/v850/v850.c (v850_asm_trampoline_template): Update
13268 2020-02-28 Michael Meissner <meissner@linux.ibm.com>
13271 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var):
13274 2020-02-28 Martin Liska <mliska@suse.cz>
13277 * configure.ac: Improve detection of ld_date by requiring
13278 either two dashes or none.
13279 * configure: Regenerate.
13281 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
13283 PR rtl-optimization/93564
13284 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
13285 do not honor reg alloc order.
13287 2020-02-27 Joel Hutton <Joel.Hutton@arm.com>
13290 * config/aarch64/aarch64.c (aarch64_override_options): Fix
13291 misleading warning string.
13293 2020-02-27 Martin Sebor <msebor@redhat.com>
13295 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo.
13297 2020-02-27 Michael Meissner <meissner@linux.ibm.com>
13300 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
13301 Split the insn into two parts. This insn only does variable
13302 extract from a register.
13303 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
13304 variable extract from memory.
13305 (vsx_extract_v4sf_var): Split the insn into two parts. This insn
13306 only does variable extract from a register.
13307 (vsx_extract_v4sf_var_load): New insn, do variable extract from
13309 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
13310 into two parts. This insn only does variable extract from a
13312 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
13313 do variable extract from memory.
13315 2020-02-27 Martin Jambor <mjambor@suse.cz>
13316 Feng Xue <fxue@os.amperecomputing.com>
13319 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with
13320 new function calls_same_node_or_its_all_contexts_clone_p.
13321 (cgraph_edge_brings_value_p): Use it.
13322 (cgraph_edge_brings_value_p): Likewise.
13323 (self_recursive_pass_through_p): Return false if caller is a clone.
13324 (self_recursive_agg_pass_through_p): Likewise.
13326 2020-02-27 Jan Hubicka <hubicka@ucw.cz>
13328 PR middle-end/92152
13329 * alias.c (ends_tbaa_access_path_p): Break out from ...
13330 (component_uses_parent_alias_set_from): ... here.
13331 * alias.h (ends_tbaa_access_path_p): Declare.
13332 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...;
13333 handle trailing arrays past end of tbaa access path.
13334 (aliasing_component_refs_p): ... here; likewise.
13335 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access
13336 path; disambiguate also past end of it.
13337 (nonoverlapping_component_refs_p): Use only TBAA segment of the access
13340 2020-02-27 Mihail Ionescu <mihail.ionescu@arm.com>
13342 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the
13343 beginning of the file.
13344 (vcreate_bf16, vcombine_bf16): New.
13345 (vdup_n_bf16, vdupq_n_bf16): New.
13346 (vdup_lane_bf16, vdup_laneq_bf16): New.
13347 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
13348 (vduph_lane_bf16, vduph_laneq_bf16): New.
13349 (vset_lane_bf16, vsetq_lane_bf16): New.
13350 (vget_lane_bf16, vgetq_lane_bf16): New.
13351 (vget_high_bf16, vget_low_bf16): New.
13352 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
13353 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
13354 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
13355 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
13356 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
13357 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
13358 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
13359 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
13360 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
13361 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
13362 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New.
13363 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
13364 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
13365 (vreinterpretq_bf16_p128): New.
13366 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
13367 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
13368 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
13369 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
13370 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
13371 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
13372 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
13373 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
13374 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
13375 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
13376 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
13377 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
13378 (vreinterpretq_p128_bf16): New.
13379 * config/arm/arm_neon_builtins.def (VDX): Add V4BF.
13380 (V_elem): Likewise.
13381 (V_elem_l): Likewise.
13382 (VD_LANE): Likewise.
13384 (V_DOUBLE): Likewise.
13385 (VDQX): Add V4BF and V8BF.
13386 (V_two_elem, V_three_elem, V_four_elem): Likewise.
13388 (V_HALF): Likewise.
13389 (V_double_vector_mode): Likewise.
13390 (V_cmp_result): Likewise.
13391 (V_uf_sclr): Likewise.
13392 (V_sz_elem): Likewise.
13393 (Is_d_reg): Likewise.
13394 (V_mode_nunits): Likewise.
13395 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16.
13397 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
13399 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator.
13400 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE.
13401 (<expander><mode>3<exec>): Likewise.
13402 (<expander><mode>3): New.
13403 (v<expander><mode>3): New.
13404 (<expander><mode>3): New.
13405 (<expander><mode>3<exec>): Rename to ...
13406 (<expander>v64si3<exec>): ... this, and change modes to V64SI.
13407 * config/gcn/gcn.md (mnemonic): Use '%B' for not.
13409 2020-02-27 Alexandre Oliva <oliva@adacore.com>
13411 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave
13414 2020-02-27 Richard Biener <rguenther@suse.de>
13416 PR tree-optimization/93508
13417 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like
13418 non-_CHK variants. Valueize their length arguments.
13420 2020-02-27 Richard Biener <rguenther@suse.de>
13422 PR tree-optimization/93953
13423 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference
13424 to the hash-map entry.
13426 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
13428 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
13430 2020-02-27 Mark Williams <mwilliams@fb.com>
13432 * dwarf2out.c (file_name_acquire): Call remap_debug_filename.
13433 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map,
13434 -ffile-prefix-map and -fmacro-prefix-map.
13435 * lto-streamer-out.c: Include file-prefix-map.h.
13436 (lto_output_location): Remap the file part of locations.
13438 2020-02-27 Jakub Jelinek <jakub@redhat.com>
13441 * gimplify.c (gimplify_init_constructor): Don't promote readonly
13442 DECL_REGISTER variables to TREE_STATIC.
13444 PR tree-optimization/93582
13445 PR tree-optimization/93945
13446 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with
13447 non-zero INTEGER_CST second argument and ref->offset or ref->size
13448 not a multiple of BITS_PER_UNIT.
13450 2020-02-27 Jonathan Wakely <jwakely@redhat.com>
13452 * doc/install.texi (Binaries): Update description of BullFreeware.
13454 2020-02-26 Sandra Loosemore <sandra@codesourcery.com>
13458 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in
13459 C++ Language Options, Warning Options, and Static Analyzer
13460 Options lists. Document negative form of options enabled by
13461 default. Move some things around to more accurately sort
13462 warnings by category.
13463 (C++ Dialect Options, Warning Options, Static Analyzer
13464 Options): Document negative form of options when enabled by
13465 default. Move some things around to more accurately sort
13466 warnings by category. Add some missing index entries.
13467 Light copy-editing.
13469 2020-02-26 Carl Love <cel@us.ibm.com>
13472 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on
13473 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only
13474 for the vector unsigned short arguments. It is also listed as the
13475 name of the built-in for arguments vector unsigned short,
13476 vector unsigned int and vector unsigned long long built-ins. The
13477 name of the builtins for these arguments should be:
13478 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and
13479 __builtin_crypto_vpmsumd respectively.
13481 2020-02-26 Richard Biener <rguenther@suse.de>
13483 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count
13484 and load permutation.
13486 2020-02-26 Richard Sandiford <richard.sandiford@arm.com>
13488 PR middle-end/93843
13489 * optabs-tree.c (supportable_convert_operation): Reject types with
13492 2020-02-26 David Malcolm <dmalcolm@redhat.com>
13494 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o.
13496 2020-02-26 Jakub Jelinek <jakub@redhat.com>
13498 PR tree-optimization/93820
13499 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE
13500 argument to ALL_INTEGER_CST_P boolean.
13501 (imm_store_chain_info::try_coalesce_bswap): Adjust caller.
13502 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle
13503 adjacent INTEGER_CST store into merged_store->only_constants like
13506 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13509 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity
13511 * cfghooks.c (verify_flow_info): Likewise.
13512 * predict.c (combine_predictions_for_bb): Likewise.
13513 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo,
13514 sucessor -> successor.
13515 (find_traces_1_round): Fix comment typo, destinarion -> destination.
13516 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors ->
13518 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump
13519 message typo, sucessors -> successors.
13521 2020-02-25 Martin Sebor <msebor@redhat.com>
13523 * doc/extend.texi (attribute access): Correct an example.
13525 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
13527 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
13529 (aarch64_init_simd_builtin_scalar_types): Register simd_bf.
13530 (VAR15, VAR16): New.
13531 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
13532 (VD): Enable for V4BF.
13534 (VQ): Enable for V8BF.
13536 (VQ_NO2E): Likewise.
13537 (VDBL, Vdbl): Add V4BF.
13538 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
13539 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
13540 (bfloat16x8x2_t): Likewise.
13541 (bfloat16x4x3_t): Likewise.
13542 (bfloat16x8x3_t): Likewise.
13543 (bfloat16x4x4_t): Likewise.
13544 (bfloat16x8x4_t): Likewise.
13545 (vcombine_bf16): New.
13546 (vld1_bf16, vld1_bf16_x2): New.
13547 (vld1_bf16_x3, vld1_bf16_x4): New.
13548 (vld1q_bf16, vld1q_bf16_x2): New.
13549 (vld1q_bf16_x3, vld1q_bf16_x4): New.
13550 (vld1_lane_bf16): New.
13551 (vld1q_lane_bf16): New.
13552 (vld1_dup_bf16): New.
13553 (vld1q_dup_bf16): New.
13556 (vld2_dup_bf16): New.
13557 (vld2q_dup_bf16): New.
13560 (vld3_dup_bf16): New.
13561 (vld3q_dup_bf16): New.
13564 (vld4_dup_bf16): New.
13565 (vld4q_dup_bf16): New.
13566 (vst1_bf16, vst1_bf16_x2): New.
13567 (vst1_bf16_x3, vst1_bf16_x4): New.
13568 (vst1q_bf16, vst1q_bf16_x2): New.
13569 (vst1q_bf16_x3, vst1q_bf16_x4): New.
13570 (vst1_lane_bf16): New.
13571 (vst1q_lane_bf16): New.
13579 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
13581 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
13582 (VALL_F16): Likewise.
13583 (VALLDI_F16): Likewise.
13585 (Vetype): Likewise.
13586 (vswap_width_name): Likewise.
13587 (VSWAP_WIDTH): Likewise.
13591 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New.
13592 (vget_lane_bf16, vgetq_lane_bf16): New.
13593 (vcreate_bf16): New.
13594 (vdup_n_bf16, vdupq_n_bf16): New.
13595 (vdup_lane_bf16, vdup_laneq_bf16): New.
13596 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
13597 (vduph_lane_bf16, vduph_laneq_bf16): New.
13598 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
13599 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
13600 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
13601 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
13602 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
13603 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
13604 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
13605 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
13606 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
13607 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
13608 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New
13609 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New
13610 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
13611 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
13612 (vreinterpretq_bf16_p128): New.
13613 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
13614 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
13615 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
13616 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
13617 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
13618 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
13619 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
13620 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
13621 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
13622 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
13623 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
13624 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
13625 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New.
13626 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New.
13627 (vreinterpretq_p128_bf16): New.
13629 2020-02-25 Dennis Zhang <dennis.zhang@arm.com>
13631 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New
13632 (vbfdot_lane_f32, vbfdotq_laneq_f32): New.
13633 (vbfdot_laneq_f32, vbfdotq_lane_f32): New.
13634 * config/arm/arm_neon_builtins.def (vbfdot): New entry.
13635 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise.
13636 * config/arm/iterators.md (VSF2BF): New attribute.
13637 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry.
13638 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise.
13639 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise.
13641 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org>
13643 * config/arm/arm.md (required_for_purecode): New attribute.
13644 (enabled): Handle required_for_purecode.
13645 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to
13646 work with -mpure-code.
13648 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13650 PR rtl-optimization/93908
13651 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src
13654 2019-02-25 Eric Botcazou <ebotcazou@adacore.com>
13656 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode.
13658 2020-02-25 Roman Zhuykov <zhroma@ispras.ru>
13660 * doc/install.texi (--enable-checking): Adjust wording.
13662 2020-02-25 Richard Biener <rguenther@suse.de>
13664 PR tree-optimization/93868
13665 * tree-vect-slp.c (slp_copy_subtree): New function.
13666 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before
13667 re-arranging stmts in it.
13669 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13671 PR middle-end/93874
13672 * passes.c (pass_manager::dump_passes): Create a cgraph node for the
13673 dummy function and remove it at the end.
13675 PR translation/93864
13676 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo
13677 paramter -> parameter.
13678 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise.
13679 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise.
13681 2020-02-24 Roman Zhuykov <zhroma@ispras.ru>
13683 * doc/install.texi (--enable-checking): Properly document current
13685 (--enable-stage1-checking): Minor clarification about bootstrap.
13687 2020-02-24 David Malcolm <dmalcolm@redhat.com>
13690 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that
13691 -fanalyzer-checker=taint is also required.
13692 (-fanalyzer-checker=): Note that providing this option enables the
13693 given checker, and doing so may be required for checkers that are
13694 disabled by default.
13696 2020-02-24 David Malcolm <dmalcolm@redhat.com>
13698 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows
13699 significant control flow events; add a "3" which shows all
13700 control flow events; the old "3" becomes "4".
13702 2020-02-24 Jakub Jelinek <jakub@redhat.com>
13704 PR tree-optimization/93582
13705 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider
13706 pd.offset and pd.size to be counted in bits rather than bytes, add
13707 support for maxsizei that is not a multiple of BITS_PER_UNIT and
13708 handle bitfield stores and loads.
13709 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with
13710 uncomparable quantities - bytes vs. bits. Allow push_partial_def
13711 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust
13712 pd.offset/pd.size to be counted in bits rather than bytes.
13713 Formatting fix. Rename shadowed len variable to buflen.
13715 2020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
13716 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org>
13719 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function.
13720 (driver::main): Call putenv_COLLECT_AS_OPTIONS.
13721 * opts-common.c (parse_options_from_collect_gcc_options): New function.
13722 (prepend_xassembler_to_collect_as_options): Likewise.
13723 * opts.h (parse_options_from_collect_gcc_options): Declare prototype.
13724 (prepend_xassembler_to_collect_as_options): Likewise.
13725 * lto-opts.c (lto_write_options): Stream assembler options
13726 in COLLECT_AS_OPTIONS.
13727 * lto-wrapper.c (xassembler_options_error): New static variable.
13728 (get_options_from_collect_gcc_options): Move parsing options code to
13729 parse_options_from_collect_gcc_options and call it.
13730 (merge_and_complain): Validate -Xassembler options.
13731 (append_compiler_options): Handle OPT_Xassembler.
13732 (run_gcc): Append command line -Xassembler options to
13733 collect_gcc_options.
13734 * doc/invoke.texi: Add documentation about using Xassembler
13737 2020-02-24 Kito Cheng <kito.cheng@sifive.com>
13739 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen
13741 (riscv_rtx_costs): Update cost model for LTGT.
13743 2020-02-23 Vladimir Makarov <vmakarov@redhat.com>
13745 PR rtl-optimization/93564
13746 * ira-color.c (struct update_cost_queue_elem): New member start.
13747 (queue_update_cost, get_next_update_cost): Add new arg start.
13748 (allocnos_conflict_p): New function.
13749 (update_costs_from_allocno): Add new arg conflict_cost_update_p.
13750 Add checking conflicts with allocnos_conflict_p.
13751 (update_costs_from_prefs, restore_costs_from_copies): Adjust
13752 update_costs_from_allocno calls.
13753 (update_conflict_hard_regno_costs): Add checking conflicts with
13754 allocnos_conflict_p. Adjust calls of queue_update_cost and
13755 get_next_update_cost.
13756 (assign_hard_reg): Adjust calls of queue_update_cost. Add
13758 (bucket_allocno_compare_func): Restore previous version.
13760 2020-02-21 John David Anglin <danglin@gcc.gnu.org>
13762 * config/pa/pa.c (pa_function_value): Fix check for word and
13763 double-word size when handling aggregate return values.
13764 * config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate
13765 that homogeneous SFmode and DFmode aggregates are passed and returned
13766 in general registers.
13768 2020-02-21 Jakub Jelinek <jakub@redhat.com>
13770 PR translation/93759
13771 * opts.c (print_filtered_help): Translate help before appending
13772 messages to it rather than after that.
13774 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13776 PR rtl-optimization/PR92989
13777 * lra-lives.c (process_bb_lives): Restore the original order
13778 of the bb liveness update. Call make_hard_regno_dead for each
13779 register clobbered at the start of an EH receiver.
13781 2020-02-18 Feng Xue <fxue@os.amperecomputing.com>
13784 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as
13785 self-recursively generated.
13787 2020-02-21 Iain Sandoe <iain@sandoe.co.uk>
13790 * config/darwin-c.c (pop_field_alignment): Adjust quoting of
13793 2020-02-21 Mihail Ionescu <mihail.ionescu@arm.com>
13795 * doc/sourcebuild.texi (arm_v8_1m_mve_ok):
13796 Document new target supports option.
13798 2020-02-21 Dennis Zhang <dennis.zhang@arm.com>
13800 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New.
13801 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New.
13802 * config/arm/iterators.md (MATMUL): New iterator.
13803 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US.
13804 (mmla_sfx): New attribute.
13805 * config/arm/neon.md (neon_<sup>mmlav16qi): New.
13806 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New.
13807 (UNSPEC_MATMUL_US): New.
13809 2020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13811 * config/arm/arm.md: Prevent scalar shifts from being used when big
13814 2020-02-21 Jan Hubicka <hubicka@ucw.cz>
13815 Richard Biener <rguenther@suse.de>
13817 PR tree-optimization/93586
13818 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk
13819 after mismatched array refs; do not sure type size information to
13820 recover from unmatched referneces with !flag_strict_aliasing_p.
13822 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13824 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ...
13825 (gather_load<mode>v64si): ... this and set operand 2 to V64SI.
13826 (scatter_store<mode>): Rename to ...
13827 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI.
13828 (scatter<mode>_exec): Delete. Move contents ...
13829 (mask_scatter_store<mode>): ... here, and rename that to ...
13830 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI.
13831 Remove mode conversion.
13832 (mask_gather_load<mode>): Rename to ...
13833 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI.
13834 Remove mode conversion.
13835 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
13837 2020-02-21 Martin Jambor <mjambor@suse.cz>
13839 PR tree-optimization/93845
13840 * tree-sra.c (verify_sra_access_forest): Only test access size of
13843 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13845 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
13846 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
13847 (addv64di3_exec): Likewise.
13848 (subv64di3): Likewise.
13849 (subv64di3_exec): Likewise.
13850 (addv64di3_zext): Likewise.
13851 (addv64di3_zext_exec): Likewise.
13852 (addv64di3_zext_dup): Likewise.
13853 (addv64di3_zext_dup_exec): Likewise.
13854 (addv64di3_zext_dup2): Likewise.
13855 (addv64di3_zext_dup2_exec): Likewise.
13856 (addv64di3_sext_dup2): Likewise.
13857 (addv64di3_sext_dup2_exec): Likewise.
13858 (<expander>v64di3): Likewise.
13859 (<expander>v64di3_exec): Likewise.
13860 (*<reduc_op>_dpp_shr_v64di): Likewise.
13861 (*plus_carry_dpp_shr_v64di): Likewise.
13862 * config/gcn/gcn.md (adddi3): Likewise.
13863 (addptrdi3): Likewise.
13864 (<expander>di3): Likewise.
13866 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13868 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
13870 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13872 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE
13873 support. Use aarch64_emit_mult instead of emitting multiplication
13874 instructions directly.
13875 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2)
13876 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders.
13878 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13880 * config/aarch64/aarch64.c (aarch64_emit_mult): New function.
13881 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult
13882 instead of emitting multiplication instructions directly.
13883 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator.
13884 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>)
13885 (@aarch64_frecps<mode>): New expanders.
13887 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13889 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate
13890 on and produce uint64_ts rather than ints.
13891 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts.
13892 (cpu_approx_modes): Change the fields from unsigned int to uint64_t.
13894 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13896 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create
13897 an unused xmsk register when handling approximate rsqrt.
13899 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13901 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted
13902 flag_finite_math_only condition.
13904 2020-02-20 Uroš Bizjak <ubizjak@gmail.com>
13907 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand
13908 to destination operand for shufps alternative.
13909 (*vec_extractv2si_1): Ditto.
13911 2020-02-20 Peter Bergner <bergner@linux.ibm.com>
13914 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
13917 2020-02-20 Martin Liska <mliska@suse.cz>
13919 PR translation/93831
13920 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode.
13922 2020-02-20 Martin Liska <mliska@suse.cz>
13924 PR translation/93830
13925 * common/config/avr/avr-common.c: Remote trailing "|".
13927 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13929 * collect2.c (maybe_run_lto_and_relink): Fix typo in
13932 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13934 PR tree-optimization/93767
13935 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the
13936 access-size bias from the offset calculations for negative strides.
13938 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13940 * collect2.c (c_file, o_file): Make const again.
13941 (ldout,lderrout, dump_ld_file): Remove.
13942 (tool_cleanup): Avoid calling not signal-safe functions.
13943 (maybe_run_lto_and_relink): Avoid possible signal handler
13944 access to unintialzed memory (lto_o_files).
13945 (main): Avoid leaking temp files in $TMPDIR.
13946 Initialize c_file/o_file with concat, which avoids exposing
13947 uninitialized memory to signal handler, which calls unlink(!).
13948 Avoid calling maybe_unlink when the main function returns,
13949 since the atexit handler is already doing this.
13950 * collect2.h (dump_ld_file, ldout, lderrout): Remove.
13952 2020-02-19 Martin Jambor <mjambor@suse.cz>
13954 PR tree-optimization/93776
13955 * tree-sra.c (create_access): Do not create zero size accesses.
13956 (get_access_for_expr): Do not search for zero sized accesses.
13958 2020-02-19 Martin Jambor <mjambor@suse.cz>
13960 PR tree-optimization/93667
13961 * tree-sra.c (scalarizable_type_p): Return false if record fields
13962 do not follow wach other.
13964 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
13966 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
13967 rather than fmv.x.s/fmv.s.x.
13969 2020-02-18 James Greenhalgh <james.greenhalgh@arm.com>
13971 * config/aarch64/aarch64-simd-builtins.def
13972 (intrinsic_vec_smult_lo_): New.
13973 (intrinsic_vec_umult_lo_): Likewise.
13974 (vec_widen_smult_hi_): Likewise.
13975 (vec_widen_umult_hi_): Likewise.
13976 * config/aarch64/aarch64-simd.md
13977 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New.
13978 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics.
13979 (vmull_high_s16): Likewise.
13980 (vmull_high_s32): Likewise.
13981 (vmull_high_u8): Likewise.
13982 (vmull_high_u16): Likewise.
13983 (vmull_high_u32): Likewise.
13984 (vmull_s8): Likewise.
13985 (vmull_s16): Likewise.
13986 (vmull_s32): Likewise.
13987 (vmull_u8): Likewise.
13988 (vmull_u16): Likewise.
13989 (vmull_u32): Likewise.
13991 2020-02-18 Martin Liska <mliska@suse.cz>
13993 * value-prof.c (stream_out_histogram_value): Restore LTO PGO
13994 bootstrap by missing removal of invalid sanity check.
13996 2020-02-18 Martin Liska <mliska@suse.cz>
13999 * ipa-icf-gimple.c (func_checker::compare_gimple_assign):
14000 Always compare LHS of gimple_assign.
14002 2020-02-18 Martin Liska <mliska@suse.cz>
14005 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute
14006 and return type of functions.
14007 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl):
14008 Drop MALLOC attribute for void functions.
14009 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop
14010 malloc_state for a new VOID clone.
14012 2020-02-18 Martin Liska <mliska@suse.cz>
14015 * common.opt: Add -fprofile-reproducibility.
14016 * doc/invoke.texi: Document it.
14017 * value-prof.c (dump_histogram_value):
14018 Document and support behavior for counters[0]
14019 being a negative value.
14020 (get_nth_most_common_value): Handle negative
14021 counters[0] in respect to flag_profile_reproducible.
14023 2020-02-18 Jakub Jelinek <jakub@redhat.com>
14026 * cgraph.c (verify_speculative_call): Use speculative_id instead of
14027 speculative_uid in messages. Remove trailing whitespace from error
14028 message. Use num_speculative_call_targets instead of
14029 num_speculative_targets in a message.
14030 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in
14031 edge messages and stmt instead of cal_stmt in reference message.
14033 PR tree-optimization/93780
14034 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p
14035 before calling build_vector_type.
14036 (execute_update_addresses_taken): Likewise.
14039 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help
14040 typo, functoin -> function.
14041 * tree.c (free_lang_data_in_decl): Fix comment typo,
14042 functoin -> function.
14043 * ipa-visibility.c (cgraph_externally_visible_p): Likewise.
14045 2020-02-17 David Malcolm <dmalcolm@redhat.com>
14047 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs
14049 (print_option_information): Don't call get_option_url if URLs
14052 2020-02-17 Alexandre Oliva <oliva@adacore.com>
14054 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete
14055 handling of register_common-less targets.
14057 2020-02-17 Martin Liska <mliska@suse.cz>
14060 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar.
14062 2020-02-17 Martin Liska <mliska@suse.cz>
14064 PR translation/93755
14065 * config/rs6000/rs6000.c (rs6000_option_override_internal):
14068 2020-02-17 Martin Liska <mliska@suse.cz>
14071 * config/rx/elf.opt: Fix typo.
14073 2020-02-17 Richard Biener <rguenther@suse.de>
14076 * opts-global.c (print_ignored_options): Use inform and
14079 2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
14082 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber.
14084 2020-02-16 Uroš Bizjak <ubizjak@gmail.com>
14087 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2.
14088 (atan2<mode>3): Update operand order in the call to gen_atan2xf3.
14090 2020-02-15 Jason Merrill <jason@redhat.com>
14092 * doc/invoke.texi (C Dialect Options): Add -std=c++20.
14094 2020-02-15 Jakub Jelinek <jakub@redhat.com>
14096 PR tree-optimization/93744
14097 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0,
14098 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A,
14099 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make
14100 sure @2 in the first and @1 in the other patterns has no side-effects.
14102 2020-02-15 David Malcolm <dmalcolm@redhat.com>
14103 Bernd Edlinger <bernd.edlinger@hotmail.de>
14107 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
14108 * configure.ac (--with-diagnostics-urls): New configuration
14109 option, based on --with-diagnostics-color.
14110 (DIAGNOSTICS_URLS_DEFAULT): New define.
14111 * config.h: Regenerate.
14112 * configure: Regenerate.
14113 * diagnostic.c (diagnostic_urls_init): Handle -1 for
14114 DIAGNOSTICS_URLS_DEFAULT from configure-time
14115 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
14116 and TERM_URLS environment variable.
14117 * diagnostic-url.h (diagnostic_url_format): New enum type.
14118 (diagnostic_urls_enabled_p): rename to...
14119 (determine_url_format): ... this, and change return type.
14120 * diagnostic-color.c (parse_env_vars_for_urls): New helper function.
14121 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
14122 the linux console, and mingw.
14123 (diagnostic_urls_enabled_p): rename to...
14124 (determine_url_format): ... this, and adjust.
14125 * pretty-print.h (pretty_printer::show_urls): rename to...
14126 (pretty_printer::url_format): ... this, and change to enum.
14127 * pretty-print.c (pretty_printer::pretty_printer,
14128 pp_begin_url, pp_end_url, test_urls): Adjust.
14129 * doc/install.texi (--with-diagnostics-urls): Document the new
14130 configuration option.
14131 (--with-diagnostics-color): Document the existing interaction
14132 with GCC_COLORS better.
14133 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
14134 vindex reference. Update description of defaults based on the above.
14135 (-fdiagnostics-color): Update description of how -fdiagnostics-color
14136 interacts with GCC_COLORS.
14138 2020-02-14 Eric Botcazou <ebotcazou@adacore.com>
14141 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in
14142 conjunction with TARGET_GNU_TLS in early return.
14144 2020-02-14 Alexander Monakov <amonakov@ispras.ru>
14146 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if
14147 the mode is not wider than UNITS_PER_WORD.
14149 2020-02-14 Martin Jambor <mjambor@suse.cz>
14151 PR tree-optimization/93516
14152 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create
14153 access of the same type as the parent.
14154 (propagate_subaccesses_from_lhs): Likewise.
14156 2020-02-14 Hongtao Liu <hongtao.liu@intel.com>
14159 * config/i386/avx512vbmi2intrin.h
14160 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16,
14161 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32,
14162 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
14163 _m512_shrdi_epi64, _m512_mask_shrdi_epi64,
14164 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16,
14165 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16,
14166 _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
14167 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64,
14168 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo
14169 of lacking a closing parenthesis.
14170 * config/i386/avx512vbmi2vlintrin.h
14171 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16,
14172 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32,
14173 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32,
14174 _m256_shrdi_epi64, _m256_mask_shrdi_epi64,
14175 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16,
14176 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16,
14177 _mm256_shldi_epi32, _mm256_mask_shldi_epi32,
14178 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64,
14179 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64,
14180 _mm_shrdi_epi16, _mm_mask_shrdi_epi16,
14181 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32,
14182 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32,
14183 _mm_shrdi_epi64, _mm_mask_shrdi_epi64,
14184 _m_maskz_shrdi_epi64, _mm_shldi_epi16,
14185 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16,
14186 _mm_shldi_epi32, _mm_mask_shldi_epi32,
14187 _mm_maskz_shldi_epi32, _mm_shldi_epi64,
14188 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto.
14190 2020-02-13 H.J. Lu <hongjiu.lu@intel.com>
14193 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
14194 the target function entry.
14196 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
14198 * common/config/arc/arc-common.c (arc_option_optimization_table):
14199 Disable if-conversion step when optimized for size.
14201 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
14203 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
14204 R12-R15 are always in ARCOMPACT16_REGS register class.
14205 * config/arc/arc.opt (mq-class): Deprecate.
14206 * config/arc/constraint.md ("q"): Remove dependency on mq-class
14208 * doc/invoke.texi (mq-class): Update text.
14209 * common/config/arc/arc-common.c (arc_option_optimization_table):
14212 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
14214 * config/arc/arc.c (arc_insn_cost): New function.
14215 (TARGET_INSN_COST): Define.
14216 * config/arc/arc.md (cost): New attribute.
14217 (add_n): Use arc_nonmemory_operand.
14218 (ashlsi3_insn): Likewise, also update constraints.
14219 (ashrsi3_insn): Likewise.
14220 (rotrsi3): Likewise.
14221 (add_shift): Likewise.
14222 * config/arc/predicates.md (arc_nonmemory_operand): New predicate.
14224 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
14226 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
14228 (umulsidi_600): Likewise.
14230 2020-02-13 Jakub Jelinek <jakub@redhat.com>
14233 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8,
14234 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8,
14235 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8,
14236 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W,
14237 pass __A to the builtin followed by __W instead of __A followed by
14239 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32,
14240 _mm512_mask_popcnt_epi64): Likewise.
14241 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32,
14242 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64,
14243 _mm256_mask_popcnt_epi64): Likewise.
14245 PR tree-optimization/93582
14246 * fold-const.h (shift_bytes_in_array_left,
14247 shift_bytes_in_array_right): Declare.
14248 * fold-const.c (shift_bytes_in_array_left,
14249 shift_bytes_in_array_right): New function, moved from
14250 gimple-ssa-store-merging.c, no longer static.
14251 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move
14252 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left.
14253 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c.
14254 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of
14255 shift_bytes_in_array.
14256 (verify_shift_bytes_in_array): Rename to ...
14257 (verify_shift_bytes_in_array_left): ... this. Use
14258 shift_bytes_in_array_left instead of shift_bytes_in_array.
14259 (store_merging_c_tests): Call verify_shift_bytes_in_array_left
14260 instead of verify_shift_bytes_in_array.
14261 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr
14262 / native_interpret_expr where the store covers all needed bits,
14263 punt on PDP-endian, otherwise allow all involved offsets and sizes
14264 not to be byte-aligned.
14267 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and
14268 use const_0_to_255_operand predicate instead of immediate_operand.
14269 (avx512dq_fpclass<mode><mask_scalar_merge_name>,
14270 avx512dq_vmfpclass<mode><mask_scalar_merge_name>,
14271 vgf2p8affineinvqb_<mode><mask_name>,
14272 vgf2p8affineqb_<mode><mask_name>): Drop mode from
14273 const_0_to_255_operand predicated operands.
14275 2020-02-12 Jeff Law <law@redhat.com>
14277 * config/h8300/h8300.md (comparison shortening peepholes): Use
14278 a mode iterator to merge the HImode and SImode peepholes.
14280 2020-02-12 Jakub Jelinek <jakub@redhat.com>
14282 PR middle-end/93663
14283 * real.c (is_even): Make static. Function comment fix.
14284 (is_halfway_below): Make static, don't assert R is not inf/nan,
14285 instead return false for those. Small formatting fixes.
14287 2020-02-12 Martin Sebor <msebor@redhat.com>
14289 PR middle-end/93646
14290 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename...
14291 (handle_builtin_stxncpy_strncat): ...to this. Change first argument.
14292 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation.
14293 (strlen_check_and_optimize_call): Adjust callee name.
14295 2020-02-12 Jeff Law <law@redhat.com>
14297 * config/h8300/h8300.md (comparison shortening peepholes): Drop
14298 (and (xor)) variant. Combine other two into single peephole.
14300 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
14302 PR rtl-optimization/93565
14303 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs.
14305 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
14307 * config/aarch64/aarch64-simd.md
14308 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
14309 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
14310 generating separate ADDV and zero_extend patterns.
14311 * config/aarch64/iterators.md (VDQV_E): New iterator.
14313 2020-02-12 Jeff Law <law@redhat.com>
14315 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns,
14316 expanders, splits, etc.
14317 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise.
14318 (stpcpy_internal_<mode>, stpcpy splitter): Likewise.
14319 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise.
14320 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function.
14321 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise
14322 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused
14323 function prototype.
14324 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise.
14326 2020-02-12 Jakub Jelinek <jakub@redhat.com>
14329 * config/i386/sse.md (VI48F_256_DQ): New mode iterator.
14330 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove
14331 TARGET_AVX512DQ from condition.
14332 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition>
14333 instead of <mask_mode512bit_condition> in condition. If
14334 TARGET_AVX512DQ is false, emit vextract*64x4 instead of
14336 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition>
14339 2020-02-12 Kewen Lin <linkw@gcc.gnu.org>
14342 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn.
14344 2020-02-12 Segher Boessenkool <segher@kernel.crashing.org>
14346 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof
14347 where strlen is more legible.
14348 (rs6000_builtin_vectorized_libmass): Ditto.
14349 (rs6000_print_options_internal): Ditto.
14351 2020-02-11 Martin Sebor <msebor@redhat.com>
14353 PR tree-optimization/93683
14354 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set.
14356 2020-02-11 Michael Meissner <meissner@linux.ibm.com>
14358 * config/rs6000/predicates.md (cint34_operand): Rename the
14359 -mprefixed-addr option to be -mprefixed.
14360 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename
14361 the -mprefixed-addr option to be -mprefixed.
14362 (OTHER_FUTURE_MASKS): Likewise.
14363 (POWERPC_MASKS): Likewise.
14364 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
14365 the -mprefixed-addr option to be -mprefixed. Change error
14366 messages to refer to -mprefixed.
14367 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be
14369 (rs6000_legitimate_offset_address_p): Likewise.
14370 (rs6000_mode_dependent_address): Likewise.
14371 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be
14372 "-mprefixed" for target attributes and pragmas.
14373 (address_to_insn_form): Rename the -mprefixed-addr option to be
14375 (rs6000_adjust_insn_length): Likewise.
14376 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the
14377 -mprefixed-addr option to be -mprefixed.
14378 (ASM_OUTPUT_OPCODE): Likewise.
14379 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the
14380 -mprefixed-addr option to be -mprefixed.
14381 * config/rs6000/rs6000.opt (-mprefixed): Rename the
14382 -mprefixed-addr option to be prefixed. Change the option from
14383 being undocumented to being documented.
14384 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the
14385 -mprefixed option. Update the -mpcrel documentation to mention
14388 2020-02-11 Hans-Peter Nilsson <hp@axis.com>
14390 * ira-conflicts.c (print_hard_reg_set): Correct output for sets
14391 including FIRST_PSEUDO_REGISTER - 1.
14392 * ira-color.c (print_hard_reg_set): Ditto.
14394 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14396 * config/arm/arm-builtins.c (enum arm_type_qualifiers):
14397 (USTERNOP_QUALIFIERS): New define.
14398 (USMAC_LANE_QUADTUP_QUALIFIERS): New define.
14399 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define.
14400 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX.
14401 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index.
14402 * config/arm/arm_neon.h (vusdot_s32): New.
14403 (vusdot_lane_s32): New.
14404 (vusdotq_lane_s32): New.
14405 (vsudot_lane_s32): New.
14406 (vsudotq_lane_s32): New.
14407 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New.
14408 * config/arm/iterators.md (DOTPROD_I8MM): New.
14409 (sup, opsuffix): Add <us/su>.
14410 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New.
14411 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New.
14413 2020-02-11 Richard Biener <rguenther@suse.de>
14415 PR tree-optimization/93661
14416 PR tree-optimization/93662
14417 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard
14418 tree_to_poly_int64.
14419 * tree-sra.c (get_access_for_expr): Likewise.
14421 2020-02-10 Jakub Jelinek <jakub@redhat.com>
14424 * config/i386/sse.md (VI_256_AVX2): New mode iterator.
14425 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256.
14426 Change condition from TARGET_AVX2 to TARGET_AVX.
14428 2020-02-10 Iain Sandoe <iain@sandoe.co.uk>
14431 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last
14432 argument of strncmp.
14434 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
14436 Try to generate zero-based comparisons.
14437 * config/cris/cris.c (cris_reduce_compare): New function.
14438 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype.
14439 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4")
14440 (cstore<mode>4"): Apply cris_reduce_compare in expanders.
14442 2020-02-10 Richard Earnshaw <rearnsha@arm.com>
14445 * config/arm/arm.md (movsi_compare0): Allow SP as a source register
14446 in Thumb state and also as a destination in Arm state. Add T16
14449 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
14451 * md.texi (Define Subst): Match closing paren in example.
14453 2020-02-10 Jakub Jelinek <jakub@redhat.com>
14457 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last
14458 arguments of strncmp.
14460 2020-02-10 Feng Xue <fxue@os.amperecomputing.com>
14463 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge
14464 but different source value.
14465 (adjust_callers_for_value_intersection): New function.
14466 (gather_edges_for_value): Adjust order of callers to let a
14467 non-self-recursive caller be the first element.
14468 (self_recursive_pass_through_p): Add a new parameter "simple", and
14469 check generalized self-recursive pass-through jump function.
14470 (self_recursive_agg_pass_through_p): Likewise.
14471 (find_more_scalar_values_for_callers_subset): Compute value from
14472 pass-through jump function for self-recursive.
14473 (intersect_with_plats): Cleanup previous implementation code for value
14474 itersection with self-recursive call edge.
14475 (intersect_with_agg_replacements): Likewise.
14476 (intersect_aggregates_with_edge): Deduce value from pass-through jump
14477 function for self-recursive call edge. Cleanup previous implementation
14478 code for value intersection with self-recursive call edge.
14479 (decide_whether_version_node): Remove dead callers and adjust order
14480 to let a non-self-recursive caller be the first element.
14482 2020-02-09 Uroš Bizjak <ubizjak@gmail.com>
14484 * recog.c: Move pass_split_before_sched2 code in front of
14485 pass_split_before_regstack.
14486 (pass_data_split_before_sched2): Rename pass to split3 from split4.
14487 (pass_data_split_before_regstack): Rename pass to split4 from split3.
14488 (rest_of_handle_split_before_sched2): Remove.
14489 (pass_split_before_sched2::execute): Unconditionally call
14491 (enable_split_before_sched2): New function.
14492 (pass_split_before_sched2::gate): Use enable_split_before_sched2.
14493 (pass_split_before_regstack::gate): Ditto.
14494 * config/nds32/nds32.c (nds32_split_double_word_load_store_p):
14495 Update name check for renamed split4 pass.
14496 * config/sh/sh.c (register_sh_passes): Update pass insertion
14497 point for renamed split4 pass.
14499 2020-02-09 Jakub Jelinek <jakub@redhat.com>
14501 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote
14502 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid
14503 copying them around between host and target.
14505 2020-02-08 Andrew Pinski <apinski@marvell.com>
14508 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
14509 STRICT_ALIGNMENT also.
14511 2020-02-08 Jim Wilson <jimw@sifive.com>
14514 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
14516 2020-02-08 Uroš Bizjak <ubizjak@gmail.com>
14517 Jakub Jelinek <jakub@redhat.com>
14520 * config/i386/i386.h (CALL_USED_REGISTERS): Make
14521 xmm16-xmm31 call-used even in 64-bit ms-abi.
14523 2020-02-07 Dennis Zhang <dennis.zhang@arm.com>
14525 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry.
14526 (simd_ummla, simd_usmmla): Likewise.
14527 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New.
14528 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New.
14529 (vusmmlaq_s32): New.
14531 2020-02-07 Richard Biener <rguenther@suse.de>
14533 PR middle-end/93519
14534 * tree-inline.c (fold_marked_statements): Do a PRE walk,
14535 skipping unreachable regions.
14536 (optimize_inline_calls): Skip folding stmts when we didn't
14539 2020-02-07 H.J. Lu <hongjiu.lu@intel.com>
14542 * config/i386/i386.c (function_arg_ms_64): Add a type argument.
14543 Don't return aggregates with only SFmode and DFmode in SSE
14545 (ix86_function_arg): Pass arg.type to function_arg_ms_64.
14547 2020-02-07 Jakub Jelinek <jakub@redhat.com>
14550 * config/rs6000/rs6000-logue.c
14551 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn,
14552 if it fails, move rs into end_addr and retry. Add
14553 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or
14554 the insn pattern doesn't describe well what exactly happens to
14558 * config/i386/predicates.md (avx_identity_operand): Remove.
14559 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove.
14560 (avx_<castmode><avxsizesuffix>_<castmode>,
14561 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to
14562 a VEC_CONCAT of the operand and UNSPEC_CAST.
14563 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to
14564 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with
14568 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear
14569 recog_data.insn if distance_non_agu_define changed it.
14571 2020-02-06 Michael Meissner <meissner@linux.ibm.com>
14574 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
14575 we only had X-FORM (reg+reg) addressing for vectors. Also before
14576 ISA 3.0, we only had X-FORM addressing for scalars in the
14577 traditional Altivec registers.
14579 2020-02-06 <zhongyunde@huawei.com>
14580 Vladimir Makarov <vmakarov@redhat.com>
14582 PR rtl-optimization/93561
14583 * lra-assigns.c (spill_for): Check that tested hard regno is not out of
14584 hard register range.
14586 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14588 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type
14591 2020-02-06 Segher Boessenkool <segher@kernel.crashing.org>
14593 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case
14594 where the low and the high 32 bits are equal to each other specially,
14595 with an rldimi instruction.
14597 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
14599 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main.
14601 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
14603 * config/arm/arm-tables.opt: Regenerate.
14605 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14608 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare.
14609 * config/aarch64/aarch64.c (aarch64_movk_shift): New function.
14610 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern.
14612 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14614 PR rtl-optimization/87763
14615 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern.
14617 2020-02-06 Delia Burduv <delia.burduv@arm.com>
14619 * config/aarch64/aarch64-simd-builtins.def
14620 (bfmlaq): New built-in function.
14621 (bfmlalb): New built-in function.
14622 (bfmlalt): New built-in function.
14623 (bfmlalb_lane): New built-in function.
14624 (bfmlalt_lane): New built-in function.
14625 * config/aarch64/aarch64-simd.md
14626 (aarch64_bfmmlaqv4sf): New pattern.
14627 (aarch64_bfmlal<bt>v4sf): New pattern.
14628 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern.
14629 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic.
14630 (vbfmlalbq_f32): New intrinsic.
14631 (vbfmlaltq_f32): New intrinsic.
14632 (vbfmlalbq_lane_f32): New intrinsic.
14633 (vbfmlaltq_lane_f32): New intrinsic.
14634 (vbfmlalbq_laneq_f32): New intrinsic.
14635 (vbfmlaltq_laneq_f32): New intrinsic.
14636 * config/aarch64/iterators.md (BF_MLA): New int iterator.
14637 (bt): New int attribute.
14639 2020-02-06 Uroš Bizjak <ubizjak@gmail.com>
14641 * config/i386/i386.md (*pushtf): Emit "#" instead of
14642 calling gcc_unreachable in insn output.
14645 (*pushsf_rex64): Ditto for alternatives other than 1.
14646 (*pushsf): Ditto for alternatives other than 1.
14648 2020-02-06 Martin Liska <mliska@suse.cz>
14650 PR gcov-profile/91971
14651 PR gcov-profile/93466
14652 * coverage.c (coverage_init): Revert mangling of
14653 path into filename. It can lead to huge filename length.
14654 Creation of subfolders seem more natural.
14656 2020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14659 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New.
14660 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs.
14661 Use arm_block_arith_comp_libfuncs_for_mode for HFmode.
14663 2020-02-06 Jakub Jelinek <jakub@redhat.com>
14666 * config/i386/predicates.md (avx_identity_operand): New predicate.
14667 * config/i386/sse.md (*avx_vec_concat<mode>_1): New
14668 define_insn_and_split.
14671 * omp-low.c (use_pointer_for_field): For nested constructs, also
14672 look for map clauses on target construct.
14673 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily
14674 taskreg_nesting_level.
14677 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding
14678 shared clause, call omp_notice_variable on outer context if any.
14680 2020-02-05 Jason Merrill <jason@redhat.com>
14683 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has
14684 non-zero address even if weak and not yet defined.
14686 2020-02-05 Martin Sebor <msebor@redhat.com>
14688 PR tree-optimization/92765
14689 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL.
14690 * tree-ssa-strlen.c (compute_string_length): Remove.
14691 (determine_min_objsize): Remove.
14692 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic.
14693 Avoid using type size as the upper bound on string length.
14694 (handle_builtin_string_cmp): Add an argument. Adjust.
14695 (strlen_check_and_optimize_call): Pass additional argument to
14696 handle_builtin_string_cmp.
14698 2020-02-05 Uroš Bizjak <ubizjak@gmail.com>
14700 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove.
14701 (*pushdi2_rex64 peephole2): Unconditionally split after
14702 epilogue_completed.
14703 (*ashl<mode>3_doubleword): Ditto.
14704 (*<shift_insn><mode>3_doubleword): Ditto.
14706 2020-02-05 Michael Meissner <meissner@linux.ibm.com>
14709 * config/rs6000/rs6000.c (get_vector_offset): Fix
14711 2020-02-05 Andrew Stubbs <ams@codesourcery.com>
14713 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space.
14715 2020-02-05 David Malcolm <dmalcolm@redhat.com>
14717 * doc/analyzer.texi
14718 (Special Functions for Debugging the Analyzer): Update description
14719 of __analyzer_dump_exploded_nodes.
14721 2020-02-05 Jakub Jelinek <jakub@redhat.com>
14724 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only
14725 include sets and not clobbers in the vzeroupper pattern.
14726 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that
14727 the parallel has 17 (64-bit) or 9 (32-bit) elts.
14728 (*avx_vzeroupper_1): New define_insn_and_split.
14731 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets,
14732 don't run when !optimize.
14733 (pass_split_before_regstack::gate): For STACK_REGS targets, run even
14736 2020-02-05 Richard Biener <rguenther@suse.de>
14738 PR middle-end/90648
14739 * genmatch.c (dt_node::gen_kids_1): Emit number of argument
14740 checks before matching calls.
14742 2020-02-05 Jakub Jelinek <jakub@redhat.com>
14744 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up
14745 function comment typo.
14747 PR middle-end/93555
14748 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or
14749 simd_clone_create failed when i == 0, adjust clone->nargs by
14752 2020-02-05 Martin Liska <mliska@suse.cz>
14755 * doc/invoke.texi: Document that one should
14756 not combine ASLR and -fpch.
14758 2020-02-04 Richard Biener <rguenther@suse.de>
14760 PR tree-optimization/93538
14761 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr.
14763 2020-02-04 Richard Biener <rguenther@suse.de>
14765 PR tree-optimization/91123
14766 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method.
14767 (vn_walk_cb_data::last_vuse): New member.
14768 (vn_walk_cb_data::saved_operands): Likewsie.
14769 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands.
14770 (vn_walk_cb_data::push_partial_def): Use finish.
14771 (vn_reference_lookup_2): Update last_vuse and use finish if
14772 we've saved operands.
14773 (vn_reference_lookup_3): Use finish and update calls to
14774 push_partial_defs everywhere. When translating through
14775 memcpy or aggregate copies save off operands and alias-set.
14776 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE
14777 operation for redundant store removal.
14779 2020-02-04 Richard Biener <rguenther@suse.de>
14781 PR tree-optimization/92819
14782 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid
14783 generating more stmts than before.
14785 2020-02-04 Martin Liska <mliska@suse.cz>
14787 * config/arm/arm.c (arm_gen_far_branch): Move the function
14788 outside of selftests.
14790 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14792 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
14793 function to adjust PC-relative vector addresses.
14794 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
14795 handle vectors with PC-relative addresses.
14797 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14799 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
14801 (hard_reg_and_mode_to_addr_mask): Delete.
14802 (rs6000_adjust_vec_address): If the original vector address
14803 was REG+REG or REG+OFFSET and the element is not zero, do the add
14804 of the elements in the original address before adding the offset
14805 for the vector element. Use address_to_insn_form to validate the
14806 address using the register being loaded, rather than guessing
14807 whether the address is a DS-FORM or DQ-FORM address.
14809 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14811 * config/rs6000/rs6000.c (get_vector_offset): New helper function
14812 to calculate the offset in memory from the start of a vector of a
14813 particular element. Add code to keep the element number in
14814 bounds if the element number is variable.
14815 (rs6000_adjust_vec_address): Move calculation of offset of the
14816 vector element to get_vector_offset.
14817 (rs6000_split_vec_extract_var): Do not do the initial AND of
14818 element here, move the code to get_vector_offset.
14820 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14822 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
14825 2020-02-03 Segher Boessenkool <segher@kernel.crashing.org>
14827 * config/rs6000/constraints.md: Improve documentation.
14829 2020-02-03 Richard Earnshaw <rearnsha@arm.com>
14832 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md)
14833 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change.
14835 2020-02-03 Andrew Stubbs <ams@codesourcery.com>
14837 * config.gcc: Remove "carrizo" support.
14838 * config/gcn/gcn-opts.h (processor_type): Likewise.
14839 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
14840 * config/gcn/gcn.opt (gpu_type): Likewise.
14841 * config/gcn/t-omp-device: Likewise.
14843 2020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14846 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
14847 * config/arm/arm.c (arm_gen_far_branch): New function
14848 arm_gen_far_branch.
14849 * config/arm/arm.md: Update b<cond> for Thumb2 range checks.
14851 2020-02-03 Julian Brown <julian@codesourcery.com>
14852 Tobias Burnus <tobias@codesourcery.com>
14854 * doc/invoke.texi: Update mention of OpenACC version to 2.6.
14856 2020-02-03 Jakub Jelinek <jakub@redhat.com>
14859 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit
14860 valid RTL to sum up the lowest and second lowest bytes of the popcnt
14863 2020-02-02 Vladimir Makarov <vmakarov@redhat.com>
14865 PR rtl-optimization/91333
14866 * ira-color.c (struct allocno_color_data): Add member
14868 (init_allocno_threads): Set the member up.
14869 (bucket_allocno_compare_func): Add compare hard reg
14872 2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
14874 nios2: Support for GOT-relative DW_EH_PE_datarel encoding.
14876 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION.
14877 * config.in: Regenerated.
14878 * configure: Regenerated.
14879 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling
14880 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION.
14881 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New.
14883 2020-02-01 Andrew Burgess <andrew.burgess@embecosm.com>
14885 * configure: Regenerate.
14887 2020-01-31 Vladimir Makarov <vmakarov@redhat.com>
14889 PR rtl-optimization/91333
14890 * ira-color.c (bucket_allocno_compare_func): Move conflict hard
14891 reg preferences comparison up.
14893 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14895 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro.
14896 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to
14897 aarch64-sve-builtins-base.h.
14898 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to
14899 aarch64-sve-builtins-base.cc.
14900 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane)
14901 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14902 (svcvtnt): Declare.
14903 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane)
14904 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14905 (svcvtnt): New functions.
14906 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane)
14907 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14908 (svcvtnt): New functions.
14909 (svcvt): Add a form that converts f32 to bf16.
14910 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat)
14911 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n):
14913 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type):
14914 Treat B as bfloat16_t.
14915 (ternary_bfloat_lane_base): New class.
14916 (ternary_bfloat_def): Likewise.
14917 (ternary_bfloat): New shape.
14918 (ternary_bfloat_lane_def): New class.
14919 (ternary_bfloat_lane): New shape.
14920 (ternary_bfloat_lanex2_def): New class.
14921 (ternary_bfloat_lanex2): New shape.
14922 (ternary_bfloat_opt_n_def): New class.
14923 (ternary_bfloat_opt_n): New shape.
14924 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro.
14925 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf)
14926 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns.
14927 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
14928 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14929 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14930 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise.
14931 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key
14932 the pattern off the narrow mode instead of the wider one.
14933 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator.
14934 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs.
14935 (sve_fp_op): Handle them.
14936 (SVE_BFLOAT_TERNARY_LONG): New int itertor.
14937 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
14939 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14941 * config/aarch64/arm_sve.h: Include arm_bf16.h.
14942 * config/aarch64/aarch64-modes.def (BF): Move definition before
14943 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF.
14944 (SVE_MODES): Handle BF modes.
14945 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
14947 (aarch64_full_sve_mode): Likewise.
14948 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF
14950 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF.
14951 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
14952 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count)
14953 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the
14955 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New
14957 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro.
14958 (TYPES_all_data): Add bf16.
14959 (TYPES_reinterpret1, TYPES_reinterpret): Likewise.
14960 (register_tuple_type): Increase buffer size.
14961 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type.
14962 (bf16): New type suffix.
14963 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv)
14964 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax)
14965 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr):
14966 Change type from all_data to all_arith.
14967 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp)
14968 (svminp): Likewise.
14970 2020-01-31 Dennis Zhang <dennis.zhang@arm.com>
14971 Matthew Malcomson <matthew.malcomson@arm.com>
14972 Richard Sandiford <richard.sandiford@arm.com>
14974 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension.
14975 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
14976 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
14977 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define
14978 __ARM_FEATURE_MATMUL_FP64.
14979 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16)
14980 (sve): Add AARCH64_FL_F32MM to the list of extensions that should
14981 be disabled at the same time.
14982 (f32mm): New extension.
14983 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro.
14984 (AARCH64_FL_F64MM): Bump to the next bit up.
14985 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM)
14986 (TARGET_SVE_F64MM): New macros.
14987 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator.
14988 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL)
14989 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q)
14990 (UNSPEC_ZIP2Q): New unspeccs.
14991 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators.
14992 (optab, sur, perm_insn): Handle the new unspecs.
14993 (sve_fp_op): Handle UNSPEC_FMMLA. Resort.
14994 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
14995 TARGET_SVE_F64MM instead of separate tests.
14996 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern.
14997 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise.
14998 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise.
14999 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise.
15000 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise.
15001 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro.
15002 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it.
15003 (TYPES_s_signed): New macro.
15004 (TYPES_s_integer): Use it.
15005 (TYPES_d_float): New macro.
15006 (TYPES_d_data): Use it.
15007 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare.
15008 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq)
15009 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise.
15010 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class.
15011 (svmmla): New shape.
15012 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3
15013 template parameters.
15014 (ternary_resize2_lane_base): Likewise.
15015 (ternary_resize2_base): New class.
15016 (ternary_qq_lane_base): Likewise.
15017 (ternary_intq_uintq_lane_def): Likewise.
15018 (ternary_intq_uintq_lane): New shape.
15019 (ternary_intq_uintq_opt_n_def): New class
15020 (ternary_intq_uintq_opt_n): New shape.
15021 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base.
15022 (ternary_uintq_intq_def): New class.
15023 (ternary_uintq_intq): New shape.
15024 (ternary_uintq_intq_lane_def): New class.
15025 (ternary_uintq_intq_lane): New shape.
15026 (ternary_uintq_intq_opt_n_def): New class.
15027 (ternary_uintq_intq_opt_n): New shape.
15028 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot)
15029 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla)
15030 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare.
15031 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl):
15033 (svdotprod_lane_impl): ...this new class.
15034 (svmmla_impl, svusdot_impl): New classes.
15035 (svdot_lane): Update to use svdotprod_lane_impl.
15036 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot)
15037 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New
15039 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base
15040 function, with no types defined.
15041 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New
15042 AARCH64_FL_I8MM functions.
15043 (svmmla): New AARCH64_FL_F32MM function.
15044 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6.
15045 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New
15046 AARCH64_FL_F64MM function.
15047 (REQUIRED_EXTENSIONS):
15049 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
15051 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
15054 2020-01-31 Uroš Bizjak <ubizjak@gmail.com>
15056 * config/i386/i386.md (*movoi_internal_avx): Do not check for
15057 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling.
15058 (*movti_internal): Do not check for
15059 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
15060 (*movtf_internal): Move check for TARGET_SSE2 and size optimization
15061 just after check for TARGET_AVX.
15062 (*movdf_internal): Ditto.
15063 * config/i386/mmx.md (*mov<mode>_internal): Do not check for
15064 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
15065 * config/i386/sse.md (mov<mode>_internal): Only check
15066 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check
15067 for TARGET_SSE2 and size optimization just after check for TARGET_AVX.
15068 (<sse>_andnot<mode>3<mask_name>): Move check for
15069 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX.
15070 (<code><mode>3<mask_name>): Ditto.
15071 (*andnot<mode>3): Ditto.
15072 (*andnottf3): Ditto.
15073 (*<code><mode>3): Ditto.
15074 (*<code>tf3): Ditto.
15075 (*andnot<VI:mode>3): Remove
15076 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling.
15077 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto.
15078 (*<code><VI12_AVX_AVX512F:mode>3): Ditto.
15079 (sse4_1_blendv<ssemodesuffix>): Ditto.
15080 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL):
15081 Explain that tune applies to 128bit instructions only.
15083 2020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com>
15085 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count
15086 to definition of hsa_kernel_description. Parse assembly to find SGPR
15087 and VGPR count of kernel and store in hsa_kernel_description.
15089 2020-01-31 Tamar Christina <tamar.christina@arm.com>
15091 PR rtl-optimization/91838
15092 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case
15093 to truncate if allowed or reject combination.
15095 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
15097 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step.
15098 (find_inv_vars_cb): Likewise.
15100 2020-01-31 David Malcolm <dmalcolm@redhat.com>
15102 * calls.c (special_function_p): Split out the check for DECL_NAME
15103 being non-NULL and fndecl being extern at file scope into a
15104 new maybe_special_function_p and call it. Drop check for fndecl
15105 being non-NULL that was after a usage of DECL_NAME (fndecl).
15106 * tree.h (maybe_special_function_p): New inline function.
15108 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
15110 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ...
15111 (mask_gather_load<mode>): ... here, and zero-initialize the
15113 (maskload<mode>di): Zero-initialize the destination.
15114 * config/gcn/gcn.c:
15116 2020-01-30 David Malcolm <dmalcolm@redhat.com>
15119 * doc/analyzer.texi (Limitations): Note that constraints on
15120 floating-point values are currently ignored.
15122 2020-01-30 Jakub Jelinek <jakub@redhat.com>
15125 * symtab.c (symtab_node::noninterposable_alias): If localalias
15126 already exists, but is not usable, append numbers after it until
15127 a unique name is found. Formatting fix.
15129 PR middle-end/93505
15130 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range
15133 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
15135 * config/gcn/gcn.c (print_operand): Handle LTGT.
15136 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt.
15138 2020-01-30 Richard Biener <rguenther@suse.de>
15140 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST
15141 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE.
15143 2020-01-30 John David Anglin <danglin@gcc.gnu.org>
15145 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers
15146 without a DECL in .data.rel.ro.local.
15148 2020-01-30 Jakub Jelinek <jakub@redhat.com>
15151 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4
15155 * config/i386/sse.md
15156 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ...
15157 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use
15158 any_extend code iterator instead of always zero_extend.
15159 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ...
15160 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this.
15161 Use any_extend code iterator instead of always zero_extend.
15162 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ...
15163 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this.
15164 Use any_extend code iterator instead of always zero_extend.
15165 (*sse2_pmovmskb_ext): New define_insn.
15166 (*sse2_pmovmskb_ext_lt): New define_insn_and_split.
15169 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split.
15170 (*popcountsi2_zext_falsedep): New define_insn.
15172 2020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15174 * config.in: Regenerated.
15175 * configure: Regenerated.
15177 2020-01-29 Tobias Burnus <tobias@codesourcery.com>
15180 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as
15181 LLVM's assembler changed the default in version 9.
15183 2020-01-24 Jeff Law <law@redhat.com>
15185 PR tree-optimization/89689
15186 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure.
15188 2020-01-29 Richard Sandiford <richard.sandiford@arm.com>
15192 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15194 PR rtl-optimization/87763
15195 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
15196 simplification to handle subregs as well as bare regs.
15197 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
15199 2020-01-29 Joel Hutton <Joel.Hutton@arm.com>
15202 * ira.c (ira): Revert use of simplified LRA algorithm.
15204 2020-01-29 Martin Jambor <mjambor@suse.cz>
15206 PR tree-optimization/92706
15207 * tree-sra.c (struct access): Fields first_link, last_link,
15208 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link,
15209 next_rhs_queued and grp_rhs_queued respectively, new fields
15210 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued.
15211 (struct assign_link): Field next renamed to next_rhs, new field
15212 next_lhs. Updated comment.
15213 (work_queue_head): Renamed to rhs_work_queue_head.
15214 (lhs_work_queue_head): New variable.
15215 (add_link_to_lhs): New function.
15216 (relink_to_new_repr): Also relink LHS lists.
15217 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue.
15218 (add_access_to_lhs_work_queue): New function.
15219 (pop_access_from_work_queue): Renamed to
15220 pop_access_from_rhs_work_queue.
15221 (pop_access_from_lhs_work_queue): New function.
15222 (build_accesses_from_assign): Also add links to LHS lists and to LHS
15224 (child_would_conflict_in_lacc): Renamed to
15225 child_would_conflict_in_acc. Adjusted parameter names.
15226 (create_artificial_child_access): New parameter set_grp_read, use it.
15227 (subtree_mark_written_and_enqueue): Renamed to
15228 subtree_mark_written_and_rhs_enqueue.
15229 (propagate_subaccesses_across_link): Renamed to
15230 propagate_subaccesses_from_rhs.
15231 (propagate_subaccesses_from_lhs): New function.
15232 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to
15235 2020-01-29 Martin Jambor <mjambor@suse.cz>
15237 PR tree-optimization/92706
15238 * tree-sra.c (struct access): Adjust comment of
15239 grp_total_scalarization.
15240 (find_access_in_subtree): Look for single children spanning an entire
15242 (scalarizable_type_p): Allow register accesses, adjust callers.
15243 (completely_scalarize): Remove function.
15244 (scalarize_elem): Likewise.
15245 (create_total_scalarization_access): Likewise.
15246 (sort_and_splice_var_accesses): Do not track total scalarization
15248 (analyze_access_subtree): New parameter totally, adjust to new meaning
15249 of grp_total_scalarization.
15250 (analyze_access_trees): Pass new parameter to analyze_access_subtree.
15251 (can_totally_scalarize_forest_p): New function.
15252 (create_total_scalarization_access): Likewise.
15253 (create_total_access_and_reshape): Likewise.
15254 (total_should_skip_creating_access): Likewise.
15255 (totally_scalarize_subtree): Likewise.
15256 (analyze_all_variable_accesses): Perform total scalarization after
15257 subaccess propagation using the new functions above.
15258 (initialize_constant_pool_replacements): Output initializers by
15259 traversing the access tree.
15261 2020-01-29 Martin Jambor <mjambor@suse.cz>
15263 * tree-sra.c (verify_sra_access_forest): New function.
15264 (verify_all_sra_access_forests): Likewise.
15265 (create_artificial_child_access): Set parent.
15266 (analyze_all_variable_accesses): Call the verifier.
15268 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
15270 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge
15271 if called on indirect edge.
15272 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of
15273 speculative call if needed.
15275 2020-01-29 Richard Biener <rguenther@suse.de>
15277 PR tree-optimization/93428
15278 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load
15279 permutation when the load node is created.
15280 (vect_analyze_slp_instance): Re-use it here.
15282 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
15284 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning.
15286 2020-01-28 Vladimir Makarov <vmakarov@redhat.com>
15288 PR rtl-optimization/93272
15289 * ira-lives.c (process_out_of_region_eh_regs): New function.
15290 (process_bb_node_lives): Call it.
15292 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
15294 * coverage.c (read_counts_file): Make error message lowercase.
15296 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
15298 * profile-count.c (profile_quality_display_names): Fix ordering.
15300 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
15303 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site
15304 hash only when edge is first within the sequence.
15305 (cgraph_edge::set_call_stmt): Update handling of speculative calls.
15306 (symbol_table::create_edge): Do not set target_prob.
15307 (cgraph_edge::remove_caller): Watch for speculative calls when updating
15308 the call site hash.
15309 (cgraph_edge::make_speculative): Drop target_prob parameter.
15310 (cgraph_edge::speculative_call_info): Remove.
15311 (cgraph_edge::first_speculative_call_target): New member function.
15312 (update_call_stmt_hash_for_removing_direct_edge): New function.
15313 (cgraph_edge::resolve_speculation): Rewrite to new API.
15314 (cgraph_edge::speculative_call_for_target): New member function.
15315 (cgraph_edge::make_direct): Rewrite to new API; fix handling of
15316 multiple speculation targets.
15317 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating
15319 (verify_speculative_call): Verify that targets form an interval.
15320 * cgraph.h (cgraph_edge::speculative_call_info): Remove.
15321 (cgraph_edge::first_speculative_call_target): New member function.
15322 (cgraph_edge::next_speculative_call_target): New member function.
15323 (cgraph_edge::speculative_call_target_ref): New member function.
15324 (cgraph_edge;:speculative_call_indirect_edge): New member funtion.
15325 (cgraph_edge): Remove target_prob.
15326 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
15327 Fix handling of speculative calls.
15328 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals.
15329 * ipa-fnsummary.c (analyze_function_body): Likewise.
15330 * ipa-inline.c (speculation_useful_p): Use new speculative call API.
15331 * ipa-profile.c (dump_histogram): Fix formating.
15332 (ipa_profile_generate_summary): Watch for overflows.
15333 (ipa_profile): Do not require probablity to be 1/2; update to new API.
15334 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API.
15335 (update_indirect_edges_after_inlining): Update to new API.
15336 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call
15338 * profile-count.h: (profile_probability::adjusted): New.
15339 * tree-inline.c (copy_bb): Update to new speculative call API; fix
15340 updating of profile.
15341 * value-prof.c (gimple_ic_transform): Rename to ...
15342 (dump_ic_profile): ... this one; update dumping.
15343 (stream_in_histogram_value): Fix formating.
15344 (gimple_value_profile_transformations): Update.
15346 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
15349 * config/i386/i386.md (*movoi_internal_avx): Remove
15350 TARGET_SSE_TYPELESS_STORES check.
15351 (*movti_internal): Prefer TARGET_AVX over
15352 TARGET_SSE_TYPELESS_STORES.
15353 (*movtf_internal): Likewise.
15354 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over
15355 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check
15356 from TARGET_SSE_TYPELESS_STORES.
15358 2020-01-28 David Malcolm <dmalcolm@redhat.com>
15360 * diagnostic-core.h (warning_at): Rename overload to...
15361 (warning_meta): ...this.
15362 (emit_diagnostic_valist): Delete decl of overload taking
15363 diagnostic_metadata.
15364 * diagnostic.c (emit_diagnostic_valist): Likewise for defn.
15365 (warning_at): Rename overload taking diagnostic_metadata to...
15366 (warning_meta): ...this.
15368 2020-01-28 Richard Biener <rguenther@suse.de>
15370 PR tree-optimization/93439
15371 * tree-parloops.c (create_loop_fn): Move clique bookkeeping...
15372 * tree-cfg.c (move_sese_region_to_fn): ... here.
15373 (verify_types_in_gimple_reference): Verify used cliques are
15376 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
15379 * config/i386/i386-options.c (set_ix86_tune_features): Add an
15380 argument of a pointer to struct gcc_options and pass it to
15381 parse_mtune_ctrl_str.
15382 (ix86_function_specific_restore): Pass opts to
15383 set_ix86_tune_features.
15384 (ix86_option_override_internal): Likewise.
15385 (parse_mtune_ctrl_str): Add an argument of a pointer to struct
15386 gcc_options and use it for x_ix86_tune_ctrl_string.
15388 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15390 PR rtl-optimization/87763
15391 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
15392 simplification to handle subregs as well as bare regs.
15393 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
15395 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15397 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully
15398 for reduction chains that (now) include a call.
15400 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15402 PR tree-optimization/92822
15403 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling
15404 out the don't-care elements of a vector whose significant elements
15405 are duplicates, make the don't-care elements duplicates too.
15407 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15409 PR tree-optimization/93434
15410 * tree-predcom.c (split_data_refs_to_components): Record which
15411 components have had aliasing loads removed. Prevent store-store
15412 commoning for all such components.
15414 2020-01-28 Jakub Jelinek <jakub@redhat.com>
15417 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not
15418 -1 or is_vshift is true, use new_vector with number of elts npatterns
15419 rather than new_unary_operation.
15421 PR tree-optimization/93454
15422 * gimple-fold.c (fold_array_ctor_reference): Perform
15423 elt_size.to_uhwi () just once, instead of calling it in every
15424 iteration. Punt if that value is above size of the temporary
15425 buffer. Decrease third native_encode_expr argument when
15426 bufoff + elt_sz is above size of buf.
15428 2020-01-27 Joseph Myers <joseph@codesourcery.com>
15430 * config/mips/mips.c (mips_declare_object_name)
15431 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object.
15433 2020-01-27 Martin Liska <mliska@suse.cz>
15435 PR gcov-profile/93403
15436 * tree-profile.c (gimple_init_gcov_profiler): Generate
15437 both __gcov_indirect_call_profiler_v4 and
15438 __gcov_indirect_call_profiler_v4_atomic.
15440 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15443 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
15445 (@aarch64_split_simd_mov<mode>): Use it.
15446 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
15447 Leave the vec_extract patterns to handle 2-element vectors.
15448 (aarch64_simd_mov_from_<mode>high): Likewise.
15449 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
15450 (vec_extractv2dfv1df): Likewise.
15452 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15454 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match
15455 jump conditions for *compare_condjump<GPI:mode>.
15457 2020-01-27 David Malcolm <dmalcolm@redhat.com>
15460 * digraph.cc (test_edge::test_edge): Specify template for base
15463 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15465 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost.
15467 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15469 * config/arc/arc-protos.h (gen_mlo): Remove.
15470 (gen_mhi): Likewise.
15471 * config/arc/arc.c (AUX_MULHI): Define.
15472 (arc_must_save_reister): Special handling for r58/59.
15473 (arc_compute_frame_size): Consider mlo/mhi registers.
15474 (arc_save_callee_saves): Emit fp/sp move only when emit_move
15476 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from
15477 mlo/mhi name selection.
15478 (arc_restore_callee_saves): Don't early restore blink when ISR.
15479 (arc_expand_prologue): Add mlo/mhi saving.
15480 (arc_expand_epilogue): Add mlo/mhi restoring.
15483 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register
15484 numbering when MUL64 option is used.
15485 (DWARF2_FRAME_REG_OUT): Define.
15486 * config/arc/arc.md (arc600_stall): New pattern.
15487 (VUNSPEC_ARC_ARC600_STALL): Define.
15488 (mulsi64): Use correct mlo/mhi registers.
15489 (mulsi_600): Clean it up.
15490 * config/arc/predicates.md (mlo_operand): Remove any dependency on
15492 (mhi_operand): Likewise.
15494 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15495 Petro Karashchenko <petro.karashchenko@ring.com>
15497 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct
15498 attributes if needed.
15499 (prepare_move_operands): Generate special unspec instruction for
15501 (arc_isuncached_mem_p): Propagate uncached attribute to each
15503 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
15504 (VUNSPEC_ARC_STDI): Likewise.
15505 (ALLI): New mode iterator.
15506 (mALLI): New mode attribute.
15507 (lddi): New instruction pattern.
15509 (stdidi_split): Split instruction for architectures which are not
15510 supporting ll64 option.
15511 (lddidi_split): Likewise.
15513 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15515 PR rtl-optimization/92989
15516 * lra-lives.c (process_bb_lives): Update the live-in set before
15517 processing additional clobbers.
15519 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15521 PR rtl-optimization/93170
15522 * cselib.c (cselib_invalidate_regno_val): New function, split out
15524 (cselib_invalidate_regno): ...here.
15525 (cselib_invalidated_by_call_p): New function.
15526 (cselib_process_insn): Iterate over all the hard-register entries in
15527 REG_VALUES and invalidate any that cross call-clobbered registers.
15529 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15531 * dojump.c (split_comparison): Use HONOR_NANS rather than
15532 HONOR_SNANS when splitting LTGT.
15534 2020-01-27 Martin Liska <mliska@suse.cz>
15537 * opts.c (print_filtered_help): Exclude language-specific
15538 options from --help=common unless enabled in all FEs.
15540 2020-01-27 Martin Liska <mliska@suse.cz>
15542 * opts.c (print_help): Exclude params from
15543 all except --help=param.
15545 2020-01-27 Martin Liska <mliska@suse.cz>
15548 * config/i386/i386-features.c (make_resolver_func):
15549 Align the code with ppc64 target implementation.
15550 Do not generate a unique name for resolver function.
15552 2020-01-27 Richard Biener <rguenther@suse.de>
15554 PR tree-optimization/93397
15555 * tree-vect-slp.c (vect_analyze_slp_instance): Delay
15556 converted reduction chain SLP graph adjustment.
15558 2020-01-26 Marek Polacek <polacek@redhat.com>
15561 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on
15564 2020-01-26 Jason Merrill <jason@redhat.com>
15567 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING
15570 2020-01-26 Darius Galis <darius.galis@cyberthorstudios.com>
15572 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint
15573 (rx_setmem): Likewise.
15575 2020-01-26 Jakub Jelinek <jakub@redhat.com>
15578 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword):
15579 Use nonimmediate_operand instead of x86_64_hilo_general_operand and
15580 drop <di> from constraint of last operand.
15583 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for
15584 TARGET_AVX2 and V4DFmode not in the split condition, but in the
15585 pattern condition, though allow { 0, 0, 0, 0 } broadcast always.
15587 2020-01-25 Feng Xue <fxue@os.amperecomputing.com>
15590 * ipa-cp.c (get_info_about_necessary_edges): Remove value
15593 2020-01-24 Jeff Law <law@redhat.com>
15595 PR tree-optimization/92788
15596 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX
15599 2020-01-24 Jakub Jelinek <jakub@redhat.com>
15602 * config/i386/sse.md (*avx_vperm_broadcast_v4sf,
15603 *avx_vperm_broadcast_<mode>,
15604 <sse2_avx_avx512f>_vpermil<mode><mask_name>,
15605 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>):
15606 Move before avx2_perm<mode>/avx512f_perm<mode>.
15609 * simplify-rtx.c (simplify_const_unary_operation,
15610 simplify_const_binary_operation): Punt for mode precision above
15611 MAX_BITSIZE_MODE_ANY_INT.
15613 2020-01-24 Andrew Pinski <apinski@marvell.com>
15615 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change
15616 alu.shift_reg to 0.
15618 2020-01-24 Jeff Law <law@redhat.com>
15621 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg
15622 for REGs. Call output_operand_lossage to get more reasonable
15625 2020-01-24 Andrew Stubbs <ams@codesourcery.com>
15627 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use
15628 gcn_fp_compare_operator.
15629 (vec_cmpu<mode>di): Use gcn_compare_operator.
15630 (vec_cmp<u>v64qidi): Use gcn_compare_operator.
15631 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator.
15632 (vec_cmpu<mode>di_exec): Use gcn_compare_operator.
15633 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator.
15634 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator.
15635 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator.
15636 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use
15637 gcn_fp_compare_operator.
15638 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use
15639 gcn_fp_compare_operator.
15640 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use
15641 gcn_fp_compare_operator.
15642 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use
15643 gcn_fp_compare_operator.
15645 2020-01-24 Maciej W. Rozycki <macro@wdc.com>
15647 * doc/install.texi (Cross-Compiler-Specific Options): Document
15648 `--with-toolexeclibdir' option.
15650 2020-01-24 Hans-Peter Nilsson <hp@axis.com>
15652 * target.def (flags_regnum): Also mention effect on delay slot filling.
15653 * doc/tm.texi: Regenerate.
15655 2020-01-23 Jeff Law <law@redhat.com>
15657 PR translation/90162
15658 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text.
15660 2020-01-23 Mikael Tillenius <mti-1@tillenius.com>
15663 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of
15666 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15668 PR rtl-optimization/93402
15669 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust
15672 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15674 * config.in: Regenerated.
15675 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
15676 for TARGET_LIBC_GNUSTACK.
15677 * configure: Regenerated.
15678 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
15679 found to be 2.31 or greater.
15681 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15683 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
15685 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
15686 (mips_asm_file_end): New function. Delegate to
15687 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
15688 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.
15690 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15693 * config/i386/i386-modes.def (POImode): New mode.
15694 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160.
15695 * config/i386/i386.md (DPWI): New mode attribute.
15696 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>.
15697 (QWI): Rename to...
15698 (QPWI): ... this. Use POI instead of OI for TImode.
15699 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1,
15700 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI>
15703 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15706 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New
15708 (speculation_tracker_rev): New pattern.
15709 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation):
15710 Use speculation_tracker_rev to track the inverse condition.
15712 2020-01-23 Richard Biener <rguenther@suse.de>
15714 PR tree-optimization/93381
15715 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take
15716 alias-set of the def as argument and record the first one.
15717 (vn_walk_cb_data::first_set): New member.
15718 (vn_reference_lookup_3): Pass the alias-set of the current def
15719 to push_partial_def. Fix alias-set used in the aggregate copy
15721 (vn_reference_lookup): Consistently set *last_vuse_ptr.
15722 * real.c (clear_significand_below): Fix out-of-bound access.
15724 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15727 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3):
15728 New define_insn patterns.
15730 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15732 * doc/sourcebuild.texi (check-function-bodies): Add an
15733 optional target/xfail selector.
15735 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15737 PR rtl-optimization/93124
15738 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to
15739 bare USE and CLOBBER insns.
15741 2020-01-22 Andrew Pinski <apinski@marvell.com>
15743 * config/arc/arc.c (output_short_suffix): Check insn for nullness.
15745 2020-01-22 David Malcolm <dmalcolm@redhat.com>
15748 * gdbinit.in (break-on-saved-diagnostic): Update for move of
15749 diagnostic_manager into "ana" namespace.
15750 * selftest-run-tests.c (selftest::run_tests): Update for move of
15751 selftest::run_analyzer_selftests to
15752 ana::selftest::run_analyzer_selftests.
15754 2020-01-22 Richard Sandiford <richard.sandiford@arm.com>
15756 * cfgexpand.c (union_stack_vars): Update the size.
15758 2020-01-22 Richard Biener <rguenther@suse.de>
15760 PR tree-optimization/93381
15761 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting
15762 throughout, handle all conversions the same.
15764 2020-01-22 Jakub Jelinek <jakub@redhat.com>
15767 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use
15768 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate
15769 predicate, not whenever it is CONST_INT. Otherwise, force_reg it.
15770 Call force_reg on high_in2 unconditionally.
15772 2020-01-22 Martin Liska <mliska@suse.cz>
15774 PR tree-optimization/92924
15775 * profile.c (compute_value_histograms): Divide
15776 all counter values.
15778 2020-01-22 Jakub Jelinek <jakub@redhat.com>
15781 * output.h (assemble_name_resolve): Declare.
15782 * varasm.c (assemble_name_resolve): New function.
15783 (assemble_name): Use it.
15784 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define.
15786 2020-01-22 Joseph Myers <joseph@codesourcery.com>
15788 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to
15789 update_web_docs_git instead of update_web_docs_svn.
15791 2020-01-21 Andrew Pinski <apinski@marvell.com>
15794 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
15795 as PTR mode. Have operand 1 as being modeless, it can be P mode.
15796 (*tlsgd_small_<mode>): Likewise.
15797 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
15798 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
15799 register. Convert that register back to dest using convert_mode.
15801 2020-01-21 Jim Wilson <jimw@sifive.com>
15803 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
15806 2020-01-21 H.J. Lu <hongjiu.lu@intel.com>
15807 Uros Bizjak <ubizjak@gmail.com>
15810 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode
15812 (legitimize_tls_address): Do GNU2 TLS address computation in
15813 ptr_mode and zero-extend result to Pmode.
15814 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace
15815 :P with :PTR and Pmode with ptr_mode.
15816 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise.
15817 (*tls_dynamic_gnu2_call_64_<mode>): Likewise.
15818 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise.
15820 2020-01-21 Jakub Jelinek <jakub@redhat.com>
15823 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify
15824 the last two operands are CONST_INT_P before using them as such.
15826 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
15828 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name
15829 to get the integer element types.
15831 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
15833 * config/aarch64/aarch64-sve-builtins.h
15834 (function_expander::convert_to_pmode): Declare.
15835 * config/aarch64/aarch64-sve-builtins.cc
15836 (function_expander::convert_to_pmode): New function.
15837 (function_expander::get_contiguous_base): Use it.
15838 (function_expander::prepare_gather_address_operands): Likewise.
15839 * config/aarch64/aarch64-sve-builtins-sve2.cc
15840 (svwhilerw_svwhilewr_impl::expand): Likewise.
15842 2020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com>
15845 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set
15846 cfun->machine->label_is_assembled.
15847 (aarch64_print_patchable_function_entry): New.
15848 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define.
15849 * config/aarch64/aarch64.h (struct machine_function): New field,
15850 label_is_assembled.
15852 2020-01-21 David Malcolm <dmalcolm@redhat.com>
15855 * ipa-profile.c (ipa_profile): Delete call_sums and set it to
15858 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15861 * cgraph.c (cgraph_edge::resolve_speculation,
15862 cgraph_edge::redirect_call_stmt_to_callee): Fix update of
15863 call_stmt_site_hash.
15865 2020-01-21 Martin Liska <mliska@suse.cz>
15867 * config/rs6000/rs6000.c (common_mode_defined): Remove
15870 2020-01-21 Richard Biener <rguenther@suse.de>
15872 PR tree-optimization/92328
15873 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve
15874 type when value-numbering same-sized store by inserting a
15876 (eliminate_dom_walker::eliminate_stmt): When eliminating
15877 a redundant store handle bit-reinterpretation of the same value.
15879 2020-01-21 Andrew Pinski <apinski@marvel.com>
15882 * tree-into-ssa.c (prepare_block_for_update_1): Split out
15884 (prepare_block_for_update): This. Use a worklist instead of
15887 2020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15889 * config/arm/arm.c (clear_operation_p):
15890 Initialise last_regno, skip first iteration
15891 based on the first_set value and use ints instead
15892 of the unnecessary HOST_WIDE_INTs.
15894 2020-01-21 Jakub Jelinek <jakub@redhat.com>
15897 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for
15898 compare_mode other than SFmode or DFmode.
15900 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
15903 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
15904 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
15905 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
15907 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15909 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
15911 2020-01-20 Andrew Pinski <apinski@marvell.com>
15913 PR middle-end/93242
15914 * targhooks.c (default_print_patchable_function_entry): Use
15915 output_asm_insn to emit the nop instruction.
15917 2020-01-20 Fangrui Song <maskray@google.com>
15919 PR middle-end/93194
15920 * targhooks.c (default_print_patchable_function_entry): Align to
15923 2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
15926 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to
15927 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode.
15928 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ...
15929 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P.
15930 (*tls_dynamic_gnu2_lea_64): Renamed to ...
15931 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P.
15932 Remove the {q} suffix from lea.
15933 (*tls_dynamic_gnu2_call_64): Renamed to ...
15934 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P.
15935 (*tls_dynamic_gnu2_combine_64): Renamed to ...
15936 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P.
15937 Pass Pmode to gen_tls_dynamic_gnu2_64.
15939 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15941 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1.
15943 2020-01-20 Richard Sandiford <richard.sandiford@arm.com>
15945 * config/aarch64/aarch64-sve-builtins-base.cc
15946 (svld1ro_impl::memory_vector_mode): Remove parameter name.
15948 2020-01-20 Richard Biener <rguenther@suse.de>
15951 * dwarf2out.c (prune_unused_types): Unconditionally mark
15952 called function DIEs.
15954 2020-01-20 Martin Liska <mliska@suse.cz>
15956 PR tree-optimization/93199
15957 * tree-eh.c (struct leh_state): Add
15958 new field outer_non_cleanup.
15959 (cleanup_is_dead_in): Pass leh_state instead
15960 of eh_region. Add a checking that state->outer_non_cleanup
15961 points to outer non-clean up region.
15962 (lower_try_finally): Record outer_non_cleanup
15964 (lower_catch): Likewise.
15965 (lower_eh_filter): Likewise.
15966 (lower_eh_must_not_throw): Likewise.
15967 (lower_cleanup): Likewise.
15969 2020-01-20 Richard Biener <rguenther@suse.de>
15971 PR tree-optimization/93094
15972 * tree-vectorizer.h (vect_loop_versioning): Adjust.
15973 (vect_transform_loop): Likewise.
15974 * tree-vectorizer.c (try_vectorize_loop_1): Pass down
15975 loop_vectorized_call to vect_transform_loop.
15976 * tree-vect-loop.c (vect_transform_loop): Pass down
15977 loop_vectorized_call to vect_loop_versioning.
15978 * tree-vect-loop-manip.c (vect_loop_versioning): Use
15979 the earlier discovered loop_vectorized_call.
15981 2020-01-19 Eric S. Raymond <esr@thyrsus.com>
15983 * doc/contribute.texi: Update for SVN -> Git transition.
15984 * doc/install.texi: Likewise.
15986 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15989 * cgraph.c (cgraph_edge::make_speculative): Increase number of
15990 speculative targets.
15991 (verify_speculative_call): New function
15992 (cgraph_node::verify_node): Use it.
15993 * ipa-profile.c (ipa_profile): Fix formating; do not set number of
15996 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15999 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting.
16000 (cgraph_edge::make_direct): Remove all indirect targets.
16001 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct..
16002 (cgraph_node::verify_node): Verify that only one call_stmt or
16003 lto_stmt_uid is set.
16004 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or
16006 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt.
16007 (lto_output_ref): Simplify streaming of stmt.
16008 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid.
16010 2020-01-18 Tamar Christina <tamar.christina@arm.com>
16012 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode):
16013 Mark parameter unused.
16015 2020-01-18 Hans-Peter Nilsson <hp@axis.com>
16017 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux*
16019 2019-01-18 Gerald Pfeifer <gerald@pfeifer.com>
16021 * varpool.c (ctor_useable_for_folding_p): Fix grammar.
16023 2020-01-18 Iain Sandoe <iain@sandoe.co.uk>
16025 * Makefile.in: Add coroutine-passes.o.
16026 * builtin-types.def (BT_CONST_SIZE): New.
16027 (BT_FN_BOOL_PTR): New.
16028 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New.
16029 * builtins.def (DEF_COROUTINE_BUILTIN): New.
16030 * coroutine-builtins.def: New file.
16031 * coroutine-passes.cc: New file.
16032 * function.h (struct GTY function): Add a bit to indicate that the
16033 function is a coroutine component.
16034 * internal-fn.c (expand_CO_FRAME): New.
16035 (expand_CO_YIELD): New.
16036 (expand_CO_SUSPN): New.
16037 (expand_CO_ACTOR): New.
16038 * internal-fn.def (CO_ACTOR): New.
16042 * passes.def: Add pass_coroutine_lower_builtins,
16043 pass_coroutine_early_expand_ifns.
16044 * tree-pass.h (make_pass_coroutine_lower_builtins): New.
16045 (make_pass_coroutine_early_expand_ifns): New.
16046 * doc/invoke.texi: Document the fcoroutines command line
16049 2020-01-18 Jakub Jelinek <jakub@redhat.com>
16051 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable.
16054 * config/arm/arm.c (clear_operation_p): Don't use REGNO until
16055 after checking the argument is a REG. Don't use REGNO (reg)
16056 again to set last_regno, reuse regno variable instead.
16058 2020-01-17 David Malcolm <dmalcolm@redhat.com>
16060 * doc/analyzer.texi (Limitations): Add note about NaN.
16062 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16063 Sudakshina Das <sudi.das@arm.com>
16065 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
16066 and valid immediate.
16067 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
16068 (lshrdi3): Generate thumb2_lsrl for valid immediates.
16069 * config/arm/constraints.md (Pg): New.
16070 * config/arm/predicates.md (long_shift_imm): New.
16071 (arm_reg_or_long_shift_imm): Likewise.
16072 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
16073 (thumb2_lsll): Likewise.
16074 (thumb2_lsrl): New.
16076 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16077 Sudakshina Das <sudi.das@arm.com>
16079 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
16080 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
16081 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
16082 register pairs for doubleword quantities for ARMv8.1M-Mainline.
16083 * config/arm/thumb2.md (thumb2_asrl): New.
16084 (thumb2_lsll): Likewise.
16086 2020-01-17 Jakub Jelinek <jakub@redhat.com>
16088 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
16091 2020-01-17 Alexander Monakov <amonakov@ispras.ru>
16093 * gdbinit.in (help-gcc-hooks): New command.
16094 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
16095 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
16098 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
16100 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the
16101 correct target macro.
16103 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
16105 * config/aarch64/aarch64-protos.h
16106 (aarch64_sve_ld1ro_operand_p): New.
16107 * config/aarch64/aarch64-sve-builtins-base.cc
16108 (class load_replicate): New.
16109 (class svld1ro_impl): New.
16110 (class svld1rq_impl): Change to inherit from load_replicate.
16111 (svld1ro): New sve intrinsic function base.
16112 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
16113 New DEF_SVE_FUNCTION.
16114 * config/aarch64/aarch64-sve-builtins-base.h
16115 (svld1ro): New decl.
16116 * config/aarch64/aarch64-sve-builtins.cc
16117 (function_expander::add_mem_operand): Modify assert to allow
16119 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
16121 * config/aarch64/aarch64.c
16122 (aarch64_sve_ld1rq_operand_p): Implement in terms of ...
16123 (aarch64_sve_ld1rq_ld1ro_operand_p): This.
16124 (aarch64_sve_ld1ro_operand_p): New.
16125 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
16126 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
16127 * config/aarch64/predicates.md
16128 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New.
16130 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
16132 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
16133 Introduce this ACLE specified predefined macro.
16134 * config/aarch64/aarch64-option-extensions.def (f64mm): New.
16135 (fp): Disabling this disables f64mm.
16136 (simd): Disabling this disables f64mm.
16137 (fp16): Disabling this disables f64mm.
16138 (sve): Disabling this disables f64mm.
16139 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
16140 (AARCH64_ISA_F64MM): New.
16141 (TARGET_F64MM): New.
16142 * doc/invoke.texi (f64mm): Document new option.
16144 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
16146 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
16147 (neoversen1_tunings): Likewise.
16149 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
16152 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
16153 Add assert to ensure prolog has been emitted.
16154 (aarch64_split_atomic_op): Likewise.
16155 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
16156 Use epilogue_completed rather than reload_completed.
16157 (aarch64_atomic_exchange<mode>): Likewise.
16158 (aarch64_atomic_<atomic_optab><mode>): Likewise.
16159 (atomic_nand<mode>): Likewise.
16160 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
16161 (atomic_fetch_nand<mode>): Likewise.
16162 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
16163 (atomic_nand_fetch<mode>): Likewise.
16165 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
16168 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
16170 (REVERSE_CONDITION): Delete.
16171 * config/aarch64/iterators.md (CC_ONLY): New mode iterator.
16172 (CCFP_CCFPE): Likewise.
16173 (e): New mode attribute.
16174 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
16175 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
16176 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
16177 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
16178 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
16179 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
16180 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
16181 name of generator from gen_ccmpdi to gen_ccmpccdi.
16182 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse
16183 the previous comparison but aren't able to, use the new ccmp_rev
16186 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
16188 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
16189 than testing directly for INTEGER_CST.
16190 (gimplify_target_expr, gimplify_omp_depend): Likewise.
16192 2020-01-17 Jakub Jelinek <jakub@redhat.com>
16194 PR tree-optimization/93292
16195 * tree-vect-stmts.c (vectorizable_comparison): Punt also if
16196 get_vectype_for_scalar_type returns NULL.
16198 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
16200 * params.opt (-param=max-predicted-iterations): Increase range from 0.
16201 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.
16203 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
16205 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
16207 * params.opt: (max-predicted-iterations): Set bounds.
16208 * predict.c (real_almost_one, real_br_prob_base,
16209 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
16210 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic
16211 probabilities; do not truncate to reg_br_prob_bases.
16212 (estimate_loops_at_level): Pass max_cyclic_prob.
16213 (estimate_loops): Compute max_cyclic_prob.
16214 (estimate_bb_frequencies): Do not initialize real_*; update calculation
16216 * profile-count.c (profile_probability::to_sreal): New.
16217 * profile-count.h (class sreal): Move up in file.
16218 (profile_probability::to_sreal): Declare.
16220 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16223 (arm_invalid_conversion): New function for target hook.
16224 (arm_invalid_unary_op): New function for target hook.
16225 (arm_invalid_binary_op): New function for target hook.
16227 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16229 * config.gcc: Add arm_bf16.h.
16230 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
16231 (arm_simd_builtin_std_type): Add BFmode.
16232 (arm_init_simd_builtin_types): Define element types for vector types.
16233 (arm_init_bf16_types): New function.
16234 (arm_init_builtins): Add arm_init_bf16_types function call.
16235 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
16236 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
16237 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode.
16238 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
16239 (arm_vector_mode_supported_p): Add V4BF, V8BF.
16240 (arm_mangle_type): Add __bf16.
16241 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
16242 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
16243 arm_bf16_ptr_type_node.
16244 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
16245 define_split between ARM registers.
16246 * config/arm/arm_bf16.h: New file.
16247 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
16248 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
16249 (VQXMOV): Add V8BF.
16250 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
16251 * config/arm/vfp.md: Add BFmode to movhf patterns.
16253 2020-01-16 Mihail Ionescu <mihail.ionescu@arm.com>
16254 Andre Vieira <andre.simoesdiasvieira@arm.com>
16256 * config/arm/arm-cpus.in (mve, mve_float): New features.
16257 (dsp, mve, mve.fp): New options.
16258 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
16259 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
16260 * doc/invoke.texi: Document the armv8.1-m mve and dps options.
16262 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16263 Thomas Preud'homme <thomas.preudhomme@arm.com>
16265 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
16267 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
16268 error for using -mcmse when targeting Armv8.1-M Mainline.
16270 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16271 Thomas Preud'homme <thomas.preudhomme@arm.com>
16273 * config/arm/arm.md (nonsecure_call_internal): Do not force memory
16274 address in r4 when targeting Armv8.1-M Mainline.
16275 (nonsecure_call_value_internal): Likewise.
16276 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
16277 a register match_operand again. Emit BLXNS when targeting
16278 Armv8.1-M Mainline.
16279 (nonsecure_call_value_reg_thumb2): Likewise.
16281 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16282 Thomas Preud'homme <thomas.preudhomme@arm.com>
16284 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
16285 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
16286 variable as true when floating-point ABI is not hard. Replace
16287 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
16288 Generate VLSTM and VLLDM instruction respectively before and
16289 after a function call to cmse_nonsecure_call function.
16290 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
16291 (VUNSPEC_VLLDM): Likewise.
16292 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
16293 (lazy_load_multiple_insn): Likewise.
16295 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16296 Thomas Preud'homme <thomas.preudhomme@arm.com>
16298 * config/arm/arm.c (vfp_emit_fstmd): Declare early.
16299 (arm_emit_vfp_multi_reg_pop): Likewise.
16300 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
16301 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and
16302 restore callee-saved VFP registers.
16304 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16305 Thomas Preud'homme <thomas.preudhomme@arm.com>
16307 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
16308 (cmse_nonsecure_call_clear_caller_saved): Rename into ...
16309 (cmse_nonsecure_call_inline_register_clear): This. Save and clear
16310 callee-saved GPRs as well as clear ip register before doing a nonsecure
16311 call then restore callee-saved GPRs after it when targeting
16312 Armv8.1-M Mainline.
16313 (arm_reorg): Adapt to function rename.
16315 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16316 Thomas Preud'homme <thomas.preudhomme@arm.com>
16318 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
16319 * config/arm/arm.c (clear_operation_p): Extend to be able to check a
16320 clear_vfp_multiple pattern based on a new vfp parameter.
16321 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
16322 targeting Armv8.1-M Mainline.
16323 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers
16324 unconditionally when targeting Armv8.1-M Mainline architecture. Check
16325 whether VFP registers are available before looking call_used_regs for a
16327 * config/arm/predicates.md (clear_multiple_operation): Adapt to change
16328 of prototype of clear_operation_p.
16329 (clear_vfp_multiple_operation): New predicate.
16330 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
16331 * config/arm/vfp.md (clear_vfp_multiple): New define_insn.
16333 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16334 Thomas Preud'homme <thomas.preudhomme@arm.com>
16336 * config/arm/arm-protos.h (clear_operation_p): Declare.
16337 * config/arm/arm.c (clear_operation_p): New function.
16338 (cmse_clear_registers): Generate clear_multiple instruction pattern if
16339 targeting Armv8.1-M Mainline or successor.
16340 (output_return_instruction): Only output APSR register clearing if
16341 Armv8.1-M Mainline instructions not available.
16342 (thumb_exit): Likewise.
16343 * config/arm/predicates.md (clear_multiple_operation): New predicate.
16344 * config/arm/thumb2.md (clear_apsr): New define_insn.
16345 (clear_multiple): Likewise.
16346 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.
16348 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16349 Thomas Preud'homme <thomas.preudhomme@arm.com>
16351 * config/arm/arm.c (fp_sysreg_names): Declare and define.
16352 (use_return_insn): Also return false for Armv8.1-M Mainline.
16353 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M
16354 Mainline instructions are available.
16355 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS
16356 when targeting Armv8.1-M Mainline Security Extensions.
16357 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
16358 Mainline entry function.
16359 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
16360 targeting Armv8.1-M Mainline or successor.
16361 (arm_expand_epilogue): Fix indentation of caller-saved register
16362 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline
16364 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
16365 (FP_SYSREGS): Likewise.
16366 (enum vfp_sysregs_encoding): Define enum.
16367 (fp_sysreg_names): Declare.
16368 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
16369 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
16370 (pop_fpsysreg_insn): Likewise.
16372 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16373 Thomas Preud'homme <thomas.preudhomme@arm.com>
16375 * config/arm/arm-cpus.in (armv8_1m_main): New feature.
16376 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
16377 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
16378 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
16379 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
16380 (ARMv8_1m_main): New feature group.
16381 (armv8.1-m.main): New architecture.
16382 * config/arm/arm-tables.opt: Regenerate.
16383 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
16384 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
16385 (arm_options_perform_arch_sanity_checks): Error out when targeting
16386 Armv8.1-M Mainline Security Extensions.
16387 * config/arm/arm.h (arm_arch8_1m_main): Declare.
16389 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16391 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
16392 aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
16393 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
16394 aarch64_bfdot_laneq): New.
16395 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
16396 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
16397 vbfdotq_laneq_f32): New.
16398 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
16399 VBFMLA_W, VBF): New.
16400 (isquadop): Add V4BF, V8BF.
16402 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16404 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
16405 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
16406 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
16407 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
16408 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
16409 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
16410 usdot_laneq, sudot_lane,sudot_laneq): New.
16411 * config/aarch64/aarch64-simd.md (aarch64_usdot): New.
16412 (aarch64_<sur>dot_lane): New.
16413 * config/aarch64/arm_neon.h (vusdot_s32): New.
16414 (vusdotq_s32): New.
16415 (vusdot_lane_s32): New.
16416 (vsudot_lane_s32): New.
16417 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
16418 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.
16420 2020-01-16 Martin Liska <mliska@suse.cz>
16422 * value-prof.c (dump_histogram_value): Fix
16423 obvious spacing issue.
16425 2020-01-16 Andrew Pinski <apinski@marvell.com>
16427 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
16428 !storage_order_barrier_p.
16430 2020-01-16 Andrew Pinski <apinski@marvell.com>
16432 * sched-int.h (_dep): Add unused bit-field field for the padding.
16433 * sched-deps.c (init_dep_1): Init unused field.
16435 2020-01-16 Andrew Pinski <apinski@marvell.com>
16437 * optabs.h (create_expand_operand): Initialize target field also.
16439 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
16441 PR tree-optimization/92429
16442 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
16443 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
16445 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
16448 2020-01-16 Richard Sandiford <richard.sandiford@arm.com>
16450 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
16451 aarch64_sve_int_mode to each mode.
16453 2020-01-15 David Malcolm <dmalcolm@redhat.com>
16455 * doc/analyzer.texi (Overview): Add note about
16456 -fdump-ipa-analyzer.
16458 2020-01-15 Wilco Dijkstra <wdijkstr@arm.com>
16460 PR tree-optimization/93231
16461 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
16462 input_type is unsigned. Use tree_to_shwi for shift constant.
16463 Check CST_STRING element size is CHAR_TYPE_SIZE bits.
16464 (simplify_count_trailing_zeroes): Add test to handle known non-zero
16465 inputs more efficiently.
16467 2020-01-15 Uroš Bizjak <ubizjak@gmail.com>
16469 * config/i386/i386.md (*movsf_internal): Do not require
16470 SSE2 ISA for alternatives 14 and 15.
16472 2020-01-15 Richard Biener <rguenther@suse.de>
16474 PR middle-end/93273
16475 * tree-eh.c (sink_clobbers): If we already visited the destination
16476 block do not defer insertion.
16477 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for
16478 the purpose of defered insertion.
16480 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16482 * BASE-VER: Bump to 10.0.1.
16484 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
16486 PR tree-optimization/93247
16487 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access
16488 type of the stmt that we're going to vectorize.
16490 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
16492 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a
16493 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent
16496 2020-01-15 Martin Liska <mliska@suse.cz>
16498 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow
16499 2 calls of streamer_read_hwi in a function call.
16501 2020-01-15 Richard Biener <rguenther@suse.de>
16503 * alias.c (record_alias_subset): Avoid redundant work when
16504 subset is already recorded.
16506 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16508 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of
16509 the analyzer options provide CWE identifiers.
16511 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16513 * tree-diagnostic-path.cc (path_summary::event_range::print):
16514 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers
16515 using get_pure_location.
16517 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16519 PR tree-optimization/93262
16520 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins,
16521 perform head trimming only if the last argument is constant,
16522 either all ones, or larger or equal to head trim, in the latter
16523 case decrease the last argument by head_trim.
16525 PR tree-optimization/93249
16526 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h.
16527 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to
16528 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't
16529 perform head trim unless we can prove there are no '\0' chars
16530 from the source among the first head_trim chars.
16532 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16534 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o.
16536 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16539 * config/i386/sse.md
16540 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1,
16541 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1,
16542 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1,
16543 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use
16544 just a single alternative instead of two, make operands 1 and 2
16547 2020-01-14 Jan Hubicka <hubicka@ucw.cz>
16550 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and
16553 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16555 * Makefile.in (lang_opt_files): Add analyzer.opt.
16556 (ANALYZER_OBJS): New.
16557 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o,
16558 tristate.o and ANALYZER_OBJS.
16559 (TEXI_GCCINT_FILES): Add analyzer.texi.
16560 * common.opt (-fanalyzer): New driver option.
16561 * config.in: Regenerate.
16562 * configure: Regenerate.
16563 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option.
16564 (gccdepdir): Also create depdir for "analyzer" subdir.
16565 * digraph.cc: New file.
16566 * digraph.h: New file.
16567 * doc/analyzer.texi: New file.
16568 * doc/gccint.texi ("Static Analyzer") New menu item.
16569 (analyzer.texi): Include it.
16570 * doc/invoke.texi ("Static Analyzer Options"): New list and new section.
16571 ("Warning Options"): Add static analysis warnings to the list.
16572 (-Wno-analyzer-double-fclose): New option.
16573 (-Wno-analyzer-double-free): New option.
16574 (-Wno-analyzer-exposure-through-output-file): New option.
16575 (-Wno-analyzer-file-leak): New option.
16576 (-Wno-analyzer-free-of-non-heap): New option.
16577 (-Wno-analyzer-malloc-leak): New option.
16578 (-Wno-analyzer-possible-null-argument): New option.
16579 (-Wno-analyzer-possible-null-dereference): New option.
16580 (-Wno-analyzer-null-argument): New option.
16581 (-Wno-analyzer-null-dereference): New option.
16582 (-Wno-analyzer-stale-setjmp-buffer): New option.
16583 (-Wno-analyzer-tainted-array-index): New option.
16584 (-Wno-analyzer-use-after-free): New option.
16585 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option.
16586 (-Wno-analyzer-use-of-uninitialized-value): New option.
16587 (-Wanalyzer-too-complex): New option.
16588 (-fanalyzer-call-summaries): New warning.
16589 (-fanalyzer-checker=): New warning.
16590 (-fanalyzer-fine-grained): New warning.
16591 (-fno-analyzer-state-merge): New warning.
16592 (-fno-analyzer-state-purge): New warning.
16593 (-fanalyzer-transitivity): New warning.
16594 (-fanalyzer-verbose-edges): New warning.
16595 (-fanalyzer-verbose-state-changes): New warning.
16596 (-fanalyzer-verbosity=): New warning.
16597 (-fdump-analyzer): New warning.
16598 (-fdump-analyzer-callgraph): New warning.
16599 (-fdump-analyzer-exploded-graph): New warning.
16600 (-fdump-analyzer-exploded-nodes): New warning.
16601 (-fdump-analyzer-exploded-nodes-2): New warning.
16602 (-fdump-analyzer-exploded-nodes-3): New warning.
16603 (-fdump-analyzer-supergraph): New warning.
16604 * doc/sourcebuild.texi (dg-require-dot): New.
16605 (dg-check-dot): New.
16606 * gdbinit.in (break-on-saved-diagnostic): New command.
16607 * graphviz.cc: New file.
16608 * graphviz.h: New file.
16609 * ordered-hash-map-tests.cc: New file.
16610 * ordered-hash-map.h: New file.
16611 * passes.def (pass_analyzer): Add before
16612 pass_ipa_whole_program_visibility.
16613 * selftest-run-tests.c (selftest::run_tests): Call
16614 selftest::ordered_hash_map_tests_cc_tests.
16615 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New
16617 * shortest-paths.h: New file.
16618 * timevar.def (TV_ANALYZER): New timevar.
16619 (TV_ANALYZER_SUPERGRAPH): Likewise.
16620 (TV_ANALYZER_STATE_PURGE): Likewise.
16621 (TV_ANALYZER_PLAN): Likewise.
16622 (TV_ANALYZER_SCC): Likewise.
16623 (TV_ANALYZER_WORKLIST): Likewise.
16624 (TV_ANALYZER_DUMP): Likewise.
16625 (TV_ANALYZER_DIAGNOSTICS): Likewise.
16626 (TV_ANALYZER_SHORTEST_PATHS): Likewise.
16627 * tree-pass.h (make_pass_analyzer): New decl.
16628 * tristate.cc: New file.
16629 * tristate.h: New file.
16631 2020-01-14 Uroš Bizjak <ubizjak@gmail.com>
16634 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for
16635 alternatives 9 and 10.
16637 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16639 * attribs.c (excl_hash_traits::empty_zero_p): New static constant.
16640 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise.
16641 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise.
16642 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
16643 (selftest::hash_map_tests_c_tests): Call it.
16644 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p):
16645 New static constant, using the value of = H::empty_zero_p.
16646 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value
16647 from default_hash_traits <Value>.
16648 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value
16650 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise.
16651 * hash-table.h (hash_table::alloc_entries): Guard the loop of
16652 calls to mark_empty with !Descriptor::empty_zero_p.
16653 (hash_table::empty_slow): Conditionalize the memset call with a
16654 check that Descriptor::empty_zero_p; otherwise, loop through the
16655 entries calling mark_empty on them.
16656 * hash-traits.h (int_hash::empty_zero_p): New static constant.
16657 (pointer_hash::empty_zero_p): Likewise.
16658 (pair_hash::empty_zero_p): Likewise.
16659 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p):
16661 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise.
16662 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise.
16663 * profile.c (location_triplet_hash::empty_zero_p): Likewise.
16664 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise.
16665 (sanopt_tree_couple_hash::empty_zero_p): Likewise.
16666 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise.
16667 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise.
16668 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise.
16669 * tree-vectorizer.h
16670 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p):
16673 2020-01-14 Kewen Lin <linkw@gcc.gnu.org>
16675 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return,
16676 fix typo on return value.
16678 2020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
16681 * cgraph.c (symbol_table::create_edge): Init speculative_id and
16683 (cgraph_edge::make_speculative): Add param for setting speculative_id
16685 (cgraph_edge::speculative_call_info): Update comments and find reference
16686 by speculative_id for multiple indirect targets.
16687 (cgraph_edge::resolve_speculation): Decrease the speculations
16688 for indirect edge, drop it's speculative if not direct target
16689 left. Update comments.
16690 (cgraph_edge::redirect_call_stmt_to_callee): Likewise.
16691 (cgraph_node::dump): Print num_speculative_call_targets.
16692 (cgraph_node::verify_node): Don't report error if speculative
16693 edge not include statement.
16694 (cgraph_edge::num_speculative_call_targets_p): New function.
16695 * cgraph.h (int common_target_id): Remove.
16696 (int common_target_probability): Remove.
16697 (num_speculative_call_targets): New variable.
16698 (make_speculative): Add param for setting speculative_id.
16699 (cgraph_edge::num_speculative_call_targets_p): New declare.
16700 (target_prob): New variable.
16701 (speculative_id): New variable.
16702 * ipa-fnsummary.c (analyze_function_body): Create and duplicate
16703 call summaries for multiple speculative call targets.
16704 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id.
16705 * ipa-profile.c (struct speculative_call_target): New struct.
16706 (class speculative_call_summary): New class.
16707 (class speculative_call_summaries): New class.
16708 (call_sums): New variable.
16709 (ipa_profile_generate_summary): Generate indirect multiple targets summaries.
16710 (ipa_profile_write_edge_summary): New function.
16711 (ipa_profile_write_summary): Stream out indirect multiple targets summaries.
16712 (ipa_profile_dump_all_summaries): New function.
16713 (ipa_profile_read_edge_summary): New function.
16714 (ipa_profile_read_summary_section): New function.
16715 (ipa_profile_read_summary): Stream in indirect multiple targets summaries.
16716 (ipa_profile): Generate num_speculative_call_targets from
16718 * ipa-ref.h (speculative_id): New variable.
16719 * ipa-utils.c (ipa_merge_profiles): Update with target_prob.
16720 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and
16721 common_target_probability. Stream out speculative_id and
16722 num_speculative_call_targets.
16723 (input_edge): Likewise.
16724 * predict.c (dump_prediction): Remove edges count assert to be
16726 * symtab.c (symtab_node::create_reference): Init speculative_id.
16727 (symtab_node::clone_references): Clone speculative_id.
16728 (symtab_node::clone_referring): Clone speculative_id.
16729 (symtab_node::clone_reference): Clone speculative_id.
16730 (symtab_node::clear_stmts_in_references): Clear speculative_id.
16731 * tree-inline.c (copy_bb): Duplicate all the speculative edges
16732 if indirect call contains multiple speculative targets.
16733 * value-prof.h (check_ic_target): Remove.
16734 * value-prof.c (gimple_value_profile_transformations):
16735 Use void function gimple_ic_transform.
16736 * value-prof.c (gimple_ic_transform): Handle topn case.
16737 Fix comment typos. Change it to a void function.
16739 2020-01-13 Andrew Pinski <apinski@marvell.com>
16741 * config/aarch64/aarch64-cores.def (octeontx2): New define.
16742 (octeontx2t98): New define.
16743 (octeontx2t96): New define.
16744 (octeontx2t93): New define.
16745 (octeontx2f95): New define.
16746 (octeontx2f95n): New define.
16747 (octeontx2f95mm): New define.
16748 * config/aarch64/aarch64-tune.md: Regenerate.
16749 * doc/invoke.texi (-mcpu=): Document the new cpu types.
16751 2020-01-13 Jason Merrill <jason@redhat.com>
16753 PR c++/33799 - destroy return value if local cleanup throws.
16754 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR.
16756 2020-01-13 Martin Liska <mliska@suse.cz>
16758 * ipa-cp.c (get_max_overall_size): Use newly
16759 renamed param param_ipa_cp_unit_growth.
16760 * params.opt: Remove legacy param name.
16762 2020-01-13 Martin Sebor <msebor@redhat.com>
16764 PR tree-optimization/93213
16765 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul
16766 stores to be eliminated.
16768 2020-01-13 Martin Liska <mliska@suse.cz>
16770 * opts.c (print_help): Do not print CL_PARAM
16771 and CL_WARNING for CL_OPTIMIZATION.
16773 2020-01-13 Jonathan Wakely <jwakely@redhat.com>
16776 * doc/invoke.texi (Warning Options): Add caveat about some warnings
16777 depending on optimization settings.
16779 2020-01-13 Jakub Jelinek <jakub@redhat.com>
16781 PR tree-optimization/90838
16782 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
16783 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro
16784 argument rather than to initialize temporary for targets that
16785 don't use the mode argument at all. Initialize ctzval to avoid
16788 2020-01-10 Thomas Schwinge <thomas@codesourcery.com>
16790 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition.
16791 * tree-core.h: Document it.
16792 * gimplify.c (gimplify_omp_workshare): Set it.
16793 * omp-low.c (lower_omp_target): Use it.
16794 * tree-pretty-print.c (dump_omp_clause): Print it.
16796 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>:
16797 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'.
16799 2020-01-10 David Malcolm <dmalcolm@redhat.com>
16801 * Makefile.in (OBJS): Add tree-diagnostic-path.o.
16802 * common.opt (fdiagnostics-path-format=): New option.
16803 (diagnostic_path_format): New enum.
16804 (fdiagnostics-show-path-depths): New option.
16805 * coretypes.h (diagnostic_event_id_t): New forward decl.
16806 * diagnostic-color.c (color_dict): Add "path".
16807 * diagnostic-event-id.h: New file.
16808 * diagnostic-format-json.cc (json_from_expanded_location): Make
16810 (json_end_diagnostic): Call context->make_json_for_path if it
16811 exists and the diagnostic has a path.
16812 (diagnostic_output_format_init): Clear context->print_path.
16813 * diagnostic-path.h: New file.
16814 * diagnostic-show-locus.c (colorizer::set_range): Special-case
16815 when printing a run of events in a diagnostic_path so that they
16816 all get the same color.
16817 (layout::m_diagnostic_path_p): New field.
16818 (layout::layout): Initialize it.
16819 (layout::print_any_labels): Don't colorize the label text for an
16820 event in a diagnostic_path.
16821 (gcc_rich_location::add_location_if_nearby): Add
16822 "restrict_to_current_line_spans" and "label" params. Pass the
16823 former to layout.maybe_add_location_range; pass the latter
16824 when calling add_range.
16825 * diagnostic.c: Include "diagnostic-path.h".
16826 (diagnostic_initialize): Initialize context->path_format and
16827 context->show_path_depths.
16828 (diagnostic_show_any_path): New function.
16829 (diagnostic_path::interprocedural_p): New function.
16830 (diagnostic_report_diagnostic): Call diagnostic_show_any_path.
16831 (simple_diagnostic_path::num_events): New function.
16832 (simple_diagnostic_path::get_event): New function.
16833 (simple_diagnostic_path::add_event): New function.
16834 (simple_diagnostic_event::simple_diagnostic_event): New ctor.
16835 (simple_diagnostic_event::~simple_diagnostic_event): New dtor.
16836 (debug): New overload taking a diagnostic_path *.
16837 * diagnostic.def (DK_DIAGNOSTIC_PATH): New.
16838 * diagnostic.h (enum diagnostic_path_format): New enum.
16839 (json::value): New forward decl.
16840 (diagnostic_context::path_format): New field.
16841 (diagnostic_context::show_path_depths): New field.
16842 (diagnostic_context::print_path): New callback field.
16843 (diagnostic_context::make_json_for_path): New callback field.
16844 (diagnostic_show_any_path): New decl.
16845 (json_from_expanded_location): New decl.
16846 * doc/invoke.texi (-fdiagnostics-path-format=): New option.
16847 (-fdiagnostics-show-path-depths): New option.
16848 (-fdiagnostics-color): Add "path" to description of default
16849 GCC_COLORS; describe it.
16850 (-fdiagnostics-format=json): Document how diagnostic paths are
16851 represented in the JSON output format.
16852 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
16853 Add optional params "restrict_to_current_line_spans" and "label".
16854 * opts.c (common_handle_option): Handle
16855 OPT_fdiagnostics_path_format_ and
16856 OPT_fdiagnostics_show_path_depths.
16857 * pretty-print.c: Include "diagnostic-event-id.h".
16858 (pp_format): Implement "%@" format code for printing
16859 diagnostic_event_id_t *.
16860 (selftest::test_pp_format): Add tests for "%@".
16861 * selftest-run-tests.c (selftest::run_tests): Call
16862 selftest::tree_diagnostic_path_cc_tests.
16863 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl.
16864 * toplev.c (general_init): Initialize global_dc->path_format and
16865 global_dc->show_path_depths.
16866 * tree-diagnostic-path.cc: New file.
16867 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make
16868 non-static. Drop "diagnostic" param in favor of storing the
16869 original value of "where" and re-using it.
16870 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of
16871 maybe_unwind_expanded_macro_loc.
16872 (tree_diagnostics_defaults): Initialize context->print_path and
16873 context->make_json_for_path.
16874 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New
16876 (default_tree_make_json_for_path): New decl.
16877 (maybe_unwind_expanded_macro_loc): New decl.
16879 2020-01-10 Jakub Jelinek <jakub@redhat.com>
16881 PR tree-optimization/93210
16882 * fold-const.h (native_encode_initializer,
16883 can_native_interpret_type_p): Declare.
16884 * fold-const.c (native_encode_string): Fix up handling with off != -1,
16886 (native_encode_initializer): New function, moved from dwarf2out.c.
16887 Adjust to native_encode_expr compatible arguments, including dry-run
16888 and partial extraction modes. Don't handle STRING_CST.
16889 (can_native_interpret_type_p): No longer static.
16890 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify
16891 offset / BITS_PER_UNIT fits into int and don't call it if
16892 can_native_interpret_type_p fails. If suboff is NULL and for
16893 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with
16894 native_encode_initializer.
16895 (fold_const_aggregate_ref_1): Formatting fix.
16896 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c.
16897 (tree_add_const_value_attribute): Adjust caller.
16899 PR tree-optimization/90838
16900 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
16901 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of
16902 CTZ_DEFINED_VALUE_AT_ZERO.
16904 2020-01-10 Vladimir Makarov <vmakarov@redhat.com>
16906 PR inline-asm/93027
16907 * lra-constraints.c (match_reload): Permit input operands have the
16908 same mode as output while other input operands have a different
16911 2020-01-10 Wilco Dijkstra <wdijkstr@arm.com>
16913 PR tree-optimization/90838
16914 * tree-ssa-forwprop.c (check_ctz_array): Add new function.
16915 (check_ctz_string): Likewise.
16916 (optimize_count_trailing_zeroes): Likewise.
16917 (simplify_count_trailing_zeroes): Likewise.
16918 (pass_forwprop::execute): Try ctz simplification.
16919 * match.pd: Add matching for ctz idioms.
16921 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16923 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function
16925 (aarch64_invalid_unary_op): New function for target hook.
16926 (aarch64_invalid_binary_op): New function for target hook.
16928 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16930 * config.gcc: Add arm_bf16.h.
16931 * config/aarch64/aarch64-builtins.c
16932 (aarch64_simd_builtin_std_type): Add BFmode.
16933 (aarch64_init_simd_builtin_types): Define element types for vector
16935 (aarch64_init_bf16_types): New function.
16936 (aarch64_general_init_builtins): Add arm_init_bf16_types function call.
16937 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
16939 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
16940 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
16942 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
16943 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
16944 * config/aarch64/aarch64.c
16945 (aarch64_classify_vector_mode): Add support for BF types.
16946 (aarch64_gimplify_va_arg_expr): Add support for BF types.
16947 (aarch64_vq_mode): Add support for BF types.
16948 (aarch64_simd_container_mode): Add support for BF types.
16949 (aarch64_mangle_type): Add support for BF scalar type.
16950 * config/aarch64/aarch64.md: Add BFmode to movhf pattern.
16951 * config/aarch64/arm_bf16.h: New file.
16952 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
16953 * config/aarch64/iterators.md: Add BF types to mode attributes.
16954 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.
16956 2020-01-10 Jason Merrill <jason@redhat.com>
16958 PR c++/93173 - incorrect tree sharing.
16959 * gimplify.c (copy_if_shared): No longer static.
16960 * gimplify.h: Declare it.
16962 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16964 * doc/invoke.texi (-msve-vector-bits=): Document that
16965 -msve-vector-bits=128 now generates VL-specific code for
16966 little-endian targets.
16967 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use
16968 build_vector_type_for_mode to construct the data vector types.
16969 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate
16970 VL-specific code for -msve-vector-bits=128 on little-endian targets.
16971 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes
16972 for 128-bit vectors.
16974 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16976 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask
16979 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16981 * config/aarch64/aarch64-builtins.c
16982 (aarch64_builtin_vectorized_function): Check for specific vector modes,
16983 rather than checking the number of elements and the element mode.
16985 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16987 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use
16988 get_related_vectype_for_scalar_type rather than build_vector_type
16989 to create the index type for a conditional reduction.
16991 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16993 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF
16994 for any type of gather or scatter, including strided accesses.
16996 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16998 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function
17001 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
17003 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use
17004 get_dr_vinfo_offset
17005 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init
17006 parameter and its use to reset DR_OFFSET's.
17007 (vect_transform_loop): Remove orig_drs_init argument.
17008 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset
17009 member of dr_vec_info rather than the offset of the associated
17010 data_reference's innermost_loop_behavior.
17011 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference.
17012 (vect_do_peeling): Remove orig_drs_init parameter and its construction.
17013 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with
17014 get_dr_vinfo_offset.
17015 (vectorizable_store): Likewise.
17016 (vectorizable_load): Likewise.
17018 2020-01-10 Richard Biener <rguenther@suse.de>
17020 * gimple-ssa-store-merging
17021 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info.
17023 2020-01-10 Martin Liska <mliska@suse.cz>
17026 * ipa-inline-analysis.c (offline_size): Make proper parenthesis
17027 encapsulation that was there before r280040.
17029 2020-01-10 Richard Biener <rguenther@suse.de>
17031 PR middle-end/93199
17032 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL
17033 sequences to avoid walking them again for secondary opportunities.
17034 (pass_lower_eh_dispatch::execute): Instead actually insert
17037 2020-01-10 Richard Biener <rguenther@suse.de>
17039 PR middle-end/93199
17040 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible.
17041 (cleanup_all_empty_eh): Walk landing pads in reverse order to
17042 avoid quadraticness.
17044 2020-01-10 Martin Jambor <mjambor@suse.cz>
17046 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization.
17047 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it
17048 to get param_ipa_sra_max_replacements.
17049 (param_splitting_across_edge): Pass the caller to
17050 pull_accesses_from_callee.
17052 2020-01-10 Martin Jambor <mjambor@suse.cz>
17054 * params.opt (param_ipcp_unit_growth): Mark as Optimization.
17055 * ipa-cp.c (max_new_size): Removed.
17056 (orig_overall_size): New variable.
17057 (get_max_overall_size): New function.
17058 (estimate_local_effects): Use it. Adjust dump.
17059 (decide_about_value): Likewise.
17060 (ipcp_propagate_stage): Do not calculate max_new_size, just store
17061 orig_overall_size. Adjust dump.
17062 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size.
17064 2020-01-10 Martin Jambor <mjambor@suse.cz>
17066 * params.opt (param_ipa_max_agg_items): Mark as Optimization
17067 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use
17068 instead of param_ipa_max_agg_items.
17069 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from
17070 optimization info for the callee.
17072 2020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com>
17074 * lto-streamer-in.c (input_function): Remove streamed-in inline debug
17075 markers if debug_inline_points is false.
17077 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17079 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
17081 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
17082 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
17083 aarch64-sve-builtins-sve2.h.
17084 (aarch64-sve-builtins-sve2.o): New rule.
17085 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
17086 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
17087 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
17088 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
17089 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
17090 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
17092 * config/aarch64/aarch64-sve.md: Update comments with SVE2
17093 instructions that are handled here.
17094 (@cond_asrd<mode>): Generalize to...
17095 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
17096 (*cond_asrd<mode>_2): Generalize to...
17097 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
17098 (*cond_asrd<mode>_z): Generalize to...
17099 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
17100 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
17101 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
17102 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
17103 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
17105 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
17106 (@aarch64_scatter_stnt<mode>): Likewise.
17107 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
17108 (@aarch64_mul_lane_<mode>): Likewise.
17109 (@aarch64_sve_suqadd<mode>_const): Likewise.
17110 (*<sur>h<addsub><mode>): Generalize to...
17111 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
17113 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
17114 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
17115 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
17116 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
17117 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
17118 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
17119 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
17120 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
17121 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
17122 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
17123 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
17124 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
17125 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
17126 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
17127 (@aarch64_sve_add_mul_lane_<mode>): Likewise.
17128 (@aarch64_sve_sub_mul_lane_<mode>): Likewise.
17129 (@aarch64_sve2_xar<mode>): Likewise.
17130 (@aarch64_sve2_bcax<mode>): Likewise.
17131 (*aarch64_sve2_eor3<mode>): Rename to...
17132 (@aarch64_sve2_eor3<mode>): ...this.
17133 (@aarch64_sve2_bsl<mode>): New expander.
17134 (@aarch64_sve2_nbsl<mode>): Likewise.
17135 (@aarch64_sve2_bsl1n<mode>): Likewise.
17136 (@aarch64_sve2_bsl2n<mode>): Likewise.
17137 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
17138 (*aarch64_sve2_sra<mode>): Add MOVPRFX support.
17139 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
17140 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
17141 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
17142 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
17143 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
17144 (<su>mull<bt><Vwide>): Generalize to...
17145 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
17147 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
17148 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
17149 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
17150 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
17151 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
17152 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
17153 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
17154 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
17155 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
17156 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
17157 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
17158 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
17159 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
17160 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
17161 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
17162 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
17163 (<SHRNB:r>shrnb<mode>): Generalize to...
17164 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
17166 (<SHRNT:r>shrnt<mode>): Generalize to...
17167 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
17169 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
17170 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
17171 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
17172 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
17173 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
17174 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
17175 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
17176 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
17177 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
17178 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
17179 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
17180 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
17181 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
17182 (@aarch64_sve2_cvtnt<mode>): Likewise.
17183 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
17184 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
17185 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
17186 (@aarch64_sve2_cvtxnt<mode>): Likewise.
17187 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
17188 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
17189 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
17190 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
17191 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
17192 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
17193 (@aarch64_sve2_pmul<mode>): Likewise.
17194 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
17195 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
17196 (@aarch64_sve2_tbl2<mode>): Likewise.
17197 (@aarch64_sve2_tbx<mode>): Likewise.
17198 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
17199 (@aarch64_sve2_histcnt<mode>): Likewise.
17200 (@aarch64_sve2_histseg<mode>): Likewise.
17201 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
17202 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
17203 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
17204 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
17205 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
17206 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
17207 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
17208 (<su>mulh<r>s<mode>3): Update after above pattern name changes.
17209 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
17210 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
17211 (SVE2_PMULL_PAIR_I): New mode iterators.
17212 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
17213 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
17214 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
17215 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
17216 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
17217 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
17218 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
17219 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
17220 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
17221 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
17222 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
17223 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
17224 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
17225 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
17226 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
17227 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
17228 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
17229 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
17230 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
17231 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
17232 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
17233 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
17234 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
17235 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
17236 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
17237 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
17238 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
17239 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
17240 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
17241 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
17242 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
17244 (VNARROW, Ventype): New mode attributes.
17245 (Vewtype): Handle VNx2DI. Fix typo in comment.
17246 (VDOUBLE): New mode attribute.
17247 (sve_lane_con): Handle VNx8HI.
17248 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
17249 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
17250 (sve_int_op, sve_int_op_rev): Handle the above codes.
17251 (sve_pred_int_rhs2_operand): Likewise.
17252 (MULLBT, SHRNB, SHRNT): Delete.
17253 (SVE_INT_SHIFT_IMM): New int iterator.
17254 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
17255 and UNSPEC_WHILEHS for TARGET_SVE2.
17256 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
17257 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
17258 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
17259 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
17260 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
17261 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
17262 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
17263 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
17264 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
17265 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
17266 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
17267 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
17268 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
17269 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
17270 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
17271 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
17272 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
17273 (optab): Handle the new unspecs.
17274 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
17276 (lr): Handle the new unspecs.
17278 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
17279 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
17280 (sve_int_qsub_op): New int attributes.
17281 (sve_fp_op, rot): Handle the new unspecs.
17282 * config/aarch64/aarch64-sve-builtins.h
17283 (function_resolver::require_matching_pointer_type): Declare.
17284 (function_resolver::resolve_unary): Add an optional boolean argument.
17285 (function_resolver::finish_opt_n_resolution): Add an optional
17286 type_suffix_index argument.
17287 (gimple_folder::redirect_call): Declare.
17288 (gimple_expander::prepare_gather_address_operands): Add an optional
17290 * config/aarch64/aarch64-sve-builtins.cc: Include
17291 aarch64-sve-builtins-sve2.h.
17292 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
17293 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
17294 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
17295 (TYPES_hsd_integer): Use TYPES_hsd_signed.
17296 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
17297 (TYPES_s_unsigned): Likewise.
17298 (TYPES_s_integer): Use TYPES_s_unsigned.
17299 (TYPES_sd_signed, TYPES_sd_unsigned): New macros.
17300 (TYPES_sd_integer): Use them.
17301 (TYPES_d_unsigned): New macro.
17302 (TYPES_d_integer): Use it.
17303 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
17304 (TYPES_cvt_narrow): Likewise.
17305 (DEF_SVE_TYPES_ARRAY): Include the new types macros above.
17306 (preds_mx): New variable.
17307 (function_builder::add_overloaded_function): Allow the new feature
17308 set to be more restrictive than the original one.
17309 (function_resolver::infer_pointer_type): Remove qualifiers from
17310 the pointer type before printing it.
17311 (function_resolver::require_matching_pointer_type): New function.
17312 (function_resolver::resolve_sv_displacement): Handle functions
17313 that don't support 32-bit vector indices or svint32_t vector offsets.
17314 (function_resolver::finish_opt_n_resolution): Take the inferred type
17315 as a separate argument.
17316 (function_resolver::resolve_unary): Optionally treat all forms in
17317 the same way as normal merging functions.
17318 (gimple_folder::redirect_call): New function.
17319 (function_expander::prepare_gather_address_operands): Add an argument
17320 that says whether scaled forms are available. If they aren't,
17321 handle scaling of vector indices and don't add the extension and
17323 (function_expander::map_to_unspecs): If aarch64_sve isn't available,
17324 fall back to using cond_* instead.
17325 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
17326 Split out the member variables into...
17327 (rtx_code_function_base): ...this new base class.
17328 (rtx_code_function_rotated): Inherit rtx_code_function_base.
17329 (unspec_based_function): Split out the member variables into...
17330 (unspec_based_function_base): ...this new base class.
17331 (unspec_based_function_rotated): Inherit unspec_based_function_base.
17332 (unspec_based_function_exact_insn): New class.
17333 (unspec_based_add_function, unspec_based_add_lane_function)
17334 (unspec_based_lane_function, unspec_based_pred_function)
17335 (unspec_based_qadd_function, unspec_based_qadd_lane_function)
17336 (unspec_based_qsub_function, unspec_based_qsub_lane_function)
17337 (unspec_based_sub_function, unspec_based_sub_lane_function): New
17339 (unspec_based_fused_function): New class.
17340 (unspec_based_mla_function, unspec_based_mls_function): New typedefs.
17341 (unspec_based_fused_lane_function): New class.
17342 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
17344 (CODE_FOR_MODE1): New macro.
17345 (fixed_insn_function): New class.
17346 (while_comparison): Likewise.
17347 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
17348 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
17349 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
17350 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
17351 (load_gather_sv_restricted, shift_left_imm_long): Declare.
17352 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
17353 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
17354 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
17355 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
17356 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
17357 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
17358 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
17359 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
17360 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
17361 Also add an initial argument for unary_convert_narrowt, regardless
17362 of the predication type.
17363 (build_32_64): Allow loads and stores to specify MODE_none.
17364 (build_sv_index64, build_sv_uint_offset): New functions.
17365 (long_type_suffix): New function.
17366 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
17367 (binary_imm_long_base, load_gather_sv_base): Likewise.
17368 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
17369 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
17370 (unary_narrowb_base, unary_narrowt_base): Likewise.
17371 (binary_long_lane_def, binary_long_lane): New shape.
17372 (binary_long_opt_n_def, binary_long_opt_n): Likewise.
17373 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
17374 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
17375 (binary_to_uint_def, binary_to_uint): Likewise.
17376 (binary_wide_def, binary_wide): Likewise.
17377 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
17378 (compare_def, compare): Likewise.
17379 (compare_ptr_def, compare_ptr): Likewise.
17380 (load_ext_gather_index_restricted_def,
17381 load_ext_gather_index_restricted): Likewise.
17382 (load_ext_gather_offset_restricted_def,
17383 load_ext_gather_offset_restricted): Likewise.
17384 (load_gather_sv_def): Inherit from load_gather_sv_base.
17385 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
17386 (shift_left_imm_def, shift_left_imm): Likewise.
17387 (shift_left_imm_long_def, shift_left_imm_long): Likewise.
17388 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
17389 (store_scatter_index_restricted_def,
17390 store_scatter_index_restricted): Likewise.
17391 (store_scatter_offset_restricted_def,
17392 store_scatter_offset_restricted): Likewise.
17393 (tbl_tuple_def, tbl_tuple): Likewise.
17394 (ternary_long_lane_def, ternary_long_lane): Likewise.
17395 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
17396 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
17397 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
17398 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
17399 (ternary_qq_rotate_def, ternary_qq_rotate): New shape.
17400 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
17401 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
17402 (ternary_uint_def, ternary_uint): Likewise.
17403 (unary_convert): Fix typo in comment.
17404 (unary_convert_narrowt_def, unary_convert_narrowt): New shape.
17405 (unary_long_def, unary_long): Likewise.
17406 (unary_narrowb_def, unary_narrowb): Likewise.
17407 (unary_narrowt_def, unary_narrowt): Likewise.
17408 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
17409 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
17410 (unary_to_int_def, unary_to_int): Likewise.
17411 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
17412 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
17413 (svasrd_impl): Delete.
17414 (svcadd_impl::expand): Handle integer operations too.
17415 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
17416 new functions to derive the unspec numbers.
17417 (svmla_svmls_lane_impl): Replace with...
17418 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle
17419 integer operations too.
17420 (svwhile_impl): Rename to...
17421 (svwhilelx_impl): ...this and inherit from while_comparison.
17422 (svasrd): Use unspec_based_function.
17423 (svmla_lane): Use svmla_lane_impl.
17424 (svmls_lane): Use svmls_lane_impl.
17425 (svrecpe, svrsqrte): Handle unsigned integer operations too.
17426 (svwhilele, svwhilelt): Use svwhilelx_impl.
17427 * config/aarch64/aarch64-sve-builtins-sve2.h: New file.
17428 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
17429 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
17430 * config/aarch64/aarch64-sve-builtins.def: Include
17431 aarch64-sve-builtins-sve2.def.
17433 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17435 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
17436 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
17437 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
17438 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar
17439 immediates as well as vector ones.
17440 * config/aarch64/predicates.md (aarch64_sve_arith_immediate)
17441 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
17442 (aarch64_sve_qsub_immediate): Update calls accordingly.
17444 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17446 * config/aarch64/aarch64-sve2.md: Add banner comments.
17447 (<su>mulh<r>s<mode>3): Move further up file.
17448 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
17449 (*aarch64_sve2_sra<mode>): Move further down file.
17450 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.
17452 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17454 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW
17455 and UNSPEC_WHILEWR.
17456 (while_optab_cmp): Handle them.
17457 * config/aarch64/aarch64-sve.md
17458 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public
17459 and add a "@" marker.
17460 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it
17461 instead of gen_aarch64_sve2_while_ptest.
17462 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete.
17464 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17466 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to...
17467 (UNSPEC_WHILELE): ...this.
17468 (UNSPEC_WHILE_LO): Rename to...
17469 (UNSPEC_WHILELO): ...this.
17470 (UNSPEC_WHILE_LS): Rename to...
17471 (UNSPEC_WHILELS): ...this.
17472 (UNSPEC_WHILE_LT): Rename to...
17473 (UNSPEC_WHILELT): ...this.
17474 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly.
17475 (cmp_op, while_optab_cmp): Likewise.
17476 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise.
17477 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise.
17478 (svwhilelt): Likewise.
17480 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17482 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete.
17483 (unary_to_uint): Define.
17484 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def)
17485 (unary_count): Rename to...
17486 (unary_to_uint_def, unary_to_uint): ...this.
17487 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly.
17489 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17491 * config/aarch64/aarch64-sve-builtins-functions.h
17492 (code_for_mode_function): New class.
17493 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros.
17494 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl)
17495 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete.
17496 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0.
17497 (svmul_lane, svtmad): Use CODE_FOR_MODE0.
17499 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17501 * config/aarch64/iterators.md (addsub): New code attribute.
17502 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>):
17504 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change
17505 in the asm string and attributes. Fix indentation.
17506 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>):
17508 (@aarch64_sve_<optab><mode>): ...this.
17509 * config/aarch64/aarch64-sve-builtins.h
17510 (function_expander::expand_signed_unpred_op): Delete.
17511 * config/aarch64/aarch64-sve-builtins.cc
17512 (function_expander::expand_signed_unpred_op): Likewise.
17513 (function_expander::map_to_rtx_codes): If the optab isn't defined,
17514 try using code_for_aarch64_sve instead.
17515 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete.
17516 (svqsub_impl): Likewise.
17517 (svqadd, svqsub): Use rtx_code_function instead.
17519 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17521 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete.
17522 (HADDSUB, sur, addsub): Remove them.
17524 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17526 * tree-nrv.c (pass_return_slot::execute): Handle all internal
17527 functions the same way, rather than singling out those that
17528 aren't mapped directly to optabs.
17530 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17532 * target.def (compatible_vector_types_p): New target hook.
17533 * hooks.h (hook_bool_const_tree_const_tree_true): Declare.
17534 * hooks.c (hook_bool_const_tree_const_tree_true): New function.
17535 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook.
17536 * doc/tm.texi: Regenerate.
17537 * gimple-expr.c: Include target.h.
17538 (useless_type_conversion_p): Use targetm.compatible_vector_types_p.
17539 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New
17541 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define.
17542 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred):
17543 Use the original predicate if it already has a suitable type.
17545 2020-01-09 Martin Jambor <mjambor@suse.cz>
17547 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct,
17548 resolve_speculation and redirect_call_stmt_to_callee static. Change
17549 return type of set_call_stmt to cgraph_edge *.
17550 * auto-profile.c (afdo_indirect_call): Adjust call to
17551 redirect_call_stmt_to_callee.
17552 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *,
17553 make the this pointer explicit, adjust self-recursive calls and the
17554 call top make_direct. Return the resulting edge.
17555 (cgraph_edge::remove): Make this pointer explicit.
17556 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove.
17557 (cgraph_edge::make_direct): Likewise, adjust call to
17558 resolve_speculation.
17559 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust
17560 call to set_call_stmt.
17561 (cgraph_update_edges_for_call_stmt_node): Update call to
17562 set_call_stmt and remove.
17563 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
17564 Renamed edge to master_edge. Adjusted calls to set_call_stmt.
17565 (cgraph_node::create_edge_including_clones): Moved "first" definition
17566 of edge to the block where it was used. Adjusted calls to
17568 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to
17569 cgraph_edge::remove.
17570 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to
17571 make_direct and redirect_call_stmt_to_callee.
17572 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to
17573 resolve_speculation and make_direct.
17574 * ipa-inline-transform.c (inline_transform): Adjust call to
17575 redirect_call_stmt_to_callee.
17576 (check_speculations_1):: Adjust call to resolve_speculation.
17577 * ipa-inline.c (resolve_noninline_speculation): Adjust call to
17578 resolve-speculation.
17579 (inline_small_functions): Adjust call to resolve_speculation.
17580 (ipa_inline): Likewise.
17581 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to
17583 * ipa-visibility.c (function_and_variable_visibility): Make iteration
17584 safe with regards to edge removal, adjust calls to
17585 redirect_call_stmt_to_callee.
17586 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct
17587 and redirect_call_stmt_to_callee.
17588 * multiple_target.c (create_dispatcher_calls): Adjust call to
17589 redirect_call_stmt_to_callee
17590 (redirect_to_specific_clone): Likewise.
17591 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph):
17592 Adjust calls to cgraph_edge::remove.
17593 * tree-inline.c (copy_bb): Adjust call to set_call_stmt.
17594 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee.
17595 (expand_call_inline): Adjust call to cgraph_edge::remove.
17597 2020-01-09 Martin Liska <mliska@suse.cz>
17599 * params.opt: Set Optimization for
17600 param_max_speculative_devirt_maydefs.
17602 2020-01-09 Martin Sebor <msebor@redhat.com>
17604 PR middle-end/93200
17606 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type.
17608 2020-01-09 Martin Liska <mliska@suse.cz>
17610 * auto-profile.c (auto_profile): Use opt_for_fn
17612 * ipa-cp.c (ipcp_lattice::add_value): Likewise.
17613 (propagate_vals_across_arith_jfunc): Likewise.
17614 (hint_time_bonus): Likewise.
17615 (incorporate_penalties): Likewise.
17616 (good_cloning_opportunity_p): Likewise.
17617 (perform_estimation_of_a_value): Likewise.
17618 (estimate_local_effects): Likewise.
17619 (ipcp_propagate_stage): Likewise.
17620 * ipa-fnsummary.c (decompose_param_expr): Likewise.
17621 (set_switch_stmt_execution_predicate): Likewise.
17622 (analyze_function_body): Likewise.
17623 * ipa-inline-analysis.c (offline_size): Likewise.
17624 * ipa-inline.c (early_inliner): Likewise.
17625 * ipa-prop.c (ipa_analyze_node): Likewise.
17626 (ipcp_transform_function): Likewise.
17627 * ipa-sra.c (process_scan_results): Likewise.
17628 (ipa_sra_summarize_function): Likewise.
17629 * params.opt: Rename ipcp-unit-growth to
17630 ipa-cp-unit-growth. Add Optimization for various
17631 IPA-related parameters.
17633 2020-01-09 Richard Biener <rguenther@suse.de>
17635 PR middle-end/93054
17636 * gimplify.c (gimplify_expr): Deal with NOP definitions.
17638 2020-01-09 Richard Biener <rguenther@suse.de>
17640 PR tree-optimization/93040
17641 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit.
17643 2020-01-09 Georg-Johann Lay <avr@gjlay.de>
17645 * common/config/avr/avr-common.c (avr_option_optimization_table)
17646 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early.
17648 2020-01-09 Martin Liska <mliska@suse.cz>
17650 * cgraphclones.c (symbol_table::materialize_all_clones):
17651 Use cgraph_node::dump_name.
17653 2020-01-09 Jakub Jelinek <jakub@redhat.com>
17655 PR inline-asm/93202
17656 * config/riscv/riscv.c (riscv_print_operand_reloc): Use
17657 output_operand_lossage instead of gcc_unreachable.
17658 * doc/md.texi (riscv f constraint): Fix typo.
17661 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of
17662 SWI. Use <general_hilo_operand> instead of <general_operand>. Use
17663 CONST_SCALAR_INT_P instead of CONST_INT_P.
17664 (*subv<mode>4_1): Rename to ...
17665 (subv<mode>4_1): ... this.
17666 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
17667 define_insn_and_split patterns.
17668 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
17671 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17673 * vec.c (class selftest::count_dtor): New class.
17674 (selftest::test_auto_delete_vec): New test.
17675 (selftest::vec_c_tests): Call it.
17676 * vec.h (class auto_delete_vec): New class template.
17677 (auto_delete_vec<T>::~auto_delete_vec): New dtor.
17679 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17681 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap.
17683 2020-01-08 Jim Wilson <jimw@sifive.com>
17685 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out
17686 use of TLS_MODEL_LOCAL_EXEC when not pic.
17688 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17690 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix
17693 2020-01-08 Jakub Jelinek <jakub@redhat.com>
17696 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2,
17697 *stack_protect_set_3 peephole2): Also check that the second
17698 insns source is general_operand.
17701 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand
17702 predicate for output operand instead of register_operand.
17703 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with
17704 memory destination and non-memory operands[2].
17706 2020-01-08 Martin Liska <mliska@suse.cz>
17708 * cgraph.c (cgraph_node::dump): Use ::dump_name or
17709 ::dump_asm_name instead of (::name or ::asm_name).
17710 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise.
17711 * cgraphunit.c (walk_polymorphic_call_targets): Likewise.
17712 (analyze_functions): Likewise.
17713 (expand_all_functions): Likewise.
17714 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise.
17715 (propagate_bits_across_jump_function): Likewise.
17716 (dump_profile_updates): Likewise.
17717 (ipcp_store_bits_results): Likewise.
17718 (ipcp_store_vr_results): Likewise.
17719 * ipa-devirt.c (dump_targets): Likewise.
17720 * ipa-fnsummary.c (analyze_function_body): Likewise.
17721 * ipa-hsa.c (check_warn_node_versionable): Likewise.
17722 (process_hsa_functions): Likewise.
17723 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise.
17724 (set_alias_uids): Likewise.
17725 * ipa-inline-transform.c (save_inline_function_body): Likewise.
17726 * ipa-inline.c (recursive_inlining): Likewise.
17727 (inline_to_all_callers_1): Likewise.
17728 (ipa_inline): Likewise.
17729 * ipa-profile.c (ipa_propagate_frequency_1): Likewise.
17730 (ipa_propagate_frequency): Likewise.
17731 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.
17732 (remove_described_reference): Likewise.
17733 * ipa-pure-const.c (worse_state): Likewise.
17734 (check_retval_uses): Likewise.
17735 (analyze_function): Likewise.
17736 (propagate_pure_const): Likewise.
17737 (propagate_nothrow): Likewise.
17738 (dump_malloc_lattice): Likewise.
17739 (propagate_malloc): Likewise.
17740 (pass_local_pure_const::execute): Likewise.
17741 * ipa-visibility.c (optimize_weakref): Likewise.
17742 (function_and_variable_visibility): Likewise.
17743 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise.
17744 (ipa_discover_variable_flags): Likewise.
17745 * lto-streamer-out.c (output_function): Likewise.
17746 (output_constructor): Likewise.
17747 * tree-inline.c (copy_bb): Likewise.
17748 * tree-ssa-structalias.c (ipa_pta_execute): Likewise.
17749 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise.
17751 2020-01-08 Richard Biener <rguenther@suse.de>
17753 PR middle-end/93199
17754 * tree-eh.c (sink_clobbers): Update virtual operands for
17755 the first and last stmt only. Add a dry-run capability.
17756 (pass_lower_eh_dispatch::execute): Perform clobber sinking
17757 after CFG manipulations and in RPO order to catch all
17758 secondary opportunities reliably.
17760 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17763 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
17765 2019-01-08 Richard Biener <rguenther@suse.de>
17767 PR middle-end/93199
17768 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified.
17769 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust
17770 virtual operand, also updating SSA use.
17771 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction):
17772 Update stmt after resetting virtual operand.
17773 (tree_loop_interchange::move_code_to_inner_loop): Likewise.
17774 * gimple-iterator.c (gsi_remove): When not removing the stmt
17775 permanently do not delink immediate uses or mark the stmt modified.
17777 2020-01-08 Martin Liska <mliska@suse.cz>
17779 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name.
17780 (ipa_call_context::estimate_size_and_time): Likewise.
17781 (inline_analyze_function): Likewise.
17783 2020-01-08 Martin Liska <mliska@suse.cz>
17785 * cgraph.c (cgraph_node::dump): Use systematically
17788 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17790 Add -nodevicespecs option for avr.
17793 * config/avr/avr.opt (-nodevicespecs): New driver option.
17794 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue
17795 "-specs=device-specs/..." if that option is not set.
17796 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
17798 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17800 Implement 64-bit double functions for avr.
17803 * config.gcc (tm_defines) [target=avr]: Support --with-libf7,
17804 --with-double-comparison.
17805 * doc/install.texi: Document them.
17806 * config/avr/avr-c.c (avr_cpu_cpp_builtins)
17807 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
17808 <WITH_DOUBLE_COMPARISON>: New built-in defines.
17809 * doc/invoke.texi (AVR Built-in Macros): Document them.
17810 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
17811 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
17812 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
17814 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
17817 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
17818 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
17819 when only building rm-profile multilibs.
17821 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
17824 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
17825 lattice for a value to check.
17826 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
17827 finite propagation in self-recursive scc.
17829 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
17831 * ipa-inline.c (caller_growth_limits): Restore the AND.
17833 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
17835 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
17836 (VEC_ALLREG_ALT): New iterator.
17837 (VEC_ALLREG_INT_MODE): New iterator.
17838 (VCMP_MODE): New iterator.
17839 (VCMP_MODE_INT): New iterator.
17840 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
17841 (vec_cmp<u>v64qidi): New define_expand.
17842 (vec_cmp<mode>di_exec): Use VCMP_MODE.
17843 (vec_cmpu<mode>di_exec): New define_expand.
17844 (vec_cmp<u>v64qidi_exec): New define_expand.
17845 (vec_cmp<mode>di_dup): Use VCMP_MODE.
17846 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
17847 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
17848 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
17849 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
17850 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
17851 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
17852 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
17853 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
17854 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
17856 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
17857 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
17859 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
17861 * config/gcn/constraints.md (DA): Update description and match.
17863 (Db): New constraint.
17864 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
17866 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
17867 Implement 'Db' mixed immediate type.
17868 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
17869 (addcv64si3_dup<exec_vcc>): Delete.
17870 (subcv64si3<exec_vcc>): Rework constraints.
17871 (addv64di3): Rework constraints.
17872 (addv64di3_exec): Rework constraints.
17873 (subv64di3): Rework constraints.
17874 (addv64di3_dup): Delete.
17875 (addv64di3_dup_exec): Delete.
17876 (addv64di3_zext): Rework constraints.
17877 (addv64di3_zext_exec): Rework constraints.
17878 (addv64di3_zext_dup): Rework constraints.
17879 (addv64di3_zext_dup_exec): Rework constraints.
17880 (addv64di3_zext_dup2): Rework constraints.
17881 (addv64di3_zext_dup2_exec): Rework constraints.
17882 (addv64di3_sext_dup2): Rework constraints.
17883 (addv64di3_sext_dup2_exec): Rework constraints.
17885 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
17887 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
17888 existing target checks.
17890 2020-01-07 Richard Biener <rguenther@suse.de>
17892 * doc/install.texi: Bump minimal supported MPC version.
17894 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17896 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
17897 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
17898 * langhooks.c: Include stor-layout.h.
17899 (lhd_simulate_enum_decl): New function.
17900 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
17901 handle_arm_sve_h for the LTO frontend.
17902 (register_vector_type): Cope with null returns from pushdecl.
17904 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17906 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
17907 (aarch64_sve::nvectors_if_data_type): Replace with...
17908 (aarch64_sve::builtin_type_p): ...this.
17909 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
17910 (find_vector_type): Delete.
17911 (add_sve_type_attribute): New function.
17912 (lookup_sve_type_attribute): Likewise.
17913 (register_builtin_types): Add an "SVE type" attribute to each type.
17914 (register_tuple_type): Likewise.
17915 (svbool_type_p, nvectors_if_data_type): Delete.
17916 (mangle_builtin_type): Use lookup_sve_type_attribute.
17917 (builtin_type_p): Likewise. Add an overload that returns the
17918 number of constituent vector and predicate registers.
17919 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
17920 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
17921 instead of aarch64_sve_argument_p.
17922 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
17923 (aarch64_pass_by_reference): Likewise.
17924 (aarch64_function_value_1): Likewise.
17925 (aarch64_return_in_memory): Likewise.
17926 (aarch64_layout_arg): Likewise.
17928 2020-01-07 Jakub Jelinek <jakub@redhat.com>
17930 PR tree-optimization/93156
17931 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
17932 least significant bit is always clear.
17934 PR tree-optimization/93118
17935 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
17936 simplifier with two intermediate conversions.
17938 2020-01-07 Martin Liska <mliska@suse.cz>
17940 * params.opt: Add Optimization for various parameters.
17942 2020-01-07 Martin Liska <mliska@suse.cz>
17945 * doc/extend.texi: Explain cloning for target_clone
17948 2020-01-07 Martin Liska <mliska@suse.cz>
17950 PR tree-optimization/92860
17951 * common.opt: Make in Optimization option
17952 as it is affected by -O0, which is an Optimization
17954 * tree-inline.c (tree_inlinable_function_p):
17955 Use opt_for_fn for warn_inline.
17956 (expand_call_inline): Likewise.
17958 2020-01-07 Martin Liska <mliska@suse.cz>
17960 PR tree-optimization/92860
17961 * common.opt: Make flag_ree as optimization
17964 2020-01-07 Martin Liska <mliska@suse.cz>
17966 PR optimization/92860
17967 * params.opt: Mark param_min_crossjump_insns with Optimization
17970 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
17972 * ipa-inline-analysis.c (estimate_growth): Fix typo.
17973 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
17975 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
17977 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
17978 helper function to return the valid addressing formats for a given
17979 hard register and mode.
17980 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
17982 * config/rs6000/constraints.md (Q constraint): Update
17984 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
17987 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
17988 Use 'Q' for doing vector extract from memory.
17989 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
17991 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
17992 doing vector extract from memory.
17993 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
17994 extract from memory.
17996 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
17997 for the offset being 34-bits when -mcpu=future is used.
17999 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
18001 * config/pa/pa.md: Revert change to use ordered_comparison_operator
18002 instead of cmpib_comparison_operator in cmpib patterns.
18003 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
18004 of cmpib_comparison_operator. Revise comment.
18006 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
18008 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
18009 in an IFN_DIV_POW2 node to be equal.
18011 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
18013 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
18014 (vect_check_scalar_mask): ...this.
18015 (vectorizable_store, vectorizable_load): Update call accordingly.
18016 (vectorizable_call): Use vect_check_scalar_mask to check the mask
18017 argument in calls to conditional internal functions.
18019 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
18021 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
18022 '0' matching inputs.
18023 (subv64di3_exec): Likewise.
18025 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
18027 * config/mips/mips.c (vr4130_align_insns): Fix typo.
18028 * doc/md.texi (movstr): Likewise.
18030 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
18032 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
18035 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
18037 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
18039 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
18040 to a temporary file and use move-if-change to update the real
18041 file where necessary.
18043 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
18045 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
18046 rather than Upa for CPY /M.
18048 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
18050 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
18053 2020-01-06 Martin Liska <mliska@suse.cz>
18055 PR tree-optimization/92860
18056 * params.opt: Mark param_max_combine_insns with Optimization
18059 2020-01-05 Jakub Jelinek <jakub@redhat.com>
18062 * config/i386/i386.md (SWIDWI): New mode iterator.
18063 (DWI, dwi): Add TImode variants.
18064 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
18065 <general_hilo_operand> instead of <general_operand>. Use
18066 CONST_SCALAR_INT_P instead of CONST_INT_P.
18067 (*addv<mode>4_1): Rename to ...
18068 (addv<mode>4_1): ... this.
18069 (QWI): New mode attribute.
18070 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
18071 define_insn_and_split patterns.
18072 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
18074 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
18075 <general_hilo_operand> instead of <general_operand>.
18076 (*addcarry<mode>_1): New define_insn.
18077 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
18079 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
18081 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
18082 Use "call" instead of "set".
18084 2020-01-03 Martin Jambor <mjambor@suse.cz>
18087 * ipa-cp.c (print_all_lattices): Skip functions without info.
18089 2020-01-03 Jakub Jelinek <jakub@redhat.com>
18092 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
18093 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
18094 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
18095 for 'e' simd clones.
18098 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
18100 (mprefer-vector-width=): Add Save.
18101 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
18102 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
18103 (ix86_debug_options, ix86_function_specific_print): Adjust
18104 ix86_target_string callers.
18105 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
18106 (ix86_valid_target_attribute_tree): Likewise.
18107 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
18108 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
18109 ix86_target_string caller.
18112 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
18113 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
18114 instead of gen_int_shift_amount + convert_modes.
18116 PR rtl-optimization/93088
18117 * loop-iv.c (find_single_def_src): Punt after looking through
18118 128 reg copies for regs with single definitions. Move definitions
18121 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
18123 * config/arm/arm-c.c (arm_cpu_builtins): Define
18124 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
18125 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
18126 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
18127 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
18128 * config/arm/arm-tables.opt: Regenerated.
18129 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
18130 arm_arch_i8mm and arm_arch_bf16 when enabled.
18131 * config/arm/arm.h (TARGET_I8MM): New macro.
18132 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
18133 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
18134 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
18135 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
18136 (v8_6_a_simd_variants): New.
18137 (v8_*_a_simd_variants): Add i8mm and bf16.
18138 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
18140 2020-01-02 Jakub Jelinek <jakub@redhat.com>
18143 * predict.c (compute_function_frequency): Don't call
18144 warn_function_cold on functions that already have cold attribute.
18146 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
18149 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
18150 COMDAT group function labels in .data.rel.ro.local section.
18151 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
18154 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
18155 comparison_operator in B and S integer comparisons. Likewise, use
18156 ordered_comparison_operator instead of cmpib_comparison_operator in
18158 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
18160 2020-01-01 Jakub Jelinek <jakub@redhat.com>
18162 Update copyright years.
18164 * gcc.c (process_command): Update copyright notice dates.
18165 * gcov-dump.c (print_version): Ditto.
18166 * gcov.c (print_version): Ditto.
18167 * gcov-tool.c (print_version): Ditto.
18168 * gengtype.c (create_file): Ditto.
18169 * doc/cpp.texi: Bump @copying's copyright year.
18170 * doc/cppinternals.texi: Ditto.
18171 * doc/gcc.texi: Ditto.
18172 * doc/gccint.texi: Ditto.
18173 * doc/gcov.texi: Ditto.
18174 * doc/install.texi: Ditto.
18175 * doc/invoke.texi: Ditto.
18177 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
18179 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
18182 2020-01-01 Jakub Jelinek <jakub@redhat.com>
18184 PR tree-optimization/93098
18185 * match.pd (popcount): For shift amounts, use integer_onep
18186 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
18187 tests. Make sure that precision is power of two larger than or equal
18188 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
18189 instead of ULL suffixed constants. Formatting fixes.
18191 Copyright (C) 2020 Free Software Foundation, Inc.
18193 Copying and distribution of this file, with or without modification,
18194 are permitted in any medium without royalty provided the copyright
18195 notice and this notice are preserved.