1 2020-05-12 Richard Biener <rguenther@suse.de>
3 * cfghooks.c (split_edge): Preserve EDGE_DFS_BACK if set.
5 2020-05-12 Martin Liska <mliska@suse.cz>
9 * sanopt.c (sanitize_rewrite_addressable_params):
10 Clear DECL_NOT_GIMPLE_REG_P for argument.
12 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
14 PR tree-optimization/94980
15 * tree-vect-generic.c (expand_vector_comparison): Use
16 vector_element_bits_tree to get the element size in bits,
17 rather than using TYPE_SIZE.
18 (expand_vector_condition, vector_element): Likewise.
20 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
22 PR tree-optimization/94980
23 * tree-vect-generic.c (build_replicated_const): Take the number
24 of bits as a parameter, instead of the type of the elements.
25 (do_plus_minus): Update accordingly, using vector_element_bits
26 to calculate the correct number of bits.
27 (do_negate): Likewise.
29 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
31 PR tree-optimization/94980
32 * tree.h (vector_element_bits, vector_element_bits_tree): Declare.
33 * tree.c (vector_element_bits, vector_element_bits_tree): New.
34 * match.pd: Use the new functions instead of determining the
35 vector element size directly from TYPE_SIZE(_UNIT).
36 * tree-vect-data-refs.c (vect_gather_scatter_fn_p): Likewise.
37 * tree-vect-patterns.c (vect_recog_mask_conversion_pattern): Likewise.
38 * tree-vect-stmts.c (vect_is_simple_cond): Likewise.
39 * tree-vect-generic.c (expand_vector_piecewise): Likewise.
40 (expand_vector_conversion): Likewise.
41 (expand_vector_addition): Likewise for a TYPE_SIZE_UNIT used as
42 a divisor. Convert the dividend to bits to compensate.
43 * tree-vect-loop.c (vectorizable_live_operation): Call
44 vector_element_bits instead of open-coding it.
46 2020-05-12 Jakub Jelinek <jakub@redhat.com>
48 * omp-offload.h (omp_discover_implicit_declare_target): Declare.
49 * omp-offload.c: Include context.h.
50 (omp_declare_target_fn_p, omp_declare_target_var_p,
51 omp_discover_declare_target_fn_r, omp_discover_declare_target_var_r,
52 omp_discover_implicit_declare_target): New functions.
53 * cgraphunit.c (analyze_functions): Call
54 omp_discover_implicit_declare_target.
56 2020-05-12 Richard Biener <rguenther@suse.de>
58 * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Canonicalize
59 literal constant &MEM[..] to a constant literal.
61 2020-05-12 Richard Biener <rguenther@suse.de>
63 PR tree-optimization/95045
64 * dbgcnt.def (lim): Add debug-counter.
65 * tree-ssa-loop-im.c: Include dbgcnt.h.
66 (find_refs_for_sm): Use lim debug counter for store motion
68 (do_store_motion): Rename form store_motion. Commit edge
70 (store_motion_loop): ... here.
71 (tree_ssa_lim): Adjust.
73 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
75 * config/rs6000/altivec.h (vec_clzm): Rename to vec_cntlzm.
76 (vec_ctzm): Rename to vec_cnttzm.
77 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
78 Change fourth operand for vec_ternarylogic to require
79 compatibility with unsigned SImode rather than unsigned QImode.
80 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
81 Remove overloaded forms of vec_gnb that are no longer needed.
82 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
83 for a Future Architecture): Replace vec_clzm with vec_cntlzm;
84 replace vec_ctzm with vec_cntlzm; remove four unwanted forms of
85 vec_gnb; move vec_ternarylogic documentation into this section
86 and replace const unsigned char with const unsigned int as its
89 2020-05-11 Carl Love <cel@us.ibm.com>
91 * config/rs6000/altivec.h (vec_genpcvm): New #define.
92 * config/rs6000/rs6000-builtin.def (XXGENPCVM_V16QI): New built-in
94 (XXGENPCVM_V8HI): Likewise.
95 (XXGENPCVM_V4SI): Likewise.
96 (XXGENPCVM_V2DI): Likewise.
97 (XXGENPCVM): New overloaded built-in instantiation.
98 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add
99 entries for FUTURE_BUILTIN_VEC_XXGENPCVM.
100 (altivec_expand_builtin): Add special handling for
101 FUTURE_BUILTIN_VEC_XXGENPCVM.
102 (builtin_function_type): Add handling for
103 FUTURE_BUILTIN_XXGENPCVM_{V16QI,V8HI,V4SI,V2DI}.
104 * config/rs6000/vsx.md (VSX_EXTRACT_I4): New mode iterator.
105 (UNSPEC_XXGENPCV): New constant.
106 (xxgenpcvm_<mode>_internal): New insn.
107 (xxgenpcvm_<mode>): New expansion.
108 * doc/extend.texi: Add documentation for vec_genpcvm built-ins.
110 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
112 * config/rs6000/altivec.h (vec_strir): New #define.
113 (vec_stril): Likewise.
114 (vec_strir_p): Likewise.
115 (vec_stril_p): Likewise.
116 * config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
117 (UNSPEC_VSTRIL): Likewise.
118 (vstrir_<mode>): New expansion.
119 (vstrir_code_<mode>): New insn.
120 (vstrir_p_<mode>): New expansion.
121 (vstrir_p_code_<mode>): New insn.
122 (vstril_<mode>): New expansion.
123 (vstril_code_<mode>): New insn.
124 (vstril_p_<mode>): New expansion.
125 (vstril_p_code_<mode>): New insn.
126 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr):
127 New built-in function.
128 (__builtin_altivec_vstrihr): Likewise.
129 (__builtin_altivec_vstribl): Likewise.
130 (__builtin_altivec_vstrihl): Likewise.
131 (__builtin_altivec_vstribr_p): Likewise.
132 (__builtin_altivec_vstrihr_p): Likewise.
133 (__builtin_altivec_vstribl_p): Likewise.
134 (__builtin_altivec_vstrihl_p): Likewise.
135 (__builtin_vec_strir): New overloaded built-in function.
136 (__builtin_vec_stril): Likewise.
137 (__builtin_vec_strir_p): Likewise.
138 (__builtin_vec_stril_p): Likewise.
139 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
140 Define overloaded forms of __builtin_vec_strir,
141 __builtin_vec_stril, __builtin_vec_strir_p, and
142 __builtin_vec_stril_p.
143 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
144 for a Future Architecture): Add description of vec_stril,
145 vec_stril_p, vec_strir, and vec_strir_p built-in functions.
147 2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
149 * config/rs6000/altivec.h (vec_ternarylogic): New #define.
150 * config/rs6000/altivec.md (UNSPEC_XXEVAL): New constant.
152 * config/rs6000/predicates.md (u8bit_cint_operand): New predicate.
153 * config/rs6000/rs6000-builtin.def: Add handling of new macro
155 (BU_FUTURE_V_4): New macro. Use it.
156 (BU_FUTURE_OVERLOAD_4): Likewise.
157 * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Add
158 handling for quaternary built-in functions.
159 (altivec_resolve_overloaded_builtin): Add special-case handling
160 for __builtin_vec_xxeval.
161 * config/rs6000/rs6000-call.c: Add handling of new macro
162 RS6000_BUILTIN_4 in initialization of rs6000_builtin_info,
163 bdesc0_arg, bdesc1_arg, bdesc2_arg, bdesc_3arg,
164 bdesc_altivec_preds, bdesc_abs, and bdesc_htm arrays.
165 (altivec_overloaded_builtins): Add definitions for
166 FUTURE_BUILTIN_VEC_XXEVAL.
167 (bdesc_4arg): New array.
168 (htm_expand_builtin): Add handling for quaternary built-in
170 (rs6000_expand_quaternop_builtin): New function.
171 (rs6000_expand_builtin): Add handling for quaternary built-in
173 (rs6000_init_builtins): Initialize builtin_mode_to_type entries
174 for unsigned QImode and unsigned HImode.
175 (builtin_quaternary_function_type): New function.
176 (rs6000_common_init_builtins): Add handling of quaternary
178 * config/rs6000/rs6000.h (RS6000_BTC_QUATERNARY): New defined
180 (RS6000_BTC_PREDICATE): Change value of constant.
181 (RS6000_BTC_ABS): Likewise.
182 (rs6000_builtins): Add support for new macro RS6000_BUILTIN_4.
183 * doc/extend.texi (PowerPC AltiVec Built-In Functions Available
184 for a Future Architecture): Add description of vec_ternarylogic
187 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
189 * config/rs6000/rs6000-builtin.def (__builtin_pdepd): New built-in
191 (__builtin_pextd): Likewise.
192 * config/rs6000/rs6000.md (UNSPEC_PDEPD): New constant.
193 (UNSPEC_PEXTD): Likewise.
196 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
197 a Future Architecture): Add descriptions of __builtin_pdepd and
198 __builtin_pextd functions.
200 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
202 * config/rs6000/altivec.h (vec_clrl): New #define.
203 (vec_clrr): Likewise.
204 * config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
205 (UNSPEC_VCLRRB): Likewise.
208 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
210 (__builtin_altivec_vclrrb): Likewise.
211 (__builtin_vec_clrl): New overloaded built-in function.
212 (__builtin_vec_clrr): Likewise.
213 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
214 Define overloaded forms of __builtin_vec_clrl and
216 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
217 for a Future Architecture): Add descriptions of vec_clrl and
220 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
222 * config/rs6000/rs6000-builtin.def (__builtin_cntlzdm): New
223 built-in function definition.
224 (__builtin_cnttzdm): Likewise.
225 * config/rs6000/rs6000.md (UNSPEC_CNTLZDM): New constant.
226 (UNSPEC_CNTTZDM): Likewise.
229 * doc/extend.texi (Basic PowerPC Built-in Functions available for
230 a Future Architecture): Add descriptions of __builtin_cntlzdm and
231 __builtin_cnttzdm functions.
233 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
236 * config/i386/mmx.md (sqrtv2sf2): New insn pattern.
238 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
240 * config/rs6000/altivec.h (vec_cfuge): New #define.
241 * config/rs6000/altivec.md (UNSPEC_VCFUGED): New constant.
243 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vcfuged):
244 New built-in function.
245 * config/rs6000/rs6000-call.c (builtin_function_type): Add
246 handling for FUTURE_BUILTIN_VCFUGED case.
247 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
248 for a Future Architecture): Add description of vec_cfuge built-in
251 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
253 * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_0): New
255 (BU_FUTURE_MISC_1): Likewise.
256 (BU_FUTURE_MISC_2): Likewise.
257 (BU_FUTURE_MISC_3): Likewise.
258 (__builtin_cfuged): New built-in function definition.
259 * config/rs6000/rs6000.md (UNSPEC_CFUGED): New constant.
261 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
262 a Future Architecture): New subsubsection.
264 2020-05-11 Richard Biener <rguenther@suse.de>
266 PR tree-optimization/95049
267 * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition
268 between different constants.
270 2020-05-11 Richard Sandiford <richard.sandiford@arm.com>
272 * tree-pretty-print.c (dump_generic_node): Handle BOOLEAN_TYPEs.
274 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
275 Bill Schmidt <wschmidt@linux.ibm.com>
277 * config/rs6000/altivec.h (vec_gnb): New #define.
278 * config/rs6000/altivec.md (UNSPEC_VGNB): New constant.
280 * config/rs6000/rs6000-builtin.def (BU_FUTURE_OVERLOAD_1): New
282 (BU_FUTURE_OVERLOAD_2): Likewise.
283 (BU_FUTURE_OVERLOAD_3): Likewise.
284 (__builtin_altivec_gnb): New built-in function.
285 (__buiiltin_vec_gnb): New overloaded built-in function.
286 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
287 Define overloaded forms of __builtin_vec_gnb.
288 (rs6000_expand_binop_builtin): Add error checking for 2nd argument
289 of __builtin_vec_gnb.
290 (builtin_function_type): Mark return value and arguments unsigned
291 for FUTURE_BUILTIN_VGNB.
292 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
293 for a Future Architecture): Add description of vec_gnb built-in
296 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
297 Bill Schmidt <wschmidt@linux.ibm.com>
299 * config/rs6000/altivec.h (vec_pdep): New macro implementing new
301 (vec_pext): Likewise.
302 * config/rs6000/altivec.md (UNSPEC_VPDEPD): New constant.
303 (UNSPEC_VPEXTD): Likewise.
306 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vpdepd): New
308 (__builtin_altivec_vpextd): Likewise.
309 * config/rs6000/rs6000-call.c (builtin_function_type): Add
310 handling for FUTURE_BUILTIN_VPDEPD and FUTURE_BUILTIN_VPEXTD
312 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
313 for a Future Architecture): Add description of vec_pdep and
314 vec_pext built-in functions.
316 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
317 Bill Schmidt <wschmidt@linux.ibm.com>
319 * config/rs6000/altivec.h (vec_clzm): New macro.
320 (vec_ctzm): Likewise.
321 * config/rs6000/altivec.md (UNSPEC_VCLZDM): New constant.
322 (UNSPEC_VCTZDM): Likewise.
325 * config/rs6000/rs6000-builtin.def (BU_FUTURE_V_0): New macro.
326 (BU_FUTURE_V_1): Likewise.
327 (BU_FUTURE_V_2): Likewise.
328 (BU_FUTURE_V_3): Likewise.
329 (__builtin_altivec_vclzdm): New builtin definition.
330 (__builtin_altivec_vctzdm): Likewise.
331 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Cause
332 _ARCH_PWR_FUTURE macro to be defined if OPTION_MASK_FUTURE flag is
334 * config/rs6000/rs6000-call.c (builtin_function_type): Set return
335 value and parameter types to be unsigned for VCLZDM and VCTZDM.
336 * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
337 support for TARGET_FUTURE flag.
338 * config/rs6000/rs6000.h (RS6000_BTM_FUTURE): New macro constant.
339 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
340 for a Future Architecture): New subsubsection.
342 2020-05-11 Richard Biener <rguenther@suse.de>
344 PR tree-optimization/94988
345 PR tree-optimization/95025
346 * tree-ssa-loop-im.c (seq_entry): Make a struct, add from.
347 (sm_seq_push_down): Take extra parameter denoting where we
349 (execute_sm_exit): Re-issue sm_other stores in the correct
351 (sm_seq_valid_bb): When always executed, allow sm_other to
352 prevail inbetween sm_ord and record their stored value.
353 (hoist_memory_references): Adjust refs_not_supported propagation
354 and prune sm_other from the end of the ordered sequences.
356 2020-05-11 Felix Yang <felix.yang@huawei.com>
359 * config/aarch64/aarch64.md (mov<mode>):
360 Bitcasts to the equivalent integer mode using gen_lowpart
361 instead of doing FAIL for scalar floating point move.
363 2020-05-11 Alex Coplan <alex.coplan@arm.com>
365 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Add case
366 to correctly calculate cost for new pattern (*csinv3_uxtw_insn3).
367 * config/aarch64/aarch64.md (*csinv3_utxw_insn1): New.
368 (*csinv3_uxtw_insn2): New.
369 (*csinv3_uxtw_insn3): New.
370 * config/aarch64/iterators.md (neg_not_cs): New.
372 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
375 * config/i386/mmx.md (mmx_addv2sf3): Use "v" constraint
376 instead of "Yv" for AVX alternatives. Add "prefix" attribute.
377 (*mmx_addv2sf3): Ditto.
378 (*mmx_subv2sf3): Ditto.
379 (*mmx_mulv2sf3): Ditto.
380 (*mmx_<code>v2sf3): Ditto.
381 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
383 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
386 * config/i386/i386.c (ix86_vector_mode_supported_p):
387 Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE.
388 * config/i386/mmx.md (*mov<mode>_internal): Do not set
389 mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE.
391 (mmx_addv2sf3): Change operand predicates from
392 nonimmediate_operand to register_mmxmem_operand.
393 (addv2sf3): New expander.
394 (*mmx_addv2sf3): Add SSE/AVX alternatives. Change operand
395 predicates from nonimmediate_operand to register_mmxmem_operand.
396 Enable instruction pattern for TARGET_MMX_WITH_SSE.
398 (mmx_subv2sf3): Change operand predicate from
399 nonimmediate_operand to register_mmxmem_operand.
400 (mmx_subrv2sf3): Ditto.
401 (subv2sf3): New expander.
402 (*mmx_subv2sf3): Add SSE/AVX alternatives. Change operand
403 predicates from nonimmediate_operand to register_mmxmem_operand.
404 Enable instruction pattern for TARGET_MMX_WITH_SSE.
406 (mmx_mulv2sf3): Change operand predicates from
407 nonimmediate_operand to register_mmxmem_operand.
408 (mulv2sf3): New expander.
409 (*mmx_mulv2sf3): Add SSE/AVX alternatives. Change operand
410 predicates from nonimmediate_operand to register_mmxmem_operand.
411 Enable instruction pattern for TARGET_MMX_WITH_SSE.
413 (mmx_<code>v2sf3): Change operand predicates from
414 nonimmediate_operand to register_mmxmem_operand.
415 (<code>v2sf3): New expander.
416 (*mmx_<code>v2sf3): Add SSE/AVX alternatives. Change operand
417 predicates from nonimmediate_operand to register_mmxmem_operand.
418 Enable instruction pattern for TARGET_MMX_WITH_SSE.
419 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
421 2020-05-11 Martin Liska <mliska@suse.cz>
424 * common.opt: Fix typo in option description.
426 2020-05-11 Martin Liska <mliska@suse.cz>
428 PR gcov-profile/94928
429 * gcov-io.h: Add caveat about coverage format parsing and
430 possible outdated documentation.
432 2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com>
434 PR tree-optimization/83403
435 * tree-affine.c (expr_to_aff_combination): Replace SSA_NAME with
436 determine_value_range, Add fold conversion of MULT_EXPR, fix the
439 2020-05-10 Gerald Pfeifer <gerald@pfeifer.com>
441 * config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and
442 __ILP32__ for 32-bit targets.
444 2020-05-09 Eric Botcazou <ebotcazou@adacore.com>
446 * tree.h (expr_align): Delete.
447 * tree.c (expr_align): Likewise.
449 2020-05-09 Hans-Peter Nilsson <hp@axis.com>
451 * resource.c (init_resource_info): Filter-out TARGET_FLAGS_REGNUM
452 from end_of_function_needs.
454 * config.gcc: Remove support for crisv32-*-* and cris-*-linux*.
455 * config/cris/t-linux, config/cris/linux.h, config/cris/linux.opt:
457 * config/cris/t-elfmulti: Remove crisv32 multilib.
458 * config/cris: Remove shared-library and CRIS v32 support.
460 Move trivially from cc0 to reg:CC model, removing most optimizations.
461 * config/cris/cris.md: Remove all side-effect patterns and their
462 splitters. Remove most peepholes. Add clobbers of CRIS_CC0_REGNUM
463 to all but post-reload control-flow and movem insns. Remove
464 constraints on all modified expanders. Remove obsoleted cc0-related
466 (attr "cc"): Remove alternative "rev".
467 (mode_iterator BWDD, DI_, SI_): New.
468 (mode_attr sCC_destc, cmp_op1c, cmp_op2c): New.
469 ("tst<mode>"): Remove; fold as "M" alternative into compare insn.
470 ("mstep_shift", "mstep_mul"): Remove patterns.
471 ("s<rcond>", "s<ocond>", "s<ncond>"): Anonymize.
472 * config/cris/cris.c: Change all non-condition-code,
473 non-control-flow emitted insns to add a parallel with clobber of
474 CRIS_CC0_REGNUM, mostly by changing from gen_rtx_SET with
475 emit_insn to use of emit_move_insn, gen_add2_insn or
476 cris_emit_insn, as convenient.
477 (cris_reg_overlap_mentioned_p)
478 (cris_normal_notice_update_cc, cris_notice_update_cc): Remove.
479 (cris_movem_load_rest_p): Don't assume all elements in a
481 (cris_store_multiple_op_p): Ditto.
482 (cris_emit_insn): New function.
483 * cris/cris-protos.h (cris_emit_insn): Declare.
486 * config/cris/cris.md (zcond): New code_iterator.
487 ("*cbranch<mode>4_btstq<CC>"): New insn_and_split.
489 * config/cris/cris.c (TARGET_FLAGS_REGNUM): Define.
491 * config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.
493 * config/cris/cris.md ("movsi"): For memory destination
494 post-reload, generate clobberless variant. Similarly for a
495 zero-source post-reload.
496 ("*mov_tomem<mode>_split"): New split.
497 ("*mov_tomem<mode>"): New insn.
498 ("enabled", mov_tomem_enabled): Define and use to exclude "x" ->
499 "Q>m" for less-than-SImode.
500 ("*mov_fromzero<mode>_split"): New split.
501 ("*mov_fromzero<mode>"): New insn.
503 Prepare for cmpelim pass to eliminate redundant compare insns.
504 * config/cris/cris-modes.def: New file.
505 * config/cris/cris-protos.h (cris_select_cc_mode): Declare.
506 (cris_notice_update_cc): Remove left-over declaration.
507 * config/cris/cris.c (TARGET_CC_MODES_COMPATIBLE): Define.
508 (cris_select_cc_mode, cris_cc_modes_compatible): New functions.
509 * config/cris/cris.h (SELECT_CC_MODE): Define.
510 * config/cris/cris.md (NZSET, NZUSE, NZVCSET, NZVCUSE): New
512 (cond): New code_iterator.
513 (nzcond): Replacement for incorrect ncond. All callers changed.
514 (nzvccond): Replacement for ocond. All callers changed.
515 (rnzcond): Replacement for rcond. All callers changed.
516 (xCC): New code_attr.
517 (cmp_op1c, cmp_op0c): Renumber from cmp_op1c and cmp_op2c. All
519 ("*cmpdi<NZVCSET:mode>"): Rename from "*cmpdi". Replace
520 CCmode with iteration over NZVCSET.
521 ("*cmp_ext<BW:mode><NZVCSET:mode>"): Similarly; rename from
523 ("*cmpsi<NZVCSET:mode>"): Similarly, from "*cmpsi".
524 ("*cmp<BW:mode><NZVCSET:mode>"): Similarly from "*cmp<mode>".
525 ("*btst<mode>"): Similarly, from "*btst".
526 ("*cbranch<mode><code>4"): Rename from "*cbranch<mode>4",
527 iterating over cond instead of matching the comparison with
528 ordered_comparison_operator.
529 ("*cbranch<mode>4_btstq<CC>"): Correct label operand number.
530 ("b<zcond:code><mode>"): Rename from "b<ncond:code>", iterating
532 ("b<nzvccond:code><mode>"): Similarly from "b<ocond:code>", over
533 NZVCUSE. Remove FIXME.
534 ("*b<nzcond:code>_reversed<mode>"): Similarly from
535 "*b<ncond:code>_reversed", over NZUSE.
536 ("*b<nzvccond:code>_reversed<mode>"): Similarly from
537 "*b<ocond:code>_reversed", over NZVCUSE. Remove FIXME.
538 ("b<rnzcond:code><mode>"): Similarly from "b<rcond:code>",
539 over NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
540 depending on CC_NZmode vs. CCmode. Remove FIXME.
541 ("*b<rnzcond:code>_reversed<mode>"): Similarly from
542 "*b<rcond:code>_reversed", over NZUSE.
543 ("*cstore<mode><code>4"): Rename from "*cstore<mode>4",
544 iterating over cond instead of matching the comparison with
545 ordered_comparison_operator.
546 ("*s<nzcond:code><mode>"): Rename from "*s<ncond:code>",
547 iterating over NZUSE.
548 ("*s<rnzcond:code><mode>"): Similar from "*s<rcond:code>", over
549 NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
550 depending on CC_NZmode vs. CCmode.
551 ("*s<nzvccond:code><mode>"): Simlar from "*s<ocond:code>", over
552 NZVCUSE. Remove FIXME.
553 ("cc"): Comment on new use.
554 ("cc_enabled"): New attribute.
555 ("enabled"): Make default fall back to cc_enabled.
556 ("setnz", "ccnz", "setnzvc", "ccnzvc", "setcc", "cccc"): New
558 ("setnz_subst", "setnzvc_subst", "setcc_subst"): New default_subst.
559 ("*movsi_internal<setcc><setnz><setnzvc>"): Rename from
560 "*movsi_internal". Correct contents of, and rename attribute
561 "cc" to "cc<cccc><ccnz><ccnzvc>".
562 ("anz", "anzvc", "acc"): New define_subst_attrs.
563 ("<acc><anz><anzvc>movhi<setcc><setnz><setnzvc>"): Rename from
564 "movhi". Rename "cc" attribute to "cc<cccc><ccnz><ccnzvc>".
565 ("<acc><anz><anzvc>movqi<setcc><setnz><setnzvc>"): Similar from
566 "movqi". Correct contents of, and rename "cc" attribute to
567 "cc<cccc><ccnz><ccnzvc>".
568 ("*b<zcond:code><mode>"): Rename from "b<zcond:code><mode>".
569 ("*b<nzvccond:code><mode>"): Rename from "b<nzvccond:code><mode>".
570 ("*b<rnzcond:code><mode>"): Rename from "*b<rnzcond:code><mode>".
571 ("<acc><anz><anzvc>extend<mode>si2<setcc><setnz><setnzvc>"):
572 Rename from "extend<mode>si2".
573 ("<acc><anz><anzvc>zero_extend<mode>si2<setcc><setnz><setnzvc>"):
574 Similar, from "zero_extend<mode>si2".
575 ("*adddi3<setnz>"): Rename from "*adddi3".
576 ("*subdi3<setnz>"): Similarly from "*subdi3".
577 ("*addsi3<setnz>"): Similarly from "*addsi3".
578 ("*subsi3<setnz>"): Similarly from "*subsi3".
579 ("*addhi3<setnz>"): Similarly from "*addhi3" and decorate the
580 "cc" attribute to "cc<ccnz>".
581 ("*addqi3<setnz>"): Similarly from "*addqi3".
582 ("*sub<mode>3<setnz>"): Similarly from "*sub<mode>3".
583 ("*expanded_andsi<setcc><setnz><setnzvc>"): Rename from
585 ("*iorsi3<setcc><setnz><setnzvc>"): Similar from "*iorsi3".
586 Decorate "cc" attribute to make "cc<cccc><ccnz><ccnzvc>".
587 ("*iorhi3<setcc><setnz><setnzvc>"): Similar from "*iorhi3".
588 ("*iorqi3<setcc><setnz><setnzvc>"): Similar from "*iorqi3".
589 ("*expanded_andhi<setcc><setnz><setnzvc>"): Similar from
590 "*expanded_andhi". Add quick cc-setting alternative for 0..31.
591 ("*andqi3<setcc><setnz><setnzvc>"): Similar from "*andqi3".
592 ("<acc><anz><anzvc>xorsi3<setcc><setnz><setnzvc>"): Rename
594 ("<acc><anz><anzvc>one_cmplsi2<setcc><setnz><setnzvc>"): Rename
596 ("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"): Rename
598 ("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"): Rename
600 ("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"): Rename
602 ("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".
604 * config/cris/cris-modes.def (CC_ZnN): New CC_MODE.
605 * config/cris/cris.c (cris_rtx_costs): Handle pre-split bit-test
606 * config/cris/cris.md (ZnNNZSET, ZnNNZUSE): New mode_iterators.
607 (znnCC, rznnCC): New code_attrs.
608 ("*btst<mode>"): Iterator over ZnNNZSET instead of NZVCSET. Remove
609 obseolete comment. Add belt-and-suspenders mode-test to condition.
610 Add fixme regarding remaining matched-but-not-generated case.
611 ("*cbranch<mode>4_btstrq1_<CC>"): New insn_and_split.
612 ("*cbranch<mode>4_btstqb0_<CC>"): Rename from
613 "*cbranch<mode>4_btstq<CC>". Split to CC_NZ instead of CC.
614 ("*b<zcond:code><mode>"): Iterate over ZnNNZUSE instead of NZUSE.
615 Handle output of CC_ZnNmode.
616 ("*b<nzcond:code>_reversed<mode>"): Ditto.
618 * config/cris/cris.c (cris_select_cc_mode): Return CC_NZmode for
619 NEG too. Correct comment.
620 * config/cris/cris.md ("<anz>neg<mode>2<setnz>"): Rename from
623 2020-05-08 Vladimir Makarov <vmakarov@redhat.com>
625 * ira-color.c (update_costs_from_allocno): Remove
626 conflict_cost_update_p argument. Propagate costs only along
627 threads. Always do conflict cost update. Add printing debugging
629 (update_costs_from_copies): Add printing debugging info.
630 (restore_costs_from_copies): Ditto.
631 (assign_hard_reg): Improve debug info.
632 (push_only_colorable): Ditto. Call update_costs_from_prefs.
633 (color_allocnos): Remove update_costs_from_prefs.
635 2020-05-08 Richard Biener <rguenther@suse.de>
637 * tree-vectorizer.h (vec_info::slp_loads): New.
638 (vect_optimize_slp): Declare.
639 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Do
640 nothing when there are no loads.
641 (vect_gather_slp_loads): Gather loads into a vector.
642 (vect_supported_load_permutation_p): Remove.
643 (vect_analyze_slp_instance): Do not verify permutation
645 (vect_analyze_slp): Optimize permutations of reductions
646 after all SLP instances have been gathered and gather
648 (vect_optimize_slp): New function split out from
649 vect_supported_load_permutation_p. Elide some permutations.
650 (vect_slp_analyze_bb_1): Call vect_optimize_slp.
651 * tree-vect-loop.c (vect_analyze_loop_2): Likewise.
652 * tree-vect-stmts.c (vectorizable_load): Check whether
653 the load can be permuted. When generating code assert we can.
655 2020-05-08 Richard Biener <rguenther@suse.de>
657 * tree-ssa-sccvn.c (rpo_avail): Change type to
658 eliminate_dom_walker *.
659 (eliminate_with_rpo_vn): Adjust rpo_avail to make vn_valueize
660 use the DOM walker availability.
661 (vn_reference_fold_indirect): Use get_addr_base_and_unit_offset_1
662 with vn_valueize as valueization callback.
663 (vn_reference_maybe_forwprop_address): Likewise.
664 * tree-dfa.c (get_addr_base_and_unit_offset_1): Also valueize
667 2020-05-08 Jakub Jelinek <jakub@redhat.com>
669 PR tree-optimization/94786
670 * match.pd (A ^ ((A ^ B) & -(C cmp D)) -> (C cmp D) ? B : A): New
674 * config/i386/i386.md (peephole2 after *add<mode>3_cc_overflow_1): New
678 * tree.c (get_narrower): Reuse the op temporary instead of
681 PR tree-optimization/94783
682 * match.pd ((X + (X >> (prec - 1))) ^ (X >> (prec - 1)) to abs (X)):
685 PR tree-optimization/94956
686 * match.pd (FFS): Optimize __builtin_ffs* of non-zero argument into
687 __builtin_ctz* + 1 if direct IFN_CTZ is supported.
689 PR tree-optimization/94913
690 * match.pd (A - B + -1 >= A to B >= A): New simplification.
691 (A - B > A to A < B): Don't test TYPE_OVERFLOW_WRAPS which is always
692 true for TYPE_UNSIGNED integral types.
695 PR rtl-optimization/94516
696 * rtl.h (remove_reg_equal_equiv_notes): Add a bool argument defaulted
698 * rtlanal.c (remove_reg_equal_equiv_notes): Add no_rescan argument.
699 Call df_notes_rescan if that argument is not true and returning true.
700 * combine.c (adjust_for_new_dest): Pass true as second argument to
701 remove_reg_equal_equiv_notes.
702 * postreload.c (reload_combine_recognize_pattern): Don't call
705 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
707 * config/rs6000/rs6000.md (*setnbc_<un>signed_<GPR:mode>): New
709 (*setnbcr_<un>signed_<GPR:mode>): New define_insn.
710 (*neg_eq_<mode>): Avoid for TARGET_FUTURE; add missing && 1.
711 (*neg_ne_<mode>): Likewise.
713 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
715 * config/rs6000/rs6000.md (setbc_<un>signed_<GPR:mode>): New
717 (*setbcr_<un>signed_<GPR:mode>): Likewise.
718 (cstore<mode>4): Use setbc[r] if available.
719 (<code><GPR:mode><GPR2:mode>2_isel): Avoid for TARGET_FUTURE.
720 (eq<mode>3): Use setbc for TARGET_FUTURE.
721 (*eq<mode>3): Avoid for TARGET_FUTURE.
722 (ne<mode>3): Replace :P with :GPR; use setbc for TARGET_FUTURE;
723 else for non-Pmode, use gen_eq and gen_xor.
724 (*ne<mode>3): Avoid for TARGET_FUTURE.
725 (*eqsi3_ext<mode>): Avoid for TARGET_FUTURE; fix missing && 1.
727 2020-05-07 Jeff Law <law@redhat.com>
729 * config/h8300/h8300.md: Move expanders and patterns into
730 files based on functionality.
731 * config/h8300/addsub.md: New file.
732 * config/h8300/bitfield.md: New file
733 * config/h8300/combiner.md: New file
734 * config/h8300/divmod.md: New file
735 * config/h8300/extensions.md: New file
736 * config/h8300/jumpcall.md: New file
737 * config/h8300/logical.md: New file
738 * config/h8300/movepush.md: New file
739 * config/h8300/multiply.md: New file
740 * config/h8300/other.md: New file
741 * config/h8300/proepi.md: New file
742 * config/h8300/shiftrotate.md: New file
743 * config/h8300/testcompare.md: New file
745 * config/h8300/h8300.md (adds/subs splitters): Merge into single
747 (negation expanders and patterns): Simplify and combine using
749 (one_cmpl expanders and patterns): Likewise.
750 (tablejump, indirect_jump patterns ): Likewise.
751 (shift and rotate expanders and patterns): Likewise.
752 (absolute value expander and pattern): Drop expander, rename pattern
754 (peephole2 patterns): Move into...
755 * config/h8300/peepholes.md: New file.
757 * config/h8300/constraints.md (L and N): Simplify now that we're not
758 longer supporting the original H8/300 chip.
759 * config/h8300/elf.h (LINK_SPEC): Likewise. Default to H8/300H.
760 * config/h8300/h8300.c (shift_alg_qi): Drop H8/300 support.
761 (shift_alg_hi, shift_alg_si): Similarly.
762 (h8300_option_overrides): Similarly. Default to H8/300H. If
763 compiling for H8/S, then turn off H8/300H. Do not update the
764 shift_alg tables for H8/300 port.
765 (h8300_emit_stack_adjustment): Remove support for H8/300. Simplify
767 (push, split_adds_subs, h8300_rtx_costs): Likewise.
768 (h8300_print_operand, compute_mov_length): Likewise.
769 (output_plussi, compute_plussi_length): Likewise.
770 (compute_plussi_cc, output_logical_op): Likewise.
771 (compute_logical_op_length, compute_logical_op_cc): Likewise.
772 (get_shift_alg, h8300_shift_needs_scratch): Likewise.
773 (output_a_shift, compute_a_shift_length): Likewise.
774 (output_a_rotate, compute_a_rotate_length): Likewise.
775 (output_simode_bld, h8300_hard_regno_mode_ok): Likewise.
776 (h8300_modes_tieable_p, h8300_return_in_memory): Likewise.
777 * config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Likewise.
778 (attr_cpu, TARGET_H8300): Remove.
779 (TARGET_DEFAULT): Update.
780 (UNITS_PER_WORD, PARM_BOUNDARY): Simplify where possible.
781 (BIGGEST_ALIGNMENT, STACK_BOUNDARY): Likewise.
782 (CONSTANT_ADDRESS_P, MOVE_MAX, Pmode): Likewise.
783 (SIZE_TYPE, POINTER_SIZE, ASM_WORD_OP): Likewise.
784 * config/h8300/h8300.md: Simplify patterns throughout.
785 * config/h8300/t-h8300: Update multilib configuration.
787 * config/h8300/h8300.h (LINK_SPEC): Remove.
788 (USER_LABEL_PREFIX): Likewise.
790 * config/h8300/h8300.c (h8300_asm_named_section): Remove.
791 (h8300_option_override): Remove remnants of COFF support.
793 2020-05-07 Alan Modra <amodra@gmail.com>
795 * tree-ssa-reassoc.c (optimize_range_tests_to_bit_test): Replace
796 set_rtx_cost with set_src_cost.
797 * tree-switch-conversion.c (bit_test_cluster::emit): Likewise.
799 2020-05-07 Kewen Lin <linkw@gcc.gnu.org>
801 * tree-vect-stmts.c (vectorizable_load): Check alignment to avoid
802 redundant half vector handlings for no peeling gaps.
804 2020-05-07 Giuliano Belinassi <giuliano.belinassi@usp.br>
806 * tree-ssa-operands.c (operands_scanner): New class.
807 (operands_bitmap_obstack): Remove.
808 (n_initialized): Remove.
809 (build_uses): Move to operands_scanner class.
810 (build_vuse): Same as above.
811 (build_vdef): Same as above.
812 (verify_ssa_operands): Same as above.
813 (finalize_ssa_uses): Same as above.
814 (cleanup_build_arrays): Same as above.
815 (finalize_ssa_stmt_operands): Same as above.
816 (start_ssa_stmt_operands): Same as above.
817 (append_use): Same as above.
818 (append_vdef): Same as above.
819 (add_virtual_operand): Same as above.
820 (add_stmt_operand): Same as above.
821 (get_mem_ref_operands): Same as above.
822 (get_tmr_operands): Same as above.
823 (maybe_add_call_vops): Same as above.
824 (get_asm_stmt_operands): Same as above.
825 (get_expr_operands): Same as above.
826 (parse_ssa_operands): Same as above.
827 (finalize_ssa_defs): Same as above.
828 (build_ssa_operands): Same as above, plus create a C-like wrapper.
829 (update_stmt_operands): Create an instance of operands_scanner.
831 2020-05-07 Richard Biener <rguenther@suse.de>
834 * tree-ssa-structalias.c (refered_from_nonlocal_fn): Use
835 DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible.
836 (refered_from_nonlocal_var): Likewise.
837 (ipa_pta_execute): Likewise.
839 2020-05-07 Erick Ochoa <erick.ochoa@theobroma-systems.com>
841 * gcc/tree-ssa-struct-alias.c: Fix comments
843 2020-05-07 Martin Liska <mliska@suse.cz>
845 * doc/invoke.texi: Fix 2 optindex entries.
847 2020-05-07 Richard Biener <rguenther@suse.de>
850 * tree-core.h (tree_decl_common::gimple_reg_flag): Rename ...
851 (tree_decl_common::not_gimple_reg_flag): ... to this.
852 * tree.h (DECL_GIMPLE_REG_P): Rename ...
853 (DECL_NOT_GIMPLE_REG_P): ... to this.
854 * gimple-expr.c (copy_var_decl): Copy DECL_NOT_GIMPLE_REG_P.
855 (create_tmp_reg): Simplify.
856 (create_tmp_reg_fn): Likewise.
857 (is_gimple_reg): Check DECL_NOT_GIMPLE_REG_P for all regs.
858 * gimplify.c (create_tmp_from_val): Simplify.
859 (gimplify_bind_expr): Likewise.
860 (gimplify_compound_literal_expr): Likewise.
861 (gimplify_function_tree): Likewise.
862 (prepare_gimple_addressable): Set DECL_NOT_GIMPLE_REG_P.
863 * asan.c (create_odr_indicator): Do not clear DECL_GIMPLE_REG_P.
864 (asan_add_global): Copy it.
865 * cgraphunit.c (cgraph_node::expand_thunk): Force args
867 * function.c (gimplify_parameters): Copy
868 DECL_NOT_GIMPLE_REG_P.
869 * ipa-param-manipulation.c
870 (ipa_param_body_adjustments::common_initialization): Simplify.
871 (ipa_param_body_adjustments::reset_debug_stmts): Copy
872 DECL_NOT_GIMPLE_REG_P.
873 * omp-low.c (lower_omp_for_scan): Do not set DECL_GIMPLE_REG_P.
874 * sanopt.c (sanitize_rewrite_addressable_params): Likewise.
875 * tree-cfg.c (make_blocks_1): Simplify.
876 (verify_address): Do not verify DECL_GIMPLE_REG_P setting.
877 * tree-eh.c (lower_eh_constructs_2): Simplify.
878 * tree-inline.c (declare_return_variable): Adjust and
880 (copy_decl_to_var): Copy DECL_NOT_GIMPLE_REG_P.
881 (copy_result_decl_to_var): Likewise.
882 * tree-into-ssa.c (pass_build_ssa::execute): Adjust comment.
883 * tree-nested.c (create_tmp_var_for): Simplify.
884 * tree-parloops.c (separate_decls_in_region_name): Copy
885 DECL_NOT_GIMPLE_REG_P.
886 * tree-sra.c (create_access_replacement): Adjust and
887 generalize partial def support.
888 * tree-ssa-forwprop.c (pass_forwprop::execute): Set
889 DECL_NOT_GIMPLE_REG_P on decls we introduce partial defs on.
890 * tree-ssa.c (maybe_optimize_var): Handle clearing of
891 TREE_ADDRESSABLE and setting/clearing DECL_NOT_GIMPLE_REG_P
893 * lto-streamer-out.c (hash_tree): Hash DECL_NOT_GIMPLE_REG_P.
894 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Stream
895 DECL_NOT_GIMPLE_REG_P.
896 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
897 * cfgexpand.c (avoid_type_punning_on_regs): New.
898 (discover_nonconstant_array_refs): Call
899 avoid_type_punning_on_regs to avoid unsupported mode punning.
901 2020-05-07 Alex Coplan <alex.coplan@arm.com>
903 * config/arm/arm.c (arm_add_stmt_cost): Fix declaration, remove class
906 2020-05-07 Richard Biener <rguenther@suse.de>
908 PR tree-optimization/57359
909 * tree-ssa-loop-im.c (im_mem_ref::indep_loop): Remove.
910 (in_mem_ref::dep_loop): Repurpose.
911 (LOOP_DEP_BIT): Remove.
912 (enum dep_kind): New.
913 (enum dep_state): Likewise.
914 (record_loop_dependence): New function to populate the
916 (query_loop_dependence): New function to query the dependence
918 (memory_accesses::refs_in_loop): Rename to ...
919 (memory_accesses::refs_loaded_in_loop): ... this and change to
921 (outermost_indep_loop): Adjust.
922 (mem_ref_alloc): Likewise.
923 (gather_mem_refs_stmt): Likewise.
924 (mem_refs_may_alias_p): Add tbaa_p parameter and pass it down.
925 (struct sm_aux): New.
926 (execute_sm): Split code generation on exits, record state
929 (execute_sm_exit): Exit code generation part.
930 (sm_seq_push_down): Helper for sm_seq_valid_bb performing
931 dependence checking on stores reached from exits.
932 (sm_seq_valid_bb): New function gathering SM stores on exits.
933 (hoist_memory_references): Re-implement.
934 (refs_independent_p): Add tbaa_p parameter and pass it down.
935 (record_dep_loop): Remove.
936 (ref_indep_loop_p_1): Fold into ...
937 (ref_indep_loop_p): ... this and generalize for three kinds
938 of dependence queries.
939 (can_sm_ref_p): Adjust according to hoist_memory_references
941 (store_motion_loop): Don't do anything if the set of SM
943 (tree_ssa_lim_initialize): Adjust.
944 (tree_ssa_lim_finalize): Likewise.
946 2020-05-07 Eric Botcazou <ebotcazou@adacore.com>
947 Pierre-Marie de Rodat <derodat@adacore.com>
949 * dwarf2out.c (add_data_member_location_attribute): Take into account
950 the variant part offset in the computation of the data bit offset.
951 (add_bit_offset_attribute): Remove CTX parameter. Pass a new context
952 in the call to field_byte_offset.
953 (gen_field_die): Adjust call to add_bit_offset_attribute and remove
955 (analyze_variant_discr): Deal with boolean subtypes.
957 2020-05-07 Martin Liska <mliska@suse.cz>
959 * lto-wrapper.c: Split arguments of MAKE environment
962 2020-05-07 Uroš Bizjak <ubizjak@gmail.com>
964 * config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use
965 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
966 fenv_var and new_fenv_var.
968 2020-05-06 Jakub Jelinek <jakub@redhat.com>
971 * config/i386/subst.md (store_mask_constraint, store_mask_predicate):
973 (avx512dq_vextract<shuffletype>64x2_1_maskm,
974 avx512f_vextract<shuffletype>32x4_1_maskm,
975 vec_extract_lo_<mode>_maskm, vec_extract_hi_<mode>_maskm): Remove.
976 (<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>): Split
978 (*avx512dq_vextract<shuffletype>64x2_1,
979 avx512dq_vextract<shuffletype>64x2_1_mask): ... these new
980 define_insns. Even in the masked variant allow memory output but in
981 that case use 0 rather than 0C constraint on the source of masked-out
983 (<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>): Split
985 (*avx512f_vextract<shuffletype>32x4_1,
986 avx512f_vextract<shuffletype>32x4_1_mask): ... these new define_insns.
987 Even in the masked variant allow memory output but in that case use
988 0 rather than 0C constraint on the source of masked-out elts.
989 (vec_extract_lo_<mode><mask_name>): Split into ...
990 (vec_extract_lo_<mode>, vec_extract_lo_<mode>_mask): ... these new
991 define_insns. Even in the masked variant allow memory output but in
992 that case use 0 rather than 0C constraint on the source of masked-out
994 (vec_extract_hi_<mode><mask_name>): Split into ...
995 (vec_extract_hi_<mode>, vec_extract_hi_<mode>_mask): ... these new
996 define_insns. Even in the masked variant allow memory output but in
997 that case use 0 rather than 0C constraint on the source of masked-out
1000 2020-05-06 qing zhao <qing.zhao@oracle.com>
1003 * common.opt: Add -flarge-source-files.
1004 * doc/invoke.texi: Document it.
1005 * toplev.c (process_options): set line_table->default_range_bits
1006 to 0 when flag_large_source_files is true.
1008 2020-05-06 Uroš Bizjak <ubizjak@gmail.com>
1011 * config/i386/predicates.md (add_comparison_operator): New predicate.
1012 * config/i386/i386.md (compare->add splitter): New splitters.
1014 2020-05-06 Richard Biener <rguenther@suse.de>
1016 * tree-vectorizer.h (vect_transform_slp_perm_load): Adjust.
1017 * tree-vect-data-refs.c (vect_slp_analyze_node_dependences):
1018 Remove slp_instance parameter, just iterate over all scalar stmts.
1019 (vect_slp_analyze_instance_dependence): Adjust and likewise.
1020 * tree-vect-slp.c (vect_bb_slp_scalar_cost): Remove unused BB
1022 (vect_schedule_slp): Just iterate over all scalar stmts.
1023 (vect_supported_load_permutation_p): Adjust.
1024 (vect_transform_slp_perm_load): Remove slp_instance parameter,
1025 instead use the number of lanes in the node as group size.
1026 * tree-vect-stmts.c (vect_model_load_cost): Get vectorization
1027 factor instead of slp_instance as parameter.
1028 (vectorizable_load): Adjust.
1030 2020-05-06 Andreas Schwab <schwab@suse.de>
1032 * config/aarch64/driver-aarch64.c: Include "aarch64-protos.h".
1033 (aarch64_get_extension_string_for_isa_flags): Don't declare.
1035 2020-05-06 Richard Biener <rguenther@suse.de>
1038 * cfgloopmanip.c (create_preheader): Require non-complex
1039 preheader edge for CP_SIMPLE_PREHEADERS.
1041 2020-05-06 Richard Biener <rguenther@suse.de>
1043 PR tree-optimization/94963
1044 * tree-ssa-loop-im.c (execute_sm_if_changed): Remove
1045 no-warning marking of the conditional store.
1046 (execute_sm): Instead mark the uninitialized state
1047 on loop entry to be not warned about.
1049 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
1051 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET,
1052 OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros.
1053 * config.gcc: Add tsxldtrkintrin.h to extra_headers.
1054 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
1056 * config/i386/i386-builtin.def: Add new builtins.
1057 * config/i386/i386-c.c (ix86_target_macros_internal): Define
1059 * config/i386/i386-options.c (ix86_target_string): Add
1061 (ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk.
1062 * config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P):
1064 * config/i386/i386.md (define_c_enum "unspec"): Add
1065 UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK.
1066 (TSXLDTRK): New define_int_iterator.
1067 ("<tsxldtrk>"): New define_insn.
1068 * config/i386/i386.opt: Add -mtsxldtrk.
1069 * config/i386/immintrin.h: Include tsxldtrkintrin.h.
1070 * config/i386/tsxldtrkintrin.h: New.
1071 * doc/invoke.texi: Document -mtsxldtrk.
1073 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1075 PR tree-optimization/94921
1076 * match.pd (~(~X - Y) -> X + Y, ~(~X + Y) -> X - Y): New
1079 2020-05-06 Richard Biener <rguenther@suse.de>
1081 PR tree-optimization/94965
1082 * tree-vect-stmts.c (vectorizable_load): Fix typo.
1084 2020-05-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1086 * doc/install.texi: Replace Sun with Solaris as appropriate.
1087 (Tools/packages necessary for building GCC, Perl version between
1088 5.6.1 and 5.6.24): Remove Solaris 8 reference.
1089 (Installing GCC: Binaries, Solaris 2 (SPARC, Intel)): Remove
1091 (Specific, i?86-*-solaris2*): Update version references for
1092 Solaris 11.3 and later. Remove gas 2.26 caveat.
1093 (Specific, *-*-solaris2*): Update version references for
1094 Solaris 11.3 and later. Remove boehm-gc reference.
1095 Document GMP, MPFR caveats on Solaris 11.3.
1096 (Specific, sparc-sun-solaris2*): Update Solaris 9 references.
1097 (Specific, sparc64-*-solaris2*): Likewise.
1098 Document --build requirement.
1100 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1103 * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use
1104 TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags.
1106 PR rtl-optimization/94873
1107 * combine.c (combine_instructions): Don't optimize using REG_EQUAL
1108 note if SET_SRC (set) has side-effects.
1110 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
1111 Wei Xiao <wei3.xiao@intel.com>
1113 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
1114 OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
1115 (ix86_handle_option): Handle -mserialize.
1116 * config.gcc (serializeintrin.h): New header file.
1117 * config/i386/cpuid.h (bit_SERIALIZE): New bit.
1118 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
1120 * config/i386/i386-builtin.def: Add new builtin.
1121 * config/i386/i386-c.c (__SERIALIZE__): New macro.
1122 * config/i386/i386-options.c (ix86_target_opts_isa2_opts):
1124 * (ix86_valid_target_attribute_inner_p): Add target attribute
1126 * config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):
1128 * config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.
1129 (serialize): New define_insn.
1130 * config/i386/i386.opt (mserialize): New option
1131 * config/i386/immintrin.h: Include serailizeintrin.h.
1132 * config/i386/serializeintrin.h: New header file.
1133 * doc/invoke.texi: Add documents for -mserialize.
1135 2020-05-06 Richard Biener <rguenther@suse.de>
1137 * tree-cfg.c (verify_gimple_assign_unary): Adjust integer
1138 to/from pointer conversion checking.
1140 2020-05-05 Michael Meissner <meissner@linux.ibm.com>
1142 * config/rs6000/rs6000-builtin.def: Delete changes meant for a
1144 * config/rs6000/rs6000-c.c: Likewise.
1145 * config/rs6000/rs6000-call.c: Likewise.
1146 * config/rs6000/rs6000.c: Likewise.
1148 2020-05-05 Sebastian Huber <sebastian.huber@embedded-brains.de>
1150 * config/rtems.h (RTEMS_STARTFILE_SPEC): Define if undefined.
1151 (RTEMS_ENDFILE_SPEC): Likewise.
1152 (STARTFILE_SPEC): Update comment. Add RTEMS_STARTFILE_SPEC.
1153 (ENDFILE_SPEC): Add RTEMS_ENDFILE_SPEC.
1154 (LIB_SPECS): Support -nodefaultlibs option.
1155 * config/or1k/rtems.h (RTEMS_STARTFILE_SPEC): Define.
1156 (RTEMS_ENDFILE_SPEC): Likewise.
1157 * config/rs6000/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
1158 (RTEMS_ENDFILE_SPEC): Likewise.
1159 * config/v850/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
1160 (RTEMS_ENDFILE_SPEC): Likewise.
1162 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1164 * config/pru/pru.c (pru_hard_regno_call_part_clobbered): Remove.
1165 (TARGET_HARD_REGNO_CALL_PART_CLOBBERED): Remove.
1167 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1169 * config/pru/pru.h: Mark R3.w0 as caller saved.
1171 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1173 * config/pru/pru.c (pru_emit_doloop): Use new gen_doloop_end_internal
1174 and gen_doloop_begin_internal.
1175 (pru_reorg_loop): Use gen_pruloop with mode.
1176 * config/pru/pru.md: Use new @insn syntax.
1178 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1180 * config/pru/pru.c (pru_print_operand): Fix fall through comment.
1182 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
1184 * config/i386/i386.md (fixuns_trunc<mode>si2): Use
1185 "clobber (scratch:M)" instad of "clobber (match_scratch:M N)".
1186 (addqi3_cconly_overflow): Ditto.
1187 (umulv<mode>4): Ditto.
1188 (<s>mul<mode>3_highpart): Ditto.
1189 (tls_global_dynamic_32): Ditto.
1190 (tls_local_dynamic_base_32): Ditto.
1197 (*adddi_4): Remove "m" constraint from scratch operand.
1198 (*add<mode>_4): Ditto.
1200 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1202 PR rtl-optimization/94516
1203 * postreload.c (reload_cse_simplify): When replacing sp = sp + const
1204 with sp = reg, add REG_EQUAL note with sp + const.
1205 * combine-stack-adj.c (try_apply_stack_adjustment): Change return
1206 type from int to bool. Add LIVE and OTHER_INSN arguments. Undo
1207 postreload sp = sp + const to sp = reg optimization if needed and
1209 (combine_stack_adjustments_for_block): Add LIVE argument. Handle
1210 reg = sp insn with sp + const REG_EQUAL note. Adjust
1211 try_apply_stack_adjustment caller, call
1212 df_simulate_initialize_forwards and df_simulate_one_insn_forwards.
1213 (combine_stack_adjustments): Allocate and free LIVE bitmap,
1214 adjust combine_stack_adjustments_for_block caller.
1216 2020-05-05 Martin Liska <mliska@suse.cz>
1218 PR gcov-profile/93623
1219 * tree-cfg.c (stmt_can_terminate_bb_p): Update comment to reflect
1222 2020-05-05 Martin Liska <mliska@suse.cz>
1224 * opt-functions.awk (opt_args_non_empty): New function.
1225 * opt-read.awk: Use the function for various option arguments.
1227 2020-05-05 Martin Liska <mliska@suse.cz>
1230 * lto-wrapper.c (run_gcc): When using -flto=jobserver,
1231 report warning when the jobserver is not detected.
1233 2020-05-05 Martin Liska <mliska@suse.cz>
1235 PR gcov-profile/94636
1236 * gcov.c (main): Print total lines summary at the end.
1237 (generate_results): Expect file_name always being non-null.
1238 Print newline after intermediate file is printed in order to align with
1239 what we do for normal files.
1241 2020-05-05 Martin Liska <mliska@suse.cz>
1243 * dumpfile.c (dump_switch_p): Change return type
1244 and print option suggestion.
1245 * dumpfile.h: Change return type.
1246 * opts-global.c (handle_common_deferred_options):
1247 Move error into dump_switch_p function.
1249 2020-05-05 Martin Liska <mliska@suse.cz>
1252 * alloc-pool.h: Use const for some arguments.
1253 * bitmap.h: Likewise.
1254 * mem-stats.h: Likewise.
1255 * sese.h (get_entry_bb): Likewise.
1256 (get_exit_bb): Likewise.
1258 2020-05-05 Richard Biener <rguenther@suse.de>
1260 * tree-vect-slp.c (struct vdhs_data): New.
1261 (vect_detect_hybrid_slp): New walker.
1262 (vect_detect_hybrid_slp): Rewrite.
1264 2020-05-05 Richard Biener <rguenther@suse.de>
1267 * tree-ssa-structalias.c (ipa_pta_execute): Use
1268 varpool_node::externally_visible_p ().
1269 (refered_from_nonlocal_var): Likewise.
1271 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
1273 * gcc.c (LTO_PLUGIN_SPEC): Define if not already.
1274 (LINK_PLUGIN_SPEC): Execute LTO_PLUGIN_SPEC.
1275 * config/vxworks.h (LTO_PLUGIN_SPEC): Define.
1277 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
1279 * gimplify.c (gimplify_init_constructor): Do not put the constructor
1280 into static memory if it is not complete.
1282 2020-05-05 Richard Biener <rguenther@suse.de>
1284 PR tree-optimization/94949
1285 * tree-ssa-loop-im.c (execute_sm): Check whether we use
1286 the multithreaded model or always compute the stored value
1287 before eliding a load.
1289 2020-05-05 Alex Coplan <alex.coplan@arm.com>
1291 * config/aarch64/aarch64.md (*one_cmpl_zero_extend): New.
1293 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1295 PR tree-optimization/94800
1296 * match.pd (X + (X << C) to X * (1 + (1 << C)),
1297 (X << C1) + (X << C2) to X * ((1 << C1) + (1 << C2))): New
1301 * config/i386/mmx.md (*vec_dupv4hi): Use xYw constraints instead of Yv.
1303 PR tree-optimization/94914
1304 * match.pd ((((type)A * B) >> prec) != 0 to .MUL_OVERFLOW(A, B) != 0):
1307 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
1309 * config/i386/i386.md (*testqi_ext_3): Use
1310 int_nonimmediate_operand instead of manual mode checks.
1311 (*x86_mov<SWI48:mode>cc_0_m1_neg_leu<SWI:mode>):
1312 Use int_nonimmediate_operand predicate. Rewrite
1313 define_insn_and_split pattern to a combine pass splitter.
1315 2020-05-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1317 * configure.ac <i[34567]86-*-*>: Add --32 to tls_as_opt on Solaris.
1318 * configure: Regenerate.
1320 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1323 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
1324 ssse3_ph<plusminus_mnemonic>wv8hi3, ssse3_ph<plusminus_mnemonic>wv4hi3,
1325 avx2_ph<plusminus_mnemonic>dv8si3, ssse3_ph<plusminus_mnemonic>dv4si3,
1326 ssse3_ph<plusminus_mnemonic>dv2si3): Simplify RTL patterns.
1328 2020-05-04 Clement Chigot <clement.chigot@atos.net>
1329 David Edelsohn <dje.gcc@gmail.com>
1331 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Override explicit
1332 for fmodl, frexpl, ldexpl and modfl builtins.
1334 2020-05-04 Richard Sandiford <richard.sandiford@arm.com>
1337 * internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the
1338 chosen lhs is different from the gcall lhs.
1339 (expand_mask_load_optab_fn): Likewise.
1340 (expand_gather_load_optab_fn): Likewise.
1342 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
1345 * config/i386/i386.md (*neg<mode>_ccc): New insn pattern.
1346 (EQ compare->LTU compare splitter): New splitter.
1347 (NE compare->NEG splitter): Ditto.
1349 2020-05-04 Marek Polacek <polacek@redhat.com>
1352 2020-04-30 Marek Polacek <polacek@redhat.com>
1355 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
1356 (check_aligned_type): Check if TYPE_USER_ALIGN match.
1358 2020-05-04 Richard Biener <rguenther@suse.de>
1360 PR tree-optimization/93891
1361 * tree-ssa-sccvn.c (vn_reference_lookup_3): Fall back to
1362 the original reference tree for assessing access alignment.
1364 2020-05-04 Richard Biener <rguenther@suse.de>
1366 PR tree-optimization/39612
1367 * tree-ssa-loop-im.c (im_mem_ref::loaded): New member.
1368 (set_ref_loaded_in_loop): New.
1369 (mark_ref_loaded): Likewise.
1370 (gather_mem_refs_stmt): Call mark_ref_loaded for loads.
1371 (execute_sm): Avoid issueing a load when it was not there.
1372 (execute_sm_if_changed): Avoid issueing warnings for the
1375 2020-05-04 Martin Jambor <mjambor@suse.cz>
1378 * tree-inline.c (tree_function_versioning): Leave any type conversion
1379 of replacements to setup_one_parameter and its friend
1380 force_value_to_type.
1382 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
1385 * config/i386/predicates.md (shr_comparison_operator): New predicate.
1386 * config/i386/i386.md (compare->shr splitter): New splitters.
1388 2020-05-04 Jakub Jelinek <jakub@redhat.com>
1390 PR tree-optimization/94718
1391 * match.pd ((X < 0) != (Y < 0) into (X ^ Y) < 0): New simplification.
1393 PR tree-optimization/94718
1394 * match.pd (bitop (convert @0) (convert? @1)): For GIMPLE, if we can,
1395 replace two nop conversions on bit_{and,ior,xor} argument
1396 and result with just one conversion on the result or another argument.
1398 PR tree-optimization/94718
1399 * fold-const.c (fold_binary_loc): Move (X & C) eqne (Y & C)
1400 -> (X ^ Y) & C eqne 0 optimization to ...
1401 * match.pd ((X & C) op (Y & C) into (X ^ Y) & C op 0): ... here.
1403 * opts.c (get_option_html_page): Instead of hardcoding a list of
1404 options common between C/C++ and Fortran only use gfortran/
1405 documentation for warnings that have CL_Fortran set but not
1408 2020-05-03 Uroš Bizjak <ubizjak@gmail.com>
1410 * config/i386/i386-expand.c (ix86_expand_int_movcc):
1411 Use plus_constant instead of gen_rtx_PLUS with GEN_INT.
1412 (emit_memmov): Ditto.
1413 (emit_memset): Ditto.
1414 (ix86_expand_strlensi_unroll_1): Ditto.
1415 (release_scratch_register_on_entry): Ditto.
1416 (gen_frame_set): Ditto.
1417 (ix86_emit_restore_reg_using_pop): Ditto.
1418 (ix86_emit_outlined_ms2sysv_restore): Ditto.
1419 (ix86_expand_epilogue): Ditto.
1420 (ix86_expand_split_stack_prologue): Ditto.
1421 * config/i386/i386.md (push immediate splitter): Ditto.
1425 2020-05-02 Iain Sandoe <iain@sandoe.co.uk>
1427 PR translation/93861
1428 * config/darwin-driver.c (darwin_driver_init): Adjust spelling in
1431 2020-05-02 Jakub Jelinek <jakub@redhat.com>
1433 * config/tilegx/tilegx.md
1434 (insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>): Use <I124MODE:n>
1435 rather than just <n>.
1437 2020-05-01 H.J. Lu <hongjiu.lu@intel.com>
1440 * cfgexpand.c (pass_expand::execute): Set crtl->patch_area_size
1441 and crtl->patch_area_entry.
1442 * emit-rtl.h (rtl_data): Add patch_area_size and patch_area_entry.
1443 * opts.c (common_handle_option): Limit
1444 function_entry_patch_area_size and function_entry_patch_area_start
1445 to USHRT_MAX. Fix a typo in error message.
1446 * varasm.c (assemble_start_function): Use crtl->patch_area_size
1447 and crtl->patch_area_entry.
1448 * doc/invoke.texi: Document the maximum value for
1449 -fpatchable-function-entry.
1451 2020-05-01 Iain Sandoe <iain@sandoe.co.uk>
1453 * config/i386/darwin.h: Repair SUBTARGET_INIT_BUILTINS.
1454 Override SUBTARGET_SHADOW_OFFSET macro.
1456 2020-05-01 Andreas Tobler <andreast@gcc.gnu.org>
1458 * config/i386/i386.h: Define a new macro: SUBTARGET_SHADOW_OFFSET.
1459 * config/i386/i386.c (ix86_asan_shadow_offset): Use this macro.
1460 * config/i386/darwin.h: Override the SUBTARGET_SHADOW_OFFSET macro.
1461 * config/i386/freebsd.h: Likewise.
1462 * config/freebsd.h (LIBASAN_EARLY_SPEC): Define.
1463 LIBTSAN_EARLY_SPEC): Likewise. (LIBLSAN_EARLY_SPEC): Likewise.
1465 2020-04-30 Alexandre Oliva <oliva@adacore.com>
1467 * doc/sourcebuild.texi (Effective-Target Keywords): Document
1468 the newly-introduced fileio effective target.
1470 2020-04-30 Richard Sandiford <richard.sandiford@arm.com>
1472 PR rtl-optimization/94740
1473 * cse.c (cse_process_notes_1): Replace with...
1474 (cse_process_note_1): ...this new function, acting as a
1475 simplify_replace_fn_rtx callback to process_note. Handle only
1476 REGs and MEMs directly. Validate the MEM if cse_process_note
1477 changes its address.
1478 (cse_process_notes): Replace with...
1479 (cse_process_note): ...this new function.
1480 (cse_extended_basic_block): Update accordingly, iterating over
1481 the register notes and passing individual notes to cse_process_note.
1483 2020-04-30 Carl Love <cel@us.ibm.com>
1485 * config/rs6000/emmintrin.h (_mm_movemask_epi8): Fix comment.
1487 2020-04-30 Martin Jambor <mjambor@suse.cz>
1490 * cgraph.c (clone_of_p): Also consider thunks whih had their bodies
1491 saved by the inliner and thunks which had their call inlined.
1492 * ipa-inline-transform.c (save_inline_function_body): Fill in
1493 former_clone_of of new body holders.
1495 2020-04-30 Jakub Jelinek <jakub@redhat.com>
1497 * BASE-VER: Set to 11.0.0.
1499 2020-04-30 Jonathan Wakely <jwakely@redhat.com>
1501 * pretty-print.c (pp_take_prefix): Fix spelling in comment.
1503 2020-04-30 Marek Polacek <polacek@redhat.com>
1506 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
1507 (check_aligned_type): Check if TYPE_USER_ALIGN match.
1509 2020-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1511 * config/aarch64/aarch64.h (TARGET_OUTLINE_ATOMICS): Define.
1512 * config/aarch64/aarch64.opt (moutline-atomics): Change to Int variable.
1513 * doc/invoke.texi (moutline-atomics): Document as on by default.
1515 2020-04-30 Szabolcs Nagy <szabolcs.nagy@arm.com>
1518 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Remove
1519 the check for NOTE_INSN_DELETED_LABEL.
1521 2020-04-30 Jakub Jelinek <jakub@redhat.com>
1523 * configure.ac (--with-documentation-root-url,
1524 --with-changes-root-url): Diagnose URL not ending with /,
1525 use AC_DEFINE_UNQUOTED instead of AC_SUBST.
1526 * opts.h (get_changes_url): Remove.
1527 * opts.c (get_changes_url): Remove.
1528 * Makefile.in (CFLAGS-opts.o): Don't add -DDOCUMENTATION_ROOT_URL
1529 or -DCHANGES_ROOT_URL.
1530 * doc/install.texi (--with-documentation-root-url,
1531 --with-changes-root-url): Document.
1532 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Don't call
1533 get_changes_url and free, change url variable type to const char * and
1534 set it to CHANGES_ROOT_URL "gcc-10/changes.html#empty_base".
1535 * config/s390/s390.c (s390_function_arg_vector,
1536 s390_function_arg_float): Likewise.
1537 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
1539 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
1541 * config.in: Regenerate.
1542 * configure: Regenerate.
1544 2020-04-30 Christophe Lyon <christophe.lyon@linaro.org>
1547 * config/arm/arm.c (isr_attribute_args): Remove duplicate entries.
1549 2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
1551 * config/s390/constraints.md ("j>f", "jb4"): New constraints.
1552 * config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix
1554 * config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a
1556 ("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst.
1557 Change constraint for vlrl/vstrl to jb4.
1559 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1561 * var-tracking.c (vt_initialize): Move variables pre and post
1562 into inner block and initialize both in order to fix warning
1563 about uninitialized use. Remove unnecessary checks for
1564 frame_pointer_needed.
1566 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1568 * toplev.c (output_stack_usage_1): Ensure that first
1569 argument to fprintf is not null.
1571 2020-04-29 Jakub Jelinek <jakub@redhat.com>
1573 * configure.ac (-with-changes-root-url): New configure option,
1574 defaulting to https://gcc.gnu.org/.
1575 * Makefile.in (CFLAGS-opts.o): Define CHANGES_ROOT_URL for
1577 * pretty-print.c (get_end_url_string): New function.
1578 (pp_format): Handle %{ and %} for URLs.
1579 (pp_begin_url): Use pp_string instead of pp_printf.
1580 (pp_end_url): Use get_end_url_string.
1581 * opts.h (get_changes_url): Declare.
1582 * opts.c (get_changes_url): New function.
1583 * config/rs6000/rs6000-call.c: Include opts.h.
1584 (rs6000_discover_homogeneous_aggregate): Use %{in GCC 10.1%} instead
1585 of just in GCC 10.1 in diagnostics and add URL.
1586 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Likewise.
1587 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
1589 * config/s390/s390.c (s390_function_arg_vector,
1590 s390_function_arg_float): Likewise.
1591 * configure: Regenerated.
1594 * config/s390/s390.c (s390_function_arg_vector,
1595 s390_function_arg_float): Use DECL_FIELD_ABI_IGNORED instead of
1596 cxx17_empty_base_field_p. In -Wpsabi diagnostics use the type
1597 passed to the function rather than the type of the single element.
1598 Rename cxx17_empty_base_seen variable to empty_base_seen, change
1599 type to int, and adjust diagnostics depending on if the field
1600 has [[no_unique_attribute]] or not.
1603 * config/i386/avx512bwintrin.h (_mm512_alignr_epi8,
1604 _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands
1605 used in casts into parens.
1606 * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph,
1607 _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph,
1608 _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph,
1609 _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask,
1610 _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask,
1611 _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask,
1612 _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise.
1613 * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8,
1614 _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8,
1615 _mm256_mask_cmp_epu8_mask): Likewise.
1616 * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph,
1617 _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise.
1618 * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise.
1619 * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise.
1622 * config/i386/avx2intrin.h (_mm_mask_i32gather_pd,
1623 _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd,
1624 _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps,
1625 _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps,
1626 _mm256_mask_i64gather_ps, _mm_i32gather_epi64,
1627 _mm_mask_i32gather_epi64, _mm256_i32gather_epi64,
1628 _mm256_mask_i32gather_epi64, _mm_i64gather_epi64,
1629 _mm_mask_i64gather_epi64, _mm256_i64gather_epi64,
1630 _mm256_mask_i64gather_epi64, _mm_i32gather_epi32,
1631 _mm_mask_i32gather_epi32, _mm256_i32gather_epi32,
1632 _mm256_mask_i32gather_epi32, _mm_i64gather_epi32,
1633 _mm_mask_i64gather_epi32, _mm256_i64gather_epi32,
1634 _mm256_mask_i64gather_epi32): Surround macro parameter uses with
1636 (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd,
1637 _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps,
1638 _mm_i64gather_ps, _mm256_i64gather_ps): Likewise. Don't use
1639 as mask vector containing -1.0 or -1.0f elts, but instead vector
1640 with all bits set using _mm*_cmpeq_p? with zero operands.
1641 * config/i386/avx512fintrin.h (_mm512_i32gather_ps,
1642 _mm512_mask_i32gather_ps, _mm512_i32gather_pd,
1643 _mm512_mask_i32gather_pd, _mm512_i64gather_ps,
1644 _mm512_mask_i64gather_ps, _mm512_i64gather_pd,
1645 _mm512_mask_i64gather_pd, _mm512_i32gather_epi32,
1646 _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64,
1647 _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32,
1648 _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64,
1649 _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps,
1650 _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd,
1651 _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps,
1652 _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd,
1653 _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32,
1654 _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64,
1655 _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32,
1656 _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64,
1657 _mm512_mask_i64scatter_epi64): Surround macro parameter uses with
1659 * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd,
1660 _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd,
1661 _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd,
1662 _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd,
1663 _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd,
1664 _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd,
1665 _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd,
1666 _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd,
1667 _mm512_mask_prefetch_i64scatter_ps): Likewise.
1668 * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps,
1669 _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd,
1670 _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps,
1671 _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd,
1672 _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32,
1673 _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64,
1674 _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32,
1675 _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64,
1676 _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps,
1677 _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps,
1678 _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd,
1679 _mm_mask_i32scatter_pd, _mm256_i64scatter_ps,
1680 _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps,
1681 _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd,
1682 _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32,
1683 _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32,
1684 _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64,
1685 _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64,
1686 _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32,
1687 _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32,
1688 _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64,
1689 _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64,
1690 _mm_mask_i64scatter_epi64): Likewise.
1692 2020-04-29 Jeff Law <law@redhat.com>
1694 * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific
1695 division instructions are 4 bytes long.
1697 2020-04-29 Jakub Jelinek <jakub@redhat.com>
1700 * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use
1701 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
1702 fenv_var, fenv_clear and old_fenv variables. For fenv_addr
1703 take address of TARGET_EXPR of fenv_var with void_node initializer.
1706 2020-04-29 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1708 PR tree-optimization/94774
1709 * gimple-ssa-sprintf.c (try_substitute_return_value): Initialize
1712 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
1714 * calls.h (cxx17_empty_base_field_p): Turn into a function declaration.
1715 * calls.c (cxx17_empty_base_field_p): New function. Check
1716 DECL_ARTIFICIAL and RECORD_OR_UNION_TYPE_P in addition to the
1719 2020-04-29 H.J. Lu <hongjiu.lu@intel.com>
1722 * config/i386/i386-options.c (ix86_set_indirect_branch_type):
1723 Allow -fcf-protection with -mindirect-branch=thunk-extern and
1724 -mfunction-return=thunk-extern.
1725 * doc/invoke.texi: Update notes for -fcf-protection=branch with
1726 -mindirect-branch=thunk-extern and -mindirect-return=thunk-extern.
1728 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
1730 * doc/sourcebuild.texi: Add missing arm_arch_v8a_hard_ok anchor.
1732 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
1734 * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
1735 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
1736 fenv_var and new_fenv_var.
1738 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
1740 * doc/sourcebuild.texi (arm_arch_v8a_hard_ok): Document new
1741 effective-target keyword.
1742 (arm_arch_v8a_hard_multilib): Likewise.
1743 (arm_arch_v8a_hard): Document new dg-add-options keyword.
1744 * config/arm/arm.c (arm_return_in_memory): Note that the APCS
1745 code is deprecated and has not been updated to handle
1746 DECL_FIELD_ABI_IGNORED.
1747 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
1748 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
1749 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
1750 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
1751 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
1752 something actually is a HFA or HVA. Record whether we see a
1753 [[no_unique_address]] field that previous GCCs would not have
1754 ignored in this way.
1755 (aapcs_vfp_is_call_or_return_candidate): Update the calls to
1756 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
1757 [[no_unique_address]] case. Use TYPE_MAIN_VARIANT in the
1758 diagnostic messages.
1759 (arm_needs_doubleword_align): Add a comment explaining why we
1760 consider even zero-sized fields.
1762 2020-04-29 Richard Biener <rguenther@suse.de>
1763 Li Zekun <lizekun1@huawei.com>
1766 * tree.c (component_ref_size): Guard against error_mark_node
1767 DECL_INITIAL as it happens with LTO.
1769 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
1771 * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add a
1772 comment explaining why we consider even zero-sized fields.
1773 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
1774 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
1775 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
1776 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
1777 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
1778 something actually is a HFA or HVA. Record whether we see a
1779 [[no_unique_address]] field that previous GCCs would not have
1780 ignored in this way.
1781 (aarch64_vfp_is_call_or_return_candidate): Add a parameter to say
1782 whether diagnostics should be suppressed. Update the calls to
1783 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
1784 [[no_unique_address]] case.
1785 (aarch64_return_in_msb): Update call accordingly, never silencing
1787 (aarch64_function_value): Likewise.
1788 (aarch64_return_in_memory_1): Likewise.
1789 (aarch64_init_cumulative_args): Likewise.
1790 (aarch64_gimplify_va_arg_expr): Likewise.
1791 (aarch64_pass_by_reference_1): Take a CUMULATIVE_ARGS pointer and
1792 use it to decide whether arch64_vfp_is_call_or_return_candidate
1794 (aarch64_pass_by_reference): Update calls accordingly.
1795 (aarch64_vfp_is_call_candidate): Use the CUMULATIVE_ARGS argument
1796 to decide whether arch64_vfp_is_call_or_return_candidate should be
1799 2020-04-29 Haijian Zhang <z.zhanghaijian@huawei.com>
1802 * config/aarch64/aarch64-builtins.c
1803 (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of
1804 MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and
1807 2020-04-29 Thomas Schwinge <thomas@codesourcery.com>
1809 * configure.ac <$enable_offload_targets>: Do parsing as done
1811 * configure: Regenerate.
1813 * configure.ac <$enable_offload_targets>: 'amdgcn' is 'gcn'.
1814 * configure: Regenerate.
1817 * rtlanal.c (set_noop_p): Handle non-constant selectors.
1820 * common/config/gcn/gcn-common.c (gcn_except_unwind_info): New
1822 (TARGET_EXCEPT_UNWIND_INFO): Define.
1824 2020-04-29 Jakub Jelinek <jakub@redhat.com>
1827 * config/gcn/gcn.md (*mov<mode>_insn): Use
1828 'reg_overlap_mentioned_p' to check for overlap.
1831 * config/ia64/ia64.c (hfa_element_mode): Use DECL_FIELD_ABI_IGNORED
1832 instead of cxx17_empty_base_field_p.
1835 * tree-core.h (tree_decl_common): Note decl_flag_0 used for
1836 DECL_FIELD_ABI_IGNORED.
1837 * tree.h (DECL_FIELD_ABI_IGNORED): Define.
1838 * calls.h (cxx17_empty_base_field_p): Change into a temporary
1839 macro, check DECL_FIELD_ABI_IGNORED flag with no "no_unique_address"
1841 * calls.c (cxx17_empty_base_field_p): Remove.
1842 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Handle
1843 DECL_FIELD_ABI_IGNORED.
1844 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
1845 * lto-streamer-out.c (hash_tree): Likewise.
1846 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Rename
1847 cxx17_empty_base_seen to empty_base_seen, change type to int *,
1848 adjust recursive calls, use DECL_FIELD_ABI_IGNORED instead of
1849 cxx17_empty_base_field_p, if "no_unique_address" attribute is
1850 present, propagate that to the caller too.
1851 (rs6000_discover_homogeneous_aggregate): Adjust
1852 rs6000_aggregate_candidate caller, emit different diagnostics
1853 when c++17 empty base fields are present and when empty
1854 [[no_unique_address]] fields are present.
1855 * config/rs6000/rs6000.c (rs6000_special_round_type_align,
1856 darwin_rs6000_special_round_type_align): Skip DECL_FIELD_ABI_IGNORED
1859 2020-04-29 Richard Biener <rguenther@suse.de>
1861 * tree-ssa-loop-im.c (ref_always_accessed::operator ()):
1862 Just check whether the stmt stores.
1864 2020-04-28 Alexandre Oliva <oliva@adacore.com>
1867 * config/rs6000/rs6000.md (rs6000_mffsl): Copy result to
1868 output operand in emulation. Don't overwrite pseudos.
1870 2020-04-28 Jeff Law <law@redhat.com>
1872 * config/h8300/h8300.md (H8/SX mult patterns): All H8/SX specific
1873 multiply patterns are 4 bytes long.
1875 2020-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1877 * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option.
1878 * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option.
1880 2020-04-28 Matthew Malcomson <matthew.malcomson@arm.com>
1881 Jakub Jelinek <jakub@redhat.com>
1884 * config/arm/arm.c (aapcs_vfp_sub_candidate): Account for C++17 empty
1885 base class artificial fields.
1886 (aapcs_vfp_is_call_or_return_candidate): Warn when PCS ABI
1887 decision is different after this fix.
1889 2020-04-28 David Malcolm <dmalcolm@redhat.com>
1895 * doc/invoke.texi (Static Analyzer Options): Remove
1896 -Wanalyzer-use-of-uninitialized-value.
1897 (-Wno-analyzer-use-of-uninitialized-value): Remove item.
1899 2020-04-28 Jakub Jelinek <jakub@redhat.com>
1901 PR tree-optimization/94809
1902 * tree.c (build_call_expr_internal_loc_array): Call
1903 process_call_operands.
1905 2020-04-27 Anton Youdkevitch <anton.youdkevitch@bell-sw.com>
1907 * config/aarch64/aarch64-cores.def (thunderx3t110): Add the chip name.
1908 * config/aarch64/aarch64-tune.md: Regenerate.
1909 * config/aarch64/aarch64.c (thunderx3t110_addrcost_table): Define.
1910 (thunderx3t110_regmove_cost): Likewise.
1911 (thunderx3t110_vector_cost): Likewise.
1912 (thunderx3t110_prefetch_tune): Likewise.
1913 (thunderx3t110_tunings): Likewise.
1914 * config/aarch64/aarch64-cost-tables.h (thunderx3t110_extra_costs):
1916 * config/aarch64/thunderx3t110.md: New file.
1917 * config/aarch64/aarch64.md: Include thunderx3t110.md.
1918 * doc/invoke.texi (AArch64 options): Add thunderx3t110.
1920 2020-04-28 Jakub Jelinek <jakub@redhat.com>
1923 * config/s390/s390.c (s390_function_arg_vector,
1924 s390_function_arg_float): Emit -Wpsabi diagnostics if the ABI changed.
1926 2020-04-28 Richard Sandiford <richard.sandiford@arm.com>
1928 PR tree-optimization/94727
1929 * tree-vect-stmts.c (vect_is_simple_cond): If both comparison
1930 operands are invariant booleans, use the mask type associated with the
1931 STMT_VINFO_VECTYPE. Use !slp_node instead of !vectype to exclude SLP.
1932 (vectorizable_condition): Pass vectype unconditionally to
1933 vect_is_simple_cond.
1935 2020-04-27 Jakub Jelinek <jakub@redhat.com>
1938 * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use
1939 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
1940 sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var.
1942 2020-04-27 David Malcolm <dmalcolm@redhat.com>
1945 * configure.ac (DOCUMENTATION_ROOT_URL): Drop trailing "gcc/" from
1946 default value, so that it can by supplied by get_option_html_page.
1947 * configure: Regenerate.
1948 * opts.c: Include "selftest.h".
1949 (get_option_html_page): New function.
1950 (get_option_url): Use it. Reformat to place comments next to the
1951 expressions they refer to.
1952 (selftest::test_get_option_html_page): New.
1953 (selftest::opts_c_tests): New.
1954 * selftest-run-tests.c (selftest::run_tests): Call
1955 selftest::opts_c_tests.
1956 * selftest.h (selftest::opts_c_tests): New decl.
1958 2020-04-27 Richard Sandiford <richard.sandiford@arm.com>
1960 * config/arm/arm-builtins.c (arm_expand_builtin_args): Only apply
1961 UINTVAL to CONST_INTs.
1963 2020-04-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1965 * config/arm/constraints.md (e): Remove constraint.
1966 (Te): Define constraint.
1967 * config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in
1968 operand 0 from "e" to "Te".
1969 (vaddvaq_<supf><mode>): Likewise.
1970 (vaddvq_p_<supf><mode>): Likewise.
1971 (vmladavq_<supf><mode>): Likewise.
1972 (vmladavxq_s<mode>): Likewise.
1973 (vmlsdavq_s<mode>): Likewise.
1974 (vmlsdavxq_s<mode>): Likewise.
1975 (vaddvaq_p_<supf><mode>): Likewise.
1976 (vmladavaq_<supf><mode>): Likewise.
1977 (vmladavq_p_<supf><mode>): Likewise.
1978 (vmladavxq_p_s<mode>): Likewise.
1979 (vmlsdavq_p_s<mode>): Likewise.
1980 (vmlsdavxq_p_s<mode>): Likewise.
1981 (vmlsdavaxq_s<mode>): Likewise.
1982 (vmlsdavaq_s<mode>): Likewise.
1983 (vmladavaxq_s<mode>): Likewise.
1984 (vmladavaq_p_<supf><mode>): Likewise.
1985 (vmladavaxq_p_s<mode>): Likewise.
1986 (vmlsdavaq_p_s<mode>): Likewise.
1987 (vmlsdavaxq_p_s<mode>): Likewise.
1989 2020-04-27 Andre Vieira <andre.simoesdiasvieira@arm.com>
1991 * config/arm/arm.c (output_move_neon): Only get the first operand if
1994 2020-04-27 Felix Yang <felix.yang@huawei.com>
1996 PR tree-optimization/94784
1997 * tree-ssa-forwprop.c (simplify_vector_constructor): Flip the
1998 assert around so that it checks that the two vectors have equal
1999 TYPE_VECTOR_SUBPARTS and that converting the corresponding element
2000 types is a useless_type_conversion_p.
2002 2020-04-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
2005 * dwarf2cfi.c (struct GTY): Add ra_mangled.
2006 (cfi_row_equal_p): Check ra_mangled.
2007 (dwarf2out_frame_debug_cfa_window_save): Remove the argument,
2008 this only handles the sparc logic now.
2009 (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for
2010 the aarch64 specific logic.
2011 (dwarf2out_frame_debug): Update to use the new subroutines.
2012 (change_cfi_row): Check ra_mangled.
2014 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2017 * config/s390/s390.c (s390_function_arg_vector,
2018 s390_function_arg_float): Ignore cxx17_empty_base_field_p fields.
2020 2020-04-27 Jiufu Guo <guojiufu@cn.ibm.com>
2022 * common/config/rs6000/rs6000-common.c
2023 (rs6000_option_optimization_table) [OPT_LEVELS_ALL]: Remove turn off
2025 * config/rs6000/rs6000.c (rs6000_option_override_internal): Avoid to
2028 2020-04-27 Martin Liska <mliska@suse.cz>
2031 * cgraph.h (cgraph_node::can_remove_if_no_direct_calls_and_refs_p):
2032 Do not remove ifunc_resolvers in remove unreachable nodes in LTO.
2034 2020-04-27 Xiong Hu Luo <luoxhu@linux.ibm.com>
2037 * config/rs6000/rs6000-logue.c (frame_pointer_needed_indeed):
2039 (rs6000_emit_prologue_components):
2040 Check with frame_pointer_needed_indeed.
2041 (rs6000_emit_epilogue_components): Likewise.
2042 (rs6000_emit_prologue): Likewise.
2043 (rs6000_emit_epilogue): Set frame_pointer_needed_indeed.
2045 2020-04-25 David Edelsohn <dje.gcc@gmail.com>
2047 * config/rs6000/rs6000-logue.c (rs6000_stack_info): Don't push a
2048 stack frame when debugging and flag_compare_debug is enabled.
2050 2020-04-25 Michael Meissner <meissner@linux.ibm.com>
2052 * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to
2053 enable PC-relative addressing for -mcpu=future.
2054 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move
2055 after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS.
2056 * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined,
2057 suppress PC-relative addressing.
2058 (rs6000_option_override_internal): Split up error messages
2059 checking for -mprefixed and -mpcrel. Enable -mpcrel if the target
2062 2020-04-25 Jakub Jelinek <jakub@redhat.com>
2063 Richard Biener <rguenther@suse.de>
2065 PR tree-optimization/94734
2066 PR tree-optimization/89430
2067 * tree-ssa-phiopt.c: Include tree-eh.h.
2068 (cond_store_replacement): Return false if an automatic variable
2069 access could trap. If -fstore-data-races, don't return false
2070 just because an automatic variable is addressable.
2072 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2074 * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
2076 (add<mode>_sext_dup2_exec): Likewise.
2078 2020-04-24 Segher Boessenkool <segher@kernel.crashing.org>
2081 * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little
2082 endian byteshift_val calculation.
2084 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2086 * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
2088 2020-04-24 Richard Sandiford <richard.sandiford@arm.com>
2090 * config/aarch64/arm_sve.h: Add a comment.
2092 2020-04-24 Haijian Zhang <z.zhanghaijian@huawei.com>
2094 PR rtl-optimization/94708
2095 * combine.c (simplify_if_then_else): Add check for
2096 !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode).
2098 2020-04-23 Martin Sebor <msebor@redhat.com>
2101 * common.opt (-Wno-frame-larger-than): New option.
2102 (-Wno-larger-than, -Wno-stack-usage): Same.
2104 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
2106 * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands
2108 (mov<mode>_exec): Likewise.
2109 (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec.
2110 (<convop><mode><vndi>2_exec): Likewise.
2112 2019-04-23 Eric Botcazou <ebotcazou@adacore.com>
2114 PR tree-optimization/94717
2115 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one
2116 of the stores doesn't have the same landing pad number as the first.
2117 (coalesce_immediate_stores): Do not try to coalesce the store using
2118 bswap if it doesn't have the same landing pad number as the first.
2120 2020-04-23 Bill Schmidt <wschmidt@linux.ibm.com>
2122 * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
2123 Replace outdated link to ELFv2 ABI.
2125 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2128 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx
2132 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs
2133 temporarily with non-final second operand and updating it later,
2134 push COMPOUND_EXPRs into a vector and process it in reverse,
2135 creating COMPOUND_EXPRs with the final operands.
2137 2020-04-23 Szabolcs Nagy <szabolcs.nagy@arm.com>
2140 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap
2141 bti c and bti j handling.
2143 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
2144 Thomas Schwinge <thomas@codesourcery.com>
2148 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on
2149 t_async and the wait arguments.
2151 2020-04-23 Richard Sandiford <richard.sandiford@arm.com>
2153 PR tree-optimization/94727
2154 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when
2155 comparing invariant scalar booleans.
2157 2020-04-23 Matthew Malcomson <matthew.malcomson@arm.com>
2158 Jakub Jelinek <jakub@redhat.com>
2161 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17
2162 empty base class artificial fields.
2163 (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is
2164 different after this fix.
2166 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2169 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
2170 Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check
2171 if the same type has been diagnosed most recently already.
2173 2020-04-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2175 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's
2177 (__arm_vbicq_n_s16): Likewise.
2178 (__arm_vbicq_n_u32): Likewise.
2179 (__arm_vbicq_n_s32): Likewise.
2180 (__arm_vbicq): Likewise.
2181 (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype.
2182 (__arm_vbicq_n_s32): Likewise.
2183 (__arm_vbicq_n_u16): Likewise.
2184 (__arm_vbicq_n_u32): Likewise.
2185 (__arm_vdupq_m_n_s8): Likewise.
2186 (__arm_vdupq_m_n_s16): Likewise.
2187 (__arm_vdupq_m_n_s32): Likewise.
2188 (__arm_vdupq_m_n_u8): Likewise.
2189 (__arm_vdupq_m_n_u16): Likewise.
2190 (__arm_vdupq_m_n_u32): Likewise.
2191 (__arm_vdupq_m_n_f16): Likewise.
2192 (__arm_vdupq_m_n_f32): Likewise.
2193 (__arm_vldrhq_gather_offset_s16): Likewise.
2194 (__arm_vldrhq_gather_offset_s32): Likewise.
2195 (__arm_vldrhq_gather_offset_u16): Likewise.
2196 (__arm_vldrhq_gather_offset_u32): Likewise.
2197 (__arm_vldrhq_gather_offset_f16): Likewise.
2198 (__arm_vldrhq_gather_offset_z_s16): Likewise.
2199 (__arm_vldrhq_gather_offset_z_s32): Likewise.
2200 (__arm_vldrhq_gather_offset_z_u16): Likewise.
2201 (__arm_vldrhq_gather_offset_z_u32): Likewise.
2202 (__arm_vldrhq_gather_offset_z_f16): Likewise.
2203 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
2204 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
2205 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
2206 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
2207 (__arm_vldrhq_gather_shifted_offset_f16): Likewise.
2208 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
2209 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
2210 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
2211 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
2212 (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise.
2213 (__arm_vldrwq_gather_offset_s32): Likewise.
2214 (__arm_vldrwq_gather_offset_u32): Likewise.
2215 (__arm_vldrwq_gather_offset_f32): Likewise.
2216 (__arm_vldrwq_gather_offset_z_s32): Likewise.
2217 (__arm_vldrwq_gather_offset_z_u32): Likewise.
2218 (__arm_vldrwq_gather_offset_z_f32): Likewise.
2219 (__arm_vldrwq_gather_shifted_offset_s32): Likewise.
2220 (__arm_vldrwq_gather_shifted_offset_u32): Likewise.
2221 (__arm_vldrwq_gather_shifted_offset_f32): Likewise.
2222 (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise.
2223 (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise.
2224 (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise.
2225 (__arm_vdwdupq_x_n_u8): Likewise.
2226 (__arm_vdwdupq_x_n_u16): Likewise.
2227 (__arm_vdwdupq_x_n_u32): Likewise.
2228 (__arm_viwdupq_x_n_u8): Likewise.
2229 (__arm_viwdupq_x_n_u16): Likewise.
2230 (__arm_viwdupq_x_n_u32): Likewise.
2231 (__arm_vidupq_x_n_u8): Likewise.
2232 (__arm_vddupq_x_n_u8): Likewise.
2233 (__arm_vidupq_x_n_u16): Likewise.
2234 (__arm_vddupq_x_n_u16): Likewise.
2235 (__arm_vidupq_x_n_u32): Likewise.
2236 (__arm_vddupq_x_n_u32): Likewise.
2237 (__arm_vldrdq_gather_offset_s64): Likewise.
2238 (__arm_vldrdq_gather_offset_u64): Likewise.
2239 (__arm_vldrdq_gather_offset_z_s64): Likewise.
2240 (__arm_vldrdq_gather_offset_z_u64): Likewise.
2241 (__arm_vldrdq_gather_shifted_offset_s64): Likewise.
2242 (__arm_vldrdq_gather_shifted_offset_u64): Likewise.
2243 (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise.
2244 (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise.
2245 (__arm_vidupq_m_n_u8): Likewise.
2246 (__arm_vidupq_m_n_u16): Likewise.
2247 (__arm_vidupq_m_n_u32): Likewise.
2248 (__arm_vddupq_m_n_u8): Likewise.
2249 (__arm_vddupq_m_n_u16): Likewise.
2250 (__arm_vddupq_m_n_u32): Likewise.
2251 (__arm_vidupq_n_u16): Likewise.
2252 (__arm_vidupq_n_u32): Likewise.
2253 (__arm_vidupq_n_u8): Likewise.
2254 (__arm_vddupq_n_u16): Likewise.
2255 (__arm_vddupq_n_u32): Likewise.
2256 (__arm_vddupq_n_u8): Likewise.
2258 2020-04-23 Iain Buclaw <ibuclaw@gdcproject.org>
2260 * doc/install.texi (D-Specific Options): Document
2261 --enable-libphobos-checking and --with-libphobos-druntime-only.
2263 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2266 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add
2267 cxx17_empty_base_seen argument. Pass it to recursive calls.
2268 Ignore cxx17_empty_base_field_p fields after setting
2269 *cxx17_empty_base_seen to true.
2270 (rs6000_discover_homogeneous_aggregate): Adjust
2271 rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous
2272 aggregates with C++17 empty base fields.
2275 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
2276 if last_decl is error_mark_node or has such a TREE_TYPE.
2279 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
2280 if last_decl is error_mark_node or has such a TREE_TYPE.
2282 2020-04-22 Felix Yang <felix.yang@huawei.com>
2285 * config/aarch64/aarch64.h (TARGET_SVE):
2286 Add && !TARGET_GENERAL_REGS_ONLY.
2287 (TARGET_SVE2): Add && TARGET_SVE.
2288 (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3,
2289 TARGET_SVE2_SM4): Add && TARGET_SVE2.
2290 * config/aarch64/aarch64-sve-builtins.h
2291 (sve_switcher::m_old_general_regs_only): New member.
2292 * config/aarch64/aarch64-sve-builtins.cc (check_required_registers):
2294 (reported_missing_registers_p): New variable.
2295 (check_required_extensions): Call check_required_registers before
2296 return if all required extenstions are present.
2297 (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in
2298 m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in
2299 global_options.x_target_flags.
2300 (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in
2301 global_options.x_target_flags if m_old_general_regs_only is true.
2303 2020-04-22 Zackery Spytz <zspytz@gmail.com>
2305 * doc/extend.exi: Add "free" to list of other builtin functions
2308 2020-04-20 Aaron Sawdey <acsawdey@linux.ibm.com>
2311 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed"
2313 (store_quadpti): Ditto.
2314 (atomic_load<mode>): Do not swap doublewords if TARGET_PREFIXED as
2315 plq will be used and doesn't need it.
2316 (atomic_store<mode>): Ditto, for pstq.
2318 2020-04-22 Erick Ochoa <erick.ochoa@theobroma-systems.com>
2320 * doc/invoke.texi: Update flags turned on by -O3.
2322 2020-04-22 Jakub Jelinek <jakub@redhat.com>
2325 * config/ia64/ia64.c (hfa_element_mode): Ignore
2326 cxx17_empty_base_field_p fields.
2329 * calls.h (cxx17_empty_base_field_p): Declare.
2330 * calls.c (cxx17_empty_base_field_p): Define.
2332 2020-04-22 Christophe Lyon <christophe.lyon@linaro.org>
2334 * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document.
2336 2020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2337 Andre Vieira <andre.simoesdiasvieira@arm.com>
2338 Mihail Ionescu <mihail.ionescu@arm.com>
2340 * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
2341 * config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
2342 (ALL_QUIRKS): Add quirk_no_asmcpu.
2343 (cortex-m55): Define new cpu.
2344 * config/arm/arm-tables.opt: Regenerate.
2345 * config/arm/arm-tune.md: Likewise.
2346 * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
2348 2020-04-22 Richard Sandiford <richard.sandiford@arm.com>
2350 PR tree-optimization/94700
2351 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing
2352 an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures
2353 of similarly-structured but distinct vector types.
2355 2020-04-21 Martin Sebor <msebor@redhat.com>
2358 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct
2359 the computation of the lower bound of the source access size.
2360 (builtin_access::generic_overlap): Remove a hack for setting ranges
2363 2020-04-21 John David Anglin <danglin@gcc.gnu.org>
2365 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete.
2366 (ASM_WEAKEN_DECL): New define.
2367 (HAVE_GAS_WEAKREF): Undefine.
2369 2020-04-21 Richard Sandiford <richard.sandiford@arm.com>
2371 PR tree-optimization/94683
2372 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a
2373 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured
2374 but distinct vector types.
2376 2020-04-21 Jakub Jelinek <jakub@redhat.com>
2379 * stor-layout.c (place_field, finalize_record_size): Don't emit
2380 -Wpadded warning on TYPE_ARTIFICIAL rli->t.
2381 * ubsan.c (ubsan_get_type_descriptor_type,
2382 ubsan_get_source_location_type, ubsan_create_data): Set
2384 * asan.c (asan_global_struct): Likewise.
2386 2020-04-21 Duan bo <duanbo3@huawei.com>
2389 * config/aarch64/aarch64.c: Add an error message for option conflict.
2390 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is
2391 incompatible with -fpic, -fPIC and -mabi=ilp32.
2393 2020-04-21 Frederik Harwath <frederik@codesourcery.com>
2396 * omp-low.c (new_omp_context): Remove assignments to
2397 ctx->outer_reduction_clauses and ctx->local_reduction_clauses.
2399 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
2401 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
2402 ("popcountv2di2_vx"): Use simplify_gen_subreg.
2404 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
2407 * config/s390/s390-builtin-types.def: Add 3 new function modes.
2408 * config/s390/s390-builtins.def: Add mode dependent low-level
2409 builtin and map the overloaded builtins to these.
2410 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
2411 ("vsel<V_HW"): ... this and rewrite the pattern with bitops.
2413 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
2415 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo
2416 has a variable VF, prefer new_loop_vinfo if it is cheaper for the
2417 estimated VF and is no worse at double the estimated VF.
2419 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
2422 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix
2423 order of arguments to rtx_vector_builder.
2424 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise.
2425 When extending the trailing constants to a full vector, replace any
2426 variables with zeros.
2428 2020-04-20 Jan Hubicka <hubicka@ucw.cz>
2431 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local
2434 2020-04-20 Martin Liska <mliska@suse.cz>
2436 * symtab.c (symtab_node::dump_references): Add space after
2438 (symtab_node::dump_referring): Likewise.
2440 2020-04-18 Jeff Law <law@redhat.com>
2443 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking
2446 2020-04-18 Iain Buclaw <ibuclaw@gdcproject.org>
2448 * doc/sourcebuild.texi (Effective-Target Keywords, Environment
2449 attributes): Document d_runtime_has_std_library.
2451 2020-04-17 Jeff Law <law@redhat.com>
2453 PR rtl-optimization/90275
2454 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels
2455 when the destination has a REG_UNUSED note.
2457 2020-04-17 Tobias Burnus <tobias@codesourcery.com>
2460 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to
2463 2020-04-17 Richard Sandiford <richard.sandiford@arm.com>
2465 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function.
2466 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the
2467 cost of load and store insns if one loop iteration has enough scalar
2468 elements to use an Advanced SIMD LDP or STP.
2469 (aarch64_add_stmt_cost): Update call accordingly.
2471 2020-04-17 Jakub Jelinek <jakub@redhat.com>
2472 Jeff Law <law@redhat.com>
2475 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than
2476 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision,
2477 or pos + len >= 32, or pos + len is equal to operands[2] precision
2478 and operands[2] is not a register operand. During splitting perform
2479 SImode AND if operands[0] doesn't have CCZmode and pos + len is
2480 equal to mode precision.
2482 2020-04-17 Richard Biener <rguenther@suse.de>
2485 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate
2487 * dwarf2out.c (dw_val_equal_p): Fix pasto in
2488 dw_val_class_vms_delta comparison.
2489 * optabs.c (expand_binop_directly): Fix pasto in commutation
2491 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in
2494 2020-04-17 Jakub Jelinek <jakub@redhat.com>
2496 PR rtl-optimization/94618
2497 * cfgrtl.c (delete_insn_and_edges): Set purge not just when
2498 insn is the BB_END of its block, but also when it is only followed
2499 by DEBUG_INSNs in its block.
2501 PR tree-optimization/94621
2502 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN.
2503 Move id->adjust_array_error_bounds check first in the condition.
2505 2020-04-17 Martin Liska <mliska@suse.cz>
2506 Jonathan Yong <10walls@gmail.com>
2508 PR gcov-profile/94570
2509 * coverage.c (coverage_init): Use separator properly.
2511 2020-04-16 Peter Bergner <bergner@linux.ibm.com>
2513 PR rtl-optimization/93974
2514 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.
2515 (rs6000_cannot_substitute_mem_equiv_p): New function.
2517 2020-04-16 Martin Jambor <mjambor@suse.cz>
2520 * ipa-inline.h (ipa_saved_clone_sources): Declare.
2521 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable.
2522 (save_inline_function_body): Link the new body holder with the
2524 * cgraph.c: Include ipa-inline.h.
2525 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from
2526 the statement in ipa_saved_clone_sources.
2527 * cgraphunit.c: Include ipa-inline.h.
2528 (expand_all_functions): Free ipa_saved_clone_sources.
2530 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
2533 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
2534 the VNx16BI lowpart of the recursively-generated constant.
2536 2020-04-16 Martin Liska <mliska@suse.cz>
2537 Jakub Jelinek <jakub@redhat.com>
2540 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
2541 DECL_IS_REPLACEABLE_OPERATOR during cloning.
2542 * tree-ssa-dce.c (valid_new_delete_pair_p): New function.
2543 (propagate_necessity): Check operator names.
2545 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
2547 PR rtl-optimization/94605
2548 * early-remat.c (early_remat::process_block): Handle insns that
2549 set multiple candidate registers.
2550 2020-04-16 Jan Hubicka <hubicka@ucw.cz>
2552 PR gcov-profile/93401
2553 * common.opt (profile-prefix-path): New option.
2554 * coverae.c: Include diagnostics.h.
2555 (coverage_init): Strip profile prefix path.
2556 * doc/invoke.texi (-fprofile-prefix-path): Document.
2558 2020-04-16 Richard Biener <rguenther@suse.de>
2561 * expr.c (emit_move_multi_word): Do not generate code when
2562 the destination part is undefined_operand_subword_p.
2563 * lower-subreg.c (resolve_clobber): Look through a paradoxica
2566 2020-04-16 Martin Jambor <mjambor@suse.cz>
2568 PR tree-optimization/94598
2569 * tree-sra.c (verify_sra_access_forest): Fix verification of total
2570 scalarization accesses under access to one-element arrays.
2572 2020-04-16 Jakub Jelinek <jakub@redhat.com>
2575 * function.c (assign_parm_find_data_types): Add workaround for
2576 BROKEN_VALUE_INITIALIZATION compilers.
2578 2020-04-16 Richard Biener <rguenther@suse.de>
2580 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME
2583 2020-04-15 Uroš Bizjak <ubizjak@gmail.com>
2586 * config/i386/i386-builtin.def (__builtin_ia32_movq128):
2587 Require OPTION_MASK_ISA_SSE2.
2589 2020-04-15 Gustavo Romero <gromero@linux.ibm.com>
2592 * dumpfile.c (selftest::temp_dump_context::temp_dump_context):
2593 Don't construct a dump_context temporary to call static method.
2595 2020-04-15 Andrea Corallo <andrea.corallo@arm.com>
2597 * config/aarch64/falkor-tag-collision-avoidance.c
2598 (valid_src_p): Check for aarch64_address_info type before
2599 accessing base field.
2601 2020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
2603 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern.
2604 (V_sz_elem2): Remove unused mode attribute.
2606 2020-04-15 Matthew Malcomson <matthew.malcomson@arm.com>
2608 * config/arm/arm.md (arm_movdi): Disallow for MVE.
2610 2020-04-15 Richard Biener <rguenther@suse.de>
2613 * tree-ssa-alias.c (same_type_for_tbaa): Defer to
2614 alias_sets_conflict_p for pointers.
2616 2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
2619 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
2620 (extendhisi2_internal): Add %v1 before the load instructions.
2622 2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com>
2625 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to
2626 use PC-relative addressing for TLS references.
2628 2020-04-14 Martin Jambor <mjambor@suse.cz>
2631 * ipa-sra.c: Include internal-fn.h.
2632 (enum isra_scan_context): Update comment.
2633 (scan_function): Treat calls to internal_functions like loads or stores.
2635 2020-04-14 Yang Yang <yangyang305@huawei.com>
2637 PR tree-optimization/94574
2638 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
2639 whether a vector-insert is rewritable using a BIT_INSERT_EXPR.
2641 2020-04-14 H.J. Lu <hongjiu.lu@intel.com>
2644 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.
2646 2020-04-13 Martin Sebor <msebor@redhat.com>
2648 * doc/extend.texi (-Wall): Mention -Wformat-overflow and
2649 -Wformat-truncation. Move -Wzero-length-bounds last.
2650 (-Wrestrict): Document positive form of option enabled by -Wall.
2652 2020-04-13 Zachary Spytz <zspytz@gmail.com>
2654 * doc/extend.texi: Add realloc to list of built-in functions
2655 are recognized by the compiler.
2657 2020-04-13 H.J. Lu <hongjiu.lu@intel.com>
2660 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame
2661 pointer in word_mode for eh_return epilogues.
2663 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
2665 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to
2666 memory references in %B, %C and %D operand selectors when the inner
2667 operand is a post increment address.
2669 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
2671 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory
2672 reference by 4 bytes, and %D memory reference by 6 bytes.
2674 2020-04-11 Uroš Bizjak <ubizjak@gmail.com>
2677 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2
2678 condition for V4SI, V8HI and V16QI modes.
2680 2020-04-11 Jakub Jelinek <jakub@redhat.com>
2684 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on
2687 2020-04-10 Thomas Schwinge <thomas@codesourcery.com>
2691 * omp-general.c (oacc_verify_routine_clauses): Diagnose if
2692 "#pragma omp declare target" has also been applied.
2694 2020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com>
2696 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn
2697 when to emit the epilogue_helper insn.
2698 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the
2701 2020-04-09 Jakub Jelinek <jakub@redhat.com>
2704 * cselib.h (cselib_record_sp_cfa_base_equiv,
2705 cselib_sp_derived_value_p): Declare.
2706 * cselib.c (cselib_record_sp_cfa_base_equiv,
2707 cselib_sp_derived_value_p): New functions.
2708 * var-tracking.c (add_stores): Don't record MO_VAL_SET for
2709 cselib_sp_derived_value_p values.
2710 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the
2711 start of extended basic blocks other than the first one
2712 for !frame_pointer_needed functions.
2714 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
2716 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw)
2717 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw)
2718 (aarch64_sve2048_hw): Document.
2719 * config/aarch64/aarch64-protos.h
2720 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare.
2721 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
2722 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled.
2723 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New
2725 (find_type_suffix_for_scalar_type): Use it instead of comparing
2727 (function_resolver::infer_vector_or_tuple_type): Likewise.
2728 (function_resolver::require_vector_type): Likewise.
2729 (handle_arm_sve_vector_bits_attribute): New function.
2730 * config/aarch64/aarch64.c (pure_scalable_type_info): New class.
2731 (aarch64_attribute_table): Add arm_sve_vector_bits.
2732 (aarch64_return_in_memory_1):
2733 (pure_scalable_type_info::piece::get_rtx): New function.
2734 (pure_scalable_type_info::num_zr): Likewise.
2735 (pure_scalable_type_info::num_pr): Likewise.
2736 (pure_scalable_type_info::get_rtx): Likewise.
2737 (pure_scalable_type_info::analyze): Likewise.
2738 (pure_scalable_type_info::analyze_registers): Likewise.
2739 (pure_scalable_type_info::analyze_array): Likewise.
2740 (pure_scalable_type_info::analyze_record): Likewise.
2741 (pure_scalable_type_info::add_piece): Likewise.
2742 (aarch64_some_values_include_pst_objects_p): Likewise.
2743 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info
2744 to analyze whether the type is returned in SVE registers.
2745 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type
2746 is passed in SVE registers.
2747 (aarch64_pass_by_reference_1): New function, extracted from...
2748 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info
2749 to analyze whether the type is a pure scalable type and, if so,
2750 whether it should be passed by reference.
2751 (aarch64_return_in_msb): Return false for pure scalable types.
2752 (aarch64_function_value_1): Fold back into...
2753 (aarch64_function_value): ...this function. Use
2754 pure_scalable_type_info to analyze whether the type is a pure
2755 scalable type and, if so, which registers it should use. Handle
2756 types that include pure scalable types but are not themselves
2757 pure scalable types.
2758 (aarch64_return_in_memory_1): New function, split out from...
2759 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info
2760 to analyze whether the type is a pure scalable type and, if so,
2761 whether it should be returned by reference.
2762 (aarch64_layout_arg): Remove orig_mode argument. Use
2763 pure_scalable_type_info to analyze whether the type is a pure
2764 scalable type and, if so, which registers it should use. Handle
2765 types that include pure scalable types but are not themselves
2766 pure scalable types.
2767 (aarch64_function_arg): Update call accordingly.
2768 (aarch64_function_arg_advance): Likewise.
2769 (aarch64_pad_reg_upward): On big-endian targets, return false for
2770 pure scalable types that are smaller than 16 bytes.
2771 (aarch64_member_type_forces_blk): New function.
2772 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types.
2773 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that
2774 correspond to built-in SVE types. Do not rely on a vector mode
2775 if the type includes an pure scalable type. When returning true,
2776 assert that the mode is not an SVE mode.
2777 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE
2778 built-in types here. When returning true, assert that the type
2779 does not have an SVE mode.
2780 (aarch64_can_change_mode_class): Don't allow anything to change
2781 between a predicate mode and a non-predicate mode. Also don't
2782 allow changes between SVE vector modes and other modes that
2783 might be bigger than 128 bits.
2784 (aarch64_invalid_binary_op): Reject binary operations that mix
2785 SVE and GNU vector types.
2786 (TARGET_MEMBER_TYPE_FORCES_BLK): Define.
2788 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
2790 * config/aarch64/aarch64.c (aarch64_attribute_table): Add
2791 "SVE sizeless type".
2792 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless)
2793 (sizeless_type_p): New functions.
2794 (register_builtin_types): Apply make_type_sizeless to the type.
2795 (register_tuple_type): Likewise.
2796 (verify_type_context): Use sizeless_type_p instead of builin_type_p.
2798 2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
2800 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for
2803 2020-04-09 Martin Jambor <mjambor@suse.cz>
2804 Richard Biener <rguenther@suse.de>
2806 PR tree-optimization/94482
2807 * tree-sra.c (create_access_replacement): Dump new replacement with
2809 (sra_modify_expr): Fix handling of cases when the original EXPR writes
2810 to only part of the replacement.
2811 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
2812 the first operand of combinations into REAL/IMAGPART_EXPR and
2815 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
2817 * doc/sourcebuild.texi (check-function-bodies): Treat the third
2818 parameter as a list of option regexps and require each regexp
2821 2020-04-09 Andrea Corallo <andrea.corallo@arm.com>
2824 * config/aarch64/falkor-tag-collision-avoidance.c
2825 (valid_src_p): Fix missing rtx type check.
2827 2020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com>
2828 Richard Biener <rguenther@suse.de>
2830 PR tree-optimization/93674
2831 * tree-ssa-loop-ivopts.c (langhooks.h): New include.
2832 (add_iv_candidate_for_use): For iv_use of non integer or pointer type,
2833 or non-mode precision type, add candidate in unsigned type with the
2836 2020-04-08 Clement Chigot <clement.chigot@atos.net>
2838 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128.
2839 * config/rs6000/aix71.h (LIB_SPEC): Likewise.
2840 * config/rs6000/aix72.h (LIB_SPEC): Likewise.
2842 2020-04-08 Jakub Jelinek <jakub@redhat.com>
2845 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
2847 * reload1.c (eliminate_regs_1): Avoid creating
2848 (plus (reg) (const_int 0)) in DEBUG_INSNs.
2850 PR tree-optimization/94524
2851 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
2852 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
2853 op1 rather than op1 itself at the end. Punt for signed modulo by
2854 most negative constant.
2855 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
2856 modulo by most negative constant.
2858 2020-04-08 Richard Biener <rguenther@suse.de>
2860 PR rtl-optimization/93946
2861 * cse.c (cse_insn): Record the tabled expression in
2862 src_related. Verify a redundant store removal is valid.
2864 2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
2867 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert
2868 ENDBR at function entry if function will be called indirectly.
2870 2020-04-08 Jakub Jelinek <jakub@redhat.com>
2873 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
2876 2020-04-08 Martin Liska <mliska@suse.cz>
2879 * gimple.c (gimple_call_operator_delete_p): Rename to...
2880 (gimple_call_replaceable_operator_delete_p): ... this.
2881 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
2882 * gimple.h (gimple_call_operator_delete_p): Rename to ...
2883 (gimple_call_replaceable_operator_delete_p): ... this.
2884 * tree-core.h (tree_function_decl): Add replaceable_operator
2886 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1):
2887 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
2888 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p.
2889 (eliminate_unnecessary_stmts): Likewise.
2890 * tree-streamer-in.c (unpack_ts_function_decl_value_fields):
2891 Pack DECL_IS_REPLACEABLE_OPERATOR.
2892 * tree-streamer-out.c (pack_ts_function_decl_value_fields):
2893 Unpack the field here.
2894 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New.
2895 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New.
2896 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New.
2897 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable.
2898 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare
2899 replaceable operator flags.
2901 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
2902 Matthew Malcomson <matthew.malcomson@arm.com>
2904 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
2905 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
2906 (CX_TERNARY_QUALIFIERS): Likewise.
2907 (ARM_BUILTIN_CDE_PATTERN_START): Likewise.
2908 (ARM_BUILTIN_CDE_PATTERN_END): Likewise.
2909 (arm_init_acle_builtins): Initialize CDE builtins.
2910 (arm_expand_acle_builtin): Check CDE constant operands.
2911 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
2912 of CDE constant operand.
2913 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
2915 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
2916 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
2917 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
2918 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
2919 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
2920 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
2921 * config/arm/arm_cde_builtins.def: New file.
2922 * config/arm/iterators.md (V_reg): New attribute of SI.
2923 * config/arm/predicates.md (const_int_coproc_operand): New.
2924 (const_int_vcde1_operand, const_int_vcde2_operand): New.
2925 (const_int_vcde3_operand): New.
2926 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
2927 * config/arm/vfp.md (arm_vcx1<mode>): New entry.
2928 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
2929 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.
2931 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
2933 * config.gcc: Add arm_cde.h.
2934 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
2935 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
2936 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
2937 * config/arm/arm.c (arm_option_reconfigure_globals): Configure
2938 arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
2939 * config/arm/arm.h (TARGET_CDE): New macro.
2940 * config/arm/arm_cde.h: New file.
2941 * doc/invoke.texi: Document CDE options +cdecp[0-7].
2942 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
2944 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
2946 2020-04-08 Jakub Jelinek <jakub@redhat.com>
2948 PR rtl-optimization/94516
2949 * postreload.c: Include rtl-iter.h.
2950 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
2951 looking for all MEMs with RTX_AUTOINC operand.
2952 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.
2954 2020-04-08 Tobias Burnus <tobias@codesourcery.com>
2956 * omp-grid.c (grid_eliminate_combined_simd_part): Use
2957 OMP_CLAUSE_CODE to access the omp clause code.
2959 2020-04-07 Jeff Law <law@redhat.com>
2961 PR rtl-optimization/92264
2962 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when
2963 the destination is the stack pointer.
2965 2020-04-07 Jakub Jelinek <jakub@redhat.com>
2967 PR rtl-optimization/94291
2968 PR rtl-optimization/84169
2969 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST
2970 must be a REG or SUBREG of REG; if it is not one of these, don't
2973 2020-04-07 Richard Biener <rguenther@suse.de>
2976 * gimplify.c (gimplify_addr_expr): Also consider generated
2979 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
2981 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.
2983 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
2985 * config/arm/arm_mve.h: Cast some pointers to expected types.
2987 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
2989 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
2990 same with '__arm_' prefix.
2992 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
2994 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.
2996 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
2998 * config/arm/arm.c (arm_mve_immediate_check): Removed.
2999 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
3000 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
3001 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
3002 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
3003 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
3004 mve_vqshruntq_m_n_s*): Fixed immediate constraints.
3006 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3008 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
3010 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3012 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
3013 * config/arm/mve/md: Fix v[id]wdup patterns.
3015 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3017 * config/arm/arm.c (output_move_neon): Deal with label + offset cases.
3018 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
3020 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3022 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
3023 and remove const_ptr enums.
3025 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3027 * config/arm/arm_mve.h (vsubq_n): Merge with...
3029 (vmulq_n): Merge with...
3031 (__ARM_mve_typeid): Simplify scalar and constant detection.
3033 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3036 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
3037 for inter-lane permutation for 64-byte modes.
3040 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
3041 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
3042 Assume it is a REG after that instead of testing it and doing FAIL
3043 otherwise. Formatting fix.
3045 2020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
3047 * config/rs6000/t-rtems: Delete mcpu=8540 multilib.
3049 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3052 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
3053 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes.
3055 2020-04-06 Jakub Jelinek <jakub@redhat.com>
3057 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
3058 + const0_rtx return the SP_DERIVED_VALUE_P.
3060 2020-04-06 Richard Sandiford <richard.sandiford@arm.com>
3062 PR rtl-optimization/92989
3063 * lra-lives.c (process_bb_lives): Do not treat eh_return data
3064 registers as being live at the beginning of the EH receiver.
3066 2020-04-05 Zachary Spytz <zspytz@gmail.com>
3068 * extend.texi: Add free to list of ISO C90 functions that
3069 are recognized by the compiler.
3071 2020-04-05 Nagaraju Mekala <nmekala@xilix.com>
3073 * config/microblaze/microblaze.c (microblaze_must_save_register): Check
3076 * config/microblaze/microblaze.md (trap): Update output pattern.
3078 2020-04-04 Hannes Domani <ssbssa@yahoo.de>
3079 Jakub Jelinek <jakub@redhat.com>
3082 * dwarf2out.c (gen_subprogram_die): Look through references, pointers,
3083 arrays, pointer-to-members, function types and qualifiers when
3084 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
3085 to emit type again on definition.
3087 2020-04-04 Jan Hubicka <hubicka@ucw.cz>
3090 * ipa-fnsummary.c (vrp_will_run_p): New function.
3091 (fre_will_run_p): New function.
3092 (evaluate_properties_for_edge): Use it.
3093 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
3094 !optimize_debug to optimize_debug.
3096 2020-04-04 Jakub Jelinek <jakub@redhat.com>
3098 PR rtl-optimization/94468
3099 * cselib.c (references_value_p): Formatting fix.
3100 (cselib_useless_value_p): New function.
3101 (discard_useless_locs, discard_useless_values,
3102 cselib_invalidate_regno_val, cselib_invalidate_mem,
3103 cselib_record_set): Use it instead of
3104 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx).
3107 * tree-iterator.h (expr_single): Declare.
3108 * tree-iterator.c (expr_single): New function.
3109 * tree.h (protected_set_expr_location_if_unset): Declare.
3110 * tree.c (protected_set_expr_location): Use expr_single.
3111 (protected_set_expr_location_if_unset): New function.
3113 2020-04-03 Jeff Law <law@redhat.com>
3115 PR rtl-optimization/92264
3116 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle
3117 reloading of auto-increment addressing modes.
3119 2020-04-03 H.J. Lu <hongjiu.lu@intel.com>
3122 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand
3125 2020-04-03 Jeff Law <law@redhat.com>
3127 PR rtl-optimization/92264
3128 * config/m32r/m32r.c (m32r_output_block_move): Properly account for
3129 post-increment addressing of source operands as well as residuals
3130 when computing any adjustments to the input pointer.
3132 2020-04-03 Jakub Jelinek <jakub@redhat.com>
3135 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
3136 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
3137 second half of first lane from first lane of second operand and
3138 first half of second lane from second lane of first operand.
3140 2020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
3142 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE.
3144 2020-04-03 Tamar Christina <tamar.christina@arm.com>
3147 * common/config/aarch64/aarch64-common.c
3148 (aarch64_get_extension_string_for_isa_flags): Handle default flags.
3150 2020-04-03 Richard Biener <rguenther@suse.de>
3153 * tree.c (array_ref_low_bound): Deal with released SSA names
3156 2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com>
3158 * config/gcn/gcn.c (print_operand): Handle unordered comparison
3160 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered
3161 comparison operators.
3163 2020-04-03 Kewen Lin <linkw@gcc.gnu.org>
3165 PR tree-optimization/94443
3166 * tree-vect-loop.c (vectorizable_live_operation): Use
3167 gsi_insert_seq_before to replace gsi_insert_before.
3169 2020-04-03 Martin Liska <mliska@suse.cz>
3172 * ipa-icf-gimple.c (func_checker::compare_gimple_call):
3173 Compare type attributes for gimple_call_fntypes.
3175 2020-04-02 Sandra Loosemore <sandra@codesourcery.com>
3177 * alias.c (get_alias_set): Fix comment typos.
3179 2020-04-02 Fritz Reese <foreese@gcc.gnu.org>
3182 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
3183 attribute checking used by TYPE.
3185 2020-04-02 Martin Jambor <mjambor@suse.cz>
3188 * ipa-sra.c (struct caller_issues): New fields candidate and
3189 call_from_outside_comdat.
3190 (check_for_caller_issues): Check for calls from outsied of
3191 candidate's same_comdat_group.
3192 (check_all_callers_for_issues): Set up issues.candidate, check result
3194 (mark_callers_calls_comdat_local): New function.
3195 (process_isra_node_results): Set calls_comdat_local of callers if
3198 2020-04-02 Richard Biener <rguenther@suse.de>
3201 * common.opt (ffinite-loops): Initialize to zero.
3202 * opts.c (default_options_table): Remove OPT_ffinite_loops
3204 * cfgloop.h (loop::finite_p): New member.
3205 * cfgloopmanip.c (copy_loop_info): Copy finite_p.
3206 * ipa-icf-gimple.c (func_checker::compare_loops): Compare
3208 * lto-streamer-in.c (input_cfg): Stream finite_p.
3209 * lto-streamer-out.c (output_cfg): Likewise.
3210 * tree-cfg.c (replace_loop_annotate): Initialize finite_p
3211 from flag_finite_loops at CFG build time.
3212 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops
3213 finite_p flag instead of flag_finite_loops.
3214 * doc/invoke.texi (ffinite-loops): Adjust documentation of
3217 2020-04-02 Richard Biener <rguenther@suse.de>
3220 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting
3221 DW_TAG_imported_unit.
3223 2020-04-02 Maciej W. Rozycki <macro@wdc.com>
3225 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
3226 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
3229 2020-04-02 Kewen Lin <linkw@gcc.gnu.org>
3231 PR tree-optimization/94401
3232 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
3233 access type when loading halves of vector to avoid peeling for gaps.
3235 2020-04-02 Jakub Jelinek <jakub@redhat.com>
3237 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
3238 between a string literal and MIPS_SYSVERSION_SPEC macro.
3240 2020-04-02 Martin Jambor <mjambor@suse.cz>
3242 * doc/invoke.texi (Optimize Options): Document sra-max-propagations.
3244 2020-04-02 Jakub Jelinek <jakub@redhat.com>
3246 PR rtl-optimization/92264
3247 * params.opt (-param=max-find-base-term-values=): Decrease default
3250 PR rtl-optimization/92264
3251 * rtl.h (struct rtx_def): Mention that call bit is used as
3252 SP_DERIVED_VALUE_P in cselib.c.
3253 * cselib.c (SP_DERIVED_VALUE_P): Define.
3254 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
3255 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
3256 val_rtx and sp based expression where offsets cancel each other.
3257 (preserve_constants_and_equivs): Formatting fix.
3258 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
3259 locs list for cfa_base_preserved_val if needed. Formatting fix.
3260 (autoinc_split): If the to be returned value is a REG, MEM or
3261 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
3262 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
3263 (rtx_equal_for_cselib_1): Call autoinc_split even if both
3264 expressions are PLUS in Pmode with CONST_INT second operands.
3265 Handle SP_DERIVED_VALUE_P cases.
3266 (cselib_hash_plus_const_int): New function.
3267 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
3268 second operand, as well as for PRE_DEC etc. that ought to be
3269 hashed the same way.
3270 (cselib_subst_to_values): Substitute PLUS with Pmode and
3271 CONST_INT operand if the first operand is a VALUE which has
3272 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
3273 SP_DERIVED_VALUE_P + adjusted offset.
3274 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
3275 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding
3276 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
3277 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
3278 on the sp value before calling cselib_add_permanent_equiv on the
3280 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
3281 in the insn without REG_INC note.
3282 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
3283 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes.
3286 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
3287 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
3289 2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3292 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
3293 (LDRGBWBXU_Z_QUALIFIERS): Likewise.
3294 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
3295 intrinsic defintion by adding a new builtin call to writeback into base
3297 (__arm_vldrdq_gather_base_wb_u64): Likewise.
3298 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
3299 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
3300 (__arm_vldrwq_gather_base_wb_s32): Likewise.
3301 (__arm_vldrwq_gather_base_wb_u32): Likewise.
3302 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
3303 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
3304 (__arm_vldrwq_gather_base_wb_f32): Likewise.
3305 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
3306 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
3307 builtin's qualifier.
3308 (vldrdq_gather_base_wb_z_u): Likewise.
3309 (vldrwq_gather_base_wb_u): Likewise.
3310 (vldrdq_gather_base_wb_u): Likewise.
3311 (vldrwq_gather_base_wb_z_s): Likewise.
3312 (vldrwq_gather_base_wb_z_f): Likewise.
3313 (vldrdq_gather_base_wb_z_s): Likewise.
3314 (vldrwq_gather_base_wb_s): Likewise.
3315 (vldrwq_gather_base_wb_f): Likewise.
3316 (vldrdq_gather_base_wb_s): Likewise.
3317 (vldrwq_gather_base_nowb_z_u): Define builtin.
3318 (vldrdq_gather_base_nowb_z_u): Likewise.
3319 (vldrwq_gather_base_nowb_u): Likewise.
3320 (vldrdq_gather_base_nowb_u): Likewise.
3321 (vldrwq_gather_base_nowb_z_s): Likewise.
3322 (vldrwq_gather_base_nowb_z_f): Likewise.
3323 (vldrdq_gather_base_nowb_z_s): Likewise.
3324 (vldrwq_gather_base_nowb_s): Likewise.
3325 (vldrwq_gather_base_nowb_f): Likewise.
3326 (vldrdq_gather_base_nowb_s): Likewise.
3327 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
3329 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
3330 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
3331 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
3332 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
3333 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
3334 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
3335 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
3336 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
3337 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
3338 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
3339 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
3341 2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
3343 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
3344 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
3345 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
3346 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
3347 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
3348 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
3349 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
3350 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
3351 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
3353 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
3354 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
3355 Remove constraints from expander.
3356 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
3357 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
3358 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
3359 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
3360 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
3361 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
3363 2020-04-01 Peter Bergner <bergner@linux.ibm.com>
3365 PR rtl-optimization/94123
3366 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for
3367 flag_split_wide_types_early.
3369 2020-04-01 Joerg Sonnenberger <joerg@bec.de>
3371 * doc/extend.texi (Common Function Attributes): Fix typo.
3373 2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>
3376 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
3379 2020-04-01 Zackery Spytz <zspytz@gmail.com>
3381 * doc/extend.texi: Fix a typo in the documentation of the
3382 copy function attribute.
3384 2020-04-01 Jakub Jelinek <jakub@redhat.com>
3387 * tree-object-size.c (pass_object_sizes::execute): Don't call
3388 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
3389 call replace_call_with_value.
3391 2020-04-01 Kewen Lin <linkw@gcc.gnu.org>
3393 PR tree-optimization/94043
3394 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
3395 phi for vec_lhs and use it for lane extraction.
3397 2020-03-31 Felix Yang <felix.yang@huawei.com>
3399 PR tree-optimization/94398
3400 * tree-vect-stmts.c (vectorizable_store): Instead of calling
3401 vect_supportable_dr_alignment, set alignment_support_scheme to
3402 dr_unaligned_supported for gather-scatter accesses.
3403 (vectorizable_load): Likewise.
3405 2020-03-31 Andrew Stubbs <ams@codesourcery.com>
3407 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
3409 (vnsi, VnSI, vndi, VnDI): New mode attributes.
3410 (mov<mode>): Use <VnDI> in place of V64DI.
3411 (mov<mode>_exec): Likewise.
3412 (mov<mode>_sgprbase): Likewise.
3413 (reload_out<mode>): Likewise.
3414 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
3415 (gather_load<mode>v64si): Rename to ...
3416 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
3417 and <VnDI> in place of V64DI.
3418 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
3419 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
3420 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
3421 (scatter_store<mode>v64si): Rename to ...
3422 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
3423 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
3424 (scatter<mode>_insn_1offset<exec_scatter>): Likewise.
3425 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
3426 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
3427 (ds_bpermute<mode>): Use <VnSI>.
3428 (addv64si3_vcc<exec_vcc>): Rename to ...
3429 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
3430 (addv64si3_vcc_dup<exec_vcc>): Rename to ...
3431 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
3432 (addcv64si3<exec_vcc>): Rename to ...
3433 (addc<mode>3<exec_vcc>): ... this, and use V_SI.
3434 (subv64si3_vcc<exec_vcc>): Rename to ...
3435 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
3436 (subcv64si3<exec_vcc>): Rename to ...
3437 (subc<mode>3<exec_vcc>): ... this, and use V_SI.
3438 (addv64di3): Rename to ...
3439 (add<mode>3): ... this, and use V_DI.
3440 (addv64di3_exec): Rename to ...
3441 (add<mode>3_exec): ... this, and use V_DI.
3442 (subv64di3): Rename to ...
3443 (sub<mode>3): ... this, and use V_DI.
3444 (subv64di3_exec): Rename to ...
3445 (sub<mode>3_exec): ... this, and use V_DI.
3446 (addv64di3_zext): Rename to ...
3447 (add<mode>3_zext): ... this, and use V_DI and <VnSI>.
3448 (addv64di3_zext_exec): Rename to ...
3449 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
3450 (addv64di3_zext_dup): Rename to ...
3451 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
3452 (addv64di3_zext_dup_exec): Rename to ...
3453 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
3454 (addv64di3_zext_dup2): Rename to ...
3455 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
3456 (addv64di3_zext_dup2_exec): Rename to ...
3457 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
3458 (addv64di3_sext_dup2): Rename to ...
3459 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
3460 (addv64di3_sext_dup2_exec): Rename to ...
3461 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
3462 (<su>mulv64si3_highpart<exec>): Rename to ...
3463 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
3464 (mulv64di3): Rename to ...
3465 (mul<mode>3): ... this, and use V_DI and <VnSI>.
3466 (mulv64di3_exec): Rename to ...
3467 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
3468 (mulv64di3_zext): Rename to ...
3469 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
3470 (mulv64di3_zext_exec): Rename to ...
3471 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
3472 (mulv64di3_zext_dup2): Rename to ...
3473 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
3474 (mulv64di3_zext_dup2_exec): Rename to ...
3475 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
3476 (<expander>v64di3): Rename to ...
3477 (<expander><mode>3): ... this, and use V_DI and <VnSI>.
3478 (<expander>v64di3_exec): Rename to ...
3479 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
3480 (<expander>v64si3<exec>): Rename to ...
3481 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
3482 (v<expander>v64si3<exec>): Rename to ...
3483 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
3484 (<expander>v64si3<exec>): Rename to ...
3485 (<expander><vnsi>3<exec>): ... this, and use V_SI.
3486 (subv64df3<exec>): Rename to ...
3487 (sub<mode>3<exec>): ... this, and use V_DF.
3488 (truncv64di<mode>2): Rename to ...
3489 (trunc<vndi><mode>2): ... this, and use <VnDI>.
3490 (truncv64di<mode>2_exec): Rename to ...
3491 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
3492 (<convop><mode>v64di2): Rename to ...
3493 (<convop><mode><vndi>2): ... this, and use <VnDI>.
3494 (<convop><mode>v64di2_exec): Rename to ...
3495 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
3496 (vec_cmp<u>v64qidi): Rename to ...
3497 (vec_cmp<u><mode>di): ... this, and use <VnSI>.
3498 (vec_cmp<u>v64qidi_exec): Rename to ...
3499 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
3500 (vcond_mask_<mode>di): Use <VnDI>.
3501 (maskload<mode>di): Likewise.
3502 (maskstore<mode>di): Likewise.
3503 (mask_gather_load<mode>v64si): Rename to ...
3504 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
3505 (mask_scatter_store<mode>v64si): Rename to ...
3506 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
3507 (*<reduc_op>_dpp_shr_v64di): Rename to ...
3508 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
3509 (*plus_carry_in_dpp_shr_v64si): Rename to ...
3510 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
3511 (*plus_carry_dpp_shr_v64di): Rename to ...
3512 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
3513 (vec_seriesv64si): Rename to ...
3514 (vec_series<mode>): ... this, and use V_SI.
3515 (vec_seriesv64di): Rename to ...
3516 (vec_series<mode>): ... this, and use V_DI.
3518 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
3520 * config/arc/arc.c (arc_print_operand): Use
3521 HOST_WIDE_INT_PRINT_DEC macro.
3523 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
3525 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
3527 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3529 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
3531 (__arm_vbicq): Likewise.
3533 2020-03-31 Vineet Gupta <vgupta@synopsys.com>
3535 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
3537 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3539 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
3540 common section of both MVE Integer and MVE Floating Point.
3542 (vaddlvq_p): Likewise.
3543 (vaddvaq): Likewise.
3544 (vaddvq_p): Likewise.
3545 (vcmpcsq): Likewise.
3546 (vmlsdavxq): Likewise.
3547 (vmlsdavq): Likewise.
3548 (vmladavxq): Likewise.
3549 (vmladavq): Likewise.
3551 (vminavq): Likewise.
3553 (vmaxavq): Likewise.
3554 (vmlaldavq): Likewise.
3555 (vcmphiq): Likewise.
3556 (vaddlvaq): Likewise.
3557 (vrmlaldavhq): Likewise.
3558 (vrmlaldavhxq): Likewise.
3559 (vrmlsldavhq): Likewise.
3560 (vrmlsldavhxq): Likewise.
3561 (vmlsldavxq): Likewise.
3562 (vmlsldavq): Likewise.
3564 (vrmlaldavhaq): Likewise.
3565 (vcmpgeq_m_n): Likewise.
3566 (vmlsdavxq_p): Likewise.
3567 (vmlsdavq_p): Likewise.
3568 (vmlsdavaxq): Likewise.
3569 (vmlsdavaq): Likewise.
3570 (vaddvaq_p): Likewise.
3571 (vcmpcsq_m_n): Likewise.
3572 (vcmpcsq_m): Likewise.
3573 (vmladavxq_p): Likewise.
3574 (vmladavq_p): Likewise.
3575 (vmladavaxq): Likewise.
3576 (vmladavaq): Likewise.
3577 (vminvq_p): Likewise.
3578 (vminavq_p): Likewise.
3579 (vmaxvq_p): Likewise.
3580 (vmaxavq_p): Likewise.
3581 (vcmphiq_m): Likewise.
3582 (vaddlvaq_p): Likewise.
3583 (vmlaldavaq): Likewise.
3584 (vmlaldavaxq): Likewise.
3585 (vmlaldavq_p): Likewise.
3586 (vmlaldavxq_p): Likewise.
3587 (vmlsldavaq): Likewise.
3588 (vmlsldavaxq): Likewise.
3589 (vmlsldavq_p): Likewise.
3590 (vmlsldavxq_p): Likewise.
3591 (vrmlaldavhaxq): Likewise.
3592 (vrmlaldavhq_p): Likewise.
3593 (vrmlaldavhxq_p): Likewise.
3594 (vrmlsldavhaq): Likewise.
3595 (vrmlsldavhaxq): Likewise.
3596 (vrmlsldavhq_p): Likewise.
3597 (vrmlsldavhxq_p): Likewise.
3598 (vabavq_p): Likewise.
3599 (vmladavaq_p): Likewise.
3600 (vstrbq_scatter_offset): Likewise.
3601 (vstrbq_p): Likewise.
3602 (vstrbq_scatter_offset_p): Likewise.
3603 (vstrdq_scatter_base_p): Likewise.
3604 (vstrdq_scatter_base): Likewise.
3605 (vstrdq_scatter_offset_p): Likewise.
3606 (vstrdq_scatter_offset): Likewise.
3607 (vstrdq_scatter_shifted_offset_p): Likewise.
3608 (vstrdq_scatter_shifted_offset): Likewise.
3609 (vmaxq_x): Likewise.
3610 (vminq_x): Likewise.
3611 (vmovlbq_x): Likewise.
3612 (vmovltq_x): Likewise.
3613 (vmulhq_x): Likewise.
3614 (vmullbq_int_x): Likewise.
3615 (vmullbq_poly_x): Likewise.
3616 (vmulltq_int_x): Likewise.
3617 (vmulltq_poly_x): Likewise.
3620 2020-03-31 Jakub Jelinek <jakub@redhat.com>
3623 * config/aarch64/constraints.md (Uph): New constraint.
3624 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
3625 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
3628 2020-03-31 Marc Glisse <marc.glisse@inria.fr>
3629 Jakub Jelinek <jakub@redhat.com>
3632 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
3633 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
3635 2020-03-31 Jakub Jelinek <jakub@redhat.com>
3637 PR tree-optimization/94403
3638 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
3639 ENUMERAL_TYPE lhs_type.
3641 PR rtl-optimization/94344
3642 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
3643 conversions, either on both operands of |^+ or just one. Handle
3644 also extra same precision conversion on RSHIFT_EXPR first operand
3645 provided RSHIFT_EXPR is performed in unsigned type.
3647 2020-03-30 David Malcolm <dmalcolm@redhat.com>
3649 * lra.c (finish_insn_code_data_once): Set the array elements
3650 to NULL after freeing them.
3652 2020-03-30 Andreas Schwab <schwab@suse.de>
3654 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
3657 2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com>
3659 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
3660 to skip defining builtins based on builtin_mask.
3662 2020-03-30 Jakub Jelinek <jakub@redhat.com>
3665 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
3666 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
3667 operand is a register. Don't enable masked variants for V*[QH]Imode.
3670 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
3671 <store_mask_constraint> instead of m in output operand constraint.
3672 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
3675 2020-03-30 Alan Modra <amodra@gmail.com>
3677 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
3678 (rs6000_indirect_call_template_1): Adjust to suit.
3679 * config/rs6000/rs6000.md (call_local): Merge call_local32,
3680 call_local64, and call_local_aix.
3681 (call_value_local): Simlarly.
3682 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
3683 and disable pattern when CALL_LONG.
3684 (call_indirect_aix, call_value_indirect_aix): Adjust rtl.
3685 (call_indirect_elfv2, call_indirect_pcrel): Likewise.
3686 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
3688 2020-03-29 H.J. Lu <hongjiu.lu@intel.com>
3691 * doc/invoke.texi: Update -falign-functions, -falign-loops and
3692 -falign-jumps documentation.
3694 2020-03-29 Martin Liska <mliska@suse.cz>
3697 * cgraphunit.c (process_function_and_variable_attributes): Remove
3698 double 'attribute' words.
3700 2020-03-29 John David Anglin <dave.anglin@bell.net>
3702 * config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
3705 2020-03-28 Jakub Jelinek <jakub@redhat.com>
3708 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const
3709 to true after setting size to integer_one_node.
3711 PR tree-optimization/94329
3712 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
3713 on the last stmt in a bb, make sure gsi_prev isn't done immediately
3716 2020-03-27 Alan Modra <amodra@gmail.com>
3719 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
3720 for PLT16_LO and PLT_PCREL.
3721 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
3722 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
3723 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
3725 2020-03-27 Martin Sebor <msebor@redhat.com>
3728 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes.
3730 2020-03-27 Andrew Stubbs <ams@codesourcery.com>
3732 * config/gcn/gcn-valu.md:
3733 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout.
3734 (VEC_1REG_MODE): Delete.
3735 (VEC_1REG_ALT): Delete.
3736 (VEC_ALL1REG_MODE): Rename to V_1REG throughout.
3737 (VEC_1REG_INT_MODE): Delete.
3738 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout.
3739 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout.
3740 (VEC_2REG_MODE): Rename to V_2REG throughout.
3741 (VEC_REG_MODE): Rename to V_noHI throughout.
3742 (VEC_ALLREG_MODE): Rename to V_ALL throughout.
3743 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout.
3744 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout.
3745 (VEC_INT_MODE): Delete.
3746 (VEC_FP_MODE): Rename to V_FP throughout and move to top.
3747 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top.
3748 (FP_MODE): Delete and replace with FP throughout.
3749 (FP_1REG_MODE): Delete and replace with FP_1REG throughout.
3750 (VCMP_MODE): Rename to V_noQI throughout and move to top.
3751 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top.
3752 * config/gcn/gcn.md (FP): New mode iterator.
3753 (FP_1REG): New mode iterator.
3755 2020-03-27 David Malcolm <dmalcolm@redhat.com>
3757 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this
3758 now emits two .dot files.
3759 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD.
3760 (graphviz_out::end_tr): Only close a TR, not a TD.
3761 (graphviz_out::begin_td): New.
3762 (graphviz_out::end_td): New.
3763 (graphviz_out::begin_trtd): New, replacing the old implementation
3764 of graphviz_out::begin_tr.
3765 (graphviz_out::end_tdtr): New, replacing the old implementation
3766 of graphviz_out::end_tr.
3767 * graphviz.h (graphviz_out::begin_td): New decl.
3768 (graphviz_out::end_td): New decl.
3769 (graphviz_out::begin_trtd): New decl.
3770 (graphviz_out::end_tdtr): New decl.
3772 2020-03-27 Richard Biener <rguenther@suse.de>
3775 * dwarf2out.c (should_emit_struct_debug): Return false for
3778 2020-03-27 Richard Biener <rguenther@suse.de>
3780 PR tree-optimization/94352
3781 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the
3783 (ssa_propagation_engine::ssa_propagate): ... here after
3784 initializing curr_order.
3786 2020-03-27 Kewen Lin <linkw@gcc.gnu.org>
3788 PR tree-optimization/90332
3789 * tree-vect-stmts.c (vector_vector_composition_type): New function.
3790 (get_group_load_store_type): Adjust to call
3791 vector_vector_composition_type, extend it to construct with scalar
3793 (vectorizable_load): Likewise.
3795 2020-03-27 Roman Zhuykov <zhroma@ispras.ru>
3797 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions.
3798 (create_ddg_dep_no_link): Likewise.
3799 (add_cross_iteration_register_deps): Move debug instruction check.
3800 Other minor refactoring.
3801 (add_intra_loop_mem_dep): Do not check for debug instructions.
3802 (add_inter_loop_mem_dep): Likewise.
3803 (build_intra_loop_deps): Likewise.
3804 (create_ddg): Do not include debug insns into the graph.
3805 * ddg.h (struct ddg): Remove num_debug field.
3806 * modulo-sched.c (doloop_register_get): Adjust condition.
3807 (res_MII): Remove DDG num_debug field usage.
3808 (sms_schedule_by_order): Use assertion against debug insns.
3809 (ps_has_conflicts): Drop debug insn check.
3811 2020-03-26 Jakub Jelinek <jakub@redhat.com>
3814 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST
3815 that contains exactly one non-DEBUG_BEGIN_STMT statement.
3818 * gimple.h (gimple_seq_first_nondebug_stmt): New function.
3819 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains
3820 a single non-debug stmt followed by one or more debug stmts.
3821 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt
3822 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt
3823 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and
3824 gimple_seq_last to check if outer_stmt gbind could be reused and
3825 if yes and it is surrounded by any debug stmts, move them into the
3828 PR rtl-optimization/92264
3829 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even
3830 for sp based values in !frame_pointer_needed
3831 && !ACCUMULATE_OUTGOING_ARGS functions.
3833 2020-03-26 Felix Yang <felix.yang@huawei.com>
3835 PR tree-optimization/94269
3836 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict
3838 operation to single basic block.
3840 2020-03-25 Jeff Law <law@redhat.com>
3842 PR rtl-optimization/90275
3843 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the
3846 2020-03-25 Jakub Jelinek <jakub@redhat.com>
3849 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to
3850 mode rather than VOIDmode.
3852 2020-03-25 Martin Sebor <msebor@redhat.com>
3855 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings
3856 even for alloca calls resulting from system macro expansion.
3857 Include inlining context in all warnings.
3859 2020-03-25 Richard Sandiford <richard.sandiford@arm.com>
3862 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
3863 FPRs to change between SDmode and DDmode.
3865 2020-03-25 Martin Sebor <msebor@redhat.com>
3867 PR tree-optimization/94131
3868 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length
3870 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming
3871 types have constant sizes.
3873 2020-03-25 Martin Liska <mliska@suse.cz>
3876 * configure.ac: Report error only when --with-zstd
3878 * configure: Regenerate.
3880 2020-03-25 Jakub Jelinek <jakub@redhat.com>
3883 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
3884 INSN_CODE (insn) to -1 when changing the pattern.
3886 2020-03-25 Martin Liska <mliska@suse.cz>
3890 * config/i386/i386-features.c (make_resolver_func): Drop
3891 public flag for resolver.
3892 * config/rs6000/rs6000.c (make_resolver_func): Add comdat
3893 group for resolver and drop public flag if possible.
3894 * multiple_target.c (create_dispatcher_calls): Drop unique_name
3895 and resolution as we want to enable LTO privatization of the default
3898 2020-03-25 Martin Liska <mliska@suse.cz>
3901 * configure.ac: Respect --without-zstd and report
3902 error when we can't find header file with --with-zstd.
3903 * configure: Regenerate.
3905 2020-03-25 Jakub Jelinek <jakub@redhat.com>
3908 * varasm.c (output_constructor_array_range): If local->index
3909 RANGE_EXPR doesn't start at the current location in the constructor,
3910 skip needed number of bytes using assemble_zeros or assert we don't
3914 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong
3915 counter instead of DECL_UID.
3917 PR tree-optimization/94300
3918 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset
3919 is positive, make sure that off + size isn't larger than needed_len.
3921 2020-03-25 Richard Biener <rguenther@suse.de>
3922 Jakub Jelinek <jakub@redhat.com>
3925 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
3927 2020-03-24 Christophe Lyon <christophe.lyon@linaro.org>
3929 * doc/sourcebuild.texi (ARM-specific attributes): Add
3931 (Features for dg-add-options): Add arm_fp_dp.
3933 2020-03-24 John David Anglin <danglin@gcc.gnu.org>
3936 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.
3938 2020-03-24 Tobias Burnus <tobias@codesourcery.com>
3941 * omp-offload.c (omp_finish_file): Fix target-link handling if
3942 targetm_common.have_named_sections is false.
3944 2020-03-24 Jakub Jelinek <jakub@redhat.com>
3947 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
3951 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to
3952 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts.
3953 If not after and at *incr_pos is a debug stmt, set stmt location to
3954 location of next non-debug stmt after it if any.
3957 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
3958 GF_PLF_2, but don't add them to worklist. Don't add an assigment to
3959 worklist or set GF_PLF_2 just because it is used in a debug stmt in
3960 another bb. Formatting improvements.
3963 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and
3964 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC
3965 regardless of whether TREE_NO_WARNING is set on it or whether
3966 warn_unused_function is true or not.
3968 2020-03-23 Jeff Law <law@redhat.com>
3970 PR rtl-optimization/90275
3973 * simplify-rtx.c (comparison_code_valid_for_mode): New function.
3974 (simplify_logical_relational_operation): Use it.
3976 2020-03-23 Jakub Jelinek <jakub@redhat.com>
3979 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on
3980 ultimate rhs and if returned something different, reconstructing
3983 2020-03-23 Lewis Hyatt <lhyatt@gmail.com>
3985 * opts.c (print_filtered_help): Improve the help text for alias options.
3987 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3988 Andre Vieira <andre.simoesdiasvieira@arm.com>
3989 Mihail Ionescu <mihail.ionescu@arm.com>
3991 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro.
3992 (vshlcq_m_u8): Likewise.
3993 (vshlcq_m_s16): Likewise.
3994 (vshlcq_m_u16): Likewise.
3995 (vshlcq_m_s32): Likewise.
3996 (vshlcq_m_u32): Likewise.
3997 (__arm_vshlcq_m_s8): Define intrinsic.
3998 (__arm_vshlcq_m_u8): Likewise.
3999 (__arm_vshlcq_m_s16): Likewise.
4000 (__arm_vshlcq_m_u16): Likewise.
4001 (__arm_vshlcq_m_s32): Likewise.
4002 (__arm_vshlcq_m_u32): Likewise.
4003 (vshlcq_m): Define polymorphic variant.
4004 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE):
4005 Use builtin qualifier.
4006 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
4007 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern.
4008 (mve_vshlcq_m_carry_<supf><mode>): Likewise.
4009 (mve_vshlcq_m_<supf><mode>): Likewise.
4011 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4013 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier.
4014 (UQSHL_QUALIFIERS): Likewise.
4015 (ASRL_QUALIFIERS): Likewise.
4016 (SQSHL_QUALIFIERS): Likewise.
4017 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in
4019 (sqrshr): Define macro.
4020 (sqrshrl): Likewise.
4021 (sqrshrl_sat48): Likewise.
4027 (uqrshll): Likewise.
4028 (uqrshll_sat48): Likewise.
4035 (__arm_lsll): Define intrinsic.
4036 (__arm_asrl): Likewise.
4037 (__arm_uqrshll): Likewise.
4038 (__arm_uqrshll_sat48): Likewise.
4039 (__arm_sqrshrl): Likewise.
4040 (__arm_sqrshrl_sat48): Likewise.
4041 (__arm_uqshll): Likewise.
4042 (__arm_urshrl): Likewise.
4043 (__arm_srshrl): Likewise.
4044 (__arm_sqshll): Likewise.
4045 (__arm_uqrshl): Likewise.
4046 (__arm_sqrshr): Likewise.
4047 (__arm_uqshl): Likewise.
4048 (__arm_urshr): Likewise.
4049 (__arm_sqshl): Likewise.
4050 (__arm_srshr): Likewise.
4051 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin
4053 (UQSHL_QUALIFIERS): Likewise.
4054 (ASRL_QUALIFIERS): Likewise.
4055 (SQSHL_QUALIFIERS): Likewise.
4056 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern.
4057 (mve_sqrshrl_sat<supf>_di): Likewise.
4058 (mve_uqrshl_si): Likewise.
4059 (mve_sqrshr_si): Likewise.
4060 (mve_uqshll_di): Likewise.
4061 (mve_urshrl_di): Likewise.
4062 (mve_uqshl_si): Likewise.
4063 (mve_urshr_si): Likewise.
4064 (mve_sqshl_si): Likewise.
4065 (mve_srshr_si): Likewise.
4066 (mve_srshrl_di): Likewise.
4067 (mve_sqshll_di): Likewise.
4069 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4070 Andre Vieira <andre.simoesdiasvieira@arm.com>
4071 Mihail Ionescu <mihail.ionescu@arm.com>
4073 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro.
4074 (vsetq_lane_f32): Likewise.
4075 (vsetq_lane_s16): Likewise.
4076 (vsetq_lane_s32): Likewise.
4077 (vsetq_lane_s8): Likewise.
4078 (vsetq_lane_s64): Likewise.
4079 (vsetq_lane_u8): Likewise.
4080 (vsetq_lane_u16): Likewise.
4081 (vsetq_lane_u32): Likewise.
4082 (vsetq_lane_u64): Likewise.
4083 (vgetq_lane_f16): Likewise.
4084 (vgetq_lane_f32): Likewise.
4085 (vgetq_lane_s16): Likewise.
4086 (vgetq_lane_s32): Likewise.
4087 (vgetq_lane_s8): Likewise.
4088 (vgetq_lane_s64): Likewise.
4089 (vgetq_lane_u8): Likewise.
4090 (vgetq_lane_u16): Likewise.
4091 (vgetq_lane_u32): Likewise.
4092 (vgetq_lane_u64): Likewise.
4093 (__ARM_NUM_LANES): Likewise.
4094 (__ARM_LANEQ): Likewise.
4095 (__ARM_CHECK_LANEQ): Likewise.
4096 (__arm_vsetq_lane_s16): Define intrinsic.
4097 (__arm_vsetq_lane_s32): Likewise.
4098 (__arm_vsetq_lane_s8): Likewise.
4099 (__arm_vsetq_lane_s64): Likewise.
4100 (__arm_vsetq_lane_u8): Likewise.
4101 (__arm_vsetq_lane_u16): Likewise.
4102 (__arm_vsetq_lane_u32): Likewise.
4103 (__arm_vsetq_lane_u64): Likewise.
4104 (__arm_vgetq_lane_s16): Likewise.
4105 (__arm_vgetq_lane_s32): Likewise.
4106 (__arm_vgetq_lane_s8): Likewise.
4107 (__arm_vgetq_lane_s64): Likewise.
4108 (__arm_vgetq_lane_u8): Likewise.
4109 (__arm_vgetq_lane_u16): Likewise.
4110 (__arm_vgetq_lane_u32): Likewise.
4111 (__arm_vgetq_lane_u64): Likewise.
4112 (__arm_vsetq_lane_f16): Likewise.
4113 (__arm_vsetq_lane_f32): Likewise.
4114 (__arm_vgetq_lane_f16): Likewise.
4115 (__arm_vgetq_lane_f32): Likewise.
4116 (vgetq_lane): Define polymorphic variant.
4117 (vsetq_lane): Likewise.
4118 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL
4120 (mve_vec_extractv2didi): Likewise.
4121 (mve_vec_extract_sext_internal<mode>): Likewise.
4122 (mve_vec_extract_zext_internal<mode>): Likewise.
4123 (mve_vec_set<mode>_internal): Likewise.
4124 (mve_vec_setv2di_internal): Likewise.
4125 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md
4127 (vec_extract<mode><V_elem_l>): Rename to
4128 "neon_vec_extract<mode><V_elem_l>".
4129 (vec_extractv2didi): Rename to "neon_vec_extractv2didi".
4130 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL
4131 pattern common for MVE and NEON.
4132 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both
4135 2020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com>
4137 * config/arm/mve.md (earlyclobber_32): New mode attribute.
4138 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
4139 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.
4141 2020-03-23 Richard Biener <rguenther@suse.de>
4143 PR tree-optimization/94261
4144 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove
4145 IL operand swapping code.
4146 (vect_slp_rearrange_stmts): Do not arrange isomorphic
4147 nodes that would need operation code adjustments.
4149 2020-03-23 Tobias Burnus <tobias@codesourcery.com>
4151 * doc/install.texi (amdgcn-*-amdhsa): Renamed
4152 from amdgcn-unknown-amdhsa; change
4153 amdgcn-unknown-amdhsa to amdgcn-amdhsa.
4155 2020-03-23 Richard Biener <rguenther@suse.de>
4158 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP
4159 directly rather than also folding it via build_fold_addr_expr.
4161 2020-03-23 Richard Biener <rguenther@suse.de>
4163 PR tree-optimization/94266
4164 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate
4165 addresses of TARGET_MEM_REFs.
4167 2020-03-23 Martin Liska <mliska@suse.cz>
4170 * symtab.c (symtab_node::clone_references): Save speculative_id
4171 as ref may be overwritten by create_reference.
4172 (symtab_node::clone_referring): Likewise.
4173 (symtab_node::clone_reference): Likewise.
4175 2020-03-22 Iain Sandoe <iain@sandoe.co.uk>
4177 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
4178 references to Darwin.
4179 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
4180 unconditionally and comment on why.
4182 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
4184 * config/darwin.c (darwin_mergeable_constant_section): Collect
4185 section anchor checks into the caller.
4186 (machopic_select_section): Collect section anchor checks into
4187 the determination of 'effective zero-size' objects. When the
4188 size is unknown, assume it is non-zero, and thus return the
4189 'generic' section for the DECL.
4191 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
4194 * config/darwin.opt: Amend options descriptions.
4196 2020-03-21 Richard Sandiford <richard.sandiford@arm.com>
4198 PR rtl-optimization/94052
4199 * lra-constraints.c (simplify_operand_subreg): Reload the inner
4200 register of a paradoxical subreg if simplify_subreg_regno fails
4201 to give a valid hard register for the outer mode.
4203 2020-03-20 Martin Jambor <mjambor@suse.cz>
4205 PR tree-optimization/93435
4206 * params.opt (sra-max-propagations): New parameter.
4207 * tree-sra.c (propagation_budget): New variable.
4208 (budget_for_propagation_access): New function.
4209 (propagate_subaccesses_from_rhs): Use it.
4210 (propagate_subaccesses_from_lhs): Likewise.
4211 (propagate_all_subaccesses): Set up and destroy propagation_budget.
4213 2020-03-20 Carl Love <cel@us.ibm.com>
4216 * config/rs6000/rs6000.c (rs6000_option_override_internal):
4217 Add check for TARGET_FPRND for Power 7 or newer.
4219 2020-03-20 Jan Hubicka <hubicka@ucw.cz>
4222 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag.
4223 (cgraph_edge::redirect_callee): Move here; likewise.
4224 (cgraph_node::remove_callees): Update calls_comdat_local flag.
4225 (cgraph_node::verify_node): Verify that calls_comdat_local flag match
4227 (cgraph_node::check_calls_comdat_local_p): New member function.
4228 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare.
4229 (cgraph_edge::redirect_callee): Move offline.
4230 * ipa-fnsummary.c (compute_fn_summary): Do not compute
4231 calls_comdat_local flag here.
4232 * ipa-inline-transform.c (inline_call): Fix updating of
4233 calls_comdat_local flag.
4234 * ipa-split.c (split_function): Use true instead of 1 to set the flag.
4235 * symtab.c (symtab_node::add_to_same_comdat_group): Update
4236 calls_comdat_local flag.
4238 2020-03-20 Richard Biener <rguenther@suse.de>
4240 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree
4241 from the possibly modified root.
4243 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4244 Andre Vieira <andre.simoesdiasvieira@arm.com>
4245 Mihail Ionescu <mihail.ionescu@arm.com>
4247 * config/arm/arm_mve.h (vst1q_p_u8): Define macro.
4248 (vst1q_p_s8): Likewise.
4249 (vst2q_s8): Likewise.
4250 (vst2q_u8): Likewise.
4251 (vld1q_z_u8): Likewise.
4252 (vld1q_z_s8): Likewise.
4253 (vld2q_s8): Likewise.
4254 (vld2q_u8): Likewise.
4255 (vld4q_s8): Likewise.
4256 (vld4q_u8): Likewise.
4257 (vst1q_p_u16): Likewise.
4258 (vst1q_p_s16): Likewise.
4259 (vst2q_s16): Likewise.
4260 (vst2q_u16): Likewise.
4261 (vld1q_z_u16): Likewise.
4262 (vld1q_z_s16): Likewise.
4263 (vld2q_s16): Likewise.
4264 (vld2q_u16): Likewise.
4265 (vld4q_s16): Likewise.
4266 (vld4q_u16): Likewise.
4267 (vst1q_p_u32): Likewise.
4268 (vst1q_p_s32): Likewise.
4269 (vst2q_s32): Likewise.
4270 (vst2q_u32): Likewise.
4271 (vld1q_z_u32): Likewise.
4272 (vld1q_z_s32): Likewise.
4273 (vld2q_s32): Likewise.
4274 (vld2q_u32): Likewise.
4275 (vld4q_s32): Likewise.
4276 (vld4q_u32): Likewise.
4277 (vld4q_f16): Likewise.
4278 (vld2q_f16): Likewise.
4279 (vld1q_z_f16): Likewise.
4280 (vst2q_f16): Likewise.
4281 (vst1q_p_f16): Likewise.
4282 (vld4q_f32): Likewise.
4283 (vld2q_f32): Likewise.
4284 (vld1q_z_f32): Likewise.
4285 (vst2q_f32): Likewise.
4286 (vst1q_p_f32): Likewise.
4287 (__arm_vst1q_p_u8): Define intrinsic.
4288 (__arm_vst1q_p_s8): Likewise.
4289 (__arm_vst2q_s8): Likewise.
4290 (__arm_vst2q_u8): Likewise.
4291 (__arm_vld1q_z_u8): Likewise.
4292 (__arm_vld1q_z_s8): Likewise.
4293 (__arm_vld2q_s8): Likewise.
4294 (__arm_vld2q_u8): Likewise.
4295 (__arm_vld4q_s8): Likewise.
4296 (__arm_vld4q_u8): Likewise.
4297 (__arm_vst1q_p_u16): Likewise.
4298 (__arm_vst1q_p_s16): Likewise.
4299 (__arm_vst2q_s16): Likewise.
4300 (__arm_vst2q_u16): Likewise.
4301 (__arm_vld1q_z_u16): Likewise.
4302 (__arm_vld1q_z_s16): Likewise.
4303 (__arm_vld2q_s16): Likewise.
4304 (__arm_vld2q_u16): Likewise.
4305 (__arm_vld4q_s16): Likewise.
4306 (__arm_vld4q_u16): Likewise.
4307 (__arm_vst1q_p_u32): Likewise.
4308 (__arm_vst1q_p_s32): Likewise.
4309 (__arm_vst2q_s32): Likewise.
4310 (__arm_vst2q_u32): Likewise.
4311 (__arm_vld1q_z_u32): Likewise.
4312 (__arm_vld1q_z_s32): Likewise.
4313 (__arm_vld2q_s32): Likewise.
4314 (__arm_vld2q_u32): Likewise.
4315 (__arm_vld4q_s32): Likewise.
4316 (__arm_vld4q_u32): Likewise.
4317 (__arm_vld4q_f16): Likewise.
4318 (__arm_vld2q_f16): Likewise.
4319 (__arm_vld1q_z_f16): Likewise.
4320 (__arm_vst2q_f16): Likewise.
4321 (__arm_vst1q_p_f16): Likewise.
4322 (__arm_vld4q_f32): Likewise.
4323 (__arm_vld2q_f32): Likewise.
4324 (__arm_vld1q_z_f32): Likewise.
4325 (__arm_vst2q_f32): Likewise.
4326 (__arm_vst1q_p_f32): Likewise.
4327 (vld1q_z): Define polymorphic variant.
4330 (vst1q_p): Likewise.
4332 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier.
4334 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern.
4335 (mve_vld2q<mode>): Likewise.
4336 (mve_vld4q<mode>): Likewise.
4338 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4339 Andre Vieira <andre.simoesdiasvieira@arm.com>
4340 Mihail Ionescu <mihail.ionescu@arm.com>
4342 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define.
4343 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise.
4344 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and
4345 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array.
4346 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC
4347 and ARM_BUILTIN_SET_FPSCR_NZCVQC.
4348 * config/arm/arm_mve.h (vadciq_s32): Define macro.
4349 (vadciq_u32): Likewise.
4350 (vadciq_m_s32): Likewise.
4351 (vadciq_m_u32): Likewise.
4352 (vadcq_s32): Likewise.
4353 (vadcq_u32): Likewise.
4354 (vadcq_m_s32): Likewise.
4355 (vadcq_m_u32): Likewise.
4356 (vsbciq_s32): Likewise.
4357 (vsbciq_u32): Likewise.
4358 (vsbciq_m_s32): Likewise.
4359 (vsbciq_m_u32): Likewise.
4360 (vsbcq_s32): Likewise.
4361 (vsbcq_u32): Likewise.
4362 (vsbcq_m_s32): Likewise.
4363 (vsbcq_m_u32): Likewise.
4364 (__arm_vadciq_s32): Define intrinsic.
4365 (__arm_vadciq_u32): Likewise.
4366 (__arm_vadciq_m_s32): Likewise.
4367 (__arm_vadciq_m_u32): Likewise.
4368 (__arm_vadcq_s32): Likewise.
4369 (__arm_vadcq_u32): Likewise.
4370 (__arm_vadcq_m_s32): Likewise.
4371 (__arm_vadcq_m_u32): Likewise.
4372 (__arm_vsbciq_s32): Likewise.
4373 (__arm_vsbciq_u32): Likewise.
4374 (__arm_vsbciq_m_s32): Likewise.
4375 (__arm_vsbciq_m_u32): Likewise.
4376 (__arm_vsbcq_s32): Likewise.
4377 (__arm_vsbcq_u32): Likewise.
4378 (__arm_vsbcq_m_s32): Likewise.
4379 (__arm_vsbcq_m_u32): Likewise.
4380 (vadciq_m): Define polymorphic variant.
4382 (vadcq_m): Likewise.
4384 (vsbciq_m): Likewise.
4386 (vsbcq_m): Likewise.
4388 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin
4390 (BINOP_UNONE_UNONE_UNONE): Likewise.
4391 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
4392 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
4393 * config/arm/mve.md (VADCIQ): Define iterator.
4394 (VADCIQ_M): Likewise.
4396 (VSBCQ_M): Likewise.
4398 (VSBCIQ_M): Likewise.
4400 (VADCQ_M): Likewise.
4401 (mve_vadciq_m_<supf>v4si): Define RTL pattern.
4402 (mve_vadciq_<supf>v4si): Likewise.
4403 (mve_vadcq_m_<supf>v4si): Likewise.
4404 (mve_vadcq_<supf>v4si): Likewise.
4405 (mve_vsbciq_m_<supf>v4si): Likewise.
4406 (mve_vsbciq_<supf>v4si): Likewise.
4407 (mve_vsbcq_m_<supf>v4si): Likewise.
4408 (mve_vsbcq_<supf>v4si): Likewise.
4409 (get_fpscr_nzcvqc): Define isns.
4410 (set_fpscr_nzcvqc): Define isns.
4411 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define.
4412 (UNSPEC_SET_FPSCR_NZCVQC): Define.
4414 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4416 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
4417 (vddupq_x_n_u16): Likewise.
4418 (vddupq_x_n_u32): Likewise.
4419 (vddupq_x_wb_u8): Likewise.
4420 (vddupq_x_wb_u16): Likewise.
4421 (vddupq_x_wb_u32): Likewise.
4422 (vdwdupq_x_n_u8): Likewise.
4423 (vdwdupq_x_n_u16): Likewise.
4424 (vdwdupq_x_n_u32): Likewise.
4425 (vdwdupq_x_wb_u8): Likewise.
4426 (vdwdupq_x_wb_u16): Likewise.
4427 (vdwdupq_x_wb_u32): Likewise.
4428 (vidupq_x_n_u8): Likewise.
4429 (vidupq_x_n_u16): Likewise.
4430 (vidupq_x_n_u32): Likewise.
4431 (vidupq_x_wb_u8): Likewise.
4432 (vidupq_x_wb_u16): Likewise.
4433 (vidupq_x_wb_u32): Likewise.
4434 (viwdupq_x_n_u8): Likewise.
4435 (viwdupq_x_n_u16): Likewise.
4436 (viwdupq_x_n_u32): Likewise.
4437 (viwdupq_x_wb_u8): Likewise.
4438 (viwdupq_x_wb_u16): Likewise.
4439 (viwdupq_x_wb_u32): Likewise.
4440 (vdupq_x_n_s8): Likewise.
4441 (vdupq_x_n_s16): Likewise.
4442 (vdupq_x_n_s32): Likewise.
4443 (vdupq_x_n_u8): Likewise.
4444 (vdupq_x_n_u16): Likewise.
4445 (vdupq_x_n_u32): Likewise.
4446 (vminq_x_s8): Likewise.
4447 (vminq_x_s16): Likewise.
4448 (vminq_x_s32): Likewise.
4449 (vminq_x_u8): Likewise.
4450 (vminq_x_u16): Likewise.
4451 (vminq_x_u32): Likewise.
4452 (vmaxq_x_s8): Likewise.
4453 (vmaxq_x_s16): Likewise.
4454 (vmaxq_x_s32): Likewise.
4455 (vmaxq_x_u8): Likewise.
4456 (vmaxq_x_u16): Likewise.
4457 (vmaxq_x_u32): Likewise.
4458 (vabdq_x_s8): Likewise.
4459 (vabdq_x_s16): Likewise.
4460 (vabdq_x_s32): Likewise.
4461 (vabdq_x_u8): Likewise.
4462 (vabdq_x_u16): Likewise.
4463 (vabdq_x_u32): Likewise.
4464 (vabsq_x_s8): Likewise.
4465 (vabsq_x_s16): Likewise.
4466 (vabsq_x_s32): Likewise.
4467 (vaddq_x_s8): Likewise.
4468 (vaddq_x_s16): Likewise.
4469 (vaddq_x_s32): Likewise.
4470 (vaddq_x_n_s8): Likewise.
4471 (vaddq_x_n_s16): Likewise.
4472 (vaddq_x_n_s32): Likewise.
4473 (vaddq_x_u8): Likewise.
4474 (vaddq_x_u16): Likewise.
4475 (vaddq_x_u32): Likewise.
4476 (vaddq_x_n_u8): Likewise.
4477 (vaddq_x_n_u16): Likewise.
4478 (vaddq_x_n_u32): Likewise.
4479 (vclsq_x_s8): Likewise.
4480 (vclsq_x_s16): Likewise.
4481 (vclsq_x_s32): Likewise.
4482 (vclzq_x_s8): Likewise.
4483 (vclzq_x_s16): Likewise.
4484 (vclzq_x_s32): Likewise.
4485 (vclzq_x_u8): Likewise.
4486 (vclzq_x_u16): Likewise.
4487 (vclzq_x_u32): Likewise.
4488 (vnegq_x_s8): Likewise.
4489 (vnegq_x_s16): Likewise.
4490 (vnegq_x_s32): Likewise.
4491 (vmulhq_x_s8): Likewise.
4492 (vmulhq_x_s16): Likewise.
4493 (vmulhq_x_s32): Likewise.
4494 (vmulhq_x_u8): Likewise.
4495 (vmulhq_x_u16): Likewise.
4496 (vmulhq_x_u32): Likewise.
4497 (vmullbq_poly_x_p8): Likewise.
4498 (vmullbq_poly_x_p16): Likewise.
4499 (vmullbq_int_x_s8): Likewise.
4500 (vmullbq_int_x_s16): Likewise.
4501 (vmullbq_int_x_s32): Likewise.
4502 (vmullbq_int_x_u8): Likewise.
4503 (vmullbq_int_x_u16): Likewise.
4504 (vmullbq_int_x_u32): Likewise.
4505 (vmulltq_poly_x_p8): Likewise.
4506 (vmulltq_poly_x_p16): Likewise.
4507 (vmulltq_int_x_s8): Likewise.
4508 (vmulltq_int_x_s16): Likewise.
4509 (vmulltq_int_x_s32): Likewise.
4510 (vmulltq_int_x_u8): Likewise.
4511 (vmulltq_int_x_u16): Likewise.
4512 (vmulltq_int_x_u32): Likewise.
4513 (vmulq_x_s8): Likewise.
4514 (vmulq_x_s16): Likewise.
4515 (vmulq_x_s32): Likewise.
4516 (vmulq_x_n_s8): Likewise.
4517 (vmulq_x_n_s16): Likewise.
4518 (vmulq_x_n_s32): Likewise.
4519 (vmulq_x_u8): Likewise.
4520 (vmulq_x_u16): Likewise.
4521 (vmulq_x_u32): Likewise.
4522 (vmulq_x_n_u8): Likewise.
4523 (vmulq_x_n_u16): Likewise.
4524 (vmulq_x_n_u32): Likewise.
4525 (vsubq_x_s8): Likewise.
4526 (vsubq_x_s16): Likewise.
4527 (vsubq_x_s32): Likewise.
4528 (vsubq_x_n_s8): Likewise.
4529 (vsubq_x_n_s16): Likewise.
4530 (vsubq_x_n_s32): Likewise.
4531 (vsubq_x_u8): Likewise.
4532 (vsubq_x_u16): Likewise.
4533 (vsubq_x_u32): Likewise.
4534 (vsubq_x_n_u8): Likewise.
4535 (vsubq_x_n_u16): Likewise.
4536 (vsubq_x_n_u32): Likewise.
4537 (vcaddq_rot90_x_s8): Likewise.
4538 (vcaddq_rot90_x_s16): Likewise.
4539 (vcaddq_rot90_x_s32): Likewise.
4540 (vcaddq_rot90_x_u8): Likewise.
4541 (vcaddq_rot90_x_u16): Likewise.
4542 (vcaddq_rot90_x_u32): Likewise.
4543 (vcaddq_rot270_x_s8): Likewise.
4544 (vcaddq_rot270_x_s16): Likewise.
4545 (vcaddq_rot270_x_s32): Likewise.
4546 (vcaddq_rot270_x_u8): Likewise.
4547 (vcaddq_rot270_x_u16): Likewise.
4548 (vcaddq_rot270_x_u32): Likewise.
4549 (vhaddq_x_n_s8): Likewise.
4550 (vhaddq_x_n_s16): Likewise.
4551 (vhaddq_x_n_s32): Likewise.
4552 (vhaddq_x_n_u8): Likewise.
4553 (vhaddq_x_n_u16): Likewise.
4554 (vhaddq_x_n_u32): Likewise.
4555 (vhaddq_x_s8): Likewise.
4556 (vhaddq_x_s16): Likewise.
4557 (vhaddq_x_s32): Likewise.
4558 (vhaddq_x_u8): Likewise.
4559 (vhaddq_x_u16): Likewise.
4560 (vhaddq_x_u32): Likewise.
4561 (vhcaddq_rot90_x_s8): Likewise.
4562 (vhcaddq_rot90_x_s16): Likewise.
4563 (vhcaddq_rot90_x_s32): Likewise.
4564 (vhcaddq_rot270_x_s8): Likewise.
4565 (vhcaddq_rot270_x_s16): Likewise.
4566 (vhcaddq_rot270_x_s32): Likewise.
4567 (vhsubq_x_n_s8): Likewise.
4568 (vhsubq_x_n_s16): Likewise.
4569 (vhsubq_x_n_s32): Likewise.
4570 (vhsubq_x_n_u8): Likewise.
4571 (vhsubq_x_n_u16): Likewise.
4572 (vhsubq_x_n_u32): Likewise.
4573 (vhsubq_x_s8): Likewise.
4574 (vhsubq_x_s16): Likewise.
4575 (vhsubq_x_s32): Likewise.
4576 (vhsubq_x_u8): Likewise.
4577 (vhsubq_x_u16): Likewise.
4578 (vhsubq_x_u32): Likewise.
4579 (vrhaddq_x_s8): Likewise.
4580 (vrhaddq_x_s16): Likewise.
4581 (vrhaddq_x_s32): Likewise.
4582 (vrhaddq_x_u8): Likewise.
4583 (vrhaddq_x_u16): Likewise.
4584 (vrhaddq_x_u32): Likewise.
4585 (vrmulhq_x_s8): Likewise.
4586 (vrmulhq_x_s16): Likewise.
4587 (vrmulhq_x_s32): Likewise.
4588 (vrmulhq_x_u8): Likewise.
4589 (vrmulhq_x_u16): Likewise.
4590 (vrmulhq_x_u32): Likewise.
4591 (vandq_x_s8): Likewise.
4592 (vandq_x_s16): Likewise.
4593 (vandq_x_s32): Likewise.
4594 (vandq_x_u8): Likewise.
4595 (vandq_x_u16): Likewise.
4596 (vandq_x_u32): Likewise.
4597 (vbicq_x_s8): Likewise.
4598 (vbicq_x_s16): Likewise.
4599 (vbicq_x_s32): Likewise.
4600 (vbicq_x_u8): Likewise.
4601 (vbicq_x_u16): Likewise.
4602 (vbicq_x_u32): Likewise.
4603 (vbrsrq_x_n_s8): Likewise.
4604 (vbrsrq_x_n_s16): Likewise.
4605 (vbrsrq_x_n_s32): Likewise.
4606 (vbrsrq_x_n_u8): Likewise.
4607 (vbrsrq_x_n_u16): Likewise.
4608 (vbrsrq_x_n_u32): Likewise.
4609 (veorq_x_s8): Likewise.
4610 (veorq_x_s16): Likewise.
4611 (veorq_x_s32): Likewise.
4612 (veorq_x_u8): Likewise.
4613 (veorq_x_u16): Likewise.
4614 (veorq_x_u32): Likewise.
4615 (vmovlbq_x_s8): Likewise.
4616 (vmovlbq_x_s16): Likewise.
4617 (vmovlbq_x_u8): Likewise.
4618 (vmovlbq_x_u16): Likewise.
4619 (vmovltq_x_s8): Likewise.
4620 (vmovltq_x_s16): Likewise.
4621 (vmovltq_x_u8): Likewise.
4622 (vmovltq_x_u16): Likewise.
4623 (vmvnq_x_s8): Likewise.
4624 (vmvnq_x_s16): Likewise.
4625 (vmvnq_x_s32): Likewise.
4626 (vmvnq_x_u8): Likewise.
4627 (vmvnq_x_u16): Likewise.
4628 (vmvnq_x_u32): Likewise.
4629 (vmvnq_x_n_s16): Likewise.
4630 (vmvnq_x_n_s32): Likewise.
4631 (vmvnq_x_n_u16): Likewise.
4632 (vmvnq_x_n_u32): Likewise.
4633 (vornq_x_s8): Likewise.
4634 (vornq_x_s16): Likewise.
4635 (vornq_x_s32): Likewise.
4636 (vornq_x_u8): Likewise.
4637 (vornq_x_u16): Likewise.
4638 (vornq_x_u32): Likewise.
4639 (vorrq_x_s8): Likewise.
4640 (vorrq_x_s16): Likewise.
4641 (vorrq_x_s32): Likewise.
4642 (vorrq_x_u8): Likewise.
4643 (vorrq_x_u16): Likewise.
4644 (vorrq_x_u32): Likewise.
4645 (vrev16q_x_s8): Likewise.
4646 (vrev16q_x_u8): Likewise.
4647 (vrev32q_x_s8): Likewise.
4648 (vrev32q_x_s16): Likewise.
4649 (vrev32q_x_u8): Likewise.
4650 (vrev32q_x_u16): Likewise.
4651 (vrev64q_x_s8): Likewise.
4652 (vrev64q_x_s16): Likewise.
4653 (vrev64q_x_s32): Likewise.
4654 (vrev64q_x_u8): Likewise.
4655 (vrev64q_x_u16): Likewise.
4656 (vrev64q_x_u32): Likewise.
4657 (vrshlq_x_s8): Likewise.
4658 (vrshlq_x_s16): Likewise.
4659 (vrshlq_x_s32): Likewise.
4660 (vrshlq_x_u8): Likewise.
4661 (vrshlq_x_u16): Likewise.
4662 (vrshlq_x_u32): Likewise.
4663 (vshllbq_x_n_s8): Likewise.
4664 (vshllbq_x_n_s16): Likewise.
4665 (vshllbq_x_n_u8): Likewise.
4666 (vshllbq_x_n_u16): Likewise.
4667 (vshlltq_x_n_s8): Likewise.
4668 (vshlltq_x_n_s16): Likewise.
4669 (vshlltq_x_n_u8): Likewise.
4670 (vshlltq_x_n_u16): Likewise.
4671 (vshlq_x_s8): Likewise.
4672 (vshlq_x_s16): Likewise.
4673 (vshlq_x_s32): Likewise.
4674 (vshlq_x_u8): Likewise.
4675 (vshlq_x_u16): Likewise.
4676 (vshlq_x_u32): Likewise.
4677 (vshlq_x_n_s8): Likewise.
4678 (vshlq_x_n_s16): Likewise.
4679 (vshlq_x_n_s32): Likewise.
4680 (vshlq_x_n_u8): Likewise.
4681 (vshlq_x_n_u16): Likewise.
4682 (vshlq_x_n_u32): Likewise.
4683 (vrshrq_x_n_s8): Likewise.
4684 (vrshrq_x_n_s16): Likewise.
4685 (vrshrq_x_n_s32): Likewise.
4686 (vrshrq_x_n_u8): Likewise.
4687 (vrshrq_x_n_u16): Likewise.
4688 (vrshrq_x_n_u32): Likewise.
4689 (vshrq_x_n_s8): Likewise.
4690 (vshrq_x_n_s16): Likewise.
4691 (vshrq_x_n_s32): Likewise.
4692 (vshrq_x_n_u8): Likewise.
4693 (vshrq_x_n_u16): Likewise.
4694 (vshrq_x_n_u32): Likewise.
4695 (vdupq_x_n_f16): Likewise.
4696 (vdupq_x_n_f32): Likewise.
4697 (vminnmq_x_f16): Likewise.
4698 (vminnmq_x_f32): Likewise.
4699 (vmaxnmq_x_f16): Likewise.
4700 (vmaxnmq_x_f32): Likewise.
4701 (vabdq_x_f16): Likewise.
4702 (vabdq_x_f32): Likewise.
4703 (vabsq_x_f16): Likewise.
4704 (vabsq_x_f32): Likewise.
4705 (vaddq_x_f16): Likewise.
4706 (vaddq_x_f32): Likewise.
4707 (vaddq_x_n_f16): Likewise.
4708 (vaddq_x_n_f32): Likewise.
4709 (vnegq_x_f16): Likewise.
4710 (vnegq_x_f32): Likewise.
4711 (vmulq_x_f16): Likewise.
4712 (vmulq_x_f32): Likewise.
4713 (vmulq_x_n_f16): Likewise.
4714 (vmulq_x_n_f32): Likewise.
4715 (vsubq_x_f16): Likewise.
4716 (vsubq_x_f32): Likewise.
4717 (vsubq_x_n_f16): Likewise.
4718 (vsubq_x_n_f32): Likewise.
4719 (vcaddq_rot90_x_f16): Likewise.
4720 (vcaddq_rot90_x_f32): Likewise.
4721 (vcaddq_rot270_x_f16): Likewise.
4722 (vcaddq_rot270_x_f32): Likewise.
4723 (vcmulq_x_f16): Likewise.
4724 (vcmulq_x_f32): Likewise.
4725 (vcmulq_rot90_x_f16): Likewise.
4726 (vcmulq_rot90_x_f32): Likewise.
4727 (vcmulq_rot180_x_f16): Likewise.
4728 (vcmulq_rot180_x_f32): Likewise.
4729 (vcmulq_rot270_x_f16): Likewise.
4730 (vcmulq_rot270_x_f32): Likewise.
4731 (vcvtaq_x_s16_f16): Likewise.
4732 (vcvtaq_x_s32_f32): Likewise.
4733 (vcvtaq_x_u16_f16): Likewise.
4734 (vcvtaq_x_u32_f32): Likewise.
4735 (vcvtnq_x_s16_f16): Likewise.
4736 (vcvtnq_x_s32_f32): Likewise.
4737 (vcvtnq_x_u16_f16): Likewise.
4738 (vcvtnq_x_u32_f32): Likewise.
4739 (vcvtpq_x_s16_f16): Likewise.
4740 (vcvtpq_x_s32_f32): Likewise.
4741 (vcvtpq_x_u16_f16): Likewise.
4742 (vcvtpq_x_u32_f32): Likewise.
4743 (vcvtmq_x_s16_f16): Likewise.
4744 (vcvtmq_x_s32_f32): Likewise.
4745 (vcvtmq_x_u16_f16): Likewise.
4746 (vcvtmq_x_u32_f32): Likewise.
4747 (vcvtbq_x_f32_f16): Likewise.
4748 (vcvttq_x_f32_f16): Likewise.
4749 (vcvtq_x_f16_u16): Likewise.
4750 (vcvtq_x_f16_s16): Likewise.
4751 (vcvtq_x_f32_s32): Likewise.
4752 (vcvtq_x_f32_u32): Likewise.
4753 (vcvtq_x_n_f16_s16): Likewise.
4754 (vcvtq_x_n_f16_u16): Likewise.
4755 (vcvtq_x_n_f32_s32): Likewise.
4756 (vcvtq_x_n_f32_u32): Likewise.
4757 (vcvtq_x_s16_f16): Likewise.
4758 (vcvtq_x_s32_f32): Likewise.
4759 (vcvtq_x_u16_f16): Likewise.
4760 (vcvtq_x_u32_f32): Likewise.
4761 (vcvtq_x_n_s16_f16): Likewise.
4762 (vcvtq_x_n_s32_f32): Likewise.
4763 (vcvtq_x_n_u16_f16): Likewise.
4764 (vcvtq_x_n_u32_f32): Likewise.
4765 (vrndq_x_f16): Likewise.
4766 (vrndq_x_f32): Likewise.
4767 (vrndnq_x_f16): Likewise.
4768 (vrndnq_x_f32): Likewise.
4769 (vrndmq_x_f16): Likewise.
4770 (vrndmq_x_f32): Likewise.
4771 (vrndpq_x_f16): Likewise.
4772 (vrndpq_x_f32): Likewise.
4773 (vrndaq_x_f16): Likewise.
4774 (vrndaq_x_f32): Likewise.
4775 (vrndxq_x_f16): Likewise.
4776 (vrndxq_x_f32): Likewise.
4777 (vandq_x_f16): Likewise.
4778 (vandq_x_f32): Likewise.
4779 (vbicq_x_f16): Likewise.
4780 (vbicq_x_f32): Likewise.
4781 (vbrsrq_x_n_f16): Likewise.
4782 (vbrsrq_x_n_f32): Likewise.
4783 (veorq_x_f16): Likewise.
4784 (veorq_x_f32): Likewise.
4785 (vornq_x_f16): Likewise.
4786 (vornq_x_f32): Likewise.
4787 (vorrq_x_f16): Likewise.
4788 (vorrq_x_f32): Likewise.
4789 (vrev32q_x_f16): Likewise.
4790 (vrev64q_x_f16): Likewise.
4791 (vrev64q_x_f32): Likewise.
4792 (__arm_vddupq_x_n_u8): Define intrinsic.
4793 (__arm_vddupq_x_n_u16): Likewise.
4794 (__arm_vddupq_x_n_u32): Likewise.
4795 (__arm_vddupq_x_wb_u8): Likewise.
4796 (__arm_vddupq_x_wb_u16): Likewise.
4797 (__arm_vddupq_x_wb_u32): Likewise.
4798 (__arm_vdwdupq_x_n_u8): Likewise.
4799 (__arm_vdwdupq_x_n_u16): Likewise.
4800 (__arm_vdwdupq_x_n_u32): Likewise.
4801 (__arm_vdwdupq_x_wb_u8): Likewise.
4802 (__arm_vdwdupq_x_wb_u16): Likewise.
4803 (__arm_vdwdupq_x_wb_u32): Likewise.
4804 (__arm_vidupq_x_n_u8): Likewise.
4805 (__arm_vidupq_x_n_u16): Likewise.
4806 (__arm_vidupq_x_n_u32): Likewise.
4807 (__arm_vidupq_x_wb_u8): Likewise.
4808 (__arm_vidupq_x_wb_u16): Likewise.
4809 (__arm_vidupq_x_wb_u32): Likewise.
4810 (__arm_viwdupq_x_n_u8): Likewise.
4811 (__arm_viwdupq_x_n_u16): Likewise.
4812 (__arm_viwdupq_x_n_u32): Likewise.
4813 (__arm_viwdupq_x_wb_u8): Likewise.
4814 (__arm_viwdupq_x_wb_u16): Likewise.
4815 (__arm_viwdupq_x_wb_u32): Likewise.
4816 (__arm_vdupq_x_n_s8): Likewise.
4817 (__arm_vdupq_x_n_s16): Likewise.
4818 (__arm_vdupq_x_n_s32): Likewise.
4819 (__arm_vdupq_x_n_u8): Likewise.
4820 (__arm_vdupq_x_n_u16): Likewise.
4821 (__arm_vdupq_x_n_u32): Likewise.
4822 (__arm_vminq_x_s8): Likewise.
4823 (__arm_vminq_x_s16): Likewise.
4824 (__arm_vminq_x_s32): Likewise.
4825 (__arm_vminq_x_u8): Likewise.
4826 (__arm_vminq_x_u16): Likewise.
4827 (__arm_vminq_x_u32): Likewise.
4828 (__arm_vmaxq_x_s8): Likewise.
4829 (__arm_vmaxq_x_s16): Likewise.
4830 (__arm_vmaxq_x_s32): Likewise.
4831 (__arm_vmaxq_x_u8): Likewise.
4832 (__arm_vmaxq_x_u16): Likewise.
4833 (__arm_vmaxq_x_u32): Likewise.
4834 (__arm_vabdq_x_s8): Likewise.
4835 (__arm_vabdq_x_s16): Likewise.
4836 (__arm_vabdq_x_s32): Likewise.
4837 (__arm_vabdq_x_u8): Likewise.
4838 (__arm_vabdq_x_u16): Likewise.
4839 (__arm_vabdq_x_u32): Likewise.
4840 (__arm_vabsq_x_s8): Likewise.
4841 (__arm_vabsq_x_s16): Likewise.
4842 (__arm_vabsq_x_s32): Likewise.
4843 (__arm_vaddq_x_s8): Likewise.
4844 (__arm_vaddq_x_s16): Likewise.
4845 (__arm_vaddq_x_s32): Likewise.
4846 (__arm_vaddq_x_n_s8): Likewise.
4847 (__arm_vaddq_x_n_s16): Likewise.
4848 (__arm_vaddq_x_n_s32): Likewise.
4849 (__arm_vaddq_x_u8): Likewise.
4850 (__arm_vaddq_x_u16): Likewise.
4851 (__arm_vaddq_x_u32): Likewise.
4852 (__arm_vaddq_x_n_u8): Likewise.
4853 (__arm_vaddq_x_n_u16): Likewise.
4854 (__arm_vaddq_x_n_u32): Likewise.
4855 (__arm_vclsq_x_s8): Likewise.
4856 (__arm_vclsq_x_s16): Likewise.
4857 (__arm_vclsq_x_s32): Likewise.
4858 (__arm_vclzq_x_s8): Likewise.
4859 (__arm_vclzq_x_s16): Likewise.
4860 (__arm_vclzq_x_s32): Likewise.
4861 (__arm_vclzq_x_u8): Likewise.
4862 (__arm_vclzq_x_u16): Likewise.
4863 (__arm_vclzq_x_u32): Likewise.
4864 (__arm_vnegq_x_s8): Likewise.
4865 (__arm_vnegq_x_s16): Likewise.
4866 (__arm_vnegq_x_s32): Likewise.
4867 (__arm_vmulhq_x_s8): Likewise.
4868 (__arm_vmulhq_x_s16): Likewise.
4869 (__arm_vmulhq_x_s32): Likewise.
4870 (__arm_vmulhq_x_u8): Likewise.
4871 (__arm_vmulhq_x_u16): Likewise.
4872 (__arm_vmulhq_x_u32): Likewise.
4873 (__arm_vmullbq_poly_x_p8): Likewise.
4874 (__arm_vmullbq_poly_x_p16): Likewise.
4875 (__arm_vmullbq_int_x_s8): Likewise.
4876 (__arm_vmullbq_int_x_s16): Likewise.
4877 (__arm_vmullbq_int_x_s32): Likewise.
4878 (__arm_vmullbq_int_x_u8): Likewise.
4879 (__arm_vmullbq_int_x_u16): Likewise.
4880 (__arm_vmullbq_int_x_u32): Likewise.
4881 (__arm_vmulltq_poly_x_p8): Likewise.
4882 (__arm_vmulltq_poly_x_p16): Likewise.
4883 (__arm_vmulltq_int_x_s8): Likewise.
4884 (__arm_vmulltq_int_x_s16): Likewise.
4885 (__arm_vmulltq_int_x_s32): Likewise.
4886 (__arm_vmulltq_int_x_u8): Likewise.
4887 (__arm_vmulltq_int_x_u16): Likewise.
4888 (__arm_vmulltq_int_x_u32): Likewise.
4889 (__arm_vmulq_x_s8): Likewise.
4890 (__arm_vmulq_x_s16): Likewise.
4891 (__arm_vmulq_x_s32): Likewise.
4892 (__arm_vmulq_x_n_s8): Likewise.
4893 (__arm_vmulq_x_n_s16): Likewise.
4894 (__arm_vmulq_x_n_s32): Likewise.
4895 (__arm_vmulq_x_u8): Likewise.
4896 (__arm_vmulq_x_u16): Likewise.
4897 (__arm_vmulq_x_u32): Likewise.
4898 (__arm_vmulq_x_n_u8): Likewise.
4899 (__arm_vmulq_x_n_u16): Likewise.
4900 (__arm_vmulq_x_n_u32): Likewise.
4901 (__arm_vsubq_x_s8): Likewise.
4902 (__arm_vsubq_x_s16): Likewise.
4903 (__arm_vsubq_x_s32): Likewise.
4904 (__arm_vsubq_x_n_s8): Likewise.
4905 (__arm_vsubq_x_n_s16): Likewise.
4906 (__arm_vsubq_x_n_s32): Likewise.
4907 (__arm_vsubq_x_u8): Likewise.
4908 (__arm_vsubq_x_u16): Likewise.
4909 (__arm_vsubq_x_u32): Likewise.
4910 (__arm_vsubq_x_n_u8): Likewise.
4911 (__arm_vsubq_x_n_u16): Likewise.
4912 (__arm_vsubq_x_n_u32): Likewise.
4913 (__arm_vcaddq_rot90_x_s8): Likewise.
4914 (__arm_vcaddq_rot90_x_s16): Likewise.
4915 (__arm_vcaddq_rot90_x_s32): Likewise.
4916 (__arm_vcaddq_rot90_x_u8): Likewise.
4917 (__arm_vcaddq_rot90_x_u16): Likewise.
4918 (__arm_vcaddq_rot90_x_u32): Likewise.
4919 (__arm_vcaddq_rot270_x_s8): Likewise.
4920 (__arm_vcaddq_rot270_x_s16): Likewise.
4921 (__arm_vcaddq_rot270_x_s32): Likewise.
4922 (__arm_vcaddq_rot270_x_u8): Likewise.
4923 (__arm_vcaddq_rot270_x_u16): Likewise.
4924 (__arm_vcaddq_rot270_x_u32): Likewise.
4925 (__arm_vhaddq_x_n_s8): Likewise.
4926 (__arm_vhaddq_x_n_s16): Likewise.
4927 (__arm_vhaddq_x_n_s32): Likewise.
4928 (__arm_vhaddq_x_n_u8): Likewise.
4929 (__arm_vhaddq_x_n_u16): Likewise.
4930 (__arm_vhaddq_x_n_u32): Likewise.
4931 (__arm_vhaddq_x_s8): Likewise.
4932 (__arm_vhaddq_x_s16): Likewise.
4933 (__arm_vhaddq_x_s32): Likewise.
4934 (__arm_vhaddq_x_u8): Likewise.
4935 (__arm_vhaddq_x_u16): Likewise.
4936 (__arm_vhaddq_x_u32): Likewise.
4937 (__arm_vhcaddq_rot90_x_s8): Likewise.
4938 (__arm_vhcaddq_rot90_x_s16): Likewise.
4939 (__arm_vhcaddq_rot90_x_s32): Likewise.
4940 (__arm_vhcaddq_rot270_x_s8): Likewise.
4941 (__arm_vhcaddq_rot270_x_s16): Likewise.
4942 (__arm_vhcaddq_rot270_x_s32): Likewise.
4943 (__arm_vhsubq_x_n_s8): Likewise.
4944 (__arm_vhsubq_x_n_s16): Likewise.
4945 (__arm_vhsubq_x_n_s32): Likewise.
4946 (__arm_vhsubq_x_n_u8): Likewise.
4947 (__arm_vhsubq_x_n_u16): Likewise.
4948 (__arm_vhsubq_x_n_u32): Likewise.
4949 (__arm_vhsubq_x_s8): Likewise.
4950 (__arm_vhsubq_x_s16): Likewise.
4951 (__arm_vhsubq_x_s32): Likewise.
4952 (__arm_vhsubq_x_u8): Likewise.
4953 (__arm_vhsubq_x_u16): Likewise.
4954 (__arm_vhsubq_x_u32): Likewise.
4955 (__arm_vrhaddq_x_s8): Likewise.
4956 (__arm_vrhaddq_x_s16): Likewise.
4957 (__arm_vrhaddq_x_s32): Likewise.
4958 (__arm_vrhaddq_x_u8): Likewise.
4959 (__arm_vrhaddq_x_u16): Likewise.
4960 (__arm_vrhaddq_x_u32): Likewise.
4961 (__arm_vrmulhq_x_s8): Likewise.
4962 (__arm_vrmulhq_x_s16): Likewise.
4963 (__arm_vrmulhq_x_s32): Likewise.
4964 (__arm_vrmulhq_x_u8): Likewise.
4965 (__arm_vrmulhq_x_u16): Likewise.
4966 (__arm_vrmulhq_x_u32): Likewise.
4967 (__arm_vandq_x_s8): Likewise.
4968 (__arm_vandq_x_s16): Likewise.
4969 (__arm_vandq_x_s32): Likewise.
4970 (__arm_vandq_x_u8): Likewise.
4971 (__arm_vandq_x_u16): Likewise.
4972 (__arm_vandq_x_u32): Likewise.
4973 (__arm_vbicq_x_s8): Likewise.
4974 (__arm_vbicq_x_s16): Likewise.
4975 (__arm_vbicq_x_s32): Likewise.
4976 (__arm_vbicq_x_u8): Likewise.
4977 (__arm_vbicq_x_u16): Likewise.
4978 (__arm_vbicq_x_u32): Likewise.
4979 (__arm_vbrsrq_x_n_s8): Likewise.
4980 (__arm_vbrsrq_x_n_s16): Likewise.
4981 (__arm_vbrsrq_x_n_s32): Likewise.
4982 (__arm_vbrsrq_x_n_u8): Likewise.
4983 (__arm_vbrsrq_x_n_u16): Likewise.
4984 (__arm_vbrsrq_x_n_u32): Likewise.
4985 (__arm_veorq_x_s8): Likewise.
4986 (__arm_veorq_x_s16): Likewise.
4987 (__arm_veorq_x_s32): Likewise.
4988 (__arm_veorq_x_u8): Likewise.
4989 (__arm_veorq_x_u16): Likewise.
4990 (__arm_veorq_x_u32): Likewise.
4991 (__arm_vmovlbq_x_s8): Likewise.
4992 (__arm_vmovlbq_x_s16): Likewise.
4993 (__arm_vmovlbq_x_u8): Likewise.
4994 (__arm_vmovlbq_x_u16): Likewise.
4995 (__arm_vmovltq_x_s8): Likewise.
4996 (__arm_vmovltq_x_s16): Likewise.
4997 (__arm_vmovltq_x_u8): Likewise.
4998 (__arm_vmovltq_x_u16): Likewise.
4999 (__arm_vmvnq_x_s8): Likewise.
5000 (__arm_vmvnq_x_s16): Likewise.
5001 (__arm_vmvnq_x_s32): Likewise.
5002 (__arm_vmvnq_x_u8): Likewise.
5003 (__arm_vmvnq_x_u16): Likewise.
5004 (__arm_vmvnq_x_u32): Likewise.
5005 (__arm_vmvnq_x_n_s16): Likewise.
5006 (__arm_vmvnq_x_n_s32): Likewise.
5007 (__arm_vmvnq_x_n_u16): Likewise.
5008 (__arm_vmvnq_x_n_u32): Likewise.
5009 (__arm_vornq_x_s8): Likewise.
5010 (__arm_vornq_x_s16): Likewise.
5011 (__arm_vornq_x_s32): Likewise.
5012 (__arm_vornq_x_u8): Likewise.
5013 (__arm_vornq_x_u16): Likewise.
5014 (__arm_vornq_x_u32): Likewise.
5015 (__arm_vorrq_x_s8): Likewise.
5016 (__arm_vorrq_x_s16): Likewise.
5017 (__arm_vorrq_x_s32): Likewise.
5018 (__arm_vorrq_x_u8): Likewise.
5019 (__arm_vorrq_x_u16): Likewise.
5020 (__arm_vorrq_x_u32): Likewise.
5021 (__arm_vrev16q_x_s8): Likewise.
5022 (__arm_vrev16q_x_u8): Likewise.
5023 (__arm_vrev32q_x_s8): Likewise.
5024 (__arm_vrev32q_x_s16): Likewise.
5025 (__arm_vrev32q_x_u8): Likewise.
5026 (__arm_vrev32q_x_u16): Likewise.
5027 (__arm_vrev64q_x_s8): Likewise.
5028 (__arm_vrev64q_x_s16): Likewise.
5029 (__arm_vrev64q_x_s32): Likewise.
5030 (__arm_vrev64q_x_u8): Likewise.
5031 (__arm_vrev64q_x_u16): Likewise.
5032 (__arm_vrev64q_x_u32): Likewise.
5033 (__arm_vrshlq_x_s8): Likewise.
5034 (__arm_vrshlq_x_s16): Likewise.
5035 (__arm_vrshlq_x_s32): Likewise.
5036 (__arm_vrshlq_x_u8): Likewise.
5037 (__arm_vrshlq_x_u16): Likewise.
5038 (__arm_vrshlq_x_u32): Likewise.
5039 (__arm_vshllbq_x_n_s8): Likewise.
5040 (__arm_vshllbq_x_n_s16): Likewise.
5041 (__arm_vshllbq_x_n_u8): Likewise.
5042 (__arm_vshllbq_x_n_u16): Likewise.
5043 (__arm_vshlltq_x_n_s8): Likewise.
5044 (__arm_vshlltq_x_n_s16): Likewise.
5045 (__arm_vshlltq_x_n_u8): Likewise.
5046 (__arm_vshlltq_x_n_u16): Likewise.
5047 (__arm_vshlq_x_s8): Likewise.
5048 (__arm_vshlq_x_s16): Likewise.
5049 (__arm_vshlq_x_s32): Likewise.
5050 (__arm_vshlq_x_u8): Likewise.
5051 (__arm_vshlq_x_u16): Likewise.
5052 (__arm_vshlq_x_u32): Likewise.
5053 (__arm_vshlq_x_n_s8): Likewise.
5054 (__arm_vshlq_x_n_s16): Likewise.
5055 (__arm_vshlq_x_n_s32): Likewise.
5056 (__arm_vshlq_x_n_u8): Likewise.
5057 (__arm_vshlq_x_n_u16): Likewise.
5058 (__arm_vshlq_x_n_u32): Likewise.
5059 (__arm_vrshrq_x_n_s8): Likewise.
5060 (__arm_vrshrq_x_n_s16): Likewise.
5061 (__arm_vrshrq_x_n_s32): Likewise.
5062 (__arm_vrshrq_x_n_u8): Likewise.
5063 (__arm_vrshrq_x_n_u16): Likewise.
5064 (__arm_vrshrq_x_n_u32): Likewise.
5065 (__arm_vshrq_x_n_s8): Likewise.
5066 (__arm_vshrq_x_n_s16): Likewise.
5067 (__arm_vshrq_x_n_s32): Likewise.
5068 (__arm_vshrq_x_n_u8): Likewise.
5069 (__arm_vshrq_x_n_u16): Likewise.
5070 (__arm_vshrq_x_n_u32): Likewise.
5071 (__arm_vdupq_x_n_f16): Likewise.
5072 (__arm_vdupq_x_n_f32): Likewise.
5073 (__arm_vminnmq_x_f16): Likewise.
5074 (__arm_vminnmq_x_f32): Likewise.
5075 (__arm_vmaxnmq_x_f16): Likewise.
5076 (__arm_vmaxnmq_x_f32): Likewise.
5077 (__arm_vabdq_x_f16): Likewise.
5078 (__arm_vabdq_x_f32): Likewise.
5079 (__arm_vabsq_x_f16): Likewise.
5080 (__arm_vabsq_x_f32): Likewise.
5081 (__arm_vaddq_x_f16): Likewise.
5082 (__arm_vaddq_x_f32): Likewise.
5083 (__arm_vaddq_x_n_f16): Likewise.
5084 (__arm_vaddq_x_n_f32): Likewise.
5085 (__arm_vnegq_x_f16): Likewise.
5086 (__arm_vnegq_x_f32): Likewise.
5087 (__arm_vmulq_x_f16): Likewise.
5088 (__arm_vmulq_x_f32): Likewise.
5089 (__arm_vmulq_x_n_f16): Likewise.
5090 (__arm_vmulq_x_n_f32): Likewise.
5091 (__arm_vsubq_x_f16): Likewise.
5092 (__arm_vsubq_x_f32): Likewise.
5093 (__arm_vsubq_x_n_f16): Likewise.
5094 (__arm_vsubq_x_n_f32): Likewise.
5095 (__arm_vcaddq_rot90_x_f16): Likewise.
5096 (__arm_vcaddq_rot90_x_f32): Likewise.
5097 (__arm_vcaddq_rot270_x_f16): Likewise.
5098 (__arm_vcaddq_rot270_x_f32): Likewise.
5099 (__arm_vcmulq_x_f16): Likewise.
5100 (__arm_vcmulq_x_f32): Likewise.
5101 (__arm_vcmulq_rot90_x_f16): Likewise.
5102 (__arm_vcmulq_rot90_x_f32): Likewise.
5103 (__arm_vcmulq_rot180_x_f16): Likewise.
5104 (__arm_vcmulq_rot180_x_f32): Likewise.
5105 (__arm_vcmulq_rot270_x_f16): Likewise.
5106 (__arm_vcmulq_rot270_x_f32): Likewise.
5107 (__arm_vcvtaq_x_s16_f16): Likewise.
5108 (__arm_vcvtaq_x_s32_f32): Likewise.
5109 (__arm_vcvtaq_x_u16_f16): Likewise.
5110 (__arm_vcvtaq_x_u32_f32): Likewise.
5111 (__arm_vcvtnq_x_s16_f16): Likewise.
5112 (__arm_vcvtnq_x_s32_f32): Likewise.
5113 (__arm_vcvtnq_x_u16_f16): Likewise.
5114 (__arm_vcvtnq_x_u32_f32): Likewise.
5115 (__arm_vcvtpq_x_s16_f16): Likewise.
5116 (__arm_vcvtpq_x_s32_f32): Likewise.
5117 (__arm_vcvtpq_x_u16_f16): Likewise.
5118 (__arm_vcvtpq_x_u32_f32): Likewise.
5119 (__arm_vcvtmq_x_s16_f16): Likewise.
5120 (__arm_vcvtmq_x_s32_f32): Likewise.
5121 (__arm_vcvtmq_x_u16_f16): Likewise.
5122 (__arm_vcvtmq_x_u32_f32): Likewise.
5123 (__arm_vcvtbq_x_f32_f16): Likewise.
5124 (__arm_vcvttq_x_f32_f16): Likewise.
5125 (__arm_vcvtq_x_f16_u16): Likewise.
5126 (__arm_vcvtq_x_f16_s16): Likewise.
5127 (__arm_vcvtq_x_f32_s32): Likewise.
5128 (__arm_vcvtq_x_f32_u32): Likewise.
5129 (__arm_vcvtq_x_n_f16_s16): Likewise.
5130 (__arm_vcvtq_x_n_f16_u16): Likewise.
5131 (__arm_vcvtq_x_n_f32_s32): Likewise.
5132 (__arm_vcvtq_x_n_f32_u32): Likewise.
5133 (__arm_vcvtq_x_s16_f16): Likewise.
5134 (__arm_vcvtq_x_s32_f32): Likewise.
5135 (__arm_vcvtq_x_u16_f16): Likewise.
5136 (__arm_vcvtq_x_u32_f32): Likewise.
5137 (__arm_vcvtq_x_n_s16_f16): Likewise.
5138 (__arm_vcvtq_x_n_s32_f32): Likewise.
5139 (__arm_vcvtq_x_n_u16_f16): Likewise.
5140 (__arm_vcvtq_x_n_u32_f32): Likewise.
5141 (__arm_vrndq_x_f16): Likewise.
5142 (__arm_vrndq_x_f32): Likewise.
5143 (__arm_vrndnq_x_f16): Likewise.
5144 (__arm_vrndnq_x_f32): Likewise.
5145 (__arm_vrndmq_x_f16): Likewise.
5146 (__arm_vrndmq_x_f32): Likewise.
5147 (__arm_vrndpq_x_f16): Likewise.
5148 (__arm_vrndpq_x_f32): Likewise.
5149 (__arm_vrndaq_x_f16): Likewise.
5150 (__arm_vrndaq_x_f32): Likewise.
5151 (__arm_vrndxq_x_f16): Likewise.
5152 (__arm_vrndxq_x_f32): Likewise.
5153 (__arm_vandq_x_f16): Likewise.
5154 (__arm_vandq_x_f32): Likewise.
5155 (__arm_vbicq_x_f16): Likewise.
5156 (__arm_vbicq_x_f32): Likewise.
5157 (__arm_vbrsrq_x_n_f16): Likewise.
5158 (__arm_vbrsrq_x_n_f32): Likewise.
5159 (__arm_veorq_x_f16): Likewise.
5160 (__arm_veorq_x_f32): Likewise.
5161 (__arm_vornq_x_f16): Likewise.
5162 (__arm_vornq_x_f32): Likewise.
5163 (__arm_vorrq_x_f16): Likewise.
5164 (__arm_vorrq_x_f32): Likewise.
5165 (__arm_vrev32q_x_f16): Likewise.
5166 (__arm_vrev64q_x_f16): Likewise.
5167 (__arm_vrev64q_x_f32): Likewise.
5168 (vabdq_x): Define polymorphic variant.
5169 (vabsq_x): Likewise.
5170 (vaddq_x): Likewise.
5171 (vandq_x): Likewise.
5172 (vbicq_x): Likewise.
5173 (vbrsrq_x): Likewise.
5174 (vcaddq_rot270_x): Likewise.
5175 (vcaddq_rot90_x): Likewise.
5176 (vcmulq_rot180_x): Likewise.
5177 (vcmulq_rot270_x): Likewise.
5178 (vcmulq_x): Likewise.
5179 (vcvtq_x): Likewise.
5180 (vcvtq_x_n): Likewise.
5181 (vcvtnq_m): Likewise.
5182 (veorq_x): Likewise.
5183 (vmaxnmq_x): Likewise.
5184 (vminnmq_x): Likewise.
5185 (vmulq_x): Likewise.
5186 (vnegq_x): Likewise.
5187 (vornq_x): Likewise.
5188 (vorrq_x): Likewise.
5189 (vrev32q_x): Likewise.
5190 (vrev64q_x): Likewise.
5191 (vrndaq_x): Likewise.
5192 (vrndmq_x): Likewise.
5193 (vrndnq_x): Likewise.
5194 (vrndpq_x): Likewise.
5195 (vrndq_x): Likewise.
5196 (vrndxq_x): Likewise.
5197 (vsubq_x): Likewise.
5198 (vcmulq_rot90_x): Likewise.
5200 (vclsq_x): Likewise.
5201 (vclzq_x): Likewise.
5202 (vhaddq_x): Likewise.
5203 (vhcaddq_rot270_x): Likewise.
5204 (vhcaddq_rot90_x): Likewise.
5205 (vhsubq_x): Likewise.
5206 (vmaxq_x): Likewise.
5207 (vminq_x): Likewise.
5208 (vmovlbq_x): Likewise.
5209 (vmovltq_x): Likewise.
5210 (vmulhq_x): Likewise.
5211 (vmullbq_int_x): Likewise.
5212 (vmullbq_poly_x): Likewise.
5213 (vmulltq_int_x): Likewise.
5214 (vmulltq_poly_x): Likewise.
5215 (vmvnq_x): Likewise.
5216 (vrev16q_x): Likewise.
5217 (vrhaddq_x): Likewise.
5218 (vrmulhq_x): Likewise.
5219 (vrshlq_x): Likewise.
5220 (vrshrq_x): Likewise.
5221 (vshllbq_x): Likewise.
5222 (vshlltq_x): Likewise.
5223 (vshlq_x_n): Likewise.
5224 (vshlq_x): Likewise.
5225 (vdwdupq_x_u8): Likewise.
5226 (vdwdupq_x_u16): Likewise.
5227 (vdwdupq_x_u32): Likewise.
5228 (viwdupq_x_u8): Likewise.
5229 (viwdupq_x_u16): Likewise.
5230 (viwdupq_x_u32): Likewise.
5231 (vidupq_x_u8): Likewise.
5232 (vddupq_x_u8): Likewise.
5233 (vidupq_x_u16): Likewise.
5234 (vddupq_x_u16): Likewise.
5235 (vidupq_x_u32): Likewise.
5236 (vddupq_x_u32): Likewise.
5237 (vshrq_x): Likewise.
5239 2020-03-20 Richard Biener <rguenther@suse.de>
5241 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts
5242 to vectorize for CTOR defs.
5244 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5245 Andre Vieira <andre.simoesdiasvieira@arm.com>
5246 Mihail Ionescu <mihail.ionescu@arm.com>
5248 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin
5250 (LDRGBWBU_QUALIFIERS): Likewise.
5251 (LDRGBWBS_Z_QUALIFIERS): Likewise.
5252 (LDRGBWBU_Z_QUALIFIERS): Likewise.
5253 (STRSBWBS_QUALIFIERS): Likewise.
5254 (STRSBWBU_QUALIFIERS): Likewise.
5255 (STRSBWBS_P_QUALIFIERS): Likewise.
5256 (STRSBWBU_P_QUALIFIERS): Likewise.
5257 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro.
5258 (vldrdq_gather_base_wb_u64): Likewise.
5259 (vldrdq_gather_base_wb_z_s64): Likewise.
5260 (vldrdq_gather_base_wb_z_u64): Likewise.
5261 (vldrwq_gather_base_wb_f32): Likewise.
5262 (vldrwq_gather_base_wb_s32): Likewise.
5263 (vldrwq_gather_base_wb_u32): Likewise.
5264 (vldrwq_gather_base_wb_z_f32): Likewise.
5265 (vldrwq_gather_base_wb_z_s32): Likewise.
5266 (vldrwq_gather_base_wb_z_u32): Likewise.
5267 (vstrdq_scatter_base_wb_p_s64): Likewise.
5268 (vstrdq_scatter_base_wb_p_u64): Likewise.
5269 (vstrdq_scatter_base_wb_s64): Likewise.
5270 (vstrdq_scatter_base_wb_u64): Likewise.
5271 (vstrwq_scatter_base_wb_p_s32): Likewise.
5272 (vstrwq_scatter_base_wb_p_f32): Likewise.
5273 (vstrwq_scatter_base_wb_p_u32): Likewise.
5274 (vstrwq_scatter_base_wb_s32): Likewise.
5275 (vstrwq_scatter_base_wb_u32): Likewise.
5276 (vstrwq_scatter_base_wb_f32): Likewise.
5277 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic.
5278 (__arm_vldrdq_gather_base_wb_u64): Likewise.
5279 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
5280 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
5281 (__arm_vldrwq_gather_base_wb_s32): Likewise.
5282 (__arm_vldrwq_gather_base_wb_u32): Likewise.
5283 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
5284 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
5285 (__arm_vstrdq_scatter_base_wb_s64): Likewise.
5286 (__arm_vstrdq_scatter_base_wb_u64): Likewise.
5287 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
5288 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
5289 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
5290 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
5291 (__arm_vstrwq_scatter_base_wb_s32): Likewise.
5292 (__arm_vstrwq_scatter_base_wb_u32): Likewise.
5293 (__arm_vldrwq_gather_base_wb_f32): Likewise.
5294 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
5295 (__arm_vstrwq_scatter_base_wb_f32): Likewise.
5296 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
5297 (vstrwq_scatter_base_wb): Define polymorphic variant.
5298 (vstrwq_scatter_base_wb_p): Likewise.
5299 (vstrdq_scatter_base_wb_p): Likewise.
5300 (vstrdq_scatter_base_wb): Likewise.
5301 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin
5303 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL
5305 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise.
5306 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise.
5307 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
5308 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise.
5309 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise.
5310 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
5311 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
5312 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise.
5313 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
5314 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
5315 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise.
5316 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
5317 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise.
5318 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise.
5319 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
5320 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise.
5321 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise.
5322 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise.
5323 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
5324 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise.
5325 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
5326 (mve_vldrwq_gather_base_wb_fv4sf): Likewise.
5327 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
5328 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise.
5329 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
5330 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise.
5331 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
5332 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise.
5333 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
5335 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5336 Andre Vieira <andre.simoesdiasvieira@arm.com>
5337 Mihail Ionescu <mihail.ionescu@arm.com>
5339 * config/arm/arm-builtins.c
5340 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary
5342 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro.
5343 (vddupq_m_n_u32): Likewise.
5344 (vddupq_m_n_u16): Likewise.
5345 (vddupq_m_wb_u8): Likewise.
5346 (vddupq_m_wb_u16): Likewise.
5347 (vddupq_m_wb_u32): Likewise.
5348 (vddupq_n_u8): Likewise.
5349 (vddupq_n_u32): Likewise.
5350 (vddupq_n_u16): Likewise.
5351 (vddupq_wb_u8): Likewise.
5352 (vddupq_wb_u16): Likewise.
5353 (vddupq_wb_u32): Likewise.
5354 (vdwdupq_m_n_u8): Likewise.
5355 (vdwdupq_m_n_u32): Likewise.
5356 (vdwdupq_m_n_u16): Likewise.
5357 (vdwdupq_m_wb_u8): Likewise.
5358 (vdwdupq_m_wb_u32): Likewise.
5359 (vdwdupq_m_wb_u16): Likewise.
5360 (vdwdupq_n_u8): Likewise.
5361 (vdwdupq_n_u32): Likewise.
5362 (vdwdupq_n_u16): Likewise.
5363 (vdwdupq_wb_u8): Likewise.
5364 (vdwdupq_wb_u32): Likewise.
5365 (vdwdupq_wb_u16): Likewise.
5366 (vidupq_m_n_u8): Likewise.
5367 (vidupq_m_n_u32): Likewise.
5368 (vidupq_m_n_u16): Likewise.
5369 (vidupq_m_wb_u8): Likewise.
5370 (vidupq_m_wb_u16): Likewise.
5371 (vidupq_m_wb_u32): Likewise.
5372 (vidupq_n_u8): Likewise.
5373 (vidupq_n_u32): Likewise.
5374 (vidupq_n_u16): Likewise.
5375 (vidupq_wb_u8): Likewise.
5376 (vidupq_wb_u16): Likewise.
5377 (vidupq_wb_u32): Likewise.
5378 (viwdupq_m_n_u8): Likewise.
5379 (viwdupq_m_n_u32): Likewise.
5380 (viwdupq_m_n_u16): Likewise.
5381 (viwdupq_m_wb_u8): Likewise.
5382 (viwdupq_m_wb_u32): Likewise.
5383 (viwdupq_m_wb_u16): Likewise.
5384 (viwdupq_n_u8): Likewise.
5385 (viwdupq_n_u32): Likewise.
5386 (viwdupq_n_u16): Likewise.
5387 (viwdupq_wb_u8): Likewise.
5388 (viwdupq_wb_u32): Likewise.
5389 (viwdupq_wb_u16): Likewise.
5390 (__arm_vddupq_m_n_u8): Define intrinsic.
5391 (__arm_vddupq_m_n_u32): Likewise.
5392 (__arm_vddupq_m_n_u16): Likewise.
5393 (__arm_vddupq_m_wb_u8): Likewise.
5394 (__arm_vddupq_m_wb_u16): Likewise.
5395 (__arm_vddupq_m_wb_u32): Likewise.
5396 (__arm_vddupq_n_u8): Likewise.
5397 (__arm_vddupq_n_u32): Likewise.
5398 (__arm_vddupq_n_u16): Likewise.
5399 (__arm_vdwdupq_m_n_u8): Likewise.
5400 (__arm_vdwdupq_m_n_u32): Likewise.
5401 (__arm_vdwdupq_m_n_u16): Likewise.
5402 (__arm_vdwdupq_m_wb_u8): Likewise.
5403 (__arm_vdwdupq_m_wb_u32): Likewise.
5404 (__arm_vdwdupq_m_wb_u16): Likewise.
5405 (__arm_vdwdupq_n_u8): Likewise.
5406 (__arm_vdwdupq_n_u32): Likewise.
5407 (__arm_vdwdupq_n_u16): Likewise.
5408 (__arm_vdwdupq_wb_u8): Likewise.
5409 (__arm_vdwdupq_wb_u32): Likewise.
5410 (__arm_vdwdupq_wb_u16): Likewise.
5411 (__arm_vidupq_m_n_u8): Likewise.
5412 (__arm_vidupq_m_n_u32): Likewise.
5413 (__arm_vidupq_m_n_u16): Likewise.
5414 (__arm_vidupq_n_u8): Likewise.
5415 (__arm_vidupq_m_wb_u8): Likewise.
5416 (__arm_vidupq_m_wb_u16): Likewise.
5417 (__arm_vidupq_m_wb_u32): Likewise.
5418 (__arm_vidupq_n_u32): Likewise.
5419 (__arm_vidupq_n_u16): Likewise.
5420 (__arm_vidupq_wb_u8): Likewise.
5421 (__arm_vidupq_wb_u16): Likewise.
5422 (__arm_vidupq_wb_u32): Likewise.
5423 (__arm_vddupq_wb_u8): Likewise.
5424 (__arm_vddupq_wb_u16): Likewise.
5425 (__arm_vddupq_wb_u32): Likewise.
5426 (__arm_viwdupq_m_n_u8): Likewise.
5427 (__arm_viwdupq_m_n_u32): Likewise.
5428 (__arm_viwdupq_m_n_u16): Likewise.
5429 (__arm_viwdupq_m_wb_u8): Likewise.
5430 (__arm_viwdupq_m_wb_u32): Likewise.
5431 (__arm_viwdupq_m_wb_u16): Likewise.
5432 (__arm_viwdupq_n_u8): Likewise.
5433 (__arm_viwdupq_n_u32): Likewise.
5434 (__arm_viwdupq_n_u16): Likewise.
5435 (__arm_viwdupq_wb_u8): Likewise.
5436 (__arm_viwdupq_wb_u32): Likewise.
5437 (__arm_viwdupq_wb_u16): Likewise.
5438 (vidupq_m): Define polymorphic variant.
5439 (vddupq_m): Likewise.
5440 (vidupq_u16): Likewise.
5441 (vidupq_u32): Likewise.
5442 (vidupq_u8): Likewise.
5443 (vddupq_u16): Likewise.
5444 (vddupq_u32): Likewise.
5445 (vddupq_u8): Likewise.
5446 (viwdupq_m): Likewise.
5447 (viwdupq_u16): Likewise.
5448 (viwdupq_u32): Likewise.
5449 (viwdupq_u8): Likewise.
5450 (vdwdupq_m): Likewise.
5451 (vdwdupq_u16): Likewise.
5452 (vdwdupq_u32): Likewise.
5453 (vdwdupq_u8): Likewise.
5454 * config/arm/arm_mve_builtins.def
5455 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin
5457 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern.
5458 (mve_vidupq_u<mode>_insn): Likewise.
5459 (mve_vidupq_m_n_u<mode>): Likewise.
5460 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
5461 (mve_vddupq_n_u<mode>): Likewise.
5462 (mve_vddupq_u<mode>_insn): Likewise.
5463 (mve_vddupq_m_n_u<mode>): Likewise.
5464 (mve_vddupq_m_wb_u<mode>_insn): Likewise.
5465 (mve_vdwdupq_n_u<mode>): Likewise.
5466 (mve_vdwdupq_wb_u<mode>): Likewise.
5467 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
5468 (mve_vdwdupq_m_n_u<mode>): Likewise.
5469 (mve_vdwdupq_m_wb_u<mode>): Likewise.
5470 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
5471 (mve_viwdupq_n_u<mode>): Likewise.
5472 (mve_viwdupq_wb_u<mode>): Likewise.
5473 (mve_viwdupq_wb_u<mode>_insn): Likewise.
5474 (mve_viwdupq_m_n_u<mode>): Likewise.
5475 (mve_viwdupq_m_wb_u<mode>): Likewise.
5476 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
5478 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5480 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro.
5481 (vreinterpretq_s16_s64): Likewise.
5482 (vreinterpretq_s16_s8): Likewise.
5483 (vreinterpretq_s16_u16): Likewise.
5484 (vreinterpretq_s16_u32): Likewise.
5485 (vreinterpretq_s16_u64): Likewise.
5486 (vreinterpretq_s16_u8): Likewise.
5487 (vreinterpretq_s32_s16): Likewise.
5488 (vreinterpretq_s32_s64): Likewise.
5489 (vreinterpretq_s32_s8): Likewise.
5490 (vreinterpretq_s32_u16): Likewise.
5491 (vreinterpretq_s32_u32): Likewise.
5492 (vreinterpretq_s32_u64): Likewise.
5493 (vreinterpretq_s32_u8): Likewise.
5494 (vreinterpretq_s64_s16): Likewise.
5495 (vreinterpretq_s64_s32): Likewise.
5496 (vreinterpretq_s64_s8): Likewise.
5497 (vreinterpretq_s64_u16): Likewise.
5498 (vreinterpretq_s64_u32): Likewise.
5499 (vreinterpretq_s64_u64): Likewise.
5500 (vreinterpretq_s64_u8): Likewise.
5501 (vreinterpretq_s8_s16): Likewise.
5502 (vreinterpretq_s8_s32): Likewise.
5503 (vreinterpretq_s8_s64): Likewise.
5504 (vreinterpretq_s8_u16): Likewise.
5505 (vreinterpretq_s8_u32): Likewise.
5506 (vreinterpretq_s8_u64): Likewise.
5507 (vreinterpretq_s8_u8): Likewise.
5508 (vreinterpretq_u16_s16): Likewise.
5509 (vreinterpretq_u16_s32): Likewise.
5510 (vreinterpretq_u16_s64): Likewise.
5511 (vreinterpretq_u16_s8): Likewise.
5512 (vreinterpretq_u16_u32): Likewise.
5513 (vreinterpretq_u16_u64): Likewise.
5514 (vreinterpretq_u16_u8): Likewise.
5515 (vreinterpretq_u32_s16): Likewise.
5516 (vreinterpretq_u32_s32): Likewise.
5517 (vreinterpretq_u32_s64): Likewise.
5518 (vreinterpretq_u32_s8): Likewise.
5519 (vreinterpretq_u32_u16): Likewise.
5520 (vreinterpretq_u32_u64): Likewise.
5521 (vreinterpretq_u32_u8): Likewise.
5522 (vreinterpretq_u64_s16): Likewise.
5523 (vreinterpretq_u64_s32): Likewise.
5524 (vreinterpretq_u64_s64): Likewise.
5525 (vreinterpretq_u64_s8): Likewise.
5526 (vreinterpretq_u64_u16): Likewise.
5527 (vreinterpretq_u64_u32): Likewise.
5528 (vreinterpretq_u64_u8): Likewise.
5529 (vreinterpretq_u8_s16): Likewise.
5530 (vreinterpretq_u8_s32): Likewise.
5531 (vreinterpretq_u8_s64): Likewise.
5532 (vreinterpretq_u8_s8): Likewise.
5533 (vreinterpretq_u8_u16): Likewise.
5534 (vreinterpretq_u8_u32): Likewise.
5535 (vreinterpretq_u8_u64): Likewise.
5536 (vreinterpretq_s32_f16): Likewise.
5537 (vreinterpretq_s32_f32): Likewise.
5538 (vreinterpretq_u16_f16): Likewise.
5539 (vreinterpretq_u16_f32): Likewise.
5540 (vreinterpretq_u32_f16): Likewise.
5541 (vreinterpretq_u32_f32): Likewise.
5542 (vreinterpretq_u64_f16): Likewise.
5543 (vreinterpretq_u64_f32): Likewise.
5544 (vreinterpretq_u8_f16): Likewise.
5545 (vreinterpretq_u8_f32): Likewise.
5546 (vreinterpretq_f16_f32): Likewise.
5547 (vreinterpretq_f16_s16): Likewise.
5548 (vreinterpretq_f16_s32): Likewise.
5549 (vreinterpretq_f16_s64): Likewise.
5550 (vreinterpretq_f16_s8): Likewise.
5551 (vreinterpretq_f16_u16): Likewise.
5552 (vreinterpretq_f16_u32): Likewise.
5553 (vreinterpretq_f16_u64): Likewise.
5554 (vreinterpretq_f16_u8): Likewise.
5555 (vreinterpretq_f32_f16): Likewise.
5556 (vreinterpretq_f32_s16): Likewise.
5557 (vreinterpretq_f32_s32): Likewise.
5558 (vreinterpretq_f32_s64): Likewise.
5559 (vreinterpretq_f32_s8): Likewise.
5560 (vreinterpretq_f32_u16): Likewise.
5561 (vreinterpretq_f32_u32): Likewise.
5562 (vreinterpretq_f32_u64): Likewise.
5563 (vreinterpretq_f32_u8): Likewise.
5564 (vreinterpretq_s16_f16): Likewise.
5565 (vreinterpretq_s16_f32): Likewise.
5566 (vreinterpretq_s64_f16): Likewise.
5567 (vreinterpretq_s64_f32): Likewise.
5568 (vreinterpretq_s8_f16): Likewise.
5569 (vreinterpretq_s8_f32): Likewise.
5570 (vuninitializedq_u8): Likewise.
5571 (vuninitializedq_u16): Likewise.
5572 (vuninitializedq_u32): Likewise.
5573 (vuninitializedq_u64): Likewise.
5574 (vuninitializedq_s8): Likewise.
5575 (vuninitializedq_s16): Likewise.
5576 (vuninitializedq_s32): Likewise.
5577 (vuninitializedq_s64): Likewise.
5578 (vuninitializedq_f16): Likewise.
5579 (vuninitializedq_f32): Likewise.
5580 (__arm_vuninitializedq_u8): Define intrinsic.
5581 (__arm_vuninitializedq_u16): Likewise.
5582 (__arm_vuninitializedq_u32): Likewise.
5583 (__arm_vuninitializedq_u64): Likewise.
5584 (__arm_vuninitializedq_s8): Likewise.
5585 (__arm_vuninitializedq_s16): Likewise.
5586 (__arm_vuninitializedq_s32): Likewise.
5587 (__arm_vuninitializedq_s64): Likewise.
5588 (__arm_vreinterpretq_s16_s32): Likewise.
5589 (__arm_vreinterpretq_s16_s64): Likewise.
5590 (__arm_vreinterpretq_s16_s8): Likewise.
5591 (__arm_vreinterpretq_s16_u16): Likewise.
5592 (__arm_vreinterpretq_s16_u32): Likewise.
5593 (__arm_vreinterpretq_s16_u64): Likewise.
5594 (__arm_vreinterpretq_s16_u8): Likewise.
5595 (__arm_vreinterpretq_s32_s16): Likewise.
5596 (__arm_vreinterpretq_s32_s64): Likewise.
5597 (__arm_vreinterpretq_s32_s8): Likewise.
5598 (__arm_vreinterpretq_s32_u16): Likewise.
5599 (__arm_vreinterpretq_s32_u32): Likewise.
5600 (__arm_vreinterpretq_s32_u64): Likewise.
5601 (__arm_vreinterpretq_s32_u8): Likewise.
5602 (__arm_vreinterpretq_s64_s16): Likewise.
5603 (__arm_vreinterpretq_s64_s32): Likewise.
5604 (__arm_vreinterpretq_s64_s8): Likewise.
5605 (__arm_vreinterpretq_s64_u16): Likewise.
5606 (__arm_vreinterpretq_s64_u32): Likewise.
5607 (__arm_vreinterpretq_s64_u64): Likewise.
5608 (__arm_vreinterpretq_s64_u8): Likewise.
5609 (__arm_vreinterpretq_s8_s16): Likewise.
5610 (__arm_vreinterpretq_s8_s32): Likewise.
5611 (__arm_vreinterpretq_s8_s64): Likewise.
5612 (__arm_vreinterpretq_s8_u16): Likewise.
5613 (__arm_vreinterpretq_s8_u32): Likewise.
5614 (__arm_vreinterpretq_s8_u64): Likewise.
5615 (__arm_vreinterpretq_s8_u8): Likewise.
5616 (__arm_vreinterpretq_u16_s16): Likewise.
5617 (__arm_vreinterpretq_u16_s32): Likewise.
5618 (__arm_vreinterpretq_u16_s64): Likewise.
5619 (__arm_vreinterpretq_u16_s8): Likewise.
5620 (__arm_vreinterpretq_u16_u32): Likewise.
5621 (__arm_vreinterpretq_u16_u64): Likewise.
5622 (__arm_vreinterpretq_u16_u8): Likewise.
5623 (__arm_vreinterpretq_u32_s16): Likewise.
5624 (__arm_vreinterpretq_u32_s32): Likewise.
5625 (__arm_vreinterpretq_u32_s64): Likewise.
5626 (__arm_vreinterpretq_u32_s8): Likewise.
5627 (__arm_vreinterpretq_u32_u16): Likewise.
5628 (__arm_vreinterpretq_u32_u64): Likewise.
5629 (__arm_vreinterpretq_u32_u8): Likewise.
5630 (__arm_vreinterpretq_u64_s16): Likewise.
5631 (__arm_vreinterpretq_u64_s32): Likewise.
5632 (__arm_vreinterpretq_u64_s64): Likewise.
5633 (__arm_vreinterpretq_u64_s8): Likewise.
5634 (__arm_vreinterpretq_u64_u16): Likewise.
5635 (__arm_vreinterpretq_u64_u32): Likewise.
5636 (__arm_vreinterpretq_u64_u8): Likewise.
5637 (__arm_vreinterpretq_u8_s16): Likewise.
5638 (__arm_vreinterpretq_u8_s32): Likewise.
5639 (__arm_vreinterpretq_u8_s64): Likewise.
5640 (__arm_vreinterpretq_u8_s8): Likewise.
5641 (__arm_vreinterpretq_u8_u16): Likewise.
5642 (__arm_vreinterpretq_u8_u32): Likewise.
5643 (__arm_vreinterpretq_u8_u64): Likewise.
5644 (__arm_vuninitializedq_f16): Likewise.
5645 (__arm_vuninitializedq_f32): Likewise.
5646 (__arm_vreinterpretq_s32_f16): Likewise.
5647 (__arm_vreinterpretq_s32_f32): Likewise.
5648 (__arm_vreinterpretq_s16_f16): Likewise.
5649 (__arm_vreinterpretq_s16_f32): Likewise.
5650 (__arm_vreinterpretq_s64_f16): Likewise.
5651 (__arm_vreinterpretq_s64_f32): Likewise.
5652 (__arm_vreinterpretq_s8_f16): Likewise.
5653 (__arm_vreinterpretq_s8_f32): Likewise.
5654 (__arm_vreinterpretq_u16_f16): Likewise.
5655 (__arm_vreinterpretq_u16_f32): Likewise.
5656 (__arm_vreinterpretq_u32_f16): Likewise.
5657 (__arm_vreinterpretq_u32_f32): Likewise.
5658 (__arm_vreinterpretq_u64_f16): Likewise.
5659 (__arm_vreinterpretq_u64_f32): Likewise.
5660 (__arm_vreinterpretq_u8_f16): Likewise.
5661 (__arm_vreinterpretq_u8_f32): Likewise.
5662 (__arm_vreinterpretq_f16_f32): Likewise.
5663 (__arm_vreinterpretq_f16_s16): Likewise.
5664 (__arm_vreinterpretq_f16_s32): Likewise.
5665 (__arm_vreinterpretq_f16_s64): Likewise.
5666 (__arm_vreinterpretq_f16_s8): Likewise.
5667 (__arm_vreinterpretq_f16_u16): Likewise.
5668 (__arm_vreinterpretq_f16_u32): Likewise.
5669 (__arm_vreinterpretq_f16_u64): Likewise.
5670 (__arm_vreinterpretq_f16_u8): Likewise.
5671 (__arm_vreinterpretq_f32_f16): Likewise.
5672 (__arm_vreinterpretq_f32_s16): Likewise.
5673 (__arm_vreinterpretq_f32_s32): Likewise.
5674 (__arm_vreinterpretq_f32_s64): Likewise.
5675 (__arm_vreinterpretq_f32_s8): Likewise.
5676 (__arm_vreinterpretq_f32_u16): Likewise.
5677 (__arm_vreinterpretq_f32_u32): Likewise.
5678 (__arm_vreinterpretq_f32_u64): Likewise.
5679 (__arm_vreinterpretq_f32_u8): Likewise.
5680 (vuninitializedq): Define polymorphic variant.
5681 (vreinterpretq_f16): Likewise.
5682 (vreinterpretq_f32): Likewise.
5683 (vreinterpretq_s16): Likewise.
5684 (vreinterpretq_s32): Likewise.
5685 (vreinterpretq_s64): Likewise.
5686 (vreinterpretq_s8): Likewise.
5687 (vreinterpretq_u16): Likewise.
5688 (vreinterpretq_u32): Likewise.
5689 (vreinterpretq_u64): Likewise.
5690 (vreinterpretq_u8): Likewise.
5692 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5693 Andre Vieira <andre.simoesdiasvieira@arm.com>
5694 Mihail Ionescu <mihail.ionescu@arm.com>
5696 * config/arm/arm_mve.h (vaddq_s8): Define macro.
5697 (vaddq_s16): Likewise.
5698 (vaddq_s32): Likewise.
5699 (vaddq_u8): Likewise.
5700 (vaddq_u16): Likewise.
5701 (vaddq_u32): Likewise.
5702 (vaddq_f16): Likewise.
5703 (vaddq_f32): Likewise.
5704 (__arm_vaddq_s8): Define intrinsic.
5705 (__arm_vaddq_s16): Likewise.
5706 (__arm_vaddq_s32): Likewise.
5707 (__arm_vaddq_u8): Likewise.
5708 (__arm_vaddq_u16): Likewise.
5709 (__arm_vaddq_u32): Likewise.
5710 (__arm_vaddq_f16): Likewise.
5711 (__arm_vaddq_f32): Likewise.
5712 (vaddq): Define polymorphic variant.
5713 * config/arm/iterators.md (VNIM): Define mode iterator for common types
5714 Neon, IWMMXT and MVE.
5715 (VNINOTM): Likewise.
5716 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern.
5717 (mve_vaddq_f<mode>): Define RTL pattern.
5718 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern.
5719 (addv8hf3_neon): Define RTL pattern.
5720 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern
5722 (addv8hf3): Define standard RTL pattern for MVE and Neon.
5723 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT.
5725 2020-03-20 Martin Liska <mliska@suse.cz>
5728 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously
5729 build_ref_for_offset function was used and it transforms off to bytes
5732 2020-03-20 Richard Biener <rguenther@suse.de>
5734 PR tree-optimization/94266
5735 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the
5736 type of the underlying object to adjust for the containing
5739 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
5741 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
5742 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
5743 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
5745 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
5747 * config/arm/mve.md (mve_mov<mode>): Fix R->R case.
5749 2020-03-20 Jakub Jelinek <jakub@redhat.com>
5751 PR tree-optimization/94224
5752 * gimple-ssa-store-merging.c
5753 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping
5754 or adjacent INTEGER_CST rhs_code stores as mergeable if they have
5757 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
5759 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve.
5761 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
5764 * cgraph.c (cgraph_node::function_symbol): Fix availability computation.
5765 (cgraph_node::function_or_virtual_thunk_symbol): Likewise.
5767 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
5770 * cgraphunit.c (process_function_and_variable_attributes): warn
5771 for flatten attribute on alias.
5772 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias.
5774 2020-03-19 Martin Liska <mliska@suse.cz>
5776 * lto-section-in.c: Add ext_symtab.
5777 * lto-streamer-out.c (write_symbol_extension_info): New.
5778 (produce_symtab_extension): New.
5779 (produce_asm_for_decls): Stream also produce_symtab_extension.
5780 * lto-streamer.h (enum lto_section_type): New section.
5782 2020-03-19 Jakub Jelinek <jakub@redhat.com>
5784 PR tree-optimization/94211
5785 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
5786 instead of estimate_num_insns for bb_seq (middle_bb). Rename
5787 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
5790 2020-03-19 Richard Biener <rguenther@suse.de>
5793 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr
5794 and build_ref_for_offset.
5796 2020-03-19 Richard Biener <rguenther@suse.de>
5799 * fold-const.c (fold_binary_loc): Avoid using
5800 build_fold_addr_expr when we really want an ADDR_EXPR.
5802 2020-03-18 Segher Boessenkool <segher@kernel.crashing.org>
5804 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented
5807 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
5809 PR rtl-optimization/90275
5810 * cse.c (cse_insn): Delete no-op register moves too.
5812 2020-03-18 Martin Sebor <msebor@redhat.com>
5815 * cgraphunit.c (process_function_and_variable_attributes): Also
5816 complain about weakref function definitions and drop all effects
5819 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
5820 Mihail Ionescu <mihail.ionescu@arm.com>
5821 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5823 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
5824 (vstrdq_scatter_base_p_u64): Likewise.
5825 (vstrdq_scatter_base_s64): Likewise.
5826 (vstrdq_scatter_base_u64): Likewise.
5827 (vstrdq_scatter_offset_p_s64): Likewise.
5828 (vstrdq_scatter_offset_p_u64): Likewise.
5829 (vstrdq_scatter_offset_s64): Likewise.
5830 (vstrdq_scatter_offset_u64): Likewise.
5831 (vstrdq_scatter_shifted_offset_p_s64): Likewise.
5832 (vstrdq_scatter_shifted_offset_p_u64): Likewise.
5833 (vstrdq_scatter_shifted_offset_s64): Likewise.
5834 (vstrdq_scatter_shifted_offset_u64): Likewise.
5835 (vstrhq_scatter_offset_f16): Likewise.
5836 (vstrhq_scatter_offset_p_f16): Likewise.
5837 (vstrhq_scatter_shifted_offset_f16): Likewise.
5838 (vstrhq_scatter_shifted_offset_p_f16): Likewise.
5839 (vstrwq_scatter_base_f32): Likewise.
5840 (vstrwq_scatter_base_p_f32): Likewise.
5841 (vstrwq_scatter_offset_f32): Likewise.
5842 (vstrwq_scatter_offset_p_f32): Likewise.
5843 (vstrwq_scatter_offset_p_s32): Likewise.
5844 (vstrwq_scatter_offset_p_u32): Likewise.
5845 (vstrwq_scatter_offset_s32): Likewise.
5846 (vstrwq_scatter_offset_u32): Likewise.
5847 (vstrwq_scatter_shifted_offset_f32): Likewise.
5848 (vstrwq_scatter_shifted_offset_p_f32): Likewise.
5849 (vstrwq_scatter_shifted_offset_p_s32): Likewise.
5850 (vstrwq_scatter_shifted_offset_p_u32): Likewise.
5851 (vstrwq_scatter_shifted_offset_s32): Likewise.
5852 (vstrwq_scatter_shifted_offset_u32): Likewise.
5853 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
5854 (__arm_vstrdq_scatter_base_p_u64): Likewise.
5855 (__arm_vstrdq_scatter_base_s64): Likewise.
5856 (__arm_vstrdq_scatter_base_u64): Likewise.
5857 (__arm_vstrdq_scatter_offset_p_s64): Likewise.
5858 (__arm_vstrdq_scatter_offset_p_u64): Likewise.
5859 (__arm_vstrdq_scatter_offset_s64): Likewise.
5860 (__arm_vstrdq_scatter_offset_u64): Likewise.
5861 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
5862 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
5863 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
5864 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
5865 (__arm_vstrwq_scatter_offset_p_s32): Likewise.
5866 (__arm_vstrwq_scatter_offset_p_u32): Likewise.
5867 (__arm_vstrwq_scatter_offset_s32): Likewise.
5868 (__arm_vstrwq_scatter_offset_u32): Likewise.
5869 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
5870 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
5871 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
5872 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
5873 (__arm_vstrhq_scatter_offset_f16): Likewise.
5874 (__arm_vstrhq_scatter_offset_p_f16): Likewise.
5875 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
5876 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
5877 (__arm_vstrwq_scatter_base_f32): Likewise.
5878 (__arm_vstrwq_scatter_base_p_f32): Likewise.
5879 (__arm_vstrwq_scatter_offset_f32): Likewise.
5880 (__arm_vstrwq_scatter_offset_p_f32): Likewise.
5881 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
5882 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
5883 (vstrhq_scatter_offset): Define polymorphic variant.
5884 (vstrhq_scatter_offset_p): Likewise.
5885 (vstrhq_scatter_shifted_offset): Likewise.
5886 (vstrhq_scatter_shifted_offset_p): Likewise.
5887 (vstrwq_scatter_base): Likewise.
5888 (vstrwq_scatter_base_p): Likewise.
5889 (vstrwq_scatter_offset): Likewise.
5890 (vstrwq_scatter_offset_p): Likewise.
5891 (vstrwq_scatter_shifted_offset): Likewise.
5892 (vstrwq_scatter_shifted_offset_p): Likewise.
5893 (vstrdq_scatter_base_p): Likewise.
5894 (vstrdq_scatter_base): Likewise.
5895 (vstrdq_scatter_offset_p): Likewise.
5896 (vstrdq_scatter_offset): Likewise.
5897 (vstrdq_scatter_shifted_offset_p): Likewise.
5898 (vstrdq_scatter_shifted_offset): Likewise.
5899 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
5900 (STRSBS_P): Likewise.
5902 (STRSBU_P): Likewise.
5904 (STRSS_P): Likewise.
5906 (STRSU_P): Likewise.
5907 * config/arm/constraints.md (Ri): Define.
5908 * config/arm/mve.md (VSTRDSBQ): Define iterator.
5909 (VSTRDSOQ): Likewise.
5910 (VSTRDSSOQ): Likewise.
5911 (VSTRWSOQ): Likewise.
5912 (VSTRWSSOQ): Likewise.
5913 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
5914 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
5915 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
5916 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
5917 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
5918 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
5919 (mve_vstrhq_scatter_offset_fv8hf): Likewise.
5920 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
5921 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
5922 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
5923 (mve_vstrwq_scatter_base_fv4sf): Likewise.
5924 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
5925 (mve_vstrwq_scatter_offset_fv4sf): Likewise.
5926 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
5927 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
5928 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
5929 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
5930 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
5931 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
5932 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
5933 * config/arm/predicates.md (Ri): Define predicate to check immediate
5934 is the range +/-1016 and multiple of 8.
5936 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
5937 Mihail Ionescu <mihail.ionescu@arm.com>
5938 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5940 * config/arm/arm_mve.h (vst1q_f32): Define macro.
5941 (vst1q_f16): Likewise.
5942 (vst1q_s8): Likewise.
5943 (vst1q_s32): Likewise.
5944 (vst1q_s16): Likewise.
5945 (vst1q_u8): Likewise.
5946 (vst1q_u32): Likewise.
5947 (vst1q_u16): Likewise.
5948 (vstrhq_f16): Likewise.
5949 (vstrhq_scatter_offset_s32): Likewise.
5950 (vstrhq_scatter_offset_s16): Likewise.
5951 (vstrhq_scatter_offset_u32): Likewise.
5952 (vstrhq_scatter_offset_u16): Likewise.
5953 (vstrhq_scatter_offset_p_s32): Likewise.
5954 (vstrhq_scatter_offset_p_s16): Likewise.
5955 (vstrhq_scatter_offset_p_u32): Likewise.
5956 (vstrhq_scatter_offset_p_u16): Likewise.
5957 (vstrhq_scatter_shifted_offset_s32): Likewise.
5958 (vstrhq_scatter_shifted_offset_s16): Likewise.
5959 (vstrhq_scatter_shifted_offset_u32): Likewise.
5960 (vstrhq_scatter_shifted_offset_u16): Likewise.
5961 (vstrhq_scatter_shifted_offset_p_s32): Likewise.
5962 (vstrhq_scatter_shifted_offset_p_s16): Likewise.
5963 (vstrhq_scatter_shifted_offset_p_u32): Likewise.
5964 (vstrhq_scatter_shifted_offset_p_u16): Likewise.
5965 (vstrhq_s32): Likewise.
5966 (vstrhq_s16): Likewise.
5967 (vstrhq_u32): Likewise.
5968 (vstrhq_u16): Likewise.
5969 (vstrhq_p_f16): Likewise.
5970 (vstrhq_p_s32): Likewise.
5971 (vstrhq_p_s16): Likewise.
5972 (vstrhq_p_u32): Likewise.
5973 (vstrhq_p_u16): Likewise.
5974 (vstrwq_f32): Likewise.
5975 (vstrwq_s32): Likewise.
5976 (vstrwq_u32): Likewise.
5977 (vstrwq_p_f32): Likewise.
5978 (vstrwq_p_s32): Likewise.
5979 (vstrwq_p_u32): Likewise.
5980 (__arm_vst1q_s8): Define intrinsic.
5981 (__arm_vst1q_s32): Likewise.
5982 (__arm_vst1q_s16): Likewise.
5983 (__arm_vst1q_u8): Likewise.
5984 (__arm_vst1q_u32): Likewise.
5985 (__arm_vst1q_u16): Likewise.
5986 (__arm_vstrhq_scatter_offset_s32): Likewise.
5987 (__arm_vstrhq_scatter_offset_s16): Likewise.
5988 (__arm_vstrhq_scatter_offset_u32): Likewise.
5989 (__arm_vstrhq_scatter_offset_u16): Likewise.
5990 (__arm_vstrhq_scatter_offset_p_s32): Likewise.
5991 (__arm_vstrhq_scatter_offset_p_s16): Likewise.
5992 (__arm_vstrhq_scatter_offset_p_u32): Likewise.
5993 (__arm_vstrhq_scatter_offset_p_u16): Likewise.
5994 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
5995 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
5996 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
5997 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
5998 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
5999 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
6000 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
6001 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
6002 (__arm_vstrhq_s32): Likewise.
6003 (__arm_vstrhq_s16): Likewise.
6004 (__arm_vstrhq_u32): Likewise.
6005 (__arm_vstrhq_u16): Likewise.
6006 (__arm_vstrhq_p_s32): Likewise.
6007 (__arm_vstrhq_p_s16): Likewise.
6008 (__arm_vstrhq_p_u32): Likewise.
6009 (__arm_vstrhq_p_u16): Likewise.
6010 (__arm_vstrwq_s32): Likewise.
6011 (__arm_vstrwq_u32): Likewise.
6012 (__arm_vstrwq_p_s32): Likewise.
6013 (__arm_vstrwq_p_u32): Likewise.
6014 (__arm_vstrwq_p_f32): Likewise.
6015 (__arm_vstrwq_f32): Likewise.
6016 (__arm_vst1q_f32): Likewise.
6017 (__arm_vst1q_f16): Likewise.
6018 (__arm_vstrhq_f16): Likewise.
6019 (__arm_vstrhq_p_f16): Likewise.
6020 (vst1q): Define polymorphic variant.
6022 (vstrhq_p): Likewise.
6023 (vstrhq_scatter_offset_p): Likewise.
6024 (vstrhq_scatter_offset): Likewise.
6025 (vstrhq_scatter_shifted_offset_p): Likewise.
6026 (vstrhq_scatter_shifted_offset): Likewise.
6027 (vstrwq_p): Likewise.
6029 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
6032 (STRSS_P): Likewise.
6034 (STRSU_P): Likewise.
6037 * config/arm/mve.md (VST1Q): Define iterator.
6038 (VSTRHSOQ): Likewise.
6039 (VSTRHSSOQ): Likewise.
6042 (mve_vstrhq_fv8hf): Define RTL pattern.
6043 (mve_vstrhq_p_fv8hf): Likewise.
6044 (mve_vstrhq_p_<supf><mode>): Likewise.
6045 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
6046 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
6047 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
6048 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
6049 (mve_vstrhq_<supf><mode>): Likewise.
6050 (mve_vstrwq_fv4sf): Likewise.
6051 (mve_vstrwq_p_fv4sf): Likewise.
6052 (mve_vstrwq_p_<supf>v4si): Likewise.
6053 (mve_vstrwq_<supf>v4si): Likewise.
6054 (mve_vst1q_f<mode>): Define expand.
6055 (mve_vst1q_<supf><mode>): Likewise.
6057 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6058 Mihail Ionescu <mihail.ionescu@arm.com>
6059 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6061 * config/arm/arm_mve.h (vld1q_s8): Define macro.
6062 (vld1q_s32): Likewise.
6063 (vld1q_s16): Likewise.
6064 (vld1q_u8): Likewise.
6065 (vld1q_u32): Likewise.
6066 (vld1q_u16): Likewise.
6067 (vldrhq_gather_offset_s32): Likewise.
6068 (vldrhq_gather_offset_s16): Likewise.
6069 (vldrhq_gather_offset_u32): Likewise.
6070 (vldrhq_gather_offset_u16): Likewise.
6071 (vldrhq_gather_offset_z_s32): Likewise.
6072 (vldrhq_gather_offset_z_s16): Likewise.
6073 (vldrhq_gather_offset_z_u32): Likewise.
6074 (vldrhq_gather_offset_z_u16): Likewise.
6075 (vldrhq_gather_shifted_offset_s32): Likewise.
6076 (vldrhq_gather_shifted_offset_s16): Likewise.
6077 (vldrhq_gather_shifted_offset_u32): Likewise.
6078 (vldrhq_gather_shifted_offset_u16): Likewise.
6079 (vldrhq_gather_shifted_offset_z_s32): Likewise.
6080 (vldrhq_gather_shifted_offset_z_s16): Likewise.
6081 (vldrhq_gather_shifted_offset_z_u32): Likewise.
6082 (vldrhq_gather_shifted_offset_z_u16): Likewise.
6083 (vldrhq_s32): Likewise.
6084 (vldrhq_s16): Likewise.
6085 (vldrhq_u32): Likewise.
6086 (vldrhq_u16): Likewise.
6087 (vldrhq_z_s32): Likewise.
6088 (vldrhq_z_s16): Likewise.
6089 (vldrhq_z_u32): Likewise.
6090 (vldrhq_z_u16): Likewise.
6091 (vldrwq_s32): Likewise.
6092 (vldrwq_u32): Likewise.
6093 (vldrwq_z_s32): Likewise.
6094 (vldrwq_z_u32): Likewise.
6095 (vld1q_f32): Likewise.
6096 (vld1q_f16): Likewise.
6097 (vldrhq_f16): Likewise.
6098 (vldrhq_z_f16): Likewise.
6099 (vldrwq_f32): Likewise.
6100 (vldrwq_z_f32): Likewise.
6101 (__arm_vld1q_s8): Define intrinsic.
6102 (__arm_vld1q_s32): Likewise.
6103 (__arm_vld1q_s16): Likewise.
6104 (__arm_vld1q_u8): Likewise.
6105 (__arm_vld1q_u32): Likewise.
6106 (__arm_vld1q_u16): Likewise.
6107 (__arm_vldrhq_gather_offset_s32): Likewise.
6108 (__arm_vldrhq_gather_offset_s16): Likewise.
6109 (__arm_vldrhq_gather_offset_u32): Likewise.
6110 (__arm_vldrhq_gather_offset_u16): Likewise.
6111 (__arm_vldrhq_gather_offset_z_s32): Likewise.
6112 (__arm_vldrhq_gather_offset_z_s16): Likewise.
6113 (__arm_vldrhq_gather_offset_z_u32): Likewise.
6114 (__arm_vldrhq_gather_offset_z_u16): Likewise.
6115 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
6116 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
6117 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
6118 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
6119 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
6120 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
6121 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
6122 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
6123 (__arm_vldrhq_s32): Likewise.
6124 (__arm_vldrhq_s16): Likewise.
6125 (__arm_vldrhq_u32): Likewise.
6126 (__arm_vldrhq_u16): Likewise.
6127 (__arm_vldrhq_z_s32): Likewise.
6128 (__arm_vldrhq_z_s16): Likewise.
6129 (__arm_vldrhq_z_u32): Likewise.
6130 (__arm_vldrhq_z_u16): Likewise.
6131 (__arm_vldrwq_s32): Likewise.
6132 (__arm_vldrwq_u32): Likewise.
6133 (__arm_vldrwq_z_s32): Likewise.
6134 (__arm_vldrwq_z_u32): Likewise.
6135 (__arm_vld1q_f32): Likewise.
6136 (__arm_vld1q_f16): Likewise.
6137 (__arm_vldrwq_f32): Likewise.
6138 (__arm_vldrwq_z_f32): Likewise.
6139 (__arm_vldrhq_z_f16): Likewise.
6140 (__arm_vldrhq_f16): Likewise.
6141 (vld1q): Define polymorphic variant.
6142 (vldrhq_gather_offset): Likewise.
6143 (vldrhq_gather_offset_z): Likewise.
6144 (vldrhq_gather_shifted_offset): Likewise.
6145 (vldrhq_gather_shifted_offset_z): Likewise.
6146 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
6150 (LDRGU_Z): Likewise.
6152 (LDRGS_Z): Likewise.
6154 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
6155 (V_sz_elem1): Likewise.
6156 (VLD1Q): Define iterator.
6157 (VLDRHGOQ): Likewise.
6158 (VLDRHGSOQ): Likewise.
6161 (mve_vldrhq_fv8hf): Define RTL pattern.
6162 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
6163 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
6164 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
6165 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
6166 (mve_vldrhq_<supf><mode>): Likewise.
6167 (mve_vldrhq_z_fv8hf): Likewise.
6168 (mve_vldrhq_z_<supf><mode>): Likewise.
6169 (mve_vldrwq_fv4sf): Likewise.
6170 (mve_vldrwq_<supf>v4si): Likewise.
6171 (mve_vldrwq_z_fv4sf): Likewise.
6172 (mve_vldrwq_z_<supf>v4si): Likewise.
6173 (mve_vld1q_f<mode>): Define RTL expand pattern.
6174 (mve_vld1q_<supf><mode>): Likewise.
6176 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6177 Mihail Ionescu <mihail.ionescu@arm.com>
6178 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6180 * config/arm/arm_mve.h (vld1q_s8): Define macro.
6181 (vld1q_s32): Likewise.
6182 (vld1q_s16): Likewise.
6183 (vld1q_u8): Likewise.
6184 (vld1q_u32): Likewise.
6185 (vld1q_u16): Likewise.
6186 (vldrhq_gather_offset_s32): Likewise.
6187 (vldrhq_gather_offset_s16): Likewise.
6188 (vldrhq_gather_offset_u32): Likewise.
6189 (vldrhq_gather_offset_u16): Likewise.
6190 (vldrhq_gather_offset_z_s32): Likewise.
6191 (vldrhq_gather_offset_z_s16): Likewise.
6192 (vldrhq_gather_offset_z_u32): Likewise.
6193 (vldrhq_gather_offset_z_u16): Likewise.
6194 (vldrhq_gather_shifted_offset_s32): Likewise.
6195 (vldrhq_gather_shifted_offset_s16): Likewise.
6196 (vldrhq_gather_shifted_offset_u32): Likewise.
6197 (vldrhq_gather_shifted_offset_u16): Likewise.
6198 (vldrhq_gather_shifted_offset_z_s32): Likewise.
6199 (vldrhq_gather_shifted_offset_z_s16): Likewise.
6200 (vldrhq_gather_shifted_offset_z_u32): Likewise.
6201 (vldrhq_gather_shifted_offset_z_u16): Likewise.
6202 (vldrhq_s32): Likewise.
6203 (vldrhq_s16): Likewise.
6204 (vldrhq_u32): Likewise.
6205 (vldrhq_u16): Likewise.
6206 (vldrhq_z_s32): Likewise.
6207 (vldrhq_z_s16): Likewise.
6208 (vldrhq_z_u32): Likewise.
6209 (vldrhq_z_u16): Likewise.
6210 (vldrwq_s32): Likewise.
6211 (vldrwq_u32): Likewise.
6212 (vldrwq_z_s32): Likewise.
6213 (vldrwq_z_u32): Likewise.
6214 (vld1q_f32): Likewise.
6215 (vld1q_f16): Likewise.
6216 (vldrhq_f16): Likewise.
6217 (vldrhq_z_f16): Likewise.
6218 (vldrwq_f32): Likewise.
6219 (vldrwq_z_f32): Likewise.
6220 (__arm_vld1q_s8): Define intrinsic.
6221 (__arm_vld1q_s32): Likewise.
6222 (__arm_vld1q_s16): Likewise.
6223 (__arm_vld1q_u8): Likewise.
6224 (__arm_vld1q_u32): Likewise.
6225 (__arm_vld1q_u16): Likewise.
6226 (__arm_vldrhq_gather_offset_s32): Likewise.
6227 (__arm_vldrhq_gather_offset_s16): Likewise.
6228 (__arm_vldrhq_gather_offset_u32): Likewise.
6229 (__arm_vldrhq_gather_offset_u16): Likewise.
6230 (__arm_vldrhq_gather_offset_z_s32): Likewise.
6231 (__arm_vldrhq_gather_offset_z_s16): Likewise.
6232 (__arm_vldrhq_gather_offset_z_u32): Likewise.
6233 (__arm_vldrhq_gather_offset_z_u16): Likewise.
6234 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
6235 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
6236 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
6237 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
6238 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
6239 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
6240 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
6241 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
6242 (__arm_vldrhq_s32): Likewise.
6243 (__arm_vldrhq_s16): Likewise.
6244 (__arm_vldrhq_u32): Likewise.
6245 (__arm_vldrhq_u16): Likewise.
6246 (__arm_vldrhq_z_s32): Likewise.
6247 (__arm_vldrhq_z_s16): Likewise.
6248 (__arm_vldrhq_z_u32): Likewise.
6249 (__arm_vldrhq_z_u16): Likewise.
6250 (__arm_vldrwq_s32): Likewise.
6251 (__arm_vldrwq_u32): Likewise.
6252 (__arm_vldrwq_z_s32): Likewise.
6253 (__arm_vldrwq_z_u32): Likewise.
6254 (__arm_vld1q_f32): Likewise.
6255 (__arm_vld1q_f16): Likewise.
6256 (__arm_vldrwq_f32): Likewise.
6257 (__arm_vldrwq_z_f32): Likewise.
6258 (__arm_vldrhq_z_f16): Likewise.
6259 (__arm_vldrhq_f16): Likewise.
6260 (vld1q): Define polymorphic variant.
6261 (vldrhq_gather_offset): Likewise.
6262 (vldrhq_gather_offset_z): Likewise.
6263 (vldrhq_gather_shifted_offset): Likewise.
6264 (vldrhq_gather_shifted_offset_z): Likewise.
6265 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
6269 (LDRGU_Z): Likewise.
6271 (LDRGS_Z): Likewise.
6273 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
6274 (V_sz_elem1): Likewise.
6275 (VLD1Q): Define iterator.
6276 (VLDRHGOQ): Likewise.
6277 (VLDRHGSOQ): Likewise.
6280 (mve_vldrhq_fv8hf): Define RTL pattern.
6281 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
6282 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
6283 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
6284 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
6285 (mve_vldrhq_<supf><mode>): Likewise.
6286 (mve_vldrhq_z_fv8hf): Likewise.
6287 (mve_vldrhq_z_<supf><mode>): Likewise.
6288 (mve_vldrwq_fv4sf): Likewise.
6289 (mve_vldrwq_<supf>v4si): Likewise.
6290 (mve_vldrwq_z_fv4sf): Likewise.
6291 (mve_vldrwq_z_<supf>v4si): Likewise.
6292 (mve_vld1q_f<mode>): Define RTL expand pattern.
6293 (mve_vld1q_<supf><mode>): Likewise.
6295 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6296 Mihail Ionescu <mihail.ionescu@arm.com>
6297 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6299 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
6301 (LDRGBU_Z_QUALIFIERS): Likewise.
6302 (LDRGS_Z_QUALIFIERS): Likewise.
6303 (LDRGU_Z_QUALIFIERS): Likewise.
6304 (LDRS_Z_QUALIFIERS): Likewise.
6305 (LDRU_Z_QUALIFIERS): Likewise.
6306 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro.
6307 (vldrbq_gather_offset_z_u8): Likewise.
6308 (vldrbq_gather_offset_z_s32): Likewise.
6309 (vldrbq_gather_offset_z_u16): Likewise.
6310 (vldrbq_gather_offset_z_u32): Likewise.
6311 (vldrbq_gather_offset_z_s8): Likewise.
6312 (vldrbq_z_s16): Likewise.
6313 (vldrbq_z_u8): Likewise.
6314 (vldrbq_z_s8): Likewise.
6315 (vldrbq_z_s32): Likewise.
6316 (vldrbq_z_u16): Likewise.
6317 (vldrbq_z_u32): Likewise.
6318 (vldrwq_gather_base_z_u32): Likewise.
6319 (vldrwq_gather_base_z_s32): Likewise.
6320 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic.
6321 (__arm_vldrbq_gather_offset_z_s32): Likewise.
6322 (__arm_vldrbq_gather_offset_z_s16): Likewise.
6323 (__arm_vldrbq_gather_offset_z_u8): Likewise.
6324 (__arm_vldrbq_gather_offset_z_u32): Likewise.
6325 (__arm_vldrbq_gather_offset_z_u16): Likewise.
6326 (__arm_vldrbq_z_s8): Likewise.
6327 (__arm_vldrbq_z_s32): Likewise.
6328 (__arm_vldrbq_z_s16): Likewise.
6329 (__arm_vldrbq_z_u8): Likewise.
6330 (__arm_vldrbq_z_u32): Likewise.
6331 (__arm_vldrbq_z_u16): Likewise.
6332 (__arm_vldrwq_gather_base_z_s32): Likewise.
6333 (__arm_vldrwq_gather_base_z_u32): Likewise.
6334 (vldrbq_gather_offset_z): Define polymorphic variant.
6335 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin
6337 (LDRGBU_Z_QUALIFIERS): Likewise.
6338 (LDRGS_Z_QUALIFIERS): Likewise.
6339 (LDRGU_Z_QUALIFIERS): Likewise.
6340 (LDRS_Z_QUALIFIERS): Likewise.
6341 (LDRU_Z_QUALIFIERS): Likewise.
6342 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define
6344 (mve_vldrbq_z_<supf><mode>): Likewise.
6345 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
6347 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6348 Mihail Ionescu <mihail.ionescu@arm.com>
6349 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6351 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin
6353 (STRU_P_QUALIFIERS): Likewise.
6354 (STRSU_P_QUALIFIERS): Likewise.
6355 (STRSS_P_QUALIFIERS): Likewise.
6356 (STRSBS_P_QUALIFIERS): Likewise.
6357 (STRSBU_P_QUALIFIERS): Likewise.
6358 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro.
6359 (vstrbq_p_s32): Likewise.
6360 (vstrbq_p_s16): Likewise.
6361 (vstrbq_p_u8): Likewise.
6362 (vstrbq_p_u32): Likewise.
6363 (vstrbq_p_u16): Likewise.
6364 (vstrbq_scatter_offset_p_s8): Likewise.
6365 (vstrbq_scatter_offset_p_s32): Likewise.
6366 (vstrbq_scatter_offset_p_s16): Likewise.
6367 (vstrbq_scatter_offset_p_u8): Likewise.
6368 (vstrbq_scatter_offset_p_u32): Likewise.
6369 (vstrbq_scatter_offset_p_u16): Likewise.
6370 (vstrwq_scatter_base_p_s32): Likewise.
6371 (vstrwq_scatter_base_p_u32): Likewise.
6372 (__arm_vstrbq_p_s8): Define intrinsic.
6373 (__arm_vstrbq_p_s32): Likewise.
6374 (__arm_vstrbq_p_s16): Likewise.
6375 (__arm_vstrbq_p_u8): Likewise.
6376 (__arm_vstrbq_p_u32): Likewise.
6377 (__arm_vstrbq_p_u16): Likewise.
6378 (__arm_vstrbq_scatter_offset_p_s8): Likewise.
6379 (__arm_vstrbq_scatter_offset_p_s32): Likewise.
6380 (__arm_vstrbq_scatter_offset_p_s16): Likewise.
6381 (__arm_vstrbq_scatter_offset_p_u8): Likewise.
6382 (__arm_vstrbq_scatter_offset_p_u32): Likewise.
6383 (__arm_vstrbq_scatter_offset_p_u16): Likewise.
6384 (__arm_vstrwq_scatter_base_p_s32): Likewise.
6385 (__arm_vstrwq_scatter_base_p_u32): Likewise.
6386 (vstrbq_p): Define polymorphic variant.
6387 (vstrbq_scatter_offset_p): Likewise.
6388 (vstrwq_scatter_base_p): Likewise.
6389 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin
6391 (STRU_P_QUALIFIERS): Likewise.
6392 (STRSU_P_QUALIFIERS): Likewise.
6393 (STRSS_P_QUALIFIERS): Likewise.
6394 (STRSBS_P_QUALIFIERS): Likewise.
6395 (STRSBU_P_QUALIFIERS): Likewise.
6396 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define
6398 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
6399 (mve_vstrbq_p_<supf><mode>): Likewise.
6401 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6402 Mihail Ionescu <mihail.ionescu@arm.com>
6403 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6405 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin
6407 (LDRGS_QUALIFIERS): Likewise.
6408 (LDRS_QUALIFIERS): Likewise.
6409 (LDRU_QUALIFIERS): Likewise.
6410 (LDRGBS_QUALIFIERS): Likewise.
6411 (LDRGBU_QUALIFIERS): Likewise.
6412 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro.
6413 (vldrbq_gather_offset_s8): Likewise.
6414 (vldrbq_s8): Likewise.
6415 (vldrbq_u8): Likewise.
6416 (vldrbq_gather_offset_u16): Likewise.
6417 (vldrbq_gather_offset_s16): Likewise.
6418 (vldrbq_s16): Likewise.
6419 (vldrbq_u16): Likewise.
6420 (vldrbq_gather_offset_u32): Likewise.
6421 (vldrbq_gather_offset_s32): Likewise.
6422 (vldrbq_s32): Likewise.
6423 (vldrbq_u32): Likewise.
6424 (vldrwq_gather_base_s32): Likewise.
6425 (vldrwq_gather_base_u32): Likewise.
6426 (__arm_vldrbq_gather_offset_u8): Define intrinsic.
6427 (__arm_vldrbq_gather_offset_s8): Likewise.
6428 (__arm_vldrbq_s8): Likewise.
6429 (__arm_vldrbq_u8): Likewise.
6430 (__arm_vldrbq_gather_offset_u16): Likewise.
6431 (__arm_vldrbq_gather_offset_s16): Likewise.
6432 (__arm_vldrbq_s16): Likewise.
6433 (__arm_vldrbq_u16): Likewise.
6434 (__arm_vldrbq_gather_offset_u32): Likewise.
6435 (__arm_vldrbq_gather_offset_s32): Likewise.
6436 (__arm_vldrbq_s32): Likewise.
6437 (__arm_vldrbq_u32): Likewise.
6438 (__arm_vldrwq_gather_base_s32): Likewise.
6439 (__arm_vldrwq_gather_base_u32): Likewise.
6440 (vldrbq_gather_offset): Define polymorphic variant.
6441 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin
6443 (LDRGS_QUALIFIERS): Likewise.
6444 (LDRS_QUALIFIERS): Likewise.
6445 (LDRU_QUALIFIERS): Likewise.
6446 (LDRGBS_QUALIFIERS): Likewise.
6447 (LDRGBU_QUALIFIERS): Likewise.
6448 * config/arm/mve.md (VLDRBGOQ): Define iterator.
6450 (VLDRWGBQ): Likewise.
6451 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern.
6452 (mve_vldrbq_<supf><mode>): Likewise.
6453 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
6455 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6456 Mihail Ionescu <mihail.ionescu@arm.com>
6457 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6459 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier.
6460 (STRU_QUALIFIERS): Likewise.
6461 (STRSS_QUALIFIERS): Likewise.
6462 (STRSU_QUALIFIERS): Likewise.
6463 (STRSBS_QUALIFIERS): Likewise.
6464 (STRSBU_QUALIFIERS): Likewise.
6465 * config/arm/arm_mve.h (vstrbq_s8): Define macro.
6466 (vstrbq_u8): Likewise.
6467 (vstrbq_u16): Likewise.
6468 (vstrbq_scatter_offset_s8): Likewise.
6469 (vstrbq_scatter_offset_u8): Likewise.
6470 (vstrbq_scatter_offset_u16): Likewise.
6471 (vstrbq_s16): Likewise.
6472 (vstrbq_u32): Likewise.
6473 (vstrbq_scatter_offset_s16): Likewise.
6474 (vstrbq_scatter_offset_u32): Likewise.
6475 (vstrbq_s32): Likewise.
6476 (vstrbq_scatter_offset_s32): Likewise.
6477 (vstrwq_scatter_base_s32): Likewise.
6478 (vstrwq_scatter_base_u32): Likewise.
6479 (__arm_vstrbq_scatter_offset_s8): Define intrinsic.
6480 (__arm_vstrbq_scatter_offset_s32): Likewise.
6481 (__arm_vstrbq_scatter_offset_s16): Likewise.
6482 (__arm_vstrbq_scatter_offset_u8): Likewise.
6483 (__arm_vstrbq_scatter_offset_u32): Likewise.
6484 (__arm_vstrbq_scatter_offset_u16): Likewise.
6485 (__arm_vstrbq_s8): Likewise.
6486 (__arm_vstrbq_s32): Likewise.
6487 (__arm_vstrbq_s16): Likewise.
6488 (__arm_vstrbq_u8): Likewise.
6489 (__arm_vstrbq_u32): Likewise.
6490 (__arm_vstrbq_u16): Likewise.
6491 (__arm_vstrwq_scatter_base_s32): Likewise.
6492 (__arm_vstrwq_scatter_base_u32): Likewise.
6493 (vstrbq): Define polymorphic variant.
6494 (vstrbq_scatter_offset): Likewise.
6495 (vstrwq_scatter_base): Likewise.
6496 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin
6498 (STRU_QUALIFIERS): Likewise.
6499 (STRSS_QUALIFIERS): Likewise.
6500 (STRSU_QUALIFIERS): Likewise.
6501 (STRSBS_QUALIFIERS): Likewise.
6502 (STRSBU_QUALIFIERS): Likewise.
6503 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator.
6504 (VSTRWSBQ): Define iterators.
6505 (VSTRBSOQ): Likewise.
6507 (mve_vstrbq_<supf><mode>): Define RTL pattern.
6508 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise.
6509 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
6511 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6512 Mihail Ionescu <mihail.ionescu@arm.com>
6513 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6515 * config/arm/arm_mve.h (vabdq_m_f32): Define macro.
6516 (vabdq_m_f16): Likewise.
6517 (vaddq_m_f32): Likewise.
6518 (vaddq_m_f16): Likewise.
6519 (vaddq_m_n_f32): Likewise.
6520 (vaddq_m_n_f16): Likewise.
6521 (vandq_m_f32): Likewise.
6522 (vandq_m_f16): Likewise.
6523 (vbicq_m_f32): Likewise.
6524 (vbicq_m_f16): Likewise.
6525 (vbrsrq_m_n_f32): Likewise.
6526 (vbrsrq_m_n_f16): Likewise.
6527 (vcaddq_rot270_m_f32): Likewise.
6528 (vcaddq_rot270_m_f16): Likewise.
6529 (vcaddq_rot90_m_f32): Likewise.
6530 (vcaddq_rot90_m_f16): Likewise.
6531 (vcmlaq_m_f32): Likewise.
6532 (vcmlaq_m_f16): Likewise.
6533 (vcmlaq_rot180_m_f32): Likewise.
6534 (vcmlaq_rot180_m_f16): Likewise.
6535 (vcmlaq_rot270_m_f32): Likewise.
6536 (vcmlaq_rot270_m_f16): Likewise.
6537 (vcmlaq_rot90_m_f32): Likewise.
6538 (vcmlaq_rot90_m_f16): Likewise.
6539 (vcmulq_m_f32): Likewise.
6540 (vcmulq_m_f16): Likewise.
6541 (vcmulq_rot180_m_f32): Likewise.
6542 (vcmulq_rot180_m_f16): Likewise.
6543 (vcmulq_rot270_m_f32): Likewise.
6544 (vcmulq_rot270_m_f16): Likewise.
6545 (vcmulq_rot90_m_f32): Likewise.
6546 (vcmulq_rot90_m_f16): Likewise.
6547 (vcvtq_m_n_s32_f32): Likewise.
6548 (vcvtq_m_n_s16_f16): Likewise.
6549 (vcvtq_m_n_u32_f32): Likewise.
6550 (vcvtq_m_n_u16_f16): Likewise.
6551 (veorq_m_f32): Likewise.
6552 (veorq_m_f16): Likewise.
6553 (vfmaq_m_f32): Likewise.
6554 (vfmaq_m_f16): Likewise.
6555 (vfmaq_m_n_f32): Likewise.
6556 (vfmaq_m_n_f16): Likewise.
6557 (vfmasq_m_n_f32): Likewise.
6558 (vfmasq_m_n_f16): Likewise.
6559 (vfmsq_m_f32): Likewise.
6560 (vfmsq_m_f16): Likewise.
6561 (vmaxnmq_m_f32): Likewise.
6562 (vmaxnmq_m_f16): Likewise.
6563 (vminnmq_m_f32): Likewise.
6564 (vminnmq_m_f16): Likewise.
6565 (vmulq_m_f32): Likewise.
6566 (vmulq_m_f16): Likewise.
6567 (vmulq_m_n_f32): Likewise.
6568 (vmulq_m_n_f16): Likewise.
6569 (vornq_m_f32): Likewise.
6570 (vornq_m_f16): Likewise.
6571 (vorrq_m_f32): Likewise.
6572 (vorrq_m_f16): Likewise.
6573 (vsubq_m_f32): Likewise.
6574 (vsubq_m_f16): Likewise.
6575 (vsubq_m_n_f32): Likewise.
6576 (vsubq_m_n_f16): Likewise.
6577 (__attribute__): Likewise.
6578 (__arm_vabdq_m_f32): Likewise.
6579 (__arm_vabdq_m_f16): Likewise.
6580 (__arm_vaddq_m_f32): Likewise.
6581 (__arm_vaddq_m_f16): Likewise.
6582 (__arm_vaddq_m_n_f32): Likewise.
6583 (__arm_vaddq_m_n_f16): Likewise.
6584 (__arm_vandq_m_f32): Likewise.
6585 (__arm_vandq_m_f16): Likewise.
6586 (__arm_vbicq_m_f32): Likewise.
6587 (__arm_vbicq_m_f16): Likewise.
6588 (__arm_vbrsrq_m_n_f32): Likewise.
6589 (__arm_vbrsrq_m_n_f16): Likewise.
6590 (__arm_vcaddq_rot270_m_f32): Likewise.
6591 (__arm_vcaddq_rot270_m_f16): Likewise.
6592 (__arm_vcaddq_rot90_m_f32): Likewise.
6593 (__arm_vcaddq_rot90_m_f16): Likewise.
6594 (__arm_vcmlaq_m_f32): Likewise.
6595 (__arm_vcmlaq_m_f16): Likewise.
6596 (__arm_vcmlaq_rot180_m_f32): Likewise.
6597 (__arm_vcmlaq_rot180_m_f16): Likewise.
6598 (__arm_vcmlaq_rot270_m_f32): Likewise.
6599 (__arm_vcmlaq_rot270_m_f16): Likewise.
6600 (__arm_vcmlaq_rot90_m_f32): Likewise.
6601 (__arm_vcmlaq_rot90_m_f16): Likewise.
6602 (__arm_vcmulq_m_f32): Likewise.
6603 (__arm_vcmulq_m_f16): Likewise.
6604 (__arm_vcmulq_rot180_m_f32): Define intrinsic.
6605 (__arm_vcmulq_rot180_m_f16): Likewise.
6606 (__arm_vcmulq_rot270_m_f32): Likewise.
6607 (__arm_vcmulq_rot270_m_f16): Likewise.
6608 (__arm_vcmulq_rot90_m_f32): Likewise.
6609 (__arm_vcmulq_rot90_m_f16): Likewise.
6610 (__arm_vcvtq_m_n_s32_f32): Likewise.
6611 (__arm_vcvtq_m_n_s16_f16): Likewise.
6612 (__arm_vcvtq_m_n_u32_f32): Likewise.
6613 (__arm_vcvtq_m_n_u16_f16): Likewise.
6614 (__arm_veorq_m_f32): Likewise.
6615 (__arm_veorq_m_f16): Likewise.
6616 (__arm_vfmaq_m_f32): Likewise.
6617 (__arm_vfmaq_m_f16): Likewise.
6618 (__arm_vfmaq_m_n_f32): Likewise.
6619 (__arm_vfmaq_m_n_f16): Likewise.
6620 (__arm_vfmasq_m_n_f32): Likewise.
6621 (__arm_vfmasq_m_n_f16): Likewise.
6622 (__arm_vfmsq_m_f32): Likewise.
6623 (__arm_vfmsq_m_f16): Likewise.
6624 (__arm_vmaxnmq_m_f32): Likewise.
6625 (__arm_vmaxnmq_m_f16): Likewise.
6626 (__arm_vminnmq_m_f32): Likewise.
6627 (__arm_vminnmq_m_f16): Likewise.
6628 (__arm_vmulq_m_f32): Likewise.
6629 (__arm_vmulq_m_f16): Likewise.
6630 (__arm_vmulq_m_n_f32): Likewise.
6631 (__arm_vmulq_m_n_f16): Likewise.
6632 (__arm_vornq_m_f32): Likewise.
6633 (__arm_vornq_m_f16): Likewise.
6634 (__arm_vorrq_m_f32): Likewise.
6635 (__arm_vorrq_m_f16): Likewise.
6636 (__arm_vsubq_m_f32): Likewise.
6637 (__arm_vsubq_m_f16): Likewise.
6638 (__arm_vsubq_m_n_f32): Likewise.
6639 (__arm_vsubq_m_n_f16): Likewise.
6640 (vabdq_m): Define polymorphic variant.
6641 (vaddq_m): Likewise.
6642 (vaddq_m_n): Likewise.
6643 (vandq_m): Likewise.
6644 (vbicq_m): Likewise.
6645 (vbrsrq_m_n): Likewise.
6646 (vcaddq_rot270_m): Likewise.
6647 (vcaddq_rot90_m): Likewise.
6648 (vcmlaq_m): Likewise.
6649 (vcmlaq_rot180_m): Likewise.
6650 (vcmlaq_rot270_m): Likewise.
6651 (vcmlaq_rot90_m): Likewise.
6652 (vcmulq_m): Likewise.
6653 (vcmulq_rot180_m): Likewise.
6654 (vcmulq_rot270_m): Likewise.
6655 (vcmulq_rot90_m): Likewise.
6656 (veorq_m): Likewise.
6657 (vfmaq_m): Likewise.
6658 (vfmaq_m_n): Likewise.
6659 (vfmasq_m_n): Likewise.
6660 (vfmsq_m): Likewise.
6661 (vmaxnmq_m): Likewise.
6662 (vminnmq_m): Likewise.
6663 (vmulq_m): Likewise.
6664 (vmulq_m_n): Likewise.
6665 (vornq_m): Likewise.
6666 (vsubq_m): Likewise.
6667 (vsubq_m_n): Likewise.
6668 (vorrq_m): Likewise.
6669 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
6671 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
6672 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
6673 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern.
6674 (mve_vaddq_m_f<mode>): Likewise.
6675 (mve_vaddq_m_n_f<mode>): Likewise.
6676 (mve_vandq_m_f<mode>): Likewise.
6677 (mve_vbicq_m_f<mode>): Likewise.
6678 (mve_vbrsrq_m_n_f<mode>): Likewise.
6679 (mve_vcaddq_rot270_m_f<mode>): Likewise.
6680 (mve_vcaddq_rot90_m_f<mode>): Likewise.
6681 (mve_vcmlaq_m_f<mode>): Likewise.
6682 (mve_vcmlaq_rot180_m_f<mode>): Likewise.
6683 (mve_vcmlaq_rot270_m_f<mode>): Likewise.
6684 (mve_vcmlaq_rot90_m_f<mode>): Likewise.
6685 (mve_vcmulq_m_f<mode>): Likewise.
6686 (mve_vcmulq_rot180_m_f<mode>): Likewise.
6687 (mve_vcmulq_rot270_m_f<mode>): Likewise.
6688 (mve_vcmulq_rot90_m_f<mode>): Likewise.
6689 (mve_veorq_m_f<mode>): Likewise.
6690 (mve_vfmaq_m_f<mode>): Likewise.
6691 (mve_vfmaq_m_n_f<mode>): Likewise.
6692 (mve_vfmasq_m_n_f<mode>): Likewise.
6693 (mve_vfmsq_m_f<mode>): Likewise.
6694 (mve_vmaxnmq_m_f<mode>): Likewise.
6695 (mve_vminnmq_m_f<mode>): Likewise.
6696 (mve_vmulq_m_f<mode>): Likewise.
6697 (mve_vmulq_m_n_f<mode>): Likewise.
6698 (mve_vornq_m_f<mode>): Likewise.
6699 (mve_vorrq_m_f<mode>): Likewise.
6700 (mve_vsubq_m_f<mode>): Likewise.
6701 (mve_vsubq_m_n_f<mode>): Likewise.
6703 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6704 Mihail Ionescu <mihail.ionescu@arm.com>
6705 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6707 * config/arm/arm-protos.h (arm_mve_immediate_check):
6708 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check
6709 mode and interger value.
6710 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
6711 (vmlaldavaq_p_s16): Likewise.
6712 (vmlaldavaq_p_u32): Likewise.
6713 (vmlaldavaq_p_u16): Likewise.
6714 (vmlaldavaxq_p_s32): Likewise.
6715 (vmlaldavaxq_p_s16): Likewise.
6716 (vmlaldavaxq_p_u32): Likewise.
6717 (vmlaldavaxq_p_u16): Likewise.
6718 (vmlsldavaq_p_s32): Likewise.
6719 (vmlsldavaq_p_s16): Likewise.
6720 (vmlsldavaxq_p_s32): Likewise.
6721 (vmlsldavaxq_p_s16): Likewise.
6722 (vmullbq_poly_m_p8): Likewise.
6723 (vmullbq_poly_m_p16): Likewise.
6724 (vmulltq_poly_m_p8): Likewise.
6725 (vmulltq_poly_m_p16): Likewise.
6726 (vqdmullbq_m_n_s32): Likewise.
6727 (vqdmullbq_m_n_s16): Likewise.
6728 (vqdmullbq_m_s32): Likewise.
6729 (vqdmullbq_m_s16): Likewise.
6730 (vqdmulltq_m_n_s32): Likewise.
6731 (vqdmulltq_m_n_s16): Likewise.
6732 (vqdmulltq_m_s32): Likewise.
6733 (vqdmulltq_m_s16): Likewise.
6734 (vqrshrnbq_m_n_s32): Likewise.
6735 (vqrshrnbq_m_n_s16): Likewise.
6736 (vqrshrnbq_m_n_u32): Likewise.
6737 (vqrshrnbq_m_n_u16): Likewise.
6738 (vqrshrntq_m_n_s32): Likewise.
6739 (vqrshrntq_m_n_s16): Likewise.
6740 (vqrshrntq_m_n_u32): Likewise.
6741 (vqrshrntq_m_n_u16): Likewise.
6742 (vqrshrunbq_m_n_s32): Likewise.
6743 (vqrshrunbq_m_n_s16): Likewise.
6744 (vqrshruntq_m_n_s32): Likewise.
6745 (vqrshruntq_m_n_s16): Likewise.
6746 (vqshrnbq_m_n_s32): Likewise.
6747 (vqshrnbq_m_n_s16): Likewise.
6748 (vqshrnbq_m_n_u32): Likewise.
6749 (vqshrnbq_m_n_u16): Likewise.
6750 (vqshrntq_m_n_s32): Likewise.
6751 (vqshrntq_m_n_s16): Likewise.
6752 (vqshrntq_m_n_u32): Likewise.
6753 (vqshrntq_m_n_u16): Likewise.
6754 (vqshrunbq_m_n_s32): Likewise.
6755 (vqshrunbq_m_n_s16): Likewise.
6756 (vqshruntq_m_n_s32): Likewise.
6757 (vqshruntq_m_n_s16): Likewise.
6758 (vrmlaldavhaq_p_s32): Likewise.
6759 (vrmlaldavhaq_p_u32): Likewise.
6760 (vrmlaldavhaxq_p_s32): Likewise.
6761 (vrmlsldavhaq_p_s32): Likewise.
6762 (vrmlsldavhaxq_p_s32): Likewise.
6763 (vrshrnbq_m_n_s32): Likewise.
6764 (vrshrnbq_m_n_s16): Likewise.
6765 (vrshrnbq_m_n_u32): Likewise.
6766 (vrshrnbq_m_n_u16): Likewise.
6767 (vrshrntq_m_n_s32): Likewise.
6768 (vrshrntq_m_n_s16): Likewise.
6769 (vrshrntq_m_n_u32): Likewise.
6770 (vrshrntq_m_n_u16): Likewise.
6771 (vshllbq_m_n_s8): Likewise.
6772 (vshllbq_m_n_s16): Likewise.
6773 (vshllbq_m_n_u8): Likewise.
6774 (vshllbq_m_n_u16): Likewise.
6775 (vshlltq_m_n_s8): Likewise.
6776 (vshlltq_m_n_s16): Likewise.
6777 (vshlltq_m_n_u8): Likewise.
6778 (vshlltq_m_n_u16): Likewise.
6779 (vshrnbq_m_n_s32): Likewise.
6780 (vshrnbq_m_n_s16): Likewise.
6781 (vshrnbq_m_n_u32): Likewise.
6782 (vshrnbq_m_n_u16): Likewise.
6783 (vshrntq_m_n_s32): Likewise.
6784 (vshrntq_m_n_s16): Likewise.
6785 (vshrntq_m_n_u32): Likewise.
6786 (vshrntq_m_n_u16): Likewise.
6787 (__arm_vmlaldavaq_p_s32): Define intrinsic.
6788 (__arm_vmlaldavaq_p_s16): Likewise.
6789 (__arm_vmlaldavaq_p_u32): Likewise.
6790 (__arm_vmlaldavaq_p_u16): Likewise.
6791 (__arm_vmlaldavaxq_p_s32): Likewise.
6792 (__arm_vmlaldavaxq_p_s16): Likewise.
6793 (__arm_vmlaldavaxq_p_u32): Likewise.
6794 (__arm_vmlaldavaxq_p_u16): Likewise.
6795 (__arm_vmlsldavaq_p_s32): Likewise.
6796 (__arm_vmlsldavaq_p_s16): Likewise.
6797 (__arm_vmlsldavaxq_p_s32): Likewise.
6798 (__arm_vmlsldavaxq_p_s16): Likewise.
6799 (__arm_vmullbq_poly_m_p8): Likewise.
6800 (__arm_vmullbq_poly_m_p16): Likewise.
6801 (__arm_vmulltq_poly_m_p8): Likewise.
6802 (__arm_vmulltq_poly_m_p16): Likewise.
6803 (__arm_vqdmullbq_m_n_s32): Likewise.
6804 (__arm_vqdmullbq_m_n_s16): Likewise.
6805 (__arm_vqdmullbq_m_s32): Likewise.
6806 (__arm_vqdmullbq_m_s16): Likewise.
6807 (__arm_vqdmulltq_m_n_s32): Likewise.
6808 (__arm_vqdmulltq_m_n_s16): Likewise.
6809 (__arm_vqdmulltq_m_s32): Likewise.
6810 (__arm_vqdmulltq_m_s16): Likewise.
6811 (__arm_vqrshrnbq_m_n_s32): Likewise.
6812 (__arm_vqrshrnbq_m_n_s16): Likewise.
6813 (__arm_vqrshrnbq_m_n_u32): Likewise.
6814 (__arm_vqrshrnbq_m_n_u16): Likewise.
6815 (__arm_vqrshrntq_m_n_s32): Likewise.
6816 (__arm_vqrshrntq_m_n_s16): Likewise.
6817 (__arm_vqrshrntq_m_n_u32): Likewise.
6818 (__arm_vqrshrntq_m_n_u16): Likewise.
6819 (__arm_vqrshrunbq_m_n_s32): Likewise.
6820 (__arm_vqrshrunbq_m_n_s16): Likewise.
6821 (__arm_vqrshruntq_m_n_s32): Likewise.
6822 (__arm_vqrshruntq_m_n_s16): Likewise.
6823 (__arm_vqshrnbq_m_n_s32): Likewise.
6824 (__arm_vqshrnbq_m_n_s16): Likewise.
6825 (__arm_vqshrnbq_m_n_u32): Likewise.
6826 (__arm_vqshrnbq_m_n_u16): Likewise.
6827 (__arm_vqshrntq_m_n_s32): Likewise.
6828 (__arm_vqshrntq_m_n_s16): Likewise.
6829 (__arm_vqshrntq_m_n_u32): Likewise.
6830 (__arm_vqshrntq_m_n_u16): Likewise.
6831 (__arm_vqshrunbq_m_n_s32): Likewise.
6832 (__arm_vqshrunbq_m_n_s16): Likewise.
6833 (__arm_vqshruntq_m_n_s32): Likewise.
6834 (__arm_vqshruntq_m_n_s16): Likewise.
6835 (__arm_vrmlaldavhaq_p_s32): Likewise.
6836 (__arm_vrmlaldavhaq_p_u32): Likewise.
6837 (__arm_vrmlaldavhaxq_p_s32): Likewise.
6838 (__arm_vrmlsldavhaq_p_s32): Likewise.
6839 (__arm_vrmlsldavhaxq_p_s32): Likewise.
6840 (__arm_vrshrnbq_m_n_s32): Likewise.
6841 (__arm_vrshrnbq_m_n_s16): Likewise.
6842 (__arm_vrshrnbq_m_n_u32): Likewise.
6843 (__arm_vrshrnbq_m_n_u16): Likewise.
6844 (__arm_vrshrntq_m_n_s32): Likewise.
6845 (__arm_vrshrntq_m_n_s16): Likewise.
6846 (__arm_vrshrntq_m_n_u32): Likewise.
6847 (__arm_vrshrntq_m_n_u16): Likewise.
6848 (__arm_vshllbq_m_n_s8): Likewise.
6849 (__arm_vshllbq_m_n_s16): Likewise.
6850 (__arm_vshllbq_m_n_u8): Likewise.
6851 (__arm_vshllbq_m_n_u16): Likewise.
6852 (__arm_vshlltq_m_n_s8): Likewise.
6853 (__arm_vshlltq_m_n_s16): Likewise.
6854 (__arm_vshlltq_m_n_u8): Likewise.
6855 (__arm_vshlltq_m_n_u16): Likewise.
6856 (__arm_vshrnbq_m_n_s32): Likewise.
6857 (__arm_vshrnbq_m_n_s16): Likewise.
6858 (__arm_vshrnbq_m_n_u32): Likewise.
6859 (__arm_vshrnbq_m_n_u16): Likewise.
6860 (__arm_vshrntq_m_n_s32): Likewise.
6861 (__arm_vshrntq_m_n_s16): Likewise.
6862 (__arm_vshrntq_m_n_u32): Likewise.
6863 (__arm_vshrntq_m_n_u16): Likewise.
6864 (vmullbq_poly_m): Define polymorphic variant.
6865 (vmulltq_poly_m): Likewise.
6866 (vshllbq_m): Likewise.
6867 (vshrntq_m_n): Likewise.
6868 (vshrnbq_m_n): Likewise.
6869 (vshlltq_m_n): Likewise.
6870 (vshllbq_m_n): Likewise.
6871 (vrshrntq_m_n): Likewise.
6872 (vrshrnbq_m_n): Likewise.
6873 (vqshruntq_m_n): Likewise.
6874 (vqshrunbq_m_n): Likewise.
6875 (vqdmullbq_m_n): Likewise.
6876 (vqdmullbq_m): Likewise.
6877 (vqdmulltq_m_n): Likewise.
6878 (vqdmulltq_m): Likewise.
6879 (vqrshrnbq_m_n): Likewise.
6880 (vqrshrntq_m_n): Likewise.
6881 (vqrshrunbq_m_n): Likewise.
6882 (vqrshruntq_m_n): Likewise.
6883 (vqshrnbq_m_n): Likewise.
6884 (vqshrntq_m_n): Likewise.
6885 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
6887 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
6888 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
6889 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
6890 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
6891 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
6892 (VMLALDAVAXQ_P): Likewise.
6893 (VQRSHRNBQ_M_N): Likewise.
6894 (VQRSHRNTQ_M_N): Likewise.
6895 (VQSHRNBQ_M_N): Likewise.
6896 (VQSHRNTQ_M_N): Likewise.
6897 (VRSHRNBQ_M_N): Likewise.
6898 (VRSHRNTQ_M_N): Likewise.
6899 (VSHLLBQ_M_N): Likewise.
6900 (VSHLLTQ_M_N): Likewise.
6901 (VSHRNBQ_M_N): Likewise.
6902 (VSHRNTQ_M_N): Likewise.
6903 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
6904 (mve_vmlaldavaxq_p_<supf><mode>): Likewise.
6905 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
6906 (mve_vqrshrntq_m_n_<supf><mode>): Likewise.
6907 (mve_vqshrnbq_m_n_<supf><mode>): Likewise.
6908 (mve_vqshrntq_m_n_<supf><mode>): Likewise.
6909 (mve_vrmlaldavhaq_p_sv4si): Likewise.
6910 (mve_vrshrnbq_m_n_<supf><mode>): Likewise.
6911 (mve_vrshrntq_m_n_<supf><mode>): Likewise.
6912 (mve_vshllbq_m_n_<supf><mode>): Likewise.
6913 (mve_vshlltq_m_n_<supf><mode>): Likewise.
6914 (mve_vshrnbq_m_n_<supf><mode>): Likewise.
6915 (mve_vshrntq_m_n_<supf><mode>): Likewise.
6916 (mve_vmlsldavaq_p_s<mode>): Likewise.
6917 (mve_vmlsldavaxq_p_s<mode>): Likewise.
6918 (mve_vmullbq_poly_m_p<mode>): Likewise.
6919 (mve_vmulltq_poly_m_p<mode>): Likewise.
6920 (mve_vqdmullbq_m_n_s<mode>): Likewise.
6921 (mve_vqdmullbq_m_s<mode>): Likewise.
6922 (mve_vqdmulltq_m_n_s<mode>): Likewise.
6923 (mve_vqdmulltq_m_s<mode>): Likewise.
6924 (mve_vqrshrunbq_m_n_s<mode>): Likewise.
6925 (mve_vqrshruntq_m_n_s<mode>): Likewise.
6926 (mve_vqshrunbq_m_n_s<mode>): Likewise.
6927 (mve_vqshruntq_m_n_s<mode>): Likewise.
6928 (mve_vrmlaldavhaq_p_uv4si): Likewise.
6929 (mve_vrmlaldavhaxq_p_sv4si): Likewise.
6930 (mve_vrmlsldavhaq_p_sv4si): Likewise.
6931 (mve_vrmlsldavhaxq_p_sv4si): Likewise.
6933 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6934 Mihail Ionescu <mihail.ionescu@arm.com>
6935 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6937 * config/arm/arm_mve.h (vabdq_m_s8): Define macro.
6938 (vabdq_m_s32): Likewise.
6939 (vabdq_m_s16): Likewise.
6940 (vabdq_m_u8): Likewise.
6941 (vabdq_m_u32): Likewise.
6942 (vabdq_m_u16): Likewise.
6943 (vaddq_m_n_s8): Likewise.
6944 (vaddq_m_n_s32): Likewise.
6945 (vaddq_m_n_s16): Likewise.
6946 (vaddq_m_n_u8): Likewise.
6947 (vaddq_m_n_u32): Likewise.
6948 (vaddq_m_n_u16): Likewise.
6949 (vaddq_m_s8): Likewise.
6950 (vaddq_m_s32): Likewise.
6951 (vaddq_m_s16): Likewise.
6952 (vaddq_m_u8): Likewise.
6953 (vaddq_m_u32): Likewise.
6954 (vaddq_m_u16): Likewise.
6955 (vandq_m_s8): Likewise.
6956 (vandq_m_s32): Likewise.
6957 (vandq_m_s16): Likewise.
6958 (vandq_m_u8): Likewise.
6959 (vandq_m_u32): Likewise.
6960 (vandq_m_u16): Likewise.
6961 (vbicq_m_s8): Likewise.
6962 (vbicq_m_s32): Likewise.
6963 (vbicq_m_s16): Likewise.
6964 (vbicq_m_u8): Likewise.
6965 (vbicq_m_u32): Likewise.
6966 (vbicq_m_u16): Likewise.
6967 (vbrsrq_m_n_s8): Likewise.
6968 (vbrsrq_m_n_s32): Likewise.
6969 (vbrsrq_m_n_s16): Likewise.
6970 (vbrsrq_m_n_u8): Likewise.
6971 (vbrsrq_m_n_u32): Likewise.
6972 (vbrsrq_m_n_u16): Likewise.
6973 (vcaddq_rot270_m_s8): Likewise.
6974 (vcaddq_rot270_m_s32): Likewise.
6975 (vcaddq_rot270_m_s16): Likewise.
6976 (vcaddq_rot270_m_u8): Likewise.
6977 (vcaddq_rot270_m_u32): Likewise.
6978 (vcaddq_rot270_m_u16): Likewise.
6979 (vcaddq_rot90_m_s8): Likewise.
6980 (vcaddq_rot90_m_s32): Likewise.
6981 (vcaddq_rot90_m_s16): Likewise.
6982 (vcaddq_rot90_m_u8): Likewise.
6983 (vcaddq_rot90_m_u32): Likewise.
6984 (vcaddq_rot90_m_u16): Likewise.
6985 (veorq_m_s8): Likewise.
6986 (veorq_m_s32): Likewise.
6987 (veorq_m_s16): Likewise.
6988 (veorq_m_u8): Likewise.
6989 (veorq_m_u32): Likewise.
6990 (veorq_m_u16): Likewise.
6991 (vhaddq_m_n_s8): Likewise.
6992 (vhaddq_m_n_s32): Likewise.
6993 (vhaddq_m_n_s16): Likewise.
6994 (vhaddq_m_n_u8): Likewise.
6995 (vhaddq_m_n_u32): Likewise.
6996 (vhaddq_m_n_u16): Likewise.
6997 (vhaddq_m_s8): Likewise.
6998 (vhaddq_m_s32): Likewise.
6999 (vhaddq_m_s16): Likewise.
7000 (vhaddq_m_u8): Likewise.
7001 (vhaddq_m_u32): Likewise.
7002 (vhaddq_m_u16): Likewise.
7003 (vhcaddq_rot270_m_s8): Likewise.
7004 (vhcaddq_rot270_m_s32): Likewise.
7005 (vhcaddq_rot270_m_s16): Likewise.
7006 (vhcaddq_rot90_m_s8): Likewise.
7007 (vhcaddq_rot90_m_s32): Likewise.
7008 (vhcaddq_rot90_m_s16): Likewise.
7009 (vhsubq_m_n_s8): Likewise.
7010 (vhsubq_m_n_s32): Likewise.
7011 (vhsubq_m_n_s16): Likewise.
7012 (vhsubq_m_n_u8): Likewise.
7013 (vhsubq_m_n_u32): Likewise.
7014 (vhsubq_m_n_u16): Likewise.
7015 (vhsubq_m_s8): Likewise.
7016 (vhsubq_m_s32): Likewise.
7017 (vhsubq_m_s16): Likewise.
7018 (vhsubq_m_u8): Likewise.
7019 (vhsubq_m_u32): Likewise.
7020 (vhsubq_m_u16): Likewise.
7021 (vmaxq_m_s8): Likewise.
7022 (vmaxq_m_s32): Likewise.
7023 (vmaxq_m_s16): Likewise.
7024 (vmaxq_m_u8): Likewise.
7025 (vmaxq_m_u32): Likewise.
7026 (vmaxq_m_u16): Likewise.
7027 (vminq_m_s8): Likewise.
7028 (vminq_m_s32): Likewise.
7029 (vminq_m_s16): Likewise.
7030 (vminq_m_u8): Likewise.
7031 (vminq_m_u32): Likewise.
7032 (vminq_m_u16): Likewise.
7033 (vmladavaq_p_s8): Likewise.
7034 (vmladavaq_p_s32): Likewise.
7035 (vmladavaq_p_s16): Likewise.
7036 (vmladavaq_p_u8): Likewise.
7037 (vmladavaq_p_u32): Likewise.
7038 (vmladavaq_p_u16): Likewise.
7039 (vmladavaxq_p_s8): Likewise.
7040 (vmladavaxq_p_s32): Likewise.
7041 (vmladavaxq_p_s16): Likewise.
7042 (vmlaq_m_n_s8): Likewise.
7043 (vmlaq_m_n_s32): Likewise.
7044 (vmlaq_m_n_s16): Likewise.
7045 (vmlaq_m_n_u8): Likewise.
7046 (vmlaq_m_n_u32): Likewise.
7047 (vmlaq_m_n_u16): Likewise.
7048 (vmlasq_m_n_s8): Likewise.
7049 (vmlasq_m_n_s32): Likewise.
7050 (vmlasq_m_n_s16): Likewise.
7051 (vmlasq_m_n_u8): Likewise.
7052 (vmlasq_m_n_u32): Likewise.
7053 (vmlasq_m_n_u16): Likewise.
7054 (vmlsdavaq_p_s8): Likewise.
7055 (vmlsdavaq_p_s32): Likewise.
7056 (vmlsdavaq_p_s16): Likewise.
7057 (vmlsdavaxq_p_s8): Likewise.
7058 (vmlsdavaxq_p_s32): Likewise.
7059 (vmlsdavaxq_p_s16): Likewise.
7060 (vmulhq_m_s8): Likewise.
7061 (vmulhq_m_s32): Likewise.
7062 (vmulhq_m_s16): Likewise.
7063 (vmulhq_m_u8): Likewise.
7064 (vmulhq_m_u32): Likewise.
7065 (vmulhq_m_u16): Likewise.
7066 (vmullbq_int_m_s8): Likewise.
7067 (vmullbq_int_m_s32): Likewise.
7068 (vmullbq_int_m_s16): Likewise.
7069 (vmullbq_int_m_u8): Likewise.
7070 (vmullbq_int_m_u32): Likewise.
7071 (vmullbq_int_m_u16): Likewise.
7072 (vmulltq_int_m_s8): Likewise.
7073 (vmulltq_int_m_s32): Likewise.
7074 (vmulltq_int_m_s16): Likewise.
7075 (vmulltq_int_m_u8): Likewise.
7076 (vmulltq_int_m_u32): Likewise.
7077 (vmulltq_int_m_u16): Likewise.
7078 (vmulq_m_n_s8): Likewise.
7079 (vmulq_m_n_s32): Likewise.
7080 (vmulq_m_n_s16): Likewise.
7081 (vmulq_m_n_u8): Likewise.
7082 (vmulq_m_n_u32): Likewise.
7083 (vmulq_m_n_u16): Likewise.
7084 (vmulq_m_s8): Likewise.
7085 (vmulq_m_s32): Likewise.
7086 (vmulq_m_s16): Likewise.
7087 (vmulq_m_u8): Likewise.
7088 (vmulq_m_u32): Likewise.
7089 (vmulq_m_u16): Likewise.
7090 (vornq_m_s8): Likewise.
7091 (vornq_m_s32): Likewise.
7092 (vornq_m_s16): Likewise.
7093 (vornq_m_u8): Likewise.
7094 (vornq_m_u32): Likewise.
7095 (vornq_m_u16): Likewise.
7096 (vorrq_m_s8): Likewise.
7097 (vorrq_m_s32): Likewise.
7098 (vorrq_m_s16): Likewise.
7099 (vorrq_m_u8): Likewise.
7100 (vorrq_m_u32): Likewise.
7101 (vorrq_m_u16): Likewise.
7102 (vqaddq_m_n_s8): Likewise.
7103 (vqaddq_m_n_s32): Likewise.
7104 (vqaddq_m_n_s16): Likewise.
7105 (vqaddq_m_n_u8): Likewise.
7106 (vqaddq_m_n_u32): Likewise.
7107 (vqaddq_m_n_u16): Likewise.
7108 (vqaddq_m_s8): Likewise.
7109 (vqaddq_m_s32): Likewise.
7110 (vqaddq_m_s16): Likewise.
7111 (vqaddq_m_u8): Likewise.
7112 (vqaddq_m_u32): Likewise.
7113 (vqaddq_m_u16): Likewise.
7114 (vqdmladhq_m_s8): Likewise.
7115 (vqdmladhq_m_s32): Likewise.
7116 (vqdmladhq_m_s16): Likewise.
7117 (vqdmladhxq_m_s8): Likewise.
7118 (vqdmladhxq_m_s32): Likewise.
7119 (vqdmladhxq_m_s16): Likewise.
7120 (vqdmlahq_m_n_s8): Likewise.
7121 (vqdmlahq_m_n_s32): Likewise.
7122 (vqdmlahq_m_n_s16): Likewise.
7123 (vqdmlahq_m_n_u8): Likewise.
7124 (vqdmlahq_m_n_u32): Likewise.
7125 (vqdmlahq_m_n_u16): Likewise.
7126 (vqdmlsdhq_m_s8): Likewise.
7127 (vqdmlsdhq_m_s32): Likewise.
7128 (vqdmlsdhq_m_s16): Likewise.
7129 (vqdmlsdhxq_m_s8): Likewise.
7130 (vqdmlsdhxq_m_s32): Likewise.
7131 (vqdmlsdhxq_m_s16): Likewise.
7132 (vqdmulhq_m_n_s8): Likewise.
7133 (vqdmulhq_m_n_s32): Likewise.
7134 (vqdmulhq_m_n_s16): Likewise.
7135 (vqdmulhq_m_s8): Likewise.
7136 (vqdmulhq_m_s32): Likewise.
7137 (vqdmulhq_m_s16): Likewise.
7138 (vqrdmladhq_m_s8): Likewise.
7139 (vqrdmladhq_m_s32): Likewise.
7140 (vqrdmladhq_m_s16): Likewise.
7141 (vqrdmladhxq_m_s8): Likewise.
7142 (vqrdmladhxq_m_s32): Likewise.
7143 (vqrdmladhxq_m_s16): Likewise.
7144 (vqrdmlahq_m_n_s8): Likewise.
7145 (vqrdmlahq_m_n_s32): Likewise.
7146 (vqrdmlahq_m_n_s16): Likewise.
7147 (vqrdmlahq_m_n_u8): Likewise.
7148 (vqrdmlahq_m_n_u32): Likewise.
7149 (vqrdmlahq_m_n_u16): Likewise.
7150 (vqrdmlashq_m_n_s8): Likewise.
7151 (vqrdmlashq_m_n_s32): Likewise.
7152 (vqrdmlashq_m_n_s16): Likewise.
7153 (vqrdmlashq_m_n_u8): Likewise.
7154 (vqrdmlashq_m_n_u32): Likewise.
7155 (vqrdmlashq_m_n_u16): Likewise.
7156 (vqrdmlsdhq_m_s8): Likewise.
7157 (vqrdmlsdhq_m_s32): Likewise.
7158 (vqrdmlsdhq_m_s16): Likewise.
7159 (vqrdmlsdhxq_m_s8): Likewise.
7160 (vqrdmlsdhxq_m_s32): Likewise.
7161 (vqrdmlsdhxq_m_s16): Likewise.
7162 (vqrdmulhq_m_n_s8): Likewise.
7163 (vqrdmulhq_m_n_s32): Likewise.
7164 (vqrdmulhq_m_n_s16): Likewise.
7165 (vqrdmulhq_m_s8): Likewise.
7166 (vqrdmulhq_m_s32): Likewise.
7167 (vqrdmulhq_m_s16): Likewise.
7168 (vqrshlq_m_s8): Likewise.
7169 (vqrshlq_m_s32): Likewise.
7170 (vqrshlq_m_s16): Likewise.
7171 (vqrshlq_m_u8): Likewise.
7172 (vqrshlq_m_u32): Likewise.
7173 (vqrshlq_m_u16): Likewise.
7174 (vqshlq_m_n_s8): Likewise.
7175 (vqshlq_m_n_s32): Likewise.
7176 (vqshlq_m_n_s16): Likewise.
7177 (vqshlq_m_n_u8): Likewise.
7178 (vqshlq_m_n_u32): Likewise.
7179 (vqshlq_m_n_u16): Likewise.
7180 (vqshlq_m_s8): Likewise.
7181 (vqshlq_m_s32): Likewise.
7182 (vqshlq_m_s16): Likewise.
7183 (vqshlq_m_u8): Likewise.
7184 (vqshlq_m_u32): Likewise.
7185 (vqshlq_m_u16): Likewise.
7186 (vqsubq_m_n_s8): Likewise.
7187 (vqsubq_m_n_s32): Likewise.
7188 (vqsubq_m_n_s16): Likewise.
7189 (vqsubq_m_n_u8): Likewise.
7190 (vqsubq_m_n_u32): Likewise.
7191 (vqsubq_m_n_u16): Likewise.
7192 (vqsubq_m_s8): Likewise.
7193 (vqsubq_m_s32): Likewise.
7194 (vqsubq_m_s16): Likewise.
7195 (vqsubq_m_u8): Likewise.
7196 (vqsubq_m_u32): Likewise.
7197 (vqsubq_m_u16): Likewise.
7198 (vrhaddq_m_s8): Likewise.
7199 (vrhaddq_m_s32): Likewise.
7200 (vrhaddq_m_s16): Likewise.
7201 (vrhaddq_m_u8): Likewise.
7202 (vrhaddq_m_u32): Likewise.
7203 (vrhaddq_m_u16): Likewise.
7204 (vrmulhq_m_s8): Likewise.
7205 (vrmulhq_m_s32): Likewise.
7206 (vrmulhq_m_s16): Likewise.
7207 (vrmulhq_m_u8): Likewise.
7208 (vrmulhq_m_u32): Likewise.
7209 (vrmulhq_m_u16): Likewise.
7210 (vrshlq_m_s8): Likewise.
7211 (vrshlq_m_s32): Likewise.
7212 (vrshlq_m_s16): Likewise.
7213 (vrshlq_m_u8): Likewise.
7214 (vrshlq_m_u32): Likewise.
7215 (vrshlq_m_u16): Likewise.
7216 (vrshrq_m_n_s8): Likewise.
7217 (vrshrq_m_n_s32): Likewise.
7218 (vrshrq_m_n_s16): Likewise.
7219 (vrshrq_m_n_u8): Likewise.
7220 (vrshrq_m_n_u32): Likewise.
7221 (vrshrq_m_n_u16): Likewise.
7222 (vshlq_m_n_s8): Likewise.
7223 (vshlq_m_n_s32): Likewise.
7224 (vshlq_m_n_s16): Likewise.
7225 (vshlq_m_n_u8): Likewise.
7226 (vshlq_m_n_u32): Likewise.
7227 (vshlq_m_n_u16): Likewise.
7228 (vshrq_m_n_s8): Likewise.
7229 (vshrq_m_n_s32): Likewise.
7230 (vshrq_m_n_s16): Likewise.
7231 (vshrq_m_n_u8): Likewise.
7232 (vshrq_m_n_u32): Likewise.
7233 (vshrq_m_n_u16): Likewise.
7234 (vsliq_m_n_s8): Likewise.
7235 (vsliq_m_n_s32): Likewise.
7236 (vsliq_m_n_s16): Likewise.
7237 (vsliq_m_n_u8): Likewise.
7238 (vsliq_m_n_u32): Likewise.
7239 (vsliq_m_n_u16): Likewise.
7240 (vsubq_m_n_s8): Likewise.
7241 (vsubq_m_n_s32): Likewise.
7242 (vsubq_m_n_s16): Likewise.
7243 (vsubq_m_n_u8): Likewise.
7244 (vsubq_m_n_u32): Likewise.
7245 (vsubq_m_n_u16): Likewise.
7246 (__arm_vabdq_m_s8): Define intrinsic.
7247 (__arm_vabdq_m_s32): Likewise.
7248 (__arm_vabdq_m_s16): Likewise.
7249 (__arm_vabdq_m_u8): Likewise.
7250 (__arm_vabdq_m_u32): Likewise.
7251 (__arm_vabdq_m_u16): Likewise.
7252 (__arm_vaddq_m_n_s8): Likewise.
7253 (__arm_vaddq_m_n_s32): Likewise.
7254 (__arm_vaddq_m_n_s16): Likewise.
7255 (__arm_vaddq_m_n_u8): Likewise.
7256 (__arm_vaddq_m_n_u32): Likewise.
7257 (__arm_vaddq_m_n_u16): Likewise.
7258 (__arm_vaddq_m_s8): Likewise.
7259 (__arm_vaddq_m_s32): Likewise.
7260 (__arm_vaddq_m_s16): Likewise.
7261 (__arm_vaddq_m_u8): Likewise.
7262 (__arm_vaddq_m_u32): Likewise.
7263 (__arm_vaddq_m_u16): Likewise.
7264 (__arm_vandq_m_s8): Likewise.
7265 (__arm_vandq_m_s32): Likewise.
7266 (__arm_vandq_m_s16): Likewise.
7267 (__arm_vandq_m_u8): Likewise.
7268 (__arm_vandq_m_u32): Likewise.
7269 (__arm_vandq_m_u16): Likewise.
7270 (__arm_vbicq_m_s8): Likewise.
7271 (__arm_vbicq_m_s32): Likewise.
7272 (__arm_vbicq_m_s16): Likewise.
7273 (__arm_vbicq_m_u8): Likewise.
7274 (__arm_vbicq_m_u32): Likewise.
7275 (__arm_vbicq_m_u16): Likewise.
7276 (__arm_vbrsrq_m_n_s8): Likewise.
7277 (__arm_vbrsrq_m_n_s32): Likewise.
7278 (__arm_vbrsrq_m_n_s16): Likewise.
7279 (__arm_vbrsrq_m_n_u8): Likewise.
7280 (__arm_vbrsrq_m_n_u32): Likewise.
7281 (__arm_vbrsrq_m_n_u16): Likewise.
7282 (__arm_vcaddq_rot270_m_s8): Likewise.
7283 (__arm_vcaddq_rot270_m_s32): Likewise.
7284 (__arm_vcaddq_rot270_m_s16): Likewise.
7285 (__arm_vcaddq_rot270_m_u8): Likewise.
7286 (__arm_vcaddq_rot270_m_u32): Likewise.
7287 (__arm_vcaddq_rot270_m_u16): Likewise.
7288 (__arm_vcaddq_rot90_m_s8): Likewise.
7289 (__arm_vcaddq_rot90_m_s32): Likewise.
7290 (__arm_vcaddq_rot90_m_s16): Likewise.
7291 (__arm_vcaddq_rot90_m_u8): Likewise.
7292 (__arm_vcaddq_rot90_m_u32): Likewise.
7293 (__arm_vcaddq_rot90_m_u16): Likewise.
7294 (__arm_veorq_m_s8): Likewise.
7295 (__arm_veorq_m_s32): Likewise.
7296 (__arm_veorq_m_s16): Likewise.
7297 (__arm_veorq_m_u8): Likewise.
7298 (__arm_veorq_m_u32): Likewise.
7299 (__arm_veorq_m_u16): Likewise.
7300 (__arm_vhaddq_m_n_s8): Likewise.
7301 (__arm_vhaddq_m_n_s32): Likewise.
7302 (__arm_vhaddq_m_n_s16): Likewise.
7303 (__arm_vhaddq_m_n_u8): Likewise.
7304 (__arm_vhaddq_m_n_u32): Likewise.
7305 (__arm_vhaddq_m_n_u16): Likewise.
7306 (__arm_vhaddq_m_s8): Likewise.
7307 (__arm_vhaddq_m_s32): Likewise.
7308 (__arm_vhaddq_m_s16): Likewise.
7309 (__arm_vhaddq_m_u8): Likewise.
7310 (__arm_vhaddq_m_u32): Likewise.
7311 (__arm_vhaddq_m_u16): Likewise.
7312 (__arm_vhcaddq_rot270_m_s8): Likewise.
7313 (__arm_vhcaddq_rot270_m_s32): Likewise.
7314 (__arm_vhcaddq_rot270_m_s16): Likewise.
7315 (__arm_vhcaddq_rot90_m_s8): Likewise.
7316 (__arm_vhcaddq_rot90_m_s32): Likewise.
7317 (__arm_vhcaddq_rot90_m_s16): Likewise.
7318 (__arm_vhsubq_m_n_s8): Likewise.
7319 (__arm_vhsubq_m_n_s32): Likewise.
7320 (__arm_vhsubq_m_n_s16): Likewise.
7321 (__arm_vhsubq_m_n_u8): Likewise.
7322 (__arm_vhsubq_m_n_u32): Likewise.
7323 (__arm_vhsubq_m_n_u16): Likewise.
7324 (__arm_vhsubq_m_s8): Likewise.
7325 (__arm_vhsubq_m_s32): Likewise.
7326 (__arm_vhsubq_m_s16): Likewise.
7327 (__arm_vhsubq_m_u8): Likewise.
7328 (__arm_vhsubq_m_u32): Likewise.
7329 (__arm_vhsubq_m_u16): Likewise.
7330 (__arm_vmaxq_m_s8): Likewise.
7331 (__arm_vmaxq_m_s32): Likewise.
7332 (__arm_vmaxq_m_s16): Likewise.
7333 (__arm_vmaxq_m_u8): Likewise.
7334 (__arm_vmaxq_m_u32): Likewise.
7335 (__arm_vmaxq_m_u16): Likewise.
7336 (__arm_vminq_m_s8): Likewise.
7337 (__arm_vminq_m_s32): Likewise.
7338 (__arm_vminq_m_s16): Likewise.
7339 (__arm_vminq_m_u8): Likewise.
7340 (__arm_vminq_m_u32): Likewise.
7341 (__arm_vminq_m_u16): Likewise.
7342 (__arm_vmladavaq_p_s8): Likewise.
7343 (__arm_vmladavaq_p_s32): Likewise.
7344 (__arm_vmladavaq_p_s16): Likewise.
7345 (__arm_vmladavaq_p_u8): Likewise.
7346 (__arm_vmladavaq_p_u32): Likewise.
7347 (__arm_vmladavaq_p_u16): Likewise.
7348 (__arm_vmladavaxq_p_s8): Likewise.
7349 (__arm_vmladavaxq_p_s32): Likewise.
7350 (__arm_vmladavaxq_p_s16): Likewise.
7351 (__arm_vmlaq_m_n_s8): Likewise.
7352 (__arm_vmlaq_m_n_s32): Likewise.
7353 (__arm_vmlaq_m_n_s16): Likewise.
7354 (__arm_vmlaq_m_n_u8): Likewise.
7355 (__arm_vmlaq_m_n_u32): Likewise.
7356 (__arm_vmlaq_m_n_u16): Likewise.
7357 (__arm_vmlasq_m_n_s8): Likewise.
7358 (__arm_vmlasq_m_n_s32): Likewise.
7359 (__arm_vmlasq_m_n_s16): Likewise.
7360 (__arm_vmlasq_m_n_u8): Likewise.
7361 (__arm_vmlasq_m_n_u32): Likewise.
7362 (__arm_vmlasq_m_n_u16): Likewise.
7363 (__arm_vmlsdavaq_p_s8): Likewise.
7364 (__arm_vmlsdavaq_p_s32): Likewise.
7365 (__arm_vmlsdavaq_p_s16): Likewise.
7366 (__arm_vmlsdavaxq_p_s8): Likewise.
7367 (__arm_vmlsdavaxq_p_s32): Likewise.
7368 (__arm_vmlsdavaxq_p_s16): Likewise.
7369 (__arm_vmulhq_m_s8): Likewise.
7370 (__arm_vmulhq_m_s32): Likewise.
7371 (__arm_vmulhq_m_s16): Likewise.
7372 (__arm_vmulhq_m_u8): Likewise.
7373 (__arm_vmulhq_m_u32): Likewise.
7374 (__arm_vmulhq_m_u16): Likewise.
7375 (__arm_vmullbq_int_m_s8): Likewise.
7376 (__arm_vmullbq_int_m_s32): Likewise.
7377 (__arm_vmullbq_int_m_s16): Likewise.
7378 (__arm_vmullbq_int_m_u8): Likewise.
7379 (__arm_vmullbq_int_m_u32): Likewise.
7380 (__arm_vmullbq_int_m_u16): Likewise.
7381 (__arm_vmulltq_int_m_s8): Likewise.
7382 (__arm_vmulltq_int_m_s32): Likewise.
7383 (__arm_vmulltq_int_m_s16): Likewise.
7384 (__arm_vmulltq_int_m_u8): Likewise.
7385 (__arm_vmulltq_int_m_u32): Likewise.
7386 (__arm_vmulltq_int_m_u16): Likewise.
7387 (__arm_vmulq_m_n_s8): Likewise.
7388 (__arm_vmulq_m_n_s32): Likewise.
7389 (__arm_vmulq_m_n_s16): Likewise.
7390 (__arm_vmulq_m_n_u8): Likewise.
7391 (__arm_vmulq_m_n_u32): Likewise.
7392 (__arm_vmulq_m_n_u16): Likewise.
7393 (__arm_vmulq_m_s8): Likewise.
7394 (__arm_vmulq_m_s32): Likewise.
7395 (__arm_vmulq_m_s16): Likewise.
7396 (__arm_vmulq_m_u8): Likewise.
7397 (__arm_vmulq_m_u32): Likewise.
7398 (__arm_vmulq_m_u16): Likewise.
7399 (__arm_vornq_m_s8): Likewise.
7400 (__arm_vornq_m_s32): Likewise.
7401 (__arm_vornq_m_s16): Likewise.
7402 (__arm_vornq_m_u8): Likewise.
7403 (__arm_vornq_m_u32): Likewise.
7404 (__arm_vornq_m_u16): Likewise.
7405 (__arm_vorrq_m_s8): Likewise.
7406 (__arm_vorrq_m_s32): Likewise.
7407 (__arm_vorrq_m_s16): Likewise.
7408 (__arm_vorrq_m_u8): Likewise.
7409 (__arm_vorrq_m_u32): Likewise.
7410 (__arm_vorrq_m_u16): Likewise.
7411 (__arm_vqaddq_m_n_s8): Likewise.
7412 (__arm_vqaddq_m_n_s32): Likewise.
7413 (__arm_vqaddq_m_n_s16): Likewise.
7414 (__arm_vqaddq_m_n_u8): Likewise.
7415 (__arm_vqaddq_m_n_u32): Likewise.
7416 (__arm_vqaddq_m_n_u16): Likewise.
7417 (__arm_vqaddq_m_s8): Likewise.
7418 (__arm_vqaddq_m_s32): Likewise.
7419 (__arm_vqaddq_m_s16): Likewise.
7420 (__arm_vqaddq_m_u8): Likewise.
7421 (__arm_vqaddq_m_u32): Likewise.
7422 (__arm_vqaddq_m_u16): Likewise.
7423 (__arm_vqdmladhq_m_s8): Likewise.
7424 (__arm_vqdmladhq_m_s32): Likewise.
7425 (__arm_vqdmladhq_m_s16): Likewise.
7426 (__arm_vqdmladhxq_m_s8): Likewise.
7427 (__arm_vqdmladhxq_m_s32): Likewise.
7428 (__arm_vqdmladhxq_m_s16): Likewise.
7429 (__arm_vqdmlahq_m_n_s8): Likewise.
7430 (__arm_vqdmlahq_m_n_s32): Likewise.
7431 (__arm_vqdmlahq_m_n_s16): Likewise.
7432 (__arm_vqdmlahq_m_n_u8): Likewise.
7433 (__arm_vqdmlahq_m_n_u32): Likewise.
7434 (__arm_vqdmlahq_m_n_u16): Likewise.
7435 (__arm_vqdmlsdhq_m_s8): Likewise.
7436 (__arm_vqdmlsdhq_m_s32): Likewise.
7437 (__arm_vqdmlsdhq_m_s16): Likewise.
7438 (__arm_vqdmlsdhxq_m_s8): Likewise.
7439 (__arm_vqdmlsdhxq_m_s32): Likewise.
7440 (__arm_vqdmlsdhxq_m_s16): Likewise.
7441 (__arm_vqdmulhq_m_n_s8): Likewise.
7442 (__arm_vqdmulhq_m_n_s32): Likewise.
7443 (__arm_vqdmulhq_m_n_s16): Likewise.
7444 (__arm_vqdmulhq_m_s8): Likewise.
7445 (__arm_vqdmulhq_m_s32): Likewise.
7446 (__arm_vqdmulhq_m_s16): Likewise.
7447 (__arm_vqrdmladhq_m_s8): Likewise.
7448 (__arm_vqrdmladhq_m_s32): Likewise.
7449 (__arm_vqrdmladhq_m_s16): Likewise.
7450 (__arm_vqrdmladhxq_m_s8): Likewise.
7451 (__arm_vqrdmladhxq_m_s32): Likewise.
7452 (__arm_vqrdmladhxq_m_s16): Likewise.
7453 (__arm_vqrdmlahq_m_n_s8): Likewise.
7454 (__arm_vqrdmlahq_m_n_s32): Likewise.
7455 (__arm_vqrdmlahq_m_n_s16): Likewise.
7456 (__arm_vqrdmlahq_m_n_u8): Likewise.
7457 (__arm_vqrdmlahq_m_n_u32): Likewise.
7458 (__arm_vqrdmlahq_m_n_u16): Likewise.
7459 (__arm_vqrdmlashq_m_n_s8): Likewise.
7460 (__arm_vqrdmlashq_m_n_s32): Likewise.
7461 (__arm_vqrdmlashq_m_n_s16): Likewise.
7462 (__arm_vqrdmlashq_m_n_u8): Likewise.
7463 (__arm_vqrdmlashq_m_n_u32): Likewise.
7464 (__arm_vqrdmlashq_m_n_u16): Likewise.
7465 (__arm_vqrdmlsdhq_m_s8): Likewise.
7466 (__arm_vqrdmlsdhq_m_s32): Likewise.
7467 (__arm_vqrdmlsdhq_m_s16): Likewise.
7468 (__arm_vqrdmlsdhxq_m_s8): Likewise.
7469 (__arm_vqrdmlsdhxq_m_s32): Likewise.
7470 (__arm_vqrdmlsdhxq_m_s16): Likewise.
7471 (__arm_vqrdmulhq_m_n_s8): Likewise.
7472 (__arm_vqrdmulhq_m_n_s32): Likewise.
7473 (__arm_vqrdmulhq_m_n_s16): Likewise.
7474 (__arm_vqrdmulhq_m_s8): Likewise.
7475 (__arm_vqrdmulhq_m_s32): Likewise.
7476 (__arm_vqrdmulhq_m_s16): Likewise.
7477 (__arm_vqrshlq_m_s8): Likewise.
7478 (__arm_vqrshlq_m_s32): Likewise.
7479 (__arm_vqrshlq_m_s16): Likewise.
7480 (__arm_vqrshlq_m_u8): Likewise.
7481 (__arm_vqrshlq_m_u32): Likewise.
7482 (__arm_vqrshlq_m_u16): Likewise.
7483 (__arm_vqshlq_m_n_s8): Likewise.
7484 (__arm_vqshlq_m_n_s32): Likewise.
7485 (__arm_vqshlq_m_n_s16): Likewise.
7486 (__arm_vqshlq_m_n_u8): Likewise.
7487 (__arm_vqshlq_m_n_u32): Likewise.
7488 (__arm_vqshlq_m_n_u16): Likewise.
7489 (__arm_vqshlq_m_s8): Likewise.
7490 (__arm_vqshlq_m_s32): Likewise.
7491 (__arm_vqshlq_m_s16): Likewise.
7492 (__arm_vqshlq_m_u8): Likewise.
7493 (__arm_vqshlq_m_u32): Likewise.
7494 (__arm_vqshlq_m_u16): Likewise.
7495 (__arm_vqsubq_m_n_s8): Likewise.
7496 (__arm_vqsubq_m_n_s32): Likewise.
7497 (__arm_vqsubq_m_n_s16): Likewise.
7498 (__arm_vqsubq_m_n_u8): Likewise.
7499 (__arm_vqsubq_m_n_u32): Likewise.
7500 (__arm_vqsubq_m_n_u16): Likewise.
7501 (__arm_vqsubq_m_s8): Likewise.
7502 (__arm_vqsubq_m_s32): Likewise.
7503 (__arm_vqsubq_m_s16): Likewise.
7504 (__arm_vqsubq_m_u8): Likewise.
7505 (__arm_vqsubq_m_u32): Likewise.
7506 (__arm_vqsubq_m_u16): Likewise.
7507 (__arm_vrhaddq_m_s8): Likewise.
7508 (__arm_vrhaddq_m_s32): Likewise.
7509 (__arm_vrhaddq_m_s16): Likewise.
7510 (__arm_vrhaddq_m_u8): Likewise.
7511 (__arm_vrhaddq_m_u32): Likewise.
7512 (__arm_vrhaddq_m_u16): Likewise.
7513 (__arm_vrmulhq_m_s8): Likewise.
7514 (__arm_vrmulhq_m_s32): Likewise.
7515 (__arm_vrmulhq_m_s16): Likewise.
7516 (__arm_vrmulhq_m_u8): Likewise.
7517 (__arm_vrmulhq_m_u32): Likewise.
7518 (__arm_vrmulhq_m_u16): Likewise.
7519 (__arm_vrshlq_m_s8): Likewise.
7520 (__arm_vrshlq_m_s32): Likewise.
7521 (__arm_vrshlq_m_s16): Likewise.
7522 (__arm_vrshlq_m_u8): Likewise.
7523 (__arm_vrshlq_m_u32): Likewise.
7524 (__arm_vrshlq_m_u16): Likewise.
7525 (__arm_vrshrq_m_n_s8): Likewise.
7526 (__arm_vrshrq_m_n_s32): Likewise.
7527 (__arm_vrshrq_m_n_s16): Likewise.
7528 (__arm_vrshrq_m_n_u8): Likewise.
7529 (__arm_vrshrq_m_n_u32): Likewise.
7530 (__arm_vrshrq_m_n_u16): Likewise.
7531 (__arm_vshlq_m_n_s8): Likewise.
7532 (__arm_vshlq_m_n_s32): Likewise.
7533 (__arm_vshlq_m_n_s16): Likewise.
7534 (__arm_vshlq_m_n_u8): Likewise.
7535 (__arm_vshlq_m_n_u32): Likewise.
7536 (__arm_vshlq_m_n_u16): Likewise.
7537 (__arm_vshrq_m_n_s8): Likewise.
7538 (__arm_vshrq_m_n_s32): Likewise.
7539 (__arm_vshrq_m_n_s16): Likewise.
7540 (__arm_vshrq_m_n_u8): Likewise.
7541 (__arm_vshrq_m_n_u32): Likewise.
7542 (__arm_vshrq_m_n_u16): Likewise.
7543 (__arm_vsliq_m_n_s8): Likewise.
7544 (__arm_vsliq_m_n_s32): Likewise.
7545 (__arm_vsliq_m_n_s16): Likewise.
7546 (__arm_vsliq_m_n_u8): Likewise.
7547 (__arm_vsliq_m_n_u32): Likewise.
7548 (__arm_vsliq_m_n_u16): Likewise.
7549 (__arm_vsubq_m_n_s8): Likewise.
7550 (__arm_vsubq_m_n_s32): Likewise.
7551 (__arm_vsubq_m_n_s16): Likewise.
7552 (__arm_vsubq_m_n_u8): Likewise.
7553 (__arm_vsubq_m_n_u32): Likewise.
7554 (__arm_vsubq_m_n_u16): Likewise.
7555 (vqdmladhq_m): Define polymorphic variant.
7556 (vqdmladhxq_m): Likewise.
7557 (vqdmlsdhq_m): Likewise.
7558 (vqdmlsdhxq_m): Likewise.
7559 (vabdq_m): Likewise.
7560 (vandq_m): Likewise.
7561 (vbicq_m): Likewise.
7562 (vbrsrq_m_n): Likewise.
7563 (vcaddq_rot270_m): Likewise.
7564 (vcaddq_rot90_m): Likewise.
7565 (veorq_m): Likewise.
7566 (vmaxq_m): Likewise.
7567 (vminq_m): Likewise.
7568 (vmladavaq_p): Likewise.
7569 (vmlaq_m_n): Likewise.
7570 (vmlasq_m_n): Likewise.
7571 (vmulhq_m): Likewise.
7572 (vmullbq_int_m): Likewise.
7573 (vmulltq_int_m): Likewise.
7574 (vornq_m): Likewise.
7575 (vorrq_m): Likewise.
7576 (vqdmlahq_m_n): Likewise.
7577 (vqrdmlahq_m_n): Likewise.
7578 (vqrdmlashq_m_n): Likewise.
7579 (vqrshlq_m): Likewise.
7580 (vqshlq_m_n): Likewise.
7581 (vqshlq_m): Likewise.
7582 (vrhaddq_m): Likewise.
7583 (vrmulhq_m): Likewise.
7584 (vrshlq_m): Likewise.
7585 (vrshrq_m_n): Likewise.
7586 (vshlq_m_n): Likewise.
7587 (vshrq_m_n): Likewise.
7588 (vsliq_m): Likewise.
7589 (vaddq_m_n): Likewise.
7590 (vaddq_m): Likewise.
7591 (vhaddq_m_n): Likewise.
7592 (vhaddq_m): Likewise.
7593 (vhcaddq_rot270_m): Likewise.
7594 (vhcaddq_rot90_m): Likewise.
7595 (vhsubq_m): Likewise.
7596 (vhsubq_m_n): Likewise.
7597 (vmulq_m_n): Likewise.
7598 (vmulq_m): Likewise.
7599 (vqaddq_m_n): Likewise.
7600 (vqaddq_m): Likewise.
7601 (vqdmulhq_m_n): Likewise.
7602 (vqdmulhq_m): Likewise.
7603 (vsubq_m_n): Likewise.
7604 (vsliq_m_n): Likewise.
7605 (vqsubq_m_n): Likewise.
7606 (vqsubq_m): Likewise.
7607 (vqrdmulhq_m): Likewise.
7608 (vqrdmulhq_m_n): Likewise.
7609 (vqrdmlsdhxq_m): Likewise.
7610 (vqrdmlsdhq_m): Likewise.
7611 (vqrdmladhq_m): Likewise.
7612 (vqrdmladhxq_m): Likewise.
7613 (vmlsdavaxq_p): Likewise.
7614 (vmlsdavaq_p): Likewise.
7615 (vmladavaxq_p): Likewise.
7616 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7618 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7619 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
7620 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
7621 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
7622 * config/arm/mve.md (VHSUBQ_M): Define iterators.
7623 (VSLIQ_M_N): Likewise.
7624 (VQRDMLAHQ_M_N): Likewise.
7625 (VRSHLQ_M): Likewise.
7626 (VMINQ_M): Likewise.
7627 (VMULLBQ_INT_M): Likewise.
7628 (VMULHQ_M): Likewise.
7629 (VMULQ_M): Likewise.
7630 (VHSUBQ_M_N): Likewise.
7631 (VHADDQ_M_N): Likewise.
7632 (VORRQ_M): Likewise.
7633 (VRMULHQ_M): Likewise.
7634 (VQADDQ_M): Likewise.
7635 (VRSHRQ_M_N): Likewise.
7636 (VQSUBQ_M_N): Likewise.
7637 (VADDQ_M): Likewise.
7638 (VORNQ_M): Likewise.
7639 (VQDMLAHQ_M_N): Likewise.
7640 (VRHADDQ_M): Likewise.
7641 (VQSHLQ_M): Likewise.
7642 (VANDQ_M): Likewise.
7643 (VBICQ_M): Likewise.
7644 (VSHLQ_M_N): Likewise.
7645 (VCADDQ_ROT270_M): Likewise.
7646 (VQRSHLQ_M): Likewise.
7647 (VQADDQ_M_N): Likewise.
7648 (VADDQ_M_N): Likewise.
7649 (VMAXQ_M): Likewise.
7650 (VQSUBQ_M): Likewise.
7651 (VMLASQ_M_N): Likewise.
7652 (VMLADAVAQ_P): Likewise.
7653 (VBRSRQ_M_N): Likewise.
7654 (VMULQ_M_N): Likewise.
7655 (VCADDQ_ROT90_M): Likewise.
7656 (VMULLTQ_INT_M): Likewise.
7657 (VEORQ_M): Likewise.
7658 (VSHRQ_M_N): Likewise.
7659 (VSUBQ_M_N): Likewise.
7660 (VHADDQ_M): Likewise.
7661 (VABDQ_M): Likewise.
7662 (VQRDMLASHQ_M_N): Likewise.
7663 (VMLAQ_M_N): Likewise.
7664 (VQSHLQ_M_N): Likewise.
7665 (mve_vabdq_m_<supf><mode>): Define RTL pattern.
7666 (mve_vaddq_m_n_<supf><mode>): Likewise.
7667 (mve_vaddq_m_<supf><mode>): Likewise.
7668 (mve_vandq_m_<supf><mode>): Likewise.
7669 (mve_vbicq_m_<supf><mode>): Likewise.
7670 (mve_vbrsrq_m_n_<supf><mode>): Likewise.
7671 (mve_vcaddq_rot270_m_<supf><mode>): Likewise.
7672 (mve_vcaddq_rot90_m_<supf><mode>): Likewise.
7673 (mve_veorq_m_<supf><mode>): Likewise.
7674 (mve_vhaddq_m_n_<supf><mode>): Likewise.
7675 (mve_vhaddq_m_<supf><mode>): Likewise.
7676 (mve_vhsubq_m_n_<supf><mode>): Likewise.
7677 (mve_vhsubq_m_<supf><mode>): Likewise.
7678 (mve_vmaxq_m_<supf><mode>): Likewise.
7679 (mve_vminq_m_<supf><mode>): Likewise.
7680 (mve_vmladavaq_p_<supf><mode>): Likewise.
7681 (mve_vmlaq_m_n_<supf><mode>): Likewise.
7682 (mve_vmlasq_m_n_<supf><mode>): Likewise.
7683 (mve_vmulhq_m_<supf><mode>): Likewise.
7684 (mve_vmullbq_int_m_<supf><mode>): Likewise.
7685 (mve_vmulltq_int_m_<supf><mode>): Likewise.
7686 (mve_vmulq_m_n_<supf><mode>): Likewise.
7687 (mve_vmulq_m_<supf><mode>): Likewise.
7688 (mve_vornq_m_<supf><mode>): Likewise.
7689 (mve_vorrq_m_<supf><mode>): Likewise.
7690 (mve_vqaddq_m_n_<supf><mode>): Likewise.
7691 (mve_vqaddq_m_<supf><mode>): Likewise.
7692 (mve_vqdmlahq_m_n_<supf><mode>): Likewise.
7693 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
7694 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
7695 (mve_vqrshlq_m_<supf><mode>): Likewise.
7696 (mve_vqshlq_m_n_<supf><mode>): Likewise.
7697 (mve_vqshlq_m_<supf><mode>): Likewise.
7698 (mve_vqsubq_m_n_<supf><mode>): Likewise.
7699 (mve_vqsubq_m_<supf><mode>): Likewise.
7700 (mve_vrhaddq_m_<supf><mode>): Likewise.
7701 (mve_vrmulhq_m_<supf><mode>): Likewise.
7702 (mve_vrshlq_m_<supf><mode>): Likewise.
7703 (mve_vrshrq_m_n_<supf><mode>): Likewise.
7704 (mve_vshlq_m_n_<supf><mode>): Likewise.
7705 (mve_vshrq_m_n_<supf><mode>): Likewise.
7706 (mve_vsliq_m_n_<supf><mode>): Likewise.
7707 (mve_vsubq_m_n_<supf><mode>): Likewise.
7708 (mve_vhcaddq_rot270_m_s<mode>): Likewise.
7709 (mve_vhcaddq_rot90_m_s<mode>): Likewise.
7710 (mve_vmladavaxq_p_s<mode>): Likewise.
7711 (mve_vmlsdavaq_p_s<mode>): Likewise.
7712 (mve_vmlsdavaxq_p_s<mode>): Likewise.
7713 (mve_vqdmladhq_m_s<mode>): Likewise.
7714 (mve_vqdmladhxq_m_s<mode>): Likewise.
7715 (mve_vqdmlsdhq_m_s<mode>): Likewise.
7716 (mve_vqdmlsdhxq_m_s<mode>): Likewise.
7717 (mve_vqdmulhq_m_n_s<mode>): Likewise.
7718 (mve_vqdmulhq_m_s<mode>): Likewise.
7719 (mve_vqrdmladhq_m_s<mode>): Likewise.
7720 (mve_vqrdmladhxq_m_s<mode>): Likewise.
7721 (mve_vqrdmlsdhq_m_s<mode>): Likewise.
7722 (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
7723 (mve_vqrdmulhq_m_n_s<mode>): Likewise.
7724 (mve_vqrdmulhq_m_s<mode>): Likewise.
7726 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7727 Mihail Ionescu <mihail.ionescu@arm.com>
7728 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7730 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
7731 Define builtin qualifier.
7732 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
7733 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
7734 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
7735 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
7736 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
7737 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
7738 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
7739 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
7740 (vsubq_m_s8): Likewise.
7741 (vcvtq_m_n_f16_u16): Likewise.
7742 (vqshluq_m_n_s8): Likewise.
7743 (vabavq_p_s8): Likewise.
7744 (vsriq_m_n_u8): Likewise.
7745 (vshlq_m_u8): Likewise.
7746 (vsubq_m_u8): Likewise.
7747 (vabavq_p_u8): Likewise.
7748 (vshlq_m_s8): Likewise.
7749 (vcvtq_m_n_f16_s16): Likewise.
7750 (vsriq_m_n_s16): Likewise.
7751 (vsubq_m_s16): Likewise.
7752 (vcvtq_m_n_f32_u32): Likewise.
7753 (vqshluq_m_n_s16): Likewise.
7754 (vabavq_p_s16): Likewise.
7755 (vsriq_m_n_u16): Likewise.
7756 (vshlq_m_u16): Likewise.
7757 (vsubq_m_u16): Likewise.
7758 (vabavq_p_u16): Likewise.
7759 (vshlq_m_s16): Likewise.
7760 (vcvtq_m_n_f32_s32): Likewise.
7761 (vsriq_m_n_s32): Likewise.
7762 (vsubq_m_s32): Likewise.
7763 (vqshluq_m_n_s32): Likewise.
7764 (vabavq_p_s32): Likewise.
7765 (vsriq_m_n_u32): Likewise.
7766 (vshlq_m_u32): Likewise.
7767 (vsubq_m_u32): Likewise.
7768 (vabavq_p_u32): Likewise.
7769 (vshlq_m_s32): Likewise.
7770 (__arm_vsriq_m_n_s8): Define intrinsic.
7771 (__arm_vsubq_m_s8): Likewise.
7772 (__arm_vqshluq_m_n_s8): Likewise.
7773 (__arm_vabavq_p_s8): Likewise.
7774 (__arm_vsriq_m_n_u8): Likewise.
7775 (__arm_vshlq_m_u8): Likewise.
7776 (__arm_vsubq_m_u8): Likewise.
7777 (__arm_vabavq_p_u8): Likewise.
7778 (__arm_vshlq_m_s8): Likewise.
7779 (__arm_vsriq_m_n_s16): Likewise.
7780 (__arm_vsubq_m_s16): Likewise.
7781 (__arm_vqshluq_m_n_s16): Likewise.
7782 (__arm_vabavq_p_s16): Likewise.
7783 (__arm_vsriq_m_n_u16): Likewise.
7784 (__arm_vshlq_m_u16): Likewise.
7785 (__arm_vsubq_m_u16): Likewise.
7786 (__arm_vabavq_p_u16): Likewise.
7787 (__arm_vshlq_m_s16): Likewise.
7788 (__arm_vsriq_m_n_s32): Likewise.
7789 (__arm_vsubq_m_s32): Likewise.
7790 (__arm_vqshluq_m_n_s32): Likewise.
7791 (__arm_vabavq_p_s32): Likewise.
7792 (__arm_vsriq_m_n_u32): Likewise.
7793 (__arm_vshlq_m_u32): Likewise.
7794 (__arm_vsubq_m_u32): Likewise.
7795 (__arm_vabavq_p_u32): Likewise.
7796 (__arm_vshlq_m_s32): Likewise.
7797 (__arm_vcvtq_m_n_f16_u16): Likewise.
7798 (__arm_vcvtq_m_n_f16_s16): Likewise.
7799 (__arm_vcvtq_m_n_f32_u32): Likewise.
7800 (__arm_vcvtq_m_n_f32_s32): Likewise.
7801 (vcvtq_m_n): Define polymorphic variant.
7802 (vqshluq_m_n): Likewise.
7803 (vshlq_m): Likewise.
7804 (vsriq_m_n): Likewise.
7805 (vsubq_m): Likewise.
7806 (vabavq_p): Likewise.
7807 * config/arm/arm_mve_builtins.def
7808 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
7809 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
7810 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
7811 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
7812 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
7813 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
7814 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
7815 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
7816 * config/arm/mve.md (VABAVQ_P): Define iterator.
7817 (VSHLQ_M): Likewise.
7818 (VSRIQ_M_N): Likewise.
7819 (VSUBQ_M): Likewise.
7820 (VCVTQ_M_N_TO_F): Likewise.
7821 (mve_vabavq_p_<supf><mode>): Define RTL pattern.
7822 (mve_vqshluq_m_n_s<mode>): Likewise.
7823 (mve_vshlq_m_<supf><mode>): Likewise.
7824 (mve_vsriq_m_n_<supf><mode>): Likewise.
7825 (mve_vsubq_m_<supf><mode>): Likewise.
7826 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
7828 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7829 Mihail Ionescu <mihail.ionescu@arm.com>
7830 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7832 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
7833 (vrmlsldavhaq_s32): Likewise.
7834 (vrmlsldavhaxq_s32): Likewise.
7835 (vaddlvaq_p_s32): Likewise.
7836 (vcvtbq_m_f16_f32): Likewise.
7837 (vcvtbq_m_f32_f16): Likewise.
7838 (vcvttq_m_f16_f32): Likewise.
7839 (vcvttq_m_f32_f16): Likewise.
7840 (vrev16q_m_s8): Likewise.
7841 (vrev32q_m_f16): Likewise.
7842 (vrmlaldavhq_p_s32): Likewise.
7843 (vrmlaldavhxq_p_s32): Likewise.
7844 (vrmlsldavhq_p_s32): Likewise.
7845 (vrmlsldavhxq_p_s32): Likewise.
7846 (vaddlvaq_p_u32): Likewise.
7847 (vrev16q_m_u8): Likewise.
7848 (vrmlaldavhq_p_u32): Likewise.
7849 (vmvnq_m_n_s16): Likewise.
7850 (vorrq_m_n_s16): Likewise.
7851 (vqrshrntq_n_s16): Likewise.
7852 (vqshrnbq_n_s16): Likewise.
7853 (vqshrntq_n_s16): Likewise.
7854 (vrshrnbq_n_s16): Likewise.
7855 (vrshrntq_n_s16): Likewise.
7856 (vshrnbq_n_s16): Likewise.
7857 (vshrntq_n_s16): Likewise.
7858 (vcmlaq_f16): Likewise.
7859 (vcmlaq_rot180_f16): Likewise.
7860 (vcmlaq_rot270_f16): Likewise.
7861 (vcmlaq_rot90_f16): Likewise.
7862 (vfmaq_f16): Likewise.
7863 (vfmaq_n_f16): Likewise.
7864 (vfmasq_n_f16): Likewise.
7865 (vfmsq_f16): Likewise.
7866 (vmlaldavaq_s16): Likewise.
7867 (vmlaldavaxq_s16): Likewise.
7868 (vmlsldavaq_s16): Likewise.
7869 (vmlsldavaxq_s16): Likewise.
7870 (vabsq_m_f16): Likewise.
7871 (vcvtmq_m_s16_f16): Likewise.
7872 (vcvtnq_m_s16_f16): Likewise.
7873 (vcvtpq_m_s16_f16): Likewise.
7874 (vcvtq_m_s16_f16): Likewise.
7875 (vdupq_m_n_f16): Likewise.
7876 (vmaxnmaq_m_f16): Likewise.
7877 (vmaxnmavq_p_f16): Likewise.
7878 (vmaxnmvq_p_f16): Likewise.
7879 (vminnmaq_m_f16): Likewise.
7880 (vminnmavq_p_f16): Likewise.
7881 (vminnmvq_p_f16): Likewise.
7882 (vmlaldavq_p_s16): Likewise.
7883 (vmlaldavxq_p_s16): Likewise.
7884 (vmlsldavq_p_s16): Likewise.
7885 (vmlsldavxq_p_s16): Likewise.
7886 (vmovlbq_m_s8): Likewise.
7887 (vmovltq_m_s8): Likewise.
7888 (vmovnbq_m_s16): Likewise.
7889 (vmovntq_m_s16): Likewise.
7890 (vnegq_m_f16): Likewise.
7891 (vpselq_f16): Likewise.
7892 (vqmovnbq_m_s16): Likewise.
7893 (vqmovntq_m_s16): Likewise.
7894 (vrev32q_m_s8): Likewise.
7895 (vrev64q_m_f16): Likewise.
7896 (vrndaq_m_f16): Likewise.
7897 (vrndmq_m_f16): Likewise.
7898 (vrndnq_m_f16): Likewise.
7899 (vrndpq_m_f16): Likewise.
7900 (vrndq_m_f16): Likewise.
7901 (vrndxq_m_f16): Likewise.
7902 (vcmpeqq_m_n_f16): Likewise.
7903 (vcmpgeq_m_f16): Likewise.
7904 (vcmpgeq_m_n_f16): Likewise.
7905 (vcmpgtq_m_f16): Likewise.
7906 (vcmpgtq_m_n_f16): Likewise.
7907 (vcmpleq_m_f16): Likewise.
7908 (vcmpleq_m_n_f16): Likewise.
7909 (vcmpltq_m_f16): Likewise.
7910 (vcmpltq_m_n_f16): Likewise.
7911 (vcmpneq_m_f16): Likewise.
7912 (vcmpneq_m_n_f16): Likewise.
7913 (vmvnq_m_n_u16): Likewise.
7914 (vorrq_m_n_u16): Likewise.
7915 (vqrshruntq_n_s16): Likewise.
7916 (vqshrunbq_n_s16): Likewise.
7917 (vqshruntq_n_s16): Likewise.
7918 (vcvtmq_m_u16_f16): Likewise.
7919 (vcvtnq_m_u16_f16): Likewise.
7920 (vcvtpq_m_u16_f16): Likewise.
7921 (vcvtq_m_u16_f16): Likewise.
7922 (vqmovunbq_m_s16): Likewise.
7923 (vqmovuntq_m_s16): Likewise.
7924 (vqrshrntq_n_u16): Likewise.
7925 (vqshrnbq_n_u16): Likewise.
7926 (vqshrntq_n_u16): Likewise.
7927 (vrshrnbq_n_u16): Likewise.
7928 (vrshrntq_n_u16): Likewise.
7929 (vshrnbq_n_u16): Likewise.
7930 (vshrntq_n_u16): Likewise.
7931 (vmlaldavaq_u16): Likewise.
7932 (vmlaldavaxq_u16): Likewise.
7933 (vmlaldavq_p_u16): Likewise.
7934 (vmlaldavxq_p_u16): Likewise.
7935 (vmovlbq_m_u8): Likewise.
7936 (vmovltq_m_u8): Likewise.
7937 (vmovnbq_m_u16): Likewise.
7938 (vmovntq_m_u16): Likewise.
7939 (vqmovnbq_m_u16): Likewise.
7940 (vqmovntq_m_u16): Likewise.
7941 (vrev32q_m_u8): Likewise.
7942 (vmvnq_m_n_s32): Likewise.
7943 (vorrq_m_n_s32): Likewise.
7944 (vqrshrntq_n_s32): Likewise.
7945 (vqshrnbq_n_s32): Likewise.
7946 (vqshrntq_n_s32): Likewise.
7947 (vrshrnbq_n_s32): Likewise.
7948 (vrshrntq_n_s32): Likewise.
7949 (vshrnbq_n_s32): Likewise.
7950 (vshrntq_n_s32): Likewise.
7951 (vcmlaq_f32): Likewise.
7952 (vcmlaq_rot180_f32): Likewise.
7953 (vcmlaq_rot270_f32): Likewise.
7954 (vcmlaq_rot90_f32): Likewise.
7955 (vfmaq_f32): Likewise.
7956 (vfmaq_n_f32): Likewise.
7957 (vfmasq_n_f32): Likewise.
7958 (vfmsq_f32): Likewise.
7959 (vmlaldavaq_s32): Likewise.
7960 (vmlaldavaxq_s32): Likewise.
7961 (vmlsldavaq_s32): Likewise.
7962 (vmlsldavaxq_s32): Likewise.
7963 (vabsq_m_f32): Likewise.
7964 (vcvtmq_m_s32_f32): Likewise.
7965 (vcvtnq_m_s32_f32): Likewise.
7966 (vcvtpq_m_s32_f32): Likewise.
7967 (vcvtq_m_s32_f32): Likewise.
7968 (vdupq_m_n_f32): Likewise.
7969 (vmaxnmaq_m_f32): Likewise.
7970 (vmaxnmavq_p_f32): Likewise.
7971 (vmaxnmvq_p_f32): Likewise.
7972 (vminnmaq_m_f32): Likewise.
7973 (vminnmavq_p_f32): Likewise.
7974 (vminnmvq_p_f32): Likewise.
7975 (vmlaldavq_p_s32): Likewise.
7976 (vmlaldavxq_p_s32): Likewise.
7977 (vmlsldavq_p_s32): Likewise.
7978 (vmlsldavxq_p_s32): Likewise.
7979 (vmovlbq_m_s16): Likewise.
7980 (vmovltq_m_s16): Likewise.
7981 (vmovnbq_m_s32): Likewise.
7982 (vmovntq_m_s32): Likewise.
7983 (vnegq_m_f32): Likewise.
7984 (vpselq_f32): Likewise.
7985 (vqmovnbq_m_s32): Likewise.
7986 (vqmovntq_m_s32): Likewise.
7987 (vrev32q_m_s16): Likewise.
7988 (vrev64q_m_f32): Likewise.
7989 (vrndaq_m_f32): Likewise.
7990 (vrndmq_m_f32): Likewise.
7991 (vrndnq_m_f32): Likewise.
7992 (vrndpq_m_f32): Likewise.
7993 (vrndq_m_f32): Likewise.
7994 (vrndxq_m_f32): Likewise.
7995 (vcmpeqq_m_n_f32): Likewise.
7996 (vcmpgeq_m_f32): Likewise.
7997 (vcmpgeq_m_n_f32): Likewise.
7998 (vcmpgtq_m_f32): Likewise.
7999 (vcmpgtq_m_n_f32): Likewise.
8000 (vcmpleq_m_f32): Likewise.
8001 (vcmpleq_m_n_f32): Likewise.
8002 (vcmpltq_m_f32): Likewise.
8003 (vcmpltq_m_n_f32): Likewise.
8004 (vcmpneq_m_f32): Likewise.
8005 (vcmpneq_m_n_f32): Likewise.
8006 (vmvnq_m_n_u32): Likewise.
8007 (vorrq_m_n_u32): Likewise.
8008 (vqrshruntq_n_s32): Likewise.
8009 (vqshrunbq_n_s32): Likewise.
8010 (vqshruntq_n_s32): Likewise.
8011 (vcvtmq_m_u32_f32): Likewise.
8012 (vcvtnq_m_u32_f32): Likewise.
8013 (vcvtpq_m_u32_f32): Likewise.
8014 (vcvtq_m_u32_f32): Likewise.
8015 (vqmovunbq_m_s32): Likewise.
8016 (vqmovuntq_m_s32): Likewise.
8017 (vqrshrntq_n_u32): Likewise.
8018 (vqshrnbq_n_u32): Likewise.
8019 (vqshrntq_n_u32): Likewise.
8020 (vrshrnbq_n_u32): Likewise.
8021 (vrshrntq_n_u32): Likewise.
8022 (vshrnbq_n_u32): Likewise.
8023 (vshrntq_n_u32): Likewise.
8024 (vmlaldavaq_u32): Likewise.
8025 (vmlaldavaxq_u32): Likewise.
8026 (vmlaldavq_p_u32): Likewise.
8027 (vmlaldavxq_p_u32): Likewise.
8028 (vmovlbq_m_u16): Likewise.
8029 (vmovltq_m_u16): Likewise.
8030 (vmovnbq_m_u32): Likewise.
8031 (vmovntq_m_u32): Likewise.
8032 (vqmovnbq_m_u32): Likewise.
8033 (vqmovntq_m_u32): Likewise.
8034 (vrev32q_m_u16): Likewise.
8035 (__arm_vrmlaldavhaxq_s32): Define intrinsic.
8036 (__arm_vrmlsldavhaq_s32): Likewise.
8037 (__arm_vrmlsldavhaxq_s32): Likewise.
8038 (__arm_vaddlvaq_p_s32): Likewise.
8039 (__arm_vrev16q_m_s8): Likewise.
8040 (__arm_vrmlaldavhq_p_s32): Likewise.
8041 (__arm_vrmlaldavhxq_p_s32): Likewise.
8042 (__arm_vrmlsldavhq_p_s32): Likewise.
8043 (__arm_vrmlsldavhxq_p_s32): Likewise.
8044 (__arm_vaddlvaq_p_u32): Likewise.
8045 (__arm_vrev16q_m_u8): Likewise.
8046 (__arm_vrmlaldavhq_p_u32): Likewise.
8047 (__arm_vmvnq_m_n_s16): Likewise.
8048 (__arm_vorrq_m_n_s16): Likewise.
8049 (__arm_vqrshrntq_n_s16): Likewise.
8050 (__arm_vqshrnbq_n_s16): Likewise.
8051 (__arm_vqshrntq_n_s16): Likewise.
8052 (__arm_vrshrnbq_n_s16): Likewise.
8053 (__arm_vrshrntq_n_s16): Likewise.
8054 (__arm_vshrnbq_n_s16): Likewise.
8055 (__arm_vshrntq_n_s16): Likewise.
8056 (__arm_vmlaldavaq_s16): Likewise.
8057 (__arm_vmlaldavaxq_s16): Likewise.
8058 (__arm_vmlsldavaq_s16): Likewise.
8059 (__arm_vmlsldavaxq_s16): Likewise.
8060 (__arm_vmlaldavq_p_s16): Likewise.
8061 (__arm_vmlaldavxq_p_s16): Likewise.
8062 (__arm_vmlsldavq_p_s16): Likewise.
8063 (__arm_vmlsldavxq_p_s16): Likewise.
8064 (__arm_vmovlbq_m_s8): Likewise.
8065 (__arm_vmovltq_m_s8): Likewise.
8066 (__arm_vmovnbq_m_s16): Likewise.
8067 (__arm_vmovntq_m_s16): Likewise.
8068 (__arm_vqmovnbq_m_s16): Likewise.
8069 (__arm_vqmovntq_m_s16): Likewise.
8070 (__arm_vrev32q_m_s8): Likewise.
8071 (__arm_vmvnq_m_n_u16): Likewise.
8072 (__arm_vorrq_m_n_u16): Likewise.
8073 (__arm_vqrshruntq_n_s16): Likewise.
8074 (__arm_vqshrunbq_n_s16): Likewise.
8075 (__arm_vqshruntq_n_s16): Likewise.
8076 (__arm_vqmovunbq_m_s16): Likewise.
8077 (__arm_vqmovuntq_m_s16): Likewise.
8078 (__arm_vqrshrntq_n_u16): Likewise.
8079 (__arm_vqshrnbq_n_u16): Likewise.
8080 (__arm_vqshrntq_n_u16): Likewise.
8081 (__arm_vrshrnbq_n_u16): Likewise.
8082 (__arm_vrshrntq_n_u16): Likewise.
8083 (__arm_vshrnbq_n_u16): Likewise.
8084 (__arm_vshrntq_n_u16): Likewise.
8085 (__arm_vmlaldavaq_u16): Likewise.
8086 (__arm_vmlaldavaxq_u16): Likewise.
8087 (__arm_vmlaldavq_p_u16): Likewise.
8088 (__arm_vmlaldavxq_p_u16): Likewise.
8089 (__arm_vmovlbq_m_u8): Likewise.
8090 (__arm_vmovltq_m_u8): Likewise.
8091 (__arm_vmovnbq_m_u16): Likewise.
8092 (__arm_vmovntq_m_u16): Likewise.
8093 (__arm_vqmovnbq_m_u16): Likewise.
8094 (__arm_vqmovntq_m_u16): Likewise.
8095 (__arm_vrev32q_m_u8): Likewise.
8096 (__arm_vmvnq_m_n_s32): Likewise.
8097 (__arm_vorrq_m_n_s32): Likewise.
8098 (__arm_vqrshrntq_n_s32): Likewise.
8099 (__arm_vqshrnbq_n_s32): Likewise.
8100 (__arm_vqshrntq_n_s32): Likewise.
8101 (__arm_vrshrnbq_n_s32): Likewise.
8102 (__arm_vrshrntq_n_s32): Likewise.
8103 (__arm_vshrnbq_n_s32): Likewise.
8104 (__arm_vshrntq_n_s32): Likewise.
8105 (__arm_vmlaldavaq_s32): Likewise.
8106 (__arm_vmlaldavaxq_s32): Likewise.
8107 (__arm_vmlsldavaq_s32): Likewise.
8108 (__arm_vmlsldavaxq_s32): Likewise.
8109 (__arm_vmlaldavq_p_s32): Likewise.
8110 (__arm_vmlaldavxq_p_s32): Likewise.
8111 (__arm_vmlsldavq_p_s32): Likewise.
8112 (__arm_vmlsldavxq_p_s32): Likewise.
8113 (__arm_vmovlbq_m_s16): Likewise.
8114 (__arm_vmovltq_m_s16): Likewise.
8115 (__arm_vmovnbq_m_s32): Likewise.
8116 (__arm_vmovntq_m_s32): Likewise.
8117 (__arm_vqmovnbq_m_s32): Likewise.
8118 (__arm_vqmovntq_m_s32): Likewise.
8119 (__arm_vrev32q_m_s16): Likewise.
8120 (__arm_vmvnq_m_n_u32): Likewise.
8121 (__arm_vorrq_m_n_u32): Likewise.
8122 (__arm_vqrshruntq_n_s32): Likewise.
8123 (__arm_vqshrunbq_n_s32): Likewise.
8124 (__arm_vqshruntq_n_s32): Likewise.
8125 (__arm_vqmovunbq_m_s32): Likewise.
8126 (__arm_vqmovuntq_m_s32): Likewise.
8127 (__arm_vqrshrntq_n_u32): Likewise.
8128 (__arm_vqshrnbq_n_u32): Likewise.
8129 (__arm_vqshrntq_n_u32): Likewise.
8130 (__arm_vrshrnbq_n_u32): Likewise.
8131 (__arm_vrshrntq_n_u32): Likewise.
8132 (__arm_vshrnbq_n_u32): Likewise.
8133 (__arm_vshrntq_n_u32): Likewise.
8134 (__arm_vmlaldavaq_u32): Likewise.
8135 (__arm_vmlaldavaxq_u32): Likewise.
8136 (__arm_vmlaldavq_p_u32): Likewise.
8137 (__arm_vmlaldavxq_p_u32): Likewise.
8138 (__arm_vmovlbq_m_u16): Likewise.
8139 (__arm_vmovltq_m_u16): Likewise.
8140 (__arm_vmovnbq_m_u32): Likewise.
8141 (__arm_vmovntq_m_u32): Likewise.
8142 (__arm_vqmovnbq_m_u32): Likewise.
8143 (__arm_vqmovntq_m_u32): Likewise.
8144 (__arm_vrev32q_m_u16): Likewise.
8145 (__arm_vcvtbq_m_f16_f32): Likewise.
8146 (__arm_vcvtbq_m_f32_f16): Likewise.
8147 (__arm_vcvttq_m_f16_f32): Likewise.
8148 (__arm_vcvttq_m_f32_f16): Likewise.
8149 (__arm_vrev32q_m_f16): Likewise.
8150 (__arm_vcmlaq_f16): Likewise.
8151 (__arm_vcmlaq_rot180_f16): Likewise.
8152 (__arm_vcmlaq_rot270_f16): Likewise.
8153 (__arm_vcmlaq_rot90_f16): Likewise.
8154 (__arm_vfmaq_f16): Likewise.
8155 (__arm_vfmaq_n_f16): Likewise.
8156 (__arm_vfmasq_n_f16): Likewise.
8157 (__arm_vfmsq_f16): Likewise.
8158 (__arm_vabsq_m_f16): Likewise.
8159 (__arm_vcvtmq_m_s16_f16): Likewise.
8160 (__arm_vcvtnq_m_s16_f16): Likewise.
8161 (__arm_vcvtpq_m_s16_f16): Likewise.
8162 (__arm_vcvtq_m_s16_f16): Likewise.
8163 (__arm_vdupq_m_n_f16): Likewise.
8164 (__arm_vmaxnmaq_m_f16): Likewise.
8165 (__arm_vmaxnmavq_p_f16): Likewise.
8166 (__arm_vmaxnmvq_p_f16): Likewise.
8167 (__arm_vminnmaq_m_f16): Likewise.
8168 (__arm_vminnmavq_p_f16): Likewise.
8169 (__arm_vminnmvq_p_f16): Likewise.
8170 (__arm_vnegq_m_f16): Likewise.
8171 (__arm_vpselq_f16): Likewise.
8172 (__arm_vrev64q_m_f16): Likewise.
8173 (__arm_vrndaq_m_f16): Likewise.
8174 (__arm_vrndmq_m_f16): Likewise.
8175 (__arm_vrndnq_m_f16): Likewise.
8176 (__arm_vrndpq_m_f16): Likewise.
8177 (__arm_vrndq_m_f16): Likewise.
8178 (__arm_vrndxq_m_f16): Likewise.
8179 (__arm_vcmpeqq_m_n_f16): Likewise.
8180 (__arm_vcmpgeq_m_f16): Likewise.
8181 (__arm_vcmpgeq_m_n_f16): Likewise.
8182 (__arm_vcmpgtq_m_f16): Likewise.
8183 (__arm_vcmpgtq_m_n_f16): Likewise.
8184 (__arm_vcmpleq_m_f16): Likewise.
8185 (__arm_vcmpleq_m_n_f16): Likewise.
8186 (__arm_vcmpltq_m_f16): Likewise.
8187 (__arm_vcmpltq_m_n_f16): Likewise.
8188 (__arm_vcmpneq_m_f16): Likewise.
8189 (__arm_vcmpneq_m_n_f16): Likewise.
8190 (__arm_vcvtmq_m_u16_f16): Likewise.
8191 (__arm_vcvtnq_m_u16_f16): Likewise.
8192 (__arm_vcvtpq_m_u16_f16): Likewise.
8193 (__arm_vcvtq_m_u16_f16): Likewise.
8194 (__arm_vcmlaq_f32): Likewise.
8195 (__arm_vcmlaq_rot180_f32): Likewise.
8196 (__arm_vcmlaq_rot270_f32): Likewise.
8197 (__arm_vcmlaq_rot90_f32): Likewise.
8198 (__arm_vfmaq_f32): Likewise.
8199 (__arm_vfmaq_n_f32): Likewise.
8200 (__arm_vfmasq_n_f32): Likewise.
8201 (__arm_vfmsq_f32): Likewise.
8202 (__arm_vabsq_m_f32): Likewise.
8203 (__arm_vcvtmq_m_s32_f32): Likewise.
8204 (__arm_vcvtnq_m_s32_f32): Likewise.
8205 (__arm_vcvtpq_m_s32_f32): Likewise.
8206 (__arm_vcvtq_m_s32_f32): Likewise.
8207 (__arm_vdupq_m_n_f32): Likewise.
8208 (__arm_vmaxnmaq_m_f32): Likewise.
8209 (__arm_vmaxnmavq_p_f32): Likewise.
8210 (__arm_vmaxnmvq_p_f32): Likewise.
8211 (__arm_vminnmaq_m_f32): Likewise.
8212 (__arm_vminnmavq_p_f32): Likewise.
8213 (__arm_vminnmvq_p_f32): Likewise.
8214 (__arm_vnegq_m_f32): Likewise.
8215 (__arm_vpselq_f32): Likewise.
8216 (__arm_vrev64q_m_f32): Likewise.
8217 (__arm_vrndaq_m_f32): Likewise.
8218 (__arm_vrndmq_m_f32): Likewise.
8219 (__arm_vrndnq_m_f32): Likewise.
8220 (__arm_vrndpq_m_f32): Likewise.
8221 (__arm_vrndq_m_f32): Likewise.
8222 (__arm_vrndxq_m_f32): Likewise.
8223 (__arm_vcmpeqq_m_n_f32): Likewise.
8224 (__arm_vcmpgeq_m_f32): Likewise.
8225 (__arm_vcmpgeq_m_n_f32): Likewise.
8226 (__arm_vcmpgtq_m_f32): Likewise.
8227 (__arm_vcmpgtq_m_n_f32): Likewise.
8228 (__arm_vcmpleq_m_f32): Likewise.
8229 (__arm_vcmpleq_m_n_f32): Likewise.
8230 (__arm_vcmpltq_m_f32): Likewise.
8231 (__arm_vcmpltq_m_n_f32): Likewise.
8232 (__arm_vcmpneq_m_f32): Likewise.
8233 (__arm_vcmpneq_m_n_f32): Likewise.
8234 (__arm_vcvtmq_m_u32_f32): Likewise.
8235 (__arm_vcvtnq_m_u32_f32): Likewise.
8236 (__arm_vcvtpq_m_u32_f32): Likewise.
8237 (__arm_vcvtq_m_u32_f32): Likewise.
8238 (vcvtq_m): Define polymorphic variant.
8239 (vabsq_m): Likewise.
8241 (vcmlaq_rot180): Likewise.
8242 (vcmlaq_rot270): Likewise.
8243 (vcmlaq_rot90): Likewise.
8244 (vcmpeqq_m_n): Likewise.
8245 (vcmpgeq_m_n): Likewise.
8246 (vrndxq_m): Likewise.
8247 (vrndq_m): Likewise.
8248 (vrndpq_m): Likewise.
8249 (vcmpgtq_m_n): Likewise.
8250 (vcmpgtq_m): Likewise.
8251 (vcmpleq_m): Likewise.
8252 (vcmpleq_m_n): Likewise.
8253 (vcmpltq_m_n): Likewise.
8254 (vcmpltq_m): Likewise.
8255 (vcmpneq_m): Likewise.
8256 (vcmpneq_m_n): Likewise.
8257 (vcvtbq_m): Likewise.
8258 (vcvttq_m): Likewise.
8259 (vcvtmq_m): Likewise.
8260 (vcvtnq_m): Likewise.
8261 (vcvtpq_m): Likewise.
8262 (vdupq_m_n): Likewise.
8263 (vfmaq_n): Likewise.
8265 (vfmasq_n): Likewise.
8267 (vmaxnmaq_m): Likewise.
8268 (vmaxnmavq_m): Likewise.
8269 (vmaxnmvq_m): Likewise.
8270 (vmaxnmavq_p): Likewise.
8271 (vmaxnmvq_p): Likewise.
8272 (vminnmaq_m): Likewise.
8273 (vminnmavq_p): Likewise.
8274 (vminnmvq_p): Likewise.
8275 (vrndnq_m): Likewise.
8276 (vrndaq_m): Likewise.
8277 (vrndmq_m): Likewise.
8278 (vrev64q_m): Likewise.
8279 (vrev32q_m): Likewise.
8281 (vnegq_m): Likewise.
8282 (vcmpgeq_m): Likewise.
8283 (vshrntq_n): Likewise.
8284 (vrshrntq_n): Likewise.
8285 (vmovlbq_m): Likewise.
8286 (vmovnbq_m): Likewise.
8287 (vmovntq_m): Likewise.
8288 (vmvnq_m_n): Likewise.
8289 (vmvnq_m): Likewise.
8290 (vshrnbq_n): Likewise.
8291 (vrshrnbq_n): Likewise.
8292 (vqshruntq_n): Likewise.
8293 (vrev16q_m): Likewise.
8294 (vqshrunbq_n): Likewise.
8295 (vqshrntq_n): Likewise.
8296 (vqrshruntq_n): Likewise.
8297 (vqrshrntq_n): Likewise.
8298 (vqshrnbq_n): Likewise.
8299 (vqmovuntq_m): Likewise.
8300 (vqmovntq_m): Likewise.
8301 (vqmovnbq_m): Likewise.
8302 (vorrq_m_n): Likewise.
8303 (vmovltq_m): Likewise.
8304 (vqmovunbq_m): Likewise.
8305 (vaddlvaq_p): Likewise.
8306 (vmlaldavaq): Likewise.
8307 (vmlaldavaxq): Likewise.
8308 (vmlaldavq_p): Likewise.
8309 (vmlaldavxq_p): Likewise.
8310 (vmlsldavaq): Likewise.
8311 (vmlsldavaxq): Likewise.
8312 (vmlsldavq_p): Likewise.
8313 (vmlsldavxq_p): Likewise.
8314 (vrmlaldavhaxq): Likewise.
8315 (vrmlaldavhq_p): Likewise.
8316 (vrmlaldavhxq_p): Likewise.
8317 (vrmlsldavhaq): Likewise.
8318 (vrmlsldavhaxq): Likewise.
8319 (vrmlsldavhq_p): Likewise.
8320 (vrmlsldavhxq_p): Likewise.
8321 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use
8323 (TERNOP_NONE_NONE_NONE_IMM): Likewise.
8324 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
8325 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
8326 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
8327 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise.
8328 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise.
8329 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
8330 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
8331 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
8332 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator.
8333 (MVE_pred3): Likewise.
8334 (MVE_constraint1): Likewise.
8335 (MVE_pred1): Likewise.
8336 (VMLALDAVQ_P): Define iterator.
8337 (VQMOVNBQ_M): Likewise.
8338 (VMOVLTQ_M): Likewise.
8339 (VMOVNBQ_M): Likewise.
8340 (VRSHRNTQ_N): Likewise.
8341 (VORRQ_M_N): Likewise.
8342 (VREV32Q_M): Likewise.
8343 (VREV16Q_M): Likewise.
8344 (VQRSHRNTQ_N): Likewise.
8345 (VMOVNTQ_M): Likewise.
8346 (VMOVLBQ_M): Likewise.
8347 (VMLALDAVAQ): Likewise.
8348 (VQSHRNBQ_N): Likewise.
8349 (VSHRNBQ_N): Likewise.
8350 (VRSHRNBQ_N): Likewise.
8351 (VMLALDAVXQ_P): Likewise.
8352 (VQMOVNTQ_M): Likewise.
8353 (VMVNQ_M_N): Likewise.
8354 (VQSHRNTQ_N): Likewise.
8355 (VMLALDAVAXQ): Likewise.
8356 (VSHRNTQ_N): Likewise.
8357 (VCVTMQ_M): Likewise.
8358 (VCVTNQ_M): Likewise.
8359 (VCVTPQ_M): Likewise.
8360 (VCVTQ_M_N_FROM_F): Likewise.
8361 (VCVTQ_M_FROM_F): Likewise.
8362 (VRMLALDAVHQ_P): Likewise.
8363 (VADDLVAQ_P): Likewise.
8364 (mve_vrndq_m_f<mode>): Define RTL pattern.
8365 (mve_vabsq_m_f<mode>): Likewise.
8366 (mve_vaddlvaq_p_<supf>v4si): Likewise.
8367 (mve_vcmlaq_f<mode>): Likewise.
8368 (mve_vcmlaq_rot180_f<mode>): Likewise.
8369 (mve_vcmlaq_rot270_f<mode>): Likewise.
8370 (mve_vcmlaq_rot90_f<mode>): Likewise.
8371 (mve_vcmpeqq_m_n_f<mode>): Likewise.
8372 (mve_vcmpgeq_m_f<mode>): Likewise.
8373 (mve_vcmpgeq_m_n_f<mode>): Likewise.
8374 (mve_vcmpgtq_m_f<mode>): Likewise.
8375 (mve_vcmpgtq_m_n_f<mode>): Likewise.
8376 (mve_vcmpleq_m_f<mode>): Likewise.
8377 (mve_vcmpleq_m_n_f<mode>): Likewise.
8378 (mve_vcmpltq_m_f<mode>): Likewise.
8379 (mve_vcmpltq_m_n_f<mode>): Likewise.
8380 (mve_vcmpneq_m_f<mode>): Likewise.
8381 (mve_vcmpneq_m_n_f<mode>): Likewise.
8382 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
8383 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
8384 (mve_vcvttq_m_f16_f32v8hf): Likewise.
8385 (mve_vcvttq_m_f32_f16v4sf): Likewise.
8386 (mve_vdupq_m_n_f<mode>): Likewise.
8387 (mve_vfmaq_f<mode>): Likewise.
8388 (mve_vfmaq_n_f<mode>): Likewise.
8389 (mve_vfmasq_n_f<mode>): Likewise.
8390 (mve_vfmsq_f<mode>): Likewise.
8391 (mve_vmaxnmaq_m_f<mode>): Likewise.
8392 (mve_vmaxnmavq_p_f<mode>): Likewise.
8393 (mve_vmaxnmvq_p_f<mode>): Likewise.
8394 (mve_vminnmaq_m_f<mode>): Likewise.
8395 (mve_vminnmavq_p_f<mode>): Likewise.
8396 (mve_vminnmvq_p_f<mode>): Likewise.
8397 (mve_vmlaldavaq_<supf><mode>): Likewise.
8398 (mve_vmlaldavaxq_<supf><mode>): Likewise.
8399 (mve_vmlaldavq_p_<supf><mode>): Likewise.
8400 (mve_vmlaldavxq_p_<supf><mode>): Likewise.
8401 (mve_vmlsldavaq_s<mode>): Likewise.
8402 (mve_vmlsldavaxq_s<mode>): Likewise.
8403 (mve_vmlsldavq_p_s<mode>): Likewise.
8404 (mve_vmlsldavxq_p_s<mode>): Likewise.
8405 (mve_vmovlbq_m_<supf><mode>): Likewise.
8406 (mve_vmovltq_m_<supf><mode>): Likewise.
8407 (mve_vmovnbq_m_<supf><mode>): Likewise.
8408 (mve_vmovntq_m_<supf><mode>): Likewise.
8409 (mve_vmvnq_m_n_<supf><mode>): Likewise.
8410 (mve_vnegq_m_f<mode>): Likewise.
8411 (mve_vorrq_m_n_<supf><mode>): Likewise.
8412 (mve_vpselq_f<mode>): Likewise.
8413 (mve_vqmovnbq_m_<supf><mode>): Likewise.
8414 (mve_vqmovntq_m_<supf><mode>): Likewise.
8415 (mve_vqmovunbq_m_s<mode>): Likewise.
8416 (mve_vqmovuntq_m_s<mode>): Likewise.
8417 (mve_vqrshrntq_n_<supf><mode>): Likewise.
8418 (mve_vqrshruntq_n_s<mode>): Likewise.
8419 (mve_vqshrnbq_n_<supf><mode>): Likewise.
8420 (mve_vqshrntq_n_<supf><mode>): Likewise.
8421 (mve_vqshrunbq_n_s<mode>): Likewise.
8422 (mve_vqshruntq_n_s<mode>): Likewise.
8423 (mve_vrev32q_m_fv8hf): Likewise.
8424 (mve_vrev32q_m_<supf><mode>): Likewise.
8425 (mve_vrev64q_m_f<mode>): Likewise.
8426 (mve_vrmlaldavhaxq_sv4si): Likewise.
8427 (mve_vrmlaldavhxq_p_sv4si): Likewise.
8428 (mve_vrmlsldavhaxq_sv4si): Likewise.
8429 (mve_vrmlsldavhq_p_sv4si): Likewise.
8430 (mve_vrmlsldavhxq_p_sv4si): Likewise.
8431 (mve_vrndaq_m_f<mode>): Likewise.
8432 (mve_vrndmq_m_f<mode>): Likewise.
8433 (mve_vrndnq_m_f<mode>): Likewise.
8434 (mve_vrndpq_m_f<mode>): Likewise.
8435 (mve_vrndxq_m_f<mode>): Likewise.
8436 (mve_vrshrnbq_n_<supf><mode>): Likewise.
8437 (mve_vrshrntq_n_<supf><mode>): Likewise.
8438 (mve_vshrnbq_n_<supf><mode>): Likewise.
8439 (mve_vshrntq_n_<supf><mode>): Likewise.
8440 (mve_vcvtmq_m_<supf><mode>): Likewise.
8441 (mve_vcvtpq_m_<supf><mode>): Likewise.
8442 (mve_vcvtnq_m_<supf><mode>): Likewise.
8443 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
8444 (mve_vrev16q_m_<supf>v16qi): Likewise.
8445 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
8446 (mve_vrmlaldavhq_p_<supf>v4si): Likewise.
8447 (mve_vrmlsldavhaq_sv4si): Likewise.
8449 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8450 Mihail Ionescu <mihail.ionescu@arm.com>
8451 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8453 * config/arm/arm_mve.h (vpselq_u8): Define macro.
8454 (vpselq_s8): Likewise.
8455 (vrev64q_m_u8): Likewise.
8456 (vqrdmlashq_n_u8): Likewise.
8457 (vqrdmlahq_n_u8): Likewise.
8458 (vqdmlahq_n_u8): Likewise.
8459 (vmvnq_m_u8): Likewise.
8460 (vmlasq_n_u8): Likewise.
8461 (vmlaq_n_u8): Likewise.
8462 (vmladavq_p_u8): Likewise.
8463 (vmladavaq_u8): Likewise.
8464 (vminvq_p_u8): Likewise.
8465 (vmaxvq_p_u8): Likewise.
8466 (vdupq_m_n_u8): Likewise.
8467 (vcmpneq_m_u8): Likewise.
8468 (vcmpneq_m_n_u8): Likewise.
8469 (vcmphiq_m_u8): Likewise.
8470 (vcmphiq_m_n_u8): Likewise.
8471 (vcmpeqq_m_u8): Likewise.
8472 (vcmpeqq_m_n_u8): Likewise.
8473 (vcmpcsq_m_u8): Likewise.
8474 (vcmpcsq_m_n_u8): Likewise.
8475 (vclzq_m_u8): Likewise.
8476 (vaddvaq_p_u8): Likewise.
8477 (vsriq_n_u8): Likewise.
8478 (vsliq_n_u8): Likewise.
8479 (vshlq_m_r_u8): Likewise.
8480 (vrshlq_m_n_u8): Likewise.
8481 (vqshlq_m_r_u8): Likewise.
8482 (vqrshlq_m_n_u8): Likewise.
8483 (vminavq_p_s8): Likewise.
8484 (vminaq_m_s8): Likewise.
8485 (vmaxavq_p_s8): Likewise.
8486 (vmaxaq_m_s8): Likewise.
8487 (vcmpneq_m_s8): Likewise.
8488 (vcmpneq_m_n_s8): Likewise.
8489 (vcmpltq_m_s8): Likewise.
8490 (vcmpltq_m_n_s8): Likewise.
8491 (vcmpleq_m_s8): Likewise.
8492 (vcmpleq_m_n_s8): Likewise.
8493 (vcmpgtq_m_s8): Likewise.
8494 (vcmpgtq_m_n_s8): Likewise.
8495 (vcmpgeq_m_s8): Likewise.
8496 (vcmpgeq_m_n_s8): Likewise.
8497 (vcmpeqq_m_s8): Likewise.
8498 (vcmpeqq_m_n_s8): Likewise.
8499 (vshlq_m_r_s8): Likewise.
8500 (vrshlq_m_n_s8): Likewise.
8501 (vrev64q_m_s8): Likewise.
8502 (vqshlq_m_r_s8): Likewise.
8503 (vqrshlq_m_n_s8): Likewise.
8504 (vqnegq_m_s8): Likewise.
8505 (vqabsq_m_s8): Likewise.
8506 (vnegq_m_s8): Likewise.
8507 (vmvnq_m_s8): Likewise.
8508 (vmlsdavxq_p_s8): Likewise.
8509 (vmlsdavq_p_s8): Likewise.
8510 (vmladavxq_p_s8): Likewise.
8511 (vmladavq_p_s8): Likewise.
8512 (vminvq_p_s8): Likewise.
8513 (vmaxvq_p_s8): Likewise.
8514 (vdupq_m_n_s8): Likewise.
8515 (vclzq_m_s8): Likewise.
8516 (vclsq_m_s8): Likewise.
8517 (vaddvaq_p_s8): Likewise.
8518 (vabsq_m_s8): Likewise.
8519 (vqrdmlsdhxq_s8): Likewise.
8520 (vqrdmlsdhq_s8): Likewise.
8521 (vqrdmlashq_n_s8): Likewise.
8522 (vqrdmlahq_n_s8): Likewise.
8523 (vqrdmladhxq_s8): Likewise.
8524 (vqrdmladhq_s8): Likewise.
8525 (vqdmlsdhxq_s8): Likewise.
8526 (vqdmlsdhq_s8): Likewise.
8527 (vqdmlahq_n_s8): Likewise.
8528 (vqdmladhxq_s8): Likewise.
8529 (vqdmladhq_s8): Likewise.
8530 (vmlsdavaxq_s8): Likewise.
8531 (vmlsdavaq_s8): Likewise.
8532 (vmlasq_n_s8): Likewise.
8533 (vmlaq_n_s8): Likewise.
8534 (vmladavaxq_s8): Likewise.
8535 (vmladavaq_s8): Likewise.
8536 (vsriq_n_s8): Likewise.
8537 (vsliq_n_s8): Likewise.
8538 (vpselq_u16): Likewise.
8539 (vpselq_s16): Likewise.
8540 (vrev64q_m_u16): Likewise.
8541 (vqrdmlashq_n_u16): Likewise.
8542 (vqrdmlahq_n_u16): Likewise.
8543 (vqdmlahq_n_u16): Likewise.
8544 (vmvnq_m_u16): Likewise.
8545 (vmlasq_n_u16): Likewise.
8546 (vmlaq_n_u16): Likewise.
8547 (vmladavq_p_u16): Likewise.
8548 (vmladavaq_u16): Likewise.
8549 (vminvq_p_u16): Likewise.
8550 (vmaxvq_p_u16): Likewise.
8551 (vdupq_m_n_u16): Likewise.
8552 (vcmpneq_m_u16): Likewise.
8553 (vcmpneq_m_n_u16): Likewise.
8554 (vcmphiq_m_u16): Likewise.
8555 (vcmphiq_m_n_u16): Likewise.
8556 (vcmpeqq_m_u16): Likewise.
8557 (vcmpeqq_m_n_u16): Likewise.
8558 (vcmpcsq_m_u16): Likewise.
8559 (vcmpcsq_m_n_u16): Likewise.
8560 (vclzq_m_u16): Likewise.
8561 (vaddvaq_p_u16): Likewise.
8562 (vsriq_n_u16): Likewise.
8563 (vsliq_n_u16): Likewise.
8564 (vshlq_m_r_u16): Likewise.
8565 (vrshlq_m_n_u16): Likewise.
8566 (vqshlq_m_r_u16): Likewise.
8567 (vqrshlq_m_n_u16): Likewise.
8568 (vminavq_p_s16): Likewise.
8569 (vminaq_m_s16): Likewise.
8570 (vmaxavq_p_s16): Likewise.
8571 (vmaxaq_m_s16): Likewise.
8572 (vcmpneq_m_s16): Likewise.
8573 (vcmpneq_m_n_s16): Likewise.
8574 (vcmpltq_m_s16): Likewise.
8575 (vcmpltq_m_n_s16): Likewise.
8576 (vcmpleq_m_s16): Likewise.
8577 (vcmpleq_m_n_s16): Likewise.
8578 (vcmpgtq_m_s16): Likewise.
8579 (vcmpgtq_m_n_s16): Likewise.
8580 (vcmpgeq_m_s16): Likewise.
8581 (vcmpgeq_m_n_s16): Likewise.
8582 (vcmpeqq_m_s16): Likewise.
8583 (vcmpeqq_m_n_s16): Likewise.
8584 (vshlq_m_r_s16): Likewise.
8585 (vrshlq_m_n_s16): Likewise.
8586 (vrev64q_m_s16): Likewise.
8587 (vqshlq_m_r_s16): Likewise.
8588 (vqrshlq_m_n_s16): Likewise.
8589 (vqnegq_m_s16): Likewise.
8590 (vqabsq_m_s16): Likewise.
8591 (vnegq_m_s16): Likewise.
8592 (vmvnq_m_s16): Likewise.
8593 (vmlsdavxq_p_s16): Likewise.
8594 (vmlsdavq_p_s16): Likewise.
8595 (vmladavxq_p_s16): Likewise.
8596 (vmladavq_p_s16): Likewise.
8597 (vminvq_p_s16): Likewise.
8598 (vmaxvq_p_s16): Likewise.
8599 (vdupq_m_n_s16): Likewise.
8600 (vclzq_m_s16): Likewise.
8601 (vclsq_m_s16): Likewise.
8602 (vaddvaq_p_s16): Likewise.
8603 (vabsq_m_s16): Likewise.
8604 (vqrdmlsdhxq_s16): Likewise.
8605 (vqrdmlsdhq_s16): Likewise.
8606 (vqrdmlashq_n_s16): Likewise.
8607 (vqrdmlahq_n_s16): Likewise.
8608 (vqrdmladhxq_s16): Likewise.
8609 (vqrdmladhq_s16): Likewise.
8610 (vqdmlsdhxq_s16): Likewise.
8611 (vqdmlsdhq_s16): Likewise.
8612 (vqdmlahq_n_s16): Likewise.
8613 (vqdmladhxq_s16): Likewise.
8614 (vqdmladhq_s16): Likewise.
8615 (vmlsdavaxq_s16): Likewise.
8616 (vmlsdavaq_s16): Likewise.
8617 (vmlasq_n_s16): Likewise.
8618 (vmlaq_n_s16): Likewise.
8619 (vmladavaxq_s16): Likewise.
8620 (vmladavaq_s16): Likewise.
8621 (vsriq_n_s16): Likewise.
8622 (vsliq_n_s16): Likewise.
8623 (vpselq_u32): Likewise.
8624 (vpselq_s32): Likewise.
8625 (vrev64q_m_u32): Likewise.
8626 (vqrdmlashq_n_u32): Likewise.
8627 (vqrdmlahq_n_u32): Likewise.
8628 (vqdmlahq_n_u32): Likewise.
8629 (vmvnq_m_u32): Likewise.
8630 (vmlasq_n_u32): Likewise.
8631 (vmlaq_n_u32): Likewise.
8632 (vmladavq_p_u32): Likewise.
8633 (vmladavaq_u32): Likewise.
8634 (vminvq_p_u32): Likewise.
8635 (vmaxvq_p_u32): Likewise.
8636 (vdupq_m_n_u32): Likewise.
8637 (vcmpneq_m_u32): Likewise.
8638 (vcmpneq_m_n_u32): Likewise.
8639 (vcmphiq_m_u32): Likewise.
8640 (vcmphiq_m_n_u32): Likewise.
8641 (vcmpeqq_m_u32): Likewise.
8642 (vcmpeqq_m_n_u32): Likewise.
8643 (vcmpcsq_m_u32): Likewise.
8644 (vcmpcsq_m_n_u32): Likewise.
8645 (vclzq_m_u32): Likewise.
8646 (vaddvaq_p_u32): Likewise.
8647 (vsriq_n_u32): Likewise.
8648 (vsliq_n_u32): Likewise.
8649 (vshlq_m_r_u32): Likewise.
8650 (vrshlq_m_n_u32): Likewise.
8651 (vqshlq_m_r_u32): Likewise.
8652 (vqrshlq_m_n_u32): Likewise.
8653 (vminavq_p_s32): Likewise.
8654 (vminaq_m_s32): Likewise.
8655 (vmaxavq_p_s32): Likewise.
8656 (vmaxaq_m_s32): Likewise.
8657 (vcmpneq_m_s32): Likewise.
8658 (vcmpneq_m_n_s32): Likewise.
8659 (vcmpltq_m_s32): Likewise.
8660 (vcmpltq_m_n_s32): Likewise.
8661 (vcmpleq_m_s32): Likewise.
8662 (vcmpleq_m_n_s32): Likewise.
8663 (vcmpgtq_m_s32): Likewise.
8664 (vcmpgtq_m_n_s32): Likewise.
8665 (vcmpgeq_m_s32): Likewise.
8666 (vcmpgeq_m_n_s32): Likewise.
8667 (vcmpeqq_m_s32): Likewise.
8668 (vcmpeqq_m_n_s32): Likewise.
8669 (vshlq_m_r_s32): Likewise.
8670 (vrshlq_m_n_s32): Likewise.
8671 (vrev64q_m_s32): Likewise.
8672 (vqshlq_m_r_s32): Likewise.
8673 (vqrshlq_m_n_s32): Likewise.
8674 (vqnegq_m_s32): Likewise.
8675 (vqabsq_m_s32): Likewise.
8676 (vnegq_m_s32): Likewise.
8677 (vmvnq_m_s32): Likewise.
8678 (vmlsdavxq_p_s32): Likewise.
8679 (vmlsdavq_p_s32): Likewise.
8680 (vmladavxq_p_s32): Likewise.
8681 (vmladavq_p_s32): Likewise.
8682 (vminvq_p_s32): Likewise.
8683 (vmaxvq_p_s32): Likewise.
8684 (vdupq_m_n_s32): Likewise.
8685 (vclzq_m_s32): Likewise.
8686 (vclsq_m_s32): Likewise.
8687 (vaddvaq_p_s32): Likewise.
8688 (vabsq_m_s32): Likewise.
8689 (vqrdmlsdhxq_s32): Likewise.
8690 (vqrdmlsdhq_s32): Likewise.
8691 (vqrdmlashq_n_s32): Likewise.
8692 (vqrdmlahq_n_s32): Likewise.
8693 (vqrdmladhxq_s32): Likewise.
8694 (vqrdmladhq_s32): Likewise.
8695 (vqdmlsdhxq_s32): Likewise.
8696 (vqdmlsdhq_s32): Likewise.
8697 (vqdmlahq_n_s32): Likewise.
8698 (vqdmladhxq_s32): Likewise.
8699 (vqdmladhq_s32): Likewise.
8700 (vmlsdavaxq_s32): Likewise.
8701 (vmlsdavaq_s32): Likewise.
8702 (vmlasq_n_s32): Likewise.
8703 (vmlaq_n_s32): Likewise.
8704 (vmladavaxq_s32): Likewise.
8705 (vmladavaq_s32): Likewise.
8706 (vsriq_n_s32): Likewise.
8707 (vsliq_n_s32): Likewise.
8708 (vpselq_u64): Likewise.
8709 (vpselq_s64): Likewise.
8710 (__arm_vpselq_u8): Define intrinsic.
8711 (__arm_vpselq_s8): Likewise.
8712 (__arm_vrev64q_m_u8): Likewise.
8713 (__arm_vqrdmlashq_n_u8): Likewise.
8714 (__arm_vqrdmlahq_n_u8): Likewise.
8715 (__arm_vqdmlahq_n_u8): Likewise.
8716 (__arm_vmvnq_m_u8): Likewise.
8717 (__arm_vmlasq_n_u8): Likewise.
8718 (__arm_vmlaq_n_u8): Likewise.
8719 (__arm_vmladavq_p_u8): Likewise.
8720 (__arm_vmladavaq_u8): Likewise.
8721 (__arm_vminvq_p_u8): Likewise.
8722 (__arm_vmaxvq_p_u8): Likewise.
8723 (__arm_vdupq_m_n_u8): Likewise.
8724 (__arm_vcmpneq_m_u8): Likewise.
8725 (__arm_vcmpneq_m_n_u8): Likewise.
8726 (__arm_vcmphiq_m_u8): Likewise.
8727 (__arm_vcmphiq_m_n_u8): Likewise.
8728 (__arm_vcmpeqq_m_u8): Likewise.
8729 (__arm_vcmpeqq_m_n_u8): Likewise.
8730 (__arm_vcmpcsq_m_u8): Likewise.
8731 (__arm_vcmpcsq_m_n_u8): Likewise.
8732 (__arm_vclzq_m_u8): Likewise.
8733 (__arm_vaddvaq_p_u8): Likewise.
8734 (__arm_vsriq_n_u8): Likewise.
8735 (__arm_vsliq_n_u8): Likewise.
8736 (__arm_vshlq_m_r_u8): Likewise.
8737 (__arm_vrshlq_m_n_u8): Likewise.
8738 (__arm_vqshlq_m_r_u8): Likewise.
8739 (__arm_vqrshlq_m_n_u8): Likewise.
8740 (__arm_vminavq_p_s8): Likewise.
8741 (__arm_vminaq_m_s8): Likewise.
8742 (__arm_vmaxavq_p_s8): Likewise.
8743 (__arm_vmaxaq_m_s8): Likewise.
8744 (__arm_vcmpneq_m_s8): Likewise.
8745 (__arm_vcmpneq_m_n_s8): Likewise.
8746 (__arm_vcmpltq_m_s8): Likewise.
8747 (__arm_vcmpltq_m_n_s8): Likewise.
8748 (__arm_vcmpleq_m_s8): Likewise.
8749 (__arm_vcmpleq_m_n_s8): Likewise.
8750 (__arm_vcmpgtq_m_s8): Likewise.
8751 (__arm_vcmpgtq_m_n_s8): Likewise.
8752 (__arm_vcmpgeq_m_s8): Likewise.
8753 (__arm_vcmpgeq_m_n_s8): Likewise.
8754 (__arm_vcmpeqq_m_s8): Likewise.
8755 (__arm_vcmpeqq_m_n_s8): Likewise.
8756 (__arm_vshlq_m_r_s8): Likewise.
8757 (__arm_vrshlq_m_n_s8): Likewise.
8758 (__arm_vrev64q_m_s8): Likewise.
8759 (__arm_vqshlq_m_r_s8): Likewise.
8760 (__arm_vqrshlq_m_n_s8): Likewise.
8761 (__arm_vqnegq_m_s8): Likewise.
8762 (__arm_vqabsq_m_s8): Likewise.
8763 (__arm_vnegq_m_s8): Likewise.
8764 (__arm_vmvnq_m_s8): Likewise.
8765 (__arm_vmlsdavxq_p_s8): Likewise.
8766 (__arm_vmlsdavq_p_s8): Likewise.
8767 (__arm_vmladavxq_p_s8): Likewise.
8768 (__arm_vmladavq_p_s8): Likewise.
8769 (__arm_vminvq_p_s8): Likewise.
8770 (__arm_vmaxvq_p_s8): Likewise.
8771 (__arm_vdupq_m_n_s8): Likewise.
8772 (__arm_vclzq_m_s8): Likewise.
8773 (__arm_vclsq_m_s8): Likewise.
8774 (__arm_vaddvaq_p_s8): Likewise.
8775 (__arm_vabsq_m_s8): Likewise.
8776 (__arm_vqrdmlsdhxq_s8): Likewise.
8777 (__arm_vqrdmlsdhq_s8): Likewise.
8778 (__arm_vqrdmlashq_n_s8): Likewise.
8779 (__arm_vqrdmlahq_n_s8): Likewise.
8780 (__arm_vqrdmladhxq_s8): Likewise.
8781 (__arm_vqrdmladhq_s8): Likewise.
8782 (__arm_vqdmlsdhxq_s8): Likewise.
8783 (__arm_vqdmlsdhq_s8): Likewise.
8784 (__arm_vqdmlahq_n_s8): Likewise.
8785 (__arm_vqdmladhxq_s8): Likewise.
8786 (__arm_vqdmladhq_s8): Likewise.
8787 (__arm_vmlsdavaxq_s8): Likewise.
8788 (__arm_vmlsdavaq_s8): Likewise.
8789 (__arm_vmlasq_n_s8): Likewise.
8790 (__arm_vmlaq_n_s8): Likewise.
8791 (__arm_vmladavaxq_s8): Likewise.
8792 (__arm_vmladavaq_s8): Likewise.
8793 (__arm_vsriq_n_s8): Likewise.
8794 (__arm_vsliq_n_s8): Likewise.
8795 (__arm_vpselq_u16): Likewise.
8796 (__arm_vpselq_s16): Likewise.
8797 (__arm_vrev64q_m_u16): Likewise.
8798 (__arm_vqrdmlashq_n_u16): Likewise.
8799 (__arm_vqrdmlahq_n_u16): Likewise.
8800 (__arm_vqdmlahq_n_u16): Likewise.
8801 (__arm_vmvnq_m_u16): Likewise.
8802 (__arm_vmlasq_n_u16): Likewise.
8803 (__arm_vmlaq_n_u16): Likewise.
8804 (__arm_vmladavq_p_u16): Likewise.
8805 (__arm_vmladavaq_u16): Likewise.
8806 (__arm_vminvq_p_u16): Likewise.
8807 (__arm_vmaxvq_p_u16): Likewise.
8808 (__arm_vdupq_m_n_u16): Likewise.
8809 (__arm_vcmpneq_m_u16): Likewise.
8810 (__arm_vcmpneq_m_n_u16): Likewise.
8811 (__arm_vcmphiq_m_u16): Likewise.
8812 (__arm_vcmphiq_m_n_u16): Likewise.
8813 (__arm_vcmpeqq_m_u16): Likewise.
8814 (__arm_vcmpeqq_m_n_u16): Likewise.
8815 (__arm_vcmpcsq_m_u16): Likewise.
8816 (__arm_vcmpcsq_m_n_u16): Likewise.
8817 (__arm_vclzq_m_u16): Likewise.
8818 (__arm_vaddvaq_p_u16): Likewise.
8819 (__arm_vsriq_n_u16): Likewise.
8820 (__arm_vsliq_n_u16): Likewise.
8821 (__arm_vshlq_m_r_u16): Likewise.
8822 (__arm_vrshlq_m_n_u16): Likewise.
8823 (__arm_vqshlq_m_r_u16): Likewise.
8824 (__arm_vqrshlq_m_n_u16): Likewise.
8825 (__arm_vminavq_p_s16): Likewise.
8826 (__arm_vminaq_m_s16): Likewise.
8827 (__arm_vmaxavq_p_s16): Likewise.
8828 (__arm_vmaxaq_m_s16): Likewise.
8829 (__arm_vcmpneq_m_s16): Likewise.
8830 (__arm_vcmpneq_m_n_s16): Likewise.
8831 (__arm_vcmpltq_m_s16): Likewise.
8832 (__arm_vcmpltq_m_n_s16): Likewise.
8833 (__arm_vcmpleq_m_s16): Likewise.
8834 (__arm_vcmpleq_m_n_s16): Likewise.
8835 (__arm_vcmpgtq_m_s16): Likewise.
8836 (__arm_vcmpgtq_m_n_s16): Likewise.
8837 (__arm_vcmpgeq_m_s16): Likewise.
8838 (__arm_vcmpgeq_m_n_s16): Likewise.
8839 (__arm_vcmpeqq_m_s16): Likewise.
8840 (__arm_vcmpeqq_m_n_s16): Likewise.
8841 (__arm_vshlq_m_r_s16): Likewise.
8842 (__arm_vrshlq_m_n_s16): Likewise.
8843 (__arm_vrev64q_m_s16): Likewise.
8844 (__arm_vqshlq_m_r_s16): Likewise.
8845 (__arm_vqrshlq_m_n_s16): Likewise.
8846 (__arm_vqnegq_m_s16): Likewise.
8847 (__arm_vqabsq_m_s16): Likewise.
8848 (__arm_vnegq_m_s16): Likewise.
8849 (__arm_vmvnq_m_s16): Likewise.
8850 (__arm_vmlsdavxq_p_s16): Likewise.
8851 (__arm_vmlsdavq_p_s16): Likewise.
8852 (__arm_vmladavxq_p_s16): Likewise.
8853 (__arm_vmladavq_p_s16): Likewise.
8854 (__arm_vminvq_p_s16): Likewise.
8855 (__arm_vmaxvq_p_s16): Likewise.
8856 (__arm_vdupq_m_n_s16): Likewise.
8857 (__arm_vclzq_m_s16): Likewise.
8858 (__arm_vclsq_m_s16): Likewise.
8859 (__arm_vaddvaq_p_s16): Likewise.
8860 (__arm_vabsq_m_s16): Likewise.
8861 (__arm_vqrdmlsdhxq_s16): Likewise.
8862 (__arm_vqrdmlsdhq_s16): Likewise.
8863 (__arm_vqrdmlashq_n_s16): Likewise.
8864 (__arm_vqrdmlahq_n_s16): Likewise.
8865 (__arm_vqrdmladhxq_s16): Likewise.
8866 (__arm_vqrdmladhq_s16): Likewise.
8867 (__arm_vqdmlsdhxq_s16): Likewise.
8868 (__arm_vqdmlsdhq_s16): Likewise.
8869 (__arm_vqdmlahq_n_s16): Likewise.
8870 (__arm_vqdmladhxq_s16): Likewise.
8871 (__arm_vqdmladhq_s16): Likewise.
8872 (__arm_vmlsdavaxq_s16): Likewise.
8873 (__arm_vmlsdavaq_s16): Likewise.
8874 (__arm_vmlasq_n_s16): Likewise.
8875 (__arm_vmlaq_n_s16): Likewise.
8876 (__arm_vmladavaxq_s16): Likewise.
8877 (__arm_vmladavaq_s16): Likewise.
8878 (__arm_vsriq_n_s16): Likewise.
8879 (__arm_vsliq_n_s16): Likewise.
8880 (__arm_vpselq_u32): Likewise.
8881 (__arm_vpselq_s32): Likewise.
8882 (__arm_vrev64q_m_u32): Likewise.
8883 (__arm_vqrdmlashq_n_u32): Likewise.
8884 (__arm_vqrdmlahq_n_u32): Likewise.
8885 (__arm_vqdmlahq_n_u32): Likewise.
8886 (__arm_vmvnq_m_u32): Likewise.
8887 (__arm_vmlasq_n_u32): Likewise.
8888 (__arm_vmlaq_n_u32): Likewise.
8889 (__arm_vmladavq_p_u32): Likewise.
8890 (__arm_vmladavaq_u32): Likewise.
8891 (__arm_vminvq_p_u32): Likewise.
8892 (__arm_vmaxvq_p_u32): Likewise.
8893 (__arm_vdupq_m_n_u32): Likewise.
8894 (__arm_vcmpneq_m_u32): Likewise.
8895 (__arm_vcmpneq_m_n_u32): Likewise.
8896 (__arm_vcmphiq_m_u32): Likewise.
8897 (__arm_vcmphiq_m_n_u32): Likewise.
8898 (__arm_vcmpeqq_m_u32): Likewise.
8899 (__arm_vcmpeqq_m_n_u32): Likewise.
8900 (__arm_vcmpcsq_m_u32): Likewise.
8901 (__arm_vcmpcsq_m_n_u32): Likewise.
8902 (__arm_vclzq_m_u32): Likewise.
8903 (__arm_vaddvaq_p_u32): Likewise.
8904 (__arm_vsriq_n_u32): Likewise.
8905 (__arm_vsliq_n_u32): Likewise.
8906 (__arm_vshlq_m_r_u32): Likewise.
8907 (__arm_vrshlq_m_n_u32): Likewise.
8908 (__arm_vqshlq_m_r_u32): Likewise.
8909 (__arm_vqrshlq_m_n_u32): Likewise.
8910 (__arm_vminavq_p_s32): Likewise.
8911 (__arm_vminaq_m_s32): Likewise.
8912 (__arm_vmaxavq_p_s32): Likewise.
8913 (__arm_vmaxaq_m_s32): Likewise.
8914 (__arm_vcmpneq_m_s32): Likewise.
8915 (__arm_vcmpneq_m_n_s32): Likewise.
8916 (__arm_vcmpltq_m_s32): Likewise.
8917 (__arm_vcmpltq_m_n_s32): Likewise.
8918 (__arm_vcmpleq_m_s32): Likewise.
8919 (__arm_vcmpleq_m_n_s32): Likewise.
8920 (__arm_vcmpgtq_m_s32): Likewise.
8921 (__arm_vcmpgtq_m_n_s32): Likewise.
8922 (__arm_vcmpgeq_m_s32): Likewise.
8923 (__arm_vcmpgeq_m_n_s32): Likewise.
8924 (__arm_vcmpeqq_m_s32): Likewise.
8925 (__arm_vcmpeqq_m_n_s32): Likewise.
8926 (__arm_vshlq_m_r_s32): Likewise.
8927 (__arm_vrshlq_m_n_s32): Likewise.
8928 (__arm_vrev64q_m_s32): Likewise.
8929 (__arm_vqshlq_m_r_s32): Likewise.
8930 (__arm_vqrshlq_m_n_s32): Likewise.
8931 (__arm_vqnegq_m_s32): Likewise.
8932 (__arm_vqabsq_m_s32): Likewise.
8933 (__arm_vnegq_m_s32): Likewise.
8934 (__arm_vmvnq_m_s32): Likewise.
8935 (__arm_vmlsdavxq_p_s32): Likewise.
8936 (__arm_vmlsdavq_p_s32): Likewise.
8937 (__arm_vmladavxq_p_s32): Likewise.
8938 (__arm_vmladavq_p_s32): Likewise.
8939 (__arm_vminvq_p_s32): Likewise.
8940 (__arm_vmaxvq_p_s32): Likewise.
8941 (__arm_vdupq_m_n_s32): Likewise.
8942 (__arm_vclzq_m_s32): Likewise.
8943 (__arm_vclsq_m_s32): Likewise.
8944 (__arm_vaddvaq_p_s32): Likewise.
8945 (__arm_vabsq_m_s32): Likewise.
8946 (__arm_vqrdmlsdhxq_s32): Likewise.
8947 (__arm_vqrdmlsdhq_s32): Likewise.
8948 (__arm_vqrdmlashq_n_s32): Likewise.
8949 (__arm_vqrdmlahq_n_s32): Likewise.
8950 (__arm_vqrdmladhxq_s32): Likewise.
8951 (__arm_vqrdmladhq_s32): Likewise.
8952 (__arm_vqdmlsdhxq_s32): Likewise.
8953 (__arm_vqdmlsdhq_s32): Likewise.
8954 (__arm_vqdmlahq_n_s32): Likewise.
8955 (__arm_vqdmladhxq_s32): Likewise.
8956 (__arm_vqdmladhq_s32): Likewise.
8957 (__arm_vmlsdavaxq_s32): Likewise.
8958 (__arm_vmlsdavaq_s32): Likewise.
8959 (__arm_vmlasq_n_s32): Likewise.
8960 (__arm_vmlaq_n_s32): Likewise.
8961 (__arm_vmladavaxq_s32): Likewise.
8962 (__arm_vmladavaq_s32): Likewise.
8963 (__arm_vsriq_n_s32): Likewise.
8964 (__arm_vsliq_n_s32): Likewise.
8965 (__arm_vpselq_u64): Likewise.
8966 (__arm_vpselq_s64): Likewise.
8967 (vcmpneq_m_n): Define polymorphic variant.
8968 (vcmpneq_m): Likewise.
8969 (vqrdmlsdhq): Likewise.
8970 (vqrdmlsdhxq): Likewise.
8971 (vqrshlq_m_n): Likewise.
8972 (vqshlq_m_r): Likewise.
8973 (vrev64q_m): Likewise.
8974 (vrshlq_m_n): Likewise.
8975 (vshlq_m_r): Likewise.
8976 (vsliq_n): Likewise.
8977 (vsriq_n): Likewise.
8978 (vqrdmlashq_n): Likewise.
8979 (vqrdmlahq): Likewise.
8980 (vqrdmladhxq): Likewise.
8981 (vqrdmladhq): Likewise.
8982 (vqnegq_m): Likewise.
8983 (vqdmlsdhxq): Likewise.
8984 (vabsq_m): Likewise.
8985 (vclsq_m): Likewise.
8986 (vclzq_m): Likewise.
8987 (vcmpgeq_m): Likewise.
8988 (vcmpgeq_m_n): Likewise.
8989 (vdupq_m_n): Likewise.
8990 (vmaxaq_m): Likewise.
8991 (vmlaq_n): Likewise.
8992 (vmlasq_n): Likewise.
8993 (vmvnq_m): Likewise.
8994 (vnegq_m): Likewise.
8996 (vqdmlahq_n): Likewise.
8997 (vqrdmlahq_n): Likewise.
8998 (vqdmlsdhq): Likewise.
8999 (vqdmladhq): Likewise.
9000 (vqabsq_m): Likewise.
9001 (vminaq_m): Likewise.
9002 (vrmlaldavhaq): Likewise.
9003 (vmlsdavxq_p): Likewise.
9004 (vmlsdavq_p): Likewise.
9005 (vmlsdavaxq): Likewise.
9006 (vmlsdavaq): Likewise.
9007 (vaddvaq_p): Likewise.
9008 (vcmpcsq_m_n): Likewise.
9009 (vcmpcsq_m): Likewise.
9010 (vcmpeqq_m_n): Likewise.
9011 (vcmpeqq_m): Likewise.
9012 (vmladavxq_p): Likewise.
9013 (vmladavq_p): Likewise.
9014 (vmladavaxq): Likewise.
9015 (vmladavaq): Likewise.
9016 (vminvq_p): Likewise.
9017 (vminavq_p): Likewise.
9018 (vmaxvq_p): Likewise.
9019 (vmaxavq_p): Likewise.
9020 (vcmpltq_m_n): Likewise.
9021 (vcmpltq_m): Likewise.
9022 (vcmpleq_m): Likewise.
9023 (vcmpleq_m_n): Likewise.
9024 (vcmphiq_m_n): Likewise.
9025 (vcmphiq_m): Likewise.
9026 (vcmpgtq_m_n): Likewise.
9027 (vcmpgtq_m): Likewise.
9028 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use
9030 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
9031 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
9032 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
9033 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
9034 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
9035 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
9036 * config/arm/constraints.md (Rc): Define constraint to check constant is
9037 in the range of 0 to 15.
9038 (Re): Define constraint to check constant is in the range of 0 to 31.
9039 * config/arm/mve.md (VADDVAQ_P): Define iterator.
9040 (VCLZQ_M): Likewise.
9041 (VCMPEQQ_M_N): Likewise.
9042 (VCMPEQQ_M): Likewise.
9043 (VCMPNEQ_M_N): Likewise.
9044 (VCMPNEQ_M): Likewise.
9045 (VDUPQ_M_N): Likewise.
9046 (VMAXVQ_P): Likewise.
9047 (VMINVQ_P): Likewise.
9048 (VMLADAVAQ): Likewise.
9049 (VMLADAVQ_P): Likewise.
9050 (VMLAQ_N): Likewise.
9051 (VMLASQ_N): Likewise.
9052 (VMVNQ_M): Likewise.
9054 (VQDMLAHQ_N): Likewise.
9055 (VQRDMLAHQ_N): Likewise.
9056 (VQRDMLASHQ_N): Likewise.
9057 (VQRSHLQ_M_N): Likewise.
9058 (VQSHLQ_M_R): Likewise.
9059 (VREV64Q_M): Likewise.
9060 (VRSHLQ_M_N): Likewise.
9061 (VSHLQ_M_R): Likewise.
9062 (VSLIQ_N): Likewise.
9063 (VSRIQ_N): Likewise.
9064 (mve_vabsq_m_s<mode>): Define RTL pattern.
9065 (mve_vaddvaq_p_<supf><mode>): Likewise.
9066 (mve_vclsq_m_s<mode>): Likewise.
9067 (mve_vclzq_m_<supf><mode>): Likewise.
9068 (mve_vcmpcsq_m_n_u<mode>): Likewise.
9069 (mve_vcmpcsq_m_u<mode>): Likewise.
9070 (mve_vcmpeqq_m_n_<supf><mode>): Likewise.
9071 (mve_vcmpeqq_m_<supf><mode>): Likewise.
9072 (mve_vcmpgeq_m_n_s<mode>): Likewise.
9073 (mve_vcmpgeq_m_s<mode>): Likewise.
9074 (mve_vcmpgtq_m_n_s<mode>): Likewise.
9075 (mve_vcmpgtq_m_s<mode>): Likewise.
9076 (mve_vcmphiq_m_n_u<mode>): Likewise.
9077 (mve_vcmphiq_m_u<mode>): Likewise.
9078 (mve_vcmpleq_m_n_s<mode>): Likewise.
9079 (mve_vcmpleq_m_s<mode>): Likewise.
9080 (mve_vcmpltq_m_n_s<mode>): Likewise.
9081 (mve_vcmpltq_m_s<mode>): Likewise.
9082 (mve_vcmpneq_m_n_<supf><mode>): Likewise.
9083 (mve_vcmpneq_m_<supf><mode>): Likewise.
9084 (mve_vdupq_m_n_<supf><mode>): Likewise.
9085 (mve_vmaxaq_m_s<mode>): Likewise.
9086 (mve_vmaxavq_p_s<mode>): Likewise.
9087 (mve_vmaxvq_p_<supf><mode>): Likewise.
9088 (mve_vminaq_m_s<mode>): Likewise.
9089 (mve_vminavq_p_s<mode>): Likewise.
9090 (mve_vminvq_p_<supf><mode>): Likewise.
9091 (mve_vmladavaq_<supf><mode>): Likewise.
9092 (mve_vmladavq_p_<supf><mode>): Likewise.
9093 (mve_vmladavxq_p_s<mode>): Likewise.
9094 (mve_vmlaq_n_<supf><mode>): Likewise.
9095 (mve_vmlasq_n_<supf><mode>): Likewise.
9096 (mve_vmlsdavq_p_s<mode>): Likewise.
9097 (mve_vmlsdavxq_p_s<mode>): Likewise.
9098 (mve_vmvnq_m_<supf><mode>): Likewise.
9099 (mve_vnegq_m_s<mode>): Likewise.
9100 (mve_vpselq_<supf><mode>): Likewise.
9101 (mve_vqabsq_m_s<mode>): Likewise.
9102 (mve_vqdmlahq_n_<supf><mode>): Likewise.
9103 (mve_vqnegq_m_s<mode>): Likewise.
9104 (mve_vqrdmladhq_s<mode>): Likewise.
9105 (mve_vqrdmladhxq_s<mode>): Likewise.
9106 (mve_vqrdmlahq_n_<supf><mode>): Likewise.
9107 (mve_vqrdmlashq_n_<supf><mode>): Likewise.
9108 (mve_vqrdmlsdhq_s<mode>): Likewise.
9109 (mve_vqrdmlsdhxq_s<mode>): Likewise.
9110 (mve_vqrshlq_m_n_<supf><mode>): Likewise.
9111 (mve_vqshlq_m_r_<supf><mode>): Likewise.
9112 (mve_vrev64q_m_<supf><mode>): Likewise.
9113 (mve_vrshlq_m_n_<supf><mode>): Likewise.
9114 (mve_vshlq_m_r_<supf><mode>): Likewise.
9115 (mve_vsliq_n_<supf><mode>): Likewise.
9116 (mve_vsriq_n_<supf><mode>): Likewise.
9117 (mve_vqdmlsdhxq_s<mode>): Likewise.
9118 (mve_vqdmlsdhq_s<mode>): Likewise.
9119 (mve_vqdmladhxq_s<mode>): Likewise.
9120 (mve_vqdmladhq_s<mode>): Likewise.
9121 (mve_vmlsdavaxq_s<mode>): Likewise.
9122 (mve_vmlsdavaq_s<mode>): Likewise.
9123 (mve_vmladavaxq_s<mode>): Likewise.
9124 * config/arm/predicates.md (mve_imm_15):Define predicate to check the
9125 matching constraint Rc.
9126 (mve_imm_31): Define predicate to check the matching constraint Re.
9128 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
9130 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
9131 (vec_cmp<mode>di_dup): Likewise.
9132 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
9134 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
9136 * config/gcn/gcn-valu.md (COND_MODE): Delete.
9137 (COND_INT_MODE): Delete.
9138 (cond_op): Add "mult".
9139 (cond_<expander><mode>): Use VEC_ALLREG_MODE.
9140 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
9142 2020-03-18 Richard Biener <rguenther@suse.de>
9145 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using
9146 partial int modes or not mode-precision integer types for
9149 2020-03-18 Jakub Jelinek <jakub@redhat.com>
9151 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue
9153 * config/arc/arc.c (frame_stack_add): Likewise.
9154 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term):
9156 * ipa-predicate.c (predicate::remap_after_inlining): Likewise.
9157 * tree-ssa-strlen.h (handle_printf_call): Likewise.
9158 * tree-ssa-strlen.c (is_strlen_related_p): Likewise.
9159 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise.
9161 2020-03-18 Duan bo <duanbo3@huawei.com>
9164 * config/aarch64/aarch64.md (ldr_got_tiny): Delete.
9165 (@ldr_got_tiny_<mode>): New pattern.
9166 (ldr_got_tiny_sidi): Likewise.
9167 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
9168 them to handle SYMBOL_TINY_GOT for ILP32.
9170 2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
9172 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
9173 call-preserved for SVE PCS functions.
9174 (aarch64_layout_frame): Cope with up to 12 predicate save slots.
9175 Optimize the case in which there are no following vector save slots.
9177 2020-03-18 Richard Biener <rguenther@suse.de>
9180 * fold-const.c (build_fold_addr_expr): Convert address to
9182 * asan.c (maybe_create_ssa_name): Strip useless type conversions.
9183 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1
9184 to build the ADDR_EXPR which we don't really want to simplify.
9185 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
9186 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise.
9187 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
9188 (simplify_builtin_call): Strip useless type conversions.
9189 * tree-ssa-strlen.c (new_strinfo): Likewise.
9191 2020-03-17 Alexey Neyman <stilor@att.net>
9194 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if
9195 the debug level is terse and the declaration is public. Do not
9197 (dwarf2out_decl): Same.
9198 (add_type_attribute): Return immediately if debug level is
9201 2020-03-17 Richard Sandiford <richard.sandiford@arm.com>
9203 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF.
9205 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9206 Mihail Ionescu <mihail.ionescu@arm.com>
9207 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9209 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
9210 Define qualifier for ternary operands.
9211 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
9212 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9213 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9214 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
9215 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
9216 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
9217 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9218 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
9219 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9220 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
9221 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
9222 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
9223 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
9224 * config/arm/arm_mve.h (vabavq_s8): Define macro.
9225 (vabavq_s16): Likewise.
9226 (vabavq_s32): Likewise.
9227 (vbicq_m_n_s16): Likewise.
9228 (vbicq_m_n_s32): Likewise.
9229 (vbicq_m_n_u16): Likewise.
9230 (vbicq_m_n_u32): Likewise.
9231 (vcmpeqq_m_f16): Likewise.
9232 (vcmpeqq_m_f32): Likewise.
9233 (vcvtaq_m_s16_f16): Likewise.
9234 (vcvtaq_m_u16_f16): Likewise.
9235 (vcvtaq_m_s32_f32): Likewise.
9236 (vcvtaq_m_u32_f32): Likewise.
9237 (vcvtq_m_f16_s16): Likewise.
9238 (vcvtq_m_f16_u16): Likewise.
9239 (vcvtq_m_f32_s32): Likewise.
9240 (vcvtq_m_f32_u32): Likewise.
9241 (vqrshrnbq_n_s16): Likewise.
9242 (vqrshrnbq_n_u16): Likewise.
9243 (vqrshrnbq_n_s32): Likewise.
9244 (vqrshrnbq_n_u32): Likewise.
9245 (vqrshrunbq_n_s16): Likewise.
9246 (vqrshrunbq_n_s32): Likewise.
9247 (vrmlaldavhaq_s32): Likewise.
9248 (vrmlaldavhaq_u32): Likewise.
9249 (vshlcq_s8): Likewise.
9250 (vshlcq_u8): Likewise.
9251 (vshlcq_s16): Likewise.
9252 (vshlcq_u16): Likewise.
9253 (vshlcq_s32): Likewise.
9254 (vshlcq_u32): Likewise.
9255 (vabavq_u8): Likewise.
9256 (vabavq_u16): Likewise.
9257 (vabavq_u32): Likewise.
9258 (__arm_vabavq_s8): Define intrinsic.
9259 (__arm_vabavq_s16): Likewise.
9260 (__arm_vabavq_s32): Likewise.
9261 (__arm_vabavq_u8): Likewise.
9262 (__arm_vabavq_u16): Likewise.
9263 (__arm_vabavq_u32): Likewise.
9264 (__arm_vbicq_m_n_s16): Likewise.
9265 (__arm_vbicq_m_n_s32): Likewise.
9266 (__arm_vbicq_m_n_u16): Likewise.
9267 (__arm_vbicq_m_n_u32): Likewise.
9268 (__arm_vqrshrnbq_n_s16): Likewise.
9269 (__arm_vqrshrnbq_n_u16): Likewise.
9270 (__arm_vqrshrnbq_n_s32): Likewise.
9271 (__arm_vqrshrnbq_n_u32): Likewise.
9272 (__arm_vqrshrunbq_n_s16): Likewise.
9273 (__arm_vqrshrunbq_n_s32): Likewise.
9274 (__arm_vrmlaldavhaq_s32): Likewise.
9275 (__arm_vrmlaldavhaq_u32): Likewise.
9276 (__arm_vshlcq_s8): Likewise.
9277 (__arm_vshlcq_u8): Likewise.
9278 (__arm_vshlcq_s16): Likewise.
9279 (__arm_vshlcq_u16): Likewise.
9280 (__arm_vshlcq_s32): Likewise.
9281 (__arm_vshlcq_u32): Likewise.
9282 (__arm_vcmpeqq_m_f16): Likewise.
9283 (__arm_vcmpeqq_m_f32): Likewise.
9284 (__arm_vcvtaq_m_s16_f16): Likewise.
9285 (__arm_vcvtaq_m_u16_f16): Likewise.
9286 (__arm_vcvtaq_m_s32_f32): Likewise.
9287 (__arm_vcvtaq_m_u32_f32): Likewise.
9288 (__arm_vcvtq_m_f16_s16): Likewise.
9289 (__arm_vcvtq_m_f16_u16): Likewise.
9290 (__arm_vcvtq_m_f32_s32): Likewise.
9291 (__arm_vcvtq_m_f32_u32): Likewise.
9292 (vcvtaq_m): Define polymorphic variant.
9293 (vcvtq_m): Likewise.
9296 (vbicq_m_n): Likewise.
9297 (vqrshrnbq_n): Likewise.
9298 (vqrshrunbq_n): Likewise.
9299 * config/arm/arm_mve_builtins.def
9300 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
9301 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
9302 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9303 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9304 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
9305 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
9306 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
9307 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9308 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
9309 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9310 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
9311 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
9312 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
9313 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
9314 * config/arm/mve.md (VBICQ_M_N): Define iterator.
9315 (VCVTAQ_M): Likewise.
9316 (VCVTQ_M_TO_F): Likewise.
9317 (VQRSHRNBQ_N): Likewise.
9320 (VRMLALDAVHAQ): Likewise.
9321 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
9322 (mve_vcmpeqq_m_f<mode>): Likewise.
9323 (mve_vcvtaq_m_<supf><mode>): Likewise.
9324 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
9325 (mve_vqrshrnbq_n_<supf><mode>): Likewise.
9326 (mve_vqrshrunbq_n_s<mode>): Likewise.
9327 (mve_vrmlaldavhaq_<supf>v4si): Likewise.
9328 (mve_vabavq_<supf><mode>): Likewise.
9329 (mve_vshlcq_<supf><mode>): Likewise.
9330 (mve_vshlcq_<supf><mode>): Likewise.
9331 (mve_vshlcq_vec_<supf><mode>): Define RTL expand.
9332 (mve_vshlcq_carry_<supf><mode>): Likewise.
9334 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9335 Mihail Ionescu <mihail.ionescu@arm.com>
9336 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9338 * config/arm/arm_mve.h (vqmovntq_u16): Define macro.
9339 (vqmovnbq_u16): Likewise.
9340 (vmulltq_poly_p8): Likewise.
9341 (vmullbq_poly_p8): Likewise.
9342 (vmovntq_u16): Likewise.
9343 (vmovnbq_u16): Likewise.
9344 (vmlaldavxq_u16): Likewise.
9345 (vmlaldavq_u16): Likewise.
9346 (vqmovuntq_s16): Likewise.
9347 (vqmovunbq_s16): Likewise.
9348 (vshlltq_n_u8): Likewise.
9349 (vshllbq_n_u8): Likewise.
9350 (vorrq_n_u16): Likewise.
9351 (vbicq_n_u16): Likewise.
9352 (vcmpneq_n_f16): Likewise.
9353 (vcmpneq_f16): Likewise.
9354 (vcmpltq_n_f16): Likewise.
9355 (vcmpltq_f16): Likewise.
9356 (vcmpleq_n_f16): Likewise.
9357 (vcmpleq_f16): Likewise.
9358 (vcmpgtq_n_f16): Likewise.
9359 (vcmpgtq_f16): Likewise.
9360 (vcmpgeq_n_f16): Likewise.
9361 (vcmpgeq_f16): Likewise.
9362 (vcmpeqq_n_f16): Likewise.
9363 (vcmpeqq_f16): Likewise.
9364 (vsubq_f16): Likewise.
9365 (vqmovntq_s16): Likewise.
9366 (vqmovnbq_s16): Likewise.
9367 (vqdmulltq_s16): Likewise.
9368 (vqdmulltq_n_s16): Likewise.
9369 (vqdmullbq_s16): Likewise.
9370 (vqdmullbq_n_s16): Likewise.
9371 (vorrq_f16): Likewise.
9372 (vornq_f16): Likewise.
9373 (vmulq_n_f16): Likewise.
9374 (vmulq_f16): Likewise.
9375 (vmovntq_s16): Likewise.
9376 (vmovnbq_s16): Likewise.
9377 (vmlsldavxq_s16): Likewise.
9378 (vmlsldavq_s16): Likewise.
9379 (vmlaldavxq_s16): Likewise.
9380 (vmlaldavq_s16): Likewise.
9381 (vminnmvq_f16): Likewise.
9382 (vminnmq_f16): Likewise.
9383 (vminnmavq_f16): Likewise.
9384 (vminnmaq_f16): Likewise.
9385 (vmaxnmvq_f16): Likewise.
9386 (vmaxnmq_f16): Likewise.
9387 (vmaxnmavq_f16): Likewise.
9388 (vmaxnmaq_f16): Likewise.
9389 (veorq_f16): Likewise.
9390 (vcmulq_rot90_f16): Likewise.
9391 (vcmulq_rot270_f16): Likewise.
9392 (vcmulq_rot180_f16): Likewise.
9393 (vcmulq_f16): Likewise.
9394 (vcaddq_rot90_f16): Likewise.
9395 (vcaddq_rot270_f16): Likewise.
9396 (vbicq_f16): Likewise.
9397 (vandq_f16): Likewise.
9398 (vaddq_n_f16): Likewise.
9399 (vabdq_f16): Likewise.
9400 (vshlltq_n_s8): Likewise.
9401 (vshllbq_n_s8): Likewise.
9402 (vorrq_n_s16): Likewise.
9403 (vbicq_n_s16): Likewise.
9404 (vqmovntq_u32): Likewise.
9405 (vqmovnbq_u32): Likewise.
9406 (vmulltq_poly_p16): Likewise.
9407 (vmullbq_poly_p16): Likewise.
9408 (vmovntq_u32): Likewise.
9409 (vmovnbq_u32): Likewise.
9410 (vmlaldavxq_u32): Likewise.
9411 (vmlaldavq_u32): Likewise.
9412 (vqmovuntq_s32): Likewise.
9413 (vqmovunbq_s32): Likewise.
9414 (vshlltq_n_u16): Likewise.
9415 (vshllbq_n_u16): Likewise.
9416 (vorrq_n_u32): Likewise.
9417 (vbicq_n_u32): Likewise.
9418 (vcmpneq_n_f32): Likewise.
9419 (vcmpneq_f32): Likewise.
9420 (vcmpltq_n_f32): Likewise.
9421 (vcmpltq_f32): Likewise.
9422 (vcmpleq_n_f32): Likewise.
9423 (vcmpleq_f32): Likewise.
9424 (vcmpgtq_n_f32): Likewise.
9425 (vcmpgtq_f32): Likewise.
9426 (vcmpgeq_n_f32): Likewise.
9427 (vcmpgeq_f32): Likewise.
9428 (vcmpeqq_n_f32): Likewise.
9429 (vcmpeqq_f32): Likewise.
9430 (vsubq_f32): Likewise.
9431 (vqmovntq_s32): Likewise.
9432 (vqmovnbq_s32): Likewise.
9433 (vqdmulltq_s32): Likewise.
9434 (vqdmulltq_n_s32): Likewise.
9435 (vqdmullbq_s32): Likewise.
9436 (vqdmullbq_n_s32): Likewise.
9437 (vorrq_f32): Likewise.
9438 (vornq_f32): Likewise.
9439 (vmulq_n_f32): Likewise.
9440 (vmulq_f32): Likewise.
9441 (vmovntq_s32): Likewise.
9442 (vmovnbq_s32): Likewise.
9443 (vmlsldavxq_s32): Likewise.
9444 (vmlsldavq_s32): Likewise.
9445 (vmlaldavxq_s32): Likewise.
9446 (vmlaldavq_s32): Likewise.
9447 (vminnmvq_f32): Likewise.
9448 (vminnmq_f32): Likewise.
9449 (vminnmavq_f32): Likewise.
9450 (vminnmaq_f32): Likewise.
9451 (vmaxnmvq_f32): Likewise.
9452 (vmaxnmq_f32): Likewise.
9453 (vmaxnmavq_f32): Likewise.
9454 (vmaxnmaq_f32): Likewise.
9455 (veorq_f32): Likewise.
9456 (vcmulq_rot90_f32): Likewise.
9457 (vcmulq_rot270_f32): Likewise.
9458 (vcmulq_rot180_f32): Likewise.
9459 (vcmulq_f32): Likewise.
9460 (vcaddq_rot90_f32): Likewise.
9461 (vcaddq_rot270_f32): Likewise.
9462 (vbicq_f32): Likewise.
9463 (vandq_f32): Likewise.
9464 (vaddq_n_f32): Likewise.
9465 (vabdq_f32): Likewise.
9466 (vshlltq_n_s16): Likewise.
9467 (vshllbq_n_s16): Likewise.
9468 (vorrq_n_s32): Likewise.
9469 (vbicq_n_s32): Likewise.
9470 (vrmlaldavhq_u32): Likewise.
9471 (vctp8q_m): Likewise.
9472 (vctp64q_m): Likewise.
9473 (vctp32q_m): Likewise.
9474 (vctp16q_m): Likewise.
9475 (vaddlvaq_u32): Likewise.
9476 (vrmlsldavhxq_s32): Likewise.
9477 (vrmlsldavhq_s32): Likewise.
9478 (vrmlaldavhxq_s32): Likewise.
9479 (vrmlaldavhq_s32): Likewise.
9480 (vcvttq_f16_f32): Likewise.
9481 (vcvtbq_f16_f32): Likewise.
9482 (vaddlvaq_s32): Likewise.
9483 (__arm_vqmovntq_u16): Define intrinsic.
9484 (__arm_vqmovnbq_u16): Likewise.
9485 (__arm_vmulltq_poly_p8): Likewise.
9486 (__arm_vmullbq_poly_p8): Likewise.
9487 (__arm_vmovntq_u16): Likewise.
9488 (__arm_vmovnbq_u16): Likewise.
9489 (__arm_vmlaldavxq_u16): Likewise.
9490 (__arm_vmlaldavq_u16): Likewise.
9491 (__arm_vqmovuntq_s16): Likewise.
9492 (__arm_vqmovunbq_s16): Likewise.
9493 (__arm_vshlltq_n_u8): Likewise.
9494 (__arm_vshllbq_n_u8): Likewise.
9495 (__arm_vorrq_n_u16): Likewise.
9496 (__arm_vbicq_n_u16): Likewise.
9497 (__arm_vcmpneq_n_f16): Likewise.
9498 (__arm_vcmpneq_f16): Likewise.
9499 (__arm_vcmpltq_n_f16): Likewise.
9500 (__arm_vcmpltq_f16): Likewise.
9501 (__arm_vcmpleq_n_f16): Likewise.
9502 (__arm_vcmpleq_f16): Likewise.
9503 (__arm_vcmpgtq_n_f16): Likewise.
9504 (__arm_vcmpgtq_f16): Likewise.
9505 (__arm_vcmpgeq_n_f16): Likewise.
9506 (__arm_vcmpgeq_f16): Likewise.
9507 (__arm_vcmpeqq_n_f16): Likewise.
9508 (__arm_vcmpeqq_f16): Likewise.
9509 (__arm_vsubq_f16): Likewise.
9510 (__arm_vqmovntq_s16): Likewise.
9511 (__arm_vqmovnbq_s16): Likewise.
9512 (__arm_vqdmulltq_s16): Likewise.
9513 (__arm_vqdmulltq_n_s16): Likewise.
9514 (__arm_vqdmullbq_s16): Likewise.
9515 (__arm_vqdmullbq_n_s16): Likewise.
9516 (__arm_vorrq_f16): Likewise.
9517 (__arm_vornq_f16): Likewise.
9518 (__arm_vmulq_n_f16): Likewise.
9519 (__arm_vmulq_f16): Likewise.
9520 (__arm_vmovntq_s16): Likewise.
9521 (__arm_vmovnbq_s16): Likewise.
9522 (__arm_vmlsldavxq_s16): Likewise.
9523 (__arm_vmlsldavq_s16): Likewise.
9524 (__arm_vmlaldavxq_s16): Likewise.
9525 (__arm_vmlaldavq_s16): Likewise.
9526 (__arm_vminnmvq_f16): Likewise.
9527 (__arm_vminnmq_f16): Likewise.
9528 (__arm_vminnmavq_f16): Likewise.
9529 (__arm_vminnmaq_f16): Likewise.
9530 (__arm_vmaxnmvq_f16): Likewise.
9531 (__arm_vmaxnmq_f16): Likewise.
9532 (__arm_vmaxnmavq_f16): Likewise.
9533 (__arm_vmaxnmaq_f16): Likewise.
9534 (__arm_veorq_f16): Likewise.
9535 (__arm_vcmulq_rot90_f16): Likewise.
9536 (__arm_vcmulq_rot270_f16): Likewise.
9537 (__arm_vcmulq_rot180_f16): Likewise.
9538 (__arm_vcmulq_f16): Likewise.
9539 (__arm_vcaddq_rot90_f16): Likewise.
9540 (__arm_vcaddq_rot270_f16): Likewise.
9541 (__arm_vbicq_f16): Likewise.
9542 (__arm_vandq_f16): Likewise.
9543 (__arm_vaddq_n_f16): Likewise.
9544 (__arm_vabdq_f16): Likewise.
9545 (__arm_vshlltq_n_s8): Likewise.
9546 (__arm_vshllbq_n_s8): Likewise.
9547 (__arm_vorrq_n_s16): Likewise.
9548 (__arm_vbicq_n_s16): Likewise.
9549 (__arm_vqmovntq_u32): Likewise.
9550 (__arm_vqmovnbq_u32): Likewise.
9551 (__arm_vmulltq_poly_p16): Likewise.
9552 (__arm_vmullbq_poly_p16): Likewise.
9553 (__arm_vmovntq_u32): Likewise.
9554 (__arm_vmovnbq_u32): Likewise.
9555 (__arm_vmlaldavxq_u32): Likewise.
9556 (__arm_vmlaldavq_u32): Likewise.
9557 (__arm_vqmovuntq_s32): Likewise.
9558 (__arm_vqmovunbq_s32): Likewise.
9559 (__arm_vshlltq_n_u16): Likewise.
9560 (__arm_vshllbq_n_u16): Likewise.
9561 (__arm_vorrq_n_u32): Likewise.
9562 (__arm_vbicq_n_u32): Likewise.
9563 (__arm_vcmpneq_n_f32): Likewise.
9564 (__arm_vcmpneq_f32): Likewise.
9565 (__arm_vcmpltq_n_f32): Likewise.
9566 (__arm_vcmpltq_f32): Likewise.
9567 (__arm_vcmpleq_n_f32): Likewise.
9568 (__arm_vcmpleq_f32): Likewise.
9569 (__arm_vcmpgtq_n_f32): Likewise.
9570 (__arm_vcmpgtq_f32): Likewise.
9571 (__arm_vcmpgeq_n_f32): Likewise.
9572 (__arm_vcmpgeq_f32): Likewise.
9573 (__arm_vcmpeqq_n_f32): Likewise.
9574 (__arm_vcmpeqq_f32): Likewise.
9575 (__arm_vsubq_f32): Likewise.
9576 (__arm_vqmovntq_s32): Likewise.
9577 (__arm_vqmovnbq_s32): Likewise.
9578 (__arm_vqdmulltq_s32): Likewise.
9579 (__arm_vqdmulltq_n_s32): Likewise.
9580 (__arm_vqdmullbq_s32): Likewise.
9581 (__arm_vqdmullbq_n_s32): Likewise.
9582 (__arm_vorrq_f32): Likewise.
9583 (__arm_vornq_f32): Likewise.
9584 (__arm_vmulq_n_f32): Likewise.
9585 (__arm_vmulq_f32): Likewise.
9586 (__arm_vmovntq_s32): Likewise.
9587 (__arm_vmovnbq_s32): Likewise.
9588 (__arm_vmlsldavxq_s32): Likewise.
9589 (__arm_vmlsldavq_s32): Likewise.
9590 (__arm_vmlaldavxq_s32): Likewise.
9591 (__arm_vmlaldavq_s32): Likewise.
9592 (__arm_vminnmvq_f32): Likewise.
9593 (__arm_vminnmq_f32): Likewise.
9594 (__arm_vminnmavq_f32): Likewise.
9595 (__arm_vminnmaq_f32): Likewise.
9596 (__arm_vmaxnmvq_f32): Likewise.
9597 (__arm_vmaxnmq_f32): Likewise.
9598 (__arm_vmaxnmavq_f32): Likewise.
9599 (__arm_vmaxnmaq_f32): Likewise.
9600 (__arm_veorq_f32): Likewise.
9601 (__arm_vcmulq_rot90_f32): Likewise.
9602 (__arm_vcmulq_rot270_f32): Likewise.
9603 (__arm_vcmulq_rot180_f32): Likewise.
9604 (__arm_vcmulq_f32): Likewise.
9605 (__arm_vcaddq_rot90_f32): Likewise.
9606 (__arm_vcaddq_rot270_f32): Likewise.
9607 (__arm_vbicq_f32): Likewise.
9608 (__arm_vandq_f32): Likewise.
9609 (__arm_vaddq_n_f32): Likewise.
9610 (__arm_vabdq_f32): Likewise.
9611 (__arm_vshlltq_n_s16): Likewise.
9612 (__arm_vshllbq_n_s16): Likewise.
9613 (__arm_vorrq_n_s32): Likewise.
9614 (__arm_vbicq_n_s32): Likewise.
9615 (__arm_vrmlaldavhq_u32): Likewise.
9616 (__arm_vctp8q_m): Likewise.
9617 (__arm_vctp64q_m): Likewise.
9618 (__arm_vctp32q_m): Likewise.
9619 (__arm_vctp16q_m): Likewise.
9620 (__arm_vaddlvaq_u32): Likewise.
9621 (__arm_vrmlsldavhxq_s32): Likewise.
9622 (__arm_vrmlsldavhq_s32): Likewise.
9623 (__arm_vrmlaldavhxq_s32): Likewise.
9624 (__arm_vrmlaldavhq_s32): Likewise.
9625 (__arm_vcvttq_f16_f32): Likewise.
9626 (__arm_vcvtbq_f16_f32): Likewise.
9627 (__arm_vaddlvaq_s32): Likewise.
9628 (vst4q): Define polymorphic variant.
9635 (vrev64q): Likewise.
9637 (vdupq_n): Likewise.
9639 (vrev32q): Likewise.
9640 (vcvtbq_f32): Likewise.
9641 (vcvttq_f32): Likewise.
9643 (vsubq_n): Likewise.
9644 (vbrsrq_n): Likewise.
9645 (vcvtq_n): Likewise.
9649 (vaddq_n): Likewise.
9653 (vmulq_n): Likewise.
9655 (vcaddq_rot270): Likewise.
9656 (vcmpeqq_n): Likewise.
9657 (vcmpeqq): Likewise.
9658 (vcaddq_rot90): Likewise.
9659 (vcmpgeq_n): Likewise.
9660 (vcmpgeq): Likewise.
9661 (vcmpgtq_n): Likewise.
9662 (vcmpgtq): Likewise.
9663 (vcmpgtq): Likewise.
9664 (vcmpleq_n): Likewise.
9665 (vcmpleq_n): Likewise.
9666 (vcmpleq): Likewise.
9667 (vcmpleq): Likewise.
9668 (vcmpltq_n): Likewise.
9669 (vcmpltq_n): Likewise.
9670 (vcmpltq): Likewise.
9671 (vcmpltq): Likewise.
9672 (vcmpneq_n): Likewise.
9673 (vcmpneq_n): Likewise.
9674 (vcmpneq): Likewise.
9675 (vcmpneq): Likewise.
9678 (vcmulq_rot180): Likewise.
9679 (vcmulq_rot180): Likewise.
9680 (vcmulq_rot270): Likewise.
9681 (vcmulq_rot270): Likewise.
9682 (vcmulq_rot90): Likewise.
9683 (vcmulq_rot90): Likewise.
9686 (vmaxnmaq): Likewise.
9687 (vmaxnmaq): Likewise.
9688 (vmaxnmavq): Likewise.
9689 (vmaxnmavq): Likewise.
9690 (vmaxnmq): Likewise.
9691 (vmaxnmq): Likewise.
9692 (vmaxnmvq): Likewise.
9693 (vmaxnmvq): Likewise.
9694 (vminnmaq): Likewise.
9695 (vminnmaq): Likewise.
9696 (vminnmavq): Likewise.
9697 (vminnmavq): Likewise.
9698 (vminnmq): Likewise.
9699 (vminnmq): Likewise.
9700 (vminnmvq): Likewise.
9701 (vminnmvq): Likewise.
9702 (vbicq_n): Likewise.
9703 (vqmovntq): Likewise.
9704 (vqmovntq): Likewise.
9705 (vqmovnbq): Likewise.
9706 (vqmovnbq): Likewise.
9707 (vmulltq_poly): Likewise.
9708 (vmulltq_poly): Likewise.
9709 (vmullbq_poly): Likewise.
9710 (vmullbq_poly): Likewise.
9711 (vmovntq): Likewise.
9712 (vmovntq): Likewise.
9713 (vmovnbq): Likewise.
9714 (vmovnbq): Likewise.
9715 (vmlaldavxq): Likewise.
9716 (vmlaldavxq): Likewise.
9717 (vqmovuntq): Likewise.
9718 (vqmovuntq): Likewise.
9719 (vshlltq_n): Likewise.
9720 (vshlltq_n): Likewise.
9721 (vshllbq_n): Likewise.
9722 (vshllbq_n): Likewise.
9723 (vorrq_n): Likewise.
9724 (vorrq_n): Likewise.
9725 (vmlaldavq): Likewise.
9726 (vmlaldavq): Likewise.
9727 (vqmovunbq): Likewise.
9728 (vqmovunbq): Likewise.
9729 (vqdmulltq_n): Likewise.
9730 (vqdmulltq_n): Likewise.
9731 (vqdmulltq): Likewise.
9732 (vqdmulltq): Likewise.
9733 (vqdmullbq_n): Likewise.
9734 (vqdmullbq_n): Likewise.
9735 (vqdmullbq): Likewise.
9736 (vqdmullbq): Likewise.
9737 (vaddlvaq): Likewise.
9738 (vaddlvaq): Likewise.
9739 (vrmlaldavhq): Likewise.
9740 (vrmlaldavhq): Likewise.
9741 (vrmlaldavhxq): Likewise.
9742 (vrmlaldavhxq): Likewise.
9743 (vrmlsldavhq): Likewise.
9744 (vrmlsldavhq): Likewise.
9745 (vrmlsldavhxq): Likewise.
9746 (vrmlsldavhxq): Likewise.
9747 (vmlsldavxq): Likewise.
9748 (vmlsldavxq): Likewise.
9749 (vmlsldavq): Likewise.
9750 (vmlsldavq): Likewise.
9751 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
9752 (BINOP_NONE_NONE_NONE): Likewise.
9753 (BINOP_UNONE_NONE_NONE): Likewise.
9754 (BINOP_UNONE_UNONE_IMM): Likewise.
9755 (BINOP_UNONE_UNONE_NONE): Likewise.
9756 (BINOP_UNONE_UNONE_UNONE): Likewise.
9757 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
9758 (mve_vaddlvaq_<supf>v4si): Likewise.
9759 (mve_vaddq_n_f<mode>): Likewise.
9760 (mve_vandq_f<mode>): Likewise.
9761 (mve_vbicq_f<mode>): Likewise.
9762 (mve_vbicq_n_<supf><mode>): Likewise.
9763 (mve_vcaddq_rot270_f<mode>): Likewise.
9764 (mve_vcaddq_rot90_f<mode>): Likewise.
9765 (mve_vcmpeqq_f<mode>): Likewise.
9766 (mve_vcmpeqq_n_f<mode>): Likewise.
9767 (mve_vcmpgeq_f<mode>): Likewise.
9768 (mve_vcmpgeq_n_f<mode>): Likewise.
9769 (mve_vcmpgtq_f<mode>): Likewise.
9770 (mve_vcmpgtq_n_f<mode>): Likewise.
9771 (mve_vcmpleq_f<mode>): Likewise.
9772 (mve_vcmpleq_n_f<mode>): Likewise.
9773 (mve_vcmpltq_f<mode>): Likewise.
9774 (mve_vcmpltq_n_f<mode>): Likewise.
9775 (mve_vcmpneq_f<mode>): Likewise.
9776 (mve_vcmpneq_n_f<mode>): Likewise.
9777 (mve_vcmulq_f<mode>): Likewise.
9778 (mve_vcmulq_rot180_f<mode>): Likewise.
9779 (mve_vcmulq_rot270_f<mode>): Likewise.
9780 (mve_vcmulq_rot90_f<mode>): Likewise.
9781 (mve_vctp<mode1>q_mhi): Likewise.
9782 (mve_vcvtbq_f16_f32v8hf): Likewise.
9783 (mve_vcvttq_f16_f32v8hf): Likewise.
9784 (mve_veorq_f<mode>): Likewise.
9785 (mve_vmaxnmaq_f<mode>): Likewise.
9786 (mve_vmaxnmavq_f<mode>): Likewise.
9787 (mve_vmaxnmq_f<mode>): Likewise.
9788 (mve_vmaxnmvq_f<mode>): Likewise.
9789 (mve_vminnmaq_f<mode>): Likewise.
9790 (mve_vminnmavq_f<mode>): Likewise.
9791 (mve_vminnmq_f<mode>): Likewise.
9792 (mve_vminnmvq_f<mode>): Likewise.
9793 (mve_vmlaldavq_<supf><mode>): Likewise.
9794 (mve_vmlaldavxq_<supf><mode>): Likewise.
9795 (mve_vmlsldavq_s<mode>): Likewise.
9796 (mve_vmlsldavxq_s<mode>): Likewise.
9797 (mve_vmovnbq_<supf><mode>): Likewise.
9798 (mve_vmovntq_<supf><mode>): Likewise.
9799 (mve_vmulq_f<mode>): Likewise.
9800 (mve_vmulq_n_f<mode>): Likewise.
9801 (mve_vornq_f<mode>): Likewise.
9802 (mve_vorrq_f<mode>): Likewise.
9803 (mve_vorrq_n_<supf><mode>): Likewise.
9804 (mve_vqdmullbq_n_s<mode>): Likewise.
9805 (mve_vqdmullbq_s<mode>): Likewise.
9806 (mve_vqdmulltq_n_s<mode>): Likewise.
9807 (mve_vqdmulltq_s<mode>): Likewise.
9808 (mve_vqmovnbq_<supf><mode>): Likewise.
9809 (mve_vqmovntq_<supf><mode>): Likewise.
9810 (mve_vqmovunbq_s<mode>): Likewise.
9811 (mve_vqmovuntq_s<mode>): Likewise.
9812 (mve_vrmlaldavhxq_sv4si): Likewise.
9813 (mve_vrmlsldavhq_sv4si): Likewise.
9814 (mve_vrmlsldavhxq_sv4si): Likewise.
9815 (mve_vshllbq_n_<supf><mode>): Likewise.
9816 (mve_vshlltq_n_<supf><mode>): Likewise.
9817 (mve_vsubq_f<mode>): Likewise.
9818 (mve_vmulltq_poly_p<mode>): Likewise.
9819 (mve_vmullbq_poly_p<mode>): Likewise.
9820 (mve_vrmlaldavhq_<supf>v4si): Likewise.
9822 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9823 Mihail Ionescu <mihail.ionescu@arm.com>
9824 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9826 * config/arm/arm_mve.h (vsubq_u8): Define macro.
9827 (vsubq_n_u8): Likewise.
9828 (vrmulhq_u8): Likewise.
9829 (vrhaddq_u8): Likewise.
9830 (vqsubq_u8): Likewise.
9831 (vqsubq_n_u8): Likewise.
9832 (vqaddq_u8): Likewise.
9833 (vqaddq_n_u8): Likewise.
9834 (vorrq_u8): Likewise.
9835 (vornq_u8): Likewise.
9836 (vmulq_u8): Likewise.
9837 (vmulq_n_u8): Likewise.
9838 (vmulltq_int_u8): Likewise.
9839 (vmullbq_int_u8): Likewise.
9840 (vmulhq_u8): Likewise.
9841 (vmladavq_u8): Likewise.
9842 (vminvq_u8): Likewise.
9843 (vminq_u8): Likewise.
9844 (vmaxvq_u8): Likewise.
9845 (vmaxq_u8): Likewise.
9846 (vhsubq_u8): Likewise.
9847 (vhsubq_n_u8): Likewise.
9848 (vhaddq_u8): Likewise.
9849 (vhaddq_n_u8): Likewise.
9850 (veorq_u8): Likewise.
9851 (vcmpneq_n_u8): Likewise.
9852 (vcmphiq_u8): Likewise.
9853 (vcmphiq_n_u8): Likewise.
9854 (vcmpeqq_u8): Likewise.
9855 (vcmpeqq_n_u8): Likewise.
9856 (vcmpcsq_u8): Likewise.
9857 (vcmpcsq_n_u8): Likewise.
9858 (vcaddq_rot90_u8): Likewise.
9859 (vcaddq_rot270_u8): Likewise.
9860 (vbicq_u8): Likewise.
9861 (vandq_u8): Likewise.
9862 (vaddvq_p_u8): Likewise.
9863 (vaddvaq_u8): Likewise.
9864 (vaddq_n_u8): Likewise.
9865 (vabdq_u8): Likewise.
9866 (vshlq_r_u8): Likewise.
9867 (vrshlq_u8): Likewise.
9868 (vrshlq_n_u8): Likewise.
9869 (vqshlq_u8): Likewise.
9870 (vqshlq_r_u8): Likewise.
9871 (vqrshlq_u8): Likewise.
9872 (vqrshlq_n_u8): Likewise.
9873 (vminavq_s8): Likewise.
9874 (vminaq_s8): Likewise.
9875 (vmaxavq_s8): Likewise.
9876 (vmaxaq_s8): Likewise.
9877 (vbrsrq_n_u8): Likewise.
9878 (vshlq_n_u8): Likewise.
9879 (vrshrq_n_u8): Likewise.
9880 (vqshlq_n_u8): Likewise.
9881 (vcmpneq_n_s8): Likewise.
9882 (vcmpltq_s8): Likewise.
9883 (vcmpltq_n_s8): Likewise.
9884 (vcmpleq_s8): Likewise.
9885 (vcmpleq_n_s8): Likewise.
9886 (vcmpgtq_s8): Likewise.
9887 (vcmpgtq_n_s8): Likewise.
9888 (vcmpgeq_s8): Likewise.
9889 (vcmpgeq_n_s8): Likewise.
9890 (vcmpeqq_s8): Likewise.
9891 (vcmpeqq_n_s8): Likewise.
9892 (vqshluq_n_s8): Likewise.
9893 (vaddvq_p_s8): Likewise.
9894 (vsubq_s8): Likewise.
9895 (vsubq_n_s8): Likewise.
9896 (vshlq_r_s8): Likewise.
9897 (vrshlq_s8): Likewise.
9898 (vrshlq_n_s8): Likewise.
9899 (vrmulhq_s8): Likewise.
9900 (vrhaddq_s8): Likewise.
9901 (vqsubq_s8): Likewise.
9902 (vqsubq_n_s8): Likewise.
9903 (vqshlq_s8): Likewise.
9904 (vqshlq_r_s8): Likewise.
9905 (vqrshlq_s8): Likewise.
9906 (vqrshlq_n_s8): Likewise.
9907 (vqrdmulhq_s8): Likewise.
9908 (vqrdmulhq_n_s8): Likewise.
9909 (vqdmulhq_s8): Likewise.
9910 (vqdmulhq_n_s8): Likewise.
9911 (vqaddq_s8): Likewise.
9912 (vqaddq_n_s8): Likewise.
9913 (vorrq_s8): Likewise.
9914 (vornq_s8): Likewise.
9915 (vmulq_s8): Likewise.
9916 (vmulq_n_s8): Likewise.
9917 (vmulltq_int_s8): Likewise.
9918 (vmullbq_int_s8): Likewise.
9919 (vmulhq_s8): Likewise.
9920 (vmlsdavxq_s8): Likewise.
9921 (vmlsdavq_s8): Likewise.
9922 (vmladavxq_s8): Likewise.
9923 (vmladavq_s8): Likewise.
9924 (vminvq_s8): Likewise.
9925 (vminq_s8): Likewise.
9926 (vmaxvq_s8): Likewise.
9927 (vmaxq_s8): Likewise.
9928 (vhsubq_s8): Likewise.
9929 (vhsubq_n_s8): Likewise.
9930 (vhcaddq_rot90_s8): Likewise.
9931 (vhcaddq_rot270_s8): Likewise.
9932 (vhaddq_s8): Likewise.
9933 (vhaddq_n_s8): Likewise.
9934 (veorq_s8): Likewise.
9935 (vcaddq_rot90_s8): Likewise.
9936 (vcaddq_rot270_s8): Likewise.
9937 (vbrsrq_n_s8): Likewise.
9938 (vbicq_s8): Likewise.
9939 (vandq_s8): Likewise.
9940 (vaddvaq_s8): Likewise.
9941 (vaddq_n_s8): Likewise.
9942 (vabdq_s8): Likewise.
9943 (vshlq_n_s8): Likewise.
9944 (vrshrq_n_s8): Likewise.
9945 (vqshlq_n_s8): Likewise.
9946 (vsubq_u16): Likewise.
9947 (vsubq_n_u16): Likewise.
9948 (vrmulhq_u16): Likewise.
9949 (vrhaddq_u16): Likewise.
9950 (vqsubq_u16): Likewise.
9951 (vqsubq_n_u16): Likewise.
9952 (vqaddq_u16): Likewise.
9953 (vqaddq_n_u16): Likewise.
9954 (vorrq_u16): Likewise.
9955 (vornq_u16): Likewise.
9956 (vmulq_u16): Likewise.
9957 (vmulq_n_u16): Likewise.
9958 (vmulltq_int_u16): Likewise.
9959 (vmullbq_int_u16): Likewise.
9960 (vmulhq_u16): Likewise.
9961 (vmladavq_u16): Likewise.
9962 (vminvq_u16): Likewise.
9963 (vminq_u16): Likewise.
9964 (vmaxvq_u16): Likewise.
9965 (vmaxq_u16): Likewise.
9966 (vhsubq_u16): Likewise.
9967 (vhsubq_n_u16): Likewise.
9968 (vhaddq_u16): Likewise.
9969 (vhaddq_n_u16): Likewise.
9970 (veorq_u16): Likewise.
9971 (vcmpneq_n_u16): Likewise.
9972 (vcmphiq_u16): Likewise.
9973 (vcmphiq_n_u16): Likewise.
9974 (vcmpeqq_u16): Likewise.
9975 (vcmpeqq_n_u16): Likewise.
9976 (vcmpcsq_u16): Likewise.
9977 (vcmpcsq_n_u16): Likewise.
9978 (vcaddq_rot90_u16): Likewise.
9979 (vcaddq_rot270_u16): Likewise.
9980 (vbicq_u16): Likewise.
9981 (vandq_u16): Likewise.
9982 (vaddvq_p_u16): Likewise.
9983 (vaddvaq_u16): Likewise.
9984 (vaddq_n_u16): Likewise.
9985 (vabdq_u16): Likewise.
9986 (vshlq_r_u16): Likewise.
9987 (vrshlq_u16): Likewise.
9988 (vrshlq_n_u16): Likewise.
9989 (vqshlq_u16): Likewise.
9990 (vqshlq_r_u16): Likewise.
9991 (vqrshlq_u16): Likewise.
9992 (vqrshlq_n_u16): Likewise.
9993 (vminavq_s16): Likewise.
9994 (vminaq_s16): Likewise.
9995 (vmaxavq_s16): Likewise.
9996 (vmaxaq_s16): Likewise.
9997 (vbrsrq_n_u16): Likewise.
9998 (vshlq_n_u16): Likewise.
9999 (vrshrq_n_u16): Likewise.
10000 (vqshlq_n_u16): Likewise.
10001 (vcmpneq_n_s16): Likewise.
10002 (vcmpltq_s16): Likewise.
10003 (vcmpltq_n_s16): Likewise.
10004 (vcmpleq_s16): Likewise.
10005 (vcmpleq_n_s16): Likewise.
10006 (vcmpgtq_s16): Likewise.
10007 (vcmpgtq_n_s16): Likewise.
10008 (vcmpgeq_s16): Likewise.
10009 (vcmpgeq_n_s16): Likewise.
10010 (vcmpeqq_s16): Likewise.
10011 (vcmpeqq_n_s16): Likewise.
10012 (vqshluq_n_s16): Likewise.
10013 (vaddvq_p_s16): Likewise.
10014 (vsubq_s16): Likewise.
10015 (vsubq_n_s16): Likewise.
10016 (vshlq_r_s16): Likewise.
10017 (vrshlq_s16): Likewise.
10018 (vrshlq_n_s16): Likewise.
10019 (vrmulhq_s16): Likewise.
10020 (vrhaddq_s16): Likewise.
10021 (vqsubq_s16): Likewise.
10022 (vqsubq_n_s16): Likewise.
10023 (vqshlq_s16): Likewise.
10024 (vqshlq_r_s16): Likewise.
10025 (vqrshlq_s16): Likewise.
10026 (vqrshlq_n_s16): Likewise.
10027 (vqrdmulhq_s16): Likewise.
10028 (vqrdmulhq_n_s16): Likewise.
10029 (vqdmulhq_s16): Likewise.
10030 (vqdmulhq_n_s16): Likewise.
10031 (vqaddq_s16): Likewise.
10032 (vqaddq_n_s16): Likewise.
10033 (vorrq_s16): Likewise.
10034 (vornq_s16): Likewise.
10035 (vmulq_s16): Likewise.
10036 (vmulq_n_s16): Likewise.
10037 (vmulltq_int_s16): Likewise.
10038 (vmullbq_int_s16): Likewise.
10039 (vmulhq_s16): Likewise.
10040 (vmlsdavxq_s16): Likewise.
10041 (vmlsdavq_s16): Likewise.
10042 (vmladavxq_s16): Likewise.
10043 (vmladavq_s16): Likewise.
10044 (vminvq_s16): Likewise.
10045 (vminq_s16): Likewise.
10046 (vmaxvq_s16): Likewise.
10047 (vmaxq_s16): Likewise.
10048 (vhsubq_s16): Likewise.
10049 (vhsubq_n_s16): Likewise.
10050 (vhcaddq_rot90_s16): Likewise.
10051 (vhcaddq_rot270_s16): Likewise.
10052 (vhaddq_s16): Likewise.
10053 (vhaddq_n_s16): Likewise.
10054 (veorq_s16): Likewise.
10055 (vcaddq_rot90_s16): Likewise.
10056 (vcaddq_rot270_s16): Likewise.
10057 (vbrsrq_n_s16): Likewise.
10058 (vbicq_s16): Likewise.
10059 (vandq_s16): Likewise.
10060 (vaddvaq_s16): Likewise.
10061 (vaddq_n_s16): Likewise.
10062 (vabdq_s16): Likewise.
10063 (vshlq_n_s16): Likewise.
10064 (vrshrq_n_s16): Likewise.
10065 (vqshlq_n_s16): Likewise.
10066 (vsubq_u32): Likewise.
10067 (vsubq_n_u32): Likewise.
10068 (vrmulhq_u32): Likewise.
10069 (vrhaddq_u32): Likewise.
10070 (vqsubq_u32): Likewise.
10071 (vqsubq_n_u32): Likewise.
10072 (vqaddq_u32): Likewise.
10073 (vqaddq_n_u32): Likewise.
10074 (vorrq_u32): Likewise.
10075 (vornq_u32): Likewise.
10076 (vmulq_u32): Likewise.
10077 (vmulq_n_u32): Likewise.
10078 (vmulltq_int_u32): Likewise.
10079 (vmullbq_int_u32): Likewise.
10080 (vmulhq_u32): Likewise.
10081 (vmladavq_u32): Likewise.
10082 (vminvq_u32): Likewise.
10083 (vminq_u32): Likewise.
10084 (vmaxvq_u32): Likewise.
10085 (vmaxq_u32): Likewise.
10086 (vhsubq_u32): Likewise.
10087 (vhsubq_n_u32): Likewise.
10088 (vhaddq_u32): Likewise.
10089 (vhaddq_n_u32): Likewise.
10090 (veorq_u32): Likewise.
10091 (vcmpneq_n_u32): Likewise.
10092 (vcmphiq_u32): Likewise.
10093 (vcmphiq_n_u32): Likewise.
10094 (vcmpeqq_u32): Likewise.
10095 (vcmpeqq_n_u32): Likewise.
10096 (vcmpcsq_u32): Likewise.
10097 (vcmpcsq_n_u32): Likewise.
10098 (vcaddq_rot90_u32): Likewise.
10099 (vcaddq_rot270_u32): Likewise.
10100 (vbicq_u32): Likewise.
10101 (vandq_u32): Likewise.
10102 (vaddvq_p_u32): Likewise.
10103 (vaddvaq_u32): Likewise.
10104 (vaddq_n_u32): Likewise.
10105 (vabdq_u32): Likewise.
10106 (vshlq_r_u32): Likewise.
10107 (vrshlq_u32): Likewise.
10108 (vrshlq_n_u32): Likewise.
10109 (vqshlq_u32): Likewise.
10110 (vqshlq_r_u32): Likewise.
10111 (vqrshlq_u32): Likewise.
10112 (vqrshlq_n_u32): Likewise.
10113 (vminavq_s32): Likewise.
10114 (vminaq_s32): Likewise.
10115 (vmaxavq_s32): Likewise.
10116 (vmaxaq_s32): Likewise.
10117 (vbrsrq_n_u32): Likewise.
10118 (vshlq_n_u32): Likewise.
10119 (vrshrq_n_u32): Likewise.
10120 (vqshlq_n_u32): Likewise.
10121 (vcmpneq_n_s32): Likewise.
10122 (vcmpltq_s32): Likewise.
10123 (vcmpltq_n_s32): Likewise.
10124 (vcmpleq_s32): Likewise.
10125 (vcmpleq_n_s32): Likewise.
10126 (vcmpgtq_s32): Likewise.
10127 (vcmpgtq_n_s32): Likewise.
10128 (vcmpgeq_s32): Likewise.
10129 (vcmpgeq_n_s32): Likewise.
10130 (vcmpeqq_s32): Likewise.
10131 (vcmpeqq_n_s32): Likewise.
10132 (vqshluq_n_s32): Likewise.
10133 (vaddvq_p_s32): Likewise.
10134 (vsubq_s32): Likewise.
10135 (vsubq_n_s32): Likewise.
10136 (vshlq_r_s32): Likewise.
10137 (vrshlq_s32): Likewise.
10138 (vrshlq_n_s32): Likewise.
10139 (vrmulhq_s32): Likewise.
10140 (vrhaddq_s32): Likewise.
10141 (vqsubq_s32): Likewise.
10142 (vqsubq_n_s32): Likewise.
10143 (vqshlq_s32): Likewise.
10144 (vqshlq_r_s32): Likewise.
10145 (vqrshlq_s32): Likewise.
10146 (vqrshlq_n_s32): Likewise.
10147 (vqrdmulhq_s32): Likewise.
10148 (vqrdmulhq_n_s32): Likewise.
10149 (vqdmulhq_s32): Likewise.
10150 (vqdmulhq_n_s32): Likewise.
10151 (vqaddq_s32): Likewise.
10152 (vqaddq_n_s32): Likewise.
10153 (vorrq_s32): Likewise.
10154 (vornq_s32): Likewise.
10155 (vmulq_s32): Likewise.
10156 (vmulq_n_s32): Likewise.
10157 (vmulltq_int_s32): Likewise.
10158 (vmullbq_int_s32): Likewise.
10159 (vmulhq_s32): Likewise.
10160 (vmlsdavxq_s32): Likewise.
10161 (vmlsdavq_s32): Likewise.
10162 (vmladavxq_s32): Likewise.
10163 (vmladavq_s32): Likewise.
10164 (vminvq_s32): Likewise.
10165 (vminq_s32): Likewise.
10166 (vmaxvq_s32): Likewise.
10167 (vmaxq_s32): Likewise.
10168 (vhsubq_s32): Likewise.
10169 (vhsubq_n_s32): Likewise.
10170 (vhcaddq_rot90_s32): Likewise.
10171 (vhcaddq_rot270_s32): Likewise.
10172 (vhaddq_s32): Likewise.
10173 (vhaddq_n_s32): Likewise.
10174 (veorq_s32): Likewise.
10175 (vcaddq_rot90_s32): Likewise.
10176 (vcaddq_rot270_s32): Likewise.
10177 (vbrsrq_n_s32): Likewise.
10178 (vbicq_s32): Likewise.
10179 (vandq_s32): Likewise.
10180 (vaddvaq_s32): Likewise.
10181 (vaddq_n_s32): Likewise.
10182 (vabdq_s32): Likewise.
10183 (vshlq_n_s32): Likewise.
10184 (vrshrq_n_s32): Likewise.
10185 (vqshlq_n_s32): Likewise.
10186 (__arm_vsubq_u8): Define intrinsic.
10187 (__arm_vsubq_n_u8): Likewise.
10188 (__arm_vrmulhq_u8): Likewise.
10189 (__arm_vrhaddq_u8): Likewise.
10190 (__arm_vqsubq_u8): Likewise.
10191 (__arm_vqsubq_n_u8): Likewise.
10192 (__arm_vqaddq_u8): Likewise.
10193 (__arm_vqaddq_n_u8): Likewise.
10194 (__arm_vorrq_u8): Likewise.
10195 (__arm_vornq_u8): Likewise.
10196 (__arm_vmulq_u8): Likewise.
10197 (__arm_vmulq_n_u8): Likewise.
10198 (__arm_vmulltq_int_u8): Likewise.
10199 (__arm_vmullbq_int_u8): Likewise.
10200 (__arm_vmulhq_u8): Likewise.
10201 (__arm_vmladavq_u8): Likewise.
10202 (__arm_vminvq_u8): Likewise.
10203 (__arm_vminq_u8): Likewise.
10204 (__arm_vmaxvq_u8): Likewise.
10205 (__arm_vmaxq_u8): Likewise.
10206 (__arm_vhsubq_u8): Likewise.
10207 (__arm_vhsubq_n_u8): Likewise.
10208 (__arm_vhaddq_u8): Likewise.
10209 (__arm_vhaddq_n_u8): Likewise.
10210 (__arm_veorq_u8): Likewise.
10211 (__arm_vcmpneq_n_u8): Likewise.
10212 (__arm_vcmphiq_u8): Likewise.
10213 (__arm_vcmphiq_n_u8): Likewise.
10214 (__arm_vcmpeqq_u8): Likewise.
10215 (__arm_vcmpeqq_n_u8): Likewise.
10216 (__arm_vcmpcsq_u8): Likewise.
10217 (__arm_vcmpcsq_n_u8): Likewise.
10218 (__arm_vcaddq_rot90_u8): Likewise.
10219 (__arm_vcaddq_rot270_u8): Likewise.
10220 (__arm_vbicq_u8): Likewise.
10221 (__arm_vandq_u8): Likewise.
10222 (__arm_vaddvq_p_u8): Likewise.
10223 (__arm_vaddvaq_u8): Likewise.
10224 (__arm_vaddq_n_u8): Likewise.
10225 (__arm_vabdq_u8): Likewise.
10226 (__arm_vshlq_r_u8): Likewise.
10227 (__arm_vrshlq_u8): Likewise.
10228 (__arm_vrshlq_n_u8): Likewise.
10229 (__arm_vqshlq_u8): Likewise.
10230 (__arm_vqshlq_r_u8): Likewise.
10231 (__arm_vqrshlq_u8): Likewise.
10232 (__arm_vqrshlq_n_u8): Likewise.
10233 (__arm_vminavq_s8): Likewise.
10234 (__arm_vminaq_s8): Likewise.
10235 (__arm_vmaxavq_s8): Likewise.
10236 (__arm_vmaxaq_s8): Likewise.
10237 (__arm_vbrsrq_n_u8): Likewise.
10238 (__arm_vshlq_n_u8): Likewise.
10239 (__arm_vrshrq_n_u8): Likewise.
10240 (__arm_vqshlq_n_u8): Likewise.
10241 (__arm_vcmpneq_n_s8): Likewise.
10242 (__arm_vcmpltq_s8): Likewise.
10243 (__arm_vcmpltq_n_s8): Likewise.
10244 (__arm_vcmpleq_s8): Likewise.
10245 (__arm_vcmpleq_n_s8): Likewise.
10246 (__arm_vcmpgtq_s8): Likewise.
10247 (__arm_vcmpgtq_n_s8): Likewise.
10248 (__arm_vcmpgeq_s8): Likewise.
10249 (__arm_vcmpgeq_n_s8): Likewise.
10250 (__arm_vcmpeqq_s8): Likewise.
10251 (__arm_vcmpeqq_n_s8): Likewise.
10252 (__arm_vqshluq_n_s8): Likewise.
10253 (__arm_vaddvq_p_s8): Likewise.
10254 (__arm_vsubq_s8): Likewise.
10255 (__arm_vsubq_n_s8): Likewise.
10256 (__arm_vshlq_r_s8): Likewise.
10257 (__arm_vrshlq_s8): Likewise.
10258 (__arm_vrshlq_n_s8): Likewise.
10259 (__arm_vrmulhq_s8): Likewise.
10260 (__arm_vrhaddq_s8): Likewise.
10261 (__arm_vqsubq_s8): Likewise.
10262 (__arm_vqsubq_n_s8): Likewise.
10263 (__arm_vqshlq_s8): Likewise.
10264 (__arm_vqshlq_r_s8): Likewise.
10265 (__arm_vqrshlq_s8): Likewise.
10266 (__arm_vqrshlq_n_s8): Likewise.
10267 (__arm_vqrdmulhq_s8): Likewise.
10268 (__arm_vqrdmulhq_n_s8): Likewise.
10269 (__arm_vqdmulhq_s8): Likewise.
10270 (__arm_vqdmulhq_n_s8): Likewise.
10271 (__arm_vqaddq_s8): Likewise.
10272 (__arm_vqaddq_n_s8): Likewise.
10273 (__arm_vorrq_s8): Likewise.
10274 (__arm_vornq_s8): Likewise.
10275 (__arm_vmulq_s8): Likewise.
10276 (__arm_vmulq_n_s8): Likewise.
10277 (__arm_vmulltq_int_s8): Likewise.
10278 (__arm_vmullbq_int_s8): Likewise.
10279 (__arm_vmulhq_s8): Likewise.
10280 (__arm_vmlsdavxq_s8): Likewise.
10281 (__arm_vmlsdavq_s8): Likewise.
10282 (__arm_vmladavxq_s8): Likewise.
10283 (__arm_vmladavq_s8): Likewise.
10284 (__arm_vminvq_s8): Likewise.
10285 (__arm_vminq_s8): Likewise.
10286 (__arm_vmaxvq_s8): Likewise.
10287 (__arm_vmaxq_s8): Likewise.
10288 (__arm_vhsubq_s8): Likewise.
10289 (__arm_vhsubq_n_s8): Likewise.
10290 (__arm_vhcaddq_rot90_s8): Likewise.
10291 (__arm_vhcaddq_rot270_s8): Likewise.
10292 (__arm_vhaddq_s8): Likewise.
10293 (__arm_vhaddq_n_s8): Likewise.
10294 (__arm_veorq_s8): Likewise.
10295 (__arm_vcaddq_rot90_s8): Likewise.
10296 (__arm_vcaddq_rot270_s8): Likewise.
10297 (__arm_vbrsrq_n_s8): Likewise.
10298 (__arm_vbicq_s8): Likewise.
10299 (__arm_vandq_s8): Likewise.
10300 (__arm_vaddvaq_s8): Likewise.
10301 (__arm_vaddq_n_s8): Likewise.
10302 (__arm_vabdq_s8): Likewise.
10303 (__arm_vshlq_n_s8): Likewise.
10304 (__arm_vrshrq_n_s8): Likewise.
10305 (__arm_vqshlq_n_s8): Likewise.
10306 (__arm_vsubq_u16): Likewise.
10307 (__arm_vsubq_n_u16): Likewise.
10308 (__arm_vrmulhq_u16): Likewise.
10309 (__arm_vrhaddq_u16): Likewise.
10310 (__arm_vqsubq_u16): Likewise.
10311 (__arm_vqsubq_n_u16): Likewise.
10312 (__arm_vqaddq_u16): Likewise.
10313 (__arm_vqaddq_n_u16): Likewise.
10314 (__arm_vorrq_u16): Likewise.
10315 (__arm_vornq_u16): Likewise.
10316 (__arm_vmulq_u16): Likewise.
10317 (__arm_vmulq_n_u16): Likewise.
10318 (__arm_vmulltq_int_u16): Likewise.
10319 (__arm_vmullbq_int_u16): Likewise.
10320 (__arm_vmulhq_u16): Likewise.
10321 (__arm_vmladavq_u16): Likewise.
10322 (__arm_vminvq_u16): Likewise.
10323 (__arm_vminq_u16): Likewise.
10324 (__arm_vmaxvq_u16): Likewise.
10325 (__arm_vmaxq_u16): Likewise.
10326 (__arm_vhsubq_u16): Likewise.
10327 (__arm_vhsubq_n_u16): Likewise.
10328 (__arm_vhaddq_u16): Likewise.
10329 (__arm_vhaddq_n_u16): Likewise.
10330 (__arm_veorq_u16): Likewise.
10331 (__arm_vcmpneq_n_u16): Likewise.
10332 (__arm_vcmphiq_u16): Likewise.
10333 (__arm_vcmphiq_n_u16): Likewise.
10334 (__arm_vcmpeqq_u16): Likewise.
10335 (__arm_vcmpeqq_n_u16): Likewise.
10336 (__arm_vcmpcsq_u16): Likewise.
10337 (__arm_vcmpcsq_n_u16): Likewise.
10338 (__arm_vcaddq_rot90_u16): Likewise.
10339 (__arm_vcaddq_rot270_u16): Likewise.
10340 (__arm_vbicq_u16): Likewise.
10341 (__arm_vandq_u16): Likewise.
10342 (__arm_vaddvq_p_u16): Likewise.
10343 (__arm_vaddvaq_u16): Likewise.
10344 (__arm_vaddq_n_u16): Likewise.
10345 (__arm_vabdq_u16): Likewise.
10346 (__arm_vshlq_r_u16): Likewise.
10347 (__arm_vrshlq_u16): Likewise.
10348 (__arm_vrshlq_n_u16): Likewise.
10349 (__arm_vqshlq_u16): Likewise.
10350 (__arm_vqshlq_r_u16): Likewise.
10351 (__arm_vqrshlq_u16): Likewise.
10352 (__arm_vqrshlq_n_u16): Likewise.
10353 (__arm_vminavq_s16): Likewise.
10354 (__arm_vminaq_s16): Likewise.
10355 (__arm_vmaxavq_s16): Likewise.
10356 (__arm_vmaxaq_s16): Likewise.
10357 (__arm_vbrsrq_n_u16): Likewise.
10358 (__arm_vshlq_n_u16): Likewise.
10359 (__arm_vrshrq_n_u16): Likewise.
10360 (__arm_vqshlq_n_u16): Likewise.
10361 (__arm_vcmpneq_n_s16): Likewise.
10362 (__arm_vcmpltq_s16): Likewise.
10363 (__arm_vcmpltq_n_s16): Likewise.
10364 (__arm_vcmpleq_s16): Likewise.
10365 (__arm_vcmpleq_n_s16): Likewise.
10366 (__arm_vcmpgtq_s16): Likewise.
10367 (__arm_vcmpgtq_n_s16): Likewise.
10368 (__arm_vcmpgeq_s16): Likewise.
10369 (__arm_vcmpgeq_n_s16): Likewise.
10370 (__arm_vcmpeqq_s16): Likewise.
10371 (__arm_vcmpeqq_n_s16): Likewise.
10372 (__arm_vqshluq_n_s16): Likewise.
10373 (__arm_vaddvq_p_s16): Likewise.
10374 (__arm_vsubq_s16): Likewise.
10375 (__arm_vsubq_n_s16): Likewise.
10376 (__arm_vshlq_r_s16): Likewise.
10377 (__arm_vrshlq_s16): Likewise.
10378 (__arm_vrshlq_n_s16): Likewise.
10379 (__arm_vrmulhq_s16): Likewise.
10380 (__arm_vrhaddq_s16): Likewise.
10381 (__arm_vqsubq_s16): Likewise.
10382 (__arm_vqsubq_n_s16): Likewise.
10383 (__arm_vqshlq_s16): Likewise.
10384 (__arm_vqshlq_r_s16): Likewise.
10385 (__arm_vqrshlq_s16): Likewise.
10386 (__arm_vqrshlq_n_s16): Likewise.
10387 (__arm_vqrdmulhq_s16): Likewise.
10388 (__arm_vqrdmulhq_n_s16): Likewise.
10389 (__arm_vqdmulhq_s16): Likewise.
10390 (__arm_vqdmulhq_n_s16): Likewise.
10391 (__arm_vqaddq_s16): Likewise.
10392 (__arm_vqaddq_n_s16): Likewise.
10393 (__arm_vorrq_s16): Likewise.
10394 (__arm_vornq_s16): Likewise.
10395 (__arm_vmulq_s16): Likewise.
10396 (__arm_vmulq_n_s16): Likewise.
10397 (__arm_vmulltq_int_s16): Likewise.
10398 (__arm_vmullbq_int_s16): Likewise.
10399 (__arm_vmulhq_s16): Likewise.
10400 (__arm_vmlsdavxq_s16): Likewise.
10401 (__arm_vmlsdavq_s16): Likewise.
10402 (__arm_vmladavxq_s16): Likewise.
10403 (__arm_vmladavq_s16): Likewise.
10404 (__arm_vminvq_s16): Likewise.
10405 (__arm_vminq_s16): Likewise.
10406 (__arm_vmaxvq_s16): Likewise.
10407 (__arm_vmaxq_s16): Likewise.
10408 (__arm_vhsubq_s16): Likewise.
10409 (__arm_vhsubq_n_s16): Likewise.
10410 (__arm_vhcaddq_rot90_s16): Likewise.
10411 (__arm_vhcaddq_rot270_s16): Likewise.
10412 (__arm_vhaddq_s16): Likewise.
10413 (__arm_vhaddq_n_s16): Likewise.
10414 (__arm_veorq_s16): Likewise.
10415 (__arm_vcaddq_rot90_s16): Likewise.
10416 (__arm_vcaddq_rot270_s16): Likewise.
10417 (__arm_vbrsrq_n_s16): Likewise.
10418 (__arm_vbicq_s16): Likewise.
10419 (__arm_vandq_s16): Likewise.
10420 (__arm_vaddvaq_s16): Likewise.
10421 (__arm_vaddq_n_s16): Likewise.
10422 (__arm_vabdq_s16): Likewise.
10423 (__arm_vshlq_n_s16): Likewise.
10424 (__arm_vrshrq_n_s16): Likewise.
10425 (__arm_vqshlq_n_s16): Likewise.
10426 (__arm_vsubq_u32): Likewise.
10427 (__arm_vsubq_n_u32): Likewise.
10428 (__arm_vrmulhq_u32): Likewise.
10429 (__arm_vrhaddq_u32): Likewise.
10430 (__arm_vqsubq_u32): Likewise.
10431 (__arm_vqsubq_n_u32): Likewise.
10432 (__arm_vqaddq_u32): Likewise.
10433 (__arm_vqaddq_n_u32): Likewise.
10434 (__arm_vorrq_u32): Likewise.
10435 (__arm_vornq_u32): Likewise.
10436 (__arm_vmulq_u32): Likewise.
10437 (__arm_vmulq_n_u32): Likewise.
10438 (__arm_vmulltq_int_u32): Likewise.
10439 (__arm_vmullbq_int_u32): Likewise.
10440 (__arm_vmulhq_u32): Likewise.
10441 (__arm_vmladavq_u32): Likewise.
10442 (__arm_vminvq_u32): Likewise.
10443 (__arm_vminq_u32): Likewise.
10444 (__arm_vmaxvq_u32): Likewise.
10445 (__arm_vmaxq_u32): Likewise.
10446 (__arm_vhsubq_u32): Likewise.
10447 (__arm_vhsubq_n_u32): Likewise.
10448 (__arm_vhaddq_u32): Likewise.
10449 (__arm_vhaddq_n_u32): Likewise.
10450 (__arm_veorq_u32): Likewise.
10451 (__arm_vcmpneq_n_u32): Likewise.
10452 (__arm_vcmphiq_u32): Likewise.
10453 (__arm_vcmphiq_n_u32): Likewise.
10454 (__arm_vcmpeqq_u32): Likewise.
10455 (__arm_vcmpeqq_n_u32): Likewise.
10456 (__arm_vcmpcsq_u32): Likewise.
10457 (__arm_vcmpcsq_n_u32): Likewise.
10458 (__arm_vcaddq_rot90_u32): Likewise.
10459 (__arm_vcaddq_rot270_u32): Likewise.
10460 (__arm_vbicq_u32): Likewise.
10461 (__arm_vandq_u32): Likewise.
10462 (__arm_vaddvq_p_u32): Likewise.
10463 (__arm_vaddvaq_u32): Likewise.
10464 (__arm_vaddq_n_u32): Likewise.
10465 (__arm_vabdq_u32): Likewise.
10466 (__arm_vshlq_r_u32): Likewise.
10467 (__arm_vrshlq_u32): Likewise.
10468 (__arm_vrshlq_n_u32): Likewise.
10469 (__arm_vqshlq_u32): Likewise.
10470 (__arm_vqshlq_r_u32): Likewise.
10471 (__arm_vqrshlq_u32): Likewise.
10472 (__arm_vqrshlq_n_u32): Likewise.
10473 (__arm_vminavq_s32): Likewise.
10474 (__arm_vminaq_s32): Likewise.
10475 (__arm_vmaxavq_s32): Likewise.
10476 (__arm_vmaxaq_s32): Likewise.
10477 (__arm_vbrsrq_n_u32): Likewise.
10478 (__arm_vshlq_n_u32): Likewise.
10479 (__arm_vrshrq_n_u32): Likewise.
10480 (__arm_vqshlq_n_u32): Likewise.
10481 (__arm_vcmpneq_n_s32): Likewise.
10482 (__arm_vcmpltq_s32): Likewise.
10483 (__arm_vcmpltq_n_s32): Likewise.
10484 (__arm_vcmpleq_s32): Likewise.
10485 (__arm_vcmpleq_n_s32): Likewise.
10486 (__arm_vcmpgtq_s32): Likewise.
10487 (__arm_vcmpgtq_n_s32): Likewise.
10488 (__arm_vcmpgeq_s32): Likewise.
10489 (__arm_vcmpgeq_n_s32): Likewise.
10490 (__arm_vcmpeqq_s32): Likewise.
10491 (__arm_vcmpeqq_n_s32): Likewise.
10492 (__arm_vqshluq_n_s32): Likewise.
10493 (__arm_vaddvq_p_s32): Likewise.
10494 (__arm_vsubq_s32): Likewise.
10495 (__arm_vsubq_n_s32): Likewise.
10496 (__arm_vshlq_r_s32): Likewise.
10497 (__arm_vrshlq_s32): Likewise.
10498 (__arm_vrshlq_n_s32): Likewise.
10499 (__arm_vrmulhq_s32): Likewise.
10500 (__arm_vrhaddq_s32): Likewise.
10501 (__arm_vqsubq_s32): Likewise.
10502 (__arm_vqsubq_n_s32): Likewise.
10503 (__arm_vqshlq_s32): Likewise.
10504 (__arm_vqshlq_r_s32): Likewise.
10505 (__arm_vqrshlq_s32): Likewise.
10506 (__arm_vqrshlq_n_s32): Likewise.
10507 (__arm_vqrdmulhq_s32): Likewise.
10508 (__arm_vqrdmulhq_n_s32): Likewise.
10509 (__arm_vqdmulhq_s32): Likewise.
10510 (__arm_vqdmulhq_n_s32): Likewise.
10511 (__arm_vqaddq_s32): Likewise.
10512 (__arm_vqaddq_n_s32): Likewise.
10513 (__arm_vorrq_s32): Likewise.
10514 (__arm_vornq_s32): Likewise.
10515 (__arm_vmulq_s32): Likewise.
10516 (__arm_vmulq_n_s32): Likewise.
10517 (__arm_vmulltq_int_s32): Likewise.
10518 (__arm_vmullbq_int_s32): Likewise.
10519 (__arm_vmulhq_s32): Likewise.
10520 (__arm_vmlsdavxq_s32): Likewise.
10521 (__arm_vmlsdavq_s32): Likewise.
10522 (__arm_vmladavxq_s32): Likewise.
10523 (__arm_vmladavq_s32): Likewise.
10524 (__arm_vminvq_s32): Likewise.
10525 (__arm_vminq_s32): Likewise.
10526 (__arm_vmaxvq_s32): Likewise.
10527 (__arm_vmaxq_s32): Likewise.
10528 (__arm_vhsubq_s32): Likewise.
10529 (__arm_vhsubq_n_s32): Likewise.
10530 (__arm_vhcaddq_rot90_s32): Likewise.
10531 (__arm_vhcaddq_rot270_s32): Likewise.
10532 (__arm_vhaddq_s32): Likewise.
10533 (__arm_vhaddq_n_s32): Likewise.
10534 (__arm_veorq_s32): Likewise.
10535 (__arm_vcaddq_rot90_s32): Likewise.
10536 (__arm_vcaddq_rot270_s32): Likewise.
10537 (__arm_vbrsrq_n_s32): Likewise.
10538 (__arm_vbicq_s32): Likewise.
10539 (__arm_vandq_s32): Likewise.
10540 (__arm_vaddvaq_s32): Likewise.
10541 (__arm_vaddq_n_s32): Likewise.
10542 (__arm_vabdq_s32): Likewise.
10543 (__arm_vshlq_n_s32): Likewise.
10544 (__arm_vrshrq_n_s32): Likewise.
10545 (__arm_vqshlq_n_s32): Likewise.
10546 (vsubq): Define polymorphic variant.
10547 (vsubq_n): Likewise.
10548 (vshlq_r): Likewise.
10549 (vrshlq_n): Likewise.
10550 (vrshlq): Likewise.
10551 (vrmulhq): Likewise.
10552 (vrhaddq): Likewise.
10553 (vqsubq_n): Likewise.
10554 (vqsubq): Likewise.
10555 (vqshlq): Likewise.
10556 (vqshlq_r): Likewise.
10557 (vqshluq): Likewise.
10558 (vrshrq_n): Likewise.
10559 (vshlq_n): Likewise.
10560 (vqshluq_n): Likewise.
10561 (vqshlq_n): Likewise.
10562 (vqrshlq_n): Likewise.
10563 (vqrshlq): Likewise.
10564 (vqrdmulhq_n): Likewise.
10565 (vqrdmulhq): Likewise.
10566 (vqdmulhq_n): Likewise.
10567 (vqdmulhq): Likewise.
10568 (vqaddq_n): Likewise.
10569 (vqaddq): Likewise.
10570 (vorrq_n): Likewise.
10573 (vmulq_n): Likewise.
10575 (vmulltq_int): Likewise.
10576 (vmullbq_int): Likewise.
10577 (vmulhq): Likewise.
10579 (vminaq): Likewise.
10581 (vmaxaq): Likewise.
10582 (vhsubq_n): Likewise.
10583 (vhsubq): Likewise.
10584 (vhcaddq_rot90): Likewise.
10585 (vhcaddq_rot270): Likewise.
10586 (vhaddq_n): Likewise.
10587 (vhaddq): Likewise.
10589 (vcaddq_rot90): Likewise.
10590 (vcaddq_rot270): Likewise.
10591 (vbrsrq_n): Likewise.
10592 (vbicq_n): Likewise.
10595 (vaddq_n): Likewise.
10598 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
10599 (BINOP_NONE_NONE_NONE): Likewise.
10600 (BINOP_NONE_NONE_UNONE): Likewise.
10601 (BINOP_UNONE_NONE_IMM): Likewise.
10602 (BINOP_UNONE_NONE_NONE): Likewise.
10603 (BINOP_UNONE_UNONE_IMM): Likewise.
10604 (BINOP_UNONE_UNONE_NONE): Likewise.
10605 (BINOP_UNONE_UNONE_UNONE): Likewise.
10606 * config/arm/constraints.md (Ra): Define constraint to check constant is
10607 in the range of 0 to 7.
10608 (Rg): Define constriant to check the constant is one among 1, 2, 4
10610 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern.
10611 (mve_vaddq_n_<supf>): Likewise.
10612 (mve_vaddvaq_<supf>): Likewise.
10613 (mve_vaddvq_p_<supf>): Likewise.
10614 (mve_vandq_<supf>): Likewise.
10615 (mve_vbicq_<supf>): Likewise.
10616 (mve_vbrsrq_n_<supf>): Likewise.
10617 (mve_vcaddq_rot270_<supf>): Likewise.
10618 (mve_vcaddq_rot90_<supf>): Likewise.
10619 (mve_vcmpcsq_n_u): Likewise.
10620 (mve_vcmpcsq_u): Likewise.
10621 (mve_vcmpeqq_n_<supf>): Likewise.
10622 (mve_vcmpeqq_<supf>): Likewise.
10623 (mve_vcmpgeq_n_s): Likewise.
10624 (mve_vcmpgeq_s): Likewise.
10625 (mve_vcmpgtq_n_s): Likewise.
10626 (mve_vcmpgtq_s): Likewise.
10627 (mve_vcmphiq_n_u): Likewise.
10628 (mve_vcmphiq_u): Likewise.
10629 (mve_vcmpleq_n_s): Likewise.
10630 (mve_vcmpleq_s): Likewise.
10631 (mve_vcmpltq_n_s): Likewise.
10632 (mve_vcmpltq_s): Likewise.
10633 (mve_vcmpneq_n_<supf>): Likewise.
10634 (mve_vddupq_n_u): Likewise.
10635 (mve_veorq_<supf>): Likewise.
10636 (mve_vhaddq_n_<supf>): Likewise.
10637 (mve_vhaddq_<supf>): Likewise.
10638 (mve_vhcaddq_rot270_s): Likewise.
10639 (mve_vhcaddq_rot90_s): Likewise.
10640 (mve_vhsubq_n_<supf>): Likewise.
10641 (mve_vhsubq_<supf>): Likewise.
10642 (mve_vidupq_n_u): Likewise.
10643 (mve_vmaxaq_s): Likewise.
10644 (mve_vmaxavq_s): Likewise.
10645 (mve_vmaxq_<supf>): Likewise.
10646 (mve_vmaxvq_<supf>): Likewise.
10647 (mve_vminaq_s): Likewise.
10648 (mve_vminavq_s): Likewise.
10649 (mve_vminq_<supf>): Likewise.
10650 (mve_vminvq_<supf>): Likewise.
10651 (mve_vmladavq_<supf>): Likewise.
10652 (mve_vmladavxq_s): Likewise.
10653 (mve_vmlsdavq_s): Likewise.
10654 (mve_vmlsdavxq_s): Likewise.
10655 (mve_vmulhq_<supf>): Likewise.
10656 (mve_vmullbq_int_<supf>): Likewise.
10657 (mve_vmulltq_int_<supf>): Likewise.
10658 (mve_vmulq_n_<supf>): Likewise.
10659 (mve_vmulq_<supf>): Likewise.
10660 (mve_vornq_<supf>): Likewise.
10661 (mve_vorrq_<supf>): Likewise.
10662 (mve_vqaddq_n_<supf>): Likewise.
10663 (mve_vqaddq_<supf>): Likewise.
10664 (mve_vqdmulhq_n_s): Likewise.
10665 (mve_vqdmulhq_s): Likewise.
10666 (mve_vqrdmulhq_n_s): Likewise.
10667 (mve_vqrdmulhq_s): Likewise.
10668 (mve_vqrshlq_n_<supf>): Likewise.
10669 (mve_vqrshlq_<supf>): Likewise.
10670 (mve_vqshlq_n_<supf>): Likewise.
10671 (mve_vqshlq_r_<supf>): Likewise.
10672 (mve_vqshlq_<supf>): Likewise.
10673 (mve_vqshluq_n_s): Likewise.
10674 (mve_vqsubq_n_<supf>): Likewise.
10675 (mve_vqsubq_<supf>): Likewise.
10676 (mve_vrhaddq_<supf>): Likewise.
10677 (mve_vrmulhq_<supf>): Likewise.
10678 (mve_vrshlq_n_<supf>): Likewise.
10679 (mve_vrshlq_<supf>): Likewise.
10680 (mve_vrshrq_n_<supf>): Likewise.
10681 (mve_vshlq_n_<supf>): Likewise.
10682 (mve_vshlq_r_<supf>): Likewise.
10683 (mve_vsubq_n_<supf>): Likewise.
10684 (mve_vsubq_<supf>): Likewise.
10685 * config/arm/predicates.md (mve_imm_7): Define predicate to check
10686 the matching constraint Ra.
10687 (mve_imm_selective_upto_8): Define predicate to check the matching
10690 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10691 Mihail Ionescu <mihail.ionescu@arm.com>
10692 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10694 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define
10695 qualifier for binary operands.
10696 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
10697 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
10698 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro.
10699 (vaddlvq_p_u32): Likewise.
10700 (vcmpneq_s8): Likewise.
10701 (vcmpneq_s16): Likewise.
10702 (vcmpneq_s32): Likewise.
10703 (vcmpneq_u8): Likewise.
10704 (vcmpneq_u16): Likewise.
10705 (vcmpneq_u32): Likewise.
10706 (vshlq_s8): Likewise.
10707 (vshlq_s16): Likewise.
10708 (vshlq_s32): Likewise.
10709 (vshlq_u8): Likewise.
10710 (vshlq_u16): Likewise.
10711 (vshlq_u32): Likewise.
10712 (__arm_vaddlvq_p_s32): Define intrinsic.
10713 (__arm_vaddlvq_p_u32): Likewise.
10714 (__arm_vcmpneq_s8): Likewise.
10715 (__arm_vcmpneq_s16): Likewise.
10716 (__arm_vcmpneq_s32): Likewise.
10717 (__arm_vcmpneq_u8): Likewise.
10718 (__arm_vcmpneq_u16): Likewise.
10719 (__arm_vcmpneq_u32): Likewise.
10720 (__arm_vshlq_s8): Likewise.
10721 (__arm_vshlq_s16): Likewise.
10722 (__arm_vshlq_s32): Likewise.
10723 (__arm_vshlq_u8): Likewise.
10724 (__arm_vshlq_u16): Likewise.
10725 (__arm_vshlq_u32): Likewise.
10726 (vaddlvq_p): Define polymorphic variant.
10727 (vcmpneq): Likewise.
10729 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS):
10731 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
10732 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
10733 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern.
10734 (mve_vcmpneq_<supf><mode>): Likewise.
10735 (mve_vshlq_<supf><mode>): Likewise.
10737 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10738 Mihail Ionescu <mihail.ionescu@arm.com>
10739 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10741 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
10742 qualifier for binary operands.
10743 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
10744 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
10745 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
10746 (vcvtq_n_s32_f32): Likewise.
10747 (vcvtq_n_u16_f16): Likewise.
10748 (vcvtq_n_u32_f32): Likewise.
10749 (vcreateq_u8): Likewise.
10750 (vcreateq_u16): Likewise.
10751 (vcreateq_u32): Likewise.
10752 (vcreateq_u64): Likewise.
10753 (vcreateq_s8): Likewise.
10754 (vcreateq_s16): Likewise.
10755 (vcreateq_s32): Likewise.
10756 (vcreateq_s64): Likewise.
10757 (vshrq_n_s8): Likewise.
10758 (vshrq_n_s16): Likewise.
10759 (vshrq_n_s32): Likewise.
10760 (vshrq_n_u8): Likewise.
10761 (vshrq_n_u16): Likewise.
10762 (vshrq_n_u32): Likewise.
10763 (__arm_vcreateq_u8): Define intrinsic.
10764 (__arm_vcreateq_u16): Likewise.
10765 (__arm_vcreateq_u32): Likewise.
10766 (__arm_vcreateq_u64): Likewise.
10767 (__arm_vcreateq_s8): Likewise.
10768 (__arm_vcreateq_s16): Likewise.
10769 (__arm_vcreateq_s32): Likewise.
10770 (__arm_vcreateq_s64): Likewise.
10771 (__arm_vshrq_n_s8): Likewise.
10772 (__arm_vshrq_n_s16): Likewise.
10773 (__arm_vshrq_n_s32): Likewise.
10774 (__arm_vshrq_n_u8): Likewise.
10775 (__arm_vshrq_n_u16): Likewise.
10776 (__arm_vshrq_n_u32): Likewise.
10777 (__arm_vcvtq_n_s16_f16): Likewise.
10778 (__arm_vcvtq_n_s32_f32): Likewise.
10779 (__arm_vcvtq_n_u16_f16): Likewise.
10780 (__arm_vcvtq_n_u32_f32): Likewise.
10781 (vshrq_n): Define polymorphic variant.
10782 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
10784 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
10785 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
10786 * config/arm/constraints.md (Rb): Define constraint to check constant is
10787 in the range of 1 to 8.
10788 (Rf): Define constraint to check constant is in the range of 1 to 32.
10789 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
10790 (mve_vshrq_n_<supf><mode>): Likewise.
10791 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
10792 * config/arm/predicates.md (mve_imm_8): Define predicate to check
10793 the matching constraint Rb.
10794 (mve_imm_32): Define predicate to check the matching constraint Rf.
10796 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10797 Mihail Ionescu <mihail.ionescu@arm.com>
10798 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10800 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
10801 qualifier for binary operands.
10802 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
10803 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
10804 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
10805 * config/arm/arm_mve.h (vsubq_n_f16): Define macro.
10806 (vsubq_n_f32): Likewise.
10807 (vbrsrq_n_f16): Likewise.
10808 (vbrsrq_n_f32): Likewise.
10809 (vcvtq_n_f16_s16): Likewise.
10810 (vcvtq_n_f32_s32): Likewise.
10811 (vcvtq_n_f16_u16): Likewise.
10812 (vcvtq_n_f32_u32): Likewise.
10813 (vcreateq_f16): Likewise.
10814 (vcreateq_f32): Likewise.
10815 (__arm_vsubq_n_f16): Define intrinsic.
10816 (__arm_vsubq_n_f32): Likewise.
10817 (__arm_vbrsrq_n_f16): Likewise.
10818 (__arm_vbrsrq_n_f32): Likewise.
10819 (__arm_vcvtq_n_f16_s16): Likewise.
10820 (__arm_vcvtq_n_f32_s32): Likewise.
10821 (__arm_vcvtq_n_f16_u16): Likewise.
10822 (__arm_vcvtq_n_f32_u32): Likewise.
10823 (__arm_vcreateq_f16): Likewise.
10824 (__arm_vcreateq_f32): Likewise.
10825 (vsubq): Define polymorphic variant.
10826 (vbrsrq): Likewise.
10827 (vcvtq_n): Likewise.
10828 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use
10830 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
10831 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
10832 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
10833 * config/arm/constraints.md (Rd): Define constraint to check constant is
10834 in the range of 1 to 16.
10835 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern.
10836 mve_vbrsrq_n_f<mode>: Likewise.
10837 mve_vcvtq_n_to_f_<supf><mode>: Likewise.
10838 mve_vcreateq_f<mode>: Likewise.
10839 * config/arm/predicates.md (mve_imm_16): Define predicate to check
10840 the matching constraint Rd.
10842 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10843 Mihail Ionescu <mihail.ionescu@arm.com>
10844 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10846 * config/arm/arm-builtins.c (hi_UP): Define mode.
10847 * config/arm/arm.h (IS_VPR_REGNUM): Move.
10848 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
10849 (APSRQ_REGNUM): Modify.
10850 (APSRGE_REGNUM): Modify.
10851 * config/arm/arm_mve.h (vctp16q): Define macro.
10852 (vctp32q): Likewise.
10853 (vctp64q): Likewise.
10854 (vctp8q): Likewise.
10856 (__arm_vctp16q): Define intrinsic.
10857 (__arm_vctp32q): Likewise.
10858 (__arm_vctp64q): Likewise.
10859 (__arm_vctp8q): Likewise.
10860 (__arm_vpnot): Likewise.
10861 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
10863 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
10864 (mve_vpnothi): Likewise.
10866 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10867 Mihail Ionescu <mihail.ionescu@arm.com>
10868 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10870 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
10871 * config/arm/arm_mve.h (vdupq_n_s8): Define macro.
10872 (vdupq_n_s16): Likewise.
10873 (vdupq_n_s32): Likewise.
10874 (vabsq_s8): Likewise.
10875 (vabsq_s16): Likewise.
10876 (vabsq_s32): Likewise.
10877 (vclsq_s8): Likewise.
10878 (vclsq_s16): Likewise.
10879 (vclsq_s32): Likewise.
10880 (vclzq_s8): Likewise.
10881 (vclzq_s16): Likewise.
10882 (vclzq_s32): Likewise.
10883 (vnegq_s8): Likewise.
10884 (vnegq_s16): Likewise.
10885 (vnegq_s32): Likewise.
10886 (vaddlvq_s32): Likewise.
10887 (vaddvq_s8): Likewise.
10888 (vaddvq_s16): Likewise.
10889 (vaddvq_s32): Likewise.
10890 (vmovlbq_s8): Likewise.
10891 (vmovlbq_s16): Likewise.
10892 (vmovltq_s8): Likewise.
10893 (vmovltq_s16): Likewise.
10894 (vmvnq_s8): Likewise.
10895 (vmvnq_s16): Likewise.
10896 (vmvnq_s32): Likewise.
10897 (vrev16q_s8): Likewise.
10898 (vrev32q_s8): Likewise.
10899 (vrev32q_s16): Likewise.
10900 (vqabsq_s8): Likewise.
10901 (vqabsq_s16): Likewise.
10902 (vqabsq_s32): Likewise.
10903 (vqnegq_s8): Likewise.
10904 (vqnegq_s16): Likewise.
10905 (vqnegq_s32): Likewise.
10906 (vcvtaq_s16_f16): Likewise.
10907 (vcvtaq_s32_f32): Likewise.
10908 (vcvtnq_s16_f16): Likewise.
10909 (vcvtnq_s32_f32): Likewise.
10910 (vcvtpq_s16_f16): Likewise.
10911 (vcvtpq_s32_f32): Likewise.
10912 (vcvtmq_s16_f16): Likewise.
10913 (vcvtmq_s32_f32): Likewise.
10914 (vmvnq_u8): Likewise.
10915 (vmvnq_u16): Likewise.
10916 (vmvnq_u32): Likewise.
10917 (vdupq_n_u8): Likewise.
10918 (vdupq_n_u16): Likewise.
10919 (vdupq_n_u32): Likewise.
10920 (vclzq_u8): Likewise.
10921 (vclzq_u16): Likewise.
10922 (vclzq_u32): Likewise.
10923 (vaddvq_u8): Likewise.
10924 (vaddvq_u16): Likewise.
10925 (vaddvq_u32): Likewise.
10926 (vrev32q_u8): Likewise.
10927 (vrev32q_u16): Likewise.
10928 (vmovltq_u8): Likewise.
10929 (vmovltq_u16): Likewise.
10930 (vmovlbq_u8): Likewise.
10931 (vmovlbq_u16): Likewise.
10932 (vrev16q_u8): Likewise.
10933 (vaddlvq_u32): Likewise.
10934 (vcvtpq_u16_f16): Likewise.
10935 (vcvtpq_u32_f32): Likewise.
10936 (vcvtnq_u16_f16): Likewise.
10937 (vcvtmq_u16_f16): Likewise.
10938 (vcvtmq_u32_f32): Likewise.
10939 (vcvtaq_u16_f16): Likewise.
10940 (vcvtaq_u32_f32): Likewise.
10941 (__arm_vdupq_n_s8): Define intrinsic.
10942 (__arm_vdupq_n_s16): Likewise.
10943 (__arm_vdupq_n_s32): Likewise.
10944 (__arm_vabsq_s8): Likewise.
10945 (__arm_vabsq_s16): Likewise.
10946 (__arm_vabsq_s32): Likewise.
10947 (__arm_vclsq_s8): Likewise.
10948 (__arm_vclsq_s16): Likewise.
10949 (__arm_vclsq_s32): Likewise.
10950 (__arm_vclzq_s8): Likewise.
10951 (__arm_vclzq_s16): Likewise.
10952 (__arm_vclzq_s32): Likewise.
10953 (__arm_vnegq_s8): Likewise.
10954 (__arm_vnegq_s16): Likewise.
10955 (__arm_vnegq_s32): Likewise.
10956 (__arm_vaddlvq_s32): Likewise.
10957 (__arm_vaddvq_s8): Likewise.
10958 (__arm_vaddvq_s16): Likewise.
10959 (__arm_vaddvq_s32): Likewise.
10960 (__arm_vmovlbq_s8): Likewise.
10961 (__arm_vmovlbq_s16): Likewise.
10962 (__arm_vmovltq_s8): Likewise.
10963 (__arm_vmovltq_s16): Likewise.
10964 (__arm_vmvnq_s8): Likewise.
10965 (__arm_vmvnq_s16): Likewise.
10966 (__arm_vmvnq_s32): Likewise.
10967 (__arm_vrev16q_s8): Likewise.
10968 (__arm_vrev32q_s8): Likewise.
10969 (__arm_vrev32q_s16): Likewise.
10970 (__arm_vqabsq_s8): Likewise.
10971 (__arm_vqabsq_s16): Likewise.
10972 (__arm_vqabsq_s32): Likewise.
10973 (__arm_vqnegq_s8): Likewise.
10974 (__arm_vqnegq_s16): Likewise.
10975 (__arm_vqnegq_s32): Likewise.
10976 (__arm_vmvnq_u8): Likewise.
10977 (__arm_vmvnq_u16): Likewise.
10978 (__arm_vmvnq_u32): Likewise.
10979 (__arm_vdupq_n_u8): Likewise.
10980 (__arm_vdupq_n_u16): Likewise.
10981 (__arm_vdupq_n_u32): Likewise.
10982 (__arm_vclzq_u8): Likewise.
10983 (__arm_vclzq_u16): Likewise.
10984 (__arm_vclzq_u32): Likewise.
10985 (__arm_vaddvq_u8): Likewise.
10986 (__arm_vaddvq_u16): Likewise.
10987 (__arm_vaddvq_u32): Likewise.
10988 (__arm_vrev32q_u8): Likewise.
10989 (__arm_vrev32q_u16): Likewise.
10990 (__arm_vmovltq_u8): Likewise.
10991 (__arm_vmovltq_u16): Likewise.
10992 (__arm_vmovlbq_u8): Likewise.
10993 (__arm_vmovlbq_u16): Likewise.
10994 (__arm_vrev16q_u8): Likewise.
10995 (__arm_vaddlvq_u32): Likewise.
10996 (__arm_vcvtpq_u16_f16): Likewise.
10997 (__arm_vcvtpq_u32_f32): Likewise.
10998 (__arm_vcvtnq_u16_f16): Likewise.
10999 (__arm_vcvtmq_u16_f16): Likewise.
11000 (__arm_vcvtmq_u32_f32): Likewise.
11001 (__arm_vcvtaq_u16_f16): Likewise.
11002 (__arm_vcvtaq_u32_f32): Likewise.
11003 (__arm_vcvtaq_s16_f16): Likewise.
11004 (__arm_vcvtaq_s32_f32): Likewise.
11005 (__arm_vcvtnq_s16_f16): Likewise.
11006 (__arm_vcvtnq_s32_f32): Likewise.
11007 (__arm_vcvtpq_s16_f16): Likewise.
11008 (__arm_vcvtpq_s32_f32): Likewise.
11009 (__arm_vcvtmq_s16_f16): Likewise.
11010 (__arm_vcvtmq_s32_f32): Likewise.
11011 (vdupq_n): Define polymorphic variant.
11016 (vaddlvq): Likewise.
11017 (vaddvq): Likewise.
11018 (vmovlbq): Likewise.
11019 (vmovltq): Likewise.
11021 (vrev16q): Likewise.
11022 (vrev32q): Likewise.
11023 (vqabsq): Likewise.
11024 (vqnegq): Likewise.
11025 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
11026 (UNOP_SNONE_NONE): Likewise.
11027 (UNOP_UNONE_UNONE): Likewise.
11028 (UNOP_UNONE_NONE): Likewise.
11029 * config/arm/constraints.md (e): Define new constriant to allow only
11031 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
11032 (mve_vnegq_s<mode>): Likewise.
11033 (mve_vmvnq_<supf><mode>): Likewise.
11034 (mve_vdupq_n_<supf><mode>): Likewise.
11035 (mve_vclzq_<supf><mode>): Likewise.
11036 (mve_vclsq_s<mode>): Likewise.
11037 (mve_vaddvq_<supf><mode>): Likewise.
11038 (mve_vabsq_s<mode>): Likewise.
11039 (mve_vrev32q_<supf><mode>): Likewise.
11040 (mve_vmovltq_<supf><mode>): Likewise.
11041 (mve_vmovlbq_<supf><mode>): Likewise.
11042 (mve_vcvtpq_<supf><mode>): Likewise.
11043 (mve_vcvtnq_<supf><mode>): Likewise.
11044 (mve_vcvtmq_<supf><mode>): Likewise.
11045 (mve_vcvtaq_<supf><mode>): Likewise.
11046 (mve_vrev16q_<supf>v16qi): Likewise.
11047 (mve_vaddlvq_<supf>v4si): Likewise.
11049 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11051 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in
11053 * tree-sra.c (create_access_replacement): Fix up duplicated word issue
11055 * read-rtl-function.c (find_param_by_name,
11056 function_reader::parse_enum_value, function_reader::get_insn_by_uid):
11058 * spellcheck.c (get_edit_distance_cutoff): Likewise.
11059 * tree-data-ref.c (create_ifn_alias_checks): Likewise.
11060 * tree.def (SWITCH_EXPR): Likewise.
11061 * selftest.c (assert_str_contains): Likewise.
11062 * ipa-param-manipulation.h (class ipa_param_body_adjustments):
11064 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise.
11065 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise.
11066 * langhooks.h (struct lang_hooks_for_decls): Likewise.
11067 * ipa-prop.h (struct ipa_param_descriptor): Likewise.
11068 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store):
11070 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise.
11071 * tree-ssa-reassoc.c (reassociate_bb): Likewise.
11072 * tree.c (component_ref_size): Likewise.
11073 * hsa-common.c (hsa_init_compilation_unit_data): Likewise.
11074 * gimple-ssa-sprintf.c (get_string_length, format_string,
11075 format_directive): Likewise.
11076 * omp-grid.c (grid_process_kernel_body_copy): Likewise.
11077 * input.c (string_concat_db::get_string_concatenation,
11078 test_lexer_string_locations_ucn4): Likewise.
11079 * cfgexpand.c (pass_expand::execute): Likewise.
11080 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds,
11081 maybe_diag_overlap): Likewise.
11082 * rtl.c (RTX_CODE_HWINT_P_1): Likewise.
11083 * shrink-wrap.c (spread_components): Likewise.
11084 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse):
11086 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
11088 * dwarf2out.c (dwarf2out_early_finish): Likewise.
11089 * gimple-ssa-store-merging.c: Likewise.
11090 * ira-costs.c (record_operand_costs): Likewise.
11091 * tree-vect-loop.c (vectorizable_reduction): Likewise.
11092 * target.def (dispatch): Likewise.
11093 (validate_dims, gen_ccmp_first): Fix up duplicated word issue
11094 in documentation text.
11095 * doc/tm.texi: Regenerated.
11096 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up
11097 duplicated word issue in a comment.
11098 * config/i386/i386.c (ix86_test_loading_unspec): Likewise.
11099 * config/i386/i386-features.c (remove_partial_avx_dependency):
11101 * config/msp430/msp430.c (msp430_select_section): Likewise.
11102 * config/gcn/gcn-run.c (load_image): Likewise.
11103 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise.
11104 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise.
11105 * config/aarch64/falkor-tag-collision-avoidance.c
11106 (single_dest_per_chain): Likewise.
11107 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise.
11108 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise.
11109 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise.
11110 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant):
11112 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise.
11113 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise.
11114 * config/rs6000/rs6000-logue.c
11115 (rs6000_emit_probe_stack_range_stack_clash): Likewise.
11116 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise.
11117 Fix various other issues in the comment.
11119 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
11121 * config/arm/t-rmprofile: create new multilib for
11122 armv8.1-m.main+mve hard float and reuse v8-m.main ones for
11125 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11127 PR tree-optimization/94015
11128 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the
11129 function where EXP is address of the bytes being stored rather than
11130 the bytes themselves into count_nonzero_bytes_addr. Punt on zero
11131 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs.
11132 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before
11133 calling native_encode_expr if host or target doesn't have 8-bit
11134 chars. Formatting fixes.
11135 (count_nonzero_bytes_addr): New function.
11137 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11138 Mihail Ionescu <mihail.ionescu@arm.com>
11139 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11141 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define.
11142 (UNOP_SNONE_NONE_QUALIFIERS): Likewise.
11143 (UNOP_SNONE_IMM_QUALIFIERS): Likewise.
11144 (UNOP_UNONE_NONE_QUALIFIERS): Likewise.
11145 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise.
11146 (UNOP_UNONE_IMM_QUALIFIERS): Likewise.
11147 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro.
11148 (vmvnq_n_s32): Likewise.
11149 (vrev64q_s8): Likewise.
11150 (vrev64q_s16): Likewise.
11151 (vrev64q_s32): Likewise.
11152 (vcvtq_s16_f16): Likewise.
11153 (vcvtq_s32_f32): Likewise.
11154 (vrev64q_u8): Likewise.
11155 (vrev64q_u16): Likewise.
11156 (vrev64q_u32): Likewise.
11157 (vmvnq_n_u16): Likewise.
11158 (vmvnq_n_u32): Likewise.
11159 (vcvtq_u16_f16): Likewise.
11160 (vcvtq_u32_f32): Likewise.
11161 (__arm_vmvnq_n_s16): Define intrinsic.
11162 (__arm_vmvnq_n_s32): Likewise.
11163 (__arm_vrev64q_s8): Likewise.
11164 (__arm_vrev64q_s16): Likewise.
11165 (__arm_vrev64q_s32): Likewise.
11166 (__arm_vrev64q_u8): Likewise.
11167 (__arm_vrev64q_u16): Likewise.
11168 (__arm_vrev64q_u32): Likewise.
11169 (__arm_vmvnq_n_u16): Likewise.
11170 (__arm_vmvnq_n_u32): Likewise.
11171 (__arm_vcvtq_s16_f16): Likewise.
11172 (__arm_vcvtq_s32_f32): Likewise.
11173 (__arm_vcvtq_u16_f16): Likewise.
11174 (__arm_vcvtq_u32_f32): Likewise.
11175 (vrev64q): Define polymorphic variant.
11176 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
11177 (UNOP_SNONE_NONE): Likewise.
11178 (UNOP_SNONE_IMM): Likewise.
11179 (UNOP_UNONE_UNONE): Likewise.
11180 (UNOP_UNONE_NONE): Likewise.
11181 (UNOP_UNONE_IMM): Likewise.
11182 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern.
11183 (mve_vcvtq_from_f_<supf><mode>): Likewise.
11184 (mve_vmvnq_n_<supf><mode>): Likewise.
11186 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11187 Mihail Ionescu <mihail.ionescu@arm.com>
11188 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11190 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
11191 (UNOP_NONE_SNONE_QUALIFIERS): Likewise.
11192 (UNOP_NONE_UNONE_QUALIFIERS): Likewise.
11193 * config/arm/arm_mve.h (vrndxq_f16): Define macro.
11194 (vrndxq_f32): Likewise.
11195 (vrndq_f16) Likewise.
11196 (vrndq_f32): Likewise.
11197 (vrndpq_f16): Likewise.
11198 (vrndpq_f32): Likewise.
11199 (vrndnq_f16): Likewise.
11200 (vrndnq_f32): Likewise.
11201 (vrndmq_f16): Likewise.
11202 (vrndmq_f32): Likewise.
11203 (vrndaq_f16): Likewise.
11204 (vrndaq_f32): Likewise.
11205 (vrev64q_f16): Likewise.
11206 (vrev64q_f32): Likewise.
11207 (vnegq_f16): Likewise.
11208 (vnegq_f32): Likewise.
11209 (vdupq_n_f16): Likewise.
11210 (vdupq_n_f32): Likewise.
11211 (vabsq_f16): Likewise.
11212 (vabsq_f32): Likewise.
11213 (vrev32q_f16): Likewise.
11214 (vcvttq_f32_f16): Likewise.
11215 (vcvtbq_f32_f16): Likewise.
11216 (vcvtq_f16_s16): Likewise.
11217 (vcvtq_f32_s32): Likewise.
11218 (vcvtq_f16_u16): Likewise.
11219 (vcvtq_f32_u32): Likewise.
11220 (__arm_vrndxq_f16): Define intrinsic.
11221 (__arm_vrndxq_f32): Likewise.
11222 (__arm_vrndq_f16): Likewise.
11223 (__arm_vrndq_f32): Likewise.
11224 (__arm_vrndpq_f16): Likewise.
11225 (__arm_vrndpq_f32): Likewise.
11226 (__arm_vrndnq_f16): Likewise.
11227 (__arm_vrndnq_f32): Likewise.
11228 (__arm_vrndmq_f16): Likewise.
11229 (__arm_vrndmq_f32): Likewise.
11230 (__arm_vrndaq_f16): Likewise.
11231 (__arm_vrndaq_f32): Likewise.
11232 (__arm_vrev64q_f16): Likewise.
11233 (__arm_vrev64q_f32): Likewise.
11234 (__arm_vnegq_f16): Likewise.
11235 (__arm_vnegq_f32): Likewise.
11236 (__arm_vdupq_n_f16): Likewise.
11237 (__arm_vdupq_n_f32): Likewise.
11238 (__arm_vabsq_f16): Likewise.
11239 (__arm_vabsq_f32): Likewise.
11240 (__arm_vrev32q_f16): Likewise.
11241 (__arm_vcvttq_f32_f16): Likewise.
11242 (__arm_vcvtbq_f32_f16): Likewise.
11243 (__arm_vcvtq_f16_s16): Likewise.
11244 (__arm_vcvtq_f32_s32): Likewise.
11245 (__arm_vcvtq_f16_u16): Likewise.
11246 (__arm_vcvtq_f32_u32): Likewise.
11247 (vrndxq): Define polymorphic variants.
11249 (vrndpq): Likewise.
11250 (vrndnq): Likewise.
11251 (vrndmq): Likewise.
11252 (vrndaq): Likewise.
11253 (vrev64q): Likewise.
11256 (vrev32q): Likewise.
11257 (vcvtbq_f32): Likewise.
11258 (vcvttq_f32): Likewise.
11260 * config/arm/arm_mve_builtins.def (VAR2): Define.
11262 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
11263 (mve_vrndq_f<mode>): Likewise.
11264 (mve_vrndpq_f<mode>): Likewise.
11265 (mve_vrndnq_f<mode>): Likewise.
11266 (mve_vrndmq_f<mode>): Likewise.
11267 (mve_vrndaq_f<mode>): Likewise.
11268 (mve_vrev64q_f<mode>): Likewise.
11269 (mve_vnegq_f<mode>): Likewise.
11270 (mve_vdupq_n_f<mode>): Likewise.
11271 (mve_vabsq_f<mode>): Likewise.
11272 (mve_vrev32q_fv8hf): Likewise.
11273 (mve_vcvttq_f32_f16v4sf): Likewise.
11274 (mve_vcvtbq_f32_f16v4sf): Likewise.
11275 (mve_vcvtq_to_f_<supf><mode>): Likewise.
11277 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11278 Mihail Ionescu <mihail.ionescu@arm.com>
11279 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11281 * config/arm/arm-builtins.c (CF): Define mve_builtin_data.
11283 (ARM_BUILTIN_MVE_PATTERN_START): Define.
11284 (arm_init_mve_builtins): Define function.
11285 (arm_init_builtins): Add TARGET_HAVE_MVE check.
11286 (arm_expand_builtin_1): Check the range of fcode.
11287 (arm_expand_mve_builtin): Define function to expand MVE builtins.
11288 (arm_expand_builtin): Check the range of fcode.
11289 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point
11291 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace.
11292 (vst4q_s8): Define macro.
11293 (vst4q_s16): Likewise.
11294 (vst4q_s32): Likewise.
11295 (vst4q_u8): Likewise.
11296 (vst4q_u16): Likewise.
11297 (vst4q_u32): Likewise.
11298 (vst4q_f16): Likewise.
11299 (vst4q_f32): Likewise.
11300 (__arm_vst4q_s8): Define inline builtin.
11301 (__arm_vst4q_s16): Likewise.
11302 (__arm_vst4q_s32): Likewise.
11303 (__arm_vst4q_u8): Likewise.
11304 (__arm_vst4q_u16): Likewise.
11305 (__arm_vst4q_u32): Likewise.
11306 (__arm_vst4q_f16): Likewise.
11307 (__arm_vst4q_f32): Likewise.
11308 (__ARM_mve_typeid): Define macro with MVE types.
11309 (__ARM_mve_coerce): Define macro with _Generic feature.
11310 (vst4q): Define polymorphic variant for different vst4q builtins.
11311 * config/arm/arm_mve_builtins.def: New file.
11312 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI
11314 * config/arm/mve.md (MVE_VLD_ST): Define iterator.
11315 (unspec): Define unspec.
11316 (mve_vst4q<mode>): Define RTL pattern.
11317 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI
11319 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes
11321 (define_split): Allow OI mode split for MVE after reload.
11322 (define_split): Allow XI mode split for MVE after reload.
11323 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def.
11324 (arm-builtins.o): Likewise.
11326 2020-03-17 Christophe Lyon <christophe.lyon@linaro.org>
11328 * c-typeck.c (process_init_element): Handle constructor_type with
11329 type size represented by POLY_INT_CST.
11331 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11333 PR tree-optimization/94187
11334 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if
11335 nchars - offset < nbytes.
11337 PR middle-end/94189
11338 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would
11339 emit a warning if it was enabled and don't depend on TREE_NO_WARNING
11340 for code-generation.
11342 2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
11345 * lra-spills.c (remove_pseudos): Do not reuse insn alternative
11346 after changing memory subreg.
11348 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11349 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11351 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
11352 emulator calls for dobule precision arithmetic operations for MVE.
11354 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11355 Mihail Ionescu <mihail.ionescu@arm.com>
11356 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11358 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
11359 feature bit is on and -mfpu=auto is passed as compiler option, do not
11360 generate error on not finding any matching fpu. Because in this case
11361 fpu is not required.
11362 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
11363 enabled for MVE and also for all VFP extensions.
11364 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
11366 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
11367 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
11368 along with feature bits mve_float.
11369 (mve): Modify add options in armv8.1-m.main arch for MVE.
11370 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with
11372 * config/arm/arm.c (use_return_insn): Replace the
11373 check with TARGET_VFP_BASE.
11374 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
11376 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
11377 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
11379 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
11380 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
11382 (arm_compute_frame_layout): Likewise.
11383 (arm_save_coproc_regs): Likewise.
11384 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
11386 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
11387 with equivalent macro TARGET_VFP_BASE.
11388 (arm_expand_epilogue_apcs_frame): Likewise.
11389 (arm_expand_epilogue): Likewise.
11390 (arm_conditional_register_usage): Likewise.
11391 (arm_declare_function_name): Add check to skip printing .fpu directive
11392 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
11394 * config/arm/arm.h (TARGET_VFP_BASE): Define.
11395 * config/arm/arm.md (arch): Add "mve" to arch.
11396 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
11397 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
11398 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
11399 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR
11401 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
11402 to not allow for MVE.
11403 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
11405 (VUNSPEC_GET_FPSCR): Define.
11406 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
11407 instructions which move to general-purpose Register from Floating-point
11408 Special register and vice-versa.
11409 (thumb2_movhi_fp16): Likewise.
11410 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
11411 with MCR and MRC instructions which set and get Floating-point Status
11412 and Control Register (FPSCR).
11413 (movdi_vfp): Modify pattern to enable Single-precision scalar float move
11415 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
11416 float move patterns in MVE.
11417 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
11418 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
11419 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
11420 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
11421 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
11422 TARGET_VFP_BASE check.
11423 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
11424 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
11426 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
11427 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
11431 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11432 Mihail Ionescu <mihail.ionescu@arm.com>
11433 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11435 * config.gcc (arm_mve.h): Include mve intrinsics header file.
11436 * config/arm/aout.h (p0): Add new register name for MVE predicated
11438 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
11439 common to Neon and MVE.
11440 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
11441 (arm_init_simd_builtin_types): Disable poly types for MVE.
11442 (arm_init_neon_builtins): Move a check to arm_init_builtins function.
11443 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
11444 ARM_BUILTIN_NEON_LANE_CHECK.
11445 (mve_dereference_pointer): Add function.
11446 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
11448 (arm_expand_neon_builtin): Moved to arm_expand_builtin function.
11449 (arm_expand_builtin): Moved from arm_expand_neon_builtin function.
11450 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
11451 with floating point enabled.
11452 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
11453 simd_immediate_valid_for_move.
11454 (simd_immediate_valid_for_move): Renamed from
11455 neon_immediate_valid_for_move function.
11456 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
11457 error if vfpv2 feature bit is disabled and mve feature bit is also
11458 disabled for HARD_FLOAT_ABI.
11459 (use_return_insn): Check to not push VFP regs for MVE.
11460 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
11462 (aapcs_vfp_allocate_return_reg): Likewise.
11463 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
11464 address operand for MVE.
11465 (arm_rtx_costs_internal): MVE check to determine cost of rtx.
11466 (neon_valid_immediate): Rename to simd_valid_immediate.
11467 (simd_valid_immediate): Rename from neon_valid_immediate.
11468 (simd_valid_immediate): MVE check on size of vector is 128 bits.
11469 (neon_immediate_valid_for_move): Rename to
11470 simd_immediate_valid_for_move.
11471 (simd_immediate_valid_for_move): Rename from
11472 neon_immediate_valid_for_move.
11473 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
11475 (neon_make_constant): Modify call to neon_valid_immediate function.
11476 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
11478 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
11479 (arm_compute_frame_layout): Calculate space for saved VFP registers for
11481 (arm_save_coproc_regs): Save coproc registers for MVE.
11482 (arm_print_operand): Add case 'E' to print memory operands for MVE.
11483 (arm_print_operand_address): Check to print register number for MVE.
11484 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
11485 (arm_modes_tieable_p): Check to allow structure mode for MVE.
11486 (arm_regno_class): Add VPR_REGNUM check.
11487 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
11489 (arm_expand_epilogue): MVE check for enabling pop instructions in
11491 (arm_print_asm_arch_directives): Modify function to disable print of
11492 .arch_extension "mve" and "fp" for cases where MVE is enabled with
11494 (arm_vector_mode_supported_p): Check for modes available in MVE interger
11495 and MVE floating point.
11496 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
11498 (arm_conditional_register_usage): Enable usage of conditional regsiter
11500 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
11501 (arm_declare_function_name): Modify function to disable print of
11502 .arch_extension "mve" and "fp" for cases where MVE is enabled with
11504 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
11505 when target general registers are required.
11506 (TARGET_HAVE_MVE_FLOAT): Likewise.
11507 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
11509 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
11510 which indicate this is not available for across function calls.
11511 (FIRST_PSEUDO_REGISTER): Modify.
11512 (VALID_MVE_MODE): Define valid MVE mode.
11513 (VALID_MVE_SI_MODE): Define valid MVE SI mode.
11514 (VALID_MVE_SF_MODE): Define valid MVE SF mode.
11515 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
11516 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
11518 (IS_VPR_REGNUM): Macro to check for VPR_REG register.
11519 (REG_ALLOC_ORDER): Add VPR_REGNUM entry.
11520 (enum reg_class): Add VPR_REG entry.
11521 (REG_CLASS_NAMES): Add VPR_REG entry.
11522 * config/arm/arm.md (VPR_REGNUM): Define.
11523 (conds): Check is_mve_type attrbiute to differentiate "conditional" and
11524 "unconditional" instructions.
11525 (arm_movsf_soft_insn): Modify RTL to not allow for MVE.
11526 (movdf_soft_insn): Modify RTL to not allow for MVE.
11527 (vfp_pop_multiple_with_writeback): Enable for MVE.
11528 (include "mve.md"): Include mve.md file.
11529 * config/arm/arm_mve.h: Add MVE intrinsics head file.
11530 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
11531 for vector predicated operands.
11532 * config/arm/iterators.md (VNIM1): Define.
11533 (VNINOTM1): Define.
11534 (VHFBF_split): Define
11535 * config/arm/mve.md: New file.
11536 (mve_mov<mode>): Define RTL for move, store and load in MVE.
11537 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
11539 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with
11540 simd_immediate_valid_for_move.
11541 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
11542 is common to MVE and NEON to vec-common.md file.
11543 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
11544 * config/arm/predicates.md (vpr_register_operand): Define.
11545 * config/arm/t-arm: Add mve.md file.
11546 * config/arm/types.md (mve_move): Add MVE instructions mve_move to
11548 (mve_store): Add MVE instructions mve_store to attribute "type".
11549 (mve_load): Add MVE instructions mve_load to attribute "type".
11550 (is_mve_type): Define attribute.
11551 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
11552 standard move patterns in MVE along with NEON and IWMMXT with mode
11554 (mov<mode>): Modify RTL expand to support standard move patterns in NEON
11555 and IWMMXT with mode iterator V8HF.
11556 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in
11558 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
11559 simd_immediate_valid_for_move.
11562 2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
11565 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
11566 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
11568 * config/i386/predicates.md (ext_sse_reg_operand): Removed.
11570 2020-03-16 Jakub Jelinek <jakub@redhat.com>
11573 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
11576 PR tree-optimization/94166
11577 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
11578 as secondary comparison key.
11580 2020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com>
11582 PR tree-optimization/94125
11583 * tree-loop-distribution.c
11584 (loop_distribution::break_alias_scc_partitions): Update post order
11585 number for merged scc.
11587 2020-03-15 H.J. Lu <hongjiu.lu@intel.com>
11590 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
11592 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
11593 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
11594 and ext_sse_reg_operand check.
11596 2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
11598 * common.opt: Avoid redundancy in the help text.
11599 * config/arc/arc.opt: Likewise.
11600 * config/cr16/cr16.opt: Likewise.
11602 2020-03-14 Jakub Jelinek <jakub@redhat.com>
11604 PR middle-end/93566
11605 * tree-nested.c (convert_nonlocal_omp_clauses,
11606 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
11607 with C/C++ array sections.
11609 2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
11612 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
11613 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
11616 2020-03-14 Jakub Jelinek <jakub@redhat.com>
11618 * gimple-fold.c (gimple_fold_builtin_strncpy): Change
11619 "a an" to "an" in a comment.
11620 * hsa-common.h (is_a_helper): Likewise.
11621 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
11622 * config/arc/arc.c (arc600_corereg_hazard): Likewise.
11623 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.
11625 2020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com>
11628 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a
11629 64-bit value by 64 bits (UB).
11631 2020-03-13 Vladimir Makarov <vmakarov@redhat.com>
11633 PR rtl-optimization/92303
11634 * lra-spills.c (remove_pseudos): Try to simplify memory subreg.
11636 2020-03-13 Segher Boessenkool <segher@kernel.crashing.org>
11638 PR rtl-optimization/94148
11639 PR rtl-optimization/94042
11640 * df-core.c (BB_LAST_CHANGE_AGE): Delete.
11641 (df_worklist_propagate_forward): New parameter last_change_age, use
11642 that instead of bb->aux.
11643 (df_worklist_propagate_backward): Ditto.
11644 (df_worklist_dataflow_doublequeue): Use a local array last_change_age.
11646 2020-03-13 Richard Biener <rguenther@suse.de>
11648 PR tree-optimization/94163
11649 * tree-ssa-pre.c (create_expression_by_pieces): Check
11650 whether alignment would be zero.
11652 2020-03-13 Martin Liska <mliska@suse.cz>
11655 * lto-wrapper.c (run_gcc): Use concat for appending
11656 to collect_gcc_options.
11658 2020-03-13 Jakub Jelinek <jakub@redhat.com>
11661 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
11662 instead of GEN_INT.
11664 2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
11667 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
11668 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
11669 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
11670 TARGET_AVX512VL and ext_sse_reg_operand check.
11672 2020-03-13 Bu Le <bule1@huawei.com>
11675 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=)
11676 (-param=aarch64-double-recp-precision=): New options.
11677 * doc/invoke.texi: Document them.
11678 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them
11679 instead of hard-coding the choice of 1 for float and 2 for double.
11681 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
11683 PR rtl-optimization/94119
11684 * resource.h (clear_hashed_info_until_next_barrier): Declare.
11685 * resource.c (clear_hashed_info_until_next_barrier): New function.
11686 * reorg.c (add_to_delay_list): Fix formatting.
11687 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on
11688 the next instruction after removing a BARRIER.
11690 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
11692 PR middle-end/92071
11693 * expmed.c (store_integral_bit_field): For fields larger than a word,
11694 call extract_bit_field on the value if the mode is BLKmode. Remove
11695 specific path for big-endian targets and tidy things up a little bit.
11697 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
11699 PR rtl-optimization/90275
11700 * cse.c (cse_insn): Delete no-op register moves too.
11702 2020-03-12 Darius Galis <darius.galis@cyberthorstudios.com>
11704 * config/rx/rx.md (CTRLREG_CPEN): Remove.
11705 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support.
11707 2020-03-12 Richard Biener <rguenther@suse.de>
11709 PR tree-optimization/94103
11710 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type
11711 punning when the mode precision is not sufficient.
11713 2020-03-12 H.J. Lu <hongjiu.lu@intel.com>
11716 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
11717 MODE_V1DF and MODE_V2SF.
11718 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
11719 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
11722 2020-03-12 Jakub Jelinek <jakub@redhat.com>
11724 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
11725 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
11726 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
11727 * doc/tm.texi: Regenerated.
11729 PR tree-optimization/94130
11730 * tree-ssa-dse.c: Include gimplify.h.
11731 (increment_start_addr): If stmt has lhs, drop the lhs from call and
11732 set it after the call to the original value of the first argument.
11734 (decrement_count): Formatting fix.
11736 2020-03-11 Delia Burduv <delia.burduv@arm.com>
11738 * config/arm/arm-builtins.c
11739 (arm_init_simd_builtin_scalar_types): New.
11740 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type.
11741 (vld2q_bf16): Used new builtin type.
11742 (vld3_bf16): Used new builtin type.
11743 (vld3q_bf16): Used new builtin type.
11744 (vld4_bf16): Used new builtin type.
11745 (vld4q_bf16): Used new builtin type.
11746 (vld2_dup_bf16): Used new builtin type.
11747 (vld2q_dup_bf16): Used new builtin type.
11748 (vld3_dup_bf16): Used new builtin type.
11749 (vld3q_dup_bf16): Used new builtin type.
11750 (vld4_dup_bf16): Used new builtin type.
11751 (vld4q_dup_bf16): Used new builtin type.
11753 2020-03-11 Jakub Jelinek <jakub@redhat.com>
11756 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
11757 at the start to switch to data section. Don't print extra newline if
11758 .globl directive has not been emitted.
11760 2020-03-11 Richard Biener <rguenther@suse.de>
11762 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]):
11765 2020-03-11 Eric Botcazou <ebotcazou@adacore.com>
11767 PR middle-end/93961
11768 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields
11769 whose type is a qualified union.
11771 2020-03-11 Jakub Jelinek <jakub@redhat.com>
11774 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
11775 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
11778 * value-prof.c (dump_histogram_value): Use abs_hwi instead of
11780 (get_nth_most_common_value): Use abs_hwi instead of abs.
11782 PR middle-end/94111
11783 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
11784 is rvc_normal, otherwise use real_to_decimal to print the number to
11787 PR tree-optimization/94114
11788 * tree-loop-distribution.c (generate_memset_builtin): Call
11789 rewrite_to_non_trapping_overflow even on mem.
11790 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
11793 2020-03-10 Jeff Law <law@redhat.com>
11795 * config/bfin/bfin.md (movsi_insv): Add length attribute.
11797 2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
11800 * config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check
11801 NAN and SIGNED_ZEROR for smax/smin.
11803 2020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
11806 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
11807 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments.
11809 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
11811 * loop-iv.c (find_simple_exit): Make it static.
11812 * cfgloop.h: Remove the corresponding prototype.
11814 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
11816 * ddg.c (create_ddg): Fix intendation.
11817 (set_recurrence_length): Likewise.
11818 (create_ddg_all_sccs): Likewise.
11820 2020-03-10 Jakub Jelinek <jakub@redhat.com>
11823 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with
11824 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len
11827 2020-03-09 Jason Merrill <jason@redhat.com>
11829 * gdbinit.in (pgs): Fix typo in documentation.
11831 2020-03-09 Vladimir Makarov <vmakarov@redhat.com>
11835 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
11837 PR rtl-optimization/93564
11838 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
11839 do not honor reg alloc order.
11841 2020-03-09 Andrew Pinski <apinski@marvell.com>
11843 PR inline-asm/94095
11844 * doc/extend.texi (x86 Operand Modifiers): Fix column
11847 2020-03-09 Martin Liska <mliska@suse.cz>
11850 * config/rs6000/rs6000.c (rs6000_option_override_internal):
11851 Remove set of str_align_loops and str_align_jumps as these
11852 should be set in previous 2 conditions in the function.
11854 2020-03-09 Jakub Jelinek <jakub@redhat.com>
11856 PR rtl-optimization/94045
11857 * params.opt (-param=max-find-base-term-values=): New option.
11858 * alias.c (find_base_term): Add cut-off for number of visited VALUEs
11859 in a single toplevel find_base_term call.
11861 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
11864 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define.
11865 * config/aarch64/aarch64-simd.md
11866 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul.
11867 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise.
11868 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics.
11869 * config/aarch64/arm_neon.h:
11870 (vmlal_lane_s16): Expand using intrinsics rather than inline asm.
11871 (vmlal_lane_u16): Likewise.
11872 (vmlal_lane_s32): Likewise.
11873 (vmlal_lane_u32): Likewise.
11874 (vmlal_laneq_s16): Likewise.
11875 (vmlal_laneq_u16): Likewise.
11876 (vmlal_laneq_s32): Likewise.
11877 (vmlal_laneq_u32): Likewise.
11878 (vmull_lane_s16): Likewise.
11879 (vmull_lane_u16): Likewise.
11880 (vmull_lane_s32): Likewise.
11881 (vmull_lane_u32): Likewise.
11882 (vmull_laneq_s16): Likewise.
11883 (vmull_laneq_u16): Likewise.
11884 (vmull_laneq_s32): Likewise.
11885 (vmull_laneq_u32): Likewise.
11886 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul.
11889 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
11891 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
11892 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
11893 (aarch64_mls_elt<mode>): Likewise.
11894 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
11895 (aarch64_fma4_elt<mode>): Likewise.
11896 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
11897 (aarch64_fma4_elt_to_64v2df): Likewise.
11898 (aarch64_fnma4_elt<mode>): Likewise.
11899 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
11900 (aarch64_fnma4_elt_to_64v2df): Likewise.
11902 2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
11904 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
11905 Specify movprfx attribute.
11906 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
11908 2020-03-06 David Edelsohn <dje.gcc@gmail.com>
11911 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for
11913 (TARGET_NO_FP_IN_TOC): Same.
11914 * config/rs6000/aix71.h: Same.
11915 * config/rs6000/aix72.h: Same.
11917 2020-03-06 Andrew Pinski <apinski@marvell.com>
11918 Jeff Law <law@redhat.com>
11920 PR rtl-optimization/93996
11921 * haifa-sched.c (remove_notes): Be more careful when adding
11924 2020-03-06 Delia Burduv <delia.burduv@arm.com>
11926 * config/arm/arm_neon.h (vld2_bf16): New.
11932 (vld2_dup_bf16): New.
11933 (vld2q_dup_bf16): New.
11934 (vld3_dup_bf16): New.
11935 (vld3q_dup_bf16): New.
11936 (vld4_dup_bf16): New.
11937 (vld4q_dup_bf16): New.
11938 * config/arm/arm_neon_builtins.def
11939 (vld2): Changed to VAR13 and added v4bf, v8bf
11940 (vld2_dup): Changed to VAR8 and added v4bf, v8bf
11941 (vld3): Changed to VAR13 and added v4bf, v8bf
11942 (vld3_dup): Changed to VAR8 and added v4bf, v8bf
11943 (vld4): Changed to VAR13 and added v4bf, v8bf
11944 (vld4_dup): Changed to VAR8 and added v4bf, v8bf
11945 * config/arm/iterators.md (VDXBF2): New iterator.
11946 *config/arm/neon.md (neon_vld2): Use new iterators.
11947 (neon_vld2_dup<mode): Use new iterators.
11948 (neon_vld3<mode>): Likewise.
11949 (neon_vld3qa<mode>): Likewise.
11950 (neon_vld3qb<mode>): Likewise.
11951 (neon_vld3_dup<mode>): Likewise.
11952 (neon_vld4<mode>): Likewise.
11953 (neon_vld4qa<mode>): Likewise.
11954 (neon_vld4qb<mode>): Likewise.
11955 (neon_vld4_dup<mode>): Likewise.
11956 (neon_vld2_dupv8bf): New.
11957 (neon_vld3_dupv8bf): Likewise.
11958 (neon_vld4_dupv8bf): Likewise.
11960 2020-03-06 Delia Burduv <delia.burduv@arm.com>
11962 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef.
11963 (bfloat16x8x2_t): New typedef.
11964 (bfloat16x4x3_t): New typedef.
11965 (bfloat16x8x3_t): New typedef.
11966 (bfloat16x4x4_t): New typedef.
11967 (bfloat16x8x4_t): New typedef.
11974 * config/arm/arm-builtins.c (v2bf_UP): Define.
11976 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype.
11977 * config/arm/arm-modes.def (V2BF): New mode.
11978 * config/arm/arm-simd-builtin-types.def
11979 (Bfloat16x2_t): New entry.
11980 * config/arm/arm_neon_builtins.def
11981 (vst2): Changed to VAR13 and added v4bf, v8bf
11982 (vst3): Changed to VAR13 and added v4bf, v8bf
11983 (vst4): Changed to VAR13 and added v4bf, v8bf
11984 * config/arm/iterators.md (VDXBF): New iterator.
11985 (VQ2BF): New iterator.
11986 *config/arm/neon.md (neon_vst2<mode>): Used new iterators.
11987 (neon_vst2<mode>): Used new iterators.
11988 (neon_vst3<mode>): Used new iterators.
11989 (neon_vst3<mode>): Used new iterators.
11990 (neon_vst3qa<mode>): Used new iterators.
11991 (neon_vst3qb<mode>): Used new iterators.
11992 (neon_vst4<mode>): Used new iterators.
11993 (neon_vst4<mode>): Used new iterators.
11994 (neon_vst4qa<mode>): Used new iterators.
11995 (neon_vst4qb<mode>): Used new iterators.
11997 2020-03-06 Delia Burduv <delia.burduv@arm.com>
11999 * config/aarch64/aarch64-simd-builtins.def
12000 (bfcvtn): New built-in function.
12001 (bfcvtn_q): New built-in function.
12002 (bfcvtn2): New built-in function.
12003 (bfcvt): New built-in function.
12004 * config/aarch64/aarch64-simd.md
12005 (aarch64_bfcvtn<q><mode>): New pattern.
12006 (aarch64_bfcvtn2v8bf): New pattern.
12007 (aarch64_bfcvtbf): New pattern.
12008 * config/aarch64/arm_bf16.h (float32_t): New typedef.
12009 (vcvth_bf16_f32): New intrinsic.
12010 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic.
12011 (vcvtq_low_bf16_f32): New intrinsic.
12012 (vcvtq_high_bf16_f32): New intrinsic.
12013 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator.
12014 (UNSPEC_BFCVTN): New UNSPEC.
12015 (UNSPEC_BFCVTN2): New UNSPEC.
12016 (UNSPEC_BFCVT): New UNSPEC.
12017 * config/arm/types.md (bf_cvt): New type.
12019 2020-03-06 Andreas Krebbel <krebbel@linux.ibm.com>
12021 * config/s390/s390.md ("tabort"): Get rid of two consecutive
12022 blanks in format string.
12024 2020-03-05 H.J. Lu <hongjiu.lu@intel.com>
12028 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype.
12029 * config/i386/i386.c (ix86_get_ssemov): New function.
12030 (ix86_output_ssemov): Likewise.
12031 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call
12032 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL
12034 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV.
12035 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV.
12036 Remove ext_sse_reg_operand and TARGET_AVX512VL check.
12037 (*movti_internal): Likewise.
12038 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV.
12040 2020-03-05 Jeff Law <law@redhat.com>
12042 PR tree-optimization/91890
12043 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument.
12044 Use gimple_or_expr_nonartificial_location.
12045 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds.
12046 Use gimple_or_expr_nonartificial_location.
12047 * gimple.c (gimple_or_expr_nonartificial_location): New function.
12048 * gimple.h (gimple_or_expr_nonartificial_location): Declare it.
12049 * tree-ssa-strlen.c (maybe_warn_overflow): Use
12050 gimple_or_expr_nonartificial_location.
12051 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise.
12052 (maybe_warn_pointless_strcmp): Likewise.
12054 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12057 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
12058 SRC and MASK arguments to __m128 from __m128d.
12059 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
12061 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
12063 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
12064 argument to __m128i from __m128d.
12065 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from
12067 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
12068 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from
12071 2020-03-05 Delia Burduv <delia.burduv@arm.com>
12073 * config/arm/arm_neon.h (vbfmmlaq_f32): New.
12074 (vbfmlalbq_f32): New.
12075 (vbfmlaltq_f32): New.
12076 (vbfmlalbq_lane_f32): New.
12077 (vbfmlaltq_lane_f32): New.
12078 (vbfmlalbq_laneq_f32): New.
12079 (vbfmlaltq_laneq_f32): New.
12080 * config/arm/arm_neon_builtins.def (vmmla): New.
12085 (vfmab_laneq): New.
12086 (vfmat_laneq): New.
12087 * config/arm/iterators.md (BF_MA): New int iterator.
12088 (bt): New int attribute.
12089 (VQXBF): Copy of VQX with V8BF.
12090 * config/arm/neon.md (neon_vmmlav8bf): New insn.
12091 (neon_vfma<bt>v8bf): New insn.
12092 (neon_vfma<bt>_lanev8bf): New insn.
12093 (neon_vfma<bt>_laneqv8bf): New expand.
12094 (neon_vget_high<mode>): Changed iterator to VQXBF.
12095 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC.
12096 (UNSPEC_BFMAB): New UNSPEC.
12097 (UNSPEC_BFMAT): New UNSPEC.
12099 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12101 PR middle-end/93399
12102 * tree-pretty-print.h (pretty_print_string): Declare.
12103 * tree-pretty-print.c (pretty_print_string): Remove forward
12104 declaration, no longer static. Change nbytes parameter type
12105 from unsigned to size_t.
12106 * print-rtl.c (print_value) <case CONST_STRING>: Use
12107 pretty_print_string and for shrink way too long strings.
12109 2020-03-05 Richard Biener <rguenther@suse.de>
12110 Jakub Jelinek <jakub@redhat.com>
12112 PR tree-optimization/93582
12113 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR
12114 last operand as signed when looking for memset offset. Formatting
12117 2020-03-04 Andrew Pinski <apinski@marvell.com>
12120 * value-prof.c (dump_histogram_value): Use std::abs.
12122 2020-03-04 Martin Sebor <msebor@redhat.com>
12124 PR tree-optimization/93986
12125 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int
12126 operands to the same precision widest_int to avoid ICEs.
12128 2020-03-04 Bill Schmidt <wschmidt@linux.ibm.com>
12131 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define.
12132 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry
12133 for OPTION_MASK_ALTIVEC.
12135 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12137 * config.gcc: Include the glibc-stdint.h header for zTPF.
12139 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12141 * config/s390/s390.c (s390_secondary_memory_needed): Disallow
12142 direct FPR-GPR copies.
12143 (s390_register_info_gprtofpr): Disallow GPR content to be saved in
12146 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12148 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new
12149 operands to the prologue_tpf expander.
12150 (s390_emit_epilogue): Likewise.
12151 (s390_option_override_internal): Do error checking and setup for
12153 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK)
12154 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET)
12155 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET)
12156 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions.
12157 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new
12158 operands for the check flag and the branch target.
12159 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check")
12160 ("mtpf-trace-hook-prologue-target")
12161 ("mtpf-trace-hook-epilogue-check")
12162 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New
12164 * doc/invoke.texi: Document -mtpf-trace-skip option. The other
12165 options are for debugging purposes and will not be documented
12168 2020-03-04 Jakub Jelinek <jakub@redhat.com>
12171 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
12173 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti
12174 argument. Change pd argument so that it can be modified. Turn
12175 constant non-CONSTRUCTOR store into non-constant if it is too large.
12176 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid
12178 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust
12181 2020-02-04 Richard Biener <rguenther@suse.de>
12183 PR tree-optimization/93964
12184 * graphite-isl-ast-to-gimple.c
12185 (gcc_expression_from_isl_ast_expr_id): Add intermediate
12186 conversion for pointer to integer converts.
12187 * graphite-scop-detection.c (assign_parameter_index_in_region):
12190 2020-03-04 Martin Liska <mliska@suse.cz>
12194 * doc/invoke.texi: Clarify --help=language and --help=common
12197 2020-03-04 Jakub Jelinek <jakub@redhat.com>
12199 PR tree-optimization/94001
12200 * tree-tailcall.c (process_assignment): Before comparing op1 to
12201 *ass_var, verify *ass_var is non-NULL.
12203 2020-03-04 Kito Cheng <kito.cheng@sifive.com>
12206 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
12209 2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
12211 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
12212 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
12213 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
12214 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
12215 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
12216 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
12217 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
12218 (V_bf_low, V_bf_cvt_m): New mode attributes.
12219 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
12220 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
12221 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
12222 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
12223 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
12225 2020-03-03 Jakub Jelinek <jakub@redhat.com>
12227 PR tree-optimization/93582
12228 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument.
12229 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result
12230 members, initialize them in the constructor and if mask is non-NULL,
12231 artificially push_partial_def {} for the portions of the mask that
12233 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to
12234 val and return (void *)-1. Formatting fix.
12235 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization.
12237 (vn_reference_lookup): Add mask argument. If non-NULL, don't call
12238 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return
12240 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST
12242 (visit_stmt): Formatting fix.
12244 2020-03-03 Richard Biener <rguenther@suse.de>
12246 PR tree-optimization/93946
12247 * alias.h (refs_same_for_tbaa_p): Declare.
12248 * alias.c (refs_same_for_tbaa_p): New function.
12249 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return
12251 * tree-ssa-scopedtables.h
12252 (avail_exprs_stack::lookup_avail_expr): Add output argument
12253 giving access to the hashtable entry.
12254 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
12256 * tree-ssa-dom.c: Include alias.h.
12257 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before
12258 removing redundant store.
12259 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member.
12260 (ao_ref_init_from_vn_reference): Adjust prototype.
12261 (vn_reference_lookup_pieces): Likewise.
12262 (vn_reference_insert_pieces): Likewise.
12263 * tree-ssa-sccvn.c: Track base alias set in addition to alias
12265 (eliminate_dom_walker::eliminate_stmt): Also check base alias
12266 set when removing redundant stores.
12267 (visit_reference_op_store): Likewise.
12268 * dse.c (record_store): Adjust valdity check for redundant
12271 2020-03-03 Jakub Jelinek <jakub@redhat.com>
12274 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder.
12276 PR rtl-optimization/94002
12277 * explow.c (plus_constant): Punt if cst has VOIDmode and
12278 get_pool_mode is different from mode.
12280 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12282 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an
12283 address has an offset which fits the scalling constraint for a
12284 load/store operation.
12285 (legitimate_scaled_address_p): Update use
12286 leigitimate_small_data_address_p.
12287 (arc_print_operand): Likewise.
12288 (arc_legitimate_address_p): Likewise.
12289 (legitimate_small_data_address_p): Likewise.
12291 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12293 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate.
12294 (fnmasf4_fpu): Likewise.
12296 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12298 * config/arc/arc.md (adddi3): Early expand the 64bit operation into
12300 (subdi3): Likewise.
12301 (adddi3_i): Remove pattern.
12302 (subdi3_i): Likewise.
12304 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12306 * config/arc/arc.md (eh_return): Add length info.
12308 2020-03-02 David Malcolm <dmalcolm@redhat.com>
12310 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New.
12312 2020-03-02 David Malcolm <dmalcolm@redhat.com>
12314 * doc/invoke.texi (Static Analyzer Options): Add
12315 -Wanalyzer-stale-setjmp-buffer to the list of options enabled
12318 2020-03-02 Uroš Bizjak <ubizjak@gmail.com>
12321 * config/i386/i386.md (movstrict<mode>): Allow only
12322 registers with VALID_INT_MODE_P modes.
12324 2020-03-02 Andrew Stubbs <ams@codesourcery.com>
12326 * config/gcn/gcn-valu.md (dpp_move<mode>): New.
12327 (reduc_insn): Use 'U' and 'B' operand codes.
12328 (reduc_<reduc_op>_scal_<mode>): Allow all types.
12329 (reduc_<reduc_op>_scal_v64di): Delete.
12330 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types.
12331 (*plus_carry_dpp_shr_v64si): Change to ...
12332 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types.
12333 (mov_from_lane63_v64di): Change to ...
12334 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes.
12335 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size.
12336 Support UNSPEC_MOV_DPP_SHR output formats.
12337 (gcn_expand_reduc_scalar): Add "use_moves" reductions.
12338 Add "use_extends" reductions.
12339 (print_operand_address): Add 'I' and 'U' codes.
12340 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
12342 2020-03-02 Martin Liska <mliska@suse.cz>
12344 * lto-wrapper.c: Fix typo in comment about
12345 C++ standard version.
12347 2020-03-01 Martin Sebor <msebor@redhat.com>
12350 * calls.c (init_attr_rdwr_indices): Correctly handle attribute.
12352 2020-03-01 Martin Sebor <msebor@redhat.com>
12354 PR middle-end/93829
12355 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that
12356 of a pointer in the outermost ADDR_EXPRs.
12358 2020-02-28 Jeff Law <law@redhat.com>
12360 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19.
12361 * config/v850/v850.c (v850_asm_trampoline_template): Update
12364 2020-02-28 Michael Meissner <meissner@linux.ibm.com>
12367 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var):
12370 2020-02-28 Martin Liska <mliska@suse.cz>
12373 * configure.ac: Improve detection of ld_date by requiring
12374 either two dashes or none.
12375 * configure: Regenerate.
12377 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
12379 PR rtl-optimization/93564
12380 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
12381 do not honor reg alloc order.
12383 2020-02-27 Joel Hutton <Joel.Hutton@arm.com>
12386 * config/aarch64/aarch64.c (aarch64_override_options): Fix
12387 misleading warning string.
12389 2020-02-27 Martin Sebor <msebor@redhat.com>
12391 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo.
12393 2020-02-27 Michael Meissner <meissner@linux.ibm.com>
12396 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
12397 Split the insn into two parts. This insn only does variable
12398 extract from a register.
12399 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
12400 variable extract from memory.
12401 (vsx_extract_v4sf_var): Split the insn into two parts. This insn
12402 only does variable extract from a register.
12403 (vsx_extract_v4sf_var_load): New insn, do variable extract from
12405 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
12406 into two parts. This insn only does variable extract from a
12408 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
12409 do variable extract from memory.
12411 2020-02-27 Martin Jambor <mjambor@suse.cz>
12412 Feng Xue <fxue@os.amperecomputing.com>
12415 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with
12416 new function calls_same_node_or_its_all_contexts_clone_p.
12417 (cgraph_edge_brings_value_p): Use it.
12418 (cgraph_edge_brings_value_p): Likewise.
12419 (self_recursive_pass_through_p): Return false if caller is a clone.
12420 (self_recursive_agg_pass_through_p): Likewise.
12422 2020-02-27 Jan Hubicka <hubicka@ucw.cz>
12424 PR middle-end/92152
12425 * alias.c (ends_tbaa_access_path_p): Break out from ...
12426 (component_uses_parent_alias_set_from): ... here.
12427 * alias.h (ends_tbaa_access_path_p): Declare.
12428 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...;
12429 handle trailing arrays past end of tbaa access path.
12430 (aliasing_component_refs_p): ... here; likewise.
12431 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access
12432 path; disambiguate also past end of it.
12433 (nonoverlapping_component_refs_p): Use only TBAA segment of the access
12436 2020-02-27 Mihail Ionescu <mihail.ionescu@arm.com>
12438 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the
12439 beginning of the file.
12440 (vcreate_bf16, vcombine_bf16): New.
12441 (vdup_n_bf16, vdupq_n_bf16): New.
12442 (vdup_lane_bf16, vdup_laneq_bf16): New.
12443 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
12444 (vduph_lane_bf16, vduph_laneq_bf16): New.
12445 (vset_lane_bf16, vsetq_lane_bf16): New.
12446 (vget_lane_bf16, vgetq_lane_bf16): New.
12447 (vget_high_bf16, vget_low_bf16): New.
12448 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
12449 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
12450 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
12451 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
12452 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
12453 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
12454 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
12455 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
12456 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
12457 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
12458 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New.
12459 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
12460 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
12461 (vreinterpretq_bf16_p128): New.
12462 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
12463 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
12464 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
12465 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
12466 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
12467 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
12468 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
12469 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
12470 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
12471 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
12472 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
12473 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
12474 (vreinterpretq_p128_bf16): New.
12475 * config/arm/arm_neon_builtins.def (VDX): Add V4BF.
12476 (V_elem): Likewise.
12477 (V_elem_l): Likewise.
12478 (VD_LANE): Likewise.
12480 (V_DOUBLE): Likewise.
12481 (VDQX): Add V4BF and V8BF.
12482 (V_two_elem, V_three_elem, V_four_elem): Likewise.
12484 (V_HALF): Likewise.
12485 (V_double_vector_mode): Likewise.
12486 (V_cmp_result): Likewise.
12487 (V_uf_sclr): Likewise.
12488 (V_sz_elem): Likewise.
12489 (Is_d_reg): Likewise.
12490 (V_mode_nunits): Likewise.
12491 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16.
12493 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
12495 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator.
12496 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE.
12497 (<expander><mode>3<exec>): Likewise.
12498 (<expander><mode>3): New.
12499 (v<expander><mode>3): New.
12500 (<expander><mode>3): New.
12501 (<expander><mode>3<exec>): Rename to ...
12502 (<expander>v64si3<exec>): ... this, and change modes to V64SI.
12503 * config/gcn/gcn.md (mnemonic): Use '%B' for not.
12505 2020-02-27 Alexandre Oliva <oliva@adacore.com>
12507 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave
12510 2020-02-27 Richard Biener <rguenther@suse.de>
12512 PR tree-optimization/93508
12513 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like
12514 non-_CHK variants. Valueize their length arguments.
12516 2020-02-27 Richard Biener <rguenther@suse.de>
12518 PR tree-optimization/93953
12519 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference
12520 to the hash-map entry.
12522 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
12524 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
12526 2020-02-27 Mark Williams <mwilliams@fb.com>
12528 * dwarf2out.c (file_name_acquire): Call remap_debug_filename.
12529 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map,
12530 -ffile-prefix-map and -fmacro-prefix-map.
12531 * lto-streamer-out.c: Include file-prefix-map.h.
12532 (lto_output_location): Remap the file part of locations.
12534 2020-02-27 Jakub Jelinek <jakub@redhat.com>
12537 * gimplify.c (gimplify_init_constructor): Don't promote readonly
12538 DECL_REGISTER variables to TREE_STATIC.
12540 PR tree-optimization/93582
12541 PR tree-optimization/93945
12542 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with
12543 non-zero INTEGER_CST second argument and ref->offset or ref->size
12544 not a multiple of BITS_PER_UNIT.
12546 2020-02-27 Jonathan Wakely <jwakely@redhat.com>
12548 * doc/install.texi (Binaries): Update description of BullFreeware.
12550 2020-02-26 Sandra Loosemore <sandra@codesourcery.com>
12554 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in
12555 C++ Language Options, Warning Options, and Static Analyzer
12556 Options lists. Document negative form of options enabled by
12557 default. Move some things around to more accurately sort
12558 warnings by category.
12559 (C++ Dialect Options, Warning Options, Static Analyzer
12560 Options): Document negative form of options when enabled by
12561 default. Move some things around to more accurately sort
12562 warnings by category. Add some missing index entries.
12563 Light copy-editing.
12565 2020-02-26 Carl Love <cel@us.ibm.com>
12568 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on
12569 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only
12570 for the vector unsigned short arguments. It is also listed as the
12571 name of the built-in for arguments vector unsigned short,
12572 vector unsigned int and vector unsigned long long built-ins. The
12573 name of the builtins for these arguments should be:
12574 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and
12575 __builtin_crypto_vpmsumd respectively.
12577 2020-02-26 Richard Biener <rguenther@suse.de>
12579 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count
12580 and load permutation.
12582 2020-02-26 Richard Sandiford <richard.sandiford@arm.com>
12584 PR middle-end/93843
12585 * optabs-tree.c (supportable_convert_operation): Reject types with
12588 2020-02-26 David Malcolm <dmalcolm@redhat.com>
12590 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o.
12592 2020-02-26 Jakub Jelinek <jakub@redhat.com>
12594 PR tree-optimization/93820
12595 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE
12596 argument to ALL_INTEGER_CST_P boolean.
12597 (imm_store_chain_info::try_coalesce_bswap): Adjust caller.
12598 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle
12599 adjacent INTEGER_CST store into merged_store->only_constants like
12602 2020-02-25 Jakub Jelinek <jakub@redhat.com>
12605 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity
12607 * cfghooks.c (verify_flow_info): Likewise.
12608 * predict.c (combine_predictions_for_bb): Likewise.
12609 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo,
12610 sucessor -> successor.
12611 (find_traces_1_round): Fix comment typo, destinarion -> destination.
12612 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors ->
12614 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump
12615 message typo, sucessors -> successors.
12617 2020-02-25 Martin Sebor <msebor@redhat.com>
12619 * doc/extend.texi (attribute access): Correct an example.
12621 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
12623 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
12625 (aarch64_init_simd_builtin_scalar_types): Register simd_bf.
12626 (VAR15, VAR16): New.
12627 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
12628 (VD): Enable for V4BF.
12630 (VQ): Enable for V8BF.
12632 (VQ_NO2E): Likewise.
12633 (VDBL, Vdbl): Add V4BF.
12634 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
12635 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
12636 (bfloat16x8x2_t): Likewise.
12637 (bfloat16x4x3_t): Likewise.
12638 (bfloat16x8x3_t): Likewise.
12639 (bfloat16x4x4_t): Likewise.
12640 (bfloat16x8x4_t): Likewise.
12641 (vcombine_bf16): New.
12642 (vld1_bf16, vld1_bf16_x2): New.
12643 (vld1_bf16_x3, vld1_bf16_x4): New.
12644 (vld1q_bf16, vld1q_bf16_x2): New.
12645 (vld1q_bf16_x3, vld1q_bf16_x4): New.
12646 (vld1_lane_bf16): New.
12647 (vld1q_lane_bf16): New.
12648 (vld1_dup_bf16): New.
12649 (vld1q_dup_bf16): New.
12652 (vld2_dup_bf16): New.
12653 (vld2q_dup_bf16): New.
12656 (vld3_dup_bf16): New.
12657 (vld3q_dup_bf16): New.
12660 (vld4_dup_bf16): New.
12661 (vld4q_dup_bf16): New.
12662 (vst1_bf16, vst1_bf16_x2): New.
12663 (vst1_bf16_x3, vst1_bf16_x4): New.
12664 (vst1q_bf16, vst1q_bf16_x2): New.
12665 (vst1q_bf16_x3, vst1q_bf16_x4): New.
12666 (vst1_lane_bf16): New.
12667 (vst1q_lane_bf16): New.
12675 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
12677 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
12678 (VALL_F16): Likewise.
12679 (VALLDI_F16): Likewise.
12681 (Vetype): Likewise.
12682 (vswap_width_name): Likewise.
12683 (VSWAP_WIDTH): Likewise.
12687 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New.
12688 (vget_lane_bf16, vgetq_lane_bf16): New.
12689 (vcreate_bf16): New.
12690 (vdup_n_bf16, vdupq_n_bf16): New.
12691 (vdup_lane_bf16, vdup_laneq_bf16): New.
12692 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
12693 (vduph_lane_bf16, vduph_laneq_bf16): New.
12694 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
12695 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
12696 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
12697 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
12698 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
12699 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
12700 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
12701 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
12702 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
12703 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
12704 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New
12705 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New
12706 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
12707 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
12708 (vreinterpretq_bf16_p128): New.
12709 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
12710 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
12711 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
12712 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
12713 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
12714 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
12715 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
12716 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
12717 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
12718 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
12719 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
12720 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
12721 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New.
12722 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New.
12723 (vreinterpretq_p128_bf16): New.
12725 2020-02-25 Dennis Zhang <dennis.zhang@arm.com>
12727 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New
12728 (vbfdot_lane_f32, vbfdotq_laneq_f32): New.
12729 (vbfdot_laneq_f32, vbfdotq_lane_f32): New.
12730 * config/arm/arm_neon_builtins.def (vbfdot): New entry.
12731 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise.
12732 * config/arm/iterators.md (VSF2BF): New attribute.
12733 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry.
12734 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise.
12735 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise.
12737 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org>
12739 * config/arm/arm.md (required_for_purecode): New attribute.
12740 (enabled): Handle required_for_purecode.
12741 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to
12742 work with -mpure-code.
12744 2020-02-25 Jakub Jelinek <jakub@redhat.com>
12746 PR rtl-optimization/93908
12747 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src
12750 2019-02-25 Eric Botcazou <ebotcazou@adacore.com>
12752 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode.
12754 2020-02-25 Roman Zhuykov <zhroma@ispras.ru>
12756 * doc/install.texi (--enable-checking): Adjust wording.
12758 2020-02-25 Richard Biener <rguenther@suse.de>
12760 PR tree-optimization/93868
12761 * tree-vect-slp.c (slp_copy_subtree): New function.
12762 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before
12763 re-arranging stmts in it.
12765 2020-02-25 Jakub Jelinek <jakub@redhat.com>
12767 PR middle-end/93874
12768 * passes.c (pass_manager::dump_passes): Create a cgraph node for the
12769 dummy function and remove it at the end.
12771 PR translation/93864
12772 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo
12773 paramter -> parameter.
12774 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise.
12775 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise.
12777 2020-02-24 Roman Zhuykov <zhroma@ispras.ru>
12779 * doc/install.texi (--enable-checking): Properly document current
12781 (--enable-stage1-checking): Minor clarification about bootstrap.
12783 2020-02-24 David Malcolm <dmalcolm@redhat.com>
12786 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that
12787 -fanalyzer-checker=taint is also required.
12788 (-fanalyzer-checker=): Note that providing this option enables the
12789 given checker, and doing so may be required for checkers that are
12790 disabled by default.
12792 2020-02-24 David Malcolm <dmalcolm@redhat.com>
12794 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows
12795 significant control flow events; add a "3" which shows all
12796 control flow events; the old "3" becomes "4".
12798 2020-02-24 Jakub Jelinek <jakub@redhat.com>
12800 PR tree-optimization/93582
12801 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider
12802 pd.offset and pd.size to be counted in bits rather than bytes, add
12803 support for maxsizei that is not a multiple of BITS_PER_UNIT and
12804 handle bitfield stores and loads.
12805 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with
12806 uncomparable quantities - bytes vs. bits. Allow push_partial_def
12807 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust
12808 pd.offset/pd.size to be counted in bits rather than bytes.
12809 Formatting fix. Rename shadowed len variable to buflen.
12811 2020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
12812 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org>
12815 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function.
12816 (driver::main): Call putenv_COLLECT_AS_OPTIONS.
12817 * opts-common.c (parse_options_from_collect_gcc_options): New function.
12818 (prepend_xassembler_to_collect_as_options): Likewise.
12819 * opts.h (parse_options_from_collect_gcc_options): Declare prototype.
12820 (prepend_xassembler_to_collect_as_options): Likewise.
12821 * lto-opts.c (lto_write_options): Stream assembler options
12822 in COLLECT_AS_OPTIONS.
12823 * lto-wrapper.c (xassembler_options_error): New static variable.
12824 (get_options_from_collect_gcc_options): Move parsing options code to
12825 parse_options_from_collect_gcc_options and call it.
12826 (merge_and_complain): Validate -Xassembler options.
12827 (append_compiler_options): Handle OPT_Xassembler.
12828 (run_gcc): Append command line -Xassembler options to
12829 collect_gcc_options.
12830 * doc/invoke.texi: Add documentation about using Xassembler
12833 2020-02-24 Kito Cheng <kito.cheng@sifive.com>
12835 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen
12837 (riscv_rtx_costs): Update cost model for LTGT.
12839 2020-02-23 Vladimir Makarov <vmakarov@redhat.com>
12841 PR rtl-optimization/93564
12842 * ira-color.c (struct update_cost_queue_elem): New member start.
12843 (queue_update_cost, get_next_update_cost): Add new arg start.
12844 (allocnos_conflict_p): New function.
12845 (update_costs_from_allocno): Add new arg conflict_cost_update_p.
12846 Add checking conflicts with allocnos_conflict_p.
12847 (update_costs_from_prefs, restore_costs_from_copies): Adjust
12848 update_costs_from_allocno calls.
12849 (update_conflict_hard_regno_costs): Add checking conflicts with
12850 allocnos_conflict_p. Adjust calls of queue_update_cost and
12851 get_next_update_cost.
12852 (assign_hard_reg): Adjust calls of queue_update_cost. Add
12854 (bucket_allocno_compare_func): Restore previous version.
12856 2020-02-21 John David Anglin <danglin@gcc.gnu.org>
12858 * config/pa/pa.c (pa_function_value): Fix check for word and
12859 double-word size when handling aggregate return values.
12860 * config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate
12861 that homogeneous SFmode and DFmode aggregates are passed and returned
12862 in general registers.
12864 2020-02-21 Jakub Jelinek <jakub@redhat.com>
12866 PR translation/93759
12867 * opts.c (print_filtered_help): Translate help before appending
12868 messages to it rather than after that.
12870 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
12872 PR rtl-optimization/PR92989
12873 * lra-lives.c (process_bb_lives): Restore the original order
12874 of the bb liveness update. Call make_hard_regno_dead for each
12875 register clobbered at the start of an EH receiver.
12877 2020-02-18 Feng Xue <fxue@os.amperecomputing.com>
12880 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as
12881 self-recursively generated.
12883 2020-02-21 Iain Sandoe <iain@sandoe.co.uk>
12886 * config/darwin-c.c (pop_field_alignment): Adjust quoting of
12889 2020-02-21 Mihail Ionescu <mihail.ionescu@arm.com>
12891 * doc/sourcebuild.texi (arm_v8_1m_mve_ok):
12892 Document new target supports option.
12894 2020-02-21 Dennis Zhang <dennis.zhang@arm.com>
12896 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New.
12897 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New.
12898 * config/arm/iterators.md (MATMUL): New iterator.
12899 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US.
12900 (mmla_sfx): New attribute.
12901 * config/arm/neon.md (neon_<sup>mmlav16qi): New.
12902 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New.
12903 (UNSPEC_MATMUL_US): New.
12905 2020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
12907 * config/arm/arm.md: Prevent scalar shifts from being used when big
12910 2020-02-21 Jan Hubicka <hubicka@ucw.cz>
12911 Richard Biener <rguenther@suse.de>
12913 PR tree-optimization/93586
12914 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk
12915 after mismatched array refs; do not sure type size information to
12916 recover from unmatched referneces with !flag_strict_aliasing_p.
12918 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
12920 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ...
12921 (gather_load<mode>v64si): ... this and set operand 2 to V64SI.
12922 (scatter_store<mode>): Rename to ...
12923 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI.
12924 (scatter<mode>_exec): Delete. Move contents ...
12925 (mask_scatter_store<mode>): ... here, and rename that to ...
12926 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI.
12927 Remove mode conversion.
12928 (mask_gather_load<mode>): Rename to ...
12929 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI.
12930 Remove mode conversion.
12931 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
12933 2020-02-21 Martin Jambor <mjambor@suse.cz>
12935 PR tree-optimization/93845
12936 * tree-sra.c (verify_sra_access_forest): Only test access size of
12939 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
12941 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
12942 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
12943 (addv64di3_exec): Likewise.
12944 (subv64di3): Likewise.
12945 (subv64di3_exec): Likewise.
12946 (addv64di3_zext): Likewise.
12947 (addv64di3_zext_exec): Likewise.
12948 (addv64di3_zext_dup): Likewise.
12949 (addv64di3_zext_dup_exec): Likewise.
12950 (addv64di3_zext_dup2): Likewise.
12951 (addv64di3_zext_dup2_exec): Likewise.
12952 (addv64di3_sext_dup2): Likewise.
12953 (addv64di3_sext_dup2_exec): Likewise.
12954 (<expander>v64di3): Likewise.
12955 (<expander>v64di3_exec): Likewise.
12956 (*<reduc_op>_dpp_shr_v64di): Likewise.
12957 (*plus_carry_dpp_shr_v64di): Likewise.
12958 * config/gcn/gcn.md (adddi3): Likewise.
12959 (addptrdi3): Likewise.
12960 (<expander>di3): Likewise.
12962 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
12964 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
12966 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
12968 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE
12969 support. Use aarch64_emit_mult instead of emitting multiplication
12970 instructions directly.
12971 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2)
12972 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders.
12974 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
12976 * config/aarch64/aarch64.c (aarch64_emit_mult): New function.
12977 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult
12978 instead of emitting multiplication instructions directly.
12979 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator.
12980 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>)
12981 (@aarch64_frecps<mode>): New expanders.
12983 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
12985 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate
12986 on and produce uint64_ts rather than ints.
12987 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts.
12988 (cpu_approx_modes): Change the fields from unsigned int to uint64_t.
12990 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
12992 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create
12993 an unused xmsk register when handling approximate rsqrt.
12995 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
12997 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted
12998 flag_finite_math_only condition.
13000 2020-02-20 Uroš Bizjak <ubizjak@gmail.com>
13003 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand
13004 to destination operand for shufps alternative.
13005 (*vec_extractv2si_1): Ditto.
13007 2020-02-20 Peter Bergner <bergner@linux.ibm.com>
13010 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
13013 2020-02-20 Martin Liska <mliska@suse.cz>
13015 PR translation/93831
13016 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode.
13018 2020-02-20 Martin Liska <mliska@suse.cz>
13020 PR translation/93830
13021 * common/config/avr/avr-common.c: Remote trailing "|".
13023 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13025 * collect2.c (maybe_run_lto_and_relink): Fix typo in
13028 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13030 PR tree-optimization/93767
13031 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the
13032 access-size bias from the offset calculations for negative strides.
13034 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13036 * collect2.c (c_file, o_file): Make const again.
13037 (ldout,lderrout, dump_ld_file): Remove.
13038 (tool_cleanup): Avoid calling not signal-safe functions.
13039 (maybe_run_lto_and_relink): Avoid possible signal handler
13040 access to unintialzed memory (lto_o_files).
13041 (main): Avoid leaking temp files in $TMPDIR.
13042 Initialize c_file/o_file with concat, which avoids exposing
13043 uninitialized memory to signal handler, which calls unlink(!).
13044 Avoid calling maybe_unlink when the main function returns,
13045 since the atexit handler is already doing this.
13046 * collect2.h (dump_ld_file, ldout, lderrout): Remove.
13048 2020-02-19 Martin Jambor <mjambor@suse.cz>
13050 PR tree-optimization/93776
13051 * tree-sra.c (create_access): Do not create zero size accesses.
13052 (get_access_for_expr): Do not search for zero sized accesses.
13054 2020-02-19 Martin Jambor <mjambor@suse.cz>
13056 PR tree-optimization/93667
13057 * tree-sra.c (scalarizable_type_p): Return false if record fields
13058 do not follow wach other.
13060 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
13062 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
13063 rather than fmv.x.s/fmv.s.x.
13065 2020-02-18 James Greenhalgh <james.greenhalgh@arm.com>
13067 * config/aarch64/aarch64-simd-builtins.def
13068 (intrinsic_vec_smult_lo_): New.
13069 (intrinsic_vec_umult_lo_): Likewise.
13070 (vec_widen_smult_hi_): Likewise.
13071 (vec_widen_umult_hi_): Likewise.
13072 * config/aarch64/aarch64-simd.md
13073 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New.
13074 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics.
13075 (vmull_high_s16): Likewise.
13076 (vmull_high_s32): Likewise.
13077 (vmull_high_u8): Likewise.
13078 (vmull_high_u16): Likewise.
13079 (vmull_high_u32): Likewise.
13080 (vmull_s8): Likewise.
13081 (vmull_s16): Likewise.
13082 (vmull_s32): Likewise.
13083 (vmull_u8): Likewise.
13084 (vmull_u16): Likewise.
13085 (vmull_u32): Likewise.
13087 2020-02-18 Martin Liska <mliska@suse.cz>
13089 * value-prof.c (stream_out_histogram_value): Restore LTO PGO
13090 bootstrap by missing removal of invalid sanity check.
13092 2020-02-18 Martin Liska <mliska@suse.cz>
13095 * ipa-icf-gimple.c (func_checker::compare_gimple_assign):
13096 Always compare LHS of gimple_assign.
13098 2020-02-18 Martin Liska <mliska@suse.cz>
13101 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute
13102 and return type of functions.
13103 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl):
13104 Drop MALLOC attribute for void functions.
13105 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop
13106 malloc_state for a new VOID clone.
13108 2020-02-18 Martin Liska <mliska@suse.cz>
13111 * common.opt: Add -fprofile-reproducibility.
13112 * doc/invoke.texi: Document it.
13113 * value-prof.c (dump_histogram_value):
13114 Document and support behavior for counters[0]
13115 being a negative value.
13116 (get_nth_most_common_value): Handle negative
13117 counters[0] in respect to flag_profile_reproducible.
13119 2020-02-18 Jakub Jelinek <jakub@redhat.com>
13122 * cgraph.c (verify_speculative_call): Use speculative_id instead of
13123 speculative_uid in messages. Remove trailing whitespace from error
13124 message. Use num_speculative_call_targets instead of
13125 num_speculative_targets in a message.
13126 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in
13127 edge messages and stmt instead of cal_stmt in reference message.
13129 PR tree-optimization/93780
13130 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p
13131 before calling build_vector_type.
13132 (execute_update_addresses_taken): Likewise.
13135 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help
13136 typo, functoin -> function.
13137 * tree.c (free_lang_data_in_decl): Fix comment typo,
13138 functoin -> function.
13139 * ipa-visibility.c (cgraph_externally_visible_p): Likewise.
13141 2020-02-17 David Malcolm <dmalcolm@redhat.com>
13143 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs
13145 (print_option_information): Don't call get_option_url if URLs
13148 2020-02-17 Alexandre Oliva <oliva@adacore.com>
13150 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete
13151 handling of register_common-less targets.
13153 2020-02-17 Martin Liska <mliska@suse.cz>
13156 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar.
13158 2020-02-17 Martin Liska <mliska@suse.cz>
13160 PR translation/93755
13161 * config/rs6000/rs6000.c (rs6000_option_override_internal):
13164 2020-02-17 Martin Liska <mliska@suse.cz>
13167 * config/rx/elf.opt: Fix typo.
13169 2020-02-17 Richard Biener <rguenther@suse.de>
13172 * opts-global.c (print_ignored_options): Use inform and
13175 2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
13178 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber.
13180 2020-02-16 Uroš Bizjak <ubizjak@gmail.com>
13183 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2.
13184 (atan2<mode>3): Update operand order in the call to gen_atan2xf3.
13186 2020-02-15 Jason Merrill <jason@redhat.com>
13188 * doc/invoke.texi (C Dialect Options): Add -std=c++20.
13190 2020-02-15 Jakub Jelinek <jakub@redhat.com>
13192 PR tree-optimization/93744
13193 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0,
13194 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A,
13195 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make
13196 sure @2 in the first and @1 in the other patterns has no side-effects.
13198 2020-02-15 David Malcolm <dmalcolm@redhat.com>
13199 Bernd Edlinger <bernd.edlinger@hotmail.de>
13203 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
13204 * configure.ac (--with-diagnostics-urls): New configuration
13205 option, based on --with-diagnostics-color.
13206 (DIAGNOSTICS_URLS_DEFAULT): New define.
13207 * config.h: Regenerate.
13208 * configure: Regenerate.
13209 * diagnostic.c (diagnostic_urls_init): Handle -1 for
13210 DIAGNOSTICS_URLS_DEFAULT from configure-time
13211 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
13212 and TERM_URLS environment variable.
13213 * diagnostic-url.h (diagnostic_url_format): New enum type.
13214 (diagnostic_urls_enabled_p): rename to...
13215 (determine_url_format): ... this, and change return type.
13216 * diagnostic-color.c (parse_env_vars_for_urls): New helper function.
13217 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
13218 the linux console, and mingw.
13219 (diagnostic_urls_enabled_p): rename to...
13220 (determine_url_format): ... this, and adjust.
13221 * pretty-print.h (pretty_printer::show_urls): rename to...
13222 (pretty_printer::url_format): ... this, and change to enum.
13223 * pretty-print.c (pretty_printer::pretty_printer,
13224 pp_begin_url, pp_end_url, test_urls): Adjust.
13225 * doc/install.texi (--with-diagnostics-urls): Document the new
13226 configuration option.
13227 (--with-diagnostics-color): Document the existing interaction
13228 with GCC_COLORS better.
13229 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
13230 vindex reference. Update description of defaults based on the above.
13231 (-fdiagnostics-color): Update description of how -fdiagnostics-color
13232 interacts with GCC_COLORS.
13234 2020-02-14 Eric Botcazou <ebotcazou@adacore.com>
13237 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in
13238 conjunction with TARGET_GNU_TLS in early return.
13240 2020-02-14 Alexander Monakov <amonakov@ispras.ru>
13242 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if
13243 the mode is not wider than UNITS_PER_WORD.
13245 2020-02-14 Martin Jambor <mjambor@suse.cz>
13247 PR tree-optimization/93516
13248 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create
13249 access of the same type as the parent.
13250 (propagate_subaccesses_from_lhs): Likewise.
13252 2020-02-14 Hongtao Liu <hongtao.liu@intel.com>
13255 * config/i386/avx512vbmi2intrin.h
13256 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16,
13257 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32,
13258 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
13259 _m512_shrdi_epi64, _m512_mask_shrdi_epi64,
13260 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16,
13261 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16,
13262 _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
13263 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64,
13264 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo
13265 of lacking a closing parenthesis.
13266 * config/i386/avx512vbmi2vlintrin.h
13267 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16,
13268 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32,
13269 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32,
13270 _m256_shrdi_epi64, _m256_mask_shrdi_epi64,
13271 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16,
13272 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16,
13273 _mm256_shldi_epi32, _mm256_mask_shldi_epi32,
13274 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64,
13275 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64,
13276 _mm_shrdi_epi16, _mm_mask_shrdi_epi16,
13277 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32,
13278 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32,
13279 _mm_shrdi_epi64, _mm_mask_shrdi_epi64,
13280 _m_maskz_shrdi_epi64, _mm_shldi_epi16,
13281 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16,
13282 _mm_shldi_epi32, _mm_mask_shldi_epi32,
13283 _mm_maskz_shldi_epi32, _mm_shldi_epi64,
13284 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto.
13286 2020-02-13 H.J. Lu <hongjiu.lu@intel.com>
13289 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
13290 the target function entry.
13292 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13294 * common/config/arc/arc-common.c (arc_option_optimization_table):
13295 Disable if-conversion step when optimized for size.
13297 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13299 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
13300 R12-R15 are always in ARCOMPACT16_REGS register class.
13301 * config/arc/arc.opt (mq-class): Deprecate.
13302 * config/arc/constraint.md ("q"): Remove dependency on mq-class
13304 * doc/invoke.texi (mq-class): Update text.
13305 * common/config/arc/arc-common.c (arc_option_optimization_table):
13308 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13310 * config/arc/arc.c (arc_insn_cost): New function.
13311 (TARGET_INSN_COST): Define.
13312 * config/arc/arc.md (cost): New attribute.
13313 (add_n): Use arc_nonmemory_operand.
13314 (ashlsi3_insn): Likewise, also update constraints.
13315 (ashrsi3_insn): Likewise.
13316 (rotrsi3): Likewise.
13317 (add_shift): Likewise.
13318 * config/arc/predicates.md (arc_nonmemory_operand): New predicate.
13320 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13322 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
13324 (umulsidi_600): Likewise.
13326 2020-02-13 Jakub Jelinek <jakub@redhat.com>
13329 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8,
13330 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8,
13331 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8,
13332 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W,
13333 pass __A to the builtin followed by __W instead of __A followed by
13335 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32,
13336 _mm512_mask_popcnt_epi64): Likewise.
13337 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32,
13338 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64,
13339 _mm256_mask_popcnt_epi64): Likewise.
13341 PR tree-optimization/93582
13342 * fold-const.h (shift_bytes_in_array_left,
13343 shift_bytes_in_array_right): Declare.
13344 * fold-const.c (shift_bytes_in_array_left,
13345 shift_bytes_in_array_right): New function, moved from
13346 gimple-ssa-store-merging.c, no longer static.
13347 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move
13348 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left.
13349 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c.
13350 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of
13351 shift_bytes_in_array.
13352 (verify_shift_bytes_in_array): Rename to ...
13353 (verify_shift_bytes_in_array_left): ... this. Use
13354 shift_bytes_in_array_left instead of shift_bytes_in_array.
13355 (store_merging_c_tests): Call verify_shift_bytes_in_array_left
13356 instead of verify_shift_bytes_in_array.
13357 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr
13358 / native_interpret_expr where the store covers all needed bits,
13359 punt on PDP-endian, otherwise allow all involved offsets and sizes
13360 not to be byte-aligned.
13363 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and
13364 use const_0_to_255_operand predicate instead of immediate_operand.
13365 (avx512dq_fpclass<mode><mask_scalar_merge_name>,
13366 avx512dq_vmfpclass<mode><mask_scalar_merge_name>,
13367 vgf2p8affineinvqb_<mode><mask_name>,
13368 vgf2p8affineqb_<mode><mask_name>): Drop mode from
13369 const_0_to_255_operand predicated operands.
13371 2020-02-12 Jeff Law <law@redhat.com>
13373 * config/h8300/h8300.md (comparison shortening peepholes): Use
13374 a mode iterator to merge the HImode and SImode peepholes.
13376 2020-02-12 Jakub Jelinek <jakub@redhat.com>
13378 PR middle-end/93663
13379 * real.c (is_even): Make static. Function comment fix.
13380 (is_halfway_below): Make static, don't assert R is not inf/nan,
13381 instead return false for those. Small formatting fixes.
13383 2020-02-12 Martin Sebor <msebor@redhat.com>
13385 PR middle-end/93646
13386 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename...
13387 (handle_builtin_stxncpy_strncat): ...to this. Change first argument.
13388 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation.
13389 (strlen_check_and_optimize_call): Adjust callee name.
13391 2020-02-12 Jeff Law <law@redhat.com>
13393 * config/h8300/h8300.md (comparison shortening peepholes): Drop
13394 (and (xor)) variant. Combine other two into single peephole.
13396 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
13398 PR rtl-optimization/93565
13399 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs.
13401 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
13403 * config/aarch64/aarch64-simd.md
13404 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
13405 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
13406 generating separate ADDV and zero_extend patterns.
13407 * config/aarch64/iterators.md (VDQV_E): New iterator.
13409 2020-02-12 Jeff Law <law@redhat.com>
13411 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns,
13412 expanders, splits, etc.
13413 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise.
13414 (stpcpy_internal_<mode>, stpcpy splitter): Likewise.
13415 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise.
13416 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function.
13417 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise
13418 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused
13419 function prototype.
13420 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise.
13422 2020-02-12 Jakub Jelinek <jakub@redhat.com>
13425 * config/i386/sse.md (VI48F_256_DQ): New mode iterator.
13426 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove
13427 TARGET_AVX512DQ from condition.
13428 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition>
13429 instead of <mask_mode512bit_condition> in condition. If
13430 TARGET_AVX512DQ is false, emit vextract*64x4 instead of
13432 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition>
13435 2020-02-12 Kewen Lin <linkw@gcc.gnu.org>
13438 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn.
13440 2020-02-12 Segher Boessenkool <segher@kernel.crashing.org>
13442 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof
13443 where strlen is more legible.
13444 (rs6000_builtin_vectorized_libmass): Ditto.
13445 (rs6000_print_options_internal): Ditto.
13447 2020-02-11 Martin Sebor <msebor@redhat.com>
13449 PR tree-optimization/93683
13450 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set.
13452 2020-02-11 Michael Meissner <meissner@linux.ibm.com>
13454 * config/rs6000/predicates.md (cint34_operand): Rename the
13455 -mprefixed-addr option to be -mprefixed.
13456 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename
13457 the -mprefixed-addr option to be -mprefixed.
13458 (OTHER_FUTURE_MASKS): Likewise.
13459 (POWERPC_MASKS): Likewise.
13460 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
13461 the -mprefixed-addr option to be -mprefixed. Change error
13462 messages to refer to -mprefixed.
13463 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be
13465 (rs6000_legitimate_offset_address_p): Likewise.
13466 (rs6000_mode_dependent_address): Likewise.
13467 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be
13468 "-mprefixed" for target attributes and pragmas.
13469 (address_to_insn_form): Rename the -mprefixed-addr option to be
13471 (rs6000_adjust_insn_length): Likewise.
13472 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the
13473 -mprefixed-addr option to be -mprefixed.
13474 (ASM_OUTPUT_OPCODE): Likewise.
13475 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the
13476 -mprefixed-addr option to be -mprefixed.
13477 * config/rs6000/rs6000.opt (-mprefixed): Rename the
13478 -mprefixed-addr option to be prefixed. Change the option from
13479 being undocumented to being documented.
13480 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the
13481 -mprefixed option. Update the -mpcrel documentation to mention
13484 2020-02-11 Hans-Peter Nilsson <hp@axis.com>
13486 * ira-conflicts.c (print_hard_reg_set): Correct output for sets
13487 including FIRST_PSEUDO_REGISTER - 1.
13488 * ira-color.c (print_hard_reg_set): Ditto.
13490 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13492 * config/arm/arm-builtins.c (enum arm_type_qualifiers):
13493 (USTERNOP_QUALIFIERS): New define.
13494 (USMAC_LANE_QUADTUP_QUALIFIERS): New define.
13495 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define.
13496 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX.
13497 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index.
13498 * config/arm/arm_neon.h (vusdot_s32): New.
13499 (vusdot_lane_s32): New.
13500 (vusdotq_lane_s32): New.
13501 (vsudot_lane_s32): New.
13502 (vsudotq_lane_s32): New.
13503 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New.
13504 * config/arm/iterators.md (DOTPROD_I8MM): New.
13505 (sup, opsuffix): Add <us/su>.
13506 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New.
13507 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New.
13509 2020-02-11 Richard Biener <rguenther@suse.de>
13511 PR tree-optimization/93661
13512 PR tree-optimization/93662
13513 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard
13514 tree_to_poly_int64.
13515 * tree-sra.c (get_access_for_expr): Likewise.
13517 2020-02-10 Jakub Jelinek <jakub@redhat.com>
13520 * config/i386/sse.md (VI_256_AVX2): New mode iterator.
13521 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256.
13522 Change condition from TARGET_AVX2 to TARGET_AVX.
13524 2020-02-10 Iain Sandoe <iain@sandoe.co.uk>
13527 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last
13528 argument of strncmp.
13530 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
13532 Try to generate zero-based comparisons.
13533 * config/cris/cris.c (cris_reduce_compare): New function.
13534 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype.
13535 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4")
13536 (cstore<mode>4"): Apply cris_reduce_compare in expanders.
13538 2020-02-10 Richard Earnshaw <rearnsha@arm.com>
13541 * config/arm/arm.md (movsi_compare0): Allow SP as a source register
13542 in Thumb state and also as a destination in Arm state. Add T16
13545 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
13547 * md.texi (Define Subst): Match closing paren in example.
13549 2020-02-10 Jakub Jelinek <jakub@redhat.com>
13553 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last
13554 arguments of strncmp.
13556 2020-02-10 Feng Xue <fxue@os.amperecomputing.com>
13559 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge
13560 but different source value.
13561 (adjust_callers_for_value_intersection): New function.
13562 (gather_edges_for_value): Adjust order of callers to let a
13563 non-self-recursive caller be the first element.
13564 (self_recursive_pass_through_p): Add a new parameter "simple", and
13565 check generalized self-recursive pass-through jump function.
13566 (self_recursive_agg_pass_through_p): Likewise.
13567 (find_more_scalar_values_for_callers_subset): Compute value from
13568 pass-through jump function for self-recursive.
13569 (intersect_with_plats): Cleanup previous implementation code for value
13570 itersection with self-recursive call edge.
13571 (intersect_with_agg_replacements): Likewise.
13572 (intersect_aggregates_with_edge): Deduce value from pass-through jump
13573 function for self-recursive call edge. Cleanup previous implementation
13574 code for value intersection with self-recursive call edge.
13575 (decide_whether_version_node): Remove dead callers and adjust order
13576 to let a non-self-recursive caller be the first element.
13578 2020-02-09 Uroš Bizjak <ubizjak@gmail.com>
13580 * recog.c: Move pass_split_before_sched2 code in front of
13581 pass_split_before_regstack.
13582 (pass_data_split_before_sched2): Rename pass to split3 from split4.
13583 (pass_data_split_before_regstack): Rename pass to split4 from split3.
13584 (rest_of_handle_split_before_sched2): Remove.
13585 (pass_split_before_sched2::execute): Unconditionally call
13587 (enable_split_before_sched2): New function.
13588 (pass_split_before_sched2::gate): Use enable_split_before_sched2.
13589 (pass_split_before_regstack::gate): Ditto.
13590 * config/nds32/nds32.c (nds32_split_double_word_load_store_p):
13591 Update name check for renamed split4 pass.
13592 * config/sh/sh.c (register_sh_passes): Update pass insertion
13593 point for renamed split4 pass.
13595 2020-02-09 Jakub Jelinek <jakub@redhat.com>
13597 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote
13598 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid
13599 copying them around between host and target.
13601 2020-02-08 Andrew Pinski <apinski@marvell.com>
13604 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
13605 STRICT_ALIGNMENT also.
13607 2020-02-08 Jim Wilson <jimw@sifive.com>
13610 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
13612 2020-02-08 Uroš Bizjak <ubizjak@gmail.com>
13613 Jakub Jelinek <jakub@redhat.com>
13616 * config/i386/i386.h (CALL_USED_REGISTERS): Make
13617 xmm16-xmm31 call-used even in 64-bit ms-abi.
13619 2020-02-07 Dennis Zhang <dennis.zhang@arm.com>
13621 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry.
13622 (simd_ummla, simd_usmmla): Likewise.
13623 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New.
13624 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New.
13625 (vusmmlaq_s32): New.
13627 2020-02-07 Richard Biener <rguenther@suse.de>
13629 PR middle-end/93519
13630 * tree-inline.c (fold_marked_statements): Do a PRE walk,
13631 skipping unreachable regions.
13632 (optimize_inline_calls): Skip folding stmts when we didn't
13635 2020-02-07 H.J. Lu <hongjiu.lu@intel.com>
13638 * config/i386/i386.c (function_arg_ms_64): Add a type argument.
13639 Don't return aggregates with only SFmode and DFmode in SSE
13641 (ix86_function_arg): Pass arg.type to function_arg_ms_64.
13643 2020-02-07 Jakub Jelinek <jakub@redhat.com>
13646 * config/rs6000/rs6000-logue.c
13647 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn,
13648 if it fails, move rs into end_addr and retry. Add
13649 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or
13650 the insn pattern doesn't describe well what exactly happens to
13654 * config/i386/predicates.md (avx_identity_operand): Remove.
13655 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove.
13656 (avx_<castmode><avxsizesuffix>_<castmode>,
13657 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to
13658 a VEC_CONCAT of the operand and UNSPEC_CAST.
13659 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to
13660 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with
13664 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear
13665 recog_data.insn if distance_non_agu_define changed it.
13667 2020-02-06 Michael Meissner <meissner@linux.ibm.com>
13670 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
13671 we only had X-FORM (reg+reg) addressing for vectors. Also before
13672 ISA 3.0, we only had X-FORM addressing for scalars in the
13673 traditional Altivec registers.
13675 2020-02-06 <zhongyunde@huawei.com>
13676 Vladimir Makarov <vmakarov@redhat.com>
13678 PR rtl-optimization/93561
13679 * lra-assigns.c (spill_for): Check that tested hard regno is not out of
13680 hard register range.
13682 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
13684 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type
13687 2020-02-06 Segher Boessenkool <segher@kernel.crashing.org>
13689 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case
13690 where the low and the high 32 bits are equal to each other specially,
13691 with an rldimi instruction.
13693 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
13695 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main.
13697 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
13699 * config/arm/arm-tables.opt: Regenerate.
13701 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
13704 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare.
13705 * config/aarch64/aarch64.c (aarch64_movk_shift): New function.
13706 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern.
13708 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
13710 PR rtl-optimization/87763
13711 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern.
13713 2020-02-06 Delia Burduv <delia.burduv@arm.com>
13715 * config/aarch64/aarch64-simd-builtins.def
13716 (bfmlaq): New built-in function.
13717 (bfmlalb): New built-in function.
13718 (bfmlalt): New built-in function.
13719 (bfmlalb_lane): New built-in function.
13720 (bfmlalt_lane): New built-in function.
13721 * config/aarch64/aarch64-simd.md
13722 (aarch64_bfmmlaqv4sf): New pattern.
13723 (aarch64_bfmlal<bt>v4sf): New pattern.
13724 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern.
13725 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic.
13726 (vbfmlalbq_f32): New intrinsic.
13727 (vbfmlaltq_f32): New intrinsic.
13728 (vbfmlalbq_lane_f32): New intrinsic.
13729 (vbfmlaltq_lane_f32): New intrinsic.
13730 (vbfmlalbq_laneq_f32): New intrinsic.
13731 (vbfmlaltq_laneq_f32): New intrinsic.
13732 * config/aarch64/iterators.md (BF_MLA): New int iterator.
13733 (bt): New int attribute.
13735 2020-02-06 Uroš Bizjak <ubizjak@gmail.com>
13737 * config/i386/i386.md (*pushtf): Emit "#" instead of
13738 calling gcc_unreachable in insn output.
13741 (*pushsf_rex64): Ditto for alternatives other than 1.
13742 (*pushsf): Ditto for alternatives other than 1.
13744 2020-02-06 Martin Liska <mliska@suse.cz>
13746 PR gcov-profile/91971
13747 PR gcov-profile/93466
13748 * coverage.c (coverage_init): Revert mangling of
13749 path into filename. It can lead to huge filename length.
13750 Creation of subfolders seem more natural.
13752 2020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13755 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New.
13756 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs.
13757 Use arm_block_arith_comp_libfuncs_for_mode for HFmode.
13759 2020-02-06 Jakub Jelinek <jakub@redhat.com>
13762 * config/i386/predicates.md (avx_identity_operand): New predicate.
13763 * config/i386/sse.md (*avx_vec_concat<mode>_1): New
13764 define_insn_and_split.
13767 * omp-low.c (use_pointer_for_field): For nested constructs, also
13768 look for map clauses on target construct.
13769 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily
13770 taskreg_nesting_level.
13773 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding
13774 shared clause, call omp_notice_variable on outer context if any.
13776 2020-02-05 Jason Merrill <jason@redhat.com>
13779 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has
13780 non-zero address even if weak and not yet defined.
13782 2020-02-05 Martin Sebor <msebor@redhat.com>
13784 PR tree-optimization/92765
13785 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL.
13786 * tree-ssa-strlen.c (compute_string_length): Remove.
13787 (determine_min_objsize): Remove.
13788 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic.
13789 Avoid using type size as the upper bound on string length.
13790 (handle_builtin_string_cmp): Add an argument. Adjust.
13791 (strlen_check_and_optimize_call): Pass additional argument to
13792 handle_builtin_string_cmp.
13794 2020-02-05 Uroš Bizjak <ubizjak@gmail.com>
13796 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove.
13797 (*pushdi2_rex64 peephole2): Unconditionally split after
13798 epilogue_completed.
13799 (*ashl<mode>3_doubleword): Ditto.
13800 (*<shift_insn><mode>3_doubleword): Ditto.
13802 2020-02-05 Michael Meissner <meissner@linux.ibm.com>
13805 * config/rs6000/rs6000.c (get_vector_offset): Fix
13807 2020-02-05 Andrew Stubbs <ams@codesourcery.com>
13809 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space.
13811 2020-02-05 David Malcolm <dmalcolm@redhat.com>
13813 * doc/analyzer.texi
13814 (Special Functions for Debugging the Analyzer): Update description
13815 of __analyzer_dump_exploded_nodes.
13817 2020-02-05 Jakub Jelinek <jakub@redhat.com>
13820 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only
13821 include sets and not clobbers in the vzeroupper pattern.
13822 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that
13823 the parallel has 17 (64-bit) or 9 (32-bit) elts.
13824 (*avx_vzeroupper_1): New define_insn_and_split.
13827 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets,
13828 don't run when !optimize.
13829 (pass_split_before_regstack::gate): For STACK_REGS targets, run even
13832 2020-02-05 Richard Biener <rguenther@suse.de>
13834 PR middle-end/90648
13835 * genmatch.c (dt_node::gen_kids_1): Emit number of argument
13836 checks before matching calls.
13838 2020-02-05 Jakub Jelinek <jakub@redhat.com>
13840 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up
13841 function comment typo.
13843 PR middle-end/93555
13844 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or
13845 simd_clone_create failed when i == 0, adjust clone->nargs by
13848 2020-02-05 Martin Liska <mliska@suse.cz>
13851 * doc/invoke.texi: Document that one should
13852 not combine ASLR and -fpch.
13854 2020-02-04 Richard Biener <rguenther@suse.de>
13856 PR tree-optimization/93538
13857 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr.
13859 2020-02-04 Richard Biener <rguenther@suse.de>
13861 PR tree-optimization/91123
13862 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method.
13863 (vn_walk_cb_data::last_vuse): New member.
13864 (vn_walk_cb_data::saved_operands): Likewsie.
13865 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands.
13866 (vn_walk_cb_data::push_partial_def): Use finish.
13867 (vn_reference_lookup_2): Update last_vuse and use finish if
13868 we've saved operands.
13869 (vn_reference_lookup_3): Use finish and update calls to
13870 push_partial_defs everywhere. When translating through
13871 memcpy or aggregate copies save off operands and alias-set.
13872 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE
13873 operation for redundant store removal.
13875 2020-02-04 Richard Biener <rguenther@suse.de>
13877 PR tree-optimization/92819
13878 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid
13879 generating more stmts than before.
13881 2020-02-04 Martin Liska <mliska@suse.cz>
13883 * config/arm/arm.c (arm_gen_far_branch): Move the function
13884 outside of selftests.
13886 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
13888 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
13889 function to adjust PC-relative vector addresses.
13890 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
13891 handle vectors with PC-relative addresses.
13893 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
13895 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
13897 (hard_reg_and_mode_to_addr_mask): Delete.
13898 (rs6000_adjust_vec_address): If the original vector address
13899 was REG+REG or REG+OFFSET and the element is not zero, do the add
13900 of the elements in the original address before adding the offset
13901 for the vector element. Use address_to_insn_form to validate the
13902 address using the register being loaded, rather than guessing
13903 whether the address is a DS-FORM or DQ-FORM address.
13905 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
13907 * config/rs6000/rs6000.c (get_vector_offset): New helper function
13908 to calculate the offset in memory from the start of a vector of a
13909 particular element. Add code to keep the element number in
13910 bounds if the element number is variable.
13911 (rs6000_adjust_vec_address): Move calculation of offset of the
13912 vector element to get_vector_offset.
13913 (rs6000_split_vec_extract_var): Do not do the initial AND of
13914 element here, move the code to get_vector_offset.
13916 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
13918 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
13921 2020-02-03 Segher Boessenkool <segher@kernel.crashing.org>
13923 * config/rs6000/constraints.md: Improve documentation.
13925 2020-02-03 Richard Earnshaw <rearnsha@arm.com>
13928 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md)
13929 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change.
13931 2020-02-03 Andrew Stubbs <ams@codesourcery.com>
13933 * config.gcc: Remove "carrizo" support.
13934 * config/gcn/gcn-opts.h (processor_type): Likewise.
13935 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
13936 * config/gcn/gcn.opt (gpu_type): Likewise.
13937 * config/gcn/t-omp-device: Likewise.
13939 2020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13942 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
13943 * config/arm/arm.c (arm_gen_far_branch): New function
13944 arm_gen_far_branch.
13945 * config/arm/arm.md: Update b<cond> for Thumb2 range checks.
13947 2020-02-03 Julian Brown <julian@codesourcery.com>
13948 Tobias Burnus <tobias@codesourcery.com>
13950 * doc/invoke.texi: Update mention of OpenACC version to 2.6.
13952 2020-02-03 Jakub Jelinek <jakub@redhat.com>
13955 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit
13956 valid RTL to sum up the lowest and second lowest bytes of the popcnt
13959 2020-02-02 Vladimir Makarov <vmakarov@redhat.com>
13961 PR rtl-optimization/91333
13962 * ira-color.c (struct allocno_color_data): Add member
13964 (init_allocno_threads): Set the member up.
13965 (bucket_allocno_compare_func): Add compare hard reg
13968 2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
13970 nios2: Support for GOT-relative DW_EH_PE_datarel encoding.
13972 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION.
13973 * config.in: Regenerated.
13974 * configure: Regenerated.
13975 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling
13976 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION.
13977 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New.
13979 2020-02-01 Andrew Burgess <andrew.burgess@embecosm.com>
13981 * configure: Regenerate.
13983 2020-01-31 Vladimir Makarov <vmakarov@redhat.com>
13985 PR rtl-optimization/91333
13986 * ira-color.c (bucket_allocno_compare_func): Move conflict hard
13987 reg preferences comparison up.
13989 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
13991 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro.
13992 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to
13993 aarch64-sve-builtins-base.h.
13994 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to
13995 aarch64-sve-builtins-base.cc.
13996 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane)
13997 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
13998 (svcvtnt): Declare.
13999 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane)
14000 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14001 (svcvtnt): New functions.
14002 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane)
14003 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14004 (svcvtnt): New functions.
14005 (svcvt): Add a form that converts f32 to bf16.
14006 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat)
14007 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n):
14009 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type):
14010 Treat B as bfloat16_t.
14011 (ternary_bfloat_lane_base): New class.
14012 (ternary_bfloat_def): Likewise.
14013 (ternary_bfloat): New shape.
14014 (ternary_bfloat_lane_def): New class.
14015 (ternary_bfloat_lane): New shape.
14016 (ternary_bfloat_lanex2_def): New class.
14017 (ternary_bfloat_lanex2): New shape.
14018 (ternary_bfloat_opt_n_def): New class.
14019 (ternary_bfloat_opt_n): New shape.
14020 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro.
14021 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf)
14022 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns.
14023 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
14024 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14025 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14026 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise.
14027 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key
14028 the pattern off the narrow mode instead of the wider one.
14029 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator.
14030 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs.
14031 (sve_fp_op): Handle them.
14032 (SVE_BFLOAT_TERNARY_LONG): New int itertor.
14033 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
14035 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14037 * config/aarch64/arm_sve.h: Include arm_bf16.h.
14038 * config/aarch64/aarch64-modes.def (BF): Move definition before
14039 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF.
14040 (SVE_MODES): Handle BF modes.
14041 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
14043 (aarch64_full_sve_mode): Likewise.
14044 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF
14046 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF.
14047 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
14048 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count)
14049 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the
14051 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New
14053 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro.
14054 (TYPES_all_data): Add bf16.
14055 (TYPES_reinterpret1, TYPES_reinterpret): Likewise.
14056 (register_tuple_type): Increase buffer size.
14057 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type.
14058 (bf16): New type suffix.
14059 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv)
14060 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax)
14061 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr):
14062 Change type from all_data to all_arith.
14063 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp)
14064 (svminp): Likewise.
14066 2020-01-31 Dennis Zhang <dennis.zhang@arm.com>
14067 Matthew Malcomson <matthew.malcomson@arm.com>
14068 Richard Sandiford <richard.sandiford@arm.com>
14070 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension.
14071 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
14072 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
14073 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define
14074 __ARM_FEATURE_MATMUL_FP64.
14075 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16)
14076 (sve): Add AARCH64_FL_F32MM to the list of extensions that should
14077 be disabled at the same time.
14078 (f32mm): New extension.
14079 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro.
14080 (AARCH64_FL_F64MM): Bump to the next bit up.
14081 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM)
14082 (TARGET_SVE_F64MM): New macros.
14083 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator.
14084 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL)
14085 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q)
14086 (UNSPEC_ZIP2Q): New unspeccs.
14087 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators.
14088 (optab, sur, perm_insn): Handle the new unspecs.
14089 (sve_fp_op): Handle UNSPEC_FMMLA. Resort.
14090 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
14091 TARGET_SVE_F64MM instead of separate tests.
14092 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern.
14093 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise.
14094 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise.
14095 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise.
14096 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise.
14097 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro.
14098 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it.
14099 (TYPES_s_signed): New macro.
14100 (TYPES_s_integer): Use it.
14101 (TYPES_d_float): New macro.
14102 (TYPES_d_data): Use it.
14103 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare.
14104 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq)
14105 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise.
14106 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class.
14107 (svmmla): New shape.
14108 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3
14109 template parameters.
14110 (ternary_resize2_lane_base): Likewise.
14111 (ternary_resize2_base): New class.
14112 (ternary_qq_lane_base): Likewise.
14113 (ternary_intq_uintq_lane_def): Likewise.
14114 (ternary_intq_uintq_lane): New shape.
14115 (ternary_intq_uintq_opt_n_def): New class
14116 (ternary_intq_uintq_opt_n): New shape.
14117 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base.
14118 (ternary_uintq_intq_def): New class.
14119 (ternary_uintq_intq): New shape.
14120 (ternary_uintq_intq_lane_def): New class.
14121 (ternary_uintq_intq_lane): New shape.
14122 (ternary_uintq_intq_opt_n_def): New class.
14123 (ternary_uintq_intq_opt_n): New shape.
14124 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot)
14125 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla)
14126 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare.
14127 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl):
14129 (svdotprod_lane_impl): ...this new class.
14130 (svmmla_impl, svusdot_impl): New classes.
14131 (svdot_lane): Update to use svdotprod_lane_impl.
14132 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot)
14133 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New
14135 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base
14136 function, with no types defined.
14137 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New
14138 AARCH64_FL_I8MM functions.
14139 (svmmla): New AARCH64_FL_F32MM function.
14140 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6.
14141 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New
14142 AARCH64_FL_F64MM function.
14143 (REQUIRED_EXTENSIONS):
14145 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
14147 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
14150 2020-01-31 Uroš Bizjak <ubizjak@gmail.com>
14152 * config/i386/i386.md (*movoi_internal_avx): Do not check for
14153 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling.
14154 (*movti_internal): Do not check for
14155 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
14156 (*movtf_internal): Move check for TARGET_SSE2 and size optimization
14157 just after check for TARGET_AVX.
14158 (*movdf_internal): Ditto.
14159 * config/i386/mmx.md (*mov<mode>_internal): Do not check for
14160 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
14161 * config/i386/sse.md (mov<mode>_internal): Only check
14162 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check
14163 for TARGET_SSE2 and size optimization just after check for TARGET_AVX.
14164 (<sse>_andnot<mode>3<mask_name>): Move check for
14165 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX.
14166 (<code><mode>3<mask_name>): Ditto.
14167 (*andnot<mode>3): Ditto.
14168 (*andnottf3): Ditto.
14169 (*<code><mode>3): Ditto.
14170 (*<code>tf3): Ditto.
14171 (*andnot<VI:mode>3): Remove
14172 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling.
14173 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto.
14174 (*<code><VI12_AVX_AVX512F:mode>3): Ditto.
14175 (sse4_1_blendv<ssemodesuffix>): Ditto.
14176 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL):
14177 Explain that tune applies to 128bit instructions only.
14179 2020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com>
14181 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count
14182 to definition of hsa_kernel_description. Parse assembly to find SGPR
14183 and VGPR count of kernel and store in hsa_kernel_description.
14185 2020-01-31 Tamar Christina <tamar.christina@arm.com>
14187 PR rtl-optimization/91838
14188 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case
14189 to truncate if allowed or reject combination.
14191 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
14193 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step.
14194 (find_inv_vars_cb): Likewise.
14196 2020-01-31 David Malcolm <dmalcolm@redhat.com>
14198 * calls.c (special_function_p): Split out the check for DECL_NAME
14199 being non-NULL and fndecl being extern at file scope into a
14200 new maybe_special_function_p and call it. Drop check for fndecl
14201 being non-NULL that was after a usage of DECL_NAME (fndecl).
14202 * tree.h (maybe_special_function_p): New inline function.
14204 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
14206 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ...
14207 (mask_gather_load<mode>): ... here, and zero-initialize the
14209 (maskload<mode>di): Zero-initialize the destination.
14210 * config/gcn/gcn.c:
14212 2020-01-30 David Malcolm <dmalcolm@redhat.com>
14215 * doc/analyzer.texi (Limitations): Note that constraints on
14216 floating-point values are currently ignored.
14218 2020-01-30 Jakub Jelinek <jakub@redhat.com>
14221 * symtab.c (symtab_node::noninterposable_alias): If localalias
14222 already exists, but is not usable, append numbers after it until
14223 a unique name is found. Formatting fix.
14225 PR middle-end/93505
14226 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range
14229 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
14231 * config/gcn/gcn.c (print_operand): Handle LTGT.
14232 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt.
14234 2020-01-30 Richard Biener <rguenther@suse.de>
14236 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST
14237 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE.
14239 2020-01-30 John David Anglin <danglin@gcc.gnu.org>
14241 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers
14242 without a DECL in .data.rel.ro.local.
14244 2020-01-30 Jakub Jelinek <jakub@redhat.com>
14247 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4
14251 * config/i386/sse.md
14252 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ...
14253 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use
14254 any_extend code iterator instead of always zero_extend.
14255 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ...
14256 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this.
14257 Use any_extend code iterator instead of always zero_extend.
14258 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ...
14259 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this.
14260 Use any_extend code iterator instead of always zero_extend.
14261 (*sse2_pmovmskb_ext): New define_insn.
14262 (*sse2_pmovmskb_ext_lt): New define_insn_and_split.
14265 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split.
14266 (*popcountsi2_zext_falsedep): New define_insn.
14268 2020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
14270 * config.in: Regenerated.
14271 * configure: Regenerated.
14273 2020-01-29 Tobias Burnus <tobias@codesourcery.com>
14276 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as
14277 LLVM's assembler changed the default in version 9.
14279 2020-01-24 Jeff Law <law@redhat.com>
14281 PR tree-optimization/89689
14282 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure.
14284 2020-01-29 Richard Sandiford <richard.sandiford@arm.com>
14288 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14290 PR rtl-optimization/87763
14291 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
14292 simplification to handle subregs as well as bare regs.
14293 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
14295 2020-01-29 Joel Hutton <Joel.Hutton@arm.com>
14298 * ira.c (ira): Revert use of simplified LRA algorithm.
14300 2020-01-29 Martin Jambor <mjambor@suse.cz>
14302 PR tree-optimization/92706
14303 * tree-sra.c (struct access): Fields first_link, last_link,
14304 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link,
14305 next_rhs_queued and grp_rhs_queued respectively, new fields
14306 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued.
14307 (struct assign_link): Field next renamed to next_rhs, new field
14308 next_lhs. Updated comment.
14309 (work_queue_head): Renamed to rhs_work_queue_head.
14310 (lhs_work_queue_head): New variable.
14311 (add_link_to_lhs): New function.
14312 (relink_to_new_repr): Also relink LHS lists.
14313 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue.
14314 (add_access_to_lhs_work_queue): New function.
14315 (pop_access_from_work_queue): Renamed to
14316 pop_access_from_rhs_work_queue.
14317 (pop_access_from_lhs_work_queue): New function.
14318 (build_accesses_from_assign): Also add links to LHS lists and to LHS
14320 (child_would_conflict_in_lacc): Renamed to
14321 child_would_conflict_in_acc. Adjusted parameter names.
14322 (create_artificial_child_access): New parameter set_grp_read, use it.
14323 (subtree_mark_written_and_enqueue): Renamed to
14324 subtree_mark_written_and_rhs_enqueue.
14325 (propagate_subaccesses_across_link): Renamed to
14326 propagate_subaccesses_from_rhs.
14327 (propagate_subaccesses_from_lhs): New function.
14328 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to
14331 2020-01-29 Martin Jambor <mjambor@suse.cz>
14333 PR tree-optimization/92706
14334 * tree-sra.c (struct access): Adjust comment of
14335 grp_total_scalarization.
14336 (find_access_in_subtree): Look for single children spanning an entire
14338 (scalarizable_type_p): Allow register accesses, adjust callers.
14339 (completely_scalarize): Remove function.
14340 (scalarize_elem): Likewise.
14341 (create_total_scalarization_access): Likewise.
14342 (sort_and_splice_var_accesses): Do not track total scalarization
14344 (analyze_access_subtree): New parameter totally, adjust to new meaning
14345 of grp_total_scalarization.
14346 (analyze_access_trees): Pass new parameter to analyze_access_subtree.
14347 (can_totally_scalarize_forest_p): New function.
14348 (create_total_scalarization_access): Likewise.
14349 (create_total_access_and_reshape): Likewise.
14350 (total_should_skip_creating_access): Likewise.
14351 (totally_scalarize_subtree): Likewise.
14352 (analyze_all_variable_accesses): Perform total scalarization after
14353 subaccess propagation using the new functions above.
14354 (initialize_constant_pool_replacements): Output initializers by
14355 traversing the access tree.
14357 2020-01-29 Martin Jambor <mjambor@suse.cz>
14359 * tree-sra.c (verify_sra_access_forest): New function.
14360 (verify_all_sra_access_forests): Likewise.
14361 (create_artificial_child_access): Set parent.
14362 (analyze_all_variable_accesses): Call the verifier.
14364 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14366 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge
14367 if called on indirect edge.
14368 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of
14369 speculative call if needed.
14371 2020-01-29 Richard Biener <rguenther@suse.de>
14373 PR tree-optimization/93428
14374 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load
14375 permutation when the load node is created.
14376 (vect_analyze_slp_instance): Re-use it here.
14378 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14380 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning.
14382 2020-01-28 Vladimir Makarov <vmakarov@redhat.com>
14384 PR rtl-optimization/93272
14385 * ira-lives.c (process_out_of_region_eh_regs): New function.
14386 (process_bb_node_lives): Call it.
14388 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14390 * coverage.c (read_counts_file): Make error message lowercase.
14392 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14394 * profile-count.c (profile_quality_display_names): Fix ordering.
14396 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14399 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site
14400 hash only when edge is first within the sequence.
14401 (cgraph_edge::set_call_stmt): Update handling of speculative calls.
14402 (symbol_table::create_edge): Do not set target_prob.
14403 (cgraph_edge::remove_caller): Watch for speculative calls when updating
14404 the call site hash.
14405 (cgraph_edge::make_speculative): Drop target_prob parameter.
14406 (cgraph_edge::speculative_call_info): Remove.
14407 (cgraph_edge::first_speculative_call_target): New member function.
14408 (update_call_stmt_hash_for_removing_direct_edge): New function.
14409 (cgraph_edge::resolve_speculation): Rewrite to new API.
14410 (cgraph_edge::speculative_call_for_target): New member function.
14411 (cgraph_edge::make_direct): Rewrite to new API; fix handling of
14412 multiple speculation targets.
14413 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating
14415 (verify_speculative_call): Verify that targets form an interval.
14416 * cgraph.h (cgraph_edge::speculative_call_info): Remove.
14417 (cgraph_edge::first_speculative_call_target): New member function.
14418 (cgraph_edge::next_speculative_call_target): New member function.
14419 (cgraph_edge::speculative_call_target_ref): New member function.
14420 (cgraph_edge;:speculative_call_indirect_edge): New member funtion.
14421 (cgraph_edge): Remove target_prob.
14422 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
14423 Fix handling of speculative calls.
14424 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals.
14425 * ipa-fnsummary.c (analyze_function_body): Likewise.
14426 * ipa-inline.c (speculation_useful_p): Use new speculative call API.
14427 * ipa-profile.c (dump_histogram): Fix formating.
14428 (ipa_profile_generate_summary): Watch for overflows.
14429 (ipa_profile): Do not require probablity to be 1/2; update to new API.
14430 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API.
14431 (update_indirect_edges_after_inlining): Update to new API.
14432 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call
14434 * profile-count.h: (profile_probability::adjusted): New.
14435 * tree-inline.c (copy_bb): Update to new speculative call API; fix
14436 updating of profile.
14437 * value-prof.c (gimple_ic_transform): Rename to ...
14438 (dump_ic_profile): ... this one; update dumping.
14439 (stream_in_histogram_value): Fix formating.
14440 (gimple_value_profile_transformations): Update.
14442 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
14445 * config/i386/i386.md (*movoi_internal_avx): Remove
14446 TARGET_SSE_TYPELESS_STORES check.
14447 (*movti_internal): Prefer TARGET_AVX over
14448 TARGET_SSE_TYPELESS_STORES.
14449 (*movtf_internal): Likewise.
14450 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over
14451 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check
14452 from TARGET_SSE_TYPELESS_STORES.
14454 2020-01-28 David Malcolm <dmalcolm@redhat.com>
14456 * diagnostic-core.h (warning_at): Rename overload to...
14457 (warning_meta): ...this.
14458 (emit_diagnostic_valist): Delete decl of overload taking
14459 diagnostic_metadata.
14460 * diagnostic.c (emit_diagnostic_valist): Likewise for defn.
14461 (warning_at): Rename overload taking diagnostic_metadata to...
14462 (warning_meta): ...this.
14464 2020-01-28 Richard Biener <rguenther@suse.de>
14466 PR tree-optimization/93439
14467 * tree-parloops.c (create_loop_fn): Move clique bookkeeping...
14468 * tree-cfg.c (move_sese_region_to_fn): ... here.
14469 (verify_types_in_gimple_reference): Verify used cliques are
14472 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
14475 * config/i386/i386-options.c (set_ix86_tune_features): Add an
14476 argument of a pointer to struct gcc_options and pass it to
14477 parse_mtune_ctrl_str.
14478 (ix86_function_specific_restore): Pass opts to
14479 set_ix86_tune_features.
14480 (ix86_option_override_internal): Likewise.
14481 (parse_mtune_ctrl_str): Add an argument of a pointer to struct
14482 gcc_options and use it for x_ix86_tune_ctrl_string.
14484 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14486 PR rtl-optimization/87763
14487 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
14488 simplification to handle subregs as well as bare regs.
14489 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
14491 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14493 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully
14494 for reduction chains that (now) include a call.
14496 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14498 PR tree-optimization/92822
14499 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling
14500 out the don't-care elements of a vector whose significant elements
14501 are duplicates, make the don't-care elements duplicates too.
14503 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14505 PR tree-optimization/93434
14506 * tree-predcom.c (split_data_refs_to_components): Record which
14507 components have had aliasing loads removed. Prevent store-store
14508 commoning for all such components.
14510 2020-01-28 Jakub Jelinek <jakub@redhat.com>
14513 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not
14514 -1 or is_vshift is true, use new_vector with number of elts npatterns
14515 rather than new_unary_operation.
14517 PR tree-optimization/93454
14518 * gimple-fold.c (fold_array_ctor_reference): Perform
14519 elt_size.to_uhwi () just once, instead of calling it in every
14520 iteration. Punt if that value is above size of the temporary
14521 buffer. Decrease third native_encode_expr argument when
14522 bufoff + elt_sz is above size of buf.
14524 2020-01-27 Joseph Myers <joseph@codesourcery.com>
14526 * config/mips/mips.c (mips_declare_object_name)
14527 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object.
14529 2020-01-27 Martin Liska <mliska@suse.cz>
14531 PR gcov-profile/93403
14532 * tree-profile.c (gimple_init_gcov_profiler): Generate
14533 both __gcov_indirect_call_profiler_v4 and
14534 __gcov_indirect_call_profiler_v4_atomic.
14536 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
14539 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
14541 (@aarch64_split_simd_mov<mode>): Use it.
14542 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
14543 Leave the vec_extract patterns to handle 2-element vectors.
14544 (aarch64_simd_mov_from_<mode>high): Likewise.
14545 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
14546 (vec_extractv2dfv1df): Likewise.
14548 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
14550 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match
14551 jump conditions for *compare_condjump<GPI:mode>.
14553 2020-01-27 David Malcolm <dmalcolm@redhat.com>
14556 * digraph.cc (test_edge::test_edge): Specify template for base
14559 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
14561 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost.
14563 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
14565 * config/arc/arc-protos.h (gen_mlo): Remove.
14566 (gen_mhi): Likewise.
14567 * config/arc/arc.c (AUX_MULHI): Define.
14568 (arc_must_save_reister): Special handling for r58/59.
14569 (arc_compute_frame_size): Consider mlo/mhi registers.
14570 (arc_save_callee_saves): Emit fp/sp move only when emit_move
14572 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from
14573 mlo/mhi name selection.
14574 (arc_restore_callee_saves): Don't early restore blink when ISR.
14575 (arc_expand_prologue): Add mlo/mhi saving.
14576 (arc_expand_epilogue): Add mlo/mhi restoring.
14579 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register
14580 numbering when MUL64 option is used.
14581 (DWARF2_FRAME_REG_OUT): Define.
14582 * config/arc/arc.md (arc600_stall): New pattern.
14583 (VUNSPEC_ARC_ARC600_STALL): Define.
14584 (mulsi64): Use correct mlo/mhi registers.
14585 (mulsi_600): Clean it up.
14586 * config/arc/predicates.md (mlo_operand): Remove any dependency on
14588 (mhi_operand): Likewise.
14590 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
14591 Petro Karashchenko <petro.karashchenko@ring.com>
14593 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct
14594 attributes if needed.
14595 (prepare_move_operands): Generate special unspec instruction for
14597 (arc_isuncached_mem_p): Propagate uncached attribute to each
14599 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
14600 (VUNSPEC_ARC_STDI): Likewise.
14601 (ALLI): New mode iterator.
14602 (mALLI): New mode attribute.
14603 (lddi): New instruction pattern.
14605 (stdidi_split): Split instruction for architectures which are not
14606 supporting ll64 option.
14607 (lddidi_split): Likewise.
14609 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
14611 PR rtl-optimization/92989
14612 * lra-lives.c (process_bb_lives): Update the live-in set before
14613 processing additional clobbers.
14615 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
14617 PR rtl-optimization/93170
14618 * cselib.c (cselib_invalidate_regno_val): New function, split out
14620 (cselib_invalidate_regno): ...here.
14621 (cselib_invalidated_by_call_p): New function.
14622 (cselib_process_insn): Iterate over all the hard-register entries in
14623 REG_VALUES and invalidate any that cross call-clobbered registers.
14625 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
14627 * dojump.c (split_comparison): Use HONOR_NANS rather than
14628 HONOR_SNANS when splitting LTGT.
14630 2020-01-27 Martin Liska <mliska@suse.cz>
14633 * opts.c (print_filtered_help): Exclude language-specific
14634 options from --help=common unless enabled in all FEs.
14636 2020-01-27 Martin Liska <mliska@suse.cz>
14638 * opts.c (print_help): Exclude params from
14639 all except --help=param.
14641 2020-01-27 Martin Liska <mliska@suse.cz>
14644 * config/i386/i386-features.c (make_resolver_func):
14645 Align the code with ppc64 target implementation.
14646 Do not generate a unique name for resolver function.
14648 2020-01-27 Richard Biener <rguenther@suse.de>
14650 PR tree-optimization/93397
14651 * tree-vect-slp.c (vect_analyze_slp_instance): Delay
14652 converted reduction chain SLP graph adjustment.
14654 2020-01-26 Marek Polacek <polacek@redhat.com>
14657 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on
14660 2020-01-26 Jason Merrill <jason@redhat.com>
14663 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING
14666 2020-01-26 Darius Galis <darius.galis@cyberthorstudios.com>
14668 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint
14669 (rx_setmem): Likewise.
14671 2020-01-26 Jakub Jelinek <jakub@redhat.com>
14674 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword):
14675 Use nonimmediate_operand instead of x86_64_hilo_general_operand and
14676 drop <di> from constraint of last operand.
14679 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for
14680 TARGET_AVX2 and V4DFmode not in the split condition, but in the
14681 pattern condition, though allow { 0, 0, 0, 0 } broadcast always.
14683 2020-01-25 Feng Xue <fxue@os.amperecomputing.com>
14686 * ipa-cp.c (get_info_about_necessary_edges): Remove value
14689 2020-01-24 Jeff Law <law@redhat.com>
14691 PR tree-optimization/92788
14692 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX
14695 2020-01-24 Jakub Jelinek <jakub@redhat.com>
14698 * config/i386/sse.md (*avx_vperm_broadcast_v4sf,
14699 *avx_vperm_broadcast_<mode>,
14700 <sse2_avx_avx512f>_vpermil<mode><mask_name>,
14701 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>):
14702 Move before avx2_perm<mode>/avx512f_perm<mode>.
14705 * simplify-rtx.c (simplify_const_unary_operation,
14706 simplify_const_binary_operation): Punt for mode precision above
14707 MAX_BITSIZE_MODE_ANY_INT.
14709 2020-01-24 Andrew Pinski <apinski@marvell.com>
14711 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change
14712 alu.shift_reg to 0.
14714 2020-01-24 Jeff Law <law@redhat.com>
14717 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg
14718 for REGs. Call output_operand_lossage to get more reasonable
14721 2020-01-24 Andrew Stubbs <ams@codesourcery.com>
14723 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use
14724 gcn_fp_compare_operator.
14725 (vec_cmpu<mode>di): Use gcn_compare_operator.
14726 (vec_cmp<u>v64qidi): Use gcn_compare_operator.
14727 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator.
14728 (vec_cmpu<mode>di_exec): Use gcn_compare_operator.
14729 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator.
14730 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator.
14731 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator.
14732 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use
14733 gcn_fp_compare_operator.
14734 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use
14735 gcn_fp_compare_operator.
14736 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use
14737 gcn_fp_compare_operator.
14738 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use
14739 gcn_fp_compare_operator.
14741 2020-01-24 Maciej W. Rozycki <macro@wdc.com>
14743 * doc/install.texi (Cross-Compiler-Specific Options): Document
14744 `--with-toolexeclibdir' option.
14746 2020-01-24 Hans-Peter Nilsson <hp@axis.com>
14748 * target.def (flags_regnum): Also mention effect on delay slot filling.
14749 * doc/tm.texi: Regenerate.
14751 2020-01-23 Jeff Law <law@redhat.com>
14753 PR translation/90162
14754 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text.
14756 2020-01-23 Mikael Tillenius <mti-1@tillenius.com>
14759 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of
14762 2020-01-23 Jakub Jelinek <jakub@redhat.com>
14764 PR rtl-optimization/93402
14765 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust
14768 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
14770 * config.in: Regenerated.
14771 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
14772 for TARGET_LIBC_GNUSTACK.
14773 * configure: Regenerated.
14774 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
14775 found to be 2.31 or greater.
14777 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
14779 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
14781 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
14782 (mips_asm_file_end): New function. Delegate to
14783 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
14784 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.
14786 2020-01-23 Jakub Jelinek <jakub@redhat.com>
14789 * config/i386/i386-modes.def (POImode): New mode.
14790 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160.
14791 * config/i386/i386.md (DPWI): New mode attribute.
14792 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>.
14793 (QWI): Rename to...
14794 (QPWI): ... this. Use POI instead of OI for TImode.
14795 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1,
14796 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI>
14799 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
14802 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New
14804 (speculation_tracker_rev): New pattern.
14805 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation):
14806 Use speculation_tracker_rev to track the inverse condition.
14808 2020-01-23 Richard Biener <rguenther@suse.de>
14810 PR tree-optimization/93381
14811 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take
14812 alias-set of the def as argument and record the first one.
14813 (vn_walk_cb_data::first_set): New member.
14814 (vn_reference_lookup_3): Pass the alias-set of the current def
14815 to push_partial_def. Fix alias-set used in the aggregate copy
14817 (vn_reference_lookup): Consistently set *last_vuse_ptr.
14818 * real.c (clear_significand_below): Fix out-of-bound access.
14820 2020-01-23 Jakub Jelinek <jakub@redhat.com>
14823 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3):
14824 New define_insn patterns.
14826 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
14828 * doc/sourcebuild.texi (check-function-bodies): Add an
14829 optional target/xfail selector.
14831 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
14833 PR rtl-optimization/93124
14834 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to
14835 bare USE and CLOBBER insns.
14837 2020-01-22 Andrew Pinski <apinski@marvell.com>
14839 * config/arc/arc.c (output_short_suffix): Check insn for nullness.
14841 2020-01-22 David Malcolm <dmalcolm@redhat.com>
14844 * gdbinit.in (break-on-saved-diagnostic): Update for move of
14845 diagnostic_manager into "ana" namespace.
14846 * selftest-run-tests.c (selftest::run_tests): Update for move of
14847 selftest::run_analyzer_selftests to
14848 ana::selftest::run_analyzer_selftests.
14850 2020-01-22 Richard Sandiford <richard.sandiford@arm.com>
14852 * cfgexpand.c (union_stack_vars): Update the size.
14854 2020-01-22 Richard Biener <rguenther@suse.de>
14856 PR tree-optimization/93381
14857 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting
14858 throughout, handle all conversions the same.
14860 2020-01-22 Jakub Jelinek <jakub@redhat.com>
14863 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use
14864 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate
14865 predicate, not whenever it is CONST_INT. Otherwise, force_reg it.
14866 Call force_reg on high_in2 unconditionally.
14868 2020-01-22 Martin Liska <mliska@suse.cz>
14870 PR tree-optimization/92924
14871 * profile.c (compute_value_histograms): Divide
14872 all counter values.
14874 2020-01-22 Jakub Jelinek <jakub@redhat.com>
14877 * output.h (assemble_name_resolve): Declare.
14878 * varasm.c (assemble_name_resolve): New function.
14879 (assemble_name): Use it.
14880 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define.
14882 2020-01-22 Joseph Myers <joseph@codesourcery.com>
14884 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to
14885 update_web_docs_git instead of update_web_docs_svn.
14887 2020-01-21 Andrew Pinski <apinski@marvell.com>
14890 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
14891 as PTR mode. Have operand 1 as being modeless, it can be P mode.
14892 (*tlsgd_small_<mode>): Likewise.
14893 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
14894 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
14895 register. Convert that register back to dest using convert_mode.
14897 2020-01-21 Jim Wilson <jimw@sifive.com>
14899 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
14902 2020-01-21 H.J. Lu <hongjiu.lu@intel.com>
14903 Uros Bizjak <ubizjak@gmail.com>
14906 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode
14908 (legitimize_tls_address): Do GNU2 TLS address computation in
14909 ptr_mode and zero-extend result to Pmode.
14910 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace
14911 :P with :PTR and Pmode with ptr_mode.
14912 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise.
14913 (*tls_dynamic_gnu2_call_64_<mode>): Likewise.
14914 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise.
14916 2020-01-21 Jakub Jelinek <jakub@redhat.com>
14919 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify
14920 the last two operands are CONST_INT_P before using them as such.
14922 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
14924 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name
14925 to get the integer element types.
14927 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
14929 * config/aarch64/aarch64-sve-builtins.h
14930 (function_expander::convert_to_pmode): Declare.
14931 * config/aarch64/aarch64-sve-builtins.cc
14932 (function_expander::convert_to_pmode): New function.
14933 (function_expander::get_contiguous_base): Use it.
14934 (function_expander::prepare_gather_address_operands): Likewise.
14935 * config/aarch64/aarch64-sve-builtins-sve2.cc
14936 (svwhilerw_svwhilewr_impl::expand): Likewise.
14938 2020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com>
14941 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set
14942 cfun->machine->label_is_assembled.
14943 (aarch64_print_patchable_function_entry): New.
14944 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define.
14945 * config/aarch64/aarch64.h (struct machine_function): New field,
14946 label_is_assembled.
14948 2020-01-21 David Malcolm <dmalcolm@redhat.com>
14951 * ipa-profile.c (ipa_profile): Delete call_sums and set it to
14954 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
14957 * cgraph.c (cgraph_edge::resolve_speculation,
14958 cgraph_edge::redirect_call_stmt_to_callee): Fix update of
14959 call_stmt_site_hash.
14961 2020-01-21 Martin Liska <mliska@suse.cz>
14963 * config/rs6000/rs6000.c (common_mode_defined): Remove
14966 2020-01-21 Richard Biener <rguenther@suse.de>
14968 PR tree-optimization/92328
14969 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve
14970 type when value-numbering same-sized store by inserting a
14972 (eliminate_dom_walker::eliminate_stmt): When eliminating
14973 a redundant store handle bit-reinterpretation of the same value.
14975 2020-01-21 Andrew Pinski <apinski@marvel.com>
14978 * tree-into-ssa.c (prepare_block_for_update_1): Split out
14980 (prepare_block_for_update): This. Use a worklist instead of
14983 2020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
14985 * config/arm/arm.c (clear_operation_p):
14986 Initialise last_regno, skip first iteration
14987 based on the first_set value and use ints instead
14988 of the unnecessary HOST_WIDE_INTs.
14990 2020-01-21 Jakub Jelinek <jakub@redhat.com>
14993 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for
14994 compare_mode other than SFmode or DFmode.
14996 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
14999 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
15000 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
15001 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
15003 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15005 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
15007 2020-01-20 Andrew Pinski <apinski@marvell.com>
15009 PR middle-end/93242
15010 * targhooks.c (default_print_patchable_function_entry): Use
15011 output_asm_insn to emit the nop instruction.
15013 2020-01-20 Fangrui Song <maskray@google.com>
15015 PR middle-end/93194
15016 * targhooks.c (default_print_patchable_function_entry): Align to
15019 2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
15022 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to
15023 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode.
15024 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ...
15025 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P.
15026 (*tls_dynamic_gnu2_lea_64): Renamed to ...
15027 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P.
15028 Remove the {q} suffix from lea.
15029 (*tls_dynamic_gnu2_call_64): Renamed to ...
15030 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P.
15031 (*tls_dynamic_gnu2_combine_64): Renamed to ...
15032 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P.
15033 Pass Pmode to gen_tls_dynamic_gnu2_64.
15035 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15037 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1.
15039 2020-01-20 Richard Sandiford <richard.sandiford@arm.com>
15041 * config/aarch64/aarch64-sve-builtins-base.cc
15042 (svld1ro_impl::memory_vector_mode): Remove parameter name.
15044 2020-01-20 Richard Biener <rguenther@suse.de>
15047 * dwarf2out.c (prune_unused_types): Unconditionally mark
15048 called function DIEs.
15050 2020-01-20 Martin Liska <mliska@suse.cz>
15052 PR tree-optimization/93199
15053 * tree-eh.c (struct leh_state): Add
15054 new field outer_non_cleanup.
15055 (cleanup_is_dead_in): Pass leh_state instead
15056 of eh_region. Add a checking that state->outer_non_cleanup
15057 points to outer non-clean up region.
15058 (lower_try_finally): Record outer_non_cleanup
15060 (lower_catch): Likewise.
15061 (lower_eh_filter): Likewise.
15062 (lower_eh_must_not_throw): Likewise.
15063 (lower_cleanup): Likewise.
15065 2020-01-20 Richard Biener <rguenther@suse.de>
15067 PR tree-optimization/93094
15068 * tree-vectorizer.h (vect_loop_versioning): Adjust.
15069 (vect_transform_loop): Likewise.
15070 * tree-vectorizer.c (try_vectorize_loop_1): Pass down
15071 loop_vectorized_call to vect_transform_loop.
15072 * tree-vect-loop.c (vect_transform_loop): Pass down
15073 loop_vectorized_call to vect_loop_versioning.
15074 * tree-vect-loop-manip.c (vect_loop_versioning): Use
15075 the earlier discovered loop_vectorized_call.
15077 2020-01-19 Eric S. Raymond <esr@thyrsus.com>
15079 * doc/contribute.texi: Update for SVN -> Git transition.
15080 * doc/install.texi: Likewise.
15082 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15085 * cgraph.c (cgraph_edge::make_speculative): Increase number of
15086 speculative targets.
15087 (verify_speculative_call): New function
15088 (cgraph_node::verify_node): Use it.
15089 * ipa-profile.c (ipa_profile): Fix formating; do not set number of
15092 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15095 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting.
15096 (cgraph_edge::make_direct): Remove all indirect targets.
15097 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct..
15098 (cgraph_node::verify_node): Verify that only one call_stmt or
15099 lto_stmt_uid is set.
15100 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or
15102 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt.
15103 (lto_output_ref): Simplify streaming of stmt.
15104 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid.
15106 2020-01-18 Tamar Christina <tamar.christina@arm.com>
15108 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode):
15109 Mark parameter unused.
15111 2020-01-18 Hans-Peter Nilsson <hp@axis.com>
15113 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux*
15115 2019-01-18 Gerald Pfeifer <gerald@pfeifer.com>
15117 * varpool.c (ctor_useable_for_folding_p): Fix grammar.
15119 2020-01-18 Iain Sandoe <iain@sandoe.co.uk>
15121 * Makefile.in: Add coroutine-passes.o.
15122 * builtin-types.def (BT_CONST_SIZE): New.
15123 (BT_FN_BOOL_PTR): New.
15124 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New.
15125 * builtins.def (DEF_COROUTINE_BUILTIN): New.
15126 * coroutine-builtins.def: New file.
15127 * coroutine-passes.cc: New file.
15128 * function.h (struct GTY function): Add a bit to indicate that the
15129 function is a coroutine component.
15130 * internal-fn.c (expand_CO_FRAME): New.
15131 (expand_CO_YIELD): New.
15132 (expand_CO_SUSPN): New.
15133 (expand_CO_ACTOR): New.
15134 * internal-fn.def (CO_ACTOR): New.
15138 * passes.def: Add pass_coroutine_lower_builtins,
15139 pass_coroutine_early_expand_ifns.
15140 * tree-pass.h (make_pass_coroutine_lower_builtins): New.
15141 (make_pass_coroutine_early_expand_ifns): New.
15142 * doc/invoke.texi: Document the fcoroutines command line
15145 2020-01-18 Jakub Jelinek <jakub@redhat.com>
15147 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable.
15150 * config/arm/arm.c (clear_operation_p): Don't use REGNO until
15151 after checking the argument is a REG. Don't use REGNO (reg)
15152 again to set last_regno, reuse regno variable instead.
15154 2020-01-17 David Malcolm <dmalcolm@redhat.com>
15156 * doc/analyzer.texi (Limitations): Add note about NaN.
15158 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15159 Sudakshina Das <sudi.das@arm.com>
15161 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
15162 and valid immediate.
15163 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
15164 (lshrdi3): Generate thumb2_lsrl for valid immediates.
15165 * config/arm/constraints.md (Pg): New.
15166 * config/arm/predicates.md (long_shift_imm): New.
15167 (arm_reg_or_long_shift_imm): Likewise.
15168 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
15169 (thumb2_lsll): Likewise.
15170 (thumb2_lsrl): New.
15172 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15173 Sudakshina Das <sudi.das@arm.com>
15175 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
15176 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
15177 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
15178 register pairs for doubleword quantities for ARMv8.1M-Mainline.
15179 * config/arm/thumb2.md (thumb2_asrl): New.
15180 (thumb2_lsll): Likewise.
15182 2020-01-17 Jakub Jelinek <jakub@redhat.com>
15184 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
15187 2020-01-17 Alexander Monakov <amonakov@ispras.ru>
15189 * gdbinit.in (help-gcc-hooks): New command.
15190 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
15191 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
15194 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15196 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the
15197 correct target macro.
15199 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15201 * config/aarch64/aarch64-protos.h
15202 (aarch64_sve_ld1ro_operand_p): New.
15203 * config/aarch64/aarch64-sve-builtins-base.cc
15204 (class load_replicate): New.
15205 (class svld1ro_impl): New.
15206 (class svld1rq_impl): Change to inherit from load_replicate.
15207 (svld1ro): New sve intrinsic function base.
15208 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
15209 New DEF_SVE_FUNCTION.
15210 * config/aarch64/aarch64-sve-builtins-base.h
15211 (svld1ro): New decl.
15212 * config/aarch64/aarch64-sve-builtins.cc
15213 (function_expander::add_mem_operand): Modify assert to allow
15215 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
15217 * config/aarch64/aarch64.c
15218 (aarch64_sve_ld1rq_operand_p): Implement in terms of ...
15219 (aarch64_sve_ld1rq_ld1ro_operand_p): This.
15220 (aarch64_sve_ld1ro_operand_p): New.
15221 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
15222 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
15223 * config/aarch64/predicates.md
15224 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New.
15226 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15228 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
15229 Introduce this ACLE specified predefined macro.
15230 * config/aarch64/aarch64-option-extensions.def (f64mm): New.
15231 (fp): Disabling this disables f64mm.
15232 (simd): Disabling this disables f64mm.
15233 (fp16): Disabling this disables f64mm.
15234 (sve): Disabling this disables f64mm.
15235 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
15236 (AARCH64_ISA_F64MM): New.
15237 (TARGET_F64MM): New.
15238 * doc/invoke.texi (f64mm): Document new option.
15240 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
15242 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
15243 (neoversen1_tunings): Likewise.
15245 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
15248 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
15249 Add assert to ensure prolog has been emitted.
15250 (aarch64_split_atomic_op): Likewise.
15251 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
15252 Use epilogue_completed rather than reload_completed.
15253 (aarch64_atomic_exchange<mode>): Likewise.
15254 (aarch64_atomic_<atomic_optab><mode>): Likewise.
15255 (atomic_nand<mode>): Likewise.
15256 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
15257 (atomic_fetch_nand<mode>): Likewise.
15258 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
15259 (atomic_nand_fetch<mode>): Likewise.
15261 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
15264 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
15266 (REVERSE_CONDITION): Delete.
15267 * config/aarch64/iterators.md (CC_ONLY): New mode iterator.
15268 (CCFP_CCFPE): Likewise.
15269 (e): New mode attribute.
15270 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
15271 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
15272 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
15273 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
15274 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
15275 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
15276 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
15277 name of generator from gen_ccmpdi to gen_ccmpccdi.
15278 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse
15279 the previous comparison but aren't able to, use the new ccmp_rev
15282 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
15284 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
15285 than testing directly for INTEGER_CST.
15286 (gimplify_target_expr, gimplify_omp_depend): Likewise.
15288 2020-01-17 Jakub Jelinek <jakub@redhat.com>
15290 PR tree-optimization/93292
15291 * tree-vect-stmts.c (vectorizable_comparison): Punt also if
15292 get_vectype_for_scalar_type returns NULL.
15294 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
15296 * params.opt (-param=max-predicted-iterations): Increase range from 0.
15297 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.
15299 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
15301 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
15303 * params.opt: (max-predicted-iterations): Set bounds.
15304 * predict.c (real_almost_one, real_br_prob_base,
15305 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
15306 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic
15307 probabilities; do not truncate to reg_br_prob_bases.
15308 (estimate_loops_at_level): Pass max_cyclic_prob.
15309 (estimate_loops): Compute max_cyclic_prob.
15310 (estimate_bb_frequencies): Do not initialize real_*; update calculation
15312 * profile-count.c (profile_probability::to_sreal): New.
15313 * profile-count.h (class sreal): Move up in file.
15314 (profile_probability::to_sreal): Declare.
15316 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15319 (arm_invalid_conversion): New function for target hook.
15320 (arm_invalid_unary_op): New function for target hook.
15321 (arm_invalid_binary_op): New function for target hook.
15323 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15325 * config.gcc: Add arm_bf16.h.
15326 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
15327 (arm_simd_builtin_std_type): Add BFmode.
15328 (arm_init_simd_builtin_types): Define element types for vector types.
15329 (arm_init_bf16_types): New function.
15330 (arm_init_builtins): Add arm_init_bf16_types function call.
15331 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
15332 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
15333 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode.
15334 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
15335 (arm_vector_mode_supported_p): Add V4BF, V8BF.
15336 (arm_mangle_type): Add __bf16.
15337 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
15338 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
15339 arm_bf16_ptr_type_node.
15340 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
15341 define_split between ARM registers.
15342 * config/arm/arm_bf16.h: New file.
15343 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
15344 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
15345 (VQXMOV): Add V8BF.
15346 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
15347 * config/arm/vfp.md: Add BFmode to movhf patterns.
15349 2020-01-16 Mihail Ionescu <mihail.ionescu@arm.com>
15350 Andre Vieira <andre.simoesdiasvieira@arm.com>
15352 * config/arm/arm-cpus.in (mve, mve_float): New features.
15353 (dsp, mve, mve.fp): New options.
15354 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
15355 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
15356 * doc/invoke.texi: Document the armv8.1-m mve and dps options.
15358 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15359 Thomas Preud'homme <thomas.preudhomme@arm.com>
15361 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
15363 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
15364 error for using -mcmse when targeting Armv8.1-M Mainline.
15366 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15367 Thomas Preud'homme <thomas.preudhomme@arm.com>
15369 * config/arm/arm.md (nonsecure_call_internal): Do not force memory
15370 address in r4 when targeting Armv8.1-M Mainline.
15371 (nonsecure_call_value_internal): Likewise.
15372 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
15373 a register match_operand again. Emit BLXNS when targeting
15374 Armv8.1-M Mainline.
15375 (nonsecure_call_value_reg_thumb2): Likewise.
15377 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15378 Thomas Preud'homme <thomas.preudhomme@arm.com>
15380 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
15381 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
15382 variable as true when floating-point ABI is not hard. Replace
15383 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
15384 Generate VLSTM and VLLDM instruction respectively before and
15385 after a function call to cmse_nonsecure_call function.
15386 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
15387 (VUNSPEC_VLLDM): Likewise.
15388 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
15389 (lazy_load_multiple_insn): Likewise.
15391 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15392 Thomas Preud'homme <thomas.preudhomme@arm.com>
15394 * config/arm/arm.c (vfp_emit_fstmd): Declare early.
15395 (arm_emit_vfp_multi_reg_pop): Likewise.
15396 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
15397 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and
15398 restore callee-saved VFP registers.
15400 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15401 Thomas Preud'homme <thomas.preudhomme@arm.com>
15403 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
15404 (cmse_nonsecure_call_clear_caller_saved): Rename into ...
15405 (cmse_nonsecure_call_inline_register_clear): This. Save and clear
15406 callee-saved GPRs as well as clear ip register before doing a nonsecure
15407 call then restore callee-saved GPRs after it when targeting
15408 Armv8.1-M Mainline.
15409 (arm_reorg): Adapt to function rename.
15411 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15412 Thomas Preud'homme <thomas.preudhomme@arm.com>
15414 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
15415 * config/arm/arm.c (clear_operation_p): Extend to be able to check a
15416 clear_vfp_multiple pattern based on a new vfp parameter.
15417 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
15418 targeting Armv8.1-M Mainline.
15419 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers
15420 unconditionally when targeting Armv8.1-M Mainline architecture. Check
15421 whether VFP registers are available before looking call_used_regs for a
15423 * config/arm/predicates.md (clear_multiple_operation): Adapt to change
15424 of prototype of clear_operation_p.
15425 (clear_vfp_multiple_operation): New predicate.
15426 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
15427 * config/arm/vfp.md (clear_vfp_multiple): New define_insn.
15429 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15430 Thomas Preud'homme <thomas.preudhomme@arm.com>
15432 * config/arm/arm-protos.h (clear_operation_p): Declare.
15433 * config/arm/arm.c (clear_operation_p): New function.
15434 (cmse_clear_registers): Generate clear_multiple instruction pattern if
15435 targeting Armv8.1-M Mainline or successor.
15436 (output_return_instruction): Only output APSR register clearing if
15437 Armv8.1-M Mainline instructions not available.
15438 (thumb_exit): Likewise.
15439 * config/arm/predicates.md (clear_multiple_operation): New predicate.
15440 * config/arm/thumb2.md (clear_apsr): New define_insn.
15441 (clear_multiple): Likewise.
15442 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.
15444 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15445 Thomas Preud'homme <thomas.preudhomme@arm.com>
15447 * config/arm/arm.c (fp_sysreg_names): Declare and define.
15448 (use_return_insn): Also return false for Armv8.1-M Mainline.
15449 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M
15450 Mainline instructions are available.
15451 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS
15452 when targeting Armv8.1-M Mainline Security Extensions.
15453 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
15454 Mainline entry function.
15455 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
15456 targeting Armv8.1-M Mainline or successor.
15457 (arm_expand_epilogue): Fix indentation of caller-saved register
15458 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline
15460 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
15461 (FP_SYSREGS): Likewise.
15462 (enum vfp_sysregs_encoding): Define enum.
15463 (fp_sysreg_names): Declare.
15464 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
15465 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
15466 (pop_fpsysreg_insn): Likewise.
15468 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15469 Thomas Preud'homme <thomas.preudhomme@arm.com>
15471 * config/arm/arm-cpus.in (armv8_1m_main): New feature.
15472 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
15473 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
15474 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
15475 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
15476 (ARMv8_1m_main): New feature group.
15477 (armv8.1-m.main): New architecture.
15478 * config/arm/arm-tables.opt: Regenerate.
15479 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
15480 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
15481 (arm_options_perform_arch_sanity_checks): Error out when targeting
15482 Armv8.1-M Mainline Security Extensions.
15483 * config/arm/arm.h (arm_arch8_1m_main): Declare.
15485 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15487 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
15488 aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
15489 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
15490 aarch64_bfdot_laneq): New.
15491 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
15492 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
15493 vbfdotq_laneq_f32): New.
15494 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
15495 VBFMLA_W, VBF): New.
15496 (isquadop): Add V4BF, V8BF.
15498 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15500 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
15501 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
15502 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
15503 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
15504 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
15505 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
15506 usdot_laneq, sudot_lane,sudot_laneq): New.
15507 * config/aarch64/aarch64-simd.md (aarch64_usdot): New.
15508 (aarch64_<sur>dot_lane): New.
15509 * config/aarch64/arm_neon.h (vusdot_s32): New.
15510 (vusdotq_s32): New.
15511 (vusdot_lane_s32): New.
15512 (vsudot_lane_s32): New.
15513 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
15514 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.
15516 2020-01-16 Martin Liska <mliska@suse.cz>
15518 * value-prof.c (dump_histogram_value): Fix
15519 obvious spacing issue.
15521 2020-01-16 Andrew Pinski <apinski@marvell.com>
15523 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
15524 !storage_order_barrier_p.
15526 2020-01-16 Andrew Pinski <apinski@marvell.com>
15528 * sched-int.h (_dep): Add unused bit-field field for the padding.
15529 * sched-deps.c (init_dep_1): Init unused field.
15531 2020-01-16 Andrew Pinski <apinski@marvell.com>
15533 * optabs.h (create_expand_operand): Initialize target field also.
15535 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
15537 PR tree-optimization/92429
15538 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
15539 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
15541 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
15544 2020-01-16 Richard Sandiford <richard.sandiford@arm.com>
15546 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
15547 aarch64_sve_int_mode to each mode.
15549 2020-01-15 David Malcolm <dmalcolm@redhat.com>
15551 * doc/analyzer.texi (Overview): Add note about
15552 -fdump-ipa-analyzer.
15554 2020-01-15 Wilco Dijkstra <wdijkstr@arm.com>
15556 PR tree-optimization/93231
15557 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
15558 input_type is unsigned. Use tree_to_shwi for shift constant.
15559 Check CST_STRING element size is CHAR_TYPE_SIZE bits.
15560 (simplify_count_trailing_zeroes): Add test to handle known non-zero
15561 inputs more efficiently.
15563 2020-01-15 Uroš Bizjak <ubizjak@gmail.com>
15565 * config/i386/i386.md (*movsf_internal): Do not require
15566 SSE2 ISA for alternatives 14 and 15.
15568 2020-01-15 Richard Biener <rguenther@suse.de>
15570 PR middle-end/93273
15571 * tree-eh.c (sink_clobbers): If we already visited the destination
15572 block do not defer insertion.
15573 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for
15574 the purpose of defered insertion.
15576 2020-01-15 Jakub Jelinek <jakub@redhat.com>
15578 * BASE-VER: Bump to 10.0.1.
15580 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
15582 PR tree-optimization/93247
15583 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access
15584 type of the stmt that we're going to vectorize.
15586 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
15588 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a
15589 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent
15592 2020-01-15 Martin Liska <mliska@suse.cz>
15594 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow
15595 2 calls of streamer_read_hwi in a function call.
15597 2020-01-15 Richard Biener <rguenther@suse.de>
15599 * alias.c (record_alias_subset): Avoid redundant work when
15600 subset is already recorded.
15602 2020-01-14 David Malcolm <dmalcolm@redhat.com>
15604 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of
15605 the analyzer options provide CWE identifiers.
15607 2020-01-14 David Malcolm <dmalcolm@redhat.com>
15609 * tree-diagnostic-path.cc (path_summary::event_range::print):
15610 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers
15611 using get_pure_location.
15613 2020-01-15 Jakub Jelinek <jakub@redhat.com>
15615 PR tree-optimization/93262
15616 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins,
15617 perform head trimming only if the last argument is constant,
15618 either all ones, or larger or equal to head trim, in the latter
15619 case decrease the last argument by head_trim.
15621 PR tree-optimization/93249
15622 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h.
15623 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to
15624 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't
15625 perform head trim unless we can prove there are no '\0' chars
15626 from the source among the first head_trim chars.
15628 2020-01-14 David Malcolm <dmalcolm@redhat.com>
15630 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o.
15632 2020-01-15 Jakub Jelinek <jakub@redhat.com>
15635 * config/i386/sse.md
15636 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1,
15637 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1,
15638 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1,
15639 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use
15640 just a single alternative instead of two, make operands 1 and 2
15643 2020-01-14 Jan Hubicka <hubicka@ucw.cz>
15646 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and
15649 2020-01-14 David Malcolm <dmalcolm@redhat.com>
15651 * Makefile.in (lang_opt_files): Add analyzer.opt.
15652 (ANALYZER_OBJS): New.
15653 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o,
15654 tristate.o and ANALYZER_OBJS.
15655 (TEXI_GCCINT_FILES): Add analyzer.texi.
15656 * common.opt (-fanalyzer): New driver option.
15657 * config.in: Regenerate.
15658 * configure: Regenerate.
15659 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option.
15660 (gccdepdir): Also create depdir for "analyzer" subdir.
15661 * digraph.cc: New file.
15662 * digraph.h: New file.
15663 * doc/analyzer.texi: New file.
15664 * doc/gccint.texi ("Static Analyzer") New menu item.
15665 (analyzer.texi): Include it.
15666 * doc/invoke.texi ("Static Analyzer Options"): New list and new section.
15667 ("Warning Options"): Add static analysis warnings to the list.
15668 (-Wno-analyzer-double-fclose): New option.
15669 (-Wno-analyzer-double-free): New option.
15670 (-Wno-analyzer-exposure-through-output-file): New option.
15671 (-Wno-analyzer-file-leak): New option.
15672 (-Wno-analyzer-free-of-non-heap): New option.
15673 (-Wno-analyzer-malloc-leak): New option.
15674 (-Wno-analyzer-possible-null-argument): New option.
15675 (-Wno-analyzer-possible-null-dereference): New option.
15676 (-Wno-analyzer-null-argument): New option.
15677 (-Wno-analyzer-null-dereference): New option.
15678 (-Wno-analyzer-stale-setjmp-buffer): New option.
15679 (-Wno-analyzer-tainted-array-index): New option.
15680 (-Wno-analyzer-use-after-free): New option.
15681 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option.
15682 (-Wno-analyzer-use-of-uninitialized-value): New option.
15683 (-Wanalyzer-too-complex): New option.
15684 (-fanalyzer-call-summaries): New warning.
15685 (-fanalyzer-checker=): New warning.
15686 (-fanalyzer-fine-grained): New warning.
15687 (-fno-analyzer-state-merge): New warning.
15688 (-fno-analyzer-state-purge): New warning.
15689 (-fanalyzer-transitivity): New warning.
15690 (-fanalyzer-verbose-edges): New warning.
15691 (-fanalyzer-verbose-state-changes): New warning.
15692 (-fanalyzer-verbosity=): New warning.
15693 (-fdump-analyzer): New warning.
15694 (-fdump-analyzer-callgraph): New warning.
15695 (-fdump-analyzer-exploded-graph): New warning.
15696 (-fdump-analyzer-exploded-nodes): New warning.
15697 (-fdump-analyzer-exploded-nodes-2): New warning.
15698 (-fdump-analyzer-exploded-nodes-3): New warning.
15699 (-fdump-analyzer-supergraph): New warning.
15700 * doc/sourcebuild.texi (dg-require-dot): New.
15701 (dg-check-dot): New.
15702 * gdbinit.in (break-on-saved-diagnostic): New command.
15703 * graphviz.cc: New file.
15704 * graphviz.h: New file.
15705 * ordered-hash-map-tests.cc: New file.
15706 * ordered-hash-map.h: New file.
15707 * passes.def (pass_analyzer): Add before
15708 pass_ipa_whole_program_visibility.
15709 * selftest-run-tests.c (selftest::run_tests): Call
15710 selftest::ordered_hash_map_tests_cc_tests.
15711 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New
15713 * shortest-paths.h: New file.
15714 * timevar.def (TV_ANALYZER): New timevar.
15715 (TV_ANALYZER_SUPERGRAPH): Likewise.
15716 (TV_ANALYZER_STATE_PURGE): Likewise.
15717 (TV_ANALYZER_PLAN): Likewise.
15718 (TV_ANALYZER_SCC): Likewise.
15719 (TV_ANALYZER_WORKLIST): Likewise.
15720 (TV_ANALYZER_DUMP): Likewise.
15721 (TV_ANALYZER_DIAGNOSTICS): Likewise.
15722 (TV_ANALYZER_SHORTEST_PATHS): Likewise.
15723 * tree-pass.h (make_pass_analyzer): New decl.
15724 * tristate.cc: New file.
15725 * tristate.h: New file.
15727 2020-01-14 Uroš Bizjak <ubizjak@gmail.com>
15730 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for
15731 alternatives 9 and 10.
15733 2020-01-14 David Malcolm <dmalcolm@redhat.com>
15735 * attribs.c (excl_hash_traits::empty_zero_p): New static constant.
15736 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise.
15737 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise.
15738 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
15739 (selftest::hash_map_tests_c_tests): Call it.
15740 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p):
15741 New static constant, using the value of = H::empty_zero_p.
15742 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value
15743 from default_hash_traits <Value>.
15744 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value
15746 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise.
15747 * hash-table.h (hash_table::alloc_entries): Guard the loop of
15748 calls to mark_empty with !Descriptor::empty_zero_p.
15749 (hash_table::empty_slow): Conditionalize the memset call with a
15750 check that Descriptor::empty_zero_p; otherwise, loop through the
15751 entries calling mark_empty on them.
15752 * hash-traits.h (int_hash::empty_zero_p): New static constant.
15753 (pointer_hash::empty_zero_p): Likewise.
15754 (pair_hash::empty_zero_p): Likewise.
15755 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p):
15757 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise.
15758 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise.
15759 * profile.c (location_triplet_hash::empty_zero_p): Likewise.
15760 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise.
15761 (sanopt_tree_couple_hash::empty_zero_p): Likewise.
15762 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise.
15763 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise.
15764 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise.
15765 * tree-vectorizer.h
15766 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p):
15769 2020-01-14 Kewen Lin <linkw@gcc.gnu.org>
15771 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return,
15772 fix typo on return value.
15774 2020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
15777 * cgraph.c (symbol_table::create_edge): Init speculative_id and
15779 (cgraph_edge::make_speculative): Add param for setting speculative_id
15781 (cgraph_edge::speculative_call_info): Update comments and find reference
15782 by speculative_id for multiple indirect targets.
15783 (cgraph_edge::resolve_speculation): Decrease the speculations
15784 for indirect edge, drop it's speculative if not direct target
15785 left. Update comments.
15786 (cgraph_edge::redirect_call_stmt_to_callee): Likewise.
15787 (cgraph_node::dump): Print num_speculative_call_targets.
15788 (cgraph_node::verify_node): Don't report error if speculative
15789 edge not include statement.
15790 (cgraph_edge::num_speculative_call_targets_p): New function.
15791 * cgraph.h (int common_target_id): Remove.
15792 (int common_target_probability): Remove.
15793 (num_speculative_call_targets): New variable.
15794 (make_speculative): Add param for setting speculative_id.
15795 (cgraph_edge::num_speculative_call_targets_p): New declare.
15796 (target_prob): New variable.
15797 (speculative_id): New variable.
15798 * ipa-fnsummary.c (analyze_function_body): Create and duplicate
15799 call summaries for multiple speculative call targets.
15800 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id.
15801 * ipa-profile.c (struct speculative_call_target): New struct.
15802 (class speculative_call_summary): New class.
15803 (class speculative_call_summaries): New class.
15804 (call_sums): New variable.
15805 (ipa_profile_generate_summary): Generate indirect multiple targets summaries.
15806 (ipa_profile_write_edge_summary): New function.
15807 (ipa_profile_write_summary): Stream out indirect multiple targets summaries.
15808 (ipa_profile_dump_all_summaries): New function.
15809 (ipa_profile_read_edge_summary): New function.
15810 (ipa_profile_read_summary_section): New function.
15811 (ipa_profile_read_summary): Stream in indirect multiple targets summaries.
15812 (ipa_profile): Generate num_speculative_call_targets from
15814 * ipa-ref.h (speculative_id): New variable.
15815 * ipa-utils.c (ipa_merge_profiles): Update with target_prob.
15816 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and
15817 common_target_probability. Stream out speculative_id and
15818 num_speculative_call_targets.
15819 (input_edge): Likewise.
15820 * predict.c (dump_prediction): Remove edges count assert to be
15822 * symtab.c (symtab_node::create_reference): Init speculative_id.
15823 (symtab_node::clone_references): Clone speculative_id.
15824 (symtab_node::clone_referring): Clone speculative_id.
15825 (symtab_node::clone_reference): Clone speculative_id.
15826 (symtab_node::clear_stmts_in_references): Clear speculative_id.
15827 * tree-inline.c (copy_bb): Duplicate all the speculative edges
15828 if indirect call contains multiple speculative targets.
15829 * value-prof.h (check_ic_target): Remove.
15830 * value-prof.c (gimple_value_profile_transformations):
15831 Use void function gimple_ic_transform.
15832 * value-prof.c (gimple_ic_transform): Handle topn case.
15833 Fix comment typos. Change it to a void function.
15835 2020-01-13 Andrew Pinski <apinski@marvell.com>
15837 * config/aarch64/aarch64-cores.def (octeontx2): New define.
15838 (octeontx2t98): New define.
15839 (octeontx2t96): New define.
15840 (octeontx2t93): New define.
15841 (octeontx2f95): New define.
15842 (octeontx2f95n): New define.
15843 (octeontx2f95mm): New define.
15844 * config/aarch64/aarch64-tune.md: Regenerate.
15845 * doc/invoke.texi (-mcpu=): Document the new cpu types.
15847 2020-01-13 Jason Merrill <jason@redhat.com>
15849 PR c++/33799 - destroy return value if local cleanup throws.
15850 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR.
15852 2020-01-13 Martin Liska <mliska@suse.cz>
15854 * ipa-cp.c (get_max_overall_size): Use newly
15855 renamed param param_ipa_cp_unit_growth.
15856 * params.opt: Remove legacy param name.
15858 2020-01-13 Martin Sebor <msebor@redhat.com>
15860 PR tree-optimization/93213
15861 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul
15862 stores to be eliminated.
15864 2020-01-13 Martin Liska <mliska@suse.cz>
15866 * opts.c (print_help): Do not print CL_PARAM
15867 and CL_WARNING for CL_OPTIMIZATION.
15869 2020-01-13 Jonathan Wakely <jwakely@redhat.com>
15872 * doc/invoke.texi (Warning Options): Add caveat about some warnings
15873 depending on optimization settings.
15875 2020-01-13 Jakub Jelinek <jakub@redhat.com>
15877 PR tree-optimization/90838
15878 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
15879 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro
15880 argument rather than to initialize temporary for targets that
15881 don't use the mode argument at all. Initialize ctzval to avoid
15884 2020-01-10 Thomas Schwinge <thomas@codesourcery.com>
15886 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition.
15887 * tree-core.h: Document it.
15888 * gimplify.c (gimplify_omp_workshare): Set it.
15889 * omp-low.c (lower_omp_target): Use it.
15890 * tree-pretty-print.c (dump_omp_clause): Print it.
15892 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>:
15893 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'.
15895 2020-01-10 David Malcolm <dmalcolm@redhat.com>
15897 * Makefile.in (OBJS): Add tree-diagnostic-path.o.
15898 * common.opt (fdiagnostics-path-format=): New option.
15899 (diagnostic_path_format): New enum.
15900 (fdiagnostics-show-path-depths): New option.
15901 * coretypes.h (diagnostic_event_id_t): New forward decl.
15902 * diagnostic-color.c (color_dict): Add "path".
15903 * diagnostic-event-id.h: New file.
15904 * diagnostic-format-json.cc (json_from_expanded_location): Make
15906 (json_end_diagnostic): Call context->make_json_for_path if it
15907 exists and the diagnostic has a path.
15908 (diagnostic_output_format_init): Clear context->print_path.
15909 * diagnostic-path.h: New file.
15910 * diagnostic-show-locus.c (colorizer::set_range): Special-case
15911 when printing a run of events in a diagnostic_path so that they
15912 all get the same color.
15913 (layout::m_diagnostic_path_p): New field.
15914 (layout::layout): Initialize it.
15915 (layout::print_any_labels): Don't colorize the label text for an
15916 event in a diagnostic_path.
15917 (gcc_rich_location::add_location_if_nearby): Add
15918 "restrict_to_current_line_spans" and "label" params. Pass the
15919 former to layout.maybe_add_location_range; pass the latter
15920 when calling add_range.
15921 * diagnostic.c: Include "diagnostic-path.h".
15922 (diagnostic_initialize): Initialize context->path_format and
15923 context->show_path_depths.
15924 (diagnostic_show_any_path): New function.
15925 (diagnostic_path::interprocedural_p): New function.
15926 (diagnostic_report_diagnostic): Call diagnostic_show_any_path.
15927 (simple_diagnostic_path::num_events): New function.
15928 (simple_diagnostic_path::get_event): New function.
15929 (simple_diagnostic_path::add_event): New function.
15930 (simple_diagnostic_event::simple_diagnostic_event): New ctor.
15931 (simple_diagnostic_event::~simple_diagnostic_event): New dtor.
15932 (debug): New overload taking a diagnostic_path *.
15933 * diagnostic.def (DK_DIAGNOSTIC_PATH): New.
15934 * diagnostic.h (enum diagnostic_path_format): New enum.
15935 (json::value): New forward decl.
15936 (diagnostic_context::path_format): New field.
15937 (diagnostic_context::show_path_depths): New field.
15938 (diagnostic_context::print_path): New callback field.
15939 (diagnostic_context::make_json_for_path): New callback field.
15940 (diagnostic_show_any_path): New decl.
15941 (json_from_expanded_location): New decl.
15942 * doc/invoke.texi (-fdiagnostics-path-format=): New option.
15943 (-fdiagnostics-show-path-depths): New option.
15944 (-fdiagnostics-color): Add "path" to description of default
15945 GCC_COLORS; describe it.
15946 (-fdiagnostics-format=json): Document how diagnostic paths are
15947 represented in the JSON output format.
15948 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
15949 Add optional params "restrict_to_current_line_spans" and "label".
15950 * opts.c (common_handle_option): Handle
15951 OPT_fdiagnostics_path_format_ and
15952 OPT_fdiagnostics_show_path_depths.
15953 * pretty-print.c: Include "diagnostic-event-id.h".
15954 (pp_format): Implement "%@" format code for printing
15955 diagnostic_event_id_t *.
15956 (selftest::test_pp_format): Add tests for "%@".
15957 * selftest-run-tests.c (selftest::run_tests): Call
15958 selftest::tree_diagnostic_path_cc_tests.
15959 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl.
15960 * toplev.c (general_init): Initialize global_dc->path_format and
15961 global_dc->show_path_depths.
15962 * tree-diagnostic-path.cc: New file.
15963 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make
15964 non-static. Drop "diagnostic" param in favor of storing the
15965 original value of "where" and re-using it.
15966 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of
15967 maybe_unwind_expanded_macro_loc.
15968 (tree_diagnostics_defaults): Initialize context->print_path and
15969 context->make_json_for_path.
15970 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New
15972 (default_tree_make_json_for_path): New decl.
15973 (maybe_unwind_expanded_macro_loc): New decl.
15975 2020-01-10 Jakub Jelinek <jakub@redhat.com>
15977 PR tree-optimization/93210
15978 * fold-const.h (native_encode_initializer,
15979 can_native_interpret_type_p): Declare.
15980 * fold-const.c (native_encode_string): Fix up handling with off != -1,
15982 (native_encode_initializer): New function, moved from dwarf2out.c.
15983 Adjust to native_encode_expr compatible arguments, including dry-run
15984 and partial extraction modes. Don't handle STRING_CST.
15985 (can_native_interpret_type_p): No longer static.
15986 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify
15987 offset / BITS_PER_UNIT fits into int and don't call it if
15988 can_native_interpret_type_p fails. If suboff is NULL and for
15989 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with
15990 native_encode_initializer.
15991 (fold_const_aggregate_ref_1): Formatting fix.
15992 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c.
15993 (tree_add_const_value_attribute): Adjust caller.
15995 PR tree-optimization/90838
15996 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
15997 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of
15998 CTZ_DEFINED_VALUE_AT_ZERO.
16000 2020-01-10 Vladimir Makarov <vmakarov@redhat.com>
16002 PR inline-asm/93027
16003 * lra-constraints.c (match_reload): Permit input operands have the
16004 same mode as output while other input operands have a different
16007 2020-01-10 Wilco Dijkstra <wdijkstr@arm.com>
16009 PR tree-optimization/90838
16010 * tree-ssa-forwprop.c (check_ctz_array): Add new function.
16011 (check_ctz_string): Likewise.
16012 (optimize_count_trailing_zeroes): Likewise.
16013 (simplify_count_trailing_zeroes): Likewise.
16014 (pass_forwprop::execute): Try ctz simplification.
16015 * match.pd: Add matching for ctz idioms.
16017 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16019 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function
16021 (aarch64_invalid_unary_op): New function for target hook.
16022 (aarch64_invalid_binary_op): New function for target hook.
16024 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16026 * config.gcc: Add arm_bf16.h.
16027 * config/aarch64/aarch64-builtins.c
16028 (aarch64_simd_builtin_std_type): Add BFmode.
16029 (aarch64_init_simd_builtin_types): Define element types for vector
16031 (aarch64_init_bf16_types): New function.
16032 (aarch64_general_init_builtins): Add arm_init_bf16_types function call.
16033 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
16035 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
16036 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
16038 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
16039 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
16040 * config/aarch64/aarch64.c
16041 (aarch64_classify_vector_mode): Add support for BF types.
16042 (aarch64_gimplify_va_arg_expr): Add support for BF types.
16043 (aarch64_vq_mode): Add support for BF types.
16044 (aarch64_simd_container_mode): Add support for BF types.
16045 (aarch64_mangle_type): Add support for BF scalar type.
16046 * config/aarch64/aarch64.md: Add BFmode to movhf pattern.
16047 * config/aarch64/arm_bf16.h: New file.
16048 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
16049 * config/aarch64/iterators.md: Add BF types to mode attributes.
16050 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.
16052 2020-01-10 Jason Merrill <jason@redhat.com>
16054 PR c++/93173 - incorrect tree sharing.
16055 * gimplify.c (copy_if_shared): No longer static.
16056 * gimplify.h: Declare it.
16058 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16060 * doc/invoke.texi (-msve-vector-bits=): Document that
16061 -msve-vector-bits=128 now generates VL-specific code for
16062 little-endian targets.
16063 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use
16064 build_vector_type_for_mode to construct the data vector types.
16065 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate
16066 VL-specific code for -msve-vector-bits=128 on little-endian targets.
16067 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes
16068 for 128-bit vectors.
16070 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16072 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask
16075 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16077 * config/aarch64/aarch64-builtins.c
16078 (aarch64_builtin_vectorized_function): Check for specific vector modes,
16079 rather than checking the number of elements and the element mode.
16081 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16083 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use
16084 get_related_vectype_for_scalar_type rather than build_vector_type
16085 to create the index type for a conditional reduction.
16087 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16089 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF
16090 for any type of gather or scatter, including strided accesses.
16092 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16094 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function
16097 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16099 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use
16100 get_dr_vinfo_offset
16101 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init
16102 parameter and its use to reset DR_OFFSET's.
16103 (vect_transform_loop): Remove orig_drs_init argument.
16104 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset
16105 member of dr_vec_info rather than the offset of the associated
16106 data_reference's innermost_loop_behavior.
16107 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference.
16108 (vect_do_peeling): Remove orig_drs_init parameter and its construction.
16109 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with
16110 get_dr_vinfo_offset.
16111 (vectorizable_store): Likewise.
16112 (vectorizable_load): Likewise.
16114 2020-01-10 Richard Biener <rguenther@suse.de>
16116 * gimple-ssa-store-merging
16117 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info.
16119 2020-01-10 Martin Liska <mliska@suse.cz>
16122 * ipa-inline-analysis.c (offline_size): Make proper parenthesis
16123 encapsulation that was there before r280040.
16125 2020-01-10 Richard Biener <rguenther@suse.de>
16127 PR middle-end/93199
16128 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL
16129 sequences to avoid walking them again for secondary opportunities.
16130 (pass_lower_eh_dispatch::execute): Instead actually insert
16133 2020-01-10 Richard Biener <rguenther@suse.de>
16135 PR middle-end/93199
16136 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible.
16137 (cleanup_all_empty_eh): Walk landing pads in reverse order to
16138 avoid quadraticness.
16140 2020-01-10 Martin Jambor <mjambor@suse.cz>
16142 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization.
16143 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it
16144 to get param_ipa_sra_max_replacements.
16145 (param_splitting_across_edge): Pass the caller to
16146 pull_accesses_from_callee.
16148 2020-01-10 Martin Jambor <mjambor@suse.cz>
16150 * params.opt (param_ipcp_unit_growth): Mark as Optimization.
16151 * ipa-cp.c (max_new_size): Removed.
16152 (orig_overall_size): New variable.
16153 (get_max_overall_size): New function.
16154 (estimate_local_effects): Use it. Adjust dump.
16155 (decide_about_value): Likewise.
16156 (ipcp_propagate_stage): Do not calculate max_new_size, just store
16157 orig_overall_size. Adjust dump.
16158 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size.
16160 2020-01-10 Martin Jambor <mjambor@suse.cz>
16162 * params.opt (param_ipa_max_agg_items): Mark as Optimization
16163 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use
16164 instead of param_ipa_max_agg_items.
16165 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from
16166 optimization info for the callee.
16168 2020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com>
16170 * lto-streamer-in.c (input_function): Remove streamed-in inline debug
16171 markers if debug_inline_points is false.
16173 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16175 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
16177 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
16178 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
16179 aarch64-sve-builtins-sve2.h.
16180 (aarch64-sve-builtins-sve2.o): New rule.
16181 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
16182 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
16183 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
16184 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
16185 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
16186 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
16188 * config/aarch64/aarch64-sve.md: Update comments with SVE2
16189 instructions that are handled here.
16190 (@cond_asrd<mode>): Generalize to...
16191 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
16192 (*cond_asrd<mode>_2): Generalize to...
16193 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
16194 (*cond_asrd<mode>_z): Generalize to...
16195 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
16196 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
16197 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
16198 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
16199 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
16201 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
16202 (@aarch64_scatter_stnt<mode>): Likewise.
16203 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
16204 (@aarch64_mul_lane_<mode>): Likewise.
16205 (@aarch64_sve_suqadd<mode>_const): Likewise.
16206 (*<sur>h<addsub><mode>): Generalize to...
16207 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
16209 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
16210 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
16211 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
16212 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
16213 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
16214 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
16215 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
16216 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
16217 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
16218 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
16219 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
16220 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
16221 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
16222 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
16223 (@aarch64_sve_add_mul_lane_<mode>): Likewise.
16224 (@aarch64_sve_sub_mul_lane_<mode>): Likewise.
16225 (@aarch64_sve2_xar<mode>): Likewise.
16226 (@aarch64_sve2_bcax<mode>): Likewise.
16227 (*aarch64_sve2_eor3<mode>): Rename to...
16228 (@aarch64_sve2_eor3<mode>): ...this.
16229 (@aarch64_sve2_bsl<mode>): New expander.
16230 (@aarch64_sve2_nbsl<mode>): Likewise.
16231 (@aarch64_sve2_bsl1n<mode>): Likewise.
16232 (@aarch64_sve2_bsl2n<mode>): Likewise.
16233 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
16234 (*aarch64_sve2_sra<mode>): Add MOVPRFX support.
16235 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
16236 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
16237 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
16238 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
16239 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
16240 (<su>mull<bt><Vwide>): Generalize to...
16241 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
16243 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
16244 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
16245 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
16246 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16247 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
16248 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16249 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
16250 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16251 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
16252 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16253 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
16254 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
16255 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
16256 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
16257 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
16258 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
16259 (<SHRNB:r>shrnb<mode>): Generalize to...
16260 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
16262 (<SHRNT:r>shrnt<mode>): Generalize to...
16263 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
16265 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
16266 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
16267 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
16268 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
16269 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
16270 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
16271 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
16272 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
16273 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
16274 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
16275 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
16276 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
16277 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
16278 (@aarch64_sve2_cvtnt<mode>): Likewise.
16279 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
16280 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
16281 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
16282 (@aarch64_sve2_cvtxnt<mode>): Likewise.
16283 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
16284 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
16285 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
16286 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
16287 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
16288 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
16289 (@aarch64_sve2_pmul<mode>): Likewise.
16290 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
16291 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
16292 (@aarch64_sve2_tbl2<mode>): Likewise.
16293 (@aarch64_sve2_tbx<mode>): Likewise.
16294 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
16295 (@aarch64_sve2_histcnt<mode>): Likewise.
16296 (@aarch64_sve2_histseg<mode>): Likewise.
16297 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
16298 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
16299 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
16300 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
16301 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
16302 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
16303 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
16304 (<su>mulh<r>s<mode>3): Update after above pattern name changes.
16305 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
16306 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
16307 (SVE2_PMULL_PAIR_I): New mode iterators.
16308 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
16309 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
16310 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
16311 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
16312 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
16313 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
16314 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
16315 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
16316 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
16317 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
16318 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
16319 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
16320 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
16321 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
16322 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
16323 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
16324 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
16325 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
16326 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
16327 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
16328 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
16329 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
16330 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
16331 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
16332 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
16333 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
16334 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
16335 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
16336 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
16337 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
16338 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
16340 (VNARROW, Ventype): New mode attributes.
16341 (Vewtype): Handle VNx2DI. Fix typo in comment.
16342 (VDOUBLE): New mode attribute.
16343 (sve_lane_con): Handle VNx8HI.
16344 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
16345 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
16346 (sve_int_op, sve_int_op_rev): Handle the above codes.
16347 (sve_pred_int_rhs2_operand): Likewise.
16348 (MULLBT, SHRNB, SHRNT): Delete.
16349 (SVE_INT_SHIFT_IMM): New int iterator.
16350 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
16351 and UNSPEC_WHILEHS for TARGET_SVE2.
16352 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
16353 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
16354 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
16355 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
16356 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
16357 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
16358 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
16359 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
16360 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
16361 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
16362 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
16363 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
16364 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
16365 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
16366 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
16367 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
16368 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
16369 (optab): Handle the new unspecs.
16370 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
16372 (lr): Handle the new unspecs.
16374 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
16375 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
16376 (sve_int_qsub_op): New int attributes.
16377 (sve_fp_op, rot): Handle the new unspecs.
16378 * config/aarch64/aarch64-sve-builtins.h
16379 (function_resolver::require_matching_pointer_type): Declare.
16380 (function_resolver::resolve_unary): Add an optional boolean argument.
16381 (function_resolver::finish_opt_n_resolution): Add an optional
16382 type_suffix_index argument.
16383 (gimple_folder::redirect_call): Declare.
16384 (gimple_expander::prepare_gather_address_operands): Add an optional
16386 * config/aarch64/aarch64-sve-builtins.cc: Include
16387 aarch64-sve-builtins-sve2.h.
16388 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
16389 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
16390 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
16391 (TYPES_hsd_integer): Use TYPES_hsd_signed.
16392 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
16393 (TYPES_s_unsigned): Likewise.
16394 (TYPES_s_integer): Use TYPES_s_unsigned.
16395 (TYPES_sd_signed, TYPES_sd_unsigned): New macros.
16396 (TYPES_sd_integer): Use them.
16397 (TYPES_d_unsigned): New macro.
16398 (TYPES_d_integer): Use it.
16399 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
16400 (TYPES_cvt_narrow): Likewise.
16401 (DEF_SVE_TYPES_ARRAY): Include the new types macros above.
16402 (preds_mx): New variable.
16403 (function_builder::add_overloaded_function): Allow the new feature
16404 set to be more restrictive than the original one.
16405 (function_resolver::infer_pointer_type): Remove qualifiers from
16406 the pointer type before printing it.
16407 (function_resolver::require_matching_pointer_type): New function.
16408 (function_resolver::resolve_sv_displacement): Handle functions
16409 that don't support 32-bit vector indices or svint32_t vector offsets.
16410 (function_resolver::finish_opt_n_resolution): Take the inferred type
16411 as a separate argument.
16412 (function_resolver::resolve_unary): Optionally treat all forms in
16413 the same way as normal merging functions.
16414 (gimple_folder::redirect_call): New function.
16415 (function_expander::prepare_gather_address_operands): Add an argument
16416 that says whether scaled forms are available. If they aren't,
16417 handle scaling of vector indices and don't add the extension and
16419 (function_expander::map_to_unspecs): If aarch64_sve isn't available,
16420 fall back to using cond_* instead.
16421 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
16422 Split out the member variables into...
16423 (rtx_code_function_base): ...this new base class.
16424 (rtx_code_function_rotated): Inherit rtx_code_function_base.
16425 (unspec_based_function): Split out the member variables into...
16426 (unspec_based_function_base): ...this new base class.
16427 (unspec_based_function_rotated): Inherit unspec_based_function_base.
16428 (unspec_based_function_exact_insn): New class.
16429 (unspec_based_add_function, unspec_based_add_lane_function)
16430 (unspec_based_lane_function, unspec_based_pred_function)
16431 (unspec_based_qadd_function, unspec_based_qadd_lane_function)
16432 (unspec_based_qsub_function, unspec_based_qsub_lane_function)
16433 (unspec_based_sub_function, unspec_based_sub_lane_function): New
16435 (unspec_based_fused_function): New class.
16436 (unspec_based_mla_function, unspec_based_mls_function): New typedefs.
16437 (unspec_based_fused_lane_function): New class.
16438 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
16440 (CODE_FOR_MODE1): New macro.
16441 (fixed_insn_function): New class.
16442 (while_comparison): Likewise.
16443 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
16444 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
16445 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
16446 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
16447 (load_gather_sv_restricted, shift_left_imm_long): Declare.
16448 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
16449 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
16450 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
16451 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
16452 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
16453 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
16454 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
16455 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
16456 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
16457 Also add an initial argument for unary_convert_narrowt, regardless
16458 of the predication type.
16459 (build_32_64): Allow loads and stores to specify MODE_none.
16460 (build_sv_index64, build_sv_uint_offset): New functions.
16461 (long_type_suffix): New function.
16462 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
16463 (binary_imm_long_base, load_gather_sv_base): Likewise.
16464 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
16465 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
16466 (unary_narrowb_base, unary_narrowt_base): Likewise.
16467 (binary_long_lane_def, binary_long_lane): New shape.
16468 (binary_long_opt_n_def, binary_long_opt_n): Likewise.
16469 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
16470 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
16471 (binary_to_uint_def, binary_to_uint): Likewise.
16472 (binary_wide_def, binary_wide): Likewise.
16473 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
16474 (compare_def, compare): Likewise.
16475 (compare_ptr_def, compare_ptr): Likewise.
16476 (load_ext_gather_index_restricted_def,
16477 load_ext_gather_index_restricted): Likewise.
16478 (load_ext_gather_offset_restricted_def,
16479 load_ext_gather_offset_restricted): Likewise.
16480 (load_gather_sv_def): Inherit from load_gather_sv_base.
16481 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
16482 (shift_left_imm_def, shift_left_imm): Likewise.
16483 (shift_left_imm_long_def, shift_left_imm_long): Likewise.
16484 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
16485 (store_scatter_index_restricted_def,
16486 store_scatter_index_restricted): Likewise.
16487 (store_scatter_offset_restricted_def,
16488 store_scatter_offset_restricted): Likewise.
16489 (tbl_tuple_def, tbl_tuple): Likewise.
16490 (ternary_long_lane_def, ternary_long_lane): Likewise.
16491 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
16492 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
16493 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
16494 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
16495 (ternary_qq_rotate_def, ternary_qq_rotate): New shape.
16496 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
16497 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
16498 (ternary_uint_def, ternary_uint): Likewise.
16499 (unary_convert): Fix typo in comment.
16500 (unary_convert_narrowt_def, unary_convert_narrowt): New shape.
16501 (unary_long_def, unary_long): Likewise.
16502 (unary_narrowb_def, unary_narrowb): Likewise.
16503 (unary_narrowt_def, unary_narrowt): Likewise.
16504 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
16505 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
16506 (unary_to_int_def, unary_to_int): Likewise.
16507 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
16508 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
16509 (svasrd_impl): Delete.
16510 (svcadd_impl::expand): Handle integer operations too.
16511 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
16512 new functions to derive the unspec numbers.
16513 (svmla_svmls_lane_impl): Replace with...
16514 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle
16515 integer operations too.
16516 (svwhile_impl): Rename to...
16517 (svwhilelx_impl): ...this and inherit from while_comparison.
16518 (svasrd): Use unspec_based_function.
16519 (svmla_lane): Use svmla_lane_impl.
16520 (svmls_lane): Use svmls_lane_impl.
16521 (svrecpe, svrsqrte): Handle unsigned integer operations too.
16522 (svwhilele, svwhilelt): Use svwhilelx_impl.
16523 * config/aarch64/aarch64-sve-builtins-sve2.h: New file.
16524 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
16525 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
16526 * config/aarch64/aarch64-sve-builtins.def: Include
16527 aarch64-sve-builtins-sve2.def.
16529 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16531 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
16532 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
16533 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
16534 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar
16535 immediates as well as vector ones.
16536 * config/aarch64/predicates.md (aarch64_sve_arith_immediate)
16537 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
16538 (aarch64_sve_qsub_immediate): Update calls accordingly.
16540 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16542 * config/aarch64/aarch64-sve2.md: Add banner comments.
16543 (<su>mulh<r>s<mode>3): Move further up file.
16544 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
16545 (*aarch64_sve2_sra<mode>): Move further down file.
16546 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.
16548 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16550 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW
16551 and UNSPEC_WHILEWR.
16552 (while_optab_cmp): Handle them.
16553 * config/aarch64/aarch64-sve.md
16554 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public
16555 and add a "@" marker.
16556 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it
16557 instead of gen_aarch64_sve2_while_ptest.
16558 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete.
16560 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16562 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to...
16563 (UNSPEC_WHILELE): ...this.
16564 (UNSPEC_WHILE_LO): Rename to...
16565 (UNSPEC_WHILELO): ...this.
16566 (UNSPEC_WHILE_LS): Rename to...
16567 (UNSPEC_WHILELS): ...this.
16568 (UNSPEC_WHILE_LT): Rename to...
16569 (UNSPEC_WHILELT): ...this.
16570 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly.
16571 (cmp_op, while_optab_cmp): Likewise.
16572 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise.
16573 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise.
16574 (svwhilelt): Likewise.
16576 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16578 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete.
16579 (unary_to_uint): Define.
16580 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def)
16581 (unary_count): Rename to...
16582 (unary_to_uint_def, unary_to_uint): ...this.
16583 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly.
16585 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16587 * config/aarch64/aarch64-sve-builtins-functions.h
16588 (code_for_mode_function): New class.
16589 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros.
16590 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl)
16591 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete.
16592 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0.
16593 (svmul_lane, svtmad): Use CODE_FOR_MODE0.
16595 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16597 * config/aarch64/iterators.md (addsub): New code attribute.
16598 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>):
16600 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change
16601 in the asm string and attributes. Fix indentation.
16602 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>):
16604 (@aarch64_sve_<optab><mode>): ...this.
16605 * config/aarch64/aarch64-sve-builtins.h
16606 (function_expander::expand_signed_unpred_op): Delete.
16607 * config/aarch64/aarch64-sve-builtins.cc
16608 (function_expander::expand_signed_unpred_op): Likewise.
16609 (function_expander::map_to_rtx_codes): If the optab isn't defined,
16610 try using code_for_aarch64_sve instead.
16611 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete.
16612 (svqsub_impl): Likewise.
16613 (svqadd, svqsub): Use rtx_code_function instead.
16615 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16617 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete.
16618 (HADDSUB, sur, addsub): Remove them.
16620 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16622 * tree-nrv.c (pass_return_slot::execute): Handle all internal
16623 functions the same way, rather than singling out those that
16624 aren't mapped directly to optabs.
16626 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16628 * target.def (compatible_vector_types_p): New target hook.
16629 * hooks.h (hook_bool_const_tree_const_tree_true): Declare.
16630 * hooks.c (hook_bool_const_tree_const_tree_true): New function.
16631 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook.
16632 * doc/tm.texi: Regenerate.
16633 * gimple-expr.c: Include target.h.
16634 (useless_type_conversion_p): Use targetm.compatible_vector_types_p.
16635 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New
16637 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define.
16638 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred):
16639 Use the original predicate if it already has a suitable type.
16641 2020-01-09 Martin Jambor <mjambor@suse.cz>
16643 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct,
16644 resolve_speculation and redirect_call_stmt_to_callee static. Change
16645 return type of set_call_stmt to cgraph_edge *.
16646 * auto-profile.c (afdo_indirect_call): Adjust call to
16647 redirect_call_stmt_to_callee.
16648 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *,
16649 make the this pointer explicit, adjust self-recursive calls and the
16650 call top make_direct. Return the resulting edge.
16651 (cgraph_edge::remove): Make this pointer explicit.
16652 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove.
16653 (cgraph_edge::make_direct): Likewise, adjust call to
16654 resolve_speculation.
16655 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust
16656 call to set_call_stmt.
16657 (cgraph_update_edges_for_call_stmt_node): Update call to
16658 set_call_stmt and remove.
16659 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
16660 Renamed edge to master_edge. Adjusted calls to set_call_stmt.
16661 (cgraph_node::create_edge_including_clones): Moved "first" definition
16662 of edge to the block where it was used. Adjusted calls to
16664 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to
16665 cgraph_edge::remove.
16666 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to
16667 make_direct and redirect_call_stmt_to_callee.
16668 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to
16669 resolve_speculation and make_direct.
16670 * ipa-inline-transform.c (inline_transform): Adjust call to
16671 redirect_call_stmt_to_callee.
16672 (check_speculations_1):: Adjust call to resolve_speculation.
16673 * ipa-inline.c (resolve_noninline_speculation): Adjust call to
16674 resolve-speculation.
16675 (inline_small_functions): Adjust call to resolve_speculation.
16676 (ipa_inline): Likewise.
16677 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to
16679 * ipa-visibility.c (function_and_variable_visibility): Make iteration
16680 safe with regards to edge removal, adjust calls to
16681 redirect_call_stmt_to_callee.
16682 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct
16683 and redirect_call_stmt_to_callee.
16684 * multiple_target.c (create_dispatcher_calls): Adjust call to
16685 redirect_call_stmt_to_callee
16686 (redirect_to_specific_clone): Likewise.
16687 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph):
16688 Adjust calls to cgraph_edge::remove.
16689 * tree-inline.c (copy_bb): Adjust call to set_call_stmt.
16690 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee.
16691 (expand_call_inline): Adjust call to cgraph_edge::remove.
16693 2020-01-09 Martin Liska <mliska@suse.cz>
16695 * params.opt: Set Optimization for
16696 param_max_speculative_devirt_maydefs.
16698 2020-01-09 Martin Sebor <msebor@redhat.com>
16700 PR middle-end/93200
16702 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type.
16704 2020-01-09 Martin Liska <mliska@suse.cz>
16706 * auto-profile.c (auto_profile): Use opt_for_fn
16708 * ipa-cp.c (ipcp_lattice::add_value): Likewise.
16709 (propagate_vals_across_arith_jfunc): Likewise.
16710 (hint_time_bonus): Likewise.
16711 (incorporate_penalties): Likewise.
16712 (good_cloning_opportunity_p): Likewise.
16713 (perform_estimation_of_a_value): Likewise.
16714 (estimate_local_effects): Likewise.
16715 (ipcp_propagate_stage): Likewise.
16716 * ipa-fnsummary.c (decompose_param_expr): Likewise.
16717 (set_switch_stmt_execution_predicate): Likewise.
16718 (analyze_function_body): Likewise.
16719 * ipa-inline-analysis.c (offline_size): Likewise.
16720 * ipa-inline.c (early_inliner): Likewise.
16721 * ipa-prop.c (ipa_analyze_node): Likewise.
16722 (ipcp_transform_function): Likewise.
16723 * ipa-sra.c (process_scan_results): Likewise.
16724 (ipa_sra_summarize_function): Likewise.
16725 * params.opt: Rename ipcp-unit-growth to
16726 ipa-cp-unit-growth. Add Optimization for various
16727 IPA-related parameters.
16729 2020-01-09 Richard Biener <rguenther@suse.de>
16731 PR middle-end/93054
16732 * gimplify.c (gimplify_expr): Deal with NOP definitions.
16734 2020-01-09 Richard Biener <rguenther@suse.de>
16736 PR tree-optimization/93040
16737 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit.
16739 2020-01-09 Georg-Johann Lay <avr@gjlay.de>
16741 * common/config/avr/avr-common.c (avr_option_optimization_table)
16742 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early.
16744 2020-01-09 Martin Liska <mliska@suse.cz>
16746 * cgraphclones.c (symbol_table::materialize_all_clones):
16747 Use cgraph_node::dump_name.
16749 2020-01-09 Jakub Jelinek <jakub@redhat.com>
16751 PR inline-asm/93202
16752 * config/riscv/riscv.c (riscv_print_operand_reloc): Use
16753 output_operand_lossage instead of gcc_unreachable.
16754 * doc/md.texi (riscv f constraint): Fix typo.
16757 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of
16758 SWI. Use <general_hilo_operand> instead of <general_operand>. Use
16759 CONST_SCALAR_INT_P instead of CONST_INT_P.
16760 (*subv<mode>4_1): Rename to ...
16761 (subv<mode>4_1): ... this.
16762 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
16763 define_insn_and_split patterns.
16764 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
16767 2020-01-08 David Malcolm <dmalcolm@redhat.com>
16769 * vec.c (class selftest::count_dtor): New class.
16770 (selftest::test_auto_delete_vec): New test.
16771 (selftest::vec_c_tests): Call it.
16772 * vec.h (class auto_delete_vec): New class template.
16773 (auto_delete_vec<T>::~auto_delete_vec): New dtor.
16775 2020-01-08 David Malcolm <dmalcolm@redhat.com>
16777 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap.
16779 2020-01-08 Jim Wilson <jimw@sifive.com>
16781 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out
16782 use of TLS_MODEL_LOCAL_EXEC when not pic.
16784 2020-01-08 David Malcolm <dmalcolm@redhat.com>
16786 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix
16789 2020-01-08 Jakub Jelinek <jakub@redhat.com>
16792 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2,
16793 *stack_protect_set_3 peephole2): Also check that the second
16794 insns source is general_operand.
16797 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand
16798 predicate for output operand instead of register_operand.
16799 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with
16800 memory destination and non-memory operands[2].
16802 2020-01-08 Martin Liska <mliska@suse.cz>
16804 * cgraph.c (cgraph_node::dump): Use ::dump_name or
16805 ::dump_asm_name instead of (::name or ::asm_name).
16806 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise.
16807 * cgraphunit.c (walk_polymorphic_call_targets): Likewise.
16808 (analyze_functions): Likewise.
16809 (expand_all_functions): Likewise.
16810 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise.
16811 (propagate_bits_across_jump_function): Likewise.
16812 (dump_profile_updates): Likewise.
16813 (ipcp_store_bits_results): Likewise.
16814 (ipcp_store_vr_results): Likewise.
16815 * ipa-devirt.c (dump_targets): Likewise.
16816 * ipa-fnsummary.c (analyze_function_body): Likewise.
16817 * ipa-hsa.c (check_warn_node_versionable): Likewise.
16818 (process_hsa_functions): Likewise.
16819 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise.
16820 (set_alias_uids): Likewise.
16821 * ipa-inline-transform.c (save_inline_function_body): Likewise.
16822 * ipa-inline.c (recursive_inlining): Likewise.
16823 (inline_to_all_callers_1): Likewise.
16824 (ipa_inline): Likewise.
16825 * ipa-profile.c (ipa_propagate_frequency_1): Likewise.
16826 (ipa_propagate_frequency): Likewise.
16827 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.
16828 (remove_described_reference): Likewise.
16829 * ipa-pure-const.c (worse_state): Likewise.
16830 (check_retval_uses): Likewise.
16831 (analyze_function): Likewise.
16832 (propagate_pure_const): Likewise.
16833 (propagate_nothrow): Likewise.
16834 (dump_malloc_lattice): Likewise.
16835 (propagate_malloc): Likewise.
16836 (pass_local_pure_const::execute): Likewise.
16837 * ipa-visibility.c (optimize_weakref): Likewise.
16838 (function_and_variable_visibility): Likewise.
16839 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise.
16840 (ipa_discover_variable_flags): Likewise.
16841 * lto-streamer-out.c (output_function): Likewise.
16842 (output_constructor): Likewise.
16843 * tree-inline.c (copy_bb): Likewise.
16844 * tree-ssa-structalias.c (ipa_pta_execute): Likewise.
16845 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise.
16847 2020-01-08 Richard Biener <rguenther@suse.de>
16849 PR middle-end/93199
16850 * tree-eh.c (sink_clobbers): Update virtual operands for
16851 the first and last stmt only. Add a dry-run capability.
16852 (pass_lower_eh_dispatch::execute): Perform clobber sinking
16853 after CFG manipulations and in RPO order to catch all
16854 secondary opportunities reliably.
16856 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
16859 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
16861 2019-01-08 Richard Biener <rguenther@suse.de>
16863 PR middle-end/93199
16864 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified.
16865 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust
16866 virtual operand, also updating SSA use.
16867 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction):
16868 Update stmt after resetting virtual operand.
16869 (tree_loop_interchange::move_code_to_inner_loop): Likewise.
16870 * gimple-iterator.c (gsi_remove): When not removing the stmt
16871 permanently do not delink immediate uses or mark the stmt modified.
16873 2020-01-08 Martin Liska <mliska@suse.cz>
16875 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name.
16876 (ipa_call_context::estimate_size_and_time): Likewise.
16877 (inline_analyze_function): Likewise.
16879 2020-01-08 Martin Liska <mliska@suse.cz>
16881 * cgraph.c (cgraph_node::dump): Use systematically
16884 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
16886 Add -nodevicespecs option for avr.
16889 * config/avr/avr.opt (-nodevicespecs): New driver option.
16890 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue
16891 "-specs=device-specs/..." if that option is not set.
16892 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
16894 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
16896 Implement 64-bit double functions for avr.
16899 * config.gcc (tm_defines) [target=avr]: Support --with-libf7,
16900 --with-double-comparison.
16901 * doc/install.texi: Document them.
16902 * config/avr/avr-c.c (avr_cpu_cpp_builtins)
16903 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
16904 <WITH_DOUBLE_COMPARISON>: New built-in defines.
16905 * doc/invoke.texi (AVR Built-in Macros): Document them.
16906 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
16907 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
16908 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
16910 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
16913 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
16914 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
16915 when only building rm-profile multilibs.
16917 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
16920 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
16921 lattice for a value to check.
16922 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
16923 finite propagation in self-recursive scc.
16925 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
16927 * ipa-inline.c (caller_growth_limits): Restore the AND.
16929 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
16931 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
16932 (VEC_ALLREG_ALT): New iterator.
16933 (VEC_ALLREG_INT_MODE): New iterator.
16934 (VCMP_MODE): New iterator.
16935 (VCMP_MODE_INT): New iterator.
16936 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
16937 (vec_cmp<u>v64qidi): New define_expand.
16938 (vec_cmp<mode>di_exec): Use VCMP_MODE.
16939 (vec_cmpu<mode>di_exec): New define_expand.
16940 (vec_cmp<u>v64qidi_exec): New define_expand.
16941 (vec_cmp<mode>di_dup): Use VCMP_MODE.
16942 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
16943 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
16944 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
16945 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
16946 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
16947 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
16948 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
16949 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
16950 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
16952 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
16953 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
16955 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
16957 * config/gcn/constraints.md (DA): Update description and match.
16959 (Db): New constraint.
16960 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
16962 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
16963 Implement 'Db' mixed immediate type.
16964 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
16965 (addcv64si3_dup<exec_vcc>): Delete.
16966 (subcv64si3<exec_vcc>): Rework constraints.
16967 (addv64di3): Rework constraints.
16968 (addv64di3_exec): Rework constraints.
16969 (subv64di3): Rework constraints.
16970 (addv64di3_dup): Delete.
16971 (addv64di3_dup_exec): Delete.
16972 (addv64di3_zext): Rework constraints.
16973 (addv64di3_zext_exec): Rework constraints.
16974 (addv64di3_zext_dup): Rework constraints.
16975 (addv64di3_zext_dup_exec): Rework constraints.
16976 (addv64di3_zext_dup2): Rework constraints.
16977 (addv64di3_zext_dup2_exec): Rework constraints.
16978 (addv64di3_sext_dup2): Rework constraints.
16979 (addv64di3_sext_dup2_exec): Rework constraints.
16981 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
16983 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
16984 existing target checks.
16986 2020-01-07 Richard Biener <rguenther@suse.de>
16988 * doc/install.texi: Bump minimal supported MPC version.
16990 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
16992 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
16993 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
16994 * langhooks.c: Include stor-layout.h.
16995 (lhd_simulate_enum_decl): New function.
16996 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
16997 handle_arm_sve_h for the LTO frontend.
16998 (register_vector_type): Cope with null returns from pushdecl.
17000 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17002 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
17003 (aarch64_sve::nvectors_if_data_type): Replace with...
17004 (aarch64_sve::builtin_type_p): ...this.
17005 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
17006 (find_vector_type): Delete.
17007 (add_sve_type_attribute): New function.
17008 (lookup_sve_type_attribute): Likewise.
17009 (register_builtin_types): Add an "SVE type" attribute to each type.
17010 (register_tuple_type): Likewise.
17011 (svbool_type_p, nvectors_if_data_type): Delete.
17012 (mangle_builtin_type): Use lookup_sve_type_attribute.
17013 (builtin_type_p): Likewise. Add an overload that returns the
17014 number of constituent vector and predicate registers.
17015 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
17016 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
17017 instead of aarch64_sve_argument_p.
17018 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
17019 (aarch64_pass_by_reference): Likewise.
17020 (aarch64_function_value_1): Likewise.
17021 (aarch64_return_in_memory): Likewise.
17022 (aarch64_layout_arg): Likewise.
17024 2020-01-07 Jakub Jelinek <jakub@redhat.com>
17026 PR tree-optimization/93156
17027 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
17028 least significant bit is always clear.
17030 PR tree-optimization/93118
17031 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
17032 simplifier with two intermediate conversions.
17034 2020-01-07 Martin Liska <mliska@suse.cz>
17036 * params.opt: Add Optimization for various parameters.
17038 2020-01-07 Martin Liska <mliska@suse.cz>
17041 * doc/extend.texi: Explain cloning for target_clone
17044 2020-01-07 Martin Liska <mliska@suse.cz>
17046 PR tree-optimization/92860
17047 * common.opt: Make in Optimization option
17048 as it is affected by -O0, which is an Optimization
17050 * tree-inline.c (tree_inlinable_function_p):
17051 Use opt_for_fn for warn_inline.
17052 (expand_call_inline): Likewise.
17054 2020-01-07 Martin Liska <mliska@suse.cz>
17056 PR tree-optimization/92860
17057 * common.opt: Make flag_ree as optimization
17060 2020-01-07 Martin Liska <mliska@suse.cz>
17062 PR optimization/92860
17063 * params.opt: Mark param_min_crossjump_insns with Optimization
17066 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
17068 * ipa-inline-analysis.c (estimate_growth): Fix typo.
17069 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
17071 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
17073 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
17074 helper function to return the valid addressing formats for a given
17075 hard register and mode.
17076 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
17078 * config/rs6000/constraints.md (Q constraint): Update
17080 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
17083 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
17084 Use 'Q' for doing vector extract from memory.
17085 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
17087 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
17088 doing vector extract from memory.
17089 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
17090 extract from memory.
17092 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
17093 for the offset being 34-bits when -mcpu=future is used.
17095 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
17097 * config/pa/pa.md: Revert change to use ordered_comparison_operator
17098 instead of cmpib_comparison_operator in cmpib patterns.
17099 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
17100 of cmpib_comparison_operator. Revise comment.
17102 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17104 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
17105 in an IFN_DIV_POW2 node to be equal.
17107 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17109 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
17110 (vect_check_scalar_mask): ...this.
17111 (vectorizable_store, vectorizable_load): Update call accordingly.
17112 (vectorizable_call): Use vect_check_scalar_mask to check the mask
17113 argument in calls to conditional internal functions.
17115 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17117 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
17118 '0' matching inputs.
17119 (subv64di3_exec): Likewise.
17121 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
17123 * config/mips/mips.c (vr4130_align_insns): Fix typo.
17124 * doc/md.texi (movstr): Likewise.
17126 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17128 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
17131 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17133 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
17135 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
17136 to a temporary file and use move-if-change to update the real
17137 file where necessary.
17139 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17141 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
17142 rather than Upa for CPY /M.
17144 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17146 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
17149 2020-01-06 Martin Liska <mliska@suse.cz>
17151 PR tree-optimization/92860
17152 * params.opt: Mark param_max_combine_insns with Optimization
17155 2020-01-05 Jakub Jelinek <jakub@redhat.com>
17158 * config/i386/i386.md (SWIDWI): New mode iterator.
17159 (DWI, dwi): Add TImode variants.
17160 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
17161 <general_hilo_operand> instead of <general_operand>. Use
17162 CONST_SCALAR_INT_P instead of CONST_INT_P.
17163 (*addv<mode>4_1): Rename to ...
17164 (addv<mode>4_1): ... this.
17165 (QWI): New mode attribute.
17166 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
17167 define_insn_and_split patterns.
17168 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
17170 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
17171 <general_hilo_operand> instead of <general_operand>.
17172 (*addcarry<mode>_1): New define_insn.
17173 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
17175 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
17177 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
17178 Use "call" instead of "set".
17180 2020-01-03 Martin Jambor <mjambor@suse.cz>
17183 * ipa-cp.c (print_all_lattices): Skip functions without info.
17185 2020-01-03 Jakub Jelinek <jakub@redhat.com>
17188 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
17189 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
17190 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
17191 for 'e' simd clones.
17194 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
17196 (mprefer-vector-width=): Add Save.
17197 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
17198 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
17199 (ix86_debug_options, ix86_function_specific_print): Adjust
17200 ix86_target_string callers.
17201 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
17202 (ix86_valid_target_attribute_tree): Likewise.
17203 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
17204 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
17205 ix86_target_string caller.
17208 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
17209 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
17210 instead of gen_int_shift_amount + convert_modes.
17212 PR rtl-optimization/93088
17213 * loop-iv.c (find_single_def_src): Punt after looking through
17214 128 reg copies for regs with single definitions. Move definitions
17217 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
17219 * config/arm/arm-c.c (arm_cpu_builtins): Define
17220 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
17221 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
17222 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
17223 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
17224 * config/arm/arm-tables.opt: Regenerated.
17225 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
17226 arm_arch_i8mm and arm_arch_bf16 when enabled.
17227 * config/arm/arm.h (TARGET_I8MM): New macro.
17228 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
17229 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
17230 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
17231 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
17232 (v8_6_a_simd_variants): New.
17233 (v8_*_a_simd_variants): Add i8mm and bf16.
17234 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
17236 2020-01-02 Jakub Jelinek <jakub@redhat.com>
17239 * predict.c (compute_function_frequency): Don't call
17240 warn_function_cold on functions that already have cold attribute.
17242 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
17245 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
17246 COMDAT group function labels in .data.rel.ro.local section.
17247 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
17250 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
17251 comparison_operator in B and S integer comparisons. Likewise, use
17252 ordered_comparison_operator instead of cmpib_comparison_operator in
17254 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
17256 2020-01-01 Jakub Jelinek <jakub@redhat.com>
17258 Update copyright years.
17260 * gcc.c (process_command): Update copyright notice dates.
17261 * gcov-dump.c (print_version): Ditto.
17262 * gcov.c (print_version): Ditto.
17263 * gcov-tool.c (print_version): Ditto.
17264 * gengtype.c (create_file): Ditto.
17265 * doc/cpp.texi: Bump @copying's copyright year.
17266 * doc/cppinternals.texi: Ditto.
17267 * doc/gcc.texi: Ditto.
17268 * doc/gccint.texi: Ditto.
17269 * doc/gcov.texi: Ditto.
17270 * doc/install.texi: Ditto.
17271 * doc/invoke.texi: Ditto.
17273 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
17275 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
17278 2020-01-01 Jakub Jelinek <jakub@redhat.com>
17280 PR tree-optimization/93098
17281 * match.pd (popcount): For shift amounts, use integer_onep
17282 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
17283 tests. Make sure that precision is power of two larger than or equal
17284 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
17285 instead of ULL suffixed constants. Formatting fixes.
17287 Copyright (C) 2020 Free Software Foundation, Inc.
17289 Copying and distribution of this file, with or without modification,
17290 are permitted in any medium without royalty provided the copyright
17291 notice and this notice are preserved.