1 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
4 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
5 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
6 when only building rm-profile multilibs.
8 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
11 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
12 lattice for a value to check.
13 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
14 finite propagation in self-recursive scc.
16 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
18 * ipa-inline.c (caller_growth_limits): Restore the AND.
20 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
22 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
23 (VEC_ALLREG_ALT): New iterator.
24 (VEC_ALLREG_INT_MODE): New iterator.
25 (VCMP_MODE): New iterator.
26 (VCMP_MODE_INT): New iterator.
27 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
28 (vec_cmp<u>v64qidi): New define_expand.
29 (vec_cmp<mode>di_exec): Use VCMP_MODE.
30 (vec_cmpu<mode>di_exec): New define_expand.
31 (vec_cmp<u>v64qidi_exec): New define_expand.
32 (vec_cmp<mode>di_dup): Use VCMP_MODE.
33 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
34 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
35 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
36 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
37 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
38 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
39 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
40 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
41 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
43 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
44 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
46 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
48 * config/gcn/constraints.md (DA): Update description and match.
51 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
53 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
54 Implement 'Db' mixed immediate type.
55 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
56 (addcv64si3_dup<exec_vcc>): Delete.
57 (subcv64si3<exec_vcc>): Rework constraints.
58 (addv64di3): Rework constraints.
59 (addv64di3_exec): Rework constraints.
60 (subv64di3): Rework constraints.
61 (addv64di3_dup): Delete.
62 (addv64di3_dup_exec): Delete.
63 (addv64di3_zext): Rework constraints.
64 (addv64di3_zext_exec): Rework constraints.
65 (addv64di3_zext_dup): Rework constraints.
66 (addv64di3_zext_dup_exec): Rework constraints.
67 (addv64di3_zext_dup2): Rework constraints.
68 (addv64di3_zext_dup2_exec): Rework constraints.
69 (addv64di3_sext_dup2): Rework constraints.
70 (addv64di3_sext_dup2_exec): Rework constraints.
72 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
74 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
75 existing target checks.
77 2020-01-07 Richard Biener <rguenther@suse.de>
79 * doc/install.texi: Bump minimal supported MPC version.
81 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
83 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
84 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
85 * langhooks.c: Include stor-layout.h.
86 (lhd_simulate_enum_decl): New function.
87 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
88 handle_arm_sve_h for the LTO frontend.
89 (register_vector_type): Cope with null returns from pushdecl.
91 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
93 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
94 (aarch64_sve::nvectors_if_data_type): Replace with...
95 (aarch64_sve::builtin_type_p): ...this.
96 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
97 (find_vector_type): Delete.
98 (add_sve_type_attribute): New function.
99 (lookup_sve_type_attribute): Likewise.
100 (register_builtin_types): Add an "SVE type" attribute to each type.
101 (register_tuple_type): Likewise.
102 (svbool_type_p, nvectors_if_data_type): Delete.
103 (mangle_builtin_type): Use lookup_sve_type_attribute.
104 (builtin_type_p): Likewise. Add an overload that returns the
105 number of constituent vector and predicate registers.
106 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
107 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
108 instead of aarch64_sve_argument_p.
109 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
110 (aarch64_pass_by_reference): Likewise.
111 (aarch64_function_value_1): Likewise.
112 (aarch64_return_in_memory): Likewise.
113 (aarch64_layout_arg): Likewise.
115 2020-01-07 Jakub Jelinek <jakub@redhat.com>
117 PR tree-optimization/93156
118 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
119 least significant bit is always clear.
121 PR tree-optimization/93118
122 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
123 simplifier with two intermediate conversions.
125 2020-01-07 Martin Liska <mliska@suse.cz>
127 * params.opt: Add Optimization for various parameters.
129 2020-01-07 Martin Liska <mliska@suse.cz>
132 * doc/extend.texi: Explain cloning for target_clone
135 2020-01-07 Martin Liska <mliska@suse.cz>
137 PR tree-optimization/92860
138 * common.opt: Make in Optimization option
139 as it is affected by -O0, which is an Optimization
141 * tree-inline.c (tree_inlinable_function_p):
142 Use opt_for_fn for warn_inline.
143 (expand_call_inline): Likewise.
145 2020-01-07 Martin Liska <mliska@suse.cz>
147 PR tree-optimization/92860
148 * common.opt: Make flag_ree as optimization
151 2020-01-07 Martin Liska <mliska@suse.cz>
153 PR optimization/92860
154 * params.opt: Mark param_min_crossjump_insns with Optimization
157 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
159 * ipa-inline-analysis.c (estimate_growth): Fix typo.
160 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
162 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
164 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
165 helper function to return the valid addressing formats for a given
166 hard register and mode.
167 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
169 * config/rs6000/constraints.md (Q constraint): Update
171 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
174 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
175 Use 'Q' for doing vector extract from memory.
176 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
178 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
179 doing vector extract from memory.
180 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
183 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
184 for the offset being 34-bits when -mcpu=future is used.
186 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
188 * config/pa/pa.md: Revert change to use ordered_comparison_operator
189 instead of cmpib_comparison_operator in cmpib patterns.
190 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
191 of cmpib_comparison_operator. Revise comment.
193 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
195 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
196 in an IFN_DIV_POW2 node to be equal.
198 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
200 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
201 (vect_check_scalar_mask): ...this.
202 (vectorizable_store, vectorizable_load): Update call accordingly.
203 (vectorizable_call): Use vect_check_scalar_mask to check the mask
204 argument in calls to conditional internal functions.
206 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
208 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
210 (subv64di3_exec): Likewise.
212 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
214 * config/mips/mips.c (vr4130_align_insns): Fix typo.
215 * doc/md.texi (movstr): Likewise.
217 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
219 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
222 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
224 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
226 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
227 to a temporary file and use move-if-change to update the real
228 file where necessary.
230 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
232 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
233 rather than Upa for CPY /M.
235 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
237 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
240 2020-01-06 Martin Liska <mliska@suse.cz>
242 PR tree-optimization/92860
243 * params.opt: Mark param_max_combine_insns with Optimization
246 2020-01-05 Jakub Jelinek <jakub@redhat.com>
249 * config/i386/i386.md (SWIDWI): New mode iterator.
250 (DWI, dwi): Add TImode variants.
251 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
252 <general_hilo_operand> instead of <general_operand>. Use
253 CONST_SCALAR_INT_P instead of CONST_INT_P.
254 (*addv<mode>4_1): Rename to ...
255 (addv<mode>4_1): ... this.
256 (QWI): New mode attribute.
257 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
258 define_insn_and_split patterns.
259 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
261 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
262 <general_hilo_operand> instead of <general_operand>.
263 (*addcarry<mode>_1): New define_insn.
264 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
266 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
268 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
269 Use "call" instead of "set".
271 2020-01-03 Martin Jambor <mjambor@suse.cz>
274 * ipa-cp.c (print_all_lattices): Skip functions without info.
276 2020-01-03 Jakub Jelinek <jakub@redhat.com>
279 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
280 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
281 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
285 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
287 (mprefer-vector-width=): Add Save.
288 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
289 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
290 (ix86_debug_options, ix86_function_specific_print): Adjust
291 ix86_target_string callers.
292 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
293 (ix86_valid_target_attribute_tree): Likewise.
294 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
295 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
296 ix86_target_string caller.
299 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
300 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
301 instead of gen_int_shift_amount + convert_modes.
303 PR rtl-optimization/93088
304 * loop-iv.c (find_single_def_src): Punt after looking through
305 128 reg copies for regs with single definitions. Move definitions
308 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
310 * config/arm/arm-c.c (arm_cpu_builtins): Define
311 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
312 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
313 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
314 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
315 * config/arm/arm-tables.opt: Regenerated.
316 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
317 arm_arch_i8mm and arm_arch_bf16 when enabled.
318 * config/arm/arm.h (TARGET_I8MM): New macro.
319 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
320 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
321 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
322 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
323 (v8_6_a_simd_variants): New.
324 (v8_*_a_simd_variants): Add i8mm and bf16.
325 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
327 2020-01-02 Jakub Jelinek <jakub@redhat.com>
330 * predict.c (compute_function_frequency): Don't call
331 warn_function_cold on functions that already have cold attribute.
333 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
336 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
337 COMDAT group function labels in .data.rel.ro.local section.
338 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
341 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
342 comparison_operator in B and S integer comparisons. Likewise, use
343 ordered_comparison_operator instead of cmpib_comparison_operator in
345 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
347 2020-01-01 Jakub Jelinek <jakub@redhat.com>
349 Update copyright years.
351 * gcc.c (process_command): Update copyright notice dates.
352 * gcov-dump.c (print_version): Ditto.
353 * gcov.c (print_version): Ditto.
354 * gcov-tool.c (print_version): Ditto.
355 * gengtype.c (create_file): Ditto.
356 * doc/cpp.texi: Bump @copying's copyright year.
357 * doc/cppinternals.texi: Ditto.
358 * doc/gcc.texi: Ditto.
359 * doc/gccint.texi: Ditto.
360 * doc/gcov.texi: Ditto.
361 * doc/install.texi: Ditto.
362 * doc/invoke.texi: Ditto.
364 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
366 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
369 2020-01-01 Jakub Jelinek <jakub@redhat.com>
371 PR tree-optimization/93098
372 * match.pd (popcount): For shift amounts, use integer_onep
373 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
374 tests. Make sure that precision is power of two larger than or equal
375 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
376 instead of ULL suffixed constants. Formatting fixes.
378 Copyright (C) 2020 Free Software Foundation, Inc.
380 Copying and distribution of this file, with or without modification,
381 are permitted in any medium without royalty provided the copyright
382 notice and this notice are preserved.