1 2019-01-08 Richard Biener <rguenther@suse.de>
4 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified.
5 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust
6 virtual operand, also updating SSA use.
7 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction):
8 Update stmt after resetting virtual operand.
9 (tree_loop_interchange::move_code_to_inner_loop): Likewise.
10 * gimple-iterator.c (gsi_remove): When not removing the stmt
11 permanently do not delink immediate uses or mark the stmt modified.
13 2020-01-08 Martin Liska <mliska@suse.cz>
15 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name.
16 (ipa_call_context::estimate_size_and_time): Likewise.
17 (inline_analyze_function): Likewise.
19 2020-01-08 Martin Liska <mliska@suse.cz>
21 * cgraph.c (cgraph_node::dump): Use systematically
24 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
26 Add -nodevicespecs option for avr.
29 * config/avr/avr.opt (-nodevicespecs): New driver option.
30 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue
31 "-specs=device-specs/..." if that option is not set.
32 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
34 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
36 Implement 64-bit double functions for avr.
39 * config.gcc (tm_defines) [target=avr]: Support --with-libf7,
40 --with-double-comparison.
41 * doc/install.texi: Document them.
42 * config/avr/avr-c.c (avr_cpu_cpp_builtins)
43 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
44 <WITH_DOUBLE_COMPARISON>: New built-in defines.
45 * doc/invoke.texi (AVR Built-in Macros): Document them.
46 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
47 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
48 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
50 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
53 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
54 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
55 when only building rm-profile multilibs.
57 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
60 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
61 lattice for a value to check.
62 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
63 finite propagation in self-recursive scc.
65 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
67 * ipa-inline.c (caller_growth_limits): Restore the AND.
69 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
71 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
72 (VEC_ALLREG_ALT): New iterator.
73 (VEC_ALLREG_INT_MODE): New iterator.
74 (VCMP_MODE): New iterator.
75 (VCMP_MODE_INT): New iterator.
76 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
77 (vec_cmp<u>v64qidi): New define_expand.
78 (vec_cmp<mode>di_exec): Use VCMP_MODE.
79 (vec_cmpu<mode>di_exec): New define_expand.
80 (vec_cmp<u>v64qidi_exec): New define_expand.
81 (vec_cmp<mode>di_dup): Use VCMP_MODE.
82 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
83 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
84 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
85 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
86 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
87 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
88 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
89 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
90 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
92 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
93 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
95 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
97 * config/gcn/constraints.md (DA): Update description and match.
100 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
102 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
103 Implement 'Db' mixed immediate type.
104 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
105 (addcv64si3_dup<exec_vcc>): Delete.
106 (subcv64si3<exec_vcc>): Rework constraints.
107 (addv64di3): Rework constraints.
108 (addv64di3_exec): Rework constraints.
109 (subv64di3): Rework constraints.
110 (addv64di3_dup): Delete.
111 (addv64di3_dup_exec): Delete.
112 (addv64di3_zext): Rework constraints.
113 (addv64di3_zext_exec): Rework constraints.
114 (addv64di3_zext_dup): Rework constraints.
115 (addv64di3_zext_dup_exec): Rework constraints.
116 (addv64di3_zext_dup2): Rework constraints.
117 (addv64di3_zext_dup2_exec): Rework constraints.
118 (addv64di3_sext_dup2): Rework constraints.
119 (addv64di3_sext_dup2_exec): Rework constraints.
121 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
123 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
124 existing target checks.
126 2020-01-07 Richard Biener <rguenther@suse.de>
128 * doc/install.texi: Bump minimal supported MPC version.
130 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
132 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
133 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
134 * langhooks.c: Include stor-layout.h.
135 (lhd_simulate_enum_decl): New function.
136 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
137 handle_arm_sve_h for the LTO frontend.
138 (register_vector_type): Cope with null returns from pushdecl.
140 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
142 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
143 (aarch64_sve::nvectors_if_data_type): Replace with...
144 (aarch64_sve::builtin_type_p): ...this.
145 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
146 (find_vector_type): Delete.
147 (add_sve_type_attribute): New function.
148 (lookup_sve_type_attribute): Likewise.
149 (register_builtin_types): Add an "SVE type" attribute to each type.
150 (register_tuple_type): Likewise.
151 (svbool_type_p, nvectors_if_data_type): Delete.
152 (mangle_builtin_type): Use lookup_sve_type_attribute.
153 (builtin_type_p): Likewise. Add an overload that returns the
154 number of constituent vector and predicate registers.
155 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
156 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
157 instead of aarch64_sve_argument_p.
158 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
159 (aarch64_pass_by_reference): Likewise.
160 (aarch64_function_value_1): Likewise.
161 (aarch64_return_in_memory): Likewise.
162 (aarch64_layout_arg): Likewise.
164 2020-01-07 Jakub Jelinek <jakub@redhat.com>
166 PR tree-optimization/93156
167 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
168 least significant bit is always clear.
170 PR tree-optimization/93118
171 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
172 simplifier with two intermediate conversions.
174 2020-01-07 Martin Liska <mliska@suse.cz>
176 * params.opt: Add Optimization for various parameters.
178 2020-01-07 Martin Liska <mliska@suse.cz>
181 * doc/extend.texi: Explain cloning for target_clone
184 2020-01-07 Martin Liska <mliska@suse.cz>
186 PR tree-optimization/92860
187 * common.opt: Make in Optimization option
188 as it is affected by -O0, which is an Optimization
190 * tree-inline.c (tree_inlinable_function_p):
191 Use opt_for_fn for warn_inline.
192 (expand_call_inline): Likewise.
194 2020-01-07 Martin Liska <mliska@suse.cz>
196 PR tree-optimization/92860
197 * common.opt: Make flag_ree as optimization
200 2020-01-07 Martin Liska <mliska@suse.cz>
202 PR optimization/92860
203 * params.opt: Mark param_min_crossjump_insns with Optimization
206 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
208 * ipa-inline-analysis.c (estimate_growth): Fix typo.
209 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
211 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
213 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
214 helper function to return the valid addressing formats for a given
215 hard register and mode.
216 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
218 * config/rs6000/constraints.md (Q constraint): Update
220 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
223 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
224 Use 'Q' for doing vector extract from memory.
225 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
227 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
228 doing vector extract from memory.
229 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
232 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
233 for the offset being 34-bits when -mcpu=future is used.
235 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
237 * config/pa/pa.md: Revert change to use ordered_comparison_operator
238 instead of cmpib_comparison_operator in cmpib patterns.
239 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
240 of cmpib_comparison_operator. Revise comment.
242 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
244 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
245 in an IFN_DIV_POW2 node to be equal.
247 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
249 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
250 (vect_check_scalar_mask): ...this.
251 (vectorizable_store, vectorizable_load): Update call accordingly.
252 (vectorizable_call): Use vect_check_scalar_mask to check the mask
253 argument in calls to conditional internal functions.
255 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
257 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
259 (subv64di3_exec): Likewise.
261 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
263 * config/mips/mips.c (vr4130_align_insns): Fix typo.
264 * doc/md.texi (movstr): Likewise.
266 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
268 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
271 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
273 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
275 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
276 to a temporary file and use move-if-change to update the real
277 file where necessary.
279 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
281 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
282 rather than Upa for CPY /M.
284 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
286 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
289 2020-01-06 Martin Liska <mliska@suse.cz>
291 PR tree-optimization/92860
292 * params.opt: Mark param_max_combine_insns with Optimization
295 2020-01-05 Jakub Jelinek <jakub@redhat.com>
298 * config/i386/i386.md (SWIDWI): New mode iterator.
299 (DWI, dwi): Add TImode variants.
300 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
301 <general_hilo_operand> instead of <general_operand>. Use
302 CONST_SCALAR_INT_P instead of CONST_INT_P.
303 (*addv<mode>4_1): Rename to ...
304 (addv<mode>4_1): ... this.
305 (QWI): New mode attribute.
306 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
307 define_insn_and_split patterns.
308 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
310 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
311 <general_hilo_operand> instead of <general_operand>.
312 (*addcarry<mode>_1): New define_insn.
313 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
315 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
317 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
318 Use "call" instead of "set".
320 2020-01-03 Martin Jambor <mjambor@suse.cz>
323 * ipa-cp.c (print_all_lattices): Skip functions without info.
325 2020-01-03 Jakub Jelinek <jakub@redhat.com>
328 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
329 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
330 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
334 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
336 (mprefer-vector-width=): Add Save.
337 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
338 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
339 (ix86_debug_options, ix86_function_specific_print): Adjust
340 ix86_target_string callers.
341 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
342 (ix86_valid_target_attribute_tree): Likewise.
343 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
344 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
345 ix86_target_string caller.
348 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
349 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
350 instead of gen_int_shift_amount + convert_modes.
352 PR rtl-optimization/93088
353 * loop-iv.c (find_single_def_src): Punt after looking through
354 128 reg copies for regs with single definitions. Move definitions
357 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
359 * config/arm/arm-c.c (arm_cpu_builtins): Define
360 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
361 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
362 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
363 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
364 * config/arm/arm-tables.opt: Regenerated.
365 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
366 arm_arch_i8mm and arm_arch_bf16 when enabled.
367 * config/arm/arm.h (TARGET_I8MM): New macro.
368 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
369 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
370 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
371 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
372 (v8_6_a_simd_variants): New.
373 (v8_*_a_simd_variants): Add i8mm and bf16.
374 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
376 2020-01-02 Jakub Jelinek <jakub@redhat.com>
379 * predict.c (compute_function_frequency): Don't call
380 warn_function_cold on functions that already have cold attribute.
382 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
385 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
386 COMDAT group function labels in .data.rel.ro.local section.
387 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
390 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
391 comparison_operator in B and S integer comparisons. Likewise, use
392 ordered_comparison_operator instead of cmpib_comparison_operator in
394 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
396 2020-01-01 Jakub Jelinek <jakub@redhat.com>
398 Update copyright years.
400 * gcc.c (process_command): Update copyright notice dates.
401 * gcov-dump.c (print_version): Ditto.
402 * gcov.c (print_version): Ditto.
403 * gcov-tool.c (print_version): Ditto.
404 * gengtype.c (create_file): Ditto.
405 * doc/cpp.texi: Bump @copying's copyright year.
406 * doc/cppinternals.texi: Ditto.
407 * doc/gcc.texi: Ditto.
408 * doc/gccint.texi: Ditto.
409 * doc/gcov.texi: Ditto.
410 * doc/install.texi: Ditto.
411 * doc/invoke.texi: Ditto.
413 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
415 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
418 2020-01-01 Jakub Jelinek <jakub@redhat.com>
420 PR tree-optimization/93098
421 * match.pd (popcount): For shift amounts, use integer_onep
422 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
423 tests. Make sure that precision is power of two larger than or equal
424 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
425 instead of ULL suffixed constants. Formatting fixes.
427 Copyright (C) 2020 Free Software Foundation, Inc.
429 Copying and distribution of this file, with or without modification,
430 are permitted in any medium without royalty provided the copyright
431 notice and this notice are preserved.