2 /* Perform branch target register load optimizations.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
27 #include "hard-reg-set.h"
33 #include "insn-attr.h"
37 #include "diagnostic-core.h"
38 #include "tree-pass.h"
43 /* Target register optimizations - these are performed after reload. */
45 typedef struct btr_def_group_s
47 struct btr_def_group_s
*next
;
49 struct btr_def_s
*members
;
52 typedef struct btr_user_s
54 struct btr_user_s
*next
;
58 /* If INSN has a single use of a single branch register, then
59 USE points to it within INSN. If there is more than
60 one branch register use, or the use is in some way ambiguous,
64 int first_reaching_def
;
65 char other_use_this_block
;
68 /* btr_def structs appear on three lists:
69 1. A list of all btr_def structures (head is
70 ALL_BTR_DEFS, linked by the NEXT field).
71 2. A list of branch reg definitions per basic block (head is
72 BB_BTR_DEFS[i], linked by the NEXT_THIS_BB field).
73 3. A list of all branch reg definitions belonging to the same
74 group (head is in a BTR_DEF_GROUP struct, linked by
75 NEXT_THIS_GROUP field). */
77 typedef struct btr_def_s
79 struct btr_def_s
*next_this_bb
;
80 struct btr_def_s
*next_this_group
;
86 /* For a branch register setting insn that has a constant
87 source (i.e. a label), group links together all the
88 insns with the same source. For other branch register
89 setting insns, group is NULL. */
92 /* If this def has a reaching use which is not a simple use
93 in a branch instruction, then has_ambiguous_use will be true,
94 and we will not attempt to migrate this definition. */
95 char has_ambiguous_use
;
96 /* live_range is an approximation to the true live range for this
97 def/use web, because it records the set of blocks that contain
98 the live range. There could be other live ranges for the same
99 branch register in that set of blocks, either in the block
100 containing the def (before the def), or in a block containing
101 a use (after the use). If there are such other live ranges, then
102 other_btr_uses_before_def or other_btr_uses_after_use must be set true
104 char other_btr_uses_before_def
;
105 char other_btr_uses_after_use
;
106 /* We set own_end when we have moved a definition into a dominator.
107 Thus, when a later combination removes this definition again, we know
108 to clear out trs_live_at_end again. */
113 static int issue_rate
;
115 static int basic_block_freq (const_basic_block
);
116 static int insn_sets_btr_p (const_rtx
, int, int *);
117 static rtx
*find_btr_use (rtx
);
118 static int btr_referenced_p (rtx
, rtx
*);
119 static int find_btr_reference (rtx
*, void *);
120 static void find_btr_def_group (btr_def_group
*, btr_def
);
121 static btr_def
add_btr_def (fibheap_t
, basic_block
, int, rtx
,
122 unsigned int, int, btr_def_group
*);
123 static btr_user
new_btr_user (basic_block
, int, rtx
);
124 static void dump_hard_reg_set (HARD_REG_SET
);
125 static void dump_btrs_live (int);
126 static void note_other_use_this_block (unsigned int, btr_user
);
127 static void compute_defs_uses_and_gen (fibheap_t
, btr_def
*,btr_user
*,
128 sbitmap
*, sbitmap
*, HARD_REG_SET
*);
129 static void compute_kill (sbitmap
*, sbitmap
*, HARD_REG_SET
*);
130 static void compute_out (sbitmap
*bb_out
, sbitmap
*, sbitmap
*, int);
131 static void link_btr_uses (btr_def
*, btr_user
*, sbitmap
*, sbitmap
*, int);
132 static void build_btr_def_use_webs (fibheap_t
);
133 static int block_at_edge_of_live_range_p (int, btr_def
);
134 static void clear_btr_from_live_range (btr_def def
);
135 static void add_btr_to_live_range (btr_def
, int);
136 static void augment_live_range (bitmap
, HARD_REG_SET
*, basic_block
,
138 static int choose_btr (HARD_REG_SET
);
139 static void combine_btr_defs (btr_def
, HARD_REG_SET
*);
140 static void btr_def_live_range (btr_def
, HARD_REG_SET
*);
141 static void move_btr_def (basic_block
, int, btr_def
, bitmap
, HARD_REG_SET
*);
142 static int migrate_btr_def (btr_def
, int);
143 static void migrate_btr_defs (enum reg_class
, int);
144 static int can_move_up (const_basic_block
, const_rtx
, int);
145 static void note_btr_set (rtx
, const_rtx
, void *);
147 /* The following code performs code motion of target load instructions
148 (instructions that set branch target registers), to move them
149 forward away from the branch instructions and out of loops (or,
150 more generally, from a more frequently executed place to a less
151 frequently executed place).
152 Moving target load instructions further in front of the branch
153 instruction that uses the target register value means that the hardware
154 has a better chance of preloading the instructions at the branch
155 target by the time the branch is reached. This avoids bubbles
156 when a taken branch needs to flush out the pipeline.
157 Moving target load instructions out of loops means they are executed
160 /* An obstack to hold the def-use web data structures built up for
161 migrating branch target load instructions. */
162 static struct obstack migrate_btrl_obstack
;
164 /* Array indexed by basic block number, giving the set of registers
165 live in that block. */
166 static HARD_REG_SET
*btrs_live
;
168 /* Array indexed by basic block number, giving the set of registers live at
169 the end of that block, including any uses by a final jump insn, if any. */
170 static HARD_REG_SET
*btrs_live_at_end
;
172 /* Set of all target registers that we are willing to allocate. */
173 static HARD_REG_SET all_btrs
;
175 /* Provide lower and upper bounds for target register numbers, so that
176 we don't need to search through all the hard registers all the time. */
177 static int first_btr
, last_btr
;
181 /* Return an estimate of the frequency of execution of block bb. */
183 basic_block_freq (const_basic_block bb
)
185 return bb
->frequency
;
188 static rtx
*btr_reference_found
;
190 /* A subroutine of btr_referenced_p, called through for_each_rtx.
191 PREG is a pointer to an rtx that is to be excluded from the
192 traversal. If we find a reference to a target register anywhere
193 else, return 1, and put a pointer to it into btr_reference_found. */
195 find_btr_reference (rtx
*px
, void *preg
)
204 if (overlaps_hard_reg_set_p (all_btrs
, GET_MODE (x
), REGNO (x
)))
206 btr_reference_found
= px
;
212 /* Return nonzero if X references (sets or reads) any branch target register.
213 If EXCLUDEP is set, disregard any references within the rtx pointed to
214 by it. If returning nonzero, also set btr_reference_found as above. */
216 btr_referenced_p (rtx x
, rtx
*excludep
)
218 return for_each_rtx (&x
, find_btr_reference
, excludep
);
221 /* Return true if insn is an instruction that sets a target register.
222 if CHECK_CONST is true, only return true if the source is constant.
223 If such a set is found and REGNO is nonzero, assign the register number
224 of the destination register to *REGNO. */
226 insn_sets_btr_p (const_rtx insn
, int check_const
, int *regno
)
230 if (NONJUMP_INSN_P (insn
)
231 && (set
= single_set (insn
)))
233 rtx dest
= SET_DEST (set
);
234 rtx src
= SET_SRC (set
);
236 if (GET_CODE (dest
) == SUBREG
)
237 dest
= XEXP (dest
, 0);
240 && TEST_HARD_REG_BIT (all_btrs
, REGNO (dest
)))
242 gcc_assert (!btr_referenced_p (src
, NULL
));
244 if (!check_const
|| CONSTANT_P (src
))
247 *regno
= REGNO (dest
);
255 /* Find and return a use of a target register within an instruction INSN. */
257 find_btr_use (rtx insn
)
259 return btr_referenced_p (insn
, NULL
) ? btr_reference_found
: NULL
;
262 /* Find the group that the target register definition DEF belongs
263 to in the list starting with *ALL_BTR_DEF_GROUPS. If no such
264 group exists, create one. Add def to the group. */
266 find_btr_def_group (btr_def_group
*all_btr_def_groups
, btr_def def
)
268 if (insn_sets_btr_p (def
->insn
, 1, NULL
))
270 btr_def_group this_group
;
271 rtx def_src
= SET_SRC (single_set (def
->insn
));
273 /* ?? This linear search is an efficiency concern, particularly
274 as the search will almost always fail to find a match. */
275 for (this_group
= *all_btr_def_groups
;
277 this_group
= this_group
->next
)
278 if (rtx_equal_p (def_src
, this_group
->src
))
283 this_group
= XOBNEW (&migrate_btrl_obstack
, struct btr_def_group_s
);
284 this_group
->src
= def_src
;
285 this_group
->members
= NULL
;
286 this_group
->next
= *all_btr_def_groups
;
287 *all_btr_def_groups
= this_group
;
289 def
->group
= this_group
;
290 def
->next_this_group
= this_group
->members
;
291 this_group
->members
= def
;
297 /* Create a new target register definition structure, for a definition in
298 block BB, instruction INSN, and insert it into ALL_BTR_DEFS. Return
299 the new definition. */
301 add_btr_def (fibheap_t all_btr_defs
, basic_block bb
, int insn_luid
, rtx insn
,
302 unsigned int dest_reg
, int other_btr_uses_before_def
,
303 btr_def_group
*all_btr_def_groups
)
305 btr_def this_def
= XOBNEW (&migrate_btrl_obstack
, struct btr_def_s
);
307 this_def
->luid
= insn_luid
;
308 this_def
->insn
= insn
;
309 this_def
->btr
= dest_reg
;
310 this_def
->cost
= basic_block_freq (bb
);
311 this_def
->has_ambiguous_use
= 0;
312 this_def
->other_btr_uses_before_def
= other_btr_uses_before_def
;
313 this_def
->other_btr_uses_after_use
= 0;
314 this_def
->next_this_bb
= NULL
;
315 this_def
->next_this_group
= NULL
;
316 this_def
->uses
= NULL
;
317 this_def
->live_range
= NULL
;
318 find_btr_def_group (all_btr_def_groups
, this_def
);
320 fibheap_insert (all_btr_defs
, -this_def
->cost
, this_def
);
324 "Found target reg definition: sets %u { bb %d, insn %d }%s priority %d\n",
325 dest_reg
, bb
->index
, INSN_UID (insn
),
326 (this_def
->group
? "" : ":not const"), this_def
->cost
);
331 /* Create a new target register user structure, for a use in block BB,
332 instruction INSN. Return the new user. */
334 new_btr_user (basic_block bb
, int insn_luid
, rtx insn
)
336 /* This instruction reads target registers. We need
337 to decide whether we can replace all target register
340 rtx
*usep
= find_btr_use (PATTERN (insn
));
342 btr_user user
= NULL
;
346 int unambiguous_single_use
;
348 /* We want to ensure that USE is the only use of a target
349 register in INSN, so that we know that to rewrite INSN to use
350 a different target register, all we have to do is replace USE. */
351 unambiguous_single_use
= !btr_referenced_p (PATTERN (insn
), usep
);
352 if (!unambiguous_single_use
)
355 use
= usep
? *usep
: NULL_RTX
;
356 user
= XOBNEW (&migrate_btrl_obstack
, struct btr_user_s
);
358 user
->luid
= insn_luid
;
361 user
->other_use_this_block
= 0;
363 user
->n_reaching_defs
= 0;
364 user
->first_reaching_def
= -1;
368 fprintf (dump_file
, "Uses target reg: { bb %d, insn %d }",
369 bb
->index
, INSN_UID (insn
));
372 fprintf (dump_file
, ": unambiguous use of reg %d\n",
379 /* Write the contents of S to the dump file. */
381 dump_hard_reg_set (HARD_REG_SET s
)
384 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
385 if (TEST_HARD_REG_BIT (s
, reg
))
386 fprintf (dump_file
, " %d", reg
);
389 /* Write the set of target regs live in block BB to the dump file. */
391 dump_btrs_live (int bb
)
393 fprintf (dump_file
, "BB%d live:", bb
);
394 dump_hard_reg_set (btrs_live
[bb
]);
395 fprintf (dump_file
, "\n");
398 /* REGNO is the number of a branch target register that is being used or
399 set. USERS_THIS_BB is a list of preceding branch target register users;
400 If any of them use the same register, set their other_use_this_block
403 note_other_use_this_block (unsigned int regno
, btr_user users_this_bb
)
407 for (user
= users_this_bb
; user
!= NULL
; user
= user
->next
)
408 if (user
->use
&& REGNO (user
->use
) == regno
)
409 user
->other_use_this_block
= 1;
413 btr_user users_this_bb
;
414 HARD_REG_SET btrs_written_in_block
;
415 HARD_REG_SET btrs_live_in_block
;
420 /* Called via note_stores or directly to register stores into /
421 clobbers of a branch target register DEST that are not recognized as
422 straightforward definitions. DATA points to information about the
423 current basic block that needs updating. */
425 note_btr_set (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
, void *data
)
427 defs_uses_info
*info
= (defs_uses_info
*) data
;
428 int regno
, end_regno
;
432 regno
= REGNO (dest
);
433 end_regno
= END_HARD_REGNO (dest
);
434 for (; regno
< end_regno
; regno
++)
435 if (TEST_HARD_REG_BIT (all_btrs
, regno
))
437 note_other_use_this_block (regno
, info
->users_this_bb
);
438 SET_HARD_REG_BIT (info
->btrs_written_in_block
, regno
);
439 SET_HARD_REG_BIT (info
->btrs_live_in_block
, regno
);
440 bitmap_and_compl (info
->bb_gen
, info
->bb_gen
,
441 info
->btr_defset
[regno
- first_btr
]);
446 compute_defs_uses_and_gen (fibheap_t all_btr_defs
, btr_def
*def_array
,
447 btr_user
*use_array
, sbitmap
*btr_defset
,
448 sbitmap
*bb_gen
, HARD_REG_SET
*btrs_written
)
450 /* Scan the code building up the set of all defs and all uses.
451 For each target register, build the set of defs of that register.
452 For each block, calculate the set of target registers
453 written in that block.
454 Also calculate the set of btrs ever live in that block.
458 btr_def_group all_btr_def_groups
= NULL
;
461 bitmap_vector_clear (bb_gen
, last_basic_block
);
462 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
464 basic_block bb
= BASIC_BLOCK (i
);
466 btr_def defs_this_bb
= NULL
;
471 info
.users_this_bb
= NULL
;
472 info
.bb_gen
= bb_gen
[i
];
473 info
.btr_defset
= btr_defset
;
475 CLEAR_HARD_REG_SET (info
.btrs_live_in_block
);
476 CLEAR_HARD_REG_SET (info
.btrs_written_in_block
);
477 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
478 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
479 && REGNO_REG_SET_P (df_get_live_in (bb
), reg
))
480 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
482 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
484 insn
= NEXT_INSN (insn
), insn_luid
++)
489 int insn_uid
= INSN_UID (insn
);
491 if (insn_sets_btr_p (insn
, 0, ®no
))
493 btr_def def
= add_btr_def (
494 all_btr_defs
, bb
, insn_luid
, insn
, regno
,
495 TEST_HARD_REG_BIT (info
.btrs_live_in_block
, regno
),
496 &all_btr_def_groups
);
498 def_array
[insn_uid
] = def
;
499 SET_HARD_REG_BIT (info
.btrs_written_in_block
, regno
);
500 SET_HARD_REG_BIT (info
.btrs_live_in_block
, regno
);
501 bitmap_and_compl (bb_gen
[i
], bb_gen
[i
],
502 btr_defset
[regno
- first_btr
]);
503 SET_BIT (bb_gen
[i
], insn_uid
);
504 def
->next_this_bb
= defs_this_bb
;
506 SET_BIT (btr_defset
[regno
- first_btr
], insn_uid
);
507 note_other_use_this_block (regno
, info
.users_this_bb
);
509 /* Check for the blockage emitted by expand_nl_goto_receiver. */
510 else if (cfun
->has_nonlocal_label
511 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
)
515 /* Do the equivalent of calling note_other_use_this_block
516 for every target register. */
517 for (user
= info
.users_this_bb
; user
!= NULL
;
520 user
->other_use_this_block
= 1;
521 IOR_HARD_REG_SET (info
.btrs_written_in_block
, all_btrs
);
522 IOR_HARD_REG_SET (info
.btrs_live_in_block
, all_btrs
);
523 bitmap_clear (info
.bb_gen
);
527 if (btr_referenced_p (PATTERN (insn
), NULL
))
529 btr_user user
= new_btr_user (bb
, insn_luid
, insn
);
531 use_array
[insn_uid
] = user
;
533 SET_HARD_REG_BIT (info
.btrs_live_in_block
,
538 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
539 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
540 && refers_to_regno_p (reg
, reg
+ 1, user
->insn
,
543 note_other_use_this_block (reg
,
545 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
547 note_stores (PATTERN (insn
), note_btr_set
, &info
);
549 user
->next
= info
.users_this_bb
;
550 info
.users_this_bb
= user
;
554 HARD_REG_SET
*clobbered
= &call_used_reg_set
;
555 HARD_REG_SET call_saved
;
556 rtx pat
= PATTERN (insn
);
559 /* Check for sibcall. */
560 if (GET_CODE (pat
) == PARALLEL
)
561 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
562 if (ANY_RETURN_P (XVECEXP (pat
, 0, i
)))
564 COMPL_HARD_REG_SET (call_saved
,
566 clobbered
= &call_saved
;
569 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
570 if (TEST_HARD_REG_BIT (*clobbered
, regno
))
571 note_btr_set (regno_reg_rtx
[regno
], NULL_RTX
, &info
);
577 COPY_HARD_REG_SET (btrs_live
[i
], info
.btrs_live_in_block
);
578 COPY_HARD_REG_SET (btrs_written
[i
], info
.btrs_written_in_block
);
580 REG_SET_TO_HARD_REG_SET (btrs_live_at_end
[i
], df_get_live_out (bb
));
581 /* If this block ends in a jump insn, add any uses or even clobbers
582 of branch target registers that it might have. */
583 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
) && ! INSN_P (insn
); )
584 insn
= PREV_INSN (insn
);
585 /* ??? for the fall-through edge, it would make sense to insert the
586 btr set on the edge, but that would require to split the block
587 early on so that we can distinguish between dominance from the fall
588 through edge - which can use the call-clobbered registers - from
589 dominance by the throw edge. */
590 if (can_throw_internal (insn
))
594 COPY_HARD_REG_SET (tmp
, call_used_reg_set
);
595 AND_HARD_REG_SET (tmp
, all_btrs
);
596 IOR_HARD_REG_SET (btrs_live_at_end
[i
], tmp
);
599 if (can_throw
|| JUMP_P (insn
))
603 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
604 if (refers_to_regno_p (regno
, regno
+1, insn
, NULL
))
605 SET_HARD_REG_BIT (btrs_live_at_end
[i
], regno
);
614 compute_kill (sbitmap
*bb_kill
, sbitmap
*btr_defset
,
615 HARD_REG_SET
*btrs_written
)
620 /* For each basic block, form the set BB_KILL - the set
621 of definitions that the block kills. */
622 bitmap_vector_clear (bb_kill
, last_basic_block
);
623 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
625 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
626 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
627 && TEST_HARD_REG_BIT (btrs_written
[i
], regno
))
628 bitmap_ior (bb_kill
[i
], bb_kill
[i
],
629 btr_defset
[regno
- first_btr
]);
634 compute_out (sbitmap
*bb_out
, sbitmap
*bb_gen
, sbitmap
*bb_kill
, int max_uid
)
636 /* Perform iterative dataflow:
637 Initially, for all blocks, BB_OUT = BB_GEN.
639 BB_IN = union over predecessors of BB_OUT(pred)
640 BB_OUT = (BB_IN - BB_KILL) + BB_GEN
641 Iterate until the bb_out sets stop growing. */
644 sbitmap bb_in
= sbitmap_alloc (max_uid
);
646 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
647 bitmap_copy (bb_out
[i
], bb_gen
[i
]);
653 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
655 sbitmap_union_of_preds (bb_in
, bb_out
, BASIC_BLOCK (i
));
656 changed
|= bitmap_ior_and_compl (bb_out
[i
], bb_gen
[i
],
660 sbitmap_free (bb_in
);
664 link_btr_uses (btr_def
*def_array
, btr_user
*use_array
, sbitmap
*bb_out
,
665 sbitmap
*btr_defset
, int max_uid
)
668 sbitmap reaching_defs
= sbitmap_alloc (max_uid
);
670 /* Link uses to the uses lists of all of their reaching defs.
671 Count up the number of reaching defs of each use. */
672 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
674 basic_block bb
= BASIC_BLOCK (i
);
678 sbitmap_union_of_preds (reaching_defs
, bb_out
, BASIC_BLOCK (i
));
679 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
681 insn
= NEXT_INSN (insn
))
685 int insn_uid
= INSN_UID (insn
);
687 btr_def def
= def_array
[insn_uid
];
688 btr_user user
= use_array
[insn_uid
];
691 /* Remove all reaching defs of regno except
693 bitmap_and_compl (reaching_defs
, reaching_defs
,
694 btr_defset
[def
->btr
- first_btr
]);
695 SET_BIT(reaching_defs
, insn_uid
);
700 /* Find all the reaching defs for this use. */
701 sbitmap reaching_defs_of_reg
= sbitmap_alloc(max_uid
);
702 unsigned int uid
= 0;
703 sbitmap_iterator sbi
;
707 reaching_defs_of_reg
,
709 btr_defset
[REGNO (user
->use
) - first_btr
]);
714 bitmap_clear (reaching_defs_of_reg
);
715 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
716 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
717 && refers_to_regno_p (reg
, reg
+ 1, user
->insn
,
719 bitmap_or_and (reaching_defs_of_reg
,
720 reaching_defs_of_reg
,
722 btr_defset
[reg
- first_btr
]);
724 EXECUTE_IF_SET_IN_SBITMAP (reaching_defs_of_reg
, 0, uid
, sbi
)
726 btr_def def
= def_array
[uid
];
728 /* We now know that def reaches user. */
732 "Def in insn %d reaches use in insn %d\n",
735 user
->n_reaching_defs
++;
737 def
->has_ambiguous_use
= 1;
738 if (user
->first_reaching_def
!= -1)
739 { /* There is more than one reaching def. This is
740 a rare case, so just give up on this def/use
741 web when it occurs. */
742 def
->has_ambiguous_use
= 1;
743 def_array
[user
->first_reaching_def
]
744 ->has_ambiguous_use
= 1;
747 "(use %d has multiple reaching defs)\n",
751 user
->first_reaching_def
= uid
;
752 if (user
->other_use_this_block
)
753 def
->other_btr_uses_after_use
= 1;
754 user
->next
= def
->uses
;
757 sbitmap_free (reaching_defs_of_reg
);
764 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
765 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
766 && TEST_HARD_REG_BIT (call_used_reg_set
, regno
))
767 bitmap_and_compl (reaching_defs
, reaching_defs
,
768 btr_defset
[regno
- first_btr
]);
773 sbitmap_free (reaching_defs
);
777 build_btr_def_use_webs (fibheap_t all_btr_defs
)
779 const int max_uid
= get_max_uid ();
780 btr_def
*def_array
= XCNEWVEC (btr_def
, max_uid
);
781 btr_user
*use_array
= XCNEWVEC (btr_user
, max_uid
);
782 sbitmap
*btr_defset
= sbitmap_vector_alloc (
783 (last_btr
- first_btr
) + 1, max_uid
);
784 sbitmap
*bb_gen
= sbitmap_vector_alloc (last_basic_block
, max_uid
);
785 HARD_REG_SET
*btrs_written
= XCNEWVEC (HARD_REG_SET
, last_basic_block
);
789 bitmap_vector_clear (btr_defset
, (last_btr
- first_btr
) + 1);
791 compute_defs_uses_and_gen (all_btr_defs
, def_array
, use_array
, btr_defset
,
792 bb_gen
, btrs_written
);
794 bb_kill
= sbitmap_vector_alloc (last_basic_block
, max_uid
);
795 compute_kill (bb_kill
, btr_defset
, btrs_written
);
798 bb_out
= sbitmap_vector_alloc (last_basic_block
, max_uid
);
799 compute_out (bb_out
, bb_gen
, bb_kill
, max_uid
);
801 sbitmap_vector_free (bb_gen
);
802 sbitmap_vector_free (bb_kill
);
804 link_btr_uses (def_array
, use_array
, bb_out
, btr_defset
, max_uid
);
806 sbitmap_vector_free (bb_out
);
807 sbitmap_vector_free (btr_defset
);
812 /* Return true if basic block BB contains the start or end of the
813 live range of the definition DEF, AND there are other live
814 ranges of the same target register that include BB. */
816 block_at_edge_of_live_range_p (int bb
, btr_def def
)
818 if (def
->other_btr_uses_before_def
&& BASIC_BLOCK (bb
) == def
->bb
)
820 else if (def
->other_btr_uses_after_use
)
823 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
824 if (BASIC_BLOCK (bb
) == user
->bb
)
830 /* We are removing the def/use web DEF. The target register
831 used in this web is therefore no longer live in the live range
832 of this web, so remove it from the live set of all basic blocks
833 in the live range of the web.
834 Blocks at the boundary of the live range may contain other live
835 ranges for the same target register, so we have to be careful
836 to remove the target register from the live set of these blocks
837 only if they do not contain other live ranges for the same register. */
839 clear_btr_from_live_range (btr_def def
)
844 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
846 if ((!def
->other_btr_uses_before_def
847 && !def
->other_btr_uses_after_use
)
848 || !block_at_edge_of_live_range_p (bb
, def
))
850 CLEAR_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
851 CLEAR_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
857 CLEAR_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
861 /* We are adding the def/use web DEF. Add the target register used
862 in this web to the live set of all of the basic blocks that contain
863 the live range of the web.
864 If OWN_END is set, also show that the register is live from our
865 definitions at the end of the basic block where it is defined. */
867 add_btr_to_live_range (btr_def def
, int own_end
)
872 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
874 SET_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
875 SET_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
881 SET_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
886 /* Update a live range to contain the basic block NEW_BLOCK, and all
887 blocks on paths between the existing live range and NEW_BLOCK.
888 HEAD is a block contained in the existing live range that dominates
889 all other blocks in the existing live range.
890 Also add to the set BTRS_LIVE_IN_RANGE all target registers that
891 are live in the blocks that we add to the live range.
892 If FULL_RANGE is set, include the full live range of NEW_BB;
893 otherwise, if NEW_BB dominates HEAD_BB, only add registers that
894 are life at the end of NEW_BB for NEW_BB itself.
895 It is a precondition that either NEW_BLOCK dominates HEAD,or
896 HEAD dom NEW_BLOCK. This is used to speed up the
897 implementation of this function. */
899 augment_live_range (bitmap live_range
, HARD_REG_SET
*btrs_live_in_range
,
900 basic_block head_bb
, basic_block new_bb
, int full_range
)
902 basic_block
*worklist
, *tos
;
904 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks
+ 1);
906 if (dominated_by_p (CDI_DOMINATORS
, new_bb
, head_bb
))
908 if (new_bb
== head_bb
)
911 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_bb
->index
]);
921 int new_block
= new_bb
->index
;
923 gcc_assert (dominated_by_p (CDI_DOMINATORS
, head_bb
, new_bb
));
925 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[head_bb
->index
]);
926 bitmap_set_bit (live_range
, new_block
);
927 /* A previous btr migration could have caused a register to be
928 live just at the end of new_block which we need in full, so
929 use trs_live_at_end even if full_range is set. */
930 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live_at_end
[new_block
]);
932 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_block
]);
936 "Adding end of block %d and rest of %d to live range\n",
937 new_block
, head_bb
->index
);
938 fprintf (dump_file
,"Now live btrs are ");
939 dump_hard_reg_set (*btrs_live_in_range
);
940 fprintf (dump_file
, "\n");
942 FOR_EACH_EDGE (e
, ei
, head_bb
->preds
)
946 while (tos
!= worklist
)
948 basic_block bb
= *--tos
;
949 if (!bitmap_bit_p (live_range
, bb
->index
))
954 bitmap_set_bit (live_range
, bb
->index
);
955 IOR_HARD_REG_SET (*btrs_live_in_range
,
956 btrs_live
[bb
->index
]);
957 /* A previous btr migration could have caused a register to be
958 live just at the end of a block which we need in full. */
959 IOR_HARD_REG_SET (*btrs_live_in_range
,
960 btrs_live_at_end
[bb
->index
]);
964 "Adding block %d to live range\n", bb
->index
);
965 fprintf (dump_file
,"Now live btrs are ");
966 dump_hard_reg_set (*btrs_live_in_range
);
967 fprintf (dump_file
, "\n");
970 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
972 basic_block pred
= e
->src
;
973 if (!bitmap_bit_p (live_range
, pred
->index
))
982 /* Return the most desirable target register that is not in
983 the set USED_BTRS. */
985 choose_btr (HARD_REG_SET used_btrs
)
989 if (!hard_reg_set_subset_p (all_btrs
, used_btrs
))
990 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
992 #ifdef REG_ALLOC_ORDER
993 int regno
= reg_alloc_order
[i
];
997 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
998 && !TEST_HARD_REG_BIT (used_btrs
, regno
))
1004 /* Calculate the set of basic blocks that contain the live range of
1005 the def/use web DEF.
1006 Also calculate the set of target registers that are live at time
1007 in this live range, but ignore the live range represented by DEF
1008 when calculating this set. */
1010 btr_def_live_range (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1012 if (!def
->live_range
)
1016 def
->live_range
= BITMAP_ALLOC (NULL
);
1018 bitmap_set_bit (def
->live_range
, def
->bb
->index
);
1019 COPY_HARD_REG_SET (*btrs_live_in_range
,
1020 (flag_btr_bb_exclusive
1021 ? btrs_live
: btrs_live_at_end
)[def
->bb
->index
]);
1023 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1024 augment_live_range (def
->live_range
, btrs_live_in_range
,
1026 (flag_btr_bb_exclusive
1027 || user
->insn
!= BB_END (def
->bb
)
1028 || !JUMP_P (user
->insn
)));
1032 /* def->live_range is accurate, but we need to recompute
1033 the set of target registers live over it, because migration
1034 of other PT instructions may have affected it.
1037 unsigned def_bb
= flag_btr_bb_exclusive
? -1 : def
->bb
->index
;
1040 CLEAR_HARD_REG_SET (*btrs_live_in_range
);
1041 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
1043 IOR_HARD_REG_SET (*btrs_live_in_range
,
1045 ? btrs_live_at_end
: btrs_live
) [bb
]);
1048 if (!def
->other_btr_uses_before_def
&&
1049 !def
->other_btr_uses_after_use
)
1050 CLEAR_HARD_REG_BIT (*btrs_live_in_range
, def
->btr
);
1053 /* Merge into the def/use web DEF any other def/use webs in the same
1054 group that are dominated by DEF, provided that there is a target
1055 register available to allocate to the merged web. */
1057 combine_btr_defs (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1061 for (other_def
= def
->group
->members
;
1063 other_def
= other_def
->next_this_group
)
1065 if (other_def
!= def
1066 && other_def
->uses
!= NULL
1067 && ! other_def
->has_ambiguous_use
1068 && dominated_by_p (CDI_DOMINATORS
, other_def
->bb
, def
->bb
))
1070 /* def->bb dominates the other def, so def and other_def could
1072 /* Merge their live ranges, and get the set of
1073 target registers live over the merged range. */
1075 HARD_REG_SET combined_btrs_live
;
1076 bitmap combined_live_range
= BITMAP_ALLOC (NULL
);
1079 if (other_def
->live_range
== NULL
)
1081 HARD_REG_SET dummy_btrs_live_in_range
;
1082 btr_def_live_range (other_def
, &dummy_btrs_live_in_range
);
1084 COPY_HARD_REG_SET (combined_btrs_live
, *btrs_live_in_range
);
1085 bitmap_copy (combined_live_range
, def
->live_range
);
1087 for (user
= other_def
->uses
; user
!= NULL
; user
= user
->next
)
1088 augment_live_range (combined_live_range
, &combined_btrs_live
,
1090 (flag_btr_bb_exclusive
1091 || user
->insn
!= BB_END (def
->bb
)
1092 || !JUMP_P (user
->insn
)));
1094 btr
= choose_btr (combined_btrs_live
);
1097 /* We can combine them. */
1100 "Combining def in insn %d with def in insn %d\n",
1101 INSN_UID (other_def
->insn
), INSN_UID (def
->insn
));
1104 user
= other_def
->uses
;
1105 while (user
!= NULL
)
1107 btr_user next
= user
->next
;
1109 user
->next
= def
->uses
;
1113 /* Combining def/use webs can make target registers live
1114 after uses where they previously were not. This means
1115 some REG_DEAD notes may no longer be correct. We could
1116 be more precise about this if we looked at the combined
1117 live range, but here I just delete any REG_DEAD notes
1118 in case they are no longer correct. */
1119 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1120 remove_note (user
->insn
,
1121 find_regno_note (user
->insn
, REG_DEAD
,
1122 REGNO (user
->use
)));
1123 clear_btr_from_live_range (other_def
);
1124 other_def
->uses
= NULL
;
1125 bitmap_copy (def
->live_range
, combined_live_range
);
1126 if (other_def
->btr
== btr
&& other_def
->other_btr_uses_after_use
)
1127 def
->other_btr_uses_after_use
= 1;
1128 COPY_HARD_REG_SET (*btrs_live_in_range
, combined_btrs_live
);
1130 /* Delete the old target register initialization. */
1131 delete_insn (other_def
->insn
);
1134 BITMAP_FREE (combined_live_range
);
1139 /* Move the definition DEF from its current position to basic
1140 block NEW_DEF_BB, and modify it to use branch target register BTR.
1141 Delete the old defining insn, and insert a new one in NEW_DEF_BB.
1142 Update all reaching uses of DEF in the RTL to use BTR.
1143 If this new position means that other defs in the
1144 same group can be combined with DEF then combine them. */
1146 move_btr_def (basic_block new_def_bb
, int btr
, btr_def def
, bitmap live_range
,
1147 HARD_REG_SET
*btrs_live_in_range
)
1149 /* We can move the instruction.
1150 Set a target register in block NEW_DEF_BB to the value
1151 needed for this target register definition.
1152 Replace all uses of the old target register definition by
1153 uses of the new definition. Delete the old definition. */
1154 basic_block b
= new_def_bb
;
1155 rtx insp
= BB_HEAD (b
);
1156 rtx old_insn
= def
->insn
;
1160 enum machine_mode btr_mode
;
1165 fprintf(dump_file
, "migrating to basic block %d, using reg %d\n",
1166 new_def_bb
->index
, btr
);
1168 clear_btr_from_live_range (def
);
1170 def
->bb
= new_def_bb
;
1172 def
->cost
= basic_block_freq (new_def_bb
);
1173 bitmap_copy (def
->live_range
, live_range
);
1174 combine_btr_defs (def
, btrs_live_in_range
);
1176 def
->other_btr_uses_before_def
1177 = TEST_HARD_REG_BIT (btrs_live
[b
->index
], btr
) ? 1 : 0;
1178 add_btr_to_live_range (def
, 1);
1180 insp
= NEXT_INSN (insp
);
1181 /* N.B.: insp is expected to be NOTE_INSN_BASIC_BLOCK now. Some
1182 optimizations can result in insp being both first and last insn of
1184 /* ?? some assertions to check that insp is sensible? */
1186 if (def
->other_btr_uses_before_def
)
1189 for (insp
= BB_END (b
); ! INSN_P (insp
); insp
= PREV_INSN (insp
))
1190 gcc_assert (insp
!= BB_HEAD (b
));
1192 if (JUMP_P (insp
) || can_throw_internal (insp
))
1193 insp
= PREV_INSN (insp
);
1196 set
= single_set (old_insn
);
1197 src
= SET_SRC (set
);
1198 btr_mode
= GET_MODE (SET_DEST (set
));
1199 btr_rtx
= gen_rtx_REG (btr_mode
, btr
);
1201 new_insn
= gen_move_insn (btr_rtx
, src
);
1203 /* Insert target register initialization at head of basic block. */
1204 def
->insn
= emit_insn_after (new_insn
, insp
);
1206 df_set_regs_ever_live (btr
, true);
1209 fprintf (dump_file
, "New pt is insn %d, inserted after insn %d\n",
1210 INSN_UID (def
->insn
), INSN_UID (insp
));
1212 /* Delete the old target register initialization. */
1213 delete_insn (old_insn
);
1215 /* Replace each use of the old target register by a use of the new target
1217 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1219 /* Some extra work here to ensure consistent modes, because
1220 it seems that a target register REG rtx can be given a different
1221 mode depending on the context (surely that should not be
1223 rtx replacement_rtx
;
1224 if (GET_MODE (user
->use
) == GET_MODE (btr_rtx
)
1225 || GET_MODE (user
->use
) == VOIDmode
)
1226 replacement_rtx
= btr_rtx
;
1228 replacement_rtx
= gen_rtx_REG (GET_MODE (user
->use
), btr
);
1229 validate_replace_rtx (user
->use
, replacement_rtx
, user
->insn
);
1230 user
->use
= replacement_rtx
;
1234 /* We anticipate intra-block scheduling to be done. See if INSN could move
1235 up within BB by N_INSNS. */
1237 can_move_up (const_basic_block bb
, const_rtx insn
, int n_insns
)
1239 while (insn
!= BB_HEAD (bb
) && n_insns
> 0)
1241 insn
= PREV_INSN (insn
);
1242 /* ??? What if we have an anti-dependency that actually prevents the
1243 scheduler from doing the move? We'd like to re-allocate the register,
1244 but not necessarily put the load into another basic block. */
1248 return n_insns
<= 0;
1251 /* Attempt to migrate the target register definition DEF to an
1252 earlier point in the flowgraph.
1254 It is a precondition of this function that DEF is migratable:
1255 i.e. it has a constant source, and all uses are unambiguous.
1257 Only migrations that reduce the cost of DEF will be made.
1258 MIN_COST is the lower bound on the cost of the DEF after migration.
1259 If we migrate DEF so that its cost falls below MIN_COST,
1260 then we do not attempt to migrate further. The idea is that
1261 we migrate definitions in a priority order based on their cost,
1262 when the cost of this definition falls below MIN_COST, then
1263 there is another definition with cost == MIN_COST which now
1264 has a higher priority than this definition.
1266 Return nonzero if there may be benefit from attempting to
1267 migrate this DEF further (i.e. we have reduced the cost below
1268 MIN_COST, but we may be able to reduce it further).
1269 Return zero if no further migration is possible. */
1271 migrate_btr_def (btr_def def
, int min_cost
)
1274 HARD_REG_SET btrs_live_in_range
;
1275 int btr_used_near_def
= 0;
1276 int def_basic_block_freq
;
1277 basic_block attempt
;
1285 "Attempting to migrate pt from insn %d (cost = %d, min_cost = %d) ... ",
1286 INSN_UID (def
->insn
), def
->cost
, min_cost
);
1288 if (!def
->group
|| def
->has_ambiguous_use
)
1289 /* These defs are not migratable. */
1292 fprintf (dump_file
, "it's not migratable\n");
1297 /* We have combined this def with another in the same group, so
1298 no need to consider it further.
1302 fprintf (dump_file
, "it's already combined with another pt\n");
1306 btr_def_live_range (def
, &btrs_live_in_range
);
1307 live_range
= BITMAP_ALLOC (NULL
);
1308 bitmap_copy (live_range
, def
->live_range
);
1310 #ifdef INSN_SCHEDULING
1311 def_latency
= insn_default_latency (def
->insn
) * issue_rate
;
1313 def_latency
= issue_rate
;
1316 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1318 if (user
->bb
== def
->bb
1319 && user
->luid
> def
->luid
1320 && (def
->luid
+ def_latency
) > user
->luid
1321 && ! can_move_up (def
->bb
, def
->insn
,
1322 (def
->luid
+ def_latency
) - user
->luid
))
1324 btr_used_near_def
= 1;
1329 def_basic_block_freq
= basic_block_freq (def
->bb
);
1331 for (attempt
= get_immediate_dominator (CDI_DOMINATORS
, def
->bb
);
1332 !give_up
&& attempt
&& attempt
!= ENTRY_BLOCK_PTR
&& def
->cost
>= min_cost
;
1333 attempt
= get_immediate_dominator (CDI_DOMINATORS
, attempt
))
1335 /* Try to move the instruction that sets the target register into
1336 basic block ATTEMPT. */
1337 int try_freq
= basic_block_freq (attempt
);
1341 /* If ATTEMPT has abnormal edges, skip it. */
1342 FOR_EACH_EDGE (e
, ei
, attempt
->succs
)
1343 if (e
->flags
& EDGE_COMPLEX
)
1349 fprintf (dump_file
, "trying block %d ...", attempt
->index
);
1351 if (try_freq
< def_basic_block_freq
1352 || (try_freq
== def_basic_block_freq
&& btr_used_near_def
))
1355 augment_live_range (live_range
, &btrs_live_in_range
, def
->bb
, attempt
,
1356 flag_btr_bb_exclusive
);
1359 fprintf (dump_file
, "Now btrs live in range are: ");
1360 dump_hard_reg_set (btrs_live_in_range
);
1361 fprintf (dump_file
, "\n");
1363 btr
= choose_btr (btrs_live_in_range
);
1366 move_btr_def (attempt
, btr
, def
, live_range
, &btrs_live_in_range
);
1367 bitmap_copy(live_range
, def
->live_range
);
1368 btr_used_near_def
= 0;
1370 def_basic_block_freq
= basic_block_freq (def
->bb
);
1374 /* There are no free target registers available to move
1375 this far forward, so give up */
1379 "giving up because there are no free target registers\n");
1388 fprintf (dump_file
, "failed to move\n");
1390 BITMAP_FREE (live_range
);
1394 /* Attempt to move instructions that set target registers earlier
1395 in the flowgraph, away from their corresponding uses. */
1397 migrate_btr_defs (enum reg_class btr_class
, int allow_callee_save
)
1399 fibheap_t all_btr_defs
= fibheap_new ();
1402 gcc_obstack_init (&migrate_btrl_obstack
);
1407 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
1409 basic_block bb
= BASIC_BLOCK (i
);
1411 "Basic block %d: count = " HOST_WIDEST_INT_PRINT_DEC
1412 " loop-depth = %d idom = %d\n",
1413 i
, (HOST_WIDEST_INT
) bb
->count
, bb_loop_depth (bb
),
1414 get_immediate_dominator (CDI_DOMINATORS
, bb
)->index
);
1418 CLEAR_HARD_REG_SET (all_btrs
);
1419 for (first_btr
= -1, reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
1420 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) btr_class
], reg
)
1421 && (allow_callee_save
|| call_used_regs
[reg
]
1422 || df_regs_ever_live_p (reg
)))
1424 SET_HARD_REG_BIT (all_btrs
, reg
);
1430 btrs_live
= XCNEWVEC (HARD_REG_SET
, last_basic_block
);
1431 btrs_live_at_end
= XCNEWVEC (HARD_REG_SET
, last_basic_block
);
1433 build_btr_def_use_webs (all_btr_defs
);
1435 while (!fibheap_empty (all_btr_defs
))
1437 btr_def def
= (btr_def
) fibheap_extract_min (all_btr_defs
);
1438 int min_cost
= -fibheap_min_key (all_btr_defs
);
1439 if (migrate_btr_def (def
, min_cost
))
1441 fibheap_insert (all_btr_defs
, -def
->cost
, (void *) def
);
1445 "Putting insn %d back on queue with priority %d\n",
1446 INSN_UID (def
->insn
), def
->cost
);
1450 BITMAP_FREE (def
->live_range
);
1454 free (btrs_live_at_end
);
1455 obstack_free (&migrate_btrl_obstack
, NULL
);
1456 fibheap_delete (all_btr_defs
);
1460 branch_target_load_optimize (bool after_prologue_epilogue_gen
)
1462 enum reg_class klass
1463 = (enum reg_class
) targetm
.branch_target_register_class ();
1464 if (klass
!= NO_REGS
)
1466 /* Initialize issue_rate. */
1467 if (targetm
.sched
.issue_rate
)
1468 issue_rate
= targetm
.sched
.issue_rate ();
1472 if (!after_prologue_epilogue_gen
)
1474 /* Build the CFG for migrate_btr_defs. */
1476 /* This may or may not be needed, depending on where we
1478 cleanup_cfg (optimize
? CLEANUP_EXPENSIVE
: 0);
1484 /* Dominator info is also needed for migrate_btr_def. */
1485 calculate_dominance_info (CDI_DOMINATORS
);
1486 migrate_btr_defs (klass
,
1487 (targetm
.branch_target_register_callee_saved
1488 (after_prologue_epilogue_gen
)));
1490 free_dominance_info (CDI_DOMINATORS
);
1495 gate_handle_branch_target_load_optimize1 (void)
1497 return flag_branch_target_load_optimize
;
1502 rest_of_handle_branch_target_load_optimize1 (void)
1504 branch_target_load_optimize (epilogue_completed
);
1508 struct rtl_opt_pass pass_branch_target_load_optimize1
=
1513 OPTGROUP_NONE
, /* optinfo_flags */
1514 gate_handle_branch_target_load_optimize1
, /* gate */
1515 rest_of_handle_branch_target_load_optimize1
, /* execute */
1518 0, /* static_pass_number */
1519 TV_NONE
, /* tv_id */
1520 0, /* properties_required */
1521 0, /* properties_provided */
1522 0, /* properties_destroyed */
1523 0, /* todo_flags_start */
1524 TODO_verify_rtl_sharing
|
1525 TODO_ggc_collect
, /* todo_flags_finish */
1530 gate_handle_branch_target_load_optimize2 (void)
1532 return (optimize
> 0 && flag_branch_target_load_optimize2
);
1537 rest_of_handle_branch_target_load_optimize2 (void)
1539 static int warned
= 0;
1541 /* Leave this a warning for now so that it is possible to experiment
1542 with running this pass twice. In 3.6, we should either make this
1543 an error, or use separate dump files. */
1544 if (flag_branch_target_load_optimize
1545 && flag_branch_target_load_optimize2
1548 warning (0, "branch target register load optimization is not intended "
1554 branch_target_load_optimize (epilogue_completed
);
1558 struct rtl_opt_pass pass_branch_target_load_optimize2
=
1563 OPTGROUP_NONE
, /* optinfo_flags */
1564 gate_handle_branch_target_load_optimize2
, /* gate */
1565 rest_of_handle_branch_target_load_optimize2
, /* execute */
1568 0, /* static_pass_number */
1569 TV_NONE
, /* tv_id */
1570 0, /* properties_required */
1571 0, /* properties_provided */
1572 0, /* properties_destroyed */
1573 0, /* todo_flags_start */
1574 TODO_ggc_collect
, /* todo_flags_finish */