2 /* Perform branch target register load optimizations.
3 Copyright (C) 2001-2015 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
26 #include "hard-reg-set.h"
31 #include "insn-attr.h"
40 #include "diagnostic-core.h"
41 #include "tree-pass.h"
43 #include "dominance.h"
47 #include "cfgcleanup.h"
49 #include "basic-block.h"
53 #include "fibonacci_heap.h"
55 /* Target register optimizations - these are performed after reload. */
57 typedef struct btr_def_group_s
59 struct btr_def_group_s
*next
;
61 struct btr_def_s
*members
;
64 typedef struct btr_user_s
66 struct btr_user_s
*next
;
70 /* If INSN has a single use of a single branch register, then
71 USE points to it within INSN. If there is more than
72 one branch register use, or the use is in some way ambiguous,
76 int first_reaching_def
;
77 char other_use_this_block
;
80 /* btr_def structs appear on three lists:
81 1. A list of all btr_def structures (head is
82 ALL_BTR_DEFS, linked by the NEXT field).
83 2. A list of branch reg definitions per basic block (head is
84 BB_BTR_DEFS[i], linked by the NEXT_THIS_BB field).
85 3. A list of all branch reg definitions belonging to the same
86 group (head is in a BTR_DEF_GROUP struct, linked by
87 NEXT_THIS_GROUP field). */
89 typedef struct btr_def_s
91 struct btr_def_s
*next_this_bb
;
92 struct btr_def_s
*next_this_group
;
98 /* For a branch register setting insn that has a constant
99 source (i.e. a label), group links together all the
100 insns with the same source. For other branch register
101 setting insns, group is NULL. */
104 /* If this def has a reaching use which is not a simple use
105 in a branch instruction, then has_ambiguous_use will be true,
106 and we will not attempt to migrate this definition. */
107 char has_ambiguous_use
;
108 /* live_range is an approximation to the true live range for this
109 def/use web, because it records the set of blocks that contain
110 the live range. There could be other live ranges for the same
111 branch register in that set of blocks, either in the block
112 containing the def (before the def), or in a block containing
113 a use (after the use). If there are such other live ranges, then
114 other_btr_uses_before_def or other_btr_uses_after_use must be set true
116 char other_btr_uses_before_def
;
117 char other_btr_uses_after_use
;
118 /* We set own_end when we have moved a definition into a dominator.
119 Thus, when a later combination removes this definition again, we know
120 to clear out trs_live_at_end again. */
125 typedef fibonacci_heap
<long, btr_def_s
> btr_heap_t
;
126 typedef fibonacci_node
<long, btr_def_s
> btr_heap_node_t
;
128 static int issue_rate
;
130 static int basic_block_freq (const_basic_block
);
131 static int insn_sets_btr_p (const rtx_insn
*, int, int *);
132 static void find_btr_def_group (btr_def_group
*, btr_def
);
133 static btr_def
add_btr_def (btr_heap_t
*, basic_block
, int, rtx_insn
*,
134 unsigned int, int, btr_def_group
*);
135 static btr_user
new_btr_user (basic_block
, int, rtx_insn
*);
136 static void dump_hard_reg_set (HARD_REG_SET
);
137 static void dump_btrs_live (int);
138 static void note_other_use_this_block (unsigned int, btr_user
);
139 static void compute_defs_uses_and_gen (btr_heap_t
*, btr_def
*,btr_user
*,
140 sbitmap
*, sbitmap
*, HARD_REG_SET
*);
141 static void compute_kill (sbitmap
*, sbitmap
*, HARD_REG_SET
*);
142 static void compute_out (sbitmap
*bb_out
, sbitmap
*, sbitmap
*, int);
143 static void link_btr_uses (btr_def
*, btr_user
*, sbitmap
*, sbitmap
*, int);
144 static void build_btr_def_use_webs (btr_heap_t
*);
145 static int block_at_edge_of_live_range_p (int, btr_def
);
146 static void clear_btr_from_live_range (btr_def def
);
147 static void add_btr_to_live_range (btr_def
, int);
148 static void augment_live_range (bitmap
, HARD_REG_SET
*, basic_block
,
150 static int choose_btr (HARD_REG_SET
);
151 static void combine_btr_defs (btr_def
, HARD_REG_SET
*);
152 static void btr_def_live_range (btr_def
, HARD_REG_SET
*);
153 static void move_btr_def (basic_block
, int, btr_def
, bitmap
, HARD_REG_SET
*);
154 static int migrate_btr_def (btr_def
, int);
155 static void migrate_btr_defs (enum reg_class
, int);
156 static int can_move_up (const_basic_block
, const rtx_insn
*, int);
157 static void note_btr_set (rtx
, const_rtx
, void *);
159 /* The following code performs code motion of target load instructions
160 (instructions that set branch target registers), to move them
161 forward away from the branch instructions and out of loops (or,
162 more generally, from a more frequently executed place to a less
163 frequently executed place).
164 Moving target load instructions further in front of the branch
165 instruction that uses the target register value means that the hardware
166 has a better chance of preloading the instructions at the branch
167 target by the time the branch is reached. This avoids bubbles
168 when a taken branch needs to flush out the pipeline.
169 Moving target load instructions out of loops means they are executed
172 /* An obstack to hold the def-use web data structures built up for
173 migrating branch target load instructions. */
174 static struct obstack migrate_btrl_obstack
;
176 /* Array indexed by basic block number, giving the set of registers
177 live in that block. */
178 static HARD_REG_SET
*btrs_live
;
180 /* Array indexed by basic block number, giving the set of registers live at
181 the end of that block, including any uses by a final jump insn, if any. */
182 static HARD_REG_SET
*btrs_live_at_end
;
184 /* Set of all target registers that we are willing to allocate. */
185 static HARD_REG_SET all_btrs
;
187 /* Provide lower and upper bounds for target register numbers, so that
188 we don't need to search through all the hard registers all the time. */
189 static int first_btr
, last_btr
;
193 /* Return an estimate of the frequency of execution of block bb. */
195 basic_block_freq (const_basic_block bb
)
197 return bb
->frequency
;
200 /* If X references (sets or reads) any branch target register, return one
201 such register. If EXCLUDEP is set, disregard any references within
204 find_btr_use (rtx x
, rtx
*excludep
= 0)
206 subrtx_ptr_iterator::array_type array
;
207 FOR_EACH_SUBRTX_PTR (iter
, array
, &x
, NONCONST
)
211 iter
.skip_subrtxes ();
216 && overlaps_hard_reg_set_p (all_btrs
, GET_MODE (x
), REGNO (x
)))
223 /* Return true if insn is an instruction that sets a target register.
224 if CHECK_CONST is true, only return true if the source is constant.
225 If such a set is found and REGNO is nonzero, assign the register number
226 of the destination register to *REGNO. */
228 insn_sets_btr_p (const rtx_insn
*insn
, int check_const
, int *regno
)
232 if (NONJUMP_INSN_P (insn
)
233 && (set
= single_set (insn
)))
235 rtx dest
= SET_DEST (set
);
236 rtx src
= SET_SRC (set
);
238 if (GET_CODE (dest
) == SUBREG
)
239 dest
= XEXP (dest
, 0);
242 && TEST_HARD_REG_BIT (all_btrs
, REGNO (dest
)))
244 gcc_assert (!find_btr_use (src
));
246 if (!check_const
|| CONSTANT_P (src
))
249 *regno
= REGNO (dest
);
257 /* Find the group that the target register definition DEF belongs
258 to in the list starting with *ALL_BTR_DEF_GROUPS. If no such
259 group exists, create one. Add def to the group. */
261 find_btr_def_group (btr_def_group
*all_btr_def_groups
, btr_def def
)
263 if (insn_sets_btr_p (def
->insn
, 1, NULL
))
265 btr_def_group this_group
;
266 rtx def_src
= SET_SRC (single_set (def
->insn
));
268 /* ?? This linear search is an efficiency concern, particularly
269 as the search will almost always fail to find a match. */
270 for (this_group
= *all_btr_def_groups
;
272 this_group
= this_group
->next
)
273 if (rtx_equal_p (def_src
, this_group
->src
))
278 this_group
= XOBNEW (&migrate_btrl_obstack
, struct btr_def_group_s
);
279 this_group
->src
= def_src
;
280 this_group
->members
= NULL
;
281 this_group
->next
= *all_btr_def_groups
;
282 *all_btr_def_groups
= this_group
;
284 def
->group
= this_group
;
285 def
->next_this_group
= this_group
->members
;
286 this_group
->members
= def
;
292 /* Create a new target register definition structure, for a definition in
293 block BB, instruction INSN, and insert it into ALL_BTR_DEFS. Return
294 the new definition. */
296 add_btr_def (btr_heap_t
*all_btr_defs
, basic_block bb
, int insn_luid
,
298 unsigned int dest_reg
, int other_btr_uses_before_def
,
299 btr_def_group
*all_btr_def_groups
)
301 btr_def this_def
= XOBNEW (&migrate_btrl_obstack
, struct btr_def_s
);
303 this_def
->luid
= insn_luid
;
304 this_def
->insn
= insn
;
305 this_def
->btr
= dest_reg
;
306 this_def
->cost
= basic_block_freq (bb
);
307 this_def
->has_ambiguous_use
= 0;
308 this_def
->other_btr_uses_before_def
= other_btr_uses_before_def
;
309 this_def
->other_btr_uses_after_use
= 0;
310 this_def
->next_this_bb
= NULL
;
311 this_def
->next_this_group
= NULL
;
312 this_def
->uses
= NULL
;
313 this_def
->live_range
= NULL
;
314 find_btr_def_group (all_btr_def_groups
, this_def
);
316 all_btr_defs
->insert (-this_def
->cost
, this_def
);
320 "Found target reg definition: sets %u { bb %d, insn %d }%s priority %d\n",
321 dest_reg
, bb
->index
, INSN_UID (insn
),
322 (this_def
->group
? "" : ":not const"), this_def
->cost
);
327 /* Create a new target register user structure, for a use in block BB,
328 instruction INSN. Return the new user. */
330 new_btr_user (basic_block bb
, int insn_luid
, rtx_insn
*insn
)
332 /* This instruction reads target registers. We need
333 to decide whether we can replace all target register
336 rtx
*usep
= find_btr_use (PATTERN (insn
));
338 btr_user user
= NULL
;
342 int unambiguous_single_use
;
344 /* We want to ensure that USE is the only use of a target
345 register in INSN, so that we know that to rewrite INSN to use
346 a different target register, all we have to do is replace USE. */
347 unambiguous_single_use
= !find_btr_use (PATTERN (insn
), usep
);
348 if (!unambiguous_single_use
)
351 use
= usep
? *usep
: NULL_RTX
;
352 user
= XOBNEW (&migrate_btrl_obstack
, struct btr_user_s
);
354 user
->luid
= insn_luid
;
357 user
->other_use_this_block
= 0;
359 user
->n_reaching_defs
= 0;
360 user
->first_reaching_def
= -1;
364 fprintf (dump_file
, "Uses target reg: { bb %d, insn %d }",
365 bb
->index
, INSN_UID (insn
));
368 fprintf (dump_file
, ": unambiguous use of reg %d\n",
375 /* Write the contents of S to the dump file. */
377 dump_hard_reg_set (HARD_REG_SET s
)
380 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
381 if (TEST_HARD_REG_BIT (s
, reg
))
382 fprintf (dump_file
, " %d", reg
);
385 /* Write the set of target regs live in block BB to the dump file. */
387 dump_btrs_live (int bb
)
389 fprintf (dump_file
, "BB%d live:", bb
);
390 dump_hard_reg_set (btrs_live
[bb
]);
391 fprintf (dump_file
, "\n");
394 /* REGNO is the number of a branch target register that is being used or
395 set. USERS_THIS_BB is a list of preceding branch target register users;
396 If any of them use the same register, set their other_use_this_block
399 note_other_use_this_block (unsigned int regno
, btr_user users_this_bb
)
403 for (user
= users_this_bb
; user
!= NULL
; user
= user
->next
)
404 if (user
->use
&& REGNO (user
->use
) == regno
)
405 user
->other_use_this_block
= 1;
409 btr_user users_this_bb
;
410 HARD_REG_SET btrs_written_in_block
;
411 HARD_REG_SET btrs_live_in_block
;
416 /* Called via note_stores or directly to register stores into /
417 clobbers of a branch target register DEST that are not recognized as
418 straightforward definitions. DATA points to information about the
419 current basic block that needs updating. */
421 note_btr_set (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
, void *data
)
423 defs_uses_info
*info
= (defs_uses_info
*) data
;
424 int regno
, end_regno
;
428 regno
= REGNO (dest
);
429 end_regno
= END_HARD_REGNO (dest
);
430 for (; regno
< end_regno
; regno
++)
431 if (TEST_HARD_REG_BIT (all_btrs
, regno
))
433 note_other_use_this_block (regno
, info
->users_this_bb
);
434 SET_HARD_REG_BIT (info
->btrs_written_in_block
, regno
);
435 SET_HARD_REG_BIT (info
->btrs_live_in_block
, regno
);
436 bitmap_and_compl (info
->bb_gen
, info
->bb_gen
,
437 info
->btr_defset
[regno
- first_btr
]);
442 compute_defs_uses_and_gen (btr_heap_t
*all_btr_defs
, btr_def
*def_array
,
443 btr_user
*use_array
, sbitmap
*btr_defset
,
444 sbitmap
*bb_gen
, HARD_REG_SET
*btrs_written
)
446 /* Scan the code building up the set of all defs and all uses.
447 For each target register, build the set of defs of that register.
448 For each block, calculate the set of target registers
449 written in that block.
450 Also calculate the set of btrs ever live in that block.
454 btr_def_group all_btr_def_groups
= NULL
;
457 bitmap_vector_clear (bb_gen
, last_basic_block_for_fn (cfun
));
458 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
460 basic_block bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
462 btr_def defs_this_bb
= NULL
;
467 info
.users_this_bb
= NULL
;
468 info
.bb_gen
= bb_gen
[i
];
469 info
.btr_defset
= btr_defset
;
471 CLEAR_HARD_REG_SET (info
.btrs_live_in_block
);
472 CLEAR_HARD_REG_SET (info
.btrs_written_in_block
);
473 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
474 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
475 && REGNO_REG_SET_P (df_get_live_in (bb
), reg
))
476 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
478 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
480 insn
= NEXT_INSN (insn
), insn_luid
++)
485 int insn_uid
= INSN_UID (insn
);
487 if (insn_sets_btr_p (insn
, 0, ®no
))
489 btr_def def
= add_btr_def (
490 all_btr_defs
, bb
, insn_luid
, insn
, regno
,
491 TEST_HARD_REG_BIT (info
.btrs_live_in_block
, regno
),
492 &all_btr_def_groups
);
494 def_array
[insn_uid
] = def
;
495 SET_HARD_REG_BIT (info
.btrs_written_in_block
, regno
);
496 SET_HARD_REG_BIT (info
.btrs_live_in_block
, regno
);
497 bitmap_and_compl (bb_gen
[i
], bb_gen
[i
],
498 btr_defset
[regno
- first_btr
]);
499 bitmap_set_bit (bb_gen
[i
], insn_uid
);
500 def
->next_this_bb
= defs_this_bb
;
502 bitmap_set_bit (btr_defset
[regno
- first_btr
], insn_uid
);
503 note_other_use_this_block (regno
, info
.users_this_bb
);
505 /* Check for the blockage emitted by expand_nl_goto_receiver. */
506 else if (cfun
->has_nonlocal_label
507 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
)
511 /* Do the equivalent of calling note_other_use_this_block
512 for every target register. */
513 for (user
= info
.users_this_bb
; user
!= NULL
;
516 user
->other_use_this_block
= 1;
517 IOR_HARD_REG_SET (info
.btrs_written_in_block
, all_btrs
);
518 IOR_HARD_REG_SET (info
.btrs_live_in_block
, all_btrs
);
519 bitmap_clear (info
.bb_gen
);
523 if (find_btr_use (PATTERN (insn
)))
525 btr_user user
= new_btr_user (bb
, insn_luid
, insn
);
527 use_array
[insn_uid
] = user
;
529 SET_HARD_REG_BIT (info
.btrs_live_in_block
,
534 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
535 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
536 && refers_to_regno_p (reg
, reg
+ 1, user
->insn
,
539 note_other_use_this_block (reg
,
541 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
543 note_stores (PATTERN (insn
), note_btr_set
, &info
);
545 user
->next
= info
.users_this_bb
;
546 info
.users_this_bb
= user
;
550 HARD_REG_SET
*clobbered
= &call_used_reg_set
;
551 HARD_REG_SET call_saved
;
552 rtx pat
= PATTERN (insn
);
555 /* Check for sibcall. */
556 if (GET_CODE (pat
) == PARALLEL
)
557 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
558 if (ANY_RETURN_P (XVECEXP (pat
, 0, i
)))
560 COMPL_HARD_REG_SET (call_saved
,
562 clobbered
= &call_saved
;
565 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
566 if (TEST_HARD_REG_BIT (*clobbered
, regno
))
567 note_btr_set (regno_reg_rtx
[regno
], NULL_RTX
, &info
);
573 COPY_HARD_REG_SET (btrs_live
[i
], info
.btrs_live_in_block
);
574 COPY_HARD_REG_SET (btrs_written
[i
], info
.btrs_written_in_block
);
576 REG_SET_TO_HARD_REG_SET (btrs_live_at_end
[i
], df_get_live_out (bb
));
577 /* If this block ends in a jump insn, add any uses or even clobbers
578 of branch target registers that it might have. */
579 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
) && ! INSN_P (insn
); )
580 insn
= PREV_INSN (insn
);
581 /* ??? for the fall-through edge, it would make sense to insert the
582 btr set on the edge, but that would require to split the block
583 early on so that we can distinguish between dominance from the fall
584 through edge - which can use the call-clobbered registers - from
585 dominance by the throw edge. */
586 if (can_throw_internal (insn
))
590 COPY_HARD_REG_SET (tmp
, call_used_reg_set
);
591 AND_HARD_REG_SET (tmp
, all_btrs
);
592 IOR_HARD_REG_SET (btrs_live_at_end
[i
], tmp
);
595 if (can_throw
|| JUMP_P (insn
))
599 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
600 if (refers_to_regno_p (regno
, regno
+1, insn
, NULL
))
601 SET_HARD_REG_BIT (btrs_live_at_end
[i
], regno
);
610 compute_kill (sbitmap
*bb_kill
, sbitmap
*btr_defset
,
611 HARD_REG_SET
*btrs_written
)
616 /* For each basic block, form the set BB_KILL - the set
617 of definitions that the block kills. */
618 bitmap_vector_clear (bb_kill
, last_basic_block_for_fn (cfun
));
619 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
621 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
622 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
623 && TEST_HARD_REG_BIT (btrs_written
[i
], regno
))
624 bitmap_ior (bb_kill
[i
], bb_kill
[i
],
625 btr_defset
[regno
- first_btr
]);
630 compute_out (sbitmap
*bb_out
, sbitmap
*bb_gen
, sbitmap
*bb_kill
, int max_uid
)
632 /* Perform iterative dataflow:
633 Initially, for all blocks, BB_OUT = BB_GEN.
635 BB_IN = union over predecessors of BB_OUT(pred)
636 BB_OUT = (BB_IN - BB_KILL) + BB_GEN
637 Iterate until the bb_out sets stop growing. */
640 sbitmap bb_in
= sbitmap_alloc (max_uid
);
642 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
643 bitmap_copy (bb_out
[i
], bb_gen
[i
]);
649 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
651 bitmap_union_of_preds (bb_in
, bb_out
, BASIC_BLOCK_FOR_FN (cfun
, i
));
652 changed
|= bitmap_ior_and_compl (bb_out
[i
], bb_gen
[i
],
656 sbitmap_free (bb_in
);
660 link_btr_uses (btr_def
*def_array
, btr_user
*use_array
, sbitmap
*bb_out
,
661 sbitmap
*btr_defset
, int max_uid
)
664 sbitmap reaching_defs
= sbitmap_alloc (max_uid
);
666 /* Link uses to the uses lists of all of their reaching defs.
667 Count up the number of reaching defs of each use. */
668 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
670 basic_block bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
674 bitmap_union_of_preds (reaching_defs
, bb_out
, BASIC_BLOCK_FOR_FN (cfun
, i
));
675 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
677 insn
= NEXT_INSN (insn
))
681 int insn_uid
= INSN_UID (insn
);
683 btr_def def
= def_array
[insn_uid
];
684 btr_user user
= use_array
[insn_uid
];
687 /* Remove all reaching defs of regno except
689 bitmap_and_compl (reaching_defs
, reaching_defs
,
690 btr_defset
[def
->btr
- first_btr
]);
691 bitmap_set_bit (reaching_defs
, insn_uid
);
696 /* Find all the reaching defs for this use. */
697 sbitmap reaching_defs_of_reg
= sbitmap_alloc (max_uid
);
698 unsigned int uid
= 0;
699 sbitmap_iterator sbi
;
703 reaching_defs_of_reg
,
705 btr_defset
[REGNO (user
->use
) - first_btr
]);
710 bitmap_clear (reaching_defs_of_reg
);
711 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
712 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
713 && refers_to_regno_p (reg
, reg
+ 1, user
->insn
,
715 bitmap_or_and (reaching_defs_of_reg
,
716 reaching_defs_of_reg
,
718 btr_defset
[reg
- first_btr
]);
720 EXECUTE_IF_SET_IN_BITMAP (reaching_defs_of_reg
, 0, uid
, sbi
)
722 btr_def def
= def_array
[uid
];
724 /* We now know that def reaches user. */
728 "Def in insn %d reaches use in insn %d\n",
731 user
->n_reaching_defs
++;
733 def
->has_ambiguous_use
= 1;
734 if (user
->first_reaching_def
!= -1)
735 { /* There is more than one reaching def. This is
736 a rare case, so just give up on this def/use
737 web when it occurs. */
738 def
->has_ambiguous_use
= 1;
739 def_array
[user
->first_reaching_def
]
740 ->has_ambiguous_use
= 1;
743 "(use %d has multiple reaching defs)\n",
747 user
->first_reaching_def
= uid
;
748 if (user
->other_use_this_block
)
749 def
->other_btr_uses_after_use
= 1;
750 user
->next
= def
->uses
;
753 sbitmap_free (reaching_defs_of_reg
);
760 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
761 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
762 && TEST_HARD_REG_BIT (call_used_reg_set
, regno
))
763 bitmap_and_compl (reaching_defs
, reaching_defs
,
764 btr_defset
[regno
- first_btr
]);
769 sbitmap_free (reaching_defs
);
773 build_btr_def_use_webs (btr_heap_t
*all_btr_defs
)
775 const int max_uid
= get_max_uid ();
776 btr_def
*def_array
= XCNEWVEC (btr_def
, max_uid
);
777 btr_user
*use_array
= XCNEWVEC (btr_user
, max_uid
);
778 sbitmap
*btr_defset
= sbitmap_vector_alloc (
779 (last_btr
- first_btr
) + 1, max_uid
);
780 sbitmap
*bb_gen
= sbitmap_vector_alloc (last_basic_block_for_fn (cfun
),
782 HARD_REG_SET
*btrs_written
= XCNEWVEC (HARD_REG_SET
,
783 last_basic_block_for_fn (cfun
));
787 bitmap_vector_clear (btr_defset
, (last_btr
- first_btr
) + 1);
789 compute_defs_uses_and_gen (all_btr_defs
, def_array
, use_array
, btr_defset
,
790 bb_gen
, btrs_written
);
792 bb_kill
= sbitmap_vector_alloc (last_basic_block_for_fn (cfun
), max_uid
);
793 compute_kill (bb_kill
, btr_defset
, btrs_written
);
796 bb_out
= sbitmap_vector_alloc (last_basic_block_for_fn (cfun
), max_uid
);
797 compute_out (bb_out
, bb_gen
, bb_kill
, max_uid
);
799 sbitmap_vector_free (bb_gen
);
800 sbitmap_vector_free (bb_kill
);
802 link_btr_uses (def_array
, use_array
, bb_out
, btr_defset
, max_uid
);
804 sbitmap_vector_free (bb_out
);
805 sbitmap_vector_free (btr_defset
);
810 /* Return true if basic block BB contains the start or end of the
811 live range of the definition DEF, AND there are other live
812 ranges of the same target register that include BB. */
814 block_at_edge_of_live_range_p (int bb
, btr_def def
)
816 if (def
->other_btr_uses_before_def
817 && BASIC_BLOCK_FOR_FN (cfun
, bb
) == def
->bb
)
819 else if (def
->other_btr_uses_after_use
)
822 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
823 if (BASIC_BLOCK_FOR_FN (cfun
, bb
) == user
->bb
)
829 /* We are removing the def/use web DEF. The target register
830 used in this web is therefore no longer live in the live range
831 of this web, so remove it from the live set of all basic blocks
832 in the live range of the web.
833 Blocks at the boundary of the live range may contain other live
834 ranges for the same target register, so we have to be careful
835 to remove the target register from the live set of these blocks
836 only if they do not contain other live ranges for the same register. */
838 clear_btr_from_live_range (btr_def def
)
843 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
845 if ((!def
->other_btr_uses_before_def
846 && !def
->other_btr_uses_after_use
)
847 || !block_at_edge_of_live_range_p (bb
, def
))
849 CLEAR_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
850 CLEAR_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
856 CLEAR_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
860 /* We are adding the def/use web DEF. Add the target register used
861 in this web to the live set of all of the basic blocks that contain
862 the live range of the web.
863 If OWN_END is set, also show that the register is live from our
864 definitions at the end of the basic block where it is defined. */
866 add_btr_to_live_range (btr_def def
, int own_end
)
871 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
873 SET_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
874 SET_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
880 SET_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
885 /* Update a live range to contain the basic block NEW_BLOCK, and all
886 blocks on paths between the existing live range and NEW_BLOCK.
887 HEAD is a block contained in the existing live range that dominates
888 all other blocks in the existing live range.
889 Also add to the set BTRS_LIVE_IN_RANGE all target registers that
890 are live in the blocks that we add to the live range.
891 If FULL_RANGE is set, include the full live range of NEW_BB;
892 otherwise, if NEW_BB dominates HEAD_BB, only add registers that
893 are life at the end of NEW_BB for NEW_BB itself.
894 It is a precondition that either NEW_BLOCK dominates HEAD,or
895 HEAD dom NEW_BLOCK. This is used to speed up the
896 implementation of this function. */
898 augment_live_range (bitmap live_range
, HARD_REG_SET
*btrs_live_in_range
,
899 basic_block head_bb
, basic_block new_bb
, int full_range
)
901 basic_block
*worklist
, *tos
;
903 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
905 if (dominated_by_p (CDI_DOMINATORS
, new_bb
, head_bb
))
907 if (new_bb
== head_bb
)
910 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_bb
->index
]);
920 int new_block
= new_bb
->index
;
922 gcc_assert (dominated_by_p (CDI_DOMINATORS
, head_bb
, new_bb
));
924 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[head_bb
->index
]);
925 bitmap_set_bit (live_range
, new_block
);
926 /* A previous btr migration could have caused a register to be
927 live just at the end of new_block which we need in full, so
928 use trs_live_at_end even if full_range is set. */
929 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live_at_end
[new_block
]);
931 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_block
]);
935 "Adding end of block %d and rest of %d to live range\n",
936 new_block
, head_bb
->index
);
937 fprintf (dump_file
,"Now live btrs are ");
938 dump_hard_reg_set (*btrs_live_in_range
);
939 fprintf (dump_file
, "\n");
941 FOR_EACH_EDGE (e
, ei
, head_bb
->preds
)
945 while (tos
!= worklist
)
947 basic_block bb
= *--tos
;
948 if (!bitmap_bit_p (live_range
, bb
->index
))
953 bitmap_set_bit (live_range
, bb
->index
);
954 IOR_HARD_REG_SET (*btrs_live_in_range
,
955 btrs_live
[bb
->index
]);
956 /* A previous btr migration could have caused a register to be
957 live just at the end of a block which we need in full. */
958 IOR_HARD_REG_SET (*btrs_live_in_range
,
959 btrs_live_at_end
[bb
->index
]);
963 "Adding block %d to live range\n", bb
->index
);
964 fprintf (dump_file
,"Now live btrs are ");
965 dump_hard_reg_set (*btrs_live_in_range
);
966 fprintf (dump_file
, "\n");
969 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
971 basic_block pred
= e
->src
;
972 if (!bitmap_bit_p (live_range
, pred
->index
))
981 /* Return the most desirable target register that is not in
982 the set USED_BTRS. */
984 choose_btr (HARD_REG_SET used_btrs
)
988 if (!hard_reg_set_subset_p (all_btrs
, used_btrs
))
989 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
991 #ifdef REG_ALLOC_ORDER
992 int regno
= reg_alloc_order
[i
];
996 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
997 && !TEST_HARD_REG_BIT (used_btrs
, regno
))
1003 /* Calculate the set of basic blocks that contain the live range of
1004 the def/use web DEF.
1005 Also calculate the set of target registers that are live at time
1006 in this live range, but ignore the live range represented by DEF
1007 when calculating this set. */
1009 btr_def_live_range (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1011 if (!def
->live_range
)
1015 def
->live_range
= BITMAP_ALLOC (NULL
);
1017 bitmap_set_bit (def
->live_range
, def
->bb
->index
);
1018 COPY_HARD_REG_SET (*btrs_live_in_range
,
1019 (flag_btr_bb_exclusive
1020 ? btrs_live
: btrs_live_at_end
)[def
->bb
->index
]);
1022 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1023 augment_live_range (def
->live_range
, btrs_live_in_range
,
1025 (flag_btr_bb_exclusive
1026 || user
->insn
!= BB_END (def
->bb
)
1027 || !JUMP_P (user
->insn
)));
1031 /* def->live_range is accurate, but we need to recompute
1032 the set of target registers live over it, because migration
1033 of other PT instructions may have affected it.
1036 unsigned def_bb
= flag_btr_bb_exclusive
? -1 : def
->bb
->index
;
1039 CLEAR_HARD_REG_SET (*btrs_live_in_range
);
1040 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
1042 IOR_HARD_REG_SET (*btrs_live_in_range
,
1044 ? btrs_live_at_end
: btrs_live
) [bb
]);
1047 if (!def
->other_btr_uses_before_def
&&
1048 !def
->other_btr_uses_after_use
)
1049 CLEAR_HARD_REG_BIT (*btrs_live_in_range
, def
->btr
);
1052 /* Merge into the def/use web DEF any other def/use webs in the same
1053 group that are dominated by DEF, provided that there is a target
1054 register available to allocate to the merged web. */
1056 combine_btr_defs (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1060 for (other_def
= def
->group
->members
;
1062 other_def
= other_def
->next_this_group
)
1064 if (other_def
!= def
1065 && other_def
->uses
!= NULL
1066 && ! other_def
->has_ambiguous_use
1067 && dominated_by_p (CDI_DOMINATORS
, other_def
->bb
, def
->bb
))
1069 /* def->bb dominates the other def, so def and other_def could
1071 /* Merge their live ranges, and get the set of
1072 target registers live over the merged range. */
1074 HARD_REG_SET combined_btrs_live
;
1075 bitmap combined_live_range
= BITMAP_ALLOC (NULL
);
1078 if (other_def
->live_range
== NULL
)
1080 HARD_REG_SET dummy_btrs_live_in_range
;
1081 btr_def_live_range (other_def
, &dummy_btrs_live_in_range
);
1083 COPY_HARD_REG_SET (combined_btrs_live
, *btrs_live_in_range
);
1084 bitmap_copy (combined_live_range
, def
->live_range
);
1086 for (user
= other_def
->uses
; user
!= NULL
; user
= user
->next
)
1087 augment_live_range (combined_live_range
, &combined_btrs_live
,
1089 (flag_btr_bb_exclusive
1090 || user
->insn
!= BB_END (def
->bb
)
1091 || !JUMP_P (user
->insn
)));
1093 btr
= choose_btr (combined_btrs_live
);
1096 /* We can combine them. */
1099 "Combining def in insn %d with def in insn %d\n",
1100 INSN_UID (other_def
->insn
), INSN_UID (def
->insn
));
1103 user
= other_def
->uses
;
1104 while (user
!= NULL
)
1106 btr_user next
= user
->next
;
1108 user
->next
= def
->uses
;
1112 /* Combining def/use webs can make target registers live
1113 after uses where they previously were not. This means
1114 some REG_DEAD notes may no longer be correct. We could
1115 be more precise about this if we looked at the combined
1116 live range, but here I just delete any REG_DEAD notes
1117 in case they are no longer correct. */
1118 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1119 remove_note (user
->insn
,
1120 find_regno_note (user
->insn
, REG_DEAD
,
1121 REGNO (user
->use
)));
1122 clear_btr_from_live_range (other_def
);
1123 other_def
->uses
= NULL
;
1124 bitmap_copy (def
->live_range
, combined_live_range
);
1125 if (other_def
->btr
== btr
&& other_def
->other_btr_uses_after_use
)
1126 def
->other_btr_uses_after_use
= 1;
1127 COPY_HARD_REG_SET (*btrs_live_in_range
, combined_btrs_live
);
1129 /* Delete the old target register initialization. */
1130 delete_insn (other_def
->insn
);
1133 BITMAP_FREE (combined_live_range
);
1138 /* Move the definition DEF from its current position to basic
1139 block NEW_DEF_BB, and modify it to use branch target register BTR.
1140 Delete the old defining insn, and insert a new one in NEW_DEF_BB.
1141 Update all reaching uses of DEF in the RTL to use BTR.
1142 If this new position means that other defs in the
1143 same group can be combined with DEF then combine them. */
1145 move_btr_def (basic_block new_def_bb
, int btr
, btr_def def
, bitmap live_range
,
1146 HARD_REG_SET
*btrs_live_in_range
)
1148 /* We can move the instruction.
1149 Set a target register in block NEW_DEF_BB to the value
1150 needed for this target register definition.
1151 Replace all uses of the old target register definition by
1152 uses of the new definition. Delete the old definition. */
1153 basic_block b
= new_def_bb
;
1154 rtx_insn
*insp
= BB_HEAD (b
);
1155 rtx_insn
*old_insn
= def
->insn
;
1159 machine_mode btr_mode
;
1164 fprintf(dump_file
, "migrating to basic block %d, using reg %d\n",
1165 new_def_bb
->index
, btr
);
1167 clear_btr_from_live_range (def
);
1169 def
->bb
= new_def_bb
;
1171 def
->cost
= basic_block_freq (new_def_bb
);
1172 bitmap_copy (def
->live_range
, live_range
);
1173 combine_btr_defs (def
, btrs_live_in_range
);
1175 def
->other_btr_uses_before_def
1176 = TEST_HARD_REG_BIT (btrs_live
[b
->index
], btr
) ? 1 : 0;
1177 add_btr_to_live_range (def
, 1);
1179 insp
= NEXT_INSN (insp
);
1180 /* N.B.: insp is expected to be NOTE_INSN_BASIC_BLOCK now. Some
1181 optimizations can result in insp being both first and last insn of
1183 /* ?? some assertions to check that insp is sensible? */
1185 if (def
->other_btr_uses_before_def
)
1188 for (insp
= BB_END (b
); ! INSN_P (insp
); insp
= PREV_INSN (insp
))
1189 gcc_assert (insp
!= BB_HEAD (b
));
1191 if (JUMP_P (insp
) || can_throw_internal (insp
))
1192 insp
= PREV_INSN (insp
);
1195 set
= single_set (old_insn
);
1196 src
= SET_SRC (set
);
1197 btr_mode
= GET_MODE (SET_DEST (set
));
1198 btr_rtx
= gen_rtx_REG (btr_mode
, btr
);
1200 new_insn
= as_a
<rtx_insn
*> (gen_move_insn (btr_rtx
, src
));
1202 /* Insert target register initialization at head of basic block. */
1203 def
->insn
= emit_insn_after (new_insn
, insp
);
1205 df_set_regs_ever_live (btr
, true);
1208 fprintf (dump_file
, "New pt is insn %d, inserted after insn %d\n",
1209 INSN_UID (def
->insn
), INSN_UID (insp
));
1211 /* Delete the old target register initialization. */
1212 delete_insn (old_insn
);
1214 /* Replace each use of the old target register by a use of the new target
1216 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1218 /* Some extra work here to ensure consistent modes, because
1219 it seems that a target register REG rtx can be given a different
1220 mode depending on the context (surely that should not be
1222 rtx replacement_rtx
;
1223 if (GET_MODE (user
->use
) == GET_MODE (btr_rtx
)
1224 || GET_MODE (user
->use
) == VOIDmode
)
1225 replacement_rtx
= btr_rtx
;
1227 replacement_rtx
= gen_rtx_REG (GET_MODE (user
->use
), btr
);
1228 validate_replace_rtx (user
->use
, replacement_rtx
, user
->insn
);
1229 user
->use
= replacement_rtx
;
1233 /* We anticipate intra-block scheduling to be done. See if INSN could move
1234 up within BB by N_INSNS. */
1236 can_move_up (const_basic_block bb
, const rtx_insn
*insn
, int n_insns
)
1238 while (insn
!= BB_HEAD (bb
) && n_insns
> 0)
1240 insn
= PREV_INSN (insn
);
1241 /* ??? What if we have an anti-dependency that actually prevents the
1242 scheduler from doing the move? We'd like to re-allocate the register,
1243 but not necessarily put the load into another basic block. */
1247 return n_insns
<= 0;
1250 /* Attempt to migrate the target register definition DEF to an
1251 earlier point in the flowgraph.
1253 It is a precondition of this function that DEF is migratable:
1254 i.e. it has a constant source, and all uses are unambiguous.
1256 Only migrations that reduce the cost of DEF will be made.
1257 MIN_COST is the lower bound on the cost of the DEF after migration.
1258 If we migrate DEF so that its cost falls below MIN_COST,
1259 then we do not attempt to migrate further. The idea is that
1260 we migrate definitions in a priority order based on their cost,
1261 when the cost of this definition falls below MIN_COST, then
1262 there is another definition with cost == MIN_COST which now
1263 has a higher priority than this definition.
1265 Return nonzero if there may be benefit from attempting to
1266 migrate this DEF further (i.e. we have reduced the cost below
1267 MIN_COST, but we may be able to reduce it further).
1268 Return zero if no further migration is possible. */
1270 migrate_btr_def (btr_def def
, int min_cost
)
1273 HARD_REG_SET btrs_live_in_range
;
1274 int btr_used_near_def
= 0;
1275 int def_basic_block_freq
;
1276 basic_block attempt
;
1284 "Attempting to migrate pt from insn %d (cost = %d, min_cost = %d) ... ",
1285 INSN_UID (def
->insn
), def
->cost
, min_cost
);
1287 if (!def
->group
|| def
->has_ambiguous_use
)
1288 /* These defs are not migratable. */
1291 fprintf (dump_file
, "it's not migratable\n");
1296 /* We have combined this def with another in the same group, so
1297 no need to consider it further.
1301 fprintf (dump_file
, "it's already combined with another pt\n");
1305 btr_def_live_range (def
, &btrs_live_in_range
);
1306 live_range
= BITMAP_ALLOC (NULL
);
1307 bitmap_copy (live_range
, def
->live_range
);
1309 #ifdef INSN_SCHEDULING
1310 def_latency
= insn_default_latency (def
->insn
) * issue_rate
;
1312 def_latency
= issue_rate
;
1315 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1317 if (user
->bb
== def
->bb
1318 && user
->luid
> def
->luid
1319 && (def
->luid
+ def_latency
) > user
->luid
1320 && ! can_move_up (def
->bb
, def
->insn
,
1321 (def
->luid
+ def_latency
) - user
->luid
))
1323 btr_used_near_def
= 1;
1328 def_basic_block_freq
= basic_block_freq (def
->bb
);
1330 for (attempt
= get_immediate_dominator (CDI_DOMINATORS
, def
->bb
);
1331 !give_up
&& attempt
&& attempt
!= ENTRY_BLOCK_PTR_FOR_FN (cfun
)
1332 && def
->cost
>= min_cost
;
1333 attempt
= get_immediate_dominator (CDI_DOMINATORS
, attempt
))
1335 /* Try to move the instruction that sets the target register into
1336 basic block ATTEMPT. */
1337 int try_freq
= basic_block_freq (attempt
);
1341 /* If ATTEMPT has abnormal edges, skip it. */
1342 FOR_EACH_EDGE (e
, ei
, attempt
->succs
)
1343 if (e
->flags
& EDGE_COMPLEX
)
1349 fprintf (dump_file
, "trying block %d ...", attempt
->index
);
1351 if (try_freq
< def_basic_block_freq
1352 || (try_freq
== def_basic_block_freq
&& btr_used_near_def
))
1355 augment_live_range (live_range
, &btrs_live_in_range
, def
->bb
, attempt
,
1356 flag_btr_bb_exclusive
);
1359 fprintf (dump_file
, "Now btrs live in range are: ");
1360 dump_hard_reg_set (btrs_live_in_range
);
1361 fprintf (dump_file
, "\n");
1363 btr
= choose_btr (btrs_live_in_range
);
1366 move_btr_def (attempt
, btr
, def
, live_range
, &btrs_live_in_range
);
1367 bitmap_copy (live_range
, def
->live_range
);
1368 btr_used_near_def
= 0;
1370 def_basic_block_freq
= basic_block_freq (def
->bb
);
1374 /* There are no free target registers available to move
1375 this far forward, so give up */
1379 "giving up because there are no free target registers\n");
1388 fprintf (dump_file
, "failed to move\n");
1390 BITMAP_FREE (live_range
);
1394 /* Attempt to move instructions that set target registers earlier
1395 in the flowgraph, away from their corresponding uses. */
1397 migrate_btr_defs (enum reg_class btr_class
, int allow_callee_save
)
1399 btr_heap_t
all_btr_defs (LONG_MIN
);
1402 gcc_obstack_init (&migrate_btrl_obstack
);
1407 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
1409 basic_block bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
1411 "Basic block %d: count = %" PRId64
1412 " loop-depth = %d idom = %d\n",
1413 i
, (int64_t) bb
->count
, bb_loop_depth (bb
),
1414 get_immediate_dominator (CDI_DOMINATORS
, bb
)->index
);
1418 CLEAR_HARD_REG_SET (all_btrs
);
1419 for (first_btr
= -1, reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
1420 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) btr_class
], reg
)
1421 && (allow_callee_save
|| call_used_regs
[reg
]
1422 || df_regs_ever_live_p (reg
)))
1424 SET_HARD_REG_BIT (all_btrs
, reg
);
1430 btrs_live
= XCNEWVEC (HARD_REG_SET
, last_basic_block_for_fn (cfun
));
1431 btrs_live_at_end
= XCNEWVEC (HARD_REG_SET
, last_basic_block_for_fn (cfun
));
1433 build_btr_def_use_webs (&all_btr_defs
);
1435 while (!all_btr_defs
.empty ())
1437 int min_cost
= -all_btr_defs
.min_key ();
1438 btr_def def
= all_btr_defs
.extract_min ();
1439 if (migrate_btr_def (def
, min_cost
))
1441 all_btr_defs
.insert (-def
->cost
, def
);
1445 "Putting insn %d back on queue with priority %d\n",
1446 INSN_UID (def
->insn
), def
->cost
);
1450 BITMAP_FREE (def
->live_range
);
1454 free (btrs_live_at_end
);
1455 obstack_free (&migrate_btrl_obstack
, NULL
);
1459 branch_target_load_optimize (bool after_prologue_epilogue_gen
)
1461 enum reg_class klass
1462 = (enum reg_class
) targetm
.branch_target_register_class ();
1463 if (klass
!= NO_REGS
)
1465 /* Initialize issue_rate. */
1466 if (targetm
.sched
.issue_rate
)
1467 issue_rate
= targetm
.sched
.issue_rate ();
1471 if (!after_prologue_epilogue_gen
)
1473 /* Build the CFG for migrate_btr_defs. */
1475 /* This may or may not be needed, depending on where we
1477 cleanup_cfg (optimize
? CLEANUP_EXPENSIVE
: 0);
1483 /* Dominator info is also needed for migrate_btr_def. */
1484 calculate_dominance_info (CDI_DOMINATORS
);
1485 migrate_btr_defs (klass
,
1486 (targetm
.branch_target_register_callee_saved
1487 (after_prologue_epilogue_gen
)));
1489 free_dominance_info (CDI_DOMINATORS
);
1495 const pass_data pass_data_branch_target_load_optimize1
=
1497 RTL_PASS
, /* type */
1499 OPTGROUP_NONE
, /* optinfo_flags */
1500 TV_NONE
, /* tv_id */
1501 0, /* properties_required */
1502 0, /* properties_provided */
1503 0, /* properties_destroyed */
1504 0, /* todo_flags_start */
1505 0, /* todo_flags_finish */
1508 class pass_branch_target_load_optimize1
: public rtl_opt_pass
1511 pass_branch_target_load_optimize1 (gcc::context
*ctxt
)
1512 : rtl_opt_pass (pass_data_branch_target_load_optimize1
, ctxt
)
1515 /* opt_pass methods: */
1516 virtual bool gate (function
*) { return flag_branch_target_load_optimize
; }
1517 virtual unsigned int execute (function
*)
1519 branch_target_load_optimize (epilogue_completed
);
1523 }; // class pass_branch_target_load_optimize1
1528 make_pass_branch_target_load_optimize1 (gcc::context
*ctxt
)
1530 return new pass_branch_target_load_optimize1 (ctxt
);
1536 const pass_data pass_data_branch_target_load_optimize2
=
1538 RTL_PASS
, /* type */
1540 OPTGROUP_NONE
, /* optinfo_flags */
1541 TV_NONE
, /* tv_id */
1542 0, /* properties_required */
1543 0, /* properties_provided */
1544 0, /* properties_destroyed */
1545 0, /* todo_flags_start */
1546 0, /* todo_flags_finish */
1549 class pass_branch_target_load_optimize2
: public rtl_opt_pass
1552 pass_branch_target_load_optimize2 (gcc::context
*ctxt
)
1553 : rtl_opt_pass (pass_data_branch_target_load_optimize2
, ctxt
)
1556 /* opt_pass methods: */
1557 virtual bool gate (function
*)
1559 return (optimize
> 0 && flag_branch_target_load_optimize2
);
1562 virtual unsigned int execute (function
*);
1564 }; // class pass_branch_target_load_optimize2
1567 pass_branch_target_load_optimize2::execute (function
*)
1569 static int warned
= 0;
1571 /* Leave this a warning for now so that it is possible to experiment
1572 with running this pass twice. In 3.6, we should either make this
1573 an error, or use separate dump files. */
1574 if (flag_branch_target_load_optimize
1575 && flag_branch_target_load_optimize2
1578 warning (0, "branch target register load optimization is not intended "
1584 branch_target_load_optimize (epilogue_completed
);
1591 make_pass_branch_target_load_optimize2 (gcc::context
*ctxt
)
1593 return new pass_branch_target_load_optimize2 (ctxt
);