2 /* Perform branch target register load optimizations.
3 Copyright (C) 2001-2015 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
26 #include "hard-reg-set.h"
36 #include "statistics.h"
40 #include "insn-config.h"
49 #include "insn-attr.h"
52 #include "diagnostic-core.h"
53 #include "tree-pass.h"
55 #include "dominance.h"
59 #include "cfgcleanup.h"
61 #include "basic-block.h"
65 #include "fibonacci_heap.h"
67 /* Target register optimizations - these are performed after reload. */
69 typedef struct btr_def_group_s
71 struct btr_def_group_s
*next
;
73 struct btr_def_s
*members
;
76 typedef struct btr_user_s
78 struct btr_user_s
*next
;
82 /* If INSN has a single use of a single branch register, then
83 USE points to it within INSN. If there is more than
84 one branch register use, or the use is in some way ambiguous,
88 int first_reaching_def
;
89 char other_use_this_block
;
92 /* btr_def structs appear on three lists:
93 1. A list of all btr_def structures (head is
94 ALL_BTR_DEFS, linked by the NEXT field).
95 2. A list of branch reg definitions per basic block (head is
96 BB_BTR_DEFS[i], linked by the NEXT_THIS_BB field).
97 3. A list of all branch reg definitions belonging to the same
98 group (head is in a BTR_DEF_GROUP struct, linked by
99 NEXT_THIS_GROUP field). */
101 typedef struct btr_def_s
103 struct btr_def_s
*next_this_bb
;
104 struct btr_def_s
*next_this_group
;
110 /* For a branch register setting insn that has a constant
111 source (i.e. a label), group links together all the
112 insns with the same source. For other branch register
113 setting insns, group is NULL. */
116 /* If this def has a reaching use which is not a simple use
117 in a branch instruction, then has_ambiguous_use will be true,
118 and we will not attempt to migrate this definition. */
119 char has_ambiguous_use
;
120 /* live_range is an approximation to the true live range for this
121 def/use web, because it records the set of blocks that contain
122 the live range. There could be other live ranges for the same
123 branch register in that set of blocks, either in the block
124 containing the def (before the def), or in a block containing
125 a use (after the use). If there are such other live ranges, then
126 other_btr_uses_before_def or other_btr_uses_after_use must be set true
128 char other_btr_uses_before_def
;
129 char other_btr_uses_after_use
;
130 /* We set own_end when we have moved a definition into a dominator.
131 Thus, when a later combination removes this definition again, we know
132 to clear out trs_live_at_end again. */
137 typedef fibonacci_heap
<long, btr_def_s
> btr_heap_t
;
138 typedef fibonacci_node
<long, btr_def_s
> btr_heap_node_t
;
140 static int issue_rate
;
142 static int basic_block_freq (const_basic_block
);
143 static int insn_sets_btr_p (const rtx_insn
*, int, int *);
144 static void find_btr_def_group (btr_def_group
*, btr_def
);
145 static btr_def
add_btr_def (btr_heap_t
*, basic_block
, int, rtx_insn
*,
146 unsigned int, int, btr_def_group
*);
147 static btr_user
new_btr_user (basic_block
, int, rtx_insn
*);
148 static void dump_hard_reg_set (HARD_REG_SET
);
149 static void dump_btrs_live (int);
150 static void note_other_use_this_block (unsigned int, btr_user
);
151 static void compute_defs_uses_and_gen (btr_heap_t
*, btr_def
*,btr_user
*,
152 sbitmap
*, sbitmap
*, HARD_REG_SET
*);
153 static void compute_kill (sbitmap
*, sbitmap
*, HARD_REG_SET
*);
154 static void compute_out (sbitmap
*bb_out
, sbitmap
*, sbitmap
*, int);
155 static void link_btr_uses (btr_def
*, btr_user
*, sbitmap
*, sbitmap
*, int);
156 static void build_btr_def_use_webs (btr_heap_t
*);
157 static int block_at_edge_of_live_range_p (int, btr_def
);
158 static void clear_btr_from_live_range (btr_def def
);
159 static void add_btr_to_live_range (btr_def
, int);
160 static void augment_live_range (bitmap
, HARD_REG_SET
*, basic_block
,
162 static int choose_btr (HARD_REG_SET
);
163 static void combine_btr_defs (btr_def
, HARD_REG_SET
*);
164 static void btr_def_live_range (btr_def
, HARD_REG_SET
*);
165 static void move_btr_def (basic_block
, int, btr_def
, bitmap
, HARD_REG_SET
*);
166 static int migrate_btr_def (btr_def
, int);
167 static void migrate_btr_defs (enum reg_class
, int);
168 static int can_move_up (const_basic_block
, const rtx_insn
*, int);
169 static void note_btr_set (rtx
, const_rtx
, void *);
171 /* The following code performs code motion of target load instructions
172 (instructions that set branch target registers), to move them
173 forward away from the branch instructions and out of loops (or,
174 more generally, from a more frequently executed place to a less
175 frequently executed place).
176 Moving target load instructions further in front of the branch
177 instruction that uses the target register value means that the hardware
178 has a better chance of preloading the instructions at the branch
179 target by the time the branch is reached. This avoids bubbles
180 when a taken branch needs to flush out the pipeline.
181 Moving target load instructions out of loops means they are executed
184 /* An obstack to hold the def-use web data structures built up for
185 migrating branch target load instructions. */
186 static struct obstack migrate_btrl_obstack
;
188 /* Array indexed by basic block number, giving the set of registers
189 live in that block. */
190 static HARD_REG_SET
*btrs_live
;
192 /* Array indexed by basic block number, giving the set of registers live at
193 the end of that block, including any uses by a final jump insn, if any. */
194 static HARD_REG_SET
*btrs_live_at_end
;
196 /* Set of all target registers that we are willing to allocate. */
197 static HARD_REG_SET all_btrs
;
199 /* Provide lower and upper bounds for target register numbers, so that
200 we don't need to search through all the hard registers all the time. */
201 static int first_btr
, last_btr
;
205 /* Return an estimate of the frequency of execution of block bb. */
207 basic_block_freq (const_basic_block bb
)
209 return bb
->frequency
;
212 /* If X references (sets or reads) any branch target register, return one
213 such register. If EXCLUDEP is set, disregard any references within
216 find_btr_use (rtx x
, rtx
*excludep
= 0)
218 subrtx_ptr_iterator::array_type array
;
219 FOR_EACH_SUBRTX_PTR (iter
, array
, &x
, NONCONST
)
223 iter
.skip_subrtxes ();
228 && overlaps_hard_reg_set_p (all_btrs
, GET_MODE (x
), REGNO (x
)))
235 /* Return true if insn is an instruction that sets a target register.
236 if CHECK_CONST is true, only return true if the source is constant.
237 If such a set is found and REGNO is nonzero, assign the register number
238 of the destination register to *REGNO. */
240 insn_sets_btr_p (const rtx_insn
*insn
, int check_const
, int *regno
)
244 if (NONJUMP_INSN_P (insn
)
245 && (set
= single_set (insn
)))
247 rtx dest
= SET_DEST (set
);
248 rtx src
= SET_SRC (set
);
250 if (GET_CODE (dest
) == SUBREG
)
251 dest
= XEXP (dest
, 0);
254 && TEST_HARD_REG_BIT (all_btrs
, REGNO (dest
)))
256 gcc_assert (!find_btr_use (src
));
258 if (!check_const
|| CONSTANT_P (src
))
261 *regno
= REGNO (dest
);
269 /* Find the group that the target register definition DEF belongs
270 to in the list starting with *ALL_BTR_DEF_GROUPS. If no such
271 group exists, create one. Add def to the group. */
273 find_btr_def_group (btr_def_group
*all_btr_def_groups
, btr_def def
)
275 if (insn_sets_btr_p (def
->insn
, 1, NULL
))
277 btr_def_group this_group
;
278 rtx def_src
= SET_SRC (single_set (def
->insn
));
280 /* ?? This linear search is an efficiency concern, particularly
281 as the search will almost always fail to find a match. */
282 for (this_group
= *all_btr_def_groups
;
284 this_group
= this_group
->next
)
285 if (rtx_equal_p (def_src
, this_group
->src
))
290 this_group
= XOBNEW (&migrate_btrl_obstack
, struct btr_def_group_s
);
291 this_group
->src
= def_src
;
292 this_group
->members
= NULL
;
293 this_group
->next
= *all_btr_def_groups
;
294 *all_btr_def_groups
= this_group
;
296 def
->group
= this_group
;
297 def
->next_this_group
= this_group
->members
;
298 this_group
->members
= def
;
304 /* Create a new target register definition structure, for a definition in
305 block BB, instruction INSN, and insert it into ALL_BTR_DEFS. Return
306 the new definition. */
308 add_btr_def (btr_heap_t
*all_btr_defs
, basic_block bb
, int insn_luid
,
310 unsigned int dest_reg
, int other_btr_uses_before_def
,
311 btr_def_group
*all_btr_def_groups
)
313 btr_def this_def
= XOBNEW (&migrate_btrl_obstack
, struct btr_def_s
);
315 this_def
->luid
= insn_luid
;
316 this_def
->insn
= insn
;
317 this_def
->btr
= dest_reg
;
318 this_def
->cost
= basic_block_freq (bb
);
319 this_def
->has_ambiguous_use
= 0;
320 this_def
->other_btr_uses_before_def
= other_btr_uses_before_def
;
321 this_def
->other_btr_uses_after_use
= 0;
322 this_def
->next_this_bb
= NULL
;
323 this_def
->next_this_group
= NULL
;
324 this_def
->uses
= NULL
;
325 this_def
->live_range
= NULL
;
326 find_btr_def_group (all_btr_def_groups
, this_def
);
328 all_btr_defs
->insert (-this_def
->cost
, this_def
);
332 "Found target reg definition: sets %u { bb %d, insn %d }%s priority %d\n",
333 dest_reg
, bb
->index
, INSN_UID (insn
),
334 (this_def
->group
? "" : ":not const"), this_def
->cost
);
339 /* Create a new target register user structure, for a use in block BB,
340 instruction INSN. Return the new user. */
342 new_btr_user (basic_block bb
, int insn_luid
, rtx_insn
*insn
)
344 /* This instruction reads target registers. We need
345 to decide whether we can replace all target register
348 rtx
*usep
= find_btr_use (PATTERN (insn
));
350 btr_user user
= NULL
;
354 int unambiguous_single_use
;
356 /* We want to ensure that USE is the only use of a target
357 register in INSN, so that we know that to rewrite INSN to use
358 a different target register, all we have to do is replace USE. */
359 unambiguous_single_use
= !find_btr_use (PATTERN (insn
), usep
);
360 if (!unambiguous_single_use
)
363 use
= usep
? *usep
: NULL_RTX
;
364 user
= XOBNEW (&migrate_btrl_obstack
, struct btr_user_s
);
366 user
->luid
= insn_luid
;
369 user
->other_use_this_block
= 0;
371 user
->n_reaching_defs
= 0;
372 user
->first_reaching_def
= -1;
376 fprintf (dump_file
, "Uses target reg: { bb %d, insn %d }",
377 bb
->index
, INSN_UID (insn
));
380 fprintf (dump_file
, ": unambiguous use of reg %d\n",
387 /* Write the contents of S to the dump file. */
389 dump_hard_reg_set (HARD_REG_SET s
)
392 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
393 if (TEST_HARD_REG_BIT (s
, reg
))
394 fprintf (dump_file
, " %d", reg
);
397 /* Write the set of target regs live in block BB to the dump file. */
399 dump_btrs_live (int bb
)
401 fprintf (dump_file
, "BB%d live:", bb
);
402 dump_hard_reg_set (btrs_live
[bb
]);
403 fprintf (dump_file
, "\n");
406 /* REGNO is the number of a branch target register that is being used or
407 set. USERS_THIS_BB is a list of preceding branch target register users;
408 If any of them use the same register, set their other_use_this_block
411 note_other_use_this_block (unsigned int regno
, btr_user users_this_bb
)
415 for (user
= users_this_bb
; user
!= NULL
; user
= user
->next
)
416 if (user
->use
&& REGNO (user
->use
) == regno
)
417 user
->other_use_this_block
= 1;
421 btr_user users_this_bb
;
422 HARD_REG_SET btrs_written_in_block
;
423 HARD_REG_SET btrs_live_in_block
;
428 /* Called via note_stores or directly to register stores into /
429 clobbers of a branch target register DEST that are not recognized as
430 straightforward definitions. DATA points to information about the
431 current basic block that needs updating. */
433 note_btr_set (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
, void *data
)
435 defs_uses_info
*info
= (defs_uses_info
*) data
;
436 int regno
, end_regno
;
440 regno
= REGNO (dest
);
441 end_regno
= END_REGNO (dest
);
442 for (; regno
< end_regno
; regno
++)
443 if (TEST_HARD_REG_BIT (all_btrs
, regno
))
445 note_other_use_this_block (regno
, info
->users_this_bb
);
446 SET_HARD_REG_BIT (info
->btrs_written_in_block
, regno
);
447 SET_HARD_REG_BIT (info
->btrs_live_in_block
, regno
);
448 bitmap_and_compl (info
->bb_gen
, info
->bb_gen
,
449 info
->btr_defset
[regno
- first_btr
]);
454 compute_defs_uses_and_gen (btr_heap_t
*all_btr_defs
, btr_def
*def_array
,
455 btr_user
*use_array
, sbitmap
*btr_defset
,
456 sbitmap
*bb_gen
, HARD_REG_SET
*btrs_written
)
458 /* Scan the code building up the set of all defs and all uses.
459 For each target register, build the set of defs of that register.
460 For each block, calculate the set of target registers
461 written in that block.
462 Also calculate the set of btrs ever live in that block.
466 btr_def_group all_btr_def_groups
= NULL
;
469 bitmap_vector_clear (bb_gen
, last_basic_block_for_fn (cfun
));
470 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
472 basic_block bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
474 btr_def defs_this_bb
= NULL
;
479 info
.users_this_bb
= NULL
;
480 info
.bb_gen
= bb_gen
[i
];
481 info
.btr_defset
= btr_defset
;
483 CLEAR_HARD_REG_SET (info
.btrs_live_in_block
);
484 CLEAR_HARD_REG_SET (info
.btrs_written_in_block
);
485 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
486 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
487 && REGNO_REG_SET_P (df_get_live_in (bb
), reg
))
488 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
490 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
492 insn
= NEXT_INSN (insn
), insn_luid
++)
497 int insn_uid
= INSN_UID (insn
);
499 if (insn_sets_btr_p (insn
, 0, ®no
))
501 btr_def def
= add_btr_def (
502 all_btr_defs
, bb
, insn_luid
, insn
, regno
,
503 TEST_HARD_REG_BIT (info
.btrs_live_in_block
, regno
),
504 &all_btr_def_groups
);
506 def_array
[insn_uid
] = def
;
507 SET_HARD_REG_BIT (info
.btrs_written_in_block
, regno
);
508 SET_HARD_REG_BIT (info
.btrs_live_in_block
, regno
);
509 bitmap_and_compl (bb_gen
[i
], bb_gen
[i
],
510 btr_defset
[regno
- first_btr
]);
511 bitmap_set_bit (bb_gen
[i
], insn_uid
);
512 def
->next_this_bb
= defs_this_bb
;
514 bitmap_set_bit (btr_defset
[regno
- first_btr
], insn_uid
);
515 note_other_use_this_block (regno
, info
.users_this_bb
);
517 /* Check for the blockage emitted by expand_nl_goto_receiver. */
518 else if (cfun
->has_nonlocal_label
519 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
)
523 /* Do the equivalent of calling note_other_use_this_block
524 for every target register. */
525 for (user
= info
.users_this_bb
; user
!= NULL
;
528 user
->other_use_this_block
= 1;
529 IOR_HARD_REG_SET (info
.btrs_written_in_block
, all_btrs
);
530 IOR_HARD_REG_SET (info
.btrs_live_in_block
, all_btrs
);
531 bitmap_clear (info
.bb_gen
);
535 if (find_btr_use (PATTERN (insn
)))
537 btr_user user
= new_btr_user (bb
, insn_luid
, insn
);
539 use_array
[insn_uid
] = user
;
541 SET_HARD_REG_BIT (info
.btrs_live_in_block
,
546 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
547 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
548 && refers_to_regno_p (reg
, user
->insn
))
550 note_other_use_this_block (reg
,
552 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
554 note_stores (PATTERN (insn
), note_btr_set
, &info
);
556 user
->next
= info
.users_this_bb
;
557 info
.users_this_bb
= user
;
561 HARD_REG_SET
*clobbered
= &call_used_reg_set
;
562 HARD_REG_SET call_saved
;
563 rtx pat
= PATTERN (insn
);
566 /* Check for sibcall. */
567 if (GET_CODE (pat
) == PARALLEL
)
568 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
569 if (ANY_RETURN_P (XVECEXP (pat
, 0, i
)))
571 COMPL_HARD_REG_SET (call_saved
,
573 clobbered
= &call_saved
;
576 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
577 if (TEST_HARD_REG_BIT (*clobbered
, regno
))
578 note_btr_set (regno_reg_rtx
[regno
], NULL_RTX
, &info
);
584 COPY_HARD_REG_SET (btrs_live
[i
], info
.btrs_live_in_block
);
585 COPY_HARD_REG_SET (btrs_written
[i
], info
.btrs_written_in_block
);
587 REG_SET_TO_HARD_REG_SET (btrs_live_at_end
[i
], df_get_live_out (bb
));
588 /* If this block ends in a jump insn, add any uses or even clobbers
589 of branch target registers that it might have. */
590 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
) && ! INSN_P (insn
); )
591 insn
= PREV_INSN (insn
);
592 /* ??? for the fall-through edge, it would make sense to insert the
593 btr set on the edge, but that would require to split the block
594 early on so that we can distinguish between dominance from the fall
595 through edge - which can use the call-clobbered registers - from
596 dominance by the throw edge. */
597 if (can_throw_internal (insn
))
601 COPY_HARD_REG_SET (tmp
, call_used_reg_set
);
602 AND_HARD_REG_SET (tmp
, all_btrs
);
603 IOR_HARD_REG_SET (btrs_live_at_end
[i
], tmp
);
606 if (can_throw
|| JUMP_P (insn
))
610 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
611 if (refers_to_regno_p (regno
, insn
))
612 SET_HARD_REG_BIT (btrs_live_at_end
[i
], regno
);
621 compute_kill (sbitmap
*bb_kill
, sbitmap
*btr_defset
,
622 HARD_REG_SET
*btrs_written
)
627 /* For each basic block, form the set BB_KILL - the set
628 of definitions that the block kills. */
629 bitmap_vector_clear (bb_kill
, last_basic_block_for_fn (cfun
));
630 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
632 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
633 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
634 && TEST_HARD_REG_BIT (btrs_written
[i
], regno
))
635 bitmap_ior (bb_kill
[i
], bb_kill
[i
],
636 btr_defset
[regno
- first_btr
]);
641 compute_out (sbitmap
*bb_out
, sbitmap
*bb_gen
, sbitmap
*bb_kill
, int max_uid
)
643 /* Perform iterative dataflow:
644 Initially, for all blocks, BB_OUT = BB_GEN.
646 BB_IN = union over predecessors of BB_OUT(pred)
647 BB_OUT = (BB_IN - BB_KILL) + BB_GEN
648 Iterate until the bb_out sets stop growing. */
651 sbitmap bb_in
= sbitmap_alloc (max_uid
);
653 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
654 bitmap_copy (bb_out
[i
], bb_gen
[i
]);
660 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
662 bitmap_union_of_preds (bb_in
, bb_out
, BASIC_BLOCK_FOR_FN (cfun
, i
));
663 changed
|= bitmap_ior_and_compl (bb_out
[i
], bb_gen
[i
],
667 sbitmap_free (bb_in
);
671 link_btr_uses (btr_def
*def_array
, btr_user
*use_array
, sbitmap
*bb_out
,
672 sbitmap
*btr_defset
, int max_uid
)
675 sbitmap reaching_defs
= sbitmap_alloc (max_uid
);
677 /* Link uses to the uses lists of all of their reaching defs.
678 Count up the number of reaching defs of each use. */
679 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
681 basic_block bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
685 bitmap_union_of_preds (reaching_defs
, bb_out
, BASIC_BLOCK_FOR_FN (cfun
, i
));
686 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
688 insn
= NEXT_INSN (insn
))
692 int insn_uid
= INSN_UID (insn
);
694 btr_def def
= def_array
[insn_uid
];
695 btr_user user
= use_array
[insn_uid
];
698 /* Remove all reaching defs of regno except
700 bitmap_and_compl (reaching_defs
, reaching_defs
,
701 btr_defset
[def
->btr
- first_btr
]);
702 bitmap_set_bit (reaching_defs
, insn_uid
);
707 /* Find all the reaching defs for this use. */
708 sbitmap reaching_defs_of_reg
= sbitmap_alloc (max_uid
);
709 unsigned int uid
= 0;
710 sbitmap_iterator sbi
;
714 reaching_defs_of_reg
,
716 btr_defset
[REGNO (user
->use
) - first_btr
]);
721 bitmap_clear (reaching_defs_of_reg
);
722 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
723 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
724 && refers_to_regno_p (reg
, user
->insn
))
725 bitmap_or_and (reaching_defs_of_reg
,
726 reaching_defs_of_reg
,
728 btr_defset
[reg
- first_btr
]);
730 EXECUTE_IF_SET_IN_BITMAP (reaching_defs_of_reg
, 0, uid
, sbi
)
732 btr_def def
= def_array
[uid
];
734 /* We now know that def reaches user. */
738 "Def in insn %d reaches use in insn %d\n",
741 user
->n_reaching_defs
++;
743 def
->has_ambiguous_use
= 1;
744 if (user
->first_reaching_def
!= -1)
745 { /* There is more than one reaching def. This is
746 a rare case, so just give up on this def/use
747 web when it occurs. */
748 def
->has_ambiguous_use
= 1;
749 def_array
[user
->first_reaching_def
]
750 ->has_ambiguous_use
= 1;
753 "(use %d has multiple reaching defs)\n",
757 user
->first_reaching_def
= uid
;
758 if (user
->other_use_this_block
)
759 def
->other_btr_uses_after_use
= 1;
760 user
->next
= def
->uses
;
763 sbitmap_free (reaching_defs_of_reg
);
770 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
771 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
772 && TEST_HARD_REG_BIT (call_used_reg_set
, regno
))
773 bitmap_and_compl (reaching_defs
, reaching_defs
,
774 btr_defset
[regno
- first_btr
]);
779 sbitmap_free (reaching_defs
);
783 build_btr_def_use_webs (btr_heap_t
*all_btr_defs
)
785 const int max_uid
= get_max_uid ();
786 btr_def
*def_array
= XCNEWVEC (btr_def
, max_uid
);
787 btr_user
*use_array
= XCNEWVEC (btr_user
, max_uid
);
788 sbitmap
*btr_defset
= sbitmap_vector_alloc (
789 (last_btr
- first_btr
) + 1, max_uid
);
790 sbitmap
*bb_gen
= sbitmap_vector_alloc (last_basic_block_for_fn (cfun
),
792 HARD_REG_SET
*btrs_written
= XCNEWVEC (HARD_REG_SET
,
793 last_basic_block_for_fn (cfun
));
797 bitmap_vector_clear (btr_defset
, (last_btr
- first_btr
) + 1);
799 compute_defs_uses_and_gen (all_btr_defs
, def_array
, use_array
, btr_defset
,
800 bb_gen
, btrs_written
);
802 bb_kill
= sbitmap_vector_alloc (last_basic_block_for_fn (cfun
), max_uid
);
803 compute_kill (bb_kill
, btr_defset
, btrs_written
);
806 bb_out
= sbitmap_vector_alloc (last_basic_block_for_fn (cfun
), max_uid
);
807 compute_out (bb_out
, bb_gen
, bb_kill
, max_uid
);
809 sbitmap_vector_free (bb_gen
);
810 sbitmap_vector_free (bb_kill
);
812 link_btr_uses (def_array
, use_array
, bb_out
, btr_defset
, max_uid
);
814 sbitmap_vector_free (bb_out
);
815 sbitmap_vector_free (btr_defset
);
820 /* Return true if basic block BB contains the start or end of the
821 live range of the definition DEF, AND there are other live
822 ranges of the same target register that include BB. */
824 block_at_edge_of_live_range_p (int bb
, btr_def def
)
826 if (def
->other_btr_uses_before_def
827 && BASIC_BLOCK_FOR_FN (cfun
, bb
) == def
->bb
)
829 else if (def
->other_btr_uses_after_use
)
832 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
833 if (BASIC_BLOCK_FOR_FN (cfun
, bb
) == user
->bb
)
839 /* We are removing the def/use web DEF. The target register
840 used in this web is therefore no longer live in the live range
841 of this web, so remove it from the live set of all basic blocks
842 in the live range of the web.
843 Blocks at the boundary of the live range may contain other live
844 ranges for the same target register, so we have to be careful
845 to remove the target register from the live set of these blocks
846 only if they do not contain other live ranges for the same register. */
848 clear_btr_from_live_range (btr_def def
)
853 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
855 if ((!def
->other_btr_uses_before_def
856 && !def
->other_btr_uses_after_use
)
857 || !block_at_edge_of_live_range_p (bb
, def
))
859 CLEAR_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
860 CLEAR_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
866 CLEAR_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
870 /* We are adding the def/use web DEF. Add the target register used
871 in this web to the live set of all of the basic blocks that contain
872 the live range of the web.
873 If OWN_END is set, also show that the register is live from our
874 definitions at the end of the basic block where it is defined. */
876 add_btr_to_live_range (btr_def def
, int own_end
)
881 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
883 SET_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
884 SET_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
890 SET_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
895 /* Update a live range to contain the basic block NEW_BLOCK, and all
896 blocks on paths between the existing live range and NEW_BLOCK.
897 HEAD is a block contained in the existing live range that dominates
898 all other blocks in the existing live range.
899 Also add to the set BTRS_LIVE_IN_RANGE all target registers that
900 are live in the blocks that we add to the live range.
901 If FULL_RANGE is set, include the full live range of NEW_BB;
902 otherwise, if NEW_BB dominates HEAD_BB, only add registers that
903 are life at the end of NEW_BB for NEW_BB itself.
904 It is a precondition that either NEW_BLOCK dominates HEAD,or
905 HEAD dom NEW_BLOCK. This is used to speed up the
906 implementation of this function. */
908 augment_live_range (bitmap live_range
, HARD_REG_SET
*btrs_live_in_range
,
909 basic_block head_bb
, basic_block new_bb
, int full_range
)
911 basic_block
*worklist
, *tos
;
913 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
915 if (dominated_by_p (CDI_DOMINATORS
, new_bb
, head_bb
))
917 if (new_bb
== head_bb
)
920 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_bb
->index
]);
930 int new_block
= new_bb
->index
;
932 gcc_assert (dominated_by_p (CDI_DOMINATORS
, head_bb
, new_bb
));
934 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[head_bb
->index
]);
935 bitmap_set_bit (live_range
, new_block
);
936 /* A previous btr migration could have caused a register to be
937 live just at the end of new_block which we need in full, so
938 use trs_live_at_end even if full_range is set. */
939 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live_at_end
[new_block
]);
941 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_block
]);
945 "Adding end of block %d and rest of %d to live range\n",
946 new_block
, head_bb
->index
);
947 fprintf (dump_file
,"Now live btrs are ");
948 dump_hard_reg_set (*btrs_live_in_range
);
949 fprintf (dump_file
, "\n");
951 FOR_EACH_EDGE (e
, ei
, head_bb
->preds
)
955 while (tos
!= worklist
)
957 basic_block bb
= *--tos
;
958 if (!bitmap_bit_p (live_range
, bb
->index
))
963 bitmap_set_bit (live_range
, bb
->index
);
964 IOR_HARD_REG_SET (*btrs_live_in_range
,
965 btrs_live
[bb
->index
]);
966 /* A previous btr migration could have caused a register to be
967 live just at the end of a block which we need in full. */
968 IOR_HARD_REG_SET (*btrs_live_in_range
,
969 btrs_live_at_end
[bb
->index
]);
973 "Adding block %d to live range\n", bb
->index
);
974 fprintf (dump_file
,"Now live btrs are ");
975 dump_hard_reg_set (*btrs_live_in_range
);
976 fprintf (dump_file
, "\n");
979 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
981 basic_block pred
= e
->src
;
982 if (!bitmap_bit_p (live_range
, pred
->index
))
991 /* Return the most desirable target register that is not in
992 the set USED_BTRS. */
994 choose_btr (HARD_REG_SET used_btrs
)
998 if (!hard_reg_set_subset_p (all_btrs
, used_btrs
))
999 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1001 #ifdef REG_ALLOC_ORDER
1002 int regno
= reg_alloc_order
[i
];
1006 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
1007 && !TEST_HARD_REG_BIT (used_btrs
, regno
))
1013 /* Calculate the set of basic blocks that contain the live range of
1014 the def/use web DEF.
1015 Also calculate the set of target registers that are live at time
1016 in this live range, but ignore the live range represented by DEF
1017 when calculating this set. */
1019 btr_def_live_range (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1021 if (!def
->live_range
)
1025 def
->live_range
= BITMAP_ALLOC (NULL
);
1027 bitmap_set_bit (def
->live_range
, def
->bb
->index
);
1028 COPY_HARD_REG_SET (*btrs_live_in_range
,
1029 (flag_btr_bb_exclusive
1030 ? btrs_live
: btrs_live_at_end
)[def
->bb
->index
]);
1032 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1033 augment_live_range (def
->live_range
, btrs_live_in_range
,
1035 (flag_btr_bb_exclusive
1036 || user
->insn
!= BB_END (def
->bb
)
1037 || !JUMP_P (user
->insn
)));
1041 /* def->live_range is accurate, but we need to recompute
1042 the set of target registers live over it, because migration
1043 of other PT instructions may have affected it.
1046 unsigned def_bb
= flag_btr_bb_exclusive
? -1 : def
->bb
->index
;
1049 CLEAR_HARD_REG_SET (*btrs_live_in_range
);
1050 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
1052 IOR_HARD_REG_SET (*btrs_live_in_range
,
1054 ? btrs_live_at_end
: btrs_live
) [bb
]);
1057 if (!def
->other_btr_uses_before_def
&&
1058 !def
->other_btr_uses_after_use
)
1059 CLEAR_HARD_REG_BIT (*btrs_live_in_range
, def
->btr
);
1062 /* Merge into the def/use web DEF any other def/use webs in the same
1063 group that are dominated by DEF, provided that there is a target
1064 register available to allocate to the merged web. */
1066 combine_btr_defs (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1070 for (other_def
= def
->group
->members
;
1072 other_def
= other_def
->next_this_group
)
1074 if (other_def
!= def
1075 && other_def
->uses
!= NULL
1076 && ! other_def
->has_ambiguous_use
1077 && dominated_by_p (CDI_DOMINATORS
, other_def
->bb
, def
->bb
))
1079 /* def->bb dominates the other def, so def and other_def could
1081 /* Merge their live ranges, and get the set of
1082 target registers live over the merged range. */
1084 HARD_REG_SET combined_btrs_live
;
1085 bitmap combined_live_range
= BITMAP_ALLOC (NULL
);
1088 if (other_def
->live_range
== NULL
)
1090 HARD_REG_SET dummy_btrs_live_in_range
;
1091 btr_def_live_range (other_def
, &dummy_btrs_live_in_range
);
1093 COPY_HARD_REG_SET (combined_btrs_live
, *btrs_live_in_range
);
1094 bitmap_copy (combined_live_range
, def
->live_range
);
1096 for (user
= other_def
->uses
; user
!= NULL
; user
= user
->next
)
1097 augment_live_range (combined_live_range
, &combined_btrs_live
,
1099 (flag_btr_bb_exclusive
1100 || user
->insn
!= BB_END (def
->bb
)
1101 || !JUMP_P (user
->insn
)));
1103 btr
= choose_btr (combined_btrs_live
);
1106 /* We can combine them. */
1109 "Combining def in insn %d with def in insn %d\n",
1110 INSN_UID (other_def
->insn
), INSN_UID (def
->insn
));
1113 user
= other_def
->uses
;
1114 while (user
!= NULL
)
1116 btr_user next
= user
->next
;
1118 user
->next
= def
->uses
;
1122 /* Combining def/use webs can make target registers live
1123 after uses where they previously were not. This means
1124 some REG_DEAD notes may no longer be correct. We could
1125 be more precise about this if we looked at the combined
1126 live range, but here I just delete any REG_DEAD notes
1127 in case they are no longer correct. */
1128 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1129 remove_note (user
->insn
,
1130 find_regno_note (user
->insn
, REG_DEAD
,
1131 REGNO (user
->use
)));
1132 clear_btr_from_live_range (other_def
);
1133 other_def
->uses
= NULL
;
1134 bitmap_copy (def
->live_range
, combined_live_range
);
1135 if (other_def
->btr
== btr
&& other_def
->other_btr_uses_after_use
)
1136 def
->other_btr_uses_after_use
= 1;
1137 COPY_HARD_REG_SET (*btrs_live_in_range
, combined_btrs_live
);
1139 /* Delete the old target register initialization. */
1140 delete_insn (other_def
->insn
);
1143 BITMAP_FREE (combined_live_range
);
1148 /* Move the definition DEF from its current position to basic
1149 block NEW_DEF_BB, and modify it to use branch target register BTR.
1150 Delete the old defining insn, and insert a new one in NEW_DEF_BB.
1151 Update all reaching uses of DEF in the RTL to use BTR.
1152 If this new position means that other defs in the
1153 same group can be combined with DEF then combine them. */
1155 move_btr_def (basic_block new_def_bb
, int btr
, btr_def def
, bitmap live_range
,
1156 HARD_REG_SET
*btrs_live_in_range
)
1158 /* We can move the instruction.
1159 Set a target register in block NEW_DEF_BB to the value
1160 needed for this target register definition.
1161 Replace all uses of the old target register definition by
1162 uses of the new definition. Delete the old definition. */
1163 basic_block b
= new_def_bb
;
1164 rtx_insn
*insp
= BB_HEAD (b
);
1165 rtx_insn
*old_insn
= def
->insn
;
1169 machine_mode btr_mode
;
1174 fprintf(dump_file
, "migrating to basic block %d, using reg %d\n",
1175 new_def_bb
->index
, btr
);
1177 clear_btr_from_live_range (def
);
1179 def
->bb
= new_def_bb
;
1181 def
->cost
= basic_block_freq (new_def_bb
);
1182 bitmap_copy (def
->live_range
, live_range
);
1183 combine_btr_defs (def
, btrs_live_in_range
);
1185 def
->other_btr_uses_before_def
1186 = TEST_HARD_REG_BIT (btrs_live
[b
->index
], btr
) ? 1 : 0;
1187 add_btr_to_live_range (def
, 1);
1189 insp
= NEXT_INSN (insp
);
1190 /* N.B.: insp is expected to be NOTE_INSN_BASIC_BLOCK now. Some
1191 optimizations can result in insp being both first and last insn of
1193 /* ?? some assertions to check that insp is sensible? */
1195 if (def
->other_btr_uses_before_def
)
1198 for (insp
= BB_END (b
); ! INSN_P (insp
); insp
= PREV_INSN (insp
))
1199 gcc_assert (insp
!= BB_HEAD (b
));
1201 if (JUMP_P (insp
) || can_throw_internal (insp
))
1202 insp
= PREV_INSN (insp
);
1205 set
= single_set (old_insn
);
1206 src
= SET_SRC (set
);
1207 btr_mode
= GET_MODE (SET_DEST (set
));
1208 btr_rtx
= gen_rtx_REG (btr_mode
, btr
);
1210 new_insn
= gen_move_insn (btr_rtx
, src
);
1212 /* Insert target register initialization at head of basic block. */
1213 def
->insn
= emit_insn_after (new_insn
, insp
);
1215 df_set_regs_ever_live (btr
, true);
1218 fprintf (dump_file
, "New pt is insn %d, inserted after insn %d\n",
1219 INSN_UID (def
->insn
), INSN_UID (insp
));
1221 /* Delete the old target register initialization. */
1222 delete_insn (old_insn
);
1224 /* Replace each use of the old target register by a use of the new target
1226 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1228 /* Some extra work here to ensure consistent modes, because
1229 it seems that a target register REG rtx can be given a different
1230 mode depending on the context (surely that should not be
1232 rtx replacement_rtx
;
1233 if (GET_MODE (user
->use
) == GET_MODE (btr_rtx
)
1234 || GET_MODE (user
->use
) == VOIDmode
)
1235 replacement_rtx
= btr_rtx
;
1237 replacement_rtx
= gen_rtx_REG (GET_MODE (user
->use
), btr
);
1238 validate_replace_rtx (user
->use
, replacement_rtx
, user
->insn
);
1239 user
->use
= replacement_rtx
;
1243 /* We anticipate intra-block scheduling to be done. See if INSN could move
1244 up within BB by N_INSNS. */
1246 can_move_up (const_basic_block bb
, const rtx_insn
*insn
, int n_insns
)
1248 while (insn
!= BB_HEAD (bb
) && n_insns
> 0)
1250 insn
= PREV_INSN (insn
);
1251 /* ??? What if we have an anti-dependency that actually prevents the
1252 scheduler from doing the move? We'd like to re-allocate the register,
1253 but not necessarily put the load into another basic block. */
1257 return n_insns
<= 0;
1260 /* Attempt to migrate the target register definition DEF to an
1261 earlier point in the flowgraph.
1263 It is a precondition of this function that DEF is migratable:
1264 i.e. it has a constant source, and all uses are unambiguous.
1266 Only migrations that reduce the cost of DEF will be made.
1267 MIN_COST is the lower bound on the cost of the DEF after migration.
1268 If we migrate DEF so that its cost falls below MIN_COST,
1269 then we do not attempt to migrate further. The idea is that
1270 we migrate definitions in a priority order based on their cost,
1271 when the cost of this definition falls below MIN_COST, then
1272 there is another definition with cost == MIN_COST which now
1273 has a higher priority than this definition.
1275 Return nonzero if there may be benefit from attempting to
1276 migrate this DEF further (i.e. we have reduced the cost below
1277 MIN_COST, but we may be able to reduce it further).
1278 Return zero if no further migration is possible. */
1280 migrate_btr_def (btr_def def
, int min_cost
)
1283 HARD_REG_SET btrs_live_in_range
;
1284 int btr_used_near_def
= 0;
1285 int def_basic_block_freq
;
1286 basic_block attempt
;
1294 "Attempting to migrate pt from insn %d (cost = %d, min_cost = %d) ... ",
1295 INSN_UID (def
->insn
), def
->cost
, min_cost
);
1297 if (!def
->group
|| def
->has_ambiguous_use
)
1298 /* These defs are not migratable. */
1301 fprintf (dump_file
, "it's not migratable\n");
1306 /* We have combined this def with another in the same group, so
1307 no need to consider it further.
1311 fprintf (dump_file
, "it's already combined with another pt\n");
1315 btr_def_live_range (def
, &btrs_live_in_range
);
1316 live_range
= BITMAP_ALLOC (NULL
);
1317 bitmap_copy (live_range
, def
->live_range
);
1319 #ifdef INSN_SCHEDULING
1320 def_latency
= insn_default_latency (def
->insn
) * issue_rate
;
1322 def_latency
= issue_rate
;
1325 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1327 if (user
->bb
== def
->bb
1328 && user
->luid
> def
->luid
1329 && (def
->luid
+ def_latency
) > user
->luid
1330 && ! can_move_up (def
->bb
, def
->insn
,
1331 (def
->luid
+ def_latency
) - user
->luid
))
1333 btr_used_near_def
= 1;
1338 def_basic_block_freq
= basic_block_freq (def
->bb
);
1340 for (attempt
= get_immediate_dominator (CDI_DOMINATORS
, def
->bb
);
1341 !give_up
&& attempt
&& attempt
!= ENTRY_BLOCK_PTR_FOR_FN (cfun
)
1342 && def
->cost
>= min_cost
;
1343 attempt
= get_immediate_dominator (CDI_DOMINATORS
, attempt
))
1345 /* Try to move the instruction that sets the target register into
1346 basic block ATTEMPT. */
1347 int try_freq
= basic_block_freq (attempt
);
1351 /* If ATTEMPT has abnormal edges, skip it. */
1352 FOR_EACH_EDGE (e
, ei
, attempt
->succs
)
1353 if (e
->flags
& EDGE_COMPLEX
)
1359 fprintf (dump_file
, "trying block %d ...", attempt
->index
);
1361 if (try_freq
< def_basic_block_freq
1362 || (try_freq
== def_basic_block_freq
&& btr_used_near_def
))
1365 augment_live_range (live_range
, &btrs_live_in_range
, def
->bb
, attempt
,
1366 flag_btr_bb_exclusive
);
1369 fprintf (dump_file
, "Now btrs live in range are: ");
1370 dump_hard_reg_set (btrs_live_in_range
);
1371 fprintf (dump_file
, "\n");
1373 btr
= choose_btr (btrs_live_in_range
);
1376 move_btr_def (attempt
, btr
, def
, live_range
, &btrs_live_in_range
);
1377 bitmap_copy (live_range
, def
->live_range
);
1378 btr_used_near_def
= 0;
1380 def_basic_block_freq
= basic_block_freq (def
->bb
);
1384 /* There are no free target registers available to move
1385 this far forward, so give up */
1389 "giving up because there are no free target registers\n");
1398 fprintf (dump_file
, "failed to move\n");
1400 BITMAP_FREE (live_range
);
1404 /* Attempt to move instructions that set target registers earlier
1405 in the flowgraph, away from their corresponding uses. */
1407 migrate_btr_defs (enum reg_class btr_class
, int allow_callee_save
)
1409 btr_heap_t
all_btr_defs (LONG_MIN
);
1412 gcc_obstack_init (&migrate_btrl_obstack
);
1417 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
1419 basic_block bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
1421 "Basic block %d: count = %" PRId64
1422 " loop-depth = %d idom = %d\n",
1423 i
, (int64_t) bb
->count
, bb_loop_depth (bb
),
1424 get_immediate_dominator (CDI_DOMINATORS
, bb
)->index
);
1428 CLEAR_HARD_REG_SET (all_btrs
);
1429 for (first_btr
= -1, reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
1430 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) btr_class
], reg
)
1431 && (allow_callee_save
|| call_used_regs
[reg
]
1432 || df_regs_ever_live_p (reg
)))
1434 SET_HARD_REG_BIT (all_btrs
, reg
);
1440 btrs_live
= XCNEWVEC (HARD_REG_SET
, last_basic_block_for_fn (cfun
));
1441 btrs_live_at_end
= XCNEWVEC (HARD_REG_SET
, last_basic_block_for_fn (cfun
));
1443 build_btr_def_use_webs (&all_btr_defs
);
1445 while (!all_btr_defs
.empty ())
1447 int min_cost
= -all_btr_defs
.min_key ();
1448 btr_def def
= all_btr_defs
.extract_min ();
1449 if (migrate_btr_def (def
, min_cost
))
1451 all_btr_defs
.insert (-def
->cost
, def
);
1455 "Putting insn %d back on queue with priority %d\n",
1456 INSN_UID (def
->insn
), def
->cost
);
1460 BITMAP_FREE (def
->live_range
);
1464 free (btrs_live_at_end
);
1465 obstack_free (&migrate_btrl_obstack
, NULL
);
1469 branch_target_load_optimize (bool after_prologue_epilogue_gen
)
1471 enum reg_class klass
1472 = (enum reg_class
) targetm
.branch_target_register_class ();
1473 if (klass
!= NO_REGS
)
1475 /* Initialize issue_rate. */
1476 if (targetm
.sched
.issue_rate
)
1477 issue_rate
= targetm
.sched
.issue_rate ();
1481 if (!after_prologue_epilogue_gen
)
1483 /* Build the CFG for migrate_btr_defs. */
1485 /* This may or may not be needed, depending on where we
1487 cleanup_cfg (optimize
? CLEANUP_EXPENSIVE
: 0);
1493 /* Dominator info is also needed for migrate_btr_def. */
1494 calculate_dominance_info (CDI_DOMINATORS
);
1495 migrate_btr_defs (klass
,
1496 (targetm
.branch_target_register_callee_saved
1497 (after_prologue_epilogue_gen
)));
1499 free_dominance_info (CDI_DOMINATORS
);
1505 const pass_data pass_data_branch_target_load_optimize1
=
1507 RTL_PASS
, /* type */
1509 OPTGROUP_NONE
, /* optinfo_flags */
1510 TV_NONE
, /* tv_id */
1511 0, /* properties_required */
1512 0, /* properties_provided */
1513 0, /* properties_destroyed */
1514 0, /* todo_flags_start */
1515 0, /* todo_flags_finish */
1518 class pass_branch_target_load_optimize1
: public rtl_opt_pass
1521 pass_branch_target_load_optimize1 (gcc::context
*ctxt
)
1522 : rtl_opt_pass (pass_data_branch_target_load_optimize1
, ctxt
)
1525 /* opt_pass methods: */
1526 virtual bool gate (function
*) { return flag_branch_target_load_optimize
; }
1527 virtual unsigned int execute (function
*)
1529 branch_target_load_optimize (epilogue_completed
);
1533 }; // class pass_branch_target_load_optimize1
1538 make_pass_branch_target_load_optimize1 (gcc::context
*ctxt
)
1540 return new pass_branch_target_load_optimize1 (ctxt
);
1546 const pass_data pass_data_branch_target_load_optimize2
=
1548 RTL_PASS
, /* type */
1550 OPTGROUP_NONE
, /* optinfo_flags */
1551 TV_NONE
, /* tv_id */
1552 0, /* properties_required */
1553 0, /* properties_provided */
1554 0, /* properties_destroyed */
1555 0, /* todo_flags_start */
1556 0, /* todo_flags_finish */
1559 class pass_branch_target_load_optimize2
: public rtl_opt_pass
1562 pass_branch_target_load_optimize2 (gcc::context
*ctxt
)
1563 : rtl_opt_pass (pass_data_branch_target_load_optimize2
, ctxt
)
1566 /* opt_pass methods: */
1567 virtual bool gate (function
*)
1569 return (optimize
> 0 && flag_branch_target_load_optimize2
);
1572 virtual unsigned int execute (function
*);
1574 }; // class pass_branch_target_load_optimize2
1577 pass_branch_target_load_optimize2::execute (function
*)
1579 static int warned
= 0;
1581 /* Leave this a warning for now so that it is possible to experiment
1582 with running this pass twice. In 3.6, we should either make this
1583 an error, or use separate dump files. */
1584 if (flag_branch_target_load_optimize
1585 && flag_branch_target_load_optimize2
1588 warning (0, "branch target register load optimization is not intended "
1594 branch_target_load_optimize (epilogue_completed
);
1601 make_pass_branch_target_load_optimize2 (gcc::context
*ctxt
)
1603 return new pass_branch_target_load_optimize2 (ctxt
);