1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 #define nonzero_bits(X, M) \
141 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
143 #define num_sign_bit_copies(X, M) \
144 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno
;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx
*reg_last_death
;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx
*reg_last_set
;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set
;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid
;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn
;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid
;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs
;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn
;
196 /* Basic block in which we are performing combines. */
197 static basic_block this_basic_block
;
199 /* A bitmap indicating which blocks had registers go dead at entry.
200 After combine, we'll need to re-do global life analysis with
201 those blocks as starting points. */
202 static sbitmap refresh_blocks
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if an
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; int i
;} old_contents
;
318 union {rtx
*r
; int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST (rtx
*, rtx
);
342 static void do_SUBST_INT (int *, int);
343 static void init_reg_last_arrays (void);
344 static void setup_incoming_promotions (void);
345 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
346 static int cant_combine_insn_p (rtx
);
347 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
348 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
349 static int contains_muldiv (rtx
);
350 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
351 static void undo_all (void);
352 static void undo_commit (void);
353 static rtx
*find_split_point (rtx
*, rtx
);
354 static rtx
subst (rtx
, rtx
, rtx
, int, int);
355 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
356 static rtx
simplify_if_then_else (rtx
);
357 static rtx
simplify_set (rtx
);
358 static rtx
simplify_logical (rtx
, int);
359 static rtx
expand_compound_operation (rtx
);
360 static rtx
expand_field_assignment (rtx
);
361 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
362 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
363 static rtx
extract_left_shift (rtx
, int);
364 static rtx
make_compound_operation (rtx
, enum rtx_code
);
365 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
366 unsigned HOST_WIDE_INT
*);
367 static rtx
force_to_mode (rtx
, enum machine_mode
,
368 unsigned HOST_WIDE_INT
, rtx
, int);
369 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
370 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
371 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
372 static rtx
make_field_assignment (rtx
);
373 static rtx
apply_distributive_law (rtx
);
374 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
375 unsigned HOST_WIDE_INT
);
376 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
377 rtx
, enum machine_mode
,
378 unsigned HOST_WIDE_INT
);
379 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
381 unsigned HOST_WIDE_INT
);
382 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
385 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
386 enum machine_mode
, unsigned int);
387 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
388 HOST_WIDE_INT
, enum machine_mode
, int *);
389 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
391 static int recog_for_combine (rtx
*, rtx
, rtx
*);
392 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
393 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
394 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
395 static void update_table_tick (rtx
);
396 static void record_value_for_reg (rtx
, rtx
, rtx
);
397 static void check_promoted_subreg (rtx
, rtx
);
398 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
399 static void record_dead_and_set_regs (rtx
);
400 static int get_last_value_validate (rtx
*, rtx
, int, int);
401 static rtx
get_last_value (rtx
);
402 static int use_crosses_set_p (rtx
, int);
403 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
404 static int reg_dead_at_p (rtx
, rtx
);
405 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
406 static int reg_bitfield_target_p (rtx
, rtx
);
407 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
408 static void distribute_links (rtx
);
409 static void mark_used_regs_combine (rtx
);
410 static int insn_cuid (rtx
);
411 static void record_promoted_value (rtx
, rtx
);
412 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
413 static enum rtx_code
combine_reversed_comparison_code (rtx
);
415 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
416 insn. The substitution can be undone by undo_all. If INTO is already
417 set to NEWVAL, do not record this change. Because computing NEWVAL might
418 also call SUBST, we have to compute it before we put anything into
422 do_SUBST (rtx
*into
, rtx newval
)
427 if (oldval
== newval
)
430 /* We'd like to catch as many invalid transformations here as
431 possible. Unfortunately, there are way too many mode changes
432 that are perfectly valid, so we'd waste too much effort for
433 little gain doing the checks here. Focus on catching invalid
434 transformations involving integer constants. */
435 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
436 && GET_CODE (newval
) == CONST_INT
)
438 /* Sanity check that we're replacing oldval with a CONST_INT
439 that is a valid sign-extension for the original mode. */
440 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
444 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
445 CONST_INT is not valid, because after the replacement, the
446 original mode would be gone. Unfortunately, we can't tell
447 when do_SUBST is called to replace the operand thereof, so we
448 perform this test on oldval instead, checking whether an
449 invalid replacement took place before we got here. */
450 if ((GET_CODE (oldval
) == SUBREG
451 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
452 || (GET_CODE (oldval
) == ZERO_EXTEND
453 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
458 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
460 buf
= xmalloc (sizeof (struct undo
));
464 buf
->old_contents
.r
= oldval
;
467 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
470 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
472 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
473 for the value of a HOST_WIDE_INT value (including CONST_INT) is
477 do_SUBST_INT (int *into
, int newval
)
482 if (oldval
== newval
)
486 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
488 buf
= xmalloc (sizeof (struct undo
));
492 buf
->old_contents
.i
= oldval
;
495 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
498 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
500 /* Main entry point for combiner. F is the first insn of the function.
501 NREGS is the first unused pseudo-reg number.
503 Return nonzero if the combiner has turned an indirect jump
504 instruction into a direct jump. */
506 combine_instructions (rtx f
, unsigned int nregs
)
513 rtx links
, nextlinks
;
515 int new_direct_jump_p
= 0;
517 combine_attempts
= 0;
520 combine_successes
= 0;
522 combine_max_regno
= nregs
;
524 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
525 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
527 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
528 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
530 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
531 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
532 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
533 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
534 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
535 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
537 init_reg_last_arrays ();
539 init_recog_no_volatile ();
541 /* Compute maximum uid value so uid_cuid can be allocated. */
543 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
544 if (INSN_UID (insn
) > i
)
547 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
550 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
552 /* Don't use reg_nonzero_bits when computing it. This can cause problems
553 when, for example, we have j <<= 1 in a loop. */
555 nonzero_sign_valid
= 0;
557 /* Compute the mapping from uids to cuids.
558 Cuids are numbers assigned to insns, like uids,
559 except that cuids increase monotonically through the code.
561 Scan all SETs and see if we can deduce anything about what
562 bits are known to be zero for some registers and how many copies
563 of the sign bit are known to exist for those registers.
565 Also set any known values so that we can use it while searching
566 for what bits are known to be set. */
570 setup_incoming_promotions ();
572 refresh_blocks
= sbitmap_alloc (last_basic_block
);
573 sbitmap_zero (refresh_blocks
);
575 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
577 uid_cuid
[INSN_UID (insn
)] = ++i
;
583 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
585 record_dead_and_set_regs (insn
);
588 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
589 if (REG_NOTE_KIND (links
) == REG_INC
)
590 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
595 if (GET_CODE (insn
) == CODE_LABEL
)
599 nonzero_sign_valid
= 1;
601 /* Now scan all the insns in forward order. */
606 init_reg_last_arrays ();
607 setup_incoming_promotions ();
609 FOR_EACH_BB (this_basic_block
)
611 for (insn
= BB_HEAD (this_basic_block
);
612 insn
!= NEXT_INSN (BB_END (this_basic_block
));
613 insn
= next
? next
: NEXT_INSN (insn
))
617 if (GET_CODE (insn
) == CODE_LABEL
)
620 else if (INSN_P (insn
))
622 /* See if we know about function return values before this
623 insn based upon SUBREG flags. */
624 check_promoted_subreg (insn
, PATTERN (insn
));
626 /* Try this insn with each insn it links back to. */
628 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
629 if ((next
= try_combine (insn
, XEXP (links
, 0),
630 NULL_RTX
, &new_direct_jump_p
)) != 0)
633 /* Try each sequence of three linked insns ending with this one. */
635 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
637 rtx link
= XEXP (links
, 0);
639 /* If the linked insn has been replaced by a note, then there
640 is no point in pursuing this chain any further. */
641 if (GET_CODE (link
) == NOTE
)
644 for (nextlinks
= LOG_LINKS (link
);
646 nextlinks
= XEXP (nextlinks
, 1))
647 if ((next
= try_combine (insn
, link
,
649 &new_direct_jump_p
)) != 0)
654 /* Try to combine a jump insn that uses CC0
655 with a preceding insn that sets CC0, and maybe with its
656 logical predecessor as well.
657 This is how we make decrement-and-branch insns.
658 We need this special code because data flow connections
659 via CC0 do not get entered in LOG_LINKS. */
661 if (GET_CODE (insn
) == JUMP_INSN
662 && (prev
= prev_nonnote_insn (insn
)) != 0
663 && GET_CODE (prev
) == INSN
664 && sets_cc0_p (PATTERN (prev
)))
666 if ((next
= try_combine (insn
, prev
,
667 NULL_RTX
, &new_direct_jump_p
)) != 0)
670 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
671 nextlinks
= XEXP (nextlinks
, 1))
672 if ((next
= try_combine (insn
, prev
,
674 &new_direct_jump_p
)) != 0)
678 /* Do the same for an insn that explicitly references CC0. */
679 if (GET_CODE (insn
) == INSN
680 && (prev
= prev_nonnote_insn (insn
)) != 0
681 && GET_CODE (prev
) == INSN
682 && sets_cc0_p (PATTERN (prev
))
683 && GET_CODE (PATTERN (insn
)) == SET
684 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
686 if ((next
= try_combine (insn
, prev
,
687 NULL_RTX
, &new_direct_jump_p
)) != 0)
690 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
691 nextlinks
= XEXP (nextlinks
, 1))
692 if ((next
= try_combine (insn
, prev
,
694 &new_direct_jump_p
)) != 0)
698 /* Finally, see if any of the insns that this insn links to
699 explicitly references CC0. If so, try this insn, that insn,
700 and its predecessor if it sets CC0. */
701 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
702 if (GET_CODE (XEXP (links
, 0)) == INSN
703 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
704 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
705 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
706 && GET_CODE (prev
) == INSN
707 && sets_cc0_p (PATTERN (prev
))
708 && (next
= try_combine (insn
, XEXP (links
, 0),
709 prev
, &new_direct_jump_p
)) != 0)
713 /* Try combining an insn with two different insns whose results it
715 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
716 for (nextlinks
= XEXP (links
, 1); nextlinks
;
717 nextlinks
= XEXP (nextlinks
, 1))
718 if ((next
= try_combine (insn
, XEXP (links
, 0),
720 &new_direct_jump_p
)) != 0)
723 if (GET_CODE (insn
) != NOTE
)
724 record_dead_and_set_regs (insn
);
733 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
734 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
735 new_direct_jump_p
|= purge_all_dead_edges (0);
736 delete_noop_moves (f
);
738 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
739 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
740 | PROP_KILL_DEAD_CODE
);
743 sbitmap_free (refresh_blocks
);
744 free (reg_nonzero_bits
);
745 free (reg_sign_bit_copies
);
746 free (reg_last_death
);
748 free (reg_last_set_value
);
749 free (reg_last_set_table_tick
);
750 free (reg_last_set_label
);
751 free (reg_last_set_invalid
);
752 free (reg_last_set_mode
);
753 free (reg_last_set_nonzero_bits
);
754 free (reg_last_set_sign_bit_copies
);
758 struct undo
*undo
, *next
;
759 for (undo
= undobuf
.frees
; undo
; undo
= next
)
767 total_attempts
+= combine_attempts
;
768 total_merges
+= combine_merges
;
769 total_extras
+= combine_extras
;
770 total_successes
+= combine_successes
;
772 nonzero_sign_valid
= 0;
774 /* Make recognizer allow volatile MEMs again. */
777 return new_direct_jump_p
;
780 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
783 init_reg_last_arrays (void)
785 unsigned int nregs
= combine_max_regno
;
787 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
788 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
789 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
790 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
791 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
792 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
793 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
794 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
795 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
798 /* Set up any promoted values for incoming argument registers. */
801 setup_incoming_promotions (void)
805 enum machine_mode mode
;
807 rtx first
= get_insns ();
809 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
811 #ifndef OUTGOING_REGNO
812 #define OUTGOING_REGNO(N) N
814 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
815 /* Check whether this register can hold an incoming pointer
816 argument. FUNCTION_ARG_REGNO_P tests outgoing register
817 numbers, so translate if necessary due to register windows. */
818 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
819 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
822 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
825 gen_rtx_CLOBBER (mode
, const0_rtx
)));
830 /* Called via note_stores. If X is a pseudo that is narrower than
831 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
833 If we are setting only a portion of X and we can't figure out what
834 portion, assume all bits will be used since we don't know what will
837 Similarly, set how many bits of X are known to be copies of the sign bit
838 at all locations in the function. This is the smallest number implied
842 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
843 void *data ATTRIBUTE_UNUSED
)
847 if (GET_CODE (x
) == REG
848 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
849 /* If this register is undefined at the start of the file, we can't
850 say what its contents were. */
851 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
852 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
854 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
856 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
857 reg_sign_bit_copies
[REGNO (x
)] = 1;
861 /* If this is a complex assignment, see if we can convert it into a
862 simple assignment. */
863 set
= expand_field_assignment (set
);
865 /* If this is a simple assignment, or we have a paradoxical SUBREG,
866 set what we know about X. */
868 if (SET_DEST (set
) == x
869 || (GET_CODE (SET_DEST (set
)) == SUBREG
870 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
871 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
872 && SUBREG_REG (SET_DEST (set
)) == x
))
874 rtx src
= SET_SRC (set
);
876 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
877 /* If X is narrower than a word and SRC is a non-negative
878 constant that would appear negative in the mode of X,
879 sign-extend it for use in reg_nonzero_bits because some
880 machines (maybe most) will actually do the sign-extension
881 and this is the conservative approach.
883 ??? For 2.5, try to tighten up the MD files in this regard
884 instead of this kludge. */
886 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
887 && GET_CODE (src
) == CONST_INT
889 && 0 != (INTVAL (src
)
891 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
892 src
= GEN_INT (INTVAL (src
)
893 | ((HOST_WIDE_INT
) (-1)
894 << GET_MODE_BITSIZE (GET_MODE (x
))));
897 /* Don't call nonzero_bits if it cannot change anything. */
898 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
899 reg_nonzero_bits
[REGNO (x
)]
900 |= nonzero_bits (src
, nonzero_bits_mode
);
901 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
902 if (reg_sign_bit_copies
[REGNO (x
)] == 0
903 || reg_sign_bit_copies
[REGNO (x
)] > num
)
904 reg_sign_bit_copies
[REGNO (x
)] = num
;
908 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
909 reg_sign_bit_copies
[REGNO (x
)] = 1;
914 /* See if INSN can be combined into I3. PRED and SUCC are optionally
915 insns that were previously combined into I3 or that will be combined
916 into the merger of INSN and I3.
918 Return 0 if the combination is not allowed for any reason.
920 If the combination is allowed, *PDEST will be set to the single
921 destination of INSN and *PSRC to the single source, and this function
925 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
926 rtx
*pdest
, rtx
*psrc
)
929 rtx set
= 0, src
, dest
;
934 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
935 && next_active_insn (succ
) == i3
)
936 : next_active_insn (insn
) == i3
);
938 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
939 or a PARALLEL consisting of such a SET and CLOBBERs.
941 If INSN has CLOBBER parallel parts, ignore them for our processing.
942 By definition, these happen during the execution of the insn. When it
943 is merged with another insn, all bets are off. If they are, in fact,
944 needed and aren't also supplied in I3, they may be added by
945 recog_for_combine. Otherwise, it won't match.
947 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
950 Get the source and destination of INSN. If more than one, can't
953 if (GET_CODE (PATTERN (insn
)) == SET
)
954 set
= PATTERN (insn
);
955 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
956 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
958 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
960 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
962 switch (GET_CODE (elt
))
964 /* This is important to combine floating point insns
967 /* Combining an isolated USE doesn't make sense.
968 We depend here on combinable_i3pat to reject them. */
969 /* The code below this loop only verifies that the inputs of
970 the SET in INSN do not change. We call reg_set_between_p
971 to verify that the REG in the USE does not change between
973 If the USE in INSN was for a pseudo register, the matching
974 insn pattern will likely match any register; combining this
975 with any other USE would only be safe if we knew that the
976 used registers have identical values, or if there was
977 something to tell them apart, e.g. different modes. For
978 now, we forgo such complicated tests and simply disallow
979 combining of USES of pseudo registers with any other USE. */
980 if (GET_CODE (XEXP (elt
, 0)) == REG
981 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
983 rtx i3pat
= PATTERN (i3
);
984 int i
= XVECLEN (i3pat
, 0) - 1;
985 unsigned int regno
= REGNO (XEXP (elt
, 0));
989 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
991 if (GET_CODE (i3elt
) == USE
992 && GET_CODE (XEXP (i3elt
, 0)) == REG
993 && (REGNO (XEXP (i3elt
, 0)) == regno
994 ? reg_set_between_p (XEXP (elt
, 0),
995 PREV_INSN (insn
), i3
)
996 : regno
>= FIRST_PSEUDO_REGISTER
))
1003 /* We can ignore CLOBBERs. */
1008 /* Ignore SETs whose result isn't used but not those that
1009 have side-effects. */
1010 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1011 && ! side_effects_p (elt
))
1014 /* If we have already found a SET, this is a second one and
1015 so we cannot combine with this insn. */
1023 /* Anything else means we can't combine. */
1029 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1030 so don't do anything with it. */
1031 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1040 set
= expand_field_assignment (set
);
1041 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1043 /* Don't eliminate a store in the stack pointer. */
1044 if (dest
== stack_pointer_rtx
1045 /* Don't combine with an insn that sets a register to itself if it has
1046 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1047 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1048 /* Can't merge an ASM_OPERANDS. */
1049 || GET_CODE (src
) == ASM_OPERANDS
1050 /* Can't merge a function call. */
1051 || GET_CODE (src
) == CALL
1052 /* Don't eliminate a function call argument. */
1053 || (GET_CODE (i3
) == CALL_INSN
1054 && (find_reg_fusage (i3
, USE
, dest
)
1055 || (GET_CODE (dest
) == REG
1056 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1057 && global_regs
[REGNO (dest
)])))
1058 /* Don't substitute into an incremented register. */
1059 || FIND_REG_INC_NOTE (i3
, dest
)
1060 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1062 /* Don't combine the end of a libcall into anything. */
1063 /* ??? This gives worse code, and appears to be unnecessary, since no
1064 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1065 use REG_RETVAL notes for noconflict blocks, but other code here
1066 makes sure that those insns don't disappear. */
1067 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1069 /* Make sure that DEST is not used after SUCC but before I3. */
1070 || (succ
&& ! all_adjacent
1071 && reg_used_between_p (dest
, succ
, i3
))
1072 /* Make sure that the value that is to be substituted for the register
1073 does not use any registers whose values alter in between. However,
1074 If the insns are adjacent, a use can't cross a set even though we
1075 think it might (this can happen for a sequence of insns each setting
1076 the same destination; reg_last_set of that register might point to
1077 a NOTE). If INSN has a REG_EQUIV note, the register is always
1078 equivalent to the memory so the substitution is valid even if there
1079 are intervening stores. Also, don't move a volatile asm or
1080 UNSPEC_VOLATILE across any other insns. */
1082 && (((GET_CODE (src
) != MEM
1083 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1084 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1085 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1086 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1087 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1088 better register allocation by not doing the combine. */
1089 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1090 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1091 /* Don't combine across a CALL_INSN, because that would possibly
1092 change whether the life span of some REGs crosses calls or not,
1093 and it is a pain to update that information.
1094 Exception: if source is a constant, moving it later can't hurt.
1095 Accept that special case, because it helps -fforce-addr a lot. */
1096 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1099 /* DEST must either be a REG or CC0. */
1100 if (GET_CODE (dest
) == REG
)
1102 /* If register alignment is being enforced for multi-word items in all
1103 cases except for parameters, it is possible to have a register copy
1104 insn referencing a hard register that is not allowed to contain the
1105 mode being copied and which would not be valid as an operand of most
1106 insns. Eliminate this problem by not combining with such an insn.
1108 Also, on some machines we don't want to extend the life of a hard
1111 if (GET_CODE (src
) == REG
1112 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1113 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1114 /* Don't extend the life of a hard register unless it is
1115 user variable (if we have few registers) or it can't
1116 fit into the desired register (meaning something special
1118 Also avoid substituting a return register into I3, because
1119 reload can't handle a conflict with constraints of other
1121 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1122 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1125 else if (GET_CODE (dest
) != CC0
)
1128 /* Don't substitute for a register intended as a clobberable operand.
1129 Similarly, don't substitute an expression containing a register that
1130 will be clobbered in I3. */
1131 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1132 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1133 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1134 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1136 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1139 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1140 or not), reject, unless nothing volatile comes between it and I3 */
1142 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1144 /* Make sure succ doesn't contain a volatile reference. */
1145 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1148 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1149 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1153 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1154 to be an explicit register variable, and was chosen for a reason. */
1156 if (GET_CODE (src
) == ASM_OPERANDS
1157 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1160 /* If there are any volatile insns between INSN and I3, reject, because
1161 they might affect machine state. */
1163 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1164 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1167 /* If INSN or I2 contains an autoincrement or autodecrement,
1168 make sure that register is not used between there and I3,
1169 and not already used in I3 either.
1170 Also insist that I3 not be a jump; if it were one
1171 and the incremented register were spilled, we would lose. */
1174 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1175 if (REG_NOTE_KIND (link
) == REG_INC
1176 && (GET_CODE (i3
) == JUMP_INSN
1177 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1178 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1183 /* Don't combine an insn that follows a CC0-setting insn.
1184 An insn that uses CC0 must not be separated from the one that sets it.
1185 We do, however, allow I2 to follow a CC0-setting insn if that insn
1186 is passed as I1; in that case it will be deleted also.
1187 We also allow combining in this case if all the insns are adjacent
1188 because that would leave the two CC0 insns adjacent as well.
1189 It would be more logical to test whether CC0 occurs inside I1 or I2,
1190 but that would be much slower, and this ought to be equivalent. */
1192 p
= prev_nonnote_insn (insn
);
1193 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1198 /* If we get here, we have passed all the tests and the combination is
1207 /* LOC is the location within I3 that contains its pattern or the component
1208 of a PARALLEL of the pattern. We validate that it is valid for combining.
1210 One problem is if I3 modifies its output, as opposed to replacing it
1211 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1212 so would produce an insn that is not equivalent to the original insns.
1216 (set (reg:DI 101) (reg:DI 100))
1217 (set (subreg:SI (reg:DI 101) 0) <foo>)
1219 This is NOT equivalent to:
1221 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1222 (set (reg:DI 101) (reg:DI 100))])
1224 Not only does this modify 100 (in which case it might still be valid
1225 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1227 We can also run into a problem if I2 sets a register that I1
1228 uses and I1 gets directly substituted into I3 (not via I2). In that
1229 case, we would be getting the wrong value of I2DEST into I3, so we
1230 must reject the combination. This case occurs when I2 and I1 both
1231 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1232 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1233 of a SET must prevent combination from occurring.
1235 Before doing the above check, we first try to expand a field assignment
1236 into a set of logical operations.
1238 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1239 we place a register that is both set and used within I3. If more than one
1240 such register is detected, we fail.
1242 Return 1 if the combination is valid, zero otherwise. */
1245 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1246 int i1_not_in_src
, rtx
*pi3dest_killed
)
1250 if (GET_CODE (x
) == SET
)
1253 rtx dest
= SET_DEST (set
);
1254 rtx src
= SET_SRC (set
);
1255 rtx inner_dest
= dest
;
1257 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1258 || GET_CODE (inner_dest
) == SUBREG
1259 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1260 inner_dest
= XEXP (inner_dest
, 0);
1262 /* Check for the case where I3 modifies its output, as discussed
1263 above. We don't want to prevent pseudos from being combined
1264 into the address of a MEM, so only prevent the combination if
1265 i1 or i2 set the same MEM. */
1266 if ((inner_dest
!= dest
&&
1267 (GET_CODE (inner_dest
) != MEM
1268 || rtx_equal_p (i2dest
, inner_dest
)
1269 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1270 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1271 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1273 /* This is the same test done in can_combine_p except we can't test
1274 all_adjacent; we don't have to, since this instruction will stay
1275 in place, thus we are not considering increasing the lifetime of
1278 Also, if this insn sets a function argument, combining it with
1279 something that might need a spill could clobber a previous
1280 function argument; the all_adjacent test in can_combine_p also
1281 checks this; here, we do a more specific test for this case. */
1283 || (GET_CODE (inner_dest
) == REG
1284 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1285 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1286 GET_MODE (inner_dest
))))
1287 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1290 /* If DEST is used in I3, it is being killed in this insn,
1291 so record that for later.
1292 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1293 STACK_POINTER_REGNUM, since these are always considered to be
1294 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1295 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1296 && reg_referenced_p (dest
, PATTERN (i3
))
1297 && REGNO (dest
) != FRAME_POINTER_REGNUM
1298 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1299 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1301 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1302 && (REGNO (dest
) != ARG_POINTER_REGNUM
1303 || ! fixed_regs
[REGNO (dest
)])
1305 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1307 if (*pi3dest_killed
)
1310 *pi3dest_killed
= dest
;
1314 else if (GET_CODE (x
) == PARALLEL
)
1318 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1319 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1320 i1_not_in_src
, pi3dest_killed
))
1327 /* Return 1 if X is an arithmetic expression that contains a multiplication
1328 and division. We don't count multiplications by powers of two here. */
1331 contains_muldiv (rtx x
)
1333 switch (GET_CODE (x
))
1335 case MOD
: case DIV
: case UMOD
: case UDIV
:
1339 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1340 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1342 switch (GET_RTX_CLASS (GET_CODE (x
)))
1344 case 'c': case '<': case '2':
1345 return contains_muldiv (XEXP (x
, 0))
1346 || contains_muldiv (XEXP (x
, 1));
1349 return contains_muldiv (XEXP (x
, 0));
1357 /* Determine whether INSN can be used in a combination. Return nonzero if
1358 not. This is used in try_combine to detect early some cases where we
1359 can't perform combinations. */
1362 cant_combine_insn_p (rtx insn
)
1367 /* If this isn't really an insn, we can't do anything.
1368 This can occur when flow deletes an insn that it has merged into an
1369 auto-increment address. */
1370 if (! INSN_P (insn
))
1373 /* Never combine loads and stores involving hard regs that are likely
1374 to be spilled. The register allocator can usually handle such
1375 reg-reg moves by tying. If we allow the combiner to make
1376 substitutions of likely-spilled regs, we may abort in reload.
1377 As an exception, we allow combinations involving fixed regs; these are
1378 not available to the register allocator so there's no risk involved. */
1380 set
= single_set (insn
);
1383 src
= SET_SRC (set
);
1384 dest
= SET_DEST (set
);
1385 if (GET_CODE (src
) == SUBREG
)
1386 src
= SUBREG_REG (src
);
1387 if (GET_CODE (dest
) == SUBREG
)
1388 dest
= SUBREG_REG (dest
);
1389 if (REG_P (src
) && REG_P (dest
)
1390 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1391 && ! fixed_regs
[REGNO (src
)]
1392 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1393 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1394 && ! fixed_regs
[REGNO (dest
)]
1395 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1401 /* Adjust INSN after we made a change to its destination.
1403 Changing the destination can invalidate notes that say something about
1404 the results of the insn and a LOG_LINK pointing to the insn. */
1407 adjust_for_new_dest (rtx insn
)
1411 /* For notes, be conservative and simply remove them. */
1412 loc
= ®_NOTES (insn
);
1415 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1416 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1417 *loc
= XEXP (*loc
, 1);
1419 loc
= &XEXP (*loc
, 1);
1422 /* The new insn will have a destination that was previously the destination
1423 of an insn just above it. Call distribute_links to make a LOG_LINK from
1424 the next use of that destination. */
1425 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1428 /* Try to combine the insns I1 and I2 into I3.
1429 Here I1 and I2 appear earlier than I3.
1430 I1 can be zero; then we combine just I2 into I3.
1432 If we are combining three insns and the resulting insn is not recognized,
1433 try splitting it into two insns. If that happens, I2 and I3 are retained
1434 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1437 Return 0 if the combination does not work. Then nothing is changed.
1438 If we did the combination, return the insn at which combine should
1441 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1442 new direct jump instruction. */
1445 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1447 /* New patterns for I3 and I2, respectively. */
1448 rtx newpat
, newi2pat
= 0;
1449 int substed_i2
= 0, substed_i1
= 0;
1450 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1451 int added_sets_1
, added_sets_2
;
1452 /* Total number of SETs to put into I3. */
1454 /* Nonzero is I2's body now appears in I3. */
1456 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1457 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1458 /* Contains I3 if the destination of I3 is used in its source, which means
1459 that the old life of I3 is being killed. If that usage is placed into
1460 I2 and not in I3, a REG_DEAD note must be made. */
1461 rtx i3dest_killed
= 0;
1462 /* SET_DEST and SET_SRC of I2 and I1. */
1463 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1464 /* PATTERN (I2), or a copy of it in certain cases. */
1466 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1467 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1468 int i1_feeds_i3
= 0;
1469 /* Notes that must be added to REG_NOTES in I3 and I2. */
1470 rtx new_i3_notes
, new_i2_notes
;
1471 /* Notes that we substituted I3 into I2 instead of the normal case. */
1472 int i3_subst_into_i2
= 0;
1473 /* Notes that I1, I2 or I3 is a MULT operation. */
1481 /* Exit early if one of the insns involved can't be used for
1483 if (cant_combine_insn_p (i3
)
1484 || cant_combine_insn_p (i2
)
1485 || (i1
&& cant_combine_insn_p (i1
))
1486 /* We also can't do anything if I3 has a
1487 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1490 /* ??? This gives worse code, and appears to be unnecessary, since no
1491 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1492 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1498 undobuf
.other_insn
= 0;
1500 /* Reset the hard register usage information. */
1501 CLEAR_HARD_REG_SET (newpat_used_regs
);
1503 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1504 code below, set I1 to be the earlier of the two insns. */
1505 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1506 temp
= i1
, i1
= i2
, i2
= temp
;
1508 added_links_insn
= 0;
1510 /* First check for one important special-case that the code below will
1511 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1512 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1513 we may be able to replace that destination with the destination of I3.
1514 This occurs in the common code where we compute both a quotient and
1515 remainder into a structure, in which case we want to do the computation
1516 directly into the structure to avoid register-register copies.
1518 Note that this case handles both multiple sets in I2 and also
1519 cases where I2 has a number of CLOBBER or PARALLELs.
1521 We make very conservative checks below and only try to handle the
1522 most common cases of this. For example, we only handle the case
1523 where I2 and I3 are adjacent to avoid making difficult register
1526 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1527 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1528 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1529 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1530 && GET_CODE (PATTERN (i2
)) == PARALLEL
1531 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1532 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1533 below would need to check what is inside (and reg_overlap_mentioned_p
1534 doesn't support those codes anyway). Don't allow those destinations;
1535 the resulting insn isn't likely to be recognized anyway. */
1536 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1537 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1538 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1539 SET_DEST (PATTERN (i3
)))
1540 && next_real_insn (i2
) == i3
)
1542 rtx p2
= PATTERN (i2
);
1544 /* Make sure that the destination of I3,
1545 which we are going to substitute into one output of I2,
1546 is not used within another output of I2. We must avoid making this:
1547 (parallel [(set (mem (reg 69)) ...)
1548 (set (reg 69) ...)])
1549 which is not well-defined as to order of actions.
1550 (Besides, reload can't handle output reloads for this.)
1552 The problem can also happen if the dest of I3 is a memory ref,
1553 if another dest in I2 is an indirect memory ref. */
1554 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1555 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1556 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1557 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1558 SET_DEST (XVECEXP (p2
, 0, i
))))
1561 if (i
== XVECLEN (p2
, 0))
1562 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1563 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1564 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1565 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1570 subst_low_cuid
= INSN_CUID (i2
);
1572 added_sets_2
= added_sets_1
= 0;
1573 i2dest
= SET_SRC (PATTERN (i3
));
1575 /* Replace the dest in I2 with our dest and make the resulting
1576 insn the new pattern for I3. Then skip to where we
1577 validate the pattern. Everything was set up above. */
1578 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1579 SET_DEST (PATTERN (i3
)));
1582 i3_subst_into_i2
= 1;
1583 goto validate_replacement
;
1587 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1588 one of those words to another constant, merge them by making a new
1591 && (temp
= single_set (i2
)) != 0
1592 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1593 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1594 && GET_CODE (SET_DEST (temp
)) == REG
1595 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1596 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1597 && GET_CODE (PATTERN (i3
)) == SET
1598 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1599 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1600 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1601 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1602 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1604 HOST_WIDE_INT lo
, hi
;
1606 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1607 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1610 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1611 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1614 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1616 /* We don't handle the case of the target word being wider
1617 than a host wide int. */
1618 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1621 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1622 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1623 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1625 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1626 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1627 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1629 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1630 >> (HOST_BITS_PER_WIDE_INT
- 1));
1632 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1633 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1634 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1635 (INTVAL (SET_SRC (PATTERN (i3
)))));
1637 hi
= lo
< 0 ? -1 : 0;
1640 /* We don't handle the case of the higher word not fitting
1641 entirely in either hi or lo. */
1646 subst_low_cuid
= INSN_CUID (i2
);
1647 added_sets_2
= added_sets_1
= 0;
1648 i2dest
= SET_DEST (temp
);
1650 SUBST (SET_SRC (temp
),
1651 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1653 newpat
= PATTERN (i2
);
1654 goto validate_replacement
;
1658 /* If we have no I1 and I2 looks like:
1659 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1661 make up a dummy I1 that is
1664 (set (reg:CC X) (compare:CC Y (const_int 0)))
1666 (We can ignore any trailing CLOBBERs.)
1668 This undoes a previous combination and allows us to match a branch-and-
1671 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1672 && XVECLEN (PATTERN (i2
), 0) >= 2
1673 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1674 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1676 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1677 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1678 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1679 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1680 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1681 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1683 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1684 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1689 /* We make I1 with the same INSN_UID as I2. This gives it
1690 the same INSN_CUID for value tracking. Our fake I1 will
1691 never appear in the insn stream so giving it the same INSN_UID
1692 as I2 will not cause a problem. */
1694 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1695 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1696 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1699 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1700 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1701 SET_DEST (PATTERN (i1
)));
1706 /* Verify that I2 and I1 are valid for combining. */
1707 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1708 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1714 /* Record whether I2DEST is used in I2SRC and similarly for the other
1715 cases. Knowing this will help in register status updating below. */
1716 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1717 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1718 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1720 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1722 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1724 /* Ensure that I3's pattern can be the destination of combines. */
1725 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1726 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1733 /* See if any of the insns is a MULT operation. Unless one is, we will
1734 reject a combination that is, since it must be slower. Be conservative
1736 if (GET_CODE (i2src
) == MULT
1737 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1738 || (GET_CODE (PATTERN (i3
)) == SET
1739 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1742 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1743 We used to do this EXCEPT in one case: I3 has a post-inc in an
1744 output operand. However, that exception can give rise to insns like
1746 which is a famous insn on the PDP-11 where the value of r3 used as the
1747 source was model-dependent. Avoid this sort of thing. */
1750 if (!(GET_CODE (PATTERN (i3
)) == SET
1751 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1752 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1753 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1754 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1755 /* It's not the exception. */
1758 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1759 if (REG_NOTE_KIND (link
) == REG_INC
1760 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1762 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1769 /* See if the SETs in I1 or I2 need to be kept around in the merged
1770 instruction: whenever the value set there is still needed past I3.
1771 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1773 For the SET in I1, we have two cases: If I1 and I2 independently
1774 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1775 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1776 in I1 needs to be kept around unless I1DEST dies or is set in either
1777 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1778 I1DEST. If so, we know I1 feeds into I2. */
1780 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1783 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1784 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1786 /* If the set in I2 needs to be kept around, we must make a copy of
1787 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1788 PATTERN (I2), we are only substituting for the original I1DEST, not into
1789 an already-substituted copy. This also prevents making self-referential
1790 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1793 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1794 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1798 i2pat
= copy_rtx (i2pat
);
1802 /* Substitute in the latest insn for the regs set by the earlier ones. */
1804 maxreg
= max_reg_num ();
1808 /* It is possible that the source of I2 or I1 may be performing an
1809 unneeded operation, such as a ZERO_EXTEND of something that is known
1810 to have the high part zero. Handle that case by letting subst look at
1811 the innermost one of them.
1813 Another way to do this would be to have a function that tries to
1814 simplify a single insn instead of merging two or more insns. We don't
1815 do this because of the potential of infinite loops and because
1816 of the potential extra memory required. However, doing it the way
1817 we are is a bit of a kludge and doesn't catch all cases.
1819 But only do this if -fexpensive-optimizations since it slows things down
1820 and doesn't usually win. */
1822 if (flag_expensive_optimizations
)
1824 /* Pass pc_rtx so no substitutions are done, just simplifications.
1825 The cases that we are interested in here do not involve the few
1826 cases were is_replaced is checked. */
1829 subst_low_cuid
= INSN_CUID (i1
);
1830 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1834 subst_low_cuid
= INSN_CUID (i2
);
1835 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1840 /* Many machines that don't use CC0 have insns that can both perform an
1841 arithmetic operation and set the condition code. These operations will
1842 be represented as a PARALLEL with the first element of the vector
1843 being a COMPARE of an arithmetic operation with the constant zero.
1844 The second element of the vector will set some pseudo to the result
1845 of the same arithmetic operation. If we simplify the COMPARE, we won't
1846 match such a pattern and so will generate an extra insn. Here we test
1847 for this case, where both the comparison and the operation result are
1848 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1849 I2SRC. Later we will make the PARALLEL that contains I2. */
1851 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1852 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1853 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1854 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1856 #ifdef SELECT_CC_MODE
1858 enum machine_mode compare_mode
;
1861 newpat
= PATTERN (i3
);
1862 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1866 #ifdef SELECT_CC_MODE
1867 /* See if a COMPARE with the operand we substituted in should be done
1868 with the mode that is currently being used. If not, do the same
1869 processing we do in `subst' for a SET; namely, if the destination
1870 is used only once, try to replace it with a register of the proper
1871 mode and also replace the COMPARE. */
1872 if (undobuf
.other_insn
== 0
1873 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1874 &undobuf
.other_insn
))
1875 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1877 != GET_MODE (SET_DEST (newpat
))))
1879 unsigned int regno
= REGNO (SET_DEST (newpat
));
1880 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1882 if (regno
< FIRST_PSEUDO_REGISTER
1883 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1884 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1886 if (regno
>= FIRST_PSEUDO_REGISTER
)
1887 SUBST (regno_reg_rtx
[regno
], new_dest
);
1889 SUBST (SET_DEST (newpat
), new_dest
);
1890 SUBST (XEXP (*cc_use
, 0), new_dest
);
1891 SUBST (SET_SRC (newpat
),
1892 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1895 undobuf
.other_insn
= 0;
1902 n_occurrences
= 0; /* `subst' counts here */
1904 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1905 need to make a unique copy of I2SRC each time we substitute it
1906 to avoid self-referential rtl. */
1908 subst_low_cuid
= INSN_CUID (i2
);
1909 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1910 ! i1_feeds_i3
&& i1dest_in_i1src
);
1913 /* Record whether i2's body now appears within i3's body. */
1914 i2_is_used
= n_occurrences
;
1917 /* If we already got a failure, don't try to do more. Otherwise,
1918 try to substitute in I1 if we have it. */
1920 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1922 /* Before we can do this substitution, we must redo the test done
1923 above (see detailed comments there) that ensures that I1DEST
1924 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1926 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1934 subst_low_cuid
= INSN_CUID (i1
);
1935 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1939 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1940 to count all the ways that I2SRC and I1SRC can be used. */
1941 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1942 && i2_is_used
+ added_sets_2
> 1)
1943 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1944 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1946 /* Fail if we tried to make a new register (we used to abort, but there's
1947 really no reason to). */
1948 || max_reg_num () != maxreg
1949 /* Fail if we couldn't do something and have a CLOBBER. */
1950 || GET_CODE (newpat
) == CLOBBER
1951 /* Fail if this new pattern is a MULT and we didn't have one before
1952 at the outer level. */
1953 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1960 /* If the actions of the earlier insns must be kept
1961 in addition to substituting them into the latest one,
1962 we must make a new PARALLEL for the latest insn
1963 to hold additional the SETs. */
1965 if (added_sets_1
|| added_sets_2
)
1969 if (GET_CODE (newpat
) == PARALLEL
)
1971 rtvec old
= XVEC (newpat
, 0);
1972 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1973 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1974 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1975 sizeof (old
->elem
[0]) * old
->num_elem
);
1980 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1981 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1982 XVECEXP (newpat
, 0, 0) = old
;
1986 XVECEXP (newpat
, 0, --total_sets
)
1987 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1988 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1992 /* If there is no I1, use I2's body as is. We used to also not do
1993 the subst call below if I2 was substituted into I3,
1994 but that could lose a simplification. */
1996 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1998 /* See comment where i2pat is assigned. */
1999 XVECEXP (newpat
, 0, --total_sets
)
2000 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2004 /* We come here when we are replacing a destination in I2 with the
2005 destination of I3. */
2006 validate_replacement
:
2008 /* Note which hard regs this insn has as inputs. */
2009 mark_used_regs_combine (newpat
);
2011 /* Is the result of combination a valid instruction? */
2012 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2014 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2015 the second SET's destination is a register that is unused. In that case,
2016 we just need the first SET. This can occur when simplifying a divmod
2017 insn. We *must* test for this case here because the code below that
2018 splits two independent SETs doesn't handle this case correctly when it
2019 updates the register status. Also check the case where the first
2020 SET's destination is unused. That would not cause incorrect code, but
2021 does cause an unneeded insn to remain. */
2023 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2024 && XVECLEN (newpat
, 0) == 2
2025 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2026 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2027 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2028 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2029 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2030 && asm_noperands (newpat
) < 0)
2032 newpat
= XVECEXP (newpat
, 0, 0);
2033 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2036 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2037 && XVECLEN (newpat
, 0) == 2
2038 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2039 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2040 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2041 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2042 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2043 && asm_noperands (newpat
) < 0)
2045 newpat
= XVECEXP (newpat
, 0, 1);
2046 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2048 if (insn_code_number
>= 0)
2050 /* If we will be able to accept this, we have made a change to the
2051 destination of I3. This requires us to do a few adjustments. */
2052 PATTERN (i3
) = newpat
;
2053 adjust_for_new_dest (i3
);
2057 /* If we were combining three insns and the result is a simple SET
2058 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2059 insns. There are two ways to do this. It can be split using a
2060 machine-specific method (like when you have an addition of a large
2061 constant) or by combine in the function find_split_point. */
2063 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2064 && asm_noperands (newpat
) < 0)
2066 rtx m_split
, *split
;
2067 rtx ni2dest
= i2dest
;
2069 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2070 use I2DEST as a scratch register will help. In the latter case,
2071 convert I2DEST to the mode of the source of NEWPAT if we can. */
2073 m_split
= split_insns (newpat
, i3
);
2075 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2076 inputs of NEWPAT. */
2078 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2079 possible to try that as a scratch reg. This would require adding
2080 more code to make it work though. */
2082 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2084 /* If I2DEST is a hard register or the only use of a pseudo,
2085 we can change its mode. */
2086 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2087 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2088 && GET_CODE (i2dest
) == REG
2089 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2090 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2091 && ! REG_USERVAR_P (i2dest
))))
2092 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2095 m_split
= split_insns (gen_rtx_PARALLEL
2097 gen_rtvec (2, newpat
,
2098 gen_rtx_CLOBBER (VOIDmode
,
2101 /* If the split with the mode-changed register didn't work, try
2102 the original register. */
2103 if (! m_split
&& ni2dest
!= i2dest
)
2106 m_split
= split_insns (gen_rtx_PARALLEL
2108 gen_rtvec (2, newpat
,
2109 gen_rtx_CLOBBER (VOIDmode
,
2115 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2117 m_split
= PATTERN (m_split
);
2118 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2119 if (insn_code_number
>= 0)
2122 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2123 && (next_real_insn (i2
) == i3
2124 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2127 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2128 newi2pat
= PATTERN (m_split
);
2130 i3set
= single_set (NEXT_INSN (m_split
));
2131 i2set
= single_set (m_split
);
2133 /* In case we changed the mode of I2DEST, replace it in the
2134 pseudo-register table here. We can't do it above in case this
2135 code doesn't get executed and we do a split the other way. */
2137 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2138 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2140 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2142 /* If I2 or I3 has multiple SETs, we won't know how to track
2143 register status, so don't use these insns. If I2's destination
2144 is used between I2 and I3, we also can't use these insns. */
2146 if (i2_code_number
>= 0 && i2set
&& i3set
2147 && (next_real_insn (i2
) == i3
2148 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2149 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2151 if (insn_code_number
>= 0)
2154 /* It is possible that both insns now set the destination of I3.
2155 If so, we must show an extra use of it. */
2157 if (insn_code_number
>= 0)
2159 rtx new_i3_dest
= SET_DEST (i3set
);
2160 rtx new_i2_dest
= SET_DEST (i2set
);
2162 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2163 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2164 || GET_CODE (new_i3_dest
) == SUBREG
)
2165 new_i3_dest
= XEXP (new_i3_dest
, 0);
2167 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2168 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2169 || GET_CODE (new_i2_dest
) == SUBREG
)
2170 new_i2_dest
= XEXP (new_i2_dest
, 0);
2172 if (GET_CODE (new_i3_dest
) == REG
2173 && GET_CODE (new_i2_dest
) == REG
2174 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2175 REG_N_SETS (REGNO (new_i2_dest
))++;
2179 /* If we can split it and use I2DEST, go ahead and see if that
2180 helps things be recognized. Verify that none of the registers
2181 are set between I2 and I3. */
2182 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2184 && GET_CODE (i2dest
) == REG
2186 /* We need I2DEST in the proper mode. If it is a hard register
2187 or the only use of a pseudo, we can change its mode. */
2188 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2189 || GET_MODE (*split
) == VOIDmode
2190 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2191 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2192 && ! REG_USERVAR_P (i2dest
)))
2193 && (next_real_insn (i2
) == i3
2194 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2195 /* We can't overwrite I2DEST if its value is still used by
2197 && ! reg_referenced_p (i2dest
, newpat
))
2199 rtx newdest
= i2dest
;
2200 enum rtx_code split_code
= GET_CODE (*split
);
2201 enum machine_mode split_mode
= GET_MODE (*split
);
2203 /* Get NEWDEST as a register in the proper mode. We have already
2204 validated that we can do this. */
2205 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2207 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2209 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2210 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2213 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2214 an ASHIFT. This can occur if it was inside a PLUS and hence
2215 appeared to be a memory address. This is a kludge. */
2216 if (split_code
== MULT
2217 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2218 && INTVAL (XEXP (*split
, 1)) > 0
2219 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2221 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2222 XEXP (*split
, 0), GEN_INT (i
)));
2223 /* Update split_code because we may not have a multiply
2225 split_code
= GET_CODE (*split
);
2228 #ifdef INSN_SCHEDULING
2229 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2230 be written as a ZERO_EXTEND. */
2231 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2233 #ifdef LOAD_EXTEND_OP
2234 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2235 what it really is. */
2236 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2238 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2239 SUBREG_REG (*split
)));
2242 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2243 SUBREG_REG (*split
)));
2247 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2248 SUBST (*split
, newdest
);
2249 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2251 /* If the split point was a MULT and we didn't have one before,
2252 don't use one now. */
2253 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2254 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2258 /* Check for a case where we loaded from memory in a narrow mode and
2259 then sign extended it, but we need both registers. In that case,
2260 we have a PARALLEL with both loads from the same memory location.
2261 We can split this into a load from memory followed by a register-register
2262 copy. This saves at least one insn, more if register allocation can
2265 We cannot do this if the destination of the first assignment is a
2266 condition code register or cc0. We eliminate this case by making sure
2267 the SET_DEST and SET_SRC have the same mode.
2269 We cannot do this if the destination of the second assignment is
2270 a register that we have already assumed is zero-extended. Similarly
2271 for a SUBREG of such a register. */
2273 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2274 && GET_CODE (newpat
) == PARALLEL
2275 && XVECLEN (newpat
, 0) == 2
2276 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2277 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2278 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2279 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2280 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2281 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2282 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2283 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2285 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2286 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2287 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2288 (GET_CODE (temp
) == REG
2289 && reg_nonzero_bits
[REGNO (temp
)] != 0
2290 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2291 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2292 && (reg_nonzero_bits
[REGNO (temp
)]
2293 != GET_MODE_MASK (word_mode
))))
2294 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2295 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2296 (GET_CODE (temp
) == REG
2297 && reg_nonzero_bits
[REGNO (temp
)] != 0
2298 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2299 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2300 && (reg_nonzero_bits
[REGNO (temp
)]
2301 != GET_MODE_MASK (word_mode
)))))
2302 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2303 SET_SRC (XVECEXP (newpat
, 0, 1)))
2304 && ! find_reg_note (i3
, REG_UNUSED
,
2305 SET_DEST (XVECEXP (newpat
, 0, 0))))
2309 newi2pat
= XVECEXP (newpat
, 0, 0);
2310 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2311 newpat
= XVECEXP (newpat
, 0, 1);
2312 SUBST (SET_SRC (newpat
),
2313 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2314 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2316 if (i2_code_number
>= 0)
2317 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2319 if (insn_code_number
>= 0)
2324 /* If we will be able to accept this, we have made a change to the
2325 destination of I3. This requires us to do a few adjustments. */
2326 PATTERN (i3
) = newpat
;
2327 adjust_for_new_dest (i3
);
2329 /* I3 now uses what used to be its destination and which is
2330 now I2's destination. That means we need a LOG_LINK from
2331 I3 to I2. But we used to have one, so we still will.
2333 However, some later insn might be using I2's dest and have
2334 a LOG_LINK pointing at I3. We must remove this link.
2335 The simplest way to remove the link is to point it at I1,
2336 which we know will be a NOTE. */
2338 for (insn
= NEXT_INSN (i3
);
2339 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2340 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2341 insn
= NEXT_INSN (insn
))
2343 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2345 for (link
= LOG_LINKS (insn
); link
;
2346 link
= XEXP (link
, 1))
2347 if (XEXP (link
, 0) == i3
)
2348 XEXP (link
, 0) = i1
;
2356 /* Similarly, check for a case where we have a PARALLEL of two independent
2357 SETs but we started with three insns. In this case, we can do the sets
2358 as two separate insns. This case occurs when some SET allows two
2359 other insns to combine, but the destination of that SET is still live. */
2361 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2362 && GET_CODE (newpat
) == PARALLEL
2363 && XVECLEN (newpat
, 0) == 2
2364 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2365 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2366 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2367 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2368 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2369 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2370 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2372 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2373 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2374 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2375 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2376 XVECEXP (newpat
, 0, 0))
2377 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2378 XVECEXP (newpat
, 0, 1))
2379 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2380 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2382 /* Normally, it doesn't matter which of the two is done first,
2383 but it does if one references cc0. In that case, it has to
2386 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2388 newi2pat
= XVECEXP (newpat
, 0, 0);
2389 newpat
= XVECEXP (newpat
, 0, 1);
2394 newi2pat
= XVECEXP (newpat
, 0, 1);
2395 newpat
= XVECEXP (newpat
, 0, 0);
2398 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2400 if (i2_code_number
>= 0)
2401 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2404 /* If it still isn't recognized, fail and change things back the way they
2406 if ((insn_code_number
< 0
2407 /* Is the result a reasonable ASM_OPERANDS? */
2408 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2414 /* If we had to change another insn, make sure it is valid also. */
2415 if (undobuf
.other_insn
)
2417 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2418 rtx new_other_notes
;
2421 CLEAR_HARD_REG_SET (newpat_used_regs
);
2423 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2426 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2432 PATTERN (undobuf
.other_insn
) = other_pat
;
2434 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2435 are still valid. Then add any non-duplicate notes added by
2436 recog_for_combine. */
2437 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2439 next
= XEXP (note
, 1);
2441 if (REG_NOTE_KIND (note
) == REG_UNUSED
2442 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2444 if (GET_CODE (XEXP (note
, 0)) == REG
)
2445 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2447 remove_note (undobuf
.other_insn
, note
);
2451 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2452 if (GET_CODE (XEXP (note
, 0)) == REG
)
2453 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2455 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2456 undobuf
.other_insn
, NULL_RTX
);
2459 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2460 they are adjacent to each other or not. */
2462 rtx p
= prev_nonnote_insn (i3
);
2463 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2464 && sets_cc0_p (newi2pat
))
2472 /* We now know that we can do this combination. Merge the insns and
2473 update the status of registers and LOG_LINKS. */
2476 rtx i3notes
, i2notes
, i1notes
= 0;
2477 rtx i3links
, i2links
, i1links
= 0;
2481 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2483 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2484 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2486 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2488 /* Ensure that we do not have something that should not be shared but
2489 occurs multiple times in the new insns. Check this by first
2490 resetting all the `used' flags and then copying anything is shared. */
2492 reset_used_flags (i3notes
);
2493 reset_used_flags (i2notes
);
2494 reset_used_flags (i1notes
);
2495 reset_used_flags (newpat
);
2496 reset_used_flags (newi2pat
);
2497 if (undobuf
.other_insn
)
2498 reset_used_flags (PATTERN (undobuf
.other_insn
));
2500 i3notes
= copy_rtx_if_shared (i3notes
);
2501 i2notes
= copy_rtx_if_shared (i2notes
);
2502 i1notes
= copy_rtx_if_shared (i1notes
);
2503 newpat
= copy_rtx_if_shared (newpat
);
2504 newi2pat
= copy_rtx_if_shared (newi2pat
);
2505 if (undobuf
.other_insn
)
2506 reset_used_flags (PATTERN (undobuf
.other_insn
));
2508 INSN_CODE (i3
) = insn_code_number
;
2509 PATTERN (i3
) = newpat
;
2511 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2513 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2515 reset_used_flags (call_usage
);
2516 call_usage
= copy_rtx (call_usage
);
2519 replace_rtx (call_usage
, i2dest
, i2src
);
2522 replace_rtx (call_usage
, i1dest
, i1src
);
2524 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2527 if (undobuf
.other_insn
)
2528 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2530 /* We had one special case above where I2 had more than one set and
2531 we replaced a destination of one of those sets with the destination
2532 of I3. In that case, we have to update LOG_LINKS of insns later
2533 in this basic block. Note that this (expensive) case is rare.
2535 Also, in this case, we must pretend that all REG_NOTEs for I2
2536 actually came from I3, so that REG_UNUSED notes from I2 will be
2537 properly handled. */
2539 if (i3_subst_into_i2
)
2541 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2542 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2543 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2544 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2545 && ! find_reg_note (i2
, REG_UNUSED
,
2546 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2547 for (temp
= NEXT_INSN (i2
);
2548 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2549 || BB_HEAD (this_basic_block
) != temp
);
2550 temp
= NEXT_INSN (temp
))
2551 if (temp
!= i3
&& INSN_P (temp
))
2552 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2553 if (XEXP (link
, 0) == i2
)
2554 XEXP (link
, 0) = i3
;
2559 while (XEXP (link
, 1))
2560 link
= XEXP (link
, 1);
2561 XEXP (link
, 1) = i2notes
;
2575 INSN_CODE (i2
) = i2_code_number
;
2576 PATTERN (i2
) = newi2pat
;
2580 PUT_CODE (i2
, NOTE
);
2581 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2582 NOTE_SOURCE_FILE (i2
) = 0;
2589 PUT_CODE (i1
, NOTE
);
2590 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2591 NOTE_SOURCE_FILE (i1
) = 0;
2594 /* Get death notes for everything that is now used in either I3 or
2595 I2 and used to die in a previous insn. If we built two new
2596 patterns, move from I1 to I2 then I2 to I3 so that we get the
2597 proper movement on registers that I2 modifies. */
2601 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2602 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2605 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2608 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2610 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2612 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2614 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2616 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2618 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2619 know these are REG_UNUSED and want them to go to the desired insn,
2620 so we always pass it as i3. We have not counted the notes in
2621 reg_n_deaths yet, so we need to do so now. */
2623 if (newi2pat
&& new_i2_notes
)
2625 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2626 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2627 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2629 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2634 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2635 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2636 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2638 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2641 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2642 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2643 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2644 in that case, it might delete I2. Similarly for I2 and I1.
2645 Show an additional death due to the REG_DEAD note we make here. If
2646 we discard it in distribute_notes, we will decrement it again. */
2650 if (GET_CODE (i3dest_killed
) == REG
)
2651 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2653 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2654 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2656 NULL_RTX
, i2
, NULL_RTX
);
2658 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2660 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2663 if (i2dest_in_i2src
)
2665 if (GET_CODE (i2dest
) == REG
)
2666 REG_N_DEATHS (REGNO (i2dest
))++;
2668 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2669 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2670 NULL_RTX
, i2
, NULL_RTX
);
2672 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2673 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2676 if (i1dest_in_i1src
)
2678 if (GET_CODE (i1dest
) == REG
)
2679 REG_N_DEATHS (REGNO (i1dest
))++;
2681 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2682 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2683 NULL_RTX
, i2
, NULL_RTX
);
2685 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2686 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2689 distribute_links (i3links
);
2690 distribute_links (i2links
);
2691 distribute_links (i1links
);
2693 if (GET_CODE (i2dest
) == REG
)
2696 rtx i2_insn
= 0, i2_val
= 0, set
;
2698 /* The insn that used to set this register doesn't exist, and
2699 this life of the register may not exist either. See if one of
2700 I3's links points to an insn that sets I2DEST. If it does,
2701 that is now the last known value for I2DEST. If we don't update
2702 this and I2 set the register to a value that depended on its old
2703 contents, we will get confused. If this insn is used, thing
2704 will be set correctly in combine_instructions. */
2706 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2707 if ((set
= single_set (XEXP (link
, 0))) != 0
2708 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2709 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2711 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2713 /* If the reg formerly set in I2 died only once and that was in I3,
2714 zero its use count so it won't make `reload' do any work. */
2716 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2717 && ! i2dest_in_i2src
)
2719 regno
= REGNO (i2dest
);
2720 REG_N_SETS (regno
)--;
2724 if (i1
&& GET_CODE (i1dest
) == REG
)
2727 rtx i1_insn
= 0, i1_val
= 0, set
;
2729 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2730 if ((set
= single_set (XEXP (link
, 0))) != 0
2731 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2732 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2734 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2736 regno
= REGNO (i1dest
);
2737 if (! added_sets_1
&& ! i1dest_in_i1src
)
2738 REG_N_SETS (regno
)--;
2741 /* Update reg_nonzero_bits et al for any changes that may have been made
2742 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2743 important. Because newi2pat can affect nonzero_bits of newpat */
2745 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2746 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2748 /* Set new_direct_jump_p if a new return or simple jump instruction
2751 If I3 is now an unconditional jump, ensure that it has a
2752 BARRIER following it since it may have initially been a
2753 conditional jump. It may also be the last nonnote insn. */
2755 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2757 *new_direct_jump_p
= 1;
2758 mark_jump_label (PATTERN (i3
), i3
, 0);
2760 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2761 || GET_CODE (temp
) != BARRIER
)
2762 emit_barrier_after (i3
);
2765 if (undobuf
.other_insn
!= NULL_RTX
2766 && (returnjump_p (undobuf
.other_insn
)
2767 || any_uncondjump_p (undobuf
.other_insn
)))
2769 *new_direct_jump_p
= 1;
2771 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2772 || GET_CODE (temp
) != BARRIER
)
2773 emit_barrier_after (undobuf
.other_insn
);
2776 /* An NOOP jump does not need barrier, but it does need cleaning up
2778 if (GET_CODE (newpat
) == SET
2779 && SET_SRC (newpat
) == pc_rtx
2780 && SET_DEST (newpat
) == pc_rtx
)
2781 *new_direct_jump_p
= 1;
2784 combine_successes
++;
2787 if (added_links_insn
2788 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2789 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2790 return added_links_insn
;
2792 return newi2pat
? i2
: i3
;
2795 /* Undo all the modifications recorded in undobuf. */
2800 struct undo
*undo
, *next
;
2802 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2806 *undo
->where
.i
= undo
->old_contents
.i
;
2808 *undo
->where
.r
= undo
->old_contents
.r
;
2810 undo
->next
= undobuf
.frees
;
2811 undobuf
.frees
= undo
;
2817 /* We've committed to accepting the changes we made. Move all
2818 of the undos to the free list. */
2823 struct undo
*undo
, *next
;
2825 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2828 undo
->next
= undobuf
.frees
;
2829 undobuf
.frees
= undo
;
2835 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2836 where we have an arithmetic expression and return that point. LOC will
2839 try_combine will call this function to see if an insn can be split into
2843 find_split_point (rtx
*loc
, rtx insn
)
2846 enum rtx_code code
= GET_CODE (x
);
2848 unsigned HOST_WIDE_INT len
= 0;
2849 HOST_WIDE_INT pos
= 0;
2851 rtx inner
= NULL_RTX
;
2853 /* First special-case some codes. */
2857 #ifdef INSN_SCHEDULING
2858 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2860 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2863 return find_split_point (&SUBREG_REG (x
), insn
);
2867 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2868 using LO_SUM and HIGH. */
2869 if (GET_CODE (XEXP (x
, 0)) == CONST
2870 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2873 gen_rtx_LO_SUM (Pmode
,
2874 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2876 return &XEXP (XEXP (x
, 0), 0);
2880 /* If we have a PLUS whose second operand is a constant and the
2881 address is not valid, perhaps will can split it up using
2882 the machine-specific way to split large constants. We use
2883 the first pseudo-reg (one of the virtual regs) as a placeholder;
2884 it will not remain in the result. */
2885 if (GET_CODE (XEXP (x
, 0)) == PLUS
2886 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2887 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2889 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2890 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2893 /* This should have produced two insns, each of which sets our
2894 placeholder. If the source of the second is a valid address,
2895 we can make put both sources together and make a split point
2899 && NEXT_INSN (seq
) != NULL_RTX
2900 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2901 && GET_CODE (seq
) == INSN
2902 && GET_CODE (PATTERN (seq
)) == SET
2903 && SET_DEST (PATTERN (seq
)) == reg
2904 && ! reg_mentioned_p (reg
,
2905 SET_SRC (PATTERN (seq
)))
2906 && GET_CODE (NEXT_INSN (seq
)) == INSN
2907 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2908 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2909 && memory_address_p (GET_MODE (x
),
2910 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2912 rtx src1
= SET_SRC (PATTERN (seq
));
2913 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2915 /* Replace the placeholder in SRC2 with SRC1. If we can
2916 find where in SRC2 it was placed, that can become our
2917 split point and we can replace this address with SRC2.
2918 Just try two obvious places. */
2920 src2
= replace_rtx (src2
, reg
, src1
);
2922 if (XEXP (src2
, 0) == src1
)
2923 split
= &XEXP (src2
, 0);
2924 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2925 && XEXP (XEXP (src2
, 0), 0) == src1
)
2926 split
= &XEXP (XEXP (src2
, 0), 0);
2930 SUBST (XEXP (x
, 0), src2
);
2935 /* If that didn't work, perhaps the first operand is complex and
2936 needs to be computed separately, so make a split point there.
2937 This will occur on machines that just support REG + CONST
2938 and have a constant moved through some previous computation. */
2940 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2941 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2942 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2944 return &XEXP (XEXP (x
, 0), 0);
2950 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2951 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2952 we need to put the operand into a register. So split at that
2955 if (SET_DEST (x
) == cc0_rtx
2956 && GET_CODE (SET_SRC (x
)) != COMPARE
2957 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2958 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2959 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2960 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2961 return &SET_SRC (x
);
2964 /* See if we can split SET_SRC as it stands. */
2965 split
= find_split_point (&SET_SRC (x
), insn
);
2966 if (split
&& split
!= &SET_SRC (x
))
2969 /* See if we can split SET_DEST as it stands. */
2970 split
= find_split_point (&SET_DEST (x
), insn
);
2971 if (split
&& split
!= &SET_DEST (x
))
2974 /* See if this is a bitfield assignment with everything constant. If
2975 so, this is an IOR of an AND, so split it into that. */
2976 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2977 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2978 <= HOST_BITS_PER_WIDE_INT
)
2979 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2980 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2981 && GET_CODE (SET_SRC (x
)) == CONST_INT
2982 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2983 + INTVAL (XEXP (SET_DEST (x
), 2)))
2984 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2985 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2987 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2988 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2989 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2990 rtx dest
= XEXP (SET_DEST (x
), 0);
2991 enum machine_mode mode
= GET_MODE (dest
);
2992 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2994 if (BITS_BIG_ENDIAN
)
2995 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2999 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3002 gen_binary (IOR
, mode
,
3003 gen_binary (AND
, mode
, dest
,
3004 gen_int_mode (~(mask
<< pos
),
3006 GEN_INT (src
<< pos
)));
3008 SUBST (SET_DEST (x
), dest
);
3010 split
= find_split_point (&SET_SRC (x
), insn
);
3011 if (split
&& split
!= &SET_SRC (x
))
3015 /* Otherwise, see if this is an operation that we can split into two.
3016 If so, try to split that. */
3017 code
= GET_CODE (SET_SRC (x
));
3022 /* If we are AND'ing with a large constant that is only a single
3023 bit and the result is only being used in a context where we
3024 need to know if it is zero or nonzero, replace it with a bit
3025 extraction. This will avoid the large constant, which might
3026 have taken more than one insn to make. If the constant were
3027 not a valid argument to the AND but took only one insn to make,
3028 this is no worse, but if it took more than one insn, it will
3031 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3032 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3033 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3034 && GET_CODE (SET_DEST (x
)) == REG
3035 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3036 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3037 && XEXP (*split
, 0) == SET_DEST (x
)
3038 && XEXP (*split
, 1) == const0_rtx
)
3040 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3041 XEXP (SET_SRC (x
), 0),
3042 pos
, NULL_RTX
, 1, 1, 0, 0);
3043 if (extraction
!= 0)
3045 SUBST (SET_SRC (x
), extraction
);
3046 return find_split_point (loc
, insn
);
3052 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3053 is known to be on, this can be converted into a NEG of a shift. */
3054 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3055 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3056 && 1 <= (pos
= exact_log2
3057 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3058 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3060 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3064 gen_rtx_LSHIFTRT (mode
,
3065 XEXP (SET_SRC (x
), 0),
3068 split
= find_split_point (&SET_SRC (x
), insn
);
3069 if (split
&& split
!= &SET_SRC (x
))
3075 inner
= XEXP (SET_SRC (x
), 0);
3077 /* We can't optimize if either mode is a partial integer
3078 mode as we don't know how many bits are significant
3080 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3081 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3085 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3091 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3092 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3094 inner
= XEXP (SET_SRC (x
), 0);
3095 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3096 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3098 if (BITS_BIG_ENDIAN
)
3099 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3100 unsignedp
= (code
== ZERO_EXTRACT
);
3108 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3110 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3112 /* For unsigned, we have a choice of a shift followed by an
3113 AND or two shifts. Use two shifts for field sizes where the
3114 constant might be too large. We assume here that we can
3115 always at least get 8-bit constants in an AND insn, which is
3116 true for every current RISC. */
3118 if (unsignedp
&& len
<= 8)
3123 (mode
, gen_lowpart_for_combine (mode
, inner
),
3125 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3127 split
= find_split_point (&SET_SRC (x
), insn
);
3128 if (split
&& split
!= &SET_SRC (x
))
3135 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3136 gen_rtx_ASHIFT (mode
,
3137 gen_lowpart_for_combine (mode
, inner
),
3138 GEN_INT (GET_MODE_BITSIZE (mode
)
3140 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3142 split
= find_split_point (&SET_SRC (x
), insn
);
3143 if (split
&& split
!= &SET_SRC (x
))
3148 /* See if this is a simple operation with a constant as the second
3149 operand. It might be that this constant is out of range and hence
3150 could be used as a split point. */
3151 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3152 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3153 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3154 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3155 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3156 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3157 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3159 return &XEXP (SET_SRC (x
), 1);
3161 /* Finally, see if this is a simple operation with its first operand
3162 not in a register. The operation might require this operand in a
3163 register, so return it as a split point. We can always do this
3164 because if the first operand were another operation, we would have
3165 already found it as a split point. */
3166 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3167 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3168 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3169 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3170 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3171 return &XEXP (SET_SRC (x
), 0);
3177 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3178 it is better to write this as (not (ior A B)) so we can split it.
3179 Similarly for IOR. */
3180 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3183 gen_rtx_NOT (GET_MODE (x
),
3184 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3186 XEXP (XEXP (x
, 0), 0),
3187 XEXP (XEXP (x
, 1), 0))));
3188 return find_split_point (loc
, insn
);
3191 /* Many RISC machines have a large set of logical insns. If the
3192 second operand is a NOT, put it first so we will try to split the
3193 other operand first. */
3194 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3196 rtx tem
= XEXP (x
, 0);
3197 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3198 SUBST (XEXP (x
, 1), tem
);
3206 /* Otherwise, select our actions depending on our rtx class. */
3207 switch (GET_RTX_CLASS (code
))
3209 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3211 split
= find_split_point (&XEXP (x
, 2), insn
);
3214 /* ... fall through ... */
3218 split
= find_split_point (&XEXP (x
, 1), insn
);
3221 /* ... fall through ... */
3223 /* Some machines have (and (shift ...) ...) insns. If X is not
3224 an AND, but XEXP (X, 0) is, use it as our split point. */
3225 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3226 return &XEXP (x
, 0);
3228 split
= find_split_point (&XEXP (x
, 0), insn
);
3234 /* Otherwise, we don't have a split point. */
3238 /* Throughout X, replace FROM with TO, and return the result.
3239 The result is TO if X is FROM;
3240 otherwise the result is X, but its contents may have been modified.
3241 If they were modified, a record was made in undobuf so that
3242 undo_all will (among other things) return X to its original state.
3244 If the number of changes necessary is too much to record to undo,
3245 the excess changes are not made, so the result is invalid.
3246 The changes already made can still be undone.
3247 undobuf.num_undo is incremented for such changes, so by testing that
3248 the caller can tell whether the result is valid.
3250 `n_occurrences' is incremented each time FROM is replaced.
3252 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3254 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3255 by copying if `n_occurrences' is nonzero. */
3258 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3260 enum rtx_code code
= GET_CODE (x
);
3261 enum machine_mode op0_mode
= VOIDmode
;
3266 /* Two expressions are equal if they are identical copies of a shared
3267 RTX or if they are both registers with the same register number
3270 #define COMBINE_RTX_EQUAL_P(X,Y) \
3272 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3273 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3275 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3278 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3281 /* If X and FROM are the same register but different modes, they will
3282 not have been seen as equal above. However, flow.c will make a
3283 LOG_LINKS entry for that case. If we do nothing, we will try to
3284 rerecognize our original insn and, when it succeeds, we will
3285 delete the feeding insn, which is incorrect.
3287 So force this insn not to match in this (rare) case. */
3288 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3289 && REGNO (x
) == REGNO (from
))
3290 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3292 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3293 of which may contain things that can be combined. */
3294 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3297 /* It is possible to have a subexpression appear twice in the insn.
3298 Suppose that FROM is a register that appears within TO.
3299 Then, after that subexpression has been scanned once by `subst',
3300 the second time it is scanned, TO may be found. If we were
3301 to scan TO here, we would find FROM within it and create a
3302 self-referent rtl structure which is completely wrong. */
3303 if (COMBINE_RTX_EQUAL_P (x
, to
))
3306 /* Parallel asm_operands need special attention because all of the
3307 inputs are shared across the arms. Furthermore, unsharing the
3308 rtl results in recognition failures. Failure to handle this case
3309 specially can result in circular rtl.
3311 Solve this by doing a normal pass across the first entry of the
3312 parallel, and only processing the SET_DESTs of the subsequent
3315 if (code
== PARALLEL
3316 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3317 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3319 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3321 /* If this substitution failed, this whole thing fails. */
3322 if (GET_CODE (new) == CLOBBER
3323 && XEXP (new, 0) == const0_rtx
)
3326 SUBST (XVECEXP (x
, 0, 0), new);
3328 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3330 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3332 if (GET_CODE (dest
) != REG
3333 && GET_CODE (dest
) != CC0
3334 && GET_CODE (dest
) != PC
)
3336 new = subst (dest
, from
, to
, 0, unique_copy
);
3338 /* If this substitution failed, this whole thing fails. */
3339 if (GET_CODE (new) == CLOBBER
3340 && XEXP (new, 0) == const0_rtx
)
3343 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3349 len
= GET_RTX_LENGTH (code
);
3350 fmt
= GET_RTX_FORMAT (code
);
3352 /* We don't need to process a SET_DEST that is a register, CC0,
3353 or PC, so set up to skip this common case. All other cases
3354 where we want to suppress replacing something inside a
3355 SET_SRC are handled via the IN_DEST operand. */
3357 && (GET_CODE (SET_DEST (x
)) == REG
3358 || GET_CODE (SET_DEST (x
)) == CC0
3359 || GET_CODE (SET_DEST (x
)) == PC
))
3362 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3365 op0_mode
= GET_MODE (XEXP (x
, 0));
3367 for (i
= 0; i
< len
; i
++)
3372 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3374 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3376 new = (unique_copy
&& n_occurrences
3377 ? copy_rtx (to
) : to
);
3382 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3385 /* If this substitution failed, this whole thing
3387 if (GET_CODE (new) == CLOBBER
3388 && XEXP (new, 0) == const0_rtx
)
3392 SUBST (XVECEXP (x
, i
, j
), new);
3395 else if (fmt
[i
] == 'e')
3397 /* If this is a register being set, ignore it. */
3400 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3401 || code
== ZERO_EXTRACT
)
3403 && GET_CODE (new) == REG
)
3406 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3408 /* In general, don't install a subreg involving two
3409 modes not tieable. It can worsen register
3410 allocation, and can even make invalid reload
3411 insns, since the reg inside may need to be copied
3412 from in the outside mode, and that may be invalid
3413 if it is an fp reg copied in integer mode.
3415 We allow two exceptions to this: It is valid if
3416 it is inside another SUBREG and the mode of that
3417 SUBREG and the mode of the inside of TO is
3418 tieable and it is valid if X is a SET that copies
3421 if (GET_CODE (to
) == SUBREG
3422 && ! MODES_TIEABLE_P (GET_MODE (to
),
3423 GET_MODE (SUBREG_REG (to
)))
3424 && ! (code
== SUBREG
3425 && MODES_TIEABLE_P (GET_MODE (x
),
3426 GET_MODE (SUBREG_REG (to
))))
3428 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3431 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3433 #ifdef CANNOT_CHANGE_MODE_CLASS
3435 && GET_CODE (to
) == REG
3436 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3437 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3440 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3443 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3447 /* If we are in a SET_DEST, suppress most cases unless we
3448 have gone inside a MEM, in which case we want to
3449 simplify the address. We assume here that things that
3450 are actually part of the destination have their inner
3451 parts in the first expression. This is true for SUBREG,
3452 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3453 things aside from REG and MEM that should appear in a
3455 new = subst (XEXP (x
, i
), from
, to
,
3457 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3458 || code
== ZERO_EXTRACT
))
3460 && i
== 0), unique_copy
);
3462 /* If we found that we will have to reject this combination,
3463 indicate that by returning the CLOBBER ourselves, rather than
3464 an expression containing it. This will speed things up as
3465 well as prevent accidents where two CLOBBERs are considered
3466 to be equal, thus producing an incorrect simplification. */
3468 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3471 if (GET_CODE (x
) == SUBREG
3472 && (GET_CODE (new) == CONST_INT
3473 || GET_CODE (new) == CONST_DOUBLE
))
3475 enum machine_mode mode
= GET_MODE (x
);
3477 x
= simplify_subreg (GET_MODE (x
), new,
3478 GET_MODE (SUBREG_REG (x
)),
3481 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3483 else if (GET_CODE (new) == CONST_INT
3484 && GET_CODE (x
) == ZERO_EXTEND
)
3486 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3487 new, GET_MODE (XEXP (x
, 0)));
3492 SUBST (XEXP (x
, i
), new);
3497 /* Try to simplify X. If the simplification changed the code, it is likely
3498 that further simplification will help, so loop, but limit the number
3499 of repetitions that will be performed. */
3501 for (i
= 0; i
< 4; i
++)
3503 /* If X is sufficiently simple, don't bother trying to do anything
3505 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3506 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3508 if (GET_CODE (x
) == code
)
3511 code
= GET_CODE (x
);
3513 /* We no longer know the original mode of operand 0 since we
3514 have changed the form of X) */
3515 op0_mode
= VOIDmode
;
3521 /* Simplify X, a piece of RTL. We just operate on the expression at the
3522 outer level; call `subst' to simplify recursively. Return the new
3525 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3526 will be the iteration even if an expression with a code different from
3527 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3530 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3533 enum rtx_code code
= GET_CODE (x
);
3534 enum machine_mode mode
= GET_MODE (x
);
3539 /* If this is a commutative operation, put a constant last and a complex
3540 expression first. We don't need to do this for comparisons here. */
3541 if (GET_RTX_CLASS (code
) == 'c'
3542 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3545 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3546 SUBST (XEXP (x
, 1), temp
);
3549 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3550 sign extension of a PLUS with a constant, reverse the order of the sign
3551 extension and the addition. Note that this not the same as the original
3552 code, but overflow is undefined for signed values. Also note that the
3553 PLUS will have been partially moved "inside" the sign-extension, so that
3554 the first operand of X will really look like:
3555 (ashiftrt (plus (ashift A C4) C5) C4).
3557 (plus (ashiftrt (ashift A C4) C2) C4)
3558 and replace the first operand of X with that expression. Later parts
3559 of this function may simplify the expression further.
3561 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3562 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3563 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3565 We do this to simplify address expressions. */
3567 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3568 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3569 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3570 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3571 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3572 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3573 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3574 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3575 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3576 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3577 XEXP (XEXP (x
, 0), 1))) != 0)
3580 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3581 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3582 INTVAL (XEXP (XEXP (x
, 0), 1)));
3584 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3585 INTVAL (XEXP (XEXP (x
, 0), 1)));
3587 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3590 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3591 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3592 things. Check for cases where both arms are testing the same
3595 Don't do anything if all operands are very simple. */
3597 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3598 || GET_RTX_CLASS (code
) == '<')
3599 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3600 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3601 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3603 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3604 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3605 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3607 || (GET_RTX_CLASS (code
) == '1'
3608 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3609 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3610 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3613 rtx cond
, true_rtx
, false_rtx
;
3615 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3617 /* If everything is a comparison, what we have is highly unlikely
3618 to be simpler, so don't use it. */
3619 && ! (GET_RTX_CLASS (code
) == '<'
3620 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3621 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3623 rtx cop1
= const0_rtx
;
3624 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3626 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3629 /* Simplify the alternative arms; this may collapse the true and
3630 false arms to store-flag values. Be careful to use copy_rtx
3631 here since true_rtx or false_rtx might share RTL with x as a
3632 result of the if_then_else_cond call above. */
3633 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3634 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3636 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3637 is unlikely to be simpler. */
3638 if (general_operand (true_rtx
, VOIDmode
)
3639 && general_operand (false_rtx
, VOIDmode
))
3641 enum rtx_code reversed
;
3643 /* Restarting if we generate a store-flag expression will cause
3644 us to loop. Just drop through in this case. */
3646 /* If the result values are STORE_FLAG_VALUE and zero, we can
3647 just make the comparison operation. */
3648 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3649 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3650 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3651 && ((reversed
= reversed_comparison_code_parts
3652 (cond_code
, cond
, cop1
, NULL
))
3654 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3656 /* Likewise, we can make the negate of a comparison operation
3657 if the result values are - STORE_FLAG_VALUE and zero. */
3658 else if (GET_CODE (true_rtx
) == CONST_INT
3659 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3660 && false_rtx
== const0_rtx
)
3661 x
= simplify_gen_unary (NEG
, mode
,
3662 gen_binary (cond_code
, mode
, cond
,
3665 else if (GET_CODE (false_rtx
) == CONST_INT
3666 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3667 && true_rtx
== const0_rtx
3668 && ((reversed
= reversed_comparison_code_parts
3669 (cond_code
, cond
, cop1
, NULL
))
3671 x
= simplify_gen_unary (NEG
, mode
,
3672 gen_binary (reversed
, mode
,
3676 return gen_rtx_IF_THEN_ELSE (mode
,
3677 gen_binary (cond_code
, VOIDmode
,
3679 true_rtx
, false_rtx
);
3681 code
= GET_CODE (x
);
3682 op0_mode
= VOIDmode
;
3687 /* Try to fold this expression in case we have constants that weren't
3690 switch (GET_RTX_CLASS (code
))
3693 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3697 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3698 if (cmp_mode
== VOIDmode
)
3700 cmp_mode
= GET_MODE (XEXP (x
, 1));
3701 if (cmp_mode
== VOIDmode
)
3702 cmp_mode
= op0_mode
;
3704 temp
= simplify_relational_operation (code
, cmp_mode
,
3705 XEXP (x
, 0), XEXP (x
, 1));
3707 #ifdef FLOAT_STORE_FLAG_VALUE
3708 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3710 if (temp
== const0_rtx
)
3711 temp
= CONST0_RTX (mode
);
3713 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3720 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3724 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3725 XEXP (x
, 1), XEXP (x
, 2));
3732 code
= GET_CODE (temp
);
3733 op0_mode
= VOIDmode
;
3734 mode
= GET_MODE (temp
);
3737 /* First see if we can apply the inverse distributive law. */
3738 if (code
== PLUS
|| code
== MINUS
3739 || code
== AND
|| code
== IOR
|| code
== XOR
)
3741 x
= apply_distributive_law (x
);
3742 code
= GET_CODE (x
);
3743 op0_mode
= VOIDmode
;
3746 /* If CODE is an associative operation not otherwise handled, see if we
3747 can associate some operands. This can win if they are constants or
3748 if they are logically related (i.e. (a & b) & a). */
3749 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3750 || code
== AND
|| code
== IOR
|| code
== XOR
3751 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3752 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3753 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3755 if (GET_CODE (XEXP (x
, 0)) == code
)
3757 rtx other
= XEXP (XEXP (x
, 0), 0);
3758 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3759 rtx inner_op1
= XEXP (x
, 1);
3762 /* Make sure we pass the constant operand if any as the second
3763 one if this is a commutative operation. */
3764 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3766 rtx tem
= inner_op0
;
3767 inner_op0
= inner_op1
;
3770 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3771 : code
== DIV
? MULT
3773 mode
, inner_op0
, inner_op1
);
3775 /* For commutative operations, try the other pair if that one
3777 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3779 other
= XEXP (XEXP (x
, 0), 1);
3780 inner
= simplify_binary_operation (code
, mode
,
3781 XEXP (XEXP (x
, 0), 0),
3786 return gen_binary (code
, mode
, other
, inner
);
3790 /* A little bit of algebraic simplification here. */
3794 /* Ensure that our address has any ASHIFTs converted to MULT in case
3795 address-recognizing predicates are called later. */
3796 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3797 SUBST (XEXP (x
, 0), temp
);
3801 if (op0_mode
== VOIDmode
)
3802 op0_mode
= GET_MODE (SUBREG_REG (x
));
3804 /* simplify_subreg can't use gen_lowpart_for_combine. */
3805 if (CONSTANT_P (SUBREG_REG (x
))
3806 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3807 /* Don't call gen_lowpart_for_combine if the inner mode
3808 is VOIDmode and we cannot simplify it, as SUBREG without
3809 inner mode is invalid. */
3810 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3811 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3812 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3814 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3818 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3824 /* Don't change the mode of the MEM if that would change the meaning
3826 if (GET_CODE (SUBREG_REG (x
)) == MEM
3827 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3828 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3829 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3831 /* Note that we cannot do any narrowing for non-constants since
3832 we might have been counting on using the fact that some bits were
3833 zero. We now do this in the SET. */
3838 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3839 && subreg_lowpart_p (XEXP (x
, 0))
3840 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3841 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3842 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3843 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3845 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3847 x
= gen_rtx_ROTATE (inner_mode
,
3848 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3850 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3851 return gen_lowpart_for_combine (mode
, x
);
3854 /* Apply De Morgan's laws to reduce number of patterns for machines
3855 with negating logical insns (and-not, nand, etc.). If result has
3856 only one NOT, put it first, since that is how the patterns are
3859 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3861 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3862 enum machine_mode op_mode
;
3864 op_mode
= GET_MODE (in1
);
3865 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3867 op_mode
= GET_MODE (in2
);
3868 if (op_mode
== VOIDmode
)
3870 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3872 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3875 in2
= in1
; in1
= tem
;
3878 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3884 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3885 if (GET_CODE (XEXP (x
, 0)) == XOR
3886 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3887 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3888 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3890 temp
= expand_compound_operation (XEXP (x
, 0));
3892 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3893 replaced by (lshiftrt X C). This will convert
3894 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3896 if (GET_CODE (temp
) == ASHIFTRT
3897 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3898 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3899 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3900 INTVAL (XEXP (temp
, 1)));
3902 /* If X has only a single bit that might be nonzero, say, bit I, convert
3903 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3904 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3905 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3906 or a SUBREG of one since we'd be making the expression more
3907 complex if it was just a register. */
3909 if (GET_CODE (temp
) != REG
3910 && ! (GET_CODE (temp
) == SUBREG
3911 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3912 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3914 rtx temp1
= simplify_shift_const
3915 (NULL_RTX
, ASHIFTRT
, mode
,
3916 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3917 GET_MODE_BITSIZE (mode
) - 1 - i
),
3918 GET_MODE_BITSIZE (mode
) - 1 - i
);
3920 /* If all we did was surround TEMP with the two shifts, we
3921 haven't improved anything, so don't use it. Otherwise,
3922 we are better off with TEMP1. */
3923 if (GET_CODE (temp1
) != ASHIFTRT
3924 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3925 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3931 /* We can't handle truncation to a partial integer mode here
3932 because we don't know the real bitsize of the partial
3934 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3937 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3938 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3939 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3941 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3942 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3944 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3945 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3946 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3947 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3948 return XEXP (XEXP (x
, 0), 0);
3950 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3951 (OP:SI foo:SI) if OP is NEG or ABS. */
3952 if ((GET_CODE (XEXP (x
, 0)) == ABS
3953 || GET_CODE (XEXP (x
, 0)) == NEG
)
3954 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3955 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3956 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3957 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3958 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3960 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3962 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3963 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3964 && subreg_lowpart_p (XEXP (x
, 0)))
3965 return SUBREG_REG (XEXP (x
, 0));
3967 /* If we know that the value is already truncated, we can
3968 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3969 is nonzero for the corresponding modes. But don't do this
3970 for an (LSHIFTRT (MULT ...)) since this will cause problems
3971 with the umulXi3_highpart patterns. */
3972 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3973 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3974 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3975 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
3976 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3977 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
3978 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3980 /* A truncate of a comparison can be replaced with a subreg if
3981 STORE_FLAG_VALUE permits. This is like the previous test,
3982 but it works even if the comparison is done in a mode larger
3983 than HOST_BITS_PER_WIDE_INT. */
3984 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3985 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3986 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
3987 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3989 /* Similarly, a truncate of a register whose value is a
3990 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3992 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3993 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
3994 && (temp
= get_last_value (XEXP (x
, 0)))
3995 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
3996 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4000 case FLOAT_TRUNCATE
:
4001 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4002 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4003 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4004 return XEXP (XEXP (x
, 0), 0);
4006 /* (float_truncate:SF (float_truncate:DF foo:XF))
4007 = (float_truncate:SF foo:XF).
4008 This may eliminate double rounding, so it is unsafe.
4010 (float_truncate:SF (float_extend:XF foo:DF))
4011 = (float_truncate:SF foo:DF).
4013 (float_truncate:DF (float_extend:XF foo:SF))
4014 = (float_extend:SF foo:DF). */
4015 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4016 && flag_unsafe_math_optimizations
)
4017 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4018 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4020 > GET_MODE_SIZE (mode
)
4021 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4023 XEXP (XEXP (x
, 0), 0), mode
);
4025 /* (float_truncate (float x)) is (float x) */
4026 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4027 && (flag_unsafe_math_optimizations
4028 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4029 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4030 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4031 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4032 return simplify_gen_unary (FLOAT
, mode
,
4033 XEXP (XEXP (x
, 0), 0),
4034 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4036 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4037 (OP:SF foo:SF) if OP is NEG or ABS. */
4038 if ((GET_CODE (XEXP (x
, 0)) == ABS
4039 || GET_CODE (XEXP (x
, 0)) == NEG
)
4040 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4041 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4042 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4043 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4045 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4046 is (float_truncate:SF x). */
4047 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4048 && subreg_lowpart_p (XEXP (x
, 0))
4049 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4050 return SUBREG_REG (XEXP (x
, 0));
4053 /* (float_extend (float_extend x)) is (float_extend x)
4055 (float_extend (float x)) is (float x) assuming that double
4056 rounding can't happen.
4058 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4059 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4060 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4061 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4062 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4063 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4064 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4065 XEXP (XEXP (x
, 0), 0),
4066 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4071 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4072 using cc0, in which case we want to leave it as a COMPARE
4073 so we can distinguish it from a register-register-copy. */
4074 if (XEXP (x
, 1) == const0_rtx
)
4077 /* x - 0 is the same as x unless x's mode has signed zeros and
4078 allows rounding towards -infinity. Under those conditions,
4080 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4081 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4082 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4088 /* (const (const X)) can become (const X). Do it this way rather than
4089 returning the inner CONST since CONST can be shared with a
4091 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4092 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4097 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4098 can add in an offset. find_split_point will split this address up
4099 again if it doesn't match. */
4100 if (GET_CODE (XEXP (x
, 0)) == HIGH
4101 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4107 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4109 if (GET_CODE (XEXP (x
, 0)) == MULT
4110 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4114 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4115 in2
= XEXP (XEXP (x
, 0), 1);
4116 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4117 gen_binary (MULT
, mode
, in1
, in2
));
4120 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4121 outermost. That's because that's the way indexed addresses are
4122 supposed to appear. This code used to check many more cases, but
4123 they are now checked elsewhere. */
4124 if (GET_CODE (XEXP (x
, 0)) == PLUS
4125 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4126 return gen_binary (PLUS
, mode
,
4127 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4129 XEXP (XEXP (x
, 0), 1));
4131 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4132 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4133 bit-field and can be replaced by either a sign_extend or a
4134 sign_extract. The `and' may be a zero_extend and the two
4135 <c>, -<c> constants may be reversed. */
4136 if (GET_CODE (XEXP (x
, 0)) == XOR
4137 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4138 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4139 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4140 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4141 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4142 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4143 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4144 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4145 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4146 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4147 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4148 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4149 == (unsigned int) i
+ 1))))
4150 return simplify_shift_const
4151 (NULL_RTX
, ASHIFTRT
, mode
,
4152 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4153 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4154 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4155 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4157 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4158 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4159 is 1. This produces better code than the alternative immediately
4161 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4162 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4163 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4164 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4165 XEXP (XEXP (x
, 0), 0),
4166 XEXP (XEXP (x
, 0), 1))))
4168 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4170 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4171 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4172 the bitsize of the mode - 1. This allows simplification of
4173 "a = (b & 8) == 0;" */
4174 if (XEXP (x
, 1) == constm1_rtx
4175 && GET_CODE (XEXP (x
, 0)) != REG
4176 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4177 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4178 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4179 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4180 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4181 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4182 GET_MODE_BITSIZE (mode
) - 1),
4183 GET_MODE_BITSIZE (mode
) - 1);
4185 /* If we are adding two things that have no bits in common, convert
4186 the addition into an IOR. This will often be further simplified,
4187 for example in cases like ((a & 1) + (a & 2)), which can
4190 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4191 && (nonzero_bits (XEXP (x
, 0), mode
)
4192 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4194 /* Try to simplify the expression further. */
4195 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4196 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4198 /* If we could, great. If not, do not go ahead with the IOR
4199 replacement, since PLUS appears in many special purpose
4200 address arithmetic instructions. */
4201 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4207 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4208 by reversing the comparison code if valid. */
4209 if (STORE_FLAG_VALUE
== 1
4210 && XEXP (x
, 0) == const1_rtx
4211 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4212 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4213 XEXP (XEXP (x
, 1), 0),
4214 XEXP (XEXP (x
, 1), 1))))
4217 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4218 (and <foo> (const_int pow2-1)) */
4219 if (GET_CODE (XEXP (x
, 1)) == AND
4220 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4221 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4222 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4223 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4224 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4226 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4228 if (GET_CODE (XEXP (x
, 1)) == MULT
4229 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4233 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4234 in2
= XEXP (XEXP (x
, 1), 1);
4235 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4239 /* Canonicalize (minus (neg A) (mult B C)) to
4240 (minus (mult (neg B) C) A). */
4241 if (GET_CODE (XEXP (x
, 1)) == MULT
4242 && GET_CODE (XEXP (x
, 0)) == NEG
)
4246 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4247 in2
= XEXP (XEXP (x
, 1), 1);
4248 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4249 XEXP (XEXP (x
, 0), 0));
4252 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4254 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4255 return gen_binary (MINUS
, mode
,
4256 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4257 XEXP (XEXP (x
, 1), 0)),
4258 XEXP (XEXP (x
, 1), 1));
4262 /* If we have (mult (plus A B) C), apply the distributive law and then
4263 the inverse distributive law to see if things simplify. This
4264 occurs mostly in addresses, often when unrolling loops. */
4266 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4268 x
= apply_distributive_law
4269 (gen_binary (PLUS
, mode
,
4270 gen_binary (MULT
, mode
,
4271 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4272 gen_binary (MULT
, mode
,
4273 XEXP (XEXP (x
, 0), 1),
4274 copy_rtx (XEXP (x
, 1)))));
4276 if (GET_CODE (x
) != MULT
)
4279 /* Try simplify a*(b/c) as (a*b)/c. */
4280 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4281 && GET_CODE (XEXP (x
, 0)) == DIV
)
4283 rtx tem
= simplify_binary_operation (MULT
, mode
,
4284 XEXP (XEXP (x
, 0), 0),
4287 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4292 /* If this is a divide by a power of two, treat it as a shift if
4293 its first operand is a shift. */
4294 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4295 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4296 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4297 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4298 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4299 || GET_CODE (XEXP (x
, 0)) == ROTATE
4300 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4301 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4305 case GT
: case GTU
: case GE
: case GEU
:
4306 case LT
: case LTU
: case LE
: case LEU
:
4307 case UNEQ
: case LTGT
:
4308 case UNGT
: case UNGE
:
4309 case UNLT
: case UNLE
:
4310 case UNORDERED
: case ORDERED
:
4311 /* If the first operand is a condition code, we can't do anything
4313 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4314 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4315 && ! CC0_P (XEXP (x
, 0))))
4317 rtx op0
= XEXP (x
, 0);
4318 rtx op1
= XEXP (x
, 1);
4319 enum rtx_code new_code
;
4321 if (GET_CODE (op0
) == COMPARE
)
4322 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4324 /* Simplify our comparison, if possible. */
4325 new_code
= simplify_comparison (code
, &op0
, &op1
);
4327 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4328 if only the low-order bit is possibly nonzero in X (such as when
4329 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4330 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4331 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4334 Remove any ZERO_EXTRACT we made when thinking this was a
4335 comparison. It may now be simpler to use, e.g., an AND. If a
4336 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4337 the call to make_compound_operation in the SET case. */
4339 if (STORE_FLAG_VALUE
== 1
4340 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4341 && op1
== const0_rtx
4342 && mode
== GET_MODE (op0
)
4343 && nonzero_bits (op0
, mode
) == 1)
4344 return gen_lowpart_for_combine (mode
,
4345 expand_compound_operation (op0
));
4347 else if (STORE_FLAG_VALUE
== 1
4348 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4349 && op1
== const0_rtx
4350 && mode
== GET_MODE (op0
)
4351 && (num_sign_bit_copies (op0
, mode
)
4352 == GET_MODE_BITSIZE (mode
)))
4354 op0
= expand_compound_operation (op0
);
4355 return simplify_gen_unary (NEG
, mode
,
4356 gen_lowpart_for_combine (mode
, op0
),
4360 else if (STORE_FLAG_VALUE
== 1
4361 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4362 && op1
== const0_rtx
4363 && mode
== GET_MODE (op0
)
4364 && nonzero_bits (op0
, mode
) == 1)
4366 op0
= expand_compound_operation (op0
);
4367 return gen_binary (XOR
, mode
,
4368 gen_lowpart_for_combine (mode
, op0
),
4372 else if (STORE_FLAG_VALUE
== 1
4373 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4374 && op1
== const0_rtx
4375 && mode
== GET_MODE (op0
)
4376 && (num_sign_bit_copies (op0
, mode
)
4377 == GET_MODE_BITSIZE (mode
)))
4379 op0
= expand_compound_operation (op0
);
4380 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4383 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4385 if (STORE_FLAG_VALUE
== -1
4386 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4387 && op1
== const0_rtx
4388 && (num_sign_bit_copies (op0
, mode
)
4389 == GET_MODE_BITSIZE (mode
)))
4390 return gen_lowpart_for_combine (mode
,
4391 expand_compound_operation (op0
));
4393 else if (STORE_FLAG_VALUE
== -1
4394 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4395 && op1
== const0_rtx
4396 && mode
== GET_MODE (op0
)
4397 && nonzero_bits (op0
, mode
) == 1)
4399 op0
= expand_compound_operation (op0
);
4400 return simplify_gen_unary (NEG
, mode
,
4401 gen_lowpart_for_combine (mode
, op0
),
4405 else if (STORE_FLAG_VALUE
== -1
4406 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4407 && op1
== const0_rtx
4408 && mode
== GET_MODE (op0
)
4409 && (num_sign_bit_copies (op0
, mode
)
4410 == GET_MODE_BITSIZE (mode
)))
4412 op0
= expand_compound_operation (op0
);
4413 return simplify_gen_unary (NOT
, mode
,
4414 gen_lowpart_for_combine (mode
, op0
),
4418 /* If X is 0/1, (eq X 0) is X-1. */
4419 else if (STORE_FLAG_VALUE
== -1
4420 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4421 && op1
== const0_rtx
4422 && mode
== GET_MODE (op0
)
4423 && nonzero_bits (op0
, mode
) == 1)
4425 op0
= expand_compound_operation (op0
);
4426 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4429 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4430 one bit that might be nonzero, we can convert (ne x 0) to
4431 (ashift x c) where C puts the bit in the sign bit. Remove any
4432 AND with STORE_FLAG_VALUE when we are done, since we are only
4433 going to test the sign bit. */
4434 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4435 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4436 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4437 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4438 && op1
== const0_rtx
4439 && mode
== GET_MODE (op0
)
4440 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4442 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4443 expand_compound_operation (op0
),
4444 GET_MODE_BITSIZE (mode
) - 1 - i
);
4445 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4451 /* If the code changed, return a whole new comparison. */
4452 if (new_code
!= code
)
4453 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4455 /* Otherwise, keep this operation, but maybe change its operands.
4456 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4457 SUBST (XEXP (x
, 0), op0
);
4458 SUBST (XEXP (x
, 1), op1
);
4463 return simplify_if_then_else (x
);
4469 /* If we are processing SET_DEST, we are done. */
4473 return expand_compound_operation (x
);
4476 return simplify_set (x
);
4481 return simplify_logical (x
, last
);
4484 /* (abs (neg <foo>)) -> (abs <foo>) */
4485 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4486 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4488 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4490 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4493 /* If operand is something known to be positive, ignore the ABS. */
4494 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4495 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4496 <= HOST_BITS_PER_WIDE_INT
)
4497 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4498 & ((HOST_WIDE_INT
) 1
4499 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4503 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4504 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4505 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4510 /* (ffs (*_extend <X>)) = (ffs <X>) */
4511 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4512 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4513 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4518 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4519 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4520 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4524 /* (float (sign_extend <X>)) = (float <X>). */
4525 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4526 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4534 /* If this is a shift by a constant amount, simplify it. */
4535 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4536 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4537 INTVAL (XEXP (x
, 1)));
4539 #ifdef SHIFT_COUNT_TRUNCATED
4540 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4542 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4544 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4553 rtx op0
= XEXP (x
, 0);
4554 rtx op1
= XEXP (x
, 1);
4557 if (GET_CODE (op1
) != PARALLEL
)
4559 len
= XVECLEN (op1
, 0);
4561 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4562 && GET_CODE (op0
) == VEC_CONCAT
)
4564 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4566 /* Try to find the element in the VEC_CONCAT. */
4569 if (GET_MODE (op0
) == GET_MODE (x
))
4571 if (GET_CODE (op0
) == VEC_CONCAT
)
4573 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4574 if (op0_size
< offset
)
4575 op0
= XEXP (op0
, 0);
4579 op0
= XEXP (op0
, 1);
4597 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4600 simplify_if_then_else (rtx x
)
4602 enum machine_mode mode
= GET_MODE (x
);
4603 rtx cond
= XEXP (x
, 0);
4604 rtx true_rtx
= XEXP (x
, 1);
4605 rtx false_rtx
= XEXP (x
, 2);
4606 enum rtx_code true_code
= GET_CODE (cond
);
4607 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4610 enum rtx_code false_code
;
4613 /* Simplify storing of the truth value. */
4614 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4615 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4617 /* Also when the truth value has to be reversed. */
4619 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4620 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4624 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4625 in it is being compared against certain values. Get the true and false
4626 comparisons and see if that says anything about the value of each arm. */
4629 && ((false_code
= combine_reversed_comparison_code (cond
))
4631 && GET_CODE (XEXP (cond
, 0)) == REG
)
4634 rtx from
= XEXP (cond
, 0);
4635 rtx true_val
= XEXP (cond
, 1);
4636 rtx false_val
= true_val
;
4639 /* If FALSE_CODE is EQ, swap the codes and arms. */
4641 if (false_code
== EQ
)
4643 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4644 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4647 /* If we are comparing against zero and the expression being tested has
4648 only a single bit that might be nonzero, that is its value when it is
4649 not equal to zero. Similarly if it is known to be -1 or 0. */
4651 if (true_code
== EQ
&& true_val
== const0_rtx
4652 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4653 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4654 else if (true_code
== EQ
&& true_val
== const0_rtx
4655 && (num_sign_bit_copies (from
, GET_MODE (from
))
4656 == GET_MODE_BITSIZE (GET_MODE (from
))))
4657 false_code
= EQ
, false_val
= constm1_rtx
;
4659 /* Now simplify an arm if we know the value of the register in the
4660 branch and it is used in the arm. Be careful due to the potential
4661 of locally-shared RTL. */
4663 if (reg_mentioned_p (from
, true_rtx
))
4664 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4666 pc_rtx
, pc_rtx
, 0, 0);
4667 if (reg_mentioned_p (from
, false_rtx
))
4668 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4670 pc_rtx
, pc_rtx
, 0, 0);
4672 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4673 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4675 true_rtx
= XEXP (x
, 1);
4676 false_rtx
= XEXP (x
, 2);
4677 true_code
= GET_CODE (cond
);
4680 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4681 reversed, do so to avoid needing two sets of patterns for
4682 subtract-and-branch insns. Similarly if we have a constant in the true
4683 arm, the false arm is the same as the first operand of the comparison, or
4684 the false arm is more complicated than the true arm. */
4687 && combine_reversed_comparison_code (cond
) != UNKNOWN
4688 && (true_rtx
== pc_rtx
4689 || (CONSTANT_P (true_rtx
)
4690 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4691 || true_rtx
== const0_rtx
4692 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4693 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4694 || (GET_CODE (true_rtx
) == SUBREG
4695 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4696 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4697 || reg_mentioned_p (true_rtx
, false_rtx
)
4698 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4700 true_code
= reversed_comparison_code (cond
, NULL
);
4702 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4705 SUBST (XEXP (x
, 1), false_rtx
);
4706 SUBST (XEXP (x
, 2), true_rtx
);
4708 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4711 /* It is possible that the conditional has been simplified out. */
4712 true_code
= GET_CODE (cond
);
4713 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4716 /* If the two arms are identical, we don't need the comparison. */
4718 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4721 /* Convert a == b ? b : a to "a". */
4722 if (true_code
== EQ
&& ! side_effects_p (cond
)
4723 && !HONOR_NANS (mode
)
4724 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4725 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4727 else if (true_code
== NE
&& ! side_effects_p (cond
)
4728 && !HONOR_NANS (mode
)
4729 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4730 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4733 /* Look for cases where we have (abs x) or (neg (abs X)). */
4735 if (GET_MODE_CLASS (mode
) == MODE_INT
4736 && GET_CODE (false_rtx
) == NEG
4737 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4739 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4740 && ! side_effects_p (true_rtx
))
4745 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4749 simplify_gen_unary (NEG
, mode
,
4750 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4756 /* Look for MIN or MAX. */
4758 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4760 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4761 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4762 && ! side_effects_p (cond
))
4767 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4770 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4773 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4776 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4781 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4782 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4783 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4784 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4785 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4786 neither 1 or -1, but it isn't worth checking for. */
4788 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4790 && GET_MODE_CLASS (mode
) == MODE_INT
4791 && ! side_effects_p (x
))
4793 rtx t
= make_compound_operation (true_rtx
, SET
);
4794 rtx f
= make_compound_operation (false_rtx
, SET
);
4795 rtx cond_op0
= XEXP (cond
, 0);
4796 rtx cond_op1
= XEXP (cond
, 1);
4797 enum rtx_code op
= NIL
, extend_op
= NIL
;
4798 enum machine_mode m
= mode
;
4799 rtx z
= 0, c1
= NULL_RTX
;
4801 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4802 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4803 || GET_CODE (t
) == ASHIFT
4804 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4805 && rtx_equal_p (XEXP (t
, 0), f
))
4806 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4808 /* If an identity-zero op is commutative, check whether there
4809 would be a match if we swapped the operands. */
4810 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4811 || GET_CODE (t
) == XOR
)
4812 && rtx_equal_p (XEXP (t
, 1), f
))
4813 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4814 else if (GET_CODE (t
) == SIGN_EXTEND
4815 && (GET_CODE (XEXP (t
, 0)) == PLUS
4816 || GET_CODE (XEXP (t
, 0)) == MINUS
4817 || GET_CODE (XEXP (t
, 0)) == IOR
4818 || GET_CODE (XEXP (t
, 0)) == XOR
4819 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4820 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4821 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4822 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4823 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4824 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4825 && (num_sign_bit_copies (f
, GET_MODE (f
))
4827 (GET_MODE_BITSIZE (mode
)
4828 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4830 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4831 extend_op
= SIGN_EXTEND
;
4832 m
= GET_MODE (XEXP (t
, 0));
4834 else if (GET_CODE (t
) == SIGN_EXTEND
4835 && (GET_CODE (XEXP (t
, 0)) == PLUS
4836 || GET_CODE (XEXP (t
, 0)) == IOR
4837 || GET_CODE (XEXP (t
, 0)) == XOR
)
4838 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4839 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4840 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4841 && (num_sign_bit_copies (f
, GET_MODE (f
))
4843 (GET_MODE_BITSIZE (mode
)
4844 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4846 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4847 extend_op
= SIGN_EXTEND
;
4848 m
= GET_MODE (XEXP (t
, 0));
4850 else if (GET_CODE (t
) == ZERO_EXTEND
4851 && (GET_CODE (XEXP (t
, 0)) == PLUS
4852 || GET_CODE (XEXP (t
, 0)) == MINUS
4853 || GET_CODE (XEXP (t
, 0)) == IOR
4854 || GET_CODE (XEXP (t
, 0)) == XOR
4855 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4856 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4857 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4858 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4859 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4860 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4861 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4862 && ((nonzero_bits (f
, GET_MODE (f
))
4863 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4866 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4867 extend_op
= ZERO_EXTEND
;
4868 m
= GET_MODE (XEXP (t
, 0));
4870 else if (GET_CODE (t
) == ZERO_EXTEND
4871 && (GET_CODE (XEXP (t
, 0)) == PLUS
4872 || GET_CODE (XEXP (t
, 0)) == IOR
4873 || GET_CODE (XEXP (t
, 0)) == XOR
)
4874 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4875 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4876 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4877 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4878 && ((nonzero_bits (f
, GET_MODE (f
))
4879 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4882 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4883 extend_op
= ZERO_EXTEND
;
4884 m
= GET_MODE (XEXP (t
, 0));
4889 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4890 pc_rtx
, pc_rtx
, 0, 0);
4891 temp
= gen_binary (MULT
, m
, temp
,
4892 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4893 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4894 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4896 if (extend_op
!= NIL
)
4897 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4903 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4904 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4905 negation of a single bit, we can convert this operation to a shift. We
4906 can actually do this more generally, but it doesn't seem worth it. */
4908 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4909 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4910 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4911 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4912 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4913 == GET_MODE_BITSIZE (mode
))
4914 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4916 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4917 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4919 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4920 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4921 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4922 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4923 == nonzero_bits (XEXP (cond
, 0), mode
)
4924 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4925 return XEXP (cond
, 0);
4930 /* Simplify X, a SET expression. Return the new expression. */
4933 simplify_set (rtx x
)
4935 rtx src
= SET_SRC (x
);
4936 rtx dest
= SET_DEST (x
);
4937 enum machine_mode mode
4938 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4942 /* (set (pc) (return)) gets written as (return). */
4943 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4946 /* Now that we know for sure which bits of SRC we are using, see if we can
4947 simplify the expression for the object knowing that we only need the
4950 if (GET_MODE_CLASS (mode
) == MODE_INT
4951 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4953 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4954 SUBST (SET_SRC (x
), src
);
4957 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4958 the comparison result and try to simplify it unless we already have used
4959 undobuf.other_insn. */
4960 if ((GET_MODE_CLASS (mode
) == MODE_CC
4961 || GET_CODE (src
) == COMPARE
4963 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4964 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4965 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4966 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4968 enum rtx_code old_code
= GET_CODE (*cc_use
);
4969 enum rtx_code new_code
;
4971 int other_changed
= 0;
4972 enum machine_mode compare_mode
= GET_MODE (dest
);
4973 enum machine_mode tmp_mode
;
4975 if (GET_CODE (src
) == COMPARE
)
4976 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4978 op0
= src
, op1
= const0_rtx
;
4980 /* Check whether the comparison is known at compile time. */
4981 if (GET_MODE (op0
) != VOIDmode
)
4982 tmp_mode
= GET_MODE (op0
);
4983 else if (GET_MODE (op1
) != VOIDmode
)
4984 tmp_mode
= GET_MODE (op1
);
4986 tmp_mode
= compare_mode
;
4987 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
4988 if (tmp
!= NULL_RTX
)
4990 rtx pat
= PATTERN (other_insn
);
4991 undobuf
.other_insn
= other_insn
;
4992 SUBST (*cc_use
, tmp
);
4994 /* Attempt to simplify CC user. */
4995 if (GET_CODE (pat
) == SET
)
4997 rtx
new = simplify_rtx (SET_SRC (pat
));
4998 if (new != NULL_RTX
)
4999 SUBST (SET_SRC (pat
), new);
5002 /* Convert X into a no-op move. */
5003 SUBST (SET_DEST (x
), pc_rtx
);
5004 SUBST (SET_SRC (x
), pc_rtx
);
5008 /* Simplify our comparison, if possible. */
5009 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5011 #ifdef SELECT_CC_MODE
5012 /* If this machine has CC modes other than CCmode, check to see if we
5013 need to use a different CC mode here. */
5014 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5017 /* If the mode changed, we have to change SET_DEST, the mode in the
5018 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5019 a hard register, just build new versions with the proper mode. If it
5020 is a pseudo, we lose unless it is only time we set the pseudo, in
5021 which case we can safely change its mode. */
5022 if (compare_mode
!= GET_MODE (dest
))
5024 unsigned int regno
= REGNO (dest
);
5025 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5027 if (regno
< FIRST_PSEUDO_REGISTER
5028 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5030 if (regno
>= FIRST_PSEUDO_REGISTER
)
5031 SUBST (regno_reg_rtx
[regno
], new_dest
);
5033 SUBST (SET_DEST (x
), new_dest
);
5034 SUBST (XEXP (*cc_use
, 0), new_dest
);
5041 #endif /* SELECT_CC_MODE */
5043 /* If the code changed, we have to build a new comparison in
5044 undobuf.other_insn. */
5045 if (new_code
!= old_code
)
5047 int other_changed_previously
= other_changed
;
5048 unsigned HOST_WIDE_INT mask
;
5050 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5054 /* If the only change we made was to change an EQ into an NE or
5055 vice versa, OP0 has only one bit that might be nonzero, and OP1
5056 is zero, check if changing the user of the condition code will
5057 produce a valid insn. If it won't, we can keep the original code
5058 in that insn by surrounding our operation with an XOR. */
5060 if (((old_code
== NE
&& new_code
== EQ
)
5061 || (old_code
== EQ
&& new_code
== NE
))
5062 && ! other_changed_previously
&& op1
== const0_rtx
5063 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5064 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5066 rtx pat
= PATTERN (other_insn
), note
= 0;
5068 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5069 && ! check_asm_operands (pat
)))
5071 PUT_CODE (*cc_use
, old_code
);
5074 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5080 undobuf
.other_insn
= other_insn
;
5083 /* If we are now comparing against zero, change our source if
5084 needed. If we do not use cc0, we always have a COMPARE. */
5085 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5087 SUBST (SET_SRC (x
), op0
);
5093 /* Otherwise, if we didn't previously have a COMPARE in the
5094 correct mode, we need one. */
5095 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5097 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5102 /* Otherwise, update the COMPARE if needed. */
5103 SUBST (XEXP (src
, 0), op0
);
5104 SUBST (XEXP (src
, 1), op1
);
5109 /* Get SET_SRC in a form where we have placed back any
5110 compound expressions. Then do the checks below. */
5111 src
= make_compound_operation (src
, SET
);
5112 SUBST (SET_SRC (x
), src
);
5115 #ifdef WORD_REGISTER_OPERATIONS
5116 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5117 and X being a REG or (subreg (reg)), we may be able to convert this to
5118 (set (subreg:m2 x) (op)).
5120 On a machine where WORD_REGISTER_OPERATIONS is defined, this
5121 transformation is safe as long as M1 and M2 have the same number
5124 However, on a machine without WORD_REGISTER_OPERATIONS defined,
5125 we cannot apply this transformation because it would create a
5126 paradoxical subreg in SET_DEST. */
5128 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5129 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5130 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5132 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5133 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5134 #ifdef CANNOT_CHANGE_MODE_CLASS
5135 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5136 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5137 GET_MODE (SUBREG_REG (src
)),
5140 && (GET_CODE (dest
) == REG
5141 || (GET_CODE (dest
) == SUBREG
5142 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5144 SUBST (SET_DEST (x
),
5145 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5147 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5149 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5154 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5157 && GET_CODE (src
) == SUBREG
5158 && subreg_lowpart_p (src
)
5159 && (GET_MODE_BITSIZE (GET_MODE (src
))
5160 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5162 rtx inner
= SUBREG_REG (src
);
5163 enum machine_mode inner_mode
= GET_MODE (inner
);
5165 /* Here we make sure that we don't have a sign bit on. */
5166 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5167 && (nonzero_bits (inner
, inner_mode
)
5168 < ((unsigned HOST_WIDE_INT
) 1
5169 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5171 SUBST (SET_SRC (x
), inner
);
5177 #ifdef LOAD_EXTEND_OP
5178 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5179 would require a paradoxical subreg. Replace the subreg with a
5180 zero_extend to avoid the reload that would otherwise be required. */
5182 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5183 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5184 && SUBREG_BYTE (src
) == 0
5185 && (GET_MODE_SIZE (GET_MODE (src
))
5186 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5187 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5190 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5191 GET_MODE (src
), SUBREG_REG (src
)));
5197 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5198 are comparing an item known to be 0 or -1 against 0, use a logical
5199 operation instead. Check for one of the arms being an IOR of the other
5200 arm with some value. We compute three terms to be IOR'ed together. In
5201 practice, at most two will be nonzero. Then we do the IOR's. */
5203 if (GET_CODE (dest
) != PC
5204 && GET_CODE (src
) == IF_THEN_ELSE
5205 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5206 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5207 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5208 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5209 #ifdef HAVE_conditional_move
5210 && ! can_conditionally_move_p (GET_MODE (src
))
5212 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5213 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5214 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5215 && ! side_effects_p (src
))
5217 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5218 ? XEXP (src
, 1) : XEXP (src
, 2));
5219 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5220 ? XEXP (src
, 2) : XEXP (src
, 1));
5221 rtx term1
= const0_rtx
, term2
, term3
;
5223 if (GET_CODE (true_rtx
) == IOR
5224 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5225 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5226 else if (GET_CODE (true_rtx
) == IOR
5227 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5228 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5229 else if (GET_CODE (false_rtx
) == IOR
5230 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5231 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5232 else if (GET_CODE (false_rtx
) == IOR
5233 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5234 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5236 term2
= gen_binary (AND
, GET_MODE (src
),
5237 XEXP (XEXP (src
, 0), 0), true_rtx
);
5238 term3
= gen_binary (AND
, GET_MODE (src
),
5239 simplify_gen_unary (NOT
, GET_MODE (src
),
5240 XEXP (XEXP (src
, 0), 0),
5245 gen_binary (IOR
, GET_MODE (src
),
5246 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5252 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5253 whole thing fail. */
5254 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5256 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5259 /* Convert this into a field assignment operation, if possible. */
5260 return make_field_assignment (x
);
5263 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5264 result. LAST is nonzero if this is the last retry. */
5267 simplify_logical (rtx x
, int last
)
5269 enum machine_mode mode
= GET_MODE (x
);
5270 rtx op0
= XEXP (x
, 0);
5271 rtx op1
= XEXP (x
, 1);
5274 switch (GET_CODE (x
))
5277 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5278 insn (and may simplify more). */
5279 if (GET_CODE (op0
) == XOR
5280 && rtx_equal_p (XEXP (op0
, 0), op1
)
5281 && ! side_effects_p (op1
))
5282 x
= gen_binary (AND
, mode
,
5283 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5286 if (GET_CODE (op0
) == XOR
5287 && rtx_equal_p (XEXP (op0
, 1), op1
)
5288 && ! side_effects_p (op1
))
5289 x
= gen_binary (AND
, mode
,
5290 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5293 /* Similarly for (~(A ^ B)) & A. */
5294 if (GET_CODE (op0
) == NOT
5295 && GET_CODE (XEXP (op0
, 0)) == XOR
5296 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5297 && ! side_effects_p (op1
))
5298 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5300 if (GET_CODE (op0
) == NOT
5301 && GET_CODE (XEXP (op0
, 0)) == XOR
5302 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5303 && ! side_effects_p (op1
))
5304 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5306 /* We can call simplify_and_const_int only if we don't lose
5307 any (sign) bits when converting INTVAL (op1) to
5308 "unsigned HOST_WIDE_INT". */
5309 if (GET_CODE (op1
) == CONST_INT
5310 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5311 || INTVAL (op1
) > 0))
5313 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5315 /* If we have (ior (and (X C1) C2)) and the next restart would be
5316 the last, simplify this by making C1 as small as possible
5319 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5320 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5321 && GET_CODE (op1
) == CONST_INT
)
5322 return gen_binary (IOR
, mode
,
5323 gen_binary (AND
, mode
, XEXP (op0
, 0),
5324 GEN_INT (INTVAL (XEXP (op0
, 1))
5325 & ~INTVAL (op1
))), op1
);
5327 if (GET_CODE (x
) != AND
)
5330 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5331 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5332 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5335 /* Convert (A | B) & A to A. */
5336 if (GET_CODE (op0
) == IOR
5337 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5338 || rtx_equal_p (XEXP (op0
, 1), op1
))
5339 && ! side_effects_p (XEXP (op0
, 0))
5340 && ! side_effects_p (XEXP (op0
, 1)))
5343 /* In the following group of tests (and those in case IOR below),
5344 we start with some combination of logical operations and apply
5345 the distributive law followed by the inverse distributive law.
5346 Most of the time, this results in no change. However, if some of
5347 the operands are the same or inverses of each other, simplifications
5350 For example, (and (ior A B) (not B)) can occur as the result of
5351 expanding a bit field assignment. When we apply the distributive
5352 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5353 which then simplifies to (and (A (not B))).
5355 If we have (and (ior A B) C), apply the distributive law and then
5356 the inverse distributive law to see if things simplify. */
5358 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5360 x
= apply_distributive_law
5361 (gen_binary (GET_CODE (op0
), mode
,
5362 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5363 gen_binary (AND
, mode
, XEXP (op0
, 1),
5365 if (GET_CODE (x
) != AND
)
5369 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5370 return apply_distributive_law
5371 (gen_binary (GET_CODE (op1
), mode
,
5372 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5373 gen_binary (AND
, mode
, XEXP (op1
, 1),
5376 /* Similarly, taking advantage of the fact that
5377 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5379 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5380 return apply_distributive_law
5381 (gen_binary (XOR
, mode
,
5382 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5383 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5386 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5387 return apply_distributive_law
5388 (gen_binary (XOR
, mode
,
5389 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5390 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5394 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5395 if (GET_CODE (op1
) == CONST_INT
5396 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5397 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5400 /* Convert (A & B) | A to A. */
5401 if (GET_CODE (op0
) == AND
5402 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5403 || rtx_equal_p (XEXP (op0
, 1), op1
))
5404 && ! side_effects_p (XEXP (op0
, 0))
5405 && ! side_effects_p (XEXP (op0
, 1)))
5408 /* If we have (ior (and A B) C), apply the distributive law and then
5409 the inverse distributive law to see if things simplify. */
5411 if (GET_CODE (op0
) == AND
)
5413 x
= apply_distributive_law
5414 (gen_binary (AND
, mode
,
5415 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5416 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5419 if (GET_CODE (x
) != IOR
)
5423 if (GET_CODE (op1
) == AND
)
5425 x
= apply_distributive_law
5426 (gen_binary (AND
, mode
,
5427 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5428 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5431 if (GET_CODE (x
) != IOR
)
5435 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5436 mode size to (rotate A CX). */
5438 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5439 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5440 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5441 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5442 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5443 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5444 == GET_MODE_BITSIZE (mode
)))
5445 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5446 (GET_CODE (op0
) == ASHIFT
5447 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5449 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5450 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5451 does not affect any of the bits in OP1, it can really be done
5452 as a PLUS and we can associate. We do this by seeing if OP1
5453 can be safely shifted left C bits. */
5454 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5455 && GET_CODE (XEXP (op0
, 0)) == PLUS
5456 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5457 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5458 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5460 int count
= INTVAL (XEXP (op0
, 1));
5461 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5463 if (mask
>> count
== INTVAL (op1
)
5464 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5466 SUBST (XEXP (XEXP (op0
, 0), 1),
5467 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5474 /* If we are XORing two things that have no bits in common,
5475 convert them into an IOR. This helps to detect rotation encoded
5476 using those methods and possibly other simplifications. */
5478 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5479 && (nonzero_bits (op0
, mode
)
5480 & nonzero_bits (op1
, mode
)) == 0)
5481 return (gen_binary (IOR
, mode
, op0
, op1
));
5483 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5484 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5487 int num_negated
= 0;
5489 if (GET_CODE (op0
) == NOT
)
5490 num_negated
++, op0
= XEXP (op0
, 0);
5491 if (GET_CODE (op1
) == NOT
)
5492 num_negated
++, op1
= XEXP (op1
, 0);
5494 if (num_negated
== 2)
5496 SUBST (XEXP (x
, 0), op0
);
5497 SUBST (XEXP (x
, 1), op1
);
5499 else if (num_negated
== 1)
5501 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5505 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5506 correspond to a machine insn or result in further simplifications
5507 if B is a constant. */
5509 if (GET_CODE (op0
) == AND
5510 && rtx_equal_p (XEXP (op0
, 1), op1
)
5511 && ! side_effects_p (op1
))
5512 return gen_binary (AND
, mode
,
5513 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5516 else if (GET_CODE (op0
) == AND
5517 && rtx_equal_p (XEXP (op0
, 0), op1
)
5518 && ! side_effects_p (op1
))
5519 return gen_binary (AND
, mode
,
5520 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5523 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5524 comparison if STORE_FLAG_VALUE is 1. */
5525 if (STORE_FLAG_VALUE
== 1
5526 && op1
== const1_rtx
5527 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5528 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5532 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5533 is (lt foo (const_int 0)), so we can perform the above
5534 simplification if STORE_FLAG_VALUE is 1. */
5536 if (STORE_FLAG_VALUE
== 1
5537 && op1
== const1_rtx
5538 && GET_CODE (op0
) == LSHIFTRT
5539 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5540 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5541 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5543 /* (xor (comparison foo bar) (const_int sign-bit))
5544 when STORE_FLAG_VALUE is the sign bit. */
5545 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5546 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5547 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5548 && op1
== const_true_rtx
5549 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5550 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5563 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5564 operations" because they can be replaced with two more basic operations.
5565 ZERO_EXTEND is also considered "compound" because it can be replaced with
5566 an AND operation, which is simpler, though only one operation.
5568 The function expand_compound_operation is called with an rtx expression
5569 and will convert it to the appropriate shifts and AND operations,
5570 simplifying at each stage.
5572 The function make_compound_operation is called to convert an expression
5573 consisting of shifts and ANDs into the equivalent compound expression.
5574 It is the inverse of this function, loosely speaking. */
5577 expand_compound_operation (rtx x
)
5579 unsigned HOST_WIDE_INT pos
= 0, len
;
5581 unsigned int modewidth
;
5584 switch (GET_CODE (x
))
5589 /* We can't necessarily use a const_int for a multiword mode;
5590 it depends on implicitly extending the value.
5591 Since we don't know the right way to extend it,
5592 we can't tell whether the implicit way is right.
5594 Even for a mode that is no wider than a const_int,
5595 we can't win, because we need to sign extend one of its bits through
5596 the rest of it, and we don't know which bit. */
5597 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5600 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5601 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5602 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5603 reloaded. If not for that, MEM's would very rarely be safe.
5605 Reject MODEs bigger than a word, because we might not be able
5606 to reference a two-register group starting with an arbitrary register
5607 (and currently gen_lowpart might crash for a SUBREG). */
5609 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5612 /* Reject MODEs that aren't scalar integers because turning vector
5613 or complex modes into shifts causes problems. */
5615 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5618 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5619 /* If the inner object has VOIDmode (the only way this can happen
5620 is if it is an ASM_OPERANDS), we can't do anything since we don't
5621 know how much masking to do. */
5630 /* If the operand is a CLOBBER, just return it. */
5631 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5634 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5635 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5636 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5639 /* Reject MODEs that aren't scalar integers because turning vector
5640 or complex modes into shifts causes problems. */
5642 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5645 len
= INTVAL (XEXP (x
, 1));
5646 pos
= INTVAL (XEXP (x
, 2));
5648 /* If this goes outside the object being extracted, replace the object
5649 with a (use (mem ...)) construct that only combine understands
5650 and is used only for this purpose. */
5651 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5652 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5654 if (BITS_BIG_ENDIAN
)
5655 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5662 /* Convert sign extension to zero extension, if we know that the high
5663 bit is not set, as this is easier to optimize. It will be converted
5664 back to cheaper alternative in make_extraction. */
5665 if (GET_CODE (x
) == SIGN_EXTEND
5666 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5667 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5668 & ~(((unsigned HOST_WIDE_INT
)
5669 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5673 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5674 rtx temp2
= expand_compound_operation (temp
);
5676 /* Make sure this is a profitable operation. */
5677 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5679 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5685 /* We can optimize some special cases of ZERO_EXTEND. */
5686 if (GET_CODE (x
) == ZERO_EXTEND
)
5688 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5689 know that the last value didn't have any inappropriate bits
5691 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5692 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5693 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5694 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5695 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5696 return XEXP (XEXP (x
, 0), 0);
5698 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5699 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5700 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5701 && subreg_lowpart_p (XEXP (x
, 0))
5702 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5703 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5704 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5705 return SUBREG_REG (XEXP (x
, 0));
5707 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5708 is a comparison and STORE_FLAG_VALUE permits. This is like
5709 the first case, but it works even when GET_MODE (x) is larger
5710 than HOST_WIDE_INT. */
5711 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5712 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5713 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5714 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5715 <= HOST_BITS_PER_WIDE_INT
)
5716 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5717 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5718 return XEXP (XEXP (x
, 0), 0);
5720 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5721 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5722 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5723 && subreg_lowpart_p (XEXP (x
, 0))
5724 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5725 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5726 <= HOST_BITS_PER_WIDE_INT
)
5727 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5728 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5729 return SUBREG_REG (XEXP (x
, 0));
5733 /* If we reach here, we want to return a pair of shifts. The inner
5734 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5735 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5736 logical depending on the value of UNSIGNEDP.
5738 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5739 converted into an AND of a shift.
5741 We must check for the case where the left shift would have a negative
5742 count. This can happen in a case like (x >> 31) & 255 on machines
5743 that can't shift by a constant. On those machines, we would first
5744 combine the shift with the AND to produce a variable-position
5745 extraction. Then the constant of 31 would be substituted in to produce
5746 a such a position. */
5748 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5749 if (modewidth
+ len
>= pos
)
5750 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5752 simplify_shift_const (NULL_RTX
, ASHIFT
,
5755 modewidth
- pos
- len
),
5758 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5759 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5760 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5763 ((HOST_WIDE_INT
) 1 << len
) - 1);
5765 /* Any other cases we can't handle. */
5768 /* If we couldn't do this for some reason, return the original
5770 if (GET_CODE (tem
) == CLOBBER
)
5776 /* X is a SET which contains an assignment of one object into
5777 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5778 or certain SUBREGS). If possible, convert it into a series of
5781 We half-heartedly support variable positions, but do not at all
5782 support variable lengths. */
5785 expand_field_assignment (rtx x
)
5788 rtx pos
; /* Always counts from low bit. */
5791 enum machine_mode compute_mode
;
5793 /* Loop until we find something we can't simplify. */
5796 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5797 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5799 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5800 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5801 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5803 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5804 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5806 inner
= XEXP (SET_DEST (x
), 0);
5807 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5808 pos
= XEXP (SET_DEST (x
), 2);
5810 /* If the position is constant and spans the width of INNER,
5811 surround INNER with a USE to indicate this. */
5812 if (GET_CODE (pos
) == CONST_INT
5813 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5814 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5816 if (BITS_BIG_ENDIAN
)
5818 if (GET_CODE (pos
) == CONST_INT
)
5819 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5821 else if (GET_CODE (pos
) == MINUS
5822 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5823 && (INTVAL (XEXP (pos
, 1))
5824 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5825 /* If position is ADJUST - X, new position is X. */
5826 pos
= XEXP (pos
, 0);
5828 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5829 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5835 /* A SUBREG between two modes that occupy the same numbers of words
5836 can be done by moving the SUBREG to the source. */
5837 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5838 /* We need SUBREGs to compute nonzero_bits properly. */
5839 && nonzero_sign_valid
5840 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5841 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5842 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5843 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5845 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5846 gen_lowpart_for_combine
5847 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5854 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5855 inner
= SUBREG_REG (inner
);
5857 compute_mode
= GET_MODE (inner
);
5859 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5860 if (! SCALAR_INT_MODE_P (compute_mode
))
5862 enum machine_mode imode
;
5864 /* Don't do anything for vector or complex integral types. */
5865 if (! FLOAT_MODE_P (compute_mode
))
5868 /* Try to find an integral mode to pun with. */
5869 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5870 if (imode
== BLKmode
)
5873 compute_mode
= imode
;
5874 inner
= gen_lowpart_for_combine (imode
, inner
);
5877 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5878 if (len
< HOST_BITS_PER_WIDE_INT
)
5879 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5883 /* Now compute the equivalent expression. Make a copy of INNER
5884 for the SET_DEST in case it is a MEM into which we will substitute;
5885 we don't want shared RTL in that case. */
5887 (VOIDmode
, copy_rtx (inner
),
5888 gen_binary (IOR
, compute_mode
,
5889 gen_binary (AND
, compute_mode
,
5890 simplify_gen_unary (NOT
, compute_mode
,
5896 gen_binary (ASHIFT
, compute_mode
,
5897 gen_binary (AND
, compute_mode
,
5898 gen_lowpart_for_combine
5899 (compute_mode
, SET_SRC (x
)),
5907 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5908 it is an RTX that represents a variable starting position; otherwise,
5909 POS is the (constant) starting bit position (counted from the LSB).
5911 INNER may be a USE. This will occur when we started with a bitfield
5912 that went outside the boundary of the object in memory, which is
5913 allowed on most machines. To isolate this case, we produce a USE
5914 whose mode is wide enough and surround the MEM with it. The only
5915 code that understands the USE is this routine. If it is not removed,
5916 it will cause the resulting insn not to match.
5918 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5921 IN_DEST is nonzero if this is a reference in the destination of a
5922 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5923 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5926 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5927 ZERO_EXTRACT should be built even for bits starting at bit 0.
5929 MODE is the desired mode of the result (if IN_DEST == 0).
5931 The result is an RTX for the extraction or NULL_RTX if the target
5935 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5936 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5937 int in_dest
, int in_compare
)
5939 /* This mode describes the size of the storage area
5940 to fetch the overall value from. Within that, we
5941 ignore the POS lowest bits, etc. */
5942 enum machine_mode is_mode
= GET_MODE (inner
);
5943 enum machine_mode inner_mode
;
5944 enum machine_mode wanted_inner_mode
= byte_mode
;
5945 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5946 enum machine_mode pos_mode
= word_mode
;
5947 enum machine_mode extraction_mode
= word_mode
;
5948 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5951 rtx orig_pos_rtx
= pos_rtx
;
5952 HOST_WIDE_INT orig_pos
;
5954 /* Get some information about INNER and get the innermost object. */
5955 if (GET_CODE (inner
) == USE
)
5956 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5957 /* We don't need to adjust the position because we set up the USE
5958 to pretend that it was a full-word object. */
5959 spans_byte
= 1, inner
= XEXP (inner
, 0);
5960 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5962 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5963 consider just the QI as the memory to extract from.
5964 The subreg adds or removes high bits; its mode is
5965 irrelevant to the meaning of this extraction,
5966 since POS and LEN count from the lsb. */
5967 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5968 is_mode
= GET_MODE (SUBREG_REG (inner
));
5969 inner
= SUBREG_REG (inner
);
5971 else if (GET_CODE (inner
) == ASHIFT
5972 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5973 && pos_rtx
== 0 && pos
== 0
5974 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
5976 /* We're extracting the least significant bits of an rtx
5977 (ashift X (const_int C)), where LEN > C. Extract the
5978 least significant (LEN - C) bits of X, giving an rtx
5979 whose mode is MODE, then shift it left C times. */
5980 new = make_extraction (mode
, XEXP (inner
, 0),
5981 0, 0, len
- INTVAL (XEXP (inner
, 1)),
5982 unsignedp
, in_dest
, in_compare
);
5984 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
5987 inner_mode
= GET_MODE (inner
);
5989 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5990 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5992 /* See if this can be done without an extraction. We never can if the
5993 width of the field is not the same as that of some integer mode. For
5994 registers, we can only avoid the extraction if the position is at the
5995 low-order bit and this is either not in the destination or we have the
5996 appropriate STRICT_LOW_PART operation available.
5998 For MEM, we can avoid an extract if the field starts on an appropriate
5999 boundary and we can change the mode of the memory reference. However,
6000 we cannot directly access the MEM if we have a USE and the underlying
6001 MEM is not TMODE. This combination means that MEM was being used in a
6002 context where bits outside its mode were being referenced; that is only
6003 valid in bit-field insns. */
6005 if (tmode
!= BLKmode
6006 && ! (spans_byte
&& inner_mode
!= tmode
)
6007 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6008 && GET_CODE (inner
) != MEM
6010 || (GET_CODE (inner
) == REG
6011 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6012 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6014 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6015 : BITS_PER_UNIT
)) == 0
6016 /* We can't do this if we are widening INNER_MODE (it
6017 may not be aligned, for one thing). */
6018 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6019 && (inner_mode
== tmode
6020 || (! mode_dependent_address_p (XEXP (inner
, 0))
6021 && ! MEM_VOLATILE_P (inner
))))))
6023 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6024 field. If the original and current mode are the same, we need not
6025 adjust the offset. Otherwise, we do if bytes big endian.
6027 If INNER is not a MEM, get a piece consisting of just the field
6028 of interest (in this case POS % BITS_PER_WORD must be 0). */
6030 if (GET_CODE (inner
) == MEM
)
6032 HOST_WIDE_INT offset
;
6034 /* POS counts from lsb, but make OFFSET count in memory order. */
6035 if (BYTES_BIG_ENDIAN
)
6036 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6038 offset
= pos
/ BITS_PER_UNIT
;
6040 new = adjust_address_nv (inner
, tmode
, offset
);
6042 else if (GET_CODE (inner
) == REG
)
6044 if (tmode
!= inner_mode
)
6048 /* We can't call gen_lowpart_for_combine here since we always want
6049 a SUBREG and it would sometimes return a new hard register. */
6050 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6052 if (WORDS_BIG_ENDIAN
6053 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6054 final_word
= ((GET_MODE_SIZE (inner_mode
)
6055 - GET_MODE_SIZE (tmode
))
6056 / UNITS_PER_WORD
) - final_word
;
6058 final_word
*= UNITS_PER_WORD
;
6059 if (BYTES_BIG_ENDIAN
&&
6060 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6061 final_word
+= (GET_MODE_SIZE (inner_mode
)
6062 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6064 /* Avoid creating invalid subregs, for example when
6065 simplifying (x>>32)&255. */
6066 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6069 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6072 new = gen_lowpart_for_combine (tmode
, inner
);
6078 new = force_to_mode (inner
, tmode
,
6079 len
>= HOST_BITS_PER_WIDE_INT
6080 ? ~(unsigned HOST_WIDE_INT
) 0
6081 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6084 /* If this extraction is going into the destination of a SET,
6085 make a STRICT_LOW_PART unless we made a MEM. */
6088 return (GET_CODE (new) == MEM
? new
6089 : (GET_CODE (new) != SUBREG
6090 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6091 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6096 if (GET_CODE (new) == CONST_INT
)
6097 return gen_int_mode (INTVAL (new), mode
);
6099 /* If we know that no extraneous bits are set, and that the high
6100 bit is not set, convert the extraction to the cheaper of
6101 sign and zero extension, that are equivalent in these cases. */
6102 if (flag_expensive_optimizations
6103 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6104 && ((nonzero_bits (new, tmode
)
6105 & ~(((unsigned HOST_WIDE_INT
)
6106 GET_MODE_MASK (tmode
))
6110 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6111 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6113 /* Prefer ZERO_EXTENSION, since it gives more information to
6115 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6120 /* Otherwise, sign- or zero-extend unless we already are in the
6123 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6127 /* Unless this is a COMPARE or we have a funny memory reference,
6128 don't do anything with zero-extending field extracts starting at
6129 the low-order bit since they are simple AND operations. */
6130 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6131 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6134 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6135 we would be spanning bytes or if the position is not a constant and the
6136 length is not 1. In all other cases, we would only be going outside
6137 our object in cases when an original shift would have been
6139 if (! spans_byte
&& GET_CODE (inner
) == MEM
6140 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6141 || (pos_rtx
!= 0 && len
!= 1)))
6144 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6145 and the mode for the result. */
6146 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6148 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6149 pos_mode
= mode_for_extraction (EP_insv
, 2);
6150 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6153 if (! in_dest
&& unsignedp
6154 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6156 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6157 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6158 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6161 if (! in_dest
&& ! unsignedp
6162 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6164 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6165 pos_mode
= mode_for_extraction (EP_extv
, 3);
6166 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6169 /* Never narrow an object, since that might not be safe. */
6171 if (mode
!= VOIDmode
6172 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6173 extraction_mode
= mode
;
6175 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6176 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6177 pos_mode
= GET_MODE (pos_rtx
);
6179 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6180 if we have to change the mode of memory and cannot, the desired mode is
6182 if (GET_CODE (inner
) != MEM
)
6183 wanted_inner_mode
= wanted_inner_reg_mode
;
6184 else if (inner_mode
!= wanted_inner_mode
6185 && (mode_dependent_address_p (XEXP (inner
, 0))
6186 || MEM_VOLATILE_P (inner
)))
6187 wanted_inner_mode
= extraction_mode
;
6191 if (BITS_BIG_ENDIAN
)
6193 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6194 BITS_BIG_ENDIAN style. If position is constant, compute new
6195 position. Otherwise, build subtraction.
6196 Note that POS is relative to the mode of the original argument.
6197 If it's a MEM we need to recompute POS relative to that.
6198 However, if we're extracting from (or inserting into) a register,
6199 we want to recompute POS relative to wanted_inner_mode. */
6200 int width
= (GET_CODE (inner
) == MEM
6201 ? GET_MODE_BITSIZE (is_mode
)
6202 : GET_MODE_BITSIZE (wanted_inner_mode
));
6205 pos
= width
- len
- pos
;
6208 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6209 /* POS may be less than 0 now, but we check for that below.
6210 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6213 /* If INNER has a wider mode, make it smaller. If this is a constant
6214 extract, try to adjust the byte to point to the byte containing
6216 if (wanted_inner_mode
!= VOIDmode
6217 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6218 && ((GET_CODE (inner
) == MEM
6219 && (inner_mode
== wanted_inner_mode
6220 || (! mode_dependent_address_p (XEXP (inner
, 0))
6221 && ! MEM_VOLATILE_P (inner
))))))
6225 /* The computations below will be correct if the machine is big
6226 endian in both bits and bytes or little endian in bits and bytes.
6227 If it is mixed, we must adjust. */
6229 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6230 adjust OFFSET to compensate. */
6231 if (BYTES_BIG_ENDIAN
6233 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6234 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6236 /* If this is a constant position, we can move to the desired byte. */
6239 offset
+= pos
/ BITS_PER_UNIT
;
6240 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6243 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6245 && is_mode
!= wanted_inner_mode
)
6246 offset
= (GET_MODE_SIZE (is_mode
)
6247 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6249 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6250 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6253 /* If INNER is not memory, we can always get it into the proper mode. If we
6254 are changing its mode, POS must be a constant and smaller than the size
6256 else if (GET_CODE (inner
) != MEM
)
6258 if (GET_MODE (inner
) != wanted_inner_mode
6260 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6263 inner
= force_to_mode (inner
, wanted_inner_mode
,
6265 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6266 ? ~(unsigned HOST_WIDE_INT
) 0
6267 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6272 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6273 have to zero extend. Otherwise, we can just use a SUBREG. */
6275 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6277 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6279 /* If we know that no extraneous bits are set, and that the high
6280 bit is not set, convert extraction to cheaper one - either
6281 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6283 if (flag_expensive_optimizations
6284 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6285 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6286 & ~(((unsigned HOST_WIDE_INT
)
6287 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6291 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6293 /* Prefer ZERO_EXTENSION, since it gives more information to
6295 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6300 else if (pos_rtx
!= 0
6301 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6302 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6304 /* Make POS_RTX unless we already have it and it is correct. If we don't
6305 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6307 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6308 pos_rtx
= orig_pos_rtx
;
6310 else if (pos_rtx
== 0)
6311 pos_rtx
= GEN_INT (pos
);
6313 /* Make the required operation. See if we can use existing rtx. */
6314 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6315 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6317 new = gen_lowpart_for_combine (mode
, new);
6322 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6323 with any other operations in X. Return X without that shift if so. */
6326 extract_left_shift (rtx x
, int count
)
6328 enum rtx_code code
= GET_CODE (x
);
6329 enum machine_mode mode
= GET_MODE (x
);
6335 /* This is the shift itself. If it is wide enough, we will return
6336 either the value being shifted if the shift count is equal to
6337 COUNT or a shift for the difference. */
6338 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6339 && INTVAL (XEXP (x
, 1)) >= count
)
6340 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6341 INTVAL (XEXP (x
, 1)) - count
);
6345 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6346 return simplify_gen_unary (code
, mode
, tem
, mode
);
6350 case PLUS
: case IOR
: case XOR
: case AND
:
6351 /* If we can safely shift this constant and we find the inner shift,
6352 make a new operation. */
6353 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6354 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6355 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6356 return gen_binary (code
, mode
, tem
,
6357 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6368 /* Look at the expression rooted at X. Look for expressions
6369 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6370 Form these expressions.
6372 Return the new rtx, usually just X.
6374 Also, for machines like the VAX that don't have logical shift insns,
6375 try to convert logical to arithmetic shift operations in cases where
6376 they are equivalent. This undoes the canonicalizations to logical
6377 shifts done elsewhere.
6379 We try, as much as possible, to re-use rtl expressions to save memory.
6381 IN_CODE says what kind of expression we are processing. Normally, it is
6382 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6383 being kludges), it is MEM. When processing the arguments of a comparison
6384 or a COMPARE against zero, it is COMPARE. */
6387 make_compound_operation (rtx x
, enum rtx_code in_code
)
6389 enum rtx_code code
= GET_CODE (x
);
6390 enum machine_mode mode
= GET_MODE (x
);
6391 int mode_width
= GET_MODE_BITSIZE (mode
);
6393 enum rtx_code next_code
;
6399 /* Select the code to be used in recursive calls. Once we are inside an
6400 address, we stay there. If we have a comparison, set to COMPARE,
6401 but once inside, go back to our default of SET. */
6403 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6404 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6405 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6406 : in_code
== COMPARE
? SET
: in_code
);
6408 /* Process depending on the code of this operation. If NEW is set
6409 nonzero, it will be returned. */
6414 /* Convert shifts by constants into multiplications if inside
6416 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6417 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6418 && INTVAL (XEXP (x
, 1)) >= 0)
6420 new = make_compound_operation (XEXP (x
, 0), next_code
);
6421 new = gen_rtx_MULT (mode
, new,
6422 GEN_INT ((HOST_WIDE_INT
) 1
6423 << INTVAL (XEXP (x
, 1))));
6428 /* If the second operand is not a constant, we can't do anything
6430 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6433 /* If the constant is a power of two minus one and the first operand
6434 is a logical right shift, make an extraction. */
6435 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6436 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6438 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6439 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6440 0, in_code
== COMPARE
);
6443 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6444 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6445 && subreg_lowpart_p (XEXP (x
, 0))
6446 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6447 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6449 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6451 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6452 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6453 0, in_code
== COMPARE
);
6455 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6456 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6457 || GET_CODE (XEXP (x
, 0)) == IOR
)
6458 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6459 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6460 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6462 /* Apply the distributive law, and then try to make extractions. */
6463 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6464 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6466 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6468 new = make_compound_operation (new, in_code
);
6471 /* If we are have (and (rotate X C) M) and C is larger than the number
6472 of bits in M, this is an extraction. */
6474 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6475 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6476 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6477 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6479 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6480 new = make_extraction (mode
, new,
6481 (GET_MODE_BITSIZE (mode
)
6482 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6483 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6486 /* On machines without logical shifts, if the operand of the AND is
6487 a logical shift and our mask turns off all the propagated sign
6488 bits, we can replace the logical shift with an arithmetic shift. */
6489 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6490 && !have_insn_for (LSHIFTRT
, mode
)
6491 && have_insn_for (ASHIFTRT
, mode
)
6492 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6493 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6494 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6495 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6497 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6499 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6500 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6502 gen_rtx_ASHIFTRT (mode
,
6503 make_compound_operation
6504 (XEXP (XEXP (x
, 0), 0), next_code
),
6505 XEXP (XEXP (x
, 0), 1)));
6508 /* If the constant is one less than a power of two, this might be
6509 representable by an extraction even if no shift is present.
6510 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6511 we are in a COMPARE. */
6512 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6513 new = make_extraction (mode
,
6514 make_compound_operation (XEXP (x
, 0),
6516 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6518 /* If we are in a comparison and this is an AND with a power of two,
6519 convert this into the appropriate bit extract. */
6520 else if (in_code
== COMPARE
6521 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6522 new = make_extraction (mode
,
6523 make_compound_operation (XEXP (x
, 0),
6525 i
, NULL_RTX
, 1, 1, 0, 1);
6530 /* If the sign bit is known to be zero, replace this with an
6531 arithmetic shift. */
6532 if (have_insn_for (ASHIFTRT
, mode
)
6533 && ! have_insn_for (LSHIFTRT
, mode
)
6534 && mode_width
<= HOST_BITS_PER_WIDE_INT
6535 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6537 new = gen_rtx_ASHIFTRT (mode
,
6538 make_compound_operation (XEXP (x
, 0),
6544 /* ... fall through ... */
6550 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6551 this is a SIGN_EXTRACT. */
6552 if (GET_CODE (rhs
) == CONST_INT
6553 && GET_CODE (lhs
) == ASHIFT
6554 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6555 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6557 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6558 new = make_extraction (mode
, new,
6559 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6560 NULL_RTX
, mode_width
- INTVAL (rhs
),
6561 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6565 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6566 If so, try to merge the shifts into a SIGN_EXTEND. We could
6567 also do this for some cases of SIGN_EXTRACT, but it doesn't
6568 seem worth the effort; the case checked for occurs on Alpha. */
6570 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6571 && ! (GET_CODE (lhs
) == SUBREG
6572 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6573 && GET_CODE (rhs
) == CONST_INT
6574 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6575 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6576 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6577 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6578 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6583 /* Call ourselves recursively on the inner expression. If we are
6584 narrowing the object and it has a different RTL code from
6585 what it originally did, do this SUBREG as a force_to_mode. */
6587 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6588 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6589 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6590 && subreg_lowpart_p (x
))
6592 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6595 /* If we have something other than a SUBREG, we might have
6596 done an expansion, so rerun ourselves. */
6597 if (GET_CODE (newer
) != SUBREG
)
6598 newer
= make_compound_operation (newer
, in_code
);
6603 /* If this is a paradoxical subreg, and the new code is a sign or
6604 zero extension, omit the subreg and widen the extension. If it
6605 is a regular subreg, we can still get rid of the subreg by not
6606 widening so much, or in fact removing the extension entirely. */
6607 if ((GET_CODE (tem
) == SIGN_EXTEND
6608 || GET_CODE (tem
) == ZERO_EXTEND
)
6609 && subreg_lowpart_p (x
))
6611 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6612 || (GET_MODE_SIZE (mode
) >
6613 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6615 if (! SCALAR_INT_MODE_P (mode
))
6617 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6620 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6631 x
= gen_lowpart_for_combine (mode
, new);
6632 code
= GET_CODE (x
);
6635 /* Now recursively process each operand of this operation. */
6636 fmt
= GET_RTX_FORMAT (code
);
6637 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6640 new = make_compound_operation (XEXP (x
, i
), next_code
);
6641 SUBST (XEXP (x
, i
), new);
6647 /* Given M see if it is a value that would select a field of bits
6648 within an item, but not the entire word. Return -1 if not.
6649 Otherwise, return the starting position of the field, where 0 is the
6652 *PLEN is set to the length of the field. */
6655 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6657 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6658 int pos
= exact_log2 (m
& -m
);
6664 /* Now shift off the low-order zero bits and see if we have a power of
6666 len
= exact_log2 ((m
>> pos
) + 1);
6675 /* See if X can be simplified knowing that we will only refer to it in
6676 MODE and will only refer to those bits that are nonzero in MASK.
6677 If other bits are being computed or if masking operations are done
6678 that select a superset of the bits in MASK, they can sometimes be
6681 Return a possibly simplified expression, but always convert X to
6682 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6684 Also, if REG is nonzero and X is a register equal in value to REG,
6687 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6688 are all off in X. This is used when X will be complemented, by either
6689 NOT, NEG, or XOR. */
6692 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6693 rtx reg
, int just_select
)
6695 enum rtx_code code
= GET_CODE (x
);
6696 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6697 enum machine_mode op_mode
;
6698 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6701 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6702 code below will do the wrong thing since the mode of such an
6703 expression is VOIDmode.
6705 Also do nothing if X is a CLOBBER; this can happen if X was
6706 the return value from a call to gen_lowpart_for_combine. */
6707 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6710 /* We want to perform the operation is its present mode unless we know
6711 that the operation is valid in MODE, in which case we do the operation
6713 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6714 && have_insn_for (code
, mode
))
6715 ? mode
: GET_MODE (x
));
6717 /* It is not valid to do a right-shift in a narrower mode
6718 than the one it came in with. */
6719 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6720 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6721 op_mode
= GET_MODE (x
);
6723 /* Truncate MASK to fit OP_MODE. */
6725 mask
&= GET_MODE_MASK (op_mode
);
6727 /* When we have an arithmetic operation, or a shift whose count we
6728 do not know, we need to assume that all bits up to the highest-order
6729 bit in MASK will be needed. This is how we form such a mask. */
6730 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6731 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6733 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6736 /* Determine what bits of X are guaranteed to be (non)zero. */
6737 nonzero
= nonzero_bits (x
, mode
);
6739 /* If none of the bits in X are needed, return a zero. */
6740 if (! just_select
&& (nonzero
& mask
) == 0)
6743 /* If X is a CONST_INT, return a new one. Do this here since the
6744 test below will fail. */
6745 if (GET_CODE (x
) == CONST_INT
)
6747 if (SCALAR_INT_MODE_P (mode
))
6748 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6751 x
= GEN_INT (INTVAL (x
) & mask
);
6752 return gen_lowpart_common (mode
, x
);
6756 /* If X is narrower than MODE and we want all the bits in X's mode, just
6757 get X in the proper mode. */
6758 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6759 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6760 return gen_lowpart_for_combine (mode
, x
);
6762 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6763 MASK are already known to be zero in X, we need not do anything. */
6764 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6770 /* If X is a (clobber (const_int)), return it since we know we are
6771 generating something that won't match. */
6775 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6776 spanned the boundary of the MEM. If we are now masking so it is
6777 within that boundary, we don't need the USE any more. */
6778 if (! BITS_BIG_ENDIAN
6779 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6780 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6787 x
= expand_compound_operation (x
);
6788 if (GET_CODE (x
) != code
)
6789 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6793 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6794 || rtx_equal_p (reg
, get_last_value (x
))))
6799 if (subreg_lowpart_p (x
)
6800 /* We can ignore the effect of this SUBREG if it narrows the mode or
6801 if the constant masks to zero all the bits the mode doesn't
6803 && ((GET_MODE_SIZE (GET_MODE (x
))
6804 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6806 & GET_MODE_MASK (GET_MODE (x
))
6807 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6808 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6812 /* If this is an AND with a constant, convert it into an AND
6813 whose constant is the AND of that constant with MASK. If it
6814 remains an AND of MASK, delete it since it is redundant. */
6816 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6818 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6819 mask
& INTVAL (XEXP (x
, 1)));
6821 /* If X is still an AND, see if it is an AND with a mask that
6822 is just some low-order bits. If so, and it is MASK, we don't
6825 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6826 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6830 /* If it remains an AND, try making another AND with the bits
6831 in the mode mask that aren't in MASK turned on. If the
6832 constant in the AND is wide enough, this might make a
6833 cheaper constant. */
6835 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6836 && GET_MODE_MASK (GET_MODE (x
)) != mask
6837 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6839 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6840 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6841 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6844 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6845 number, sign extend it. */
6846 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6847 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6848 cval
|= (HOST_WIDE_INT
) -1 << width
;
6850 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6851 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6861 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6862 low-order bits (as in an alignment operation) and FOO is already
6863 aligned to that boundary, mask C1 to that boundary as well.
6864 This may eliminate that PLUS and, later, the AND. */
6867 unsigned int width
= GET_MODE_BITSIZE (mode
);
6868 unsigned HOST_WIDE_INT smask
= mask
;
6870 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6871 number, sign extend it. */
6873 if (width
< HOST_BITS_PER_WIDE_INT
6874 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6875 smask
|= (HOST_WIDE_INT
) -1 << width
;
6877 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6878 && exact_log2 (- smask
) >= 0
6879 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6880 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6881 return force_to_mode (plus_constant (XEXP (x
, 0),
6882 (INTVAL (XEXP (x
, 1)) & smask
)),
6883 mode
, smask
, reg
, next_select
);
6886 /* ... fall through ... */
6889 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6890 most significant bit in MASK since carries from those bits will
6891 affect the bits we are interested in. */
6896 /* If X is (minus C Y) where C's least set bit is larger than any bit
6897 in the mask, then we may replace with (neg Y). */
6898 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6899 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6900 & -INTVAL (XEXP (x
, 0))))
6903 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6905 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6908 /* Similarly, if C contains every bit in the fuller_mask, then we may
6909 replace with (not Y). */
6910 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6911 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6912 == INTVAL (XEXP (x
, 0))))
6914 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6915 XEXP (x
, 1), GET_MODE (x
));
6916 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6924 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6925 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6926 operation which may be a bitfield extraction. Ensure that the
6927 constant we form is not wider than the mode of X. */
6929 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6930 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6931 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6932 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6933 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6934 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6935 + floor_log2 (INTVAL (XEXP (x
, 1))))
6936 < GET_MODE_BITSIZE (GET_MODE (x
)))
6937 && (INTVAL (XEXP (x
, 1))
6938 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6940 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6941 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6942 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6943 XEXP (XEXP (x
, 0), 0), temp
);
6944 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6945 XEXP (XEXP (x
, 0), 1));
6946 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6950 /* For most binary operations, just propagate into the operation and
6951 change the mode if we have an operation of that mode. */
6953 op0
= gen_lowpart_for_combine (op_mode
,
6954 force_to_mode (XEXP (x
, 0), mode
, mask
,
6956 op1
= gen_lowpart_for_combine (op_mode
,
6957 force_to_mode (XEXP (x
, 1), mode
, mask
,
6960 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6961 x
= gen_binary (code
, op_mode
, op0
, op1
);
6965 /* For left shifts, do the same, but just for the first operand.
6966 However, we cannot do anything with shifts where we cannot
6967 guarantee that the counts are smaller than the size of the mode
6968 because such a count will have a different meaning in a
6971 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6972 && INTVAL (XEXP (x
, 1)) >= 0
6973 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6974 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6975 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6976 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6979 /* If the shift count is a constant and we can do arithmetic in
6980 the mode of the shift, refine which bits we need. Otherwise, use the
6981 conservative form of the mask. */
6982 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6983 && INTVAL (XEXP (x
, 1)) >= 0
6984 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6985 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6986 mask
>>= INTVAL (XEXP (x
, 1));
6990 op0
= gen_lowpart_for_combine (op_mode
,
6991 force_to_mode (XEXP (x
, 0), op_mode
,
6992 mask
, reg
, next_select
));
6994 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6995 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6999 /* Here we can only do something if the shift count is a constant,
7000 this shift constant is valid for the host, and we can do arithmetic
7003 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7004 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7005 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7007 rtx inner
= XEXP (x
, 0);
7008 unsigned HOST_WIDE_INT inner_mask
;
7010 /* Select the mask of the bits we need for the shift operand. */
7011 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7013 /* We can only change the mode of the shift if we can do arithmetic
7014 in the mode of the shift and INNER_MASK is no wider than the
7015 width of OP_MODE. */
7016 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7017 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7018 op_mode
= GET_MODE (x
);
7020 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7022 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7023 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7026 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7027 shift and AND produces only copies of the sign bit (C2 is one less
7028 than a power of two), we can do this with just a shift. */
7030 if (GET_CODE (x
) == LSHIFTRT
7031 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7032 /* The shift puts one of the sign bit copies in the least significant
7034 && ((INTVAL (XEXP (x
, 1))
7035 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7036 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7037 && exact_log2 (mask
+ 1) >= 0
7038 /* Number of bits left after the shift must be more than the mask
7040 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7041 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7042 /* Must be more sign bit copies than the mask needs. */
7043 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7044 >= exact_log2 (mask
+ 1)))
7045 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7046 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7047 - exact_log2 (mask
+ 1)));
7052 /* If we are just looking for the sign bit, we don't need this shift at
7053 all, even if it has a variable count. */
7054 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7055 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7056 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7057 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7059 /* If this is a shift by a constant, get a mask that contains those bits
7060 that are not copies of the sign bit. We then have two cases: If
7061 MASK only includes those bits, this can be a logical shift, which may
7062 allow simplifications. If MASK is a single-bit field not within
7063 those bits, we are requesting a copy of the sign bit and hence can
7064 shift the sign bit to the appropriate location. */
7066 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7067 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7071 /* If the considered data is wider than HOST_WIDE_INT, we can't
7072 represent a mask for all its bits in a single scalar.
7073 But we only care about the lower bits, so calculate these. */
7075 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7077 nonzero
= ~(HOST_WIDE_INT
) 0;
7079 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7080 is the number of bits a full-width mask would have set.
7081 We need only shift if these are fewer than nonzero can
7082 hold. If not, we must keep all bits set in nonzero. */
7084 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7085 < HOST_BITS_PER_WIDE_INT
)
7086 nonzero
>>= INTVAL (XEXP (x
, 1))
7087 + HOST_BITS_PER_WIDE_INT
7088 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7092 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7093 nonzero
>>= INTVAL (XEXP (x
, 1));
7096 if ((mask
& ~nonzero
) == 0
7097 || (i
= exact_log2 (mask
)) >= 0)
7099 x
= simplify_shift_const
7100 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7101 i
< 0 ? INTVAL (XEXP (x
, 1))
7102 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7104 if (GET_CODE (x
) != ASHIFTRT
)
7105 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7109 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7110 even if the shift count isn't a constant. */
7112 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7116 /* If this is a zero- or sign-extension operation that just affects bits
7117 we don't care about, remove it. Be sure the call above returned
7118 something that is still a shift. */
7120 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7121 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7122 && INTVAL (XEXP (x
, 1)) >= 0
7123 && (INTVAL (XEXP (x
, 1))
7124 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7125 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7126 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7127 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7134 /* If the shift count is constant and we can do computations
7135 in the mode of X, compute where the bits we care about are.
7136 Otherwise, we can't do anything. Don't change the mode of
7137 the shift or propagate MODE into the shift, though. */
7138 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7139 && INTVAL (XEXP (x
, 1)) >= 0)
7141 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7142 GET_MODE (x
), GEN_INT (mask
),
7144 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7146 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7147 INTVAL (temp
), reg
, next_select
));
7152 /* If we just want the low-order bit, the NEG isn't needed since it
7153 won't change the low-order bit. */
7155 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7157 /* We need any bits less significant than the most significant bit in
7158 MASK since carries from those bits will affect the bits we are
7164 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7165 same as the XOR case above. Ensure that the constant we form is not
7166 wider than the mode of X. */
7168 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7169 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7170 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7171 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7172 < GET_MODE_BITSIZE (GET_MODE (x
)))
7173 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7175 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7177 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7178 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7180 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7183 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7184 use the full mask inside the NOT. */
7188 op0
= gen_lowpart_for_combine (op_mode
,
7189 force_to_mode (XEXP (x
, 0), mode
, mask
,
7191 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7192 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7196 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7197 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7198 which is equal to STORE_FLAG_VALUE. */
7199 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7200 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7201 && (nonzero_bits (XEXP (x
, 0), mode
)
7202 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7203 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7208 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7209 written in a narrower mode. We play it safe and do not do so. */
7212 gen_lowpart_for_combine (GET_MODE (x
),
7213 force_to_mode (XEXP (x
, 1), mode
,
7214 mask
, reg
, next_select
)));
7216 gen_lowpart_for_combine (GET_MODE (x
),
7217 force_to_mode (XEXP (x
, 2), mode
,
7218 mask
, reg
, next_select
)));
7225 /* Ensure we return a value of the proper mode. */
7226 return gen_lowpart_for_combine (mode
, x
);
7229 /* Return nonzero if X is an expression that has one of two values depending on
7230 whether some other value is zero or nonzero. In that case, we return the
7231 value that is being tested, *PTRUE is set to the value if the rtx being
7232 returned has a nonzero value, and *PFALSE is set to the other alternative.
7234 If we return zero, we set *PTRUE and *PFALSE to X. */
7237 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7239 enum machine_mode mode
= GET_MODE (x
);
7240 enum rtx_code code
= GET_CODE (x
);
7241 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7242 unsigned HOST_WIDE_INT nz
;
7244 /* If we are comparing a value against zero, we are done. */
7245 if ((code
== NE
|| code
== EQ
)
7246 && XEXP (x
, 1) == const0_rtx
)
7248 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7249 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7253 /* If this is a unary operation whose operand has one of two values, apply
7254 our opcode to compute those values. */
7255 else if (GET_RTX_CLASS (code
) == '1'
7256 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7258 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7259 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7260 GET_MODE (XEXP (x
, 0)));
7264 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7265 make can't possibly match and would suppress other optimizations. */
7266 else if (code
== COMPARE
)
7269 /* If this is a binary operation, see if either side has only one of two
7270 values. If either one does or if both do and they are conditional on
7271 the same value, compute the new true and false values. */
7272 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7273 || GET_RTX_CLASS (code
) == '<')
7275 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7276 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7278 if ((cond0
!= 0 || cond1
!= 0)
7279 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7281 /* If if_then_else_cond returned zero, then true/false are the
7282 same rtl. We must copy one of them to prevent invalid rtl
7285 true0
= copy_rtx (true0
);
7286 else if (cond1
== 0)
7287 true1
= copy_rtx (true1
);
7289 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7290 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7291 return cond0
? cond0
: cond1
;
7294 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7295 operands is zero when the other is nonzero, and vice-versa,
7296 and STORE_FLAG_VALUE is 1 or -1. */
7298 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7299 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7301 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7303 rtx op0
= XEXP (XEXP (x
, 0), 1);
7304 rtx op1
= XEXP (XEXP (x
, 1), 1);
7306 cond0
= XEXP (XEXP (x
, 0), 0);
7307 cond1
= XEXP (XEXP (x
, 1), 0);
7309 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7310 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7311 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7312 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7313 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7314 || ((swap_condition (GET_CODE (cond0
))
7315 == combine_reversed_comparison_code (cond1
))
7316 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7317 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7318 && ! side_effects_p (x
))
7320 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7321 *pfalse
= gen_binary (MULT
, mode
,
7323 ? simplify_gen_unary (NEG
, mode
, op1
,
7331 /* Similarly for MULT, AND and UMIN, except that for these the result
7333 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7334 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7335 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7337 cond0
= XEXP (XEXP (x
, 0), 0);
7338 cond1
= XEXP (XEXP (x
, 1), 0);
7340 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7341 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7342 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7343 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7344 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7345 || ((swap_condition (GET_CODE (cond0
))
7346 == combine_reversed_comparison_code (cond1
))
7347 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7348 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7349 && ! side_effects_p (x
))
7351 *ptrue
= *pfalse
= const0_rtx
;
7357 else if (code
== IF_THEN_ELSE
)
7359 /* If we have IF_THEN_ELSE already, extract the condition and
7360 canonicalize it if it is NE or EQ. */
7361 cond0
= XEXP (x
, 0);
7362 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7363 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7364 return XEXP (cond0
, 0);
7365 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7367 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7368 return XEXP (cond0
, 0);
7374 /* If X is a SUBREG, we can narrow both the true and false values
7375 if the inner expression, if there is a condition. */
7376 else if (code
== SUBREG
7377 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7380 *ptrue
= simplify_gen_subreg (mode
, true0
,
7381 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7382 *pfalse
= simplify_gen_subreg (mode
, false0
,
7383 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7388 /* If X is a constant, this isn't special and will cause confusions
7389 if we treat it as such. Likewise if it is equivalent to a constant. */
7390 else if (CONSTANT_P (x
)
7391 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7394 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7395 will be least confusing to the rest of the compiler. */
7396 else if (mode
== BImode
)
7398 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7402 /* If X is known to be either 0 or -1, those are the true and
7403 false values when testing X. */
7404 else if (x
== constm1_rtx
|| x
== const0_rtx
7405 || (mode
!= VOIDmode
7406 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7408 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7412 /* Likewise for 0 or a single bit. */
7413 else if (SCALAR_INT_MODE_P (mode
)
7414 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7415 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7417 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7421 /* Otherwise fail; show no condition with true and false values the same. */
7422 *ptrue
= *pfalse
= x
;
7426 /* Return the value of expression X given the fact that condition COND
7427 is known to be true when applied to REG as its first operand and VAL
7428 as its second. X is known to not be shared and so can be modified in
7431 We only handle the simplest cases, and specifically those cases that
7432 arise with IF_THEN_ELSE expressions. */
7435 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7437 enum rtx_code code
= GET_CODE (x
);
7442 if (side_effects_p (x
))
7445 /* If either operand of the condition is a floating point value,
7446 then we have to avoid collapsing an EQ comparison. */
7448 && rtx_equal_p (x
, reg
)
7449 && ! FLOAT_MODE_P (GET_MODE (x
))
7450 && ! FLOAT_MODE_P (GET_MODE (val
)))
7453 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7456 /* If X is (abs REG) and we know something about REG's relationship
7457 with zero, we may be able to simplify this. */
7459 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7462 case GE
: case GT
: case EQ
:
7465 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7467 GET_MODE (XEXP (x
, 0)));
7472 /* The only other cases we handle are MIN, MAX, and comparisons if the
7473 operands are the same as REG and VAL. */
7475 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7477 if (rtx_equal_p (XEXP (x
, 0), val
))
7478 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7480 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7482 if (GET_RTX_CLASS (code
) == '<')
7484 if (comparison_dominates_p (cond
, code
))
7485 return const_true_rtx
;
7487 code
= combine_reversed_comparison_code (x
);
7489 && comparison_dominates_p (cond
, code
))
7494 else if (code
== SMAX
|| code
== SMIN
7495 || code
== UMIN
|| code
== UMAX
)
7497 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7499 /* Do not reverse the condition when it is NE or EQ.
7500 This is because we cannot conclude anything about
7501 the value of 'SMAX (x, y)' when x is not equal to y,
7502 but we can when x equals y. */
7503 if ((code
== SMAX
|| code
== UMAX
)
7504 && ! (cond
== EQ
|| cond
== NE
))
7505 cond
= reverse_condition (cond
);
7510 return unsignedp
? x
: XEXP (x
, 1);
7512 return unsignedp
? x
: XEXP (x
, 0);
7514 return unsignedp
? XEXP (x
, 1) : x
;
7516 return unsignedp
? XEXP (x
, 0) : x
;
7523 else if (code
== SUBREG
)
7525 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7526 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7528 if (SUBREG_REG (x
) != r
)
7530 /* We must simplify subreg here, before we lose track of the
7531 original inner_mode. */
7532 new = simplify_subreg (GET_MODE (x
), r
,
7533 inner_mode
, SUBREG_BYTE (x
));
7537 SUBST (SUBREG_REG (x
), r
);
7542 /* We don't have to handle SIGN_EXTEND here, because even in the
7543 case of replacing something with a modeless CONST_INT, a
7544 CONST_INT is already (supposed to be) a valid sign extension for
7545 its narrower mode, which implies it's already properly
7546 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7547 story is different. */
7548 else if (code
== ZERO_EXTEND
)
7550 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7551 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7553 if (XEXP (x
, 0) != r
)
7555 /* We must simplify the zero_extend here, before we lose
7556 track of the original inner_mode. */
7557 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7562 SUBST (XEXP (x
, 0), r
);
7568 fmt
= GET_RTX_FORMAT (code
);
7569 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7572 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7573 else if (fmt
[i
] == 'E')
7574 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7575 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7582 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7583 assignment as a field assignment. */
7586 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7588 if (x
== y
|| rtx_equal_p (x
, y
))
7591 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7594 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7595 Note that all SUBREGs of MEM are paradoxical; otherwise they
7596 would have been rewritten. */
7597 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7598 && GET_CODE (SUBREG_REG (y
)) == MEM
7599 && rtx_equal_p (SUBREG_REG (y
),
7600 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7603 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7604 && GET_CODE (SUBREG_REG (x
)) == MEM
7605 && rtx_equal_p (SUBREG_REG (x
),
7606 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7609 /* We used to see if get_last_value of X and Y were the same but that's
7610 not correct. In one direction, we'll cause the assignment to have
7611 the wrong destination and in the case, we'll import a register into this
7612 insn that might have already have been dead. So fail if none of the
7613 above cases are true. */
7617 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7618 Return that assignment if so.
7620 We only handle the most common cases. */
7623 make_field_assignment (rtx x
)
7625 rtx dest
= SET_DEST (x
);
7626 rtx src
= SET_SRC (x
);
7631 unsigned HOST_WIDE_INT len
;
7633 enum machine_mode mode
;
7635 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7636 a clear of a one-bit field. We will have changed it to
7637 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7640 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7641 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7642 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7643 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7645 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7648 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7652 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7653 && subreg_lowpart_p (XEXP (src
, 0))
7654 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7655 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7656 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7657 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7658 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7659 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7661 assign
= make_extraction (VOIDmode
, dest
, 0,
7662 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7665 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7669 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7671 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7672 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7673 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7675 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7678 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7682 /* The other case we handle is assignments into a constant-position
7683 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7684 a mask that has all one bits except for a group of zero bits and
7685 OTHER is known to have zeros where C1 has ones, this is such an
7686 assignment. Compute the position and length from C1. Shift OTHER
7687 to the appropriate position, force it to the required mode, and
7688 make the extraction. Check for the AND in both operands. */
7690 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7693 rhs
= expand_compound_operation (XEXP (src
, 0));
7694 lhs
= expand_compound_operation (XEXP (src
, 1));
7696 if (GET_CODE (rhs
) == AND
7697 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7698 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7699 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7700 else if (GET_CODE (lhs
) == AND
7701 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7702 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7703 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7707 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7708 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7709 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7710 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7713 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7717 /* The mode to use for the source is the mode of the assignment, or of
7718 what is inside a possible STRICT_LOW_PART. */
7719 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7720 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7722 /* Shift OTHER right POS places and make it the source, restricting it
7723 to the proper length and mode. */
7725 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7726 GET_MODE (src
), other
, pos
),
7728 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7729 ? ~(unsigned HOST_WIDE_INT
) 0
7730 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7733 /* If SRC is masked by an AND that does not make a difference in
7734 the value being stored, strip it. */
7735 if (GET_CODE (assign
) == ZERO_EXTRACT
7736 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7737 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7738 && GET_CODE (src
) == AND
7739 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7740 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7741 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7742 src
= XEXP (src
, 0);
7744 return gen_rtx_SET (VOIDmode
, assign
, src
);
7747 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7751 apply_distributive_law (rtx x
)
7753 enum rtx_code code
= GET_CODE (x
);
7754 enum rtx_code inner_code
;
7755 rtx lhs
, rhs
, other
;
7758 /* Distributivity is not true for floating point as it can change the
7759 value. So we don't do it unless -funsafe-math-optimizations. */
7760 if (FLOAT_MODE_P (GET_MODE (x
))
7761 && ! flag_unsafe_math_optimizations
)
7764 /* The outer operation can only be one of the following: */
7765 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7766 && code
!= PLUS
&& code
!= MINUS
)
7772 /* If either operand is a primitive we can't do anything, so get out
7774 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7775 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7778 lhs
= expand_compound_operation (lhs
);
7779 rhs
= expand_compound_operation (rhs
);
7780 inner_code
= GET_CODE (lhs
);
7781 if (inner_code
!= GET_CODE (rhs
))
7784 /* See if the inner and outer operations distribute. */
7791 /* These all distribute except over PLUS. */
7792 if (code
== PLUS
|| code
== MINUS
)
7797 if (code
!= PLUS
&& code
!= MINUS
)
7802 /* This is also a multiply, so it distributes over everything. */
7806 /* Non-paradoxical SUBREGs distributes over all operations, provided
7807 the inner modes and byte offsets are the same, this is an extraction
7808 of a low-order part, we don't convert an fp operation to int or
7809 vice versa, and we would not be converting a single-word
7810 operation into a multi-word operation. The latter test is not
7811 required, but it prevents generating unneeded multi-word operations.
7812 Some of the previous tests are redundant given the latter test, but
7813 are retained because they are required for correctness.
7815 We produce the result slightly differently in this case. */
7817 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7818 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7819 || ! subreg_lowpart_p (lhs
)
7820 || (GET_MODE_CLASS (GET_MODE (lhs
))
7821 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7822 || (GET_MODE_SIZE (GET_MODE (lhs
))
7823 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7824 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7827 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7828 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7829 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7835 /* Set LHS and RHS to the inner operands (A and B in the example
7836 above) and set OTHER to the common operand (C in the example).
7837 These is only one way to do this unless the inner operation is
7839 if (GET_RTX_CLASS (inner_code
) == 'c'
7840 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7841 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7842 else if (GET_RTX_CLASS (inner_code
) == 'c'
7843 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7844 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7845 else if (GET_RTX_CLASS (inner_code
) == 'c'
7846 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7847 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7848 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7849 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7853 /* Form the new inner operation, seeing if it simplifies first. */
7854 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7856 /* There is one exception to the general way of distributing:
7857 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7858 if (code
== XOR
&& inner_code
== IOR
)
7861 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7864 /* We may be able to continuing distributing the result, so call
7865 ourselves recursively on the inner operation before forming the
7866 outer operation, which we return. */
7867 return gen_binary (inner_code
, GET_MODE (x
),
7868 apply_distributive_law (tem
), other
);
7871 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7874 Return an equivalent form, if different from X. Otherwise, return X. If
7875 X is zero, we are to always construct the equivalent form. */
7878 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7879 unsigned HOST_WIDE_INT constop
)
7881 unsigned HOST_WIDE_INT nonzero
;
7884 /* Simplify VAROP knowing that we will be only looking at some of the
7887 Note by passing in CONSTOP, we guarantee that the bits not set in
7888 CONSTOP are not significant and will never be examined. We must
7889 ensure that is the case by explicitly masking out those bits
7890 before returning. */
7891 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7893 /* If VAROP is a CLOBBER, we will fail so return it. */
7894 if (GET_CODE (varop
) == CLOBBER
)
7897 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7898 to VAROP and return the new constant. */
7899 if (GET_CODE (varop
) == CONST_INT
)
7900 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7902 /* See what bits may be nonzero in VAROP. Unlike the general case of
7903 a call to nonzero_bits, here we don't care about bits outside
7906 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7908 /* Turn off all bits in the constant that are known to already be zero.
7909 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7910 which is tested below. */
7914 /* If we don't have any bits left, return zero. */
7918 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7919 a power of two, we can replace this with an ASHIFT. */
7920 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7921 && (i
= exact_log2 (constop
)) >= 0)
7922 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7924 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7925 or XOR, then try to apply the distributive law. This may eliminate
7926 operations if either branch can be simplified because of the AND.
7927 It may also make some cases more complex, but those cases probably
7928 won't match a pattern either with or without this. */
7930 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7932 gen_lowpart_for_combine
7934 apply_distributive_law
7935 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7936 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7937 XEXP (varop
, 0), constop
),
7938 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7939 XEXP (varop
, 1), constop
))));
7941 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7942 the AND and see if one of the operands simplifies to zero. If so, we
7943 may eliminate it. */
7945 if (GET_CODE (varop
) == PLUS
7946 && exact_log2 (constop
+ 1) >= 0)
7950 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7951 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7952 if (o0
== const0_rtx
)
7954 if (o1
== const0_rtx
)
7958 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7959 if we already had one (just check for the simplest cases). */
7960 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7961 && GET_MODE (XEXP (x
, 0)) == mode
7962 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7963 varop
= XEXP (x
, 0);
7965 varop
= gen_lowpart_for_combine (mode
, varop
);
7967 /* If we can't make the SUBREG, try to return what we were given. */
7968 if (GET_CODE (varop
) == CLOBBER
)
7969 return x
? x
: varop
;
7971 /* If we are only masking insignificant bits, return VAROP. */
7972 if (constop
== nonzero
)
7976 /* Otherwise, return an AND. */
7977 constop
= trunc_int_for_mode (constop
, mode
);
7978 /* See how much, if any, of X we can use. */
7979 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7980 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7984 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7985 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7986 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7988 SUBST (XEXP (x
, 0), varop
);
7995 #define nonzero_bits_with_known(X, MODE) \
7996 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
7998 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
7999 It avoids exponential behavior in nonzero_bits1 when X has
8000 identical subexpressions on the first or the second level. */
8002 static unsigned HOST_WIDE_INT
8003 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8004 enum machine_mode known_mode
,
8005 unsigned HOST_WIDE_INT known_ret
)
8007 if (x
== known_x
&& mode
== known_mode
)
8010 /* Try to find identical subexpressions. If found call
8011 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8012 precomputed value for the subexpression as KNOWN_RET. */
8014 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8015 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8017 rtx x0
= XEXP (x
, 0);
8018 rtx x1
= XEXP (x
, 1);
8020 /* Check the first level. */
8022 return nonzero_bits1 (x
, mode
, x0
, mode
,
8023 nonzero_bits_with_known (x0
, mode
));
8025 /* Check the second level. */
8026 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8027 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8028 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8029 return nonzero_bits1 (x
, mode
, x1
, mode
,
8030 nonzero_bits_with_known (x1
, mode
));
8032 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8033 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8034 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8035 return nonzero_bits1 (x
, mode
, x0
, mode
,
8036 nonzero_bits_with_known (x0
, mode
));
8039 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8042 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8043 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8044 is less useful. We can't allow both, because that results in exponential
8045 run time recursion. There is a nullstone testcase that triggered
8046 this. This macro avoids accidental uses of num_sign_bit_copies. */
8047 #define cached_num_sign_bit_copies()
8049 /* Given an expression, X, compute which bits in X can be nonzero.
8050 We don't care about bits outside of those defined in MODE.
8052 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8053 a shift, AND, or zero_extract, we can do better. */
8055 static unsigned HOST_WIDE_INT
8056 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8057 enum machine_mode known_mode
,
8058 unsigned HOST_WIDE_INT known_ret
)
8060 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8061 unsigned HOST_WIDE_INT inner_nz
;
8063 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8066 /* For floating-point values, assume all bits are needed. */
8067 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8070 /* If X is wider than MODE, use its mode instead. */
8071 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8073 mode
= GET_MODE (x
);
8074 nonzero
= GET_MODE_MASK (mode
);
8075 mode_width
= GET_MODE_BITSIZE (mode
);
8078 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8079 /* Our only callers in this case look for single bit values. So
8080 just return the mode mask. Those tests will then be false. */
8083 #ifndef WORD_REGISTER_OPERATIONS
8084 /* If MODE is wider than X, but both are a single word for both the host
8085 and target machines, we can compute this from which bits of the
8086 object might be nonzero in its own mode, taking into account the fact
8087 that on many CISC machines, accessing an object in a wider mode
8088 causes the high-order bits to become undefined. So they are
8089 not known to be zero. */
8091 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8092 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8093 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8094 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8096 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8097 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8102 code
= GET_CODE (x
);
8106 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8107 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8108 all the bits above ptr_mode are known to be zero. */
8109 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8111 nonzero
&= GET_MODE_MASK (ptr_mode
);
8114 /* Include declared information about alignment of pointers. */
8115 /* ??? We don't properly preserve REG_POINTER changes across
8116 pointer-to-integer casts, so we can't trust it except for
8117 things that we know must be pointers. See execute/960116-1.c. */
8118 if ((x
== stack_pointer_rtx
8119 || x
== frame_pointer_rtx
8120 || x
== arg_pointer_rtx
)
8121 && REGNO_POINTER_ALIGN (REGNO (x
)))
8123 unsigned HOST_WIDE_INT alignment
8124 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8126 #ifdef PUSH_ROUNDING
8127 /* If PUSH_ROUNDING is defined, it is possible for the
8128 stack to be momentarily aligned only to that amount,
8129 so we pick the least alignment. */
8130 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8131 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8135 nonzero
&= ~(alignment
- 1);
8138 /* If X is a register whose nonzero bits value is current, use it.
8139 Otherwise, if X is a register whose value we can find, use that
8140 value. Otherwise, use the previously-computed global nonzero bits
8141 for this register. */
8143 if (reg_last_set_value
[REGNO (x
)] != 0
8144 && (reg_last_set_mode
[REGNO (x
)] == mode
8145 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8146 && GET_MODE_CLASS (mode
) == MODE_INT
))
8147 && (reg_last_set_label
[REGNO (x
)] == label_tick
8148 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8149 && REG_N_SETS (REGNO (x
)) == 1
8150 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8152 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8153 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8155 tem
= get_last_value (x
);
8159 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8160 /* If X is narrower than MODE and TEM is a non-negative
8161 constant that would appear negative in the mode of X,
8162 sign-extend it for use in reg_nonzero_bits because some
8163 machines (maybe most) will actually do the sign-extension
8164 and this is the conservative approach.
8166 ??? For 2.5, try to tighten up the MD files in this regard
8167 instead of this kludge. */
8169 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8170 && GET_CODE (tem
) == CONST_INT
8172 && 0 != (INTVAL (tem
)
8173 & ((HOST_WIDE_INT
) 1
8174 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8175 tem
= GEN_INT (INTVAL (tem
)
8176 | ((HOST_WIDE_INT
) (-1)
8177 << GET_MODE_BITSIZE (GET_MODE (x
))));
8179 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8181 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8183 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8185 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8186 /* We don't know anything about the upper bits. */
8187 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8188 return nonzero
& mask
;
8194 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8195 /* If X is negative in MODE, sign-extend the value. */
8196 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8197 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8198 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8204 #ifdef LOAD_EXTEND_OP
8205 /* In many, if not most, RISC machines, reading a byte from memory
8206 zeros the rest of the register. Noticing that fact saves a lot
8207 of extra zero-extends. */
8208 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8209 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8214 case UNEQ
: case LTGT
:
8215 case GT
: case GTU
: case UNGT
:
8216 case LT
: case LTU
: case UNLT
:
8217 case GE
: case GEU
: case UNGE
:
8218 case LE
: case LEU
: case UNLE
:
8219 case UNORDERED
: case ORDERED
:
8221 /* If this produces an integer result, we know which bits are set.
8222 Code here used to clear bits outside the mode of X, but that is
8225 if (GET_MODE_CLASS (mode
) == MODE_INT
8226 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8227 nonzero
= STORE_FLAG_VALUE
;
8232 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8233 and num_sign_bit_copies. */
8234 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8235 == GET_MODE_BITSIZE (GET_MODE (x
)))
8239 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8240 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8245 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8246 and num_sign_bit_copies. */
8247 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8248 == GET_MODE_BITSIZE (GET_MODE (x
)))
8254 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8255 & GET_MODE_MASK (mode
));
8259 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8260 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8261 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8265 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8266 Otherwise, show all the bits in the outer mode but not the inner
8268 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8269 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8271 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8273 & (((HOST_WIDE_INT
) 1
8274 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8275 inner_nz
|= (GET_MODE_MASK (mode
)
8276 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8279 nonzero
&= inner_nz
;
8283 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8284 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8288 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8290 unsigned HOST_WIDE_INT nonzero0
=
8291 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8293 /* Don't call nonzero_bits for the second time if it cannot change
8295 if ((nonzero
& nonzero0
) != nonzero
)
8296 nonzero
&= (nonzero0
8297 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8301 case PLUS
: case MINUS
:
8303 case DIV
: case UDIV
:
8304 case MOD
: case UMOD
:
8305 /* We can apply the rules of arithmetic to compute the number of
8306 high- and low-order zero bits of these operations. We start by
8307 computing the width (position of the highest-order nonzero bit)
8308 and the number of low-order zero bits for each value. */
8310 unsigned HOST_WIDE_INT nz0
=
8311 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8312 unsigned HOST_WIDE_INT nz1
=
8313 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8314 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8315 int width0
= floor_log2 (nz0
) + 1;
8316 int width1
= floor_log2 (nz1
) + 1;
8317 int low0
= floor_log2 (nz0
& -nz0
);
8318 int low1
= floor_log2 (nz1
& -nz1
);
8319 HOST_WIDE_INT op0_maybe_minusp
8320 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8321 HOST_WIDE_INT op1_maybe_minusp
8322 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8323 unsigned int result_width
= mode_width
;
8329 result_width
= MAX (width0
, width1
) + 1;
8330 result_low
= MIN (low0
, low1
);
8333 result_low
= MIN (low0
, low1
);
8336 result_width
= width0
+ width1
;
8337 result_low
= low0
+ low1
;
8342 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8343 result_width
= width0
;
8348 result_width
= width0
;
8353 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8354 result_width
= MIN (width0
, width1
);
8355 result_low
= MIN (low0
, low1
);
8360 result_width
= MIN (width0
, width1
);
8361 result_low
= MIN (low0
, low1
);
8367 if (result_width
< mode_width
)
8368 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8371 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8373 #ifdef POINTERS_EXTEND_UNSIGNED
8374 /* If pointers extend unsigned and this is an addition or subtraction
8375 to a pointer in Pmode, all the bits above ptr_mode are known to be
8377 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8378 && (code
== PLUS
|| code
== MINUS
)
8379 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8380 nonzero
&= GET_MODE_MASK (ptr_mode
);
8386 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8387 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8388 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8392 /* If this is a SUBREG formed for a promoted variable that has
8393 been zero-extended, we know that at least the high-order bits
8394 are zero, though others might be too. */
8396 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8397 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8398 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8400 /* If the inner mode is a single word for both the host and target
8401 machines, we can compute this from which bits of the inner
8402 object might be nonzero. */
8403 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8404 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8405 <= HOST_BITS_PER_WIDE_INT
))
8407 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8409 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8410 /* If this is a typical RISC machine, we only have to worry
8411 about the way loads are extended. */
8412 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8414 & (((unsigned HOST_WIDE_INT
) 1
8415 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8417 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8418 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8421 /* On many CISC machines, accessing an object in a wider mode
8422 causes the high-order bits to become undefined. So they are
8423 not known to be zero. */
8424 if (GET_MODE_SIZE (GET_MODE (x
))
8425 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8426 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8427 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8436 /* The nonzero bits are in two classes: any bits within MODE
8437 that aren't in GET_MODE (x) are always significant. The rest of the
8438 nonzero bits are those that are significant in the operand of
8439 the shift when shifted the appropriate number of bits. This
8440 shows that high-order bits are cleared by the right shift and
8441 low-order bits by left shifts. */
8442 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8443 && INTVAL (XEXP (x
, 1)) >= 0
8444 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8446 enum machine_mode inner_mode
= GET_MODE (x
);
8447 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8448 int count
= INTVAL (XEXP (x
, 1));
8449 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8450 unsigned HOST_WIDE_INT op_nonzero
=
8451 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8452 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8453 unsigned HOST_WIDE_INT outer
= 0;
8455 if (mode_width
> width
)
8456 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8458 if (code
== LSHIFTRT
)
8460 else if (code
== ASHIFTRT
)
8464 /* If the sign bit may have been nonzero before the shift, we
8465 need to mark all the places it could have been copied to
8466 by the shift as possibly nonzero. */
8467 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8468 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8470 else if (code
== ASHIFT
)
8473 inner
= ((inner
<< (count
% width
)
8474 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8476 nonzero
&= (outer
| inner
);
8482 /* This is at most the number of bits in the mode. */
8483 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8487 /* If CLZ has a known value at zero, then the nonzero bits are
8488 that value, plus the number of bits in the mode minus one. */
8489 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8490 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8496 /* If CTZ has a known value at zero, then the nonzero bits are
8497 that value, plus the number of bits in the mode minus one. */
8498 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8499 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8509 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8510 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8520 /* See the macro definition above. */
8521 #undef cached_num_sign_bit_copies
8523 #define num_sign_bit_copies_with_known(X, M) \
8524 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8526 /* The function cached_num_sign_bit_copies is a wrapper around
8527 num_sign_bit_copies1. It avoids exponential behavior in
8528 num_sign_bit_copies1 when X has identical subexpressions on the
8529 first or the second level. */
8532 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8533 enum machine_mode known_mode
,
8534 unsigned int known_ret
)
8536 if (x
== known_x
&& mode
== known_mode
)
8539 /* Try to find identical subexpressions. If found call
8540 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8541 the precomputed value for the subexpression as KNOWN_RET. */
8543 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8544 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8546 rtx x0
= XEXP (x
, 0);
8547 rtx x1
= XEXP (x
, 1);
8549 /* Check the first level. */
8552 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8553 num_sign_bit_copies_with_known (x0
, mode
));
8555 /* Check the second level. */
8556 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8557 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8558 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8560 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8561 num_sign_bit_copies_with_known (x1
, mode
));
8563 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8564 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8565 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8567 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8568 num_sign_bit_copies_with_known (x0
, mode
));
8571 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8574 /* Return the number of bits at the high-order end of X that are known to
8575 be equal to the sign bit. X will be used in mode MODE; if MODE is
8576 VOIDmode, X will be used in its own mode. The returned value will always
8577 be between 1 and the number of bits in MODE. */
8580 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8581 enum machine_mode known_mode
,
8582 unsigned int known_ret
)
8584 enum rtx_code code
= GET_CODE (x
);
8585 unsigned int bitwidth
;
8586 int num0
, num1
, result
;
8587 unsigned HOST_WIDE_INT nonzero
;
8590 /* If we weren't given a mode, use the mode of X. If the mode is still
8591 VOIDmode, we don't know anything. Likewise if one of the modes is
8594 if (mode
== VOIDmode
)
8595 mode
= GET_MODE (x
);
8597 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8600 bitwidth
= GET_MODE_BITSIZE (mode
);
8602 /* For a smaller object, just ignore the high bits. */
8603 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8605 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8607 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8610 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8612 #ifndef WORD_REGISTER_OPERATIONS
8613 /* If this machine does not do all register operations on the entire
8614 register and MODE is wider than the mode of X, we can say nothing
8615 at all about the high-order bits. */
8618 /* Likewise on machines that do, if the mode of the object is smaller
8619 than a word and loads of that size don't sign extend, we can say
8620 nothing about the high order bits. */
8621 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8622 #ifdef LOAD_EXTEND_OP
8623 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8634 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8635 /* If pointers extend signed and this is a pointer in Pmode, say that
8636 all the bits above ptr_mode are known to be sign bit copies. */
8637 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8639 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8642 if (reg_last_set_value
[REGNO (x
)] != 0
8643 && reg_last_set_mode
[REGNO (x
)] == mode
8644 && (reg_last_set_label
[REGNO (x
)] == label_tick
8645 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8646 && REG_N_SETS (REGNO (x
)) == 1
8647 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8649 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8650 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8652 tem
= get_last_value (x
);
8654 return num_sign_bit_copies_with_known (tem
, mode
);
8656 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8657 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8658 return reg_sign_bit_copies
[REGNO (x
)];
8662 #ifdef LOAD_EXTEND_OP
8663 /* Some RISC machines sign-extend all loads of smaller than a word. */
8664 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8665 return MAX (1, ((int) bitwidth
8666 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8671 /* If the constant is negative, take its 1's complement and remask.
8672 Then see how many zero bits we have. */
8673 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8674 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8675 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8676 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8678 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8681 /* If this is a SUBREG for a promoted object that is sign-extended
8682 and we are looking at it in a wider mode, we know that at least the
8683 high-order bits are known to be sign bit copies. */
8685 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8687 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8688 return MAX ((int) bitwidth
8689 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8693 /* For a smaller object, just ignore the high bits. */
8694 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8696 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8697 return MAX (1, (num0
8698 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8702 #ifdef WORD_REGISTER_OPERATIONS
8703 #ifdef LOAD_EXTEND_OP
8704 /* For paradoxical SUBREGs on machines where all register operations
8705 affect the entire register, just look inside. Note that we are
8706 passing MODE to the recursive call, so the number of sign bit copies
8707 will remain relative to that mode, not the inner mode. */
8709 /* This works only if loads sign extend. Otherwise, if we get a
8710 reload for the inner part, it may be loaded from the stack, and
8711 then we lose all sign bit copies that existed before the store
8714 if ((GET_MODE_SIZE (GET_MODE (x
))
8715 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8716 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8717 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8718 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8724 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8725 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8729 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8730 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8733 /* For a smaller object, just ignore the high bits. */
8734 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8735 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8739 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8741 case ROTATE
: case ROTATERT
:
8742 /* If we are rotating left by a number of bits less than the number
8743 of sign bit copies, we can just subtract that amount from the
8745 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8746 && INTVAL (XEXP (x
, 1)) >= 0
8747 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8749 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8750 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8751 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8756 /* In general, this subtracts one sign bit copy. But if the value
8757 is known to be positive, the number of sign bit copies is the
8758 same as that of the input. Finally, if the input has just one bit
8759 that might be nonzero, all the bits are copies of the sign bit. */
8760 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8761 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8762 return num0
> 1 ? num0
- 1 : 1;
8764 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8769 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8774 case IOR
: case AND
: case XOR
:
8775 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8776 /* Logical operations will preserve the number of sign-bit copies.
8777 MIN and MAX operations always return one of the operands. */
8778 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8779 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8780 return MIN (num0
, num1
);
8782 case PLUS
: case MINUS
:
8783 /* For addition and subtraction, we can have a 1-bit carry. However,
8784 if we are subtracting 1 from a positive number, there will not
8785 be such a carry. Furthermore, if the positive number is known to
8786 be 0 or 1, we know the result is either -1 or 0. */
8788 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8789 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8791 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8792 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8793 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8794 : bitwidth
- floor_log2 (nonzero
) - 1);
8797 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8798 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8799 result
= MAX (1, MIN (num0
, num1
) - 1);
8801 #ifdef POINTERS_EXTEND_UNSIGNED
8802 /* If pointers extend signed and this is an addition or subtraction
8803 to a pointer in Pmode, all the bits above ptr_mode are known to be
8805 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8806 && (code
== PLUS
|| code
== MINUS
)
8807 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8808 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8809 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8815 /* The number of bits of the product is the sum of the number of
8816 bits of both terms. However, unless one of the terms if known
8817 to be positive, we must allow for an additional bit since negating
8818 a negative number can remove one sign bit copy. */
8820 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8821 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8823 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8825 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8826 || (((nonzero_bits (XEXP (x
, 0), mode
)
8827 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8828 && ((nonzero_bits (XEXP (x
, 1), mode
)
8829 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8832 return MAX (1, result
);
8835 /* The result must be <= the first operand. If the first operand
8836 has the high bit set, we know nothing about the number of sign
8838 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8840 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8841 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8844 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8847 /* The result must be <= the second operand. */
8848 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8851 /* Similar to unsigned division, except that we have to worry about
8852 the case where the divisor is negative, in which case we have
8854 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8856 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8857 || (nonzero_bits (XEXP (x
, 1), mode
)
8858 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8864 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8866 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8867 || (nonzero_bits (XEXP (x
, 1), mode
)
8868 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8874 /* Shifts by a constant add to the number of bits equal to the
8876 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8877 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8878 && INTVAL (XEXP (x
, 1)) > 0)
8879 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8884 /* Left shifts destroy copies. */
8885 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8886 || INTVAL (XEXP (x
, 1)) < 0
8887 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8890 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8891 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8894 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8895 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8896 return MIN (num0
, num1
);
8898 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8899 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8900 case GEU
: case GTU
: case LEU
: case LTU
:
8901 case UNORDERED
: case ORDERED
:
8902 /* If the constant is negative, take its 1's complement and remask.
8903 Then see how many zero bits we have. */
8904 nonzero
= STORE_FLAG_VALUE
;
8905 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8906 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8907 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8909 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8916 /* If we haven't been able to figure it out by one of the above rules,
8917 see if some of the high-order bits are known to be zero. If so,
8918 count those bits and return one less than that amount. If we can't
8919 safely compute the mask for this mode, always return BITWIDTH. */
8921 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8924 nonzero
= nonzero_bits (x
, mode
);
8925 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8926 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8929 /* Return the number of "extended" bits there are in X, when interpreted
8930 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8931 unsigned quantities, this is the number of high-order zero bits.
8932 For signed quantities, this is the number of copies of the sign bit
8933 minus 1. In both case, this function returns the number of "spare"
8934 bits. For example, if two quantities for which this function returns
8935 at least 1 are added, the addition is known not to overflow.
8937 This function will always return 0 unless called during combine, which
8938 implies that it must be called from a define_split. */
8941 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8943 if (nonzero_sign_valid
== 0)
8947 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8948 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8949 - floor_log2 (nonzero_bits (x
, mode
)))
8951 : num_sign_bit_copies (x
, mode
) - 1);
8954 /* This function is called from `simplify_shift_const' to merge two
8955 outer operations. Specifically, we have already found that we need
8956 to perform operation *POP0 with constant *PCONST0 at the outermost
8957 position. We would now like to also perform OP1 with constant CONST1
8958 (with *POP0 being done last).
8960 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8961 the resulting operation. *PCOMP_P is set to 1 if we would need to
8962 complement the innermost operand, otherwise it is unchanged.
8964 MODE is the mode in which the operation will be done. No bits outside
8965 the width of this mode matter. It is assumed that the width of this mode
8966 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8968 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8969 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8970 result is simply *PCONST0.
8972 If the resulting operation cannot be expressed as one operation, we
8973 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8976 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8978 enum rtx_code op0
= *pop0
;
8979 HOST_WIDE_INT const0
= *pconst0
;
8981 const0
&= GET_MODE_MASK (mode
);
8982 const1
&= GET_MODE_MASK (mode
);
8984 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8988 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8991 if (op1
== NIL
|| op0
== SET
)
8994 else if (op0
== NIL
)
8995 op0
= op1
, const0
= const1
;
8997 else if (op0
== op1
)
9021 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9022 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9025 /* If the two constants aren't the same, we can't do anything. The
9026 remaining six cases can all be done. */
9027 else if (const0
!= const1
)
9035 /* (a & b) | b == b */
9037 else /* op1 == XOR */
9038 /* (a ^ b) | b == a | b */
9044 /* (a & b) ^ b == (~a) & b */
9045 op0
= AND
, *pcomp_p
= 1;
9046 else /* op1 == IOR */
9047 /* (a | b) ^ b == a & ~b */
9048 op0
= AND
, const0
= ~const0
;
9053 /* (a | b) & b == b */
9055 else /* op1 == XOR */
9056 /* (a ^ b) & b) == (~a) & b */
9063 /* Check for NO-OP cases. */
9064 const0
&= GET_MODE_MASK (mode
);
9066 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9068 else if (const0
== 0 && op0
== AND
)
9070 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9074 /* ??? Slightly redundant with the above mask, but not entirely.
9075 Moving this above means we'd have to sign-extend the mode mask
9076 for the final test. */
9077 const0
= trunc_int_for_mode (const0
, mode
);
9085 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9086 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9087 that we started with.
9089 The shift is normally computed in the widest mode we find in VAROP, as
9090 long as it isn't a different number of words than RESULT_MODE. Exceptions
9091 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9094 simplify_shift_const (rtx x
, enum rtx_code code
,
9095 enum machine_mode result_mode
, rtx varop
,
9098 enum rtx_code orig_code
= code
;
9101 enum machine_mode mode
= result_mode
;
9102 enum machine_mode shift_mode
, tmode
;
9103 unsigned int mode_words
9104 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9105 /* We form (outer_op (code varop count) (outer_const)). */
9106 enum rtx_code outer_op
= NIL
;
9107 HOST_WIDE_INT outer_const
= 0;
9109 int complement_p
= 0;
9112 /* Make sure and truncate the "natural" shift on the way in. We don't
9113 want to do this inside the loop as it makes it more difficult to
9115 #ifdef SHIFT_COUNT_TRUNCATED
9116 if (SHIFT_COUNT_TRUNCATED
)
9117 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9120 /* If we were given an invalid count, don't do anything except exactly
9121 what was requested. */
9123 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9128 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9133 /* Unless one of the branches of the `if' in this loop does a `continue',
9134 we will `break' the loop after the `if'. */
9138 /* If we have an operand of (clobber (const_int 0)), just return that
9140 if (GET_CODE (varop
) == CLOBBER
)
9143 /* If we discovered we had to complement VAROP, leave. Making a NOT
9144 here would cause an infinite loop. */
9148 /* Convert ROTATERT to ROTATE. */
9149 if (code
== ROTATERT
)
9151 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9153 if (VECTOR_MODE_P (result_mode
))
9154 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9156 count
= bitsize
- count
;
9159 /* We need to determine what mode we will do the shift in. If the
9160 shift is a right shift or a ROTATE, we must always do it in the mode
9161 it was originally done in. Otherwise, we can do it in MODE, the
9162 widest mode encountered. */
9164 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9165 ? result_mode
: mode
);
9167 /* Handle cases where the count is greater than the size of the mode
9168 minus 1. For ASHIFT, use the size minus one as the count (this can
9169 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9170 take the count modulo the size. For other shifts, the result is
9173 Since these shifts are being produced by the compiler by combining
9174 multiple operations, each of which are defined, we know what the
9175 result is supposed to be. */
9177 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9179 if (code
== ASHIFTRT
)
9180 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9181 else if (code
== ROTATE
|| code
== ROTATERT
)
9182 count
%= GET_MODE_BITSIZE (shift_mode
);
9185 /* We can't simply return zero because there may be an
9193 /* An arithmetic right shift of a quantity known to be -1 or 0
9195 if (code
== ASHIFTRT
9196 && (num_sign_bit_copies (varop
, shift_mode
)
9197 == GET_MODE_BITSIZE (shift_mode
)))
9203 /* If we are doing an arithmetic right shift and discarding all but
9204 the sign bit copies, this is equivalent to doing a shift by the
9205 bitsize minus one. Convert it into that shift because it will often
9206 allow other simplifications. */
9208 if (code
== ASHIFTRT
9209 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9210 >= GET_MODE_BITSIZE (shift_mode
)))
9211 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9213 /* We simplify the tests below and elsewhere by converting
9214 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9215 `make_compound_operation' will convert it to an ASHIFTRT for
9216 those machines (such as VAX) that don't have an LSHIFTRT. */
9217 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9219 && ((nonzero_bits (varop
, shift_mode
)
9220 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9224 if (code
== LSHIFTRT
9225 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9226 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9229 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9230 && !((nonzero_bits (varop
, shift_mode
) << count
)
9231 & GET_MODE_MASK (shift_mode
)))
9234 switch (GET_CODE (varop
))
9240 new = expand_compound_operation (varop
);
9249 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9250 minus the width of a smaller mode, we can do this with a
9251 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9252 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9253 && ! mode_dependent_address_p (XEXP (varop
, 0))
9254 && ! MEM_VOLATILE_P (varop
)
9255 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9256 MODE_INT
, 1)) != BLKmode
)
9258 new = adjust_address_nv (varop
, tmode
,
9259 BYTES_BIG_ENDIAN
? 0
9260 : count
/ BITS_PER_UNIT
);
9262 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9263 : ZERO_EXTEND
, mode
, new);
9270 /* Similar to the case above, except that we can only do this if
9271 the resulting mode is the same as that of the underlying
9272 MEM and adjust the address depending on the *bits* endianness
9273 because of the way that bit-field extract insns are defined. */
9274 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9275 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9276 MODE_INT
, 1)) != BLKmode
9277 && tmode
== GET_MODE (XEXP (varop
, 0)))
9279 if (BITS_BIG_ENDIAN
)
9280 new = XEXP (varop
, 0);
9283 new = copy_rtx (XEXP (varop
, 0));
9284 SUBST (XEXP (new, 0),
9285 plus_constant (XEXP (new, 0),
9286 count
/ BITS_PER_UNIT
));
9289 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9290 : ZERO_EXTEND
, mode
, new);
9297 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9298 the same number of words as what we've seen so far. Then store
9299 the widest mode in MODE. */
9300 if (subreg_lowpart_p (varop
)
9301 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9302 > GET_MODE_SIZE (GET_MODE (varop
)))
9303 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9304 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9307 varop
= SUBREG_REG (varop
);
9308 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9309 mode
= GET_MODE (varop
);
9315 /* Some machines use MULT instead of ASHIFT because MULT
9316 is cheaper. But it is still better on those machines to
9317 merge two shifts into one. */
9318 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9319 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9322 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9323 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9329 /* Similar, for when divides are cheaper. */
9330 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9331 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9334 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9335 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9341 /* If we are extracting just the sign bit of an arithmetic
9342 right shift, that shift is not needed. However, the sign
9343 bit of a wider mode may be different from what would be
9344 interpreted as the sign bit in a narrower mode, so, if
9345 the result is narrower, don't discard the shift. */
9346 if (code
== LSHIFTRT
9347 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9348 && (GET_MODE_BITSIZE (result_mode
)
9349 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9351 varop
= XEXP (varop
, 0);
9355 /* ... fall through ... */
9360 /* Here we have two nested shifts. The result is usually the
9361 AND of a new shift with a mask. We compute the result below. */
9362 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9363 && INTVAL (XEXP (varop
, 1)) >= 0
9364 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9365 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9366 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9368 enum rtx_code first_code
= GET_CODE (varop
);
9369 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9370 unsigned HOST_WIDE_INT mask
;
9373 /* We have one common special case. We can't do any merging if
9374 the inner code is an ASHIFTRT of a smaller mode. However, if
9375 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9376 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9377 we can convert it to
9378 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9379 This simplifies certain SIGN_EXTEND operations. */
9380 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9381 && count
== (unsigned int)
9382 (GET_MODE_BITSIZE (result_mode
)
9383 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9385 /* C3 has the low-order C1 bits zero. */
9387 mask
= (GET_MODE_MASK (mode
)
9388 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9390 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9391 XEXP (varop
, 0), mask
);
9392 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9394 count
= first_count
;
9399 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9400 than C1 high-order bits equal to the sign bit, we can convert
9401 this to either an ASHIFT or an ASHIFTRT depending on the
9404 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9406 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9407 && GET_MODE (varop
) == shift_mode
9408 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9411 varop
= XEXP (varop
, 0);
9413 signed_count
= count
- first_count
;
9414 if (signed_count
< 0)
9415 count
= -signed_count
, code
= ASHIFT
;
9417 count
= signed_count
;
9422 /* There are some cases we can't do. If CODE is ASHIFTRT,
9423 we can only do this if FIRST_CODE is also ASHIFTRT.
9425 We can't do the case when CODE is ROTATE and FIRST_CODE is
9428 If the mode of this shift is not the mode of the outer shift,
9429 we can't do this if either shift is a right shift or ROTATE.
9431 Finally, we can't do any of these if the mode is too wide
9432 unless the codes are the same.
9434 Handle the case where the shift codes are the same
9437 if (code
== first_code
)
9439 if (GET_MODE (varop
) != result_mode
9440 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9444 count
+= first_count
;
9445 varop
= XEXP (varop
, 0);
9449 if (code
== ASHIFTRT
9450 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9451 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9452 || (GET_MODE (varop
) != result_mode
9453 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9454 || first_code
== ROTATE
9455 || code
== ROTATE
)))
9458 /* To compute the mask to apply after the shift, shift the
9459 nonzero bits of the inner shift the same way the
9460 outer shift will. */
9462 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9465 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9468 /* Give up if we can't compute an outer operation to use. */
9470 || GET_CODE (mask_rtx
) != CONST_INT
9471 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9473 result_mode
, &complement_p
))
9476 /* If the shifts are in the same direction, we add the
9477 counts. Otherwise, we subtract them. */
9478 signed_count
= count
;
9479 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9480 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9481 signed_count
+= first_count
;
9483 signed_count
-= first_count
;
9485 /* If COUNT is positive, the new shift is usually CODE,
9486 except for the two exceptions below, in which case it is
9487 FIRST_CODE. If the count is negative, FIRST_CODE should
9489 if (signed_count
> 0
9490 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9491 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9492 code
= first_code
, count
= signed_count
;
9493 else if (signed_count
< 0)
9494 code
= first_code
, count
= -signed_count
;
9496 count
= signed_count
;
9498 varop
= XEXP (varop
, 0);
9502 /* If we have (A << B << C) for any shift, we can convert this to
9503 (A << C << B). This wins if A is a constant. Only try this if
9504 B is not a constant. */
9506 else if (GET_CODE (varop
) == code
9507 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9509 = simplify_binary_operation (code
, mode
,
9513 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9520 /* Make this fit the case below. */
9521 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9522 GEN_INT (GET_MODE_MASK (mode
)));
9528 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9529 with C the size of VAROP - 1 and the shift is logical if
9530 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9531 we have an (le X 0) operation. If we have an arithmetic shift
9532 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9533 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9535 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9536 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9537 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9538 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9539 && count
== (unsigned int)
9540 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9541 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9544 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9547 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9548 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9553 /* If we have (shift (logical)), move the logical to the outside
9554 to allow it to possibly combine with another logical and the
9555 shift to combine with another shift. This also canonicalizes to
9556 what a ZERO_EXTRACT looks like. Also, some machines have
9557 (and (shift)) insns. */
9559 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9560 && (new = simplify_binary_operation (code
, result_mode
,
9562 GEN_INT (count
))) != 0
9563 && GET_CODE (new) == CONST_INT
9564 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9565 INTVAL (new), result_mode
, &complement_p
))
9567 varop
= XEXP (varop
, 0);
9571 /* If we can't do that, try to simplify the shift in each arm of the
9572 logical expression, make a new logical expression, and apply
9573 the inverse distributive law. */
9575 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9576 XEXP (varop
, 0), count
);
9577 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9578 XEXP (varop
, 1), count
);
9580 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9581 varop
= apply_distributive_law (varop
);
9588 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9589 says that the sign bit can be tested, FOO has mode MODE, C is
9590 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9591 that may be nonzero. */
9592 if (code
== LSHIFTRT
9593 && XEXP (varop
, 1) == const0_rtx
9594 && GET_MODE (XEXP (varop
, 0)) == result_mode
9595 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9596 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9597 && ((STORE_FLAG_VALUE
9598 & ((HOST_WIDE_INT
) 1
9599 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9600 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9601 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9602 (HOST_WIDE_INT
) 1, result_mode
,
9605 varop
= XEXP (varop
, 0);
9612 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9613 than the number of bits in the mode is equivalent to A. */
9614 if (code
== LSHIFTRT
9615 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9616 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9618 varop
= XEXP (varop
, 0);
9623 /* NEG commutes with ASHIFT since it is multiplication. Move the
9624 NEG outside to allow shifts to combine. */
9626 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9627 (HOST_WIDE_INT
) 0, result_mode
,
9630 varop
= XEXP (varop
, 0);
9636 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9637 is one less than the number of bits in the mode is
9638 equivalent to (xor A 1). */
9639 if (code
== LSHIFTRT
9640 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9641 && XEXP (varop
, 1) == constm1_rtx
9642 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9643 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9644 (HOST_WIDE_INT
) 1, result_mode
,
9648 varop
= XEXP (varop
, 0);
9652 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9653 that might be nonzero in BAR are those being shifted out and those
9654 bits are known zero in FOO, we can replace the PLUS with FOO.
9655 Similarly in the other operand order. This code occurs when
9656 we are computing the size of a variable-size array. */
9658 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9659 && count
< HOST_BITS_PER_WIDE_INT
9660 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9661 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9662 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9664 varop
= XEXP (varop
, 0);
9667 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9668 && count
< HOST_BITS_PER_WIDE_INT
9669 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9670 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9672 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9673 & nonzero_bits (XEXP (varop
, 1),
9676 varop
= XEXP (varop
, 1);
9680 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9682 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9683 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9685 GEN_INT (count
))) != 0
9686 && GET_CODE (new) == CONST_INT
9687 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9688 INTVAL (new), result_mode
, &complement_p
))
9690 varop
= XEXP (varop
, 0);
9696 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9697 with C the size of VAROP - 1 and the shift is logical if
9698 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9699 we have a (gt X 0) operation. If the shift is arithmetic with
9700 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9701 we have a (neg (gt X 0)) operation. */
9703 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9704 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9705 && count
== (unsigned int)
9706 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9707 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9708 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9709 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9711 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9714 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9717 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9718 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9725 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9726 if the truncate does not affect the value. */
9727 if (code
== LSHIFTRT
9728 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9729 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9730 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9731 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9732 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9734 rtx varop_inner
= XEXP (varop
, 0);
9737 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9738 XEXP (varop_inner
, 0),
9740 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9741 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9754 /* We need to determine what mode to do the shift in. If the shift is
9755 a right shift or ROTATE, we must always do it in the mode it was
9756 originally done in. Otherwise, we can do it in MODE, the widest mode
9757 encountered. The code we care about is that of the shift that will
9758 actually be done, not the shift that was originally requested. */
9760 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9761 ? result_mode
: mode
);
9763 /* We have now finished analyzing the shift. The result should be
9764 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9765 OUTER_OP is non-NIL, it is an operation that needs to be applied
9766 to the result of the shift. OUTER_CONST is the relevant constant,
9767 but we must turn off all bits turned off in the shift.
9769 If we were passed a value for X, see if we can use any pieces of
9770 it. If not, make new rtx. */
9772 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9773 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9774 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9775 const_rtx
= XEXP (x
, 1);
9777 const_rtx
= GEN_INT (count
);
9779 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9780 && GET_MODE (XEXP (x
, 0)) == shift_mode
9781 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9782 varop
= XEXP (x
, 0);
9783 else if (GET_MODE (varop
) != shift_mode
)
9784 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9786 /* If we can't make the SUBREG, try to return what we were given. */
9787 if (GET_CODE (varop
) == CLOBBER
)
9788 return x
? x
: varop
;
9790 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9794 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9796 /* If we have an outer operation and we just made a shift, it is
9797 possible that we could have simplified the shift were it not
9798 for the outer operation. So try to do the simplification
9801 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9802 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9803 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9804 INTVAL (XEXP (x
, 1)));
9806 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9807 turn off all the bits that the shift would have turned off. */
9808 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9809 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9810 GET_MODE_MASK (result_mode
) >> orig_count
);
9812 /* Do the remainder of the processing in RESULT_MODE. */
9813 x
= gen_lowpart_for_combine (result_mode
, x
);
9815 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9818 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9820 if (outer_op
!= NIL
)
9822 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9823 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9825 if (outer_op
== AND
)
9826 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9827 else if (outer_op
== SET
)
9828 /* This means that we have determined that the result is
9829 equivalent to a constant. This should be rare. */
9830 x
= GEN_INT (outer_const
);
9831 else if (GET_RTX_CLASS (outer_op
) == '1')
9832 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9834 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9840 /* Like recog, but we receive the address of a pointer to a new pattern.
9841 We try to match the rtx that the pointer points to.
9842 If that fails, we may try to modify or replace the pattern,
9843 storing the replacement into the same pointer object.
9845 Modifications include deletion or addition of CLOBBERs.
9847 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9848 the CLOBBERs are placed.
9850 The value is the final insn code from the pattern ultimately matched,
9854 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9857 int insn_code_number
;
9858 int num_clobbers_to_add
= 0;
9863 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9864 we use to indicate that something didn't match. If we find such a
9865 thing, force rejection. */
9866 if (GET_CODE (pat
) == PARALLEL
)
9867 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9868 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9869 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9872 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9873 instruction for pattern recognition. */
9874 dummy_insn
= shallow_copy_rtx (insn
);
9875 PATTERN (dummy_insn
) = pat
;
9876 REG_NOTES (dummy_insn
) = 0;
9878 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9880 /* If it isn't, there is the possibility that we previously had an insn
9881 that clobbered some register as a side effect, but the combined
9882 insn doesn't need to do that. So try once more without the clobbers
9883 unless this represents an ASM insn. */
9885 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9886 && GET_CODE (pat
) == PARALLEL
)
9890 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9891 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9894 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9898 SUBST_INT (XVECLEN (pat
, 0), pos
);
9901 pat
= XVECEXP (pat
, 0, 0);
9903 PATTERN (dummy_insn
) = pat
;
9904 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9907 /* Recognize all noop sets, these will be killed by followup pass. */
9908 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9909 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9911 /* If we had any clobbers to add, make a new pattern than contains
9912 them. Then check to make sure that all of them are dead. */
9913 if (num_clobbers_to_add
)
9915 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9916 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9918 + num_clobbers_to_add
)
9919 : num_clobbers_to_add
+ 1));
9921 if (GET_CODE (pat
) == PARALLEL
)
9922 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9923 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9925 XVECEXP (newpat
, 0, 0) = pat
;
9927 add_clobbers (newpat
, insn_code_number
);
9929 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9930 i
< XVECLEN (newpat
, 0); i
++)
9932 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9933 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9935 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9936 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9944 return insn_code_number
;
9947 /* Like gen_lowpart but for use by combine. In combine it is not possible
9948 to create any new pseudoregs. However, it is safe to create
9949 invalid memory addresses, because combine will try to recognize
9950 them and all they will do is make the combine attempt fail.
9952 If for some reason this cannot do its job, an rtx
9953 (clobber (const_int 0)) is returned.
9954 An insn containing that will not be recognized. */
9959 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
9963 if (GET_MODE (x
) == mode
)
9966 /* Return identity if this is a CONST or symbolic
9969 && (GET_CODE (x
) == CONST
9970 || GET_CODE (x
) == SYMBOL_REF
9971 || GET_CODE (x
) == LABEL_REF
))
9974 /* We can only support MODE being wider than a word if X is a
9975 constant integer or has a mode the same size. */
9977 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9978 && ! ((GET_MODE (x
) == VOIDmode
9979 && (GET_CODE (x
) == CONST_INT
9980 || GET_CODE (x
) == CONST_DOUBLE
))
9981 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9982 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9984 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9985 won't know what to do. So we will strip off the SUBREG here and
9986 process normally. */
9987 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9990 if (GET_MODE (x
) == mode
)
9994 result
= gen_lowpart_common (mode
, x
);
9995 #ifdef CANNOT_CHANGE_MODE_CLASS
9997 && GET_CODE (result
) == SUBREG
9998 && GET_CODE (SUBREG_REG (result
)) == REG
9999 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10000 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10002 + GET_MODE (result
));
10008 if (GET_CODE (x
) == MEM
)
10012 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10014 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10015 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10017 /* If we want to refer to something bigger than the original memref,
10018 generate a perverse subreg instead. That will force a reload
10019 of the original memref X. */
10020 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10021 return gen_rtx_SUBREG (mode
, x
, 0);
10023 if (WORDS_BIG_ENDIAN
)
10024 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10025 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10027 if (BYTES_BIG_ENDIAN
)
10029 /* Adjust the address so that the address-after-the-data is
10031 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10032 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10035 return adjust_address_nv (x
, mode
, offset
);
10038 /* If X is a comparison operator, rewrite it in a new mode. This
10039 probably won't match, but may allow further simplifications. */
10040 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10041 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10043 /* If we couldn't simplify X any other way, just enclose it in a
10044 SUBREG. Normally, this SUBREG won't match, but some patterns may
10045 include an explicit SUBREG or we may simplify it further in combine. */
10050 enum machine_mode sub_mode
= GET_MODE (x
);
10052 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10053 if (sub_mode
== VOIDmode
)
10055 sub_mode
= int_mode_for_mode (mode
);
10056 x
= gen_lowpart_common (sub_mode
, x
);
10058 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10060 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10063 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10067 /* These routines make binary and unary operations by first seeing if they
10068 fold; if not, a new expression is allocated. */
10071 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10076 if (GET_CODE (op0
) == CLOBBER
)
10078 else if (GET_CODE (op1
) == CLOBBER
)
10081 if (GET_RTX_CLASS (code
) == 'c'
10082 && swap_commutative_operands_p (op0
, op1
))
10083 tem
= op0
, op0
= op1
, op1
= tem
;
10085 if (GET_RTX_CLASS (code
) == '<')
10087 enum machine_mode op_mode
= GET_MODE (op0
);
10089 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10090 just (REL_OP X Y). */
10091 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10093 op1
= XEXP (op0
, 1);
10094 op0
= XEXP (op0
, 0);
10095 op_mode
= GET_MODE (op0
);
10098 if (op_mode
== VOIDmode
)
10099 op_mode
= GET_MODE (op1
);
10100 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10103 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10108 /* Put complex operands first and constants second. */
10109 if (GET_RTX_CLASS (code
) == 'c'
10110 && swap_commutative_operands_p (op0
, op1
))
10111 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10113 /* If we are turning off bits already known off in OP0, we need not do
10115 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10116 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10117 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10120 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10123 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10124 comparison code that will be tested.
10126 The result is a possibly different comparison code to use. *POP0 and
10127 *POP1 may be updated.
10129 It is possible that we might detect that a comparison is either always
10130 true or always false. However, we do not perform general constant
10131 folding in combine, so this knowledge isn't useful. Such tautologies
10132 should have been detected earlier. Hence we ignore all such cases. */
10134 static enum rtx_code
10135 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10141 enum machine_mode mode
, tmode
;
10143 /* Try a few ways of applying the same transformation to both operands. */
10146 #ifndef WORD_REGISTER_OPERATIONS
10147 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10148 so check specially. */
10149 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10150 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10151 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10152 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10153 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10154 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10155 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10156 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10157 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10158 && XEXP (op0
, 1) == XEXP (op1
, 1)
10159 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10160 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10161 && (INTVAL (XEXP (op0
, 1))
10162 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10163 - (GET_MODE_BITSIZE
10164 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10166 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10167 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10171 /* If both operands are the same constant shift, see if we can ignore the
10172 shift. We can if the shift is a rotate or if the bits shifted out of
10173 this shift are known to be zero for both inputs and if the type of
10174 comparison is compatible with the shift. */
10175 if (GET_CODE (op0
) == GET_CODE (op1
)
10176 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10177 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10178 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10179 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10180 || (GET_CODE (op0
) == ASHIFTRT
10181 && (code
!= GTU
&& code
!= LTU
10182 && code
!= GEU
&& code
!= LEU
)))
10183 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10184 && INTVAL (XEXP (op0
, 1)) >= 0
10185 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10186 && XEXP (op0
, 1) == XEXP (op1
, 1))
10188 enum machine_mode mode
= GET_MODE (op0
);
10189 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10190 int shift_count
= INTVAL (XEXP (op0
, 1));
10192 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10193 mask
&= (mask
>> shift_count
) << shift_count
;
10194 else if (GET_CODE (op0
) == ASHIFT
)
10195 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10197 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10198 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10199 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10204 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10205 SUBREGs are of the same mode, and, in both cases, the AND would
10206 be redundant if the comparison was done in the narrower mode,
10207 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10208 and the operand's possibly nonzero bits are 0xffffff01; in that case
10209 if we only care about QImode, we don't need the AND). This case
10210 occurs if the output mode of an scc insn is not SImode and
10211 STORE_FLAG_VALUE == 1 (e.g., the 386).
10213 Similarly, check for a case where the AND's are ZERO_EXTEND
10214 operations from some narrower mode even though a SUBREG is not
10217 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10218 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10219 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10221 rtx inner_op0
= XEXP (op0
, 0);
10222 rtx inner_op1
= XEXP (op1
, 0);
10223 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10224 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10227 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10228 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10229 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10230 && (GET_MODE (SUBREG_REG (inner_op0
))
10231 == GET_MODE (SUBREG_REG (inner_op1
)))
10232 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10233 <= HOST_BITS_PER_WIDE_INT
)
10234 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10235 GET_MODE (SUBREG_REG (inner_op0
)))))
10236 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10237 GET_MODE (SUBREG_REG (inner_op1
))))))
10239 op0
= SUBREG_REG (inner_op0
);
10240 op1
= SUBREG_REG (inner_op1
);
10242 /* The resulting comparison is always unsigned since we masked
10243 off the original sign bit. */
10244 code
= unsigned_condition (code
);
10250 for (tmode
= GET_CLASS_NARROWEST_MODE
10251 (GET_MODE_CLASS (GET_MODE (op0
)));
10252 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10253 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10255 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10256 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10257 code
= unsigned_condition (code
);
10266 /* If both operands are NOT, we can strip off the outer operation
10267 and adjust the comparison code for swapped operands; similarly for
10268 NEG, except that this must be an equality comparison. */
10269 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10270 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10271 && (code
== EQ
|| code
== NE
)))
10272 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10278 /* If the first operand is a constant, swap the operands and adjust the
10279 comparison code appropriately, but don't do this if the second operand
10280 is already a constant integer. */
10281 if (swap_commutative_operands_p (op0
, op1
))
10283 tem
= op0
, op0
= op1
, op1
= tem
;
10284 code
= swap_condition (code
);
10287 /* We now enter a loop during which we will try to simplify the comparison.
10288 For the most part, we only are concerned with comparisons with zero,
10289 but some things may really be comparisons with zero but not start
10290 out looking that way. */
10292 while (GET_CODE (op1
) == CONST_INT
)
10294 enum machine_mode mode
= GET_MODE (op0
);
10295 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10296 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10297 int equality_comparison_p
;
10298 int sign_bit_comparison_p
;
10299 int unsigned_comparison_p
;
10300 HOST_WIDE_INT const_op
;
10302 /* We only want to handle integral modes. This catches VOIDmode,
10303 CCmode, and the floating-point modes. An exception is that we
10304 can handle VOIDmode if OP0 is a COMPARE or a comparison
10307 if (GET_MODE_CLASS (mode
) != MODE_INT
10308 && ! (mode
== VOIDmode
10309 && (GET_CODE (op0
) == COMPARE
10310 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10313 /* Get the constant we are comparing against and turn off all bits
10314 not on in our mode. */
10315 const_op
= INTVAL (op1
);
10316 if (mode
!= VOIDmode
)
10317 const_op
= trunc_int_for_mode (const_op
, mode
);
10318 op1
= GEN_INT (const_op
);
10320 /* If we are comparing against a constant power of two and the value
10321 being compared can only have that single bit nonzero (e.g., it was
10322 `and'ed with that bit), we can replace this with a comparison
10325 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10326 || code
== LT
|| code
== LTU
)
10327 && mode_width
<= HOST_BITS_PER_WIDE_INT
10328 && exact_log2 (const_op
) >= 0
10329 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10331 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10332 op1
= const0_rtx
, const_op
= 0;
10335 /* Similarly, if we are comparing a value known to be either -1 or
10336 0 with -1, change it to the opposite comparison against zero. */
10339 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10340 || code
== GEU
|| code
== LTU
)
10341 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10343 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10344 op1
= const0_rtx
, const_op
= 0;
10347 /* Do some canonicalizations based on the comparison code. We prefer
10348 comparisons against zero and then prefer equality comparisons.
10349 If we can reduce the size of a constant, we will do that too. */
10354 /* < C is equivalent to <= (C - 1) */
10358 op1
= GEN_INT (const_op
);
10360 /* ... fall through to LE case below. */
10366 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10370 op1
= GEN_INT (const_op
);
10374 /* If we are doing a <= 0 comparison on a value known to have
10375 a zero sign bit, we can replace this with == 0. */
10376 else if (const_op
== 0
10377 && mode_width
<= HOST_BITS_PER_WIDE_INT
10378 && (nonzero_bits (op0
, mode
)
10379 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10384 /* >= C is equivalent to > (C - 1). */
10388 op1
= GEN_INT (const_op
);
10390 /* ... fall through to GT below. */
10396 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10400 op1
= GEN_INT (const_op
);
10404 /* If we are doing a > 0 comparison on a value known to have
10405 a zero sign bit, we can replace this with != 0. */
10406 else if (const_op
== 0
10407 && mode_width
<= HOST_BITS_PER_WIDE_INT
10408 && (nonzero_bits (op0
, mode
)
10409 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10414 /* < C is equivalent to <= (C - 1). */
10418 op1
= GEN_INT (const_op
);
10420 /* ... fall through ... */
10423 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10424 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10425 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10427 const_op
= 0, op1
= const0_rtx
;
10435 /* unsigned <= 0 is equivalent to == 0 */
10439 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10440 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10441 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10443 const_op
= 0, op1
= const0_rtx
;
10449 /* >= C is equivalent to < (C - 1). */
10453 op1
= GEN_INT (const_op
);
10455 /* ... fall through ... */
10458 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10459 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10460 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10462 const_op
= 0, op1
= const0_rtx
;
10470 /* unsigned > 0 is equivalent to != 0 */
10474 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10475 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10476 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10478 const_op
= 0, op1
= const0_rtx
;
10487 /* Compute some predicates to simplify code below. */
10489 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10490 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10491 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10494 /* If this is a sign bit comparison and we can do arithmetic in
10495 MODE, say that we will only be needing the sign bit of OP0. */
10496 if (sign_bit_comparison_p
10497 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10498 op0
= force_to_mode (op0
, mode
,
10500 << (GET_MODE_BITSIZE (mode
) - 1)),
10503 /* Now try cases based on the opcode of OP0. If none of the cases
10504 does a "continue", we exit this loop immediately after the
10507 switch (GET_CODE (op0
))
10510 /* If we are extracting a single bit from a variable position in
10511 a constant that has only a single bit set and are comparing it
10512 with zero, we can convert this into an equality comparison
10513 between the position and the location of the single bit. */
10515 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10516 && XEXP (op0
, 1) == const1_rtx
10517 && equality_comparison_p
&& const_op
== 0
10518 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10520 if (BITS_BIG_ENDIAN
)
10522 enum machine_mode new_mode
10523 = mode_for_extraction (EP_extzv
, 1);
10524 if (new_mode
== MAX_MACHINE_MODE
)
10525 i
= BITS_PER_WORD
- 1 - i
;
10529 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10533 op0
= XEXP (op0
, 2);
10537 /* Result is nonzero iff shift count is equal to I. */
10538 code
= reverse_condition (code
);
10542 /* ... fall through ... */
10545 tem
= expand_compound_operation (op0
);
10554 /* If testing for equality, we can take the NOT of the constant. */
10555 if (equality_comparison_p
10556 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10558 op0
= XEXP (op0
, 0);
10563 /* If just looking at the sign bit, reverse the sense of the
10565 if (sign_bit_comparison_p
)
10567 op0
= XEXP (op0
, 0);
10568 code
= (code
== GE
? LT
: GE
);
10574 /* If testing for equality, we can take the NEG of the constant. */
10575 if (equality_comparison_p
10576 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10578 op0
= XEXP (op0
, 0);
10583 /* The remaining cases only apply to comparisons with zero. */
10587 /* When X is ABS or is known positive,
10588 (neg X) is < 0 if and only if X != 0. */
10590 if (sign_bit_comparison_p
10591 && (GET_CODE (XEXP (op0
, 0)) == ABS
10592 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10593 && (nonzero_bits (XEXP (op0
, 0), mode
)
10594 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10596 op0
= XEXP (op0
, 0);
10597 code
= (code
== LT
? NE
: EQ
);
10601 /* If we have NEG of something whose two high-order bits are the
10602 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10603 if (num_sign_bit_copies (op0
, mode
) >= 2)
10605 op0
= XEXP (op0
, 0);
10606 code
= swap_condition (code
);
10612 /* If we are testing equality and our count is a constant, we
10613 can perform the inverse operation on our RHS. */
10614 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10615 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10616 op1
, XEXP (op0
, 1))) != 0)
10618 op0
= XEXP (op0
, 0);
10623 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10624 a particular bit. Convert it to an AND of a constant of that
10625 bit. This will be converted into a ZERO_EXTRACT. */
10626 if (const_op
== 0 && sign_bit_comparison_p
10627 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10628 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10630 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10633 - INTVAL (XEXP (op0
, 1)))));
10634 code
= (code
== LT
? NE
: EQ
);
10638 /* Fall through. */
10641 /* ABS is ignorable inside an equality comparison with zero. */
10642 if (const_op
== 0 && equality_comparison_p
)
10644 op0
= XEXP (op0
, 0);
10650 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10651 to (compare FOO CONST) if CONST fits in FOO's mode and we
10652 are either testing inequality or have an unsigned comparison
10653 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10654 if (! unsigned_comparison_p
10655 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10656 <= HOST_BITS_PER_WIDE_INT
)
10657 && ((unsigned HOST_WIDE_INT
) const_op
10658 < (((unsigned HOST_WIDE_INT
) 1
10659 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10661 op0
= XEXP (op0
, 0);
10667 /* Check for the case where we are comparing A - C1 with C2,
10668 both constants are smaller than 1/2 the maximum positive
10669 value in MODE, and the comparison is equality or unsigned.
10670 In that case, if A is either zero-extended to MODE or has
10671 sufficient sign bits so that the high-order bit in MODE
10672 is a copy of the sign in the inner mode, we can prove that it is
10673 safe to do the operation in the wider mode. This simplifies
10674 many range checks. */
10676 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10677 && subreg_lowpart_p (op0
)
10678 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10679 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10680 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10681 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10682 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10683 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10684 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10685 GET_MODE (SUBREG_REG (op0
)))
10686 & ~GET_MODE_MASK (mode
))
10687 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10688 GET_MODE (SUBREG_REG (op0
)))
10690 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10691 - GET_MODE_BITSIZE (mode
)))))
10693 op0
= SUBREG_REG (op0
);
10697 /* If the inner mode is narrower and we are extracting the low part,
10698 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10699 if (subreg_lowpart_p (op0
)
10700 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10701 /* Fall through */ ;
10705 /* ... fall through ... */
10708 if ((unsigned_comparison_p
|| equality_comparison_p
)
10709 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10710 <= HOST_BITS_PER_WIDE_INT
)
10711 && ((unsigned HOST_WIDE_INT
) const_op
10712 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10714 op0
= XEXP (op0
, 0);
10720 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10721 this for equality comparisons due to pathological cases involving
10723 if (equality_comparison_p
10724 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10725 op1
, XEXP (op0
, 1))))
10727 op0
= XEXP (op0
, 0);
10732 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10733 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10734 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10736 op0
= XEXP (XEXP (op0
, 0), 0);
10737 code
= (code
== LT
? EQ
: NE
);
10743 /* We used to optimize signed comparisons against zero, but that
10744 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10745 arrive here as equality comparisons, or (GEU, LTU) are
10746 optimized away. No need to special-case them. */
10748 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10749 (eq B (minus A C)), whichever simplifies. We can only do
10750 this for equality comparisons due to pathological cases involving
10752 if (equality_comparison_p
10753 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10754 XEXP (op0
, 1), op1
)))
10756 op0
= XEXP (op0
, 0);
10761 if (equality_comparison_p
10762 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10763 XEXP (op0
, 0), op1
)))
10765 op0
= XEXP (op0
, 1);
10770 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10771 of bits in X minus 1, is one iff X > 0. */
10772 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10773 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10774 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10776 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10778 op0
= XEXP (op0
, 1);
10779 code
= (code
== GE
? LE
: GT
);
10785 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10786 if C is zero or B is a constant. */
10787 if (equality_comparison_p
10788 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10789 XEXP (op0
, 1), op1
)))
10791 op0
= XEXP (op0
, 0);
10798 case UNEQ
: case LTGT
:
10799 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10800 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10801 case UNORDERED
: case ORDERED
:
10802 /* We can't do anything if OP0 is a condition code value, rather
10803 than an actual data value. */
10805 || CC0_P (XEXP (op0
, 0))
10806 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10809 /* Get the two operands being compared. */
10810 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10811 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10813 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10815 /* Check for the cases where we simply want the result of the
10816 earlier test or the opposite of that result. */
10817 if (code
== NE
|| code
== EQ
10818 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10819 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10820 && (STORE_FLAG_VALUE
10821 & (((HOST_WIDE_INT
) 1
10822 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10823 && (code
== LT
|| code
== GE
)))
10825 enum rtx_code new_code
;
10826 if (code
== LT
|| code
== NE
)
10827 new_code
= GET_CODE (op0
);
10829 new_code
= combine_reversed_comparison_code (op0
);
10831 if (new_code
!= UNKNOWN
)
10842 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10844 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10845 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10846 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10848 op0
= XEXP (op0
, 1);
10849 code
= (code
== GE
? GT
: LE
);
10855 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10856 will be converted to a ZERO_EXTRACT later. */
10857 if (const_op
== 0 && equality_comparison_p
10858 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10859 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10861 op0
= simplify_and_const_int
10862 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10864 XEXP (XEXP (op0
, 0), 1)),
10865 (HOST_WIDE_INT
) 1);
10869 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10870 zero and X is a comparison and C1 and C2 describe only bits set
10871 in STORE_FLAG_VALUE, we can compare with X. */
10872 if (const_op
== 0 && equality_comparison_p
10873 && mode_width
<= HOST_BITS_PER_WIDE_INT
10874 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10875 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10876 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10877 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10878 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10880 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10881 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10882 if ((~STORE_FLAG_VALUE
& mask
) == 0
10883 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10884 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10885 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10887 op0
= XEXP (XEXP (op0
, 0), 0);
10892 /* If we are doing an equality comparison of an AND of a bit equal
10893 to the sign bit, replace this with a LT or GE comparison of
10894 the underlying value. */
10895 if (equality_comparison_p
10897 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10898 && mode_width
<= HOST_BITS_PER_WIDE_INT
10899 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10900 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10902 op0
= XEXP (op0
, 0);
10903 code
= (code
== EQ
? GE
: LT
);
10907 /* If this AND operation is really a ZERO_EXTEND from a narrower
10908 mode, the constant fits within that mode, and this is either an
10909 equality or unsigned comparison, try to do this comparison in
10910 the narrower mode. */
10911 if ((equality_comparison_p
|| unsigned_comparison_p
)
10912 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10913 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10914 & GET_MODE_MASK (mode
))
10916 && const_op
>> i
== 0
10917 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10919 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10923 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10924 fits in both M1 and M2 and the SUBREG is either paradoxical
10925 or represents the low part, permute the SUBREG and the AND
10927 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10929 unsigned HOST_WIDE_INT c1
;
10930 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10931 /* Require an integral mode, to avoid creating something like
10933 if (SCALAR_INT_MODE_P (tmode
)
10934 /* It is unsafe to commute the AND into the SUBREG if the
10935 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10936 not defined. As originally written the upper bits
10937 have a defined value due to the AND operation.
10938 However, if we commute the AND inside the SUBREG then
10939 they no longer have defined values and the meaning of
10940 the code has been changed. */
10942 #ifdef WORD_REGISTER_OPERATIONS
10943 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10944 && mode_width
<= BITS_PER_WORD
)
10946 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10947 && subreg_lowpart_p (XEXP (op0
, 0))))
10948 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10949 && mode_width
<= HOST_BITS_PER_WIDE_INT
10950 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10951 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10952 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10954 && c1
!= GET_MODE_MASK (tmode
))
10956 op0
= gen_binary (AND
, tmode
,
10957 SUBREG_REG (XEXP (op0
, 0)),
10958 gen_int_mode (c1
, tmode
));
10959 op0
= gen_lowpart_for_combine (mode
, op0
);
10964 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10965 if (const_op
== 0 && equality_comparison_p
10966 && XEXP (op0
, 1) == const1_rtx
10967 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10969 op0
= simplify_and_const_int
10970 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10971 code
= (code
== NE
? EQ
: NE
);
10975 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10976 (eq (and (lshiftrt X) 1) 0).
10977 Also handle the case where (not X) is expressed using xor. */
10978 if (const_op
== 0 && equality_comparison_p
10979 && XEXP (op0
, 1) == const1_rtx
10980 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10982 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10983 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10985 if (GET_CODE (shift_op
) == NOT
10986 || (GET_CODE (shift_op
) == XOR
10987 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10988 && GET_CODE (shift_count
) == CONST_INT
10989 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10990 && (INTVAL (XEXP (shift_op
, 1))
10991 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10993 op0
= simplify_and_const_int
10995 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10996 (HOST_WIDE_INT
) 1);
10997 code
= (code
== NE
? EQ
: NE
);
11004 /* If we have (compare (ashift FOO N) (const_int C)) and
11005 the high order N bits of FOO (N+1 if an inequality comparison)
11006 are known to be zero, we can do this by comparing FOO with C
11007 shifted right N bits so long as the low-order N bits of C are
11009 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11010 && INTVAL (XEXP (op0
, 1)) >= 0
11011 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11012 < HOST_BITS_PER_WIDE_INT
)
11014 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11015 && mode_width
<= HOST_BITS_PER_WIDE_INT
11016 && (nonzero_bits (XEXP (op0
, 0), mode
)
11017 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11018 + ! equality_comparison_p
))) == 0)
11020 /* We must perform a logical shift, not an arithmetic one,
11021 as we want the top N bits of C to be zero. */
11022 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11024 temp
>>= INTVAL (XEXP (op0
, 1));
11025 op1
= gen_int_mode (temp
, mode
);
11026 op0
= XEXP (op0
, 0);
11030 /* If we are doing a sign bit comparison, it means we are testing
11031 a particular bit. Convert it to the appropriate AND. */
11032 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11033 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11035 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11038 - INTVAL (XEXP (op0
, 1)))));
11039 code
= (code
== LT
? NE
: EQ
);
11043 /* If this an equality comparison with zero and we are shifting
11044 the low bit to the sign bit, we can convert this to an AND of the
11046 if (const_op
== 0 && equality_comparison_p
11047 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11048 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11051 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11052 (HOST_WIDE_INT
) 1);
11058 /* If this is an equality comparison with zero, we can do this
11059 as a logical shift, which might be much simpler. */
11060 if (equality_comparison_p
&& const_op
== 0
11061 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11063 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11065 INTVAL (XEXP (op0
, 1)));
11069 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11070 do the comparison in a narrower mode. */
11071 if (! unsigned_comparison_p
11072 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11073 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11074 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11075 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11076 MODE_INT
, 1)) != BLKmode
11077 && (((unsigned HOST_WIDE_INT
) const_op
11078 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11079 <= GET_MODE_MASK (tmode
)))
11081 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11085 /* Likewise if OP0 is a PLUS of a sign extension with a
11086 constant, which is usually represented with the PLUS
11087 between the shifts. */
11088 if (! unsigned_comparison_p
11089 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11090 && GET_CODE (XEXP (op0
, 0)) == PLUS
11091 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11092 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11093 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11094 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11095 MODE_INT
, 1)) != BLKmode
11096 && (((unsigned HOST_WIDE_INT
) const_op
11097 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11098 <= GET_MODE_MASK (tmode
)))
11100 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11101 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11102 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11105 op0
= gen_binary (PLUS
, tmode
,
11106 gen_lowpart_for_combine (tmode
, inner
),
11111 /* ... fall through ... */
11113 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11114 the low order N bits of FOO are known to be zero, we can do this
11115 by comparing FOO with C shifted left N bits so long as no
11116 overflow occurs. */
11117 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11118 && INTVAL (XEXP (op0
, 1)) >= 0
11119 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11120 && mode_width
<= HOST_BITS_PER_WIDE_INT
11121 && (nonzero_bits (XEXP (op0
, 0), mode
)
11122 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11123 && (((unsigned HOST_WIDE_INT
) const_op
11124 + (GET_CODE (op0
) != LSHIFTRT
11125 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11128 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11130 /* If the shift was logical, then we must make the condition
11132 if (GET_CODE (op0
) == LSHIFTRT
)
11133 code
= unsigned_condition (code
);
11135 const_op
<<= INTVAL (XEXP (op0
, 1));
11136 op1
= GEN_INT (const_op
);
11137 op0
= XEXP (op0
, 0);
11141 /* If we are using this shift to extract just the sign bit, we
11142 can replace this with an LT or GE comparison. */
11144 && (equality_comparison_p
|| sign_bit_comparison_p
)
11145 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11146 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11149 op0
= XEXP (op0
, 0);
11150 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11162 /* Now make any compound operations involved in this comparison. Then,
11163 check for an outmost SUBREG on OP0 that is not doing anything or is
11164 paradoxical. The latter transformation must only be performed when
11165 it is known that the "extra" bits will be the same in op0 and op1 or
11166 that they don't matter. There are three cases to consider:
11168 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11169 care bits and we can assume they have any convenient value. So
11170 making the transformation is safe.
11172 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11173 In this case the upper bits of op0 are undefined. We should not make
11174 the simplification in that case as we do not know the contents of
11177 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11178 NIL. In that case we know those bits are zeros or ones. We must
11179 also be sure that they are the same as the upper bits of op1.
11181 We can never remove a SUBREG for a non-equality comparison because
11182 the sign bit is in a different place in the underlying object. */
11184 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11185 op1
= make_compound_operation (op1
, SET
);
11187 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11188 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11189 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11190 && (code
== NE
|| code
== EQ
))
11192 if (GET_MODE_SIZE (GET_MODE (op0
))
11193 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11195 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11197 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
11199 op0
= SUBREG_REG (op0
);
11200 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11203 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11204 <= HOST_BITS_PER_WIDE_INT
)
11205 && (nonzero_bits (SUBREG_REG (op0
),
11206 GET_MODE (SUBREG_REG (op0
)))
11207 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11209 tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)), op1
);
11211 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11212 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11213 op0
= SUBREG_REG (op0
), op1
= tem
;
11217 /* We now do the opposite procedure: Some machines don't have compare
11218 insns in all modes. If OP0's mode is an integer mode smaller than a
11219 word and we can't do a compare in that mode, see if there is a larger
11220 mode for which we can do the compare. There are a number of cases in
11221 which we can use the wider mode. */
11223 mode
= GET_MODE (op0
);
11224 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11225 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11226 && ! have_insn_for (COMPARE
, mode
))
11227 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11229 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11230 tmode
= GET_MODE_WIDER_MODE (tmode
))
11231 if (have_insn_for (COMPARE
, tmode
))
11235 /* If the only nonzero bits in OP0 and OP1 are those in the
11236 narrower mode and this is an equality or unsigned comparison,
11237 we can use the wider mode. Similarly for sign-extended
11238 values, in which case it is true for all comparisons. */
11239 zero_extended
= ((code
== EQ
|| code
== NE
11240 || code
== GEU
|| code
== GTU
11241 || code
== LEU
|| code
== LTU
)
11242 && (nonzero_bits (op0
, tmode
)
11243 & ~GET_MODE_MASK (mode
)) == 0
11244 && ((GET_CODE (op1
) == CONST_INT
11245 || (nonzero_bits (op1
, tmode
)
11246 & ~GET_MODE_MASK (mode
)) == 0)));
11249 || ((num_sign_bit_copies (op0
, tmode
)
11250 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11251 - GET_MODE_BITSIZE (mode
)))
11252 && (num_sign_bit_copies (op1
, tmode
)
11253 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11254 - GET_MODE_BITSIZE (mode
)))))
11256 /* If OP0 is an AND and we don't have an AND in MODE either,
11257 make a new AND in the proper mode. */
11258 if (GET_CODE (op0
) == AND
11259 && !have_insn_for (AND
, mode
))
11260 op0
= gen_binary (AND
, tmode
,
11261 gen_lowpart_for_combine (tmode
,
11263 gen_lowpart_for_combine (tmode
,
11266 op0
= gen_lowpart_for_combine (tmode
, op0
);
11267 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11268 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11269 op1
= gen_lowpart_for_combine (tmode
, op1
);
11273 /* If this is a test for negative, we can make an explicit
11274 test of the sign bit. */
11276 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11277 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11279 op0
= gen_binary (AND
, tmode
,
11280 gen_lowpart_for_combine (tmode
, op0
),
11281 GEN_INT ((HOST_WIDE_INT
) 1
11282 << (GET_MODE_BITSIZE (mode
) - 1)));
11283 code
= (code
== LT
) ? NE
: EQ
;
11288 #ifdef CANONICALIZE_COMPARISON
11289 /* If this machine only supports a subset of valid comparisons, see if we
11290 can convert an unsupported one into a supported one. */
11291 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11300 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11301 searching backward. */
11302 static enum rtx_code
11303 combine_reversed_comparison_code (rtx exp
)
11305 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11308 if (code1
!= UNKNOWN
11309 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11311 /* Otherwise try and find where the condition codes were last set and
11313 x
= get_last_value (XEXP (exp
, 0));
11314 if (!x
|| GET_CODE (x
) != COMPARE
)
11316 return reversed_comparison_code_parts (GET_CODE (exp
),
11317 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11320 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11321 Return NULL_RTX in case we fail to do the reversal. */
11323 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11325 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11326 if (reversed_code
== UNKNOWN
)
11329 return gen_binary (reversed_code
, mode
, op0
, op1
);
11332 /* Utility function for following routine. Called when X is part of a value
11333 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11334 for each register mentioned. Similar to mention_regs in cse.c */
11337 update_table_tick (rtx x
)
11339 enum rtx_code code
= GET_CODE (x
);
11340 const char *fmt
= GET_RTX_FORMAT (code
);
11345 unsigned int regno
= REGNO (x
);
11346 unsigned int endregno
11347 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11348 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11351 for (r
= regno
; r
< endregno
; r
++)
11352 reg_last_set_table_tick
[r
] = label_tick
;
11357 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11358 /* Note that we can't have an "E" in values stored; see
11359 get_last_value_validate. */
11362 /* Check for identical subexpressions. If x contains
11363 identical subexpression we only have to traverse one of
11366 && (GET_RTX_CLASS (code
) == '2'
11367 || GET_RTX_CLASS (code
) == 'c'))
11369 /* Note that at this point x1 has already been
11371 rtx x0
= XEXP (x
, 0);
11372 rtx x1
= XEXP (x
, 1);
11374 /* If x0 and x1 are identical then there is no need to
11379 /* If x0 is identical to a subexpression of x1 then while
11380 processing x1, x0 has already been processed. Thus we
11381 are done with x. */
11382 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11383 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11384 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11387 /* If x1 is identical to a subexpression of x0 then we
11388 still have to process the rest of x0. */
11389 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11390 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11391 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11393 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11398 update_table_tick (XEXP (x
, i
));
11402 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11403 are saying that the register is clobbered and we no longer know its
11404 value. If INSN is zero, don't update reg_last_set; this is only permitted
11405 with VALUE also zero and is used to invalidate the register. */
11408 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11410 unsigned int regno
= REGNO (reg
);
11411 unsigned int endregno
11412 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11413 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11416 /* If VALUE contains REG and we have a previous value for REG, substitute
11417 the previous value. */
11418 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11422 /* Set things up so get_last_value is allowed to see anything set up to
11424 subst_low_cuid
= INSN_CUID (insn
);
11425 tem
= get_last_value (reg
);
11427 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11428 it isn't going to be useful and will take a lot of time to process,
11429 so just use the CLOBBER. */
11433 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11434 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11435 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11436 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11437 tem
= XEXP (tem
, 0);
11439 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11443 /* For each register modified, show we don't know its value, that
11444 we don't know about its bitwise content, that its value has been
11445 updated, and that we don't know the location of the death of the
11447 for (i
= regno
; i
< endregno
; i
++)
11450 reg_last_set
[i
] = insn
;
11452 reg_last_set_value
[i
] = 0;
11453 reg_last_set_mode
[i
] = 0;
11454 reg_last_set_nonzero_bits
[i
] = 0;
11455 reg_last_set_sign_bit_copies
[i
] = 0;
11456 reg_last_death
[i
] = 0;
11459 /* Mark registers that are being referenced in this value. */
11461 update_table_tick (value
);
11463 /* Now update the status of each register being set.
11464 If someone is using this register in this block, set this register
11465 to invalid since we will get confused between the two lives in this
11466 basic block. This makes using this register always invalid. In cse, we
11467 scan the table to invalidate all entries using this register, but this
11468 is too much work for us. */
11470 for (i
= regno
; i
< endregno
; i
++)
11472 reg_last_set_label
[i
] = label_tick
;
11473 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11474 reg_last_set_invalid
[i
] = 1;
11476 reg_last_set_invalid
[i
] = 0;
11479 /* The value being assigned might refer to X (like in "x++;"). In that
11480 case, we must replace it with (clobber (const_int 0)) to prevent
11482 if (value
&& ! get_last_value_validate (&value
, insn
,
11483 reg_last_set_label
[regno
], 0))
11485 value
= copy_rtx (value
);
11486 if (! get_last_value_validate (&value
, insn
,
11487 reg_last_set_label
[regno
], 1))
11491 /* For the main register being modified, update the value, the mode, the
11492 nonzero bits, and the number of sign bit copies. */
11494 reg_last_set_value
[regno
] = value
;
11498 enum machine_mode mode
= GET_MODE (reg
);
11499 subst_low_cuid
= INSN_CUID (insn
);
11500 reg_last_set_mode
[regno
] = mode
;
11501 if (GET_MODE_CLASS (mode
) == MODE_INT
11502 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11503 mode
= nonzero_bits_mode
;
11504 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11505 reg_last_set_sign_bit_copies
[regno
]
11506 = num_sign_bit_copies (value
, GET_MODE (reg
));
11510 /* Called via note_stores from record_dead_and_set_regs to handle one
11511 SET or CLOBBER in an insn. DATA is the instruction in which the
11512 set is occurring. */
11515 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11517 rtx record_dead_insn
= (rtx
) data
;
11519 if (GET_CODE (dest
) == SUBREG
)
11520 dest
= SUBREG_REG (dest
);
11522 if (GET_CODE (dest
) == REG
)
11524 /* If we are setting the whole register, we know its value. Otherwise
11525 show that we don't know the value. We can handle SUBREG in
11527 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11528 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11529 else if (GET_CODE (setter
) == SET
11530 && GET_CODE (SET_DEST (setter
)) == SUBREG
11531 && SUBREG_REG (SET_DEST (setter
)) == dest
11532 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11533 && subreg_lowpart_p (SET_DEST (setter
)))
11534 record_value_for_reg (dest
, record_dead_insn
,
11535 gen_lowpart_for_combine (GET_MODE (dest
),
11536 SET_SRC (setter
)));
11538 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11540 else if (GET_CODE (dest
) == MEM
11541 /* Ignore pushes, they clobber nothing. */
11542 && ! push_operand (dest
, GET_MODE (dest
)))
11543 mem_last_set
= INSN_CUID (record_dead_insn
);
11546 /* Update the records of when each REG was most recently set or killed
11547 for the things done by INSN. This is the last thing done in processing
11548 INSN in the combiner loop.
11550 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11551 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11552 and also the similar information mem_last_set (which insn most recently
11553 modified memory) and last_call_cuid (which insn was the most recent
11554 subroutine call). */
11557 record_dead_and_set_regs (rtx insn
)
11562 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11564 if (REG_NOTE_KIND (link
) == REG_DEAD
11565 && GET_CODE (XEXP (link
, 0)) == REG
)
11567 unsigned int regno
= REGNO (XEXP (link
, 0));
11568 unsigned int endregno
11569 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11570 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11573 for (i
= regno
; i
< endregno
; i
++)
11574 reg_last_death
[i
] = insn
;
11576 else if (REG_NOTE_KIND (link
) == REG_INC
)
11577 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11580 if (GET_CODE (insn
) == CALL_INSN
)
11582 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11583 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11585 reg_last_set_value
[i
] = 0;
11586 reg_last_set_mode
[i
] = 0;
11587 reg_last_set_nonzero_bits
[i
] = 0;
11588 reg_last_set_sign_bit_copies
[i
] = 0;
11589 reg_last_death
[i
] = 0;
11592 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11594 /* Don't bother recording what this insn does. It might set the
11595 return value register, but we can't combine into a call
11596 pattern anyway, so there's no point trying (and it may cause
11597 a crash, if e.g. we wind up asking for last_set_value of a
11598 SUBREG of the return value register). */
11602 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11605 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11606 register present in the SUBREG, so for each such SUBREG go back and
11607 adjust nonzero and sign bit information of the registers that are
11608 known to have some zero/sign bits set.
11610 This is needed because when combine blows the SUBREGs away, the
11611 information on zero/sign bits is lost and further combines can be
11612 missed because of that. */
11615 record_promoted_value (rtx insn
, rtx subreg
)
11618 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11619 enum machine_mode mode
= GET_MODE (subreg
);
11621 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11624 for (links
= LOG_LINKS (insn
); links
;)
11626 insn
= XEXP (links
, 0);
11627 set
= single_set (insn
);
11629 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11630 || REGNO (SET_DEST (set
)) != regno
11631 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11633 links
= XEXP (links
, 1);
11637 if (reg_last_set
[regno
] == insn
)
11639 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11640 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11643 if (GET_CODE (SET_SRC (set
)) == REG
)
11645 regno
= REGNO (SET_SRC (set
));
11646 links
= LOG_LINKS (insn
);
11653 /* Scan X for promoted SUBREGs. For each one found,
11654 note what it implies to the registers used in it. */
11657 check_promoted_subreg (rtx insn
, rtx x
)
11659 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11660 && GET_CODE (SUBREG_REG (x
)) == REG
)
11661 record_promoted_value (insn
, x
);
11664 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11667 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11671 check_promoted_subreg (insn
, XEXP (x
, i
));
11675 if (XVEC (x
, i
) != 0)
11676 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11677 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11683 /* Utility routine for the following function. Verify that all the registers
11684 mentioned in *LOC are valid when *LOC was part of a value set when
11685 label_tick == TICK. Return 0 if some are not.
11687 If REPLACE is nonzero, replace the invalid reference with
11688 (clobber (const_int 0)) and return 1. This replacement is useful because
11689 we often can get useful information about the form of a value (e.g., if
11690 it was produced by a shift that always produces -1 or 0) even though
11691 we don't know exactly what registers it was produced from. */
11694 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11697 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11698 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11701 if (GET_CODE (x
) == REG
)
11703 unsigned int regno
= REGNO (x
);
11704 unsigned int endregno
11705 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11706 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11709 for (j
= regno
; j
< endregno
; j
++)
11710 if (reg_last_set_invalid
[j
]
11711 /* If this is a pseudo-register that was only set once and not
11712 live at the beginning of the function, it is always valid. */
11713 || (! (regno
>= FIRST_PSEUDO_REGISTER
11714 && REG_N_SETS (regno
) == 1
11715 && (! REGNO_REG_SET_P
11716 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11717 && reg_last_set_label
[j
] > tick
))
11720 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11726 /* If this is a memory reference, make sure that there were
11727 no stores after it that might have clobbered the value. We don't
11728 have alias info, so we assume any store invalidates it. */
11729 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11730 && INSN_CUID (insn
) <= mem_last_set
)
11733 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11737 for (i
= 0; i
< len
; i
++)
11741 /* Check for identical subexpressions. If x contains
11742 identical subexpression we only have to traverse one of
11745 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11746 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11748 /* Note that at this point x0 has already been checked
11749 and found valid. */
11750 rtx x0
= XEXP (x
, 0);
11751 rtx x1
= XEXP (x
, 1);
11753 /* If x0 and x1 are identical then x is also valid. */
11757 /* If x1 is identical to a subexpression of x0 then
11758 while checking x0, x1 has already been checked. Thus
11759 it is valid and so as x. */
11760 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11761 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11762 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11765 /* If x0 is identical to a subexpression of x1 then x is
11766 valid iff the rest of x1 is valid. */
11767 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11768 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11769 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11771 get_last_value_validate (&XEXP (x1
,
11772 x0
== XEXP (x1
, 0) ? 1 : 0),
11773 insn
, tick
, replace
);
11776 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11780 /* Don't bother with these. They shouldn't occur anyway. */
11781 else if (fmt
[i
] == 'E')
11785 /* If we haven't found a reason for it to be invalid, it is valid. */
11789 /* Get the last value assigned to X, if known. Some registers
11790 in the value may be replaced with (clobber (const_int 0)) if their value
11791 is known longer known reliably. */
11794 get_last_value (rtx x
)
11796 unsigned int regno
;
11799 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11800 then convert it to the desired mode. If this is a paradoxical SUBREG,
11801 we cannot predict what values the "extra" bits might have. */
11802 if (GET_CODE (x
) == SUBREG
11803 && subreg_lowpart_p (x
)
11804 && (GET_MODE_SIZE (GET_MODE (x
))
11805 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11806 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11807 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11809 if (GET_CODE (x
) != REG
)
11813 value
= reg_last_set_value
[regno
];
11815 /* If we don't have a value, or if it isn't for this basic block and
11816 it's either a hard register, set more than once, or it's a live
11817 at the beginning of the function, return 0.
11819 Because if it's not live at the beginning of the function then the reg
11820 is always set before being used (is never used without being set).
11821 And, if it's set only once, and it's always set before use, then all
11822 uses must have the same last value, even if it's not from this basic
11826 || (reg_last_set_label
[regno
] != label_tick
11827 && (regno
< FIRST_PSEUDO_REGISTER
11828 || REG_N_SETS (regno
) != 1
11829 || (REGNO_REG_SET_P
11830 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11833 /* If the value was set in a later insn than the ones we are processing,
11834 we can't use it even if the register was only set once. */
11835 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11838 /* If the value has all its registers valid, return it. */
11839 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11840 reg_last_set_label
[regno
], 0))
11843 /* Otherwise, make a copy and replace any invalid register with
11844 (clobber (const_int 0)). If that fails for some reason, return 0. */
11846 value
= copy_rtx (value
);
11847 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11848 reg_last_set_label
[regno
], 1))
11854 /* Return nonzero if expression X refers to a REG or to memory
11855 that is set in an instruction more recent than FROM_CUID. */
11858 use_crosses_set_p (rtx x
, int from_cuid
)
11862 enum rtx_code code
= GET_CODE (x
);
11866 unsigned int regno
= REGNO (x
);
11867 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11868 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11870 #ifdef PUSH_ROUNDING
11871 /* Don't allow uses of the stack pointer to be moved,
11872 because we don't know whether the move crosses a push insn. */
11873 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11876 for (; regno
< endreg
; regno
++)
11877 if (reg_last_set
[regno
]
11878 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11883 if (code
== MEM
&& mem_last_set
> from_cuid
)
11886 fmt
= GET_RTX_FORMAT (code
);
11888 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11893 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11894 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11897 else if (fmt
[i
] == 'e'
11898 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11904 /* Define three variables used for communication between the following
11907 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11908 static int reg_dead_flag
;
11910 /* Function called via note_stores from reg_dead_at_p.
11912 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11913 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11916 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11918 unsigned int regno
, endregno
;
11920 if (GET_CODE (dest
) != REG
)
11923 regno
= REGNO (dest
);
11924 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11925 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11927 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11928 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11931 /* Return nonzero if REG is known to be dead at INSN.
11933 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11934 referencing REG, it is dead. If we hit a SET referencing REG, it is
11935 live. Otherwise, see if it is live or dead at the start of the basic
11936 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11937 must be assumed to be always live. */
11940 reg_dead_at_p (rtx reg
, rtx insn
)
11945 /* Set variables for reg_dead_at_p_1. */
11946 reg_dead_regno
= REGNO (reg
);
11947 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11948 ? HARD_REGNO_NREGS (reg_dead_regno
,
11954 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11955 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11957 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11958 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11962 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11963 beginning of function. */
11964 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11965 insn
= prev_nonnote_insn (insn
))
11967 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11969 return reg_dead_flag
== 1 ? 1 : 0;
11971 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11975 /* Get the basic block that we were in. */
11977 block
= ENTRY_BLOCK_PTR
->next_bb
;
11980 FOR_EACH_BB (block
)
11981 if (insn
== BB_HEAD (block
))
11984 if (block
== EXIT_BLOCK_PTR
)
11988 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11989 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11995 /* Note hard registers in X that are used. This code is similar to
11996 that in flow.c, but much simpler since we don't care about pseudos. */
11999 mark_used_regs_combine (rtx x
)
12001 RTX_CODE code
= GET_CODE (x
);
12002 unsigned int regno
;
12015 case ADDR_DIFF_VEC
:
12018 /* CC0 must die in the insn after it is set, so we don't need to take
12019 special note of it here. */
12025 /* If we are clobbering a MEM, mark any hard registers inside the
12026 address as used. */
12027 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12028 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12033 /* A hard reg in a wide mode may really be multiple registers.
12034 If so, mark all of them just like the first. */
12035 if (regno
< FIRST_PSEUDO_REGISTER
)
12037 unsigned int endregno
, r
;
12039 /* None of this applies to the stack, frame or arg pointers. */
12040 if (regno
== STACK_POINTER_REGNUM
12041 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12042 || regno
== HARD_FRAME_POINTER_REGNUM
12044 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12045 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12047 || regno
== FRAME_POINTER_REGNUM
)
12050 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12051 for (r
= regno
; r
< endregno
; r
++)
12052 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12058 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12060 rtx testreg
= SET_DEST (x
);
12062 while (GET_CODE (testreg
) == SUBREG
12063 || GET_CODE (testreg
) == ZERO_EXTRACT
12064 || GET_CODE (testreg
) == SIGN_EXTRACT
12065 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12066 testreg
= XEXP (testreg
, 0);
12068 if (GET_CODE (testreg
) == MEM
)
12069 mark_used_regs_combine (XEXP (testreg
, 0));
12071 mark_used_regs_combine (SET_SRC (x
));
12079 /* Recursively scan the operands of this expression. */
12082 const char *fmt
= GET_RTX_FORMAT (code
);
12084 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12087 mark_used_regs_combine (XEXP (x
, i
));
12088 else if (fmt
[i
] == 'E')
12092 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12093 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12099 /* Remove register number REGNO from the dead registers list of INSN.
12101 Return the note used to record the death, if there was one. */
12104 remove_death (unsigned int regno
, rtx insn
)
12106 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12110 REG_N_DEATHS (regno
)--;
12111 remove_note (insn
, note
);
12117 /* For each register (hardware or pseudo) used within expression X, if its
12118 death is in an instruction with cuid between FROM_CUID (inclusive) and
12119 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12120 list headed by PNOTES.
12122 That said, don't move registers killed by maybe_kill_insn.
12124 This is done when X is being merged by combination into TO_INSN. These
12125 notes will then be distributed as needed. */
12128 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12133 enum rtx_code code
= GET_CODE (x
);
12137 unsigned int regno
= REGNO (x
);
12138 rtx where_dead
= reg_last_death
[regno
];
12139 rtx before_dead
, after_dead
;
12141 /* Don't move the register if it gets killed in between from and to. */
12142 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12143 && ! reg_referenced_p (x
, maybe_kill_insn
))
12146 /* WHERE_DEAD could be a USE insn made by combine, so first we
12147 make sure that we have insns with valid INSN_CUID values. */
12148 before_dead
= where_dead
;
12149 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12150 before_dead
= PREV_INSN (before_dead
);
12152 after_dead
= where_dead
;
12153 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12154 after_dead
= NEXT_INSN (after_dead
);
12156 if (before_dead
&& after_dead
12157 && INSN_CUID (before_dead
) >= from_cuid
12158 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12159 || (where_dead
!= after_dead
12160 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12162 rtx note
= remove_death (regno
, where_dead
);
12164 /* It is possible for the call above to return 0. This can occur
12165 when reg_last_death points to I2 or I1 that we combined with.
12166 In that case make a new note.
12168 We must also check for the case where X is a hard register
12169 and NOTE is a death note for a range of hard registers
12170 including X. In that case, we must put REG_DEAD notes for
12171 the remaining registers in place of NOTE. */
12173 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12174 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12175 > GET_MODE_SIZE (GET_MODE (x
))))
12177 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12178 unsigned int deadend
12179 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12180 GET_MODE (XEXP (note
, 0))));
12181 unsigned int ourend
12182 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12185 for (i
= deadregno
; i
< deadend
; i
++)
12186 if (i
< regno
|| i
>= ourend
)
12187 REG_NOTES (where_dead
)
12188 = gen_rtx_EXPR_LIST (REG_DEAD
,
12190 REG_NOTES (where_dead
));
12193 /* If we didn't find any note, or if we found a REG_DEAD note that
12194 covers only part of the given reg, and we have a multi-reg hard
12195 register, then to be safe we must check for REG_DEAD notes
12196 for each register other than the first. They could have
12197 their own REG_DEAD notes lying around. */
12198 else if ((note
== 0
12200 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12201 < GET_MODE_SIZE (GET_MODE (x
)))))
12202 && regno
< FIRST_PSEUDO_REGISTER
12203 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12205 unsigned int ourend
12206 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12207 unsigned int i
, offset
;
12211 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12215 for (i
= regno
+ offset
; i
< ourend
; i
++)
12216 move_deaths (regno_reg_rtx
[i
],
12217 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12220 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12222 XEXP (note
, 1) = *pnotes
;
12226 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12228 REG_N_DEATHS (regno
)++;
12234 else if (GET_CODE (x
) == SET
)
12236 rtx dest
= SET_DEST (x
);
12238 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12240 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12241 that accesses one word of a multi-word item, some
12242 piece of everything register in the expression is used by
12243 this insn, so remove any old death. */
12244 /* ??? So why do we test for equality of the sizes? */
12246 if (GET_CODE (dest
) == ZERO_EXTRACT
12247 || GET_CODE (dest
) == STRICT_LOW_PART
12248 || (GET_CODE (dest
) == SUBREG
12249 && (((GET_MODE_SIZE (GET_MODE (dest
))
12250 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12251 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12252 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12254 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12258 /* If this is some other SUBREG, we know it replaces the entire
12259 value, so use that as the destination. */
12260 if (GET_CODE (dest
) == SUBREG
)
12261 dest
= SUBREG_REG (dest
);
12263 /* If this is a MEM, adjust deaths of anything used in the address.
12264 For a REG (the only other possibility), the entire value is
12265 being replaced so the old value is not used in this insn. */
12267 if (GET_CODE (dest
) == MEM
)
12268 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12273 else if (GET_CODE (x
) == CLOBBER
)
12276 len
= GET_RTX_LENGTH (code
);
12277 fmt
= GET_RTX_FORMAT (code
);
12279 for (i
= 0; i
< len
; i
++)
12284 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12285 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12288 else if (fmt
[i
] == 'e')
12289 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12293 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12294 pattern of an insn. X must be a REG. */
12297 reg_bitfield_target_p (rtx x
, rtx body
)
12301 if (GET_CODE (body
) == SET
)
12303 rtx dest
= SET_DEST (body
);
12305 unsigned int regno
, tregno
, endregno
, endtregno
;
12307 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12308 target
= XEXP (dest
, 0);
12309 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12310 target
= SUBREG_REG (XEXP (dest
, 0));
12314 if (GET_CODE (target
) == SUBREG
)
12315 target
= SUBREG_REG (target
);
12317 if (GET_CODE (target
) != REG
)
12320 tregno
= REGNO (target
), regno
= REGNO (x
);
12321 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12322 return target
== x
;
12324 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12325 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12327 return endregno
> tregno
&& regno
< endtregno
;
12330 else if (GET_CODE (body
) == PARALLEL
)
12331 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12332 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12338 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12339 as appropriate. I3 and I2 are the insns resulting from the combination
12340 insns including FROM (I2 may be zero).
12342 Each note in the list is either ignored or placed on some insns, depending
12343 on the type of note. */
12346 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12348 rtx note
, next_note
;
12351 for (note
= notes
; note
; note
= next_note
)
12353 rtx place
= 0, place2
= 0;
12355 /* If this NOTE references a pseudo register, ensure it references
12356 the latest copy of that register. */
12357 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12358 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12359 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12361 next_note
= XEXP (note
, 1);
12362 switch (REG_NOTE_KIND (note
))
12366 /* Doesn't matter much where we put this, as long as it's somewhere.
12367 It is preferable to keep these notes on branches, which is most
12368 likely to be i3. */
12372 case REG_VALUE_PROFILE
:
12373 /* Just get rid of this note, as it is unused later anyway. */
12376 case REG_VTABLE_REF
:
12377 /* ??? Should remain with *a particular* memory load. Given the
12378 nature of vtable data, the last insn seems relatively safe. */
12382 case REG_NON_LOCAL_GOTO
:
12383 if (GET_CODE (i3
) == JUMP_INSN
)
12385 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12391 case REG_EH_REGION
:
12392 /* These notes must remain with the call or trapping instruction. */
12393 if (GET_CODE (i3
) == CALL_INSN
)
12395 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12397 else if (flag_non_call_exceptions
)
12399 if (may_trap_p (i3
))
12401 else if (i2
&& may_trap_p (i2
))
12403 /* ??? Otherwise assume we've combined things such that we
12404 can now prove that the instructions can't trap. Drop the
12405 note in this case. */
12411 case REG_ALWAYS_RETURN
:
12414 /* These notes must remain with the call. It should not be
12415 possible for both I2 and I3 to be a call. */
12416 if (GET_CODE (i3
) == CALL_INSN
)
12418 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12425 /* Any clobbers for i3 may still exist, and so we must process
12426 REG_UNUSED notes from that insn.
12428 Any clobbers from i2 or i1 can only exist if they were added by
12429 recog_for_combine. In that case, recog_for_combine created the
12430 necessary REG_UNUSED notes. Trying to keep any original
12431 REG_UNUSED notes from these insns can cause incorrect output
12432 if it is for the same register as the original i3 dest.
12433 In that case, we will notice that the register is set in i3,
12434 and then add a REG_UNUSED note for the destination of i3, which
12435 is wrong. However, it is possible to have REG_UNUSED notes from
12436 i2 or i1 for register which were both used and clobbered, so
12437 we keep notes from i2 or i1 if they will turn into REG_DEAD
12440 /* If this register is set or clobbered in I3, put the note there
12441 unless there is one already. */
12442 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12444 if (from_insn
!= i3
)
12447 if (! (GET_CODE (XEXP (note
, 0)) == REG
12448 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12449 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12452 /* Otherwise, if this register is used by I3, then this register
12453 now dies here, so we must put a REG_DEAD note here unless there
12455 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12456 && ! (GET_CODE (XEXP (note
, 0)) == REG
12457 ? find_regno_note (i3
, REG_DEAD
,
12458 REGNO (XEXP (note
, 0)))
12459 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12461 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12469 /* These notes say something about results of an insn. We can
12470 only support them if they used to be on I3 in which case they
12471 remain on I3. Otherwise they are ignored.
12473 If the note refers to an expression that is not a constant, we
12474 must also ignore the note since we cannot tell whether the
12475 equivalence is still true. It might be possible to do
12476 slightly better than this (we only have a problem if I2DEST
12477 or I1DEST is present in the expression), but it doesn't
12478 seem worth the trouble. */
12480 if (from_insn
== i3
12481 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12486 case REG_NO_CONFLICT
:
12487 /* These notes say something about how a register is used. They must
12488 be present on any use of the register in I2 or I3. */
12489 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12492 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12502 /* This can show up in several ways -- either directly in the
12503 pattern, or hidden off in the constant pool with (or without?)
12504 a REG_EQUAL note. */
12505 /* ??? Ignore the without-reg_equal-note problem for now. */
12506 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12507 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12508 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12509 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12513 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12514 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12515 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12516 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12524 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12525 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12526 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12528 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12530 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12531 LABEL_NUSES (JUMP_LABEL (place
))--;
12534 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12536 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12538 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12539 LABEL_NUSES (JUMP_LABEL (place2
))--;
12545 /* This note says something about the value of a register prior
12546 to the execution of an insn. It is too much trouble to see
12547 if the note is still correct in all situations. It is better
12548 to simply delete it. */
12552 /* If the insn previously containing this note still exists,
12553 put it back where it was. Otherwise move it to the previous
12554 insn. Adjust the corresponding REG_LIBCALL note. */
12555 if (GET_CODE (from_insn
) != NOTE
)
12559 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12560 place
= prev_real_insn (from_insn
);
12562 XEXP (tem
, 0) = place
;
12563 /* If we're deleting the last remaining instruction of a
12564 libcall sequence, don't add the notes. */
12565 else if (XEXP (note
, 0) == from_insn
)
12571 /* This is handled similarly to REG_RETVAL. */
12572 if (GET_CODE (from_insn
) != NOTE
)
12576 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12577 place
= next_real_insn (from_insn
);
12579 XEXP (tem
, 0) = place
;
12580 /* If we're deleting the last remaining instruction of a
12581 libcall sequence, don't add the notes. */
12582 else if (XEXP (note
, 0) == from_insn
)
12588 /* If the register is used as an input in I3, it dies there.
12589 Similarly for I2, if it is nonzero and adjacent to I3.
12591 If the register is not used as an input in either I3 or I2
12592 and it is not one of the registers we were supposed to eliminate,
12593 there are two possibilities. We might have a non-adjacent I2
12594 or we might have somehow eliminated an additional register
12595 from a computation. For example, we might have had A & B where
12596 we discover that B will always be zero. In this case we will
12597 eliminate the reference to A.
12599 In both cases, we must search to see if we can find a previous
12600 use of A and put the death note there. */
12603 && GET_CODE (from_insn
) == CALL_INSN
12604 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12606 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12608 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12609 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12614 basic_block bb
= this_basic_block
;
12616 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12618 if (! INSN_P (tem
))
12620 if (tem
== BB_HEAD (bb
))
12625 /* If the register is being set at TEM, see if that is all
12626 TEM is doing. If so, delete TEM. Otherwise, make this
12627 into a REG_UNUSED note instead. */
12628 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12630 rtx set
= single_set (tem
);
12631 rtx inner_dest
= 0;
12633 rtx cc0_setter
= NULL_RTX
;
12637 for (inner_dest
= SET_DEST (set
);
12638 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12639 || GET_CODE (inner_dest
) == SUBREG
12640 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12641 inner_dest
= XEXP (inner_dest
, 0))
12644 /* Verify that it was the set, and not a clobber that
12645 modified the register.
12647 CC0 targets must be careful to maintain setter/user
12648 pairs. If we cannot delete the setter due to side
12649 effects, mark the user with an UNUSED note instead
12652 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12653 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12655 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12656 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12657 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12661 /* Move the notes and links of TEM elsewhere.
12662 This might delete other dead insns recursively.
12663 First set the pattern to something that won't use
12665 rtx old_notes
= REG_NOTES (tem
);
12667 PATTERN (tem
) = pc_rtx
;
12668 REG_NOTES (tem
) = NULL
;
12670 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12671 distribute_links (LOG_LINKS (tem
));
12673 PUT_CODE (tem
, NOTE
);
12674 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12675 NOTE_SOURCE_FILE (tem
) = 0;
12678 /* Delete the setter too. */
12681 PATTERN (cc0_setter
) = pc_rtx
;
12682 old_notes
= REG_NOTES (cc0_setter
);
12683 REG_NOTES (cc0_setter
) = NULL
;
12685 distribute_notes (old_notes
, cc0_setter
,
12686 cc0_setter
, NULL_RTX
);
12687 distribute_links (LOG_LINKS (cc0_setter
));
12689 PUT_CODE (cc0_setter
, NOTE
);
12690 NOTE_LINE_NUMBER (cc0_setter
)
12691 = NOTE_INSN_DELETED
;
12692 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12696 /* If the register is both set and used here, put the
12697 REG_DEAD note here, but place a REG_UNUSED note
12698 here too unless there already is one. */
12699 else if (reg_referenced_p (XEXP (note
, 0),
12704 if (! find_regno_note (tem
, REG_UNUSED
,
12705 REGNO (XEXP (note
, 0))))
12707 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12712 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12714 /* If there isn't already a REG_UNUSED note, put one
12716 if (! find_regno_note (tem
, REG_UNUSED
,
12717 REGNO (XEXP (note
, 0))))
12722 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12723 || (GET_CODE (tem
) == CALL_INSN
12724 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12728 /* If we are doing a 3->2 combination, and we have a
12729 register which formerly died in i3 and was not used
12730 by i2, which now no longer dies in i3 and is used in
12731 i2 but does not die in i2, and place is between i2
12732 and i3, then we may need to move a link from place to
12734 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12735 && INSN_CUID (place
) > INSN_CUID (i2
)
12737 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12738 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12740 rtx links
= LOG_LINKS (place
);
12741 LOG_LINKS (place
) = 0;
12742 distribute_links (links
);
12747 if (tem
== BB_HEAD (bb
))
12751 /* We haven't found an insn for the death note and it
12752 is still a REG_DEAD note, but we have hit the beginning
12753 of the block. If the existing life info says the reg
12754 was dead, there's nothing left to do. Otherwise, we'll
12755 need to do a global life update after combine. */
12756 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12757 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12758 REGNO (XEXP (note
, 0))))
12759 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12762 /* If the register is set or already dead at PLACE, we needn't do
12763 anything with this note if it is still a REG_DEAD note.
12764 We can here if it is set at all, not if is it totally replace,
12765 which is what `dead_or_set_p' checks, so also check for it being
12768 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12770 unsigned int regno
= REGNO (XEXP (note
, 0));
12772 /* Similarly, if the instruction on which we want to place
12773 the note is a noop, we'll need do a global live update
12774 after we remove them in delete_noop_moves. */
12775 if (noop_move_p (place
))
12776 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12778 if (dead_or_set_p (place
, XEXP (note
, 0))
12779 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12781 /* Unless the register previously died in PLACE, clear
12782 reg_last_death. [I no longer understand why this is
12784 if (reg_last_death
[regno
] != place
)
12785 reg_last_death
[regno
] = 0;
12789 reg_last_death
[regno
] = place
;
12791 /* If this is a death note for a hard reg that is occupying
12792 multiple registers, ensure that we are still using all
12793 parts of the object. If we find a piece of the object
12794 that is unused, we must arrange for an appropriate REG_DEAD
12795 note to be added for it. However, we can't just emit a USE
12796 and tag the note to it, since the register might actually
12797 be dead; so we recourse, and the recursive call then finds
12798 the previous insn that used this register. */
12800 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12801 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12803 unsigned int endregno
12804 = regno
+ HARD_REGNO_NREGS (regno
,
12805 GET_MODE (XEXP (note
, 0)));
12809 for (i
= regno
; i
< endregno
; i
++)
12810 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12811 && ! find_regno_fusage (place
, USE
, i
))
12812 || dead_or_set_regno_p (place
, i
))
12817 /* Put only REG_DEAD notes for pieces that are
12818 not already dead or set. */
12820 for (i
= regno
; i
< endregno
;
12821 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12823 rtx piece
= regno_reg_rtx
[i
];
12824 basic_block bb
= this_basic_block
;
12826 if (! dead_or_set_p (place
, piece
)
12827 && ! reg_bitfield_target_p (piece
,
12831 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12833 distribute_notes (new_note
, place
, place
,
12836 else if (! refers_to_regno_p (i
, i
+ 1,
12837 PATTERN (place
), 0)
12838 && ! find_regno_fusage (place
, USE
, i
))
12839 for (tem
= PREV_INSN (place
); ;
12840 tem
= PREV_INSN (tem
))
12842 if (! INSN_P (tem
))
12844 if (tem
== BB_HEAD (bb
))
12846 SET_BIT (refresh_blocks
,
12847 this_basic_block
->index
);
12852 if (dead_or_set_p (tem
, piece
)
12853 || reg_bitfield_target_p (piece
,
12857 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12872 /* Any other notes should not be present at this point in the
12879 XEXP (note
, 1) = REG_NOTES (place
);
12880 REG_NOTES (place
) = note
;
12882 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12883 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12884 && GET_CODE (XEXP (note
, 0)) == REG
)
12885 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12889 if ((REG_NOTE_KIND (note
) == REG_DEAD
12890 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12891 && GET_CODE (XEXP (note
, 0)) == REG
)
12892 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12894 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12895 REG_NOTE_KIND (note
),
12897 REG_NOTES (place2
));
12902 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12903 I3, I2, and I1 to new locations. This is also called to add a link
12904 pointing at I3 when I3's destination is changed. */
12907 distribute_links (rtx links
)
12909 rtx link
, next_link
;
12911 for (link
= links
; link
; link
= next_link
)
12917 next_link
= XEXP (link
, 1);
12919 /* If the insn that this link points to is a NOTE or isn't a single
12920 set, ignore it. In the latter case, it isn't clear what we
12921 can do other than ignore the link, since we can't tell which
12922 register it was for. Such links wouldn't be used by combine
12925 It is not possible for the destination of the target of the link to
12926 have been changed by combine. The only potential of this is if we
12927 replace I3, I2, and I1 by I3 and I2. But in that case the
12928 destination of I2 also remains unchanged. */
12930 if (GET_CODE (XEXP (link
, 0)) == NOTE
12931 || (set
= single_set (XEXP (link
, 0))) == 0)
12934 reg
= SET_DEST (set
);
12935 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12936 || GET_CODE (reg
) == SIGN_EXTRACT
12937 || GET_CODE (reg
) == STRICT_LOW_PART
)
12938 reg
= XEXP (reg
, 0);
12940 /* A LOG_LINK is defined as being placed on the first insn that uses
12941 a register and points to the insn that sets the register. Start
12942 searching at the next insn after the target of the link and stop
12943 when we reach a set of the register or the end of the basic block.
12945 Note that this correctly handles the link that used to point from
12946 I3 to I2. Also note that not much searching is typically done here
12947 since most links don't point very far away. */
12949 for (insn
= NEXT_INSN (XEXP (link
, 0));
12950 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12951 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12952 insn
= NEXT_INSN (insn
))
12953 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12955 if (reg_referenced_p (reg
, PATTERN (insn
)))
12959 else if (GET_CODE (insn
) == CALL_INSN
12960 && find_reg_fusage (insn
, USE
, reg
))
12965 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12968 /* If we found a place to put the link, place it there unless there
12969 is already a link to the same insn as LINK at that point. */
12975 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12976 if (XEXP (link2
, 0) == XEXP (link
, 0))
12981 XEXP (link
, 1) = LOG_LINKS (place
);
12982 LOG_LINKS (place
) = link
;
12984 /* Set added_links_insn to the earliest insn we added a
12986 if (added_links_insn
== 0
12987 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12988 added_links_insn
= place
;
12994 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12997 insn_cuid (rtx insn
)
12999 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13000 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13001 insn
= NEXT_INSN (insn
);
13003 if (INSN_UID (insn
) > max_uid_cuid
)
13006 return INSN_CUID (insn
);
13010 dump_combine_stats (FILE *file
)
13014 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13015 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13019 dump_combine_total_stats (FILE *file
)
13023 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13024 total_attempts
, total_merges
, total_extras
, total_successes
);