1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx
*reg_last_death
;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx
*reg_last_set
;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set
;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid
;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn
;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn
;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid
;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs
;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn
;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block
;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks
;
202 static int need_refresh
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; unsigned int i
;} old_contents
;
318 union {rtx
*r
; unsigned int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST
PARAMS ((rtx
*, rtx
));
342 static void do_SUBST_INT
PARAMS ((unsigned int *,
344 static void init_reg_last_arrays
PARAMS ((void));
345 static void setup_incoming_promotions
PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
347 static int cant_combine_insn_p
PARAMS ((rtx
));
348 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
349 static int sets_function_arg_p
PARAMS ((rtx
));
350 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
351 static int contains_muldiv
PARAMS ((rtx
));
352 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
353 static void undo_all
PARAMS ((void));
354 static void undo_commit
PARAMS ((void));
355 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
356 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
357 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
358 static rtx simplify_if_then_else
PARAMS ((rtx
));
359 static rtx simplify_set
PARAMS ((rtx
));
360 static rtx simplify_logical
PARAMS ((rtx
, int));
361 static rtx expand_compound_operation
PARAMS ((rtx
));
362 static rtx expand_field_assignment
PARAMS ((rtx
));
363 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
364 rtx
, unsigned HOST_WIDE_INT
, int,
366 static rtx extract_left_shift
PARAMS ((rtx
, int));
367 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
368 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
369 unsigned HOST_WIDE_INT
*));
370 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
371 unsigned HOST_WIDE_INT
, rtx
, int));
372 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
373 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
374 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
375 static rtx make_field_assignment
PARAMS ((rtx
));
376 static rtx apply_distributive_law
PARAMS ((rtx
));
377 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
378 unsigned HOST_WIDE_INT
));
379 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
380 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
381 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
382 enum rtx_code
, HOST_WIDE_INT
,
383 enum machine_mode
, int *));
384 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
386 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
387 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
388 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
390 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
391 static void update_table_tick
PARAMS ((rtx
));
392 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
393 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
394 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
395 static void record_dead_and_set_regs
PARAMS ((rtx
));
396 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
397 static rtx get_last_value
PARAMS ((rtx
));
398 static int use_crosses_set_p
PARAMS ((rtx
, int));
399 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
400 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
401 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
402 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
403 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
404 static void distribute_links
PARAMS ((rtx
));
405 static void mark_used_regs_combine
PARAMS ((rtx
));
406 static int insn_cuid
PARAMS ((rtx
));
407 static void record_promoted_value
PARAMS ((rtx
, rtx
));
408 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
409 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into
, newval
)
424 if (oldval
== newval
)
428 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
430 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
434 buf
->old_contents
.r
= oldval
;
437 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
440 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
442 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
443 for the value of a HOST_WIDE_INT value (including CONST_INT) is
447 do_SUBST_INT (into
, newval
)
448 unsigned int *into
, newval
;
451 unsigned int oldval
= *into
;
453 if (oldval
== newval
)
457 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
459 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
463 buf
->old_contents
.i
= oldval
;
466 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
469 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
471 /* Main entry point for combiner. F is the first insn of the function.
472 NREGS is the first unused pseudo-reg number.
474 Return non-zero if the combiner has turned an indirect jump
475 instruction into a direct jump. */
477 combine_instructions (f
, nregs
)
481 register rtx insn
, next
;
486 register rtx links
, nextlinks
;
488 int new_direct_jump_p
= 0;
490 combine_attempts
= 0;
493 combine_successes
= 0;
495 combine_max_regno
= nregs
;
497 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
498 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
500 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
502 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
503 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
504 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
505 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
506 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
507 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
509 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
510 reg_last_set_nonzero_bits
511 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
512 reg_last_set_sign_bit_copies
513 = (char *) xmalloc (nregs
* sizeof (char));
515 init_reg_last_arrays ();
517 init_recog_no_volatile ();
519 /* Compute maximum uid value so uid_cuid can be allocated. */
521 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
522 if (INSN_UID (insn
) > i
)
525 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
528 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
530 /* Don't use reg_nonzero_bits when computing it. This can cause problems
531 when, for example, we have j <<= 1 in a loop. */
533 nonzero_sign_valid
= 0;
535 /* Compute the mapping from uids to cuids.
536 Cuids are numbers assigned to insns, like uids,
537 except that cuids increase monotonically through the code.
539 Scan all SETs and see if we can deduce anything about what
540 bits are known to be zero for some registers and how many copies
541 of the sign bit are known to exist for those registers.
543 Also set any known values so that we can use it while searching
544 for what bits are known to be set. */
548 /* We need to initialize it here, because record_dead_and_set_regs may call
550 subst_prev_insn
= NULL_RTX
;
552 setup_incoming_promotions ();
554 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
555 sbitmap_zero (refresh_blocks
);
558 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
560 uid_cuid
[INSN_UID (insn
)] = ++i
;
566 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
568 record_dead_and_set_regs (insn
);
571 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
572 if (REG_NOTE_KIND (links
) == REG_INC
)
573 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
578 if (GET_CODE (insn
) == CODE_LABEL
)
582 nonzero_sign_valid
= 1;
584 /* Now scan all the insns in forward order. */
586 this_basic_block
= -1;
590 init_reg_last_arrays ();
591 setup_incoming_promotions ();
593 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
597 /* If INSN starts a new basic block, update our basic block number. */
598 if (this_basic_block
+ 1 < n_basic_blocks
599 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
602 if (GET_CODE (insn
) == CODE_LABEL
)
605 else if (INSN_P (insn
))
607 /* See if we know about function return values before this
608 insn based upon SUBREG flags. */
609 check_promoted_subreg (insn
, PATTERN (insn
));
611 /* Try this insn with each insn it links back to. */
613 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
614 if ((next
= try_combine (insn
, XEXP (links
, 0),
615 NULL_RTX
, &new_direct_jump_p
)) != 0)
618 /* Try each sequence of three linked insns ending with this one. */
620 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
622 rtx link
= XEXP (links
, 0);
624 /* If the linked insn has been replaced by a note, then there
625 is no point in persuing this chain any further. */
626 if (GET_CODE (link
) == NOTE
)
629 for (nextlinks
= LOG_LINKS (link
);
631 nextlinks
= XEXP (nextlinks
, 1))
632 if ((next
= try_combine (insn
, XEXP (links
, 0),
634 &new_direct_jump_p
)) != 0)
639 /* Try to combine a jump insn that uses CC0
640 with a preceding insn that sets CC0, and maybe with its
641 logical predecessor as well.
642 This is how we make decrement-and-branch insns.
643 We need this special code because data flow connections
644 via CC0 do not get entered in LOG_LINKS. */
646 if (GET_CODE (insn
) == JUMP_INSN
647 && (prev
= prev_nonnote_insn (insn
)) != 0
648 && GET_CODE (prev
) == INSN
649 && sets_cc0_p (PATTERN (prev
)))
651 if ((next
= try_combine (insn
, prev
,
652 NULL_RTX
, &new_direct_jump_p
)) != 0)
655 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
656 nextlinks
= XEXP (nextlinks
, 1))
657 if ((next
= try_combine (insn
, prev
,
659 &new_direct_jump_p
)) != 0)
663 /* Do the same for an insn that explicitly references CC0. */
664 if (GET_CODE (insn
) == INSN
665 && (prev
= prev_nonnote_insn (insn
)) != 0
666 && GET_CODE (prev
) == INSN
667 && sets_cc0_p (PATTERN (prev
))
668 && GET_CODE (PATTERN (insn
)) == SET
669 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
671 if ((next
= try_combine (insn
, prev
,
672 NULL_RTX
, &new_direct_jump_p
)) != 0)
675 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
676 nextlinks
= XEXP (nextlinks
, 1))
677 if ((next
= try_combine (insn
, prev
,
679 &new_direct_jump_p
)) != 0)
683 /* Finally, see if any of the insns that this insn links to
684 explicitly references CC0. If so, try this insn, that insn,
685 and its predecessor if it sets CC0. */
686 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
687 if (GET_CODE (XEXP (links
, 0)) == INSN
688 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
689 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
690 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
691 && GET_CODE (prev
) == INSN
692 && sets_cc0_p (PATTERN (prev
))
693 && (next
= try_combine (insn
, XEXP (links
, 0),
694 prev
, &new_direct_jump_p
)) != 0)
698 /* Try combining an insn with two different insns whose results it
700 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
701 for (nextlinks
= XEXP (links
, 1); nextlinks
;
702 nextlinks
= XEXP (nextlinks
, 1))
703 if ((next
= try_combine (insn
, XEXP (links
, 0),
705 &new_direct_jump_p
)) != 0)
708 if (GET_CODE (insn
) != NOTE
)
709 record_dead_and_set_regs (insn
);
716 delete_noop_moves (f
);
720 compute_bb_for_insn (get_max_uid ());
721 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
726 sbitmap_free (refresh_blocks
);
727 free (reg_nonzero_bits
);
728 free (reg_sign_bit_copies
);
729 free (reg_last_death
);
731 free (reg_last_set_value
);
732 free (reg_last_set_table_tick
);
733 free (reg_last_set_label
);
734 free (reg_last_set_invalid
);
735 free (reg_last_set_mode
);
736 free (reg_last_set_nonzero_bits
);
737 free (reg_last_set_sign_bit_copies
);
741 struct undo
*undo
, *next
;
742 for (undo
= undobuf
.frees
; undo
; undo
= next
)
750 total_attempts
+= combine_attempts
;
751 total_merges
+= combine_merges
;
752 total_extras
+= combine_extras
;
753 total_successes
+= combine_successes
;
755 nonzero_sign_valid
= 0;
757 /* Make recognizer allow volatile MEMs again. */
760 return new_direct_jump_p
;
763 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
766 init_reg_last_arrays ()
768 unsigned int nregs
= combine_max_regno
;
770 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
771 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
772 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
773 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
774 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
775 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
776 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
777 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
778 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
781 /* Set up any promoted values for incoming argument registers. */
784 setup_incoming_promotions ()
786 #ifdef PROMOTE_FUNCTION_ARGS
789 enum machine_mode mode
;
791 rtx first
= get_insns ();
793 #ifndef OUTGOING_REGNO
794 #define OUTGOING_REGNO(N) N
796 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
797 /* Check whether this register can hold an incoming pointer
798 argument. FUNCTION_ARG_REGNO_P tests outgoing register
799 numbers, so translate if necessary due to register windows. */
800 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
801 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
804 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
807 gen_rtx_CLOBBER (mode
, const0_rtx
)));
812 /* Called via note_stores. If X is a pseudo that is narrower than
813 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
815 If we are setting only a portion of X and we can't figure out what
816 portion, assume all bits will be used since we don't know what will
819 Similarly, set how many bits of X are known to be copies of the sign bit
820 at all locations in the function. This is the smallest number implied
824 set_nonzero_bits_and_sign_copies (x
, set
, data
)
827 void *data ATTRIBUTE_UNUSED
;
831 if (GET_CODE (x
) == REG
832 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
833 /* If this register is undefined at the start of the file, we can't
834 say what its contents were. */
835 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
836 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
838 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
840 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
841 reg_sign_bit_copies
[REGNO (x
)] = 1;
845 /* If this is a complex assignment, see if we can convert it into a
846 simple assignment. */
847 set
= expand_field_assignment (set
);
849 /* If this is a simple assignment, or we have a paradoxical SUBREG,
850 set what we know about X. */
852 if (SET_DEST (set
) == x
853 || (GET_CODE (SET_DEST (set
)) == SUBREG
854 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
855 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
856 && SUBREG_REG (SET_DEST (set
)) == x
))
858 rtx src
= SET_SRC (set
);
860 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
861 /* If X is narrower than a word and SRC is a non-negative
862 constant that would appear negative in the mode of X,
863 sign-extend it for use in reg_nonzero_bits because some
864 machines (maybe most) will actually do the sign-extension
865 and this is the conservative approach.
867 ??? For 2.5, try to tighten up the MD files in this regard
868 instead of this kludge. */
870 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
871 && GET_CODE (src
) == CONST_INT
873 && 0 != (INTVAL (src
)
875 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
876 src
= GEN_INT (INTVAL (src
)
877 | ((HOST_WIDE_INT
) (-1)
878 << GET_MODE_BITSIZE (GET_MODE (x
))));
881 reg_nonzero_bits
[REGNO (x
)]
882 |= nonzero_bits (src
, nonzero_bits_mode
);
883 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
884 if (reg_sign_bit_copies
[REGNO (x
)] == 0
885 || reg_sign_bit_copies
[REGNO (x
)] > num
)
886 reg_sign_bit_copies
[REGNO (x
)] = num
;
890 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
891 reg_sign_bit_copies
[REGNO (x
)] = 1;
896 /* See if INSN can be combined into I3. PRED and SUCC are optionally
897 insns that were previously combined into I3 or that will be combined
898 into the merger of INSN and I3.
900 Return 0 if the combination is not allowed for any reason.
902 If the combination is allowed, *PDEST will be set to the single
903 destination of INSN and *PSRC to the single source, and this function
907 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
910 rtx pred ATTRIBUTE_UNUSED
;
915 rtx set
= 0, src
, dest
;
920 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
921 && next_active_insn (succ
) == i3
)
922 : next_active_insn (insn
) == i3
);
924 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
925 or a PARALLEL consisting of such a SET and CLOBBERs.
927 If INSN has CLOBBER parallel parts, ignore them for our processing.
928 By definition, these happen during the execution of the insn. When it
929 is merged with another insn, all bets are off. If they are, in fact,
930 needed and aren't also supplied in I3, they may be added by
931 recog_for_combine. Otherwise, it won't match.
933 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
936 Get the source and destination of INSN. If more than one, can't
939 if (GET_CODE (PATTERN (insn
)) == SET
)
940 set
= PATTERN (insn
);
941 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
942 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
944 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
946 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
948 switch (GET_CODE (elt
))
950 /* This is important to combine floating point insns
953 /* Combining an isolated USE doesn't make sense.
954 We depend here on combinable_i3_pat to reject them. */
955 /* The code below this loop only verifies that the inputs of
956 the SET in INSN do not change. We call reg_set_between_p
957 to verify that the REG in the USE does not change betweeen
959 If the USE in INSN was for a pseudo register, the matching
960 insn pattern will likely match any register; combining this
961 with any other USE would only be safe if we knew that the
962 used registers have identical values, or if there was
963 something to tell them apart, e.g. different modes. For
964 now, we forgo such compilcated tests and simply disallow
965 combining of USES of pseudo registers with any other USE. */
966 if (GET_CODE (XEXP (elt
, 0)) == REG
967 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
969 rtx i3pat
= PATTERN (i3
);
970 int i
= XVECLEN (i3pat
, 0) - 1;
971 unsigned int regno
= REGNO (XEXP (elt
, 0));
975 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
977 if (GET_CODE (i3elt
) == USE
978 && GET_CODE (XEXP (i3elt
, 0)) == REG
979 && (REGNO (XEXP (i3elt
, 0)) == regno
980 ? reg_set_between_p (XEXP (elt
, 0),
981 PREV_INSN (insn
), i3
)
982 : regno
>= FIRST_PSEUDO_REGISTER
))
989 /* We can ignore CLOBBERs. */
994 /* Ignore SETs whose result isn't used but not those that
995 have side-effects. */
996 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
997 && ! side_effects_p (elt
))
1000 /* If we have already found a SET, this is a second one and
1001 so we cannot combine with this insn. */
1009 /* Anything else means we can't combine. */
1015 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1016 so don't do anything with it. */
1017 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1026 set
= expand_field_assignment (set
);
1027 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1029 /* Don't eliminate a store in the stack pointer. */
1030 if (dest
== stack_pointer_rtx
1031 /* If we couldn't eliminate a field assignment, we can't combine. */
1032 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1033 /* Don't combine with an insn that sets a register to itself if it has
1034 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1035 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1036 /* Can't merge an ASM_OPERANDS. */
1037 || GET_CODE (src
) == ASM_OPERANDS
1038 /* Can't merge a function call. */
1039 || GET_CODE (src
) == CALL
1040 /* Don't eliminate a function call argument. */
1041 || (GET_CODE (i3
) == CALL_INSN
1042 && (find_reg_fusage (i3
, USE
, dest
)
1043 || (GET_CODE (dest
) == REG
1044 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1045 && global_regs
[REGNO (dest
)])))
1046 /* Don't substitute into an incremented register. */
1047 || FIND_REG_INC_NOTE (i3
, dest
)
1048 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1050 /* Don't combine the end of a libcall into anything. */
1051 /* ??? This gives worse code, and appears to be unnecessary, since no
1052 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1053 use REG_RETVAL notes for noconflict blocks, but other code here
1054 makes sure that those insns don't disappear. */
1055 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1057 /* Make sure that DEST is not used after SUCC but before I3. */
1058 || (succ
&& ! all_adjacent
1059 && reg_used_between_p (dest
, succ
, i3
))
1060 /* Make sure that the value that is to be substituted for the register
1061 does not use any registers whose values alter in between. However,
1062 If the insns are adjacent, a use can't cross a set even though we
1063 think it might (this can happen for a sequence of insns each setting
1064 the same destination; reg_last_set of that register might point to
1065 a NOTE). If INSN has a REG_EQUIV note, the register is always
1066 equivalent to the memory so the substitution is valid even if there
1067 are intervening stores. Also, don't move a volatile asm or
1068 UNSPEC_VOLATILE across any other insns. */
1070 && (((GET_CODE (src
) != MEM
1071 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1072 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1073 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1074 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1075 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1076 better register allocation by not doing the combine. */
1077 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1078 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1079 /* Don't combine across a CALL_INSN, because that would possibly
1080 change whether the life span of some REGs crosses calls or not,
1081 and it is a pain to update that information.
1082 Exception: if source is a constant, moving it later can't hurt.
1083 Accept that special case, because it helps -fforce-addr a lot. */
1084 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1087 /* DEST must either be a REG or CC0. */
1088 if (GET_CODE (dest
) == REG
)
1090 /* If register alignment is being enforced for multi-word items in all
1091 cases except for parameters, it is possible to have a register copy
1092 insn referencing a hard register that is not allowed to contain the
1093 mode being copied and which would not be valid as an operand of most
1094 insns. Eliminate this problem by not combining with such an insn.
1096 Also, on some machines we don't want to extend the life of a hard
1099 if (GET_CODE (src
) == REG
1100 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1101 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1102 /* Don't extend the life of a hard register unless it is
1103 user variable (if we have few registers) or it can't
1104 fit into the desired register (meaning something special
1106 Also avoid substituting a return register into I3, because
1107 reload can't handle a conflict with constraints of other
1109 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1110 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1113 else if (GET_CODE (dest
) != CC0
)
1116 /* Don't substitute for a register intended as a clobberable operand.
1117 Similarly, don't substitute an expression containing a register that
1118 will be clobbered in I3. */
1119 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1120 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1121 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1122 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1124 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1127 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1128 or not), reject, unless nothing volatile comes between it and I3 */
1130 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1132 /* Make sure succ doesn't contain a volatile reference. */
1133 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1136 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1137 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1141 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1142 to be an explicit register variable, and was chosen for a reason. */
1144 if (GET_CODE (src
) == ASM_OPERANDS
1145 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1148 /* If there are any volatile insns between INSN and I3, reject, because
1149 they might affect machine state. */
1151 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1152 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1155 /* If INSN or I2 contains an autoincrement or autodecrement,
1156 make sure that register is not used between there and I3,
1157 and not already used in I3 either.
1158 Also insist that I3 not be a jump; if it were one
1159 and the incremented register were spilled, we would lose. */
1162 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1163 if (REG_NOTE_KIND (link
) == REG_INC
1164 && (GET_CODE (i3
) == JUMP_INSN
1165 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1166 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1171 /* Don't combine an insn that follows a CC0-setting insn.
1172 An insn that uses CC0 must not be separated from the one that sets it.
1173 We do, however, allow I2 to follow a CC0-setting insn if that insn
1174 is passed as I1; in that case it will be deleted also.
1175 We also allow combining in this case if all the insns are adjacent
1176 because that would leave the two CC0 insns adjacent as well.
1177 It would be more logical to test whether CC0 occurs inside I1 or I2,
1178 but that would be much slower, and this ought to be equivalent. */
1180 p
= prev_nonnote_insn (insn
);
1181 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1186 /* If we get here, we have passed all the tests and the combination is
1195 /* Check if PAT is an insn - or a part of it - used to set up an
1196 argument for a function in a hard register. */
1199 sets_function_arg_p (pat
)
1205 switch (GET_CODE (pat
))
1208 return sets_function_arg_p (PATTERN (pat
));
1211 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1212 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1218 inner_dest
= SET_DEST (pat
);
1219 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1220 || GET_CODE (inner_dest
) == SUBREG
1221 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1222 inner_dest
= XEXP (inner_dest
, 0);
1224 return (GET_CODE (inner_dest
) == REG
1225 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1226 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1235 /* LOC is the location within I3 that contains its pattern or the component
1236 of a PARALLEL of the pattern. We validate that it is valid for combining.
1238 One problem is if I3 modifies its output, as opposed to replacing it
1239 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1240 so would produce an insn that is not equivalent to the original insns.
1244 (set (reg:DI 101) (reg:DI 100))
1245 (set (subreg:SI (reg:DI 101) 0) <foo>)
1247 This is NOT equivalent to:
1249 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1250 (set (reg:DI 101) (reg:DI 100))])
1252 Not only does this modify 100 (in which case it might still be valid
1253 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1255 We can also run into a problem if I2 sets a register that I1
1256 uses and I1 gets directly substituted into I3 (not via I2). In that
1257 case, we would be getting the wrong value of I2DEST into I3, so we
1258 must reject the combination. This case occurs when I2 and I1 both
1259 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1260 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1261 of a SET must prevent combination from occurring.
1263 Before doing the above check, we first try to expand a field assignment
1264 into a set of logical operations.
1266 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1267 we place a register that is both set and used within I3. If more than one
1268 such register is detected, we fail.
1270 Return 1 if the combination is valid, zero otherwise. */
1273 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1279 rtx
*pi3dest_killed
;
1283 if (GET_CODE (x
) == SET
)
1285 rtx set
= expand_field_assignment (x
);
1286 rtx dest
= SET_DEST (set
);
1287 rtx src
= SET_SRC (set
);
1288 rtx inner_dest
= dest
;
1291 rtx inner_src
= src
;
1296 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1297 || GET_CODE (inner_dest
) == SUBREG
1298 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1299 inner_dest
= XEXP (inner_dest
, 0);
1301 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1304 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1305 || GET_CODE (inner_src
) == SUBREG
1306 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1307 inner_src
= XEXP (inner_src
, 0);
1309 /* If it is better that two different modes keep two different pseudos,
1310 avoid combining them. This avoids producing the following pattern
1312 (set (subreg:SI (reg/v:QI 21) 0)
1313 (lshiftrt:SI (reg/v:SI 20)
1315 If that were made, reload could not handle the pair of
1316 reg 20/21, since it would try to get any GENERAL_REGS
1317 but some of them don't handle QImode. */
1319 if (rtx_equal_p (inner_src
, i2dest
)
1320 && GET_CODE (inner_dest
) == REG
1321 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1325 /* Check for the case where I3 modifies its output, as
1327 if ((inner_dest
!= dest
1328 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1329 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1331 /* This is the same test done in can_combine_p except we can't test
1332 all_adjacent; we don't have to, since this instruction will stay
1333 in place, thus we are not considering increasing the lifetime of
1336 Also, if this insn sets a function argument, combining it with
1337 something that might need a spill could clobber a previous
1338 function argument; the all_adjacent test in can_combine_p also
1339 checks this; here, we do a more specific test for this case. */
1341 || (GET_CODE (inner_dest
) == REG
1342 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1343 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1344 GET_MODE (inner_dest
))))
1345 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1348 /* If DEST is used in I3, it is being killed in this insn,
1349 so record that for later.
1350 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1351 STACK_POINTER_REGNUM, since these are always considered to be
1352 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1353 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1354 && reg_referenced_p (dest
, PATTERN (i3
))
1355 && REGNO (dest
) != FRAME_POINTER_REGNUM
1356 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1357 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1359 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1360 && (REGNO (dest
) != ARG_POINTER_REGNUM
1361 || ! fixed_regs
[REGNO (dest
)])
1363 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1365 if (*pi3dest_killed
)
1368 *pi3dest_killed
= dest
;
1372 else if (GET_CODE (x
) == PARALLEL
)
1376 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1377 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1378 i1_not_in_src
, pi3dest_killed
))
1385 /* Return 1 if X is an arithmetic expression that contains a multiplication
1386 and division. We don't count multiplications by powers of two here. */
1392 switch (GET_CODE (x
))
1394 case MOD
: case DIV
: case UMOD
: case UDIV
:
1398 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1399 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1401 switch (GET_RTX_CLASS (GET_CODE (x
)))
1403 case 'c': case '<': case '2':
1404 return contains_muldiv (XEXP (x
, 0))
1405 || contains_muldiv (XEXP (x
, 1));
1408 return contains_muldiv (XEXP (x
, 0));
1416 /* Determine whether INSN can be used in a combination. Return nonzero if
1417 not. This is used in try_combine to detect early some cases where we
1418 can't perform combinations. */
1421 cant_combine_insn_p (insn
)
1427 /* If this isn't really an insn, we can't do anything.
1428 This can occur when flow deletes an insn that it has merged into an
1429 auto-increment address. */
1430 if (! INSN_P (insn
))
1433 /* Never combine loads and stores involving hard regs. The register
1434 allocator can usually handle such reg-reg moves by tying. If we allow
1435 the combiner to make substitutions of hard regs, we risk aborting in
1436 reload on machines that have SMALL_REGISTER_CLASSES.
1437 As an exception, we allow combinations involving fixed regs; these are
1438 not available to the register allocator so there's no risk involved. */
1440 set
= single_set (insn
);
1443 src
= SET_SRC (set
);
1444 dest
= SET_DEST (set
);
1445 if (GET_CODE (src
) == SUBREG
)
1446 src
= SUBREG_REG (src
);
1447 if (GET_CODE (dest
) == SUBREG
)
1448 dest
= SUBREG_REG (dest
);
1449 if (REG_P (src
) && REG_P (dest
)
1450 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1451 && ! fixed_regs
[REGNO (src
)])
1452 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1453 && ! fixed_regs
[REGNO (dest
)])))
1459 /* Try to combine the insns I1 and I2 into I3.
1460 Here I1 and I2 appear earlier than I3.
1461 I1 can be zero; then we combine just I2 into I3.
1463 If we are combining three insns and the resulting insn is not recognized,
1464 try splitting it into two insns. If that happens, I2 and I3 are retained
1465 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1468 Return 0 if the combination does not work. Then nothing is changed.
1469 If we did the combination, return the insn at which combine should
1472 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1473 new direct jump instruction. */
1476 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1477 register rtx i3
, i2
, i1
;
1478 register int *new_direct_jump_p
;
1480 /* New patterns for I3 and I2, respectively. */
1481 rtx newpat
, newi2pat
= 0;
1482 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1483 int added_sets_1
, added_sets_2
;
1484 /* Total number of SETs to put into I3. */
1486 /* Nonzero is I2's body now appears in I3. */
1488 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1489 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1490 /* Contains I3 if the destination of I3 is used in its source, which means
1491 that the old life of I3 is being killed. If that usage is placed into
1492 I2 and not in I3, a REG_DEAD note must be made. */
1493 rtx i3dest_killed
= 0;
1494 /* SET_DEST and SET_SRC of I2 and I1. */
1495 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1496 /* PATTERN (I2), or a copy of it in certain cases. */
1498 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1499 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1500 int i1_feeds_i3
= 0;
1501 /* Notes that must be added to REG_NOTES in I3 and I2. */
1502 rtx new_i3_notes
, new_i2_notes
;
1503 /* Notes that we substituted I3 into I2 instead of the normal case. */
1504 int i3_subst_into_i2
= 0;
1505 /* Notes that I1, I2 or I3 is a MULT operation. */
1513 /* Exit early if one of the insns involved can't be used for
1515 if (cant_combine_insn_p (i3
)
1516 || cant_combine_insn_p (i2
)
1517 || (i1
&& cant_combine_insn_p (i1
))
1518 /* We also can't do anything if I3 has a
1519 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1522 /* ??? This gives worse code, and appears to be unnecessary, since no
1523 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1524 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1530 undobuf
.other_insn
= 0;
1532 /* Reset the hard register usage information. */
1533 CLEAR_HARD_REG_SET (newpat_used_regs
);
1535 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1536 code below, set I1 to be the earlier of the two insns. */
1537 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1538 temp
= i1
, i1
= i2
, i2
= temp
;
1540 added_links_insn
= 0;
1542 /* First check for one important special-case that the code below will
1543 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1544 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1545 we may be able to replace that destination with the destination of I3.
1546 This occurs in the common code where we compute both a quotient and
1547 remainder into a structure, in which case we want to do the computation
1548 directly into the structure to avoid register-register copies.
1550 Note that this case handles both multiple sets in I2 and also
1551 cases where I2 has a number of CLOBBER or PARALLELs.
1553 We make very conservative checks below and only try to handle the
1554 most common cases of this. For example, we only handle the case
1555 where I2 and I3 are adjacent to avoid making difficult register
1558 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1559 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1560 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1561 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1562 && GET_CODE (PATTERN (i2
)) == PARALLEL
1563 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1564 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1565 below would need to check what is inside (and reg_overlap_mentioned_p
1566 doesn't support those codes anyway). Don't allow those destinations;
1567 the resulting insn isn't likely to be recognized anyway. */
1568 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1569 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1570 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1571 SET_DEST (PATTERN (i3
)))
1572 && next_real_insn (i2
) == i3
)
1574 rtx p2
= PATTERN (i2
);
1576 /* Make sure that the destination of I3,
1577 which we are going to substitute into one output of I2,
1578 is not used within another output of I2. We must avoid making this:
1579 (parallel [(set (mem (reg 69)) ...)
1580 (set (reg 69) ...)])
1581 which is not well-defined as to order of actions.
1582 (Besides, reload can't handle output reloads for this.)
1584 The problem can also happen if the dest of I3 is a memory ref,
1585 if another dest in I2 is an indirect memory ref. */
1586 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1587 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1588 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1589 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1590 SET_DEST (XVECEXP (p2
, 0, i
))))
1593 if (i
== XVECLEN (p2
, 0))
1594 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1595 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1596 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1597 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1602 subst_low_cuid
= INSN_CUID (i2
);
1604 added_sets_2
= added_sets_1
= 0;
1605 i2dest
= SET_SRC (PATTERN (i3
));
1607 /* Replace the dest in I2 with our dest and make the resulting
1608 insn the new pattern for I3. Then skip to where we
1609 validate the pattern. Everything was set up above. */
1610 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1611 SET_DEST (PATTERN (i3
)));
1614 i3_subst_into_i2
= 1;
1615 goto validate_replacement
;
1619 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1620 one of those words to another constant, merge them by making a new
1623 && (temp
= single_set (i2
)) != 0
1624 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1625 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1626 && GET_CODE (SET_DEST (temp
)) == REG
1627 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1628 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1629 && GET_CODE (PATTERN (i3
)) == SET
1630 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1631 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1632 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1633 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1634 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1636 HOST_WIDE_INT lo
, hi
;
1638 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1639 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1642 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1643 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1646 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1648 /* We don't handle the case of the target word being wider
1649 than a host wide int. */
1650 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1653 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1654 lo
|= INTVAL (SET_SRC (PATTERN (i3
)));
1656 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1657 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1658 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1660 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1661 >> (HOST_BITS_PER_WIDE_INT
- 1));
1663 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1664 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1665 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1666 (INTVAL (SET_SRC (PATTERN (i3
)))));
1668 hi
= lo
< 0 ? -1 : 0;
1671 /* We don't handle the case of the higher word not fitting
1672 entirely in either hi or lo. */
1677 subst_low_cuid
= INSN_CUID (i2
);
1678 added_sets_2
= added_sets_1
= 0;
1679 i2dest
= SET_DEST (temp
);
1681 SUBST (SET_SRC (temp
),
1682 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1684 newpat
= PATTERN (i2
);
1685 goto validate_replacement
;
1689 /* If we have no I1 and I2 looks like:
1690 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1692 make up a dummy I1 that is
1695 (set (reg:CC X) (compare:CC Y (const_int 0)))
1697 (We can ignore any trailing CLOBBERs.)
1699 This undoes a previous combination and allows us to match a branch-and-
1702 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1703 && XVECLEN (PATTERN (i2
), 0) >= 2
1704 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1705 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1707 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1708 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1709 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1710 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1711 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1712 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1714 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1715 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1720 /* We make I1 with the same INSN_UID as I2. This gives it
1721 the same INSN_CUID for value tracking. Our fake I1 will
1722 never appear in the insn stream so giving it the same INSN_UID
1723 as I2 will not cause a problem. */
1725 subst_prev_insn
= i1
1726 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1727 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1730 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1731 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1732 SET_DEST (PATTERN (i1
)));
1737 /* Verify that I2 and I1 are valid for combining. */
1738 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1739 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1745 /* Record whether I2DEST is used in I2SRC and similarly for the other
1746 cases. Knowing this will help in register status updating below. */
1747 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1748 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1749 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1751 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1753 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1755 /* Ensure that I3's pattern can be the destination of combines. */
1756 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1757 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1764 /* See if any of the insns is a MULT operation. Unless one is, we will
1765 reject a combination that is, since it must be slower. Be conservative
1767 if (GET_CODE (i2src
) == MULT
1768 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1769 || (GET_CODE (PATTERN (i3
)) == SET
1770 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1773 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1774 We used to do this EXCEPT in one case: I3 has a post-inc in an
1775 output operand. However, that exception can give rise to insns like
1777 which is a famous insn on the PDP-11 where the value of r3 used as the
1778 source was model-dependent. Avoid this sort of thing. */
1781 if (!(GET_CODE (PATTERN (i3
)) == SET
1782 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1783 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1784 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1785 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1786 /* It's not the exception. */
1789 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1790 if (REG_NOTE_KIND (link
) == REG_INC
1791 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1793 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1800 /* See if the SETs in I1 or I2 need to be kept around in the merged
1801 instruction: whenever the value set there is still needed past I3.
1802 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1804 For the SET in I1, we have two cases: If I1 and I2 independently
1805 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1806 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1807 in I1 needs to be kept around unless I1DEST dies or is set in either
1808 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1809 I1DEST. If so, we know I1 feeds into I2. */
1811 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1814 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1815 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1817 /* If the set in I2 needs to be kept around, we must make a copy of
1818 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1819 PATTERN (I2), we are only substituting for the original I1DEST, not into
1820 an already-substituted copy. This also prevents making self-referential
1821 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1824 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1825 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1829 i2pat
= copy_rtx (i2pat
);
1833 /* Substitute in the latest insn for the regs set by the earlier ones. */
1835 maxreg
= max_reg_num ();
1839 /* It is possible that the source of I2 or I1 may be performing an
1840 unneeded operation, such as a ZERO_EXTEND of something that is known
1841 to have the high part zero. Handle that case by letting subst look at
1842 the innermost one of them.
1844 Another way to do this would be to have a function that tries to
1845 simplify a single insn instead of merging two or more insns. We don't
1846 do this because of the potential of infinite loops and because
1847 of the potential extra memory required. However, doing it the way
1848 we are is a bit of a kludge and doesn't catch all cases.
1850 But only do this if -fexpensive-optimizations since it slows things down
1851 and doesn't usually win. */
1853 if (flag_expensive_optimizations
)
1855 /* Pass pc_rtx so no substitutions are done, just simplifications.
1856 The cases that we are interested in here do not involve the few
1857 cases were is_replaced is checked. */
1860 subst_low_cuid
= INSN_CUID (i1
);
1861 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1865 subst_low_cuid
= INSN_CUID (i2
);
1866 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1871 /* Many machines that don't use CC0 have insns that can both perform an
1872 arithmetic operation and set the condition code. These operations will
1873 be represented as a PARALLEL with the first element of the vector
1874 being a COMPARE of an arithmetic operation with the constant zero.
1875 The second element of the vector will set some pseudo to the result
1876 of the same arithmetic operation. If we simplify the COMPARE, we won't
1877 match such a pattern and so will generate an extra insn. Here we test
1878 for this case, where both the comparison and the operation result are
1879 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1880 I2SRC. Later we will make the PARALLEL that contains I2. */
1882 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1883 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1884 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1885 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1887 #ifdef EXTRA_CC_MODES
1889 enum machine_mode compare_mode
;
1892 newpat
= PATTERN (i3
);
1893 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1897 #ifdef EXTRA_CC_MODES
1898 /* See if a COMPARE with the operand we substituted in should be done
1899 with the mode that is currently being used. If not, do the same
1900 processing we do in `subst' for a SET; namely, if the destination
1901 is used only once, try to replace it with a register of the proper
1902 mode and also replace the COMPARE. */
1903 if (undobuf
.other_insn
== 0
1904 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1905 &undobuf
.other_insn
))
1906 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1908 != GET_MODE (SET_DEST (newpat
))))
1910 unsigned int regno
= REGNO (SET_DEST (newpat
));
1911 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1913 if (regno
< FIRST_PSEUDO_REGISTER
1914 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1915 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1917 if (regno
>= FIRST_PSEUDO_REGISTER
)
1918 SUBST (regno_reg_rtx
[regno
], new_dest
);
1920 SUBST (SET_DEST (newpat
), new_dest
);
1921 SUBST (XEXP (*cc_use
, 0), new_dest
);
1922 SUBST (SET_SRC (newpat
),
1923 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1926 undobuf
.other_insn
= 0;
1933 n_occurrences
= 0; /* `subst' counts here */
1935 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1936 need to make a unique copy of I2SRC each time we substitute it
1937 to avoid self-referential rtl. */
1939 subst_low_cuid
= INSN_CUID (i2
);
1940 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1941 ! i1_feeds_i3
&& i1dest_in_i1src
);
1943 /* Record whether i2's body now appears within i3's body. */
1944 i2_is_used
= n_occurrences
;
1947 /* If we already got a failure, don't try to do more. Otherwise,
1948 try to substitute in I1 if we have it. */
1950 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1952 /* Before we can do this substitution, we must redo the test done
1953 above (see detailed comments there) that ensures that I1DEST
1954 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1956 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1964 subst_low_cuid
= INSN_CUID (i1
);
1965 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1968 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1969 to count all the ways that I2SRC and I1SRC can be used. */
1970 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1971 && i2_is_used
+ added_sets_2
> 1)
1972 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1973 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1975 /* Fail if we tried to make a new register (we used to abort, but there's
1976 really no reason to). */
1977 || max_reg_num () != maxreg
1978 /* Fail if we couldn't do something and have a CLOBBER. */
1979 || GET_CODE (newpat
) == CLOBBER
1980 /* Fail if this new pattern is a MULT and we didn't have one before
1981 at the outer level. */
1982 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1989 /* If the actions of the earlier insns must be kept
1990 in addition to substituting them into the latest one,
1991 we must make a new PARALLEL for the latest insn
1992 to hold additional the SETs. */
1994 if (added_sets_1
|| added_sets_2
)
1998 if (GET_CODE (newpat
) == PARALLEL
)
2000 rtvec old
= XVEC (newpat
, 0);
2001 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2002 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2003 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2004 sizeof (old
->elem
[0]) * old
->num_elem
);
2009 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2010 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2011 XVECEXP (newpat
, 0, 0) = old
;
2015 XVECEXP (newpat
, 0, --total_sets
)
2016 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2017 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2021 /* If there is no I1, use I2's body as is. We used to also not do
2022 the subst call below if I2 was substituted into I3,
2023 but that could lose a simplification. */
2025 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2027 /* See comment where i2pat is assigned. */
2028 XVECEXP (newpat
, 0, --total_sets
)
2029 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2033 /* We come here when we are replacing a destination in I2 with the
2034 destination of I3. */
2035 validate_replacement
:
2037 /* Note which hard regs this insn has as inputs. */
2038 mark_used_regs_combine (newpat
);
2040 /* Is the result of combination a valid instruction? */
2041 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2043 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2044 the second SET's destination is a register that is unused. In that case,
2045 we just need the first SET. This can occur when simplifying a divmod
2046 insn. We *must* test for this case here because the code below that
2047 splits two independent SETs doesn't handle this case correctly when it
2048 updates the register status. Also check the case where the first
2049 SET's destination is unused. That would not cause incorrect code, but
2050 does cause an unneeded insn to remain. */
2052 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2053 && XVECLEN (newpat
, 0) == 2
2054 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2055 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2056 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2057 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2058 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2059 && asm_noperands (newpat
) < 0)
2061 newpat
= XVECEXP (newpat
, 0, 0);
2062 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2065 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2066 && XVECLEN (newpat
, 0) == 2
2067 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2068 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2069 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2070 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2071 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2072 && asm_noperands (newpat
) < 0)
2074 newpat
= XVECEXP (newpat
, 0, 1);
2075 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2078 /* If we were combining three insns and the result is a simple SET
2079 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2080 insns. There are two ways to do this. It can be split using a
2081 machine-specific method (like when you have an addition of a large
2082 constant) or by combine in the function find_split_point. */
2084 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2085 && asm_noperands (newpat
) < 0)
2087 rtx m_split
, *split
;
2088 rtx ni2dest
= i2dest
;
2090 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2091 use I2DEST as a scratch register will help. In the latter case,
2092 convert I2DEST to the mode of the source of NEWPAT if we can. */
2094 m_split
= split_insns (newpat
, i3
);
2096 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2097 inputs of NEWPAT. */
2099 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2100 possible to try that as a scratch reg. This would require adding
2101 more code to make it work though. */
2103 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2105 /* If I2DEST is a hard register or the only use of a pseudo,
2106 we can change its mode. */
2107 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2108 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2109 && GET_CODE (i2dest
) == REG
2110 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2111 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2112 && ! REG_USERVAR_P (i2dest
))))
2113 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2116 m_split
= split_insns (gen_rtx_PARALLEL
2118 gen_rtvec (2, newpat
,
2119 gen_rtx_CLOBBER (VOIDmode
,
2122 /* If the split with the mode-changed register didn't work, try
2123 the original register. */
2124 if (! m_split
&& ni2dest
!= i2dest
)
2127 m_split
= split_insns (gen_rtx_PARALLEL
2129 gen_rtvec (2, newpat
,
2130 gen_rtx_CLOBBER (VOIDmode
,
2136 if (m_split
&& GET_CODE (m_split
) != SEQUENCE
)
2138 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2139 if (insn_code_number
>= 0)
2142 else if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2143 && XVECLEN (m_split
, 0) == 2
2144 && (next_real_insn (i2
) == i3
2145 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2149 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2150 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2152 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2153 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2155 /* In case we changed the mode of I2DEST, replace it in the
2156 pseudo-register table here. We can't do it above in case this
2157 code doesn't get executed and we do a split the other way. */
2159 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2160 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2162 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2164 /* If I2 or I3 has multiple SETs, we won't know how to track
2165 register status, so don't use these insns. If I2's destination
2166 is used between I2 and I3, we also can't use these insns. */
2168 if (i2_code_number
>= 0 && i2set
&& i3set
2169 && (next_real_insn (i2
) == i3
2170 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2171 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2173 if (insn_code_number
>= 0)
2176 /* It is possible that both insns now set the destination of I3.
2177 If so, we must show an extra use of it. */
2179 if (insn_code_number
>= 0)
2181 rtx new_i3_dest
= SET_DEST (i3set
);
2182 rtx new_i2_dest
= SET_DEST (i2set
);
2184 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2185 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2186 || GET_CODE (new_i3_dest
) == SUBREG
)
2187 new_i3_dest
= XEXP (new_i3_dest
, 0);
2189 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2190 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2191 || GET_CODE (new_i2_dest
) == SUBREG
)
2192 new_i2_dest
= XEXP (new_i2_dest
, 0);
2194 if (GET_CODE (new_i3_dest
) == REG
2195 && GET_CODE (new_i2_dest
) == REG
2196 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2197 REG_N_SETS (REGNO (new_i2_dest
))++;
2201 /* If we can split it and use I2DEST, go ahead and see if that
2202 helps things be recognized. Verify that none of the registers
2203 are set between I2 and I3. */
2204 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2206 && GET_CODE (i2dest
) == REG
2208 /* We need I2DEST in the proper mode. If it is a hard register
2209 or the only use of a pseudo, we can change its mode. */
2210 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2211 || GET_MODE (*split
) == VOIDmode
2212 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2213 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2214 && ! REG_USERVAR_P (i2dest
)))
2215 && (next_real_insn (i2
) == i3
2216 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2217 /* We can't overwrite I2DEST if its value is still used by
2219 && ! reg_referenced_p (i2dest
, newpat
))
2221 rtx newdest
= i2dest
;
2222 enum rtx_code split_code
= GET_CODE (*split
);
2223 enum machine_mode split_mode
= GET_MODE (*split
);
2225 /* Get NEWDEST as a register in the proper mode. We have already
2226 validated that we can do this. */
2227 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2229 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2231 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2232 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2235 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2236 an ASHIFT. This can occur if it was inside a PLUS and hence
2237 appeared to be a memory address. This is a kludge. */
2238 if (split_code
== MULT
2239 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2240 && INTVAL (XEXP (*split
, 1)) > 0
2241 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2243 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2244 XEXP (*split
, 0), GEN_INT (i
)));
2245 /* Update split_code because we may not have a multiply
2247 split_code
= GET_CODE (*split
);
2250 #ifdef INSN_SCHEDULING
2251 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2252 be written as a ZERO_EXTEND. */
2253 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2254 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2255 SUBREG_REG (*split
)));
2258 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2259 SUBST (*split
, newdest
);
2260 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2262 /* If the split point was a MULT and we didn't have one before,
2263 don't use one now. */
2264 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2265 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2269 /* Check for a case where we loaded from memory in a narrow mode and
2270 then sign extended it, but we need both registers. In that case,
2271 we have a PARALLEL with both loads from the same memory location.
2272 We can split this into a load from memory followed by a register-register
2273 copy. This saves at least one insn, more if register allocation can
2276 We cannot do this if the destination of the second assignment is
2277 a register that we have already assumed is zero-extended. Similarly
2278 for a SUBREG of such a register. */
2280 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2281 && GET_CODE (newpat
) == PARALLEL
2282 && XVECLEN (newpat
, 0) == 2
2283 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2284 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2285 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2286 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2287 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2288 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2290 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2291 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2292 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2293 (GET_CODE (temp
) == REG
2294 && reg_nonzero_bits
[REGNO (temp
)] != 0
2295 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2296 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2297 && (reg_nonzero_bits
[REGNO (temp
)]
2298 != GET_MODE_MASK (word_mode
))))
2299 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2300 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2301 (GET_CODE (temp
) == REG
2302 && reg_nonzero_bits
[REGNO (temp
)] != 0
2303 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2304 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2305 && (reg_nonzero_bits
[REGNO (temp
)]
2306 != GET_MODE_MASK (word_mode
)))))
2307 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2308 SET_SRC (XVECEXP (newpat
, 0, 1)))
2309 && ! find_reg_note (i3
, REG_UNUSED
,
2310 SET_DEST (XVECEXP (newpat
, 0, 0))))
2314 newi2pat
= XVECEXP (newpat
, 0, 0);
2315 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2316 newpat
= XVECEXP (newpat
, 0, 1);
2317 SUBST (SET_SRC (newpat
),
2318 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2319 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2321 if (i2_code_number
>= 0)
2322 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2324 if (insn_code_number
>= 0)
2329 /* If we will be able to accept this, we have made a change to the
2330 destination of I3. This can invalidate a LOG_LINKS pointing
2331 to I3. No other part of combine.c makes such a transformation.
2333 The new I3 will have a destination that was previously the
2334 destination of I1 or I2 and which was used in i2 or I3. Call
2335 distribute_links to make a LOG_LINK from the next use of
2336 that destination. */
2338 PATTERN (i3
) = newpat
;
2339 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2341 /* I3 now uses what used to be its destination and which is
2342 now I2's destination. That means we need a LOG_LINK from
2343 I3 to I2. But we used to have one, so we still will.
2345 However, some later insn might be using I2's dest and have
2346 a LOG_LINK pointing at I3. We must remove this link.
2347 The simplest way to remove the link is to point it at I1,
2348 which we know will be a NOTE. */
2350 for (insn
= NEXT_INSN (i3
);
2351 insn
&& (this_basic_block
== n_basic_blocks
- 1
2352 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2353 insn
= NEXT_INSN (insn
))
2355 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2357 for (link
= LOG_LINKS (insn
); link
;
2358 link
= XEXP (link
, 1))
2359 if (XEXP (link
, 0) == i3
)
2360 XEXP (link
, 0) = i1
;
2368 /* Similarly, check for a case where we have a PARALLEL of two independent
2369 SETs but we started with three insns. In this case, we can do the sets
2370 as two separate insns. This case occurs when some SET allows two
2371 other insns to combine, but the destination of that SET is still live. */
2373 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2374 && GET_CODE (newpat
) == PARALLEL
2375 && XVECLEN (newpat
, 0) == 2
2376 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2379 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2380 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2381 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2382 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2384 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2385 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2386 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2387 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2388 XVECEXP (newpat
, 0, 0))
2389 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2390 XVECEXP (newpat
, 0, 1))
2391 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2392 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2394 /* Normally, it doesn't matter which of the two is done first,
2395 but it does if one references cc0. In that case, it has to
2398 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2400 newi2pat
= XVECEXP (newpat
, 0, 0);
2401 newpat
= XVECEXP (newpat
, 0, 1);
2406 newi2pat
= XVECEXP (newpat
, 0, 1);
2407 newpat
= XVECEXP (newpat
, 0, 0);
2410 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2412 if (i2_code_number
>= 0)
2413 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2416 /* If it still isn't recognized, fail and change things back the way they
2418 if ((insn_code_number
< 0
2419 /* Is the result a reasonable ASM_OPERANDS? */
2420 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2426 /* If we had to change another insn, make sure it is valid also. */
2427 if (undobuf
.other_insn
)
2429 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2430 rtx new_other_notes
;
2433 CLEAR_HARD_REG_SET (newpat_used_regs
);
2435 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2438 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2444 PATTERN (undobuf
.other_insn
) = other_pat
;
2446 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2447 are still valid. Then add any non-duplicate notes added by
2448 recog_for_combine. */
2449 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2451 next
= XEXP (note
, 1);
2453 if (REG_NOTE_KIND (note
) == REG_UNUSED
2454 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2456 if (GET_CODE (XEXP (note
, 0)) == REG
)
2457 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2459 remove_note (undobuf
.other_insn
, note
);
2463 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2464 if (GET_CODE (XEXP (note
, 0)) == REG
)
2465 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2467 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2468 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2471 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2472 they are adjacent to each other or not. */
2474 rtx p
= prev_nonnote_insn (i3
);
2475 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2476 && sets_cc0_p (newi2pat
))
2484 /* We now know that we can do this combination. Merge the insns and
2485 update the status of registers and LOG_LINKS. */
2488 rtx i3notes
, i2notes
, i1notes
= 0;
2489 rtx i3links
, i2links
, i1links
= 0;
2492 /* Compute which registers we expect to eliminate. newi2pat may be setting
2493 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2494 same as i3dest, in which case newi2pat may be setting i1dest. */
2495 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2496 || i2dest_in_i2src
|| i2dest_in_i1src
2498 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2499 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2502 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2504 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2505 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2507 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2509 /* Ensure that we do not have something that should not be shared but
2510 occurs multiple times in the new insns. Check this by first
2511 resetting all the `used' flags and then copying anything is shared. */
2513 reset_used_flags (i3notes
);
2514 reset_used_flags (i2notes
);
2515 reset_used_flags (i1notes
);
2516 reset_used_flags (newpat
);
2517 reset_used_flags (newi2pat
);
2518 if (undobuf
.other_insn
)
2519 reset_used_flags (PATTERN (undobuf
.other_insn
));
2521 i3notes
= copy_rtx_if_shared (i3notes
);
2522 i2notes
= copy_rtx_if_shared (i2notes
);
2523 i1notes
= copy_rtx_if_shared (i1notes
);
2524 newpat
= copy_rtx_if_shared (newpat
);
2525 newi2pat
= copy_rtx_if_shared (newi2pat
);
2526 if (undobuf
.other_insn
)
2527 reset_used_flags (PATTERN (undobuf
.other_insn
));
2529 INSN_CODE (i3
) = insn_code_number
;
2530 PATTERN (i3
) = newpat
;
2531 if (undobuf
.other_insn
)
2532 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2534 /* We had one special case above where I2 had more than one set and
2535 we replaced a destination of one of those sets with the destination
2536 of I3. In that case, we have to update LOG_LINKS of insns later
2537 in this basic block. Note that this (expensive) case is rare.
2539 Also, in this case, we must pretend that all REG_NOTEs for I2
2540 actually came from I3, so that REG_UNUSED notes from I2 will be
2541 properly handled. */
2543 if (i3_subst_into_i2
)
2545 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2546 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2547 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2548 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2549 && ! find_reg_note (i2
, REG_UNUSED
,
2550 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2551 for (temp
= NEXT_INSN (i2
);
2552 temp
&& (this_basic_block
== n_basic_blocks
- 1
2553 || BLOCK_HEAD (this_basic_block
) != temp
);
2554 temp
= NEXT_INSN (temp
))
2555 if (temp
!= i3
&& INSN_P (temp
))
2556 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2557 if (XEXP (link
, 0) == i2
)
2558 XEXP (link
, 0) = i3
;
2563 while (XEXP (link
, 1))
2564 link
= XEXP (link
, 1);
2565 XEXP (link
, 1) = i2notes
;
2579 INSN_CODE (i2
) = i2_code_number
;
2580 PATTERN (i2
) = newi2pat
;
2584 PUT_CODE (i2
, NOTE
);
2585 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2586 NOTE_SOURCE_FILE (i2
) = 0;
2593 PUT_CODE (i1
, NOTE
);
2594 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2595 NOTE_SOURCE_FILE (i1
) = 0;
2598 /* Get death notes for everything that is now used in either I3 or
2599 I2 and used to die in a previous insn. If we built two new
2600 patterns, move from I1 to I2 then I2 to I3 so that we get the
2601 proper movement on registers that I2 modifies. */
2605 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2606 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2609 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2612 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2614 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2617 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2620 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2623 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2626 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2627 know these are REG_UNUSED and want them to go to the desired insn,
2628 so we always pass it as i3. We have not counted the notes in
2629 reg_n_deaths yet, so we need to do so now. */
2631 if (newi2pat
&& new_i2_notes
)
2633 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2634 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2635 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2637 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2642 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2643 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2644 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2646 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2649 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2650 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2651 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2652 in that case, it might delete I2. Similarly for I2 and I1.
2653 Show an additional death due to the REG_DEAD note we make here. If
2654 we discard it in distribute_notes, we will decrement it again. */
2658 if (GET_CODE (i3dest_killed
) == REG
)
2659 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2661 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2662 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2664 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2666 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2668 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2672 if (i2dest_in_i2src
)
2674 if (GET_CODE (i2dest
) == REG
)
2675 REG_N_DEATHS (REGNO (i2dest
))++;
2677 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2679 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2682 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2683 NULL_RTX
, NULL_RTX
);
2686 if (i1dest_in_i1src
)
2688 if (GET_CODE (i1dest
) == REG
)
2689 REG_N_DEATHS (REGNO (i1dest
))++;
2691 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2692 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2693 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2695 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2696 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2697 NULL_RTX
, NULL_RTX
);
2700 distribute_links (i3links
);
2701 distribute_links (i2links
);
2702 distribute_links (i1links
);
2704 if (GET_CODE (i2dest
) == REG
)
2707 rtx i2_insn
= 0, i2_val
= 0, set
;
2709 /* The insn that used to set this register doesn't exist, and
2710 this life of the register may not exist either. See if one of
2711 I3's links points to an insn that sets I2DEST. If it does,
2712 that is now the last known value for I2DEST. If we don't update
2713 this and I2 set the register to a value that depended on its old
2714 contents, we will get confused. If this insn is used, thing
2715 will be set correctly in combine_instructions. */
2717 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2718 if ((set
= single_set (XEXP (link
, 0))) != 0
2719 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2720 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2722 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2724 /* If the reg formerly set in I2 died only once and that was in I3,
2725 zero its use count so it won't make `reload' do any work. */
2727 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2728 && ! i2dest_in_i2src
)
2730 regno
= REGNO (i2dest
);
2731 REG_N_SETS (regno
)--;
2735 if (i1
&& GET_CODE (i1dest
) == REG
)
2738 rtx i1_insn
= 0, i1_val
= 0, set
;
2740 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2741 if ((set
= single_set (XEXP (link
, 0))) != 0
2742 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2743 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2745 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2747 regno
= REGNO (i1dest
);
2748 if (! added_sets_1
&& ! i1dest_in_i1src
)
2749 REG_N_SETS (regno
)--;
2752 /* Update reg_nonzero_bits et al for any changes that may have been made
2753 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2754 important. Because newi2pat can affect nonzero_bits of newpat */
2756 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2757 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2759 /* Set new_direct_jump_p if a new return or simple jump instruction
2762 If I3 is now an unconditional jump, ensure that it has a
2763 BARRIER following it since it may have initially been a
2764 conditional jump. It may also be the last nonnote insn. */
2766 if (GET_CODE (newpat
) == RETURN
|| any_uncondjump_p (i3
)
2767 || (GET_CODE (newpat
) == SET
2768 && SET_SRC (newpat
) == pc_rtx
2769 && SET_DEST (newpat
) == pc_rtx
))
2771 *new_direct_jump_p
= 1;
2773 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2774 || GET_CODE (temp
) != BARRIER
)
2775 emit_barrier_after (i3
);
2779 combine_successes
++;
2782 /* Clear this here, so that subsequent get_last_value calls are not
2784 subst_prev_insn
= NULL_RTX
;
2786 if (added_links_insn
2787 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2788 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2789 return added_links_insn
;
2791 return newi2pat
? i2
: i3
;
2794 /* Undo all the modifications recorded in undobuf. */
2799 struct undo
*undo
, *next
;
2801 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2805 *undo
->where
.i
= undo
->old_contents
.i
;
2807 *undo
->where
.r
= undo
->old_contents
.r
;
2809 undo
->next
= undobuf
.frees
;
2810 undobuf
.frees
= undo
;
2815 /* Clear this here, so that subsequent get_last_value calls are not
2817 subst_prev_insn
= NULL_RTX
;
2820 /* We've committed to accepting the changes we made. Move all
2821 of the undos to the free list. */
2826 struct undo
*undo
, *next
;
2828 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2831 undo
->next
= undobuf
.frees
;
2832 undobuf
.frees
= undo
;
2838 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2839 where we have an arithmetic expression and return that point. LOC will
2842 try_combine will call this function to see if an insn can be split into
2846 find_split_point (loc
, insn
)
2851 enum rtx_code code
= GET_CODE (x
);
2853 unsigned HOST_WIDE_INT len
= 0;
2854 HOST_WIDE_INT pos
= 0;
2856 rtx inner
= NULL_RTX
;
2858 /* First special-case some codes. */
2862 #ifdef INSN_SCHEDULING
2863 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2865 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2868 return find_split_point (&SUBREG_REG (x
), insn
);
2872 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2873 using LO_SUM and HIGH. */
2874 if (GET_CODE (XEXP (x
, 0)) == CONST
2875 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2878 gen_rtx_LO_SUM (Pmode
,
2879 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2881 return &XEXP (XEXP (x
, 0), 0);
2885 /* If we have a PLUS whose second operand is a constant and the
2886 address is not valid, perhaps will can split it up using
2887 the machine-specific way to split large constants. We use
2888 the first pseudo-reg (one of the virtual regs) as a placeholder;
2889 it will not remain in the result. */
2890 if (GET_CODE (XEXP (x
, 0)) == PLUS
2891 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2892 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2894 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2895 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2898 /* This should have produced two insns, each of which sets our
2899 placeholder. If the source of the second is a valid address,
2900 we can make put both sources together and make a split point
2903 if (seq
&& XVECLEN (seq
, 0) == 2
2904 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2905 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2906 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2907 && ! reg_mentioned_p (reg
,
2908 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2909 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2910 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2911 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2912 && memory_address_p (GET_MODE (x
),
2913 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2915 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2916 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2918 /* Replace the placeholder in SRC2 with SRC1. If we can
2919 find where in SRC2 it was placed, that can become our
2920 split point and we can replace this address with SRC2.
2921 Just try two obvious places. */
2923 src2
= replace_rtx (src2
, reg
, src1
);
2925 if (XEXP (src2
, 0) == src1
)
2926 split
= &XEXP (src2
, 0);
2927 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2928 && XEXP (XEXP (src2
, 0), 0) == src1
)
2929 split
= &XEXP (XEXP (src2
, 0), 0);
2933 SUBST (XEXP (x
, 0), src2
);
2938 /* If that didn't work, perhaps the first operand is complex and
2939 needs to be computed separately, so make a split point there.
2940 This will occur on machines that just support REG + CONST
2941 and have a constant moved through some previous computation. */
2943 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2944 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2945 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2947 return &XEXP (XEXP (x
, 0), 0);
2953 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2954 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2955 we need to put the operand into a register. So split at that
2958 if (SET_DEST (x
) == cc0_rtx
2959 && GET_CODE (SET_SRC (x
)) != COMPARE
2960 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2961 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2962 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2963 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2964 return &SET_SRC (x
);
2967 /* See if we can split SET_SRC as it stands. */
2968 split
= find_split_point (&SET_SRC (x
), insn
);
2969 if (split
&& split
!= &SET_SRC (x
))
2972 /* See if we can split SET_DEST as it stands. */
2973 split
= find_split_point (&SET_DEST (x
), insn
);
2974 if (split
&& split
!= &SET_DEST (x
))
2977 /* See if this is a bitfield assignment with everything constant. If
2978 so, this is an IOR of an AND, so split it into that. */
2979 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2980 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2981 <= HOST_BITS_PER_WIDE_INT
)
2982 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2983 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2984 && GET_CODE (SET_SRC (x
)) == CONST_INT
2985 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2986 + INTVAL (XEXP (SET_DEST (x
), 2)))
2987 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2988 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2990 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2991 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2992 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2993 rtx dest
= XEXP (SET_DEST (x
), 0);
2994 enum machine_mode mode
= GET_MODE (dest
);
2995 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2997 if (BITS_BIG_ENDIAN
)
2998 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3002 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3005 gen_binary (IOR
, mode
,
3006 gen_binary (AND
, mode
, dest
,
3007 GEN_INT (~(mask
<< pos
)
3008 & GET_MODE_MASK (mode
))),
3009 GEN_INT (src
<< pos
)));
3011 SUBST (SET_DEST (x
), dest
);
3013 split
= find_split_point (&SET_SRC (x
), insn
);
3014 if (split
&& split
!= &SET_SRC (x
))
3018 /* Otherwise, see if this is an operation that we can split into two.
3019 If so, try to split that. */
3020 code
= GET_CODE (SET_SRC (x
));
3025 /* If we are AND'ing with a large constant that is only a single
3026 bit and the result is only being used in a context where we
3027 need to know if it is zero or non-zero, replace it with a bit
3028 extraction. This will avoid the large constant, which might
3029 have taken more than one insn to make. If the constant were
3030 not a valid argument to the AND but took only one insn to make,
3031 this is no worse, but if it took more than one insn, it will
3034 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3035 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3036 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3037 && GET_CODE (SET_DEST (x
)) == REG
3038 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*)0)) != 0
3039 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3040 && XEXP (*split
, 0) == SET_DEST (x
)
3041 && XEXP (*split
, 1) == const0_rtx
)
3043 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3044 XEXP (SET_SRC (x
), 0),
3045 pos
, NULL_RTX
, 1, 1, 0, 0);
3046 if (extraction
!= 0)
3048 SUBST (SET_SRC (x
), extraction
);
3049 return find_split_point (loc
, insn
);
3055 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3056 is known to be on, this can be converted into a NEG of a shift. */
3057 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3058 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3059 && 1 <= (pos
= exact_log2
3060 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3061 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3063 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3067 gen_rtx_LSHIFTRT (mode
,
3068 XEXP (SET_SRC (x
), 0),
3071 split
= find_split_point (&SET_SRC (x
), insn
);
3072 if (split
&& split
!= &SET_SRC (x
))
3078 inner
= XEXP (SET_SRC (x
), 0);
3080 /* We can't optimize if either mode is a partial integer
3081 mode as we don't know how many bits are significant
3083 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3084 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3088 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3094 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3095 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3097 inner
= XEXP (SET_SRC (x
), 0);
3098 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3099 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3101 if (BITS_BIG_ENDIAN
)
3102 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3103 unsignedp
= (code
== ZERO_EXTRACT
);
3111 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3113 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3115 /* For unsigned, we have a choice of a shift followed by an
3116 AND or two shifts. Use two shifts for field sizes where the
3117 constant might be too large. We assume here that we can
3118 always at least get 8-bit constants in an AND insn, which is
3119 true for every current RISC. */
3121 if (unsignedp
&& len
<= 8)
3126 (mode
, gen_lowpart_for_combine (mode
, inner
),
3128 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3130 split
= find_split_point (&SET_SRC (x
), insn
);
3131 if (split
&& split
!= &SET_SRC (x
))
3138 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3139 gen_rtx_ASHIFT (mode
,
3140 gen_lowpart_for_combine (mode
, inner
),
3141 GEN_INT (GET_MODE_BITSIZE (mode
)
3143 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3145 split
= find_split_point (&SET_SRC (x
), insn
);
3146 if (split
&& split
!= &SET_SRC (x
))
3151 /* See if this is a simple operation with a constant as the second
3152 operand. It might be that this constant is out of range and hence
3153 could be used as a split point. */
3154 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3155 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3156 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3157 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3158 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3159 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3160 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3162 return &XEXP (SET_SRC (x
), 1);
3164 /* Finally, see if this is a simple operation with its first operand
3165 not in a register. The operation might require this operand in a
3166 register, so return it as a split point. We can always do this
3167 because if the first operand were another operation, we would have
3168 already found it as a split point. */
3169 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3170 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3171 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3172 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3173 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3174 return &XEXP (SET_SRC (x
), 0);
3180 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3181 it is better to write this as (not (ior A B)) so we can split it.
3182 Similarly for IOR. */
3183 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3186 gen_rtx_NOT (GET_MODE (x
),
3187 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3189 XEXP (XEXP (x
, 0), 0),
3190 XEXP (XEXP (x
, 1), 0))));
3191 return find_split_point (loc
, insn
);
3194 /* Many RISC machines have a large set of logical insns. If the
3195 second operand is a NOT, put it first so we will try to split the
3196 other operand first. */
3197 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3199 rtx tem
= XEXP (x
, 0);
3200 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3201 SUBST (XEXP (x
, 1), tem
);
3209 /* Otherwise, select our actions depending on our rtx class. */
3210 switch (GET_RTX_CLASS (code
))
3212 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3214 split
= find_split_point (&XEXP (x
, 2), insn
);
3217 /* ... fall through ... */
3221 split
= find_split_point (&XEXP (x
, 1), insn
);
3224 /* ... fall through ... */
3226 /* Some machines have (and (shift ...) ...) insns. If X is not
3227 an AND, but XEXP (X, 0) is, use it as our split point. */
3228 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3229 return &XEXP (x
, 0);
3231 split
= find_split_point (&XEXP (x
, 0), insn
);
3237 /* Otherwise, we don't have a split point. */
3241 /* Throughout X, replace FROM with TO, and return the result.
3242 The result is TO if X is FROM;
3243 otherwise the result is X, but its contents may have been modified.
3244 If they were modified, a record was made in undobuf so that
3245 undo_all will (among other things) return X to its original state.
3247 If the number of changes necessary is too much to record to undo,
3248 the excess changes are not made, so the result is invalid.
3249 The changes already made can still be undone.
3250 undobuf.num_undo is incremented for such changes, so by testing that
3251 the caller can tell whether the result is valid.
3253 `n_occurrences' is incremented each time FROM is replaced.
3255 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3257 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3258 by copying if `n_occurrences' is non-zero. */
3261 subst (x
, from
, to
, in_dest
, unique_copy
)
3262 register rtx x
, from
, to
;
3266 register enum rtx_code code
= GET_CODE (x
);
3267 enum machine_mode op0_mode
= VOIDmode
;
3268 register const char *fmt
;
3269 register int len
, i
;
3272 /* Two expressions are equal if they are identical copies of a shared
3273 RTX or if they are both registers with the same register number
3276 #define COMBINE_RTX_EQUAL_P(X,Y) \
3278 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3279 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3281 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3284 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3287 /* If X and FROM are the same register but different modes, they will
3288 not have been seen as equal above. However, flow.c will make a
3289 LOG_LINKS entry for that case. If we do nothing, we will try to
3290 rerecognize our original insn and, when it succeeds, we will
3291 delete the feeding insn, which is incorrect.
3293 So force this insn not to match in this (rare) case. */
3294 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3295 && REGNO (x
) == REGNO (from
))
3296 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3298 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3299 of which may contain things that can be combined. */
3300 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3303 /* It is possible to have a subexpression appear twice in the insn.
3304 Suppose that FROM is a register that appears within TO.
3305 Then, after that subexpression has been scanned once by `subst',
3306 the second time it is scanned, TO may be found. If we were
3307 to scan TO here, we would find FROM within it and create a
3308 self-referent rtl structure which is completely wrong. */
3309 if (COMBINE_RTX_EQUAL_P (x
, to
))
3312 /* Parallel asm_operands need special attention because all of the
3313 inputs are shared across the arms. Furthermore, unsharing the
3314 rtl results in recognition failures. Failure to handle this case
3315 specially can result in circular rtl.
3317 Solve this by doing a normal pass across the first entry of the
3318 parallel, and only processing the SET_DESTs of the subsequent
3321 if (code
== PARALLEL
3322 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3323 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3325 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3327 /* If this substitution failed, this whole thing fails. */
3328 if (GET_CODE (new) == CLOBBER
3329 && XEXP (new, 0) == const0_rtx
)
3332 SUBST (XVECEXP (x
, 0, 0), new);
3334 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3336 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3338 if (GET_CODE (dest
) != REG
3339 && GET_CODE (dest
) != CC0
3340 && GET_CODE (dest
) != PC
)
3342 new = subst (dest
, from
, to
, 0, unique_copy
);
3344 /* If this substitution failed, this whole thing fails. */
3345 if (GET_CODE (new) == CLOBBER
3346 && XEXP (new, 0) == const0_rtx
)
3349 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3355 len
= GET_RTX_LENGTH (code
);
3356 fmt
= GET_RTX_FORMAT (code
);
3358 /* We don't need to process a SET_DEST that is a register, CC0,
3359 or PC, so set up to skip this common case. All other cases
3360 where we want to suppress replacing something inside a
3361 SET_SRC are handled via the IN_DEST operand. */
3363 && (GET_CODE (SET_DEST (x
)) == REG
3364 || GET_CODE (SET_DEST (x
)) == CC0
3365 || GET_CODE (SET_DEST (x
)) == PC
))
3368 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3371 op0_mode
= GET_MODE (XEXP (x
, 0));
3373 for (i
= 0; i
< len
; i
++)
3378 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3380 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3382 new = (unique_copy
&& n_occurrences
3383 ? copy_rtx (to
) : to
);
3388 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3391 /* If this substitution failed, this whole thing
3393 if (GET_CODE (new) == CLOBBER
3394 && XEXP (new, 0) == const0_rtx
)
3398 SUBST (XVECEXP (x
, i
, j
), new);
3401 else if (fmt
[i
] == 'e')
3403 /* If this is a register being set, ignore it. */
3406 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3407 || code
== ZERO_EXTRACT
)
3409 && GET_CODE (new) == REG
)
3412 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3414 /* In general, don't install a subreg involving two
3415 modes not tieable. It can worsen register
3416 allocation, and can even make invalid reload
3417 insns, since the reg inside may need to be copied
3418 from in the outside mode, and that may be invalid
3419 if it is an fp reg copied in integer mode.
3421 We allow two exceptions to this: It is valid if
3422 it is inside another SUBREG and the mode of that
3423 SUBREG and the mode of the inside of TO is
3424 tieable and it is valid if X is a SET that copies
3427 if (GET_CODE (to
) == SUBREG
3428 && ! MODES_TIEABLE_P (GET_MODE (to
),
3429 GET_MODE (SUBREG_REG (to
)))
3430 && ! (code
== SUBREG
3431 && MODES_TIEABLE_P (GET_MODE (x
),
3432 GET_MODE (SUBREG_REG (to
))))
3434 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3437 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3439 #ifdef CLASS_CANNOT_CHANGE_MODE
3441 && GET_CODE (to
) == REG
3442 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3443 && (TEST_HARD_REG_BIT
3444 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3446 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3448 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3451 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3455 /* If we are in a SET_DEST, suppress most cases unless we
3456 have gone inside a MEM, in which case we want to
3457 simplify the address. We assume here that things that
3458 are actually part of the destination have their inner
3459 parts in the first expression. This is true for SUBREG,
3460 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3461 things aside from REG and MEM that should appear in a
3463 new = subst (XEXP (x
, i
), from
, to
,
3465 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3466 || code
== ZERO_EXTRACT
))
3468 && i
== 0), unique_copy
);
3470 /* If we found that we will have to reject this combination,
3471 indicate that by returning the CLOBBER ourselves, rather than
3472 an expression containing it. This will speed things up as
3473 well as prevent accidents where two CLOBBERs are considered
3474 to be equal, thus producing an incorrect simplification. */
3476 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3479 SUBST (XEXP (x
, i
), new);
3484 /* Try to simplify X. If the simplification changed the code, it is likely
3485 that further simplification will help, so loop, but limit the number
3486 of repetitions that will be performed. */
3488 for (i
= 0; i
< 4; i
++)
3490 /* If X is sufficiently simple, don't bother trying to do anything
3492 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3493 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3495 if (GET_CODE (x
) == code
)
3498 code
= GET_CODE (x
);
3500 /* We no longer know the original mode of operand 0 since we
3501 have changed the form of X) */
3502 op0_mode
= VOIDmode
;
3508 /* Simplify X, a piece of RTL. We just operate on the expression at the
3509 outer level; call `subst' to simplify recursively. Return the new
3512 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3513 will be the iteration even if an expression with a code different from
3514 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3517 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3519 enum machine_mode op0_mode
;
3523 enum rtx_code code
= GET_CODE (x
);
3524 enum machine_mode mode
= GET_MODE (x
);
3529 /* If this is a commutative operation, put a constant last and a complex
3530 expression first. We don't need to do this for comparisons here. */
3531 if (GET_RTX_CLASS (code
) == 'c'
3532 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3535 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3536 SUBST (XEXP (x
, 1), temp
);
3539 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3540 sign extension of a PLUS with a constant, reverse the order of the sign
3541 extension and the addition. Note that this not the same as the original
3542 code, but overflow is undefined for signed values. Also note that the
3543 PLUS will have been partially moved "inside" the sign-extension, so that
3544 the first operand of X will really look like:
3545 (ashiftrt (plus (ashift A C4) C5) C4).
3547 (plus (ashiftrt (ashift A C4) C2) C4)
3548 and replace the first operand of X with that expression. Later parts
3549 of this function may simplify the expression further.
3551 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3552 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3553 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3555 We do this to simplify address expressions. */
3557 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3558 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3559 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3560 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3561 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3562 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3563 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3564 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3565 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3566 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3567 XEXP (XEXP (x
, 0), 1))) != 0)
3570 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3571 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3572 INTVAL (XEXP (XEXP (x
, 0), 1)));
3574 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3575 INTVAL (XEXP (XEXP (x
, 0), 1)));
3577 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3580 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3581 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3582 things. Check for cases where both arms are testing the same
3585 Don't do anything if all operands are very simple. */
3587 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3588 || GET_RTX_CLASS (code
) == '<')
3589 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3590 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3591 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3593 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3594 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3595 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3597 || (GET_RTX_CLASS (code
) == '1'
3598 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3599 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3600 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3603 rtx cond
, true_rtx
, false_rtx
;
3605 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3607 /* If everything is a comparison, what we have is highly unlikely
3608 to be simpler, so don't use it. */
3609 && ! (GET_RTX_CLASS (code
) == '<'
3610 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3611 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3613 rtx cop1
= const0_rtx
;
3614 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3616 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3619 /* Simplify the alternative arms; this may collapse the true and
3620 false arms to store-flag values. */
3621 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3622 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3624 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3625 is unlikely to be simpler. */
3626 if (general_operand (true_rtx
, VOIDmode
)
3627 && general_operand (false_rtx
, VOIDmode
))
3629 /* Restarting if we generate a store-flag expression will cause
3630 us to loop. Just drop through in this case. */
3632 /* If the result values are STORE_FLAG_VALUE and zero, we can
3633 just make the comparison operation. */
3634 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3635 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3636 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
)
3637 x
= gen_binary (reverse_condition (cond_code
),
3640 /* Likewise, we can make the negate of a comparison operation
3641 if the result values are - STORE_FLAG_VALUE and zero. */
3642 else if (GET_CODE (true_rtx
) == CONST_INT
3643 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3644 && false_rtx
== const0_rtx
)
3645 x
= simplify_gen_unary (NEG
, mode
,
3646 gen_binary (cond_code
, mode
, cond
,
3649 else if (GET_CODE (false_rtx
) == CONST_INT
3650 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3651 && true_rtx
== const0_rtx
)
3652 x
= simplify_gen_unary (NEG
, mode
,
3653 gen_binary (reverse_condition
3658 return gen_rtx_IF_THEN_ELSE (mode
,
3659 gen_binary (cond_code
, VOIDmode
,
3661 true_rtx
, false_rtx
);
3663 code
= GET_CODE (x
);
3664 op0_mode
= VOIDmode
;
3669 /* Try to fold this expression in case we have constants that weren't
3672 switch (GET_RTX_CLASS (code
))
3675 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3679 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3680 if (cmp_mode
== VOIDmode
)
3682 cmp_mode
= GET_MODE (XEXP (x
, 1));
3683 if (cmp_mode
== VOIDmode
)
3684 cmp_mode
= op0_mode
;
3686 temp
= simplify_relational_operation (code
, cmp_mode
,
3687 XEXP (x
, 0), XEXP (x
, 1));
3689 #ifdef FLOAT_STORE_FLAG_VALUE
3690 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3692 if (temp
== const0_rtx
)
3693 temp
= CONST0_RTX (mode
);
3695 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3701 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3705 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3706 XEXP (x
, 1), XEXP (x
, 2));
3713 code
= GET_CODE (temp
);
3714 op0_mode
= VOIDmode
;
3715 mode
= GET_MODE (temp
);
3718 /* First see if we can apply the inverse distributive law. */
3719 if (code
== PLUS
|| code
== MINUS
3720 || code
== AND
|| code
== IOR
|| code
== XOR
)
3722 x
= apply_distributive_law (x
);
3723 code
= GET_CODE (x
);
3724 op0_mode
= VOIDmode
;
3727 /* If CODE is an associative operation not otherwise handled, see if we
3728 can associate some operands. This can win if they are constants or
3729 if they are logically related (i.e. (a & b) & a). */
3730 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3731 || code
== AND
|| code
== IOR
|| code
== XOR
3732 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3733 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3734 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3736 if (GET_CODE (XEXP (x
, 0)) == code
)
3738 rtx other
= XEXP (XEXP (x
, 0), 0);
3739 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3740 rtx inner_op1
= XEXP (x
, 1);
3743 /* Make sure we pass the constant operand if any as the second
3744 one if this is a commutative operation. */
3745 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3747 rtx tem
= inner_op0
;
3748 inner_op0
= inner_op1
;
3751 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3752 : code
== DIV
? MULT
3754 mode
, inner_op0
, inner_op1
);
3756 /* For commutative operations, try the other pair if that one
3758 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3760 other
= XEXP (XEXP (x
, 0), 1);
3761 inner
= simplify_binary_operation (code
, mode
,
3762 XEXP (XEXP (x
, 0), 0),
3767 return gen_binary (code
, mode
, other
, inner
);
3771 /* A little bit of algebraic simplification here. */
3775 /* Ensure that our address has any ASHIFTs converted to MULT in case
3776 address-recognizing predicates are called later. */
3777 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3778 SUBST (XEXP (x
, 0), temp
);
3782 if (op0_mode
== VOIDmode
)
3783 op0_mode
= GET_MODE (SUBREG_REG (x
));
3785 /* simplify_subreg can't use gen_lowpart_for_combine. */
3786 if (CONSTANT_P (SUBREG_REG (x
))
3787 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
))
3788 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3792 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3798 /* Note that we cannot do any narrowing for non-constants since
3799 we might have been counting on using the fact that some bits were
3800 zero. We now do this in the SET. */
3805 /* (not (plus X -1)) can become (neg X). */
3806 if (GET_CODE (XEXP (x
, 0)) == PLUS
3807 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3808 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3810 /* Similarly, (not (neg X)) is (plus X -1). */
3811 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3812 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3814 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3815 if (GET_CODE (XEXP (x
, 0)) == XOR
3816 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3817 && (temp
= simplify_unary_operation (NOT
, mode
,
3818 XEXP (XEXP (x
, 0), 1),
3820 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3822 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3823 other than 1, but that is not valid. We could do a similar
3824 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3825 but this doesn't seem common enough to bother with. */
3826 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3827 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3828 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3830 XEXP (XEXP (x
, 0), 1));
3832 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3833 && subreg_lowpart_p (XEXP (x
, 0))
3834 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3835 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3836 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3837 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3839 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3841 x
= gen_rtx_ROTATE (inner_mode
,
3842 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3844 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3845 return gen_lowpart_for_combine (mode
, x
);
3848 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3849 reversing the comparison code if valid. */
3850 if (STORE_FLAG_VALUE
== -1
3851 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3852 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3853 XEXP (XEXP (x
, 0), 1))))
3856 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3857 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3858 perform the above simplification. */
3860 if (STORE_FLAG_VALUE
== -1
3861 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3862 && XEXP (x
, 1) == const1_rtx
3863 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3864 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3865 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3867 /* Apply De Morgan's laws to reduce number of patterns for machines
3868 with negating logical insns (and-not, nand, etc.). If result has
3869 only one NOT, put it first, since that is how the patterns are
3872 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3874 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3875 enum machine_mode op_mode
;
3877 op_mode
= GET_MODE (in1
);
3878 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3880 op_mode
= GET_MODE (in2
);
3881 if (op_mode
== VOIDmode
)
3883 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3885 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3888 in2
= in1
; in1
= tem
;
3891 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3897 /* (neg (plus X 1)) can become (not X). */
3898 if (GET_CODE (XEXP (x
, 0)) == PLUS
3899 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3900 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
3902 /* Similarly, (neg (not X)) is (plus X 1). */
3903 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3904 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3906 /* (neg (minus X Y)) can become (minus Y X). */
3907 if (GET_CODE (XEXP (x
, 0)) == MINUS
3908 && (! FLOAT_MODE_P (mode
)
3909 /* x-y != -(y-x) with IEEE floating point. */
3910 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3911 || flag_unsafe_math_optimizations
))
3912 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3913 XEXP (XEXP (x
, 0), 0));
3915 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3916 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3917 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3918 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3920 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3921 if we can then eliminate the NEG (e.g.,
3922 if the operand is a constant). */
3924 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3926 temp
= simplify_unary_operation (NEG
, mode
,
3927 XEXP (XEXP (x
, 0), 0), mode
);
3929 return gen_binary (ASHIFT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
3932 temp
= expand_compound_operation (XEXP (x
, 0));
3934 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3935 replaced by (lshiftrt X C). This will convert
3936 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3938 if (GET_CODE (temp
) == ASHIFTRT
3939 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3940 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3941 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3942 INTVAL (XEXP (temp
, 1)));
3944 /* If X has only a single bit that might be nonzero, say, bit I, convert
3945 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3946 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3947 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3948 or a SUBREG of one since we'd be making the expression more
3949 complex if it was just a register. */
3951 if (GET_CODE (temp
) != REG
3952 && ! (GET_CODE (temp
) == SUBREG
3953 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3954 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3956 rtx temp1
= simplify_shift_const
3957 (NULL_RTX
, ASHIFTRT
, mode
,
3958 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3959 GET_MODE_BITSIZE (mode
) - 1 - i
),
3960 GET_MODE_BITSIZE (mode
) - 1 - i
);
3962 /* If all we did was surround TEMP with the two shifts, we
3963 haven't improved anything, so don't use it. Otherwise,
3964 we are better off with TEMP1. */
3965 if (GET_CODE (temp1
) != ASHIFTRT
3966 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3967 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3973 /* We can't handle truncation to a partial integer mode here
3974 because we don't know the real bitsize of the partial
3976 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3979 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3980 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3981 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3983 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3984 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3986 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3987 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3988 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3989 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3990 return XEXP (XEXP (x
, 0), 0);
3992 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3993 (OP:SI foo:SI) if OP is NEG or ABS. */
3994 if ((GET_CODE (XEXP (x
, 0)) == ABS
3995 || GET_CODE (XEXP (x
, 0)) == NEG
)
3996 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3997 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3998 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3999 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4000 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4002 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4004 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4005 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4006 && subreg_lowpart_p (XEXP (x
, 0)))
4007 return SUBREG_REG (XEXP (x
, 0));
4009 /* If we know that the value is already truncated, we can
4010 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4011 is nonzero for the corresponding modes. But don't do this
4012 for an (LSHIFTRT (MULT ...)) since this will cause problems
4013 with the umulXi3_highpart patterns. */
4014 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4015 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4016 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4017 >= GET_MODE_BITSIZE (mode
) + 1
4018 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4019 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4020 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4022 /* A truncate of a comparison can be replaced with a subreg if
4023 STORE_FLAG_VALUE permits. This is like the previous test,
4024 but it works even if the comparison is done in a mode larger
4025 than HOST_BITS_PER_WIDE_INT. */
4026 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4027 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4028 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4029 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4031 /* Similarly, a truncate of a register whose value is a
4032 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4034 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4035 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4036 && (temp
= get_last_value (XEXP (x
, 0)))
4037 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4038 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4042 case FLOAT_TRUNCATE
:
4043 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4044 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4045 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4046 return XEXP (XEXP (x
, 0), 0);
4048 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4049 (OP:SF foo:SF) if OP is NEG or ABS. */
4050 if ((GET_CODE (XEXP (x
, 0)) == ABS
4051 || GET_CODE (XEXP (x
, 0)) == NEG
)
4052 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4053 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4054 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4055 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4057 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4058 is (float_truncate:SF x). */
4059 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4060 && subreg_lowpart_p (XEXP (x
, 0))
4061 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4062 return SUBREG_REG (XEXP (x
, 0));
4067 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4068 using cc0, in which case we want to leave it as a COMPARE
4069 so we can distinguish it from a register-register-copy. */
4070 if (XEXP (x
, 1) == const0_rtx
)
4073 /* In IEEE floating point, x-0 is not the same as x. */
4074 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4075 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4076 || flag_unsafe_math_optimizations
)
4077 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4083 /* (const (const X)) can become (const X). Do it this way rather than
4084 returning the inner CONST since CONST can be shared with a
4086 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4087 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4092 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4093 can add in an offset. find_split_point will split this address up
4094 again if it doesn't match. */
4095 if (GET_CODE (XEXP (x
, 0)) == HIGH
4096 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4102 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4103 outermost. That's because that's the way indexed addresses are
4104 supposed to appear. This code used to check many more cases, but
4105 they are now checked elsewhere. */
4106 if (GET_CODE (XEXP (x
, 0)) == PLUS
4107 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4108 return gen_binary (PLUS
, mode
,
4109 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4111 XEXP (XEXP (x
, 0), 1));
4113 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4114 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4115 bit-field and can be replaced by either a sign_extend or a
4116 sign_extract. The `and' may be a zero_extend and the two
4117 <c>, -<c> constants may be reversed. */
4118 if (GET_CODE (XEXP (x
, 0)) == XOR
4119 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4120 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4121 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4122 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4123 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4124 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4125 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4126 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4127 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4128 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4129 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4130 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4131 == (unsigned int) i
+ 1))))
4132 return simplify_shift_const
4133 (NULL_RTX
, ASHIFTRT
, mode
,
4134 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4135 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4136 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4137 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4139 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4140 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4141 is 1. This produces better code than the alternative immediately
4143 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4144 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4145 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4146 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4147 XEXP (XEXP (x
, 0), 0),
4148 XEXP (XEXP (x
, 0), 1))))
4150 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4152 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4153 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4154 the bitsize of the mode - 1. This allows simplification of
4155 "a = (b & 8) == 0;" */
4156 if (XEXP (x
, 1) == constm1_rtx
4157 && GET_CODE (XEXP (x
, 0)) != REG
4158 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4159 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4160 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4161 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4162 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4163 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4164 GET_MODE_BITSIZE (mode
) - 1),
4165 GET_MODE_BITSIZE (mode
) - 1);
4167 /* If we are adding two things that have no bits in common, convert
4168 the addition into an IOR. This will often be further simplified,
4169 for example in cases like ((a & 1) + (a & 2)), which can
4172 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4173 && (nonzero_bits (XEXP (x
, 0), mode
)
4174 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4176 /* Try to simplify the expression further. */
4177 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4178 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4180 /* If we could, great. If not, do not go ahead with the IOR
4181 replacement, since PLUS appears in many special purpose
4182 address arithmetic instructions. */
4183 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4189 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4190 by reversing the comparison code if valid. */
4191 if (STORE_FLAG_VALUE
== 1
4192 && XEXP (x
, 0) == const1_rtx
4193 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4194 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4195 XEXP (XEXP (x
, 1), 0),
4196 XEXP (XEXP (x
, 1), 1))))
4199 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4200 (and <foo> (const_int pow2-1)) */
4201 if (GET_CODE (XEXP (x
, 1)) == AND
4202 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4203 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4204 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4205 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4206 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4208 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4210 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4211 return gen_binary (MINUS
, mode
,
4212 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4213 XEXP (XEXP (x
, 1), 0)),
4214 XEXP (XEXP (x
, 1), 1));
4218 /* If we have (mult (plus A B) C), apply the distributive law and then
4219 the inverse distributive law to see if things simplify. This
4220 occurs mostly in addresses, often when unrolling loops. */
4222 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4224 x
= apply_distributive_law
4225 (gen_binary (PLUS
, mode
,
4226 gen_binary (MULT
, mode
,
4227 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4228 gen_binary (MULT
, mode
,
4229 XEXP (XEXP (x
, 0), 1),
4230 copy_rtx (XEXP (x
, 1)))));
4232 if (GET_CODE (x
) != MULT
)
4235 /* Try simplify a*(b/c) as (a*b)/c. */
4236 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4237 && GET_CODE (XEXP (x
, 0)) == DIV
)
4239 rtx tem
= simplify_binary_operation (MULT
, mode
,
4240 XEXP (XEXP (x
, 0), 0),
4243 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4248 /* If this is a divide by a power of two, treat it as a shift if
4249 its first operand is a shift. */
4250 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4251 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4252 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4253 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4254 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4255 || GET_CODE (XEXP (x
, 0)) == ROTATE
4256 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4257 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4261 case GT
: case GTU
: case GE
: case GEU
:
4262 case LT
: case LTU
: case LE
: case LEU
:
4263 case UNEQ
: case LTGT
:
4264 case UNGT
: case UNGE
:
4265 case UNLT
: case UNLE
:
4266 case UNORDERED
: case ORDERED
:
4267 /* If the first operand is a condition code, we can't do anything
4269 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4270 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4272 && XEXP (x
, 0) != cc0_rtx
4276 rtx op0
= XEXP (x
, 0);
4277 rtx op1
= XEXP (x
, 1);
4278 enum rtx_code new_code
;
4280 if (GET_CODE (op0
) == COMPARE
)
4281 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4283 /* Simplify our comparison, if possible. */
4284 new_code
= simplify_comparison (code
, &op0
, &op1
);
4286 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4287 if only the low-order bit is possibly nonzero in X (such as when
4288 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4289 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4290 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4293 Remove any ZERO_EXTRACT we made when thinking this was a
4294 comparison. It may now be simpler to use, e.g., an AND. If a
4295 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4296 the call to make_compound_operation in the SET case. */
4298 if (STORE_FLAG_VALUE
== 1
4299 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4300 && op1
== const0_rtx
4301 && mode
== GET_MODE (op0
)
4302 && nonzero_bits (op0
, mode
) == 1)
4303 return gen_lowpart_for_combine (mode
,
4304 expand_compound_operation (op0
));
4306 else if (STORE_FLAG_VALUE
== 1
4307 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4308 && op1
== const0_rtx
4309 && mode
== GET_MODE (op0
)
4310 && (num_sign_bit_copies (op0
, mode
)
4311 == GET_MODE_BITSIZE (mode
)))
4313 op0
= expand_compound_operation (op0
);
4314 return simplify_gen_unary (NEG
, mode
,
4315 gen_lowpart_for_combine (mode
, op0
),
4319 else if (STORE_FLAG_VALUE
== 1
4320 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4321 && op1
== const0_rtx
4322 && mode
== GET_MODE (op0
)
4323 && nonzero_bits (op0
, mode
) == 1)
4325 op0
= expand_compound_operation (op0
);
4326 return gen_binary (XOR
, mode
,
4327 gen_lowpart_for_combine (mode
, op0
),
4331 else if (STORE_FLAG_VALUE
== 1
4332 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4333 && op1
== const0_rtx
4334 && mode
== GET_MODE (op0
)
4335 && (num_sign_bit_copies (op0
, mode
)
4336 == GET_MODE_BITSIZE (mode
)))
4338 op0
= expand_compound_operation (op0
);
4339 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4342 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4344 if (STORE_FLAG_VALUE
== -1
4345 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4346 && op1
== const0_rtx
4347 && (num_sign_bit_copies (op0
, mode
)
4348 == GET_MODE_BITSIZE (mode
)))
4349 return gen_lowpart_for_combine (mode
,
4350 expand_compound_operation (op0
));
4352 else if (STORE_FLAG_VALUE
== -1
4353 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4354 && op1
== const0_rtx
4355 && mode
== GET_MODE (op0
)
4356 && nonzero_bits (op0
, mode
) == 1)
4358 op0
= expand_compound_operation (op0
);
4359 return simplify_gen_unary (NEG
, mode
,
4360 gen_lowpart_for_combine (mode
, op0
),
4364 else if (STORE_FLAG_VALUE
== -1
4365 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4366 && op1
== const0_rtx
4367 && mode
== GET_MODE (op0
)
4368 && (num_sign_bit_copies (op0
, mode
)
4369 == GET_MODE_BITSIZE (mode
)))
4371 op0
= expand_compound_operation (op0
);
4372 return simplify_gen_unary (NOT
, mode
,
4373 gen_lowpart_for_combine (mode
, op0
),
4377 /* If X is 0/1, (eq X 0) is X-1. */
4378 else if (STORE_FLAG_VALUE
== -1
4379 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4380 && op1
== const0_rtx
4381 && mode
== GET_MODE (op0
)
4382 && nonzero_bits (op0
, mode
) == 1)
4384 op0
= expand_compound_operation (op0
);
4385 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4388 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4389 one bit that might be nonzero, we can convert (ne x 0) to
4390 (ashift x c) where C puts the bit in the sign bit. Remove any
4391 AND with STORE_FLAG_VALUE when we are done, since we are only
4392 going to test the sign bit. */
4393 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4394 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4395 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4396 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4397 && op1
== const0_rtx
4398 && mode
== GET_MODE (op0
)
4399 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4401 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4402 expand_compound_operation (op0
),
4403 GET_MODE_BITSIZE (mode
) - 1 - i
);
4404 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4410 /* If the code changed, return a whole new comparison. */
4411 if (new_code
!= code
)
4412 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4414 /* Otherwise, keep this operation, but maybe change its operands.
4415 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4416 SUBST (XEXP (x
, 0), op0
);
4417 SUBST (XEXP (x
, 1), op1
);
4422 return simplify_if_then_else (x
);
4428 /* If we are processing SET_DEST, we are done. */
4432 return expand_compound_operation (x
);
4435 return simplify_set (x
);
4440 return simplify_logical (x
, last
);
4443 /* (abs (neg <foo>)) -> (abs <foo>) */
4444 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4445 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4447 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4449 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4452 /* If operand is something known to be positive, ignore the ABS. */
4453 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4454 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4455 <= HOST_BITS_PER_WIDE_INT
)
4456 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4457 & ((HOST_WIDE_INT
) 1
4458 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4462 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4463 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4464 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4469 /* (ffs (*_extend <X>)) = (ffs <X>) */
4470 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4471 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4472 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4476 /* (float (sign_extend <X>)) = (float <X>). */
4477 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4478 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4486 /* If this is a shift by a constant amount, simplify it. */
4487 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4488 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4489 INTVAL (XEXP (x
, 1)));
4491 #ifdef SHIFT_COUNT_TRUNCATED
4492 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4494 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4496 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4505 rtx op0
= XEXP (x
, 0);
4506 rtx op1
= XEXP (x
, 1);
4509 if (GET_CODE (op1
) != PARALLEL
)
4511 len
= XVECLEN (op1
, 0);
4513 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4514 && GET_CODE (op0
) == VEC_CONCAT
)
4516 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4518 /* Try to find the element in the VEC_CONCAT. */
4521 if (GET_MODE (op0
) == GET_MODE (x
))
4523 if (GET_CODE (op0
) == VEC_CONCAT
)
4525 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4526 if (op0_size
< offset
)
4527 op0
= XEXP (op0
, 0);
4531 op0
= XEXP (op0
, 1);
4549 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4552 simplify_if_then_else (x
)
4555 enum machine_mode mode
= GET_MODE (x
);
4556 rtx cond
= XEXP (x
, 0);
4557 rtx true_rtx
= XEXP (x
, 1);
4558 rtx false_rtx
= XEXP (x
, 2);
4559 enum rtx_code true_code
= GET_CODE (cond
);
4560 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4563 enum rtx_code false_code
;
4566 /* Simplify storing of the truth value. */
4567 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4568 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4570 /* Also when the truth value has to be reversed. */
4572 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4573 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4577 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4578 in it is being compared against certain values. Get the true and false
4579 comparisons and see if that says anything about the value of each arm. */
4582 && ((false_code
= combine_reversed_comparison_code (cond
))
4584 && GET_CODE (XEXP (cond
, 0)) == REG
)
4587 rtx from
= XEXP (cond
, 0);
4588 rtx true_val
= XEXP (cond
, 1);
4589 rtx false_val
= true_val
;
4592 /* If FALSE_CODE is EQ, swap the codes and arms. */
4594 if (false_code
== EQ
)
4596 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4597 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4600 /* If we are comparing against zero and the expression being tested has
4601 only a single bit that might be nonzero, that is its value when it is
4602 not equal to zero. Similarly if it is known to be -1 or 0. */
4604 if (true_code
== EQ
&& true_val
== const0_rtx
4605 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4606 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4607 else if (true_code
== EQ
&& true_val
== const0_rtx
4608 && (num_sign_bit_copies (from
, GET_MODE (from
))
4609 == GET_MODE_BITSIZE (GET_MODE (from
))))
4610 false_code
= EQ
, false_val
= constm1_rtx
;
4612 /* Now simplify an arm if we know the value of the register in the
4613 branch and it is used in the arm. Be careful due to the potential
4614 of locally-shared RTL. */
4616 if (reg_mentioned_p (from
, true_rtx
))
4617 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4619 pc_rtx
, pc_rtx
, 0, 0);
4620 if (reg_mentioned_p (from
, false_rtx
))
4621 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4623 pc_rtx
, pc_rtx
, 0, 0);
4625 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4626 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4628 true_rtx
= XEXP (x
, 1);
4629 false_rtx
= XEXP (x
, 2);
4630 true_code
= GET_CODE (cond
);
4633 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4634 reversed, do so to avoid needing two sets of patterns for
4635 subtract-and-branch insns. Similarly if we have a constant in the true
4636 arm, the false arm is the same as the first operand of the comparison, or
4637 the false arm is more complicated than the true arm. */
4640 && combine_reversed_comparison_code (cond
) != UNKNOWN
4641 && (true_rtx
== pc_rtx
4642 || (CONSTANT_P (true_rtx
)
4643 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4644 || true_rtx
== const0_rtx
4645 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4646 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4647 || (GET_CODE (true_rtx
) == SUBREG
4648 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4649 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4650 || reg_mentioned_p (true_rtx
, false_rtx
)
4651 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4653 true_code
= reversed_comparison_code (cond
, NULL
);
4655 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4658 SUBST (XEXP (x
, 1), false_rtx
);
4659 SUBST (XEXP (x
, 2), true_rtx
);
4661 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4664 /* It is possible that the conditional has been simplified out. */
4665 true_code
= GET_CODE (cond
);
4666 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4669 /* If the two arms are identical, we don't need the comparison. */
4671 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4674 /* Convert a == b ? b : a to "a". */
4675 if (true_code
== EQ
&& ! side_effects_p (cond
)
4676 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4677 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4678 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4680 else if (true_code
== NE
&& ! side_effects_p (cond
)
4681 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4682 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4683 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4686 /* Look for cases where we have (abs x) or (neg (abs X)). */
4688 if (GET_MODE_CLASS (mode
) == MODE_INT
4689 && GET_CODE (false_rtx
) == NEG
4690 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4692 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4693 && ! side_effects_p (true_rtx
))
4698 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4702 simplify_gen_unary (NEG
, mode
,
4703 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4709 /* Look for MIN or MAX. */
4711 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4713 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4714 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4715 && ! side_effects_p (cond
))
4720 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4723 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4726 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4729 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4734 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4735 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4736 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4737 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4738 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4739 neither 1 or -1, but it isn't worth checking for. */
4741 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4742 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4744 rtx t
= make_compound_operation (true_rtx
, SET
);
4745 rtx f
= make_compound_operation (false_rtx
, SET
);
4746 rtx cond_op0
= XEXP (cond
, 0);
4747 rtx cond_op1
= XEXP (cond
, 1);
4748 enum rtx_code op
= NIL
, extend_op
= NIL
;
4749 enum machine_mode m
= mode
;
4750 rtx z
= 0, c1
= NULL_RTX
;
4752 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4753 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4754 || GET_CODE (t
) == ASHIFT
4755 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4756 && rtx_equal_p (XEXP (t
, 0), f
))
4757 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4759 /* If an identity-zero op is commutative, check whether there
4760 would be a match if we swapped the operands. */
4761 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4762 || GET_CODE (t
) == XOR
)
4763 && rtx_equal_p (XEXP (t
, 1), f
))
4764 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4765 else if (GET_CODE (t
) == SIGN_EXTEND
4766 && (GET_CODE (XEXP (t
, 0)) == PLUS
4767 || GET_CODE (XEXP (t
, 0)) == MINUS
4768 || GET_CODE (XEXP (t
, 0)) == IOR
4769 || GET_CODE (XEXP (t
, 0)) == XOR
4770 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4771 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4772 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4773 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4774 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4775 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4776 && (num_sign_bit_copies (f
, GET_MODE (f
))
4777 > (GET_MODE_BITSIZE (mode
)
4778 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4780 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4781 extend_op
= SIGN_EXTEND
;
4782 m
= GET_MODE (XEXP (t
, 0));
4784 else if (GET_CODE (t
) == SIGN_EXTEND
4785 && (GET_CODE (XEXP (t
, 0)) == PLUS
4786 || GET_CODE (XEXP (t
, 0)) == IOR
4787 || GET_CODE (XEXP (t
, 0)) == XOR
)
4788 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4789 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4790 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4791 && (num_sign_bit_copies (f
, GET_MODE (f
))
4792 > (GET_MODE_BITSIZE (mode
)
4793 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4795 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4796 extend_op
= SIGN_EXTEND
;
4797 m
= GET_MODE (XEXP (t
, 0));
4799 else if (GET_CODE (t
) == ZERO_EXTEND
4800 && (GET_CODE (XEXP (t
, 0)) == PLUS
4801 || GET_CODE (XEXP (t
, 0)) == MINUS
4802 || GET_CODE (XEXP (t
, 0)) == IOR
4803 || GET_CODE (XEXP (t
, 0)) == XOR
4804 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4805 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4806 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4807 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4808 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4809 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4810 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4811 && ((nonzero_bits (f
, GET_MODE (f
))
4812 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4815 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4816 extend_op
= ZERO_EXTEND
;
4817 m
= GET_MODE (XEXP (t
, 0));
4819 else if (GET_CODE (t
) == ZERO_EXTEND
4820 && (GET_CODE (XEXP (t
, 0)) == PLUS
4821 || GET_CODE (XEXP (t
, 0)) == IOR
4822 || GET_CODE (XEXP (t
, 0)) == XOR
)
4823 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4824 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4825 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4826 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4827 && ((nonzero_bits (f
, GET_MODE (f
))
4828 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4831 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4832 extend_op
= ZERO_EXTEND
;
4833 m
= GET_MODE (XEXP (t
, 0));
4838 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4839 pc_rtx
, pc_rtx
, 0, 0);
4840 temp
= gen_binary (MULT
, m
, temp
,
4841 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4842 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4843 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4845 if (extend_op
!= NIL
)
4846 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4852 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4853 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4854 negation of a single bit, we can convert this operation to a shift. We
4855 can actually do this more generally, but it doesn't seem worth it. */
4857 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4858 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4859 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4860 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4861 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4862 == GET_MODE_BITSIZE (mode
))
4863 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4865 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4866 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4871 /* Simplify X, a SET expression. Return the new expression. */
4877 rtx src
= SET_SRC (x
);
4878 rtx dest
= SET_DEST (x
);
4879 enum machine_mode mode
4880 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4884 /* (set (pc) (return)) gets written as (return). */
4885 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4888 /* Now that we know for sure which bits of SRC we are using, see if we can
4889 simplify the expression for the object knowing that we only need the
4892 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4894 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4895 SUBST (SET_SRC (x
), src
);
4898 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4899 the comparison result and try to simplify it unless we already have used
4900 undobuf.other_insn. */
4901 if ((GET_CODE (src
) == COMPARE
4906 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4907 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4908 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4909 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4911 enum rtx_code old_code
= GET_CODE (*cc_use
);
4912 enum rtx_code new_code
;
4914 int other_changed
= 0;
4915 enum machine_mode compare_mode
= GET_MODE (dest
);
4917 if (GET_CODE (src
) == COMPARE
)
4918 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4920 op0
= src
, op1
= const0_rtx
;
4922 /* Simplify our comparison, if possible. */
4923 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4925 #ifdef EXTRA_CC_MODES
4926 /* If this machine has CC modes other than CCmode, check to see if we
4927 need to use a different CC mode here. */
4928 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4929 #endif /* EXTRA_CC_MODES */
4931 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4932 /* If the mode changed, we have to change SET_DEST, the mode in the
4933 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4934 a hard register, just build new versions with the proper mode. If it
4935 is a pseudo, we lose unless it is only time we set the pseudo, in
4936 which case we can safely change its mode. */
4937 if (compare_mode
!= GET_MODE (dest
))
4939 unsigned int regno
= REGNO (dest
);
4940 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
4942 if (regno
< FIRST_PSEUDO_REGISTER
4943 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
4945 if (regno
>= FIRST_PSEUDO_REGISTER
)
4946 SUBST (regno_reg_rtx
[regno
], new_dest
);
4948 SUBST (SET_DEST (x
), new_dest
);
4949 SUBST (XEXP (*cc_use
, 0), new_dest
);
4957 /* If the code changed, we have to build a new comparison in
4958 undobuf.other_insn. */
4959 if (new_code
!= old_code
)
4961 unsigned HOST_WIDE_INT mask
;
4963 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
4966 /* If the only change we made was to change an EQ into an NE or
4967 vice versa, OP0 has only one bit that might be nonzero, and OP1
4968 is zero, check if changing the user of the condition code will
4969 produce a valid insn. If it won't, we can keep the original code
4970 in that insn by surrounding our operation with an XOR. */
4972 if (((old_code
== NE
&& new_code
== EQ
)
4973 || (old_code
== EQ
&& new_code
== NE
))
4974 && ! other_changed
&& op1
== const0_rtx
4975 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4976 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4978 rtx pat
= PATTERN (other_insn
), note
= 0;
4980 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
4981 && ! check_asm_operands (pat
)))
4983 PUT_CODE (*cc_use
, old_code
);
4986 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4994 undobuf
.other_insn
= other_insn
;
4997 /* If we are now comparing against zero, change our source if
4998 needed. If we do not use cc0, we always have a COMPARE. */
4999 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5001 SUBST (SET_SRC (x
), op0
);
5007 /* Otherwise, if we didn't previously have a COMPARE in the
5008 correct mode, we need one. */
5009 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5011 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5016 /* Otherwise, update the COMPARE if needed. */
5017 SUBST (XEXP (src
, 0), op0
);
5018 SUBST (XEXP (src
, 1), op1
);
5023 /* Get SET_SRC in a form where we have placed back any
5024 compound expressions. Then do the checks below. */
5025 src
= make_compound_operation (src
, SET
);
5026 SUBST (SET_SRC (x
), src
);
5029 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5030 and X being a REG or (subreg (reg)), we may be able to convert this to
5031 (set (subreg:m2 x) (op)).
5033 We can always do this if M1 is narrower than M2 because that means that
5034 we only care about the low bits of the result.
5036 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5037 perform a narrower operation than requested since the high-order bits will
5038 be undefined. On machine where it is defined, this transformation is safe
5039 as long as M1 and M2 have the same number of words. */
5041 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5042 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5043 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5045 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5046 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5047 #ifndef WORD_REGISTER_OPERATIONS
5048 && (GET_MODE_SIZE (GET_MODE (src
))
5049 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5051 #ifdef CLASS_CANNOT_CHANGE_MODE
5052 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5053 && (TEST_HARD_REG_BIT
5054 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5056 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5057 GET_MODE (SUBREG_REG (src
))))
5059 && (GET_CODE (dest
) == REG
5060 || (GET_CODE (dest
) == SUBREG
5061 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5063 SUBST (SET_DEST (x
),
5064 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5066 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5068 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5071 #ifdef LOAD_EXTEND_OP
5072 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5073 would require a paradoxical subreg. Replace the subreg with a
5074 zero_extend to avoid the reload that would otherwise be required. */
5076 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5077 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5078 && SUBREG_BYTE (src
) == 0
5079 && (GET_MODE_SIZE (GET_MODE (src
))
5080 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5081 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5084 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5085 GET_MODE (src
), SUBREG_REG (src
)));
5091 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5092 are comparing an item known to be 0 or -1 against 0, use a logical
5093 operation instead. Check for one of the arms being an IOR of the other
5094 arm with some value. We compute three terms to be IOR'ed together. In
5095 practice, at most two will be nonzero. Then we do the IOR's. */
5097 if (GET_CODE (dest
) != PC
5098 && GET_CODE (src
) == IF_THEN_ELSE
5099 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5100 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5101 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5102 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5103 #ifdef HAVE_conditional_move
5104 && ! can_conditionally_move_p (GET_MODE (src
))
5106 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5107 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5108 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5109 && ! side_effects_p (src
))
5111 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5112 ? XEXP (src
, 1) : XEXP (src
, 2));
5113 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5114 ? XEXP (src
, 2) : XEXP (src
, 1));
5115 rtx term1
= const0_rtx
, term2
, term3
;
5117 if (GET_CODE (true_rtx
) == IOR
5118 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5119 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5120 else if (GET_CODE (true_rtx
) == IOR
5121 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5122 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5123 else if (GET_CODE (false_rtx
) == IOR
5124 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5125 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5126 else if (GET_CODE (false_rtx
) == IOR
5127 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5128 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5130 term2
= gen_binary (AND
, GET_MODE (src
),
5131 XEXP (XEXP (src
, 0), 0), true_rtx
);
5132 term3
= gen_binary (AND
, GET_MODE (src
),
5133 simplify_gen_unary (NOT
, GET_MODE (src
),
5134 XEXP (XEXP (src
, 0), 0),
5139 gen_binary (IOR
, GET_MODE (src
),
5140 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5146 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5147 whole thing fail. */
5148 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5150 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5153 /* Convert this into a field assignment operation, if possible. */
5154 return make_field_assignment (x
);
5157 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5158 result. LAST is nonzero if this is the last retry. */
5161 simplify_logical (x
, last
)
5165 enum machine_mode mode
= GET_MODE (x
);
5166 rtx op0
= XEXP (x
, 0);
5167 rtx op1
= XEXP (x
, 1);
5170 switch (GET_CODE (x
))
5173 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5174 insn (and may simplify more). */
5175 if (GET_CODE (op0
) == XOR
5176 && rtx_equal_p (XEXP (op0
, 0), op1
)
5177 && ! side_effects_p (op1
))
5178 x
= gen_binary (AND
, mode
,
5179 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5182 if (GET_CODE (op0
) == XOR
5183 && rtx_equal_p (XEXP (op0
, 1), op1
)
5184 && ! side_effects_p (op1
))
5185 x
= gen_binary (AND
, mode
,
5186 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5189 /* Similarly for (~(A ^ B)) & A. */
5190 if (GET_CODE (op0
) == NOT
5191 && GET_CODE (XEXP (op0
, 0)) == XOR
5192 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5193 && ! side_effects_p (op1
))
5194 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5196 if (GET_CODE (op0
) == NOT
5197 && GET_CODE (XEXP (op0
, 0)) == XOR
5198 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5199 && ! side_effects_p (op1
))
5200 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5202 /* We can call simplify_and_const_int only if we don't lose
5203 any (sign) bits when converting INTVAL (op1) to
5204 "unsigned HOST_WIDE_INT". */
5205 if (GET_CODE (op1
) == CONST_INT
5206 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5207 || INTVAL (op1
) > 0))
5209 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5211 /* If we have (ior (and (X C1) C2)) and the next restart would be
5212 the last, simplify this by making C1 as small as possible
5215 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5216 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5217 && GET_CODE (op1
) == CONST_INT
)
5218 return gen_binary (IOR
, mode
,
5219 gen_binary (AND
, mode
, XEXP (op0
, 0),
5220 GEN_INT (INTVAL (XEXP (op0
, 1))
5221 & ~INTVAL (op1
))), op1
);
5223 if (GET_CODE (x
) != AND
)
5226 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5227 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5228 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5231 /* Convert (A | B) & A to A. */
5232 if (GET_CODE (op0
) == IOR
5233 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5234 || rtx_equal_p (XEXP (op0
, 1), op1
))
5235 && ! side_effects_p (XEXP (op0
, 0))
5236 && ! side_effects_p (XEXP (op0
, 1)))
5239 /* In the following group of tests (and those in case IOR below),
5240 we start with some combination of logical operations and apply
5241 the distributive law followed by the inverse distributive law.
5242 Most of the time, this results in no change. However, if some of
5243 the operands are the same or inverses of each other, simplifications
5246 For example, (and (ior A B) (not B)) can occur as the result of
5247 expanding a bit field assignment. When we apply the distributive
5248 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5249 which then simplifies to (and (A (not B))).
5251 If we have (and (ior A B) C), apply the distributive law and then
5252 the inverse distributive law to see if things simplify. */
5254 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5256 x
= apply_distributive_law
5257 (gen_binary (GET_CODE (op0
), mode
,
5258 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5259 gen_binary (AND
, mode
, XEXP (op0
, 1),
5261 if (GET_CODE (x
) != AND
)
5265 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5266 return apply_distributive_law
5267 (gen_binary (GET_CODE (op1
), mode
,
5268 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5269 gen_binary (AND
, mode
, XEXP (op1
, 1),
5272 /* Similarly, taking advantage of the fact that
5273 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5275 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5276 return apply_distributive_law
5277 (gen_binary (XOR
, mode
,
5278 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5279 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5282 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5283 return apply_distributive_law
5284 (gen_binary (XOR
, mode
,
5285 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5286 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5290 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5291 if (GET_CODE (op1
) == CONST_INT
5292 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5293 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5296 /* Convert (A & B) | A to A. */
5297 if (GET_CODE (op0
) == AND
5298 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5299 || rtx_equal_p (XEXP (op0
, 1), op1
))
5300 && ! side_effects_p (XEXP (op0
, 0))
5301 && ! side_effects_p (XEXP (op0
, 1)))
5304 /* If we have (ior (and A B) C), apply the distributive law and then
5305 the inverse distributive law to see if things simplify. */
5307 if (GET_CODE (op0
) == AND
)
5309 x
= apply_distributive_law
5310 (gen_binary (AND
, mode
,
5311 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5312 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5315 if (GET_CODE (x
) != IOR
)
5319 if (GET_CODE (op1
) == AND
)
5321 x
= apply_distributive_law
5322 (gen_binary (AND
, mode
,
5323 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5324 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5327 if (GET_CODE (x
) != IOR
)
5331 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5332 mode size to (rotate A CX). */
5334 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5335 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5336 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5337 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5338 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5339 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5340 == GET_MODE_BITSIZE (mode
)))
5341 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5342 (GET_CODE (op0
) == ASHIFT
5343 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5345 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5346 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5347 does not affect any of the bits in OP1, it can really be done
5348 as a PLUS and we can associate. We do this by seeing if OP1
5349 can be safely shifted left C bits. */
5350 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5351 && GET_CODE (XEXP (op0
, 0)) == PLUS
5352 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5353 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5354 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5356 int count
= INTVAL (XEXP (op0
, 1));
5357 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5359 if (mask
>> count
== INTVAL (op1
)
5360 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5362 SUBST (XEXP (XEXP (op0
, 0), 1),
5363 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5370 /* If we are XORing two things that have no bits in common,
5371 convert them into an IOR. This helps to detect rotation encoded
5372 using those methods and possibly other simplifications. */
5374 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5375 && (nonzero_bits (op0
, mode
)
5376 & nonzero_bits (op1
, mode
)) == 0)
5377 return (gen_binary (IOR
, mode
, op0
, op1
));
5379 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5380 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5383 int num_negated
= 0;
5385 if (GET_CODE (op0
) == NOT
)
5386 num_negated
++, op0
= XEXP (op0
, 0);
5387 if (GET_CODE (op1
) == NOT
)
5388 num_negated
++, op1
= XEXP (op1
, 0);
5390 if (num_negated
== 2)
5392 SUBST (XEXP (x
, 0), op0
);
5393 SUBST (XEXP (x
, 1), op1
);
5395 else if (num_negated
== 1)
5397 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5401 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5402 correspond to a machine insn or result in further simplifications
5403 if B is a constant. */
5405 if (GET_CODE (op0
) == AND
5406 && rtx_equal_p (XEXP (op0
, 1), op1
)
5407 && ! side_effects_p (op1
))
5408 return gen_binary (AND
, mode
,
5409 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5412 else if (GET_CODE (op0
) == AND
5413 && rtx_equal_p (XEXP (op0
, 0), op1
)
5414 && ! side_effects_p (op1
))
5415 return gen_binary (AND
, mode
,
5416 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5419 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5420 comparison if STORE_FLAG_VALUE is 1. */
5421 if (STORE_FLAG_VALUE
== 1
5422 && op1
== const1_rtx
5423 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5424 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5428 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5429 is (lt foo (const_int 0)), so we can perform the above
5430 simplification if STORE_FLAG_VALUE is 1. */
5432 if (STORE_FLAG_VALUE
== 1
5433 && op1
== const1_rtx
5434 && GET_CODE (op0
) == LSHIFTRT
5435 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5436 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5437 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5439 /* (xor (comparison foo bar) (const_int sign-bit))
5440 when STORE_FLAG_VALUE is the sign bit. */
5441 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5442 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5443 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5444 && op1
== const_true_rtx
5445 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5446 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5459 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5460 operations" because they can be replaced with two more basic operations.
5461 ZERO_EXTEND is also considered "compound" because it can be replaced with
5462 an AND operation, which is simpler, though only one operation.
5464 The function expand_compound_operation is called with an rtx expression
5465 and will convert it to the appropriate shifts and AND operations,
5466 simplifying at each stage.
5468 The function make_compound_operation is called to convert an expression
5469 consisting of shifts and ANDs into the equivalent compound expression.
5470 It is the inverse of this function, loosely speaking. */
5473 expand_compound_operation (x
)
5476 unsigned HOST_WIDE_INT pos
= 0, len
;
5478 unsigned int modewidth
;
5481 switch (GET_CODE (x
))
5486 /* We can't necessarily use a const_int for a multiword mode;
5487 it depends on implicitly extending the value.
5488 Since we don't know the right way to extend it,
5489 we can't tell whether the implicit way is right.
5491 Even for a mode that is no wider than a const_int,
5492 we can't win, because we need to sign extend one of its bits through
5493 the rest of it, and we don't know which bit. */
5494 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5497 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5498 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5499 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5500 reloaded. If not for that, MEM's would very rarely be safe.
5502 Reject MODEs bigger than a word, because we might not be able
5503 to reference a two-register group starting with an arbitrary register
5504 (and currently gen_lowpart might crash for a SUBREG). */
5506 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5509 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5510 /* If the inner object has VOIDmode (the only way this can happen
5511 is if it is a ASM_OPERANDS), we can't do anything since we don't
5512 know how much masking to do. */
5521 /* If the operand is a CLOBBER, just return it. */
5522 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5525 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5526 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5527 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5530 len
= INTVAL (XEXP (x
, 1));
5531 pos
= INTVAL (XEXP (x
, 2));
5533 /* If this goes outside the object being extracted, replace the object
5534 with a (use (mem ...)) construct that only combine understands
5535 and is used only for this purpose. */
5536 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5537 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5539 if (BITS_BIG_ENDIAN
)
5540 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5547 /* Convert sign extension to zero extension, if we know that the high
5548 bit is not set, as this is easier to optimize. It will be converted
5549 back to cheaper alternative in make_extraction. */
5550 if (GET_CODE (x
) == SIGN_EXTEND
5551 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5552 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5553 & ~(((unsigned HOST_WIDE_INT
)
5554 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5558 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5559 return expand_compound_operation (temp
);
5562 /* We can optimize some special cases of ZERO_EXTEND. */
5563 if (GET_CODE (x
) == ZERO_EXTEND
)
5565 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5566 know that the last value didn't have any inappropriate bits
5568 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5569 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5570 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5571 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5572 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5573 return XEXP (XEXP (x
, 0), 0);
5575 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5576 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5577 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5578 && subreg_lowpart_p (XEXP (x
, 0))
5579 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5580 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5581 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5582 return SUBREG_REG (XEXP (x
, 0));
5584 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5585 is a comparison and STORE_FLAG_VALUE permits. This is like
5586 the first case, but it works even when GET_MODE (x) is larger
5587 than HOST_WIDE_INT. */
5588 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5589 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5590 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5591 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5592 <= HOST_BITS_PER_WIDE_INT
)
5593 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5594 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5595 return XEXP (XEXP (x
, 0), 0);
5597 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5598 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5599 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5600 && subreg_lowpart_p (XEXP (x
, 0))
5601 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5602 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5603 <= HOST_BITS_PER_WIDE_INT
)
5604 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5605 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5606 return SUBREG_REG (XEXP (x
, 0));
5610 /* If we reach here, we want to return a pair of shifts. The inner
5611 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5612 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5613 logical depending on the value of UNSIGNEDP.
5615 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5616 converted into an AND of a shift.
5618 We must check for the case where the left shift would have a negative
5619 count. This can happen in a case like (x >> 31) & 255 on machines
5620 that can't shift by a constant. On those machines, we would first
5621 combine the shift with the AND to produce a variable-position
5622 extraction. Then the constant of 31 would be substituted in to produce
5623 a such a position. */
5625 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5626 if (modewidth
+ len
>= pos
)
5627 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5629 simplify_shift_const (NULL_RTX
, ASHIFT
,
5632 modewidth
- pos
- len
),
5635 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5636 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5637 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5640 ((HOST_WIDE_INT
) 1 << len
) - 1);
5642 /* Any other cases we can't handle. */
5645 /* If we couldn't do this for some reason, return the original
5647 if (GET_CODE (tem
) == CLOBBER
)
5653 /* X is a SET which contains an assignment of one object into
5654 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5655 or certain SUBREGS). If possible, convert it into a series of
5658 We half-heartedly support variable positions, but do not at all
5659 support variable lengths. */
5662 expand_field_assignment (x
)
5666 rtx pos
; /* Always counts from low bit. */
5669 enum machine_mode compute_mode
;
5671 /* Loop until we find something we can't simplify. */
5674 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5675 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5677 int byte_offset
= SUBREG_BYTE (XEXP (SET_DEST (x
), 0));
5679 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5680 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5681 pos
= GEN_INT (BITS_PER_WORD
* (byte_offset
/ UNITS_PER_WORD
));
5683 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5684 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5686 inner
= XEXP (SET_DEST (x
), 0);
5687 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5688 pos
= XEXP (SET_DEST (x
), 2);
5690 /* If the position is constant and spans the width of INNER,
5691 surround INNER with a USE to indicate this. */
5692 if (GET_CODE (pos
) == CONST_INT
5693 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5694 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5696 if (BITS_BIG_ENDIAN
)
5698 if (GET_CODE (pos
) == CONST_INT
)
5699 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5701 else if (GET_CODE (pos
) == MINUS
5702 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5703 && (INTVAL (XEXP (pos
, 1))
5704 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5705 /* If position is ADJUST - X, new position is X. */
5706 pos
= XEXP (pos
, 0);
5708 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5709 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5715 /* A SUBREG between two modes that occupy the same numbers of words
5716 can be done by moving the SUBREG to the source. */
5717 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5718 /* We need SUBREGs to compute nonzero_bits properly. */
5719 && nonzero_sign_valid
5720 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5721 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5722 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5723 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5725 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5726 gen_lowpart_for_combine
5727 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5734 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5735 inner
= SUBREG_REG (inner
);
5737 compute_mode
= GET_MODE (inner
);
5739 /* Don't attempt bitwise arithmetic on non-integral modes. */
5740 if (! INTEGRAL_MODE_P (compute_mode
))
5742 enum machine_mode imode
;
5744 /* Something is probably seriously wrong if this matches. */
5745 if (! FLOAT_MODE_P (compute_mode
))
5748 /* Try to find an integral mode to pun with. */
5749 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5750 if (imode
== BLKmode
)
5753 compute_mode
= imode
;
5754 inner
= gen_lowpart_for_combine (imode
, inner
);
5757 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5758 if (len
< HOST_BITS_PER_WIDE_INT
)
5759 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5763 /* Now compute the equivalent expression. Make a copy of INNER
5764 for the SET_DEST in case it is a MEM into which we will substitute;
5765 we don't want shared RTL in that case. */
5767 (VOIDmode
, copy_rtx (inner
),
5768 gen_binary (IOR
, compute_mode
,
5769 gen_binary (AND
, compute_mode
,
5770 simplify_gen_unary (NOT
, compute_mode
,
5776 gen_binary (ASHIFT
, compute_mode
,
5777 gen_binary (AND
, compute_mode
,
5778 gen_lowpart_for_combine
5779 (compute_mode
, SET_SRC (x
)),
5787 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5788 it is an RTX that represents a variable starting position; otherwise,
5789 POS is the (constant) starting bit position (counted from the LSB).
5791 INNER may be a USE. This will occur when we started with a bitfield
5792 that went outside the boundary of the object in memory, which is
5793 allowed on most machines. To isolate this case, we produce a USE
5794 whose mode is wide enough and surround the MEM with it. The only
5795 code that understands the USE is this routine. If it is not removed,
5796 it will cause the resulting insn not to match.
5798 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5801 IN_DEST is non-zero if this is a reference in the destination of a
5802 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5803 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5806 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5807 ZERO_EXTRACT should be built even for bits starting at bit 0.
5809 MODE is the desired mode of the result (if IN_DEST == 0).
5811 The result is an RTX for the extraction or NULL_RTX if the target
5815 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5816 unsignedp
, in_dest
, in_compare
)
5817 enum machine_mode mode
;
5821 unsigned HOST_WIDE_INT len
;
5823 int in_dest
, in_compare
;
5825 /* This mode describes the size of the storage area
5826 to fetch the overall value from. Within that, we
5827 ignore the POS lowest bits, etc. */
5828 enum machine_mode is_mode
= GET_MODE (inner
);
5829 enum machine_mode inner_mode
;
5830 enum machine_mode wanted_inner_mode
= byte_mode
;
5831 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5832 enum machine_mode pos_mode
= word_mode
;
5833 enum machine_mode extraction_mode
= word_mode
;
5834 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5837 rtx orig_pos_rtx
= pos_rtx
;
5838 HOST_WIDE_INT orig_pos
;
5840 /* Get some information about INNER and get the innermost object. */
5841 if (GET_CODE (inner
) == USE
)
5842 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5843 /* We don't need to adjust the position because we set up the USE
5844 to pretend that it was a full-word object. */
5845 spans_byte
= 1, inner
= XEXP (inner
, 0);
5846 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5848 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5849 consider just the QI as the memory to extract from.
5850 The subreg adds or removes high bits; its mode is
5851 irrelevant to the meaning of this extraction,
5852 since POS and LEN count from the lsb. */
5853 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5854 is_mode
= GET_MODE (SUBREG_REG (inner
));
5855 inner
= SUBREG_REG (inner
);
5858 inner_mode
= GET_MODE (inner
);
5860 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5861 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5863 /* See if this can be done without an extraction. We never can if the
5864 width of the field is not the same as that of some integer mode. For
5865 registers, we can only avoid the extraction if the position is at the
5866 low-order bit and this is either not in the destination or we have the
5867 appropriate STRICT_LOW_PART operation available.
5869 For MEM, we can avoid an extract if the field starts on an appropriate
5870 boundary and we can change the mode of the memory reference. However,
5871 we cannot directly access the MEM if we have a USE and the underlying
5872 MEM is not TMODE. This combination means that MEM was being used in a
5873 context where bits outside its mode were being referenced; that is only
5874 valid in bit-field insns. */
5876 if (tmode
!= BLKmode
5877 && ! (spans_byte
&& inner_mode
!= tmode
)
5878 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5879 && GET_CODE (inner
) != MEM
5881 || (GET_CODE (inner
) == REG
5882 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
5883 != CODE_FOR_nothing
))))
5884 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5886 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5887 : BITS_PER_UNIT
)) == 0
5888 /* We can't do this if we are widening INNER_MODE (it
5889 may not be aligned, for one thing). */
5890 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5891 && (inner_mode
== tmode
5892 || (! mode_dependent_address_p (XEXP (inner
, 0))
5893 && ! MEM_VOLATILE_P (inner
))))))
5895 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5896 field. If the original and current mode are the same, we need not
5897 adjust the offset. Otherwise, we do if bytes big endian.
5899 If INNER is not a MEM, get a piece consisting of just the field
5900 of interest (in this case POS % BITS_PER_WORD must be 0). */
5902 if (GET_CODE (inner
) == MEM
)
5904 HOST_WIDE_INT offset
;
5906 /* POS counts from lsb, but make OFFSET count in memory order. */
5907 if (BYTES_BIG_ENDIAN
)
5908 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5910 offset
= pos
/ BITS_PER_UNIT
;
5912 new = adjust_address_nv (inner
, tmode
, offset
);
5914 else if (GET_CODE (inner
) == REG
)
5916 /* We can't call gen_lowpart_for_combine here since we always want
5917 a SUBREG and it would sometimes return a new hard register. */
5918 if (tmode
!= inner_mode
)
5920 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
5922 if (WORDS_BIG_ENDIAN
5923 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
5924 final_word
= ((GET_MODE_SIZE (inner_mode
)
5925 - GET_MODE_SIZE (tmode
))
5926 / UNITS_PER_WORD
) - final_word
;
5928 final_word
*= UNITS_PER_WORD
;
5929 if (BYTES_BIG_ENDIAN
&&
5930 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
5931 final_word
+= (GET_MODE_SIZE (inner_mode
)
5932 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
5934 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
5940 new = force_to_mode (inner
, tmode
,
5941 len
>= HOST_BITS_PER_WIDE_INT
5942 ? ~(unsigned HOST_WIDE_INT
) 0
5943 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
5946 /* If this extraction is going into the destination of a SET,
5947 make a STRICT_LOW_PART unless we made a MEM. */
5950 return (GET_CODE (new) == MEM
? new
5951 : (GET_CODE (new) != SUBREG
5952 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
5953 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
5958 /* If we know that no extraneous bits are set, and that the high
5959 bit is not set, convert the extraction to the cheaper of
5960 sign and zero extension, that are equivalent in these cases. */
5961 if (flag_expensive_optimizations
5962 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
5963 && ((nonzero_bits (new, tmode
)
5964 & ~(((unsigned HOST_WIDE_INT
)
5965 GET_MODE_MASK (tmode
))
5969 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
5970 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
5972 /* Prefer ZERO_EXTENSION, since it gives more information to
5974 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
5979 /* Otherwise, sign- or zero-extend unless we already are in the
5982 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5986 /* Unless this is a COMPARE or we have a funny memory reference,
5987 don't do anything with zero-extending field extracts starting at
5988 the low-order bit since they are simple AND operations. */
5989 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5990 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5993 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5994 we would be spanning bytes or if the position is not a constant and the
5995 length is not 1. In all other cases, we would only be going outside
5996 our object in cases when an original shift would have been
5998 if (! spans_byte
&& GET_CODE (inner
) == MEM
5999 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6000 || (pos_rtx
!= 0 && len
!= 1)))
6003 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6004 and the mode for the result. */
6008 wanted_inner_reg_mode
6009 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
6010 if (wanted_inner_reg_mode
== VOIDmode
)
6011 wanted_inner_reg_mode
= word_mode
;
6013 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
6014 if (pos_mode
== VOIDmode
)
6015 pos_mode
= word_mode
;
6017 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
6018 if (extraction_mode
== VOIDmode
)
6019 extraction_mode
= word_mode
;
6024 if (! in_dest
&& unsignedp
)
6026 wanted_inner_reg_mode
6027 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
6028 if (wanted_inner_reg_mode
== VOIDmode
)
6029 wanted_inner_reg_mode
= word_mode
;
6031 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
6032 if (pos_mode
== VOIDmode
)
6033 pos_mode
= word_mode
;
6035 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
6036 if (extraction_mode
== VOIDmode
)
6037 extraction_mode
= word_mode
;
6042 if (! in_dest
&& ! unsignedp
)
6044 wanted_inner_reg_mode
6045 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
6046 if (wanted_inner_reg_mode
== VOIDmode
)
6047 wanted_inner_reg_mode
= word_mode
;
6049 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
6050 if (pos_mode
== VOIDmode
)
6051 pos_mode
= word_mode
;
6053 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
6054 if (extraction_mode
== VOIDmode
)
6055 extraction_mode
= word_mode
;
6059 /* Never narrow an object, since that might not be safe. */
6061 if (mode
!= VOIDmode
6062 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6063 extraction_mode
= mode
;
6065 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6066 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6067 pos_mode
= GET_MODE (pos_rtx
);
6069 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6070 if we have to change the mode of memory and cannot, the desired mode is
6072 if (GET_CODE (inner
) != MEM
)
6073 wanted_inner_mode
= wanted_inner_reg_mode
;
6074 else if (inner_mode
!= wanted_inner_mode
6075 && (mode_dependent_address_p (XEXP (inner
, 0))
6076 || MEM_VOLATILE_P (inner
)))
6077 wanted_inner_mode
= extraction_mode
;
6081 if (BITS_BIG_ENDIAN
)
6083 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6084 BITS_BIG_ENDIAN style. If position is constant, compute new
6085 position. Otherwise, build subtraction.
6086 Note that POS is relative to the mode of the original argument.
6087 If it's a MEM we need to recompute POS relative to that.
6088 However, if we're extracting from (or inserting into) a register,
6089 we want to recompute POS relative to wanted_inner_mode. */
6090 int width
= (GET_CODE (inner
) == MEM
6091 ? GET_MODE_BITSIZE (is_mode
)
6092 : GET_MODE_BITSIZE (wanted_inner_mode
));
6095 pos
= width
- len
- pos
;
6098 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6099 /* POS may be less than 0 now, but we check for that below.
6100 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6103 /* If INNER has a wider mode, make it smaller. If this is a constant
6104 extract, try to adjust the byte to point to the byte containing
6106 if (wanted_inner_mode
!= VOIDmode
6107 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6108 && ((GET_CODE (inner
) == MEM
6109 && (inner_mode
== wanted_inner_mode
6110 || (! mode_dependent_address_p (XEXP (inner
, 0))
6111 && ! MEM_VOLATILE_P (inner
))))))
6115 /* The computations below will be correct if the machine is big
6116 endian in both bits and bytes or little endian in bits and bytes.
6117 If it is mixed, we must adjust. */
6119 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6120 adjust OFFSET to compensate. */
6121 if (BYTES_BIG_ENDIAN
6123 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6124 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6126 /* If this is a constant position, we can move to the desired byte. */
6129 offset
+= pos
/ BITS_PER_UNIT
;
6130 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6133 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6135 && is_mode
!= wanted_inner_mode
)
6136 offset
= (GET_MODE_SIZE (is_mode
)
6137 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6139 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6140 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6143 /* If INNER is not memory, we can always get it into the proper mode. If we
6144 are changing its mode, POS must be a constant and smaller than the size
6146 else if (GET_CODE (inner
) != MEM
)
6148 if (GET_MODE (inner
) != wanted_inner_mode
6150 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6153 inner
= force_to_mode (inner
, wanted_inner_mode
,
6155 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6156 ? ~(unsigned HOST_WIDE_INT
) 0
6157 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6162 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6163 have to zero extend. Otherwise, we can just use a SUBREG. */
6165 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6167 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6169 /* If we know that no extraneous bits are set, and that the high
6170 bit is not set, convert extraction to cheaper one - eighter
6171 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6173 if (flag_expensive_optimizations
6174 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6175 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6176 & ~(((unsigned HOST_WIDE_INT
)
6177 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6181 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6183 /* Prefer ZERO_EXTENSION, since it gives more information to
6185 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6190 else if (pos_rtx
!= 0
6191 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6192 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6194 /* Make POS_RTX unless we already have it and it is correct. If we don't
6195 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6197 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6198 pos_rtx
= orig_pos_rtx
;
6200 else if (pos_rtx
== 0)
6201 pos_rtx
= GEN_INT (pos
);
6203 /* Make the required operation. See if we can use existing rtx. */
6204 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6205 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6207 new = gen_lowpart_for_combine (mode
, new);
6212 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6213 with any other operations in X. Return X without that shift if so. */
6216 extract_left_shift (x
, count
)
6220 enum rtx_code code
= GET_CODE (x
);
6221 enum machine_mode mode
= GET_MODE (x
);
6227 /* This is the shift itself. If it is wide enough, we will return
6228 either the value being shifted if the shift count is equal to
6229 COUNT or a shift for the difference. */
6230 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6231 && INTVAL (XEXP (x
, 1)) >= count
)
6232 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6233 INTVAL (XEXP (x
, 1)) - count
);
6237 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6238 return simplify_gen_unary (code
, mode
, tem
, mode
);
6242 case PLUS
: case IOR
: case XOR
: case AND
:
6243 /* If we can safely shift this constant and we find the inner shift,
6244 make a new operation. */
6245 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6246 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6247 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6248 return gen_binary (code
, mode
, tem
,
6249 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6260 /* Look at the expression rooted at X. Look for expressions
6261 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6262 Form these expressions.
6264 Return the new rtx, usually just X.
6266 Also, for machines like the Vax that don't have logical shift insns,
6267 try to convert logical to arithmetic shift operations in cases where
6268 they are equivalent. This undoes the canonicalizations to logical
6269 shifts done elsewhere.
6271 We try, as much as possible, to re-use rtl expressions to save memory.
6273 IN_CODE says what kind of expression we are processing. Normally, it is
6274 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6275 being kludges), it is MEM. When processing the arguments of a comparison
6276 or a COMPARE against zero, it is COMPARE. */
6279 make_compound_operation (x
, in_code
)
6281 enum rtx_code in_code
;
6283 enum rtx_code code
= GET_CODE (x
);
6284 enum machine_mode mode
= GET_MODE (x
);
6285 int mode_width
= GET_MODE_BITSIZE (mode
);
6287 enum rtx_code next_code
;
6293 /* Select the code to be used in recursive calls. Once we are inside an
6294 address, we stay there. If we have a comparison, set to COMPARE,
6295 but once inside, go back to our default of SET. */
6297 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6298 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6299 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6300 : in_code
== COMPARE
? SET
: in_code
);
6302 /* Process depending on the code of this operation. If NEW is set
6303 non-zero, it will be returned. */
6308 /* Convert shifts by constants into multiplications if inside
6310 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6311 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6312 && INTVAL (XEXP (x
, 1)) >= 0)
6314 new = make_compound_operation (XEXP (x
, 0), next_code
);
6315 new = gen_rtx_MULT (mode
, new,
6316 GEN_INT ((HOST_WIDE_INT
) 1
6317 << INTVAL (XEXP (x
, 1))));
6322 /* If the second operand is not a constant, we can't do anything
6324 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6327 /* If the constant is a power of two minus one and the first operand
6328 is a logical right shift, make an extraction. */
6329 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6330 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6332 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6333 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6334 0, in_code
== COMPARE
);
6337 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6338 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6339 && subreg_lowpart_p (XEXP (x
, 0))
6340 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6341 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6343 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6345 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6346 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6347 0, in_code
== COMPARE
);
6349 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6350 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6351 || GET_CODE (XEXP (x
, 0)) == IOR
)
6352 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6353 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6354 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6356 /* Apply the distributive law, and then try to make extractions. */
6357 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6358 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6360 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6362 new = make_compound_operation (new, in_code
);
6365 /* If we are have (and (rotate X C) M) and C is larger than the number
6366 of bits in M, this is an extraction. */
6368 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6369 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6370 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6371 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6373 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6374 new = make_extraction (mode
, new,
6375 (GET_MODE_BITSIZE (mode
)
6376 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6377 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6380 /* On machines without logical shifts, if the operand of the AND is
6381 a logical shift and our mask turns off all the propagated sign
6382 bits, we can replace the logical shift with an arithmetic shift. */
6383 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6384 && (lshr_optab
->handlers
[(int) mode
].insn_code
6385 == CODE_FOR_nothing
)
6386 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6387 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6388 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6389 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6390 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6392 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6394 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6395 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6397 gen_rtx_ASHIFTRT (mode
,
6398 make_compound_operation
6399 (XEXP (XEXP (x
, 0), 0), next_code
),
6400 XEXP (XEXP (x
, 0), 1)));
6403 /* If the constant is one less than a power of two, this might be
6404 representable by an extraction even if no shift is present.
6405 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6406 we are in a COMPARE. */
6407 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6408 new = make_extraction (mode
,
6409 make_compound_operation (XEXP (x
, 0),
6411 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6413 /* If we are in a comparison and this is an AND with a power of two,
6414 convert this into the appropriate bit extract. */
6415 else if (in_code
== COMPARE
6416 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6417 new = make_extraction (mode
,
6418 make_compound_operation (XEXP (x
, 0),
6420 i
, NULL_RTX
, 1, 1, 0, 1);
6425 /* If the sign bit is known to be zero, replace this with an
6426 arithmetic shift. */
6427 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6428 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6429 && mode_width
<= HOST_BITS_PER_WIDE_INT
6430 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6432 new = gen_rtx_ASHIFTRT (mode
,
6433 make_compound_operation (XEXP (x
, 0),
6439 /* ... fall through ... */
6445 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6446 this is a SIGN_EXTRACT. */
6447 if (GET_CODE (rhs
) == CONST_INT
6448 && GET_CODE (lhs
) == ASHIFT
6449 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6450 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6452 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6453 new = make_extraction (mode
, new,
6454 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6455 NULL_RTX
, mode_width
- INTVAL (rhs
),
6456 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6460 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6461 If so, try to merge the shifts into a SIGN_EXTEND. We could
6462 also do this for some cases of SIGN_EXTRACT, but it doesn't
6463 seem worth the effort; the case checked for occurs on Alpha. */
6465 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6466 && ! (GET_CODE (lhs
) == SUBREG
6467 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6468 && GET_CODE (rhs
) == CONST_INT
6469 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6470 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6471 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6472 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6473 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6478 /* Call ourselves recursively on the inner expression. If we are
6479 narrowing the object and it has a different RTL code from
6480 what it originally did, do this SUBREG as a force_to_mode. */
6482 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6483 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6484 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6485 && subreg_lowpart_p (x
))
6487 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6490 /* If we have something other than a SUBREG, we might have
6491 done an expansion, so rerun outselves. */
6492 if (GET_CODE (newer
) != SUBREG
)
6493 newer
= make_compound_operation (newer
, in_code
);
6498 /* If this is a paradoxical subreg, and the new code is a sign or
6499 zero extension, omit the subreg and widen the extension. If it
6500 is a regular subreg, we can still get rid of the subreg by not
6501 widening so much, or in fact removing the extension entirely. */
6502 if ((GET_CODE (tem
) == SIGN_EXTEND
6503 || GET_CODE (tem
) == ZERO_EXTEND
)
6504 && subreg_lowpart_p (x
))
6506 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6507 || (GET_MODE_SIZE (mode
) >
6508 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6509 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6511 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6522 x
= gen_lowpart_for_combine (mode
, new);
6523 code
= GET_CODE (x
);
6526 /* Now recursively process each operand of this operation. */
6527 fmt
= GET_RTX_FORMAT (code
);
6528 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6531 new = make_compound_operation (XEXP (x
, i
), next_code
);
6532 SUBST (XEXP (x
, i
), new);
6538 /* Given M see if it is a value that would select a field of bits
6539 within an item, but not the entire word. Return -1 if not.
6540 Otherwise, return the starting position of the field, where 0 is the
6543 *PLEN is set to the length of the field. */
6546 get_pos_from_mask (m
, plen
)
6547 unsigned HOST_WIDE_INT m
;
6548 unsigned HOST_WIDE_INT
*plen
;
6550 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6551 int pos
= exact_log2 (m
& -m
);
6557 /* Now shift off the low-order zero bits and see if we have a power of
6559 len
= exact_log2 ((m
>> pos
) + 1);
6568 /* See if X can be simplified knowing that we will only refer to it in
6569 MODE and will only refer to those bits that are nonzero in MASK.
6570 If other bits are being computed or if masking operations are done
6571 that select a superset of the bits in MASK, they can sometimes be
6574 Return a possibly simplified expression, but always convert X to
6575 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6577 Also, if REG is non-zero and X is a register equal in value to REG,
6580 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6581 are all off in X. This is used when X will be complemented, by either
6582 NOT, NEG, or XOR. */
6585 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6587 enum machine_mode mode
;
6588 unsigned HOST_WIDE_INT mask
;
6592 enum rtx_code code
= GET_CODE (x
);
6593 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6594 enum machine_mode op_mode
;
6595 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6598 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6599 code below will do the wrong thing since the mode of such an
6600 expression is VOIDmode.
6602 Also do nothing if X is a CLOBBER; this can happen if X was
6603 the return value from a call to gen_lowpart_for_combine. */
6604 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6607 /* We want to perform the operation is its present mode unless we know
6608 that the operation is valid in MODE, in which case we do the operation
6610 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6611 && code_to_optab
[(int) code
] != 0
6612 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6613 != CODE_FOR_nothing
))
6614 ? mode
: GET_MODE (x
));
6616 /* It is not valid to do a right-shift in a narrower mode
6617 than the one it came in with. */
6618 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6619 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6620 op_mode
= GET_MODE (x
);
6622 /* Truncate MASK to fit OP_MODE. */
6624 mask
&= GET_MODE_MASK (op_mode
);
6626 /* When we have an arithmetic operation, or a shift whose count we
6627 do not know, we need to assume that all bit the up to the highest-order
6628 bit in MASK will be needed. This is how we form such a mask. */
6630 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6631 ? GET_MODE_MASK (op_mode
)
6632 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6635 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6637 /* Determine what bits of X are guaranteed to be (non)zero. */
6638 nonzero
= nonzero_bits (x
, mode
);
6640 /* If none of the bits in X are needed, return a zero. */
6641 if (! just_select
&& (nonzero
& mask
) == 0)
6644 /* If X is a CONST_INT, return a new one. Do this here since the
6645 test below will fail. */
6646 if (GET_CODE (x
) == CONST_INT
)
6648 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6649 int width
= GET_MODE_BITSIZE (mode
);
6651 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6652 number, sign extend it. */
6653 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6654 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6655 cval
|= (HOST_WIDE_INT
) -1 << width
;
6657 return GEN_INT (cval
);
6660 /* If X is narrower than MODE and we want all the bits in X's mode, just
6661 get X in the proper mode. */
6662 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6663 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6664 return gen_lowpart_for_combine (mode
, x
);
6666 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6667 MASK are already known to be zero in X, we need not do anything. */
6668 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6674 /* If X is a (clobber (const_int)), return it since we know we are
6675 generating something that won't match. */
6679 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6680 spanned the boundary of the MEM. If we are now masking so it is
6681 within that boundary, we don't need the USE any more. */
6682 if (! BITS_BIG_ENDIAN
6683 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6684 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6691 x
= expand_compound_operation (x
);
6692 if (GET_CODE (x
) != code
)
6693 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6697 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6698 || rtx_equal_p (reg
, get_last_value (x
))))
6703 if (subreg_lowpart_p (x
)
6704 /* We can ignore the effect of this SUBREG if it narrows the mode or
6705 if the constant masks to zero all the bits the mode doesn't
6707 && ((GET_MODE_SIZE (GET_MODE (x
))
6708 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6710 & GET_MODE_MASK (GET_MODE (x
))
6711 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6712 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6716 /* If this is an AND with a constant, convert it into an AND
6717 whose constant is the AND of that constant with MASK. If it
6718 remains an AND of MASK, delete it since it is redundant. */
6720 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6722 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6723 mask
& INTVAL (XEXP (x
, 1)));
6725 /* If X is still an AND, see if it is an AND with a mask that
6726 is just some low-order bits. If so, and it is MASK, we don't
6729 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6730 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6733 /* If it remains an AND, try making another AND with the bits
6734 in the mode mask that aren't in MASK turned on. If the
6735 constant in the AND is wide enough, this might make a
6736 cheaper constant. */
6738 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6739 && GET_MODE_MASK (GET_MODE (x
)) != mask
6740 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6742 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6743 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6744 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6747 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6748 number, sign extend it. */
6749 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6750 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6751 cval
|= (HOST_WIDE_INT
) -1 << width
;
6753 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6754 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6764 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6765 low-order bits (as in an alignment operation) and FOO is already
6766 aligned to that boundary, mask C1 to that boundary as well.
6767 This may eliminate that PLUS and, later, the AND. */
6770 unsigned int width
= GET_MODE_BITSIZE (mode
);
6771 unsigned HOST_WIDE_INT smask
= mask
;
6773 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6774 number, sign extend it. */
6776 if (width
< HOST_BITS_PER_WIDE_INT
6777 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6778 smask
|= (HOST_WIDE_INT
) -1 << width
;
6780 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6781 && exact_log2 (- smask
) >= 0)
6785 && (XEXP (x
, 0) == stack_pointer_rtx
6786 || XEXP (x
, 0) == frame_pointer_rtx
))
6788 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6789 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6791 sp_mask
&= ~(sp_alignment
- 1);
6792 if ((sp_mask
& ~smask
) == 0
6793 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~smask
) != 0)
6794 return force_to_mode (plus_constant (XEXP (x
, 0),
6795 ((INTVAL (XEXP (x
, 1)) -
6796 STACK_BIAS
) & smask
)
6798 mode
, smask
, reg
, next_select
);
6801 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6802 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6803 return force_to_mode (plus_constant (XEXP (x
, 0),
6804 (INTVAL (XEXP (x
, 1))
6806 mode
, smask
, reg
, next_select
);
6810 /* ... fall through ... */
6813 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6814 most significant bit in MASK since carries from those bits will
6815 affect the bits we are interested in. */
6820 /* If X is (minus C Y) where C's least set bit is larger than any bit
6821 in the mask, then we may replace with (neg Y). */
6822 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6823 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6824 & -INTVAL (XEXP (x
, 0))))
6827 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6829 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6832 /* Similarly, if C contains every bit in the mask, then we may
6833 replace with (not Y). */
6834 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6835 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6836 == INTVAL (XEXP (x
, 0))))
6838 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6839 XEXP (x
, 1), GET_MODE (x
));
6840 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6848 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6849 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6850 operation which may be a bitfield extraction. Ensure that the
6851 constant we form is not wider than the mode of X. */
6853 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6854 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6855 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6856 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6857 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6858 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6859 + floor_log2 (INTVAL (XEXP (x
, 1))))
6860 < GET_MODE_BITSIZE (GET_MODE (x
)))
6861 && (INTVAL (XEXP (x
, 1))
6862 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6864 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6865 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6866 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6867 XEXP (XEXP (x
, 0), 0), temp
);
6868 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6869 XEXP (XEXP (x
, 0), 1));
6870 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6874 /* For most binary operations, just propagate into the operation and
6875 change the mode if we have an operation of that mode. */
6877 op0
= gen_lowpart_for_combine (op_mode
,
6878 force_to_mode (XEXP (x
, 0), mode
, mask
,
6880 op1
= gen_lowpart_for_combine (op_mode
,
6881 force_to_mode (XEXP (x
, 1), mode
, mask
,
6884 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6885 MASK since OP1 might have been sign-extended but we never want
6886 to turn on extra bits, since combine might have previously relied
6887 on them being off. */
6888 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6889 && (INTVAL (op1
) & mask
) != 0)
6890 op1
= GEN_INT (INTVAL (op1
) & mask
);
6892 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6893 x
= gen_binary (code
, op_mode
, op0
, op1
);
6897 /* For left shifts, do the same, but just for the first operand.
6898 However, we cannot do anything with shifts where we cannot
6899 guarantee that the counts are smaller than the size of the mode
6900 because such a count will have a different meaning in a
6903 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6904 && INTVAL (XEXP (x
, 1)) >= 0
6905 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6906 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6907 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6908 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6911 /* If the shift count is a constant and we can do arithmetic in
6912 the mode of the shift, refine which bits we need. Otherwise, use the
6913 conservative form of the mask. */
6914 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6915 && INTVAL (XEXP (x
, 1)) >= 0
6916 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6917 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6918 mask
>>= INTVAL (XEXP (x
, 1));
6922 op0
= gen_lowpart_for_combine (op_mode
,
6923 force_to_mode (XEXP (x
, 0), op_mode
,
6924 mask
, reg
, next_select
));
6926 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6927 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6931 /* Here we can only do something if the shift count is a constant,
6932 this shift constant is valid for the host, and we can do arithmetic
6935 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6936 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6937 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6939 rtx inner
= XEXP (x
, 0);
6940 unsigned HOST_WIDE_INT inner_mask
;
6942 /* Select the mask of the bits we need for the shift operand. */
6943 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
6945 /* We can only change the mode of the shift if we can do arithmetic
6946 in the mode of the shift and INNER_MASK is no wider than the
6947 width of OP_MODE. */
6948 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
6949 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
6950 op_mode
= GET_MODE (x
);
6952 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
6954 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
6955 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
6958 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6959 shift and AND produces only copies of the sign bit (C2 is one less
6960 than a power of two), we can do this with just a shift. */
6962 if (GET_CODE (x
) == LSHIFTRT
6963 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6964 /* The shift puts one of the sign bit copies in the least significant
6966 && ((INTVAL (XEXP (x
, 1))
6967 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
6968 >= GET_MODE_BITSIZE (GET_MODE (x
)))
6969 && exact_log2 (mask
+ 1) >= 0
6970 /* Number of bits left after the shift must be more than the mask
6972 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
6973 <= GET_MODE_BITSIZE (GET_MODE (x
)))
6974 /* Must be more sign bit copies than the mask needs. */
6975 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6976 >= exact_log2 (mask
+ 1)))
6977 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6978 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
6979 - exact_log2 (mask
+ 1)));
6984 /* If we are just looking for the sign bit, we don't need this shift at
6985 all, even if it has a variable count. */
6986 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6987 && (mask
== ((unsigned HOST_WIDE_INT
) 1
6988 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6989 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6991 /* If this is a shift by a constant, get a mask that contains those bits
6992 that are not copies of the sign bit. We then have two cases: If
6993 MASK only includes those bits, this can be a logical shift, which may
6994 allow simplifications. If MASK is a single-bit field not within
6995 those bits, we are requesting a copy of the sign bit and hence can
6996 shift the sign bit to the appropriate location. */
6998 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
6999 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7003 /* If the considered data is wider then HOST_WIDE_INT, we can't
7004 represent a mask for all its bits in a single scalar.
7005 But we only care about the lower bits, so calculate these. */
7007 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7009 nonzero
= ~(HOST_WIDE_INT
) 0;
7011 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7012 is the number of bits a full-width mask would have set.
7013 We need only shift if these are fewer than nonzero can
7014 hold. If not, we must keep all bits set in nonzero. */
7016 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7017 < HOST_BITS_PER_WIDE_INT
)
7018 nonzero
>>= INTVAL (XEXP (x
, 1))
7019 + HOST_BITS_PER_WIDE_INT
7020 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7024 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7025 nonzero
>>= INTVAL (XEXP (x
, 1));
7028 if ((mask
& ~nonzero
) == 0
7029 || (i
= exact_log2 (mask
)) >= 0)
7031 x
= simplify_shift_const
7032 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7033 i
< 0 ? INTVAL (XEXP (x
, 1))
7034 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7036 if (GET_CODE (x
) != ASHIFTRT
)
7037 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7041 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7042 even if the shift count isn't a constant. */
7044 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7048 /* If this is a zero- or sign-extension operation that just affects bits
7049 we don't care about, remove it. Be sure the call above returned
7050 something that is still a shift. */
7052 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7053 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7054 && INTVAL (XEXP (x
, 1)) >= 0
7055 && (INTVAL (XEXP (x
, 1))
7056 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7057 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7058 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7059 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7060 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7067 /* If the shift count is constant and we can do computations
7068 in the mode of X, compute where the bits we care about are.
7069 Otherwise, we can't do anything. Don't change the mode of
7070 the shift or propagate MODE into the shift, though. */
7071 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7072 && INTVAL (XEXP (x
, 1)) >= 0)
7074 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7075 GET_MODE (x
), GEN_INT (mask
),
7077 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7079 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7080 INTVAL (temp
), reg
, next_select
));
7085 /* If we just want the low-order bit, the NEG isn't needed since it
7086 won't change the low-order bit. */
7088 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7090 /* We need any bits less significant than the most significant bit in
7091 MASK since carries from those bits will affect the bits we are
7097 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7098 same as the XOR case above. Ensure that the constant we form is not
7099 wider than the mode of X. */
7101 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7102 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7103 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7104 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7105 < GET_MODE_BITSIZE (GET_MODE (x
)))
7106 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7108 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7109 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7110 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7112 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7115 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7116 use the full mask inside the NOT. */
7120 op0
= gen_lowpart_for_combine (op_mode
,
7121 force_to_mode (XEXP (x
, 0), mode
, mask
,
7123 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7124 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7128 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7129 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7130 which is equal to STORE_FLAG_VALUE. */
7131 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7132 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7133 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7134 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7139 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7140 written in a narrower mode. We play it safe and do not do so. */
7143 gen_lowpart_for_combine (GET_MODE (x
),
7144 force_to_mode (XEXP (x
, 1), mode
,
7145 mask
, reg
, next_select
)));
7147 gen_lowpart_for_combine (GET_MODE (x
),
7148 force_to_mode (XEXP (x
, 2), mode
,
7149 mask
, reg
,next_select
)));
7156 /* Ensure we return a value of the proper mode. */
7157 return gen_lowpart_for_combine (mode
, x
);
7160 /* Return nonzero if X is an expression that has one of two values depending on
7161 whether some other value is zero or nonzero. In that case, we return the
7162 value that is being tested, *PTRUE is set to the value if the rtx being
7163 returned has a nonzero value, and *PFALSE is set to the other alternative.
7165 If we return zero, we set *PTRUE and *PFALSE to X. */
7168 if_then_else_cond (x
, ptrue
, pfalse
)
7170 rtx
*ptrue
, *pfalse
;
7172 enum machine_mode mode
= GET_MODE (x
);
7173 enum rtx_code code
= GET_CODE (x
);
7174 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7175 unsigned HOST_WIDE_INT nz
;
7177 /* If we are comparing a value against zero, we are done. */
7178 if ((code
== NE
|| code
== EQ
)
7179 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7181 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7182 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7186 /* If this is a unary operation whose operand has one of two values, apply
7187 our opcode to compute those values. */
7188 else if (GET_RTX_CLASS (code
) == '1'
7189 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7191 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7192 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7193 GET_MODE (XEXP (x
, 0)));
7197 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7198 make can't possibly match and would suppress other optimizations. */
7199 else if (code
== COMPARE
)
7202 /* If this is a binary operation, see if either side has only one of two
7203 values. If either one does or if both do and they are conditional on
7204 the same value, compute the new true and false values. */
7205 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7206 || GET_RTX_CLASS (code
) == '<')
7208 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7209 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7211 if ((cond0
!= 0 || cond1
!= 0)
7212 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7214 /* If if_then_else_cond returned zero, then true/false are the
7215 same rtl. We must copy one of them to prevent invalid rtl
7218 true0
= copy_rtx (true0
);
7219 else if (cond1
== 0)
7220 true1
= copy_rtx (true1
);
7222 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7223 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7224 return cond0
? cond0
: cond1
;
7227 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7228 operands is zero when the other is non-zero, and vice-versa,
7229 and STORE_FLAG_VALUE is 1 or -1. */
7231 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7232 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7234 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7236 rtx op0
= XEXP (XEXP (x
, 0), 1);
7237 rtx op1
= XEXP (XEXP (x
, 1), 1);
7239 cond0
= XEXP (XEXP (x
, 0), 0);
7240 cond1
= XEXP (XEXP (x
, 1), 0);
7242 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7243 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7244 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7245 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7246 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7247 || ((swap_condition (GET_CODE (cond0
))
7248 == combine_reversed_comparison_code (cond1
))
7249 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7250 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7251 && ! side_effects_p (x
))
7253 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7254 *pfalse
= gen_binary (MULT
, mode
,
7256 ? simplify_gen_unary (NEG
, mode
, op1
,
7264 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7266 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7267 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7268 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7270 cond0
= XEXP (XEXP (x
, 0), 0);
7271 cond1
= XEXP (XEXP (x
, 1), 0);
7273 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7274 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7275 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7276 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7277 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7278 || ((swap_condition (GET_CODE (cond0
))
7279 == combine_reversed_comparison_code (cond1
))
7280 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7281 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7282 && ! side_effects_p (x
))
7284 *ptrue
= *pfalse
= const0_rtx
;
7290 else if (code
== IF_THEN_ELSE
)
7292 /* If we have IF_THEN_ELSE already, extract the condition and
7293 canonicalize it if it is NE or EQ. */
7294 cond0
= XEXP (x
, 0);
7295 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7296 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7297 return XEXP (cond0
, 0);
7298 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7300 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7301 return XEXP (cond0
, 0);
7307 /* If X is a SUBREG, we can narrow both the true and false values
7308 if the inner expression, if there is a condition. */
7309 else if (code
== SUBREG
7310 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7313 *ptrue
= simplify_gen_subreg (mode
, true0
,
7314 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7315 *pfalse
= simplify_gen_subreg (mode
, false0
,
7316 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7321 /* If X is a constant, this isn't special and will cause confusions
7322 if we treat it as such. Likewise if it is equivalent to a constant. */
7323 else if (CONSTANT_P (x
)
7324 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7327 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7328 will be least confusing to the rest of the compiler. */
7329 else if (mode
== BImode
)
7331 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7335 /* If X is known to be either 0 or -1, those are the true and
7336 false values when testing X. */
7337 else if (x
== constm1_rtx
|| x
== const0_rtx
7338 || (mode
!= VOIDmode
7339 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7341 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7345 /* Likewise for 0 or a single bit. */
7346 else if (mode
!= VOIDmode
7347 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7348 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7350 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7354 /* Otherwise fail; show no condition with true and false values the same. */
7355 *ptrue
= *pfalse
= x
;
7359 /* Return the value of expression X given the fact that condition COND
7360 is known to be true when applied to REG as its first operand and VAL
7361 as its second. X is known to not be shared and so can be modified in
7364 We only handle the simplest cases, and specifically those cases that
7365 arise with IF_THEN_ELSE expressions. */
7368 known_cond (x
, cond
, reg
, val
)
7373 enum rtx_code code
= GET_CODE (x
);
7378 if (side_effects_p (x
))
7381 if (cond
== EQ
&& rtx_equal_p (x
, reg
) && !FLOAT_MODE_P (cond
))
7383 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7386 /* If X is (abs REG) and we know something about REG's relationship
7387 with zero, we may be able to simplify this. */
7389 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7392 case GE
: case GT
: case EQ
:
7395 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7397 GET_MODE (XEXP (x
, 0)));
7402 /* The only other cases we handle are MIN, MAX, and comparisons if the
7403 operands are the same as REG and VAL. */
7405 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7407 if (rtx_equal_p (XEXP (x
, 0), val
))
7408 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7410 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7412 if (GET_RTX_CLASS (code
) == '<')
7414 if (comparison_dominates_p (cond
, code
))
7415 return const_true_rtx
;
7417 code
= combine_reversed_comparison_code (x
);
7419 && comparison_dominates_p (cond
, code
))
7424 else if (code
== SMAX
|| code
== SMIN
7425 || code
== UMIN
|| code
== UMAX
)
7427 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7429 /* Do not reverse the condition when it is NE or EQ.
7430 This is because we cannot conclude anything about
7431 the value of 'SMAX (x, y)' when x is not equal to y,
7432 but we can when x equals y. */
7433 if ((code
== SMAX
|| code
== UMAX
)
7434 && ! (cond
== EQ
|| cond
== NE
))
7435 cond
= reverse_condition (cond
);
7440 return unsignedp
? x
: XEXP (x
, 1);
7442 return unsignedp
? x
: XEXP (x
, 0);
7444 return unsignedp
? XEXP (x
, 1) : x
;
7446 return unsignedp
? XEXP (x
, 0) : x
;
7454 fmt
= GET_RTX_FORMAT (code
);
7455 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7458 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7459 else if (fmt
[i
] == 'E')
7460 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7461 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7468 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7469 assignment as a field assignment. */
7472 rtx_equal_for_field_assignment_p (x
, y
)
7476 if (x
== y
|| rtx_equal_p (x
, y
))
7479 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7482 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7483 Note that all SUBREGs of MEM are paradoxical; otherwise they
7484 would have been rewritten. */
7485 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7486 && GET_CODE (SUBREG_REG (y
)) == MEM
7487 && rtx_equal_p (SUBREG_REG (y
),
7488 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7491 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7492 && GET_CODE (SUBREG_REG (x
)) == MEM
7493 && rtx_equal_p (SUBREG_REG (x
),
7494 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7497 /* We used to see if get_last_value of X and Y were the same but that's
7498 not correct. In one direction, we'll cause the assignment to have
7499 the wrong destination and in the case, we'll import a register into this
7500 insn that might have already have been dead. So fail if none of the
7501 above cases are true. */
7505 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7506 Return that assignment if so.
7508 We only handle the most common cases. */
7511 make_field_assignment (x
)
7514 rtx dest
= SET_DEST (x
);
7515 rtx src
= SET_SRC (x
);
7520 unsigned HOST_WIDE_INT len
;
7522 enum machine_mode mode
;
7524 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7525 a clear of a one-bit field. We will have changed it to
7526 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7529 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7530 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7531 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7532 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7534 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7537 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7541 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7542 && subreg_lowpart_p (XEXP (src
, 0))
7543 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7544 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7545 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7546 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7547 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7549 assign
= make_extraction (VOIDmode
, dest
, 0,
7550 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7553 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7557 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7559 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7560 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7561 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7563 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7566 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7570 /* The other case we handle is assignments into a constant-position
7571 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7572 a mask that has all one bits except for a group of zero bits and
7573 OTHER is known to have zeros where C1 has ones, this is such an
7574 assignment. Compute the position and length from C1. Shift OTHER
7575 to the appropriate position, force it to the required mode, and
7576 make the extraction. Check for the AND in both operands. */
7578 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7581 rhs
= expand_compound_operation (XEXP (src
, 0));
7582 lhs
= expand_compound_operation (XEXP (src
, 1));
7584 if (GET_CODE (rhs
) == AND
7585 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7586 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7587 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7588 else if (GET_CODE (lhs
) == AND
7589 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7590 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7591 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7595 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7596 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7597 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7598 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7601 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7605 /* The mode to use for the source is the mode of the assignment, or of
7606 what is inside a possible STRICT_LOW_PART. */
7607 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7608 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7610 /* Shift OTHER right POS places and make it the source, restricting it
7611 to the proper length and mode. */
7613 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7614 GET_MODE (src
), other
, pos
),
7616 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7617 ? ~(unsigned HOST_WIDE_INT
) 0
7618 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7621 return gen_rtx_SET (VOIDmode
, assign
, src
);
7624 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7628 apply_distributive_law (x
)
7631 enum rtx_code code
= GET_CODE (x
);
7632 rtx lhs
, rhs
, other
;
7634 enum rtx_code inner_code
;
7636 /* Distributivity is not true for floating point.
7637 It can change the value. So don't do it.
7638 -- rms and moshier@world.std.com. */
7639 if (FLOAT_MODE_P (GET_MODE (x
)))
7642 /* The outer operation can only be one of the following: */
7643 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7644 && code
!= PLUS
&& code
!= MINUS
)
7647 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7649 /* If either operand is a primitive we can't do anything, so get out
7651 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7652 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7655 lhs
= expand_compound_operation (lhs
);
7656 rhs
= expand_compound_operation (rhs
);
7657 inner_code
= GET_CODE (lhs
);
7658 if (inner_code
!= GET_CODE (rhs
))
7661 /* See if the inner and outer operations distribute. */
7668 /* These all distribute except over PLUS. */
7669 if (code
== PLUS
|| code
== MINUS
)
7674 if (code
!= PLUS
&& code
!= MINUS
)
7679 /* This is also a multiply, so it distributes over everything. */
7683 /* Non-paradoxical SUBREGs distributes over all operations, provided
7684 the inner modes and byte offsets are the same, this is an extraction
7685 of a low-order part, we don't convert an fp operation to int or
7686 vice versa, and we would not be converting a single-word
7687 operation into a multi-word operation. The latter test is not
7688 required, but it prevents generating unneeded multi-word operations.
7689 Some of the previous tests are redundant given the latter test, but
7690 are retained because they are required for correctness.
7692 We produce the result slightly differently in this case. */
7694 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7695 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7696 || ! subreg_lowpart_p (lhs
)
7697 || (GET_MODE_CLASS (GET_MODE (lhs
))
7698 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7699 || (GET_MODE_SIZE (GET_MODE (lhs
))
7700 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7701 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7704 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7705 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7706 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7712 /* Set LHS and RHS to the inner operands (A and B in the example
7713 above) and set OTHER to the common operand (C in the example).
7714 These is only one way to do this unless the inner operation is
7716 if (GET_RTX_CLASS (inner_code
) == 'c'
7717 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7718 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7719 else if (GET_RTX_CLASS (inner_code
) == 'c'
7720 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7721 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7722 else if (GET_RTX_CLASS (inner_code
) == 'c'
7723 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7724 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7725 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7726 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7730 /* Form the new inner operation, seeing if it simplifies first. */
7731 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7733 /* There is one exception to the general way of distributing:
7734 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7735 if (code
== XOR
&& inner_code
== IOR
)
7738 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7741 /* We may be able to continuing distributing the result, so call
7742 ourselves recursively on the inner operation before forming the
7743 outer operation, which we return. */
7744 return gen_binary (inner_code
, GET_MODE (x
),
7745 apply_distributive_law (tem
), other
);
7748 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7751 Return an equivalent form, if different from X. Otherwise, return X. If
7752 X is zero, we are to always construct the equivalent form. */
7755 simplify_and_const_int (x
, mode
, varop
, constop
)
7757 enum machine_mode mode
;
7759 unsigned HOST_WIDE_INT constop
;
7761 unsigned HOST_WIDE_INT nonzero
;
7764 /* Simplify VAROP knowing that we will be only looking at some of the
7766 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7768 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7769 CONST_INT, we are done. */
7770 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7773 /* See what bits may be nonzero in VAROP. Unlike the general case of
7774 a call to nonzero_bits, here we don't care about bits outside
7777 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7778 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7780 /* Turn off all bits in the constant that are known to already be zero.
7781 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7782 which is tested below. */
7786 /* If we don't have any bits left, return zero. */
7790 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7791 a power of two, we can replace this with a ASHIFT. */
7792 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7793 && (i
= exact_log2 (constop
)) >= 0)
7794 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7796 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7797 or XOR, then try to apply the distributive law. This may eliminate
7798 operations if either branch can be simplified because of the AND.
7799 It may also make some cases more complex, but those cases probably
7800 won't match a pattern either with or without this. */
7802 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7804 gen_lowpart_for_combine
7806 apply_distributive_law
7807 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7808 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7809 XEXP (varop
, 0), constop
),
7810 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7811 XEXP (varop
, 1), constop
))));
7813 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7814 if we already had one (just check for the simplest cases). */
7815 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7816 && GET_MODE (XEXP (x
, 0)) == mode
7817 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7818 varop
= XEXP (x
, 0);
7820 varop
= gen_lowpart_for_combine (mode
, varop
);
7822 /* If we can't make the SUBREG, try to return what we were given. */
7823 if (GET_CODE (varop
) == CLOBBER
)
7824 return x
? x
: varop
;
7826 /* If we are only masking insignificant bits, return VAROP. */
7827 if (constop
== nonzero
)
7830 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7831 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7832 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7836 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7837 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7838 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7840 SUBST (XEXP (x
, 0), varop
);
7846 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7847 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7848 is less useful. We can't allow both, because that results in exponential
7849 run time recursion. There is a nullstone testcase that triggered
7850 this. This macro avoids accidental uses of num_sign_bit_copies. */
7851 #define num_sign_bit_copies()
7853 /* Given an expression, X, compute which bits in X can be non-zero.
7854 We don't care about bits outside of those defined in MODE.
7856 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7857 a shift, AND, or zero_extract, we can do better. */
7859 static unsigned HOST_WIDE_INT
7860 nonzero_bits (x
, mode
)
7862 enum machine_mode mode
;
7864 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7865 unsigned HOST_WIDE_INT inner_nz
;
7867 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
7870 /* For floating-point values, assume all bits are needed. */
7871 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7874 /* If X is wider than MODE, use its mode instead. */
7875 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7877 mode
= GET_MODE (x
);
7878 nonzero
= GET_MODE_MASK (mode
);
7879 mode_width
= GET_MODE_BITSIZE (mode
);
7882 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7883 /* Our only callers in this case look for single bit values. So
7884 just return the mode mask. Those tests will then be false. */
7887 #ifndef WORD_REGISTER_OPERATIONS
7888 /* If MODE is wider than X, but both are a single word for both the host
7889 and target machines, we can compute this from which bits of the
7890 object might be nonzero in its own mode, taking into account the fact
7891 that on many CISC machines, accessing an object in a wider mode
7892 causes the high-order bits to become undefined. So they are
7893 not known to be zero. */
7895 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
7896 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
7897 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7898 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
7900 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
7901 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
7906 code
= GET_CODE (x
);
7910 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
7911 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7912 all the bits above ptr_mode are known to be zero. */
7913 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
7915 nonzero
&= GET_MODE_MASK (ptr_mode
);
7918 #ifdef STACK_BOUNDARY
7919 /* If this is the stack pointer, we may know something about its
7920 alignment. If PUSH_ROUNDING is defined, it is possible for the
7921 stack to be momentarily aligned only to that amount, so we pick
7922 the least alignment. */
7924 /* We can't check for arg_pointer_rtx here, because it is not
7925 guaranteed to have as much alignment as the stack pointer.
7926 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7927 alignment but the argument pointer has only 64 bit alignment. */
7929 if ((x
== frame_pointer_rtx
7930 || x
== stack_pointer_rtx
7931 || x
== hard_frame_pointer_rtx
7932 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
7933 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
7939 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7941 #ifdef PUSH_ROUNDING
7942 if (REGNO (x
) == STACK_POINTER_REGNUM
&& PUSH_ARGS
)
7943 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
7946 /* We must return here, otherwise we may get a worse result from
7947 one of the choices below. There is nothing useful below as
7948 far as the stack pointer is concerned. */
7949 return nonzero
&= ~(sp_alignment
- 1);
7953 /* If X is a register whose nonzero bits value is current, use it.
7954 Otherwise, if X is a register whose value we can find, use that
7955 value. Otherwise, use the previously-computed global nonzero bits
7956 for this register. */
7958 if (reg_last_set_value
[REGNO (x
)] != 0
7959 && reg_last_set_mode
[REGNO (x
)] == mode
7960 && (reg_last_set_label
[REGNO (x
)] == label_tick
7961 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
7962 && REG_N_SETS (REGNO (x
)) == 1
7963 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
7965 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7966 return reg_last_set_nonzero_bits
[REGNO (x
)];
7968 tem
= get_last_value (x
);
7972 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7973 /* If X is narrower than MODE and TEM is a non-negative
7974 constant that would appear negative in the mode of X,
7975 sign-extend it for use in reg_nonzero_bits because some
7976 machines (maybe most) will actually do the sign-extension
7977 and this is the conservative approach.
7979 ??? For 2.5, try to tighten up the MD files in this regard
7980 instead of this kludge. */
7982 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
7983 && GET_CODE (tem
) == CONST_INT
7985 && 0 != (INTVAL (tem
)
7986 & ((HOST_WIDE_INT
) 1
7987 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7988 tem
= GEN_INT (INTVAL (tem
)
7989 | ((HOST_WIDE_INT
) (-1)
7990 << GET_MODE_BITSIZE (GET_MODE (x
))));
7992 return nonzero_bits (tem
, mode
);
7994 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
7995 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
8000 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8001 /* If X is negative in MODE, sign-extend the value. */
8002 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8003 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8004 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8010 #ifdef LOAD_EXTEND_OP
8011 /* In many, if not most, RISC machines, reading a byte from memory
8012 zeros the rest of the register. Noticing that fact saves a lot
8013 of extra zero-extends. */
8014 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8015 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8020 case UNEQ
: case LTGT
:
8021 case GT
: case GTU
: case UNGT
:
8022 case LT
: case LTU
: case UNLT
:
8023 case GE
: case GEU
: case UNGE
:
8024 case LE
: case LEU
: case UNLE
:
8025 case UNORDERED
: case ORDERED
:
8027 /* If this produces an integer result, we know which bits are set.
8028 Code here used to clear bits outside the mode of X, but that is
8031 if (GET_MODE_CLASS (mode
) == MODE_INT
8032 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8033 nonzero
= STORE_FLAG_VALUE
;
8038 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8039 and num_sign_bit_copies. */
8040 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8041 == GET_MODE_BITSIZE (GET_MODE (x
)))
8045 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8046 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8051 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8052 and num_sign_bit_copies. */
8053 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8054 == GET_MODE_BITSIZE (GET_MODE (x
)))
8060 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8064 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8065 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8066 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8070 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8071 Otherwise, show all the bits in the outer mode but not the inner
8073 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8074 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8076 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8078 & (((HOST_WIDE_INT
) 1
8079 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8080 inner_nz
|= (GET_MODE_MASK (mode
)
8081 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8084 nonzero
&= inner_nz
;
8088 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8089 & nonzero_bits (XEXP (x
, 1), mode
));
8093 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8094 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8095 | nonzero_bits (XEXP (x
, 1), mode
));
8098 case PLUS
: case MINUS
:
8100 case DIV
: case UDIV
:
8101 case MOD
: case UMOD
:
8102 /* We can apply the rules of arithmetic to compute the number of
8103 high- and low-order zero bits of these operations. We start by
8104 computing the width (position of the highest-order non-zero bit)
8105 and the number of low-order zero bits for each value. */
8107 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8108 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8109 int width0
= floor_log2 (nz0
) + 1;
8110 int width1
= floor_log2 (nz1
) + 1;
8111 int low0
= floor_log2 (nz0
& -nz0
);
8112 int low1
= floor_log2 (nz1
& -nz1
);
8113 HOST_WIDE_INT op0_maybe_minusp
8114 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8115 HOST_WIDE_INT op1_maybe_minusp
8116 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8117 unsigned int result_width
= mode_width
;
8125 && (XEXP (x
, 0) == stack_pointer_rtx
8126 || XEXP (x
, 0) == frame_pointer_rtx
)
8127 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8129 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8131 nz0
= (GET_MODE_MASK (mode
) & ~(sp_alignment
- 1));
8132 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8133 width0
= floor_log2 (nz0
) + 1;
8134 width1
= floor_log2 (nz1
) + 1;
8135 low0
= floor_log2 (nz0
& -nz0
);
8136 low1
= floor_log2 (nz1
& -nz1
);
8139 result_width
= MAX (width0
, width1
) + 1;
8140 result_low
= MIN (low0
, low1
);
8143 result_low
= MIN (low0
, low1
);
8146 result_width
= width0
+ width1
;
8147 result_low
= low0
+ low1
;
8152 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8153 result_width
= width0
;
8158 result_width
= width0
;
8163 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8164 result_width
= MIN (width0
, width1
);
8165 result_low
= MIN (low0
, low1
);
8170 result_width
= MIN (width0
, width1
);
8171 result_low
= MIN (low0
, low1
);
8177 if (result_width
< mode_width
)
8178 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8181 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8183 #ifdef POINTERS_EXTEND_UNSIGNED
8184 /* If pointers extend unsigned and this is an addition or subtraction
8185 to a pointer in Pmode, all the bits above ptr_mode are known to be
8187 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8188 && (code
== PLUS
|| code
== MINUS
)
8189 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8190 nonzero
&= GET_MODE_MASK (ptr_mode
);
8196 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8197 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8198 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8202 /* If this is a SUBREG formed for a promoted variable that has
8203 been zero-extended, we know that at least the high-order bits
8204 are zero, though others might be too. */
8206 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8207 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8208 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8210 /* If the inner mode is a single word for both the host and target
8211 machines, we can compute this from which bits of the inner
8212 object might be nonzero. */
8213 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8214 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8215 <= HOST_BITS_PER_WIDE_INT
))
8217 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8219 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8220 /* If this is a typical RISC machine, we only have to worry
8221 about the way loads are extended. */
8222 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8224 & (((unsigned HOST_WIDE_INT
) 1
8225 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8227 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8230 /* On many CISC machines, accessing an object in a wider mode
8231 causes the high-order bits to become undefined. So they are
8232 not known to be zero. */
8233 if (GET_MODE_SIZE (GET_MODE (x
))
8234 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8235 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8236 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8245 /* The nonzero bits are in two classes: any bits within MODE
8246 that aren't in GET_MODE (x) are always significant. The rest of the
8247 nonzero bits are those that are significant in the operand of
8248 the shift when shifted the appropriate number of bits. This
8249 shows that high-order bits are cleared by the right shift and
8250 low-order bits by left shifts. */
8251 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8252 && INTVAL (XEXP (x
, 1)) >= 0
8253 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8255 enum machine_mode inner_mode
= GET_MODE (x
);
8256 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8257 int count
= INTVAL (XEXP (x
, 1));
8258 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8259 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8260 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8261 unsigned HOST_WIDE_INT outer
= 0;
8263 if (mode_width
> width
)
8264 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8266 if (code
== LSHIFTRT
)
8268 else if (code
== ASHIFTRT
)
8272 /* If the sign bit may have been nonzero before the shift, we
8273 need to mark all the places it could have been copied to
8274 by the shift as possibly nonzero. */
8275 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8276 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8278 else if (code
== ASHIFT
)
8281 inner
= ((inner
<< (count
% width
)
8282 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8284 nonzero
&= (outer
| inner
);
8289 /* This is at most the number of bits in the mode. */
8290 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8294 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8295 | nonzero_bits (XEXP (x
, 2), mode
));
8305 /* See the macro definition above. */
8306 #undef num_sign_bit_copies
8308 /* Return the number of bits at the high-order end of X that are known to
8309 be equal to the sign bit. X will be used in mode MODE; if MODE is
8310 VOIDmode, X will be used in its own mode. The returned value will always
8311 be between 1 and the number of bits in MODE. */
8314 num_sign_bit_copies (x
, mode
)
8316 enum machine_mode mode
;
8318 enum rtx_code code
= GET_CODE (x
);
8319 unsigned int bitwidth
;
8320 int num0
, num1
, result
;
8321 unsigned HOST_WIDE_INT nonzero
;
8324 /* If we weren't given a mode, use the mode of X. If the mode is still
8325 VOIDmode, we don't know anything. Likewise if one of the modes is
8328 if (mode
== VOIDmode
)
8329 mode
= GET_MODE (x
);
8331 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8334 bitwidth
= GET_MODE_BITSIZE (mode
);
8336 /* For a smaller object, just ignore the high bits. */
8337 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8339 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8341 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8344 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8346 #ifndef WORD_REGISTER_OPERATIONS
8347 /* If this machine does not do all register operations on the entire
8348 register and MODE is wider than the mode of X, we can say nothing
8349 at all about the high-order bits. */
8352 /* Likewise on machines that do, if the mode of the object is smaller
8353 than a word and loads of that size don't sign extend, we can say
8354 nothing about the high order bits. */
8355 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8356 #ifdef LOAD_EXTEND_OP
8357 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8368 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8369 /* If pointers extend signed and this is a pointer in Pmode, say that
8370 all the bits above ptr_mode are known to be sign bit copies. */
8371 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8373 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8376 if (reg_last_set_value
[REGNO (x
)] != 0
8377 && reg_last_set_mode
[REGNO (x
)] == mode
8378 && (reg_last_set_label
[REGNO (x
)] == label_tick
8379 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8380 && REG_N_SETS (REGNO (x
)) == 1
8381 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8383 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8384 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8386 tem
= get_last_value (x
);
8388 return num_sign_bit_copies (tem
, mode
);
8390 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8391 return reg_sign_bit_copies
[REGNO (x
)];
8395 #ifdef LOAD_EXTEND_OP
8396 /* Some RISC machines sign-extend all loads of smaller than a word. */
8397 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8398 return MAX (1, ((int) bitwidth
8399 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8404 /* If the constant is negative, take its 1's complement and remask.
8405 Then see how many zero bits we have. */
8406 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8407 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8408 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8409 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8411 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8414 /* If this is a SUBREG for a promoted object that is sign-extended
8415 and we are looking at it in a wider mode, we know that at least the
8416 high-order bits are known to be sign bit copies. */
8418 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8420 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8421 return MAX ((int) bitwidth
8422 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8426 /* For a smaller object, just ignore the high bits. */
8427 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8429 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8430 return MAX (1, (num0
8431 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8435 #ifdef WORD_REGISTER_OPERATIONS
8436 #ifdef LOAD_EXTEND_OP
8437 /* For paradoxical SUBREGs on machines where all register operations
8438 affect the entire register, just look inside. Note that we are
8439 passing MODE to the recursive call, so the number of sign bit copies
8440 will remain relative to that mode, not the inner mode. */
8442 /* This works only if loads sign extend. Otherwise, if we get a
8443 reload for the inner part, it may be loaded from the stack, and
8444 then we lose all sign bit copies that existed before the store
8447 if ((GET_MODE_SIZE (GET_MODE (x
))
8448 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8449 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8450 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8456 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8457 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8461 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8462 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8465 /* For a smaller object, just ignore the high bits. */
8466 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8467 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8471 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8473 case ROTATE
: case ROTATERT
:
8474 /* If we are rotating left by a number of bits less than the number
8475 of sign bit copies, we can just subtract that amount from the
8477 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8478 && INTVAL (XEXP (x
, 1)) >= 0
8479 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8481 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8482 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8483 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8488 /* In general, this subtracts one sign bit copy. But if the value
8489 is known to be positive, the number of sign bit copies is the
8490 same as that of the input. Finally, if the input has just one bit
8491 that might be nonzero, all the bits are copies of the sign bit. */
8492 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8493 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8494 return num0
> 1 ? num0
- 1 : 1;
8496 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8501 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8506 case IOR
: case AND
: case XOR
:
8507 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8508 /* Logical operations will preserve the number of sign-bit copies.
8509 MIN and MAX operations always return one of the operands. */
8510 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8511 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8512 return MIN (num0
, num1
);
8514 case PLUS
: case MINUS
:
8515 /* For addition and subtraction, we can have a 1-bit carry. However,
8516 if we are subtracting 1 from a positive number, there will not
8517 be such a carry. Furthermore, if the positive number is known to
8518 be 0 or 1, we know the result is either -1 or 0. */
8520 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8521 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8523 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8524 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8525 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8526 : bitwidth
- floor_log2 (nonzero
) - 1);
8529 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8530 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8531 result
= MAX (1, MIN (num0
, num1
) - 1);
8533 #ifdef POINTERS_EXTEND_UNSIGNED
8534 /* If pointers extend signed and this is an addition or subtraction
8535 to a pointer in Pmode, all the bits above ptr_mode are known to be
8537 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8538 && (code
== PLUS
|| code
== MINUS
)
8539 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8540 result
= MAX ((GET_MODE_BITSIZE (Pmode
)
8541 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8547 /* The number of bits of the product is the sum of the number of
8548 bits of both terms. However, unless one of the terms if known
8549 to be positive, we must allow for an additional bit since negating
8550 a negative number can remove one sign bit copy. */
8552 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8553 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8555 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8557 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8558 || (((nonzero_bits (XEXP (x
, 0), mode
)
8559 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8560 && ((nonzero_bits (XEXP (x
, 1), mode
)
8561 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8564 return MAX (1, result
);
8567 /* The result must be <= the first operand. If the first operand
8568 has the high bit set, we know nothing about the number of sign
8570 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8572 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8573 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8576 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8579 /* The result must be <= the scond operand. */
8580 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8583 /* Similar to unsigned division, except that we have to worry about
8584 the case where the divisor is negative, in which case we have
8586 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8588 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8589 || (nonzero_bits (XEXP (x
, 1), mode
)
8590 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8596 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8598 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8599 || (nonzero_bits (XEXP (x
, 1), mode
)
8600 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8606 /* Shifts by a constant add to the number of bits equal to the
8608 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8609 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8610 && INTVAL (XEXP (x
, 1)) > 0)
8611 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8616 /* Left shifts destroy copies. */
8617 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8618 || INTVAL (XEXP (x
, 1)) < 0
8619 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8622 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8623 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8626 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8627 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8628 return MIN (num0
, num1
);
8630 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8631 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8632 case GEU
: case GTU
: case LEU
: case LTU
:
8633 case UNORDERED
: case ORDERED
:
8634 /* If the constant is negative, take its 1's complement and remask.
8635 Then see how many zero bits we have. */
8636 nonzero
= STORE_FLAG_VALUE
;
8637 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8638 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8639 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8641 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8648 /* If we haven't been able to figure it out by one of the above rules,
8649 see if some of the high-order bits are known to be zero. If so,
8650 count those bits and return one less than that amount. If we can't
8651 safely compute the mask for this mode, always return BITWIDTH. */
8653 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8656 nonzero
= nonzero_bits (x
, mode
);
8657 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8658 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8661 /* Return the number of "extended" bits there are in X, when interpreted
8662 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8663 unsigned quantities, this is the number of high-order zero bits.
8664 For signed quantities, this is the number of copies of the sign bit
8665 minus 1. In both case, this function returns the number of "spare"
8666 bits. For example, if two quantities for which this function returns
8667 at least 1 are added, the addition is known not to overflow.
8669 This function will always return 0 unless called during combine, which
8670 implies that it must be called from a define_split. */
8673 extended_count (x
, mode
, unsignedp
)
8675 enum machine_mode mode
;
8678 if (nonzero_sign_valid
== 0)
8682 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8683 ? (GET_MODE_BITSIZE (mode
) - 1
8684 - floor_log2 (nonzero_bits (x
, mode
)))
8686 : num_sign_bit_copies (x
, mode
) - 1);
8689 /* This function is called from `simplify_shift_const' to merge two
8690 outer operations. Specifically, we have already found that we need
8691 to perform operation *POP0 with constant *PCONST0 at the outermost
8692 position. We would now like to also perform OP1 with constant CONST1
8693 (with *POP0 being done last).
8695 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8696 the resulting operation. *PCOMP_P is set to 1 if we would need to
8697 complement the innermost operand, otherwise it is unchanged.
8699 MODE is the mode in which the operation will be done. No bits outside
8700 the width of this mode matter. It is assumed that the width of this mode
8701 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8703 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8704 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8705 result is simply *PCONST0.
8707 If the resulting operation cannot be expressed as one operation, we
8708 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8711 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8712 enum rtx_code
*pop0
;
8713 HOST_WIDE_INT
*pconst0
;
8715 HOST_WIDE_INT const1
;
8716 enum machine_mode mode
;
8719 enum rtx_code op0
= *pop0
;
8720 HOST_WIDE_INT const0
= *pconst0
;
8722 const0
&= GET_MODE_MASK (mode
);
8723 const1
&= GET_MODE_MASK (mode
);
8725 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8729 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8732 if (op1
== NIL
|| op0
== SET
)
8735 else if (op0
== NIL
)
8736 op0
= op1
, const0
= const1
;
8738 else if (op0
== op1
)
8762 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8763 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8766 /* If the two constants aren't the same, we can't do anything. The
8767 remaining six cases can all be done. */
8768 else if (const0
!= const1
)
8776 /* (a & b) | b == b */
8778 else /* op1 == XOR */
8779 /* (a ^ b) | b == a | b */
8785 /* (a & b) ^ b == (~a) & b */
8786 op0
= AND
, *pcomp_p
= 1;
8787 else /* op1 == IOR */
8788 /* (a | b) ^ b == a & ~b */
8789 op0
= AND
, *pconst0
= ~const0
;
8794 /* (a | b) & b == b */
8796 else /* op1 == XOR */
8797 /* (a ^ b) & b) == (~a) & b */
8804 /* Check for NO-OP cases. */
8805 const0
&= GET_MODE_MASK (mode
);
8807 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8809 else if (const0
== 0 && op0
== AND
)
8811 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8815 /* ??? Slightly redundant with the above mask, but not entirely.
8816 Moving this above means we'd have to sign-extend the mode mask
8817 for the final test. */
8818 const0
= trunc_int_for_mode (const0
, mode
);
8826 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8827 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8828 that we started with.
8830 The shift is normally computed in the widest mode we find in VAROP, as
8831 long as it isn't a different number of words than RESULT_MODE. Exceptions
8832 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8835 simplify_shift_const (x
, code
, result_mode
, varop
, input_count
)
8838 enum machine_mode result_mode
;
8842 enum rtx_code orig_code
= code
;
8843 int orig_count
= input_count
;
8846 enum machine_mode mode
= result_mode
;
8847 enum machine_mode shift_mode
, tmode
;
8848 unsigned int mode_words
8849 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8850 /* We form (outer_op (code varop count) (outer_const)). */
8851 enum rtx_code outer_op
= NIL
;
8852 HOST_WIDE_INT outer_const
= 0;
8854 int complement_p
= 0;
8857 /* If we were given an invalid count, don't do anything except exactly
8858 what was requested. */
8860 if (input_count
< 0 || input_count
> (int) GET_MODE_BITSIZE (mode
))
8865 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (input_count
));
8868 count
= input_count
;
8870 /* Make sure and truncate the "natural" shift on the way in. We don't
8871 want to do this inside the loop as it makes it more difficult to
8873 #ifdef SHIFT_COUNT_TRUNCATED
8874 if (SHIFT_COUNT_TRUNCATED
)
8875 count
%= GET_MODE_BITSIZE (mode
);
8878 /* Unless one of the branches of the `if' in this loop does a `continue',
8879 we will `break' the loop after the `if'. */
8883 /* If we have an operand of (clobber (const_int 0)), just return that
8885 if (GET_CODE (varop
) == CLOBBER
)
8888 /* If we discovered we had to complement VAROP, leave. Making a NOT
8889 here would cause an infinite loop. */
8893 /* Convert ROTATERT to ROTATE. */
8894 if (code
== ROTATERT
)
8895 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8897 /* We need to determine what mode we will do the shift in. If the
8898 shift is a right shift or a ROTATE, we must always do it in the mode
8899 it was originally done in. Otherwise, we can do it in MODE, the
8900 widest mode encountered. */
8902 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8903 ? result_mode
: mode
);
8905 /* Handle cases where the count is greater than the size of the mode
8906 minus 1. For ASHIFT, use the size minus one as the count (this can
8907 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8908 take the count modulo the size. For other shifts, the result is
8911 Since these shifts are being produced by the compiler by combining
8912 multiple operations, each of which are defined, we know what the
8913 result is supposed to be. */
8915 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
8917 if (code
== ASHIFTRT
)
8918 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8919 else if (code
== ROTATE
|| code
== ROTATERT
)
8920 count
%= GET_MODE_BITSIZE (shift_mode
);
8923 /* We can't simply return zero because there may be an
8931 /* An arithmetic right shift of a quantity known to be -1 or 0
8933 if (code
== ASHIFTRT
8934 && (num_sign_bit_copies (varop
, shift_mode
)
8935 == GET_MODE_BITSIZE (shift_mode
)))
8941 /* If we are doing an arithmetic right shift and discarding all but
8942 the sign bit copies, this is equivalent to doing a shift by the
8943 bitsize minus one. Convert it into that shift because it will often
8944 allow other simplifications. */
8946 if (code
== ASHIFTRT
8947 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8948 >= GET_MODE_BITSIZE (shift_mode
)))
8949 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8951 /* We simplify the tests below and elsewhere by converting
8952 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8953 `make_compound_operation' will convert it to a ASHIFTRT for
8954 those machines (such as Vax) that don't have a LSHIFTRT. */
8955 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8957 && ((nonzero_bits (varop
, shift_mode
)
8958 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8962 switch (GET_CODE (varop
))
8968 new = expand_compound_operation (varop
);
8977 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8978 minus the width of a smaller mode, we can do this with a
8979 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8980 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8981 && ! mode_dependent_address_p (XEXP (varop
, 0))
8982 && ! MEM_VOLATILE_P (varop
)
8983 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8984 MODE_INT
, 1)) != BLKmode
)
8986 new = adjust_address_nv (varop
, tmode
,
8987 BYTES_BIG_ENDIAN
? 0
8988 : count
/ BITS_PER_UNIT
);
8990 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8991 : ZERO_EXTEND
, mode
, new);
8998 /* Similar to the case above, except that we can only do this if
8999 the resulting mode is the same as that of the underlying
9000 MEM and adjust the address depending on the *bits* endianness
9001 because of the way that bit-field extract insns are defined. */
9002 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9003 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9004 MODE_INT
, 1)) != BLKmode
9005 && tmode
== GET_MODE (XEXP (varop
, 0)))
9007 if (BITS_BIG_ENDIAN
)
9008 new = XEXP (varop
, 0);
9011 new = copy_rtx (XEXP (varop
, 0));
9012 SUBST (XEXP (new, 0),
9013 plus_constant (XEXP (new, 0),
9014 count
/ BITS_PER_UNIT
));
9017 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9018 : ZERO_EXTEND
, mode
, new);
9025 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9026 the same number of words as what we've seen so far. Then store
9027 the widest mode in MODE. */
9028 if (subreg_lowpart_p (varop
)
9029 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9030 > GET_MODE_SIZE (GET_MODE (varop
)))
9031 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9032 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9035 varop
= SUBREG_REG (varop
);
9036 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9037 mode
= GET_MODE (varop
);
9043 /* Some machines use MULT instead of ASHIFT because MULT
9044 is cheaper. But it is still better on those machines to
9045 merge two shifts into one. */
9046 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9047 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9050 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9051 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9057 /* Similar, for when divides are cheaper. */
9058 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9059 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9062 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9063 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9069 /* If we are extracting just the sign bit of an arithmetic
9070 right shift, that shift is not needed. However, the sign
9071 bit of a wider mode may be different from what would be
9072 interpreted as the sign bit in a narrower mode, so, if
9073 the result is narrower, don't discard the shift. */
9074 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9075 && (GET_MODE_BITSIZE (result_mode
)
9076 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9078 varop
= XEXP (varop
, 0);
9082 /* ... fall through ... */
9087 /* Here we have two nested shifts. The result is usually the
9088 AND of a new shift with a mask. We compute the result below. */
9089 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9090 && INTVAL (XEXP (varop
, 1)) >= 0
9091 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9092 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9093 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9095 enum rtx_code first_code
= GET_CODE (varop
);
9096 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9097 unsigned HOST_WIDE_INT mask
;
9100 /* We have one common special case. We can't do any merging if
9101 the inner code is an ASHIFTRT of a smaller mode. However, if
9102 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9103 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9104 we can convert it to
9105 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9106 This simplifies certain SIGN_EXTEND operations. */
9107 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9108 && (GET_MODE_BITSIZE (result_mode
)
9109 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
9111 /* C3 has the low-order C1 bits zero. */
9113 mask
= (GET_MODE_MASK (mode
)
9114 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9116 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9117 XEXP (varop
, 0), mask
);
9118 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9120 count
= first_count
;
9125 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9126 than C1 high-order bits equal to the sign bit, we can convert
9127 this to either an ASHIFT or a ASHIFTRT depending on the
9130 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9132 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9133 && GET_MODE (varop
) == shift_mode
9134 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9137 varop
= XEXP (varop
, 0);
9139 signed_count
= count
- first_count
;
9140 if (signed_count
< 0)
9141 count
= -signed_count
, code
= ASHIFT
;
9143 count
= signed_count
;
9148 /* There are some cases we can't do. If CODE is ASHIFTRT,
9149 we can only do this if FIRST_CODE is also ASHIFTRT.
9151 We can't do the case when CODE is ROTATE and FIRST_CODE is
9154 If the mode of this shift is not the mode of the outer shift,
9155 we can't do this if either shift is a right shift or ROTATE.
9157 Finally, we can't do any of these if the mode is too wide
9158 unless the codes are the same.
9160 Handle the case where the shift codes are the same
9163 if (code
== first_code
)
9165 if (GET_MODE (varop
) != result_mode
9166 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9170 count
+= first_count
;
9171 varop
= XEXP (varop
, 0);
9175 if (code
== ASHIFTRT
9176 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9177 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9178 || (GET_MODE (varop
) != result_mode
9179 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9180 || first_code
== ROTATE
9181 || code
== ROTATE
)))
9184 /* To compute the mask to apply after the shift, shift the
9185 nonzero bits of the inner shift the same way the
9186 outer shift will. */
9188 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9191 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9194 /* Give up if we can't compute an outer operation to use. */
9196 || GET_CODE (mask_rtx
) != CONST_INT
9197 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9199 result_mode
, &complement_p
))
9202 /* If the shifts are in the same direction, we add the
9203 counts. Otherwise, we subtract them. */
9204 signed_count
= count
;
9205 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9206 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9207 signed_count
+= first_count
;
9209 signed_count
-= first_count
;
9211 /* If COUNT is positive, the new shift is usually CODE,
9212 except for the two exceptions below, in which case it is
9213 FIRST_CODE. If the count is negative, FIRST_CODE should
9215 if (signed_count
> 0
9216 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9217 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9218 code
= first_code
, count
= signed_count
;
9219 else if (signed_count
< 0)
9220 code
= first_code
, count
= -signed_count
;
9222 count
= signed_count
;
9224 varop
= XEXP (varop
, 0);
9228 /* If we have (A << B << C) for any shift, we can convert this to
9229 (A << C << B). This wins if A is a constant. Only try this if
9230 B is not a constant. */
9232 else if (GET_CODE (varop
) == code
9233 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9235 = simplify_binary_operation (code
, mode
,
9239 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9246 /* Make this fit the case below. */
9247 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9248 GEN_INT (GET_MODE_MASK (mode
)));
9254 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9255 with C the size of VAROP - 1 and the shift is logical if
9256 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9257 we have an (le X 0) operation. If we have an arithmetic shift
9258 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9259 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9261 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9262 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9263 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9264 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9265 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9266 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9269 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9272 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9273 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9278 /* If we have (shift (logical)), move the logical to the outside
9279 to allow it to possibly combine with another logical and the
9280 shift to combine with another shift. This also canonicalizes to
9281 what a ZERO_EXTRACT looks like. Also, some machines have
9282 (and (shift)) insns. */
9284 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9285 && (new = simplify_binary_operation (code
, result_mode
,
9287 GEN_INT (count
))) != 0
9288 && GET_CODE (new) == CONST_INT
9289 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9290 INTVAL (new), result_mode
, &complement_p
))
9292 varop
= XEXP (varop
, 0);
9296 /* If we can't do that, try to simplify the shift in each arm of the
9297 logical expression, make a new logical expression, and apply
9298 the inverse distributive law. */
9300 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9301 XEXP (varop
, 0), count
);
9302 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9303 XEXP (varop
, 1), count
);
9305 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9306 varop
= apply_distributive_law (varop
);
9313 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9314 says that the sign bit can be tested, FOO has mode MODE, C is
9315 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9316 that may be nonzero. */
9317 if (code
== LSHIFTRT
9318 && XEXP (varop
, 1) == const0_rtx
9319 && GET_MODE (XEXP (varop
, 0)) == result_mode
9320 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9321 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9322 && ((STORE_FLAG_VALUE
9323 & ((HOST_WIDE_INT
) 1
9324 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9325 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9326 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9327 (HOST_WIDE_INT
) 1, result_mode
,
9330 varop
= XEXP (varop
, 0);
9337 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9338 than the number of bits in the mode is equivalent to A. */
9339 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9340 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9342 varop
= XEXP (varop
, 0);
9347 /* NEG commutes with ASHIFT since it is multiplication. Move the
9348 NEG outside to allow shifts to combine. */
9350 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9351 (HOST_WIDE_INT
) 0, result_mode
,
9354 varop
= XEXP (varop
, 0);
9360 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9361 is one less than the number of bits in the mode is
9362 equivalent to (xor A 1). */
9363 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9364 && XEXP (varop
, 1) == constm1_rtx
9365 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9366 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9367 (HOST_WIDE_INT
) 1, result_mode
,
9371 varop
= XEXP (varop
, 0);
9375 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9376 that might be nonzero in BAR are those being shifted out and those
9377 bits are known zero in FOO, we can replace the PLUS with FOO.
9378 Similarly in the other operand order. This code occurs when
9379 we are computing the size of a variable-size array. */
9381 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9382 && count
< HOST_BITS_PER_WIDE_INT
9383 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9384 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9385 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9387 varop
= XEXP (varop
, 0);
9390 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9391 && count
< HOST_BITS_PER_WIDE_INT
9392 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9393 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9395 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9396 & nonzero_bits (XEXP (varop
, 1),
9399 varop
= XEXP (varop
, 1);
9403 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9405 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9406 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9408 GEN_INT (count
))) != 0
9409 && GET_CODE (new) == CONST_INT
9410 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9411 INTVAL (new), result_mode
, &complement_p
))
9413 varop
= XEXP (varop
, 0);
9419 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9420 with C the size of VAROP - 1 and the shift is logical if
9421 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9422 we have a (gt X 0) operation. If the shift is arithmetic with
9423 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9424 we have a (neg (gt X 0)) operation. */
9426 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9427 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9428 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9429 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9430 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9431 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9432 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9435 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9438 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9439 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9446 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9447 if the truncate does not affect the value. */
9448 if (code
== LSHIFTRT
9449 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9450 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9451 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9452 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9453 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9455 rtx varop_inner
= XEXP (varop
, 0);
9458 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9459 XEXP (varop_inner
, 0),
9461 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9462 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9475 /* We need to determine what mode to do the shift in. If the shift is
9476 a right shift or ROTATE, we must always do it in the mode it was
9477 originally done in. Otherwise, we can do it in MODE, the widest mode
9478 encountered. The code we care about is that of the shift that will
9479 actually be done, not the shift that was originally requested. */
9481 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9482 ? result_mode
: mode
);
9484 /* We have now finished analyzing the shift. The result should be
9485 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9486 OUTER_OP is non-NIL, it is an operation that needs to be applied
9487 to the result of the shift. OUTER_CONST is the relevant constant,
9488 but we must turn off all bits turned off in the shift.
9490 If we were passed a value for X, see if we can use any pieces of
9491 it. If not, make new rtx. */
9493 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9494 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9495 && INTVAL (XEXP (x
, 1)) == count
)
9496 const_rtx
= XEXP (x
, 1);
9498 const_rtx
= GEN_INT (count
);
9500 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9501 && GET_MODE (XEXP (x
, 0)) == shift_mode
9502 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9503 varop
= XEXP (x
, 0);
9504 else if (GET_MODE (varop
) != shift_mode
)
9505 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9507 /* If we can't make the SUBREG, try to return what we were given. */
9508 if (GET_CODE (varop
) == CLOBBER
)
9509 return x
? x
: varop
;
9511 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9516 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9517 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9519 SUBST (XEXP (x
, 0), varop
);
9520 SUBST (XEXP (x
, 1), const_rtx
);
9523 /* If we have an outer operation and we just made a shift, it is
9524 possible that we could have simplified the shift were it not
9525 for the outer operation. So try to do the simplification
9528 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9529 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9530 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9531 INTVAL (XEXP (x
, 1)));
9533 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9534 turn off all the bits that the shift would have turned off. */
9535 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9536 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9537 GET_MODE_MASK (result_mode
) >> orig_count
);
9539 /* Do the remainder of the processing in RESULT_MODE. */
9540 x
= gen_lowpart_for_combine (result_mode
, x
);
9542 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9545 x
=simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9547 if (outer_op
!= NIL
)
9549 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9550 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9552 if (outer_op
== AND
)
9553 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9554 else if (outer_op
== SET
)
9555 /* This means that we have determined that the result is
9556 equivalent to a constant. This should be rare. */
9557 x
= GEN_INT (outer_const
);
9558 else if (GET_RTX_CLASS (outer_op
) == '1')
9559 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9561 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9567 /* Like recog, but we receive the address of a pointer to a new pattern.
9568 We try to match the rtx that the pointer points to.
9569 If that fails, we may try to modify or replace the pattern,
9570 storing the replacement into the same pointer object.
9572 Modifications include deletion or addition of CLOBBERs.
9574 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9575 the CLOBBERs are placed.
9577 The value is the final insn code from the pattern ultimately matched,
9581 recog_for_combine (pnewpat
, insn
, pnotes
)
9586 register rtx pat
= *pnewpat
;
9587 int insn_code_number
;
9588 int num_clobbers_to_add
= 0;
9593 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9594 we use to indicate that something didn't match. If we find such a
9595 thing, force rejection. */
9596 if (GET_CODE (pat
) == PARALLEL
)
9597 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9598 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9599 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9602 /* Remove the old notes prior to trying to recognize the new pattern. */
9603 old_notes
= REG_NOTES (insn
);
9604 REG_NOTES (insn
) = 0;
9606 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9608 /* If it isn't, there is the possibility that we previously had an insn
9609 that clobbered some register as a side effect, but the combined
9610 insn doesn't need to do that. So try once more without the clobbers
9611 unless this represents an ASM insn. */
9613 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9614 && GET_CODE (pat
) == PARALLEL
)
9618 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9619 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9622 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9626 SUBST_INT (XVECLEN (pat
, 0), pos
);
9629 pat
= XVECEXP (pat
, 0, 0);
9631 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9634 /* Recognize all noop sets, these will be killed by followup pass. */
9635 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9636 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9638 REG_NOTES (insn
) = old_notes
;
9640 /* If we had any clobbers to add, make a new pattern than contains
9641 them. Then check to make sure that all of them are dead. */
9642 if (num_clobbers_to_add
)
9644 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9645 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9647 + num_clobbers_to_add
)
9648 : num_clobbers_to_add
+ 1));
9650 if (GET_CODE (pat
) == PARALLEL
)
9651 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9652 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9654 XVECEXP (newpat
, 0, 0) = pat
;
9656 add_clobbers (newpat
, insn_code_number
);
9658 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9659 i
< XVECLEN (newpat
, 0); i
++)
9661 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9662 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9664 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9665 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9673 return insn_code_number
;
9676 /* Like gen_lowpart but for use by combine. In combine it is not possible
9677 to create any new pseudoregs. However, it is safe to create
9678 invalid memory addresses, because combine will try to recognize
9679 them and all they will do is make the combine attempt fail.
9681 If for some reason this cannot do its job, an rtx
9682 (clobber (const_int 0)) is returned.
9683 An insn containing that will not be recognized. */
9688 gen_lowpart_for_combine (mode
, x
)
9689 enum machine_mode mode
;
9694 if (GET_MODE (x
) == mode
)
9697 /* We can only support MODE being wider than a word if X is a
9698 constant integer or has a mode the same size. */
9700 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9701 && ! ((GET_MODE (x
) == VOIDmode
9702 && (GET_CODE (x
) == CONST_INT
9703 || GET_CODE (x
) == CONST_DOUBLE
))
9704 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9705 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9707 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9708 won't know what to do. So we will strip off the SUBREG here and
9709 process normally. */
9710 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9713 if (GET_MODE (x
) == mode
)
9717 result
= gen_lowpart_common (mode
, x
);
9718 #ifdef CLASS_CANNOT_CHANGE_MODE
9720 && GET_CODE (result
) == SUBREG
9721 && GET_CODE (SUBREG_REG (result
)) == REG
9722 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9723 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9724 GET_MODE (SUBREG_REG (result
))))
9725 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9731 if (GET_CODE (x
) == MEM
)
9733 register int offset
= 0;
9735 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9737 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9738 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9740 /* If we want to refer to something bigger than the original memref,
9741 generate a perverse subreg instead. That will force a reload
9742 of the original memref X. */
9743 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9744 return gen_rtx_SUBREG (mode
, x
, 0);
9746 if (WORDS_BIG_ENDIAN
)
9747 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9748 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9750 if (BYTES_BIG_ENDIAN
)
9752 /* Adjust the address so that the address-after-the-data is
9754 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9755 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9758 return adjust_address_nv (x
, mode
, offset
);
9761 /* If X is a comparison operator, rewrite it in a new mode. This
9762 probably won't match, but may allow further simplifications. */
9763 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9764 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9766 /* If we couldn't simplify X any other way, just enclose it in a
9767 SUBREG. Normally, this SUBREG won't match, but some patterns may
9768 include an explicit SUBREG or we may simplify it further in combine. */
9774 offset
= subreg_lowpart_offset (mode
, GET_MODE (x
));
9775 res
= simplify_gen_subreg (mode
, x
, GET_MODE (x
), offset
);
9778 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9782 /* These routines make binary and unary operations by first seeing if they
9783 fold; if not, a new expression is allocated. */
9786 gen_binary (code
, mode
, op0
, op1
)
9788 enum machine_mode mode
;
9794 if (GET_RTX_CLASS (code
) == 'c'
9795 && swap_commutative_operands_p (op0
, op1
))
9796 tem
= op0
, op0
= op1
, op1
= tem
;
9798 if (GET_RTX_CLASS (code
) == '<')
9800 enum machine_mode op_mode
= GET_MODE (op0
);
9802 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9803 just (REL_OP X Y). */
9804 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9806 op1
= XEXP (op0
, 1);
9807 op0
= XEXP (op0
, 0);
9808 op_mode
= GET_MODE (op0
);
9811 if (op_mode
== VOIDmode
)
9812 op_mode
= GET_MODE (op1
);
9813 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9816 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9821 /* Put complex operands first and constants second. */
9822 if (GET_RTX_CLASS (code
) == 'c'
9823 && swap_commutative_operands_p (op0
, op1
))
9824 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
9826 /* If we are turning off bits already known off in OP0, we need not do
9828 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9829 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9830 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9833 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
9836 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9837 comparison code that will be tested.
9839 The result is a possibly different comparison code to use. *POP0 and
9840 *POP1 may be updated.
9842 It is possible that we might detect that a comparison is either always
9843 true or always false. However, we do not perform general constant
9844 folding in combine, so this knowledge isn't useful. Such tautologies
9845 should have been detected earlier. Hence we ignore all such cases. */
9847 static enum rtx_code
9848 simplify_comparison (code
, pop0
, pop1
)
9857 enum machine_mode mode
, tmode
;
9859 /* Try a few ways of applying the same transformation to both operands. */
9862 #ifndef WORD_REGISTER_OPERATIONS
9863 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9864 so check specially. */
9865 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9866 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9867 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9868 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9869 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9870 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9871 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9872 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9873 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9874 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
9875 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9876 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
9877 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
9878 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
9879 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
9880 && (INTVAL (XEXP (op0
, 1))
9881 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9883 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9885 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9886 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9890 /* If both operands are the same constant shift, see if we can ignore the
9891 shift. We can if the shift is a rotate or if the bits shifted out of
9892 this shift are known to be zero for both inputs and if the type of
9893 comparison is compatible with the shift. */
9894 if (GET_CODE (op0
) == GET_CODE (op1
)
9895 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9896 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9897 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9898 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9899 || (GET_CODE (op0
) == ASHIFTRT
9900 && (code
!= GTU
&& code
!= LTU
9901 && code
!= GEU
&& code
!= LEU
)))
9902 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9903 && INTVAL (XEXP (op0
, 1)) >= 0
9904 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9905 && XEXP (op0
, 1) == XEXP (op1
, 1))
9907 enum machine_mode mode
= GET_MODE (op0
);
9908 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9909 int shift_count
= INTVAL (XEXP (op0
, 1));
9911 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9912 mask
&= (mask
>> shift_count
) << shift_count
;
9913 else if (GET_CODE (op0
) == ASHIFT
)
9914 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9916 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9917 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9918 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9923 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9924 SUBREGs are of the same mode, and, in both cases, the AND would
9925 be redundant if the comparison was done in the narrower mode,
9926 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9927 and the operand's possibly nonzero bits are 0xffffff01; in that case
9928 if we only care about QImode, we don't need the AND). This case
9929 occurs if the output mode of an scc insn is not SImode and
9930 STORE_FLAG_VALUE == 1 (e.g., the 386).
9932 Similarly, check for a case where the AND's are ZERO_EXTEND
9933 operations from some narrower mode even though a SUBREG is not
9936 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9937 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9938 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9940 rtx inner_op0
= XEXP (op0
, 0);
9941 rtx inner_op1
= XEXP (op1
, 0);
9942 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9943 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9946 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9947 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9948 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9949 && (GET_MODE (SUBREG_REG (inner_op0
))
9950 == GET_MODE (SUBREG_REG (inner_op1
)))
9951 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9952 <= HOST_BITS_PER_WIDE_INT
)
9953 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9954 GET_MODE (SUBREG_REG (inner_op0
)))))
9955 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9956 GET_MODE (SUBREG_REG (inner_op1
))))))
9958 op0
= SUBREG_REG (inner_op0
);
9959 op1
= SUBREG_REG (inner_op1
);
9961 /* The resulting comparison is always unsigned since we masked
9962 off the original sign bit. */
9963 code
= unsigned_condition (code
);
9969 for (tmode
= GET_CLASS_NARROWEST_MODE
9970 (GET_MODE_CLASS (GET_MODE (op0
)));
9971 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9972 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9974 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
9975 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
9976 code
= unsigned_condition (code
);
9985 /* If both operands are NOT, we can strip off the outer operation
9986 and adjust the comparison code for swapped operands; similarly for
9987 NEG, except that this must be an equality comparison. */
9988 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9989 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9990 && (code
== EQ
|| code
== NE
)))
9991 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9997 /* If the first operand is a constant, swap the operands and adjust the
9998 comparison code appropriately, but don't do this if the second operand
9999 is already a constant integer. */
10000 if (swap_commutative_operands_p (op0
, op1
))
10002 tem
= op0
, op0
= op1
, op1
= tem
;
10003 code
= swap_condition (code
);
10006 /* We now enter a loop during which we will try to simplify the comparison.
10007 For the most part, we only are concerned with comparisons with zero,
10008 but some things may really be comparisons with zero but not start
10009 out looking that way. */
10011 while (GET_CODE (op1
) == CONST_INT
)
10013 enum machine_mode mode
= GET_MODE (op0
);
10014 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10015 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10016 int equality_comparison_p
;
10017 int sign_bit_comparison_p
;
10018 int unsigned_comparison_p
;
10019 HOST_WIDE_INT const_op
;
10021 /* We only want to handle integral modes. This catches VOIDmode,
10022 CCmode, and the floating-point modes. An exception is that we
10023 can handle VOIDmode if OP0 is a COMPARE or a comparison
10026 if (GET_MODE_CLASS (mode
) != MODE_INT
10027 && ! (mode
== VOIDmode
10028 && (GET_CODE (op0
) == COMPARE
10029 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10032 /* Get the constant we are comparing against and turn off all bits
10033 not on in our mode. */
10034 const_op
= trunc_int_for_mode (INTVAL (op1
), mode
);
10035 op1
= GEN_INT (const_op
);
10037 /* If we are comparing against a constant power of two and the value
10038 being compared can only have that single bit nonzero (e.g., it was
10039 `and'ed with that bit), we can replace this with a comparison
10042 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10043 || code
== LT
|| code
== LTU
)
10044 && mode_width
<= HOST_BITS_PER_WIDE_INT
10045 && exact_log2 (const_op
) >= 0
10046 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10048 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10049 op1
= const0_rtx
, const_op
= 0;
10052 /* Similarly, if we are comparing a value known to be either -1 or
10053 0 with -1, change it to the opposite comparison against zero. */
10056 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10057 || code
== GEU
|| code
== LTU
)
10058 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10060 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10061 op1
= const0_rtx
, const_op
= 0;
10064 /* Do some canonicalizations based on the comparison code. We prefer
10065 comparisons against zero and then prefer equality comparisons.
10066 If we can reduce the size of a constant, we will do that too. */
10071 /* < C is equivalent to <= (C - 1) */
10075 op1
= GEN_INT (const_op
);
10077 /* ... fall through to LE case below. */
10083 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10087 op1
= GEN_INT (const_op
);
10091 /* If we are doing a <= 0 comparison on a value known to have
10092 a zero sign bit, we can replace this with == 0. */
10093 else if (const_op
== 0
10094 && mode_width
<= HOST_BITS_PER_WIDE_INT
10095 && (nonzero_bits (op0
, mode
)
10096 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10101 /* >= C is equivalent to > (C - 1). */
10105 op1
= GEN_INT (const_op
);
10107 /* ... fall through to GT below. */
10113 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10117 op1
= GEN_INT (const_op
);
10121 /* If we are doing a > 0 comparison on a value known to have
10122 a zero sign bit, we can replace this with != 0. */
10123 else if (const_op
== 0
10124 && mode_width
<= HOST_BITS_PER_WIDE_INT
10125 && (nonzero_bits (op0
, mode
)
10126 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10131 /* < C is equivalent to <= (C - 1). */
10135 op1
= GEN_INT (const_op
);
10137 /* ... fall through ... */
10140 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10141 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10142 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10144 const_op
= 0, op1
= const0_rtx
;
10152 /* unsigned <= 0 is equivalent to == 0 */
10156 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10157 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10158 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10160 const_op
= 0, op1
= const0_rtx
;
10166 /* >= C is equivalent to < (C - 1). */
10170 op1
= GEN_INT (const_op
);
10172 /* ... fall through ... */
10175 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10176 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10177 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10179 const_op
= 0, op1
= const0_rtx
;
10187 /* unsigned > 0 is equivalent to != 0 */
10191 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10192 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10193 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10195 const_op
= 0, op1
= const0_rtx
;
10204 /* Compute some predicates to simplify code below. */
10206 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10207 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10208 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10211 /* If this is a sign bit comparison and we can do arithmetic in
10212 MODE, say that we will only be needing the sign bit of OP0. */
10213 if (sign_bit_comparison_p
10214 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10215 op0
= force_to_mode (op0
, mode
,
10217 << (GET_MODE_BITSIZE (mode
) - 1)),
10220 /* Now try cases based on the opcode of OP0. If none of the cases
10221 does a "continue", we exit this loop immediately after the
10224 switch (GET_CODE (op0
))
10227 /* If we are extracting a single bit from a variable position in
10228 a constant that has only a single bit set and are comparing it
10229 with zero, we can convert this into an equality comparison
10230 between the position and the location of the single bit. */
10232 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10233 && XEXP (op0
, 1) == const1_rtx
10234 && equality_comparison_p
&& const_op
== 0
10235 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10237 if (BITS_BIG_ENDIAN
)
10240 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10241 if (mode
== VOIDmode
)
10243 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10245 i
= BITS_PER_WORD
- 1 - i
;
10249 op0
= XEXP (op0
, 2);
10253 /* Result is nonzero iff shift count is equal to I. */
10254 code
= reverse_condition (code
);
10258 /* ... fall through ... */
10261 tem
= expand_compound_operation (op0
);
10270 /* If testing for equality, we can take the NOT of the constant. */
10271 if (equality_comparison_p
10272 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10274 op0
= XEXP (op0
, 0);
10279 /* If just looking at the sign bit, reverse the sense of the
10281 if (sign_bit_comparison_p
)
10283 op0
= XEXP (op0
, 0);
10284 code
= (code
== GE
? LT
: GE
);
10290 /* If testing for equality, we can take the NEG of the constant. */
10291 if (equality_comparison_p
10292 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10294 op0
= XEXP (op0
, 0);
10299 /* The remaining cases only apply to comparisons with zero. */
10303 /* When X is ABS or is known positive,
10304 (neg X) is < 0 if and only if X != 0. */
10306 if (sign_bit_comparison_p
10307 && (GET_CODE (XEXP (op0
, 0)) == ABS
10308 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10309 && (nonzero_bits (XEXP (op0
, 0), mode
)
10310 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10312 op0
= XEXP (op0
, 0);
10313 code
= (code
== LT
? NE
: EQ
);
10317 /* If we have NEG of something whose two high-order bits are the
10318 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10319 if (num_sign_bit_copies (op0
, mode
) >= 2)
10321 op0
= XEXP (op0
, 0);
10322 code
= swap_condition (code
);
10328 /* If we are testing equality and our count is a constant, we
10329 can perform the inverse operation on our RHS. */
10330 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10331 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10332 op1
, XEXP (op0
, 1))) != 0)
10334 op0
= XEXP (op0
, 0);
10339 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10340 a particular bit. Convert it to an AND of a constant of that
10341 bit. This will be converted into a ZERO_EXTRACT. */
10342 if (const_op
== 0 && sign_bit_comparison_p
10343 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10344 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10346 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10349 - INTVAL (XEXP (op0
, 1)))));
10350 code
= (code
== LT
? NE
: EQ
);
10354 /* Fall through. */
10357 /* ABS is ignorable inside an equality comparison with zero. */
10358 if (const_op
== 0 && equality_comparison_p
)
10360 op0
= XEXP (op0
, 0);
10366 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10367 to (compare FOO CONST) if CONST fits in FOO's mode and we
10368 are either testing inequality or have an unsigned comparison
10369 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10370 if (! unsigned_comparison_p
10371 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10372 <= HOST_BITS_PER_WIDE_INT
)
10373 && ((unsigned HOST_WIDE_INT
) const_op
10374 < (((unsigned HOST_WIDE_INT
) 1
10375 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10377 op0
= XEXP (op0
, 0);
10383 /* Check for the case where we are comparing A - C1 with C2,
10384 both constants are smaller than 1/2 the maximum positive
10385 value in MODE, and the comparison is equality or unsigned.
10386 In that case, if A is either zero-extended to MODE or has
10387 sufficient sign bits so that the high-order bit in MODE
10388 is a copy of the sign in the inner mode, we can prove that it is
10389 safe to do the operation in the wider mode. This simplifies
10390 many range checks. */
10392 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10393 && subreg_lowpart_p (op0
)
10394 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10395 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10396 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10397 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10398 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10399 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10400 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10401 GET_MODE (SUBREG_REG (op0
)))
10402 & ~GET_MODE_MASK (mode
))
10403 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10404 GET_MODE (SUBREG_REG (op0
)))
10405 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10406 - GET_MODE_BITSIZE (mode
)))))
10408 op0
= SUBREG_REG (op0
);
10412 /* If the inner mode is narrower and we are extracting the low part,
10413 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10414 if (subreg_lowpart_p (op0
)
10415 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10416 /* Fall through */ ;
10420 /* ... fall through ... */
10423 if ((unsigned_comparison_p
|| equality_comparison_p
)
10424 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10425 <= HOST_BITS_PER_WIDE_INT
)
10426 && ((unsigned HOST_WIDE_INT
) const_op
10427 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10429 op0
= XEXP (op0
, 0);
10435 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10436 this for equality comparisons due to pathological cases involving
10438 if (equality_comparison_p
10439 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10440 op1
, XEXP (op0
, 1))))
10442 op0
= XEXP (op0
, 0);
10447 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10448 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10449 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10451 op0
= XEXP (XEXP (op0
, 0), 0);
10452 code
= (code
== LT
? EQ
: NE
);
10458 /* We used to optimize signed comparisons against zero, but that
10459 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10460 arrive here as equality comparisons, or (GEU, LTU) are
10461 optimized away. No need to special-case them. */
10463 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10464 (eq B (minus A C)), whichever simplifies. We can only do
10465 this for equality comparisons due to pathological cases involving
10467 if (equality_comparison_p
10468 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10469 XEXP (op0
, 1), op1
)))
10471 op0
= XEXP (op0
, 0);
10476 if (equality_comparison_p
10477 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10478 XEXP (op0
, 0), op1
)))
10480 op0
= XEXP (op0
, 1);
10485 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10486 of bits in X minus 1, is one iff X > 0. */
10487 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10488 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10489 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10490 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10492 op0
= XEXP (op0
, 1);
10493 code
= (code
== GE
? LE
: GT
);
10499 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10500 if C is zero or B is a constant. */
10501 if (equality_comparison_p
10502 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10503 XEXP (op0
, 1), op1
)))
10505 op0
= XEXP (op0
, 0);
10512 case UNEQ
: case LTGT
:
10513 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10514 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10515 case UNORDERED
: case ORDERED
:
10516 /* We can't do anything if OP0 is a condition code value, rather
10517 than an actual data value. */
10520 || XEXP (op0
, 0) == cc0_rtx
10522 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10525 /* Get the two operands being compared. */
10526 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10527 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10529 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10531 /* Check for the cases where we simply want the result of the
10532 earlier test or the opposite of that result. */
10533 if (code
== NE
|| code
== EQ
10534 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10535 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10536 && (STORE_FLAG_VALUE
10537 & (((HOST_WIDE_INT
) 1
10538 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10539 && (code
== LT
|| code
== GE
)))
10541 enum rtx_code new_code
;
10542 if (code
== LT
|| code
== NE
)
10543 new_code
= GET_CODE (op0
);
10545 new_code
= combine_reversed_comparison_code (op0
);
10547 if (new_code
!= UNKNOWN
)
10558 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10560 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10561 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10562 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10564 op0
= XEXP (op0
, 1);
10565 code
= (code
== GE
? GT
: LE
);
10571 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10572 will be converted to a ZERO_EXTRACT later. */
10573 if (const_op
== 0 && equality_comparison_p
10574 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10575 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10577 op0
= simplify_and_const_int
10578 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10580 XEXP (XEXP (op0
, 0), 1)),
10581 (HOST_WIDE_INT
) 1);
10585 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10586 zero and X is a comparison and C1 and C2 describe only bits set
10587 in STORE_FLAG_VALUE, we can compare with X. */
10588 if (const_op
== 0 && equality_comparison_p
10589 && mode_width
<= HOST_BITS_PER_WIDE_INT
10590 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10591 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10592 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10593 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10594 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10596 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10597 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10598 if ((~STORE_FLAG_VALUE
& mask
) == 0
10599 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10600 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10601 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10603 op0
= XEXP (XEXP (op0
, 0), 0);
10608 /* If we are doing an equality comparison of an AND of a bit equal
10609 to the sign bit, replace this with a LT or GE comparison of
10610 the underlying value. */
10611 if (equality_comparison_p
10613 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10614 && mode_width
<= HOST_BITS_PER_WIDE_INT
10615 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10616 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10618 op0
= XEXP (op0
, 0);
10619 code
= (code
== EQ
? GE
: LT
);
10623 /* If this AND operation is really a ZERO_EXTEND from a narrower
10624 mode, the constant fits within that mode, and this is either an
10625 equality or unsigned comparison, try to do this comparison in
10626 the narrower mode. */
10627 if ((equality_comparison_p
|| unsigned_comparison_p
)
10628 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10629 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10630 & GET_MODE_MASK (mode
))
10632 && const_op
>> i
== 0
10633 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10635 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10639 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10640 in both M1 and M2 and the SUBREG is either paradoxical or
10641 represents the low part, permute the SUBREG and the AND and
10643 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10645 #ifdef WORD_REGISTER_OPERATIONS
10647 > (GET_MODE_BITSIZE
10648 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10649 && mode_width
<= BITS_PER_WORD
)
10652 <= (GET_MODE_BITSIZE
10653 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10654 && subreg_lowpart_p (XEXP (op0
, 0))))
10655 #ifndef WORD_REGISTER_OPERATIONS
10656 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10657 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10658 As originally written the upper bits have a defined value
10659 due to the AND operation. However, if we commute the AND
10660 inside the SUBREG then they no longer have defined values
10661 and the meaning of the code has been changed. */
10662 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10663 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10665 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10666 && mode_width
<= HOST_BITS_PER_WIDE_INT
10667 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10668 <= HOST_BITS_PER_WIDE_INT
)
10669 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10670 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10671 & INTVAL (XEXP (op0
, 1)))
10672 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10673 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10674 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10678 = gen_lowpart_for_combine
10680 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10681 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10685 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10686 (eq (and (lshiftrt X) 1) 0). */
10687 if (const_op
== 0 && equality_comparison_p
10688 && XEXP (op0
, 1) == const1_rtx
10689 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10690 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10692 op0
= simplify_and_const_int
10694 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10695 XEXP (XEXP (op0
, 0), 1)),
10696 (HOST_WIDE_INT
) 1);
10697 code
= (code
== NE
? EQ
: NE
);
10703 /* If we have (compare (ashift FOO N) (const_int C)) and
10704 the high order N bits of FOO (N+1 if an inequality comparison)
10705 are known to be zero, we can do this by comparing FOO with C
10706 shifted right N bits so long as the low-order N bits of C are
10708 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10709 && INTVAL (XEXP (op0
, 1)) >= 0
10710 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10711 < HOST_BITS_PER_WIDE_INT
)
10713 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10714 && mode_width
<= HOST_BITS_PER_WIDE_INT
10715 && (nonzero_bits (XEXP (op0
, 0), mode
)
10716 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10717 + ! equality_comparison_p
))) == 0)
10719 /* We must perform a logical shift, not an arithmetic one,
10720 as we want the top N bits of C to be zero. */
10721 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10723 temp
>>= INTVAL (XEXP (op0
, 1));
10724 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10725 op0
= XEXP (op0
, 0);
10729 /* If we are doing a sign bit comparison, it means we are testing
10730 a particular bit. Convert it to the appropriate AND. */
10731 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10732 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10734 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10737 - INTVAL (XEXP (op0
, 1)))));
10738 code
= (code
== LT
? NE
: EQ
);
10742 /* If this an equality comparison with zero and we are shifting
10743 the low bit to the sign bit, we can convert this to an AND of the
10745 if (const_op
== 0 && equality_comparison_p
10746 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10747 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10749 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10750 (HOST_WIDE_INT
) 1);
10756 /* If this is an equality comparison with zero, we can do this
10757 as a logical shift, which might be much simpler. */
10758 if (equality_comparison_p
&& const_op
== 0
10759 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10761 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10763 INTVAL (XEXP (op0
, 1)));
10767 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10768 do the comparison in a narrower mode. */
10769 if (! unsigned_comparison_p
10770 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10771 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10772 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10773 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10774 MODE_INT
, 1)) != BLKmode
10775 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10776 || ((unsigned HOST_WIDE_INT
) -const_op
10777 <= GET_MODE_MASK (tmode
))))
10779 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10783 /* Likewise if OP0 is a PLUS of a sign extension with a
10784 constant, which is usually represented with the PLUS
10785 between the shifts. */
10786 if (! unsigned_comparison_p
10787 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10788 && GET_CODE (XEXP (op0
, 0)) == PLUS
10789 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10790 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10791 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10792 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10793 MODE_INT
, 1)) != BLKmode
10794 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10795 || ((unsigned HOST_WIDE_INT
) -const_op
10796 <= GET_MODE_MASK (tmode
))))
10798 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10799 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10800 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10803 op0
= gen_binary (PLUS
, tmode
,
10804 gen_lowpart_for_combine (tmode
, inner
),
10809 /* ... fall through ... */
10811 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10812 the low order N bits of FOO are known to be zero, we can do this
10813 by comparing FOO with C shifted left N bits so long as no
10814 overflow occurs. */
10815 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10816 && INTVAL (XEXP (op0
, 1)) >= 0
10817 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10818 && mode_width
<= HOST_BITS_PER_WIDE_INT
10819 && (nonzero_bits (XEXP (op0
, 0), mode
)
10820 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10822 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10825 const_op
<<= INTVAL (XEXP (op0
, 1));
10826 op1
= GEN_INT (const_op
);
10827 op0
= XEXP (op0
, 0);
10831 /* If we are using this shift to extract just the sign bit, we
10832 can replace this with an LT or GE comparison. */
10834 && (equality_comparison_p
|| sign_bit_comparison_p
)
10835 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10836 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10838 op0
= XEXP (op0
, 0);
10839 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10851 /* Now make any compound operations involved in this comparison. Then,
10852 check for an outmost SUBREG on OP0 that is not doing anything or is
10853 paradoxical. The latter case can only occur when it is known that the
10854 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10855 We can never remove a SUBREG for a non-equality comparison because the
10856 sign bit is in a different place in the underlying object. */
10858 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10859 op1
= make_compound_operation (op1
, SET
);
10861 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10862 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10863 && (code
== NE
|| code
== EQ
)
10864 && ((GET_MODE_SIZE (GET_MODE (op0
))
10865 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
10867 op0
= SUBREG_REG (op0
);
10868 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
10871 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10872 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10873 && (code
== NE
|| code
== EQ
)
10874 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10875 <= HOST_BITS_PER_WIDE_INT
)
10876 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
10877 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0
10878 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
10880 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10881 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0))
10882 op0
= SUBREG_REG (op0
), op1
= tem
;
10884 /* We now do the opposite procedure: Some machines don't have compare
10885 insns in all modes. If OP0's mode is an integer mode smaller than a
10886 word and we can't do a compare in that mode, see if there is a larger
10887 mode for which we can do the compare. There are a number of cases in
10888 which we can use the wider mode. */
10890 mode
= GET_MODE (op0
);
10891 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10892 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10893 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
10894 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10896 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10897 tmode
= GET_MODE_WIDER_MODE (tmode
))
10898 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
10900 /* If the only nonzero bits in OP0 and OP1 are those in the
10901 narrower mode and this is an equality or unsigned comparison,
10902 we can use the wider mode. Similarly for sign-extended
10903 values, in which case it is true for all comparisons. */
10904 if (((code
== EQ
|| code
== NE
10905 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
10906 && (nonzero_bits (op0
, tmode
) & ~GET_MODE_MASK (mode
)) == 0
10907 && (nonzero_bits (op1
, tmode
) & ~GET_MODE_MASK (mode
)) == 0)
10908 || ((num_sign_bit_copies (op0
, tmode
)
10909 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
10910 && (num_sign_bit_copies (op1
, tmode
)
10911 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
10913 /* If OP0 is an AND and we don't have an AND in MODE either,
10914 make a new AND in the proper mode. */
10915 if (GET_CODE (op0
) == AND
10916 && (add_optab
->handlers
[(int) mode
].insn_code
10917 == CODE_FOR_nothing
))
10918 op0
= gen_binary (AND
, tmode
,
10919 gen_lowpart_for_combine (tmode
,
10921 gen_lowpart_for_combine (tmode
,
10924 op0
= gen_lowpart_for_combine (tmode
, op0
);
10925 op1
= gen_lowpart_for_combine (tmode
, op1
);
10929 /* If this is a test for negative, we can make an explicit
10930 test of the sign bit. */
10932 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10933 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10935 op0
= gen_binary (AND
, tmode
,
10936 gen_lowpart_for_combine (tmode
, op0
),
10937 GEN_INT ((HOST_WIDE_INT
) 1
10938 << (GET_MODE_BITSIZE (mode
) - 1)));
10939 code
= (code
== LT
) ? NE
: EQ
;
10944 #ifdef CANONICALIZE_COMPARISON
10945 /* If this machine only supports a subset of valid comparisons, see if we
10946 can convert an unsupported one into a supported one. */
10947 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10956 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10957 searching backward. */
10958 static enum rtx_code
10959 combine_reversed_comparison_code (exp
)
10962 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
10965 if (code1
!= UNKNOWN
10966 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
10968 /* Otherwise try and find where the condition codes were last set and
10970 x
= get_last_value (XEXP (exp
, 0));
10971 if (!x
|| GET_CODE (x
) != COMPARE
)
10973 return reversed_comparison_code_parts (GET_CODE (exp
),
10974 XEXP (x
, 0), XEXP (x
, 1), NULL
);
10976 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10977 Return NULL_RTX in case we fail to do the reversal. */
10979 reversed_comparison (exp
, mode
, op0
, op1
)
10981 enum machine_mode mode
;
10983 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
10984 if (reversed_code
== UNKNOWN
)
10987 return gen_binary (reversed_code
, mode
, op0
, op1
);
10990 /* Utility function for following routine. Called when X is part of a value
10991 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10992 for each register mentioned. Similar to mention_regs in cse.c */
10995 update_table_tick (x
)
10998 register enum rtx_code code
= GET_CODE (x
);
10999 register const char *fmt
= GET_RTX_FORMAT (code
);
11004 unsigned int regno
= REGNO (x
);
11005 unsigned int endregno
11006 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11007 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11010 for (r
= regno
; r
< endregno
; r
++)
11011 reg_last_set_table_tick
[r
] = label_tick
;
11016 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11017 /* Note that we can't have an "E" in values stored; see
11018 get_last_value_validate. */
11020 update_table_tick (XEXP (x
, i
));
11023 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11024 are saying that the register is clobbered and we no longer know its
11025 value. If INSN is zero, don't update reg_last_set; this is only permitted
11026 with VALUE also zero and is used to invalidate the register. */
11029 record_value_for_reg (reg
, insn
, value
)
11034 unsigned int regno
= REGNO (reg
);
11035 unsigned int endregno
11036 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11037 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11040 /* If VALUE contains REG and we have a previous value for REG, substitute
11041 the previous value. */
11042 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11046 /* Set things up so get_last_value is allowed to see anything set up to
11048 subst_low_cuid
= INSN_CUID (insn
);
11049 tem
= get_last_value (reg
);
11051 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11052 it isn't going to be useful and will take a lot of time to process,
11053 so just use the CLOBBER. */
11057 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11058 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11059 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11060 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11061 tem
= XEXP (tem
, 0);
11063 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11067 /* For each register modified, show we don't know its value, that
11068 we don't know about its bitwise content, that its value has been
11069 updated, and that we don't know the location of the death of the
11071 for (i
= regno
; i
< endregno
; i
++)
11074 reg_last_set
[i
] = insn
;
11076 reg_last_set_value
[i
] = 0;
11077 reg_last_set_mode
[i
] = 0;
11078 reg_last_set_nonzero_bits
[i
] = 0;
11079 reg_last_set_sign_bit_copies
[i
] = 0;
11080 reg_last_death
[i
] = 0;
11083 /* Mark registers that are being referenced in this value. */
11085 update_table_tick (value
);
11087 /* Now update the status of each register being set.
11088 If someone is using this register in this block, set this register
11089 to invalid since we will get confused between the two lives in this
11090 basic block. This makes using this register always invalid. In cse, we
11091 scan the table to invalidate all entries using this register, but this
11092 is too much work for us. */
11094 for (i
= regno
; i
< endregno
; i
++)
11096 reg_last_set_label
[i
] = label_tick
;
11097 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11098 reg_last_set_invalid
[i
] = 1;
11100 reg_last_set_invalid
[i
] = 0;
11103 /* The value being assigned might refer to X (like in "x++;"). In that
11104 case, we must replace it with (clobber (const_int 0)) to prevent
11106 if (value
&& ! get_last_value_validate (&value
, insn
,
11107 reg_last_set_label
[regno
], 0))
11109 value
= copy_rtx (value
);
11110 if (! get_last_value_validate (&value
, insn
,
11111 reg_last_set_label
[regno
], 1))
11115 /* For the main register being modified, update the value, the mode, the
11116 nonzero bits, and the number of sign bit copies. */
11118 reg_last_set_value
[regno
] = value
;
11122 subst_low_cuid
= INSN_CUID (insn
);
11123 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11124 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11125 reg_last_set_sign_bit_copies
[regno
]
11126 = num_sign_bit_copies (value
, GET_MODE (reg
));
11130 /* Called via note_stores from record_dead_and_set_regs to handle one
11131 SET or CLOBBER in an insn. DATA is the instruction in which the
11132 set is occurring. */
11135 record_dead_and_set_regs_1 (dest
, setter
, data
)
11139 rtx record_dead_insn
= (rtx
) data
;
11141 if (GET_CODE (dest
) == SUBREG
)
11142 dest
= SUBREG_REG (dest
);
11144 if (GET_CODE (dest
) == REG
)
11146 /* If we are setting the whole register, we know its value. Otherwise
11147 show that we don't know the value. We can handle SUBREG in
11149 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11150 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11151 else if (GET_CODE (setter
) == SET
11152 && GET_CODE (SET_DEST (setter
)) == SUBREG
11153 && SUBREG_REG (SET_DEST (setter
)) == dest
11154 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11155 && subreg_lowpart_p (SET_DEST (setter
)))
11156 record_value_for_reg (dest
, record_dead_insn
,
11157 gen_lowpart_for_combine (GET_MODE (dest
),
11158 SET_SRC (setter
)));
11160 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11162 else if (GET_CODE (dest
) == MEM
11163 /* Ignore pushes, they clobber nothing. */
11164 && ! push_operand (dest
, GET_MODE (dest
)))
11165 mem_last_set
= INSN_CUID (record_dead_insn
);
11168 /* Update the records of when each REG was most recently set or killed
11169 for the things done by INSN. This is the last thing done in processing
11170 INSN in the combiner loop.
11172 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11173 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11174 and also the similar information mem_last_set (which insn most recently
11175 modified memory) and last_call_cuid (which insn was the most recent
11176 subroutine call). */
11179 record_dead_and_set_regs (insn
)
11185 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11187 if (REG_NOTE_KIND (link
) == REG_DEAD
11188 && GET_CODE (XEXP (link
, 0)) == REG
)
11190 unsigned int regno
= REGNO (XEXP (link
, 0));
11191 unsigned int endregno
11192 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11193 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11196 for (i
= regno
; i
< endregno
; i
++)
11197 reg_last_death
[i
] = insn
;
11199 else if (REG_NOTE_KIND (link
) == REG_INC
)
11200 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11203 if (GET_CODE (insn
) == CALL_INSN
)
11205 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11206 if (call_used_regs
[i
])
11208 reg_last_set_value
[i
] = 0;
11209 reg_last_set_mode
[i
] = 0;
11210 reg_last_set_nonzero_bits
[i
] = 0;
11211 reg_last_set_sign_bit_copies
[i
] = 0;
11212 reg_last_death
[i
] = 0;
11215 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11218 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11221 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11222 register present in the SUBREG, so for each such SUBREG go back and
11223 adjust nonzero and sign bit information of the registers that are
11224 known to have some zero/sign bits set.
11226 This is needed because when combine blows the SUBREGs away, the
11227 information on zero/sign bits is lost and further combines can be
11228 missed because of that. */
11231 record_promoted_value (insn
, subreg
)
11236 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11237 enum machine_mode mode
= GET_MODE (subreg
);
11239 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11242 for (links
= LOG_LINKS (insn
); links
;)
11244 insn
= XEXP (links
, 0);
11245 set
= single_set (insn
);
11247 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11248 || REGNO (SET_DEST (set
)) != regno
11249 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11251 links
= XEXP (links
, 1);
11255 if (reg_last_set
[regno
] == insn
)
11257 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11258 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11261 if (GET_CODE (SET_SRC (set
)) == REG
)
11263 regno
= REGNO (SET_SRC (set
));
11264 links
= LOG_LINKS (insn
);
11271 /* Scan X for promoted SUBREGs. For each one found,
11272 note what it implies to the registers used in it. */
11275 check_promoted_subreg (insn
, x
)
11279 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11280 && GET_CODE (SUBREG_REG (x
)) == REG
)
11281 record_promoted_value (insn
, x
);
11284 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11287 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11291 check_promoted_subreg (insn
, XEXP (x
, i
));
11295 if (XVEC (x
, i
) != 0)
11296 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11297 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11303 /* Utility routine for the following function. Verify that all the registers
11304 mentioned in *LOC are valid when *LOC was part of a value set when
11305 label_tick == TICK. Return 0 if some are not.
11307 If REPLACE is non-zero, replace the invalid reference with
11308 (clobber (const_int 0)) and return 1. This replacement is useful because
11309 we often can get useful information about the form of a value (e.g., if
11310 it was produced by a shift that always produces -1 or 0) even though
11311 we don't know exactly what registers it was produced from. */
11314 get_last_value_validate (loc
, insn
, tick
, replace
)
11321 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11322 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11325 if (GET_CODE (x
) == REG
)
11327 unsigned int regno
= REGNO (x
);
11328 unsigned int endregno
11329 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11330 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11333 for (j
= regno
; j
< endregno
; j
++)
11334 if (reg_last_set_invalid
[j
]
11335 /* If this is a pseudo-register that was only set once and not
11336 live at the beginning of the function, it is always valid. */
11337 || (! (regno
>= FIRST_PSEUDO_REGISTER
11338 && REG_N_SETS (regno
) == 1
11339 && (! REGNO_REG_SET_P
11340 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))
11341 && reg_last_set_label
[j
] > tick
))
11344 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11350 /* If this is a memory reference, make sure that there were
11351 no stores after it that might have clobbered the value. We don't
11352 have alias info, so we assume any store invalidates it. */
11353 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11354 && INSN_CUID (insn
) <= mem_last_set
)
11357 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11361 for (i
= 0; i
< len
; i
++)
11363 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11364 /* Don't bother with these. They shouldn't occur anyway. */
11368 /* If we haven't found a reason for it to be invalid, it is valid. */
11372 /* Get the last value assigned to X, if known. Some registers
11373 in the value may be replaced with (clobber (const_int 0)) if their value
11374 is known longer known reliably. */
11380 unsigned int regno
;
11383 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11384 then convert it to the desired mode. If this is a paradoxical SUBREG,
11385 we cannot predict what values the "extra" bits might have. */
11386 if (GET_CODE (x
) == SUBREG
11387 && subreg_lowpart_p (x
)
11388 && (GET_MODE_SIZE (GET_MODE (x
))
11389 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11390 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11391 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11393 if (GET_CODE (x
) != REG
)
11397 value
= reg_last_set_value
[regno
];
11399 /* If we don't have a value, or if it isn't for this basic block and
11400 it's either a hard register, set more than once, or it's a live
11401 at the beginning of the function, return 0.
11403 Because if it's not live at the beginnning of the function then the reg
11404 is always set before being used (is never used without being set).
11405 And, if it's set only once, and it's always set before use, then all
11406 uses must have the same last value, even if it's not from this basic
11410 || (reg_last_set_label
[regno
] != label_tick
11411 && (regno
< FIRST_PSEUDO_REGISTER
11412 || REG_N_SETS (regno
) != 1
11413 || (REGNO_REG_SET_P
11414 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))))
11417 /* If the value was set in a later insn than the ones we are processing,
11418 we can't use it even if the register was only set once. */
11419 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11422 /* If the value has all its registers valid, return it. */
11423 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11424 reg_last_set_label
[regno
], 0))
11427 /* Otherwise, make a copy and replace any invalid register with
11428 (clobber (const_int 0)). If that fails for some reason, return 0. */
11430 value
= copy_rtx (value
);
11431 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11432 reg_last_set_label
[regno
], 1))
11438 /* Return nonzero if expression X refers to a REG or to memory
11439 that is set in an instruction more recent than FROM_CUID. */
11442 use_crosses_set_p (x
, from_cuid
)
11446 register const char *fmt
;
11448 register enum rtx_code code
= GET_CODE (x
);
11452 unsigned int regno
= REGNO (x
);
11453 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11454 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11456 #ifdef PUSH_ROUNDING
11457 /* Don't allow uses of the stack pointer to be moved,
11458 because we don't know whether the move crosses a push insn. */
11459 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11462 for (; regno
< endreg
; regno
++)
11463 if (reg_last_set
[regno
]
11464 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11469 if (code
== MEM
&& mem_last_set
> from_cuid
)
11472 fmt
= GET_RTX_FORMAT (code
);
11474 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11479 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11480 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11483 else if (fmt
[i
] == 'e'
11484 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11490 /* Define three variables used for communication between the following
11493 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11494 static int reg_dead_flag
;
11496 /* Function called via note_stores from reg_dead_at_p.
11498 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11499 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11502 reg_dead_at_p_1 (dest
, x
, data
)
11505 void *data ATTRIBUTE_UNUSED
;
11507 unsigned int regno
, endregno
;
11509 if (GET_CODE (dest
) != REG
)
11512 regno
= REGNO (dest
);
11513 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11514 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11516 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11517 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11520 /* Return non-zero if REG is known to be dead at INSN.
11522 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11523 referencing REG, it is dead. If we hit a SET referencing REG, it is
11524 live. Otherwise, see if it is live or dead at the start of the basic
11525 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11526 must be assumed to be always live. */
11529 reg_dead_at_p (reg
, insn
)
11536 /* Set variables for reg_dead_at_p_1. */
11537 reg_dead_regno
= REGNO (reg
);
11538 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11539 ? HARD_REGNO_NREGS (reg_dead_regno
,
11545 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11546 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11548 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11549 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11553 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11554 beginning of function. */
11555 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11556 insn
= prev_nonnote_insn (insn
))
11558 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11560 return reg_dead_flag
== 1 ? 1 : 0;
11562 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11566 /* Get the basic block number that we were in. */
11571 for (block
= 0; block
< n_basic_blocks
; block
++)
11572 if (insn
== BLOCK_HEAD (block
))
11575 if (block
== n_basic_blocks
)
11579 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11580 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11586 /* Note hard registers in X that are used. This code is similar to
11587 that in flow.c, but much simpler since we don't care about pseudos. */
11590 mark_used_regs_combine (x
)
11593 RTX_CODE code
= GET_CODE (x
);
11594 unsigned int regno
;
11606 case ADDR_DIFF_VEC
:
11609 /* CC0 must die in the insn after it is set, so we don't need to take
11610 special note of it here. */
11616 /* If we are clobbering a MEM, mark any hard registers inside the
11617 address as used. */
11618 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11619 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11624 /* A hard reg in a wide mode may really be multiple registers.
11625 If so, mark all of them just like the first. */
11626 if (regno
< FIRST_PSEUDO_REGISTER
)
11628 unsigned int endregno
, r
;
11630 /* None of this applies to the stack, frame or arg pointers */
11631 if (regno
== STACK_POINTER_REGNUM
11632 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11633 || regno
== HARD_FRAME_POINTER_REGNUM
11635 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11636 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11638 || regno
== FRAME_POINTER_REGNUM
)
11641 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11642 for (r
= regno
; r
< endregno
; r
++)
11643 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11649 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11651 register rtx testreg
= SET_DEST (x
);
11653 while (GET_CODE (testreg
) == SUBREG
11654 || GET_CODE (testreg
) == ZERO_EXTRACT
11655 || GET_CODE (testreg
) == SIGN_EXTRACT
11656 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11657 testreg
= XEXP (testreg
, 0);
11659 if (GET_CODE (testreg
) == MEM
)
11660 mark_used_regs_combine (XEXP (testreg
, 0));
11662 mark_used_regs_combine (SET_SRC (x
));
11670 /* Recursively scan the operands of this expression. */
11673 register const char *fmt
= GET_RTX_FORMAT (code
);
11675 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11678 mark_used_regs_combine (XEXP (x
, i
));
11679 else if (fmt
[i
] == 'E')
11683 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11684 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11690 /* Remove register number REGNO from the dead registers list of INSN.
11692 Return the note used to record the death, if there was one. */
11695 remove_death (regno
, insn
)
11696 unsigned int regno
;
11699 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11703 REG_N_DEATHS (regno
)--;
11704 remove_note (insn
, note
);
11710 /* For each register (hardware or pseudo) used within expression X, if its
11711 death is in an instruction with cuid between FROM_CUID (inclusive) and
11712 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11713 list headed by PNOTES.
11715 That said, don't move registers killed by maybe_kill_insn.
11717 This is done when X is being merged by combination into TO_INSN. These
11718 notes will then be distributed as needed. */
11721 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11723 rtx maybe_kill_insn
;
11728 register const char *fmt
;
11729 register int len
, i
;
11730 register enum rtx_code code
= GET_CODE (x
);
11734 unsigned int regno
= REGNO (x
);
11735 register rtx where_dead
= reg_last_death
[regno
];
11736 register rtx before_dead
, after_dead
;
11738 /* Don't move the register if it gets killed in between from and to */
11739 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11740 && ! reg_referenced_p (x
, maybe_kill_insn
))
11743 /* WHERE_DEAD could be a USE insn made by combine, so first we
11744 make sure that we have insns with valid INSN_CUID values. */
11745 before_dead
= where_dead
;
11746 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11747 before_dead
= PREV_INSN (before_dead
);
11749 after_dead
= where_dead
;
11750 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11751 after_dead
= NEXT_INSN (after_dead
);
11753 if (before_dead
&& after_dead
11754 && INSN_CUID (before_dead
) >= from_cuid
11755 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11756 || (where_dead
!= after_dead
11757 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11759 rtx note
= remove_death (regno
, where_dead
);
11761 /* It is possible for the call above to return 0. This can occur
11762 when reg_last_death points to I2 or I1 that we combined with.
11763 In that case make a new note.
11765 We must also check for the case where X is a hard register
11766 and NOTE is a death note for a range of hard registers
11767 including X. In that case, we must put REG_DEAD notes for
11768 the remaining registers in place of NOTE. */
11770 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11771 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11772 > GET_MODE_SIZE (GET_MODE (x
))))
11774 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11775 unsigned int deadend
11776 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11777 GET_MODE (XEXP (note
, 0))));
11778 unsigned int ourend
11779 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11782 for (i
= deadregno
; i
< deadend
; i
++)
11783 if (i
< regno
|| i
>= ourend
)
11784 REG_NOTES (where_dead
)
11785 = gen_rtx_EXPR_LIST (REG_DEAD
,
11786 gen_rtx_REG (reg_raw_mode
[i
], i
),
11787 REG_NOTES (where_dead
));
11790 /* If we didn't find any note, or if we found a REG_DEAD note that
11791 covers only part of the given reg, and we have a multi-reg hard
11792 register, then to be safe we must check for REG_DEAD notes
11793 for each register other than the first. They could have
11794 their own REG_DEAD notes lying around. */
11795 else if ((note
== 0
11797 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11798 < GET_MODE_SIZE (GET_MODE (x
)))))
11799 && regno
< FIRST_PSEUDO_REGISTER
11800 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11802 unsigned int ourend
11803 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11804 unsigned int i
, offset
;
11808 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11812 for (i
= regno
+ offset
; i
< ourend
; i
++)
11813 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11814 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11817 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11819 XEXP (note
, 1) = *pnotes
;
11823 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11825 REG_N_DEATHS (regno
)++;
11831 else if (GET_CODE (x
) == SET
)
11833 rtx dest
= SET_DEST (x
);
11835 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11837 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11838 that accesses one word of a multi-word item, some
11839 piece of everything register in the expression is used by
11840 this insn, so remove any old death. */
11841 /* ??? So why do we test for equality of the sizes? */
11843 if (GET_CODE (dest
) == ZERO_EXTRACT
11844 || GET_CODE (dest
) == STRICT_LOW_PART
11845 || (GET_CODE (dest
) == SUBREG
11846 && (((GET_MODE_SIZE (GET_MODE (dest
))
11847 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11848 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11849 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11851 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11855 /* If this is some other SUBREG, we know it replaces the entire
11856 value, so use that as the destination. */
11857 if (GET_CODE (dest
) == SUBREG
)
11858 dest
= SUBREG_REG (dest
);
11860 /* If this is a MEM, adjust deaths of anything used in the address.
11861 For a REG (the only other possibility), the entire value is
11862 being replaced so the old value is not used in this insn. */
11864 if (GET_CODE (dest
) == MEM
)
11865 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11870 else if (GET_CODE (x
) == CLOBBER
)
11873 len
= GET_RTX_LENGTH (code
);
11874 fmt
= GET_RTX_FORMAT (code
);
11876 for (i
= 0; i
< len
; i
++)
11881 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11882 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11885 else if (fmt
[i
] == 'e')
11886 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11890 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11891 pattern of an insn. X must be a REG. */
11894 reg_bitfield_target_p (x
, body
)
11900 if (GET_CODE (body
) == SET
)
11902 rtx dest
= SET_DEST (body
);
11904 unsigned int regno
, tregno
, endregno
, endtregno
;
11906 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11907 target
= XEXP (dest
, 0);
11908 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11909 target
= SUBREG_REG (XEXP (dest
, 0));
11913 if (GET_CODE (target
) == SUBREG
)
11914 target
= SUBREG_REG (target
);
11916 if (GET_CODE (target
) != REG
)
11919 tregno
= REGNO (target
), regno
= REGNO (x
);
11920 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11921 return target
== x
;
11923 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
11924 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11926 return endregno
> tregno
&& regno
< endtregno
;
11929 else if (GET_CODE (body
) == PARALLEL
)
11930 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11931 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11937 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11938 as appropriate. I3 and I2 are the insns resulting from the combination
11939 insns including FROM (I2 may be zero).
11941 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11942 not need REG_DEAD notes because they are being substituted for. This
11943 saves searching in the most common cases.
11945 Each note in the list is either ignored or placed on some insns, depending
11946 on the type of note. */
11949 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
11953 rtx elim_i2
, elim_i1
;
11955 rtx note
, next_note
;
11958 for (note
= notes
; note
; note
= next_note
)
11960 rtx place
= 0, place2
= 0;
11962 /* If this NOTE references a pseudo register, ensure it references
11963 the latest copy of that register. */
11964 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
11965 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11966 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11968 next_note
= XEXP (note
, 1);
11969 switch (REG_NOTE_KIND (note
))
11973 case REG_EXEC_COUNT
:
11974 /* Doesn't matter much where we put this, as long as it's somewhere.
11975 It is preferable to keep these notes on branches, which is most
11976 likely to be i3. */
11980 case REG_NON_LOCAL_GOTO
:
11981 if (GET_CODE (i3
) == JUMP_INSN
)
11983 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
11989 case REG_EH_REGION
:
11990 /* These notes must remain with the call or trapping instruction. */
11991 if (GET_CODE (i3
) == CALL_INSN
)
11993 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11995 else if (flag_non_call_exceptions
)
11997 if (may_trap_p (i3
))
11999 else if (i2
&& may_trap_p (i2
))
12001 /* ??? Otherwise assume we've combined things such that we
12002 can now prove that the instructions can't trap. Drop the
12003 note in this case. */
12009 case REG_EH_RETHROW
:
12011 /* These notes must remain with the call. It should not be
12012 possible for both I2 and I3 to be a call. */
12013 if (GET_CODE (i3
) == CALL_INSN
)
12015 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12022 /* Any clobbers for i3 may still exist, and so we must process
12023 REG_UNUSED notes from that insn.
12025 Any clobbers from i2 or i1 can only exist if they were added by
12026 recog_for_combine. In that case, recog_for_combine created the
12027 necessary REG_UNUSED notes. Trying to keep any original
12028 REG_UNUSED notes from these insns can cause incorrect output
12029 if it is for the same register as the original i3 dest.
12030 In that case, we will notice that the register is set in i3,
12031 and then add a REG_UNUSED note for the destination of i3, which
12032 is wrong. However, it is possible to have REG_UNUSED notes from
12033 i2 or i1 for register which were both used and clobbered, so
12034 we keep notes from i2 or i1 if they will turn into REG_DEAD
12037 /* If this register is set or clobbered in I3, put the note there
12038 unless there is one already. */
12039 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12041 if (from_insn
!= i3
)
12044 if (! (GET_CODE (XEXP (note
, 0)) == REG
12045 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12046 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12049 /* Otherwise, if this register is used by I3, then this register
12050 now dies here, so we must put a REG_DEAD note here unless there
12052 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12053 && ! (GET_CODE (XEXP (note
, 0)) == REG
12054 ? find_regno_note (i3
, REG_DEAD
,
12055 REGNO (XEXP (note
, 0)))
12056 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12058 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12066 /* These notes say something about results of an insn. We can
12067 only support them if they used to be on I3 in which case they
12068 remain on I3. Otherwise they are ignored.
12070 If the note refers to an expression that is not a constant, we
12071 must also ignore the note since we cannot tell whether the
12072 equivalence is still true. It might be possible to do
12073 slightly better than this (we only have a problem if I2DEST
12074 or I1DEST is present in the expression), but it doesn't
12075 seem worth the trouble. */
12077 if (from_insn
== i3
12078 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12083 case REG_NO_CONFLICT
:
12084 /* These notes say something about how a register is used. They must
12085 be present on any use of the register in I2 or I3. */
12086 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12089 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12099 /* This can show up in several ways -- either directly in the
12100 pattern, or hidden off in the constant pool with (or without?)
12101 a REG_EQUAL note. */
12102 /* ??? Ignore the without-reg_equal-note problem for now. */
12103 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12104 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12105 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12106 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12110 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12111 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12112 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12113 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12124 /* These notes say something about the value of a register prior
12125 to the execution of an insn. It is too much trouble to see
12126 if the note is still correct in all situations. It is better
12127 to simply delete it. */
12131 /* If the insn previously containing this note still exists,
12132 put it back where it was. Otherwise move it to the previous
12133 insn. Adjust the corresponding REG_LIBCALL note. */
12134 if (GET_CODE (from_insn
) != NOTE
)
12138 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12139 place
= prev_real_insn (from_insn
);
12141 XEXP (tem
, 0) = place
;
12142 /* If we're deleting the last remaining instruction of a
12143 libcall sequence, don't add the notes. */
12144 else if (XEXP (note
, 0) == from_insn
)
12150 /* This is handled similarly to REG_RETVAL. */
12151 if (GET_CODE (from_insn
) != NOTE
)
12155 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12156 place
= next_real_insn (from_insn
);
12158 XEXP (tem
, 0) = place
;
12159 /* If we're deleting the last remaining instruction of a
12160 libcall sequence, don't add the notes. */
12161 else if (XEXP (note
, 0) == from_insn
)
12167 /* If the register is used as an input in I3, it dies there.
12168 Similarly for I2, if it is non-zero and adjacent to I3.
12170 If the register is not used as an input in either I3 or I2
12171 and it is not one of the registers we were supposed to eliminate,
12172 there are two possibilities. We might have a non-adjacent I2
12173 or we might have somehow eliminated an additional register
12174 from a computation. For example, we might have had A & B where
12175 we discover that B will always be zero. In this case we will
12176 eliminate the reference to A.
12178 In both cases, we must search to see if we can find a previous
12179 use of A and put the death note there. */
12182 && GET_CODE (from_insn
) == CALL_INSN
12183 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12185 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12187 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12188 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12191 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12192 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12197 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12199 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12201 if (! INSN_P (tem
))
12203 if (tem
== bb
->head
)
12208 /* If the register is being set at TEM, see if that is all
12209 TEM is doing. If so, delete TEM. Otherwise, make this
12210 into a REG_UNUSED note instead. */
12211 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12213 rtx set
= single_set (tem
);
12214 rtx inner_dest
= 0;
12216 rtx cc0_setter
= NULL_RTX
;
12220 for (inner_dest
= SET_DEST (set
);
12221 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12222 || GET_CODE (inner_dest
) == SUBREG
12223 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12224 inner_dest
= XEXP (inner_dest
, 0))
12227 /* Verify that it was the set, and not a clobber that
12228 modified the register.
12230 CC0 targets must be careful to maintain setter/user
12231 pairs. If we cannot delete the setter due to side
12232 effects, mark the user with an UNUSED note instead
12235 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12236 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12238 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12239 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12240 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12244 /* Move the notes and links of TEM elsewhere.
12245 This might delete other dead insns recursively.
12246 First set the pattern to something that won't use
12249 PATTERN (tem
) = pc_rtx
;
12251 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12252 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12253 distribute_links (LOG_LINKS (tem
));
12255 PUT_CODE (tem
, NOTE
);
12256 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12257 NOTE_SOURCE_FILE (tem
) = 0;
12260 /* Delete the setter too. */
12263 PATTERN (cc0_setter
) = pc_rtx
;
12265 distribute_notes (REG_NOTES (cc0_setter
),
12266 cc0_setter
, cc0_setter
,
12267 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12268 distribute_links (LOG_LINKS (cc0_setter
));
12270 PUT_CODE (cc0_setter
, NOTE
);
12271 NOTE_LINE_NUMBER (cc0_setter
)
12272 = NOTE_INSN_DELETED
;
12273 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12277 /* If the register is both set and used here, put the
12278 REG_DEAD note here, but place a REG_UNUSED note
12279 here too unless there already is one. */
12280 else if (reg_referenced_p (XEXP (note
, 0),
12285 if (! find_regno_note (tem
, REG_UNUSED
,
12286 REGNO (XEXP (note
, 0))))
12288 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12293 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12295 /* If there isn't already a REG_UNUSED note, put one
12297 if (! find_regno_note (tem
, REG_UNUSED
,
12298 REGNO (XEXP (note
, 0))))
12303 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12304 || (GET_CODE (tem
) == CALL_INSN
12305 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12309 /* If we are doing a 3->2 combination, and we have a
12310 register which formerly died in i3 and was not used
12311 by i2, which now no longer dies in i3 and is used in
12312 i2 but does not die in i2, and place is between i2
12313 and i3, then we may need to move a link from place to
12315 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12316 && INSN_CUID (place
) > INSN_CUID (i2
)
12318 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12319 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12321 rtx links
= LOG_LINKS (place
);
12322 LOG_LINKS (place
) = 0;
12323 distribute_links (links
);
12328 if (tem
== bb
->head
)
12332 /* We haven't found an insn for the death note and it
12333 is still a REG_DEAD note, but we have hit the beginning
12334 of the block. If the existing life info says the reg
12335 was dead, there's nothing left to do. Otherwise, we'll
12336 need to do a global life update after combine. */
12337 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12338 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12339 REGNO (XEXP (note
, 0))))
12341 SET_BIT (refresh_blocks
, this_basic_block
);
12346 /* If the register is set or already dead at PLACE, we needn't do
12347 anything with this note if it is still a REG_DEAD note.
12348 We can here if it is set at all, not if is it totally replace,
12349 which is what `dead_or_set_p' checks, so also check for it being
12352 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12354 unsigned int regno
= REGNO (XEXP (note
, 0));
12356 /* Similarly, if the instruction on which we want to place
12357 the note is a noop, we'll need do a global live update
12358 after we remove them in delete_noop_moves. */
12359 if (noop_move_p (place
))
12361 SET_BIT (refresh_blocks
, this_basic_block
);
12365 if (dead_or_set_p (place
, XEXP (note
, 0))
12366 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12368 /* Unless the register previously died in PLACE, clear
12369 reg_last_death. [I no longer understand why this is
12371 if (reg_last_death
[regno
] != place
)
12372 reg_last_death
[regno
] = 0;
12376 reg_last_death
[regno
] = place
;
12378 /* If this is a death note for a hard reg that is occupying
12379 multiple registers, ensure that we are still using all
12380 parts of the object. If we find a piece of the object
12381 that is unused, we must arrange for an appropriate REG_DEAD
12382 note to be added for it. However, we can't just emit a USE
12383 and tag the note to it, since the register might actually
12384 be dead; so we recourse, and the recursive call then finds
12385 the previous insn that used this register. */
12387 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12388 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12390 unsigned int endregno
12391 = regno
+ HARD_REGNO_NREGS (regno
,
12392 GET_MODE (XEXP (note
, 0)));
12396 for (i
= regno
; i
< endregno
; i
++)
12397 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12398 && ! find_regno_fusage (place
, USE
, i
))
12399 || dead_or_set_regno_p (place
, i
))
12404 /* Put only REG_DEAD notes for pieces that are
12405 not already dead or set. */
12407 for (i
= regno
; i
< endregno
;
12408 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12410 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12411 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12413 if (! dead_or_set_p (place
, piece
)
12414 && ! reg_bitfield_target_p (piece
,
12418 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12420 distribute_notes (new_note
, place
, place
,
12421 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12423 else if (! refers_to_regno_p (i
, i
+ 1,
12424 PATTERN (place
), 0)
12425 && ! find_regno_fusage (place
, USE
, i
))
12426 for (tem
= PREV_INSN (place
); ;
12427 tem
= PREV_INSN (tem
))
12429 if (! INSN_P (tem
))
12431 if (tem
== bb
->head
)
12433 SET_BIT (refresh_blocks
,
12440 if (dead_or_set_p (tem
, piece
)
12441 || reg_bitfield_target_p (piece
,
12445 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12460 /* Any other notes should not be present at this point in the
12467 XEXP (note
, 1) = REG_NOTES (place
);
12468 REG_NOTES (place
) = note
;
12470 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12471 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12472 && GET_CODE (XEXP (note
, 0)) == REG
)
12473 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12477 if ((REG_NOTE_KIND (note
) == REG_DEAD
12478 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12479 && GET_CODE (XEXP (note
, 0)) == REG
)
12480 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12482 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12483 REG_NOTE_KIND (note
),
12485 REG_NOTES (place2
));
12490 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12491 I3, I2, and I1 to new locations. This is also called in one case to
12492 add a link pointing at I3 when I3's destination is changed. */
12495 distribute_links (links
)
12498 rtx link
, next_link
;
12500 for (link
= links
; link
; link
= next_link
)
12506 next_link
= XEXP (link
, 1);
12508 /* If the insn that this link points to is a NOTE or isn't a single
12509 set, ignore it. In the latter case, it isn't clear what we
12510 can do other than ignore the link, since we can't tell which
12511 register it was for. Such links wouldn't be used by combine
12514 It is not possible for the destination of the target of the link to
12515 have been changed by combine. The only potential of this is if we
12516 replace I3, I2, and I1 by I3 and I2. But in that case the
12517 destination of I2 also remains unchanged. */
12519 if (GET_CODE (XEXP (link
, 0)) == NOTE
12520 || (set
= single_set (XEXP (link
, 0))) == 0)
12523 reg
= SET_DEST (set
);
12524 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12525 || GET_CODE (reg
) == SIGN_EXTRACT
12526 || GET_CODE (reg
) == STRICT_LOW_PART
)
12527 reg
= XEXP (reg
, 0);
12529 /* A LOG_LINK is defined as being placed on the first insn that uses
12530 a register and points to the insn that sets the register. Start
12531 searching at the next insn after the target of the link and stop
12532 when we reach a set of the register or the end of the basic block.
12534 Note that this correctly handles the link that used to point from
12535 I3 to I2. Also note that not much searching is typically done here
12536 since most links don't point very far away. */
12538 for (insn
= NEXT_INSN (XEXP (link
, 0));
12539 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12540 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12541 insn
= NEXT_INSN (insn
))
12542 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12544 if (reg_referenced_p (reg
, PATTERN (insn
)))
12548 else if (GET_CODE (insn
) == CALL_INSN
12549 && find_reg_fusage (insn
, USE
, reg
))
12555 /* If we found a place to put the link, place it there unless there
12556 is already a link to the same insn as LINK at that point. */
12562 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12563 if (XEXP (link2
, 0) == XEXP (link
, 0))
12568 XEXP (link
, 1) = LOG_LINKS (place
);
12569 LOG_LINKS (place
) = link
;
12571 /* Set added_links_insn to the earliest insn we added a
12573 if (added_links_insn
== 0
12574 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12575 added_links_insn
= place
;
12581 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12587 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12588 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12589 insn
= NEXT_INSN (insn
);
12591 if (INSN_UID (insn
) > max_uid_cuid
)
12594 return INSN_CUID (insn
);
12598 dump_combine_stats (file
)
12603 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12604 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12608 dump_combine_total_stats (file
)
12613 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12614 total_attempts
, total_merges
, total_extras
, total_successes
);