1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "rtl.h" /* stdio.h must precede rtl.h for FFS. */
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
85 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
87 #include "insn-flags.h"
88 #include "insn-codes.h"
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
118 /* Define a default value for REVERSIBLE_CC_MODE.
119 We can never assume that a condition code mode is safe to reverse unless
120 the md tells us so. */
121 #ifndef REVERSIBLE_CC_MODE
122 #define REVERSIBLE_CC_MODE(MODE) 0
125 /* Vector mapping INSN_UIDs to cuids.
126 The cuids are like uids but increase monotonically always.
127 Combine always uses cuids so that it can compare them.
128 But actually renumbering the uids, which we used to do,
129 proves to be a bad idea because it makes it hard to compare
130 the dumps produced by earlier passes with those from later passes. */
132 static int *uid_cuid
;
133 static int max_uid_cuid
;
135 /* Get the cuid of an insn. */
137 #define INSN_CUID(INSN) \
138 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
140 /* Maximum register number, which is the size of the tables below. */
142 static int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx
*reg_last_death
;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx
*reg_last_set
;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set
;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid
;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn
;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn
;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid
;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs
;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn
;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block
;
198 /* The next group of arrays allows the recording of the last value assigned
199 to (hard or pseudo) register n. We use this information to see if a
200 operation being processed is redundant given a prior operation performed
201 on the register. For example, an `and' with a constant is redundant if
202 all the zero bits are already known to be turned off.
204 We use an approach similar to that used by cse, but change it in the
207 (1) We do not want to reinitialize at each label.
208 (2) It is useful, but not critical, to know the actual value assigned
209 to a register. Often just its form is helpful.
211 Therefore, we maintain the following arrays:
213 reg_last_set_value the last value assigned
214 reg_last_set_label records the value of label_tick when the
215 register was assigned
216 reg_last_set_table_tick records the value of label_tick when a
217 value using the register is assigned
218 reg_last_set_invalid set to non-zero when it is not valid
219 to use the value of this register in some
222 To understand the usage of these tables, it is important to understand
223 the distinction between the value in reg_last_set_value being valid
224 and the register being validly contained in some other expression in the
227 Entry I in reg_last_set_value is valid if it is non-zero, and either
228 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
230 Register I may validly appear in any expression returned for the value
231 of another register if reg_n_sets[i] is 1. It may also appear in the
232 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
233 reg_last_set_invalid[j] is zero.
235 If an expression is found in the table containing a register which may
236 not validly appear in an expression, the register is replaced by
237 something that won't match, (clobber (const_int 0)).
239 reg_last_set_invalid[i] is set non-zero when register I is being assigned
240 to and reg_last_set_table_tick[i] == label_tick. */
242 /* Record last value assigned to (hard or pseudo) register n. */
244 static rtx
*reg_last_set_value
;
246 /* Record the value of label_tick when the value for register n is placed in
247 reg_last_set_value[n]. */
249 static int *reg_last_set_label
;
251 /* Record the value of label_tick when an expression involving register n
252 is placed in reg_last_set_value. */
254 static int *reg_last_set_table_tick
;
256 /* Set non-zero if references to register n in expressions should not be
259 static char *reg_last_set_invalid
;
261 /* Incremented for each label. */
263 static int label_tick
;
265 /* Some registers that are set more than once and used in more than one
266 basic block are nevertheless always set in similar ways. For example,
267 a QImode register may be loaded from memory in two places on a machine
268 where byte loads zero extend.
270 We record in the following array what we know about the nonzero
271 bits of a register, specifically which bits are known to be zero.
273 If an entry is zero, it means that we don't know anything special. */
275 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
277 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
278 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
280 static enum machine_mode nonzero_bits_mode
;
282 /* Nonzero if we know that a register has some leading bits that are always
283 equal to the sign bit. */
285 static char *reg_sign_bit_copies
;
287 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
288 It is zero while computing them and after combine has completed. This
289 former test prevents propagating values based on previously set values,
290 which can be incorrect if a variable is modified in a loop. */
292 static int nonzero_sign_valid
;
294 /* These arrays are maintained in parallel with reg_last_set_value
295 and are used to store the mode in which the register was last set,
296 the bits that were known to be zero when it was last set, and the
297 number of sign bits copies it was known to have when it was last set. */
299 static enum machine_mode
*reg_last_set_mode
;
300 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
301 static char *reg_last_set_sign_bit_copies
;
303 /* Record one modification to rtl structure
304 to be undone by storing old_contents into *where.
305 is_int is 1 if the contents are an int. */
311 union {rtx r
; int i
;} old_contents
;
312 union {rtx
*r
; int *i
;} where
;
315 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
316 num_undo says how many are currently recorded.
318 storage is nonzero if we must undo the allocation of new storage.
319 The value of storage is what to pass to obfree.
321 other_insn is nonzero if we have modified some other insn in the process
322 of working on subst_insn. It must be verified too.
324 previous_undos is the value of undobuf.undos when we started processing
325 this substitution. This will prevent gen_rtx_combine from re-used a piece
326 from the previous expression. Doing so can produce circular rtl
334 struct undo
*previous_undos
;
338 static struct undobuf undobuf
;
340 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
341 insn. The substitution can be undone by undo_all. If INTO is already
342 set to NEWVAL, do not record this change. Because computing NEWVAL might
343 also call SUBST, we have to compute it before we put anything into
346 #define SUBST(INTO, NEWVAL) \
347 do { rtx _new = (NEWVAL); \
351 _buf = undobuf.frees, undobuf.frees = _buf->next; \
353 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
356 _buf->where.r = &INTO; \
357 _buf->old_contents.r = INTO; \
359 if (_buf->old_contents.r == INTO) \
360 _buf->next = undobuf.frees, undobuf.frees = _buf; \
362 _buf->next = undobuf.undos, undobuf.undos = _buf; \
365 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
366 for the value of a HOST_WIDE_INT value (including CONST_INT) is
369 #define SUBST_INT(INTO, NEWVAL) \
370 do { struct undo *_buf; \
373 _buf = undobuf.frees, undobuf.frees = _buf->next; \
375 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
378 _buf->where.i = (int *) &INTO; \
379 _buf->old_contents.i = INTO; \
381 if (_buf->old_contents.i == INTO) \
382 _buf->next = undobuf.frees, undobuf.frees = _buf; \
384 _buf->next = undobuf.undos, undobuf.undos = _buf; \
387 /* Number of times the pseudo being substituted for
388 was found and replaced. */
390 static int n_occurrences
;
392 static void init_reg_last_arrays
PROTO((void));
393 static void setup_incoming_promotions
PROTO((void));
394 static void set_nonzero_bits_and_sign_copies
PROTO((rtx
, rtx
));
395 static int can_combine_p
PROTO((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
396 static int sets_function_arg_p
PROTO((rtx
));
397 static int combinable_i3pat
PROTO((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
398 static rtx try_combine
PROTO((rtx
, rtx
, rtx
));
399 static void undo_all
PROTO((void));
400 static rtx
*find_split_point
PROTO((rtx
*, rtx
));
401 static rtx subst
PROTO((rtx
, rtx
, rtx
, int, int));
402 static rtx simplify_rtx
PROTO((rtx
, enum machine_mode
, int, int));
403 static rtx simplify_if_then_else
PROTO((rtx
));
404 static rtx simplify_set
PROTO((rtx
));
405 static rtx simplify_logical
PROTO((rtx
, int));
406 static rtx expand_compound_operation
PROTO((rtx
));
407 static rtx expand_field_assignment
PROTO((rtx
));
408 static rtx make_extraction
PROTO((enum machine_mode
, rtx
, int, rtx
, int,
410 static rtx extract_left_shift
PROTO((rtx
, int));
411 static rtx make_compound_operation
PROTO((rtx
, enum rtx_code
));
412 static int get_pos_from_mask
PROTO((unsigned HOST_WIDE_INT
, int *));
413 static rtx force_to_mode
PROTO((rtx
, enum machine_mode
,
414 unsigned HOST_WIDE_INT
, rtx
, int));
415 static rtx if_then_else_cond
PROTO((rtx
, rtx
*, rtx
*));
416 static rtx known_cond
PROTO((rtx
, enum rtx_code
, rtx
, rtx
));
417 static int rtx_equal_for_field_assignment_p
PROTO((rtx
, rtx
));
418 static rtx make_field_assignment
PROTO((rtx
));
419 static rtx apply_distributive_law
PROTO((rtx
));
420 static rtx simplify_and_const_int
PROTO((rtx
, enum machine_mode
, rtx
,
421 unsigned HOST_WIDE_INT
));
422 static unsigned HOST_WIDE_INT nonzero_bits
PROTO((rtx
, enum machine_mode
));
423 static int num_sign_bit_copies
PROTO((rtx
, enum machine_mode
));
424 static int merge_outer_ops
PROTO((enum rtx_code
*, HOST_WIDE_INT
*,
425 enum rtx_code
, HOST_WIDE_INT
,
426 enum machine_mode
, int *));
427 static rtx simplify_shift_const
PROTO((rtx
, enum rtx_code
, enum machine_mode
,
429 static int recog_for_combine
PROTO((rtx
*, rtx
, rtx
*));
430 static rtx gen_lowpart_for_combine
PROTO((enum machine_mode
, rtx
));
431 static rtx gen_rtx_combine
PVPROTO((enum rtx_code code
, enum machine_mode mode
,
433 static rtx gen_binary
PROTO((enum rtx_code
, enum machine_mode
,
435 static rtx gen_unary
PROTO((enum rtx_code
, enum machine_mode
,
436 enum machine_mode
, rtx
));
437 static enum rtx_code simplify_comparison
PROTO((enum rtx_code
, rtx
*, rtx
*));
438 static int reversible_comparison_p
PROTO((rtx
));
439 static void update_table_tick
PROTO((rtx
));
440 static void record_value_for_reg
PROTO((rtx
, rtx
, rtx
));
441 static void record_dead_and_set_regs_1
PROTO((rtx
, rtx
));
442 static void record_dead_and_set_regs
PROTO((rtx
));
443 static int get_last_value_validate
PROTO((rtx
*, rtx
, int, int));
444 static rtx get_last_value
PROTO((rtx
));
445 static int use_crosses_set_p
PROTO((rtx
, int));
446 static void reg_dead_at_p_1
PROTO((rtx
, rtx
));
447 static int reg_dead_at_p
PROTO((rtx
, rtx
));
448 static void move_deaths
PROTO((rtx
, rtx
, int, rtx
, rtx
*));
449 static int reg_bitfield_target_p
PROTO((rtx
, rtx
));
450 static void distribute_notes
PROTO((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
451 static void distribute_links
PROTO((rtx
));
452 static void mark_used_regs_combine
PROTO((rtx
));
453 static int insn_cuid
PROTO((rtx
));
455 /* Main entry point for combiner. F is the first insn of the function.
456 NREGS is the first unused pseudo-reg number. */
459 combine_instructions (f
, nregs
)
463 register rtx insn
, next
;
468 register rtx links
, nextlinks
;
470 combine_attempts
= 0;
473 combine_successes
= 0;
474 undobuf
.undos
= undobuf
.previous_undos
= 0;
476 combine_max_regno
= nregs
;
479 = (unsigned HOST_WIDE_INT
*) alloca (nregs
* sizeof (HOST_WIDE_INT
));
480 reg_sign_bit_copies
= (char *) alloca (nregs
* sizeof (char));
482 bzero ((char *) reg_nonzero_bits
, nregs
* sizeof (HOST_WIDE_INT
));
483 bzero (reg_sign_bit_copies
, nregs
* sizeof (char));
485 reg_last_death
= (rtx
*) alloca (nregs
* sizeof (rtx
));
486 reg_last_set
= (rtx
*) alloca (nregs
* sizeof (rtx
));
487 reg_last_set_value
= (rtx
*) alloca (nregs
* sizeof (rtx
));
488 reg_last_set_table_tick
= (int *) alloca (nregs
* sizeof (int));
489 reg_last_set_label
= (int *) alloca (nregs
* sizeof (int));
490 reg_last_set_invalid
= (char *) alloca (nregs
* sizeof (char));
492 = (enum machine_mode
*) alloca (nregs
* sizeof (enum machine_mode
));
493 reg_last_set_nonzero_bits
494 = (unsigned HOST_WIDE_INT
*) alloca (nregs
* sizeof (HOST_WIDE_INT
));
495 reg_last_set_sign_bit_copies
496 = (char *) alloca (nregs
* sizeof (char));
498 init_reg_last_arrays ();
500 init_recog_no_volatile ();
502 /* Compute maximum uid value so uid_cuid can be allocated. */
504 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
505 if (INSN_UID (insn
) > i
)
508 uid_cuid
= (int *) alloca ((i
+ 1) * sizeof (int));
511 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
513 /* Don't use reg_nonzero_bits when computing it. This can cause problems
514 when, for example, we have j <<= 1 in a loop. */
516 nonzero_sign_valid
= 0;
518 /* Compute the mapping from uids to cuids.
519 Cuids are numbers assigned to insns, like uids,
520 except that cuids increase monotonically through the code.
522 Scan all SETs and see if we can deduce anything about what
523 bits are known to be zero for some registers and how many copies
524 of the sign bit are known to exist for those registers.
526 Also set any known values so that we can use it while searching
527 for what bits are known to be set. */
531 /* We need to initialize it here, because record_dead_and_set_regs may call
533 subst_prev_insn
= NULL_RTX
;
535 setup_incoming_promotions ();
537 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
539 uid_cuid
[INSN_UID (insn
)] = ++i
;
543 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
545 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
);
546 record_dead_and_set_regs (insn
);
549 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
550 if (REG_NOTE_KIND (links
) == REG_INC
)
551 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
);
555 if (GET_CODE (insn
) == CODE_LABEL
)
559 nonzero_sign_valid
= 1;
561 /* Now scan all the insns in forward order. */
563 this_basic_block
= -1;
567 init_reg_last_arrays ();
568 setup_incoming_promotions ();
570 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
574 /* If INSN starts a new basic block, update our basic block number. */
575 if (this_basic_block
+ 1 < n_basic_blocks
576 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
579 if (GET_CODE (insn
) == CODE_LABEL
)
582 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
584 /* Try this insn with each insn it links back to. */
586 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
587 if ((next
= try_combine (insn
, XEXP (links
, 0), NULL_RTX
)) != 0)
590 /* Try each sequence of three linked insns ending with this one. */
592 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
593 for (nextlinks
= LOG_LINKS (XEXP (links
, 0)); nextlinks
;
594 nextlinks
= XEXP (nextlinks
, 1))
595 if ((next
= try_combine (insn
, XEXP (links
, 0),
596 XEXP (nextlinks
, 0))) != 0)
600 /* Try to combine a jump insn that uses CC0
601 with a preceding insn that sets CC0, and maybe with its
602 logical predecessor as well.
603 This is how we make decrement-and-branch insns.
604 We need this special code because data flow connections
605 via CC0 do not get entered in LOG_LINKS. */
607 if (GET_CODE (insn
) == JUMP_INSN
608 && (prev
= prev_nonnote_insn (insn
)) != 0
609 && GET_CODE (prev
) == INSN
610 && sets_cc0_p (PATTERN (prev
)))
612 if ((next
= try_combine (insn
, prev
, NULL_RTX
)) != 0)
615 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
616 nextlinks
= XEXP (nextlinks
, 1))
617 if ((next
= try_combine (insn
, prev
,
618 XEXP (nextlinks
, 0))) != 0)
622 /* Do the same for an insn that explicitly references CC0. */
623 if (GET_CODE (insn
) == INSN
624 && (prev
= prev_nonnote_insn (insn
)) != 0
625 && GET_CODE (prev
) == INSN
626 && sets_cc0_p (PATTERN (prev
))
627 && GET_CODE (PATTERN (insn
)) == SET
628 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
630 if ((next
= try_combine (insn
, prev
, NULL_RTX
)) != 0)
633 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
634 nextlinks
= XEXP (nextlinks
, 1))
635 if ((next
= try_combine (insn
, prev
,
636 XEXP (nextlinks
, 0))) != 0)
640 /* Finally, see if any of the insns that this insn links to
641 explicitly references CC0. If so, try this insn, that insn,
642 and its predecessor if it sets CC0. */
643 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
644 if (GET_CODE (XEXP (links
, 0)) == INSN
645 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
646 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
647 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
648 && GET_CODE (prev
) == INSN
649 && sets_cc0_p (PATTERN (prev
))
650 && (next
= try_combine (insn
, XEXP (links
, 0), prev
)) != 0)
654 /* Try combining an insn with two different insns whose results it
656 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
657 for (nextlinks
= XEXP (links
, 1); nextlinks
;
658 nextlinks
= XEXP (nextlinks
, 1))
659 if ((next
= try_combine (insn
, XEXP (links
, 0),
660 XEXP (nextlinks
, 0))) != 0)
663 if (GET_CODE (insn
) != NOTE
)
664 record_dead_and_set_regs (insn
);
671 total_attempts
+= combine_attempts
;
672 total_merges
+= combine_merges
;
673 total_extras
+= combine_extras
;
674 total_successes
+= combine_successes
;
676 nonzero_sign_valid
= 0;
678 /* Make recognizer allow volatile MEMs again. */
682 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
685 init_reg_last_arrays ()
687 int nregs
= combine_max_regno
;
689 bzero ((char *) reg_last_death
, nregs
* sizeof (rtx
));
690 bzero ((char *) reg_last_set
, nregs
* sizeof (rtx
));
691 bzero ((char *) reg_last_set_value
, nregs
* sizeof (rtx
));
692 bzero ((char *) reg_last_set_table_tick
, nregs
* sizeof (int));
693 bzero ((char *) reg_last_set_label
, nregs
* sizeof (int));
694 bzero (reg_last_set_invalid
, nregs
* sizeof (char));
695 bzero ((char *) reg_last_set_mode
, nregs
* sizeof (enum machine_mode
));
696 bzero ((char *) reg_last_set_nonzero_bits
, nregs
* sizeof (HOST_WIDE_INT
));
697 bzero (reg_last_set_sign_bit_copies
, nregs
* sizeof (char));
700 /* Set up any promoted values for incoming argument registers. */
703 setup_incoming_promotions ()
705 #ifdef PROMOTE_FUNCTION_ARGS
708 enum machine_mode mode
;
710 rtx first
= get_insns ();
712 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
713 if (FUNCTION_ARG_REGNO_P (regno
)
714 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
717 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
720 gen_rtx_CLOBBER (mode
, const0_rtx
)));
725 /* Called via note_stores. If X is a pseudo that is narrower than
726 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
728 If we are setting only a portion of X and we can't figure out what
729 portion, assume all bits will be used since we don't know what will
732 Similarly, set how many bits of X are known to be copies of the sign bit
733 at all locations in the function. This is the smallest number implied
737 set_nonzero_bits_and_sign_copies (x
, set
)
743 if (GET_CODE (x
) == REG
744 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
745 /* If this register is undefined at the start of the file, we can't
746 say what its contents were. */
747 && ! REGNO_REG_SET_P (basic_block_live_at_start
[0], REGNO (x
))
748 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
750 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
752 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
753 reg_sign_bit_copies
[REGNO (x
)] = 1;
757 /* If this is a complex assignment, see if we can convert it into a
758 simple assignment. */
759 set
= expand_field_assignment (set
);
761 /* If this is a simple assignment, or we have a paradoxical SUBREG,
762 set what we know about X. */
764 if (SET_DEST (set
) == x
765 || (GET_CODE (SET_DEST (set
)) == SUBREG
766 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
767 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
768 && SUBREG_REG (SET_DEST (set
)) == x
))
770 rtx src
= SET_SRC (set
);
772 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
773 /* If X is narrower than a word and SRC is a non-negative
774 constant that would appear negative in the mode of X,
775 sign-extend it for use in reg_nonzero_bits because some
776 machines (maybe most) will actually do the sign-extension
777 and this is the conservative approach.
779 ??? For 2.5, try to tighten up the MD files in this regard
780 instead of this kludge. */
782 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
783 && GET_CODE (src
) == CONST_INT
785 && 0 != (INTVAL (src
)
787 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
788 src
= GEN_INT (INTVAL (src
)
789 | ((HOST_WIDE_INT
) (-1)
790 << GET_MODE_BITSIZE (GET_MODE (x
))));
793 reg_nonzero_bits
[REGNO (x
)]
794 |= nonzero_bits (src
, nonzero_bits_mode
);
795 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
796 if (reg_sign_bit_copies
[REGNO (x
)] == 0
797 || reg_sign_bit_copies
[REGNO (x
)] > num
)
798 reg_sign_bit_copies
[REGNO (x
)] = num
;
802 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
803 reg_sign_bit_copies
[REGNO (x
)] = 1;
808 /* See if INSN can be combined into I3. PRED and SUCC are optionally
809 insns that were previously combined into I3 or that will be combined
810 into the merger of INSN and I3.
812 Return 0 if the combination is not allowed for any reason.
814 If the combination is allowed, *PDEST will be set to the single
815 destination of INSN and *PSRC to the single source, and this function
819 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
822 rtx pred ATTRIBUTE_UNUSED
;
827 rtx set
= 0, src
, dest
;
832 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
833 && next_active_insn (succ
) == i3
)
834 : next_active_insn (insn
) == i3
);
836 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
837 or a PARALLEL consisting of such a SET and CLOBBERs.
839 If INSN has CLOBBER parallel parts, ignore them for our processing.
840 By definition, these happen during the execution of the insn. When it
841 is merged with another insn, all bets are off. If they are, in fact,
842 needed and aren't also supplied in I3, they may be added by
843 recog_for_combine. Otherwise, it won't match.
845 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
848 Get the source and destination of INSN. If more than one, can't
851 if (GET_CODE (PATTERN (insn
)) == SET
)
852 set
= PATTERN (insn
);
853 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
854 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
856 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
858 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
860 switch (GET_CODE (elt
))
862 /* This is important to combine floating point insns
865 /* Combining an isolated USE doesn't make sense.
866 We depend here on combinable_i3_pat to reject them. */
867 /* The code below this loop only verifies that the inputs of
868 the SET in INSN do not change. We call reg_set_between_p
869 to verify that the REG in the USE does not change betweeen
871 If the USE in INSN was for a pseudo register, the matching
872 insn pattern will likely match any register; combining this
873 with any other USE would only be safe if we knew that the
874 used registers have identical values, or if there was
875 something to tell them apart, e.g. different modes. For
876 now, we forgo such compilcated tests and simply disallow
877 combining of USES of pseudo registers with any other USE. */
878 if (GET_CODE (XEXP (elt
, 0)) == REG
879 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
881 rtx i3pat
= PATTERN (i3
);
882 int i
= XVECLEN (i3pat
, 0) - 1;
883 int regno
= REGNO (XEXP (elt
, 0));
886 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
887 if (GET_CODE (i3elt
) == USE
888 && GET_CODE (XEXP (i3elt
, 0)) == REG
889 && (REGNO (XEXP (i3elt
, 0)) == regno
890 ? reg_set_between_p (XEXP (elt
, 0),
891 PREV_INSN (insn
), i3
)
892 : regno
>= FIRST_PSEUDO_REGISTER
))
899 /* We can ignore CLOBBERs. */
904 /* Ignore SETs whose result isn't used but not those that
905 have side-effects. */
906 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
907 && ! side_effects_p (elt
))
910 /* If we have already found a SET, this is a second one and
911 so we cannot combine with this insn. */
919 /* Anything else means we can't combine. */
925 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
926 so don't do anything with it. */
927 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
936 set
= expand_field_assignment (set
);
937 src
= SET_SRC (set
), dest
= SET_DEST (set
);
939 /* Don't eliminate a store in the stack pointer. */
940 if (dest
== stack_pointer_rtx
941 /* If we couldn't eliminate a field assignment, we can't combine. */
942 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
943 /* Don't combine with an insn that sets a register to itself if it has
944 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
945 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
946 /* Can't merge a function call. */
947 || GET_CODE (src
) == CALL
948 /* Don't eliminate a function call argument. */
949 || (GET_CODE (i3
) == CALL_INSN
950 && (find_reg_fusage (i3
, USE
, dest
)
951 || (GET_CODE (dest
) == REG
952 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
953 && global_regs
[REGNO (dest
)])))
954 /* Don't substitute into an incremented register. */
955 || FIND_REG_INC_NOTE (i3
, dest
)
956 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
958 /* Don't combine the end of a libcall into anything. */
959 /* ??? This gives worse code, and appears to be unnecessary, since no
960 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
961 use REG_RETVAL notes for noconflict blocks, but other code here
962 makes sure that those insns don't disappear. */
963 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
965 /* Make sure that DEST is not used after SUCC but before I3. */
966 || (succ
&& ! all_adjacent
967 && reg_used_between_p (dest
, succ
, i3
))
968 /* Make sure that the value that is to be substituted for the register
969 does not use any registers whose values alter in between. However,
970 If the insns are adjacent, a use can't cross a set even though we
971 think it might (this can happen for a sequence of insns each setting
972 the same destination; reg_last_set of that register might point to
973 a NOTE). If INSN has a REG_EQUIV note, the register is always
974 equivalent to the memory so the substitution is valid even if there
975 are intervening stores. Also, don't move a volatile asm or
976 UNSPEC_VOLATILE across any other insns. */
978 && (((GET_CODE (src
) != MEM
979 || ! find_reg_note (insn
, REG_EQUIV
, src
))
980 && use_crosses_set_p (src
, INSN_CUID (insn
)))
981 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
982 || GET_CODE (src
) == UNSPEC_VOLATILE
))
983 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
984 better register allocation by not doing the combine. */
985 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
986 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
987 /* Don't combine across a CALL_INSN, because that would possibly
988 change whether the life span of some REGs crosses calls or not,
989 and it is a pain to update that information.
990 Exception: if source is a constant, moving it later can't hurt.
991 Accept that special case, because it helps -fforce-addr a lot. */
992 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
995 /* DEST must either be a REG or CC0. */
996 if (GET_CODE (dest
) == REG
)
998 /* If register alignment is being enforced for multi-word items in all
999 cases except for parameters, it is possible to have a register copy
1000 insn referencing a hard register that is not allowed to contain the
1001 mode being copied and which would not be valid as an operand of most
1002 insns. Eliminate this problem by not combining with such an insn.
1004 Also, on some machines we don't want to extend the life of a hard
1007 This is the same test done in can_combine except that we don't test
1008 if SRC is a CALL operation to permit a hard register with
1009 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1012 if (GET_CODE (src
) == REG
1013 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1014 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1015 /* Don't extend the life of a hard register unless it is
1016 user variable (if we have few registers) or it can't
1017 fit into the desired register (meaning something special
1019 Also avoid substituting a return register into I3, because
1020 reload can't handle a conflict with constraints of other
1022 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1023 && (! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
))
1024 || (SMALL_REGISTER_CLASSES
1025 && ((! all_adjacent
&& ! REG_USERVAR_P (src
))
1026 || (FUNCTION_VALUE_REGNO_P (REGNO (src
))
1027 && ! REG_USERVAR_P (src
))))))))
1030 else if (GET_CODE (dest
) != CC0
)
1033 /* Don't substitute for a register intended as a clobberable operand.
1034 Similarly, don't substitute an expression containing a register that
1035 will be clobbered in I3. */
1036 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1037 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1038 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1039 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1041 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1044 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1045 or not), reject, unless nothing volatile comes between it and I3 */
1047 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1049 /* Make sure succ doesn't contain a volatile reference. */
1050 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1053 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1054 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
1055 && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1059 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1060 to be an explicit register variable, and was chosen for a reason. */
1062 if (GET_CODE (src
) == ASM_OPERANDS
1063 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1066 /* If there are any volatile insns between INSN and I3, reject, because
1067 they might affect machine state. */
1069 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1070 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
1071 && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1074 /* If INSN or I2 contains an autoincrement or autodecrement,
1075 make sure that register is not used between there and I3,
1076 and not already used in I3 either.
1077 Also insist that I3 not be a jump; if it were one
1078 and the incremented register were spilled, we would lose. */
1081 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1082 if (REG_NOTE_KIND (link
) == REG_INC
1083 && (GET_CODE (i3
) == JUMP_INSN
1084 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1085 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1090 /* Don't combine an insn that follows a CC0-setting insn.
1091 An insn that uses CC0 must not be separated from the one that sets it.
1092 We do, however, allow I2 to follow a CC0-setting insn if that insn
1093 is passed as I1; in that case it will be deleted also.
1094 We also allow combining in this case if all the insns are adjacent
1095 because that would leave the two CC0 insns adjacent as well.
1096 It would be more logical to test whether CC0 occurs inside I1 or I2,
1097 but that would be much slower, and this ought to be equivalent. */
1099 p
= prev_nonnote_insn (insn
);
1100 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1105 /* If we get here, we have passed all the tests and the combination is
1114 /* Check if PAT is an insn - or a part of it - used to set up an
1115 argument for a function in a hard register. */
1118 sets_function_arg_p (pat
)
1124 switch (GET_CODE (pat
))
1127 return sets_function_arg_p (PATTERN (pat
));
1130 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1131 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1137 inner_dest
= SET_DEST (pat
);
1138 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1139 || GET_CODE (inner_dest
) == SUBREG
1140 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1141 inner_dest
= XEXP (inner_dest
, 0);
1143 return (GET_CODE (inner_dest
) == REG
1144 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1145 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1154 /* LOC is the location within I3 that contains its pattern or the component
1155 of a PARALLEL of the pattern. We validate that it is valid for combining.
1157 One problem is if I3 modifies its output, as opposed to replacing it
1158 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1159 so would produce an insn that is not equivalent to the original insns.
1163 (set (reg:DI 101) (reg:DI 100))
1164 (set (subreg:SI (reg:DI 101) 0) <foo>)
1166 This is NOT equivalent to:
1168 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1169 (set (reg:DI 101) (reg:DI 100))])
1171 Not only does this modify 100 (in which case it might still be valid
1172 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1174 We can also run into a problem if I2 sets a register that I1
1175 uses and I1 gets directly substituted into I3 (not via I2). In that
1176 case, we would be getting the wrong value of I2DEST into I3, so we
1177 must reject the combination. This case occurs when I2 and I1 both
1178 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1179 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1180 of a SET must prevent combination from occurring.
1182 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1183 if the destination of a SET is a hard register that isn't a user
1186 Before doing the above check, we first try to expand a field assignment
1187 into a set of logical operations.
1189 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1190 we place a register that is both set and used within I3. If more than one
1191 such register is detected, we fail.
1193 Return 1 if the combination is valid, zero otherwise. */
1196 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1202 rtx
*pi3dest_killed
;
1206 if (GET_CODE (x
) == SET
)
1208 rtx set
= expand_field_assignment (x
);
1209 rtx dest
= SET_DEST (set
);
1210 rtx src
= SET_SRC (set
);
1211 rtx inner_dest
= dest
;
1214 rtx inner_src
= src
;
1219 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1220 || GET_CODE (inner_dest
) == SUBREG
1221 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1222 inner_dest
= XEXP (inner_dest
, 0);
1224 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1227 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1228 || GET_CODE (inner_src
) == SUBREG
1229 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1230 inner_src
= XEXP (inner_src
, 0);
1232 /* If it is better that two different modes keep two different pseudos,
1233 avoid combining them. This avoids producing the following pattern
1235 (set (subreg:SI (reg/v:QI 21) 0)
1236 (lshiftrt:SI (reg/v:SI 20)
1238 If that were made, reload could not handle the pair of
1239 reg 20/21, since it would try to get any GENERAL_REGS
1240 but some of them don't handle QImode. */
1242 if (rtx_equal_p (inner_src
, i2dest
)
1243 && GET_CODE (inner_dest
) == REG
1244 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1248 /* Check for the case where I3 modifies its output, as
1250 if ((inner_dest
!= dest
1251 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1252 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1254 /* This is the same test done in can_combine_p except that we
1255 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1256 CALL operation. Moreover, we can't test all_adjacent; we don't
1257 have to, since this instruction will stay in place, thus we are
1258 not considering increasing the lifetime of INNER_DEST.
1260 Also, if this insn sets a function argument, combining it with
1261 something that might need a spill could clobber a previous
1262 function argument; the all_adjacent test in can_combine_p also
1263 checks this; here, we do a more specific test for this case. */
1265 || (GET_CODE (inner_dest
) == REG
1266 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1267 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1268 GET_MODE (inner_dest
))
1269 || (SMALL_REGISTER_CLASSES
&& GET_CODE (src
) != CALL
1270 && ! REG_USERVAR_P (inner_dest
)
1271 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest
))
1272 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest
))
1274 && sets_function_arg_p (prev_nonnote_insn (i3
)))))))
1275 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1278 /* If DEST is used in I3, it is being killed in this insn,
1279 so record that for later.
1280 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1281 STACK_POINTER_REGNUM, since these are always considered to be
1282 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1283 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1284 && reg_referenced_p (dest
, PATTERN (i3
))
1285 && REGNO (dest
) != FRAME_POINTER_REGNUM
1286 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1287 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1289 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1290 && (REGNO (dest
) != ARG_POINTER_REGNUM
1291 || ! fixed_regs
[REGNO (dest
)])
1293 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1295 if (*pi3dest_killed
)
1298 *pi3dest_killed
= dest
;
1302 else if (GET_CODE (x
) == PARALLEL
)
1306 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1307 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1308 i1_not_in_src
, pi3dest_killed
))
1315 /* Try to combine the insns I1 and I2 into I3.
1316 Here I1 and I2 appear earlier than I3.
1317 I1 can be zero; then we combine just I2 into I3.
1319 It we are combining three insns and the resulting insn is not recognized,
1320 try splitting it into two insns. If that happens, I2 and I3 are retained
1321 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1324 Return 0 if the combination does not work. Then nothing is changed.
1325 If we did the combination, return the insn at which combine should
1329 try_combine (i3
, i2
, i1
)
1330 register rtx i3
, i2
, i1
;
1332 /* New patterns for I3 and I3, respectively. */
1333 rtx newpat
, newi2pat
= 0;
1334 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1335 int added_sets_1
, added_sets_2
;
1336 /* Total number of SETs to put into I3. */
1338 /* Nonzero is I2's body now appears in I3. */
1340 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1341 int insn_code_number
, i2_code_number
, other_code_number
;
1342 /* Contains I3 if the destination of I3 is used in its source, which means
1343 that the old life of I3 is being killed. If that usage is placed into
1344 I2 and not in I3, a REG_DEAD note must be made. */
1345 rtx i3dest_killed
= 0;
1346 /* SET_DEST and SET_SRC of I2 and I1. */
1347 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1348 /* PATTERN (I2), or a copy of it in certain cases. */
1350 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1351 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1352 int i1_feeds_i3
= 0;
1353 /* Notes that must be added to REG_NOTES in I3 and I2. */
1354 rtx new_i3_notes
, new_i2_notes
;
1355 /* Notes that we substituted I3 into I2 instead of the normal case. */
1356 int i3_subst_into_i2
= 0;
1357 /* Notes that I1, I2 or I3 is a MULT operation. */
1365 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1366 This can occur when flow deletes an insn that it has merged into an
1367 auto-increment address. We also can't do anything if I3 has a
1368 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1371 if (GET_RTX_CLASS (GET_CODE (i3
)) != 'i'
1372 || GET_RTX_CLASS (GET_CODE (i2
)) != 'i'
1373 || (i1
&& GET_RTX_CLASS (GET_CODE (i1
)) != 'i')
1375 /* ??? This gives worse code, and appears to be unnecessary, since no
1376 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1377 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1384 undobuf
.undos
= undobuf
.previous_undos
= 0;
1385 undobuf
.other_insn
= 0;
1387 /* Save the current high-water-mark so we can free storage if we didn't
1388 accept this combination. */
1389 undobuf
.storage
= (char *) oballoc (0);
1391 /* Reset the hard register usage information. */
1392 CLEAR_HARD_REG_SET (newpat_used_regs
);
1394 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1395 code below, set I1 to be the earlier of the two insns. */
1396 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1397 temp
= i1
, i1
= i2
, i2
= temp
;
1399 added_links_insn
= 0;
1401 /* First check for one important special-case that the code below will
1402 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1403 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1404 we may be able to replace that destination with the destination of I3.
1405 This occurs in the common code where we compute both a quotient and
1406 remainder into a structure, in which case we want to do the computation
1407 directly into the structure to avoid register-register copies.
1409 We make very conservative checks below and only try to handle the
1410 most common cases of this. For example, we only handle the case
1411 where I2 and I3 are adjacent to avoid making difficult register
1414 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1415 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1416 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1417 && (! SMALL_REGISTER_CLASSES
1418 || (GET_CODE (SET_DEST (PATTERN (i3
))) != REG
1419 || REGNO (SET_DEST (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1420 || REG_USERVAR_P (SET_DEST (PATTERN (i3
)))))
1421 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1422 && GET_CODE (PATTERN (i2
)) == PARALLEL
1423 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1424 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1425 below would need to check what is inside (and reg_overlap_mentioned_p
1426 doesn't support those codes anyway). Don't allow those destinations;
1427 the resulting insn isn't likely to be recognized anyway. */
1428 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1429 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1430 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1431 SET_DEST (PATTERN (i3
)))
1432 && next_real_insn (i2
) == i3
)
1434 rtx p2
= PATTERN (i2
);
1436 /* Make sure that the destination of I3,
1437 which we are going to substitute into one output of I2,
1438 is not used within another output of I2. We must avoid making this:
1439 (parallel [(set (mem (reg 69)) ...)
1440 (set (reg 69) ...)])
1441 which is not well-defined as to order of actions.
1442 (Besides, reload can't handle output reloads for this.)
1444 The problem can also happen if the dest of I3 is a memory ref,
1445 if another dest in I2 is an indirect memory ref. */
1446 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1447 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1448 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1449 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1450 SET_DEST (XVECEXP (p2
, 0, i
))))
1453 if (i
== XVECLEN (p2
, 0))
1454 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1455 if (SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1460 subst_low_cuid
= INSN_CUID (i2
);
1462 added_sets_2
= added_sets_1
= 0;
1463 i2dest
= SET_SRC (PATTERN (i3
));
1465 /* Replace the dest in I2 with our dest and make the resulting
1466 insn the new pattern for I3. Then skip to where we
1467 validate the pattern. Everything was set up above. */
1468 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1469 SET_DEST (PATTERN (i3
)));
1472 i3_subst_into_i2
= 1;
1473 goto validate_replacement
;
1478 /* If we have no I1 and I2 looks like:
1479 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1481 make up a dummy I1 that is
1484 (set (reg:CC X) (compare:CC Y (const_int 0)))
1486 (We can ignore any trailing CLOBBERs.)
1488 This undoes a previous combination and allows us to match a branch-and-
1491 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1492 && XVECLEN (PATTERN (i2
), 0) >= 2
1493 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1494 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1496 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1497 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1498 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1499 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1500 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1501 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1503 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1504 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1509 /* We make I1 with the same INSN_UID as I2. This gives it
1510 the same INSN_CUID for value tracking. Our fake I1 will
1511 never appear in the insn stream so giving it the same INSN_UID
1512 as I2 will not cause a problem. */
1514 subst_prev_insn
= i1
1515 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1516 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1519 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1520 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1521 SET_DEST (PATTERN (i1
)));
1526 /* Verify that I2 and I1 are valid for combining. */
1527 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1528 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1534 /* Record whether I2DEST is used in I2SRC and similarly for the other
1535 cases. Knowing this will help in register status updating below. */
1536 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1537 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1538 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1540 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1542 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1544 /* Ensure that I3's pattern can be the destination of combines. */
1545 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1546 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1553 /* See if any of the insns is a MULT operation. Unless one is, we will
1554 reject a combination that is, since it must be slower. Be conservative
1556 if (GET_CODE (i2src
) == MULT
1557 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1558 || (GET_CODE (PATTERN (i3
)) == SET
1559 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1562 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1563 We used to do this EXCEPT in one case: I3 has a post-inc in an
1564 output operand. However, that exception can give rise to insns like
1566 which is a famous insn on the PDP-11 where the value of r3 used as the
1567 source was model-dependent. Avoid this sort of thing. */
1570 if (!(GET_CODE (PATTERN (i3
)) == SET
1571 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1572 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1573 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1574 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1575 /* It's not the exception. */
1578 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1579 if (REG_NOTE_KIND (link
) == REG_INC
1580 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1582 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1589 /* See if the SETs in I1 or I2 need to be kept around in the merged
1590 instruction: whenever the value set there is still needed past I3.
1591 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1593 For the SET in I1, we have two cases: If I1 and I2 independently
1594 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1595 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1596 in I1 needs to be kept around unless I1DEST dies or is set in either
1597 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1598 I1DEST. If so, we know I1 feeds into I2. */
1600 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1603 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1604 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1606 /* If the set in I2 needs to be kept around, we must make a copy of
1607 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1608 PATTERN (I2), we are only substituting for the original I1DEST, not into
1609 an already-substituted copy. This also prevents making self-referential
1610 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1613 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1614 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1618 i2pat
= copy_rtx (i2pat
);
1622 /* Substitute in the latest insn for the regs set by the earlier ones. */
1624 maxreg
= max_reg_num ();
1628 /* It is possible that the source of I2 or I1 may be performing an
1629 unneeded operation, such as a ZERO_EXTEND of something that is known
1630 to have the high part zero. Handle that case by letting subst look at
1631 the innermost one of them.
1633 Another way to do this would be to have a function that tries to
1634 simplify a single insn instead of merging two or more insns. We don't
1635 do this because of the potential of infinite loops and because
1636 of the potential extra memory required. However, doing it the way
1637 we are is a bit of a kludge and doesn't catch all cases.
1639 But only do this if -fexpensive-optimizations since it slows things down
1640 and doesn't usually win. */
1642 if (flag_expensive_optimizations
)
1644 /* Pass pc_rtx so no substitutions are done, just simplifications.
1645 The cases that we are interested in here do not involve the few
1646 cases were is_replaced is checked. */
1649 subst_low_cuid
= INSN_CUID (i1
);
1650 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1654 subst_low_cuid
= INSN_CUID (i2
);
1655 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1658 undobuf
.previous_undos
= undobuf
.undos
;
1662 /* Many machines that don't use CC0 have insns that can both perform an
1663 arithmetic operation and set the condition code. These operations will
1664 be represented as a PARALLEL with the first element of the vector
1665 being a COMPARE of an arithmetic operation with the constant zero.
1666 The second element of the vector will set some pseudo to the result
1667 of the same arithmetic operation. If we simplify the COMPARE, we won't
1668 match such a pattern and so will generate an extra insn. Here we test
1669 for this case, where both the comparison and the operation result are
1670 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1671 I2SRC. Later we will make the PARALLEL that contains I2. */
1673 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1674 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1675 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1676 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1678 #ifdef EXTRA_CC_MODES
1680 enum machine_mode compare_mode
;
1683 newpat
= PATTERN (i3
);
1684 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1688 #ifdef EXTRA_CC_MODES
1689 /* See if a COMPARE with the operand we substituted in should be done
1690 with the mode that is currently being used. If not, do the same
1691 processing we do in `subst' for a SET; namely, if the destination
1692 is used only once, try to replace it with a register of the proper
1693 mode and also replace the COMPARE. */
1694 if (undobuf
.other_insn
== 0
1695 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1696 &undobuf
.other_insn
))
1697 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1699 != GET_MODE (SET_DEST (newpat
))))
1701 int regno
= REGNO (SET_DEST (newpat
));
1702 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1704 if (regno
< FIRST_PSEUDO_REGISTER
1705 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1706 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1708 if (regno
>= FIRST_PSEUDO_REGISTER
)
1709 SUBST (regno_reg_rtx
[regno
], new_dest
);
1711 SUBST (SET_DEST (newpat
), new_dest
);
1712 SUBST (XEXP (*cc_use
, 0), new_dest
);
1713 SUBST (SET_SRC (newpat
),
1714 gen_rtx_combine (COMPARE
, compare_mode
,
1715 i2src
, const0_rtx
));
1718 undobuf
.other_insn
= 0;
1725 n_occurrences
= 0; /* `subst' counts here */
1727 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1728 need to make a unique copy of I2SRC each time we substitute it
1729 to avoid self-referential rtl. */
1731 subst_low_cuid
= INSN_CUID (i2
);
1732 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1733 ! i1_feeds_i3
&& i1dest_in_i1src
);
1734 undobuf
.previous_undos
= undobuf
.undos
;
1736 /* Record whether i2's body now appears within i3's body. */
1737 i2_is_used
= n_occurrences
;
1740 /* If we already got a failure, don't try to do more. Otherwise,
1741 try to substitute in I1 if we have it. */
1743 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1745 /* Before we can do this substitution, we must redo the test done
1746 above (see detailed comments there) that ensures that I1DEST
1747 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1749 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1757 subst_low_cuid
= INSN_CUID (i1
);
1758 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1759 undobuf
.previous_undos
= undobuf
.undos
;
1762 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1763 to count all the ways that I2SRC and I1SRC can be used. */
1764 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1765 && i2_is_used
+ added_sets_2
> 1)
1766 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1767 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1769 /* Fail if we tried to make a new register (we used to abort, but there's
1770 really no reason to). */
1771 || max_reg_num () != maxreg
1772 /* Fail if we couldn't do something and have a CLOBBER. */
1773 || GET_CODE (newpat
) == CLOBBER
1774 /* Fail if this new pattern is a MULT and we didn't have one before
1775 at the outer level. */
1776 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1783 /* If the actions of the earlier insns must be kept
1784 in addition to substituting them into the latest one,
1785 we must make a new PARALLEL for the latest insn
1786 to hold additional the SETs. */
1788 if (added_sets_1
|| added_sets_2
)
1792 if (GET_CODE (newpat
) == PARALLEL
)
1794 rtvec old
= XVEC (newpat
, 0);
1795 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1796 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1797 bcopy ((char *) &old
->elem
[0], (char *) XVEC (newpat
, 0)->elem
,
1798 sizeof (old
->elem
[0]) * old
->num_elem
);
1803 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1804 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1805 XVECEXP (newpat
, 0, 0) = old
;
1809 XVECEXP (newpat
, 0, --total_sets
)
1810 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1811 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1815 /* If there is no I1, use I2's body as is. We used to also not do
1816 the subst call below if I2 was substituted into I3,
1817 but that could lose a simplification. */
1819 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1821 /* See comment where i2pat is assigned. */
1822 XVECEXP (newpat
, 0, --total_sets
)
1823 = subst (i2pat
, i1dest
, i1src
, 0, 0);
1827 /* We come here when we are replacing a destination in I2 with the
1828 destination of I3. */
1829 validate_replacement
:
1831 /* Note which hard regs this insn has as inputs. */
1832 mark_used_regs_combine (newpat
);
1834 /* Is the result of combination a valid instruction? */
1835 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1837 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1838 the second SET's destination is a register that is unused. In that case,
1839 we just need the first SET. This can occur when simplifying a divmod
1840 insn. We *must* test for this case here because the code below that
1841 splits two independent SETs doesn't handle this case correctly when it
1842 updates the register status. Also check the case where the first
1843 SET's destination is unused. That would not cause incorrect code, but
1844 does cause an unneeded insn to remain. */
1846 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1847 && XVECLEN (newpat
, 0) == 2
1848 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1849 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1850 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
1851 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
1852 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
1853 && asm_noperands (newpat
) < 0)
1855 newpat
= XVECEXP (newpat
, 0, 0);
1856 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1859 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1860 && XVECLEN (newpat
, 0) == 2
1861 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1862 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1863 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
1864 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
1865 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
1866 && asm_noperands (newpat
) < 0)
1868 newpat
= XVECEXP (newpat
, 0, 1);
1869 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1872 /* If we were combining three insns and the result is a simple SET
1873 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1874 insns. There are two ways to do this. It can be split using a
1875 machine-specific method (like when you have an addition of a large
1876 constant) or by combine in the function find_split_point. */
1878 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
1879 && asm_noperands (newpat
) < 0)
1881 rtx m_split
, *split
;
1882 rtx ni2dest
= i2dest
;
1884 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1885 use I2DEST as a scratch register will help. In the latter case,
1886 convert I2DEST to the mode of the source of NEWPAT if we can. */
1888 m_split
= split_insns (newpat
, i3
);
1890 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1891 inputs of NEWPAT. */
1893 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1894 possible to try that as a scratch reg. This would require adding
1895 more code to make it work though. */
1897 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
1899 /* If I2DEST is a hard register or the only use of a pseudo,
1900 we can change its mode. */
1901 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
1902 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
1903 && GET_CODE (i2dest
) == REG
1904 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1905 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
1906 && ! REG_USERVAR_P (i2dest
))))
1907 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
1910 m_split
= split_insns
1911 (gen_rtx_PARALLEL (VOIDmode
,
1912 gen_rtvec (2, newpat
,
1913 gen_rtx_CLOBBER (VOIDmode
,
1918 if (m_split
&& GET_CODE (m_split
) == SEQUENCE
1919 && XVECLEN (m_split
, 0) == 2
1920 && (next_real_insn (i2
) == i3
1921 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
1925 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
1926 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
1928 i3set
= single_set (XVECEXP (m_split
, 0, 1));
1929 i2set
= single_set (XVECEXP (m_split
, 0, 0));
1931 /* In case we changed the mode of I2DEST, replace it in the
1932 pseudo-register table here. We can't do it above in case this
1933 code doesn't get executed and we do a split the other way. */
1935 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
1936 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
1938 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1940 /* If I2 or I3 has multiple SETs, we won't know how to track
1941 register status, so don't use these insns. If I2's destination
1942 is used between I2 and I3, we also can't use these insns. */
1944 if (i2_code_number
>= 0 && i2set
&& i3set
1945 && (next_real_insn (i2
) == i3
1946 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
1947 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
1949 if (insn_code_number
>= 0)
1952 /* It is possible that both insns now set the destination of I3.
1953 If so, we must show an extra use of it. */
1955 if (insn_code_number
>= 0)
1957 rtx new_i3_dest
= SET_DEST (i3set
);
1958 rtx new_i2_dest
= SET_DEST (i2set
);
1960 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
1961 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
1962 || GET_CODE (new_i3_dest
) == SUBREG
)
1963 new_i3_dest
= XEXP (new_i3_dest
, 0);
1965 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
1966 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
1967 || GET_CODE (new_i2_dest
) == SUBREG
)
1968 new_i2_dest
= XEXP (new_i2_dest
, 0);
1970 if (GET_CODE (new_i3_dest
) == REG
1971 && GET_CODE (new_i2_dest
) == REG
1972 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
1973 REG_N_SETS (REGNO (new_i2_dest
))++;
1977 /* If we can split it and use I2DEST, go ahead and see if that
1978 helps things be recognized. Verify that none of the registers
1979 are set between I2 and I3. */
1980 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
1982 && GET_CODE (i2dest
) == REG
1984 /* We need I2DEST in the proper mode. If it is a hard register
1985 or the only use of a pseudo, we can change its mode. */
1986 && (GET_MODE (*split
) == GET_MODE (i2dest
)
1987 || GET_MODE (*split
) == VOIDmode
1988 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1989 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
1990 && ! REG_USERVAR_P (i2dest
)))
1991 && (next_real_insn (i2
) == i3
1992 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
1993 /* We can't overwrite I2DEST if its value is still used by
1995 && ! reg_referenced_p (i2dest
, newpat
))
1997 rtx newdest
= i2dest
;
1998 enum rtx_code split_code
= GET_CODE (*split
);
1999 enum machine_mode split_mode
= GET_MODE (*split
);
2001 /* Get NEWDEST as a register in the proper mode. We have already
2002 validated that we can do this. */
2003 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2005 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2007 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2008 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2011 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2012 an ASHIFT. This can occur if it was inside a PLUS and hence
2013 appeared to be a memory address. This is a kludge. */
2014 if (split_code
== MULT
2015 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2016 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2018 SUBST (*split
, gen_rtx_combine (ASHIFT
, split_mode
,
2019 XEXP (*split
, 0), GEN_INT (i
)));
2020 /* Update split_code because we may not have a multiply
2022 split_code
= GET_CODE (*split
);
2025 #ifdef INSN_SCHEDULING
2026 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2027 be written as a ZERO_EXTEND. */
2028 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2029 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, split_mode
,
2033 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
2034 SUBST (*split
, newdest
);
2035 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2037 /* If the split point was a MULT and we didn't have one before,
2038 don't use one now. */
2039 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2040 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2044 /* Check for a case where we loaded from memory in a narrow mode and
2045 then sign extended it, but we need both registers. In that case,
2046 we have a PARALLEL with both loads from the same memory location.
2047 We can split this into a load from memory followed by a register-register
2048 copy. This saves at least one insn, more if register allocation can
2051 We cannot do this if the destination of the second assignment is
2052 a register that we have already assumed is zero-extended. Similarly
2053 for a SUBREG of such a register. */
2055 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2056 && GET_CODE (newpat
) == PARALLEL
2057 && XVECLEN (newpat
, 0) == 2
2058 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2059 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2060 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2061 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2062 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2063 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2065 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2066 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2067 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2068 (GET_CODE (temp
) == REG
2069 && reg_nonzero_bits
[REGNO (temp
)] != 0
2070 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2071 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2072 && (reg_nonzero_bits
[REGNO (temp
)]
2073 != GET_MODE_MASK (word_mode
))))
2074 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2075 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2076 (GET_CODE (temp
) == REG
2077 && reg_nonzero_bits
[REGNO (temp
)] != 0
2078 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2079 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2080 && (reg_nonzero_bits
[REGNO (temp
)]
2081 != GET_MODE_MASK (word_mode
)))))
2082 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2083 SET_SRC (XVECEXP (newpat
, 0, 1)))
2084 && ! find_reg_note (i3
, REG_UNUSED
,
2085 SET_DEST (XVECEXP (newpat
, 0, 0))))
2089 newi2pat
= XVECEXP (newpat
, 0, 0);
2090 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2091 newpat
= XVECEXP (newpat
, 0, 1);
2092 SUBST (SET_SRC (newpat
),
2093 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2094 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2096 if (i2_code_number
>= 0)
2097 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2099 if (insn_code_number
>= 0)
2104 /* If we will be able to accept this, we have made a change to the
2105 destination of I3. This can invalidate a LOG_LINKS pointing
2106 to I3. No other part of combine.c makes such a transformation.
2108 The new I3 will have a destination that was previously the
2109 destination of I1 or I2 and which was used in i2 or I3. Call
2110 distribute_links to make a LOG_LINK from the next use of
2111 that destination. */
2113 PATTERN (i3
) = newpat
;
2114 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2116 /* I3 now uses what used to be its destination and which is
2117 now I2's destination. That means we need a LOG_LINK from
2118 I3 to I2. But we used to have one, so we still will.
2120 However, some later insn might be using I2's dest and have
2121 a LOG_LINK pointing at I3. We must remove this link.
2122 The simplest way to remove the link is to point it at I1,
2123 which we know will be a NOTE. */
2125 for (insn
= NEXT_INSN (i3
);
2126 insn
&& (this_basic_block
== n_basic_blocks
- 1
2127 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2128 insn
= NEXT_INSN (insn
))
2130 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
2131 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2133 for (link
= LOG_LINKS (insn
); link
;
2134 link
= XEXP (link
, 1))
2135 if (XEXP (link
, 0) == i3
)
2136 XEXP (link
, 0) = i1
;
2144 /* Similarly, check for a case where we have a PARALLEL of two independent
2145 SETs but we started with three insns. In this case, we can do the sets
2146 as two separate insns. This case occurs when some SET allows two
2147 other insns to combine, but the destination of that SET is still live. */
2149 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2150 && GET_CODE (newpat
) == PARALLEL
2151 && XVECLEN (newpat
, 0) == 2
2152 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2153 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2154 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2155 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2156 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2157 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2158 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2160 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2161 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2162 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2163 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2164 XVECEXP (newpat
, 0, 0))
2165 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2166 XVECEXP (newpat
, 0, 1)))
2168 /* Normally, it doesn't matter which of the two is done first,
2169 but it does if one references cc0. In that case, it has to
2172 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2174 newi2pat
= XVECEXP (newpat
, 0, 0);
2175 newpat
= XVECEXP (newpat
, 0, 1);
2180 newi2pat
= XVECEXP (newpat
, 0, 1);
2181 newpat
= XVECEXP (newpat
, 0, 0);
2184 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2186 if (i2_code_number
>= 0)
2187 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2190 /* If it still isn't recognized, fail and change things back the way they
2192 if ((insn_code_number
< 0
2193 /* Is the result a reasonable ASM_OPERANDS? */
2194 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2200 /* If we had to change another insn, make sure it is valid also. */
2201 if (undobuf
.other_insn
)
2203 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2204 rtx new_other_notes
;
2207 CLEAR_HARD_REG_SET (newpat_used_regs
);
2209 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2212 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2218 PATTERN (undobuf
.other_insn
) = other_pat
;
2220 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2221 are still valid. Then add any non-duplicate notes added by
2222 recog_for_combine. */
2223 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2225 next
= XEXP (note
, 1);
2227 if (REG_NOTE_KIND (note
) == REG_UNUSED
2228 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2230 if (GET_CODE (XEXP (note
, 0)) == REG
)
2231 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2233 remove_note (undobuf
.other_insn
, note
);
2237 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2238 if (GET_CODE (XEXP (note
, 0)) == REG
)
2239 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2241 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2242 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2245 /* We now know that we can do this combination. Merge the insns and
2246 update the status of registers and LOG_LINKS. */
2249 rtx i3notes
, i2notes
, i1notes
= 0;
2250 rtx i3links
, i2links
, i1links
= 0;
2253 /* Compute which registers we expect to eliminate. newi2pat may be setting
2254 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2255 same as i3dest, in which case newi2pat may be setting i1dest. */
2256 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2257 || i2dest_in_i2src
|| i2dest_in_i1src
2259 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2260 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2263 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2265 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2266 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2268 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2270 /* Ensure that we do not have something that should not be shared but
2271 occurs multiple times in the new insns. Check this by first
2272 resetting all the `used' flags and then copying anything is shared. */
2274 reset_used_flags (i3notes
);
2275 reset_used_flags (i2notes
);
2276 reset_used_flags (i1notes
);
2277 reset_used_flags (newpat
);
2278 reset_used_flags (newi2pat
);
2279 if (undobuf
.other_insn
)
2280 reset_used_flags (PATTERN (undobuf
.other_insn
));
2282 i3notes
= copy_rtx_if_shared (i3notes
);
2283 i2notes
= copy_rtx_if_shared (i2notes
);
2284 i1notes
= copy_rtx_if_shared (i1notes
);
2285 newpat
= copy_rtx_if_shared (newpat
);
2286 newi2pat
= copy_rtx_if_shared (newi2pat
);
2287 if (undobuf
.other_insn
)
2288 reset_used_flags (PATTERN (undobuf
.other_insn
));
2290 INSN_CODE (i3
) = insn_code_number
;
2291 PATTERN (i3
) = newpat
;
2292 if (undobuf
.other_insn
)
2293 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2295 /* We had one special case above where I2 had more than one set and
2296 we replaced a destination of one of those sets with the destination
2297 of I3. In that case, we have to update LOG_LINKS of insns later
2298 in this basic block. Note that this (expensive) case is rare.
2300 Also, in this case, we must pretend that all REG_NOTEs for I2
2301 actually came from I3, so that REG_UNUSED notes from I2 will be
2302 properly handled. */
2304 if (i3_subst_into_i2
)
2306 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2307 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2308 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2309 && ! find_reg_note (i2
, REG_UNUSED
,
2310 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2311 for (temp
= NEXT_INSN (i2
);
2312 temp
&& (this_basic_block
== n_basic_blocks
- 1
2313 || BLOCK_HEAD (this_basic_block
) != temp
);
2314 temp
= NEXT_INSN (temp
))
2315 if (temp
!= i3
&& GET_RTX_CLASS (GET_CODE (temp
)) == 'i')
2316 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2317 if (XEXP (link
, 0) == i2
)
2318 XEXP (link
, 0) = i3
;
2323 while (XEXP (link
, 1))
2324 link
= XEXP (link
, 1);
2325 XEXP (link
, 1) = i2notes
;
2339 INSN_CODE (i2
) = i2_code_number
;
2340 PATTERN (i2
) = newi2pat
;
2344 PUT_CODE (i2
, NOTE
);
2345 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2346 NOTE_SOURCE_FILE (i2
) = 0;
2353 PUT_CODE (i1
, NOTE
);
2354 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2355 NOTE_SOURCE_FILE (i1
) = 0;
2358 /* Get death notes for everything that is now used in either I3 or
2359 I2 and used to die in a previous insn. If we built two new
2360 patterns, move from I1 to I2 then I2 to I3 so that we get the
2361 proper movement on registers that I2 modifies. */
2365 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2366 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2369 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2372 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2374 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2377 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2380 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2383 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2386 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2387 know these are REG_UNUSED and want them to go to the desired insn,
2388 so we always pass it as i3. We have not counted the notes in
2389 reg_n_deaths yet, so we need to do so now. */
2391 if (newi2pat
&& new_i2_notes
)
2393 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2394 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2395 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2397 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2402 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2403 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2404 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2406 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2409 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2410 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2411 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2412 in that case, it might delete I2. Similarly for I2 and I1.
2413 Show an additional death due to the REG_DEAD note we make here. If
2414 we discard it in distribute_notes, we will decrement it again. */
2418 if (GET_CODE (i3dest_killed
) == REG
)
2419 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2421 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2422 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2424 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2426 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2428 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2432 if (i2dest_in_i2src
)
2434 if (GET_CODE (i2dest
) == REG
)
2435 REG_N_DEATHS (REGNO (i2dest
))++;
2437 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2438 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2439 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2441 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2442 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2443 NULL_RTX
, NULL_RTX
);
2446 if (i1dest_in_i1src
)
2448 if (GET_CODE (i1dest
) == REG
)
2449 REG_N_DEATHS (REGNO (i1dest
))++;
2451 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2452 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2453 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2455 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2456 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2457 NULL_RTX
, NULL_RTX
);
2460 distribute_links (i3links
);
2461 distribute_links (i2links
);
2462 distribute_links (i1links
);
2464 if (GET_CODE (i2dest
) == REG
)
2467 rtx i2_insn
= 0, i2_val
= 0, set
;
2469 /* The insn that used to set this register doesn't exist, and
2470 this life of the register may not exist either. See if one of
2471 I3's links points to an insn that sets I2DEST. If it does,
2472 that is now the last known value for I2DEST. If we don't update
2473 this and I2 set the register to a value that depended on its old
2474 contents, we will get confused. If this insn is used, thing
2475 will be set correctly in combine_instructions. */
2477 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2478 if ((set
= single_set (XEXP (link
, 0))) != 0
2479 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2480 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2482 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2484 /* If the reg formerly set in I2 died only once and that was in I3,
2485 zero its use count so it won't make `reload' do any work. */
2487 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2488 && ! i2dest_in_i2src
)
2490 regno
= REGNO (i2dest
);
2491 REG_N_SETS (regno
)--;
2492 if (REG_N_SETS (regno
) == 0
2493 && ! REGNO_REG_SET_P (basic_block_live_at_start
[0], regno
))
2494 REG_N_REFS (regno
) = 0;
2498 if (i1
&& GET_CODE (i1dest
) == REG
)
2501 rtx i1_insn
= 0, i1_val
= 0, set
;
2503 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2504 if ((set
= single_set (XEXP (link
, 0))) != 0
2505 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2506 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2508 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2510 regno
= REGNO (i1dest
);
2511 if (! added_sets_1
&& ! i1dest_in_i1src
)
2513 REG_N_SETS (regno
)--;
2514 if (REG_N_SETS (regno
) == 0
2515 && ! REGNO_REG_SET_P (basic_block_live_at_start
[0], regno
))
2516 REG_N_REFS (regno
) = 0;
2520 /* Update reg_nonzero_bits et al for any changes that may have been made
2523 note_stores (newpat
, set_nonzero_bits_and_sign_copies
);
2525 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
);
2527 /* If I3 is now an unconditional jump, ensure that it has a
2528 BARRIER following it since it may have initially been a
2529 conditional jump. It may also be the last nonnote insn. */
2531 if ((GET_CODE (newpat
) == RETURN
|| simplejump_p (i3
))
2532 && ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2533 || GET_CODE (temp
) != BARRIER
))
2534 emit_barrier_after (i3
);
2537 combine_successes
++;
2539 /* Clear this here, so that subsequent get_last_value calls are not
2541 subst_prev_insn
= NULL_RTX
;
2543 if (added_links_insn
2544 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2545 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2546 return added_links_insn
;
2548 return newi2pat
? i2
: i3
;
2551 /* Undo all the modifications recorded in undobuf. */
2556 struct undo
*undo
, *next
;
2558 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2562 *undo
->where
.i
= undo
->old_contents
.i
;
2564 *undo
->where
.r
= undo
->old_contents
.r
;
2566 undo
->next
= undobuf
.frees
;
2567 undobuf
.frees
= undo
;
2570 obfree (undobuf
.storage
);
2571 undobuf
.undos
= undobuf
.previous_undos
= 0;
2573 /* Clear this here, so that subsequent get_last_value calls are not
2575 subst_prev_insn
= NULL_RTX
;
2578 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2579 where we have an arithmetic expression and return that point. LOC will
2582 try_combine will call this function to see if an insn can be split into
2586 find_split_point (loc
, insn
)
2591 enum rtx_code code
= GET_CODE (x
);
2593 int len
= 0, pos
, unsignedp
;
2596 /* First special-case some codes. */
2600 #ifdef INSN_SCHEDULING
2601 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2603 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2606 return find_split_point (&SUBREG_REG (x
), insn
);
2610 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2611 using LO_SUM and HIGH. */
2612 if (GET_CODE (XEXP (x
, 0)) == CONST
2613 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2616 gen_rtx_combine (LO_SUM
, Pmode
,
2617 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
2619 return &XEXP (XEXP (x
, 0), 0);
2623 /* If we have a PLUS whose second operand is a constant and the
2624 address is not valid, perhaps will can split it up using
2625 the machine-specific way to split large constants. We use
2626 the first pseudo-reg (one of the virtual regs) as a placeholder;
2627 it will not remain in the result. */
2628 if (GET_CODE (XEXP (x
, 0)) == PLUS
2629 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2630 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2632 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2633 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2636 /* This should have produced two insns, each of which sets our
2637 placeholder. If the source of the second is a valid address,
2638 we can make put both sources together and make a split point
2641 if (seq
&& XVECLEN (seq
, 0) == 2
2642 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2643 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2644 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2645 && ! reg_mentioned_p (reg
,
2646 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2647 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2648 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2649 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2650 && memory_address_p (GET_MODE (x
),
2651 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2653 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2654 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2656 /* Replace the placeholder in SRC2 with SRC1. If we can
2657 find where in SRC2 it was placed, that can become our
2658 split point and we can replace this address with SRC2.
2659 Just try two obvious places. */
2661 src2
= replace_rtx (src2
, reg
, src1
);
2663 if (XEXP (src2
, 0) == src1
)
2664 split
= &XEXP (src2
, 0);
2665 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2666 && XEXP (XEXP (src2
, 0), 0) == src1
)
2667 split
= &XEXP (XEXP (src2
, 0), 0);
2671 SUBST (XEXP (x
, 0), src2
);
2676 /* If that didn't work, perhaps the first operand is complex and
2677 needs to be computed separately, so make a split point there.
2678 This will occur on machines that just support REG + CONST
2679 and have a constant moved through some previous computation. */
2681 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2682 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2683 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2685 return &XEXP (XEXP (x
, 0), 0);
2691 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2692 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2693 we need to put the operand into a register. So split at that
2696 if (SET_DEST (x
) == cc0_rtx
2697 && GET_CODE (SET_SRC (x
)) != COMPARE
2698 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2699 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2700 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2701 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2702 return &SET_SRC (x
);
2705 /* See if we can split SET_SRC as it stands. */
2706 split
= find_split_point (&SET_SRC (x
), insn
);
2707 if (split
&& split
!= &SET_SRC (x
))
2710 /* See if we can split SET_DEST as it stands. */
2711 split
= find_split_point (&SET_DEST (x
), insn
);
2712 if (split
&& split
!= &SET_DEST (x
))
2715 /* See if this is a bitfield assignment with everything constant. If
2716 so, this is an IOR of an AND, so split it into that. */
2717 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2718 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2719 <= HOST_BITS_PER_WIDE_INT
)
2720 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2721 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2722 && GET_CODE (SET_SRC (x
)) == CONST_INT
2723 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2724 + INTVAL (XEXP (SET_DEST (x
), 2)))
2725 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2726 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2728 int pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2729 int len
= INTVAL (XEXP (SET_DEST (x
), 1));
2730 int src
= INTVAL (SET_SRC (x
));
2731 rtx dest
= XEXP (SET_DEST (x
), 0);
2732 enum machine_mode mode
= GET_MODE (dest
);
2733 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2735 if (BITS_BIG_ENDIAN
)
2736 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2738 if ((unsigned HOST_WIDE_INT
) src
== mask
)
2740 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
2743 gen_binary (IOR
, mode
,
2744 gen_binary (AND
, mode
, dest
,
2745 GEN_INT (~ (mask
<< pos
)
2746 & GET_MODE_MASK (mode
))),
2747 GEN_INT (src
<< pos
)));
2749 SUBST (SET_DEST (x
), dest
);
2751 split
= find_split_point (&SET_SRC (x
), insn
);
2752 if (split
&& split
!= &SET_SRC (x
))
2756 /* Otherwise, see if this is an operation that we can split into two.
2757 If so, try to split that. */
2758 code
= GET_CODE (SET_SRC (x
));
2763 /* If we are AND'ing with a large constant that is only a single
2764 bit and the result is only being used in a context where we
2765 need to know if it is zero or non-zero, replace it with a bit
2766 extraction. This will avoid the large constant, which might
2767 have taken more than one insn to make. If the constant were
2768 not a valid argument to the AND but took only one insn to make,
2769 this is no worse, but if it took more than one insn, it will
2772 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2773 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2774 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
2775 && GET_CODE (SET_DEST (x
)) == REG
2776 && (split
= find_single_use (SET_DEST (x
), insn
, NULL_PTR
)) != 0
2777 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
2778 && XEXP (*split
, 0) == SET_DEST (x
)
2779 && XEXP (*split
, 1) == const0_rtx
)
2781 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
2782 XEXP (SET_SRC (x
), 0),
2783 pos
, NULL_RTX
, 1, 1, 0, 0);
2784 if (extraction
!= 0)
2786 SUBST (SET_SRC (x
), extraction
);
2787 return find_split_point (loc
, insn
);
2793 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2794 is known to be on, this can be converted into a NEG of a shift. */
2795 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
2796 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
2797 && 1 <= (pos
= exact_log2
2798 (nonzero_bits (XEXP (SET_SRC (x
), 0),
2799 GET_MODE (XEXP (SET_SRC (x
), 0))))))
2801 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
2804 gen_rtx_combine (NEG
, mode
,
2805 gen_rtx_combine (LSHIFTRT
, mode
,
2806 XEXP (SET_SRC (x
), 0),
2809 split
= find_split_point (&SET_SRC (x
), insn
);
2810 if (split
&& split
!= &SET_SRC (x
))
2816 inner
= XEXP (SET_SRC (x
), 0);
2818 /* We can't optimize if either mode is a partial integer
2819 mode as we don't know how many bits are significant
2821 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
2822 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
2826 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
2832 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2833 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
2835 inner
= XEXP (SET_SRC (x
), 0);
2836 len
= INTVAL (XEXP (SET_SRC (x
), 1));
2837 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
2839 if (BITS_BIG_ENDIAN
)
2840 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
2841 unsignedp
= (code
== ZERO_EXTRACT
);
2849 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
2851 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
2853 /* For unsigned, we have a choice of a shift followed by an
2854 AND or two shifts. Use two shifts for field sizes where the
2855 constant might be too large. We assume here that we can
2856 always at least get 8-bit constants in an AND insn, which is
2857 true for every current RISC. */
2859 if (unsignedp
&& len
<= 8)
2864 gen_rtx_combine (LSHIFTRT
, mode
,
2865 gen_lowpart_for_combine (mode
, inner
),
2867 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
2869 split
= find_split_point (&SET_SRC (x
), insn
);
2870 if (split
&& split
!= &SET_SRC (x
))
2877 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
2878 gen_rtx_combine (ASHIFT
, mode
,
2879 gen_lowpart_for_combine (mode
, inner
),
2880 GEN_INT (GET_MODE_BITSIZE (mode
)
2882 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
2884 split
= find_split_point (&SET_SRC (x
), insn
);
2885 if (split
&& split
!= &SET_SRC (x
))
2890 /* See if this is a simple operation with a constant as the second
2891 operand. It might be that this constant is out of range and hence
2892 could be used as a split point. */
2893 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2894 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2895 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
2896 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
2897 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
2898 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
2899 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
2901 return &XEXP (SET_SRC (x
), 1);
2903 /* Finally, see if this is a simple operation with its first operand
2904 not in a register. The operation might require this operand in a
2905 register, so return it as a split point. We can always do this
2906 because if the first operand were another operation, we would have
2907 already found it as a split point. */
2908 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2909 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2910 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
2911 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
2912 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
2913 return &XEXP (SET_SRC (x
), 0);
2919 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2920 it is better to write this as (not (ior A B)) so we can split it.
2921 Similarly for IOR. */
2922 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
2925 gen_rtx_combine (NOT
, GET_MODE (x
),
2926 gen_rtx_combine (code
== IOR
? AND
: IOR
,
2928 XEXP (XEXP (x
, 0), 0),
2929 XEXP (XEXP (x
, 1), 0))));
2930 return find_split_point (loc
, insn
);
2933 /* Many RISC machines have a large set of logical insns. If the
2934 second operand is a NOT, put it first so we will try to split the
2935 other operand first. */
2936 if (GET_CODE (XEXP (x
, 1)) == NOT
)
2938 rtx tem
= XEXP (x
, 0);
2939 SUBST (XEXP (x
, 0), XEXP (x
, 1));
2940 SUBST (XEXP (x
, 1), tem
);
2948 /* Otherwise, select our actions depending on our rtx class. */
2949 switch (GET_RTX_CLASS (code
))
2951 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2953 split
= find_split_point (&XEXP (x
, 2), insn
);
2956 /* ... fall through ... */
2960 split
= find_split_point (&XEXP (x
, 1), insn
);
2963 /* ... fall through ... */
2965 /* Some machines have (and (shift ...) ...) insns. If X is not
2966 an AND, but XEXP (X, 0) is, use it as our split point. */
2967 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
2968 return &XEXP (x
, 0);
2970 split
= find_split_point (&XEXP (x
, 0), insn
);
2976 /* Otherwise, we don't have a split point. */
2980 /* Throughout X, replace FROM with TO, and return the result.
2981 The result is TO if X is FROM;
2982 otherwise the result is X, but its contents may have been modified.
2983 If they were modified, a record was made in undobuf so that
2984 undo_all will (among other things) return X to its original state.
2986 If the number of changes necessary is too much to record to undo,
2987 the excess changes are not made, so the result is invalid.
2988 The changes already made can still be undone.
2989 undobuf.num_undo is incremented for such changes, so by testing that
2990 the caller can tell whether the result is valid.
2992 `n_occurrences' is incremented each time FROM is replaced.
2994 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2996 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2997 by copying if `n_occurrences' is non-zero. */
3000 subst (x
, from
, to
, in_dest
, unique_copy
)
3001 register rtx x
, from
, to
;
3005 register enum rtx_code code
= GET_CODE (x
);
3006 enum machine_mode op0_mode
= VOIDmode
;
3008 register int len
, i
;
3011 /* Two expressions are equal if they are identical copies of a shared
3012 RTX or if they are both registers with the same register number
3015 #define COMBINE_RTX_EQUAL_P(X,Y) \
3017 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3018 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3020 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3023 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3026 /* If X and FROM are the same register but different modes, they will
3027 not have been seen as equal above. However, flow.c will make a
3028 LOG_LINKS entry for that case. If we do nothing, we will try to
3029 rerecognize our original insn and, when it succeeds, we will
3030 delete the feeding insn, which is incorrect.
3032 So force this insn not to match in this (rare) case. */
3033 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3034 && REGNO (x
) == REGNO (from
))
3035 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3037 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3038 of which may contain things that can be combined. */
3039 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3042 /* It is possible to have a subexpression appear twice in the insn.
3043 Suppose that FROM is a register that appears within TO.
3044 Then, after that subexpression has been scanned once by `subst',
3045 the second time it is scanned, TO may be found. If we were
3046 to scan TO here, we would find FROM within it and create a
3047 self-referent rtl structure which is completely wrong. */
3048 if (COMBINE_RTX_EQUAL_P (x
, to
))
3051 /* Parallel asm_operands need special attention because all of the
3052 inputs are shared across the arms. Furthermore, unsharing the
3053 rtl results in recognition failures. Failure to handle this case
3054 specially can result in circular rtl.
3056 Solve this by doing a normal pass across the first entry of the
3057 parallel, and only processing the SET_DESTs of the subsequent
3060 if (code
== PARALLEL
3061 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3062 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3064 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3066 /* If this substitution failed, this whole thing fails. */
3067 if (GET_CODE (new) == CLOBBER
3068 && XEXP (new, 0) == const0_rtx
)
3071 SUBST (XVECEXP (x
, 0, 0), new);
3073 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3075 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3077 if (GET_CODE (dest
) != REG
3078 && GET_CODE (dest
) != CC0
3079 && GET_CODE (dest
) != PC
)
3081 new = subst (dest
, from
, to
, 0, unique_copy
);
3083 /* If this substitution failed, this whole thing fails. */
3084 if (GET_CODE (new) == CLOBBER
3085 && XEXP (new, 0) == const0_rtx
)
3088 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3094 len
= GET_RTX_LENGTH (code
);
3095 fmt
= GET_RTX_FORMAT (code
);
3097 /* We don't need to process a SET_DEST that is a register, CC0,
3098 or PC, so set up to skip this common case. All other cases
3099 where we want to suppress replacing something inside a
3100 SET_SRC are handled via the IN_DEST operand. */
3102 && (GET_CODE (SET_DEST (x
)) == REG
3103 || GET_CODE (SET_DEST (x
)) == CC0
3104 || GET_CODE (SET_DEST (x
)) == PC
))
3107 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3110 op0_mode
= GET_MODE (XEXP (x
, 0));
3112 for (i
= 0; i
< len
; i
++)
3117 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3119 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3121 new = (unique_copy
&& n_occurrences
3122 ? copy_rtx (to
) : to
);
3127 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3130 /* If this substitution failed, this whole thing
3132 if (GET_CODE (new) == CLOBBER
3133 && XEXP (new, 0) == const0_rtx
)
3137 SUBST (XVECEXP (x
, i
, j
), new);
3140 else if (fmt
[i
] == 'e')
3142 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3144 /* In general, don't install a subreg involving two
3145 modes not tieable. It can worsen register
3146 allocation, and can even make invalid reload
3147 insns, since the reg inside may need to be copied
3148 from in the outside mode, and that may be invalid
3149 if it is an fp reg copied in integer mode.
3151 We allow two exceptions to this: It is valid if
3152 it is inside another SUBREG and the mode of that
3153 SUBREG and the mode of the inside of TO is
3154 tieable and it is valid if X is a SET that copies
3157 if (GET_CODE (to
) == SUBREG
3158 && ! MODES_TIEABLE_P (GET_MODE (to
),
3159 GET_MODE (SUBREG_REG (to
)))
3160 && ! (code
== SUBREG
3161 && MODES_TIEABLE_P (GET_MODE (x
),
3162 GET_MODE (SUBREG_REG (to
))))
3164 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3167 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3169 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3173 /* If we are in a SET_DEST, suppress most cases unless we
3174 have gone inside a MEM, in which case we want to
3175 simplify the address. We assume here that things that
3176 are actually part of the destination have their inner
3177 parts in the first expression. This is true for SUBREG,
3178 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3179 things aside from REG and MEM that should appear in a
3181 new = subst (XEXP (x
, i
), from
, to
,
3183 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3184 || code
== ZERO_EXTRACT
))
3186 && i
== 0), unique_copy
);
3188 /* If we found that we will have to reject this combination,
3189 indicate that by returning the CLOBBER ourselves, rather than
3190 an expression containing it. This will speed things up as
3191 well as prevent accidents where two CLOBBERs are considered
3192 to be equal, thus producing an incorrect simplification. */
3194 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3197 SUBST (XEXP (x
, i
), new);
3202 /* Try to simplify X. If the simplification changed the code, it is likely
3203 that further simplification will help, so loop, but limit the number
3204 of repetitions that will be performed. */
3206 for (i
= 0; i
< 4; i
++)
3208 /* If X is sufficiently simple, don't bother trying to do anything
3210 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3211 x
= simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3213 if (GET_CODE (x
) == code
)
3216 code
= GET_CODE (x
);
3218 /* We no longer know the original mode of operand 0 since we
3219 have changed the form of X) */
3220 op0_mode
= VOIDmode
;
3226 /* Simplify X, a piece of RTL. We just operate on the expression at the
3227 outer level; call `subst' to simplify recursively. Return the new
3230 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3231 will be the iteration even if an expression with a code different from
3232 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3235 simplify_rtx (x
, op0_mode
, last
, in_dest
)
3237 enum machine_mode op0_mode
;
3241 enum rtx_code code
= GET_CODE (x
);
3242 enum machine_mode mode
= GET_MODE (x
);
3246 /* If this is a commutative operation, put a constant last and a complex
3247 expression first. We don't need to do this for comparisons here. */
3248 if (GET_RTX_CLASS (code
) == 'c'
3249 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3250 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
3251 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
3252 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3253 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
3254 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
3257 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3258 SUBST (XEXP (x
, 1), temp
);
3261 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3262 sign extension of a PLUS with a constant, reverse the order of the sign
3263 extension and the addition. Note that this not the same as the original
3264 code, but overflow is undefined for signed values. Also note that the
3265 PLUS will have been partially moved "inside" the sign-extension, so that
3266 the first operand of X will really look like:
3267 (ashiftrt (plus (ashift A C4) C5) C4).
3269 (plus (ashiftrt (ashift A C4) C2) C4)
3270 and replace the first operand of X with that expression. Later parts
3271 of this function may simplify the expression further.
3273 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3274 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3275 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3277 We do this to simplify address expressions. */
3279 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3280 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3281 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3282 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3283 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3284 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3285 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3286 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3287 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3288 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3289 XEXP (XEXP (x
, 0), 1))) != 0)
3292 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3293 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3294 INTVAL (XEXP (XEXP (x
, 0), 1)));
3296 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3297 INTVAL (XEXP (XEXP (x
, 0), 1)));
3299 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3302 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3303 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3304 things. Check for cases where both arms are testing the same
3307 Don't do anything if all operands are very simple. */
3309 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3310 || GET_RTX_CLASS (code
) == '<')
3311 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3312 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3313 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3315 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3316 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3317 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3319 || (GET_RTX_CLASS (code
) == '1'
3320 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3321 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3322 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3325 rtx cond
, true, false;
3327 cond
= if_then_else_cond (x
, &true, &false);
3329 /* If everything is a comparison, what we have is highly unlikely
3330 to be simpler, so don't use it. */
3331 && ! (GET_RTX_CLASS (code
) == '<'
3332 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3333 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3335 rtx cop1
= const0_rtx
;
3336 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3338 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3341 /* Simplify the alternative arms; this may collapse the true and
3342 false arms to store-flag values. */
3343 true = subst (true, pc_rtx
, pc_rtx
, 0, 0);
3344 false = subst (false, pc_rtx
, pc_rtx
, 0, 0);
3346 /* Restarting if we generate a store-flag expression will cause
3347 us to loop. Just drop through in this case. */
3349 /* If the result values are STORE_FLAG_VALUE and zero, we can
3350 just make the comparison operation. */
3351 if (true == const_true_rtx
&& false == const0_rtx
)
3352 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3353 else if (true == const0_rtx
&& false == const_true_rtx
)
3354 x
= gen_binary (reverse_condition (cond_code
), mode
, cond
, cop1
);
3356 /* Likewise, we can make the negate of a comparison operation
3357 if the result values are - STORE_FLAG_VALUE and zero. */
3358 else if (GET_CODE (true) == CONST_INT
3359 && INTVAL (true) == - STORE_FLAG_VALUE
3360 && false == const0_rtx
)
3361 x
= gen_unary (NEG
, mode
, mode
,
3362 gen_binary (cond_code
, mode
, cond
, cop1
));
3363 else if (GET_CODE (false) == CONST_INT
3364 && INTVAL (false) == - STORE_FLAG_VALUE
3365 && true == const0_rtx
)
3366 x
= gen_unary (NEG
, mode
, mode
,
3367 gen_binary (reverse_condition (cond_code
),
3370 return gen_rtx_IF_THEN_ELSE (mode
,
3371 gen_binary (cond_code
, VOIDmode
,
3375 code
= GET_CODE (x
);
3376 op0_mode
= VOIDmode
;
3380 /* Try to fold this expression in case we have constants that weren't
3383 switch (GET_RTX_CLASS (code
))
3386 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3389 temp
= simplify_relational_operation (code
, op0_mode
,
3390 XEXP (x
, 0), XEXP (x
, 1));
3391 #ifdef FLOAT_STORE_FLAG_VALUE
3392 if (temp
!= 0 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3393 temp
= ((temp
== const0_rtx
) ? CONST0_RTX (GET_MODE (x
))
3394 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE
, GET_MODE (x
)));
3399 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3403 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3404 XEXP (x
, 1), XEXP (x
, 2));
3409 x
= temp
, code
= GET_CODE (temp
);
3411 /* First see if we can apply the inverse distributive law. */
3412 if (code
== PLUS
|| code
== MINUS
3413 || code
== AND
|| code
== IOR
|| code
== XOR
)
3415 x
= apply_distributive_law (x
);
3416 code
= GET_CODE (x
);
3419 /* If CODE is an associative operation not otherwise handled, see if we
3420 can associate some operands. This can win if they are constants or
3421 if they are logically related (i.e. (a & b) & a. */
3422 if ((code
== PLUS
|| code
== MINUS
3423 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3424 || code
== DIV
|| code
== UDIV
3425 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3426 && INTEGRAL_MODE_P (mode
))
3428 if (GET_CODE (XEXP (x
, 0)) == code
)
3430 rtx other
= XEXP (XEXP (x
, 0), 0);
3431 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3432 rtx inner_op1
= XEXP (x
, 1);
3435 /* Make sure we pass the constant operand if any as the second
3436 one if this is a commutative operation. */
3437 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3439 rtx tem
= inner_op0
;
3440 inner_op0
= inner_op1
;
3443 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3444 : code
== DIV
? MULT
3445 : code
== UDIV
? MULT
3447 mode
, inner_op0
, inner_op1
);
3449 /* For commutative operations, try the other pair if that one
3451 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3453 other
= XEXP (XEXP (x
, 0), 1);
3454 inner
= simplify_binary_operation (code
, mode
,
3455 XEXP (XEXP (x
, 0), 0),
3460 return gen_binary (code
, mode
, other
, inner
);
3464 /* A little bit of algebraic simplification here. */
3468 /* Ensure that our address has any ASHIFTs converted to MULT in case
3469 address-recognizing predicates are called later. */
3470 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3471 SUBST (XEXP (x
, 0), temp
);
3475 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3476 is paradoxical. If we can't do that safely, then it becomes
3477 something nonsensical so that this combination won't take place. */
3479 if (GET_CODE (SUBREG_REG (x
)) == MEM
3480 && (GET_MODE_SIZE (mode
)
3481 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3483 rtx inner
= SUBREG_REG (x
);
3484 int endian_offset
= 0;
3485 /* Don't change the mode of the MEM
3486 if that would change the meaning of the address. */
3487 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3488 || mode_dependent_address_p (XEXP (inner
, 0)))
3489 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3491 if (BYTES_BIG_ENDIAN
)
3493 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3494 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
3495 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
3496 endian_offset
-= (UNITS_PER_WORD
3497 - GET_MODE_SIZE (GET_MODE (inner
)));
3499 /* Note if the plus_constant doesn't make a valid address
3500 then this combination won't be accepted. */
3501 x
= gen_rtx_MEM (mode
,
3502 plus_constant (XEXP (inner
, 0),
3503 (SUBREG_WORD (x
) * UNITS_PER_WORD
3505 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (inner
);
3506 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (inner
);
3507 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (inner
);
3511 /* If we are in a SET_DEST, these other cases can't apply. */
3515 /* Changing mode twice with SUBREG => just change it once,
3516 or not at all if changing back to starting mode. */
3517 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3519 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
3520 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
3521 return SUBREG_REG (SUBREG_REG (x
));
3523 SUBST_INT (SUBREG_WORD (x
),
3524 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
3525 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3528 /* SUBREG of a hard register => just change the register number
3529 and/or mode. If the hard register is not valid in that mode,
3530 suppress this combination. If the hard register is the stack,
3531 frame, or argument pointer, leave this as a SUBREG. */
3533 if (GET_CODE (SUBREG_REG (x
)) == REG
3534 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3535 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3536 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3537 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3539 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3540 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3542 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3544 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
3546 return gen_rtx_REG (mode
,
3547 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
3549 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3552 /* For a constant, try to pick up the part we want. Handle a full
3553 word and low-order part. Only do this if we are narrowing
3554 the constant; if it is being widened, we have no idea what
3555 the extra bits will have been set to. */
3557 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3558 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3559 && GET_MODE_SIZE (op0_mode
) > UNITS_PER_WORD
3560 && GET_MODE_CLASS (mode
) == MODE_INT
)
3562 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
3568 /* If we want a subreg of a constant, at offset 0,
3569 take the low bits. On a little-endian machine, that's
3570 always valid. On a big-endian machine, it's valid
3571 only if the constant's mode fits in one word. Note that we
3572 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3573 if (CONSTANT_P (SUBREG_REG (x
))
3574 && ((GET_MODE_SIZE (op0_mode
) <= UNITS_PER_WORD
3575 || ! WORDS_BIG_ENDIAN
)
3576 ? SUBREG_WORD (x
) == 0
3578 == ((GET_MODE_SIZE (op0_mode
)
3579 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
3581 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (op0_mode
)
3582 && (! WORDS_BIG_ENDIAN
3583 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3584 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3586 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3587 since we are saying that the high bits don't matter. */
3588 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3589 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3590 return SUBREG_REG (x
);
3592 /* Note that we cannot do any narrowing for non-constants since
3593 we might have been counting on using the fact that some bits were
3594 zero. We now do this in the SET. */
3599 /* (not (plus X -1)) can become (neg X). */
3600 if (GET_CODE (XEXP (x
, 0)) == PLUS
3601 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3602 return gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
3604 /* Similarly, (not (neg X)) is (plus X -1). */
3605 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3606 return gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3609 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3610 if (GET_CODE (XEXP (x
, 0)) == XOR
3611 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3612 && (temp
= simplify_unary_operation (NOT
, mode
,
3613 XEXP (XEXP (x
, 0), 1),
3615 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3617 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3618 other than 1, but that is not valid. We could do a similar
3619 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3620 but this doesn't seem common enough to bother with. */
3621 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3622 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3623 return gen_rtx_ROTATE (mode
, gen_unary (NOT
, mode
, mode
, const1_rtx
),
3624 XEXP (XEXP (x
, 0), 1));
3626 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3627 && subreg_lowpart_p (XEXP (x
, 0))
3628 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3629 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3630 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3631 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3633 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3635 x
= gen_rtx_ROTATE (inner_mode
,
3636 gen_unary (NOT
, inner_mode
, inner_mode
,
3638 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3639 return gen_lowpart_for_combine (mode
, x
);
3642 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3643 reversing the comparison code if valid. */
3644 if (STORE_FLAG_VALUE
== -1
3645 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3646 && reversible_comparison_p (XEXP (x
, 0)))
3647 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3648 mode
, XEXP (XEXP (x
, 0), 0),
3649 XEXP (XEXP (x
, 0), 1));
3651 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3652 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3653 perform the above simplification. */
3655 if (STORE_FLAG_VALUE
== -1
3656 && XEXP (x
, 1) == const1_rtx
3657 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3658 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3659 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3660 return gen_rtx_combine (GE
, mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3662 /* Apply De Morgan's laws to reduce number of patterns for machines
3663 with negating logical insns (and-not, nand, etc.). If result has
3664 only one NOT, put it first, since that is how the patterns are
3667 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3669 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3671 if (GET_CODE (in1
) == NOT
)
3672 in1
= XEXP (in1
, 0);
3674 in1
= gen_rtx_combine (NOT
, GET_MODE (in1
), in1
);
3676 if (GET_CODE (in2
) == NOT
)
3677 in2
= XEXP (in2
, 0);
3678 else if (GET_CODE (in2
) == CONST_INT
3679 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3680 in2
= GEN_INT (GET_MODE_MASK (mode
) & ~ INTVAL (in2
));
3682 in2
= gen_rtx_combine (NOT
, GET_MODE (in2
), in2
);
3684 if (GET_CODE (in2
) == NOT
)
3687 in2
= in1
; in1
= tem
;
3690 return gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3696 /* (neg (plus X 1)) can become (not X). */
3697 if (GET_CODE (XEXP (x
, 0)) == PLUS
3698 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3699 return gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
3701 /* Similarly, (neg (not X)) is (plus X 1). */
3702 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3703 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3705 /* (neg (minus X Y)) can become (minus Y X). */
3706 if (GET_CODE (XEXP (x
, 0)) == MINUS
3707 && (! FLOAT_MODE_P (mode
)
3708 /* x-y != -(y-x) with IEEE floating point. */
3709 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3711 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3712 XEXP (XEXP (x
, 0), 0));
3714 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3715 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3716 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3717 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3719 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3720 if we can then eliminate the NEG (e.g.,
3721 if the operand is a constant). */
3723 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3725 temp
= simplify_unary_operation (NEG
, mode
,
3726 XEXP (XEXP (x
, 0), 0), mode
);
3729 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
3734 temp
= expand_compound_operation (XEXP (x
, 0));
3736 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3737 replaced by (lshiftrt X C). This will convert
3738 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3740 if (GET_CODE (temp
) == ASHIFTRT
3741 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3742 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3743 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3744 INTVAL (XEXP (temp
, 1)));
3746 /* If X has only a single bit that might be nonzero, say, bit I, convert
3747 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3748 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3749 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3750 or a SUBREG of one since we'd be making the expression more
3751 complex if it was just a register. */
3753 if (GET_CODE (temp
) != REG
3754 && ! (GET_CODE (temp
) == SUBREG
3755 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3756 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3758 rtx temp1
= simplify_shift_const
3759 (NULL_RTX
, ASHIFTRT
, mode
,
3760 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3761 GET_MODE_BITSIZE (mode
) - 1 - i
),
3762 GET_MODE_BITSIZE (mode
) - 1 - i
);
3764 /* If all we did was surround TEMP with the two shifts, we
3765 haven't improved anything, so don't use it. Otherwise,
3766 we are better off with TEMP1. */
3767 if (GET_CODE (temp1
) != ASHIFTRT
3768 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3769 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3775 /* We can't handle truncation to a partial integer mode here
3776 because we don't know the real bitsize of the partial
3778 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3781 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3782 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3783 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3785 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3786 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3788 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3789 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3790 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3791 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3792 return XEXP (XEXP (x
, 0), 0);
3794 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3795 (OP:SI foo:SI) if OP is NEG or ABS. */
3796 if ((GET_CODE (XEXP (x
, 0)) == ABS
3797 || GET_CODE (XEXP (x
, 0)) == NEG
)
3798 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3799 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3800 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3801 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
3802 XEXP (XEXP (XEXP (x
, 0), 0), 0));
3804 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3806 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3807 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3808 && subreg_lowpart_p (XEXP (x
, 0)))
3809 return SUBREG_REG (XEXP (x
, 0));
3811 /* If we know that the value is already truncated, we can
3812 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION is
3813 nonzero for the corresponding modes. */
3814 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3815 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3816 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3817 >= GET_MODE_BITSIZE (mode
) + 1)
3818 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3820 /* A truncate of a comparison can be replaced with a subreg if
3821 STORE_FLAG_VALUE permits. This is like the previous test,
3822 but it works even if the comparison is done in a mode larger
3823 than HOST_BITS_PER_WIDE_INT. */
3824 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3825 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3826 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
&~ GET_MODE_MASK (mode
)) == 0)
3827 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3829 /* Similarly, a truncate of a register whose value is a
3830 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3832 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3833 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
&~ GET_MODE_MASK (mode
)) == 0
3834 && (temp
= get_last_value (XEXP (x
, 0)))
3835 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
3836 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3840 case FLOAT_TRUNCATE
:
3841 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3842 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
3843 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3844 return XEXP (XEXP (x
, 0), 0);
3846 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3847 (OP:SF foo:SF) if OP is NEG or ABS. */
3848 if ((GET_CODE (XEXP (x
, 0)) == ABS
3849 || GET_CODE (XEXP (x
, 0)) == NEG
)
3850 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
3851 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3852 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
3853 XEXP (XEXP (XEXP (x
, 0), 0), 0));
3855 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3856 is (float_truncate:SF x). */
3857 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3858 && subreg_lowpart_p (XEXP (x
, 0))
3859 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
3860 return SUBREG_REG (XEXP (x
, 0));
3865 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3866 using cc0, in which case we want to leave it as a COMPARE
3867 so we can distinguish it from a register-register-copy. */
3868 if (XEXP (x
, 1) == const0_rtx
)
3871 /* In IEEE floating point, x-0 is not the same as x. */
3872 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3873 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
3875 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
3881 /* (const (const X)) can become (const X). Do it this way rather than
3882 returning the inner CONST since CONST can be shared with a
3884 if (GET_CODE (XEXP (x
, 0)) == CONST
)
3885 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3890 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3891 can add in an offset. find_split_point will split this address up
3892 again if it doesn't match. */
3893 if (GET_CODE (XEXP (x
, 0)) == HIGH
3894 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
3900 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3901 outermost. That's because that's the way indexed addresses are
3902 supposed to appear. This code used to check many more cases, but
3903 they are now checked elsewhere. */
3904 if (GET_CODE (XEXP (x
, 0)) == PLUS
3905 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
3906 return gen_binary (PLUS
, mode
,
3907 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3909 XEXP (XEXP (x
, 0), 1));
3911 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3912 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3913 bit-field and can be replaced by either a sign_extend or a
3914 sign_extract. The `and' may be a zero_extend. */
3915 if (GET_CODE (XEXP (x
, 0)) == XOR
3916 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3917 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3918 && INTVAL (XEXP (x
, 1)) == - INTVAL (XEXP (XEXP (x
, 0), 1))
3919 && (i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
3920 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3921 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
3922 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3923 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
3924 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
3925 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
3926 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
3928 return simplify_shift_const
3929 (NULL_RTX
, ASHIFTRT
, mode
,
3930 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3931 XEXP (XEXP (XEXP (x
, 0), 0), 0),
3932 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
3933 GET_MODE_BITSIZE (mode
) - (i
+ 1));
3935 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3936 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3937 is 1. This produces better code than the alternative immediately
3939 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3940 && reversible_comparison_p (XEXP (x
, 0))
3941 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
3942 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
)))
3944 gen_unary (NEG
, mode
, mode
,
3945 gen_binary (reverse_condition (GET_CODE (XEXP (x
, 0))),
3946 mode
, XEXP (XEXP (x
, 0), 0),
3947 XEXP (XEXP (x
, 0), 1)));
3949 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3950 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3951 the bitsize of the mode - 1. This allows simplification of
3952 "a = (b & 8) == 0;" */
3953 if (XEXP (x
, 1) == constm1_rtx
3954 && GET_CODE (XEXP (x
, 0)) != REG
3955 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
3956 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
3957 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
3958 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
3959 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3960 gen_rtx_combine (XOR
, mode
,
3961 XEXP (x
, 0), const1_rtx
),
3962 GET_MODE_BITSIZE (mode
) - 1),
3963 GET_MODE_BITSIZE (mode
) - 1);
3965 /* If we are adding two things that have no bits in common, convert
3966 the addition into an IOR. This will often be further simplified,
3967 for example in cases like ((a & 1) + (a & 2)), which can
3970 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3971 && (nonzero_bits (XEXP (x
, 0), mode
)
3972 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
3973 return gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3977 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3978 by reversing the comparison code if valid. */
3979 if (STORE_FLAG_VALUE
== 1
3980 && XEXP (x
, 0) == const1_rtx
3981 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
3982 && reversible_comparison_p (XEXP (x
, 1)))
3983 return gen_binary (reverse_condition (GET_CODE (XEXP (x
, 1))),
3984 mode
, XEXP (XEXP (x
, 1), 0),
3985 XEXP (XEXP (x
, 1), 1));
3987 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3988 (and <foo> (const_int pow2-1)) */
3989 if (GET_CODE (XEXP (x
, 1)) == AND
3990 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3991 && exact_log2 (- INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
3992 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3993 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
3994 - INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
3996 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3998 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
3999 return gen_binary (MINUS
, mode
,
4000 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4001 XEXP (XEXP (x
, 1), 0)),
4002 XEXP (XEXP (x
, 1), 1));
4006 /* If we have (mult (plus A B) C), apply the distributive law and then
4007 the inverse distributive law to see if things simplify. This
4008 occurs mostly in addresses, often when unrolling loops. */
4010 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4012 x
= apply_distributive_law
4013 (gen_binary (PLUS
, mode
,
4014 gen_binary (MULT
, mode
,
4015 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4016 gen_binary (MULT
, mode
,
4017 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
4019 if (GET_CODE (x
) != MULT
)
4025 /* If this is a divide by a power of two, treat it as a shift if
4026 its first operand is a shift. */
4027 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4028 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4029 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4030 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4031 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4032 || GET_CODE (XEXP (x
, 0)) == ROTATE
4033 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4034 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4038 case GT
: case GTU
: case GE
: case GEU
:
4039 case LT
: case LTU
: case LE
: case LEU
:
4040 /* If the first operand is a condition code, we can't do anything
4042 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4043 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4045 && XEXP (x
, 0) != cc0_rtx
4049 rtx op0
= XEXP (x
, 0);
4050 rtx op1
= XEXP (x
, 1);
4051 enum rtx_code new_code
;
4053 if (GET_CODE (op0
) == COMPARE
)
4054 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4056 /* Simplify our comparison, if possible. */
4057 new_code
= simplify_comparison (code
, &op0
, &op1
);
4059 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4060 if only the low-order bit is possibly nonzero in X (such as when
4061 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4062 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4063 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4066 Remove any ZERO_EXTRACT we made when thinking this was a
4067 comparison. It may now be simpler to use, e.g., an AND. If a
4068 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4069 the call to make_compound_operation in the SET case. */
4071 if (STORE_FLAG_VALUE
== 1
4072 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4073 && op1
== const0_rtx
&& nonzero_bits (op0
, mode
) == 1)
4074 return gen_lowpart_for_combine (mode
,
4075 expand_compound_operation (op0
));
4077 else if (STORE_FLAG_VALUE
== 1
4078 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4079 && op1
== const0_rtx
4080 && (num_sign_bit_copies (op0
, mode
)
4081 == GET_MODE_BITSIZE (mode
)))
4083 op0
= expand_compound_operation (op0
);
4084 return gen_unary (NEG
, mode
, mode
,
4085 gen_lowpart_for_combine (mode
, op0
));
4088 else if (STORE_FLAG_VALUE
== 1
4089 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4090 && op1
== const0_rtx
4091 && nonzero_bits (op0
, mode
) == 1)
4093 op0
= expand_compound_operation (op0
);
4094 return gen_binary (XOR
, mode
,
4095 gen_lowpart_for_combine (mode
, op0
),
4099 else if (STORE_FLAG_VALUE
== 1
4100 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4101 && op1
== const0_rtx
4102 && (num_sign_bit_copies (op0
, mode
)
4103 == GET_MODE_BITSIZE (mode
)))
4105 op0
= expand_compound_operation (op0
);
4106 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4109 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4111 if (STORE_FLAG_VALUE
== -1
4112 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4113 && op1
== const0_rtx
4114 && (num_sign_bit_copies (op0
, mode
)
4115 == GET_MODE_BITSIZE (mode
)))
4116 return gen_lowpart_for_combine (mode
,
4117 expand_compound_operation (op0
));
4119 else if (STORE_FLAG_VALUE
== -1
4120 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4121 && op1
== const0_rtx
4122 && nonzero_bits (op0
, mode
) == 1)
4124 op0
= expand_compound_operation (op0
);
4125 return gen_unary (NEG
, mode
, mode
,
4126 gen_lowpart_for_combine (mode
, op0
));
4129 else if (STORE_FLAG_VALUE
== -1
4130 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4131 && op1
== const0_rtx
4132 && (num_sign_bit_copies (op0
, mode
)
4133 == GET_MODE_BITSIZE (mode
)))
4135 op0
= expand_compound_operation (op0
);
4136 return gen_unary (NOT
, mode
, mode
,
4137 gen_lowpart_for_combine (mode
, op0
));
4140 /* If X is 0/1, (eq X 0) is X-1. */
4141 else if (STORE_FLAG_VALUE
== -1
4142 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4143 && op1
== const0_rtx
4144 && nonzero_bits (op0
, mode
) == 1)
4146 op0
= expand_compound_operation (op0
);
4147 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4150 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4151 one bit that might be nonzero, we can convert (ne x 0) to
4152 (ashift x c) where C puts the bit in the sign bit. Remove any
4153 AND with STORE_FLAG_VALUE when we are done, since we are only
4154 going to test the sign bit. */
4155 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4156 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4157 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4158 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4159 && op1
== const0_rtx
4160 && mode
== GET_MODE (op0
)
4161 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4163 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4164 expand_compound_operation (op0
),
4165 GET_MODE_BITSIZE (mode
) - 1 - i
);
4166 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4172 /* If the code changed, return a whole new comparison. */
4173 if (new_code
!= code
)
4174 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
4176 /* Otherwise, keep this operation, but maybe change its operands.
4177 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4178 SUBST (XEXP (x
, 0), op0
);
4179 SUBST (XEXP (x
, 1), op1
);
4184 return simplify_if_then_else (x
);
4190 /* If we are processing SET_DEST, we are done. */
4194 return expand_compound_operation (x
);
4197 return simplify_set (x
);
4202 return simplify_logical (x
, last
);
4205 /* (abs (neg <foo>)) -> (abs <foo>) */
4206 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4207 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4209 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4211 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4214 /* If operand is something known to be positive, ignore the ABS. */
4215 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4216 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4217 <= HOST_BITS_PER_WIDE_INT
)
4218 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4219 & ((HOST_WIDE_INT
) 1
4220 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4225 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4226 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4227 return gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
4232 /* (ffs (*_extend <X>)) = (ffs <X>) */
4233 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4234 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4235 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4239 /* (float (sign_extend <X>)) = (float <X>). */
4240 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4241 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4249 /* If this is a shift by a constant amount, simplify it. */
4250 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4251 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4252 INTVAL (XEXP (x
, 1)));
4254 #ifdef SHIFT_COUNT_TRUNCATED
4255 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4257 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4259 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4273 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4276 simplify_if_then_else (x
)
4279 enum machine_mode mode
= GET_MODE (x
);
4280 rtx cond
= XEXP (x
, 0);
4281 rtx
true = XEXP (x
, 1);
4282 rtx
false = XEXP (x
, 2);
4283 enum rtx_code true_code
= GET_CODE (cond
);
4284 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4288 /* Simplify storing of the truth value. */
4289 if (comparison_p
&& true == const_true_rtx
&& false == const0_rtx
)
4290 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4292 /* Also when the truth value has to be reversed. */
4293 if (comparison_p
&& reversible_comparison_p (cond
)
4294 && true == const0_rtx
&& false == const_true_rtx
)
4295 return gen_binary (reverse_condition (true_code
),
4296 mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4298 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4299 in it is being compared against certain values. Get the true and false
4300 comparisons and see if that says anything about the value of each arm. */
4302 if (comparison_p
&& reversible_comparison_p (cond
)
4303 && GET_CODE (XEXP (cond
, 0)) == REG
)
4306 rtx from
= XEXP (cond
, 0);
4307 enum rtx_code false_code
= reverse_condition (true_code
);
4308 rtx true_val
= XEXP (cond
, 1);
4309 rtx false_val
= true_val
;
4312 /* If FALSE_CODE is EQ, swap the codes and arms. */
4314 if (false_code
== EQ
)
4316 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4317 temp
= true, true = false, false = temp
;
4320 /* If we are comparing against zero and the expression being tested has
4321 only a single bit that might be nonzero, that is its value when it is
4322 not equal to zero. Similarly if it is known to be -1 or 0. */
4324 if (true_code
== EQ
&& true_val
== const0_rtx
4325 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4326 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4327 else if (true_code
== EQ
&& true_val
== const0_rtx
4328 && (num_sign_bit_copies (from
, GET_MODE (from
))
4329 == GET_MODE_BITSIZE (GET_MODE (from
))))
4330 false_code
= EQ
, false_val
= constm1_rtx
;
4332 /* Now simplify an arm if we know the value of the register in the
4333 branch and it is used in the arm. Be careful due to the potential
4334 of locally-shared RTL. */
4336 if (reg_mentioned_p (from
, true))
4337 true = subst (known_cond (copy_rtx (true), true_code
, from
, true_val
),
4338 pc_rtx
, pc_rtx
, 0, 0);
4339 if (reg_mentioned_p (from
, false))
4340 false = subst (known_cond (copy_rtx (false), false_code
,
4342 pc_rtx
, pc_rtx
, 0, 0);
4344 SUBST (XEXP (x
, 1), swapped
? false : true);
4345 SUBST (XEXP (x
, 2), swapped
? true : false);
4347 true = XEXP (x
, 1), false = XEXP (x
, 2), true_code
= GET_CODE (cond
);
4350 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4351 reversed, do so to avoid needing two sets of patterns for
4352 subtract-and-branch insns. Similarly if we have a constant in the true
4353 arm, the false arm is the same as the first operand of the comparison, or
4354 the false arm is more complicated than the true arm. */
4356 if (comparison_p
&& reversible_comparison_p (cond
)
4358 || (CONSTANT_P (true)
4359 && GET_CODE (false) != CONST_INT
&& false != pc_rtx
)
4360 || true == const0_rtx
4361 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4362 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4363 || (GET_CODE (true) == SUBREG
4364 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4365 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4366 || reg_mentioned_p (true, false)
4367 || rtx_equal_p (false, XEXP (cond
, 0))))
4369 true_code
= reverse_condition (true_code
);
4371 gen_binary (true_code
, GET_MODE (cond
), XEXP (cond
, 0),
4374 SUBST (XEXP (x
, 1), false);
4375 SUBST (XEXP (x
, 2), true);
4377 temp
= true, true = false, false = temp
, cond
= XEXP (x
, 0);
4379 /* It is possible that the conditional has been simplified out. */
4380 true_code
= GET_CODE (cond
);
4381 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4384 /* If the two arms are identical, we don't need the comparison. */
4386 if (rtx_equal_p (true, false) && ! side_effects_p (cond
))
4389 /* Convert a == b ? b : a to "a". */
4390 if (true_code
== EQ
&& ! side_effects_p (cond
)
4391 && rtx_equal_p (XEXP (cond
, 0), false)
4392 && rtx_equal_p (XEXP (cond
, 1), true))
4394 else if (true_code
== NE
&& ! side_effects_p (cond
)
4395 && rtx_equal_p (XEXP (cond
, 0), true)
4396 && rtx_equal_p (XEXP (cond
, 1), false))
4399 /* Look for cases where we have (abs x) or (neg (abs X)). */
4401 if (GET_MODE_CLASS (mode
) == MODE_INT
4402 && GET_CODE (false) == NEG
4403 && rtx_equal_p (true, XEXP (false, 0))
4405 && rtx_equal_p (true, XEXP (cond
, 0))
4406 && ! side_effects_p (true))
4411 return gen_unary (ABS
, mode
, mode
, true);
4414 return gen_unary (NEG
, mode
, mode
, gen_unary (ABS
, mode
, mode
, true));
4419 /* Look for MIN or MAX. */
4421 if ((! FLOAT_MODE_P (mode
) || flag_fast_math
)
4423 && rtx_equal_p (XEXP (cond
, 0), true)
4424 && rtx_equal_p (XEXP (cond
, 1), false)
4425 && ! side_effects_p (cond
))
4430 return gen_binary (SMAX
, mode
, true, false);
4433 return gen_binary (SMIN
, mode
, true, false);
4436 return gen_binary (UMAX
, mode
, true, false);
4439 return gen_binary (UMIN
, mode
, true, false);
4444 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4445 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4446 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4447 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4448 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4449 neither 1 or -1, but it isn't worth checking for. */
4451 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4452 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4454 rtx t
= make_compound_operation (true, SET
);
4455 rtx f
= make_compound_operation (false, SET
);
4456 rtx cond_op0
= XEXP (cond
, 0);
4457 rtx cond_op1
= XEXP (cond
, 1);
4458 enum rtx_code op
, extend_op
= NIL
;
4459 enum machine_mode m
= mode
;
4462 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4463 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4464 || GET_CODE (t
) == ASHIFT
4465 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4466 && rtx_equal_p (XEXP (t
, 0), f
))
4467 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4469 /* If an identity-zero op is commutative, check whether there
4470 would be a match if we swapped the operands. */
4471 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4472 || GET_CODE (t
) == XOR
)
4473 && rtx_equal_p (XEXP (t
, 1), f
))
4474 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4475 else if (GET_CODE (t
) == SIGN_EXTEND
4476 && (GET_CODE (XEXP (t
, 0)) == PLUS
4477 || GET_CODE (XEXP (t
, 0)) == MINUS
4478 || GET_CODE (XEXP (t
, 0)) == IOR
4479 || GET_CODE (XEXP (t
, 0)) == XOR
4480 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4481 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4482 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4483 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4484 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4485 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4486 && (num_sign_bit_copies (f
, GET_MODE (f
))
4487 > (GET_MODE_BITSIZE (mode
)
4488 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4490 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4491 extend_op
= SIGN_EXTEND
;
4492 m
= GET_MODE (XEXP (t
, 0));
4494 else if (GET_CODE (t
) == SIGN_EXTEND
4495 && (GET_CODE (XEXP (t
, 0)) == PLUS
4496 || GET_CODE (XEXP (t
, 0)) == IOR
4497 || GET_CODE (XEXP (t
, 0)) == XOR
)
4498 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4499 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4500 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4501 && (num_sign_bit_copies (f
, GET_MODE (f
))
4502 > (GET_MODE_BITSIZE (mode
)
4503 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4505 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4506 extend_op
= SIGN_EXTEND
;
4507 m
= GET_MODE (XEXP (t
, 0));
4509 else if (GET_CODE (t
) == ZERO_EXTEND
4510 && (GET_CODE (XEXP (t
, 0)) == PLUS
4511 || GET_CODE (XEXP (t
, 0)) == MINUS
4512 || GET_CODE (XEXP (t
, 0)) == IOR
4513 || GET_CODE (XEXP (t
, 0)) == XOR
4514 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4515 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4516 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4517 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4518 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4519 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4520 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4521 && ((nonzero_bits (f
, GET_MODE (f
))
4522 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4525 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4526 extend_op
= ZERO_EXTEND
;
4527 m
= GET_MODE (XEXP (t
, 0));
4529 else if (GET_CODE (t
) == ZERO_EXTEND
4530 && (GET_CODE (XEXP (t
, 0)) == PLUS
4531 || GET_CODE (XEXP (t
, 0)) == IOR
4532 || GET_CODE (XEXP (t
, 0)) == XOR
)
4533 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4534 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4535 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4536 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4537 && ((nonzero_bits (f
, GET_MODE (f
))
4538 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4541 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4542 extend_op
= ZERO_EXTEND
;
4543 m
= GET_MODE (XEXP (t
, 0));
4548 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4549 pc_rtx
, pc_rtx
, 0, 0);
4550 temp
= gen_binary (MULT
, m
, temp
,
4551 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4552 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4553 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4555 if (extend_op
!= NIL
)
4556 temp
= gen_unary (extend_op
, mode
, m
, temp
);
4562 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4563 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4564 negation of a single bit, we can convert this operation to a shift. We
4565 can actually do this more generally, but it doesn't seem worth it. */
4567 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4568 && false == const0_rtx
&& GET_CODE (true) == CONST_INT
4569 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4570 && (i
= exact_log2 (INTVAL (true))) >= 0)
4571 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4572 == GET_MODE_BITSIZE (mode
))
4573 && (i
= exact_log2 (- INTVAL (true))) >= 0)))
4575 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4576 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4581 /* Simplify X, a SET expression. Return the new expression. */
4587 rtx src
= SET_SRC (x
);
4588 rtx dest
= SET_DEST (x
);
4589 enum machine_mode mode
4590 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4594 /* (set (pc) (return)) gets written as (return). */
4595 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4598 /* Now that we know for sure which bits of SRC we are using, see if we can
4599 simplify the expression for the object knowing that we only need the
4602 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4603 src
= force_to_mode (src
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
4605 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4606 the comparison result and try to simplify it unless we already have used
4607 undobuf.other_insn. */
4608 if ((GET_CODE (src
) == COMPARE
4613 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4614 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4615 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4616 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4618 enum rtx_code old_code
= GET_CODE (*cc_use
);
4619 enum rtx_code new_code
;
4621 int other_changed
= 0;
4622 enum machine_mode compare_mode
= GET_MODE (dest
);
4624 if (GET_CODE (src
) == COMPARE
)
4625 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4627 op0
= src
, op1
= const0_rtx
;
4629 /* Simplify our comparison, if possible. */
4630 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4632 #ifdef EXTRA_CC_MODES
4633 /* If this machine has CC modes other than CCmode, check to see if we
4634 need to use a different CC mode here. */
4635 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4636 #endif /* EXTRA_CC_MODES */
4638 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4639 /* If the mode changed, we have to change SET_DEST, the mode in the
4640 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4641 a hard register, just build new versions with the proper mode. If it
4642 is a pseudo, we lose unless it is only time we set the pseudo, in
4643 which case we can safely change its mode. */
4644 if (compare_mode
!= GET_MODE (dest
))
4646 int regno
= REGNO (dest
);
4647 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
4649 if (regno
< FIRST_PSEUDO_REGISTER
4650 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
4652 if (regno
>= FIRST_PSEUDO_REGISTER
)
4653 SUBST (regno_reg_rtx
[regno
], new_dest
);
4655 SUBST (SET_DEST (x
), new_dest
);
4656 SUBST (XEXP (*cc_use
, 0), new_dest
);
4664 /* If the code changed, we have to build a new comparison in
4665 undobuf.other_insn. */
4666 if (new_code
!= old_code
)
4668 unsigned HOST_WIDE_INT mask
;
4670 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
4673 /* If the only change we made was to change an EQ into an NE or
4674 vice versa, OP0 has only one bit that might be nonzero, and OP1
4675 is zero, check if changing the user of the condition code will
4676 produce a valid insn. If it won't, we can keep the original code
4677 in that insn by surrounding our operation with an XOR. */
4679 if (((old_code
== NE
&& new_code
== EQ
)
4680 || (old_code
== EQ
&& new_code
== NE
))
4681 && ! other_changed
&& op1
== const0_rtx
4682 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4683 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4685 rtx pat
= PATTERN (other_insn
), note
= 0;
4687 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
4688 && ! check_asm_operands (pat
)))
4690 PUT_CODE (*cc_use
, old_code
);
4693 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4701 undobuf
.other_insn
= other_insn
;
4704 /* If we are now comparing against zero, change our source if
4705 needed. If we do not use cc0, we always have a COMPARE. */
4706 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
4708 SUBST (SET_SRC (x
), op0
);
4714 /* Otherwise, if we didn't previously have a COMPARE in the
4715 correct mode, we need one. */
4716 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
4719 gen_rtx_combine (COMPARE
, compare_mode
, op0
, op1
));
4724 /* Otherwise, update the COMPARE if needed. */
4725 SUBST (XEXP (src
, 0), op0
);
4726 SUBST (XEXP (src
, 1), op1
);
4731 /* Get SET_SRC in a form where we have placed back any
4732 compound expressions. Then do the checks below. */
4733 src
= make_compound_operation (src
, SET
);
4734 SUBST (SET_SRC (x
), src
);
4737 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4738 and X being a REG or (subreg (reg)), we may be able to convert this to
4739 (set (subreg:m2 x) (op)).
4741 We can always do this if M1 is narrower than M2 because that means that
4742 we only care about the low bits of the result.
4744 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4745 perform a narrower operation than requested since the high-order bits will
4746 be undefined. On machine where it is defined, this transformation is safe
4747 as long as M1 and M2 have the same number of words. */
4749 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4750 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
4751 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
4753 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
4754 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
4755 #ifndef WORD_REGISTER_OPERATIONS
4756 && (GET_MODE_SIZE (GET_MODE (src
))
4757 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4759 #ifdef CLASS_CANNOT_CHANGE_SIZE
4760 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
4761 && (TEST_HARD_REG_BIT
4762 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_SIZE
],
4764 && (GET_MODE_SIZE (GET_MODE (src
))
4765 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
4767 && (GET_CODE (dest
) == REG
4768 || (GET_CODE (dest
) == SUBREG
4769 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
4771 SUBST (SET_DEST (x
),
4772 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
4774 SUBST (SET_SRC (x
), SUBREG_REG (src
));
4776 src
= SET_SRC (x
), dest
= SET_DEST (x
);
4779 #ifdef LOAD_EXTEND_OP
4780 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4781 would require a paradoxical subreg. Replace the subreg with a
4782 zero_extend to avoid the reload that would otherwise be required. */
4784 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4785 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
4786 && SUBREG_WORD (src
) == 0
4787 && (GET_MODE_SIZE (GET_MODE (src
))
4788 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4789 && GET_CODE (SUBREG_REG (src
)) == MEM
)
4792 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
4793 GET_MODE (src
), XEXP (src
, 0)));
4799 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4800 are comparing an item known to be 0 or -1 against 0, use a logical
4801 operation instead. Check for one of the arms being an IOR of the other
4802 arm with some value. We compute three terms to be IOR'ed together. In
4803 practice, at most two will be nonzero. Then we do the IOR's. */
4805 if (GET_CODE (dest
) != PC
4806 && GET_CODE (src
) == IF_THEN_ELSE
4807 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
4808 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
4809 && XEXP (XEXP (src
, 0), 1) == const0_rtx
4810 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
4811 #ifdef HAVE_conditional_move
4812 && ! can_conditionally_move_p (GET_MODE (src
))
4814 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
4815 GET_MODE (XEXP (XEXP (src
, 0), 0)))
4816 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
4817 && ! side_effects_p (src
))
4819 rtx
true = (GET_CODE (XEXP (src
, 0)) == NE
4820 ? XEXP (src
, 1) : XEXP (src
, 2));
4821 rtx
false = (GET_CODE (XEXP (src
, 0)) == NE
4822 ? XEXP (src
, 2) : XEXP (src
, 1));
4823 rtx term1
= const0_rtx
, term2
, term3
;
4825 if (GET_CODE (true) == IOR
&& rtx_equal_p (XEXP (true, 0), false))
4826 term1
= false, true = XEXP (true, 1), false = const0_rtx
;
4827 else if (GET_CODE (true) == IOR
4828 && rtx_equal_p (XEXP (true, 1), false))
4829 term1
= false, true = XEXP (true, 0), false = const0_rtx
;
4830 else if (GET_CODE (false) == IOR
4831 && rtx_equal_p (XEXP (false, 0), true))
4832 term1
= true, false = XEXP (false, 1), true = const0_rtx
;
4833 else if (GET_CODE (false) == IOR
4834 && rtx_equal_p (XEXP (false, 1), true))
4835 term1
= true, false = XEXP (false, 0), true = const0_rtx
;
4837 term2
= gen_binary (AND
, GET_MODE (src
), XEXP (XEXP (src
, 0), 0), true);
4838 term3
= gen_binary (AND
, GET_MODE (src
),
4839 gen_unary (NOT
, GET_MODE (src
), GET_MODE (src
),
4840 XEXP (XEXP (src
, 0), 0)),
4844 gen_binary (IOR
, GET_MODE (src
),
4845 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
4851 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4852 whole thing fail. */
4853 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
4855 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
4858 /* Convert this into a field assignment operation, if possible. */
4859 return make_field_assignment (x
);
4862 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4863 result. LAST is nonzero if this is the last retry. */
4866 simplify_logical (x
, last
)
4870 enum machine_mode mode
= GET_MODE (x
);
4871 rtx op0
= XEXP (x
, 0);
4872 rtx op1
= XEXP (x
, 1);
4874 switch (GET_CODE (x
))
4877 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4878 insn (and may simplify more). */
4879 if (GET_CODE (op0
) == XOR
4880 && rtx_equal_p (XEXP (op0
, 0), op1
)
4881 && ! side_effects_p (op1
))
4882 x
= gen_binary (AND
, mode
,
4883 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)), op1
);
4885 if (GET_CODE (op0
) == XOR
4886 && rtx_equal_p (XEXP (op0
, 1), op1
)
4887 && ! side_effects_p (op1
))
4888 x
= gen_binary (AND
, mode
,
4889 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)), op1
);
4891 /* Similarly for (~ (A ^ B)) & A. */
4892 if (GET_CODE (op0
) == NOT
4893 && GET_CODE (XEXP (op0
, 0)) == XOR
4894 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
4895 && ! side_effects_p (op1
))
4896 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
4898 if (GET_CODE (op0
) == NOT
4899 && GET_CODE (XEXP (op0
, 0)) == XOR
4900 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
4901 && ! side_effects_p (op1
))
4902 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
4904 if (GET_CODE (op1
) == CONST_INT
)
4906 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
4908 /* If we have (ior (and (X C1) C2)) and the next restart would be
4909 the last, simplify this by making C1 as small as possible
4912 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
4913 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
4914 && GET_CODE (op1
) == CONST_INT
)
4915 return gen_binary (IOR
, mode
,
4916 gen_binary (AND
, mode
, XEXP (op0
, 0),
4917 GEN_INT (INTVAL (XEXP (op0
, 1))
4918 & ~ INTVAL (op1
))), op1
);
4920 if (GET_CODE (x
) != AND
)
4923 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
4924 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
4925 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
4928 /* Convert (A | B) & A to A. */
4929 if (GET_CODE (op0
) == IOR
4930 && (rtx_equal_p (XEXP (op0
, 0), op1
)
4931 || rtx_equal_p (XEXP (op0
, 1), op1
))
4932 && ! side_effects_p (XEXP (op0
, 0))
4933 && ! side_effects_p (XEXP (op0
, 1)))
4936 /* In the following group of tests (and those in case IOR below),
4937 we start with some combination of logical operations and apply
4938 the distributive law followed by the inverse distributive law.
4939 Most of the time, this results in no change. However, if some of
4940 the operands are the same or inverses of each other, simplifications
4943 For example, (and (ior A B) (not B)) can occur as the result of
4944 expanding a bit field assignment. When we apply the distributive
4945 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4946 which then simplifies to (and (A (not B))).
4948 If we have (and (ior A B) C), apply the distributive law and then
4949 the inverse distributive law to see if things simplify. */
4951 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
4953 x
= apply_distributive_law
4954 (gen_binary (GET_CODE (op0
), mode
,
4955 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
4956 gen_binary (AND
, mode
, XEXP (op0
, 1), op1
)));
4957 if (GET_CODE (x
) != AND
)
4961 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
4962 return apply_distributive_law
4963 (gen_binary (GET_CODE (op1
), mode
,
4964 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
4965 gen_binary (AND
, mode
, XEXP (op1
, 1), op0
)));
4967 /* Similarly, taking advantage of the fact that
4968 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4970 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
4971 return apply_distributive_law
4972 (gen_binary (XOR
, mode
,
4973 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
4974 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 1))));
4976 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
4977 return apply_distributive_law
4978 (gen_binary (XOR
, mode
,
4979 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
4980 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 1))));
4984 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4985 if (GET_CODE (op1
) == CONST_INT
4986 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4987 && (nonzero_bits (op0
, mode
) & ~ INTVAL (op1
)) == 0)
4990 /* Convert (A & B) | A to A. */
4991 if (GET_CODE (op0
) == AND
4992 && (rtx_equal_p (XEXP (op0
, 0), op1
)
4993 || rtx_equal_p (XEXP (op0
, 1), op1
))
4994 && ! side_effects_p (XEXP (op0
, 0))
4995 && ! side_effects_p (XEXP (op0
, 1)))
4998 /* If we have (ior (and A B) C), apply the distributive law and then
4999 the inverse distributive law to see if things simplify. */
5001 if (GET_CODE (op0
) == AND
)
5003 x
= apply_distributive_law
5004 (gen_binary (AND
, mode
,
5005 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5006 gen_binary (IOR
, mode
, XEXP (op0
, 1), op1
)));
5008 if (GET_CODE (x
) != IOR
)
5012 if (GET_CODE (op1
) == AND
)
5014 x
= apply_distributive_law
5015 (gen_binary (AND
, mode
,
5016 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5017 gen_binary (IOR
, mode
, XEXP (op1
, 1), op0
)));
5019 if (GET_CODE (x
) != IOR
)
5023 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5024 mode size to (rotate A CX). */
5026 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5027 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5028 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5029 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5030 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5031 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5032 == GET_MODE_BITSIZE (mode
)))
5033 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5034 (GET_CODE (op0
) == ASHIFT
5035 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5037 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5038 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5039 does not affect any of the bits in OP1, it can really be done
5040 as a PLUS and we can associate. We do this by seeing if OP1
5041 can be safely shifted left C bits. */
5042 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5043 && GET_CODE (XEXP (op0
, 0)) == PLUS
5044 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5045 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5046 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5048 int count
= INTVAL (XEXP (op0
, 1));
5049 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5051 if (mask
>> count
== INTVAL (op1
)
5052 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5054 SUBST (XEXP (XEXP (op0
, 0), 1),
5055 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5062 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5063 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5066 int num_negated
= 0;
5068 if (GET_CODE (op0
) == NOT
)
5069 num_negated
++, op0
= XEXP (op0
, 0);
5070 if (GET_CODE (op1
) == NOT
)
5071 num_negated
++, op1
= XEXP (op1
, 0);
5073 if (num_negated
== 2)
5075 SUBST (XEXP (x
, 0), op0
);
5076 SUBST (XEXP (x
, 1), op1
);
5078 else if (num_negated
== 1)
5079 return gen_unary (NOT
, mode
, mode
, gen_binary (XOR
, mode
, op0
, op1
));
5082 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5083 correspond to a machine insn or result in further simplifications
5084 if B is a constant. */
5086 if (GET_CODE (op0
) == AND
5087 && rtx_equal_p (XEXP (op0
, 1), op1
)
5088 && ! side_effects_p (op1
))
5089 return gen_binary (AND
, mode
,
5090 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)),
5093 else if (GET_CODE (op0
) == AND
5094 && rtx_equal_p (XEXP (op0
, 0), op1
)
5095 && ! side_effects_p (op1
))
5096 return gen_binary (AND
, mode
,
5097 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)),
5100 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5101 comparison if STORE_FLAG_VALUE is 1. */
5102 if (STORE_FLAG_VALUE
== 1
5103 && op1
== const1_rtx
5104 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5105 && reversible_comparison_p (op0
))
5106 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
5107 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
5109 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5110 is (lt foo (const_int 0)), so we can perform the above
5111 simplification if STORE_FLAG_VALUE is 1. */
5113 if (STORE_FLAG_VALUE
== 1
5114 && op1
== const1_rtx
5115 && GET_CODE (op0
) == LSHIFTRT
5116 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5117 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5118 return gen_rtx_combine (GE
, mode
, XEXP (op0
, 0), const0_rtx
);
5120 /* (xor (comparison foo bar) (const_int sign-bit))
5121 when STORE_FLAG_VALUE is the sign bit. */
5122 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5123 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5124 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5125 && op1
== const_true_rtx
5126 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5127 && reversible_comparison_p (op0
))
5128 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
5129 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
5139 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5140 operations" because they can be replaced with two more basic operations.
5141 ZERO_EXTEND is also considered "compound" because it can be replaced with
5142 an AND operation, which is simpler, though only one operation.
5144 The function expand_compound_operation is called with an rtx expression
5145 and will convert it to the appropriate shifts and AND operations,
5146 simplifying at each stage.
5148 The function make_compound_operation is called to convert an expression
5149 consisting of shifts and ANDs into the equivalent compound expression.
5150 It is the inverse of this function, loosely speaking. */
5153 expand_compound_operation (x
)
5161 switch (GET_CODE (x
))
5166 /* We can't necessarily use a const_int for a multiword mode;
5167 it depends on implicitly extending the value.
5168 Since we don't know the right way to extend it,
5169 we can't tell whether the implicit way is right.
5171 Even for a mode that is no wider than a const_int,
5172 we can't win, because we need to sign extend one of its bits through
5173 the rest of it, and we don't know which bit. */
5174 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5177 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5178 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5179 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5180 reloaded. If not for that, MEM's would very rarely be safe.
5182 Reject MODEs bigger than a word, because we might not be able
5183 to reference a two-register group starting with an arbitrary register
5184 (and currently gen_lowpart might crash for a SUBREG). */
5186 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5189 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5190 /* If the inner object has VOIDmode (the only way this can happen
5191 is if it is a ASM_OPERANDS), we can't do anything since we don't
5192 know how much masking to do. */
5201 /* If the operand is a CLOBBER, just return it. */
5202 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5205 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5206 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5207 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5210 len
= INTVAL (XEXP (x
, 1));
5211 pos
= INTVAL (XEXP (x
, 2));
5213 /* If this goes outside the object being extracted, replace the object
5214 with a (use (mem ...)) construct that only combine understands
5215 and is used only for this purpose. */
5216 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5217 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5219 if (BITS_BIG_ENDIAN
)
5220 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5228 /* We can optimize some special cases of ZERO_EXTEND. */
5229 if (GET_CODE (x
) == ZERO_EXTEND
)
5231 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5232 know that the last value didn't have any inappropriate bits
5234 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5235 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5236 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5237 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5238 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5239 return XEXP (XEXP (x
, 0), 0);
5241 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5242 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5243 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5244 && subreg_lowpart_p (XEXP (x
, 0))
5245 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5246 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5247 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5248 return SUBREG_REG (XEXP (x
, 0));
5250 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5251 is a comparison and STORE_FLAG_VALUE permits. This is like
5252 the first case, but it works even when GET_MODE (x) is larger
5253 than HOST_WIDE_INT. */
5254 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5255 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5256 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5257 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5258 <= HOST_BITS_PER_WIDE_INT
)
5259 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5260 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5261 return XEXP (XEXP (x
, 0), 0);
5263 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5264 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5265 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5266 && subreg_lowpart_p (XEXP (x
, 0))
5267 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5268 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5269 <= HOST_BITS_PER_WIDE_INT
)
5270 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5271 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5272 return SUBREG_REG (XEXP (x
, 0));
5274 /* If sign extension is cheaper than zero extension, then use it
5275 if we know that no extraneous bits are set, and that the high
5277 if (flag_expensive_optimizations
5278 && ((GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5279 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (x
))
5280 & ~ (((unsigned HOST_WIDE_INT
)
5281 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5284 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5285 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5286 <= HOST_BITS_PER_WIDE_INT
)
5287 && (((HOST_WIDE_INT
) STORE_FLAG_VALUE
5288 & ~ (((unsigned HOST_WIDE_INT
)
5289 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5293 rtx temp
= gen_rtx_SIGN_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5295 if (rtx_cost (temp
, SET
) < rtx_cost (x
, SET
))
5296 return expand_compound_operation (temp
);
5300 /* If we reach here, we want to return a pair of shifts. The inner
5301 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5302 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5303 logical depending on the value of UNSIGNEDP.
5305 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5306 converted into an AND of a shift.
5308 We must check for the case where the left shift would have a negative
5309 count. This can happen in a case like (x >> 31) & 255 on machines
5310 that can't shift by a constant. On those machines, we would first
5311 combine the shift with the AND to produce a variable-position
5312 extraction. Then the constant of 31 would be substituted in to produce
5313 a such a position. */
5315 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5316 if (modewidth
>= pos
- len
)
5317 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5319 simplify_shift_const (NULL_RTX
, ASHIFT
,
5322 modewidth
- pos
- len
),
5325 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5326 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5327 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5330 ((HOST_WIDE_INT
) 1 << len
) - 1);
5332 /* Any other cases we can't handle. */
5336 /* If we couldn't do this for some reason, return the original
5338 if (GET_CODE (tem
) == CLOBBER
)
5344 /* X is a SET which contains an assignment of one object into
5345 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5346 or certain SUBREGS). If possible, convert it into a series of
5349 We half-heartedly support variable positions, but do not at all
5350 support variable lengths. */
5353 expand_field_assignment (x
)
5357 rtx pos
; /* Always counts from low bit. */
5360 enum machine_mode compute_mode
;
5362 /* Loop until we find something we can't simplify. */
5365 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5366 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5368 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5369 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5370 pos
= GEN_INT (BITS_PER_WORD
* SUBREG_WORD (XEXP (SET_DEST (x
), 0)));
5372 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5373 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5375 inner
= XEXP (SET_DEST (x
), 0);
5376 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5377 pos
= XEXP (SET_DEST (x
), 2);
5379 /* If the position is constant and spans the width of INNER,
5380 surround INNER with a USE to indicate this. */
5381 if (GET_CODE (pos
) == CONST_INT
5382 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5383 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5385 if (BITS_BIG_ENDIAN
)
5387 if (GET_CODE (pos
) == CONST_INT
)
5388 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5390 else if (GET_CODE (pos
) == MINUS
5391 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5392 && (INTVAL (XEXP (pos
, 1))
5393 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5394 /* If position is ADJUST - X, new position is X. */
5395 pos
= XEXP (pos
, 0);
5397 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5398 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5404 /* A SUBREG between two modes that occupy the same numbers of words
5405 can be done by moving the SUBREG to the source. */
5406 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5407 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5408 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5409 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5410 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5412 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5413 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5420 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5421 inner
= SUBREG_REG (inner
);
5423 compute_mode
= GET_MODE (inner
);
5425 /* Don't attempt bitwise arithmetic on non-integral modes. */
5426 if (! INTEGRAL_MODE_P (compute_mode
))
5428 enum machine_mode imode
;
5430 /* Something is probably seriously wrong if this matches. */
5431 if (! FLOAT_MODE_P (compute_mode
))
5434 /* Try to find an integral mode to pun with. */
5435 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5436 if (imode
== BLKmode
)
5439 compute_mode
= imode
;
5440 inner
= gen_lowpart_for_combine (imode
, inner
);
5443 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5444 if (len
< HOST_BITS_PER_WIDE_INT
)
5445 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5449 /* Now compute the equivalent expression. Make a copy of INNER
5450 for the SET_DEST in case it is a MEM into which we will substitute;
5451 we don't want shared RTL in that case. */
5452 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
5453 gen_binary (IOR
, compute_mode
,
5454 gen_binary (AND
, compute_mode
,
5455 gen_unary (NOT
, compute_mode
,
5461 gen_binary (ASHIFT
, compute_mode
,
5462 gen_binary (AND
, compute_mode
,
5463 gen_lowpart_for_combine
5473 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5474 it is an RTX that represents a variable starting position; otherwise,
5475 POS is the (constant) starting bit position (counted from the LSB).
5477 INNER may be a USE. This will occur when we started with a bitfield
5478 that went outside the boundary of the object in memory, which is
5479 allowed on most machines. To isolate this case, we produce a USE
5480 whose mode is wide enough and surround the MEM with it. The only
5481 code that understands the USE is this routine. If it is not removed,
5482 it will cause the resulting insn not to match.
5484 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5487 IN_DEST is non-zero if this is a reference in the destination of a
5488 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5489 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5492 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5493 ZERO_EXTRACT should be built even for bits starting at bit 0.
5495 MODE is the desired mode of the result (if IN_DEST == 0).
5497 The result is an RTX for the extraction or NULL_RTX if the target
5501 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5502 unsignedp
, in_dest
, in_compare
)
5503 enum machine_mode mode
;
5509 int in_dest
, in_compare
;
5511 /* This mode describes the size of the storage area
5512 to fetch the overall value from. Within that, we
5513 ignore the POS lowest bits, etc. */
5514 enum machine_mode is_mode
= GET_MODE (inner
);
5515 enum machine_mode inner_mode
;
5516 enum machine_mode wanted_inner_mode
= byte_mode
;
5517 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5518 enum machine_mode pos_mode
= word_mode
;
5519 enum machine_mode extraction_mode
= word_mode
;
5520 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5523 rtx orig_pos_rtx
= pos_rtx
;
5526 /* Get some information about INNER and get the innermost object. */
5527 if (GET_CODE (inner
) == USE
)
5528 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5529 /* We don't need to adjust the position because we set up the USE
5530 to pretend that it was a full-word object. */
5531 spans_byte
= 1, inner
= XEXP (inner
, 0);
5532 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5534 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5535 consider just the QI as the memory to extract from.
5536 The subreg adds or removes high bits; its mode is
5537 irrelevant to the meaning of this extraction,
5538 since POS and LEN count from the lsb. */
5539 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5540 is_mode
= GET_MODE (SUBREG_REG (inner
));
5541 inner
= SUBREG_REG (inner
);
5544 inner_mode
= GET_MODE (inner
);
5546 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5547 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5549 /* See if this can be done without an extraction. We never can if the
5550 width of the field is not the same as that of some integer mode. For
5551 registers, we can only avoid the extraction if the position is at the
5552 low-order bit and this is either not in the destination or we have the
5553 appropriate STRICT_LOW_PART operation available.
5555 For MEM, we can avoid an extract if the field starts on an appropriate
5556 boundary and we can change the mode of the memory reference. However,
5557 we cannot directly access the MEM if we have a USE and the underlying
5558 MEM is not TMODE. This combination means that MEM was being used in a
5559 context where bits outside its mode were being referenced; that is only
5560 valid in bit-field insns. */
5562 if (tmode
!= BLKmode
5563 && ! (spans_byte
&& inner_mode
!= tmode
)
5564 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5565 && GET_CODE (inner
) != MEM
5567 || (GET_CODE (inner
) == REG
5568 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
5569 != CODE_FOR_nothing
))))
5570 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5572 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5573 : BITS_PER_UNIT
)) == 0
5574 /* We can't do this if we are widening INNER_MODE (it
5575 may not be aligned, for one thing). */
5576 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5577 && (inner_mode
== tmode
5578 || (! mode_dependent_address_p (XEXP (inner
, 0))
5579 && ! MEM_VOLATILE_P (inner
))))))
5581 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5582 field. If the original and current mode are the same, we need not
5583 adjust the offset. Otherwise, we do if bytes big endian.
5585 If INNER is not a MEM, get a piece consisting of just the field
5586 of interest (in this case POS % BITS_PER_WORD must be 0). */
5588 if (GET_CODE (inner
) == MEM
)
5591 /* POS counts from lsb, but make OFFSET count in memory order. */
5592 if (BYTES_BIG_ENDIAN
)
5593 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5595 offset
= pos
/ BITS_PER_UNIT
;
5597 new = gen_rtx_MEM (tmode
, plus_constant (XEXP (inner
, 0), offset
));
5598 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner
);
5599 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner
);
5600 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner
);
5602 else if (GET_CODE (inner
) == REG
)
5604 /* We can't call gen_lowpart_for_combine here since we always want
5605 a SUBREG and it would sometimes return a new hard register. */
5606 if (tmode
!= inner_mode
)
5607 new = gen_rtx_SUBREG (tmode
, inner
,
5609 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
5610 ? (((GET_MODE_SIZE (inner_mode
)
5611 - GET_MODE_SIZE (tmode
))
5613 - pos
/ BITS_PER_WORD
)
5614 : pos
/ BITS_PER_WORD
));
5619 new = force_to_mode (inner
, tmode
,
5620 len
>= HOST_BITS_PER_WIDE_INT
5621 ? GET_MODE_MASK (tmode
)
5622 : ((HOST_WIDE_INT
) 1 << len
) - 1,
5625 /* If this extraction is going into the destination of a SET,
5626 make a STRICT_LOW_PART unless we made a MEM. */
5629 return (GET_CODE (new) == MEM
? new
5630 : (GET_CODE (new) != SUBREG
5631 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
5632 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
5634 /* Otherwise, sign- or zero-extend unless we already are in the
5637 return (mode
== tmode
? new
5638 : gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5642 /* Unless this is a COMPARE or we have a funny memory reference,
5643 don't do anything with zero-extending field extracts starting at
5644 the low-order bit since they are simple AND operations. */
5645 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5646 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5649 /* Unless we are allowed to span bytes, reject this if we would be
5650 spanning bytes or if the position is not a constant and the length
5651 is not 1. In all other cases, we would only be going outside
5652 out object in cases when an original shift would have been
5655 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
5656 || (pos_rtx
!= 0 && len
!= 1)))
5659 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5660 and the mode for the result. */
5664 wanted_inner_reg_mode
5665 = (insn_operand_mode
[(int) CODE_FOR_insv
][0] == VOIDmode
5667 : insn_operand_mode
[(int) CODE_FOR_insv
][0]);
5668 pos_mode
= (insn_operand_mode
[(int) CODE_FOR_insv
][2] == VOIDmode
5669 ? word_mode
: insn_operand_mode
[(int) CODE_FOR_insv
][2]);
5670 extraction_mode
= (insn_operand_mode
[(int) CODE_FOR_insv
][3] == VOIDmode
5672 : insn_operand_mode
[(int) CODE_FOR_insv
][3]);
5677 if (! in_dest
&& unsignedp
)
5679 wanted_inner_reg_mode
5680 = (insn_operand_mode
[(int) CODE_FOR_extzv
][1] == VOIDmode
5682 : insn_operand_mode
[(int) CODE_FOR_extzv
][1]);
5683 pos_mode
= (insn_operand_mode
[(int) CODE_FOR_extzv
][3] == VOIDmode
5684 ? word_mode
: insn_operand_mode
[(int) CODE_FOR_extzv
][3]);
5685 extraction_mode
= (insn_operand_mode
[(int) CODE_FOR_extzv
][0] == VOIDmode
5687 : insn_operand_mode
[(int) CODE_FOR_extzv
][0]);
5692 if (! in_dest
&& ! unsignedp
)
5694 wanted_inner_reg_mode
5695 = (insn_operand_mode
[(int) CODE_FOR_extv
][1] == VOIDmode
5697 : insn_operand_mode
[(int) CODE_FOR_extv
][1]);
5698 pos_mode
= (insn_operand_mode
[(int) CODE_FOR_extv
][3] == VOIDmode
5699 ? word_mode
: insn_operand_mode
[(int) CODE_FOR_extv
][3]);
5700 extraction_mode
= (insn_operand_mode
[(int) CODE_FOR_extv
][0] == VOIDmode
5702 : insn_operand_mode
[(int) CODE_FOR_extv
][0]);
5706 /* Never narrow an object, since that might not be safe. */
5708 if (mode
!= VOIDmode
5709 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
5710 extraction_mode
= mode
;
5712 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
5713 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5714 pos_mode
= GET_MODE (pos_rtx
);
5716 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5717 if we have to change the mode of memory and cannot, the desired mode is
5719 if (GET_CODE (inner
) != MEM
)
5720 wanted_inner_mode
= wanted_inner_reg_mode
;
5721 else if (inner_mode
!= wanted_inner_mode
5722 && (mode_dependent_address_p (XEXP (inner
, 0))
5723 || MEM_VOLATILE_P (inner
)))
5724 wanted_inner_mode
= extraction_mode
;
5728 if (BITS_BIG_ENDIAN
)
5730 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5731 BITS_BIG_ENDIAN style. If position is constant, compute new
5732 position. Otherwise, build subtraction.
5733 Note that POS is relative to the mode of the original argument.
5734 If it's a MEM we need to recompute POS relative to that.
5735 However, if we're extracting from (or inserting into) a register,
5736 we want to recompute POS relative to wanted_inner_mode. */
5737 int width
= (GET_CODE (inner
) == MEM
5738 ? GET_MODE_BITSIZE (is_mode
)
5739 : GET_MODE_BITSIZE (wanted_inner_mode
));
5742 pos
= width
- len
- pos
;
5745 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
5746 GEN_INT (width
- len
), pos_rtx
);
5747 /* POS may be less than 0 now, but we check for that below.
5748 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5751 /* If INNER has a wider mode, make it smaller. If this is a constant
5752 extract, try to adjust the byte to point to the byte containing
5754 if (wanted_inner_mode
!= VOIDmode
5755 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
5756 && ((GET_CODE (inner
) == MEM
5757 && (inner_mode
== wanted_inner_mode
5758 || (! mode_dependent_address_p (XEXP (inner
, 0))
5759 && ! MEM_VOLATILE_P (inner
))))))
5763 /* The computations below will be correct if the machine is big
5764 endian in both bits and bytes or little endian in bits and bytes.
5765 If it is mixed, we must adjust. */
5767 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5768 adjust OFFSET to compensate. */
5769 if (BYTES_BIG_ENDIAN
5771 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
5772 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
5774 /* If this is a constant position, we can move to the desired byte. */
5777 offset
+= pos
/ BITS_PER_UNIT
;
5778 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
5781 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
5783 && is_mode
!= wanted_inner_mode
)
5784 offset
= (GET_MODE_SIZE (is_mode
)
5785 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
5787 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
5789 rtx newmem
= gen_rtx_MEM (wanted_inner_mode
,
5790 plus_constant (XEXP (inner
, 0), offset
));
5791 RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (inner
);
5792 MEM_VOLATILE_P (newmem
) = MEM_VOLATILE_P (inner
);
5793 MEM_IN_STRUCT_P (newmem
) = MEM_IN_STRUCT_P (inner
);
5798 /* If INNER is not memory, we can always get it into the proper mode. If we
5799 are changing its mode, POS must be a constant and smaller than the size
5801 else if (GET_CODE (inner
) != MEM
)
5803 if (GET_MODE (inner
) != wanted_inner_mode
5805 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
5808 inner
= force_to_mode (inner
, wanted_inner_mode
,
5810 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
5811 ? GET_MODE_MASK (wanted_inner_mode
)
5812 : (((HOST_WIDE_INT
) 1 << len
) - 1) << orig_pos
,
5816 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5817 have to zero extend. Otherwise, we can just use a SUBREG. */
5819 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5820 pos_rtx
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
5821 else if (pos_rtx
!= 0
5822 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5823 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
5825 /* Make POS_RTX unless we already have it and it is correct. If we don't
5826 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5828 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
5829 pos_rtx
= orig_pos_rtx
;
5831 else if (pos_rtx
== 0)
5832 pos_rtx
= GEN_INT (pos
);
5834 /* Make the required operation. See if we can use existing rtx. */
5835 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
5836 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
5838 new = gen_lowpart_for_combine (mode
, new);
5843 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5844 with any other operations in X. Return X without that shift if so. */
5847 extract_left_shift (x
, count
)
5851 enum rtx_code code
= GET_CODE (x
);
5852 enum machine_mode mode
= GET_MODE (x
);
5858 /* This is the shift itself. If it is wide enough, we will return
5859 either the value being shifted if the shift count is equal to
5860 COUNT or a shift for the difference. */
5861 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5862 && INTVAL (XEXP (x
, 1)) >= count
)
5863 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
5864 INTVAL (XEXP (x
, 1)) - count
);
5868 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
5869 return gen_unary (code
, mode
, mode
, tem
);
5873 case PLUS
: case IOR
: case XOR
: case AND
:
5874 /* If we can safely shift this constant and we find the inner shift,
5875 make a new operation. */
5876 if (GET_CODE (XEXP (x
,1)) == CONST_INT
5877 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
5878 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
5879 return gen_binary (code
, mode
, tem
,
5880 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
5891 /* Look at the expression rooted at X. Look for expressions
5892 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5893 Form these expressions.
5895 Return the new rtx, usually just X.
5897 Also, for machines like the Vax that don't have logical shift insns,
5898 try to convert logical to arithmetic shift operations in cases where
5899 they are equivalent. This undoes the canonicalizations to logical
5900 shifts done elsewhere.
5902 We try, as much as possible, to re-use rtl expressions to save memory.
5904 IN_CODE says what kind of expression we are processing. Normally, it is
5905 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5906 being kludges), it is MEM. When processing the arguments of a comparison
5907 or a COMPARE against zero, it is COMPARE. */
5910 make_compound_operation (x
, in_code
)
5912 enum rtx_code in_code
;
5914 enum rtx_code code
= GET_CODE (x
);
5915 enum machine_mode mode
= GET_MODE (x
);
5916 int mode_width
= GET_MODE_BITSIZE (mode
);
5918 enum rtx_code next_code
;
5924 /* Select the code to be used in recursive calls. Once we are inside an
5925 address, we stay there. If we have a comparison, set to COMPARE,
5926 but once inside, go back to our default of SET. */
5928 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
5929 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
5930 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
5931 : in_code
== COMPARE
? SET
: in_code
);
5933 /* Process depending on the code of this operation. If NEW is set
5934 non-zero, it will be returned. */
5939 /* Convert shifts by constants into multiplications if inside
5941 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
5942 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
5943 && INTVAL (XEXP (x
, 1)) >= 0)
5945 new = make_compound_operation (XEXP (x
, 0), next_code
);
5946 new = gen_rtx_combine (MULT
, mode
, new,
5947 GEN_INT ((HOST_WIDE_INT
) 1
5948 << INTVAL (XEXP (x
, 1))));
5953 /* If the second operand is not a constant, we can't do anything
5955 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5958 /* If the constant is a power of two minus one and the first operand
5959 is a logical right shift, make an extraction. */
5960 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5961 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5963 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
5964 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
5965 0, in_code
== COMPARE
);
5968 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5969 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
5970 && subreg_lowpart_p (XEXP (x
, 0))
5971 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
5972 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5974 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
5976 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
5977 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
5978 0, in_code
== COMPARE
);
5980 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5981 else if ((GET_CODE (XEXP (x
, 0)) == XOR
5982 || GET_CODE (XEXP (x
, 0)) == IOR
)
5983 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
5984 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
5985 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
5987 /* Apply the distributive law, and then try to make extractions. */
5988 new = gen_rtx_combine (GET_CODE (XEXP (x
, 0)), mode
,
5989 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
5991 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
5993 new = make_compound_operation (new, in_code
);
5996 /* If we are have (and (rotate X C) M) and C is larger than the number
5997 of bits in M, this is an extraction. */
5999 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6000 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6001 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6002 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6004 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6005 new = make_extraction (mode
, new,
6006 (GET_MODE_BITSIZE (mode
)
6007 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6008 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6011 /* On machines without logical shifts, if the operand of the AND is
6012 a logical shift and our mask turns off all the propagated sign
6013 bits, we can replace the logical shift with an arithmetic shift. */
6014 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6015 && (lshr_optab
->handlers
[(int) mode
].insn_code
6016 == CODE_FOR_nothing
)
6017 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6018 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6019 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6020 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6021 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6023 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6025 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6026 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6028 gen_rtx_combine (ASHIFTRT
, mode
,
6029 make_compound_operation (XEXP (XEXP (x
, 0), 0),
6031 XEXP (XEXP (x
, 0), 1)));
6034 /* If the constant is one less than a power of two, this might be
6035 representable by an extraction even if no shift is present.
6036 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6037 we are in a COMPARE. */
6038 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6039 new = make_extraction (mode
,
6040 make_compound_operation (XEXP (x
, 0),
6042 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6044 /* If we are in a comparison and this is an AND with a power of two,
6045 convert this into the appropriate bit extract. */
6046 else if (in_code
== COMPARE
6047 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6048 new = make_extraction (mode
,
6049 make_compound_operation (XEXP (x
, 0),
6051 i
, NULL_RTX
, 1, 1, 0, 1);
6056 /* If the sign bit is known to be zero, replace this with an
6057 arithmetic shift. */
6058 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6059 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6060 && mode_width
<= HOST_BITS_PER_WIDE_INT
6061 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6063 new = gen_rtx_combine (ASHIFTRT
, mode
,
6064 make_compound_operation (XEXP (x
, 0),
6070 /* ... fall through ... */
6076 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6077 this is a SIGN_EXTRACT. */
6078 if (GET_CODE (rhs
) == CONST_INT
6079 && GET_CODE (lhs
) == ASHIFT
6080 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6081 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6083 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6084 new = make_extraction (mode
, new,
6085 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6086 NULL_RTX
, mode_width
- INTVAL (rhs
),
6087 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6090 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6091 If so, try to merge the shifts into a SIGN_EXTEND. We could
6092 also do this for some cases of SIGN_EXTRACT, but it doesn't
6093 seem worth the effort; the case checked for occurs on Alpha. */
6095 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6096 && ! (GET_CODE (lhs
) == SUBREG
6097 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6098 && GET_CODE (rhs
) == CONST_INT
6099 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6100 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6101 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6102 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6103 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6108 /* Call ourselves recursively on the inner expression. If we are
6109 narrowing the object and it has a different RTL code from
6110 what it originally did, do this SUBREG as a force_to_mode. */
6112 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6113 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6114 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6115 && subreg_lowpart_p (x
))
6117 rtx newer
= force_to_mode (tem
, mode
,
6118 GET_MODE_MASK (mode
), NULL_RTX
, 0);
6120 /* If we have something other than a SUBREG, we might have
6121 done an expansion, so rerun outselves. */
6122 if (GET_CODE (newer
) != SUBREG
)
6123 newer
= make_compound_operation (newer
, in_code
);
6128 /* If this is a paradoxical subreg, and the new code is a sign or
6129 zero extension, omit the subreg and widen the extension. If it
6130 is a regular subreg, we can still get rid of the subreg by not
6131 widening so much, or in fact removing the extension entirely. */
6132 if ((GET_CODE (tem
) == SIGN_EXTEND
6133 || GET_CODE (tem
) == ZERO_EXTEND
)
6134 && subreg_lowpart_p (x
))
6136 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6137 || (GET_MODE_SIZE (mode
) >
6138 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6139 tem
= gen_rtx_combine (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6141 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6152 x
= gen_lowpart_for_combine (mode
, new);
6153 code
= GET_CODE (x
);
6156 /* Now recursively process each operand of this operation. */
6157 fmt
= GET_RTX_FORMAT (code
);
6158 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6161 new = make_compound_operation (XEXP (x
, i
), next_code
);
6162 SUBST (XEXP (x
, i
), new);
6168 /* Given M see if it is a value that would select a field of bits
6169 within an item, but not the entire word. Return -1 if not.
6170 Otherwise, return the starting position of the field, where 0 is the
6173 *PLEN is set to the length of the field. */
6176 get_pos_from_mask (m
, plen
)
6177 unsigned HOST_WIDE_INT m
;
6180 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6181 int pos
= exact_log2 (m
& - m
);
6186 /* Now shift off the low-order zero bits and see if we have a power of
6188 *plen
= exact_log2 ((m
>> pos
) + 1);
6196 /* See if X can be simplified knowing that we will only refer to it in
6197 MODE and will only refer to those bits that are nonzero in MASK.
6198 If other bits are being computed or if masking operations are done
6199 that select a superset of the bits in MASK, they can sometimes be
6202 Return a possibly simplified expression, but always convert X to
6203 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6205 Also, if REG is non-zero and X is a register equal in value to REG,
6208 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6209 are all off in X. This is used when X will be complemented, by either
6210 NOT, NEG, or XOR. */
6213 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6215 enum machine_mode mode
;
6216 unsigned HOST_WIDE_INT mask
;
6220 enum rtx_code code
= GET_CODE (x
);
6221 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6222 enum machine_mode op_mode
;
6223 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6226 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6227 code below will do the wrong thing since the mode of such an
6228 expression is VOIDmode.
6230 Also do nothing if X is a CLOBBER; this can happen if X was
6231 the return value from a call to gen_lowpart_for_combine. */
6232 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6235 /* We want to perform the operation is its present mode unless we know
6236 that the operation is valid in MODE, in which case we do the operation
6238 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6239 && code_to_optab
[(int) code
] != 0
6240 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6241 != CODE_FOR_nothing
))
6242 ? mode
: GET_MODE (x
));
6244 /* It is not valid to do a right-shift in a narrower mode
6245 than the one it came in with. */
6246 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6247 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6248 op_mode
= GET_MODE (x
);
6250 /* Truncate MASK to fit OP_MODE. */
6252 mask
&= GET_MODE_MASK (op_mode
);
6254 /* When we have an arithmetic operation, or a shift whose count we
6255 do not know, we need to assume that all bit the up to the highest-order
6256 bit in MASK will be needed. This is how we form such a mask. */
6258 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6259 ? GET_MODE_MASK (op_mode
)
6260 : ((HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1)) - 1);
6262 fuller_mask
= ~ (HOST_WIDE_INT
) 0;
6264 /* Determine what bits of X are guaranteed to be (non)zero. */
6265 nonzero
= nonzero_bits (x
, mode
);
6267 /* If none of the bits in X are needed, return a zero. */
6268 if (! just_select
&& (nonzero
& mask
) == 0)
6271 /* If X is a CONST_INT, return a new one. Do this here since the
6272 test below will fail. */
6273 if (GET_CODE (x
) == CONST_INT
)
6275 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6276 int width
= GET_MODE_BITSIZE (mode
);
6278 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6279 number, sign extend it. */
6280 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6281 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6282 cval
|= (HOST_WIDE_INT
) -1 << width
;
6284 return GEN_INT (cval
);
6287 /* If X is narrower than MODE and we want all the bits in X's mode, just
6288 get X in the proper mode. */
6289 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6290 && (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
) == 0)
6291 return gen_lowpart_for_combine (mode
, x
);
6293 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6294 MASK are already known to be zero in X, we need not do anything. */
6295 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~ mask
& nonzero
) == 0)
6301 /* If X is a (clobber (const_int)), return it since we know we are
6302 generating something that won't match. */
6306 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6307 spanned the boundary of the MEM. If we are now masking so it is
6308 within that boundary, we don't need the USE any more. */
6309 if (! BITS_BIG_ENDIAN
6310 && (mask
& ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6311 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6318 x
= expand_compound_operation (x
);
6319 if (GET_CODE (x
) != code
)
6320 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6324 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6325 || rtx_equal_p (reg
, get_last_value (x
))))
6330 if (subreg_lowpart_p (x
)
6331 /* We can ignore the effect of this SUBREG if it narrows the mode or
6332 if the constant masks to zero all the bits the mode doesn't
6334 && ((GET_MODE_SIZE (GET_MODE (x
))
6335 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6337 & GET_MODE_MASK (GET_MODE (x
))
6338 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6339 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6343 /* If this is an AND with a constant, convert it into an AND
6344 whose constant is the AND of that constant with MASK. If it
6345 remains an AND of MASK, delete it since it is redundant. */
6347 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6349 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6350 mask
& INTVAL (XEXP (x
, 1)));
6352 /* If X is still an AND, see if it is an AND with a mask that
6353 is just some low-order bits. If so, and it is MASK, we don't
6356 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6357 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6360 /* If it remains an AND, try making another AND with the bits
6361 in the mode mask that aren't in MASK turned on. If the
6362 constant in the AND is wide enough, this might make a
6363 cheaper constant. */
6365 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6366 && GET_MODE_MASK (GET_MODE (x
)) != mask
6367 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6369 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6370 | (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
));
6371 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6374 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6375 number, sign extend it. */
6376 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6377 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6378 cval
|= (HOST_WIDE_INT
) -1 << width
;
6380 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6381 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6391 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6392 low-order bits (as in an alignment operation) and FOO is already
6393 aligned to that boundary, mask C1 to that boundary as well.
6394 This may eliminate that PLUS and, later, the AND. */
6397 int width
= GET_MODE_BITSIZE (mode
);
6398 unsigned HOST_WIDE_INT smask
= mask
;
6400 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6401 number, sign extend it. */
6403 if (width
< HOST_BITS_PER_WIDE_INT
6404 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6405 smask
|= (HOST_WIDE_INT
) -1 << width
;
6407 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6408 && exact_log2 (- smask
) >= 0)
6412 && (XEXP (x
, 0) == stack_pointer_rtx
6413 || XEXP (x
, 0) == frame_pointer_rtx
))
6415 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6416 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6418 sp_mask
&= ~ (sp_alignment
- 1);
6419 if ((sp_mask
& ~ mask
) == 0
6420 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~ mask
) != 0)
6421 return force_to_mode (plus_constant (XEXP (x
, 0),
6422 ((INTVAL (XEXP (x
, 1)) -
6425 mode
, mask
, reg
, next_select
);
6428 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~ mask
) == 0
6429 && (INTVAL (XEXP (x
, 1)) & ~ mask
) != 0)
6430 return force_to_mode (plus_constant (XEXP (x
, 0),
6431 INTVAL (XEXP (x
, 1)) & mask
),
6432 mode
, mask
, reg
, next_select
);
6436 /* ... fall through ... */
6440 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6441 most significant bit in MASK since carries from those bits will
6442 affect the bits we are interested in. */
6448 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6449 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6450 operation which may be a bitfield extraction. Ensure that the
6451 constant we form is not wider than the mode of X. */
6453 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6454 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6455 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6456 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6457 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6458 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6459 + floor_log2 (INTVAL (XEXP (x
, 1))))
6460 < GET_MODE_BITSIZE (GET_MODE (x
)))
6461 && (INTVAL (XEXP (x
, 1))
6462 & ~ nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6464 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6465 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6466 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6467 XEXP (XEXP (x
, 0), 0), temp
);
6468 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6469 XEXP (XEXP (x
, 0), 1));
6470 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6474 /* For most binary operations, just propagate into the operation and
6475 change the mode if we have an operation of that mode. */
6477 op0
= gen_lowpart_for_combine (op_mode
,
6478 force_to_mode (XEXP (x
, 0), mode
, mask
,
6480 op1
= gen_lowpart_for_combine (op_mode
,
6481 force_to_mode (XEXP (x
, 1), mode
, mask
,
6484 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6485 MASK since OP1 might have been sign-extended but we never want
6486 to turn on extra bits, since combine might have previously relied
6487 on them being off. */
6488 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6489 && (INTVAL (op1
) & mask
) != 0)
6490 op1
= GEN_INT (INTVAL (op1
) & mask
);
6492 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6493 x
= gen_binary (code
, op_mode
, op0
, op1
);
6497 /* For left shifts, do the same, but just for the first operand.
6498 However, we cannot do anything with shifts where we cannot
6499 guarantee that the counts are smaller than the size of the mode
6500 because such a count will have a different meaning in a
6503 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6504 && INTVAL (XEXP (x
, 1)) >= 0
6505 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6506 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6507 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6508 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6511 /* If the shift count is a constant and we can do arithmetic in
6512 the mode of the shift, refine which bits we need. Otherwise, use the
6513 conservative form of the mask. */
6514 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6515 && INTVAL (XEXP (x
, 1)) >= 0
6516 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6517 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6518 mask
>>= INTVAL (XEXP (x
, 1));
6522 op0
= gen_lowpart_for_combine (op_mode
,
6523 force_to_mode (XEXP (x
, 0), op_mode
,
6524 mask
, reg
, next_select
));
6526 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6527 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6531 /* Here we can only do something if the shift count is a constant,
6532 this shift constant is valid for the host, and we can do arithmetic
6535 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6536 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6537 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6539 rtx inner
= XEXP (x
, 0);
6541 /* Select the mask of the bits we need for the shift operand. */
6542 mask
<<= INTVAL (XEXP (x
, 1));
6544 /* We can only change the mode of the shift if we can do arithmetic
6545 in the mode of the shift and MASK is no wider than the width of
6547 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
6548 || (mask
& ~ GET_MODE_MASK (op_mode
)) != 0)
6549 op_mode
= GET_MODE (x
);
6551 inner
= force_to_mode (inner
, op_mode
, mask
, reg
, next_select
);
6553 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
6554 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
6557 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6558 shift and AND produces only copies of the sign bit (C2 is one less
6559 than a power of two), we can do this with just a shift. */
6561 if (GET_CODE (x
) == LSHIFTRT
6562 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6563 && ((INTVAL (XEXP (x
, 1))
6564 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
6565 >= GET_MODE_BITSIZE (GET_MODE (x
)))
6566 && exact_log2 (mask
+ 1) >= 0
6567 && (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6568 >= exact_log2 (mask
+ 1)))
6569 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6570 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
6571 - exact_log2 (mask
+ 1)));
6575 /* If we are just looking for the sign bit, we don't need this shift at
6576 all, even if it has a variable count. */
6577 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6578 && (mask
== ((unsigned HOST_WIDE_INT
) 1
6579 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6580 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6582 /* If this is a shift by a constant, get a mask that contains those bits
6583 that are not copies of the sign bit. We then have two cases: If
6584 MASK only includes those bits, this can be a logical shift, which may
6585 allow simplifications. If MASK is a single-bit field not within
6586 those bits, we are requesting a copy of the sign bit and hence can
6587 shift the sign bit to the appropriate location. */
6589 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
6590 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
6594 /* If the considered data is wider then HOST_WIDE_INT, we can't
6595 represent a mask for all its bits in a single scalar.
6596 But we only care about the lower bits, so calculate these. */
6598 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
6600 nonzero
= ~ (HOST_WIDE_INT
) 0;
6602 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6603 is the number of bits a full-width mask would have set.
6604 We need only shift if these are fewer than nonzero can
6605 hold. If not, we must keep all bits set in nonzero. */
6607 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
6608 < HOST_BITS_PER_WIDE_INT
)
6609 nonzero
>>= INTVAL (XEXP (x
, 1))
6610 + HOST_BITS_PER_WIDE_INT
6611 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
6615 nonzero
= GET_MODE_MASK (GET_MODE (x
));
6616 nonzero
>>= INTVAL (XEXP (x
, 1));
6619 if ((mask
& ~ nonzero
) == 0
6620 || (i
= exact_log2 (mask
)) >= 0)
6622 x
= simplify_shift_const
6623 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6624 i
< 0 ? INTVAL (XEXP (x
, 1))
6625 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
6627 if (GET_CODE (x
) != ASHIFTRT
)
6628 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6632 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6633 even if the shift count isn't a constant. */
6635 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
6637 /* If this is a sign-extension operation that just affects bits
6638 we don't care about, remove it. Be sure the call above returned
6639 something that is still a shift. */
6641 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
6642 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6643 && INTVAL (XEXP (x
, 1)) >= 0
6644 && (INTVAL (XEXP (x
, 1))
6645 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
6646 && GET_CODE (XEXP (x
, 0)) == ASHIFT
6647 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6648 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
6649 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
6656 /* If the shift count is constant and we can do computations
6657 in the mode of X, compute where the bits we care about are.
6658 Otherwise, we can't do anything. Don't change the mode of
6659 the shift or propagate MODE into the shift, though. */
6660 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6661 && INTVAL (XEXP (x
, 1)) >= 0)
6663 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
6664 GET_MODE (x
), GEN_INT (mask
),
6666 if (temp
&& GET_CODE(temp
) == CONST_INT
)
6668 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
6669 INTVAL (temp
), reg
, next_select
));
6674 /* If we just want the low-order bit, the NEG isn't needed since it
6675 won't change the low-order bit. */
6677 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
6679 /* We need any bits less significant than the most significant bit in
6680 MASK since carries from those bits will affect the bits we are
6686 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6687 same as the XOR case above. Ensure that the constant we form is not
6688 wider than the mode of X. */
6690 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6691 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6692 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6693 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
6694 < GET_MODE_BITSIZE (GET_MODE (x
)))
6695 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
6697 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
6698 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
6699 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
6701 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6704 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6705 use the full mask inside the NOT. */
6709 op0
= gen_lowpart_for_combine (op_mode
,
6710 force_to_mode (XEXP (x
, 0), mode
, mask
,
6712 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6713 x
= gen_unary (code
, op_mode
, op_mode
, op0
);
6717 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6718 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6719 which is equal to STORE_FLAG_VALUE. */
6720 if ((mask
& ~ STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
6721 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
6722 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
6723 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6728 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6729 written in a narrower mode. We play it safe and do not do so. */
6732 gen_lowpart_for_combine (GET_MODE (x
),
6733 force_to_mode (XEXP (x
, 1), mode
,
6734 mask
, reg
, next_select
)));
6736 gen_lowpart_for_combine (GET_MODE (x
),
6737 force_to_mode (XEXP (x
, 2), mode
,
6738 mask
, reg
,next_select
)));
6745 /* Ensure we return a value of the proper mode. */
6746 return gen_lowpart_for_combine (mode
, x
);
6749 /* Return nonzero if X is an expression that has one of two values depending on
6750 whether some other value is zero or nonzero. In that case, we return the
6751 value that is being tested, *PTRUE is set to the value if the rtx being
6752 returned has a nonzero value, and *PFALSE is set to the other alternative.
6754 If we return zero, we set *PTRUE and *PFALSE to X. */
6757 if_then_else_cond (x
, ptrue
, pfalse
)
6759 rtx
*ptrue
, *pfalse
;
6761 enum machine_mode mode
= GET_MODE (x
);
6762 enum rtx_code code
= GET_CODE (x
);
6763 int size
= GET_MODE_BITSIZE (mode
);
6764 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
6765 unsigned HOST_WIDE_INT nz
;
6767 /* If this is a unary operation whose operand has one of two values, apply
6768 our opcode to compute those values. */
6769 if (GET_RTX_CLASS (code
) == '1'
6770 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
6772 *ptrue
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), true0
);
6773 *pfalse
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), false0
);
6777 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6778 make can't possibly match and would suppress other optimizations. */
6779 else if (code
== COMPARE
)
6782 /* If this is a binary operation, see if either side has only one of two
6783 values. If either one does or if both do and they are conditional on
6784 the same value, compute the new true and false values. */
6785 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
6786 || GET_RTX_CLASS (code
) == '<')
6788 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
6789 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
6791 if ((cond0
!= 0 || cond1
!= 0)
6792 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
6794 /* If if_then_else_cond returned zero, then true/false are the
6795 same rtl. We must copy one of them to prevent invalid rtl
6798 true0
= copy_rtx (true0
);
6799 else if (cond1
== 0)
6800 true1
= copy_rtx (true1
);
6802 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
6803 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
6804 return cond0
? cond0
: cond1
;
6807 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6808 operands is zero when the other is non-zero, and vice-versa,
6809 and STORE_FLAG_VALUE is 1 or -1. */
6811 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6812 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
6814 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
6816 rtx op0
= XEXP (XEXP (x
, 0), 1);
6817 rtx op1
= XEXP (XEXP (x
, 1), 1);
6819 cond0
= XEXP (XEXP (x
, 0), 0);
6820 cond1
= XEXP (XEXP (x
, 1), 0);
6822 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
6823 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
6824 && reversible_comparison_p (cond1
)
6825 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
6826 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
6827 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
6828 || ((swap_condition (GET_CODE (cond0
))
6829 == reverse_condition (GET_CODE (cond1
)))
6830 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
6831 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
6832 && ! side_effects_p (x
))
6834 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
6835 *pfalse
= gen_binary (MULT
, mode
,
6837 ? gen_unary (NEG
, mode
, mode
, op1
) : op1
),
6843 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6845 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6846 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
6847 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
6849 cond0
= XEXP (XEXP (x
, 0), 0);
6850 cond1
= XEXP (XEXP (x
, 1), 0);
6852 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
6853 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
6854 && reversible_comparison_p (cond1
)
6855 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
6856 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
6857 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
6858 || ((swap_condition (GET_CODE (cond0
))
6859 == reverse_condition (GET_CODE (cond1
)))
6860 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
6861 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
6862 && ! side_effects_p (x
))
6864 *ptrue
= *pfalse
= const0_rtx
;
6870 else if (code
== IF_THEN_ELSE
)
6872 /* If we have IF_THEN_ELSE already, extract the condition and
6873 canonicalize it if it is NE or EQ. */
6874 cond0
= XEXP (x
, 0);
6875 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
6876 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
6877 return XEXP (cond0
, 0);
6878 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
6880 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
6881 return XEXP (cond0
, 0);
6887 /* If X is a normal SUBREG with both inner and outer modes integral,
6888 we can narrow both the true and false values of the inner expression,
6889 if there is a condition. */
6890 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
6891 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
6892 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
6893 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
6896 *ptrue
= force_to_mode (true0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
6898 = force_to_mode (false0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
6903 /* If X is a constant, this isn't special and will cause confusions
6904 if we treat it as such. Likewise if it is equivalent to a constant. */
6905 else if (CONSTANT_P (x
)
6906 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
6909 /* If X is known to be either 0 or -1, those are the true and
6910 false values when testing X. */
6911 else if (num_sign_bit_copies (x
, mode
) == size
)
6913 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
6917 /* Likewise for 0 or a single bit. */
6918 else if (exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
6920 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
6924 /* Otherwise fail; show no condition with true and false values the same. */
6925 *ptrue
= *pfalse
= x
;
6929 /* Return the value of expression X given the fact that condition COND
6930 is known to be true when applied to REG as its first operand and VAL
6931 as its second. X is known to not be shared and so can be modified in
6934 We only handle the simplest cases, and specifically those cases that
6935 arise with IF_THEN_ELSE expressions. */
6938 known_cond (x
, cond
, reg
, val
)
6943 enum rtx_code code
= GET_CODE (x
);
6948 if (side_effects_p (x
))
6951 if (cond
== EQ
&& rtx_equal_p (x
, reg
))
6954 /* If X is (abs REG) and we know something about REG's relationship
6955 with zero, we may be able to simplify this. */
6957 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
6960 case GE
: case GT
: case EQ
:
6963 return gen_unary (NEG
, GET_MODE (XEXP (x
, 0)), GET_MODE (XEXP (x
, 0)),
6969 /* The only other cases we handle are MIN, MAX, and comparisons if the
6970 operands are the same as REG and VAL. */
6972 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
6974 if (rtx_equal_p (XEXP (x
, 0), val
))
6975 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
6977 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
6979 if (GET_RTX_CLASS (code
) == '<')
6980 return (comparison_dominates_p (cond
, code
) ? const_true_rtx
6981 : (comparison_dominates_p (cond
,
6982 reverse_condition (code
))
6985 else if (code
== SMAX
|| code
== SMIN
6986 || code
== UMIN
|| code
== UMAX
)
6988 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
6990 if (code
== SMAX
|| code
== UMAX
)
6991 cond
= reverse_condition (cond
);
6996 return unsignedp
? x
: XEXP (x
, 1);
6998 return unsignedp
? x
: XEXP (x
, 0);
7000 return unsignedp
? XEXP (x
, 1) : x
;
7002 return unsignedp
? XEXP (x
, 0) : x
;
7010 fmt
= GET_RTX_FORMAT (code
);
7011 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7014 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7015 else if (fmt
[i
] == 'E')
7016 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7017 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7024 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7025 assignment as a field assignment. */
7028 rtx_equal_for_field_assignment_p (x
, y
)
7032 if (x
== y
|| rtx_equal_p (x
, y
))
7035 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7038 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7039 Note that all SUBREGs of MEM are paradoxical; otherwise they
7040 would have been rewritten. */
7041 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7042 && GET_CODE (SUBREG_REG (y
)) == MEM
7043 && rtx_equal_p (SUBREG_REG (y
),
7044 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7047 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7048 && GET_CODE (SUBREG_REG (x
)) == MEM
7049 && rtx_equal_p (SUBREG_REG (x
),
7050 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7053 /* We used to see if get_last_value of X and Y were the same but that's
7054 not correct. In one direction, we'll cause the assignment to have
7055 the wrong destination and in the case, we'll import a register into this
7056 insn that might have already have been dead. So fail if none of the
7057 above cases are true. */
7061 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7062 Return that assignment if so.
7064 We only handle the most common cases. */
7067 make_field_assignment (x
)
7070 rtx dest
= SET_DEST (x
);
7071 rtx src
= SET_SRC (x
);
7077 enum machine_mode mode
;
7079 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7080 a clear of a one-bit field. We will have changed it to
7081 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7084 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7085 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7086 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7087 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7089 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7092 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7096 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7097 && subreg_lowpart_p (XEXP (src
, 0))
7098 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7099 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7100 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7101 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7102 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7104 assign
= make_extraction (VOIDmode
, dest
, 0,
7105 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7108 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7112 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7114 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7115 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7116 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7118 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7121 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7125 /* The other case we handle is assignments into a constant-position
7126 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7127 a mask that has all one bits except for a group of zero bits and
7128 OTHER is known to have zeros where C1 has ones, this is such an
7129 assignment. Compute the position and length from C1. Shift OTHER
7130 to the appropriate position, force it to the required mode, and
7131 make the extraction. Check for the AND in both operands. */
7133 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7136 rhs
= expand_compound_operation (XEXP (src
, 0));
7137 lhs
= expand_compound_operation (XEXP (src
, 1));
7139 if (GET_CODE (rhs
) == AND
7140 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7141 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7142 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7143 else if (GET_CODE (lhs
) == AND
7144 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7145 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7146 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7150 pos
= get_pos_from_mask ((~ c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7151 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7152 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7153 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7156 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7160 /* The mode to use for the source is the mode of the assignment, or of
7161 what is inside a possible STRICT_LOW_PART. */
7162 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7163 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7165 /* Shift OTHER right POS places and make it the source, restricting it
7166 to the proper length and mode. */
7168 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7169 GET_MODE (src
), other
, pos
),
7171 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7172 ? GET_MODE_MASK (mode
)
7173 : ((HOST_WIDE_INT
) 1 << len
) - 1,
7176 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
7179 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7183 apply_distributive_law (x
)
7186 enum rtx_code code
= GET_CODE (x
);
7187 rtx lhs
, rhs
, other
;
7189 enum rtx_code inner_code
;
7191 /* Distributivity is not true for floating point.
7192 It can change the value. So don't do it.
7193 -- rms and moshier@world.std.com. */
7194 if (FLOAT_MODE_P (GET_MODE (x
)))
7197 /* The outer operation can only be one of the following: */
7198 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7199 && code
!= PLUS
&& code
!= MINUS
)
7202 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7204 /* If either operand is a primitive we can't do anything, so get out
7206 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7207 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7210 lhs
= expand_compound_operation (lhs
);
7211 rhs
= expand_compound_operation (rhs
);
7212 inner_code
= GET_CODE (lhs
);
7213 if (inner_code
!= GET_CODE (rhs
))
7216 /* See if the inner and outer operations distribute. */
7223 /* These all distribute except over PLUS. */
7224 if (code
== PLUS
|| code
== MINUS
)
7229 if (code
!= PLUS
&& code
!= MINUS
)
7234 /* This is also a multiply, so it distributes over everything. */
7238 /* Non-paradoxical SUBREGs distributes over all operations, provided
7239 the inner modes and word numbers are the same, this is an extraction
7240 of a low-order part, we don't convert an fp operation to int or
7241 vice versa, and we would not be converting a single-word
7242 operation into a multi-word operation. The latter test is not
7243 required, but it prevents generating unneeded multi-word operations.
7244 Some of the previous tests are redundant given the latter test, but
7245 are retained because they are required for correctness.
7247 We produce the result slightly differently in this case. */
7249 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7250 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
7251 || ! subreg_lowpart_p (lhs
)
7252 || (GET_MODE_CLASS (GET_MODE (lhs
))
7253 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7254 || (GET_MODE_SIZE (GET_MODE (lhs
))
7255 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7256 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7259 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7260 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7261 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7267 /* Set LHS and RHS to the inner operands (A and B in the example
7268 above) and set OTHER to the common operand (C in the example).
7269 These is only one way to do this unless the inner operation is
7271 if (GET_RTX_CLASS (inner_code
) == 'c'
7272 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7273 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7274 else if (GET_RTX_CLASS (inner_code
) == 'c'
7275 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7276 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7277 else if (GET_RTX_CLASS (inner_code
) == 'c'
7278 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7279 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7280 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7281 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7285 /* Form the new inner operation, seeing if it simplifies first. */
7286 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7288 /* There is one exception to the general way of distributing:
7289 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7290 if (code
== XOR
&& inner_code
== IOR
)
7293 other
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), other
);
7296 /* We may be able to continuing distributing the result, so call
7297 ourselves recursively on the inner operation before forming the
7298 outer operation, which we return. */
7299 return gen_binary (inner_code
, GET_MODE (x
),
7300 apply_distributive_law (tem
), other
);
7303 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7306 Return an equivalent form, if different from X. Otherwise, return X. If
7307 X is zero, we are to always construct the equivalent form. */
7310 simplify_and_const_int (x
, mode
, varop
, constop
)
7312 enum machine_mode mode
;
7314 unsigned HOST_WIDE_INT constop
;
7316 unsigned HOST_WIDE_INT nonzero
;
7317 int width
= GET_MODE_BITSIZE (mode
);
7320 /* Simplify VAROP knowing that we will be only looking at some of the
7322 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7324 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7325 CONST_INT, we are done. */
7326 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7329 /* See what bits may be nonzero in VAROP. Unlike the general case of
7330 a call to nonzero_bits, here we don't care about bits outside
7333 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7335 /* If this would be an entire word for the target, but is not for
7336 the host, then sign-extend on the host so that the number will look
7337 the same way on the host that it would on the target.
7339 For example, when building a 64 bit alpha hosted 32 bit sparc
7340 targeted compiler, then we want the 32 bit unsigned value -1 to be
7341 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7342 The later confuses the sparc backend. */
7344 if (BITS_PER_WORD
< HOST_BITS_PER_WIDE_INT
&& BITS_PER_WORD
== width
7345 && (nonzero
& ((HOST_WIDE_INT
) 1 << (width
- 1))))
7346 nonzero
|= ((HOST_WIDE_INT
) (-1) << width
);
7348 /* Turn off all bits in the constant that are known to already be zero.
7349 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7350 which is tested below. */
7354 /* If we don't have any bits left, return zero. */
7358 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7359 a power of two, we can replace this with a ASHIFT. */
7360 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7361 && (i
= exact_log2 (constop
)) >= 0)
7362 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7364 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7365 or XOR, then try to apply the distributive law. This may eliminate
7366 operations if either branch can be simplified because of the AND.
7367 It may also make some cases more complex, but those cases probably
7368 won't match a pattern either with or without this. */
7370 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7372 gen_lowpart_for_combine
7374 apply_distributive_law
7375 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7376 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7377 XEXP (varop
, 0), constop
),
7378 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7379 XEXP (varop
, 1), constop
))));
7381 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7382 if we already had one (just check for the simplest cases). */
7383 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7384 && GET_MODE (XEXP (x
, 0)) == mode
7385 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7386 varop
= XEXP (x
, 0);
7388 varop
= gen_lowpart_for_combine (mode
, varop
);
7390 /* If we can't make the SUBREG, try to return what we were given. */
7391 if (GET_CODE (varop
) == CLOBBER
)
7392 return x
? x
: varop
;
7394 /* If we are only masking insignificant bits, return VAROP. */
7395 if (constop
== nonzero
)
7398 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7399 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7400 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7404 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7405 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7406 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7408 SUBST (XEXP (x
, 0), varop
);
7414 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7415 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7416 is less useful. We can't allow both, because that results in exponential
7417 run time recursion. There is a nullstone testcase that triggered
7418 this. This macro avoids accidental uses of num_sign_bit_copies. */
7419 #define num_sign_bit_copies()
7421 /* Given an expression, X, compute which bits in X can be non-zero.
7422 We don't care about bits outside of those defined in MODE.
7424 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7425 a shift, AND, or zero_extract, we can do better. */
7427 static unsigned HOST_WIDE_INT
7428 nonzero_bits (x
, mode
)
7430 enum machine_mode mode
;
7432 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7433 unsigned HOST_WIDE_INT inner_nz
;
7435 int mode_width
= GET_MODE_BITSIZE (mode
);
7438 /* For floating-point values, assume all bits are needed. */
7439 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7442 /* If X is wider than MODE, use its mode instead. */
7443 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7445 mode
= GET_MODE (x
);
7446 nonzero
= GET_MODE_MASK (mode
);
7447 mode_width
= GET_MODE_BITSIZE (mode
);
7450 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7451 /* Our only callers in this case look for single bit values. So
7452 just return the mode mask. Those tests will then be false. */
7455 #ifndef WORD_REGISTER_OPERATIONS
7456 /* If MODE is wider than X, but both are a single word for both the host
7457 and target machines, we can compute this from which bits of the
7458 object might be nonzero in its own mode, taking into account the fact
7459 that on many CISC machines, accessing an object in a wider mode
7460 causes the high-order bits to become undefined. So they are
7461 not known to be zero. */
7463 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
7464 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
7465 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7466 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
7468 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
7469 nonzero
|= GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
));
7474 code
= GET_CODE (x
);
7478 #ifdef POINTERS_EXTEND_UNSIGNED
7479 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7480 all the bits above ptr_mode are known to be zero. */
7481 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
7482 && REGNO_POINTER_FLAG (REGNO (x
)))
7483 nonzero
&= GET_MODE_MASK (ptr_mode
);
7486 #ifdef STACK_BOUNDARY
7487 /* If this is the stack pointer, we may know something about its
7488 alignment. If PUSH_ROUNDING is defined, it is possible for the
7489 stack to be momentarily aligned only to that amount, so we pick
7490 the least alignment. */
7492 /* We can't check for arg_pointer_rtx here, because it is not
7493 guaranteed to have as much alignment as the stack pointer.
7494 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7495 alignment but the argument pointer has only 64 bit alignment. */
7497 if ((x
== frame_pointer_rtx
7498 || x
== stack_pointer_rtx
7499 || x
== hard_frame_pointer_rtx
7500 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
7501 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
7507 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7509 #ifdef PUSH_ROUNDING
7510 if (REGNO (x
) == STACK_POINTER_REGNUM
)
7511 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
7514 /* We must return here, otherwise we may get a worse result from
7515 one of the choices below. There is nothing useful below as
7516 far as the stack pointer is concerned. */
7517 return nonzero
&= ~ (sp_alignment
- 1);
7521 /* If X is a register whose nonzero bits value is current, use it.
7522 Otherwise, if X is a register whose value we can find, use that
7523 value. Otherwise, use the previously-computed global nonzero bits
7524 for this register. */
7526 if (reg_last_set_value
[REGNO (x
)] != 0
7527 && reg_last_set_mode
[REGNO (x
)] == mode
7528 && (REG_N_SETS (REGNO (x
)) == 1
7529 || reg_last_set_label
[REGNO (x
)] == label_tick
)
7530 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7531 return reg_last_set_nonzero_bits
[REGNO (x
)];
7533 tem
= get_last_value (x
);
7537 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7538 /* If X is narrower than MODE and TEM is a non-negative
7539 constant that would appear negative in the mode of X,
7540 sign-extend it for use in reg_nonzero_bits because some
7541 machines (maybe most) will actually do the sign-extension
7542 and this is the conservative approach.
7544 ??? For 2.5, try to tighten up the MD files in this regard
7545 instead of this kludge. */
7547 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
7548 && GET_CODE (tem
) == CONST_INT
7550 && 0 != (INTVAL (tem
)
7551 & ((HOST_WIDE_INT
) 1
7552 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7553 tem
= GEN_INT (INTVAL (tem
)
7554 | ((HOST_WIDE_INT
) (-1)
7555 << GET_MODE_BITSIZE (GET_MODE (x
))));
7557 return nonzero_bits (tem
, mode
);
7559 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
7560 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
7565 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7566 /* If X is negative in MODE, sign-extend the value. */
7567 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
7568 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
7569 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
7575 #ifdef LOAD_EXTEND_OP
7576 /* In many, if not most, RISC machines, reading a byte from memory
7577 zeros the rest of the register. Noticing that fact saves a lot
7578 of extra zero-extends. */
7579 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
7580 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
7590 /* If this produces an integer result, we know which bits are set.
7591 Code here used to clear bits outside the mode of X, but that is
7594 if (GET_MODE_CLASS (mode
) == MODE_INT
7595 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7596 nonzero
= STORE_FLAG_VALUE
;
7601 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7602 and num_sign_bit_copies. */
7603 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
7604 == GET_MODE_BITSIZE (GET_MODE (x
)))
7608 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
7609 nonzero
|= (GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
)));
7614 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7615 and num_sign_bit_copies. */
7616 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
7617 == GET_MODE_BITSIZE (GET_MODE (x
)))
7623 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
7627 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
7628 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
7629 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
7633 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7634 Otherwise, show all the bits in the outer mode but not the inner
7636 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
7637 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
7639 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
7641 & (((HOST_WIDE_INT
) 1
7642 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
7643 inner_nz
|= (GET_MODE_MASK (mode
)
7644 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
7647 nonzero
&= inner_nz
;
7651 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
7652 & nonzero_bits (XEXP (x
, 1), mode
));
7656 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
7657 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
7658 | nonzero_bits (XEXP (x
, 1), mode
));
7661 case PLUS
: case MINUS
:
7663 case DIV
: case UDIV
:
7664 case MOD
: case UMOD
:
7665 /* We can apply the rules of arithmetic to compute the number of
7666 high- and low-order zero bits of these operations. We start by
7667 computing the width (position of the highest-order non-zero bit)
7668 and the number of low-order zero bits for each value. */
7670 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
7671 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
7672 int width0
= floor_log2 (nz0
) + 1;
7673 int width1
= floor_log2 (nz1
) + 1;
7674 int low0
= floor_log2 (nz0
& -nz0
);
7675 int low1
= floor_log2 (nz1
& -nz1
);
7676 HOST_WIDE_INT op0_maybe_minusp
7677 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
7678 HOST_WIDE_INT op1_maybe_minusp
7679 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
7680 int result_width
= mode_width
;
7688 && (XEXP (x
, 0) == stack_pointer_rtx
7689 || XEXP (x
, 0) == frame_pointer_rtx
)
7690 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7692 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7694 nz0
= (GET_MODE_MASK (mode
) & ~ (sp_alignment
- 1));
7695 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
7696 width0
= floor_log2 (nz0
) + 1;
7697 width1
= floor_log2 (nz1
) + 1;
7698 low0
= floor_log2 (nz0
& -nz0
);
7699 low1
= floor_log2 (nz1
& -nz1
);
7702 result_width
= MAX (width0
, width1
) + 1;
7703 result_low
= MIN (low0
, low1
);
7706 result_low
= MIN (low0
, low1
);
7709 result_width
= width0
+ width1
;
7710 result_low
= low0
+ low1
;
7713 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
7714 result_width
= width0
;
7717 result_width
= width0
;
7720 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
7721 result_width
= MIN (width0
, width1
);
7722 result_low
= MIN (low0
, low1
);
7725 result_width
= MIN (width0
, width1
);
7726 result_low
= MIN (low0
, low1
);
7732 if (result_width
< mode_width
)
7733 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
7736 nonzero
&= ~ (((HOST_WIDE_INT
) 1 << result_low
) - 1);
7741 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7742 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7743 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
7747 /* If this is a SUBREG formed for a promoted variable that has
7748 been zero-extended, we know that at least the high-order bits
7749 are zero, though others might be too. */
7751 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
7752 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
7753 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
7755 /* If the inner mode is a single word for both the host and target
7756 machines, we can compute this from which bits of the inner
7757 object might be nonzero. */
7758 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
7759 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
7760 <= HOST_BITS_PER_WIDE_INT
))
7762 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
7764 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7765 /* If this is a typical RISC machine, we only have to worry
7766 about the way loads are extended. */
7767 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
7769 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1)))
7770 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
7773 /* On many CISC machines, accessing an object in a wider mode
7774 causes the high-order bits to become undefined. So they are
7775 not known to be zero. */
7776 if (GET_MODE_SIZE (GET_MODE (x
))
7777 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7778 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
7779 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
7788 /* The nonzero bits are in two classes: any bits within MODE
7789 that aren't in GET_MODE (x) are always significant. The rest of the
7790 nonzero bits are those that are significant in the operand of
7791 the shift when shifted the appropriate number of bits. This
7792 shows that high-order bits are cleared by the right shift and
7793 low-order bits by left shifts. */
7794 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7795 && INTVAL (XEXP (x
, 1)) >= 0
7796 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7798 enum machine_mode inner_mode
= GET_MODE (x
);
7799 int width
= GET_MODE_BITSIZE (inner_mode
);
7800 int count
= INTVAL (XEXP (x
, 1));
7801 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
7802 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
7803 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
7804 unsigned HOST_WIDE_INT outer
= 0;
7806 if (mode_width
> width
)
7807 outer
= (op_nonzero
& nonzero
& ~ mode_mask
);
7809 if (code
== LSHIFTRT
)
7811 else if (code
== ASHIFTRT
)
7815 /* If the sign bit may have been nonzero before the shift, we
7816 need to mark all the places it could have been copied to
7817 by the shift as possibly nonzero. */
7818 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
7819 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
7821 else if (code
== ASHIFT
)
7824 inner
= ((inner
<< (count
% width
)
7825 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
7827 nonzero
&= (outer
| inner
);
7832 /* This is at most the number of bits in the mode. */
7833 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
7837 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
7838 | nonzero_bits (XEXP (x
, 2), mode
));
7848 /* See the macro definition above. */
7849 #undef num_sign_bit_copies
7851 /* Return the number of bits at the high-order end of X that are known to
7852 be equal to the sign bit. X will be used in mode MODE; if MODE is
7853 VOIDmode, X will be used in its own mode. The returned value will always
7854 be between 1 and the number of bits in MODE. */
7857 num_sign_bit_copies (x
, mode
)
7859 enum machine_mode mode
;
7861 enum rtx_code code
= GET_CODE (x
);
7863 int num0
, num1
, result
;
7864 unsigned HOST_WIDE_INT nonzero
;
7867 /* If we weren't given a mode, use the mode of X. If the mode is still
7868 VOIDmode, we don't know anything. Likewise if one of the modes is
7871 if (mode
== VOIDmode
)
7872 mode
= GET_MODE (x
);
7874 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
7877 bitwidth
= GET_MODE_BITSIZE (mode
);
7879 /* For a smaller object, just ignore the high bits. */
7880 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
7881 return MAX (1, (num_sign_bit_copies (x
, GET_MODE (x
))
7882 - (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
)));
7884 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
7886 #ifndef WORD_REGISTER_OPERATIONS
7887 /* If this machine does not do all register operations on the entire
7888 register and MODE is wider than the mode of X, we can say nothing
7889 at all about the high-order bits. */
7892 /* Likewise on machines that do, if the mode of the object is smaller
7893 than a word and loads of that size don't sign extend, we can say
7894 nothing about the high order bits. */
7895 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
7896 #ifdef LOAD_EXTEND_OP
7897 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
7908 #ifdef POINTERS_EXTEND_UNSIGNED
7909 /* If pointers extend signed and this is a pointer in Pmode, say that
7910 all the bits above ptr_mode are known to be sign bit copies. */
7911 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
7912 && REGNO_POINTER_FLAG (REGNO (x
)))
7913 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
7916 if (reg_last_set_value
[REGNO (x
)] != 0
7917 && reg_last_set_mode
[REGNO (x
)] == mode
7918 && (REG_N_SETS (REGNO (x
)) == 1
7919 || reg_last_set_label
[REGNO (x
)] == label_tick
)
7920 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7921 return reg_last_set_sign_bit_copies
[REGNO (x
)];
7923 tem
= get_last_value (x
);
7925 return num_sign_bit_copies (tem
, mode
);
7927 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
7928 return reg_sign_bit_copies
[REGNO (x
)];
7932 #ifdef LOAD_EXTEND_OP
7933 /* Some RISC machines sign-extend all loads of smaller than a word. */
7934 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
7935 return MAX (1, bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1);
7940 /* If the constant is negative, take its 1's complement and remask.
7941 Then see how many zero bits we have. */
7942 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
7943 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
7944 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
7945 nonzero
= (~ nonzero
) & GET_MODE_MASK (mode
);
7947 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
7950 /* If this is a SUBREG for a promoted object that is sign-extended
7951 and we are looking at it in a wider mode, we know that at least the
7952 high-order bits are known to be sign bit copies. */
7954 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
7955 return MAX (bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
7956 num_sign_bit_copies (SUBREG_REG (x
), mode
));
7958 /* For a smaller object, just ignore the high bits. */
7959 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
7961 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
7962 return MAX (1, (num0
7963 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
7967 #ifdef WORD_REGISTER_OPERATIONS
7968 #ifdef LOAD_EXTEND_OP
7969 /* For paradoxical SUBREGs on machines where all register operations
7970 affect the entire register, just look inside. Note that we are
7971 passing MODE to the recursive call, so the number of sign bit copies
7972 will remain relative to that mode, not the inner mode. */
7974 /* This works only if loads sign extend. Otherwise, if we get a
7975 reload for the inner part, it may be loaded from the stack, and
7976 then we lose all sign bit copies that existed before the store
7979 if ((GET_MODE_SIZE (GET_MODE (x
))
7980 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7981 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
7982 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
7988 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7989 return MAX (1, bitwidth
- INTVAL (XEXP (x
, 1)));
7993 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
7994 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
7997 /* For a smaller object, just ignore the high bits. */
7998 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
7999 return MAX (1, (num0
- (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8003 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8005 case ROTATE
: case ROTATERT
:
8006 /* If we are rotating left by a number of bits less than the number
8007 of sign bit copies, we can just subtract that amount from the
8009 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8010 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
8012 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8013 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8014 : bitwidth
- INTVAL (XEXP (x
, 1))));
8019 /* In general, this subtracts one sign bit copy. But if the value
8020 is known to be positive, the number of sign bit copies is the
8021 same as that of the input. Finally, if the input has just one bit
8022 that might be nonzero, all the bits are copies of the sign bit. */
8023 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8024 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8025 return num0
> 1 ? num0
- 1 : 1;
8027 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8032 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8037 case IOR
: case AND
: case XOR
:
8038 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8039 /* Logical operations will preserve the number of sign-bit copies.
8040 MIN and MAX operations always return one of the operands. */
8041 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8042 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8043 return MIN (num0
, num1
);
8045 case PLUS
: case MINUS
:
8046 /* For addition and subtraction, we can have a 1-bit carry. However,
8047 if we are subtracting 1 from a positive number, there will not
8048 be such a carry. Furthermore, if the positive number is known to
8049 be 0 or 1, we know the result is either -1 or 0. */
8051 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8052 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8054 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8055 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8056 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8057 : bitwidth
- floor_log2 (nonzero
) - 1);
8060 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8061 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8062 return MAX (1, MIN (num0
, num1
) - 1);
8065 /* The number of bits of the product is the sum of the number of
8066 bits of both terms. However, unless one of the terms if known
8067 to be positive, we must allow for an additional bit since negating
8068 a negative number can remove one sign bit copy. */
8070 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8071 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8073 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8075 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8076 || (((nonzero_bits (XEXP (x
, 0), mode
)
8077 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8078 && ((nonzero_bits (XEXP (x
, 1), mode
)
8079 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8082 return MAX (1, result
);
8085 /* The result must be <= the first operand. If the first operand
8086 has the high bit set, we know nothing about the number of sign
8088 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8090 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8091 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8094 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8097 /* The result must be <= the scond operand. */
8098 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8101 /* Similar to unsigned division, except that we have to worry about
8102 the case where the divisor is negative, in which case we have
8104 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8106 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8107 || (nonzero_bits (XEXP (x
, 1), mode
)
8108 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8114 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8116 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8117 || (nonzero_bits (XEXP (x
, 1), mode
)
8118 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8124 /* Shifts by a constant add to the number of bits equal to the
8126 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8127 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8128 && INTVAL (XEXP (x
, 1)) > 0)
8129 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8134 /* Left shifts destroy copies. */
8135 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8136 || INTVAL (XEXP (x
, 1)) < 0
8137 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
8140 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8141 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8144 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8145 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8146 return MIN (num0
, num1
);
8148 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8149 case GEU
: case GTU
: case LEU
: case LTU
:
8150 if (STORE_FLAG_VALUE
== -1)
8158 /* If we haven't been able to figure it out by one of the above rules,
8159 see if some of the high-order bits are known to be zero. If so,
8160 count those bits and return one less than that amount. If we can't
8161 safely compute the mask for this mode, always return BITWIDTH. */
8163 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8166 nonzero
= nonzero_bits (x
, mode
);
8167 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8168 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8171 /* Return the number of "extended" bits there are in X, when interpreted
8172 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8173 unsigned quantities, this is the number of high-order zero bits.
8174 For signed quantities, this is the number of copies of the sign bit
8175 minus 1. In both case, this function returns the number of "spare"
8176 bits. For example, if two quantities for which this function returns
8177 at least 1 are added, the addition is known not to overflow.
8179 This function will always return 0 unless called during combine, which
8180 implies that it must be called from a define_split. */
8183 extended_count (x
, mode
, unsignedp
)
8185 enum machine_mode mode
;
8188 if (nonzero_sign_valid
== 0)
8192 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8193 && (GET_MODE_BITSIZE (mode
) - 1
8194 - floor_log2 (nonzero_bits (x
, mode
))))
8195 : num_sign_bit_copies (x
, mode
) - 1);
8198 /* This function is called from `simplify_shift_const' to merge two
8199 outer operations. Specifically, we have already found that we need
8200 to perform operation *POP0 with constant *PCONST0 at the outermost
8201 position. We would now like to also perform OP1 with constant CONST1
8202 (with *POP0 being done last).
8204 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8205 the resulting operation. *PCOMP_P is set to 1 if we would need to
8206 complement the innermost operand, otherwise it is unchanged.
8208 MODE is the mode in which the operation will be done. No bits outside
8209 the width of this mode matter. It is assumed that the width of this mode
8210 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8212 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8213 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8214 result is simply *PCONST0.
8216 If the resulting operation cannot be expressed as one operation, we
8217 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8220 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8221 enum rtx_code
*pop0
;
8222 HOST_WIDE_INT
*pconst0
;
8224 HOST_WIDE_INT const1
;
8225 enum machine_mode mode
;
8228 enum rtx_code op0
= *pop0
;
8229 HOST_WIDE_INT const0
= *pconst0
;
8230 int width
= GET_MODE_BITSIZE (mode
);
8232 const0
&= GET_MODE_MASK (mode
);
8233 const1
&= GET_MODE_MASK (mode
);
8235 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8239 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8242 if (op1
== NIL
|| op0
== SET
)
8245 else if (op0
== NIL
)
8246 op0
= op1
, const0
= const1
;
8248 else if (op0
== op1
)
8272 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8273 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8276 /* If the two constants aren't the same, we can't do anything. The
8277 remaining six cases can all be done. */
8278 else if (const0
!= const1
)
8286 /* (a & b) | b == b */
8288 else /* op1 == XOR */
8289 /* (a ^ b) | b == a | b */
8295 /* (a & b) ^ b == (~a) & b */
8296 op0
= AND
, *pcomp_p
= 1;
8297 else /* op1 == IOR */
8298 /* (a | b) ^ b == a & ~b */
8299 op0
= AND
, *pconst0
= ~ const0
;
8304 /* (a | b) & b == b */
8306 else /* op1 == XOR */
8307 /* (a ^ b) & b) == (~a) & b */
8314 /* Check for NO-OP cases. */
8315 const0
&= GET_MODE_MASK (mode
);
8317 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8319 else if (const0
== 0 && op0
== AND
)
8321 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8325 /* If this would be an entire word for the target, but is not for
8326 the host, then sign-extend on the host so that the number will look
8327 the same way on the host that it would on the target.
8329 For example, when building a 64 bit alpha hosted 32 bit sparc
8330 targeted compiler, then we want the 32 bit unsigned value -1 to be
8331 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8332 The later confuses the sparc backend. */
8334 if (BITS_PER_WORD
< HOST_BITS_PER_WIDE_INT
&& BITS_PER_WORD
== width
8335 && (const0
& ((HOST_WIDE_INT
) 1 << (width
- 1))))
8336 const0
|= ((HOST_WIDE_INT
) (-1) << width
);
8344 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8345 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8346 that we started with.
8348 The shift is normally computed in the widest mode we find in VAROP, as
8349 long as it isn't a different number of words than RESULT_MODE. Exceptions
8350 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8353 simplify_shift_const (x
, code
, result_mode
, varop
, count
)
8356 enum machine_mode result_mode
;
8360 enum rtx_code orig_code
= code
;
8361 int orig_count
= count
;
8362 enum machine_mode mode
= result_mode
;
8363 enum machine_mode shift_mode
, tmode
;
8365 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8366 /* We form (outer_op (code varop count) (outer_const)). */
8367 enum rtx_code outer_op
= NIL
;
8368 HOST_WIDE_INT outer_const
= 0;
8370 int complement_p
= 0;
8373 /* If we were given an invalid count, don't do anything except exactly
8374 what was requested. */
8376 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
8381 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (count
));
8384 /* Unless one of the branches of the `if' in this loop does a `continue',
8385 we will `break' the loop after the `if'. */
8389 /* If we have an operand of (clobber (const_int 0)), just return that
8391 if (GET_CODE (varop
) == CLOBBER
)
8394 /* If we discovered we had to complement VAROP, leave. Making a NOT
8395 here would cause an infinite loop. */
8399 /* Convert ROTATERT to ROTATE. */
8400 if (code
== ROTATERT
)
8401 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8403 /* We need to determine what mode we will do the shift in. If the
8404 shift is a right shift or a ROTATE, we must always do it in the mode
8405 it was originally done in. Otherwise, we can do it in MODE, the
8406 widest mode encountered. */
8408 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8409 ? result_mode
: mode
);
8411 /* Handle cases where the count is greater than the size of the mode
8412 minus 1. For ASHIFT, use the size minus one as the count (this can
8413 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8414 take the count modulo the size. For other shifts, the result is
8417 Since these shifts are being produced by the compiler by combining
8418 multiple operations, each of which are defined, we know what the
8419 result is supposed to be. */
8421 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
8423 if (code
== ASHIFTRT
)
8424 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8425 else if (code
== ROTATE
|| code
== ROTATERT
)
8426 count
%= GET_MODE_BITSIZE (shift_mode
);
8429 /* We can't simply return zero because there may be an
8437 /* Negative counts are invalid and should not have been made (a
8438 programmer-specified negative count should have been handled
8443 /* An arithmetic right shift of a quantity known to be -1 or 0
8445 if (code
== ASHIFTRT
8446 && (num_sign_bit_copies (varop
, shift_mode
)
8447 == GET_MODE_BITSIZE (shift_mode
)))
8453 /* If we are doing an arithmetic right shift and discarding all but
8454 the sign bit copies, this is equivalent to doing a shift by the
8455 bitsize minus one. Convert it into that shift because it will often
8456 allow other simplifications. */
8458 if (code
== ASHIFTRT
8459 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8460 >= GET_MODE_BITSIZE (shift_mode
)))
8461 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8463 /* We simplify the tests below and elsewhere by converting
8464 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8465 `make_compound_operation' will convert it to a ASHIFTRT for
8466 those machines (such as Vax) that don't have a LSHIFTRT. */
8467 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8469 && ((nonzero_bits (varop
, shift_mode
)
8470 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8474 switch (GET_CODE (varop
))
8480 new = expand_compound_operation (varop
);
8489 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8490 minus the width of a smaller mode, we can do this with a
8491 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8492 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8493 && ! mode_dependent_address_p (XEXP (varop
, 0))
8494 && ! MEM_VOLATILE_P (varop
)
8495 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8496 MODE_INT
, 1)) != BLKmode
)
8498 if (BYTES_BIG_ENDIAN
)
8499 new = gen_rtx_MEM (tmode
, XEXP (varop
, 0));
8501 new = gen_rtx_MEM (tmode
,
8502 plus_constant (XEXP (varop
, 0),
8503 count
/ BITS_PER_UNIT
));
8504 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop
);
8505 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop
);
8506 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop
);
8507 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
8508 : ZERO_EXTEND
, mode
, new);
8515 /* Similar to the case above, except that we can only do this if
8516 the resulting mode is the same as that of the underlying
8517 MEM and adjust the address depending on the *bits* endianness
8518 because of the way that bit-field extract insns are defined. */
8519 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8520 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8521 MODE_INT
, 1)) != BLKmode
8522 && tmode
== GET_MODE (XEXP (varop
, 0)))
8524 if (BITS_BIG_ENDIAN
)
8525 new = XEXP (varop
, 0);
8528 new = copy_rtx (XEXP (varop
, 0));
8529 SUBST (XEXP (new, 0),
8530 plus_constant (XEXP (new, 0),
8531 count
/ BITS_PER_UNIT
));
8534 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
8535 : ZERO_EXTEND
, mode
, new);
8542 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8543 the same number of words as what we've seen so far. Then store
8544 the widest mode in MODE. */
8545 if (subreg_lowpart_p (varop
)
8546 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8547 > GET_MODE_SIZE (GET_MODE (varop
)))
8548 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8549 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8552 varop
= SUBREG_REG (varop
);
8553 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8554 mode
= GET_MODE (varop
);
8560 /* Some machines use MULT instead of ASHIFT because MULT
8561 is cheaper. But it is still better on those machines to
8562 merge two shifts into one. */
8563 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8564 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8566 varop
= gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
8567 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));;
8573 /* Similar, for when divides are cheaper. */
8574 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8575 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8577 varop
= gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
8578 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8584 /* If we are extracting just the sign bit of an arithmetic right
8585 shift, that shift is not needed. */
8586 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1)
8588 varop
= XEXP (varop
, 0);
8592 /* ... fall through ... */
8597 /* Here we have two nested shifts. The result is usually the
8598 AND of a new shift with a mask. We compute the result below. */
8599 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8600 && INTVAL (XEXP (varop
, 1)) >= 0
8601 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8602 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8603 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8605 enum rtx_code first_code
= GET_CODE (varop
);
8606 int first_count
= INTVAL (XEXP (varop
, 1));
8607 unsigned HOST_WIDE_INT mask
;
8610 /* We have one common special case. We can't do any merging if
8611 the inner code is an ASHIFTRT of a smaller mode. However, if
8612 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8613 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8614 we can convert it to
8615 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8616 This simplifies certain SIGN_EXTEND operations. */
8617 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8618 && (GET_MODE_BITSIZE (result_mode
)
8619 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
8621 /* C3 has the low-order C1 bits zero. */
8623 mask
= (GET_MODE_MASK (mode
)
8624 & ~ (((HOST_WIDE_INT
) 1 << first_count
) - 1));
8626 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8627 XEXP (varop
, 0), mask
);
8628 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8630 count
= first_count
;
8635 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8636 than C1 high-order bits equal to the sign bit, we can convert
8637 this to either an ASHIFT or a ASHIFTRT depending on the
8640 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8642 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8643 && GET_MODE (varop
) == shift_mode
8644 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8647 count
-= first_count
;
8649 count
= - count
, code
= ASHIFT
;
8650 varop
= XEXP (varop
, 0);
8654 /* There are some cases we can't do. If CODE is ASHIFTRT,
8655 we can only do this if FIRST_CODE is also ASHIFTRT.
8657 We can't do the case when CODE is ROTATE and FIRST_CODE is
8660 If the mode of this shift is not the mode of the outer shift,
8661 we can't do this if either shift is a right shift or ROTATE.
8663 Finally, we can't do any of these if the mode is too wide
8664 unless the codes are the same.
8666 Handle the case where the shift codes are the same
8669 if (code
== first_code
)
8671 if (GET_MODE (varop
) != result_mode
8672 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8676 count
+= first_count
;
8677 varop
= XEXP (varop
, 0);
8681 if (code
== ASHIFTRT
8682 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8683 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8684 || (GET_MODE (varop
) != result_mode
8685 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8686 || first_code
== ROTATE
8687 || code
== ROTATE
)))
8690 /* To compute the mask to apply after the shift, shift the
8691 nonzero bits of the inner shift the same way the
8692 outer shift will. */
8694 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8697 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8700 /* Give up if we can't compute an outer operation to use. */
8702 || GET_CODE (mask_rtx
) != CONST_INT
8703 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8705 result_mode
, &complement_p
))
8708 /* If the shifts are in the same direction, we add the
8709 counts. Otherwise, we subtract them. */
8710 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8711 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8712 count
+= first_count
;
8714 count
-= first_count
;
8716 /* If COUNT is positive, the new shift is usually CODE,
8717 except for the two exceptions below, in which case it is
8718 FIRST_CODE. If the count is negative, FIRST_CODE should
8721 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8722 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8725 code
= first_code
, count
= - count
;
8727 varop
= XEXP (varop
, 0);
8731 /* If we have (A << B << C) for any shift, we can convert this to
8732 (A << C << B). This wins if A is a constant. Only try this if
8733 B is not a constant. */
8735 else if (GET_CODE (varop
) == code
8736 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
8738 = simplify_binary_operation (code
, mode
,
8742 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
8749 /* Make this fit the case below. */
8750 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
8751 GEN_INT (GET_MODE_MASK (mode
)));
8757 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8758 with C the size of VAROP - 1 and the shift is logical if
8759 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8760 we have an (le X 0) operation. If we have an arithmetic shift
8761 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8762 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8764 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8765 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8766 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8767 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8768 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
8769 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8772 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
8775 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8776 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
8781 /* If we have (shift (logical)), move the logical to the outside
8782 to allow it to possibly combine with another logical and the
8783 shift to combine with another shift. This also canonicalizes to
8784 what a ZERO_EXTRACT looks like. Also, some machines have
8785 (and (shift)) insns. */
8787 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8788 && (new = simplify_binary_operation (code
, result_mode
,
8790 GEN_INT (count
))) != 0
8791 && GET_CODE(new) == CONST_INT
8792 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
8793 INTVAL (new), result_mode
, &complement_p
))
8795 varop
= XEXP (varop
, 0);
8799 /* If we can't do that, try to simplify the shift in each arm of the
8800 logical expression, make a new logical expression, and apply
8801 the inverse distributive law. */
8803 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8804 XEXP (varop
, 0), count
);
8805 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8806 XEXP (varop
, 1), count
);
8808 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
8809 varop
= apply_distributive_law (varop
);
8816 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8817 says that the sign bit can be tested, FOO has mode MODE, C is
8818 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8819 that may be nonzero. */
8820 if (code
== LSHIFTRT
8821 && XEXP (varop
, 1) == const0_rtx
8822 && GET_MODE (XEXP (varop
, 0)) == result_mode
8823 && count
== GET_MODE_BITSIZE (result_mode
) - 1
8824 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8825 && ((STORE_FLAG_VALUE
8826 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (result_mode
) - 1))))
8827 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8828 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8829 (HOST_WIDE_INT
) 1, result_mode
,
8832 varop
= XEXP (varop
, 0);
8839 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8840 than the number of bits in the mode is equivalent to A. */
8841 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
8842 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
8844 varop
= XEXP (varop
, 0);
8849 /* NEG commutes with ASHIFT since it is multiplication. Move the
8850 NEG outside to allow shifts to combine. */
8852 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
8853 (HOST_WIDE_INT
) 0, result_mode
,
8856 varop
= XEXP (varop
, 0);
8862 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8863 is one less than the number of bits in the mode is
8864 equivalent to (xor A 1). */
8865 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
8866 && XEXP (varop
, 1) == constm1_rtx
8867 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8868 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8869 (HOST_WIDE_INT
) 1, result_mode
,
8873 varop
= XEXP (varop
, 0);
8877 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8878 that might be nonzero in BAR are those being shifted out and those
8879 bits are known zero in FOO, we can replace the PLUS with FOO.
8880 Similarly in the other operand order. This code occurs when
8881 we are computing the size of a variable-size array. */
8883 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8884 && count
< HOST_BITS_PER_WIDE_INT
8885 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
8886 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
8887 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
8889 varop
= XEXP (varop
, 0);
8892 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8893 && count
< HOST_BITS_PER_WIDE_INT
8894 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8895 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
8897 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
8898 & nonzero_bits (XEXP (varop
, 1),
8901 varop
= XEXP (varop
, 1);
8905 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8907 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
8908 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
8910 GEN_INT (count
))) != 0
8911 && GET_CODE(new) == CONST_INT
8912 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
8913 INTVAL (new), result_mode
, &complement_p
))
8915 varop
= XEXP (varop
, 0);
8921 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8922 with C the size of VAROP - 1 and the shift is logical if
8923 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8924 we have a (gt X 0) operation. If the shift is arithmetic with
8925 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8926 we have a (neg (gt X 0)) operation. */
8928 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8929 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
8930 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
8931 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8932 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
8933 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
8934 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8937 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
8940 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8941 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
8948 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8949 if the truncate does not affect the value. */
8950 if (code
== LSHIFTRT
8951 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
8952 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
8953 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
8954 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
8955 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
8957 rtx varop_inner
= XEXP (varop
, 0);
8959 varop_inner
= gen_rtx_combine (LSHIFTRT
,
8960 GET_MODE (varop_inner
),
8961 XEXP (varop_inner
, 0),
8962 GEN_INT (count
+ INTVAL (XEXP (varop_inner
, 1))));
8963 varop
= gen_rtx_combine (TRUNCATE
, GET_MODE (varop
),
8977 /* We need to determine what mode to do the shift in. If the shift is
8978 a right shift or ROTATE, we must always do it in the mode it was
8979 originally done in. Otherwise, we can do it in MODE, the widest mode
8980 encountered. The code we care about is that of the shift that will
8981 actually be done, not the shift that was originally requested. */
8983 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8984 ? result_mode
: mode
);
8986 /* We have now finished analyzing the shift. The result should be
8987 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8988 OUTER_OP is non-NIL, it is an operation that needs to be applied
8989 to the result of the shift. OUTER_CONST is the relevant constant,
8990 but we must turn off all bits turned off in the shift.
8992 If we were passed a value for X, see if we can use any pieces of
8993 it. If not, make new rtx. */
8995 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
8996 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8997 && INTVAL (XEXP (x
, 1)) == count
)
8998 const_rtx
= XEXP (x
, 1);
9000 const_rtx
= GEN_INT (count
);
9002 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9003 && GET_MODE (XEXP (x
, 0)) == shift_mode
9004 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9005 varop
= XEXP (x
, 0);
9006 else if (GET_MODE (varop
) != shift_mode
)
9007 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9009 /* If we can't make the SUBREG, try to return what we were given. */
9010 if (GET_CODE (varop
) == CLOBBER
)
9011 return x
? x
: varop
;
9013 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9018 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9019 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
9021 SUBST (XEXP (x
, 0), varop
);
9022 SUBST (XEXP (x
, 1), const_rtx
);
9025 /* If we have an outer operation and we just made a shift, it is
9026 possible that we could have simplified the shift were it not
9027 for the outer operation. So try to do the simplification
9030 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9031 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9032 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9033 INTVAL (XEXP (x
, 1)));
9035 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9036 turn off all the bits that the shift would have turned off. */
9037 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9038 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9039 GET_MODE_MASK (result_mode
) >> orig_count
);
9041 /* Do the remainder of the processing in RESULT_MODE. */
9042 x
= gen_lowpart_for_combine (result_mode
, x
);
9044 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9047 x
= gen_unary (NOT
, result_mode
, result_mode
, x
);
9049 if (outer_op
!= NIL
)
9051 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9053 int width
= GET_MODE_BITSIZE (result_mode
);
9055 outer_const
&= GET_MODE_MASK (result_mode
);
9057 /* If this would be an entire word for the target, but is not for
9058 the host, then sign-extend on the host so that the number will
9059 look the same way on the host that it would on the target.
9061 For example, when building a 64 bit alpha hosted 32 bit sparc
9062 targeted compiler, then we want the 32 bit unsigned value -1 to be
9063 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
9064 The later confuses the sparc backend. */
9066 if (BITS_PER_WORD
< HOST_BITS_PER_WIDE_INT
&& BITS_PER_WORD
== width
9067 && (outer_const
& ((HOST_WIDE_INT
) 1 << (width
- 1))))
9068 outer_const
|= ((HOST_WIDE_INT
) (-1) << width
);
9071 if (outer_op
== AND
)
9072 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9073 else if (outer_op
== SET
)
9074 /* This means that we have determined that the result is
9075 equivalent to a constant. This should be rare. */
9076 x
= GEN_INT (outer_const
);
9077 else if (GET_RTX_CLASS (outer_op
) == '1')
9078 x
= gen_unary (outer_op
, result_mode
, result_mode
, x
);
9080 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9086 /* Like recog, but we receive the address of a pointer to a new pattern.
9087 We try to match the rtx that the pointer points to.
9088 If that fails, we may try to modify or replace the pattern,
9089 storing the replacement into the same pointer object.
9091 Modifications include deletion or addition of CLOBBERs.
9093 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9094 the CLOBBERs are placed.
9096 The value is the final insn code from the pattern ultimately matched,
9100 recog_for_combine (pnewpat
, insn
, pnotes
)
9105 register rtx pat
= *pnewpat
;
9106 int insn_code_number
;
9107 int num_clobbers_to_add
= 0;
9111 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9112 we use to indicate that something didn't match. If we find such a
9113 thing, force rejection. */
9114 if (GET_CODE (pat
) == PARALLEL
)
9115 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9116 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9117 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9120 /* Is the result of combination a valid instruction? */
9121 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9123 /* If it isn't, there is the possibility that we previously had an insn
9124 that clobbered some register as a side effect, but the combined
9125 insn doesn't need to do that. So try once more without the clobbers
9126 unless this represents an ASM insn. */
9128 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9129 && GET_CODE (pat
) == PARALLEL
)
9133 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9134 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9137 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9141 SUBST_INT (XVECLEN (pat
, 0), pos
);
9144 pat
= XVECEXP (pat
, 0, 0);
9146 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9149 /* If we had any clobbers to add, make a new pattern than contains
9150 them. Then check to make sure that all of them are dead. */
9151 if (num_clobbers_to_add
)
9153 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9154 gen_rtvec (GET_CODE (pat
) == PARALLEL
9155 ? XVECLEN (pat
, 0) + num_clobbers_to_add
9156 : num_clobbers_to_add
+ 1));
9158 if (GET_CODE (pat
) == PARALLEL
)
9159 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9160 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9162 XVECEXP (newpat
, 0, 0) = pat
;
9164 add_clobbers (newpat
, insn_code_number
);
9166 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9167 i
< XVECLEN (newpat
, 0); i
++)
9169 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9170 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9172 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9173 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9181 return insn_code_number
;
9184 /* Like gen_lowpart but for use by combine. In combine it is not possible
9185 to create any new pseudoregs. However, it is safe to create
9186 invalid memory addresses, because combine will try to recognize
9187 them and all they will do is make the combine attempt fail.
9189 If for some reason this cannot do its job, an rtx
9190 (clobber (const_int 0)) is returned.
9191 An insn containing that will not be recognized. */
9196 gen_lowpart_for_combine (mode
, x
)
9197 enum machine_mode mode
;
9202 if (GET_MODE (x
) == mode
)
9205 /* We can only support MODE being wider than a word if X is a
9206 constant integer or has a mode the same size. */
9208 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9209 && ! ((GET_MODE (x
) == VOIDmode
9210 && (GET_CODE (x
) == CONST_INT
9211 || GET_CODE (x
) == CONST_DOUBLE
))
9212 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9213 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9215 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9216 won't know what to do. So we will strip off the SUBREG here and
9217 process normally. */
9218 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9221 if (GET_MODE (x
) == mode
)
9225 result
= gen_lowpart_common (mode
, x
);
9227 && GET_CODE (result
) == SUBREG
9228 && GET_CODE (SUBREG_REG (result
)) == REG
9229 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9230 && (GET_MODE_SIZE (GET_MODE (result
))
9231 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result
)))))
9232 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result
))) = 1;
9237 if (GET_CODE (x
) == MEM
)
9239 register int offset
= 0;
9242 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9244 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9245 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9247 /* If we want to refer to something bigger than the original memref,
9248 generate a perverse subreg instead. That will force a reload
9249 of the original memref X. */
9250 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9251 return gen_rtx_SUBREG (mode
, x
, 0);
9253 if (WORDS_BIG_ENDIAN
)
9254 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9255 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9256 if (BYTES_BIG_ENDIAN
)
9258 /* Adjust the address so that the address-after-the-data is
9260 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9261 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9263 new = gen_rtx_MEM (mode
, plus_constant (XEXP (x
, 0), offset
));
9264 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x
);
9265 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x
);
9266 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x
);
9270 /* If X is a comparison operator, rewrite it in a new mode. This
9271 probably won't match, but may allow further simplifications. */
9272 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9273 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9275 /* If we couldn't simplify X any other way, just enclose it in a
9276 SUBREG. Normally, this SUBREG won't match, but some patterns may
9277 include an explicit SUBREG or we may simplify it further in combine. */
9282 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
9283 word
= ((GET_MODE_SIZE (GET_MODE (x
))
9284 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
9286 return gen_rtx_SUBREG (mode
, x
, word
);
9290 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9291 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9293 If the identical expression was previously in the insn (in the undobuf),
9294 it will be returned. Only if it is not found will a new expression
9299 gen_rtx_combine
VPROTO((enum rtx_code code
, enum machine_mode mode
, ...))
9301 #ifndef ANSI_PROTOTYPES
9303 enum machine_mode mode
;
9315 #ifndef ANSI_PROTOTYPES
9316 code
= va_arg (p
, enum rtx_code
);
9317 mode
= va_arg (p
, enum machine_mode
);
9320 n_args
= GET_RTX_LENGTH (code
);
9321 fmt
= GET_RTX_FORMAT (code
);
9323 if (n_args
== 0 || n_args
> 3)
9326 /* Get each arg and verify that it is supposed to be an expression. */
9327 for (j
= 0; j
< n_args
; j
++)
9332 args
[j
] = va_arg (p
, rtx
);
9335 /* See if this is in undobuf. Be sure we don't use objects that came
9336 from another insn; this could produce circular rtl structures. */
9338 for (undo
= undobuf
.undos
; undo
!= undobuf
.previous_undos
; undo
= undo
->next
)
9340 && GET_CODE (undo
->old_contents
.r
) == code
9341 && GET_MODE (undo
->old_contents
.r
) == mode
)
9343 for (j
= 0; j
< n_args
; j
++)
9344 if (XEXP (undo
->old_contents
.r
, j
) != args
[j
])
9348 return undo
->old_contents
.r
;
9351 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9352 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9353 rt
= rtx_alloc (code
);
9354 PUT_MODE (rt
, mode
);
9355 XEXP (rt
, 0) = args
[0];
9358 XEXP (rt
, 1) = args
[1];
9360 XEXP (rt
, 2) = args
[2];
9365 /* These routines make binary and unary operations by first seeing if they
9366 fold; if not, a new expression is allocated. */
9369 gen_binary (code
, mode
, op0
, op1
)
9371 enum machine_mode mode
;
9377 if (GET_RTX_CLASS (code
) == 'c'
9378 && (GET_CODE (op0
) == CONST_INT
9379 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
9380 tem
= op0
, op0
= op1
, op1
= tem
;
9382 if (GET_RTX_CLASS (code
) == '<')
9384 enum machine_mode op_mode
= GET_MODE (op0
);
9386 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9387 just (REL_OP X Y). */
9388 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9390 op1
= XEXP (op0
, 1);
9391 op0
= XEXP (op0
, 0);
9392 op_mode
= GET_MODE (op0
);
9395 if (op_mode
== VOIDmode
)
9396 op_mode
= GET_MODE (op1
);
9397 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9400 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9405 /* Put complex operands first and constants second. */
9406 if (GET_RTX_CLASS (code
) == 'c'
9407 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9408 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
9409 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
9410 || (GET_CODE (op0
) == SUBREG
9411 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
9412 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
9413 return gen_rtx_combine (code
, mode
, op1
, op0
);
9415 /* If we are turning off bits already known off in OP0, we need not do
9417 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9418 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9419 && (nonzero_bits (op0
, mode
) & ~ INTVAL (op1
)) == 0)
9422 return gen_rtx_combine (code
, mode
, op0
, op1
);
9426 gen_unary (code
, mode
, op0_mode
, op0
)
9428 enum machine_mode mode
, op0_mode
;
9431 rtx result
= simplify_unary_operation (code
, mode
, op0
, op0_mode
);
9436 return gen_rtx_combine (code
, mode
, op0
);
9439 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9440 comparison code that will be tested.
9442 The result is a possibly different comparison code to use. *POP0 and
9443 *POP1 may be updated.
9445 It is possible that we might detect that a comparison is either always
9446 true or always false. However, we do not perform general constant
9447 folding in combine, so this knowledge isn't useful. Such tautologies
9448 should have been detected earlier. Hence we ignore all such cases. */
9450 static enum rtx_code
9451 simplify_comparison (code
, pop0
, pop1
)
9460 enum machine_mode mode
, tmode
;
9462 /* Try a few ways of applying the same transformation to both operands. */
9465 #ifndef WORD_REGISTER_OPERATIONS
9466 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9467 so check specially. */
9468 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9469 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9470 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9471 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9472 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9473 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9474 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9475 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9476 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9477 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
9478 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9479 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
9480 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
9481 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
9482 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
9483 && (INTVAL (XEXP (op0
, 1))
9484 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9486 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9488 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9489 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9493 /* If both operands are the same constant shift, see if we can ignore the
9494 shift. We can if the shift is a rotate or if the bits shifted out of
9495 this shift are known to be zero for both inputs and if the type of
9496 comparison is compatible with the shift. */
9497 if (GET_CODE (op0
) == GET_CODE (op1
)
9498 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9499 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9500 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9501 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9502 || (GET_CODE (op0
) == ASHIFTRT
9503 && (code
!= GTU
&& code
!= LTU
9504 && code
!= GEU
&& code
!= GEU
)))
9505 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9506 && INTVAL (XEXP (op0
, 1)) >= 0
9507 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9508 && XEXP (op0
, 1) == XEXP (op1
, 1))
9510 enum machine_mode mode
= GET_MODE (op0
);
9511 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9512 int shift_count
= INTVAL (XEXP (op0
, 1));
9514 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9515 mask
&= (mask
>> shift_count
) << shift_count
;
9516 else if (GET_CODE (op0
) == ASHIFT
)
9517 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9519 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~ mask
) == 0
9520 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~ mask
) == 0)
9521 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9526 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9527 SUBREGs are of the same mode, and, in both cases, the AND would
9528 be redundant if the comparison was done in the narrower mode,
9529 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9530 and the operand's possibly nonzero bits are 0xffffff01; in that case
9531 if we only care about QImode, we don't need the AND). This case
9532 occurs if the output mode of an scc insn is not SImode and
9533 STORE_FLAG_VALUE == 1 (e.g., the 386).
9535 Similarly, check for a case where the AND's are ZERO_EXTEND
9536 operations from some narrower mode even though a SUBREG is not
9539 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9540 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9541 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9543 rtx inner_op0
= XEXP (op0
, 0);
9544 rtx inner_op1
= XEXP (op1
, 0);
9545 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9546 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9549 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9550 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9551 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9552 && (GET_MODE (SUBREG_REG (inner_op0
))
9553 == GET_MODE (SUBREG_REG (inner_op1
)))
9554 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9555 <= HOST_BITS_PER_WIDE_INT
)
9556 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9557 GET_MODE (SUBREG_REG (inner_op0
)))))
9558 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9559 GET_MODE (SUBREG_REG (inner_op1
))))))
9561 op0
= SUBREG_REG (inner_op0
);
9562 op1
= SUBREG_REG (inner_op1
);
9564 /* The resulting comparison is always unsigned since we masked
9565 off the original sign bit. */
9566 code
= unsigned_condition (code
);
9572 for (tmode
= GET_CLASS_NARROWEST_MODE
9573 (GET_MODE_CLASS (GET_MODE (op0
)));
9574 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9575 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9577 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
9578 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
9579 code
= unsigned_condition (code
);
9588 /* If both operands are NOT, we can strip off the outer operation
9589 and adjust the comparison code for swapped operands; similarly for
9590 NEG, except that this must be an equality comparison. */
9591 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9592 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9593 && (code
== EQ
|| code
== NE
)))
9594 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9600 /* If the first operand is a constant, swap the operands and adjust the
9601 comparison code appropriately, but don't do this if the second operand
9602 is already a constant integer. */
9603 if (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9605 tem
= op0
, op0
= op1
, op1
= tem
;
9606 code
= swap_condition (code
);
9609 /* We now enter a loop during which we will try to simplify the comparison.
9610 For the most part, we only are concerned with comparisons with zero,
9611 but some things may really be comparisons with zero but not start
9612 out looking that way. */
9614 while (GET_CODE (op1
) == CONST_INT
)
9616 enum machine_mode mode
= GET_MODE (op0
);
9617 int mode_width
= GET_MODE_BITSIZE (mode
);
9618 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9619 int equality_comparison_p
;
9620 int sign_bit_comparison_p
;
9621 int unsigned_comparison_p
;
9622 HOST_WIDE_INT const_op
;
9624 /* We only want to handle integral modes. This catches VOIDmode,
9625 CCmode, and the floating-point modes. An exception is that we
9626 can handle VOIDmode if OP0 is a COMPARE or a comparison
9629 if (GET_MODE_CLASS (mode
) != MODE_INT
9630 && ! (mode
== VOIDmode
9631 && (GET_CODE (op0
) == COMPARE
9632 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
9635 /* Get the constant we are comparing against and turn off all bits
9636 not on in our mode. */
9637 const_op
= INTVAL (op1
);
9638 if (mode_width
<= HOST_BITS_PER_WIDE_INT
)
9641 /* If we are comparing against a constant power of two and the value
9642 being compared can only have that single bit nonzero (e.g., it was
9643 `and'ed with that bit), we can replace this with a comparison
9646 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9647 || code
== LT
|| code
== LTU
)
9648 && mode_width
<= HOST_BITS_PER_WIDE_INT
9649 && exact_log2 (const_op
) >= 0
9650 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9652 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9653 op1
= const0_rtx
, const_op
= 0;
9656 /* Similarly, if we are comparing a value known to be either -1 or
9657 0 with -1, change it to the opposite comparison against zero. */
9660 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9661 || code
== GEU
|| code
== LTU
)
9662 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9664 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9665 op1
= const0_rtx
, const_op
= 0;
9668 /* Do some canonicalizations based on the comparison code. We prefer
9669 comparisons against zero and then prefer equality comparisons.
9670 If we can reduce the size of a constant, we will do that too. */
9675 /* < C is equivalent to <= (C - 1) */
9679 op1
= GEN_INT (const_op
);
9681 /* ... fall through to LE case below. */
9687 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9691 op1
= GEN_INT (const_op
);
9695 /* If we are doing a <= 0 comparison on a value known to have
9696 a zero sign bit, we can replace this with == 0. */
9697 else if (const_op
== 0
9698 && mode_width
<= HOST_BITS_PER_WIDE_INT
9699 && (nonzero_bits (op0
, mode
)
9700 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9705 /* >= C is equivalent to > (C - 1). */
9709 op1
= GEN_INT (const_op
);
9711 /* ... fall through to GT below. */
9717 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9721 op1
= GEN_INT (const_op
);
9725 /* If we are doing a > 0 comparison on a value known to have
9726 a zero sign bit, we can replace this with != 0. */
9727 else if (const_op
== 0
9728 && mode_width
<= HOST_BITS_PER_WIDE_INT
9729 && (nonzero_bits (op0
, mode
)
9730 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9735 /* < C is equivalent to <= (C - 1). */
9739 op1
= GEN_INT (const_op
);
9741 /* ... fall through ... */
9744 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9745 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9746 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9748 const_op
= 0, op1
= const0_rtx
;
9756 /* unsigned <= 0 is equivalent to == 0 */
9760 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9761 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9762 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9764 const_op
= 0, op1
= const0_rtx
;
9770 /* >= C is equivalent to < (C - 1). */
9774 op1
= GEN_INT (const_op
);
9776 /* ... fall through ... */
9779 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9780 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9781 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9783 const_op
= 0, op1
= const0_rtx
;
9791 /* unsigned > 0 is equivalent to != 0 */
9795 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9796 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9797 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9799 const_op
= 0, op1
= const0_rtx
;
9808 /* Compute some predicates to simplify code below. */
9810 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9811 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9812 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9815 /* If this is a sign bit comparison and we can do arithmetic in
9816 MODE, say that we will only be needing the sign bit of OP0. */
9817 if (sign_bit_comparison_p
9818 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9819 op0
= force_to_mode (op0
, mode
,
9821 << (GET_MODE_BITSIZE (mode
) - 1)),
9824 /* Now try cases based on the opcode of OP0. If none of the cases
9825 does a "continue", we exit this loop immediately after the
9828 switch (GET_CODE (op0
))
9831 /* If we are extracting a single bit from a variable position in
9832 a constant that has only a single bit set and are comparing it
9833 with zero, we can convert this into an equality comparison
9834 between the position and the location of the single bit. */
9836 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
9837 && XEXP (op0
, 1) == const1_rtx
9838 && equality_comparison_p
&& const_op
== 0
9839 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
9841 if (BITS_BIG_ENDIAN
)
9844 mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][1];
9845 if (mode
== VOIDmode
)
9847 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
9849 i
= BITS_PER_WORD
- 1 - i
;
9853 op0
= XEXP (op0
, 2);
9857 /* Result is nonzero iff shift count is equal to I. */
9858 code
= reverse_condition (code
);
9862 /* ... fall through ... */
9865 tem
= expand_compound_operation (op0
);
9874 /* If testing for equality, we can take the NOT of the constant. */
9875 if (equality_comparison_p
9876 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
9878 op0
= XEXP (op0
, 0);
9883 /* If just looking at the sign bit, reverse the sense of the
9885 if (sign_bit_comparison_p
)
9887 op0
= XEXP (op0
, 0);
9888 code
= (code
== GE
? LT
: GE
);
9894 /* If testing for equality, we can take the NEG of the constant. */
9895 if (equality_comparison_p
9896 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
9898 op0
= XEXP (op0
, 0);
9903 /* The remaining cases only apply to comparisons with zero. */
9907 /* When X is ABS or is known positive,
9908 (neg X) is < 0 if and only if X != 0. */
9910 if (sign_bit_comparison_p
9911 && (GET_CODE (XEXP (op0
, 0)) == ABS
9912 || (mode_width
<= HOST_BITS_PER_WIDE_INT
9913 && (nonzero_bits (XEXP (op0
, 0), mode
)
9914 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
9916 op0
= XEXP (op0
, 0);
9917 code
= (code
== LT
? NE
: EQ
);
9921 /* If we have NEG of something whose two high-order bits are the
9922 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9923 if (num_sign_bit_copies (op0
, mode
) >= 2)
9925 op0
= XEXP (op0
, 0);
9926 code
= swap_condition (code
);
9932 /* If we are testing equality and our count is a constant, we
9933 can perform the inverse operation on our RHS. */
9934 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
9935 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
9936 op1
, XEXP (op0
, 1))) != 0)
9938 op0
= XEXP (op0
, 0);
9943 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9944 a particular bit. Convert it to an AND of a constant of that
9945 bit. This will be converted into a ZERO_EXTRACT. */
9946 if (const_op
== 0 && sign_bit_comparison_p
9947 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9948 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
9950 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
9953 - INTVAL (XEXP (op0
, 1)))));
9954 code
= (code
== LT
? NE
: EQ
);
9958 /* ... fall through ... */
9961 /* ABS is ignorable inside an equality comparison with zero. */
9962 if (const_op
== 0 && equality_comparison_p
)
9964 op0
= XEXP (op0
, 0);
9971 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9972 to (compare FOO CONST) if CONST fits in FOO's mode and we
9973 are either testing inequality or have an unsigned comparison
9974 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9975 if (! unsigned_comparison_p
9976 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
9977 <= HOST_BITS_PER_WIDE_INT
)
9978 && ((unsigned HOST_WIDE_INT
) const_op
9979 < (((unsigned HOST_WIDE_INT
) 1
9980 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
9982 op0
= XEXP (op0
, 0);
9988 /* Check for the case where we are comparing A - C1 with C2,
9989 both constants are smaller than 1/2 the maximum positive
9990 value in MODE, and the comparison is equality or unsigned.
9991 In that case, if A is either zero-extended to MODE or has
9992 sufficient sign bits so that the high-order bit in MODE
9993 is a copy of the sign in the inner mode, we can prove that it is
9994 safe to do the operation in the wider mode. This simplifies
9995 many range checks. */
9997 if (mode_width
<= HOST_BITS_PER_WIDE_INT
9998 && subreg_lowpart_p (op0
)
9999 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10000 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10001 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10002 && (- INTVAL (XEXP (SUBREG_REG (op0
), 1))
10003 < (HOST_WIDE_INT
)(GET_MODE_MASK (mode
) / 2))
10004 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10005 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10006 GET_MODE (SUBREG_REG (op0
)))
10007 & ~ GET_MODE_MASK (mode
))
10008 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10009 GET_MODE (SUBREG_REG (op0
)))
10010 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10011 - GET_MODE_BITSIZE (mode
)))))
10013 op0
= SUBREG_REG (op0
);
10017 /* If the inner mode is narrower and we are extracting the low part,
10018 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10019 if (subreg_lowpart_p (op0
)
10020 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10021 /* Fall through */ ;
10025 /* ... fall through ... */
10028 if ((unsigned_comparison_p
|| equality_comparison_p
)
10029 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10030 <= HOST_BITS_PER_WIDE_INT
)
10031 && ((unsigned HOST_WIDE_INT
) const_op
10032 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10034 op0
= XEXP (op0
, 0);
10040 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10041 this for equality comparisons due to pathological cases involving
10043 if (equality_comparison_p
10044 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10045 op1
, XEXP (op0
, 1))))
10047 op0
= XEXP (op0
, 0);
10052 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10053 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10054 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10056 op0
= XEXP (XEXP (op0
, 0), 0);
10057 code
= (code
== LT
? EQ
: NE
);
10063 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10064 (eq B (minus A C)), whichever simplifies. We can only do
10065 this for equality comparisons due to pathological cases involving
10067 if (equality_comparison_p
10068 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10069 XEXP (op0
, 1), op1
)))
10071 op0
= XEXP (op0
, 0);
10076 if (equality_comparison_p
10077 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10078 XEXP (op0
, 0), op1
)))
10080 op0
= XEXP (op0
, 1);
10085 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10086 of bits in X minus 1, is one iff X > 0. */
10087 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10088 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10089 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10090 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10092 op0
= XEXP (op0
, 1);
10093 code
= (code
== GE
? LE
: GT
);
10099 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10100 if C is zero or B is a constant. */
10101 if (equality_comparison_p
10102 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10103 XEXP (op0
, 1), op1
)))
10105 op0
= XEXP (op0
, 0);
10112 case LT
: case LTU
: case LE
: case LEU
:
10113 case GT
: case GTU
: case GE
: case GEU
:
10114 /* We can't do anything if OP0 is a condition code value, rather
10115 than an actual data value. */
10118 || XEXP (op0
, 0) == cc0_rtx
10120 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10123 /* Get the two operands being compared. */
10124 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10125 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10127 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10129 /* Check for the cases where we simply want the result of the
10130 earlier test or the opposite of that result. */
10132 || (code
== EQ
&& reversible_comparison_p (op0
))
10133 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10134 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10135 && (STORE_FLAG_VALUE
10136 & (((HOST_WIDE_INT
) 1
10137 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10139 || (code
== GE
&& reversible_comparison_p (op0
)))))
10141 code
= (code
== LT
|| code
== NE
10142 ? GET_CODE (op0
) : reverse_condition (GET_CODE (op0
)));
10143 op0
= tem
, op1
= tem1
;
10149 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10151 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10152 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10153 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10155 op0
= XEXP (op0
, 1);
10156 code
= (code
== GE
? GT
: LE
);
10162 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10163 will be converted to a ZERO_EXTRACT later. */
10164 if (const_op
== 0 && equality_comparison_p
10165 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10166 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10168 op0
= simplify_and_const_int
10169 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10171 XEXP (XEXP (op0
, 0), 1)),
10172 (HOST_WIDE_INT
) 1);
10176 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10177 zero and X is a comparison and C1 and C2 describe only bits set
10178 in STORE_FLAG_VALUE, we can compare with X. */
10179 if (const_op
== 0 && equality_comparison_p
10180 && mode_width
<= HOST_BITS_PER_WIDE_INT
10181 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10182 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10183 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10184 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10185 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10187 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10188 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10189 if ((~ STORE_FLAG_VALUE
& mask
) == 0
10190 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10191 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10192 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10194 op0
= XEXP (XEXP (op0
, 0), 0);
10199 /* If we are doing an equality comparison of an AND of a bit equal
10200 to the sign bit, replace this with a LT or GE comparison of
10201 the underlying value. */
10202 if (equality_comparison_p
10204 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10205 && mode_width
<= HOST_BITS_PER_WIDE_INT
10206 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10207 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10209 op0
= XEXP (op0
, 0);
10210 code
= (code
== EQ
? GE
: LT
);
10214 /* If this AND operation is really a ZERO_EXTEND from a narrower
10215 mode, the constant fits within that mode, and this is either an
10216 equality or unsigned comparison, try to do this comparison in
10217 the narrower mode. */
10218 if ((equality_comparison_p
|| unsigned_comparison_p
)
10219 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10220 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10221 & GET_MODE_MASK (mode
))
10223 && const_op
>> i
== 0
10224 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10226 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10230 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10231 in both M1 and M2 and the SUBREG is either paradoxical or
10232 represents the low part, permute the SUBREG and the AND and
10234 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10236 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10237 #ifdef WORD_REGISTER_OPERATIONS
10238 || subreg_lowpart_p (XEXP (op0
, 0))
10241 #ifndef WORD_REGISTER_OPERATIONS
10242 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10243 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10244 As originally written the upper bits have a defined value
10245 due to the AND operation. However, if we commute the AND
10246 inside the SUBREG then they no longer have defined values
10247 and the meaning of the code has been changed. */
10248 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10249 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10251 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10252 && mode_width
<= HOST_BITS_PER_WIDE_INT
10253 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10254 <= HOST_BITS_PER_WIDE_INT
)
10255 && (INTVAL (XEXP (op0
, 1)) & ~ mask
) == 0
10256 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10257 & INTVAL (XEXP (op0
, 1)))
10258 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10259 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10260 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10264 = gen_lowpart_for_combine
10266 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10267 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10274 /* If we have (compare (ashift FOO N) (const_int C)) and
10275 the high order N bits of FOO (N+1 if an inequality comparison)
10276 are known to be zero, we can do this by comparing FOO with C
10277 shifted right N bits so long as the low-order N bits of C are
10279 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10280 && INTVAL (XEXP (op0
, 1)) >= 0
10281 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10282 < HOST_BITS_PER_WIDE_INT
)
10284 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10285 && mode_width
<= HOST_BITS_PER_WIDE_INT
10286 && (nonzero_bits (XEXP (op0
, 0), mode
)
10287 & ~ (mask
>> (INTVAL (XEXP (op0
, 1))
10288 + ! equality_comparison_p
))) == 0)
10290 const_op
>>= INTVAL (XEXP (op0
, 1));
10291 op1
= GEN_INT (const_op
);
10292 op0
= XEXP (op0
, 0);
10296 /* If we are doing a sign bit comparison, it means we are testing
10297 a particular bit. Convert it to the appropriate AND. */
10298 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10299 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10301 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10304 - INTVAL (XEXP (op0
, 1)))));
10305 code
= (code
== LT
? NE
: EQ
);
10309 /* If this an equality comparison with zero and we are shifting
10310 the low bit to the sign bit, we can convert this to an AND of the
10312 if (const_op
== 0 && equality_comparison_p
10313 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10314 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10316 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10317 (HOST_WIDE_INT
) 1);
10323 /* If this is an equality comparison with zero, we can do this
10324 as a logical shift, which might be much simpler. */
10325 if (equality_comparison_p
&& const_op
== 0
10326 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10328 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10330 INTVAL (XEXP (op0
, 1)));
10334 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10335 do the comparison in a narrower mode. */
10336 if (! unsigned_comparison_p
10337 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10338 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10339 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10340 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10341 MODE_INT
, 1)) != BLKmode
10342 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10343 || ((unsigned HOST_WIDE_INT
) - const_op
10344 <= GET_MODE_MASK (tmode
))))
10346 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10350 /* ... fall through ... */
10352 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10353 the low order N bits of FOO are known to be zero, we can do this
10354 by comparing FOO with C shifted left N bits so long as no
10355 overflow occurs. */
10356 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10357 && INTVAL (XEXP (op0
, 1)) >= 0
10358 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10359 && mode_width
<= HOST_BITS_PER_WIDE_INT
10360 && (nonzero_bits (XEXP (op0
, 0), mode
)
10361 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10363 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10366 const_op
<<= INTVAL (XEXP (op0
, 1));
10367 op1
= GEN_INT (const_op
);
10368 op0
= XEXP (op0
, 0);
10372 /* If we are using this shift to extract just the sign bit, we
10373 can replace this with an LT or GE comparison. */
10375 && (equality_comparison_p
|| sign_bit_comparison_p
)
10376 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10377 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10379 op0
= XEXP (op0
, 0);
10380 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10392 /* Now make any compound operations involved in this comparison. Then,
10393 check for an outmost SUBREG on OP0 that is not doing anything or is
10394 paradoxical. The latter case can only occur when it is known that the
10395 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10396 We can never remove a SUBREG for a non-equality comparison because the
10397 sign bit is in a different place in the underlying object. */
10399 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10400 op1
= make_compound_operation (op1
, SET
);
10402 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10403 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10404 && (code
== NE
|| code
== EQ
)
10405 && ((GET_MODE_SIZE (GET_MODE (op0
))
10406 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
10408 op0
= SUBREG_REG (op0
);
10409 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
10412 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10413 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10414 && (code
== NE
|| code
== EQ
)
10415 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10416 <= HOST_BITS_PER_WIDE_INT
)
10417 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
10418 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0
10419 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
10421 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10422 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0))
10423 op0
= SUBREG_REG (op0
), op1
= tem
;
10425 /* We now do the opposite procedure: Some machines don't have compare
10426 insns in all modes. If OP0's mode is an integer mode smaller than a
10427 word and we can't do a compare in that mode, see if there is a larger
10428 mode for which we can do the compare. There are a number of cases in
10429 which we can use the wider mode. */
10431 mode
= GET_MODE (op0
);
10432 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10433 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10434 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
10435 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10437 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10438 tmode
= GET_MODE_WIDER_MODE (tmode
))
10439 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
10441 /* If the only nonzero bits in OP0 and OP1 are those in the
10442 narrower mode and this is an equality or unsigned comparison,
10443 we can use the wider mode. Similarly for sign-extended
10444 values, in which case it is true for all comparisons. */
10445 if (((code
== EQ
|| code
== NE
10446 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
10447 && (nonzero_bits (op0
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0
10448 && (nonzero_bits (op1
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0)
10449 || ((num_sign_bit_copies (op0
, tmode
)
10450 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
10451 && (num_sign_bit_copies (op1
, tmode
)
10452 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
10454 op0
= gen_lowpart_for_combine (tmode
, op0
);
10455 op1
= gen_lowpart_for_combine (tmode
, op1
);
10459 /* If this is a test for negative, we can make an explicit
10460 test of the sign bit. */
10462 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10463 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10465 op0
= gen_binary (AND
, tmode
,
10466 gen_lowpart_for_combine (tmode
, op0
),
10467 GEN_INT ((HOST_WIDE_INT
) 1
10468 << (GET_MODE_BITSIZE (mode
) - 1)));
10469 code
= (code
== LT
) ? NE
: EQ
;
10474 #ifdef CANONICALIZE_COMPARISON
10475 /* If this machine only supports a subset of valid comparisons, see if we
10476 can convert an unsupported one into a supported one. */
10477 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10486 /* Return 1 if we know that X, a comparison operation, is not operating
10487 on a floating-point value or is EQ or NE, meaning that we can safely
10491 reversible_comparison_p (x
)
10494 if (TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
10496 || GET_CODE (x
) == NE
|| GET_CODE (x
) == EQ
)
10499 switch (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))))
10502 case MODE_PARTIAL_INT
:
10503 case MODE_COMPLEX_INT
:
10507 /* If the mode of the condition codes tells us that this is safe,
10508 we need look no further. */
10509 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x
, 0))))
10512 /* Otherwise try and find where the condition codes were last set and
10514 x
= get_last_value (XEXP (x
, 0));
10515 return (x
&& GET_CODE (x
) == COMPARE
10516 && ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0))));
10523 /* Utility function for following routine. Called when X is part of a value
10524 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10525 for each register mentioned. Similar to mention_regs in cse.c */
10528 update_table_tick (x
)
10531 register enum rtx_code code
= GET_CODE (x
);
10532 register char *fmt
= GET_RTX_FORMAT (code
);
10537 int regno
= REGNO (x
);
10538 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10539 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10541 for (i
= regno
; i
< endregno
; i
++)
10542 reg_last_set_table_tick
[i
] = label_tick
;
10547 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10548 /* Note that we can't have an "E" in values stored; see
10549 get_last_value_validate. */
10551 update_table_tick (XEXP (x
, i
));
10554 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10555 are saying that the register is clobbered and we no longer know its
10556 value. If INSN is zero, don't update reg_last_set; this is only permitted
10557 with VALUE also zero and is used to invalidate the register. */
10560 record_value_for_reg (reg
, insn
, value
)
10565 int regno
= REGNO (reg
);
10566 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10567 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
10570 /* If VALUE contains REG and we have a previous value for REG, substitute
10571 the previous value. */
10572 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10576 /* Set things up so get_last_value is allowed to see anything set up to
10578 subst_low_cuid
= INSN_CUID (insn
);
10579 tem
= get_last_value (reg
);
10582 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10585 /* For each register modified, show we don't know its value, that
10586 we don't know about its bitwise content, that its value has been
10587 updated, and that we don't know the location of the death of the
10589 for (i
= regno
; i
< endregno
; i
++)
10592 reg_last_set
[i
] = insn
;
10593 reg_last_set_value
[i
] = 0;
10594 reg_last_set_mode
[i
] = 0;
10595 reg_last_set_nonzero_bits
[i
] = 0;
10596 reg_last_set_sign_bit_copies
[i
] = 0;
10597 reg_last_death
[i
] = 0;
10600 /* Mark registers that are being referenced in this value. */
10602 update_table_tick (value
);
10604 /* Now update the status of each register being set.
10605 If someone is using this register in this block, set this register
10606 to invalid since we will get confused between the two lives in this
10607 basic block. This makes using this register always invalid. In cse, we
10608 scan the table to invalidate all entries using this register, but this
10609 is too much work for us. */
10611 for (i
= regno
; i
< endregno
; i
++)
10613 reg_last_set_label
[i
] = label_tick
;
10614 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
10615 reg_last_set_invalid
[i
] = 1;
10617 reg_last_set_invalid
[i
] = 0;
10620 /* The value being assigned might refer to X (like in "x++;"). In that
10621 case, we must replace it with (clobber (const_int 0)) to prevent
10623 if (value
&& ! get_last_value_validate (&value
, insn
,
10624 reg_last_set_label
[regno
], 0))
10626 value
= copy_rtx (value
);
10627 if (! get_last_value_validate (&value
, insn
,
10628 reg_last_set_label
[regno
], 1))
10632 /* For the main register being modified, update the value, the mode, the
10633 nonzero bits, and the number of sign bit copies. */
10635 reg_last_set_value
[regno
] = value
;
10639 subst_low_cuid
= INSN_CUID (insn
);
10640 reg_last_set_mode
[regno
] = GET_MODE (reg
);
10641 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
10642 reg_last_set_sign_bit_copies
[regno
]
10643 = num_sign_bit_copies (value
, GET_MODE (reg
));
10647 /* Used for communication between the following two routines. */
10648 static rtx record_dead_insn
;
10650 /* Called via note_stores from record_dead_and_set_regs to handle one
10651 SET or CLOBBER in an insn. */
10654 record_dead_and_set_regs_1 (dest
, setter
)
10657 if (GET_CODE (dest
) == SUBREG
)
10658 dest
= SUBREG_REG (dest
);
10660 if (GET_CODE (dest
) == REG
)
10662 /* If we are setting the whole register, we know its value. Otherwise
10663 show that we don't know the value. We can handle SUBREG in
10665 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
10666 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
10667 else if (GET_CODE (setter
) == SET
10668 && GET_CODE (SET_DEST (setter
)) == SUBREG
10669 && SUBREG_REG (SET_DEST (setter
)) == dest
10670 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
10671 && subreg_lowpart_p (SET_DEST (setter
)))
10672 record_value_for_reg (dest
, record_dead_insn
,
10673 gen_lowpart_for_combine (GET_MODE (dest
),
10674 SET_SRC (setter
)));
10676 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
10678 else if (GET_CODE (dest
) == MEM
10679 /* Ignore pushes, they clobber nothing. */
10680 && ! push_operand (dest
, GET_MODE (dest
)))
10681 mem_last_set
= INSN_CUID (record_dead_insn
);
10684 /* Update the records of when each REG was most recently set or killed
10685 for the things done by INSN. This is the last thing done in processing
10686 INSN in the combiner loop.
10688 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10689 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10690 and also the similar information mem_last_set (which insn most recently
10691 modified memory) and last_call_cuid (which insn was the most recent
10692 subroutine call). */
10695 record_dead_and_set_regs (insn
)
10701 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
10703 if (REG_NOTE_KIND (link
) == REG_DEAD
10704 && GET_CODE (XEXP (link
, 0)) == REG
)
10706 int regno
= REGNO (XEXP (link
, 0));
10708 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10709 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
10712 for (i
= regno
; i
< endregno
; i
++)
10713 reg_last_death
[i
] = insn
;
10715 else if (REG_NOTE_KIND (link
) == REG_INC
)
10716 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
10719 if (GET_CODE (insn
) == CALL_INSN
)
10721 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
10722 if (call_used_regs
[i
])
10724 reg_last_set_value
[i
] = 0;
10725 reg_last_set_mode
[i
] = 0;
10726 reg_last_set_nonzero_bits
[i
] = 0;
10727 reg_last_set_sign_bit_copies
[i
] = 0;
10728 reg_last_death
[i
] = 0;
10731 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
10734 record_dead_insn
= insn
;
10735 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
);
10738 /* Utility routine for the following function. Verify that all the registers
10739 mentioned in *LOC are valid when *LOC was part of a value set when
10740 label_tick == TICK. Return 0 if some are not.
10742 If REPLACE is non-zero, replace the invalid reference with
10743 (clobber (const_int 0)) and return 1. This replacement is useful because
10744 we often can get useful information about the form of a value (e.g., if
10745 it was produced by a shift that always produces -1 or 0) even though
10746 we don't know exactly what registers it was produced from. */
10749 get_last_value_validate (loc
, insn
, tick
, replace
)
10756 char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
10757 int len
= GET_RTX_LENGTH (GET_CODE (x
));
10760 if (GET_CODE (x
) == REG
)
10762 int regno
= REGNO (x
);
10763 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10764 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10767 for (j
= regno
; j
< endregno
; j
++)
10768 if (reg_last_set_invalid
[j
]
10769 /* If this is a pseudo-register that was only set once, it is
10771 || (! (regno
>= FIRST_PSEUDO_REGISTER
&& REG_N_SETS (regno
) == 1)
10772 && reg_last_set_label
[j
] > tick
))
10775 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10781 /* If this is a memory reference, make sure that there were
10782 no stores after it that might have clobbered the value. We don't
10783 have alias info, so we assume any store invalidates it. */
10784 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
10785 && INSN_CUID (insn
) <= mem_last_set
)
10788 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10792 for (i
= 0; i
< len
; i
++)
10794 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
10795 /* Don't bother with these. They shouldn't occur anyway. */
10799 /* If we haven't found a reason for it to be invalid, it is valid. */
10803 /* Get the last value assigned to X, if known. Some registers
10804 in the value may be replaced with (clobber (const_int 0)) if their value
10805 is known longer known reliably. */
10814 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10815 then convert it to the desired mode. If this is a paradoxical SUBREG,
10816 we cannot predict what values the "extra" bits might have. */
10817 if (GET_CODE (x
) == SUBREG
10818 && subreg_lowpart_p (x
)
10819 && (GET_MODE_SIZE (GET_MODE (x
))
10820 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
10821 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
10822 return gen_lowpart_for_combine (GET_MODE (x
), value
);
10824 if (GET_CODE (x
) != REG
)
10828 value
= reg_last_set_value
[regno
];
10830 /* If we don't have a value or if it isn't for this basic block,
10834 || (REG_N_SETS (regno
) != 1
10835 && reg_last_set_label
[regno
] != label_tick
))
10838 /* If the value was set in a later insn than the ones we are processing,
10839 we can't use it even if the register was only set once, but make a quick
10840 check to see if the previous insn set it to something. This is commonly
10841 the case when the same pseudo is used by repeated insns.
10843 This does not work if there exists an instruction which is temporarily
10844 not on the insn chain. */
10846 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
10850 /* We can not do anything useful in this case, because there is
10851 an instruction which is not on the insn chain. */
10852 if (subst_prev_insn
)
10855 /* Skip over USE insns. They are not useful here, and they may have
10856 been made by combine, in which case they do not have a INSN_CUID
10857 value. We can't use prev_real_insn, because that would incorrectly
10858 take us backwards across labels. Skip over BARRIERs also, since
10859 they could have been made by combine. If we see one, we must be
10860 optimizing dead code, so it doesn't matter what we do. */
10861 for (insn
= prev_nonnote_insn (subst_insn
);
10862 insn
&& ((GET_CODE (insn
) == INSN
10863 && GET_CODE (PATTERN (insn
)) == USE
)
10864 || GET_CODE (insn
) == BARRIER
10865 || INSN_CUID (insn
) >= subst_low_cuid
);
10866 insn
= prev_nonnote_insn (insn
))
10870 && (set
= single_set (insn
)) != 0
10871 && rtx_equal_p (SET_DEST (set
), x
))
10873 value
= SET_SRC (set
);
10875 /* Make sure that VALUE doesn't reference X. Replace any
10876 explicit references with a CLOBBER. If there are any remaining
10877 references (rare), don't use the value. */
10879 if (reg_mentioned_p (x
, value
))
10880 value
= replace_rtx (copy_rtx (value
), x
,
10881 gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
));
10883 if (reg_overlap_mentioned_p (x
, value
))
10890 /* If the value has all its registers valid, return it. */
10891 if (get_last_value_validate (&value
, reg_last_set
[regno
],
10892 reg_last_set_label
[regno
], 0))
10895 /* Otherwise, make a copy and replace any invalid register with
10896 (clobber (const_int 0)). If that fails for some reason, return 0. */
10898 value
= copy_rtx (value
);
10899 if (get_last_value_validate (&value
, reg_last_set
[regno
],
10900 reg_last_set_label
[regno
], 1))
10906 /* Return nonzero if expression X refers to a REG or to memory
10907 that is set in an instruction more recent than FROM_CUID. */
10910 use_crosses_set_p (x
, from_cuid
)
10914 register char *fmt
;
10916 register enum rtx_code code
= GET_CODE (x
);
10920 register int regno
= REGNO (x
);
10921 int endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10922 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10924 #ifdef PUSH_ROUNDING
10925 /* Don't allow uses of the stack pointer to be moved,
10926 because we don't know whether the move crosses a push insn. */
10927 if (regno
== STACK_POINTER_REGNUM
)
10930 for (;regno
< endreg
; regno
++)
10931 if (reg_last_set
[regno
]
10932 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
10937 if (code
== MEM
&& mem_last_set
> from_cuid
)
10940 fmt
= GET_RTX_FORMAT (code
);
10942 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10947 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10948 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
10951 else if (fmt
[i
] == 'e'
10952 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
10958 /* Define three variables used for communication between the following
10961 static int reg_dead_regno
, reg_dead_endregno
;
10962 static int reg_dead_flag
;
10964 /* Function called via note_stores from reg_dead_at_p.
10966 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10967 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10970 reg_dead_at_p_1 (dest
, x
)
10974 int regno
, endregno
;
10976 if (GET_CODE (dest
) != REG
)
10979 regno
= REGNO (dest
);
10980 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10981 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
10983 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
10984 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
10987 /* Return non-zero if REG is known to be dead at INSN.
10989 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10990 referencing REG, it is dead. If we hit a SET referencing REG, it is
10991 live. Otherwise, see if it is live or dead at the start of the basic
10992 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10993 must be assumed to be always live. */
10996 reg_dead_at_p (reg
, insn
)
11002 /* Set variables for reg_dead_at_p_1. */
11003 reg_dead_regno
= REGNO (reg
);
11004 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11005 ? HARD_REGNO_NREGS (reg_dead_regno
,
11011 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11012 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11014 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11015 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11019 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11020 beginning of function. */
11021 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11022 insn
= prev_nonnote_insn (insn
))
11024 note_stores (PATTERN (insn
), reg_dead_at_p_1
);
11026 return reg_dead_flag
== 1 ? 1 : 0;
11028 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11032 /* Get the basic block number that we were in. */
11037 for (block
= 0; block
< n_basic_blocks
; block
++)
11038 if (insn
== BLOCK_HEAD (block
))
11041 if (block
== n_basic_blocks
)
11045 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11046 if (REGNO_REG_SET_P (basic_block_live_at_start
[block
], i
))
11052 /* Note hard registers in X that are used. This code is similar to
11053 that in flow.c, but much simpler since we don't care about pseudos. */
11056 mark_used_regs_combine (x
)
11059 register RTX_CODE code
= GET_CODE (x
);
11060 register int regno
;
11072 case ADDR_DIFF_VEC
:
11075 /* CC0 must die in the insn after it is set, so we don't need to take
11076 special note of it here. */
11082 /* If we are clobbering a MEM, mark any hard registers inside the
11083 address as used. */
11084 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11085 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11090 /* A hard reg in a wide mode may really be multiple registers.
11091 If so, mark all of them just like the first. */
11092 if (regno
< FIRST_PSEUDO_REGISTER
)
11094 /* None of this applies to the stack, frame or arg pointers */
11095 if (regno
== STACK_POINTER_REGNUM
11096 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11097 || regno
== HARD_FRAME_POINTER_REGNUM
11099 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11100 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11102 || regno
== FRAME_POINTER_REGNUM
)
11105 i
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11107 SET_HARD_REG_BIT (newpat_used_regs
, regno
+ i
);
11113 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11115 register rtx testreg
= SET_DEST (x
);
11117 while (GET_CODE (testreg
) == SUBREG
11118 || GET_CODE (testreg
) == ZERO_EXTRACT
11119 || GET_CODE (testreg
) == SIGN_EXTRACT
11120 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11121 testreg
= XEXP (testreg
, 0);
11123 if (GET_CODE (testreg
) == MEM
)
11124 mark_used_regs_combine (XEXP (testreg
, 0));
11126 mark_used_regs_combine (SET_SRC (x
));
11134 /* Recursively scan the operands of this expression. */
11137 register char *fmt
= GET_RTX_FORMAT (code
);
11139 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11142 mark_used_regs_combine (XEXP (x
, i
));
11143 else if (fmt
[i
] == 'E')
11147 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11148 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11155 /* Remove register number REGNO from the dead registers list of INSN.
11157 Return the note used to record the death, if there was one. */
11160 remove_death (regno
, insn
)
11164 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11168 REG_N_DEATHS (regno
)--;
11169 remove_note (insn
, note
);
11175 /* For each register (hardware or pseudo) used within expression X, if its
11176 death is in an instruction with cuid between FROM_CUID (inclusive) and
11177 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11178 list headed by PNOTES.
11180 That said, don't move registers killed by maybe_kill_insn.
11182 This is done when X is being merged by combination into TO_INSN. These
11183 notes will then be distributed as needed. */
11186 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11188 rtx maybe_kill_insn
;
11193 register char *fmt
;
11194 register int len
, i
;
11195 register enum rtx_code code
= GET_CODE (x
);
11199 register int regno
= REGNO (x
);
11200 register rtx where_dead
= reg_last_death
[regno
];
11201 register rtx before_dead
, after_dead
;
11203 /* Don't move the register if it gets killed in between from and to */
11204 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11205 && !reg_referenced_p (x
, maybe_kill_insn
))
11208 /* WHERE_DEAD could be a USE insn made by combine, so first we
11209 make sure that we have insns with valid INSN_CUID values. */
11210 before_dead
= where_dead
;
11211 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11212 before_dead
= PREV_INSN (before_dead
);
11213 after_dead
= where_dead
;
11214 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11215 after_dead
= NEXT_INSN (after_dead
);
11217 if (before_dead
&& after_dead
11218 && INSN_CUID (before_dead
) >= from_cuid
11219 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11220 || (where_dead
!= after_dead
11221 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11223 rtx note
= remove_death (regno
, where_dead
);
11225 /* It is possible for the call above to return 0. This can occur
11226 when reg_last_death points to I2 or I1 that we combined with.
11227 In that case make a new note.
11229 We must also check for the case where X is a hard register
11230 and NOTE is a death note for a range of hard registers
11231 including X. In that case, we must put REG_DEAD notes for
11232 the remaining registers in place of NOTE. */
11234 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11235 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11236 > GET_MODE_SIZE (GET_MODE (x
))))
11238 int deadregno
= REGNO (XEXP (note
, 0));
11240 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11241 GET_MODE (XEXP (note
, 0))));
11242 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11245 for (i
= deadregno
; i
< deadend
; i
++)
11246 if (i
< regno
|| i
>= ourend
)
11247 REG_NOTES (where_dead
)
11248 = gen_rtx_EXPR_LIST (REG_DEAD
,
11249 gen_rtx_REG (reg_raw_mode
[i
], i
),
11250 REG_NOTES (where_dead
));
11252 /* If we didn't find any note, or if we found a REG_DEAD note that
11253 covers only part of the given reg, and we have a multi-reg hard
11254 register, then to be safe we must check for REG_DEAD notes
11255 for each register other than the first. They could have
11256 their own REG_DEAD notes lying around. */
11257 else if ((note
== 0
11259 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11260 < GET_MODE_SIZE (GET_MODE (x
)))))
11261 && regno
< FIRST_PSEUDO_REGISTER
11262 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11264 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11269 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11273 for (i
= regno
+ offset
; i
< ourend
; i
++)
11274 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11275 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11278 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11280 XEXP (note
, 1) = *pnotes
;
11284 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11286 REG_N_DEATHS (regno
)++;
11292 else if (GET_CODE (x
) == SET
)
11294 rtx dest
= SET_DEST (x
);
11296 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11298 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11299 that accesses one word of a multi-word item, some
11300 piece of everything register in the expression is used by
11301 this insn, so remove any old death. */
11303 if (GET_CODE (dest
) == ZERO_EXTRACT
11304 || GET_CODE (dest
) == STRICT_LOW_PART
11305 || (GET_CODE (dest
) == SUBREG
11306 && (((GET_MODE_SIZE (GET_MODE (dest
))
11307 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11308 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11309 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11311 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11315 /* If this is some other SUBREG, we know it replaces the entire
11316 value, so use that as the destination. */
11317 if (GET_CODE (dest
) == SUBREG
)
11318 dest
= SUBREG_REG (dest
);
11320 /* If this is a MEM, adjust deaths of anything used in the address.
11321 For a REG (the only other possibility), the entire value is
11322 being replaced so the old value is not used in this insn. */
11324 if (GET_CODE (dest
) == MEM
)
11325 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11330 else if (GET_CODE (x
) == CLOBBER
)
11333 len
= GET_RTX_LENGTH (code
);
11334 fmt
= GET_RTX_FORMAT (code
);
11336 for (i
= 0; i
< len
; i
++)
11341 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11342 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11345 else if (fmt
[i
] == 'e')
11346 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11350 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11351 pattern of an insn. X must be a REG. */
11354 reg_bitfield_target_p (x
, body
)
11360 if (GET_CODE (body
) == SET
)
11362 rtx dest
= SET_DEST (body
);
11364 int regno
, tregno
, endregno
, endtregno
;
11366 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11367 target
= XEXP (dest
, 0);
11368 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11369 target
= SUBREG_REG (XEXP (dest
, 0));
11373 if (GET_CODE (target
) == SUBREG
)
11374 target
= SUBREG_REG (target
);
11376 if (GET_CODE (target
) != REG
)
11379 tregno
= REGNO (target
), regno
= REGNO (x
);
11380 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11381 return target
== x
;
11383 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
11384 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11386 return endregno
> tregno
&& regno
< endtregno
;
11389 else if (GET_CODE (body
) == PARALLEL
)
11390 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11391 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11397 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11398 as appropriate. I3 and I2 are the insns resulting from the combination
11399 insns including FROM (I2 may be zero).
11401 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11402 not need REG_DEAD notes because they are being substituted for. This
11403 saves searching in the most common cases.
11405 Each note in the list is either ignored or placed on some insns, depending
11406 on the type of note. */
11409 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
11413 rtx elim_i2
, elim_i1
;
11415 rtx note
, next_note
;
11418 for (note
= notes
; note
; note
= next_note
)
11420 rtx place
= 0, place2
= 0;
11422 /* If this NOTE references a pseudo register, ensure it references
11423 the latest copy of that register. */
11424 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
11425 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11426 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11428 next_note
= XEXP (note
, 1);
11429 switch (REG_NOTE_KIND (note
))
11432 case REG_EXEC_COUNT
:
11433 /* Doesn't matter much where we put this, as long as it's somewhere.
11434 It is preferable to keep these notes on branches, which is most
11435 likely to be i3. */
11440 /* Any clobbers for i3 may still exist, and so we must process
11441 REG_UNUSED notes from that insn.
11443 Any clobbers from i2 or i1 can only exist if they were added by
11444 recog_for_combine. In that case, recog_for_combine created the
11445 necessary REG_UNUSED notes. Trying to keep any original
11446 REG_UNUSED notes from these insns can cause incorrect output
11447 if it is for the same register as the original i3 dest.
11448 In that case, we will notice that the register is set in i3,
11449 and then add a REG_UNUSED note for the destination of i3, which
11450 is wrong. However, it is possible to have REG_UNUSED notes from
11451 i2 or i1 for register which were both used and clobbered, so
11452 we keep notes from i2 or i1 if they will turn into REG_DEAD
11455 /* If this register is set or clobbered in I3, put the note there
11456 unless there is one already. */
11457 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11459 if (from_insn
!= i3
)
11462 if (! (GET_CODE (XEXP (note
, 0)) == REG
11463 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11464 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11467 /* Otherwise, if this register is used by I3, then this register
11468 now dies here, so we must put a REG_DEAD note here unless there
11470 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11471 && ! (GET_CODE (XEXP (note
, 0)) == REG
11472 ? find_regno_note (i3
, REG_DEAD
, REGNO (XEXP (note
, 0)))
11473 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11475 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11484 /* These notes say something about results of an insn. We can
11485 only support them if they used to be on I3 in which case they
11486 remain on I3. Otherwise they are ignored.
11488 If the note refers to an expression that is not a constant, we
11489 must also ignore the note since we cannot tell whether the
11490 equivalence is still true. It might be possible to do
11491 slightly better than this (we only have a problem if I2DEST
11492 or I1DEST is present in the expression), but it doesn't
11493 seem worth the trouble. */
11495 if (from_insn
== i3
11496 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11501 case REG_NO_CONFLICT
:
11503 /* These notes say something about how a register is used. They must
11504 be present on any use of the register in I2 or I3. */
11505 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11508 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11518 /* It is too much trouble to try to see if this note is still
11519 correct in all situations. It is better to simply delete it. */
11523 /* If the insn previously containing this note still exists,
11524 put it back where it was. Otherwise move it to the previous
11525 insn. Adjust the corresponding REG_LIBCALL note. */
11526 if (GET_CODE (from_insn
) != NOTE
)
11530 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
11531 place
= prev_real_insn (from_insn
);
11533 XEXP (tem
, 0) = place
;
11538 /* This is handled similarly to REG_RETVAL. */
11539 if (GET_CODE (from_insn
) != NOTE
)
11543 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
11544 place
= next_real_insn (from_insn
);
11546 XEXP (tem
, 0) = place
;
11551 /* If the register is used as an input in I3, it dies there.
11552 Similarly for I2, if it is non-zero and adjacent to I3.
11554 If the register is not used as an input in either I3 or I2
11555 and it is not one of the registers we were supposed to eliminate,
11556 there are two possibilities. We might have a non-adjacent I2
11557 or we might have somehow eliminated an additional register
11558 from a computation. For example, we might have had A & B where
11559 we discover that B will always be zero. In this case we will
11560 eliminate the reference to A.
11562 In both cases, we must search to see if we can find a previous
11563 use of A and put the death note there. */
11566 && GET_CODE (from_insn
) == CALL_INSN
11567 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
11569 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
11571 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
11572 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11575 if (XEXP (note
, 0) == elim_i2
|| XEXP (note
, 0) == elim_i1
)
11578 /* If the register is used in both I2 and I3 and it dies in I3,
11579 we might have added another reference to it. If reg_n_refs
11580 was 2, bump it to 3. This has to be correct since the
11581 register must have been set somewhere. The reason this is
11582 done is because local-alloc.c treats 2 references as a
11585 if (place
== i3
&& i2
!= 0 && GET_CODE (XEXP (note
, 0)) == REG
11586 && REG_N_REFS (REGNO (XEXP (note
, 0)))== 2
11587 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11588 REG_N_REFS (REGNO (XEXP (note
, 0))) = 3;
11592 for (tem
= prev_nonnote_insn (i3
);
11594 && (GET_CODE (tem
) == INSN
|| GET_CODE (tem
) == CALL_INSN
);
11595 tem
= prev_nonnote_insn (tem
))
11597 /* If the register is being set at TEM, see if that is all
11598 TEM is doing. If so, delete TEM. Otherwise, make this
11599 into a REG_UNUSED note instead. */
11600 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
11602 rtx set
= single_set (tem
);
11603 rtx inner_dest
= 0;
11605 rtx cc0_setter
= NULL_RTX
;
11609 for (inner_dest
= SET_DEST (set
);
11610 GET_CODE (inner_dest
) == STRICT_LOW_PART
11611 || GET_CODE (inner_dest
) == SUBREG
11612 || GET_CODE (inner_dest
) == ZERO_EXTRACT
;
11613 inner_dest
= XEXP (inner_dest
, 0))
11616 /* Verify that it was the set, and not a clobber that
11617 modified the register.
11619 CC0 targets must be careful to maintain setter/user
11620 pairs. If we cannot delete the setter due to side
11621 effects, mark the user with an UNUSED note instead
11624 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
11625 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
11627 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
11628 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
11629 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
11633 /* Move the notes and links of TEM elsewhere.
11634 This might delete other dead insns recursively.
11635 First set the pattern to something that won't use
11638 PATTERN (tem
) = pc_rtx
;
11640 distribute_notes (REG_NOTES (tem
), tem
, tem
,
11641 NULL_RTX
, NULL_RTX
, NULL_RTX
);
11642 distribute_links (LOG_LINKS (tem
));
11644 PUT_CODE (tem
, NOTE
);
11645 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
11646 NOTE_SOURCE_FILE (tem
) = 0;
11649 /* Delete the setter too. */
11652 PATTERN (cc0_setter
) = pc_rtx
;
11654 distribute_notes (REG_NOTES (cc0_setter
),
11655 cc0_setter
, cc0_setter
,
11656 NULL_RTX
, NULL_RTX
, NULL_RTX
);
11657 distribute_links (LOG_LINKS (cc0_setter
));
11659 PUT_CODE (cc0_setter
, NOTE
);
11660 NOTE_LINE_NUMBER (cc0_setter
) = NOTE_INSN_DELETED
;
11661 NOTE_SOURCE_FILE (cc0_setter
) = 0;
11665 /* If the register is both set and used here, put the
11666 REG_DEAD note here, but place a REG_UNUSED note
11667 here too unless there already is one. */
11668 else if (reg_referenced_p (XEXP (note
, 0),
11673 if (! find_regno_note (tem
, REG_UNUSED
,
11674 REGNO (XEXP (note
, 0))))
11676 = gen_rtx_EXPR_LIST (REG_UNUSED
,
11682 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
11684 /* If there isn't already a REG_UNUSED note, put one
11686 if (! find_regno_note (tem
, REG_UNUSED
,
11687 REGNO (XEXP (note
, 0))))
11692 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
11693 || (GET_CODE (tem
) == CALL_INSN
11694 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
11698 /* If we are doing a 3->2 combination, and we have a
11699 register which formerly died in i3 and was not used
11700 by i2, which now no longer dies in i3 and is used in
11701 i2 but does not die in i2, and place is between i2
11702 and i3, then we may need to move a link from place to
11704 if (i2
&& INSN_UID (place
) <= max_uid_cuid
11705 && INSN_CUID (place
) > INSN_CUID (i2
)
11706 && from_insn
&& INSN_CUID (from_insn
) > INSN_CUID (i2
)
11707 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11709 rtx links
= LOG_LINKS (place
);
11710 LOG_LINKS (place
) = 0;
11711 distribute_links (links
);
11717 /* If we haven't found an insn for the death note and it
11718 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11719 insert a USE insn for the register at that label and
11720 put the death node there. This prevents problems with
11721 call-state tracking in caller-save.c. */
11722 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0 && tem
!= 0)
11725 = emit_insn_after (gen_rtx_USE (VOIDmode
, XEXP (note
, 0)),
11728 /* If this insn was emitted between blocks, then update
11729 BLOCK_HEAD of the current block to include it. */
11730 if (BLOCK_END (this_basic_block
- 1) == tem
)
11731 BLOCK_HEAD (this_basic_block
) = place
;
11735 /* If the register is set or already dead at PLACE, we needn't do
11736 anything with this note if it is still a REG_DEAD note.
11737 We can here if it is set at all, not if is it totally replace,
11738 which is what `dead_or_set_p' checks, so also check for it being
11742 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
11744 int regno
= REGNO (XEXP (note
, 0));
11746 if (dead_or_set_p (place
, XEXP (note
, 0))
11747 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
11749 /* Unless the register previously died in PLACE, clear
11750 reg_last_death. [I no longer understand why this is
11752 if (reg_last_death
[regno
] != place
)
11753 reg_last_death
[regno
] = 0;
11757 reg_last_death
[regno
] = place
;
11759 /* If this is a death note for a hard reg that is occupying
11760 multiple registers, ensure that we are still using all
11761 parts of the object. If we find a piece of the object
11762 that is unused, we must add a USE for that piece before
11763 PLACE and put the appropriate REG_DEAD note on it.
11765 An alternative would be to put a REG_UNUSED for the pieces
11766 on the insn that set the register, but that can't be done if
11767 it is not in the same block. It is simpler, though less
11768 efficient, to add the USE insns. */
11770 if (place
&& regno
< FIRST_PSEUDO_REGISTER
11771 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
11774 = regno
+ HARD_REGNO_NREGS (regno
,
11775 GET_MODE (XEXP (note
, 0)));
11779 for (i
= regno
; i
< endregno
; i
++)
11780 if (! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
11781 && ! find_regno_fusage (place
, USE
, i
))
11783 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
11786 /* See if we already placed a USE note for this
11787 register in front of PLACE. */
11789 GET_CODE (PREV_INSN (p
)) == INSN
11790 && GET_CODE (PATTERN (PREV_INSN (p
))) == USE
;
11792 if (rtx_equal_p (piece
,
11793 XEXP (PATTERN (PREV_INSN (p
)), 0)))
11802 = emit_insn_before (gen_rtx_USE (VOIDmode
,
11805 REG_NOTES (use_insn
)
11806 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
,
11807 REG_NOTES (use_insn
));
11813 /* Check for the case where the register dying partially
11814 overlaps the register set by this insn. */
11816 for (i
= regno
; i
< endregno
; i
++)
11817 if (dead_or_set_regno_p (place
, i
))
11825 /* Put only REG_DEAD notes for pieces that are
11826 still used and that are not already dead or set. */
11828 for (i
= regno
; i
< endregno
; i
++)
11830 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
11832 if ((reg_referenced_p (piece
, PATTERN (place
))
11833 || (GET_CODE (place
) == CALL_INSN
11834 && find_reg_fusage (place
, USE
, piece
)))
11835 && ! dead_or_set_p (place
, piece
)
11836 && ! reg_bitfield_target_p (piece
,
11839 = gen_rtx_EXPR_LIST (REG_DEAD
,
11840 piece
, REG_NOTES (place
));
11850 /* Any other notes should not be present at this point in the
11857 XEXP (note
, 1) = REG_NOTES (place
);
11858 REG_NOTES (place
) = note
;
11860 else if ((REG_NOTE_KIND (note
) == REG_DEAD
11861 || REG_NOTE_KIND (note
) == REG_UNUSED
)
11862 && GET_CODE (XEXP (note
, 0)) == REG
)
11863 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
11867 if ((REG_NOTE_KIND (note
) == REG_DEAD
11868 || REG_NOTE_KIND (note
) == REG_UNUSED
)
11869 && GET_CODE (XEXP (note
, 0)) == REG
)
11870 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
11872 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
11873 REG_NOTE_KIND (note
),
11875 REG_NOTES (place2
));
11880 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11881 I3, I2, and I1 to new locations. This is also called in one case to
11882 add a link pointing at I3 when I3's destination is changed. */
11885 distribute_links (links
)
11888 rtx link
, next_link
;
11890 for (link
= links
; link
; link
= next_link
)
11896 next_link
= XEXP (link
, 1);
11898 /* If the insn that this link points to is a NOTE or isn't a single
11899 set, ignore it. In the latter case, it isn't clear what we
11900 can do other than ignore the link, since we can't tell which
11901 register it was for. Such links wouldn't be used by combine
11904 It is not possible for the destination of the target of the link to
11905 have been changed by combine. The only potential of this is if we
11906 replace I3, I2, and I1 by I3 and I2. But in that case the
11907 destination of I2 also remains unchanged. */
11909 if (GET_CODE (XEXP (link
, 0)) == NOTE
11910 || (set
= single_set (XEXP (link
, 0))) == 0)
11913 reg
= SET_DEST (set
);
11914 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
11915 || GET_CODE (reg
) == SIGN_EXTRACT
11916 || GET_CODE (reg
) == STRICT_LOW_PART
)
11917 reg
= XEXP (reg
, 0);
11919 /* A LOG_LINK is defined as being placed on the first insn that uses
11920 a register and points to the insn that sets the register. Start
11921 searching at the next insn after the target of the link and stop
11922 when we reach a set of the register or the end of the basic block.
11924 Note that this correctly handles the link that used to point from
11925 I3 to I2. Also note that not much searching is typically done here
11926 since most links don't point very far away. */
11928 for (insn
= NEXT_INSN (XEXP (link
, 0));
11929 (insn
&& (this_basic_block
== n_basic_blocks
- 1
11930 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
11931 insn
= NEXT_INSN (insn
))
11932 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
11933 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
11935 if (reg_referenced_p (reg
, PATTERN (insn
)))
11939 else if (GET_CODE (insn
) == CALL_INSN
11940 && find_reg_fusage (insn
, USE
, reg
))
11946 /* If we found a place to put the link, place it there unless there
11947 is already a link to the same insn as LINK at that point. */
11953 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
11954 if (XEXP (link2
, 0) == XEXP (link
, 0))
11959 XEXP (link
, 1) = LOG_LINKS (place
);
11960 LOG_LINKS (place
) = link
;
11962 /* Set added_links_insn to the earliest insn we added a
11964 if (added_links_insn
== 0
11965 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
11966 added_links_insn
= place
;
11972 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
11978 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
11979 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
11980 insn
= NEXT_INSN (insn
);
11982 if (INSN_UID (insn
) > max_uid_cuid
)
11985 return INSN_CUID (insn
);
11989 dump_combine_stats (file
)
11994 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11995 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
11999 dump_combine_total_stats (file
)
12004 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12005 total_attempts
, total_merges
, total_extras
, total_successes
);