1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx
*reg_last_death
;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx
*reg_last_set
;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set
;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid
;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn
;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn
;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid
;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs
;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn
;
195 /* Basic block in which we are performing combines. */
196 static basic_block this_basic_block
;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks
;
202 static int need_refresh
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; int i
;} old_contents
;
318 union {rtx
*r
; int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST
PARAMS ((rtx
*, rtx
));
342 static void do_SUBST_INT
PARAMS ((int *, int));
343 static void init_reg_last_arrays
PARAMS ((void));
344 static void setup_incoming_promotions
PARAMS ((void));
345 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
346 static int cant_combine_insn_p
PARAMS ((rtx
));
347 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
348 static int sets_function_arg_p
PARAMS ((rtx
));
349 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
350 static int contains_muldiv
PARAMS ((rtx
));
351 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
352 static void undo_all
PARAMS ((void));
353 static void undo_commit
PARAMS ((void));
354 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
355 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
356 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
357 static rtx simplify_if_then_else
PARAMS ((rtx
));
358 static rtx simplify_set
PARAMS ((rtx
));
359 static rtx simplify_logical
PARAMS ((rtx
, int));
360 static rtx expand_compound_operation
PARAMS ((rtx
));
361 static rtx expand_field_assignment
PARAMS ((rtx
));
362 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
363 rtx
, unsigned HOST_WIDE_INT
, int,
365 static rtx extract_left_shift
PARAMS ((rtx
, int));
366 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
367 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
368 unsigned HOST_WIDE_INT
*));
369 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
370 unsigned HOST_WIDE_INT
, rtx
, int));
371 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
372 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
373 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
374 static rtx make_field_assignment
PARAMS ((rtx
));
375 static rtx apply_distributive_law
PARAMS ((rtx
));
376 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
377 unsigned HOST_WIDE_INT
));
378 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
379 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
380 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
381 enum rtx_code
, HOST_WIDE_INT
,
382 enum machine_mode
, int *));
383 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
385 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
386 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
387 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
389 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
390 static void update_table_tick
PARAMS ((rtx
));
391 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
392 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
393 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
394 static void record_dead_and_set_regs
PARAMS ((rtx
));
395 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
396 static rtx get_last_value
PARAMS ((rtx
));
397 static int use_crosses_set_p
PARAMS ((rtx
, int));
398 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
399 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
400 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
401 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
402 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
403 static void distribute_links
PARAMS ((rtx
));
404 static void mark_used_regs_combine
PARAMS ((rtx
));
405 static int insn_cuid
PARAMS ((rtx
));
406 static void record_promoted_value
PARAMS ((rtx
, rtx
));
407 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
408 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
410 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
411 insn. The substitution can be undone by undo_all. If INTO is already
412 set to NEWVAL, do not record this change. Because computing NEWVAL might
413 also call SUBST, we have to compute it before we put anything into
417 do_SUBST (into
, newval
)
423 if (oldval
== newval
)
426 /* We'd like to catch as many invalid transformations here as
427 possible. Unfortunately, there are way too many mode changes
428 that are perfectly valid, so we'd waste too much effort for
429 little gain doing the checks here. Focus on catching invalid
430 transformations involving integer constants. */
431 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
432 && GET_CODE (newval
) == CONST_INT
)
434 /* Sanity check that we're replacing oldval with a CONST_INT
435 that is a valid sign-extension for the original mode. */
436 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
440 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
441 CONST_INT is not valid, because after the replacement, the
442 original mode would be gone. Unfortunately, we can't tell
443 when do_SUBST is called to replace the operand thereof, so we
444 perform this test on oldval instead, checking whether an
445 invalid replacement took place before we got here. */
446 if ((GET_CODE (oldval
) == SUBREG
447 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
448 || (GET_CODE (oldval
) == ZERO_EXTEND
449 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
454 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
456 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
460 buf
->old_contents
.r
= oldval
;
463 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
466 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
468 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
469 for the value of a HOST_WIDE_INT value (including CONST_INT) is
473 do_SUBST_INT (into
, newval
)
479 if (oldval
== newval
)
483 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
485 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
489 buf
->old_contents
.i
= oldval
;
492 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
495 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
497 /* Main entry point for combiner. F is the first insn of the function.
498 NREGS is the first unused pseudo-reg number.
500 Return nonzero if the combiner has turned an indirect jump
501 instruction into a direct jump. */
503 combine_instructions (f
, nregs
)
512 rtx links
, nextlinks
;
514 int new_direct_jump_p
= 0;
516 combine_attempts
= 0;
519 combine_successes
= 0;
521 combine_max_regno
= nregs
;
523 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
524 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
526 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
528 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
530 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
531 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
532 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
533 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
535 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
536 reg_last_set_nonzero_bits
537 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
538 reg_last_set_sign_bit_copies
539 = (char *) xmalloc (nregs
* sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
548 if (INSN_UID (insn
) > i
)
551 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
554 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid
= 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 /* We need to initialize it here, because record_dead_and_set_regs may call
576 subst_prev_insn
= NULL_RTX
;
578 setup_incoming_promotions ();
580 refresh_blocks
= sbitmap_alloc (last_basic_block
);
581 sbitmap_zero (refresh_blocks
);
584 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
586 uid_cuid
[INSN_UID (insn
)] = ++i
;
592 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
594 record_dead_and_set_regs (insn
);
597 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
598 if (REG_NOTE_KIND (links
) == REG_INC
)
599 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
604 if (GET_CODE (insn
) == CODE_LABEL
)
608 nonzero_sign_valid
= 1;
610 /* Now scan all the insns in forward order. */
615 init_reg_last_arrays ();
616 setup_incoming_promotions ();
618 FOR_EACH_BB (this_basic_block
)
620 for (insn
= this_basic_block
->head
;
621 insn
!= NEXT_INSN (this_basic_block
->end
);
622 insn
= next
? next
: NEXT_INSN (insn
))
626 if (GET_CODE (insn
) == CODE_LABEL
)
629 else if (INSN_P (insn
))
631 /* See if we know about function return values before this
632 insn based upon SUBREG flags. */
633 check_promoted_subreg (insn
, PATTERN (insn
));
635 /* Try this insn with each insn it links back to. */
637 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
638 if ((next
= try_combine (insn
, XEXP (links
, 0),
639 NULL_RTX
, &new_direct_jump_p
)) != 0)
642 /* Try each sequence of three linked insns ending with this one. */
644 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
646 rtx link
= XEXP (links
, 0);
648 /* If the linked insn has been replaced by a note, then there
649 is no point in pursuing this chain any further. */
650 if (GET_CODE (link
) == NOTE
)
653 for (nextlinks
= LOG_LINKS (link
);
655 nextlinks
= XEXP (nextlinks
, 1))
656 if ((next
= try_combine (insn
, link
,
658 &new_direct_jump_p
)) != 0)
663 /* Try to combine a jump insn that uses CC0
664 with a preceding insn that sets CC0, and maybe with its
665 logical predecessor as well.
666 This is how we make decrement-and-branch insns.
667 We need this special code because data flow connections
668 via CC0 do not get entered in LOG_LINKS. */
670 if (GET_CODE (insn
) == JUMP_INSN
671 && (prev
= prev_nonnote_insn (insn
)) != 0
672 && GET_CODE (prev
) == INSN
673 && sets_cc0_p (PATTERN (prev
)))
675 if ((next
= try_combine (insn
, prev
,
676 NULL_RTX
, &new_direct_jump_p
)) != 0)
679 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
680 nextlinks
= XEXP (nextlinks
, 1))
681 if ((next
= try_combine (insn
, prev
,
683 &new_direct_jump_p
)) != 0)
687 /* Do the same for an insn that explicitly references CC0. */
688 if (GET_CODE (insn
) == INSN
689 && (prev
= prev_nonnote_insn (insn
)) != 0
690 && GET_CODE (prev
) == INSN
691 && sets_cc0_p (PATTERN (prev
))
692 && GET_CODE (PATTERN (insn
)) == SET
693 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
695 if ((next
= try_combine (insn
, prev
,
696 NULL_RTX
, &new_direct_jump_p
)) != 0)
699 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
700 nextlinks
= XEXP (nextlinks
, 1))
701 if ((next
= try_combine (insn
, prev
,
703 &new_direct_jump_p
)) != 0)
707 /* Finally, see if any of the insns that this insn links to
708 explicitly references CC0. If so, try this insn, that insn,
709 and its predecessor if it sets CC0. */
710 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
711 if (GET_CODE (XEXP (links
, 0)) == INSN
712 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
713 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
714 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
715 && GET_CODE (prev
) == INSN
716 && sets_cc0_p (PATTERN (prev
))
717 && (next
= try_combine (insn
, XEXP (links
, 0),
718 prev
, &new_direct_jump_p
)) != 0)
722 /* Try combining an insn with two different insns whose results it
724 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
725 for (nextlinks
= XEXP (links
, 1); nextlinks
;
726 nextlinks
= XEXP (nextlinks
, 1))
727 if ((next
= try_combine (insn
, XEXP (links
, 0),
729 &new_direct_jump_p
)) != 0)
732 if (GET_CODE (insn
) != NOTE
)
733 record_dead_and_set_regs (insn
);
742 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
743 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
744 new_direct_jump_p
|= purge_all_dead_edges (0);
745 delete_noop_moves (f
);
747 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
748 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
749 | PROP_KILL_DEAD_CODE
);
752 sbitmap_free (refresh_blocks
);
753 free (reg_nonzero_bits
);
754 free (reg_sign_bit_copies
);
755 free (reg_last_death
);
757 free (reg_last_set_value
);
758 free (reg_last_set_table_tick
);
759 free (reg_last_set_label
);
760 free (reg_last_set_invalid
);
761 free (reg_last_set_mode
);
762 free (reg_last_set_nonzero_bits
);
763 free (reg_last_set_sign_bit_copies
);
767 struct undo
*undo
, *next
;
768 for (undo
= undobuf
.frees
; undo
; undo
= next
)
776 total_attempts
+= combine_attempts
;
777 total_merges
+= combine_merges
;
778 total_extras
+= combine_extras
;
779 total_successes
+= combine_successes
;
781 nonzero_sign_valid
= 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p
;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs
= combine_max_regno
;
796 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
797 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
798 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
799 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
800 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
801 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
802 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
803 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
804 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode
;
817 rtx first
= get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
827 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
830 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode
, const0_rtx
)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x
, set
, data
)
853 void *data ATTRIBUTE_UNUSED
;
857 if (GET_CODE (x
) == REG
858 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
862 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
864 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
866 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
867 reg_sign_bit_copies
[REGNO (x
)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set
= expand_field_assignment (set
);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set
) == x
879 || (GET_CODE (SET_DEST (set
)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
882 && SUBREG_REG (SET_DEST (set
)) == x
))
884 rtx src
= SET_SRC (set
);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
897 && GET_CODE (src
) == CONST_INT
899 && 0 != (INTVAL (src
)
901 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
902 src
= GEN_INT (INTVAL (src
)
903 | ((HOST_WIDE_INT
) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x
))));
907 /* Don't call nonzero_bits if it cannot change anything. */
908 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
909 reg_nonzero_bits
[REGNO (x
)]
910 |= nonzero_bits (src
, nonzero_bits_mode
);
911 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
912 if (reg_sign_bit_copies
[REGNO (x
)] == 0
913 || reg_sign_bit_copies
[REGNO (x
)] > num
)
914 reg_sign_bit_copies
[REGNO (x
)] = num
;
918 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
919 reg_sign_bit_copies
[REGNO (x
)] = 1;
924 /* See if INSN can be combined into I3. PRED and SUCC are optionally
925 insns that were previously combined into I3 or that will be combined
926 into the merger of INSN and I3.
928 Return 0 if the combination is not allowed for any reason.
930 If the combination is allowed, *PDEST will be set to the single
931 destination of INSN and *PSRC to the single source, and this function
935 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
938 rtx pred ATTRIBUTE_UNUSED
;
943 rtx set
= 0, src
, dest
;
948 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
949 && next_active_insn (succ
) == i3
)
950 : next_active_insn (insn
) == i3
);
952 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
953 or a PARALLEL consisting of such a SET and CLOBBERs.
955 If INSN has CLOBBER parallel parts, ignore them for our processing.
956 By definition, these happen during the execution of the insn. When it
957 is merged with another insn, all bets are off. If they are, in fact,
958 needed and aren't also supplied in I3, they may be added by
959 recog_for_combine. Otherwise, it won't match.
961 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
964 Get the source and destination of INSN. If more than one, can't
967 if (GET_CODE (PATTERN (insn
)) == SET
)
968 set
= PATTERN (insn
);
969 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
970 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
972 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
974 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
976 switch (GET_CODE (elt
))
978 /* This is important to combine floating point insns
981 /* Combining an isolated USE doesn't make sense.
982 We depend here on combinable_i3pat to reject them. */
983 /* The code below this loop only verifies that the inputs of
984 the SET in INSN do not change. We call reg_set_between_p
985 to verify that the REG in the USE does not change between
987 If the USE in INSN was for a pseudo register, the matching
988 insn pattern will likely match any register; combining this
989 with any other USE would only be safe if we knew that the
990 used registers have identical values, or if there was
991 something to tell them apart, e.g. different modes. For
992 now, we forgo such complicated tests and simply disallow
993 combining of USES of pseudo registers with any other USE. */
994 if (GET_CODE (XEXP (elt
, 0)) == REG
995 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
997 rtx i3pat
= PATTERN (i3
);
998 int i
= XVECLEN (i3pat
, 0) - 1;
999 unsigned int regno
= REGNO (XEXP (elt
, 0));
1003 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1005 if (GET_CODE (i3elt
) == USE
1006 && GET_CODE (XEXP (i3elt
, 0)) == REG
1007 && (REGNO (XEXP (i3elt
, 0)) == regno
1008 ? reg_set_between_p (XEXP (elt
, 0),
1009 PREV_INSN (insn
), i3
)
1010 : regno
>= FIRST_PSEUDO_REGISTER
))
1017 /* We can ignore CLOBBERs. */
1022 /* Ignore SETs whose result isn't used but not those that
1023 have side-effects. */
1024 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1025 && ! side_effects_p (elt
))
1028 /* If we have already found a SET, this is a second one and
1029 so we cannot combine with this insn. */
1037 /* Anything else means we can't combine. */
1043 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1044 so don't do anything with it. */
1045 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1054 set
= expand_field_assignment (set
);
1055 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1057 /* Don't eliminate a store in the stack pointer. */
1058 if (dest
== stack_pointer_rtx
1059 /* If we couldn't eliminate a field assignment, we can't combine. */
1060 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1061 /* Don't combine with an insn that sets a register to itself if it has
1062 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1063 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1064 /* Can't merge an ASM_OPERANDS. */
1065 || GET_CODE (src
) == ASM_OPERANDS
1066 /* Can't merge a function call. */
1067 || GET_CODE (src
) == CALL
1068 /* Don't eliminate a function call argument. */
1069 || (GET_CODE (i3
) == CALL_INSN
1070 && (find_reg_fusage (i3
, USE
, dest
)
1071 || (GET_CODE (dest
) == REG
1072 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1073 && global_regs
[REGNO (dest
)])))
1074 /* Don't substitute into an incremented register. */
1075 || FIND_REG_INC_NOTE (i3
, dest
)
1076 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1078 /* Don't combine the end of a libcall into anything. */
1079 /* ??? This gives worse code, and appears to be unnecessary, since no
1080 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1081 use REG_RETVAL notes for noconflict blocks, but other code here
1082 makes sure that those insns don't disappear. */
1083 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1085 /* Make sure that DEST is not used after SUCC but before I3. */
1086 || (succ
&& ! all_adjacent
1087 && reg_used_between_p (dest
, succ
, i3
))
1088 /* Make sure that the value that is to be substituted for the register
1089 does not use any registers whose values alter in between. However,
1090 If the insns are adjacent, a use can't cross a set even though we
1091 think it might (this can happen for a sequence of insns each setting
1092 the same destination; reg_last_set of that register might point to
1093 a NOTE). If INSN has a REG_EQUIV note, the register is always
1094 equivalent to the memory so the substitution is valid even if there
1095 are intervening stores. Also, don't move a volatile asm or
1096 UNSPEC_VOLATILE across any other insns. */
1098 && (((GET_CODE (src
) != MEM
1099 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1100 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1101 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1102 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1103 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1104 better register allocation by not doing the combine. */
1105 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1106 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1107 /* Don't combine across a CALL_INSN, because that would possibly
1108 change whether the life span of some REGs crosses calls or not,
1109 and it is a pain to update that information.
1110 Exception: if source is a constant, moving it later can't hurt.
1111 Accept that special case, because it helps -fforce-addr a lot. */
1112 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1115 /* DEST must either be a REG or CC0. */
1116 if (GET_CODE (dest
) == REG
)
1118 /* If register alignment is being enforced for multi-word items in all
1119 cases except for parameters, it is possible to have a register copy
1120 insn referencing a hard register that is not allowed to contain the
1121 mode being copied and which would not be valid as an operand of most
1122 insns. Eliminate this problem by not combining with such an insn.
1124 Also, on some machines we don't want to extend the life of a hard
1127 if (GET_CODE (src
) == REG
1128 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1130 /* Don't extend the life of a hard register unless it is
1131 user variable (if we have few registers) or it can't
1132 fit into the desired register (meaning something special
1134 Also avoid substituting a return register into I3, because
1135 reload can't handle a conflict with constraints of other
1137 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1138 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1141 else if (GET_CODE (dest
) != CC0
)
1144 /* Don't substitute for a register intended as a clobberable operand.
1145 Similarly, don't substitute an expression containing a register that
1146 will be clobbered in I3. */
1147 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1148 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1149 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1150 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1152 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1155 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1156 or not), reject, unless nothing volatile comes between it and I3 */
1158 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1160 /* Make sure succ doesn't contain a volatile reference. */
1161 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1164 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1165 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1169 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1170 to be an explicit register variable, and was chosen for a reason. */
1172 if (GET_CODE (src
) == ASM_OPERANDS
1173 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1176 /* If there are any volatile insns between INSN and I3, reject, because
1177 they might affect machine state. */
1179 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1180 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1183 /* If INSN or I2 contains an autoincrement or autodecrement,
1184 make sure that register is not used between there and I3,
1185 and not already used in I3 either.
1186 Also insist that I3 not be a jump; if it were one
1187 and the incremented register were spilled, we would lose. */
1190 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1191 if (REG_NOTE_KIND (link
) == REG_INC
1192 && (GET_CODE (i3
) == JUMP_INSN
1193 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1194 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1199 /* Don't combine an insn that follows a CC0-setting insn.
1200 An insn that uses CC0 must not be separated from the one that sets it.
1201 We do, however, allow I2 to follow a CC0-setting insn if that insn
1202 is passed as I1; in that case it will be deleted also.
1203 We also allow combining in this case if all the insns are adjacent
1204 because that would leave the two CC0 insns adjacent as well.
1205 It would be more logical to test whether CC0 occurs inside I1 or I2,
1206 but that would be much slower, and this ought to be equivalent. */
1208 p
= prev_nonnote_insn (insn
);
1209 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1214 /* If we get here, we have passed all the tests and the combination is
1223 /* Check if PAT is an insn - or a part of it - used to set up an
1224 argument for a function in a hard register. */
1227 sets_function_arg_p (pat
)
1233 switch (GET_CODE (pat
))
1236 return sets_function_arg_p (PATTERN (pat
));
1239 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1240 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1246 inner_dest
= SET_DEST (pat
);
1247 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1248 || GET_CODE (inner_dest
) == SUBREG
1249 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1250 inner_dest
= XEXP (inner_dest
, 0);
1252 return (GET_CODE (inner_dest
) == REG
1253 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1254 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1263 /* LOC is the location within I3 that contains its pattern or the component
1264 of a PARALLEL of the pattern. We validate that it is valid for combining.
1266 One problem is if I3 modifies its output, as opposed to replacing it
1267 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1268 so would produce an insn that is not equivalent to the original insns.
1272 (set (reg:DI 101) (reg:DI 100))
1273 (set (subreg:SI (reg:DI 101) 0) <foo>)
1275 This is NOT equivalent to:
1277 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1278 (set (reg:DI 101) (reg:DI 100))])
1280 Not only does this modify 100 (in which case it might still be valid
1281 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1283 We can also run into a problem if I2 sets a register that I1
1284 uses and I1 gets directly substituted into I3 (not via I2). In that
1285 case, we would be getting the wrong value of I2DEST into I3, so we
1286 must reject the combination. This case occurs when I2 and I1 both
1287 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1288 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1289 of a SET must prevent combination from occurring.
1291 Before doing the above check, we first try to expand a field assignment
1292 into a set of logical operations.
1294 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1295 we place a register that is both set and used within I3. If more than one
1296 such register is detected, we fail.
1298 Return 1 if the combination is valid, zero otherwise. */
1301 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1307 rtx
*pi3dest_killed
;
1311 if (GET_CODE (x
) == SET
)
1313 rtx set
= expand_field_assignment (x
);
1314 rtx dest
= SET_DEST (set
);
1315 rtx src
= SET_SRC (set
);
1316 rtx inner_dest
= dest
;
1319 rtx inner_src
= src
;
1324 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1325 || GET_CODE (inner_dest
) == SUBREG
1326 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1327 inner_dest
= XEXP (inner_dest
, 0);
1329 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1332 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1333 || GET_CODE (inner_src
) == SUBREG
1334 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1335 inner_src
= XEXP (inner_src
, 0);
1337 /* If it is better that two different modes keep two different pseudos,
1338 avoid combining them. This avoids producing the following pattern
1340 (set (subreg:SI (reg/v:QI 21) 0)
1341 (lshiftrt:SI (reg/v:SI 20)
1343 If that were made, reload could not handle the pair of
1344 reg 20/21, since it would try to get any GENERAL_REGS
1345 but some of them don't handle QImode. */
1347 if (rtx_equal_p (inner_src
, i2dest
)
1348 && GET_CODE (inner_dest
) == REG
1349 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1353 /* Check for the case where I3 modifies its output, as
1355 if ((inner_dest
!= dest
1356 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1357 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1359 /* This is the same test done in can_combine_p except we can't test
1360 all_adjacent; we don't have to, since this instruction will stay
1361 in place, thus we are not considering increasing the lifetime of
1364 Also, if this insn sets a function argument, combining it with
1365 something that might need a spill could clobber a previous
1366 function argument; the all_adjacent test in can_combine_p also
1367 checks this; here, we do a more specific test for this case. */
1369 || (GET_CODE (inner_dest
) == REG
1370 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1371 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1372 GET_MODE (inner_dest
))))
1373 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1376 /* If DEST is used in I3, it is being killed in this insn,
1377 so record that for later.
1378 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1379 STACK_POINTER_REGNUM, since these are always considered to be
1380 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1381 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1382 && reg_referenced_p (dest
, PATTERN (i3
))
1383 && REGNO (dest
) != FRAME_POINTER_REGNUM
1384 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1385 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1387 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1388 && (REGNO (dest
) != ARG_POINTER_REGNUM
1389 || ! fixed_regs
[REGNO (dest
)])
1391 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1393 if (*pi3dest_killed
)
1396 *pi3dest_killed
= dest
;
1400 else if (GET_CODE (x
) == PARALLEL
)
1404 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1405 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1406 i1_not_in_src
, pi3dest_killed
))
1413 /* Return 1 if X is an arithmetic expression that contains a multiplication
1414 and division. We don't count multiplications by powers of two here. */
1420 switch (GET_CODE (x
))
1422 case MOD
: case DIV
: case UMOD
: case UDIV
:
1426 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1427 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1429 switch (GET_RTX_CLASS (GET_CODE (x
)))
1431 case 'c': case '<': case '2':
1432 return contains_muldiv (XEXP (x
, 0))
1433 || contains_muldiv (XEXP (x
, 1));
1436 return contains_muldiv (XEXP (x
, 0));
1444 /* Determine whether INSN can be used in a combination. Return nonzero if
1445 not. This is used in try_combine to detect early some cases where we
1446 can't perform combinations. */
1449 cant_combine_insn_p (insn
)
1455 /* If this isn't really an insn, we can't do anything.
1456 This can occur when flow deletes an insn that it has merged into an
1457 auto-increment address. */
1458 if (! INSN_P (insn
))
1461 /* Never combine loads and stores involving hard regs. The register
1462 allocator can usually handle such reg-reg moves by tying. If we allow
1463 the combiner to make substitutions of hard regs, we risk aborting in
1464 reload on machines that have SMALL_REGISTER_CLASSES.
1465 As an exception, we allow combinations involving fixed regs; these are
1466 not available to the register allocator so there's no risk involved. */
1468 set
= single_set (insn
);
1471 src
= SET_SRC (set
);
1472 dest
= SET_DEST (set
);
1473 if (GET_CODE (src
) == SUBREG
)
1474 src
= SUBREG_REG (src
);
1475 if (GET_CODE (dest
) == SUBREG
)
1476 dest
= SUBREG_REG (dest
);
1477 if (REG_P (src
) && REG_P (dest
)
1478 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1479 && ! fixed_regs
[REGNO (src
)])
1480 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1481 && ! fixed_regs
[REGNO (dest
)])))
1487 /* Try to combine the insns I1 and I2 into I3.
1488 Here I1 and I2 appear earlier than I3.
1489 I1 can be zero; then we combine just I2 into I3.
1491 If we are combining three insns and the resulting insn is not recognized,
1492 try splitting it into two insns. If that happens, I2 and I3 are retained
1493 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1496 Return 0 if the combination does not work. Then nothing is changed.
1497 If we did the combination, return the insn at which combine should
1500 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1501 new direct jump instruction. */
1504 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1506 int *new_direct_jump_p
;
1508 /* New patterns for I3 and I2, respectively. */
1509 rtx newpat
, newi2pat
= 0;
1510 int substed_i2
= 0, substed_i1
= 0;
1511 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1512 int added_sets_1
, added_sets_2
;
1513 /* Total number of SETs to put into I3. */
1515 /* Nonzero is I2's body now appears in I3. */
1517 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1518 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1519 /* Contains I3 if the destination of I3 is used in its source, which means
1520 that the old life of I3 is being killed. If that usage is placed into
1521 I2 and not in I3, a REG_DEAD note must be made. */
1522 rtx i3dest_killed
= 0;
1523 /* SET_DEST and SET_SRC of I2 and I1. */
1524 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1525 /* PATTERN (I2), or a copy of it in certain cases. */
1527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1528 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1529 int i1_feeds_i3
= 0;
1530 /* Notes that must be added to REG_NOTES in I3 and I2. */
1531 rtx new_i3_notes
, new_i2_notes
;
1532 /* Notes that we substituted I3 into I2 instead of the normal case. */
1533 int i3_subst_into_i2
= 0;
1534 /* Notes that I1, I2 or I3 is a MULT operation. */
1542 /* Exit early if one of the insns involved can't be used for
1544 if (cant_combine_insn_p (i3
)
1545 || cant_combine_insn_p (i2
)
1546 || (i1
&& cant_combine_insn_p (i1
))
1547 /* We also can't do anything if I3 has a
1548 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1551 /* ??? This gives worse code, and appears to be unnecessary, since no
1552 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1553 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1559 undobuf
.other_insn
= 0;
1561 /* Reset the hard register usage information. */
1562 CLEAR_HARD_REG_SET (newpat_used_regs
);
1564 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1565 code below, set I1 to be the earlier of the two insns. */
1566 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1567 temp
= i1
, i1
= i2
, i2
= temp
;
1569 added_links_insn
= 0;
1571 /* First check for one important special-case that the code below will
1572 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1573 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1574 we may be able to replace that destination with the destination of I3.
1575 This occurs in the common code where we compute both a quotient and
1576 remainder into a structure, in which case we want to do the computation
1577 directly into the structure to avoid register-register copies.
1579 Note that this case handles both multiple sets in I2 and also
1580 cases where I2 has a number of CLOBBER or PARALLELs.
1582 We make very conservative checks below and only try to handle the
1583 most common cases of this. For example, we only handle the case
1584 where I2 and I3 are adjacent to avoid making difficult register
1587 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1588 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1589 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1590 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1591 && GET_CODE (PATTERN (i2
)) == PARALLEL
1592 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1593 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1594 below would need to check what is inside (and reg_overlap_mentioned_p
1595 doesn't support those codes anyway). Don't allow those destinations;
1596 the resulting insn isn't likely to be recognized anyway. */
1597 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1598 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1599 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1600 SET_DEST (PATTERN (i3
)))
1601 && next_real_insn (i2
) == i3
)
1603 rtx p2
= PATTERN (i2
);
1605 /* Make sure that the destination of I3,
1606 which we are going to substitute into one output of I2,
1607 is not used within another output of I2. We must avoid making this:
1608 (parallel [(set (mem (reg 69)) ...)
1609 (set (reg 69) ...)])
1610 which is not well-defined as to order of actions.
1611 (Besides, reload can't handle output reloads for this.)
1613 The problem can also happen if the dest of I3 is a memory ref,
1614 if another dest in I2 is an indirect memory ref. */
1615 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1616 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1617 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1618 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1619 SET_DEST (XVECEXP (p2
, 0, i
))))
1622 if (i
== XVECLEN (p2
, 0))
1623 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1624 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1625 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1626 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1631 subst_low_cuid
= INSN_CUID (i2
);
1633 added_sets_2
= added_sets_1
= 0;
1634 i2dest
= SET_SRC (PATTERN (i3
));
1636 /* Replace the dest in I2 with our dest and make the resulting
1637 insn the new pattern for I3. Then skip to where we
1638 validate the pattern. Everything was set up above. */
1639 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1640 SET_DEST (PATTERN (i3
)));
1643 i3_subst_into_i2
= 1;
1644 goto validate_replacement
;
1648 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1649 one of those words to another constant, merge them by making a new
1652 && (temp
= single_set (i2
)) != 0
1653 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1654 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1655 && GET_CODE (SET_DEST (temp
)) == REG
1656 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1657 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1658 && GET_CODE (PATTERN (i3
)) == SET
1659 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1660 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1661 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1662 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1663 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1665 HOST_WIDE_INT lo
, hi
;
1667 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1668 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1671 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1672 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1675 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1677 /* We don't handle the case of the target word being wider
1678 than a host wide int. */
1679 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1682 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1683 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1684 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1686 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1687 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1688 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1690 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1691 >> (HOST_BITS_PER_WIDE_INT
- 1));
1693 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1694 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1695 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1696 (INTVAL (SET_SRC (PATTERN (i3
)))));
1698 hi
= lo
< 0 ? -1 : 0;
1701 /* We don't handle the case of the higher word not fitting
1702 entirely in either hi or lo. */
1707 subst_low_cuid
= INSN_CUID (i2
);
1708 added_sets_2
= added_sets_1
= 0;
1709 i2dest
= SET_DEST (temp
);
1711 SUBST (SET_SRC (temp
),
1712 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1714 newpat
= PATTERN (i2
);
1715 goto validate_replacement
;
1719 /* If we have no I1 and I2 looks like:
1720 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1722 make up a dummy I1 that is
1725 (set (reg:CC X) (compare:CC Y (const_int 0)))
1727 (We can ignore any trailing CLOBBERs.)
1729 This undoes a previous combination and allows us to match a branch-and-
1732 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1733 && XVECLEN (PATTERN (i2
), 0) >= 2
1734 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1735 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1737 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1738 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1739 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1740 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1741 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1742 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1744 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1745 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1750 /* We make I1 with the same INSN_UID as I2. This gives it
1751 the same INSN_CUID for value tracking. Our fake I1 will
1752 never appear in the insn stream so giving it the same INSN_UID
1753 as I2 will not cause a problem. */
1755 subst_prev_insn
= i1
1756 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1757 BLOCK_FOR_INSN (i2
), INSN_SCOPE (i2
),
1758 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1761 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1762 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1763 SET_DEST (PATTERN (i1
)));
1768 /* Verify that I2 and I1 are valid for combining. */
1769 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1770 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1776 /* Record whether I2DEST is used in I2SRC and similarly for the other
1777 cases. Knowing this will help in register status updating below. */
1778 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1779 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1780 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1782 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1784 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1786 /* Ensure that I3's pattern can be the destination of combines. */
1787 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1788 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1795 /* See if any of the insns is a MULT operation. Unless one is, we will
1796 reject a combination that is, since it must be slower. Be conservative
1798 if (GET_CODE (i2src
) == MULT
1799 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1800 || (GET_CODE (PATTERN (i3
)) == SET
1801 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1804 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1805 We used to do this EXCEPT in one case: I3 has a post-inc in an
1806 output operand. However, that exception can give rise to insns like
1808 which is a famous insn on the PDP-11 where the value of r3 used as the
1809 source was model-dependent. Avoid this sort of thing. */
1812 if (!(GET_CODE (PATTERN (i3
)) == SET
1813 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1814 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1815 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1816 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1817 /* It's not the exception. */
1820 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1821 if (REG_NOTE_KIND (link
) == REG_INC
1822 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1824 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1831 /* See if the SETs in I1 or I2 need to be kept around in the merged
1832 instruction: whenever the value set there is still needed past I3.
1833 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1835 For the SET in I1, we have two cases: If I1 and I2 independently
1836 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1837 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1838 in I1 needs to be kept around unless I1DEST dies or is set in either
1839 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1840 I1DEST. If so, we know I1 feeds into I2. */
1842 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1845 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1846 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1848 /* If the set in I2 needs to be kept around, we must make a copy of
1849 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1850 PATTERN (I2), we are only substituting for the original I1DEST, not into
1851 an already-substituted copy. This also prevents making self-referential
1852 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1855 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1856 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1860 i2pat
= copy_rtx (i2pat
);
1864 /* Substitute in the latest insn for the regs set by the earlier ones. */
1866 maxreg
= max_reg_num ();
1870 /* It is possible that the source of I2 or I1 may be performing an
1871 unneeded operation, such as a ZERO_EXTEND of something that is known
1872 to have the high part zero. Handle that case by letting subst look at
1873 the innermost one of them.
1875 Another way to do this would be to have a function that tries to
1876 simplify a single insn instead of merging two or more insns. We don't
1877 do this because of the potential of infinite loops and because
1878 of the potential extra memory required. However, doing it the way
1879 we are is a bit of a kludge and doesn't catch all cases.
1881 But only do this if -fexpensive-optimizations since it slows things down
1882 and doesn't usually win. */
1884 if (flag_expensive_optimizations
)
1886 /* Pass pc_rtx so no substitutions are done, just simplifications.
1887 The cases that we are interested in here do not involve the few
1888 cases were is_replaced is checked. */
1891 subst_low_cuid
= INSN_CUID (i1
);
1892 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1896 subst_low_cuid
= INSN_CUID (i2
);
1897 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1902 /* Many machines that don't use CC0 have insns that can both perform an
1903 arithmetic operation and set the condition code. These operations will
1904 be represented as a PARALLEL with the first element of the vector
1905 being a COMPARE of an arithmetic operation with the constant zero.
1906 The second element of the vector will set some pseudo to the result
1907 of the same arithmetic operation. If we simplify the COMPARE, we won't
1908 match such a pattern and so will generate an extra insn. Here we test
1909 for this case, where both the comparison and the operation result are
1910 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1911 I2SRC. Later we will make the PARALLEL that contains I2. */
1913 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1914 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1915 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1916 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1918 #ifdef EXTRA_CC_MODES
1920 enum machine_mode compare_mode
;
1923 newpat
= PATTERN (i3
);
1924 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1928 #ifdef EXTRA_CC_MODES
1929 /* See if a COMPARE with the operand we substituted in should be done
1930 with the mode that is currently being used. If not, do the same
1931 processing we do in `subst' for a SET; namely, if the destination
1932 is used only once, try to replace it with a register of the proper
1933 mode and also replace the COMPARE. */
1934 if (undobuf
.other_insn
== 0
1935 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1936 &undobuf
.other_insn
))
1937 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1939 != GET_MODE (SET_DEST (newpat
))))
1941 unsigned int regno
= REGNO (SET_DEST (newpat
));
1942 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1944 if (regno
< FIRST_PSEUDO_REGISTER
1945 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1946 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1948 if (regno
>= FIRST_PSEUDO_REGISTER
)
1949 SUBST (regno_reg_rtx
[regno
], new_dest
);
1951 SUBST (SET_DEST (newpat
), new_dest
);
1952 SUBST (XEXP (*cc_use
, 0), new_dest
);
1953 SUBST (SET_SRC (newpat
),
1954 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1957 undobuf
.other_insn
= 0;
1964 n_occurrences
= 0; /* `subst' counts here */
1966 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1967 need to make a unique copy of I2SRC each time we substitute it
1968 to avoid self-referential rtl. */
1970 subst_low_cuid
= INSN_CUID (i2
);
1971 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1972 ! i1_feeds_i3
&& i1dest_in_i1src
);
1975 /* Record whether i2's body now appears within i3's body. */
1976 i2_is_used
= n_occurrences
;
1979 /* If we already got a failure, don't try to do more. Otherwise,
1980 try to substitute in I1 if we have it. */
1982 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1984 /* Before we can do this substitution, we must redo the test done
1985 above (see detailed comments there) that ensures that I1DEST
1986 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1988 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1996 subst_low_cuid
= INSN_CUID (i1
);
1997 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2001 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2002 to count all the ways that I2SRC and I1SRC can be used. */
2003 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2004 && i2_is_used
+ added_sets_2
> 1)
2005 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2006 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2008 /* Fail if we tried to make a new register (we used to abort, but there's
2009 really no reason to). */
2010 || max_reg_num () != maxreg
2011 /* Fail if we couldn't do something and have a CLOBBER. */
2012 || GET_CODE (newpat
) == CLOBBER
2013 /* Fail if this new pattern is a MULT and we didn't have one before
2014 at the outer level. */
2015 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2022 /* If the actions of the earlier insns must be kept
2023 in addition to substituting them into the latest one,
2024 we must make a new PARALLEL for the latest insn
2025 to hold additional the SETs. */
2027 if (added_sets_1
|| added_sets_2
)
2031 if (GET_CODE (newpat
) == PARALLEL
)
2033 rtvec old
= XVEC (newpat
, 0);
2034 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2035 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2036 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2037 sizeof (old
->elem
[0]) * old
->num_elem
);
2042 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2043 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2044 XVECEXP (newpat
, 0, 0) = old
;
2048 XVECEXP (newpat
, 0, --total_sets
)
2049 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2050 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2054 /* If there is no I1, use I2's body as is. We used to also not do
2055 the subst call below if I2 was substituted into I3,
2056 but that could lose a simplification. */
2058 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2060 /* See comment where i2pat is assigned. */
2061 XVECEXP (newpat
, 0, --total_sets
)
2062 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2066 /* We come here when we are replacing a destination in I2 with the
2067 destination of I3. */
2068 validate_replacement
:
2070 /* Note which hard regs this insn has as inputs. */
2071 mark_used_regs_combine (newpat
);
2073 /* Is the result of combination a valid instruction? */
2074 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2076 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2077 the second SET's destination is a register that is unused. In that case,
2078 we just need the first SET. This can occur when simplifying a divmod
2079 insn. We *must* test for this case here because the code below that
2080 splits two independent SETs doesn't handle this case correctly when it
2081 updates the register status. Also check the case where the first
2082 SET's destination is unused. That would not cause incorrect code, but
2083 does cause an unneeded insn to remain. */
2085 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2086 && XVECLEN (newpat
, 0) == 2
2087 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2088 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2089 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2090 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2091 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2092 && asm_noperands (newpat
) < 0)
2094 newpat
= XVECEXP (newpat
, 0, 0);
2095 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2098 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2099 && XVECLEN (newpat
, 0) == 2
2100 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2101 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2102 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2103 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2104 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2105 && asm_noperands (newpat
) < 0)
2107 newpat
= XVECEXP (newpat
, 0, 1);
2108 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2111 /* If we were combining three insns and the result is a simple SET
2112 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2113 insns. There are two ways to do this. It can be split using a
2114 machine-specific method (like when you have an addition of a large
2115 constant) or by combine in the function find_split_point. */
2117 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2118 && asm_noperands (newpat
) < 0)
2120 rtx m_split
, *split
;
2121 rtx ni2dest
= i2dest
;
2123 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2124 use I2DEST as a scratch register will help. In the latter case,
2125 convert I2DEST to the mode of the source of NEWPAT if we can. */
2127 m_split
= split_insns (newpat
, i3
);
2129 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2130 inputs of NEWPAT. */
2132 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2133 possible to try that as a scratch reg. This would require adding
2134 more code to make it work though. */
2136 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2138 /* If I2DEST is a hard register or the only use of a pseudo,
2139 we can change its mode. */
2140 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2141 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2142 && GET_CODE (i2dest
) == REG
2143 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2144 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2145 && ! REG_USERVAR_P (i2dest
))))
2146 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2149 m_split
= split_insns (gen_rtx_PARALLEL
2151 gen_rtvec (2, newpat
,
2152 gen_rtx_CLOBBER (VOIDmode
,
2155 /* If the split with the mode-changed register didn't work, try
2156 the original register. */
2157 if (! m_split
&& ni2dest
!= i2dest
)
2160 m_split
= split_insns (gen_rtx_PARALLEL
2162 gen_rtvec (2, newpat
,
2163 gen_rtx_CLOBBER (VOIDmode
,
2169 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2171 m_split
= PATTERN (m_split
);
2172 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2173 if (insn_code_number
>= 0)
2176 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2177 && (next_real_insn (i2
) == i3
2178 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2181 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2182 newi2pat
= PATTERN (m_split
);
2184 i3set
= single_set (NEXT_INSN (m_split
));
2185 i2set
= single_set (m_split
);
2187 /* In case we changed the mode of I2DEST, replace it in the
2188 pseudo-register table here. We can't do it above in case this
2189 code doesn't get executed and we do a split the other way. */
2191 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2192 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2194 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2196 /* If I2 or I3 has multiple SETs, we won't know how to track
2197 register status, so don't use these insns. If I2's destination
2198 is used between I2 and I3, we also can't use these insns. */
2200 if (i2_code_number
>= 0 && i2set
&& i3set
2201 && (next_real_insn (i2
) == i3
2202 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2203 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2205 if (insn_code_number
>= 0)
2208 /* It is possible that both insns now set the destination of I3.
2209 If so, we must show an extra use of it. */
2211 if (insn_code_number
>= 0)
2213 rtx new_i3_dest
= SET_DEST (i3set
);
2214 rtx new_i2_dest
= SET_DEST (i2set
);
2216 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2217 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2218 || GET_CODE (new_i3_dest
) == SUBREG
)
2219 new_i3_dest
= XEXP (new_i3_dest
, 0);
2221 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2222 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2223 || GET_CODE (new_i2_dest
) == SUBREG
)
2224 new_i2_dest
= XEXP (new_i2_dest
, 0);
2226 if (GET_CODE (new_i3_dest
) == REG
2227 && GET_CODE (new_i2_dest
) == REG
2228 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2229 REG_N_SETS (REGNO (new_i2_dest
))++;
2233 /* If we can split it and use I2DEST, go ahead and see if that
2234 helps things be recognized. Verify that none of the registers
2235 are set between I2 and I3. */
2236 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2238 && GET_CODE (i2dest
) == REG
2240 /* We need I2DEST in the proper mode. If it is a hard register
2241 or the only use of a pseudo, we can change its mode. */
2242 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2243 || GET_MODE (*split
) == VOIDmode
2244 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2245 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2246 && ! REG_USERVAR_P (i2dest
)))
2247 && (next_real_insn (i2
) == i3
2248 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2249 /* We can't overwrite I2DEST if its value is still used by
2251 && ! reg_referenced_p (i2dest
, newpat
))
2253 rtx newdest
= i2dest
;
2254 enum rtx_code split_code
= GET_CODE (*split
);
2255 enum machine_mode split_mode
= GET_MODE (*split
);
2257 /* Get NEWDEST as a register in the proper mode. We have already
2258 validated that we can do this. */
2259 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2261 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2263 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2264 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2267 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2268 an ASHIFT. This can occur if it was inside a PLUS and hence
2269 appeared to be a memory address. This is a kludge. */
2270 if (split_code
== MULT
2271 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2272 && INTVAL (XEXP (*split
, 1)) > 0
2273 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2275 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2276 XEXP (*split
, 0), GEN_INT (i
)));
2277 /* Update split_code because we may not have a multiply
2279 split_code
= GET_CODE (*split
);
2282 #ifdef INSN_SCHEDULING
2283 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2284 be written as a ZERO_EXTEND. */
2285 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2287 #ifdef LOAD_EXTEND_OP
2288 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2289 what it really is. */
2290 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2292 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2293 SUBREG_REG (*split
)));
2296 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2297 SUBREG_REG (*split
)));
2301 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2302 SUBST (*split
, newdest
);
2303 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2305 /* If the split point was a MULT and we didn't have one before,
2306 don't use one now. */
2307 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2308 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2312 /* Check for a case where we loaded from memory in a narrow mode and
2313 then sign extended it, but we need both registers. In that case,
2314 we have a PARALLEL with both loads from the same memory location.
2315 We can split this into a load from memory followed by a register-register
2316 copy. This saves at least one insn, more if register allocation can
2319 We cannot do this if the destination of the first assignment is a
2320 condition code register or cc0. We eliminate this case by making sure
2321 the SET_DEST and SET_SRC have the same mode.
2323 We cannot do this if the destination of the second assignment is
2324 a register that we have already assumed is zero-extended. Similarly
2325 for a SUBREG of such a register. */
2327 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2328 && GET_CODE (newpat
) == PARALLEL
2329 && XVECLEN (newpat
, 0) == 2
2330 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2331 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2332 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2333 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2334 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2335 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2336 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2337 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2339 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2340 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2341 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2342 (GET_CODE (temp
) == REG
2343 && reg_nonzero_bits
[REGNO (temp
)] != 0
2344 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2345 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2346 && (reg_nonzero_bits
[REGNO (temp
)]
2347 != GET_MODE_MASK (word_mode
))))
2348 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2349 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2350 (GET_CODE (temp
) == REG
2351 && reg_nonzero_bits
[REGNO (temp
)] != 0
2352 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2353 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2354 && (reg_nonzero_bits
[REGNO (temp
)]
2355 != GET_MODE_MASK (word_mode
)))))
2356 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2357 SET_SRC (XVECEXP (newpat
, 0, 1)))
2358 && ! find_reg_note (i3
, REG_UNUSED
,
2359 SET_DEST (XVECEXP (newpat
, 0, 0))))
2363 newi2pat
= XVECEXP (newpat
, 0, 0);
2364 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2365 newpat
= XVECEXP (newpat
, 0, 1);
2366 SUBST (SET_SRC (newpat
),
2367 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2368 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2370 if (i2_code_number
>= 0)
2371 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2373 if (insn_code_number
>= 0)
2378 /* If we will be able to accept this, we have made a change to the
2379 destination of I3. This can invalidate a LOG_LINKS pointing
2380 to I3. No other part of combine.c makes such a transformation.
2382 The new I3 will have a destination that was previously the
2383 destination of I1 or I2 and which was used in i2 or I3. Call
2384 distribute_links to make a LOG_LINK from the next use of
2385 that destination. */
2387 PATTERN (i3
) = newpat
;
2388 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2390 /* I3 now uses what used to be its destination and which is
2391 now I2's destination. That means we need a LOG_LINK from
2392 I3 to I2. But we used to have one, so we still will.
2394 However, some later insn might be using I2's dest and have
2395 a LOG_LINK pointing at I3. We must remove this link.
2396 The simplest way to remove the link is to point it at I1,
2397 which we know will be a NOTE. */
2399 for (insn
= NEXT_INSN (i3
);
2400 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2401 || insn
!= this_basic_block
->next_bb
->head
);
2402 insn
= NEXT_INSN (insn
))
2404 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2406 for (link
= LOG_LINKS (insn
); link
;
2407 link
= XEXP (link
, 1))
2408 if (XEXP (link
, 0) == i3
)
2409 XEXP (link
, 0) = i1
;
2417 /* Similarly, check for a case where we have a PARALLEL of two independent
2418 SETs but we started with three insns. In this case, we can do the sets
2419 as two separate insns. This case occurs when some SET allows two
2420 other insns to combine, but the destination of that SET is still live. */
2422 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2423 && GET_CODE (newpat
) == PARALLEL
2424 && XVECLEN (newpat
, 0) == 2
2425 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2426 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2427 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2428 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2429 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2430 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2431 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2433 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2434 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2435 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2436 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2437 XVECEXP (newpat
, 0, 0))
2438 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2439 XVECEXP (newpat
, 0, 1))
2440 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2441 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2443 /* Normally, it doesn't matter which of the two is done first,
2444 but it does if one references cc0. In that case, it has to
2447 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2449 newi2pat
= XVECEXP (newpat
, 0, 0);
2450 newpat
= XVECEXP (newpat
, 0, 1);
2455 newi2pat
= XVECEXP (newpat
, 0, 1);
2456 newpat
= XVECEXP (newpat
, 0, 0);
2459 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2461 if (i2_code_number
>= 0)
2462 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2465 /* If it still isn't recognized, fail and change things back the way they
2467 if ((insn_code_number
< 0
2468 /* Is the result a reasonable ASM_OPERANDS? */
2469 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2475 /* If we had to change another insn, make sure it is valid also. */
2476 if (undobuf
.other_insn
)
2478 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2479 rtx new_other_notes
;
2482 CLEAR_HARD_REG_SET (newpat_used_regs
);
2484 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2487 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2493 PATTERN (undobuf
.other_insn
) = other_pat
;
2495 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2496 are still valid. Then add any non-duplicate notes added by
2497 recog_for_combine. */
2498 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2500 next
= XEXP (note
, 1);
2502 if (REG_NOTE_KIND (note
) == REG_UNUSED
2503 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2505 if (GET_CODE (XEXP (note
, 0)) == REG
)
2506 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2508 remove_note (undobuf
.other_insn
, note
);
2512 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2513 if (GET_CODE (XEXP (note
, 0)) == REG
)
2514 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2516 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2517 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2520 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2521 they are adjacent to each other or not. */
2523 rtx p
= prev_nonnote_insn (i3
);
2524 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2525 && sets_cc0_p (newi2pat
))
2533 /* We now know that we can do this combination. Merge the insns and
2534 update the status of registers and LOG_LINKS. */
2537 rtx i3notes
, i2notes
, i1notes
= 0;
2538 rtx i3links
, i2links
, i1links
= 0;
2541 /* Compute which registers we expect to eliminate. newi2pat may be setting
2542 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2543 same as i3dest, in which case newi2pat may be setting i1dest. */
2544 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2545 || i2dest_in_i2src
|| i2dest_in_i1src
2547 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2548 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2551 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2553 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2554 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2556 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2558 /* Ensure that we do not have something that should not be shared but
2559 occurs multiple times in the new insns. Check this by first
2560 resetting all the `used' flags and then copying anything is shared. */
2562 reset_used_flags (i3notes
);
2563 reset_used_flags (i2notes
);
2564 reset_used_flags (i1notes
);
2565 reset_used_flags (newpat
);
2566 reset_used_flags (newi2pat
);
2567 if (undobuf
.other_insn
)
2568 reset_used_flags (PATTERN (undobuf
.other_insn
));
2570 i3notes
= copy_rtx_if_shared (i3notes
);
2571 i2notes
= copy_rtx_if_shared (i2notes
);
2572 i1notes
= copy_rtx_if_shared (i1notes
);
2573 newpat
= copy_rtx_if_shared (newpat
);
2574 newi2pat
= copy_rtx_if_shared (newi2pat
);
2575 if (undobuf
.other_insn
)
2576 reset_used_flags (PATTERN (undobuf
.other_insn
));
2578 INSN_CODE (i3
) = insn_code_number
;
2579 PATTERN (i3
) = newpat
;
2581 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2583 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2585 reset_used_flags (call_usage
);
2586 call_usage
= copy_rtx (call_usage
);
2589 replace_rtx (call_usage
, i2dest
, i2src
);
2592 replace_rtx (call_usage
, i1dest
, i1src
);
2594 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2597 if (undobuf
.other_insn
)
2598 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2600 /* We had one special case above where I2 had more than one set and
2601 we replaced a destination of one of those sets with the destination
2602 of I3. In that case, we have to update LOG_LINKS of insns later
2603 in this basic block. Note that this (expensive) case is rare.
2605 Also, in this case, we must pretend that all REG_NOTEs for I2
2606 actually came from I3, so that REG_UNUSED notes from I2 will be
2607 properly handled. */
2609 if (i3_subst_into_i2
)
2611 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2612 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2613 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2614 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2615 && ! find_reg_note (i2
, REG_UNUSED
,
2616 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2617 for (temp
= NEXT_INSN (i2
);
2618 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2619 || this_basic_block
->head
!= temp
);
2620 temp
= NEXT_INSN (temp
))
2621 if (temp
!= i3
&& INSN_P (temp
))
2622 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2623 if (XEXP (link
, 0) == i2
)
2624 XEXP (link
, 0) = i3
;
2629 while (XEXP (link
, 1))
2630 link
= XEXP (link
, 1);
2631 XEXP (link
, 1) = i2notes
;
2645 INSN_CODE (i2
) = i2_code_number
;
2646 PATTERN (i2
) = newi2pat
;
2650 PUT_CODE (i2
, NOTE
);
2651 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2652 NOTE_SOURCE_FILE (i2
) = 0;
2659 PUT_CODE (i1
, NOTE
);
2660 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2661 NOTE_SOURCE_FILE (i1
) = 0;
2664 /* Get death notes for everything that is now used in either I3 or
2665 I2 and used to die in a previous insn. If we built two new
2666 patterns, move from I1 to I2 then I2 to I3 so that we get the
2667 proper movement on registers that I2 modifies. */
2671 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2672 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2675 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2678 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2680 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2683 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2686 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2689 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2692 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2693 know these are REG_UNUSED and want them to go to the desired insn,
2694 so we always pass it as i3. We have not counted the notes in
2695 reg_n_deaths yet, so we need to do so now. */
2697 if (newi2pat
&& new_i2_notes
)
2699 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2700 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2701 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2703 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2708 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2709 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2710 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2712 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2715 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2716 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2717 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2718 in that case, it might delete I2. Similarly for I2 and I1.
2719 Show an additional death due to the REG_DEAD note we make here. If
2720 we discard it in distribute_notes, we will decrement it again. */
2724 if (GET_CODE (i3dest_killed
) == REG
)
2725 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2727 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2728 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2730 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2732 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2734 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2738 if (i2dest_in_i2src
)
2740 if (GET_CODE (i2dest
) == REG
)
2741 REG_N_DEATHS (REGNO (i2dest
))++;
2743 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2744 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2745 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2747 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2748 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2749 NULL_RTX
, NULL_RTX
);
2752 if (i1dest_in_i1src
)
2754 if (GET_CODE (i1dest
) == REG
)
2755 REG_N_DEATHS (REGNO (i1dest
))++;
2757 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2758 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2759 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2761 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2762 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2763 NULL_RTX
, NULL_RTX
);
2766 distribute_links (i3links
);
2767 distribute_links (i2links
);
2768 distribute_links (i1links
);
2770 if (GET_CODE (i2dest
) == REG
)
2773 rtx i2_insn
= 0, i2_val
= 0, set
;
2775 /* The insn that used to set this register doesn't exist, and
2776 this life of the register may not exist either. See if one of
2777 I3's links points to an insn that sets I2DEST. If it does,
2778 that is now the last known value for I2DEST. If we don't update
2779 this and I2 set the register to a value that depended on its old
2780 contents, we will get confused. If this insn is used, thing
2781 will be set correctly in combine_instructions. */
2783 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2784 if ((set
= single_set (XEXP (link
, 0))) != 0
2785 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2786 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2788 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2790 /* If the reg formerly set in I2 died only once and that was in I3,
2791 zero its use count so it won't make `reload' do any work. */
2793 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2794 && ! i2dest_in_i2src
)
2796 regno
= REGNO (i2dest
);
2797 REG_N_SETS (regno
)--;
2801 if (i1
&& GET_CODE (i1dest
) == REG
)
2804 rtx i1_insn
= 0, i1_val
= 0, set
;
2806 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2807 if ((set
= single_set (XEXP (link
, 0))) != 0
2808 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2809 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2811 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2813 regno
= REGNO (i1dest
);
2814 if (! added_sets_1
&& ! i1dest_in_i1src
)
2815 REG_N_SETS (regno
)--;
2818 /* Update reg_nonzero_bits et al for any changes that may have been made
2819 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2820 important. Because newi2pat can affect nonzero_bits of newpat */
2822 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2823 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2825 /* Set new_direct_jump_p if a new return or simple jump instruction
2828 If I3 is now an unconditional jump, ensure that it has a
2829 BARRIER following it since it may have initially been a
2830 conditional jump. It may also be the last nonnote insn. */
2832 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2834 *new_direct_jump_p
= 1;
2836 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2837 || GET_CODE (temp
) != BARRIER
)
2838 emit_barrier_after (i3
);
2841 if (undobuf
.other_insn
!= NULL_RTX
2842 && (returnjump_p (undobuf
.other_insn
)
2843 || any_uncondjump_p (undobuf
.other_insn
)))
2845 *new_direct_jump_p
= 1;
2847 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2848 || GET_CODE (temp
) != BARRIER
)
2849 emit_barrier_after (undobuf
.other_insn
);
2852 /* An NOOP jump does not need barrier, but it does need cleaning up
2854 if (GET_CODE (newpat
) == SET
2855 && SET_SRC (newpat
) == pc_rtx
2856 && SET_DEST (newpat
) == pc_rtx
)
2857 *new_direct_jump_p
= 1;
2860 combine_successes
++;
2863 /* Clear this here, so that subsequent get_last_value calls are not
2865 subst_prev_insn
= NULL_RTX
;
2867 if (added_links_insn
2868 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2869 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2870 return added_links_insn
;
2872 return newi2pat
? i2
: i3
;
2875 /* Undo all the modifications recorded in undobuf. */
2880 struct undo
*undo
, *next
;
2882 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2886 *undo
->where
.i
= undo
->old_contents
.i
;
2888 *undo
->where
.r
= undo
->old_contents
.r
;
2890 undo
->next
= undobuf
.frees
;
2891 undobuf
.frees
= undo
;
2896 /* Clear this here, so that subsequent get_last_value calls are not
2898 subst_prev_insn
= NULL_RTX
;
2901 /* We've committed to accepting the changes we made. Move all
2902 of the undos to the free list. */
2907 struct undo
*undo
, *next
;
2909 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2912 undo
->next
= undobuf
.frees
;
2913 undobuf
.frees
= undo
;
2919 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2920 where we have an arithmetic expression and return that point. LOC will
2923 try_combine will call this function to see if an insn can be split into
2927 find_split_point (loc
, insn
)
2932 enum rtx_code code
= GET_CODE (x
);
2934 unsigned HOST_WIDE_INT len
= 0;
2935 HOST_WIDE_INT pos
= 0;
2937 rtx inner
= NULL_RTX
;
2939 /* First special-case some codes. */
2943 #ifdef INSN_SCHEDULING
2944 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2946 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2949 return find_split_point (&SUBREG_REG (x
), insn
);
2953 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2954 using LO_SUM and HIGH. */
2955 if (GET_CODE (XEXP (x
, 0)) == CONST
2956 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2959 gen_rtx_LO_SUM (Pmode
,
2960 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2962 return &XEXP (XEXP (x
, 0), 0);
2966 /* If we have a PLUS whose second operand is a constant and the
2967 address is not valid, perhaps will can split it up using
2968 the machine-specific way to split large constants. We use
2969 the first pseudo-reg (one of the virtual regs) as a placeholder;
2970 it will not remain in the result. */
2971 if (GET_CODE (XEXP (x
, 0)) == PLUS
2972 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2973 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2975 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2976 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2979 /* This should have produced two insns, each of which sets our
2980 placeholder. If the source of the second is a valid address,
2981 we can make put both sources together and make a split point
2985 && NEXT_INSN (seq
) != NULL_RTX
2986 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2987 && GET_CODE (seq
) == INSN
2988 && GET_CODE (PATTERN (seq
)) == SET
2989 && SET_DEST (PATTERN (seq
)) == reg
2990 && ! reg_mentioned_p (reg
,
2991 SET_SRC (PATTERN (seq
)))
2992 && GET_CODE (NEXT_INSN (seq
)) == INSN
2993 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2994 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2995 && memory_address_p (GET_MODE (x
),
2996 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2998 rtx src1
= SET_SRC (PATTERN (seq
));
2999 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3001 /* Replace the placeholder in SRC2 with SRC1. If we can
3002 find where in SRC2 it was placed, that can become our
3003 split point and we can replace this address with SRC2.
3004 Just try two obvious places. */
3006 src2
= replace_rtx (src2
, reg
, src1
);
3008 if (XEXP (src2
, 0) == src1
)
3009 split
= &XEXP (src2
, 0);
3010 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3011 && XEXP (XEXP (src2
, 0), 0) == src1
)
3012 split
= &XEXP (XEXP (src2
, 0), 0);
3016 SUBST (XEXP (x
, 0), src2
);
3021 /* If that didn't work, perhaps the first operand is complex and
3022 needs to be computed separately, so make a split point there.
3023 This will occur on machines that just support REG + CONST
3024 and have a constant moved through some previous computation. */
3026 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
3027 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3028 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
3030 return &XEXP (XEXP (x
, 0), 0);
3036 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3037 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3038 we need to put the operand into a register. So split at that
3041 if (SET_DEST (x
) == cc0_rtx
3042 && GET_CODE (SET_SRC (x
)) != COMPARE
3043 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3044 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
3045 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3046 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
3047 return &SET_SRC (x
);
3050 /* See if we can split SET_SRC as it stands. */
3051 split
= find_split_point (&SET_SRC (x
), insn
);
3052 if (split
&& split
!= &SET_SRC (x
))
3055 /* See if we can split SET_DEST as it stands. */
3056 split
= find_split_point (&SET_DEST (x
), insn
);
3057 if (split
&& split
!= &SET_DEST (x
))
3060 /* See if this is a bitfield assignment with everything constant. If
3061 so, this is an IOR of an AND, so split it into that. */
3062 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3063 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3064 <= HOST_BITS_PER_WIDE_INT
)
3065 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3066 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3067 && GET_CODE (SET_SRC (x
)) == CONST_INT
3068 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3069 + INTVAL (XEXP (SET_DEST (x
), 2)))
3070 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3071 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3073 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3074 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3075 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3076 rtx dest
= XEXP (SET_DEST (x
), 0);
3077 enum machine_mode mode
= GET_MODE (dest
);
3078 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3080 if (BITS_BIG_ENDIAN
)
3081 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3085 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3088 gen_binary (IOR
, mode
,
3089 gen_binary (AND
, mode
, dest
,
3090 gen_int_mode (~(mask
<< pos
),
3092 GEN_INT (src
<< pos
)));
3094 SUBST (SET_DEST (x
), dest
);
3096 split
= find_split_point (&SET_SRC (x
), insn
);
3097 if (split
&& split
!= &SET_SRC (x
))
3101 /* Otherwise, see if this is an operation that we can split into two.
3102 If so, try to split that. */
3103 code
= GET_CODE (SET_SRC (x
));
3108 /* If we are AND'ing with a large constant that is only a single
3109 bit and the result is only being used in a context where we
3110 need to know if it is zero or nonzero, replace it with a bit
3111 extraction. This will avoid the large constant, which might
3112 have taken more than one insn to make. If the constant were
3113 not a valid argument to the AND but took only one insn to make,
3114 this is no worse, but if it took more than one insn, it will
3117 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3118 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3119 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3120 && GET_CODE (SET_DEST (x
)) == REG
3121 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3122 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3123 && XEXP (*split
, 0) == SET_DEST (x
)
3124 && XEXP (*split
, 1) == const0_rtx
)
3126 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3127 XEXP (SET_SRC (x
), 0),
3128 pos
, NULL_RTX
, 1, 1, 0, 0);
3129 if (extraction
!= 0)
3131 SUBST (SET_SRC (x
), extraction
);
3132 return find_split_point (loc
, insn
);
3138 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3139 is known to be on, this can be converted into a NEG of a shift. */
3140 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3141 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3142 && 1 <= (pos
= exact_log2
3143 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3144 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3146 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3150 gen_rtx_LSHIFTRT (mode
,
3151 XEXP (SET_SRC (x
), 0),
3154 split
= find_split_point (&SET_SRC (x
), insn
);
3155 if (split
&& split
!= &SET_SRC (x
))
3161 inner
= XEXP (SET_SRC (x
), 0);
3163 /* We can't optimize if either mode is a partial integer
3164 mode as we don't know how many bits are significant
3166 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3167 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3171 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3177 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3178 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3180 inner
= XEXP (SET_SRC (x
), 0);
3181 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3182 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3184 if (BITS_BIG_ENDIAN
)
3185 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3186 unsignedp
= (code
== ZERO_EXTRACT
);
3194 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3196 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3198 /* For unsigned, we have a choice of a shift followed by an
3199 AND or two shifts. Use two shifts for field sizes where the
3200 constant might be too large. We assume here that we can
3201 always at least get 8-bit constants in an AND insn, which is
3202 true for every current RISC. */
3204 if (unsignedp
&& len
<= 8)
3209 (mode
, gen_lowpart_for_combine (mode
, inner
),
3211 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3213 split
= find_split_point (&SET_SRC (x
), insn
);
3214 if (split
&& split
!= &SET_SRC (x
))
3221 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3222 gen_rtx_ASHIFT (mode
,
3223 gen_lowpart_for_combine (mode
, inner
),
3224 GEN_INT (GET_MODE_BITSIZE (mode
)
3226 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3228 split
= find_split_point (&SET_SRC (x
), insn
);
3229 if (split
&& split
!= &SET_SRC (x
))
3234 /* See if this is a simple operation with a constant as the second
3235 operand. It might be that this constant is out of range and hence
3236 could be used as a split point. */
3237 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3238 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3239 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3240 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3241 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3242 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3243 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3245 return &XEXP (SET_SRC (x
), 1);
3247 /* Finally, see if this is a simple operation with its first operand
3248 not in a register. The operation might require this operand in a
3249 register, so return it as a split point. We can always do this
3250 because if the first operand were another operation, we would have
3251 already found it as a split point. */
3252 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3253 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3254 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3255 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3256 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3257 return &XEXP (SET_SRC (x
), 0);
3263 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3264 it is better to write this as (not (ior A B)) so we can split it.
3265 Similarly for IOR. */
3266 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3269 gen_rtx_NOT (GET_MODE (x
),
3270 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3272 XEXP (XEXP (x
, 0), 0),
3273 XEXP (XEXP (x
, 1), 0))));
3274 return find_split_point (loc
, insn
);
3277 /* Many RISC machines have a large set of logical insns. If the
3278 second operand is a NOT, put it first so we will try to split the
3279 other operand first. */
3280 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3282 rtx tem
= XEXP (x
, 0);
3283 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3284 SUBST (XEXP (x
, 1), tem
);
3292 /* Otherwise, select our actions depending on our rtx class. */
3293 switch (GET_RTX_CLASS (code
))
3295 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3297 split
= find_split_point (&XEXP (x
, 2), insn
);
3300 /* ... fall through ... */
3304 split
= find_split_point (&XEXP (x
, 1), insn
);
3307 /* ... fall through ... */
3309 /* Some machines have (and (shift ...) ...) insns. If X is not
3310 an AND, but XEXP (X, 0) is, use it as our split point. */
3311 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3312 return &XEXP (x
, 0);
3314 split
= find_split_point (&XEXP (x
, 0), insn
);
3320 /* Otherwise, we don't have a split point. */
3324 /* Throughout X, replace FROM with TO, and return the result.
3325 The result is TO if X is FROM;
3326 otherwise the result is X, but its contents may have been modified.
3327 If they were modified, a record was made in undobuf so that
3328 undo_all will (among other things) return X to its original state.
3330 If the number of changes necessary is too much to record to undo,
3331 the excess changes are not made, so the result is invalid.
3332 The changes already made can still be undone.
3333 undobuf.num_undo is incremented for such changes, so by testing that
3334 the caller can tell whether the result is valid.
3336 `n_occurrences' is incremented each time FROM is replaced.
3338 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3340 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3341 by copying if `n_occurrences' is nonzero. */
3344 subst (x
, from
, to
, in_dest
, unique_copy
)
3349 enum rtx_code code
= GET_CODE (x
);
3350 enum machine_mode op0_mode
= VOIDmode
;
3355 /* Two expressions are equal if they are identical copies of a shared
3356 RTX or if they are both registers with the same register number
3359 #define COMBINE_RTX_EQUAL_P(X,Y) \
3361 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3362 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3364 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3367 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3370 /* If X and FROM are the same register but different modes, they will
3371 not have been seen as equal above. However, flow.c will make a
3372 LOG_LINKS entry for that case. If we do nothing, we will try to
3373 rerecognize our original insn and, when it succeeds, we will
3374 delete the feeding insn, which is incorrect.
3376 So force this insn not to match in this (rare) case. */
3377 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3378 && REGNO (x
) == REGNO (from
))
3379 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3381 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3382 of which may contain things that can be combined. */
3383 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3386 /* It is possible to have a subexpression appear twice in the insn.
3387 Suppose that FROM is a register that appears within TO.
3388 Then, after that subexpression has been scanned once by `subst',
3389 the second time it is scanned, TO may be found. If we were
3390 to scan TO here, we would find FROM within it and create a
3391 self-referent rtl structure which is completely wrong. */
3392 if (COMBINE_RTX_EQUAL_P (x
, to
))
3395 /* Parallel asm_operands need special attention because all of the
3396 inputs are shared across the arms. Furthermore, unsharing the
3397 rtl results in recognition failures. Failure to handle this case
3398 specially can result in circular rtl.
3400 Solve this by doing a normal pass across the first entry of the
3401 parallel, and only processing the SET_DESTs of the subsequent
3404 if (code
== PARALLEL
3405 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3406 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3408 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3410 /* If this substitution failed, this whole thing fails. */
3411 if (GET_CODE (new) == CLOBBER
3412 && XEXP (new, 0) == const0_rtx
)
3415 SUBST (XVECEXP (x
, 0, 0), new);
3417 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3419 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3421 if (GET_CODE (dest
) != REG
3422 && GET_CODE (dest
) != CC0
3423 && GET_CODE (dest
) != PC
)
3425 new = subst (dest
, from
, to
, 0, unique_copy
);
3427 /* If this substitution failed, this whole thing fails. */
3428 if (GET_CODE (new) == CLOBBER
3429 && XEXP (new, 0) == const0_rtx
)
3432 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3438 len
= GET_RTX_LENGTH (code
);
3439 fmt
= GET_RTX_FORMAT (code
);
3441 /* We don't need to process a SET_DEST that is a register, CC0,
3442 or PC, so set up to skip this common case. All other cases
3443 where we want to suppress replacing something inside a
3444 SET_SRC are handled via the IN_DEST operand. */
3446 && (GET_CODE (SET_DEST (x
)) == REG
3447 || GET_CODE (SET_DEST (x
)) == CC0
3448 || GET_CODE (SET_DEST (x
)) == PC
))
3451 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3454 op0_mode
= GET_MODE (XEXP (x
, 0));
3456 for (i
= 0; i
< len
; i
++)
3461 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3463 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3465 new = (unique_copy
&& n_occurrences
3466 ? copy_rtx (to
) : to
);
3471 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3474 /* If this substitution failed, this whole thing
3476 if (GET_CODE (new) == CLOBBER
3477 && XEXP (new, 0) == const0_rtx
)
3481 SUBST (XVECEXP (x
, i
, j
), new);
3484 else if (fmt
[i
] == 'e')
3486 /* If this is a register being set, ignore it. */
3489 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3490 || code
== ZERO_EXTRACT
)
3492 && GET_CODE (new) == REG
)
3495 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3497 /* In general, don't install a subreg involving two
3498 modes not tieable. It can worsen register
3499 allocation, and can even make invalid reload
3500 insns, since the reg inside may need to be copied
3501 from in the outside mode, and that may be invalid
3502 if it is an fp reg copied in integer mode.
3504 We allow two exceptions to this: It is valid if
3505 it is inside another SUBREG and the mode of that
3506 SUBREG and the mode of the inside of TO is
3507 tieable and it is valid if X is a SET that copies
3510 if (GET_CODE (to
) == SUBREG
3511 && ! MODES_TIEABLE_P (GET_MODE (to
),
3512 GET_MODE (SUBREG_REG (to
)))
3513 && ! (code
== SUBREG
3514 && MODES_TIEABLE_P (GET_MODE (x
),
3515 GET_MODE (SUBREG_REG (to
))))
3517 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3520 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3522 #ifdef CANNOT_CHANGE_MODE_CLASS
3524 && GET_CODE (to
) == REG
3525 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3526 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3529 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3532 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3536 /* If we are in a SET_DEST, suppress most cases unless we
3537 have gone inside a MEM, in which case we want to
3538 simplify the address. We assume here that things that
3539 are actually part of the destination have their inner
3540 parts in the first expression. This is true for SUBREG,
3541 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3542 things aside from REG and MEM that should appear in a
3544 new = subst (XEXP (x
, i
), from
, to
,
3546 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3547 || code
== ZERO_EXTRACT
))
3549 && i
== 0), unique_copy
);
3551 /* If we found that we will have to reject this combination,
3552 indicate that by returning the CLOBBER ourselves, rather than
3553 an expression containing it. This will speed things up as
3554 well as prevent accidents where two CLOBBERs are considered
3555 to be equal, thus producing an incorrect simplification. */
3557 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3560 if (GET_CODE (new) == CONST_INT
&& GET_CODE (x
) == SUBREG
)
3562 enum machine_mode mode
= GET_MODE (x
);
3564 x
= simplify_subreg (GET_MODE (x
), new,
3565 GET_MODE (SUBREG_REG (x
)),
3568 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3570 else if (GET_CODE (new) == CONST_INT
3571 && GET_CODE (x
) == ZERO_EXTEND
)
3573 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3574 new, GET_MODE (XEXP (x
, 0)));
3579 SUBST (XEXP (x
, i
), new);
3584 /* Try to simplify X. If the simplification changed the code, it is likely
3585 that further simplification will help, so loop, but limit the number
3586 of repetitions that will be performed. */
3588 for (i
= 0; i
< 4; i
++)
3590 /* If X is sufficiently simple, don't bother trying to do anything
3592 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3593 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3595 if (GET_CODE (x
) == code
)
3598 code
= GET_CODE (x
);
3600 /* We no longer know the original mode of operand 0 since we
3601 have changed the form of X) */
3602 op0_mode
= VOIDmode
;
3608 /* Simplify X, a piece of RTL. We just operate on the expression at the
3609 outer level; call `subst' to simplify recursively. Return the new
3612 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3613 will be the iteration even if an expression with a code different from
3614 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3617 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3619 enum machine_mode op0_mode
;
3623 enum rtx_code code
= GET_CODE (x
);
3624 enum machine_mode mode
= GET_MODE (x
);
3629 /* If this is a commutative operation, put a constant last and a complex
3630 expression first. We don't need to do this for comparisons here. */
3631 if (GET_RTX_CLASS (code
) == 'c'
3632 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3635 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3636 SUBST (XEXP (x
, 1), temp
);
3639 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3640 sign extension of a PLUS with a constant, reverse the order of the sign
3641 extension and the addition. Note that this not the same as the original
3642 code, but overflow is undefined for signed values. Also note that the
3643 PLUS will have been partially moved "inside" the sign-extension, so that
3644 the first operand of X will really look like:
3645 (ashiftrt (plus (ashift A C4) C5) C4).
3647 (plus (ashiftrt (ashift A C4) C2) C4)
3648 and replace the first operand of X with that expression. Later parts
3649 of this function may simplify the expression further.
3651 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3652 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3653 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3655 We do this to simplify address expressions. */
3657 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3658 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3659 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3660 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3661 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3662 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3663 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3664 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3665 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3666 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3667 XEXP (XEXP (x
, 0), 1))) != 0)
3670 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3671 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3672 INTVAL (XEXP (XEXP (x
, 0), 1)));
3674 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3675 INTVAL (XEXP (XEXP (x
, 0), 1)));
3677 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3680 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3681 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3682 things. Check for cases where both arms are testing the same
3685 Don't do anything if all operands are very simple. */
3687 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3688 || GET_RTX_CLASS (code
) == '<')
3689 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3690 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3691 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3693 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3694 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3695 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3697 || (GET_RTX_CLASS (code
) == '1'
3698 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3699 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3700 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3703 rtx cond
, true_rtx
, false_rtx
;
3705 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3707 /* If everything is a comparison, what we have is highly unlikely
3708 to be simpler, so don't use it. */
3709 && ! (GET_RTX_CLASS (code
) == '<'
3710 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3711 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3713 rtx cop1
= const0_rtx
;
3714 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3716 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3719 /* Simplify the alternative arms; this may collapse the true and
3720 false arms to store-flag values. */
3721 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3722 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3724 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3725 is unlikely to be simpler. */
3726 if (general_operand (true_rtx
, VOIDmode
)
3727 && general_operand (false_rtx
, VOIDmode
))
3729 /* Restarting if we generate a store-flag expression will cause
3730 us to loop. Just drop through in this case. */
3732 /* If the result values are STORE_FLAG_VALUE and zero, we can
3733 just make the comparison operation. */
3734 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3735 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3736 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3737 && reverse_condition (cond_code
) != UNKNOWN
)
3738 x
= gen_binary (reverse_condition (cond_code
),
3741 /* Likewise, we can make the negate of a comparison operation
3742 if the result values are - STORE_FLAG_VALUE and zero. */
3743 else if (GET_CODE (true_rtx
) == CONST_INT
3744 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3745 && false_rtx
== const0_rtx
)
3746 x
= simplify_gen_unary (NEG
, mode
,
3747 gen_binary (cond_code
, mode
, cond
,
3750 else if (GET_CODE (false_rtx
) == CONST_INT
3751 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3752 && true_rtx
== const0_rtx
)
3753 x
= simplify_gen_unary (NEG
, mode
,
3754 gen_binary (reverse_condition
3759 return gen_rtx_IF_THEN_ELSE (mode
,
3760 gen_binary (cond_code
, VOIDmode
,
3762 true_rtx
, false_rtx
);
3764 code
= GET_CODE (x
);
3765 op0_mode
= VOIDmode
;
3770 /* Try to fold this expression in case we have constants that weren't
3773 switch (GET_RTX_CLASS (code
))
3776 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3780 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3781 if (cmp_mode
== VOIDmode
)
3783 cmp_mode
= GET_MODE (XEXP (x
, 1));
3784 if (cmp_mode
== VOIDmode
)
3785 cmp_mode
= op0_mode
;
3787 temp
= simplify_relational_operation (code
, cmp_mode
,
3788 XEXP (x
, 0), XEXP (x
, 1));
3790 #ifdef FLOAT_STORE_FLAG_VALUE
3791 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3793 if (temp
== const0_rtx
)
3794 temp
= CONST0_RTX (mode
);
3796 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3803 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3807 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3808 XEXP (x
, 1), XEXP (x
, 2));
3815 code
= GET_CODE (temp
);
3816 op0_mode
= VOIDmode
;
3817 mode
= GET_MODE (temp
);
3820 /* First see if we can apply the inverse distributive law. */
3821 if (code
== PLUS
|| code
== MINUS
3822 || code
== AND
|| code
== IOR
|| code
== XOR
)
3824 x
= apply_distributive_law (x
);
3825 code
= GET_CODE (x
);
3826 op0_mode
= VOIDmode
;
3829 /* If CODE is an associative operation not otherwise handled, see if we
3830 can associate some operands. This can win if they are constants or
3831 if they are logically related (i.e. (a & b) & a). */
3832 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3833 || code
== AND
|| code
== IOR
|| code
== XOR
3834 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3835 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3836 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3838 if (GET_CODE (XEXP (x
, 0)) == code
)
3840 rtx other
= XEXP (XEXP (x
, 0), 0);
3841 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3842 rtx inner_op1
= XEXP (x
, 1);
3845 /* Make sure we pass the constant operand if any as the second
3846 one if this is a commutative operation. */
3847 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3849 rtx tem
= inner_op0
;
3850 inner_op0
= inner_op1
;
3853 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3854 : code
== DIV
? MULT
3856 mode
, inner_op0
, inner_op1
);
3858 /* For commutative operations, try the other pair if that one
3860 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3862 other
= XEXP (XEXP (x
, 0), 1);
3863 inner
= simplify_binary_operation (code
, mode
,
3864 XEXP (XEXP (x
, 0), 0),
3869 return gen_binary (code
, mode
, other
, inner
);
3873 /* A little bit of algebraic simplification here. */
3877 /* Ensure that our address has any ASHIFTs converted to MULT in case
3878 address-recognizing predicates are called later. */
3879 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3880 SUBST (XEXP (x
, 0), temp
);
3884 if (op0_mode
== VOIDmode
)
3885 op0_mode
= GET_MODE (SUBREG_REG (x
));
3887 /* simplify_subreg can't use gen_lowpart_for_combine. */
3888 if (CONSTANT_P (SUBREG_REG (x
))
3889 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3890 /* Don't call gen_lowpart_for_combine if the inner mode
3891 is VOIDmode and we cannot simplify it, as SUBREG without
3892 inner mode is invalid. */
3893 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3894 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3895 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3897 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3901 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3907 /* Don't change the mode of the MEM if that would change the meaning
3909 if (GET_CODE (SUBREG_REG (x
)) == MEM
3910 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3911 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3912 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3914 /* Note that we cannot do any narrowing for non-constants since
3915 we might have been counting on using the fact that some bits were
3916 zero. We now do this in the SET. */
3921 /* (not (plus X -1)) can become (neg X). */
3922 if (GET_CODE (XEXP (x
, 0)) == PLUS
3923 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3924 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3926 /* Similarly, (not (neg X)) is (plus X -1). */
3927 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3928 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3930 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3931 if (GET_CODE (XEXP (x
, 0)) == XOR
3932 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3933 && (temp
= simplify_unary_operation (NOT
, mode
,
3934 XEXP (XEXP (x
, 0), 1),
3936 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3938 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3939 other than 1, but that is not valid. We could do a similar
3940 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3941 but this doesn't seem common enough to bother with. */
3942 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3943 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3944 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3946 XEXP (XEXP (x
, 0), 1));
3948 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3949 && subreg_lowpart_p (XEXP (x
, 0))
3950 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3951 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3952 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3953 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3955 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3957 x
= gen_rtx_ROTATE (inner_mode
,
3958 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3960 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3961 return gen_lowpart_for_combine (mode
, x
);
3964 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3965 reversing the comparison code if valid. */
3966 if (STORE_FLAG_VALUE
== -1
3967 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3968 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3969 XEXP (XEXP (x
, 0), 1))))
3972 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3973 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3974 perform the above simplification. */
3976 if (STORE_FLAG_VALUE
== -1
3977 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3978 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3979 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3980 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3982 /* Apply De Morgan's laws to reduce number of patterns for machines
3983 with negating logical insns (and-not, nand, etc.). If result has
3984 only one NOT, put it first, since that is how the patterns are
3987 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3989 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3990 enum machine_mode op_mode
;
3992 op_mode
= GET_MODE (in1
);
3993 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3995 op_mode
= GET_MODE (in2
);
3996 if (op_mode
== VOIDmode
)
3998 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4000 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4003 in2
= in1
; in1
= tem
;
4006 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4012 /* (neg (plus X 1)) can become (not X). */
4013 if (GET_CODE (XEXP (x
, 0)) == PLUS
4014 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
4015 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
4017 /* Similarly, (neg (not X)) is (plus X 1). */
4018 if (GET_CODE (XEXP (x
, 0)) == NOT
)
4019 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
4021 /* (neg (minus X Y)) can become (minus Y X). This transformation
4022 isn't safe for modes with signed zeros, since if X and Y are
4023 both +0, (minus Y X) is the same as (minus X Y). If the rounding
4024 mode is towards +infinity (or -infinity) then the two expressions
4025 will be rounded differently. */
4026 if (GET_CODE (XEXP (x
, 0)) == MINUS
4027 && !HONOR_SIGNED_ZEROS (mode
)
4028 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
4029 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
4030 XEXP (XEXP (x
, 0), 0));
4032 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4033 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
4034 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4035 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4037 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4038 if we can then eliminate the NEG (e.g.,
4039 if the operand is a constant). */
4041 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
4043 temp
= simplify_unary_operation (NEG
, mode
,
4044 XEXP (XEXP (x
, 0), 0), mode
);
4046 return gen_binary (ASHIFT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
4049 temp
= expand_compound_operation (XEXP (x
, 0));
4051 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4052 replaced by (lshiftrt X C). This will convert
4053 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4055 if (GET_CODE (temp
) == ASHIFTRT
4056 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4057 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4058 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4059 INTVAL (XEXP (temp
, 1)));
4061 /* If X has only a single bit that might be nonzero, say, bit I, convert
4062 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4063 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4064 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4065 or a SUBREG of one since we'd be making the expression more
4066 complex if it was just a register. */
4068 if (GET_CODE (temp
) != REG
4069 && ! (GET_CODE (temp
) == SUBREG
4070 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4071 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4073 rtx temp1
= simplify_shift_const
4074 (NULL_RTX
, ASHIFTRT
, mode
,
4075 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4076 GET_MODE_BITSIZE (mode
) - 1 - i
),
4077 GET_MODE_BITSIZE (mode
) - 1 - i
);
4079 /* If all we did was surround TEMP with the two shifts, we
4080 haven't improved anything, so don't use it. Otherwise,
4081 we are better off with TEMP1. */
4082 if (GET_CODE (temp1
) != ASHIFTRT
4083 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4084 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4090 /* We can't handle truncation to a partial integer mode here
4091 because we don't know the real bitsize of the partial
4093 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4096 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4097 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4098 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4100 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4101 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4103 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4104 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4105 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4106 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4107 return XEXP (XEXP (x
, 0), 0);
4109 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4110 (OP:SI foo:SI) if OP is NEG or ABS. */
4111 if ((GET_CODE (XEXP (x
, 0)) == ABS
4112 || GET_CODE (XEXP (x
, 0)) == NEG
)
4113 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4114 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4115 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4116 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4117 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4119 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4121 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4122 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4123 && subreg_lowpart_p (XEXP (x
, 0)))
4124 return SUBREG_REG (XEXP (x
, 0));
4126 /* If we know that the value is already truncated, we can
4127 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4128 is nonzero for the corresponding modes. But don't do this
4129 for an (LSHIFTRT (MULT ...)) since this will cause problems
4130 with the umulXi3_highpart patterns. */
4131 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4132 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4133 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4134 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4135 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4136 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4137 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4139 /* A truncate of a comparison can be replaced with a subreg if
4140 STORE_FLAG_VALUE permits. This is like the previous test,
4141 but it works even if the comparison is done in a mode larger
4142 than HOST_BITS_PER_WIDE_INT. */
4143 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4144 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4145 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4146 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4148 /* Similarly, a truncate of a register whose value is a
4149 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4151 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4152 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4153 && (temp
= get_last_value (XEXP (x
, 0)))
4154 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4155 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4159 case FLOAT_TRUNCATE
:
4160 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4161 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4162 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4163 return XEXP (XEXP (x
, 0), 0);
4165 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4166 (OP:SF foo:SF) if OP is NEG or ABS. */
4167 if ((GET_CODE (XEXP (x
, 0)) == ABS
4168 || GET_CODE (XEXP (x
, 0)) == NEG
)
4169 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4170 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4171 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4172 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4174 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4175 is (float_truncate:SF x). */
4176 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4177 && subreg_lowpart_p (XEXP (x
, 0))
4178 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4179 return SUBREG_REG (XEXP (x
, 0));
4184 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4185 using cc0, in which case we want to leave it as a COMPARE
4186 so we can distinguish it from a register-register-copy. */
4187 if (XEXP (x
, 1) == const0_rtx
)
4190 /* x - 0 is the same as x unless x's mode has signed zeros and
4191 allows rounding towards -infinity. Under those conditions,
4193 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4194 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4195 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4201 /* (const (const X)) can become (const X). Do it this way rather than
4202 returning the inner CONST since CONST can be shared with a
4204 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4205 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4210 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4211 can add in an offset. find_split_point will split this address up
4212 again if it doesn't match. */
4213 if (GET_CODE (XEXP (x
, 0)) == HIGH
4214 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4220 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4221 outermost. That's because that's the way indexed addresses are
4222 supposed to appear. This code used to check many more cases, but
4223 they are now checked elsewhere. */
4224 if (GET_CODE (XEXP (x
, 0)) == PLUS
4225 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4226 return gen_binary (PLUS
, mode
,
4227 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4229 XEXP (XEXP (x
, 0), 1));
4231 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4232 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4233 bit-field and can be replaced by either a sign_extend or a
4234 sign_extract. The `and' may be a zero_extend and the two
4235 <c>, -<c> constants may be reversed. */
4236 if (GET_CODE (XEXP (x
, 0)) == XOR
4237 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4238 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4239 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4240 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4241 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4242 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4243 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4244 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4245 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4246 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4247 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4248 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4249 == (unsigned int) i
+ 1))))
4250 return simplify_shift_const
4251 (NULL_RTX
, ASHIFTRT
, mode
,
4252 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4253 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4254 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4255 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4257 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4258 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4259 is 1. This produces better code than the alternative immediately
4261 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4262 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4263 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4264 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4265 XEXP (XEXP (x
, 0), 0),
4266 XEXP (XEXP (x
, 0), 1))))
4268 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4270 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4271 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4272 the bitsize of the mode - 1. This allows simplification of
4273 "a = (b & 8) == 0;" */
4274 if (XEXP (x
, 1) == constm1_rtx
4275 && GET_CODE (XEXP (x
, 0)) != REG
4276 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4277 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4278 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4279 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4280 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4281 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4282 GET_MODE_BITSIZE (mode
) - 1),
4283 GET_MODE_BITSIZE (mode
) - 1);
4285 /* If we are adding two things that have no bits in common, convert
4286 the addition into an IOR. This will often be further simplified,
4287 for example in cases like ((a & 1) + (a & 2)), which can
4290 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4291 && (nonzero_bits (XEXP (x
, 0), mode
)
4292 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4294 /* Try to simplify the expression further. */
4295 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4296 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4298 /* If we could, great. If not, do not go ahead with the IOR
4299 replacement, since PLUS appears in many special purpose
4300 address arithmetic instructions. */
4301 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4307 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4308 by reversing the comparison code if valid. */
4309 if (STORE_FLAG_VALUE
== 1
4310 && XEXP (x
, 0) == const1_rtx
4311 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4312 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4313 XEXP (XEXP (x
, 1), 0),
4314 XEXP (XEXP (x
, 1), 1))))
4317 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4318 (and <foo> (const_int pow2-1)) */
4319 if (GET_CODE (XEXP (x
, 1)) == AND
4320 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4321 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4322 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4323 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4324 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4326 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4328 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4329 return gen_binary (MINUS
, mode
,
4330 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4331 XEXP (XEXP (x
, 1), 0)),
4332 XEXP (XEXP (x
, 1), 1));
4336 /* If we have (mult (plus A B) C), apply the distributive law and then
4337 the inverse distributive law to see if things simplify. This
4338 occurs mostly in addresses, often when unrolling loops. */
4340 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4342 x
= apply_distributive_law
4343 (gen_binary (PLUS
, mode
,
4344 gen_binary (MULT
, mode
,
4345 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4346 gen_binary (MULT
, mode
,
4347 XEXP (XEXP (x
, 0), 1),
4348 copy_rtx (XEXP (x
, 1)))));
4350 if (GET_CODE (x
) != MULT
)
4353 /* Try simplify a*(b/c) as (a*b)/c. */
4354 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4355 && GET_CODE (XEXP (x
, 0)) == DIV
)
4357 rtx tem
= simplify_binary_operation (MULT
, mode
,
4358 XEXP (XEXP (x
, 0), 0),
4361 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4366 /* If this is a divide by a power of two, treat it as a shift if
4367 its first operand is a shift. */
4368 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4369 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4370 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4371 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4372 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4373 || GET_CODE (XEXP (x
, 0)) == ROTATE
4374 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4375 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4379 case GT
: case GTU
: case GE
: case GEU
:
4380 case LT
: case LTU
: case LE
: case LEU
:
4381 case UNEQ
: case LTGT
:
4382 case UNGT
: case UNGE
:
4383 case UNLT
: case UNLE
:
4384 case UNORDERED
: case ORDERED
:
4385 /* If the first operand is a condition code, we can't do anything
4387 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4388 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4390 && XEXP (x
, 0) != cc0_rtx
4394 rtx op0
= XEXP (x
, 0);
4395 rtx op1
= XEXP (x
, 1);
4396 enum rtx_code new_code
;
4398 if (GET_CODE (op0
) == COMPARE
)
4399 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4401 /* Simplify our comparison, if possible. */
4402 new_code
= simplify_comparison (code
, &op0
, &op1
);
4404 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4405 if only the low-order bit is possibly nonzero in X (such as when
4406 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4407 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4408 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4411 Remove any ZERO_EXTRACT we made when thinking this was a
4412 comparison. It may now be simpler to use, e.g., an AND. If a
4413 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4414 the call to make_compound_operation in the SET case. */
4416 if (STORE_FLAG_VALUE
== 1
4417 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4418 && op1
== const0_rtx
4419 && mode
== GET_MODE (op0
)
4420 && nonzero_bits (op0
, mode
) == 1)
4421 return gen_lowpart_for_combine (mode
,
4422 expand_compound_operation (op0
));
4424 else if (STORE_FLAG_VALUE
== 1
4425 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4426 && op1
== const0_rtx
4427 && mode
== GET_MODE (op0
)
4428 && (num_sign_bit_copies (op0
, mode
)
4429 == GET_MODE_BITSIZE (mode
)))
4431 op0
= expand_compound_operation (op0
);
4432 return simplify_gen_unary (NEG
, mode
,
4433 gen_lowpart_for_combine (mode
, op0
),
4437 else if (STORE_FLAG_VALUE
== 1
4438 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4439 && op1
== const0_rtx
4440 && mode
== GET_MODE (op0
)
4441 && nonzero_bits (op0
, mode
) == 1)
4443 op0
= expand_compound_operation (op0
);
4444 return gen_binary (XOR
, mode
,
4445 gen_lowpart_for_combine (mode
, op0
),
4449 else if (STORE_FLAG_VALUE
== 1
4450 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4451 && op1
== const0_rtx
4452 && mode
== GET_MODE (op0
)
4453 && (num_sign_bit_copies (op0
, mode
)
4454 == GET_MODE_BITSIZE (mode
)))
4456 op0
= expand_compound_operation (op0
);
4457 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4460 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4462 if (STORE_FLAG_VALUE
== -1
4463 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4464 && op1
== const0_rtx
4465 && (num_sign_bit_copies (op0
, mode
)
4466 == GET_MODE_BITSIZE (mode
)))
4467 return gen_lowpart_for_combine (mode
,
4468 expand_compound_operation (op0
));
4470 else if (STORE_FLAG_VALUE
== -1
4471 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4472 && op1
== const0_rtx
4473 && mode
== GET_MODE (op0
)
4474 && nonzero_bits (op0
, mode
) == 1)
4476 op0
= expand_compound_operation (op0
);
4477 return simplify_gen_unary (NEG
, mode
,
4478 gen_lowpart_for_combine (mode
, op0
),
4482 else if (STORE_FLAG_VALUE
== -1
4483 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4484 && op1
== const0_rtx
4485 && mode
== GET_MODE (op0
)
4486 && (num_sign_bit_copies (op0
, mode
)
4487 == GET_MODE_BITSIZE (mode
)))
4489 op0
= expand_compound_operation (op0
);
4490 return simplify_gen_unary (NOT
, mode
,
4491 gen_lowpart_for_combine (mode
, op0
),
4495 /* If X is 0/1, (eq X 0) is X-1. */
4496 else if (STORE_FLAG_VALUE
== -1
4497 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4498 && op1
== const0_rtx
4499 && mode
== GET_MODE (op0
)
4500 && nonzero_bits (op0
, mode
) == 1)
4502 op0
= expand_compound_operation (op0
);
4503 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4506 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4507 one bit that might be nonzero, we can convert (ne x 0) to
4508 (ashift x c) where C puts the bit in the sign bit. Remove any
4509 AND with STORE_FLAG_VALUE when we are done, since we are only
4510 going to test the sign bit. */
4511 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4512 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4513 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4514 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4515 && op1
== const0_rtx
4516 && mode
== GET_MODE (op0
)
4517 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4519 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4520 expand_compound_operation (op0
),
4521 GET_MODE_BITSIZE (mode
) - 1 - i
);
4522 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4528 /* If the code changed, return a whole new comparison. */
4529 if (new_code
!= code
)
4530 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4532 /* Otherwise, keep this operation, but maybe change its operands.
4533 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4534 SUBST (XEXP (x
, 0), op0
);
4535 SUBST (XEXP (x
, 1), op1
);
4540 return simplify_if_then_else (x
);
4546 /* If we are processing SET_DEST, we are done. */
4550 return expand_compound_operation (x
);
4553 return simplify_set (x
);
4558 return simplify_logical (x
, last
);
4561 /* (abs (neg <foo>)) -> (abs <foo>) */
4562 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4563 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4565 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4567 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4570 /* If operand is something known to be positive, ignore the ABS. */
4571 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4572 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4573 <= HOST_BITS_PER_WIDE_INT
)
4574 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4575 & ((HOST_WIDE_INT
) 1
4576 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4580 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4581 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4582 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4587 /* (ffs (*_extend <X>)) = (ffs <X>) */
4588 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4589 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4590 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4594 /* (float (sign_extend <X>)) = (float <X>). */
4595 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4596 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4604 /* If this is a shift by a constant amount, simplify it. */
4605 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4606 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4607 INTVAL (XEXP (x
, 1)));
4609 #ifdef SHIFT_COUNT_TRUNCATED
4610 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4612 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4614 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4623 rtx op0
= XEXP (x
, 0);
4624 rtx op1
= XEXP (x
, 1);
4627 if (GET_CODE (op1
) != PARALLEL
)
4629 len
= XVECLEN (op1
, 0);
4631 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4632 && GET_CODE (op0
) == VEC_CONCAT
)
4634 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4636 /* Try to find the element in the VEC_CONCAT. */
4639 if (GET_MODE (op0
) == GET_MODE (x
))
4641 if (GET_CODE (op0
) == VEC_CONCAT
)
4643 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4644 if (op0_size
< offset
)
4645 op0
= XEXP (op0
, 0);
4649 op0
= XEXP (op0
, 1);
4667 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4670 simplify_if_then_else (x
)
4673 enum machine_mode mode
= GET_MODE (x
);
4674 rtx cond
= XEXP (x
, 0);
4675 rtx true_rtx
= XEXP (x
, 1);
4676 rtx false_rtx
= XEXP (x
, 2);
4677 enum rtx_code true_code
= GET_CODE (cond
);
4678 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4681 enum rtx_code false_code
;
4684 /* Simplify storing of the truth value. */
4685 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4686 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4688 /* Also when the truth value has to be reversed. */
4690 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4691 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4695 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4696 in it is being compared against certain values. Get the true and false
4697 comparisons and see if that says anything about the value of each arm. */
4700 && ((false_code
= combine_reversed_comparison_code (cond
))
4702 && GET_CODE (XEXP (cond
, 0)) == REG
)
4705 rtx from
= XEXP (cond
, 0);
4706 rtx true_val
= XEXP (cond
, 1);
4707 rtx false_val
= true_val
;
4710 /* If FALSE_CODE is EQ, swap the codes and arms. */
4712 if (false_code
== EQ
)
4714 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4715 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4718 /* If we are comparing against zero and the expression being tested has
4719 only a single bit that might be nonzero, that is its value when it is
4720 not equal to zero. Similarly if it is known to be -1 or 0. */
4722 if (true_code
== EQ
&& true_val
== const0_rtx
4723 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4724 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4725 else if (true_code
== EQ
&& true_val
== const0_rtx
4726 && (num_sign_bit_copies (from
, GET_MODE (from
))
4727 == GET_MODE_BITSIZE (GET_MODE (from
))))
4728 false_code
= EQ
, false_val
= constm1_rtx
;
4730 /* Now simplify an arm if we know the value of the register in the
4731 branch and it is used in the arm. Be careful due to the potential
4732 of locally-shared RTL. */
4734 if (reg_mentioned_p (from
, true_rtx
))
4735 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4737 pc_rtx
, pc_rtx
, 0, 0);
4738 if (reg_mentioned_p (from
, false_rtx
))
4739 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4741 pc_rtx
, pc_rtx
, 0, 0);
4743 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4744 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4746 true_rtx
= XEXP (x
, 1);
4747 false_rtx
= XEXP (x
, 2);
4748 true_code
= GET_CODE (cond
);
4751 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4752 reversed, do so to avoid needing two sets of patterns for
4753 subtract-and-branch insns. Similarly if we have a constant in the true
4754 arm, the false arm is the same as the first operand of the comparison, or
4755 the false arm is more complicated than the true arm. */
4758 && combine_reversed_comparison_code (cond
) != UNKNOWN
4759 && (true_rtx
== pc_rtx
4760 || (CONSTANT_P (true_rtx
)
4761 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4762 || true_rtx
== const0_rtx
4763 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4764 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4765 || (GET_CODE (true_rtx
) == SUBREG
4766 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4767 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4768 || reg_mentioned_p (true_rtx
, false_rtx
)
4769 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4771 true_code
= reversed_comparison_code (cond
, NULL
);
4773 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4776 SUBST (XEXP (x
, 1), false_rtx
);
4777 SUBST (XEXP (x
, 2), true_rtx
);
4779 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4782 /* It is possible that the conditional has been simplified out. */
4783 true_code
= GET_CODE (cond
);
4784 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4787 /* If the two arms are identical, we don't need the comparison. */
4789 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4792 /* Convert a == b ? b : a to "a". */
4793 if (true_code
== EQ
&& ! side_effects_p (cond
)
4794 && !HONOR_NANS (mode
)
4795 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4796 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4798 else if (true_code
== NE
&& ! side_effects_p (cond
)
4799 && !HONOR_NANS (mode
)
4800 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4801 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4804 /* Look for cases where we have (abs x) or (neg (abs X)). */
4806 if (GET_MODE_CLASS (mode
) == MODE_INT
4807 && GET_CODE (false_rtx
) == NEG
4808 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4810 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4811 && ! side_effects_p (true_rtx
))
4816 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4820 simplify_gen_unary (NEG
, mode
,
4821 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4827 /* Look for MIN or MAX. */
4829 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4831 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4832 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4833 && ! side_effects_p (cond
))
4838 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4841 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4844 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4847 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4852 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4853 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4854 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4855 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4856 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4857 neither 1 or -1, but it isn't worth checking for. */
4859 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4860 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4862 rtx t
= make_compound_operation (true_rtx
, SET
);
4863 rtx f
= make_compound_operation (false_rtx
, SET
);
4864 rtx cond_op0
= XEXP (cond
, 0);
4865 rtx cond_op1
= XEXP (cond
, 1);
4866 enum rtx_code op
= NIL
, extend_op
= NIL
;
4867 enum machine_mode m
= mode
;
4868 rtx z
= 0, c1
= NULL_RTX
;
4870 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4871 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4872 || GET_CODE (t
) == ASHIFT
4873 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4874 && rtx_equal_p (XEXP (t
, 0), f
))
4875 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4877 /* If an identity-zero op is commutative, check whether there
4878 would be a match if we swapped the operands. */
4879 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4880 || GET_CODE (t
) == XOR
)
4881 && rtx_equal_p (XEXP (t
, 1), f
))
4882 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4883 else if (GET_CODE (t
) == SIGN_EXTEND
4884 && (GET_CODE (XEXP (t
, 0)) == PLUS
4885 || GET_CODE (XEXP (t
, 0)) == MINUS
4886 || GET_CODE (XEXP (t
, 0)) == IOR
4887 || GET_CODE (XEXP (t
, 0)) == XOR
4888 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4889 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4890 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4891 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4892 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4893 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4894 && (num_sign_bit_copies (f
, GET_MODE (f
))
4896 (GET_MODE_BITSIZE (mode
)
4897 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4899 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4900 extend_op
= SIGN_EXTEND
;
4901 m
= GET_MODE (XEXP (t
, 0));
4903 else if (GET_CODE (t
) == SIGN_EXTEND
4904 && (GET_CODE (XEXP (t
, 0)) == PLUS
4905 || GET_CODE (XEXP (t
, 0)) == IOR
4906 || GET_CODE (XEXP (t
, 0)) == XOR
)
4907 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4908 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4909 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4910 && (num_sign_bit_copies (f
, GET_MODE (f
))
4912 (GET_MODE_BITSIZE (mode
)
4913 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4915 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4916 extend_op
= SIGN_EXTEND
;
4917 m
= GET_MODE (XEXP (t
, 0));
4919 else if (GET_CODE (t
) == ZERO_EXTEND
4920 && (GET_CODE (XEXP (t
, 0)) == PLUS
4921 || GET_CODE (XEXP (t
, 0)) == MINUS
4922 || GET_CODE (XEXP (t
, 0)) == IOR
4923 || GET_CODE (XEXP (t
, 0)) == XOR
4924 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4925 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4926 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4927 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4928 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4929 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4930 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4931 && ((nonzero_bits (f
, GET_MODE (f
))
4932 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4935 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4936 extend_op
= ZERO_EXTEND
;
4937 m
= GET_MODE (XEXP (t
, 0));
4939 else if (GET_CODE (t
) == ZERO_EXTEND
4940 && (GET_CODE (XEXP (t
, 0)) == PLUS
4941 || GET_CODE (XEXP (t
, 0)) == IOR
4942 || GET_CODE (XEXP (t
, 0)) == XOR
)
4943 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4944 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4945 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4946 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4947 && ((nonzero_bits (f
, GET_MODE (f
))
4948 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4951 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4952 extend_op
= ZERO_EXTEND
;
4953 m
= GET_MODE (XEXP (t
, 0));
4958 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4959 pc_rtx
, pc_rtx
, 0, 0);
4960 temp
= gen_binary (MULT
, m
, temp
,
4961 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4962 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4963 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4965 if (extend_op
!= NIL
)
4966 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4972 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4973 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4974 negation of a single bit, we can convert this operation to a shift. We
4975 can actually do this more generally, but it doesn't seem worth it. */
4977 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4978 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4979 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4980 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4981 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4982 == GET_MODE_BITSIZE (mode
))
4983 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4985 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4986 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4991 /* Simplify X, a SET expression. Return the new expression. */
4997 rtx src
= SET_SRC (x
);
4998 rtx dest
= SET_DEST (x
);
4999 enum machine_mode mode
5000 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5004 /* (set (pc) (return)) gets written as (return). */
5005 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5008 /* Now that we know for sure which bits of SRC we are using, see if we can
5009 simplify the expression for the object knowing that we only need the
5012 if (GET_MODE_CLASS (mode
) == MODE_INT
5013 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5015 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5016 SUBST (SET_SRC (x
), src
);
5019 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5020 the comparison result and try to simplify it unless we already have used
5021 undobuf.other_insn. */
5022 if ((GET_MODE_CLASS (mode
) == MODE_CC
5023 || GET_CODE (src
) == COMPARE
5025 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5026 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5027 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
5028 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5030 enum rtx_code old_code
= GET_CODE (*cc_use
);
5031 enum rtx_code new_code
;
5033 int other_changed
= 0;
5034 enum machine_mode compare_mode
= GET_MODE (dest
);
5035 enum machine_mode tmp_mode
;
5037 if (GET_CODE (src
) == COMPARE
)
5038 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5040 op0
= src
, op1
= const0_rtx
;
5042 /* Check whether the comparison is known at compile time. */
5043 if (GET_MODE (op0
) != VOIDmode
)
5044 tmp_mode
= GET_MODE (op0
);
5045 else if (GET_MODE (op1
) != VOIDmode
)
5046 tmp_mode
= GET_MODE (op1
);
5048 tmp_mode
= compare_mode
;
5049 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5050 if (tmp
!= NULL_RTX
)
5052 rtx pat
= PATTERN (other_insn
);
5053 undobuf
.other_insn
= other_insn
;
5054 SUBST (*cc_use
, tmp
);
5056 /* Attempt to simplify CC user. */
5057 if (GET_CODE (pat
) == SET
)
5059 rtx
new = simplify_rtx (SET_SRC (pat
));
5060 if (new != NULL_RTX
)
5061 SUBST (SET_SRC (pat
), new);
5064 /* Convert X into a no-op move. */
5065 SUBST (SET_DEST (x
), pc_rtx
);
5066 SUBST (SET_SRC (x
), pc_rtx
);
5070 /* Simplify our comparison, if possible. */
5071 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5073 #ifdef EXTRA_CC_MODES
5074 /* If this machine has CC modes other than CCmode, check to see if we
5075 need to use a different CC mode here. */
5076 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5077 #endif /* EXTRA_CC_MODES */
5079 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5080 /* If the mode changed, we have to change SET_DEST, the mode in the
5081 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5082 a hard register, just build new versions with the proper mode. If it
5083 is a pseudo, we lose unless it is only time we set the pseudo, in
5084 which case we can safely change its mode. */
5085 if (compare_mode
!= GET_MODE (dest
))
5087 unsigned int regno
= REGNO (dest
);
5088 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5090 if (regno
< FIRST_PSEUDO_REGISTER
5091 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5093 if (regno
>= FIRST_PSEUDO_REGISTER
)
5094 SUBST (regno_reg_rtx
[regno
], new_dest
);
5096 SUBST (SET_DEST (x
), new_dest
);
5097 SUBST (XEXP (*cc_use
, 0), new_dest
);
5105 /* If the code changed, we have to build a new comparison in
5106 undobuf.other_insn. */
5107 if (new_code
!= old_code
)
5109 unsigned HOST_WIDE_INT mask
;
5111 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5114 /* If the only change we made was to change an EQ into an NE or
5115 vice versa, OP0 has only one bit that might be nonzero, and OP1
5116 is zero, check if changing the user of the condition code will
5117 produce a valid insn. If it won't, we can keep the original code
5118 in that insn by surrounding our operation with an XOR. */
5120 if (((old_code
== NE
&& new_code
== EQ
)
5121 || (old_code
== EQ
&& new_code
== NE
))
5122 && ! other_changed
&& op1
== const0_rtx
5123 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5124 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5126 rtx pat
= PATTERN (other_insn
), note
= 0;
5128 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5129 && ! check_asm_operands (pat
)))
5131 PUT_CODE (*cc_use
, old_code
);
5134 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5142 undobuf
.other_insn
= other_insn
;
5145 /* If we are now comparing against zero, change our source if
5146 needed. If we do not use cc0, we always have a COMPARE. */
5147 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5149 SUBST (SET_SRC (x
), op0
);
5155 /* Otherwise, if we didn't previously have a COMPARE in the
5156 correct mode, we need one. */
5157 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5159 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5164 /* Otherwise, update the COMPARE if needed. */
5165 SUBST (XEXP (src
, 0), op0
);
5166 SUBST (XEXP (src
, 1), op1
);
5171 /* Get SET_SRC in a form where we have placed back any
5172 compound expressions. Then do the checks below. */
5173 src
= make_compound_operation (src
, SET
);
5174 SUBST (SET_SRC (x
), src
);
5177 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5178 and X being a REG or (subreg (reg)), we may be able to convert this to
5179 (set (subreg:m2 x) (op)).
5181 We can always do this if M1 is narrower than M2 because that means that
5182 we only care about the low bits of the result.
5184 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5185 perform a narrower operation than requested since the high-order bits will
5186 be undefined. On machine where it is defined, this transformation is safe
5187 as long as M1 and M2 have the same number of words. */
5189 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5190 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5191 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5193 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5194 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5195 #ifndef WORD_REGISTER_OPERATIONS
5196 && (GET_MODE_SIZE (GET_MODE (src
))
5197 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5199 #ifdef CANNOT_CHANGE_MODE_CLASS
5200 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5201 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5203 GET_MODE (SUBREG_REG (src
))))
5205 && (GET_CODE (dest
) == REG
5206 || (GET_CODE (dest
) == SUBREG
5207 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5209 SUBST (SET_DEST (x
),
5210 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5212 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5214 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5218 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5221 && GET_CODE (src
) == SUBREG
5222 && subreg_lowpart_p (src
)
5223 && (GET_MODE_BITSIZE (GET_MODE (src
))
5224 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5226 rtx inner
= SUBREG_REG (src
);
5227 enum machine_mode inner_mode
= GET_MODE (inner
);
5229 /* Here we make sure that we don't have a sign bit on. */
5230 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5231 && (nonzero_bits (inner
, inner_mode
)
5232 < ((unsigned HOST_WIDE_INT
) 1
5233 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5235 SUBST (SET_SRC (x
), inner
);
5241 #ifdef LOAD_EXTEND_OP
5242 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5243 would require a paradoxical subreg. Replace the subreg with a
5244 zero_extend to avoid the reload that would otherwise be required. */
5246 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5247 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5248 && SUBREG_BYTE (src
) == 0
5249 && (GET_MODE_SIZE (GET_MODE (src
))
5250 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5251 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5254 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5255 GET_MODE (src
), SUBREG_REG (src
)));
5261 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5262 are comparing an item known to be 0 or -1 against 0, use a logical
5263 operation instead. Check for one of the arms being an IOR of the other
5264 arm with some value. We compute three terms to be IOR'ed together. In
5265 practice, at most two will be nonzero. Then we do the IOR's. */
5267 if (GET_CODE (dest
) != PC
5268 && GET_CODE (src
) == IF_THEN_ELSE
5269 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5270 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5271 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5272 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5273 #ifdef HAVE_conditional_move
5274 && ! can_conditionally_move_p (GET_MODE (src
))
5276 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5277 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5278 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5279 && ! side_effects_p (src
))
5281 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5282 ? XEXP (src
, 1) : XEXP (src
, 2));
5283 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5284 ? XEXP (src
, 2) : XEXP (src
, 1));
5285 rtx term1
= const0_rtx
, term2
, term3
;
5287 if (GET_CODE (true_rtx
) == IOR
5288 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5289 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5290 else if (GET_CODE (true_rtx
) == IOR
5291 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5292 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5293 else if (GET_CODE (false_rtx
) == IOR
5294 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5295 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5296 else if (GET_CODE (false_rtx
) == IOR
5297 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5298 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5300 term2
= gen_binary (AND
, GET_MODE (src
),
5301 XEXP (XEXP (src
, 0), 0), true_rtx
);
5302 term3
= gen_binary (AND
, GET_MODE (src
),
5303 simplify_gen_unary (NOT
, GET_MODE (src
),
5304 XEXP (XEXP (src
, 0), 0),
5309 gen_binary (IOR
, GET_MODE (src
),
5310 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5316 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5317 whole thing fail. */
5318 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5320 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5323 /* Convert this into a field assignment operation, if possible. */
5324 return make_field_assignment (x
);
5327 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5328 result. LAST is nonzero if this is the last retry. */
5331 simplify_logical (x
, last
)
5335 enum machine_mode mode
= GET_MODE (x
);
5336 rtx op0
= XEXP (x
, 0);
5337 rtx op1
= XEXP (x
, 1);
5340 switch (GET_CODE (x
))
5343 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5344 insn (and may simplify more). */
5345 if (GET_CODE (op0
) == XOR
5346 && rtx_equal_p (XEXP (op0
, 0), op1
)
5347 && ! side_effects_p (op1
))
5348 x
= gen_binary (AND
, mode
,
5349 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5352 if (GET_CODE (op0
) == XOR
5353 && rtx_equal_p (XEXP (op0
, 1), op1
)
5354 && ! side_effects_p (op1
))
5355 x
= gen_binary (AND
, mode
,
5356 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5359 /* Similarly for (~(A ^ B)) & A. */
5360 if (GET_CODE (op0
) == NOT
5361 && GET_CODE (XEXP (op0
, 0)) == XOR
5362 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5363 && ! side_effects_p (op1
))
5364 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5366 if (GET_CODE (op0
) == NOT
5367 && GET_CODE (XEXP (op0
, 0)) == XOR
5368 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5369 && ! side_effects_p (op1
))
5370 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5372 /* We can call simplify_and_const_int only if we don't lose
5373 any (sign) bits when converting INTVAL (op1) to
5374 "unsigned HOST_WIDE_INT". */
5375 if (GET_CODE (op1
) == CONST_INT
5376 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5377 || INTVAL (op1
) > 0))
5379 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5381 /* If we have (ior (and (X C1) C2)) and the next restart would be
5382 the last, simplify this by making C1 as small as possible
5385 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5386 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5387 && GET_CODE (op1
) == CONST_INT
)
5388 return gen_binary (IOR
, mode
,
5389 gen_binary (AND
, mode
, XEXP (op0
, 0),
5390 GEN_INT (INTVAL (XEXP (op0
, 1))
5391 & ~INTVAL (op1
))), op1
);
5393 if (GET_CODE (x
) != AND
)
5396 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5397 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5398 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5401 /* Convert (A | B) & A to A. */
5402 if (GET_CODE (op0
) == IOR
5403 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5404 || rtx_equal_p (XEXP (op0
, 1), op1
))
5405 && ! side_effects_p (XEXP (op0
, 0))
5406 && ! side_effects_p (XEXP (op0
, 1)))
5409 /* In the following group of tests (and those in case IOR below),
5410 we start with some combination of logical operations and apply
5411 the distributive law followed by the inverse distributive law.
5412 Most of the time, this results in no change. However, if some of
5413 the operands are the same or inverses of each other, simplifications
5416 For example, (and (ior A B) (not B)) can occur as the result of
5417 expanding a bit field assignment. When we apply the distributive
5418 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5419 which then simplifies to (and (A (not B))).
5421 If we have (and (ior A B) C), apply the distributive law and then
5422 the inverse distributive law to see if things simplify. */
5424 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5426 x
= apply_distributive_law
5427 (gen_binary (GET_CODE (op0
), mode
,
5428 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5429 gen_binary (AND
, mode
, XEXP (op0
, 1),
5431 if (GET_CODE (x
) != AND
)
5435 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5436 return apply_distributive_law
5437 (gen_binary (GET_CODE (op1
), mode
,
5438 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5439 gen_binary (AND
, mode
, XEXP (op1
, 1),
5442 /* Similarly, taking advantage of the fact that
5443 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5445 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5446 return apply_distributive_law
5447 (gen_binary (XOR
, mode
,
5448 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5449 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5452 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5453 return apply_distributive_law
5454 (gen_binary (XOR
, mode
,
5455 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5456 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5460 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5461 if (GET_CODE (op1
) == CONST_INT
5462 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5463 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5466 /* Convert (A & B) | A to A. */
5467 if (GET_CODE (op0
) == AND
5468 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5469 || rtx_equal_p (XEXP (op0
, 1), op1
))
5470 && ! side_effects_p (XEXP (op0
, 0))
5471 && ! side_effects_p (XEXP (op0
, 1)))
5474 /* If we have (ior (and A B) C), apply the distributive law and then
5475 the inverse distributive law to see if things simplify. */
5477 if (GET_CODE (op0
) == AND
)
5479 x
= apply_distributive_law
5480 (gen_binary (AND
, mode
,
5481 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5482 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5485 if (GET_CODE (x
) != IOR
)
5489 if (GET_CODE (op1
) == AND
)
5491 x
= apply_distributive_law
5492 (gen_binary (AND
, mode
,
5493 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5494 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5497 if (GET_CODE (x
) != IOR
)
5501 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5502 mode size to (rotate A CX). */
5504 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5505 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5506 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5507 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5508 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5509 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5510 == GET_MODE_BITSIZE (mode
)))
5511 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5512 (GET_CODE (op0
) == ASHIFT
5513 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5515 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5516 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5517 does not affect any of the bits in OP1, it can really be done
5518 as a PLUS and we can associate. We do this by seeing if OP1
5519 can be safely shifted left C bits. */
5520 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5521 && GET_CODE (XEXP (op0
, 0)) == PLUS
5522 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5523 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5524 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5526 int count
= INTVAL (XEXP (op0
, 1));
5527 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5529 if (mask
>> count
== INTVAL (op1
)
5530 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5532 SUBST (XEXP (XEXP (op0
, 0), 1),
5533 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5540 /* If we are XORing two things that have no bits in common,
5541 convert them into an IOR. This helps to detect rotation encoded
5542 using those methods and possibly other simplifications. */
5544 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5545 && (nonzero_bits (op0
, mode
)
5546 & nonzero_bits (op1
, mode
)) == 0)
5547 return (gen_binary (IOR
, mode
, op0
, op1
));
5549 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5550 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5553 int num_negated
= 0;
5555 if (GET_CODE (op0
) == NOT
)
5556 num_negated
++, op0
= XEXP (op0
, 0);
5557 if (GET_CODE (op1
) == NOT
)
5558 num_negated
++, op1
= XEXP (op1
, 0);
5560 if (num_negated
== 2)
5562 SUBST (XEXP (x
, 0), op0
);
5563 SUBST (XEXP (x
, 1), op1
);
5565 else if (num_negated
== 1)
5567 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5571 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5572 correspond to a machine insn or result in further simplifications
5573 if B is a constant. */
5575 if (GET_CODE (op0
) == AND
5576 && rtx_equal_p (XEXP (op0
, 1), op1
)
5577 && ! side_effects_p (op1
))
5578 return gen_binary (AND
, mode
,
5579 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5582 else if (GET_CODE (op0
) == AND
5583 && rtx_equal_p (XEXP (op0
, 0), op1
)
5584 && ! side_effects_p (op1
))
5585 return gen_binary (AND
, mode
,
5586 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5589 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5590 comparison if STORE_FLAG_VALUE is 1. */
5591 if (STORE_FLAG_VALUE
== 1
5592 && op1
== const1_rtx
5593 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5594 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5598 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5599 is (lt foo (const_int 0)), so we can perform the above
5600 simplification if STORE_FLAG_VALUE is 1. */
5602 if (STORE_FLAG_VALUE
== 1
5603 && op1
== const1_rtx
5604 && GET_CODE (op0
) == LSHIFTRT
5605 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5606 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5607 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5609 /* (xor (comparison foo bar) (const_int sign-bit))
5610 when STORE_FLAG_VALUE is the sign bit. */
5611 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5612 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5613 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5614 && op1
== const_true_rtx
5615 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5616 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5629 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5630 operations" because they can be replaced with two more basic operations.
5631 ZERO_EXTEND is also considered "compound" because it can be replaced with
5632 an AND operation, which is simpler, though only one operation.
5634 The function expand_compound_operation is called with an rtx expression
5635 and will convert it to the appropriate shifts and AND operations,
5636 simplifying at each stage.
5638 The function make_compound_operation is called to convert an expression
5639 consisting of shifts and ANDs into the equivalent compound expression.
5640 It is the inverse of this function, loosely speaking. */
5643 expand_compound_operation (x
)
5646 unsigned HOST_WIDE_INT pos
= 0, len
;
5648 unsigned int modewidth
;
5651 switch (GET_CODE (x
))
5656 /* We can't necessarily use a const_int for a multiword mode;
5657 it depends on implicitly extending the value.
5658 Since we don't know the right way to extend it,
5659 we can't tell whether the implicit way is right.
5661 Even for a mode that is no wider than a const_int,
5662 we can't win, because we need to sign extend one of its bits through
5663 the rest of it, and we don't know which bit. */
5664 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5667 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5668 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5669 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5670 reloaded. If not for that, MEM's would very rarely be safe.
5672 Reject MODEs bigger than a word, because we might not be able
5673 to reference a two-register group starting with an arbitrary register
5674 (and currently gen_lowpart might crash for a SUBREG). */
5676 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5679 /* Reject MODEs that aren't scalar integers because turning vector
5680 or complex modes into shifts causes problems. */
5682 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5685 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5686 /* If the inner object has VOIDmode (the only way this can happen
5687 is if it is an ASM_OPERANDS), we can't do anything since we don't
5688 know how much masking to do. */
5697 /* If the operand is a CLOBBER, just return it. */
5698 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5701 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5702 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5703 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5706 /* Reject MODEs that aren't scalar integers because turning vector
5707 or complex modes into shifts causes problems. */
5709 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5712 len
= INTVAL (XEXP (x
, 1));
5713 pos
= INTVAL (XEXP (x
, 2));
5715 /* If this goes outside the object being extracted, replace the object
5716 with a (use (mem ...)) construct that only combine understands
5717 and is used only for this purpose. */
5718 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5719 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5721 if (BITS_BIG_ENDIAN
)
5722 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5729 /* Convert sign extension to zero extension, if we know that the high
5730 bit is not set, as this is easier to optimize. It will be converted
5731 back to cheaper alternative in make_extraction. */
5732 if (GET_CODE (x
) == SIGN_EXTEND
5733 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5734 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5735 & ~(((unsigned HOST_WIDE_INT
)
5736 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5740 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5741 return expand_compound_operation (temp
);
5744 /* We can optimize some special cases of ZERO_EXTEND. */
5745 if (GET_CODE (x
) == ZERO_EXTEND
)
5747 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5748 know that the last value didn't have any inappropriate bits
5750 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5751 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5752 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5753 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5754 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5755 return XEXP (XEXP (x
, 0), 0);
5757 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5758 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5759 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5760 && subreg_lowpart_p (XEXP (x
, 0))
5761 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5762 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5763 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5764 return SUBREG_REG (XEXP (x
, 0));
5766 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5767 is a comparison and STORE_FLAG_VALUE permits. This is like
5768 the first case, but it works even when GET_MODE (x) is larger
5769 than HOST_WIDE_INT. */
5770 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5771 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5772 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5773 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5774 <= HOST_BITS_PER_WIDE_INT
)
5775 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5776 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5777 return XEXP (XEXP (x
, 0), 0);
5779 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5780 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5781 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5782 && subreg_lowpart_p (XEXP (x
, 0))
5783 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5784 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5785 <= HOST_BITS_PER_WIDE_INT
)
5786 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5787 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5788 return SUBREG_REG (XEXP (x
, 0));
5792 /* If we reach here, we want to return a pair of shifts. The inner
5793 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5794 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5795 logical depending on the value of UNSIGNEDP.
5797 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5798 converted into an AND of a shift.
5800 We must check for the case where the left shift would have a negative
5801 count. This can happen in a case like (x >> 31) & 255 on machines
5802 that can't shift by a constant. On those machines, we would first
5803 combine the shift with the AND to produce a variable-position
5804 extraction. Then the constant of 31 would be substituted in to produce
5805 a such a position. */
5807 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5808 if (modewidth
+ len
>= pos
)
5809 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5811 simplify_shift_const (NULL_RTX
, ASHIFT
,
5814 modewidth
- pos
- len
),
5817 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5818 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5819 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5822 ((HOST_WIDE_INT
) 1 << len
) - 1);
5824 /* Any other cases we can't handle. */
5827 /* If we couldn't do this for some reason, return the original
5829 if (GET_CODE (tem
) == CLOBBER
)
5835 /* X is a SET which contains an assignment of one object into
5836 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5837 or certain SUBREGS). If possible, convert it into a series of
5840 We half-heartedly support variable positions, but do not at all
5841 support variable lengths. */
5844 expand_field_assignment (x
)
5848 rtx pos
; /* Always counts from low bit. */
5851 enum machine_mode compute_mode
;
5853 /* Loop until we find something we can't simplify. */
5856 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5857 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5859 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5860 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5861 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5863 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5864 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5866 inner
= XEXP (SET_DEST (x
), 0);
5867 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5868 pos
= XEXP (SET_DEST (x
), 2);
5870 /* If the position is constant and spans the width of INNER,
5871 surround INNER with a USE to indicate this. */
5872 if (GET_CODE (pos
) == CONST_INT
5873 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5874 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5876 if (BITS_BIG_ENDIAN
)
5878 if (GET_CODE (pos
) == CONST_INT
)
5879 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5881 else if (GET_CODE (pos
) == MINUS
5882 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5883 && (INTVAL (XEXP (pos
, 1))
5884 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5885 /* If position is ADJUST - X, new position is X. */
5886 pos
= XEXP (pos
, 0);
5888 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5889 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5895 /* A SUBREG between two modes that occupy the same numbers of words
5896 can be done by moving the SUBREG to the source. */
5897 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5898 /* We need SUBREGs to compute nonzero_bits properly. */
5899 && nonzero_sign_valid
5900 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5901 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5902 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5903 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5905 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5906 gen_lowpart_for_combine
5907 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5914 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5915 inner
= SUBREG_REG (inner
);
5917 compute_mode
= GET_MODE (inner
);
5919 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5920 if (! SCALAR_INT_MODE_P (compute_mode
))
5922 enum machine_mode imode
;
5924 /* Don't do anything for vector or complex integral types. */
5925 if (! FLOAT_MODE_P (compute_mode
))
5928 /* Try to find an integral mode to pun with. */
5929 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5930 if (imode
== BLKmode
)
5933 compute_mode
= imode
;
5934 inner
= gen_lowpart_for_combine (imode
, inner
);
5937 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5938 if (len
< HOST_BITS_PER_WIDE_INT
)
5939 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5943 /* Now compute the equivalent expression. Make a copy of INNER
5944 for the SET_DEST in case it is a MEM into which we will substitute;
5945 we don't want shared RTL in that case. */
5947 (VOIDmode
, copy_rtx (inner
),
5948 gen_binary (IOR
, compute_mode
,
5949 gen_binary (AND
, compute_mode
,
5950 simplify_gen_unary (NOT
, compute_mode
,
5956 gen_binary (ASHIFT
, compute_mode
,
5957 gen_binary (AND
, compute_mode
,
5958 gen_lowpart_for_combine
5959 (compute_mode
, SET_SRC (x
)),
5967 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5968 it is an RTX that represents a variable starting position; otherwise,
5969 POS is the (constant) starting bit position (counted from the LSB).
5971 INNER may be a USE. This will occur when we started with a bitfield
5972 that went outside the boundary of the object in memory, which is
5973 allowed on most machines. To isolate this case, we produce a USE
5974 whose mode is wide enough and surround the MEM with it. The only
5975 code that understands the USE is this routine. If it is not removed,
5976 it will cause the resulting insn not to match.
5978 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5981 IN_DEST is nonzero if this is a reference in the destination of a
5982 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5983 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5986 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5987 ZERO_EXTRACT should be built even for bits starting at bit 0.
5989 MODE is the desired mode of the result (if IN_DEST == 0).
5991 The result is an RTX for the extraction or NULL_RTX if the target
5995 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5996 unsignedp
, in_dest
, in_compare
)
5997 enum machine_mode mode
;
6001 unsigned HOST_WIDE_INT len
;
6003 int in_dest
, in_compare
;
6005 /* This mode describes the size of the storage area
6006 to fetch the overall value from. Within that, we
6007 ignore the POS lowest bits, etc. */
6008 enum machine_mode is_mode
= GET_MODE (inner
);
6009 enum machine_mode inner_mode
;
6010 enum machine_mode wanted_inner_mode
= byte_mode
;
6011 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6012 enum machine_mode pos_mode
= word_mode
;
6013 enum machine_mode extraction_mode
= word_mode
;
6014 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6017 rtx orig_pos_rtx
= pos_rtx
;
6018 HOST_WIDE_INT orig_pos
;
6020 /* Get some information about INNER and get the innermost object. */
6021 if (GET_CODE (inner
) == USE
)
6022 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6023 /* We don't need to adjust the position because we set up the USE
6024 to pretend that it was a full-word object. */
6025 spans_byte
= 1, inner
= XEXP (inner
, 0);
6026 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6028 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6029 consider just the QI as the memory to extract from.
6030 The subreg adds or removes high bits; its mode is
6031 irrelevant to the meaning of this extraction,
6032 since POS and LEN count from the lsb. */
6033 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
6034 is_mode
= GET_MODE (SUBREG_REG (inner
));
6035 inner
= SUBREG_REG (inner
);
6037 else if (GET_CODE (inner
) == ASHIFT
6038 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6039 && pos_rtx
== 0 && pos
== 0
6040 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6042 /* We're extracting the least significant bits of an rtx
6043 (ashift X (const_int C)), where LEN > C. Extract the
6044 least significant (LEN - C) bits of X, giving an rtx
6045 whose mode is MODE, then shift it left C times. */
6046 new = make_extraction (mode
, XEXP (inner
, 0),
6047 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6048 unsignedp
, in_dest
, in_compare
);
6050 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6053 inner_mode
= GET_MODE (inner
);
6055 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6056 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6058 /* See if this can be done without an extraction. We never can if the
6059 width of the field is not the same as that of some integer mode. For
6060 registers, we can only avoid the extraction if the position is at the
6061 low-order bit and this is either not in the destination or we have the
6062 appropriate STRICT_LOW_PART operation available.
6064 For MEM, we can avoid an extract if the field starts on an appropriate
6065 boundary and we can change the mode of the memory reference. However,
6066 we cannot directly access the MEM if we have a USE and the underlying
6067 MEM is not TMODE. This combination means that MEM was being used in a
6068 context where bits outside its mode were being referenced; that is only
6069 valid in bit-field insns. */
6071 if (tmode
!= BLKmode
6072 && ! (spans_byte
&& inner_mode
!= tmode
)
6073 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6074 && GET_CODE (inner
) != MEM
6076 || (GET_CODE (inner
) == REG
6077 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6078 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6080 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6081 : BITS_PER_UNIT
)) == 0
6082 /* We can't do this if we are widening INNER_MODE (it
6083 may not be aligned, for one thing). */
6084 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6085 && (inner_mode
== tmode
6086 || (! mode_dependent_address_p (XEXP (inner
, 0))
6087 && ! MEM_VOLATILE_P (inner
))))))
6089 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6090 field. If the original and current mode are the same, we need not
6091 adjust the offset. Otherwise, we do if bytes big endian.
6093 If INNER is not a MEM, get a piece consisting of just the field
6094 of interest (in this case POS % BITS_PER_WORD must be 0). */
6096 if (GET_CODE (inner
) == MEM
)
6098 HOST_WIDE_INT offset
;
6100 /* POS counts from lsb, but make OFFSET count in memory order. */
6101 if (BYTES_BIG_ENDIAN
)
6102 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6104 offset
= pos
/ BITS_PER_UNIT
;
6106 new = adjust_address_nv (inner
, tmode
, offset
);
6108 else if (GET_CODE (inner
) == REG
)
6110 /* We can't call gen_lowpart_for_combine here since we always want
6111 a SUBREG and it would sometimes return a new hard register. */
6112 if (tmode
!= inner_mode
)
6114 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6116 if (WORDS_BIG_ENDIAN
6117 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6118 final_word
= ((GET_MODE_SIZE (inner_mode
)
6119 - GET_MODE_SIZE (tmode
))
6120 / UNITS_PER_WORD
) - final_word
;
6122 final_word
*= UNITS_PER_WORD
;
6123 if (BYTES_BIG_ENDIAN
&&
6124 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6125 final_word
+= (GET_MODE_SIZE (inner_mode
)
6126 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6128 /* Avoid creating invalid subregs, for example when
6129 simplifying (x>>32)&255. */
6130 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6133 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6139 new = force_to_mode (inner
, tmode
,
6140 len
>= HOST_BITS_PER_WIDE_INT
6141 ? ~(unsigned HOST_WIDE_INT
) 0
6142 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6145 /* If this extraction is going into the destination of a SET,
6146 make a STRICT_LOW_PART unless we made a MEM. */
6149 return (GET_CODE (new) == MEM
? new
6150 : (GET_CODE (new) != SUBREG
6151 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6152 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6157 if (GET_CODE (new) == CONST_INT
)
6158 return gen_int_mode (INTVAL (new), mode
);
6160 /* If we know that no extraneous bits are set, and that the high
6161 bit is not set, convert the extraction to the cheaper of
6162 sign and zero extension, that are equivalent in these cases. */
6163 if (flag_expensive_optimizations
6164 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6165 && ((nonzero_bits (new, tmode
)
6166 & ~(((unsigned HOST_WIDE_INT
)
6167 GET_MODE_MASK (tmode
))
6171 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6172 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6174 /* Prefer ZERO_EXTENSION, since it gives more information to
6176 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6181 /* Otherwise, sign- or zero-extend unless we already are in the
6184 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6188 /* Unless this is a COMPARE or we have a funny memory reference,
6189 don't do anything with zero-extending field extracts starting at
6190 the low-order bit since they are simple AND operations. */
6191 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6192 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6195 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6196 we would be spanning bytes or if the position is not a constant and the
6197 length is not 1. In all other cases, we would only be going outside
6198 our object in cases when an original shift would have been
6200 if (! spans_byte
&& GET_CODE (inner
) == MEM
6201 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6202 || (pos_rtx
!= 0 && len
!= 1)))
6205 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6206 and the mode for the result. */
6207 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6209 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6210 pos_mode
= mode_for_extraction (EP_insv
, 2);
6211 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6214 if (! in_dest
&& unsignedp
6215 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6217 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6218 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6219 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6222 if (! in_dest
&& ! unsignedp
6223 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6225 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6226 pos_mode
= mode_for_extraction (EP_extv
, 3);
6227 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6230 /* Never narrow an object, since that might not be safe. */
6232 if (mode
!= VOIDmode
6233 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6234 extraction_mode
= mode
;
6236 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6237 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6238 pos_mode
= GET_MODE (pos_rtx
);
6240 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6241 if we have to change the mode of memory and cannot, the desired mode is
6243 if (GET_CODE (inner
) != MEM
)
6244 wanted_inner_mode
= wanted_inner_reg_mode
;
6245 else if (inner_mode
!= wanted_inner_mode
6246 && (mode_dependent_address_p (XEXP (inner
, 0))
6247 || MEM_VOLATILE_P (inner
)))
6248 wanted_inner_mode
= extraction_mode
;
6252 if (BITS_BIG_ENDIAN
)
6254 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6255 BITS_BIG_ENDIAN style. If position is constant, compute new
6256 position. Otherwise, build subtraction.
6257 Note that POS is relative to the mode of the original argument.
6258 If it's a MEM we need to recompute POS relative to that.
6259 However, if we're extracting from (or inserting into) a register,
6260 we want to recompute POS relative to wanted_inner_mode. */
6261 int width
= (GET_CODE (inner
) == MEM
6262 ? GET_MODE_BITSIZE (is_mode
)
6263 : GET_MODE_BITSIZE (wanted_inner_mode
));
6266 pos
= width
- len
- pos
;
6269 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6270 /* POS may be less than 0 now, but we check for that below.
6271 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6274 /* If INNER has a wider mode, make it smaller. If this is a constant
6275 extract, try to adjust the byte to point to the byte containing
6277 if (wanted_inner_mode
!= VOIDmode
6278 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6279 && ((GET_CODE (inner
) == MEM
6280 && (inner_mode
== wanted_inner_mode
6281 || (! mode_dependent_address_p (XEXP (inner
, 0))
6282 && ! MEM_VOLATILE_P (inner
))))))
6286 /* The computations below will be correct if the machine is big
6287 endian in both bits and bytes or little endian in bits and bytes.
6288 If it is mixed, we must adjust. */
6290 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6291 adjust OFFSET to compensate. */
6292 if (BYTES_BIG_ENDIAN
6294 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6295 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6297 /* If this is a constant position, we can move to the desired byte. */
6300 offset
+= pos
/ BITS_PER_UNIT
;
6301 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6304 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6306 && is_mode
!= wanted_inner_mode
)
6307 offset
= (GET_MODE_SIZE (is_mode
)
6308 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6310 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6311 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6314 /* If INNER is not memory, we can always get it into the proper mode. If we
6315 are changing its mode, POS must be a constant and smaller than the size
6317 else if (GET_CODE (inner
) != MEM
)
6319 if (GET_MODE (inner
) != wanted_inner_mode
6321 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6324 inner
= force_to_mode (inner
, wanted_inner_mode
,
6326 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6327 ? ~(unsigned HOST_WIDE_INT
) 0
6328 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6333 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6334 have to zero extend. Otherwise, we can just use a SUBREG. */
6336 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6338 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6340 /* If we know that no extraneous bits are set, and that the high
6341 bit is not set, convert extraction to cheaper one - either
6342 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6344 if (flag_expensive_optimizations
6345 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6346 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6347 & ~(((unsigned HOST_WIDE_INT
)
6348 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6352 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6354 /* Prefer ZERO_EXTENSION, since it gives more information to
6356 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6361 else if (pos_rtx
!= 0
6362 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6363 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6365 /* Make POS_RTX unless we already have it and it is correct. If we don't
6366 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6368 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6369 pos_rtx
= orig_pos_rtx
;
6371 else if (pos_rtx
== 0)
6372 pos_rtx
= GEN_INT (pos
);
6374 /* Make the required operation. See if we can use existing rtx. */
6375 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6376 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6378 new = gen_lowpart_for_combine (mode
, new);
6383 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6384 with any other operations in X. Return X without that shift if so. */
6387 extract_left_shift (x
, count
)
6391 enum rtx_code code
= GET_CODE (x
);
6392 enum machine_mode mode
= GET_MODE (x
);
6398 /* This is the shift itself. If it is wide enough, we will return
6399 either the value being shifted if the shift count is equal to
6400 COUNT or a shift for the difference. */
6401 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6402 && INTVAL (XEXP (x
, 1)) >= count
)
6403 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6404 INTVAL (XEXP (x
, 1)) - count
);
6408 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6409 return simplify_gen_unary (code
, mode
, tem
, mode
);
6413 case PLUS
: case IOR
: case XOR
: case AND
:
6414 /* If we can safely shift this constant and we find the inner shift,
6415 make a new operation. */
6416 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6417 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6418 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6419 return gen_binary (code
, mode
, tem
,
6420 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6431 /* Look at the expression rooted at X. Look for expressions
6432 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6433 Form these expressions.
6435 Return the new rtx, usually just X.
6437 Also, for machines like the VAX that don't have logical shift insns,
6438 try to convert logical to arithmetic shift operations in cases where
6439 they are equivalent. This undoes the canonicalizations to logical
6440 shifts done elsewhere.
6442 We try, as much as possible, to re-use rtl expressions to save memory.
6444 IN_CODE says what kind of expression we are processing. Normally, it is
6445 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6446 being kludges), it is MEM. When processing the arguments of a comparison
6447 or a COMPARE against zero, it is COMPARE. */
6450 make_compound_operation (x
, in_code
)
6452 enum rtx_code in_code
;
6454 enum rtx_code code
= GET_CODE (x
);
6455 enum machine_mode mode
= GET_MODE (x
);
6456 int mode_width
= GET_MODE_BITSIZE (mode
);
6458 enum rtx_code next_code
;
6464 /* Select the code to be used in recursive calls. Once we are inside an
6465 address, we stay there. If we have a comparison, set to COMPARE,
6466 but once inside, go back to our default of SET. */
6468 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6469 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6470 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6471 : in_code
== COMPARE
? SET
: in_code
);
6473 /* Process depending on the code of this operation. If NEW is set
6474 nonzero, it will be returned. */
6479 /* Convert shifts by constants into multiplications if inside
6481 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6482 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6483 && INTVAL (XEXP (x
, 1)) >= 0)
6485 new = make_compound_operation (XEXP (x
, 0), next_code
);
6486 new = gen_rtx_MULT (mode
, new,
6487 GEN_INT ((HOST_WIDE_INT
) 1
6488 << INTVAL (XEXP (x
, 1))));
6493 /* If the second operand is not a constant, we can't do anything
6495 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6498 /* If the constant is a power of two minus one and the first operand
6499 is a logical right shift, make an extraction. */
6500 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6501 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6503 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6504 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6505 0, in_code
== COMPARE
);
6508 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6509 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6510 && subreg_lowpart_p (XEXP (x
, 0))
6511 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6512 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6514 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6516 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6517 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6518 0, in_code
== COMPARE
);
6520 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6521 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6522 || GET_CODE (XEXP (x
, 0)) == IOR
)
6523 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6524 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6525 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6527 /* Apply the distributive law, and then try to make extractions. */
6528 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6529 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6531 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6533 new = make_compound_operation (new, in_code
);
6536 /* If we are have (and (rotate X C) M) and C is larger than the number
6537 of bits in M, this is an extraction. */
6539 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6540 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6541 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6542 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6544 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6545 new = make_extraction (mode
, new,
6546 (GET_MODE_BITSIZE (mode
)
6547 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6548 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6551 /* On machines without logical shifts, if the operand of the AND is
6552 a logical shift and our mask turns off all the propagated sign
6553 bits, we can replace the logical shift with an arithmetic shift. */
6554 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6555 && !have_insn_for (LSHIFTRT
, mode
)
6556 && have_insn_for (ASHIFTRT
, mode
)
6557 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6558 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6559 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6560 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6562 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6564 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6565 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6567 gen_rtx_ASHIFTRT (mode
,
6568 make_compound_operation
6569 (XEXP (XEXP (x
, 0), 0), next_code
),
6570 XEXP (XEXP (x
, 0), 1)));
6573 /* If the constant is one less than a power of two, this might be
6574 representable by an extraction even if no shift is present.
6575 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6576 we are in a COMPARE. */
6577 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6578 new = make_extraction (mode
,
6579 make_compound_operation (XEXP (x
, 0),
6581 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6583 /* If we are in a comparison and this is an AND with a power of two,
6584 convert this into the appropriate bit extract. */
6585 else if (in_code
== COMPARE
6586 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6587 new = make_extraction (mode
,
6588 make_compound_operation (XEXP (x
, 0),
6590 i
, NULL_RTX
, 1, 1, 0, 1);
6595 /* If the sign bit is known to be zero, replace this with an
6596 arithmetic shift. */
6597 if (have_insn_for (ASHIFTRT
, mode
)
6598 && ! have_insn_for (LSHIFTRT
, mode
)
6599 && mode_width
<= HOST_BITS_PER_WIDE_INT
6600 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6602 new = gen_rtx_ASHIFTRT (mode
,
6603 make_compound_operation (XEXP (x
, 0),
6609 /* ... fall through ... */
6615 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6616 this is a SIGN_EXTRACT. */
6617 if (GET_CODE (rhs
) == CONST_INT
6618 && GET_CODE (lhs
) == ASHIFT
6619 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6620 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6622 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6623 new = make_extraction (mode
, new,
6624 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6625 NULL_RTX
, mode_width
- INTVAL (rhs
),
6626 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6630 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6631 If so, try to merge the shifts into a SIGN_EXTEND. We could
6632 also do this for some cases of SIGN_EXTRACT, but it doesn't
6633 seem worth the effort; the case checked for occurs on Alpha. */
6635 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6636 && ! (GET_CODE (lhs
) == SUBREG
6637 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6638 && GET_CODE (rhs
) == CONST_INT
6639 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6640 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6641 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6642 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6643 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6648 /* Call ourselves recursively on the inner expression. If we are
6649 narrowing the object and it has a different RTL code from
6650 what it originally did, do this SUBREG as a force_to_mode. */
6652 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6653 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6654 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6655 && subreg_lowpart_p (x
))
6657 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6660 /* If we have something other than a SUBREG, we might have
6661 done an expansion, so rerun ourselves. */
6662 if (GET_CODE (newer
) != SUBREG
)
6663 newer
= make_compound_operation (newer
, in_code
);
6668 /* If this is a paradoxical subreg, and the new code is a sign or
6669 zero extension, omit the subreg and widen the extension. If it
6670 is a regular subreg, we can still get rid of the subreg by not
6671 widening so much, or in fact removing the extension entirely. */
6672 if ((GET_CODE (tem
) == SIGN_EXTEND
6673 || GET_CODE (tem
) == ZERO_EXTEND
)
6674 && subreg_lowpart_p (x
))
6676 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6677 || (GET_MODE_SIZE (mode
) >
6678 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6680 if (! INTEGRAL_MODE_P (mode
))
6682 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6685 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6696 x
= gen_lowpart_for_combine (mode
, new);
6697 code
= GET_CODE (x
);
6700 /* Now recursively process each operand of this operation. */
6701 fmt
= GET_RTX_FORMAT (code
);
6702 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6705 new = make_compound_operation (XEXP (x
, i
), next_code
);
6706 SUBST (XEXP (x
, i
), new);
6712 /* Given M see if it is a value that would select a field of bits
6713 within an item, but not the entire word. Return -1 if not.
6714 Otherwise, return the starting position of the field, where 0 is the
6717 *PLEN is set to the length of the field. */
6720 get_pos_from_mask (m
, plen
)
6721 unsigned HOST_WIDE_INT m
;
6722 unsigned HOST_WIDE_INT
*plen
;
6724 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6725 int pos
= exact_log2 (m
& -m
);
6731 /* Now shift off the low-order zero bits and see if we have a power of
6733 len
= exact_log2 ((m
>> pos
) + 1);
6742 /* See if X can be simplified knowing that we will only refer to it in
6743 MODE and will only refer to those bits that are nonzero in MASK.
6744 If other bits are being computed or if masking operations are done
6745 that select a superset of the bits in MASK, they can sometimes be
6748 Return a possibly simplified expression, but always convert X to
6749 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6751 Also, if REG is nonzero and X is a register equal in value to REG,
6754 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6755 are all off in X. This is used when X will be complemented, by either
6756 NOT, NEG, or XOR. */
6759 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6761 enum machine_mode mode
;
6762 unsigned HOST_WIDE_INT mask
;
6766 enum rtx_code code
= GET_CODE (x
);
6767 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6768 enum machine_mode op_mode
;
6769 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6772 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6773 code below will do the wrong thing since the mode of such an
6774 expression is VOIDmode.
6776 Also do nothing if X is a CLOBBER; this can happen if X was
6777 the return value from a call to gen_lowpart_for_combine. */
6778 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6781 /* We want to perform the operation is its present mode unless we know
6782 that the operation is valid in MODE, in which case we do the operation
6784 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6785 && have_insn_for (code
, mode
))
6786 ? mode
: GET_MODE (x
));
6788 /* It is not valid to do a right-shift in a narrower mode
6789 than the one it came in with. */
6790 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6791 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6792 op_mode
= GET_MODE (x
);
6794 /* Truncate MASK to fit OP_MODE. */
6796 mask
&= GET_MODE_MASK (op_mode
);
6798 /* When we have an arithmetic operation, or a shift whose count we
6799 do not know, we need to assume that all bit the up to the highest-order
6800 bit in MASK will be needed. This is how we form such a mask. */
6802 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6803 ? GET_MODE_MASK (op_mode
)
6804 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6807 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6809 /* Determine what bits of X are guaranteed to be (non)zero. */
6810 nonzero
= nonzero_bits (x
, mode
);
6812 /* If none of the bits in X are needed, return a zero. */
6813 if (! just_select
&& (nonzero
& mask
) == 0)
6816 /* If X is a CONST_INT, return a new one. Do this here since the
6817 test below will fail. */
6818 if (GET_CODE (x
) == CONST_INT
)
6820 if (SCALAR_INT_MODE_P (mode
))
6821 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6824 x
= GEN_INT (INTVAL (x
) & mask
);
6825 return gen_lowpart_common (mode
, x
);
6829 /* If X is narrower than MODE and we want all the bits in X's mode, just
6830 get X in the proper mode. */
6831 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6832 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6833 return gen_lowpart_for_combine (mode
, x
);
6835 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6836 MASK are already known to be zero in X, we need not do anything. */
6837 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6843 /* If X is a (clobber (const_int)), return it since we know we are
6844 generating something that won't match. */
6848 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6849 spanned the boundary of the MEM. If we are now masking so it is
6850 within that boundary, we don't need the USE any more. */
6851 if (! BITS_BIG_ENDIAN
6852 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6853 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6860 x
= expand_compound_operation (x
);
6861 if (GET_CODE (x
) != code
)
6862 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6866 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6867 || rtx_equal_p (reg
, get_last_value (x
))))
6872 if (subreg_lowpart_p (x
)
6873 /* We can ignore the effect of this SUBREG if it narrows the mode or
6874 if the constant masks to zero all the bits the mode doesn't
6876 && ((GET_MODE_SIZE (GET_MODE (x
))
6877 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6879 & GET_MODE_MASK (GET_MODE (x
))
6880 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6881 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6885 /* If this is an AND with a constant, convert it into an AND
6886 whose constant is the AND of that constant with MASK. If it
6887 remains an AND of MASK, delete it since it is redundant. */
6889 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6891 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6892 mask
& INTVAL (XEXP (x
, 1)));
6894 /* If X is still an AND, see if it is an AND with a mask that
6895 is just some low-order bits. If so, and it is MASK, we don't
6898 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6899 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6903 /* If it remains an AND, try making another AND with the bits
6904 in the mode mask that aren't in MASK turned on. If the
6905 constant in the AND is wide enough, this might make a
6906 cheaper constant. */
6908 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6909 && GET_MODE_MASK (GET_MODE (x
)) != mask
6910 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6912 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6913 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6914 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6917 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6918 number, sign extend it. */
6919 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6920 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6921 cval
|= (HOST_WIDE_INT
) -1 << width
;
6923 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6924 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6934 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6935 low-order bits (as in an alignment operation) and FOO is already
6936 aligned to that boundary, mask C1 to that boundary as well.
6937 This may eliminate that PLUS and, later, the AND. */
6940 unsigned int width
= GET_MODE_BITSIZE (mode
);
6941 unsigned HOST_WIDE_INT smask
= mask
;
6943 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6944 number, sign extend it. */
6946 if (width
< HOST_BITS_PER_WIDE_INT
6947 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6948 smask
|= (HOST_WIDE_INT
) -1 << width
;
6950 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6951 && exact_log2 (- smask
) >= 0
6952 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6953 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6954 return force_to_mode (plus_constant (XEXP (x
, 0),
6955 (INTVAL (XEXP (x
, 1)) & smask
)),
6956 mode
, smask
, reg
, next_select
);
6959 /* ... fall through ... */
6962 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6963 most significant bit in MASK since carries from those bits will
6964 affect the bits we are interested in. */
6969 /* If X is (minus C Y) where C's least set bit is larger than any bit
6970 in the mask, then we may replace with (neg Y). */
6971 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6972 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6973 & -INTVAL (XEXP (x
, 0))))
6976 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6978 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6981 /* Similarly, if C contains every bit in the fuller_mask, then we may
6982 replace with (not Y). */
6983 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6984 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6985 == INTVAL (XEXP (x
, 0))))
6987 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6988 XEXP (x
, 1), GET_MODE (x
));
6989 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6997 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6998 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6999 operation which may be a bitfield extraction. Ensure that the
7000 constant we form is not wider than the mode of X. */
7002 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7003 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7004 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7005 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7006 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7007 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7008 + floor_log2 (INTVAL (XEXP (x
, 1))))
7009 < GET_MODE_BITSIZE (GET_MODE (x
)))
7010 && (INTVAL (XEXP (x
, 1))
7011 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7013 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7014 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7015 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
7016 XEXP (XEXP (x
, 0), 0), temp
);
7017 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7018 XEXP (XEXP (x
, 0), 1));
7019 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7023 /* For most binary operations, just propagate into the operation and
7024 change the mode if we have an operation of that mode. */
7026 op0
= gen_lowpart_for_combine (op_mode
,
7027 force_to_mode (XEXP (x
, 0), mode
, mask
,
7029 op1
= gen_lowpart_for_combine (op_mode
,
7030 force_to_mode (XEXP (x
, 1), mode
, mask
,
7033 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7034 x
= gen_binary (code
, op_mode
, op0
, op1
);
7038 /* For left shifts, do the same, but just for the first operand.
7039 However, we cannot do anything with shifts where we cannot
7040 guarantee that the counts are smaller than the size of the mode
7041 because such a count will have a different meaning in a
7044 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7045 && INTVAL (XEXP (x
, 1)) >= 0
7046 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7047 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7048 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7049 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7052 /* If the shift count is a constant and we can do arithmetic in
7053 the mode of the shift, refine which bits we need. Otherwise, use the
7054 conservative form of the mask. */
7055 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7056 && INTVAL (XEXP (x
, 1)) >= 0
7057 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7058 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7059 mask
>>= INTVAL (XEXP (x
, 1));
7063 op0
= gen_lowpart_for_combine (op_mode
,
7064 force_to_mode (XEXP (x
, 0), op_mode
,
7065 mask
, reg
, next_select
));
7067 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7068 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7072 /* Here we can only do something if the shift count is a constant,
7073 this shift constant is valid for the host, and we can do arithmetic
7076 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7077 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7078 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7080 rtx inner
= XEXP (x
, 0);
7081 unsigned HOST_WIDE_INT inner_mask
;
7083 /* Select the mask of the bits we need for the shift operand. */
7084 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7086 /* We can only change the mode of the shift if we can do arithmetic
7087 in the mode of the shift and INNER_MASK is no wider than the
7088 width of OP_MODE. */
7089 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7090 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7091 op_mode
= GET_MODE (x
);
7093 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7095 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7096 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7099 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7100 shift and AND produces only copies of the sign bit (C2 is one less
7101 than a power of two), we can do this with just a shift. */
7103 if (GET_CODE (x
) == LSHIFTRT
7104 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7105 /* The shift puts one of the sign bit copies in the least significant
7107 && ((INTVAL (XEXP (x
, 1))
7108 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7109 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7110 && exact_log2 (mask
+ 1) >= 0
7111 /* Number of bits left after the shift must be more than the mask
7113 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7114 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7115 /* Must be more sign bit copies than the mask needs. */
7116 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7117 >= exact_log2 (mask
+ 1)))
7118 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7119 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7120 - exact_log2 (mask
+ 1)));
7125 /* If we are just looking for the sign bit, we don't need this shift at
7126 all, even if it has a variable count. */
7127 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7128 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7129 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7130 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7132 /* If this is a shift by a constant, get a mask that contains those bits
7133 that are not copies of the sign bit. We then have two cases: If
7134 MASK only includes those bits, this can be a logical shift, which may
7135 allow simplifications. If MASK is a single-bit field not within
7136 those bits, we are requesting a copy of the sign bit and hence can
7137 shift the sign bit to the appropriate location. */
7139 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7140 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7144 /* If the considered data is wider than HOST_WIDE_INT, we can't
7145 represent a mask for all its bits in a single scalar.
7146 But we only care about the lower bits, so calculate these. */
7148 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7150 nonzero
= ~(HOST_WIDE_INT
) 0;
7152 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7153 is the number of bits a full-width mask would have set.
7154 We need only shift if these are fewer than nonzero can
7155 hold. If not, we must keep all bits set in nonzero. */
7157 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7158 < HOST_BITS_PER_WIDE_INT
)
7159 nonzero
>>= INTVAL (XEXP (x
, 1))
7160 + HOST_BITS_PER_WIDE_INT
7161 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7165 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7166 nonzero
>>= INTVAL (XEXP (x
, 1));
7169 if ((mask
& ~nonzero
) == 0
7170 || (i
= exact_log2 (mask
)) >= 0)
7172 x
= simplify_shift_const
7173 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7174 i
< 0 ? INTVAL (XEXP (x
, 1))
7175 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7177 if (GET_CODE (x
) != ASHIFTRT
)
7178 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7182 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7183 even if the shift count isn't a constant. */
7185 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7189 /* If this is a zero- or sign-extension operation that just affects bits
7190 we don't care about, remove it. Be sure the call above returned
7191 something that is still a shift. */
7193 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7194 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7195 && INTVAL (XEXP (x
, 1)) >= 0
7196 && (INTVAL (XEXP (x
, 1))
7197 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7198 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7199 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7200 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7201 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7208 /* If the shift count is constant and we can do computations
7209 in the mode of X, compute where the bits we care about are.
7210 Otherwise, we can't do anything. Don't change the mode of
7211 the shift or propagate MODE into the shift, though. */
7212 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7213 && INTVAL (XEXP (x
, 1)) >= 0)
7215 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7216 GET_MODE (x
), GEN_INT (mask
),
7218 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7220 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7221 INTVAL (temp
), reg
, next_select
));
7226 /* If we just want the low-order bit, the NEG isn't needed since it
7227 won't change the low-order bit. */
7229 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7231 /* We need any bits less significant than the most significant bit in
7232 MASK since carries from those bits will affect the bits we are
7238 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7239 same as the XOR case above. Ensure that the constant we form is not
7240 wider than the mode of X. */
7242 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7243 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7244 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7245 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7246 < GET_MODE_BITSIZE (GET_MODE (x
)))
7247 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7249 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7250 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7251 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7253 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7256 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7257 use the full mask inside the NOT. */
7261 op0
= gen_lowpart_for_combine (op_mode
,
7262 force_to_mode (XEXP (x
, 0), mode
, mask
,
7264 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7265 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7269 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7270 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7271 which is equal to STORE_FLAG_VALUE. */
7272 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7273 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7274 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7275 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7280 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7281 written in a narrower mode. We play it safe and do not do so. */
7284 gen_lowpart_for_combine (GET_MODE (x
),
7285 force_to_mode (XEXP (x
, 1), mode
,
7286 mask
, reg
, next_select
)));
7288 gen_lowpart_for_combine (GET_MODE (x
),
7289 force_to_mode (XEXP (x
, 2), mode
,
7290 mask
, reg
,next_select
)));
7297 /* Ensure we return a value of the proper mode. */
7298 return gen_lowpart_for_combine (mode
, x
);
7301 /* Return nonzero if X is an expression that has one of two values depending on
7302 whether some other value is zero or nonzero. In that case, we return the
7303 value that is being tested, *PTRUE is set to the value if the rtx being
7304 returned has a nonzero value, and *PFALSE is set to the other alternative.
7306 If we return zero, we set *PTRUE and *PFALSE to X. */
7309 if_then_else_cond (x
, ptrue
, pfalse
)
7311 rtx
*ptrue
, *pfalse
;
7313 enum machine_mode mode
= GET_MODE (x
);
7314 enum rtx_code code
= GET_CODE (x
);
7315 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7316 unsigned HOST_WIDE_INT nz
;
7318 /* If we are comparing a value against zero, we are done. */
7319 if ((code
== NE
|| code
== EQ
)
7320 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7322 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7323 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7327 /* If this is a unary operation whose operand has one of two values, apply
7328 our opcode to compute those values. */
7329 else if (GET_RTX_CLASS (code
) == '1'
7330 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7332 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7333 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7334 GET_MODE (XEXP (x
, 0)));
7338 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7339 make can't possibly match and would suppress other optimizations. */
7340 else if (code
== COMPARE
)
7343 /* If this is a binary operation, see if either side has only one of two
7344 values. If either one does or if both do and they are conditional on
7345 the same value, compute the new true and false values. */
7346 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7347 || GET_RTX_CLASS (code
) == '<')
7349 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7350 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7352 if ((cond0
!= 0 || cond1
!= 0)
7353 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7355 /* If if_then_else_cond returned zero, then true/false are the
7356 same rtl. We must copy one of them to prevent invalid rtl
7359 true0
= copy_rtx (true0
);
7360 else if (cond1
== 0)
7361 true1
= copy_rtx (true1
);
7363 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7364 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7365 return cond0
? cond0
: cond1
;
7368 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7369 operands is zero when the other is nonzero, and vice-versa,
7370 and STORE_FLAG_VALUE is 1 or -1. */
7372 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7373 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7375 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7377 rtx op0
= XEXP (XEXP (x
, 0), 1);
7378 rtx op1
= XEXP (XEXP (x
, 1), 1);
7380 cond0
= XEXP (XEXP (x
, 0), 0);
7381 cond1
= XEXP (XEXP (x
, 1), 0);
7383 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7384 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7385 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7386 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7387 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7388 || ((swap_condition (GET_CODE (cond0
))
7389 == combine_reversed_comparison_code (cond1
))
7390 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7391 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7392 && ! side_effects_p (x
))
7394 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7395 *pfalse
= gen_binary (MULT
, mode
,
7397 ? simplify_gen_unary (NEG
, mode
, op1
,
7405 /* Similarly for MULT, AND and UMIN, except that for these the result
7407 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7408 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7409 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7411 cond0
= XEXP (XEXP (x
, 0), 0);
7412 cond1
= XEXP (XEXP (x
, 1), 0);
7414 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7415 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7416 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7417 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7418 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7419 || ((swap_condition (GET_CODE (cond0
))
7420 == combine_reversed_comparison_code (cond1
))
7421 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7422 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7423 && ! side_effects_p (x
))
7425 *ptrue
= *pfalse
= const0_rtx
;
7431 else if (code
== IF_THEN_ELSE
)
7433 /* If we have IF_THEN_ELSE already, extract the condition and
7434 canonicalize it if it is NE or EQ. */
7435 cond0
= XEXP (x
, 0);
7436 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7437 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7438 return XEXP (cond0
, 0);
7439 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7441 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7442 return XEXP (cond0
, 0);
7448 /* If X is a SUBREG, we can narrow both the true and false values
7449 if the inner expression, if there is a condition. */
7450 else if (code
== SUBREG
7451 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7454 *ptrue
= simplify_gen_subreg (mode
, true0
,
7455 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7456 *pfalse
= simplify_gen_subreg (mode
, false0
,
7457 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7462 /* If X is a constant, this isn't special and will cause confusions
7463 if we treat it as such. Likewise if it is equivalent to a constant. */
7464 else if (CONSTANT_P (x
)
7465 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7468 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7469 will be least confusing to the rest of the compiler. */
7470 else if (mode
== BImode
)
7472 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7476 /* If X is known to be either 0 or -1, those are the true and
7477 false values when testing X. */
7478 else if (x
== constm1_rtx
|| x
== const0_rtx
7479 || (mode
!= VOIDmode
7480 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7482 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7486 /* Likewise for 0 or a single bit. */
7487 else if (mode
!= VOIDmode
7488 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7489 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7491 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7495 /* Otherwise fail; show no condition with true and false values the same. */
7496 *ptrue
= *pfalse
= x
;
7500 /* Return the value of expression X given the fact that condition COND
7501 is known to be true when applied to REG as its first operand and VAL
7502 as its second. X is known to not be shared and so can be modified in
7505 We only handle the simplest cases, and specifically those cases that
7506 arise with IF_THEN_ELSE expressions. */
7509 known_cond (x
, cond
, reg
, val
)
7514 enum rtx_code code
= GET_CODE (x
);
7519 if (side_effects_p (x
))
7522 /* If either operand of the condition is a floating point value,
7523 then we have to avoid collapsing an EQ comparison. */
7525 && rtx_equal_p (x
, reg
)
7526 && ! FLOAT_MODE_P (GET_MODE (x
))
7527 && ! FLOAT_MODE_P (GET_MODE (val
)))
7530 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7533 /* If X is (abs REG) and we know something about REG's relationship
7534 with zero, we may be able to simplify this. */
7536 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7539 case GE
: case GT
: case EQ
:
7542 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7544 GET_MODE (XEXP (x
, 0)));
7549 /* The only other cases we handle are MIN, MAX, and comparisons if the
7550 operands are the same as REG and VAL. */
7552 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7554 if (rtx_equal_p (XEXP (x
, 0), val
))
7555 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7557 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7559 if (GET_RTX_CLASS (code
) == '<')
7561 if (comparison_dominates_p (cond
, code
))
7562 return const_true_rtx
;
7564 code
= combine_reversed_comparison_code (x
);
7566 && comparison_dominates_p (cond
, code
))
7571 else if (code
== SMAX
|| code
== SMIN
7572 || code
== UMIN
|| code
== UMAX
)
7574 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7576 /* Do not reverse the condition when it is NE or EQ.
7577 This is because we cannot conclude anything about
7578 the value of 'SMAX (x, y)' when x is not equal to y,
7579 but we can when x equals y. */
7580 if ((code
== SMAX
|| code
== UMAX
)
7581 && ! (cond
== EQ
|| cond
== NE
))
7582 cond
= reverse_condition (cond
);
7587 return unsignedp
? x
: XEXP (x
, 1);
7589 return unsignedp
? x
: XEXP (x
, 0);
7591 return unsignedp
? XEXP (x
, 1) : x
;
7593 return unsignedp
? XEXP (x
, 0) : x
;
7600 else if (code
== SUBREG
)
7602 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7603 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7605 if (SUBREG_REG (x
) != r
)
7607 /* We must simplify subreg here, before we lose track of the
7608 original inner_mode. */
7609 new = simplify_subreg (GET_MODE (x
), r
,
7610 inner_mode
, SUBREG_BYTE (x
));
7614 SUBST (SUBREG_REG (x
), r
);
7619 /* We don't have to handle SIGN_EXTEND here, because even in the
7620 case of replacing something with a modeless CONST_INT, a
7621 CONST_INT is already (supposed to be) a valid sign extension for
7622 its narrower mode, which implies it's already properly
7623 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7624 story is different. */
7625 else if (code
== ZERO_EXTEND
)
7627 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7628 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7630 if (XEXP (x
, 0) != r
)
7632 /* We must simplify the zero_extend here, before we lose
7633 track of the original inner_mode. */
7634 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7639 SUBST (XEXP (x
, 0), r
);
7645 fmt
= GET_RTX_FORMAT (code
);
7646 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7649 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7650 else if (fmt
[i
] == 'E')
7651 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7652 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7659 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7660 assignment as a field assignment. */
7663 rtx_equal_for_field_assignment_p (x
, y
)
7667 if (x
== y
|| rtx_equal_p (x
, y
))
7670 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7673 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7674 Note that all SUBREGs of MEM are paradoxical; otherwise they
7675 would have been rewritten. */
7676 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7677 && GET_CODE (SUBREG_REG (y
)) == MEM
7678 && rtx_equal_p (SUBREG_REG (y
),
7679 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7682 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7683 && GET_CODE (SUBREG_REG (x
)) == MEM
7684 && rtx_equal_p (SUBREG_REG (x
),
7685 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7688 /* We used to see if get_last_value of X and Y were the same but that's
7689 not correct. In one direction, we'll cause the assignment to have
7690 the wrong destination and in the case, we'll import a register into this
7691 insn that might have already have been dead. So fail if none of the
7692 above cases are true. */
7696 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7697 Return that assignment if so.
7699 We only handle the most common cases. */
7702 make_field_assignment (x
)
7705 rtx dest
= SET_DEST (x
);
7706 rtx src
= SET_SRC (x
);
7711 unsigned HOST_WIDE_INT len
;
7713 enum machine_mode mode
;
7715 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7716 a clear of a one-bit field. We will have changed it to
7717 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7720 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7721 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7722 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7723 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7725 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7728 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7732 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7733 && subreg_lowpart_p (XEXP (src
, 0))
7734 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7735 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7736 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7737 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7738 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7740 assign
= make_extraction (VOIDmode
, dest
, 0,
7741 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7744 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7748 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7750 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7751 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7752 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7754 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7757 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7761 /* The other case we handle is assignments into a constant-position
7762 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7763 a mask that has all one bits except for a group of zero bits and
7764 OTHER is known to have zeros where C1 has ones, this is such an
7765 assignment. Compute the position and length from C1. Shift OTHER
7766 to the appropriate position, force it to the required mode, and
7767 make the extraction. Check for the AND in both operands. */
7769 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7772 rhs
= expand_compound_operation (XEXP (src
, 0));
7773 lhs
= expand_compound_operation (XEXP (src
, 1));
7775 if (GET_CODE (rhs
) == AND
7776 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7777 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7778 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7779 else if (GET_CODE (lhs
) == AND
7780 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7781 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7782 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7786 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7787 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7788 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7789 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7792 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7796 /* The mode to use for the source is the mode of the assignment, or of
7797 what is inside a possible STRICT_LOW_PART. */
7798 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7799 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7801 /* Shift OTHER right POS places and make it the source, restricting it
7802 to the proper length and mode. */
7804 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7805 GET_MODE (src
), other
, pos
),
7807 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7808 ? ~(unsigned HOST_WIDE_INT
) 0
7809 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7812 return gen_rtx_SET (VOIDmode
, assign
, src
);
7815 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7819 apply_distributive_law (x
)
7822 enum rtx_code code
= GET_CODE (x
);
7823 rtx lhs
, rhs
, other
;
7825 enum rtx_code inner_code
;
7827 /* Distributivity is not true for floating point.
7828 It can change the value. So don't do it.
7829 -- rms and moshier@world.std.com. */
7830 if (FLOAT_MODE_P (GET_MODE (x
)))
7833 /* The outer operation can only be one of the following: */
7834 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7835 && code
!= PLUS
&& code
!= MINUS
)
7838 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7840 /* If either operand is a primitive we can't do anything, so get out
7842 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7843 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7846 lhs
= expand_compound_operation (lhs
);
7847 rhs
= expand_compound_operation (rhs
);
7848 inner_code
= GET_CODE (lhs
);
7849 if (inner_code
!= GET_CODE (rhs
))
7852 /* See if the inner and outer operations distribute. */
7859 /* These all distribute except over PLUS. */
7860 if (code
== PLUS
|| code
== MINUS
)
7865 if (code
!= PLUS
&& code
!= MINUS
)
7870 /* This is also a multiply, so it distributes over everything. */
7874 /* Non-paradoxical SUBREGs distributes over all operations, provided
7875 the inner modes and byte offsets are the same, this is an extraction
7876 of a low-order part, we don't convert an fp operation to int or
7877 vice versa, and we would not be converting a single-word
7878 operation into a multi-word operation. The latter test is not
7879 required, but it prevents generating unneeded multi-word operations.
7880 Some of the previous tests are redundant given the latter test, but
7881 are retained because they are required for correctness.
7883 We produce the result slightly differently in this case. */
7885 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7886 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7887 || ! subreg_lowpart_p (lhs
)
7888 || (GET_MODE_CLASS (GET_MODE (lhs
))
7889 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7890 || (GET_MODE_SIZE (GET_MODE (lhs
))
7891 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7892 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7895 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7896 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7897 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7903 /* Set LHS and RHS to the inner operands (A and B in the example
7904 above) and set OTHER to the common operand (C in the example).
7905 These is only one way to do this unless the inner operation is
7907 if (GET_RTX_CLASS (inner_code
) == 'c'
7908 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7909 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7910 else if (GET_RTX_CLASS (inner_code
) == 'c'
7911 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7912 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7913 else if (GET_RTX_CLASS (inner_code
) == 'c'
7914 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7915 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7916 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7917 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7921 /* Form the new inner operation, seeing if it simplifies first. */
7922 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7924 /* There is one exception to the general way of distributing:
7925 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7926 if (code
== XOR
&& inner_code
== IOR
)
7929 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7932 /* We may be able to continuing distributing the result, so call
7933 ourselves recursively on the inner operation before forming the
7934 outer operation, which we return. */
7935 return gen_binary (inner_code
, GET_MODE (x
),
7936 apply_distributive_law (tem
), other
);
7939 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7942 Return an equivalent form, if different from X. Otherwise, return X. If
7943 X is zero, we are to always construct the equivalent form. */
7946 simplify_and_const_int (x
, mode
, varop
, constop
)
7948 enum machine_mode mode
;
7950 unsigned HOST_WIDE_INT constop
;
7952 unsigned HOST_WIDE_INT nonzero
;
7955 /* Simplify VAROP knowing that we will be only looking at some of the
7958 Note by passing in CONSTOP, we guarantee that the bits not set in
7959 CONSTOP are not significant and will never be examined. We must
7960 ensure that is the case by explicitly masking out those bits
7961 before returning. */
7962 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7964 /* If VAROP is a CLOBBER, we will fail so return it. */
7965 if (GET_CODE (varop
) == CLOBBER
)
7968 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7969 to VAROP and return the new constant. */
7970 if (GET_CODE (varop
) == CONST_INT
)
7971 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7973 /* See what bits may be nonzero in VAROP. Unlike the general case of
7974 a call to nonzero_bits, here we don't care about bits outside
7977 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7979 /* Turn off all bits in the constant that are known to already be zero.
7980 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7981 which is tested below. */
7985 /* If we don't have any bits left, return zero. */
7989 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7990 a power of two, we can replace this with an ASHIFT. */
7991 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7992 && (i
= exact_log2 (constop
)) >= 0)
7993 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7995 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7996 or XOR, then try to apply the distributive law. This may eliminate
7997 operations if either branch can be simplified because of the AND.
7998 It may also make some cases more complex, but those cases probably
7999 won't match a pattern either with or without this. */
8001 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8003 gen_lowpart_for_combine
8005 apply_distributive_law
8006 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8007 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8008 XEXP (varop
, 0), constop
),
8009 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8010 XEXP (varop
, 1), constop
))));
8012 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8013 the AND and see if one of the operands simplifies to zero. If so, we
8014 may eliminate it. */
8016 if (GET_CODE (varop
) == PLUS
8017 && exact_log2 (constop
+ 1) >= 0)
8021 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8022 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8023 if (o0
== const0_rtx
)
8025 if (o1
== const0_rtx
)
8029 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8030 if we already had one (just check for the simplest cases). */
8031 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8032 && GET_MODE (XEXP (x
, 0)) == mode
8033 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8034 varop
= XEXP (x
, 0);
8036 varop
= gen_lowpart_for_combine (mode
, varop
);
8038 /* If we can't make the SUBREG, try to return what we were given. */
8039 if (GET_CODE (varop
) == CLOBBER
)
8040 return x
? x
: varop
;
8042 /* If we are only masking insignificant bits, return VAROP. */
8043 if (constop
== nonzero
)
8047 /* Otherwise, return an AND. */
8048 constop
= trunc_int_for_mode (constop
, mode
);
8049 /* See how much, if any, of X we can use. */
8050 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8051 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8055 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8056 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8057 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8059 SUBST (XEXP (x
, 0), varop
);
8066 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8067 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8068 is less useful. We can't allow both, because that results in exponential
8069 run time recursion. There is a nullstone testcase that triggered
8070 this. This macro avoids accidental uses of num_sign_bit_copies. */
8071 #define num_sign_bit_copies()
8073 /* Given an expression, X, compute which bits in X can be nonzero.
8074 We don't care about bits outside of those defined in MODE.
8076 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8077 a shift, AND, or zero_extract, we can do better. */
8079 static unsigned HOST_WIDE_INT
8080 nonzero_bits (x
, mode
)
8082 enum machine_mode mode
;
8084 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8085 unsigned HOST_WIDE_INT inner_nz
;
8087 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8090 /* For floating-point values, assume all bits are needed. */
8091 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8094 /* If X is wider than MODE, use its mode instead. */
8095 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8097 mode
= GET_MODE (x
);
8098 nonzero
= GET_MODE_MASK (mode
);
8099 mode_width
= GET_MODE_BITSIZE (mode
);
8102 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8103 /* Our only callers in this case look for single bit values. So
8104 just return the mode mask. Those tests will then be false. */
8107 #ifndef WORD_REGISTER_OPERATIONS
8108 /* If MODE is wider than X, but both are a single word for both the host
8109 and target machines, we can compute this from which bits of the
8110 object might be nonzero in its own mode, taking into account the fact
8111 that on many CISC machines, accessing an object in a wider mode
8112 causes the high-order bits to become undefined. So they are
8113 not known to be zero. */
8115 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8116 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8117 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8118 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8120 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
8121 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8126 code
= GET_CODE (x
);
8130 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8131 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8132 all the bits above ptr_mode are known to be zero. */
8133 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8135 nonzero
&= GET_MODE_MASK (ptr_mode
);
8138 /* Include declared information about alignment of pointers. */
8139 /* ??? We don't properly preserve REG_POINTER changes across
8140 pointer-to-integer casts, so we can't trust it except for
8141 things that we know must be pointers. See execute/960116-1.c. */
8142 if ((x
== stack_pointer_rtx
8143 || x
== frame_pointer_rtx
8144 || x
== arg_pointer_rtx
)
8145 && REGNO_POINTER_ALIGN (REGNO (x
)))
8147 unsigned HOST_WIDE_INT alignment
8148 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8150 #ifdef PUSH_ROUNDING
8151 /* If PUSH_ROUNDING is defined, it is possible for the
8152 stack to be momentarily aligned only to that amount,
8153 so we pick the least alignment. */
8154 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8155 alignment
= MIN (PUSH_ROUNDING (1), alignment
);
8158 nonzero
&= ~(alignment
- 1);
8161 /* If X is a register whose nonzero bits value is current, use it.
8162 Otherwise, if X is a register whose value we can find, use that
8163 value. Otherwise, use the previously-computed global nonzero bits
8164 for this register. */
8166 if (reg_last_set_value
[REGNO (x
)] != 0
8167 && (reg_last_set_mode
[REGNO (x
)] == mode
8168 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8169 && GET_MODE_CLASS (mode
) == MODE_INT
))
8170 && (reg_last_set_label
[REGNO (x
)] == label_tick
8171 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8172 && REG_N_SETS (REGNO (x
)) == 1
8173 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8175 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8176 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8178 tem
= get_last_value (x
);
8182 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8183 /* If X is narrower than MODE and TEM is a non-negative
8184 constant that would appear negative in the mode of X,
8185 sign-extend it for use in reg_nonzero_bits because some
8186 machines (maybe most) will actually do the sign-extension
8187 and this is the conservative approach.
8189 ??? For 2.5, try to tighten up the MD files in this regard
8190 instead of this kludge. */
8192 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8193 && GET_CODE (tem
) == CONST_INT
8195 && 0 != (INTVAL (tem
)
8196 & ((HOST_WIDE_INT
) 1
8197 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8198 tem
= GEN_INT (INTVAL (tem
)
8199 | ((HOST_WIDE_INT
) (-1)
8200 << GET_MODE_BITSIZE (GET_MODE (x
))));
8202 return nonzero_bits (tem
, mode
) & nonzero
;
8204 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8206 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8208 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8209 /* We don't know anything about the upper bits. */
8210 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8211 return nonzero
& mask
;
8217 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8218 /* If X is negative in MODE, sign-extend the value. */
8219 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8220 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8221 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8227 #ifdef LOAD_EXTEND_OP
8228 /* In many, if not most, RISC machines, reading a byte from memory
8229 zeros the rest of the register. Noticing that fact saves a lot
8230 of extra zero-extends. */
8231 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8232 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8237 case UNEQ
: case LTGT
:
8238 case GT
: case GTU
: case UNGT
:
8239 case LT
: case LTU
: case UNLT
:
8240 case GE
: case GEU
: case UNGE
:
8241 case LE
: case LEU
: case UNLE
:
8242 case UNORDERED
: case ORDERED
:
8244 /* If this produces an integer result, we know which bits are set.
8245 Code here used to clear bits outside the mode of X, but that is
8248 if (GET_MODE_CLASS (mode
) == MODE_INT
8249 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8250 nonzero
= STORE_FLAG_VALUE
;
8255 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8256 and num_sign_bit_copies. */
8257 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8258 == GET_MODE_BITSIZE (GET_MODE (x
)))
8262 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8263 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8268 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8269 and num_sign_bit_copies. */
8270 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8271 == GET_MODE_BITSIZE (GET_MODE (x
)))
8277 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8281 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8282 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8283 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8287 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8288 Otherwise, show all the bits in the outer mode but not the inner
8290 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8291 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8293 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8295 & (((HOST_WIDE_INT
) 1
8296 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8297 inner_nz
|= (GET_MODE_MASK (mode
)
8298 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8301 nonzero
&= inner_nz
;
8305 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8306 & nonzero_bits (XEXP (x
, 1), mode
));
8310 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8312 unsigned HOST_WIDE_INT nonzero0
= nonzero_bits (XEXP (x
, 0), mode
);
8314 /* Don't call nonzero_bits for the second time if it cannot change
8316 if ((nonzero
& nonzero0
) != nonzero
)
8317 nonzero
&= (nonzero0
| nonzero_bits (XEXP (x
, 1), mode
));
8321 case PLUS
: case MINUS
:
8323 case DIV
: case UDIV
:
8324 case MOD
: case UMOD
:
8325 /* We can apply the rules of arithmetic to compute the number of
8326 high- and low-order zero bits of these operations. We start by
8327 computing the width (position of the highest-order nonzero bit)
8328 and the number of low-order zero bits for each value. */
8330 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8331 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8332 int width0
= floor_log2 (nz0
) + 1;
8333 int width1
= floor_log2 (nz1
) + 1;
8334 int low0
= floor_log2 (nz0
& -nz0
);
8335 int low1
= floor_log2 (nz1
& -nz1
);
8336 HOST_WIDE_INT op0_maybe_minusp
8337 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8338 HOST_WIDE_INT op1_maybe_minusp
8339 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8340 unsigned int result_width
= mode_width
;
8346 result_width
= MAX (width0
, width1
) + 1;
8347 result_low
= MIN (low0
, low1
);
8350 result_low
= MIN (low0
, low1
);
8353 result_width
= width0
+ width1
;
8354 result_low
= low0
+ low1
;
8359 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8360 result_width
= width0
;
8365 result_width
= width0
;
8370 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8371 result_width
= MIN (width0
, width1
);
8372 result_low
= MIN (low0
, low1
);
8377 result_width
= MIN (width0
, width1
);
8378 result_low
= MIN (low0
, low1
);
8384 if (result_width
< mode_width
)
8385 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8388 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8390 #ifdef POINTERS_EXTEND_UNSIGNED
8391 /* If pointers extend unsigned and this is an addition or subtraction
8392 to a pointer in Pmode, all the bits above ptr_mode are known to be
8394 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8395 && (code
== PLUS
|| code
== MINUS
)
8396 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8397 nonzero
&= GET_MODE_MASK (ptr_mode
);
8403 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8404 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8405 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8409 /* If this is a SUBREG formed for a promoted variable that has
8410 been zero-extended, we know that at least the high-order bits
8411 are zero, though others might be too. */
8413 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8414 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8415 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8417 /* If the inner mode is a single word for both the host and target
8418 machines, we can compute this from which bits of the inner
8419 object might be nonzero. */
8420 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8421 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8422 <= HOST_BITS_PER_WIDE_INT
))
8424 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8426 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8427 /* If this is a typical RISC machine, we only have to worry
8428 about the way loads are extended. */
8429 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8431 & (((unsigned HOST_WIDE_INT
) 1
8432 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8434 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8435 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8438 /* On many CISC machines, accessing an object in a wider mode
8439 causes the high-order bits to become undefined. So they are
8440 not known to be zero. */
8441 if (GET_MODE_SIZE (GET_MODE (x
))
8442 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8443 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8444 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8453 /* The nonzero bits are in two classes: any bits within MODE
8454 that aren't in GET_MODE (x) are always significant. The rest of the
8455 nonzero bits are those that are significant in the operand of
8456 the shift when shifted the appropriate number of bits. This
8457 shows that high-order bits are cleared by the right shift and
8458 low-order bits by left shifts. */
8459 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8460 && INTVAL (XEXP (x
, 1)) >= 0
8461 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8463 enum machine_mode inner_mode
= GET_MODE (x
);
8464 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8465 int count
= INTVAL (XEXP (x
, 1));
8466 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8467 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8468 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8469 unsigned HOST_WIDE_INT outer
= 0;
8471 if (mode_width
> width
)
8472 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8474 if (code
== LSHIFTRT
)
8476 else if (code
== ASHIFTRT
)
8480 /* If the sign bit may have been nonzero before the shift, we
8481 need to mark all the places it could have been copied to
8482 by the shift as possibly nonzero. */
8483 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8484 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8486 else if (code
== ASHIFT
)
8489 inner
= ((inner
<< (count
% width
)
8490 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8492 nonzero
&= (outer
| inner
);
8497 /* This is at most the number of bits in the mode. */
8498 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8502 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8503 | nonzero_bits (XEXP (x
, 2), mode
));
8513 /* See the macro definition above. */
8514 #undef num_sign_bit_copies
8516 /* Return the number of bits at the high-order end of X that are known to
8517 be equal to the sign bit. X will be used in mode MODE; if MODE is
8518 VOIDmode, X will be used in its own mode. The returned value will always
8519 be between 1 and the number of bits in MODE. */
8522 num_sign_bit_copies (x
, mode
)
8524 enum machine_mode mode
;
8526 enum rtx_code code
= GET_CODE (x
);
8527 unsigned int bitwidth
;
8528 int num0
, num1
, result
;
8529 unsigned HOST_WIDE_INT nonzero
;
8532 /* If we weren't given a mode, use the mode of X. If the mode is still
8533 VOIDmode, we don't know anything. Likewise if one of the modes is
8536 if (mode
== VOIDmode
)
8537 mode
= GET_MODE (x
);
8539 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8542 bitwidth
= GET_MODE_BITSIZE (mode
);
8544 /* For a smaller object, just ignore the high bits. */
8545 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8547 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8549 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8552 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8554 #ifndef WORD_REGISTER_OPERATIONS
8555 /* If this machine does not do all register operations on the entire
8556 register and MODE is wider than the mode of X, we can say nothing
8557 at all about the high-order bits. */
8560 /* Likewise on machines that do, if the mode of the object is smaller
8561 than a word and loads of that size don't sign extend, we can say
8562 nothing about the high order bits. */
8563 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8564 #ifdef LOAD_EXTEND_OP
8565 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8576 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8577 /* If pointers extend signed and this is a pointer in Pmode, say that
8578 all the bits above ptr_mode are known to be sign bit copies. */
8579 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8581 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8584 if (reg_last_set_value
[REGNO (x
)] != 0
8585 && reg_last_set_mode
[REGNO (x
)] == mode
8586 && (reg_last_set_label
[REGNO (x
)] == label_tick
8587 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8588 && REG_N_SETS (REGNO (x
)) == 1
8589 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8591 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8592 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8594 tem
= get_last_value (x
);
8596 return num_sign_bit_copies (tem
, mode
);
8598 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8599 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8600 return reg_sign_bit_copies
[REGNO (x
)];
8604 #ifdef LOAD_EXTEND_OP
8605 /* Some RISC machines sign-extend all loads of smaller than a word. */
8606 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8607 return MAX (1, ((int) bitwidth
8608 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8613 /* If the constant is negative, take its 1's complement and remask.
8614 Then see how many zero bits we have. */
8615 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8616 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8617 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8618 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8620 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8623 /* If this is a SUBREG for a promoted object that is sign-extended
8624 and we are looking at it in a wider mode, we know that at least the
8625 high-order bits are known to be sign bit copies. */
8627 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8629 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8630 return MAX ((int) bitwidth
8631 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8635 /* For a smaller object, just ignore the high bits. */
8636 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8638 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8639 return MAX (1, (num0
8640 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8644 #ifdef WORD_REGISTER_OPERATIONS
8645 #ifdef LOAD_EXTEND_OP
8646 /* For paradoxical SUBREGs on machines where all register operations
8647 affect the entire register, just look inside. Note that we are
8648 passing MODE to the recursive call, so the number of sign bit copies
8649 will remain relative to that mode, not the inner mode. */
8651 /* This works only if loads sign extend. Otherwise, if we get a
8652 reload for the inner part, it may be loaded from the stack, and
8653 then we lose all sign bit copies that existed before the store
8656 if ((GET_MODE_SIZE (GET_MODE (x
))
8657 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8658 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8659 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8660 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8666 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8667 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8671 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8672 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8675 /* For a smaller object, just ignore the high bits. */
8676 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8677 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8681 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8683 case ROTATE
: case ROTATERT
:
8684 /* If we are rotating left by a number of bits less than the number
8685 of sign bit copies, we can just subtract that amount from the
8687 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8688 && INTVAL (XEXP (x
, 1)) >= 0
8689 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8691 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8692 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8693 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8698 /* In general, this subtracts one sign bit copy. But if the value
8699 is known to be positive, the number of sign bit copies is the
8700 same as that of the input. Finally, if the input has just one bit
8701 that might be nonzero, all the bits are copies of the sign bit. */
8702 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8703 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8704 return num0
> 1 ? num0
- 1 : 1;
8706 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8711 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8716 case IOR
: case AND
: case XOR
:
8717 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8718 /* Logical operations will preserve the number of sign-bit copies.
8719 MIN and MAX operations always return one of the operands. */
8720 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8721 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8722 return MIN (num0
, num1
);
8724 case PLUS
: case MINUS
:
8725 /* For addition and subtraction, we can have a 1-bit carry. However,
8726 if we are subtracting 1 from a positive number, there will not
8727 be such a carry. Furthermore, if the positive number is known to
8728 be 0 or 1, we know the result is either -1 or 0. */
8730 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8731 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8733 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8734 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8735 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8736 : bitwidth
- floor_log2 (nonzero
) - 1);
8739 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8740 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8741 result
= MAX (1, MIN (num0
, num1
) - 1);
8743 #ifdef POINTERS_EXTEND_UNSIGNED
8744 /* If pointers extend signed and this is an addition or subtraction
8745 to a pointer in Pmode, all the bits above ptr_mode are known to be
8747 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8748 && (code
== PLUS
|| code
== MINUS
)
8749 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8750 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8751 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8757 /* The number of bits of the product is the sum of the number of
8758 bits of both terms. However, unless one of the terms if known
8759 to be positive, we must allow for an additional bit since negating
8760 a negative number can remove one sign bit copy. */
8762 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8763 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8765 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8767 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8768 || (((nonzero_bits (XEXP (x
, 0), mode
)
8769 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8770 && ((nonzero_bits (XEXP (x
, 1), mode
)
8771 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8774 return MAX (1, result
);
8777 /* The result must be <= the first operand. If the first operand
8778 has the high bit set, we know nothing about the number of sign
8780 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8782 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8783 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8786 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8789 /* The result must be <= the second operand. */
8790 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8793 /* Similar to unsigned division, except that we have to worry about
8794 the case where the divisor is negative, in which case we have
8796 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8798 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8799 || (nonzero_bits (XEXP (x
, 1), mode
)
8800 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8806 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8808 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8809 || (nonzero_bits (XEXP (x
, 1), mode
)
8810 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8816 /* Shifts by a constant add to the number of bits equal to the
8818 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8819 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8820 && INTVAL (XEXP (x
, 1)) > 0)
8821 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8826 /* Left shifts destroy copies. */
8827 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8828 || INTVAL (XEXP (x
, 1)) < 0
8829 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8832 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8833 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8836 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8837 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8838 return MIN (num0
, num1
);
8840 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8841 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8842 case GEU
: case GTU
: case LEU
: case LTU
:
8843 case UNORDERED
: case ORDERED
:
8844 /* If the constant is negative, take its 1's complement and remask.
8845 Then see how many zero bits we have. */
8846 nonzero
= STORE_FLAG_VALUE
;
8847 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8848 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8849 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8851 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8858 /* If we haven't been able to figure it out by one of the above rules,
8859 see if some of the high-order bits are known to be zero. If so,
8860 count those bits and return one less than that amount. If we can't
8861 safely compute the mask for this mode, always return BITWIDTH. */
8863 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8866 nonzero
= nonzero_bits (x
, mode
);
8867 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8868 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8871 /* Return the number of "extended" bits there are in X, when interpreted
8872 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8873 unsigned quantities, this is the number of high-order zero bits.
8874 For signed quantities, this is the number of copies of the sign bit
8875 minus 1. In both case, this function returns the number of "spare"
8876 bits. For example, if two quantities for which this function returns
8877 at least 1 are added, the addition is known not to overflow.
8879 This function will always return 0 unless called during combine, which
8880 implies that it must be called from a define_split. */
8883 extended_count (x
, mode
, unsignedp
)
8885 enum machine_mode mode
;
8888 if (nonzero_sign_valid
== 0)
8892 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8893 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8894 - floor_log2 (nonzero_bits (x
, mode
)))
8896 : num_sign_bit_copies (x
, mode
) - 1);
8899 /* This function is called from `simplify_shift_const' to merge two
8900 outer operations. Specifically, we have already found that we need
8901 to perform operation *POP0 with constant *PCONST0 at the outermost
8902 position. We would now like to also perform OP1 with constant CONST1
8903 (with *POP0 being done last).
8905 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8906 the resulting operation. *PCOMP_P is set to 1 if we would need to
8907 complement the innermost operand, otherwise it is unchanged.
8909 MODE is the mode in which the operation will be done. No bits outside
8910 the width of this mode matter. It is assumed that the width of this mode
8911 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8913 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8914 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8915 result is simply *PCONST0.
8917 If the resulting operation cannot be expressed as one operation, we
8918 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8921 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8922 enum rtx_code
*pop0
;
8923 HOST_WIDE_INT
*pconst0
;
8925 HOST_WIDE_INT const1
;
8926 enum machine_mode mode
;
8929 enum rtx_code op0
= *pop0
;
8930 HOST_WIDE_INT const0
= *pconst0
;
8932 const0
&= GET_MODE_MASK (mode
);
8933 const1
&= GET_MODE_MASK (mode
);
8935 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8939 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8942 if (op1
== NIL
|| op0
== SET
)
8945 else if (op0
== NIL
)
8946 op0
= op1
, const0
= const1
;
8948 else if (op0
== op1
)
8972 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8973 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8976 /* If the two constants aren't the same, we can't do anything. The
8977 remaining six cases can all be done. */
8978 else if (const0
!= const1
)
8986 /* (a & b) | b == b */
8988 else /* op1 == XOR */
8989 /* (a ^ b) | b == a | b */
8995 /* (a & b) ^ b == (~a) & b */
8996 op0
= AND
, *pcomp_p
= 1;
8997 else /* op1 == IOR */
8998 /* (a | b) ^ b == a & ~b */
8999 op0
= AND
, *pconst0
= ~const0
;
9004 /* (a | b) & b == b */
9006 else /* op1 == XOR */
9007 /* (a ^ b) & b) == (~a) & b */
9014 /* Check for NO-OP cases. */
9015 const0
&= GET_MODE_MASK (mode
);
9017 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9019 else if (const0
== 0 && op0
== AND
)
9021 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9025 /* ??? Slightly redundant with the above mask, but not entirely.
9026 Moving this above means we'd have to sign-extend the mode mask
9027 for the final test. */
9028 const0
= trunc_int_for_mode (const0
, mode
);
9036 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9037 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9038 that we started with.
9040 The shift is normally computed in the widest mode we find in VAROP, as
9041 long as it isn't a different number of words than RESULT_MODE. Exceptions
9042 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9045 simplify_shift_const (x
, code
, result_mode
, varop
, orig_count
)
9048 enum machine_mode result_mode
;
9052 enum rtx_code orig_code
= code
;
9055 enum machine_mode mode
= result_mode
;
9056 enum machine_mode shift_mode
, tmode
;
9057 unsigned int mode_words
9058 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9059 /* We form (outer_op (code varop count) (outer_const)). */
9060 enum rtx_code outer_op
= NIL
;
9061 HOST_WIDE_INT outer_const
= 0;
9063 int complement_p
= 0;
9066 /* Make sure and truncate the "natural" shift on the way in. We don't
9067 want to do this inside the loop as it makes it more difficult to
9069 #ifdef SHIFT_COUNT_TRUNCATED
9070 if (SHIFT_COUNT_TRUNCATED
)
9071 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9074 /* If we were given an invalid count, don't do anything except exactly
9075 what was requested. */
9077 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9082 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9087 /* Unless one of the branches of the `if' in this loop does a `continue',
9088 we will `break' the loop after the `if'. */
9092 /* If we have an operand of (clobber (const_int 0)), just return that
9094 if (GET_CODE (varop
) == CLOBBER
)
9097 /* If we discovered we had to complement VAROP, leave. Making a NOT
9098 here would cause an infinite loop. */
9102 /* Convert ROTATERT to ROTATE. */
9103 if (code
== ROTATERT
)
9105 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9107 if (VECTOR_MODE_P (result_mode
))
9108 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9110 count
= bitsize
- count
;
9113 /* We need to determine what mode we will do the shift in. If the
9114 shift is a right shift or a ROTATE, we must always do it in the mode
9115 it was originally done in. Otherwise, we can do it in MODE, the
9116 widest mode encountered. */
9118 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9119 ? result_mode
: mode
);
9121 /* Handle cases where the count is greater than the size of the mode
9122 minus 1. For ASHIFT, use the size minus one as the count (this can
9123 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9124 take the count modulo the size. For other shifts, the result is
9127 Since these shifts are being produced by the compiler by combining
9128 multiple operations, each of which are defined, we know what the
9129 result is supposed to be. */
9131 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9133 if (code
== ASHIFTRT
)
9134 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9135 else if (code
== ROTATE
|| code
== ROTATERT
)
9136 count
%= GET_MODE_BITSIZE (shift_mode
);
9139 /* We can't simply return zero because there may be an
9147 /* An arithmetic right shift of a quantity known to be -1 or 0
9149 if (code
== ASHIFTRT
9150 && (num_sign_bit_copies (varop
, shift_mode
)
9151 == GET_MODE_BITSIZE (shift_mode
)))
9157 /* If we are doing an arithmetic right shift and discarding all but
9158 the sign bit copies, this is equivalent to doing a shift by the
9159 bitsize minus one. Convert it into that shift because it will often
9160 allow other simplifications. */
9162 if (code
== ASHIFTRT
9163 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9164 >= GET_MODE_BITSIZE (shift_mode
)))
9165 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9167 /* We simplify the tests below and elsewhere by converting
9168 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9169 `make_compound_operation' will convert it to an ASHIFTRT for
9170 those machines (such as VAX) that don't have an LSHIFTRT. */
9171 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9173 && ((nonzero_bits (varop
, shift_mode
)
9174 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9178 switch (GET_CODE (varop
))
9184 new = expand_compound_operation (varop
);
9193 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9194 minus the width of a smaller mode, we can do this with a
9195 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9196 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9197 && ! mode_dependent_address_p (XEXP (varop
, 0))
9198 && ! MEM_VOLATILE_P (varop
)
9199 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9200 MODE_INT
, 1)) != BLKmode
)
9202 new = adjust_address_nv (varop
, tmode
,
9203 BYTES_BIG_ENDIAN
? 0
9204 : count
/ BITS_PER_UNIT
);
9206 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9207 : ZERO_EXTEND
, mode
, new);
9214 /* Similar to the case above, except that we can only do this if
9215 the resulting mode is the same as that of the underlying
9216 MEM and adjust the address depending on the *bits* endianness
9217 because of the way that bit-field extract insns are defined. */
9218 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9219 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9220 MODE_INT
, 1)) != BLKmode
9221 && tmode
== GET_MODE (XEXP (varop
, 0)))
9223 if (BITS_BIG_ENDIAN
)
9224 new = XEXP (varop
, 0);
9227 new = copy_rtx (XEXP (varop
, 0));
9228 SUBST (XEXP (new, 0),
9229 plus_constant (XEXP (new, 0),
9230 count
/ BITS_PER_UNIT
));
9233 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9234 : ZERO_EXTEND
, mode
, new);
9241 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9242 the same number of words as what we've seen so far. Then store
9243 the widest mode in MODE. */
9244 if (subreg_lowpart_p (varop
)
9245 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9246 > GET_MODE_SIZE (GET_MODE (varop
)))
9247 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9248 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9251 varop
= SUBREG_REG (varop
);
9252 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9253 mode
= GET_MODE (varop
);
9259 /* Some machines use MULT instead of ASHIFT because MULT
9260 is cheaper. But it is still better on those machines to
9261 merge two shifts into one. */
9262 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9263 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9266 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9267 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9273 /* Similar, for when divides are cheaper. */
9274 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9275 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9278 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9279 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9285 /* If we are extracting just the sign bit of an arithmetic
9286 right shift, that shift is not needed. However, the sign
9287 bit of a wider mode may be different from what would be
9288 interpreted as the sign bit in a narrower mode, so, if
9289 the result is narrower, don't discard the shift. */
9290 if (code
== LSHIFTRT
9291 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9292 && (GET_MODE_BITSIZE (result_mode
)
9293 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9295 varop
= XEXP (varop
, 0);
9299 /* ... fall through ... */
9304 /* Here we have two nested shifts. The result is usually the
9305 AND of a new shift with a mask. We compute the result below. */
9306 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9307 && INTVAL (XEXP (varop
, 1)) >= 0
9308 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9309 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9310 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9312 enum rtx_code first_code
= GET_CODE (varop
);
9313 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9314 unsigned HOST_WIDE_INT mask
;
9317 /* We have one common special case. We can't do any merging if
9318 the inner code is an ASHIFTRT of a smaller mode. However, if
9319 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9320 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9321 we can convert it to
9322 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9323 This simplifies certain SIGN_EXTEND operations. */
9324 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9325 && count
== (unsigned int)
9326 (GET_MODE_BITSIZE (result_mode
)
9327 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9329 /* C3 has the low-order C1 bits zero. */
9331 mask
= (GET_MODE_MASK (mode
)
9332 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9334 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9335 XEXP (varop
, 0), mask
);
9336 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9338 count
= first_count
;
9343 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9344 than C1 high-order bits equal to the sign bit, we can convert
9345 this to either an ASHIFT or an ASHIFTRT depending on the
9348 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9350 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9351 && GET_MODE (varop
) == shift_mode
9352 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9355 varop
= XEXP (varop
, 0);
9357 signed_count
= count
- first_count
;
9358 if (signed_count
< 0)
9359 count
= -signed_count
, code
= ASHIFT
;
9361 count
= signed_count
;
9366 /* There are some cases we can't do. If CODE is ASHIFTRT,
9367 we can only do this if FIRST_CODE is also ASHIFTRT.
9369 We can't do the case when CODE is ROTATE and FIRST_CODE is
9372 If the mode of this shift is not the mode of the outer shift,
9373 we can't do this if either shift is a right shift or ROTATE.
9375 Finally, we can't do any of these if the mode is too wide
9376 unless the codes are the same.
9378 Handle the case where the shift codes are the same
9381 if (code
== first_code
)
9383 if (GET_MODE (varop
) != result_mode
9384 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9388 count
+= first_count
;
9389 varop
= XEXP (varop
, 0);
9393 if (code
== ASHIFTRT
9394 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9395 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9396 || (GET_MODE (varop
) != result_mode
9397 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9398 || first_code
== ROTATE
9399 || code
== ROTATE
)))
9402 /* To compute the mask to apply after the shift, shift the
9403 nonzero bits of the inner shift the same way the
9404 outer shift will. */
9406 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9409 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9412 /* Give up if we can't compute an outer operation to use. */
9414 || GET_CODE (mask_rtx
) != CONST_INT
9415 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9417 result_mode
, &complement_p
))
9420 /* If the shifts are in the same direction, we add the
9421 counts. Otherwise, we subtract them. */
9422 signed_count
= count
;
9423 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9424 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9425 signed_count
+= first_count
;
9427 signed_count
-= first_count
;
9429 /* If COUNT is positive, the new shift is usually CODE,
9430 except for the two exceptions below, in which case it is
9431 FIRST_CODE. If the count is negative, FIRST_CODE should
9433 if (signed_count
> 0
9434 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9435 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9436 code
= first_code
, count
= signed_count
;
9437 else if (signed_count
< 0)
9438 code
= first_code
, count
= -signed_count
;
9440 count
= signed_count
;
9442 varop
= XEXP (varop
, 0);
9446 /* If we have (A << B << C) for any shift, we can convert this to
9447 (A << C << B). This wins if A is a constant. Only try this if
9448 B is not a constant. */
9450 else if (GET_CODE (varop
) == code
9451 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9453 = simplify_binary_operation (code
, mode
,
9457 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9464 /* Make this fit the case below. */
9465 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9466 GEN_INT (GET_MODE_MASK (mode
)));
9472 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9473 with C the size of VAROP - 1 and the shift is logical if
9474 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9475 we have an (le X 0) operation. If we have an arithmetic shift
9476 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9477 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9479 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9480 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9481 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9482 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9483 && count
== (unsigned int)
9484 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9485 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9488 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9491 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9492 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9497 /* If we have (shift (logical)), move the logical to the outside
9498 to allow it to possibly combine with another logical and the
9499 shift to combine with another shift. This also canonicalizes to
9500 what a ZERO_EXTRACT looks like. Also, some machines have
9501 (and (shift)) insns. */
9503 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9504 && (new = simplify_binary_operation (code
, result_mode
,
9506 GEN_INT (count
))) != 0
9507 && GET_CODE (new) == CONST_INT
9508 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9509 INTVAL (new), result_mode
, &complement_p
))
9511 varop
= XEXP (varop
, 0);
9515 /* If we can't do that, try to simplify the shift in each arm of the
9516 logical expression, make a new logical expression, and apply
9517 the inverse distributive law. */
9519 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9520 XEXP (varop
, 0), count
);
9521 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9522 XEXP (varop
, 1), count
);
9524 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9525 varop
= apply_distributive_law (varop
);
9532 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9533 says that the sign bit can be tested, FOO has mode MODE, C is
9534 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9535 that may be nonzero. */
9536 if (code
== LSHIFTRT
9537 && XEXP (varop
, 1) == const0_rtx
9538 && GET_MODE (XEXP (varop
, 0)) == result_mode
9539 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9540 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9541 && ((STORE_FLAG_VALUE
9542 & ((HOST_WIDE_INT
) 1
9543 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9544 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9545 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9546 (HOST_WIDE_INT
) 1, result_mode
,
9549 varop
= XEXP (varop
, 0);
9556 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9557 than the number of bits in the mode is equivalent to A. */
9558 if (code
== LSHIFTRT
9559 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9560 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9562 varop
= XEXP (varop
, 0);
9567 /* NEG commutes with ASHIFT since it is multiplication. Move the
9568 NEG outside to allow shifts to combine. */
9570 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9571 (HOST_WIDE_INT
) 0, result_mode
,
9574 varop
= XEXP (varop
, 0);
9580 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9581 is one less than the number of bits in the mode is
9582 equivalent to (xor A 1). */
9583 if (code
== LSHIFTRT
9584 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9585 && XEXP (varop
, 1) == constm1_rtx
9586 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9587 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9588 (HOST_WIDE_INT
) 1, result_mode
,
9592 varop
= XEXP (varop
, 0);
9596 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9597 that might be nonzero in BAR are those being shifted out and those
9598 bits are known zero in FOO, we can replace the PLUS with FOO.
9599 Similarly in the other operand order. This code occurs when
9600 we are computing the size of a variable-size array. */
9602 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9603 && count
< HOST_BITS_PER_WIDE_INT
9604 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9605 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9606 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9608 varop
= XEXP (varop
, 0);
9611 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9612 && count
< HOST_BITS_PER_WIDE_INT
9613 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9614 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9616 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9617 & nonzero_bits (XEXP (varop
, 1),
9620 varop
= XEXP (varop
, 1);
9624 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9626 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9627 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9629 GEN_INT (count
))) != 0
9630 && GET_CODE (new) == CONST_INT
9631 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9632 INTVAL (new), result_mode
, &complement_p
))
9634 varop
= XEXP (varop
, 0);
9640 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9641 with C the size of VAROP - 1 and the shift is logical if
9642 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9643 we have a (gt X 0) operation. If the shift is arithmetic with
9644 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9645 we have a (neg (gt X 0)) operation. */
9647 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9648 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9649 && count
== (unsigned int)
9650 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9651 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9652 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9653 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9655 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9658 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9661 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9662 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9669 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9670 if the truncate does not affect the value. */
9671 if (code
== LSHIFTRT
9672 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9673 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9674 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9675 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9676 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9678 rtx varop_inner
= XEXP (varop
, 0);
9681 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9682 XEXP (varop_inner
, 0),
9684 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9685 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9698 /* We need to determine what mode to do the shift in. If the shift is
9699 a right shift or ROTATE, we must always do it in the mode it was
9700 originally done in. Otherwise, we can do it in MODE, the widest mode
9701 encountered. The code we care about is that of the shift that will
9702 actually be done, not the shift that was originally requested. */
9704 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9705 ? result_mode
: mode
);
9707 /* We have now finished analyzing the shift. The result should be
9708 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9709 OUTER_OP is non-NIL, it is an operation that needs to be applied
9710 to the result of the shift. OUTER_CONST is the relevant constant,
9711 but we must turn off all bits turned off in the shift.
9713 If we were passed a value for X, see if we can use any pieces of
9714 it. If not, make new rtx. */
9716 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9717 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9718 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9719 const_rtx
= XEXP (x
, 1);
9721 const_rtx
= GEN_INT (count
);
9723 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9724 && GET_MODE (XEXP (x
, 0)) == shift_mode
9725 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9726 varop
= XEXP (x
, 0);
9727 else if (GET_MODE (varop
) != shift_mode
)
9728 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9730 /* If we can't make the SUBREG, try to return what we were given. */
9731 if (GET_CODE (varop
) == CLOBBER
)
9732 return x
? x
: varop
;
9734 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9738 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9740 /* If we have an outer operation and we just made a shift, it is
9741 possible that we could have simplified the shift were it not
9742 for the outer operation. So try to do the simplification
9745 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9746 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9747 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9748 INTVAL (XEXP (x
, 1)));
9750 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9751 turn off all the bits that the shift would have turned off. */
9752 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9753 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9754 GET_MODE_MASK (result_mode
) >> orig_count
);
9756 /* Do the remainder of the processing in RESULT_MODE. */
9757 x
= gen_lowpart_for_combine (result_mode
, x
);
9759 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9762 x
=simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9764 if (outer_op
!= NIL
)
9766 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9767 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9769 if (outer_op
== AND
)
9770 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9771 else if (outer_op
== SET
)
9772 /* This means that we have determined that the result is
9773 equivalent to a constant. This should be rare. */
9774 x
= GEN_INT (outer_const
);
9775 else if (GET_RTX_CLASS (outer_op
) == '1')
9776 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9778 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9784 /* Like recog, but we receive the address of a pointer to a new pattern.
9785 We try to match the rtx that the pointer points to.
9786 If that fails, we may try to modify or replace the pattern,
9787 storing the replacement into the same pointer object.
9789 Modifications include deletion or addition of CLOBBERs.
9791 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9792 the CLOBBERs are placed.
9794 The value is the final insn code from the pattern ultimately matched,
9798 recog_for_combine (pnewpat
, insn
, pnotes
)
9804 int insn_code_number
;
9805 int num_clobbers_to_add
= 0;
9810 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9811 we use to indicate that something didn't match. If we find such a
9812 thing, force rejection. */
9813 if (GET_CODE (pat
) == PARALLEL
)
9814 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9815 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9816 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9819 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9820 instruction for pattern recognition. */
9821 dummy_insn
= shallow_copy_rtx (insn
);
9822 PATTERN (dummy_insn
) = pat
;
9823 REG_NOTES (dummy_insn
) = 0;
9825 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9827 /* If it isn't, there is the possibility that we previously had an insn
9828 that clobbered some register as a side effect, but the combined
9829 insn doesn't need to do that. So try once more without the clobbers
9830 unless this represents an ASM insn. */
9832 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9833 && GET_CODE (pat
) == PARALLEL
)
9837 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9838 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9841 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9845 SUBST_INT (XVECLEN (pat
, 0), pos
);
9848 pat
= XVECEXP (pat
, 0, 0);
9850 PATTERN (dummy_insn
) = pat
;
9851 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9854 /* Recognize all noop sets, these will be killed by followup pass. */
9855 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9856 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9858 /* If we had any clobbers to add, make a new pattern than contains
9859 them. Then check to make sure that all of them are dead. */
9860 if (num_clobbers_to_add
)
9862 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9863 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9865 + num_clobbers_to_add
)
9866 : num_clobbers_to_add
+ 1));
9868 if (GET_CODE (pat
) == PARALLEL
)
9869 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9870 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9872 XVECEXP (newpat
, 0, 0) = pat
;
9874 add_clobbers (newpat
, insn_code_number
);
9876 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9877 i
< XVECLEN (newpat
, 0); i
++)
9879 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9880 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9882 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9883 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9891 return insn_code_number
;
9894 /* Like gen_lowpart but for use by combine. In combine it is not possible
9895 to create any new pseudoregs. However, it is safe to create
9896 invalid memory addresses, because combine will try to recognize
9897 them and all they will do is make the combine attempt fail.
9899 If for some reason this cannot do its job, an rtx
9900 (clobber (const_int 0)) is returned.
9901 An insn containing that will not be recognized. */
9906 gen_lowpart_for_combine (mode
, x
)
9907 enum machine_mode mode
;
9912 if (GET_MODE (x
) == mode
)
9915 /* We can only support MODE being wider than a word if X is a
9916 constant integer or has a mode the same size. */
9918 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9919 && ! ((GET_MODE (x
) == VOIDmode
9920 && (GET_CODE (x
) == CONST_INT
9921 || GET_CODE (x
) == CONST_DOUBLE
))
9922 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9923 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9925 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9926 won't know what to do. So we will strip off the SUBREG here and
9927 process normally. */
9928 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9931 if (GET_MODE (x
) == mode
)
9935 result
= gen_lowpart_common (mode
, x
);
9936 #ifdef CANNOT_CHANGE_MODE_CLASS
9938 && GET_CODE (result
) == SUBREG
9939 && GET_CODE (SUBREG_REG (result
)) == REG
9940 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
9941 SET_REGNO_REG_SET (&subregs_of_mode
[GET_MODE (result
)],
9942 REGNO (SUBREG_REG (result
)));
9948 if (GET_CODE (x
) == MEM
)
9952 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9954 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9955 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9957 /* If we want to refer to something bigger than the original memref,
9958 generate a perverse subreg instead. That will force a reload
9959 of the original memref X. */
9960 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9961 return gen_rtx_SUBREG (mode
, x
, 0);
9963 if (WORDS_BIG_ENDIAN
)
9964 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9965 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9967 if (BYTES_BIG_ENDIAN
)
9969 /* Adjust the address so that the address-after-the-data is
9971 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9972 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9975 return adjust_address_nv (x
, mode
, offset
);
9978 /* If X is a comparison operator, rewrite it in a new mode. This
9979 probably won't match, but may allow further simplifications. */
9980 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9981 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9983 /* If we couldn't simplify X any other way, just enclose it in a
9984 SUBREG. Normally, this SUBREG won't match, but some patterns may
9985 include an explicit SUBREG or we may simplify it further in combine. */
9990 enum machine_mode sub_mode
= GET_MODE (x
);
9992 offset
= subreg_lowpart_offset (mode
, sub_mode
);
9993 if (sub_mode
== VOIDmode
)
9995 sub_mode
= int_mode_for_mode (mode
);
9996 x
= gen_lowpart_common (sub_mode
, x
);
9998 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10001 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10005 /* These routines make binary and unary operations by first seeing if they
10006 fold; if not, a new expression is allocated. */
10009 gen_binary (code
, mode
, op0
, op1
)
10010 enum rtx_code code
;
10011 enum machine_mode mode
;
10017 if (GET_RTX_CLASS (code
) == 'c'
10018 && swap_commutative_operands_p (op0
, op1
))
10019 tem
= op0
, op0
= op1
, op1
= tem
;
10021 if (GET_RTX_CLASS (code
) == '<')
10023 enum machine_mode op_mode
= GET_MODE (op0
);
10025 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10026 just (REL_OP X Y). */
10027 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10029 op1
= XEXP (op0
, 1);
10030 op0
= XEXP (op0
, 0);
10031 op_mode
= GET_MODE (op0
);
10034 if (op_mode
== VOIDmode
)
10035 op_mode
= GET_MODE (op1
);
10036 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10039 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10044 /* Put complex operands first and constants second. */
10045 if (GET_RTX_CLASS (code
) == 'c'
10046 && swap_commutative_operands_p (op0
, op1
))
10047 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10049 /* If we are turning off bits already known off in OP0, we need not do
10051 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10052 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10053 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10056 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10059 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10060 comparison code that will be tested.
10062 The result is a possibly different comparison code to use. *POP0 and
10063 *POP1 may be updated.
10065 It is possible that we might detect that a comparison is either always
10066 true or always false. However, we do not perform general constant
10067 folding in combine, so this knowledge isn't useful. Such tautologies
10068 should have been detected earlier. Hence we ignore all such cases. */
10070 static enum rtx_code
10071 simplify_comparison (code
, pop0
, pop1
)
10072 enum rtx_code code
;
10080 enum machine_mode mode
, tmode
;
10082 /* Try a few ways of applying the same transformation to both operands. */
10085 #ifndef WORD_REGISTER_OPERATIONS
10086 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10087 so check specially. */
10088 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10089 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10090 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10091 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10092 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10093 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10094 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10095 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10096 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10097 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
10098 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10099 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
10100 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
10101 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
10102 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
10103 && (INTVAL (XEXP (op0
, 1))
10104 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10105 - (GET_MODE_BITSIZE
10106 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10108 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10109 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10113 /* If both operands are the same constant shift, see if we can ignore the
10114 shift. We can if the shift is a rotate or if the bits shifted out of
10115 this shift are known to be zero for both inputs and if the type of
10116 comparison is compatible with the shift. */
10117 if (GET_CODE (op0
) == GET_CODE (op1
)
10118 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10119 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10120 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10121 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10122 || (GET_CODE (op0
) == ASHIFTRT
10123 && (code
!= GTU
&& code
!= LTU
10124 && code
!= GEU
&& code
!= LEU
)))
10125 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10126 && INTVAL (XEXP (op0
, 1)) >= 0
10127 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10128 && XEXP (op0
, 1) == XEXP (op1
, 1))
10130 enum machine_mode mode
= GET_MODE (op0
);
10131 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10132 int shift_count
= INTVAL (XEXP (op0
, 1));
10134 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10135 mask
&= (mask
>> shift_count
) << shift_count
;
10136 else if (GET_CODE (op0
) == ASHIFT
)
10137 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10139 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10140 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10141 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10146 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10147 SUBREGs are of the same mode, and, in both cases, the AND would
10148 be redundant if the comparison was done in the narrower mode,
10149 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10150 and the operand's possibly nonzero bits are 0xffffff01; in that case
10151 if we only care about QImode, we don't need the AND). This case
10152 occurs if the output mode of an scc insn is not SImode and
10153 STORE_FLAG_VALUE == 1 (e.g., the 386).
10155 Similarly, check for a case where the AND's are ZERO_EXTEND
10156 operations from some narrower mode even though a SUBREG is not
10159 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10160 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10161 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10163 rtx inner_op0
= XEXP (op0
, 0);
10164 rtx inner_op1
= XEXP (op1
, 0);
10165 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10166 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10169 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10170 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10171 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10172 && (GET_MODE (SUBREG_REG (inner_op0
))
10173 == GET_MODE (SUBREG_REG (inner_op1
)))
10174 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10175 <= HOST_BITS_PER_WIDE_INT
)
10176 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10177 GET_MODE (SUBREG_REG (inner_op0
)))))
10178 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10179 GET_MODE (SUBREG_REG (inner_op1
))))))
10181 op0
= SUBREG_REG (inner_op0
);
10182 op1
= SUBREG_REG (inner_op1
);
10184 /* The resulting comparison is always unsigned since we masked
10185 off the original sign bit. */
10186 code
= unsigned_condition (code
);
10192 for (tmode
= GET_CLASS_NARROWEST_MODE
10193 (GET_MODE_CLASS (GET_MODE (op0
)));
10194 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10195 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10197 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10198 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10199 code
= unsigned_condition (code
);
10208 /* If both operands are NOT, we can strip off the outer operation
10209 and adjust the comparison code for swapped operands; similarly for
10210 NEG, except that this must be an equality comparison. */
10211 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10212 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10213 && (code
== EQ
|| code
== NE
)))
10214 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10220 /* If the first operand is a constant, swap the operands and adjust the
10221 comparison code appropriately, but don't do this if the second operand
10222 is already a constant integer. */
10223 if (swap_commutative_operands_p (op0
, op1
))
10225 tem
= op0
, op0
= op1
, op1
= tem
;
10226 code
= swap_condition (code
);
10229 /* We now enter a loop during which we will try to simplify the comparison.
10230 For the most part, we only are concerned with comparisons with zero,
10231 but some things may really be comparisons with zero but not start
10232 out looking that way. */
10234 while (GET_CODE (op1
) == CONST_INT
)
10236 enum machine_mode mode
= GET_MODE (op0
);
10237 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10238 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10239 int equality_comparison_p
;
10240 int sign_bit_comparison_p
;
10241 int unsigned_comparison_p
;
10242 HOST_WIDE_INT const_op
;
10244 /* We only want to handle integral modes. This catches VOIDmode,
10245 CCmode, and the floating-point modes. An exception is that we
10246 can handle VOIDmode if OP0 is a COMPARE or a comparison
10249 if (GET_MODE_CLASS (mode
) != MODE_INT
10250 && ! (mode
== VOIDmode
10251 && (GET_CODE (op0
) == COMPARE
10252 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10255 /* Get the constant we are comparing against and turn off all bits
10256 not on in our mode. */
10257 const_op
= INTVAL (op1
);
10258 if (mode
!= VOIDmode
)
10259 const_op
= trunc_int_for_mode (const_op
, mode
);
10260 op1
= GEN_INT (const_op
);
10262 /* If we are comparing against a constant power of two and the value
10263 being compared can only have that single bit nonzero (e.g., it was
10264 `and'ed with that bit), we can replace this with a comparison
10267 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10268 || code
== LT
|| code
== LTU
)
10269 && mode_width
<= HOST_BITS_PER_WIDE_INT
10270 && exact_log2 (const_op
) >= 0
10271 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10273 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10274 op1
= const0_rtx
, const_op
= 0;
10277 /* Similarly, if we are comparing a value known to be either -1 or
10278 0 with -1, change it to the opposite comparison against zero. */
10281 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10282 || code
== GEU
|| code
== LTU
)
10283 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10285 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10286 op1
= const0_rtx
, const_op
= 0;
10289 /* Do some canonicalizations based on the comparison code. We prefer
10290 comparisons against zero and then prefer equality comparisons.
10291 If we can reduce the size of a constant, we will do that too. */
10296 /* < C is equivalent to <= (C - 1) */
10300 op1
= GEN_INT (const_op
);
10302 /* ... fall through to LE case below. */
10308 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10312 op1
= GEN_INT (const_op
);
10316 /* If we are doing a <= 0 comparison on a value known to have
10317 a zero sign bit, we can replace this with == 0. */
10318 else if (const_op
== 0
10319 && mode_width
<= HOST_BITS_PER_WIDE_INT
10320 && (nonzero_bits (op0
, mode
)
10321 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10326 /* >= C is equivalent to > (C - 1). */
10330 op1
= GEN_INT (const_op
);
10332 /* ... fall through to GT below. */
10338 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10342 op1
= GEN_INT (const_op
);
10346 /* If we are doing a > 0 comparison on a value known to have
10347 a zero sign bit, we can replace this with != 0. */
10348 else if (const_op
== 0
10349 && mode_width
<= HOST_BITS_PER_WIDE_INT
10350 && (nonzero_bits (op0
, mode
)
10351 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10356 /* < C is equivalent to <= (C - 1). */
10360 op1
= GEN_INT (const_op
);
10362 /* ... fall through ... */
10365 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10366 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10367 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10369 const_op
= 0, op1
= const0_rtx
;
10377 /* unsigned <= 0 is equivalent to == 0 */
10381 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10382 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10383 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10385 const_op
= 0, op1
= const0_rtx
;
10391 /* >= C is equivalent to < (C - 1). */
10395 op1
= GEN_INT (const_op
);
10397 /* ... fall through ... */
10400 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10401 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10402 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10404 const_op
= 0, op1
= const0_rtx
;
10412 /* unsigned > 0 is equivalent to != 0 */
10416 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10417 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10418 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10420 const_op
= 0, op1
= const0_rtx
;
10429 /* Compute some predicates to simplify code below. */
10431 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10432 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10433 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10436 /* If this is a sign bit comparison and we can do arithmetic in
10437 MODE, say that we will only be needing the sign bit of OP0. */
10438 if (sign_bit_comparison_p
10439 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10440 op0
= force_to_mode (op0
, mode
,
10442 << (GET_MODE_BITSIZE (mode
) - 1)),
10445 /* Now try cases based on the opcode of OP0. If none of the cases
10446 does a "continue", we exit this loop immediately after the
10449 switch (GET_CODE (op0
))
10452 /* If we are extracting a single bit from a variable position in
10453 a constant that has only a single bit set and are comparing it
10454 with zero, we can convert this into an equality comparison
10455 between the position and the location of the single bit. */
10457 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10458 && XEXP (op0
, 1) == const1_rtx
10459 && equality_comparison_p
&& const_op
== 0
10460 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10462 if (BITS_BIG_ENDIAN
)
10464 enum machine_mode new_mode
10465 = mode_for_extraction (EP_extzv
, 1);
10466 if (new_mode
== MAX_MACHINE_MODE
)
10467 i
= BITS_PER_WORD
- 1 - i
;
10471 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10475 op0
= XEXP (op0
, 2);
10479 /* Result is nonzero iff shift count is equal to I. */
10480 code
= reverse_condition (code
);
10484 /* ... fall through ... */
10487 tem
= expand_compound_operation (op0
);
10496 /* If testing for equality, we can take the NOT of the constant. */
10497 if (equality_comparison_p
10498 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10500 op0
= XEXP (op0
, 0);
10505 /* If just looking at the sign bit, reverse the sense of the
10507 if (sign_bit_comparison_p
)
10509 op0
= XEXP (op0
, 0);
10510 code
= (code
== GE
? LT
: GE
);
10516 /* If testing for equality, we can take the NEG of the constant. */
10517 if (equality_comparison_p
10518 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10520 op0
= XEXP (op0
, 0);
10525 /* The remaining cases only apply to comparisons with zero. */
10529 /* When X is ABS or is known positive,
10530 (neg X) is < 0 if and only if X != 0. */
10532 if (sign_bit_comparison_p
10533 && (GET_CODE (XEXP (op0
, 0)) == ABS
10534 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10535 && (nonzero_bits (XEXP (op0
, 0), mode
)
10536 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10538 op0
= XEXP (op0
, 0);
10539 code
= (code
== LT
? NE
: EQ
);
10543 /* If we have NEG of something whose two high-order bits are the
10544 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10545 if (num_sign_bit_copies (op0
, mode
) >= 2)
10547 op0
= XEXP (op0
, 0);
10548 code
= swap_condition (code
);
10554 /* If we are testing equality and our count is a constant, we
10555 can perform the inverse operation on our RHS. */
10556 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10557 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10558 op1
, XEXP (op0
, 1))) != 0)
10560 op0
= XEXP (op0
, 0);
10565 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10566 a particular bit. Convert it to an AND of a constant of that
10567 bit. This will be converted into a ZERO_EXTRACT. */
10568 if (const_op
== 0 && sign_bit_comparison_p
10569 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10570 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10572 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10575 - INTVAL (XEXP (op0
, 1)))));
10576 code
= (code
== LT
? NE
: EQ
);
10580 /* Fall through. */
10583 /* ABS is ignorable inside an equality comparison with zero. */
10584 if (const_op
== 0 && equality_comparison_p
)
10586 op0
= XEXP (op0
, 0);
10592 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10593 to (compare FOO CONST) if CONST fits in FOO's mode and we
10594 are either testing inequality or have an unsigned comparison
10595 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10596 if (! unsigned_comparison_p
10597 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10598 <= HOST_BITS_PER_WIDE_INT
)
10599 && ((unsigned HOST_WIDE_INT
) const_op
10600 < (((unsigned HOST_WIDE_INT
) 1
10601 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10603 op0
= XEXP (op0
, 0);
10609 /* Check for the case where we are comparing A - C1 with C2,
10610 both constants are smaller than 1/2 the maximum positive
10611 value in MODE, and the comparison is equality or unsigned.
10612 In that case, if A is either zero-extended to MODE or has
10613 sufficient sign bits so that the high-order bit in MODE
10614 is a copy of the sign in the inner mode, we can prove that it is
10615 safe to do the operation in the wider mode. This simplifies
10616 many range checks. */
10618 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10619 && subreg_lowpart_p (op0
)
10620 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10621 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10622 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10623 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10624 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10625 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10626 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10627 GET_MODE (SUBREG_REG (op0
)))
10628 & ~GET_MODE_MASK (mode
))
10629 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10630 GET_MODE (SUBREG_REG (op0
)))
10632 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10633 - GET_MODE_BITSIZE (mode
)))))
10635 op0
= SUBREG_REG (op0
);
10639 /* If the inner mode is narrower and we are extracting the low part,
10640 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10641 if (subreg_lowpart_p (op0
)
10642 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10643 /* Fall through */ ;
10647 /* ... fall through ... */
10650 if ((unsigned_comparison_p
|| equality_comparison_p
)
10651 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10652 <= HOST_BITS_PER_WIDE_INT
)
10653 && ((unsigned HOST_WIDE_INT
) const_op
10654 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10656 op0
= XEXP (op0
, 0);
10662 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10663 this for equality comparisons due to pathological cases involving
10665 if (equality_comparison_p
10666 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10667 op1
, XEXP (op0
, 1))))
10669 op0
= XEXP (op0
, 0);
10674 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10675 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10676 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10678 op0
= XEXP (XEXP (op0
, 0), 0);
10679 code
= (code
== LT
? EQ
: NE
);
10685 /* We used to optimize signed comparisons against zero, but that
10686 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10687 arrive here as equality comparisons, or (GEU, LTU) are
10688 optimized away. No need to special-case them. */
10690 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10691 (eq B (minus A C)), whichever simplifies. We can only do
10692 this for equality comparisons due to pathological cases involving
10694 if (equality_comparison_p
10695 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10696 XEXP (op0
, 1), op1
)))
10698 op0
= XEXP (op0
, 0);
10703 if (equality_comparison_p
10704 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10705 XEXP (op0
, 0), op1
)))
10707 op0
= XEXP (op0
, 1);
10712 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10713 of bits in X minus 1, is one iff X > 0. */
10714 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10715 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10716 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10718 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10720 op0
= XEXP (op0
, 1);
10721 code
= (code
== GE
? LE
: GT
);
10727 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10728 if C is zero or B is a constant. */
10729 if (equality_comparison_p
10730 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10731 XEXP (op0
, 1), op1
)))
10733 op0
= XEXP (op0
, 0);
10740 case UNEQ
: case LTGT
:
10741 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10742 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10743 case UNORDERED
: case ORDERED
:
10744 /* We can't do anything if OP0 is a condition code value, rather
10745 than an actual data value. */
10748 || XEXP (op0
, 0) == cc0_rtx
10750 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10753 /* Get the two operands being compared. */
10754 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10755 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10757 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10759 /* Check for the cases where we simply want the result of the
10760 earlier test or the opposite of that result. */
10761 if (code
== NE
|| code
== EQ
10762 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10763 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10764 && (STORE_FLAG_VALUE
10765 & (((HOST_WIDE_INT
) 1
10766 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10767 && (code
== LT
|| code
== GE
)))
10769 enum rtx_code new_code
;
10770 if (code
== LT
|| code
== NE
)
10771 new_code
= GET_CODE (op0
);
10773 new_code
= combine_reversed_comparison_code (op0
);
10775 if (new_code
!= UNKNOWN
)
10786 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10788 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10789 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10790 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10792 op0
= XEXP (op0
, 1);
10793 code
= (code
== GE
? GT
: LE
);
10799 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10800 will be converted to a ZERO_EXTRACT later. */
10801 if (const_op
== 0 && equality_comparison_p
10802 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10803 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10805 op0
= simplify_and_const_int
10806 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10808 XEXP (XEXP (op0
, 0), 1)),
10809 (HOST_WIDE_INT
) 1);
10813 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10814 zero and X is a comparison and C1 and C2 describe only bits set
10815 in STORE_FLAG_VALUE, we can compare with X. */
10816 if (const_op
== 0 && equality_comparison_p
10817 && mode_width
<= HOST_BITS_PER_WIDE_INT
10818 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10819 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10820 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10821 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10822 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10824 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10825 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10826 if ((~STORE_FLAG_VALUE
& mask
) == 0
10827 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10828 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10829 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10831 op0
= XEXP (XEXP (op0
, 0), 0);
10836 /* If we are doing an equality comparison of an AND of a bit equal
10837 to the sign bit, replace this with a LT or GE comparison of
10838 the underlying value. */
10839 if (equality_comparison_p
10841 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10842 && mode_width
<= HOST_BITS_PER_WIDE_INT
10843 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10844 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10846 op0
= XEXP (op0
, 0);
10847 code
= (code
== EQ
? GE
: LT
);
10851 /* If this AND operation is really a ZERO_EXTEND from a narrower
10852 mode, the constant fits within that mode, and this is either an
10853 equality or unsigned comparison, try to do this comparison in
10854 the narrower mode. */
10855 if ((equality_comparison_p
|| unsigned_comparison_p
)
10856 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10857 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10858 & GET_MODE_MASK (mode
))
10860 && const_op
>> i
== 0
10861 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10863 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10867 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10868 in both M1 and M2 and the SUBREG is either paradoxical or
10869 represents the low part, permute the SUBREG and the AND and
10871 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10873 #ifdef WORD_REGISTER_OPERATIONS
10875 > (GET_MODE_BITSIZE
10876 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10877 && mode_width
<= BITS_PER_WORD
)
10880 <= (GET_MODE_BITSIZE
10881 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10882 && subreg_lowpart_p (XEXP (op0
, 0))))
10883 #ifndef WORD_REGISTER_OPERATIONS
10884 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10885 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10886 As originally written the upper bits have a defined value
10887 due to the AND operation. However, if we commute the AND
10888 inside the SUBREG then they no longer have defined values
10889 and the meaning of the code has been changed. */
10890 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10891 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10893 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10894 && mode_width
<= HOST_BITS_PER_WIDE_INT
10895 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10896 <= HOST_BITS_PER_WIDE_INT
)
10897 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10898 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10899 & INTVAL (XEXP (op0
, 1)))
10900 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10901 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10902 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10906 = gen_lowpart_for_combine
10908 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10909 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10913 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10914 (eq (and (lshiftrt X) 1) 0). */
10915 if (const_op
== 0 && equality_comparison_p
10916 && XEXP (op0
, 1) == const1_rtx
10917 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10918 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10920 op0
= simplify_and_const_int
10922 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10923 XEXP (XEXP (op0
, 0), 1)),
10924 (HOST_WIDE_INT
) 1);
10925 code
= (code
== NE
? EQ
: NE
);
10931 /* If we have (compare (ashift FOO N) (const_int C)) and
10932 the high order N bits of FOO (N+1 if an inequality comparison)
10933 are known to be zero, we can do this by comparing FOO with C
10934 shifted right N bits so long as the low-order N bits of C are
10936 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10937 && INTVAL (XEXP (op0
, 1)) >= 0
10938 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10939 < HOST_BITS_PER_WIDE_INT
)
10941 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10942 && mode_width
<= HOST_BITS_PER_WIDE_INT
10943 && (nonzero_bits (XEXP (op0
, 0), mode
)
10944 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10945 + ! equality_comparison_p
))) == 0)
10947 /* We must perform a logical shift, not an arithmetic one,
10948 as we want the top N bits of C to be zero. */
10949 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10951 temp
>>= INTVAL (XEXP (op0
, 1));
10952 op1
= gen_int_mode (temp
, mode
);
10953 op0
= XEXP (op0
, 0);
10957 /* If we are doing a sign bit comparison, it means we are testing
10958 a particular bit. Convert it to the appropriate AND. */
10959 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10960 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10962 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10965 - INTVAL (XEXP (op0
, 1)))));
10966 code
= (code
== LT
? NE
: EQ
);
10970 /* If this an equality comparison with zero and we are shifting
10971 the low bit to the sign bit, we can convert this to an AND of the
10973 if (const_op
== 0 && equality_comparison_p
10974 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10975 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10978 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10979 (HOST_WIDE_INT
) 1);
10985 /* If this is an equality comparison with zero, we can do this
10986 as a logical shift, which might be much simpler. */
10987 if (equality_comparison_p
&& const_op
== 0
10988 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10990 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10992 INTVAL (XEXP (op0
, 1)));
10996 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10997 do the comparison in a narrower mode. */
10998 if (! unsigned_comparison_p
10999 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11000 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11001 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11002 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11003 MODE_INT
, 1)) != BLKmode
11004 && (((unsigned HOST_WIDE_INT
) const_op
11005 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11006 <= GET_MODE_MASK (tmode
)))
11008 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11012 /* Likewise if OP0 is a PLUS of a sign extension with a
11013 constant, which is usually represented with the PLUS
11014 between the shifts. */
11015 if (! unsigned_comparison_p
11016 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11017 && GET_CODE (XEXP (op0
, 0)) == PLUS
11018 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11019 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11020 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11021 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11022 MODE_INT
, 1)) != BLKmode
11023 && (((unsigned HOST_WIDE_INT
) const_op
11024 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11025 <= GET_MODE_MASK (tmode
)))
11027 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11028 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11029 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11032 op0
= gen_binary (PLUS
, tmode
,
11033 gen_lowpart_for_combine (tmode
, inner
),
11038 /* ... fall through ... */
11040 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11041 the low order N bits of FOO are known to be zero, we can do this
11042 by comparing FOO with C shifted left N bits so long as no
11043 overflow occurs. */
11044 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11045 && INTVAL (XEXP (op0
, 1)) >= 0
11046 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11047 && mode_width
<= HOST_BITS_PER_WIDE_INT
11048 && (nonzero_bits (XEXP (op0
, 0), mode
)
11049 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11050 && (((unsigned HOST_WIDE_INT
) const_op
11051 + (GET_CODE (op0
) != LSHIFTRT
11052 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11055 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11057 /* If the shift was logical, then we must make the condition
11059 if (GET_CODE (op0
) == LSHIFTRT
)
11060 code
= unsigned_condition (code
);
11062 const_op
<<= INTVAL (XEXP (op0
, 1));
11063 op1
= GEN_INT (const_op
);
11064 op0
= XEXP (op0
, 0);
11068 /* If we are using this shift to extract just the sign bit, we
11069 can replace this with an LT or GE comparison. */
11071 && (equality_comparison_p
|| sign_bit_comparison_p
)
11072 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11073 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11076 op0
= XEXP (op0
, 0);
11077 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11089 /* Now make any compound operations involved in this comparison. Then,
11090 check for an outmost SUBREG on OP0 that is not doing anything or is
11091 paradoxical. The latter transformation must only be performed when
11092 it is known that the "extra" bits will be the same in op0 and op1 or
11093 that they don't matter. There are three cases to consider:
11095 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11096 care bits and we can assume they have any convenient value. So
11097 making the transformation is safe.
11099 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11100 In this case the upper bits of op0 are undefined. We should not make
11101 the simplification in that case as we do not know the contents of
11104 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11105 NIL. In that case we know those bits are zeros or ones. We must
11106 also be sure that they are the same as the upper bits of op1.
11108 We can never remove a SUBREG for a non-equality comparison because
11109 the sign bit is in a different place in the underlying object. */
11111 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11112 op1
= make_compound_operation (op1
, SET
);
11114 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11115 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11117 && GET_CODE (SUBREG_REG (op0
)) == REG
11118 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11119 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11120 && (code
== NE
|| code
== EQ
))
11122 if (GET_MODE_SIZE (GET_MODE (op0
))
11123 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11125 op0
= SUBREG_REG (op0
);
11126 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11128 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11129 <= HOST_BITS_PER_WIDE_INT
)
11130 && (nonzero_bits (SUBREG_REG (op0
),
11131 GET_MODE (SUBREG_REG (op0
)))
11132 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11134 tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)), op1
);
11136 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11137 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11138 op0
= SUBREG_REG (op0
), op1
= tem
;
11142 /* We now do the opposite procedure: Some machines don't have compare
11143 insns in all modes. If OP0's mode is an integer mode smaller than a
11144 word and we can't do a compare in that mode, see if there is a larger
11145 mode for which we can do the compare. There are a number of cases in
11146 which we can use the wider mode. */
11148 mode
= GET_MODE (op0
);
11149 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11150 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11151 && ! have_insn_for (COMPARE
, mode
))
11152 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11154 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11155 tmode
= GET_MODE_WIDER_MODE (tmode
))
11156 if (have_insn_for (COMPARE
, tmode
))
11160 /* If the only nonzero bits in OP0 and OP1 are those in the
11161 narrower mode and this is an equality or unsigned comparison,
11162 we can use the wider mode. Similarly for sign-extended
11163 values, in which case it is true for all comparisons. */
11164 zero_extended
= ((code
== EQ
|| code
== NE
11165 || code
== GEU
|| code
== GTU
11166 || code
== LEU
|| code
== LTU
)
11167 && (nonzero_bits (op0
, tmode
)
11168 & ~GET_MODE_MASK (mode
)) == 0
11169 && ((GET_CODE (op1
) == CONST_INT
11170 || (nonzero_bits (op1
, tmode
)
11171 & ~GET_MODE_MASK (mode
)) == 0)));
11174 || ((num_sign_bit_copies (op0
, tmode
)
11175 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11176 - GET_MODE_BITSIZE (mode
)))
11177 && (num_sign_bit_copies (op1
, tmode
)
11178 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11179 - GET_MODE_BITSIZE (mode
)))))
11181 /* If OP0 is an AND and we don't have an AND in MODE either,
11182 make a new AND in the proper mode. */
11183 if (GET_CODE (op0
) == AND
11184 && !have_insn_for (AND
, mode
))
11185 op0
= gen_binary (AND
, tmode
,
11186 gen_lowpart_for_combine (tmode
,
11188 gen_lowpart_for_combine (tmode
,
11191 op0
= gen_lowpart_for_combine (tmode
, op0
);
11192 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11193 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11194 op1
= gen_lowpart_for_combine (tmode
, op1
);
11198 /* If this is a test for negative, we can make an explicit
11199 test of the sign bit. */
11201 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11202 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11204 op0
= gen_binary (AND
, tmode
,
11205 gen_lowpart_for_combine (tmode
, op0
),
11206 GEN_INT ((HOST_WIDE_INT
) 1
11207 << (GET_MODE_BITSIZE (mode
) - 1)));
11208 code
= (code
== LT
) ? NE
: EQ
;
11213 #ifdef CANONICALIZE_COMPARISON
11214 /* If this machine only supports a subset of valid comparisons, see if we
11215 can convert an unsupported one into a supported one. */
11216 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11225 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11226 searching backward. */
11227 static enum rtx_code
11228 combine_reversed_comparison_code (exp
)
11231 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11234 if (code1
!= UNKNOWN
11235 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11237 /* Otherwise try and find where the condition codes were last set and
11239 x
= get_last_value (XEXP (exp
, 0));
11240 if (!x
|| GET_CODE (x
) != COMPARE
)
11242 return reversed_comparison_code_parts (GET_CODE (exp
),
11243 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11245 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11246 Return NULL_RTX in case we fail to do the reversal. */
11248 reversed_comparison (exp
, mode
, op0
, op1
)
11250 enum machine_mode mode
;
11252 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11253 if (reversed_code
== UNKNOWN
)
11256 return gen_binary (reversed_code
, mode
, op0
, op1
);
11259 /* Utility function for following routine. Called when X is part of a value
11260 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11261 for each register mentioned. Similar to mention_regs in cse.c */
11264 update_table_tick (x
)
11267 enum rtx_code code
= GET_CODE (x
);
11268 const char *fmt
= GET_RTX_FORMAT (code
);
11273 unsigned int regno
= REGNO (x
);
11274 unsigned int endregno
11275 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11276 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11279 for (r
= regno
; r
< endregno
; r
++)
11280 reg_last_set_table_tick
[r
] = label_tick
;
11285 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11286 /* Note that we can't have an "E" in values stored; see
11287 get_last_value_validate. */
11289 update_table_tick (XEXP (x
, i
));
11292 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11293 are saying that the register is clobbered and we no longer know its
11294 value. If INSN is zero, don't update reg_last_set; this is only permitted
11295 with VALUE also zero and is used to invalidate the register. */
11298 record_value_for_reg (reg
, insn
, value
)
11303 unsigned int regno
= REGNO (reg
);
11304 unsigned int endregno
11305 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11306 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11309 /* If VALUE contains REG and we have a previous value for REG, substitute
11310 the previous value. */
11311 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11315 /* Set things up so get_last_value is allowed to see anything set up to
11317 subst_low_cuid
= INSN_CUID (insn
);
11318 tem
= get_last_value (reg
);
11320 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11321 it isn't going to be useful and will take a lot of time to process,
11322 so just use the CLOBBER. */
11326 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11327 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11328 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11329 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11330 tem
= XEXP (tem
, 0);
11332 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11336 /* For each register modified, show we don't know its value, that
11337 we don't know about its bitwise content, that its value has been
11338 updated, and that we don't know the location of the death of the
11340 for (i
= regno
; i
< endregno
; i
++)
11343 reg_last_set
[i
] = insn
;
11345 reg_last_set_value
[i
] = 0;
11346 reg_last_set_mode
[i
] = 0;
11347 reg_last_set_nonzero_bits
[i
] = 0;
11348 reg_last_set_sign_bit_copies
[i
] = 0;
11349 reg_last_death
[i
] = 0;
11352 /* Mark registers that are being referenced in this value. */
11354 update_table_tick (value
);
11356 /* Now update the status of each register being set.
11357 If someone is using this register in this block, set this register
11358 to invalid since we will get confused between the two lives in this
11359 basic block. This makes using this register always invalid. In cse, we
11360 scan the table to invalidate all entries using this register, but this
11361 is too much work for us. */
11363 for (i
= regno
; i
< endregno
; i
++)
11365 reg_last_set_label
[i
] = label_tick
;
11366 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11367 reg_last_set_invalid
[i
] = 1;
11369 reg_last_set_invalid
[i
] = 0;
11372 /* The value being assigned might refer to X (like in "x++;"). In that
11373 case, we must replace it with (clobber (const_int 0)) to prevent
11375 if (value
&& ! get_last_value_validate (&value
, insn
,
11376 reg_last_set_label
[regno
], 0))
11378 value
= copy_rtx (value
);
11379 if (! get_last_value_validate (&value
, insn
,
11380 reg_last_set_label
[regno
], 1))
11384 /* For the main register being modified, update the value, the mode, the
11385 nonzero bits, and the number of sign bit copies. */
11387 reg_last_set_value
[regno
] = value
;
11391 enum machine_mode mode
= GET_MODE (reg
);
11392 subst_low_cuid
= INSN_CUID (insn
);
11393 reg_last_set_mode
[regno
] = mode
;
11394 if (GET_MODE_CLASS (mode
) == MODE_INT
11395 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11396 mode
= nonzero_bits_mode
;
11397 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11398 reg_last_set_sign_bit_copies
[regno
]
11399 = num_sign_bit_copies (value
, GET_MODE (reg
));
11403 /* Called via note_stores from record_dead_and_set_regs to handle one
11404 SET or CLOBBER in an insn. DATA is the instruction in which the
11405 set is occurring. */
11408 record_dead_and_set_regs_1 (dest
, setter
, data
)
11412 rtx record_dead_insn
= (rtx
) data
;
11414 if (GET_CODE (dest
) == SUBREG
)
11415 dest
= SUBREG_REG (dest
);
11417 if (GET_CODE (dest
) == REG
)
11419 /* If we are setting the whole register, we know its value. Otherwise
11420 show that we don't know the value. We can handle SUBREG in
11422 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11423 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11424 else if (GET_CODE (setter
) == SET
11425 && GET_CODE (SET_DEST (setter
)) == SUBREG
11426 && SUBREG_REG (SET_DEST (setter
)) == dest
11427 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11428 && subreg_lowpart_p (SET_DEST (setter
)))
11429 record_value_for_reg (dest
, record_dead_insn
,
11430 gen_lowpart_for_combine (GET_MODE (dest
),
11431 SET_SRC (setter
)));
11433 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11435 else if (GET_CODE (dest
) == MEM
11436 /* Ignore pushes, they clobber nothing. */
11437 && ! push_operand (dest
, GET_MODE (dest
)))
11438 mem_last_set
= INSN_CUID (record_dead_insn
);
11441 /* Update the records of when each REG was most recently set or killed
11442 for the things done by INSN. This is the last thing done in processing
11443 INSN in the combiner loop.
11445 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11446 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11447 and also the similar information mem_last_set (which insn most recently
11448 modified memory) and last_call_cuid (which insn was the most recent
11449 subroutine call). */
11452 record_dead_and_set_regs (insn
)
11458 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11460 if (REG_NOTE_KIND (link
) == REG_DEAD
11461 && GET_CODE (XEXP (link
, 0)) == REG
)
11463 unsigned int regno
= REGNO (XEXP (link
, 0));
11464 unsigned int endregno
11465 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11466 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11469 for (i
= regno
; i
< endregno
; i
++)
11470 reg_last_death
[i
] = insn
;
11472 else if (REG_NOTE_KIND (link
) == REG_INC
)
11473 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11476 if (GET_CODE (insn
) == CALL_INSN
)
11478 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11479 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11481 reg_last_set_value
[i
] = 0;
11482 reg_last_set_mode
[i
] = 0;
11483 reg_last_set_nonzero_bits
[i
] = 0;
11484 reg_last_set_sign_bit_copies
[i
] = 0;
11485 reg_last_death
[i
] = 0;
11488 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11490 /* Don't bother recording what this insn does. It might set the
11491 return value register, but we can't combine into a call
11492 pattern anyway, so there's no point trying (and it may cause
11493 a crash, if e.g. we wind up asking for last_set_value of a
11494 SUBREG of the return value register). */
11498 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11501 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11502 register present in the SUBREG, so for each such SUBREG go back and
11503 adjust nonzero and sign bit information of the registers that are
11504 known to have some zero/sign bits set.
11506 This is needed because when combine blows the SUBREGs away, the
11507 information on zero/sign bits is lost and further combines can be
11508 missed because of that. */
11511 record_promoted_value (insn
, subreg
)
11516 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11517 enum machine_mode mode
= GET_MODE (subreg
);
11519 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11522 for (links
= LOG_LINKS (insn
); links
;)
11524 insn
= XEXP (links
, 0);
11525 set
= single_set (insn
);
11527 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11528 || REGNO (SET_DEST (set
)) != regno
11529 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11531 links
= XEXP (links
, 1);
11535 if (reg_last_set
[regno
] == insn
)
11537 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11538 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11541 if (GET_CODE (SET_SRC (set
)) == REG
)
11543 regno
= REGNO (SET_SRC (set
));
11544 links
= LOG_LINKS (insn
);
11551 /* Scan X for promoted SUBREGs. For each one found,
11552 note what it implies to the registers used in it. */
11555 check_promoted_subreg (insn
, x
)
11559 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11560 && GET_CODE (SUBREG_REG (x
)) == REG
)
11561 record_promoted_value (insn
, x
);
11564 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11567 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11571 check_promoted_subreg (insn
, XEXP (x
, i
));
11575 if (XVEC (x
, i
) != 0)
11576 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11577 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11583 /* Utility routine for the following function. Verify that all the registers
11584 mentioned in *LOC are valid when *LOC was part of a value set when
11585 label_tick == TICK. Return 0 if some are not.
11587 If REPLACE is nonzero, replace the invalid reference with
11588 (clobber (const_int 0)) and return 1. This replacement is useful because
11589 we often can get useful information about the form of a value (e.g., if
11590 it was produced by a shift that always produces -1 or 0) even though
11591 we don't know exactly what registers it was produced from. */
11594 get_last_value_validate (loc
, insn
, tick
, replace
)
11601 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11602 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11605 if (GET_CODE (x
) == REG
)
11607 unsigned int regno
= REGNO (x
);
11608 unsigned int endregno
11609 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11610 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11613 for (j
= regno
; j
< endregno
; j
++)
11614 if (reg_last_set_invalid
[j
]
11615 /* If this is a pseudo-register that was only set once and not
11616 live at the beginning of the function, it is always valid. */
11617 || (! (regno
>= FIRST_PSEUDO_REGISTER
11618 && REG_N_SETS (regno
) == 1
11619 && (! REGNO_REG_SET_P
11620 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11621 && reg_last_set_label
[j
] > tick
))
11624 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11630 /* If this is a memory reference, make sure that there were
11631 no stores after it that might have clobbered the value. We don't
11632 have alias info, so we assume any store invalidates it. */
11633 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11634 && INSN_CUID (insn
) <= mem_last_set
)
11637 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11641 for (i
= 0; i
< len
; i
++)
11643 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11644 /* Don't bother with these. They shouldn't occur anyway. */
11648 /* If we haven't found a reason for it to be invalid, it is valid. */
11652 /* Get the last value assigned to X, if known. Some registers
11653 in the value may be replaced with (clobber (const_int 0)) if their value
11654 is known longer known reliably. */
11660 unsigned int regno
;
11663 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11664 then convert it to the desired mode. If this is a paradoxical SUBREG,
11665 we cannot predict what values the "extra" bits might have. */
11666 if (GET_CODE (x
) == SUBREG
11667 && subreg_lowpart_p (x
)
11668 && (GET_MODE_SIZE (GET_MODE (x
))
11669 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11670 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11671 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11673 if (GET_CODE (x
) != REG
)
11677 value
= reg_last_set_value
[regno
];
11679 /* If we don't have a value, or if it isn't for this basic block and
11680 it's either a hard register, set more than once, or it's a live
11681 at the beginning of the function, return 0.
11683 Because if it's not live at the beginning of the function then the reg
11684 is always set before being used (is never used without being set).
11685 And, if it's set only once, and it's always set before use, then all
11686 uses must have the same last value, even if it's not from this basic
11690 || (reg_last_set_label
[regno
] != label_tick
11691 && (regno
< FIRST_PSEUDO_REGISTER
11692 || REG_N_SETS (regno
) != 1
11693 || (REGNO_REG_SET_P
11694 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11697 /* If the value was set in a later insn than the ones we are processing,
11698 we can't use it even if the register was only set once. */
11699 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11702 /* If the value has all its registers valid, return it. */
11703 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11704 reg_last_set_label
[regno
], 0))
11707 /* Otherwise, make a copy and replace any invalid register with
11708 (clobber (const_int 0)). If that fails for some reason, return 0. */
11710 value
= copy_rtx (value
);
11711 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11712 reg_last_set_label
[regno
], 1))
11718 /* Return nonzero if expression X refers to a REG or to memory
11719 that is set in an instruction more recent than FROM_CUID. */
11722 use_crosses_set_p (x
, from_cuid
)
11728 enum rtx_code code
= GET_CODE (x
);
11732 unsigned int regno
= REGNO (x
);
11733 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11734 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11736 #ifdef PUSH_ROUNDING
11737 /* Don't allow uses of the stack pointer to be moved,
11738 because we don't know whether the move crosses a push insn. */
11739 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11742 for (; regno
< endreg
; regno
++)
11743 if (reg_last_set
[regno
]
11744 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11749 if (code
== MEM
&& mem_last_set
> from_cuid
)
11752 fmt
= GET_RTX_FORMAT (code
);
11754 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11759 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11760 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11763 else if (fmt
[i
] == 'e'
11764 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11770 /* Define three variables used for communication between the following
11773 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11774 static int reg_dead_flag
;
11776 /* Function called via note_stores from reg_dead_at_p.
11778 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11779 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11782 reg_dead_at_p_1 (dest
, x
, data
)
11785 void *data ATTRIBUTE_UNUSED
;
11787 unsigned int regno
, endregno
;
11789 if (GET_CODE (dest
) != REG
)
11792 regno
= REGNO (dest
);
11793 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11794 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11796 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11797 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11800 /* Return nonzero if REG is known to be dead at INSN.
11802 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11803 referencing REG, it is dead. If we hit a SET referencing REG, it is
11804 live. Otherwise, see if it is live or dead at the start of the basic
11805 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11806 must be assumed to be always live. */
11809 reg_dead_at_p (reg
, insn
)
11816 /* Set variables for reg_dead_at_p_1. */
11817 reg_dead_regno
= REGNO (reg
);
11818 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11819 ? HARD_REGNO_NREGS (reg_dead_regno
,
11825 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11826 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11828 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11829 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11833 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11834 beginning of function. */
11835 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11836 insn
= prev_nonnote_insn (insn
))
11838 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11840 return reg_dead_flag
== 1 ? 1 : 0;
11842 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11846 /* Get the basic block that we were in. */
11848 block
= ENTRY_BLOCK_PTR
->next_bb
;
11851 FOR_EACH_BB (block
)
11852 if (insn
== block
->head
)
11855 if (block
== EXIT_BLOCK_PTR
)
11859 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11860 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11866 /* Note hard registers in X that are used. This code is similar to
11867 that in flow.c, but much simpler since we don't care about pseudos. */
11870 mark_used_regs_combine (x
)
11873 RTX_CODE code
= GET_CODE (x
);
11874 unsigned int regno
;
11887 case ADDR_DIFF_VEC
:
11890 /* CC0 must die in the insn after it is set, so we don't need to take
11891 special note of it here. */
11897 /* If we are clobbering a MEM, mark any hard registers inside the
11898 address as used. */
11899 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11900 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11905 /* A hard reg in a wide mode may really be multiple registers.
11906 If so, mark all of them just like the first. */
11907 if (regno
< FIRST_PSEUDO_REGISTER
)
11909 unsigned int endregno
, r
;
11911 /* None of this applies to the stack, frame or arg pointers. */
11912 if (regno
== STACK_POINTER_REGNUM
11913 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11914 || regno
== HARD_FRAME_POINTER_REGNUM
11916 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11917 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11919 || regno
== FRAME_POINTER_REGNUM
)
11922 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11923 for (r
= regno
; r
< endregno
; r
++)
11924 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11930 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11932 rtx testreg
= SET_DEST (x
);
11934 while (GET_CODE (testreg
) == SUBREG
11935 || GET_CODE (testreg
) == ZERO_EXTRACT
11936 || GET_CODE (testreg
) == SIGN_EXTRACT
11937 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11938 testreg
= XEXP (testreg
, 0);
11940 if (GET_CODE (testreg
) == MEM
)
11941 mark_used_regs_combine (XEXP (testreg
, 0));
11943 mark_used_regs_combine (SET_SRC (x
));
11951 /* Recursively scan the operands of this expression. */
11954 const char *fmt
= GET_RTX_FORMAT (code
);
11956 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11959 mark_used_regs_combine (XEXP (x
, i
));
11960 else if (fmt
[i
] == 'E')
11964 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11965 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11971 /* Remove register number REGNO from the dead registers list of INSN.
11973 Return the note used to record the death, if there was one. */
11976 remove_death (regno
, insn
)
11977 unsigned int regno
;
11980 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11984 REG_N_DEATHS (regno
)--;
11985 remove_note (insn
, note
);
11991 /* For each register (hardware or pseudo) used within expression X, if its
11992 death is in an instruction with cuid between FROM_CUID (inclusive) and
11993 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11994 list headed by PNOTES.
11996 That said, don't move registers killed by maybe_kill_insn.
11998 This is done when X is being merged by combination into TO_INSN. These
11999 notes will then be distributed as needed. */
12002 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
12004 rtx maybe_kill_insn
;
12011 enum rtx_code code
= GET_CODE (x
);
12015 unsigned int regno
= REGNO (x
);
12016 rtx where_dead
= reg_last_death
[regno
];
12017 rtx before_dead
, after_dead
;
12019 /* Don't move the register if it gets killed in between from and to. */
12020 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12021 && ! reg_referenced_p (x
, maybe_kill_insn
))
12024 /* WHERE_DEAD could be a USE insn made by combine, so first we
12025 make sure that we have insns with valid INSN_CUID values. */
12026 before_dead
= where_dead
;
12027 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12028 before_dead
= PREV_INSN (before_dead
);
12030 after_dead
= where_dead
;
12031 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12032 after_dead
= NEXT_INSN (after_dead
);
12034 if (before_dead
&& after_dead
12035 && INSN_CUID (before_dead
) >= from_cuid
12036 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12037 || (where_dead
!= after_dead
12038 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12040 rtx note
= remove_death (regno
, where_dead
);
12042 /* It is possible for the call above to return 0. This can occur
12043 when reg_last_death points to I2 or I1 that we combined with.
12044 In that case make a new note.
12046 We must also check for the case where X is a hard register
12047 and NOTE is a death note for a range of hard registers
12048 including X. In that case, we must put REG_DEAD notes for
12049 the remaining registers in place of NOTE. */
12051 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12052 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12053 > GET_MODE_SIZE (GET_MODE (x
))))
12055 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12056 unsigned int deadend
12057 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12058 GET_MODE (XEXP (note
, 0))));
12059 unsigned int ourend
12060 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12063 for (i
= deadregno
; i
< deadend
; i
++)
12064 if (i
< regno
|| i
>= ourend
)
12065 REG_NOTES (where_dead
)
12066 = gen_rtx_EXPR_LIST (REG_DEAD
,
12068 REG_NOTES (where_dead
));
12071 /* If we didn't find any note, or if we found a REG_DEAD note that
12072 covers only part of the given reg, and we have a multi-reg hard
12073 register, then to be safe we must check for REG_DEAD notes
12074 for each register other than the first. They could have
12075 their own REG_DEAD notes lying around. */
12076 else if ((note
== 0
12078 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12079 < GET_MODE_SIZE (GET_MODE (x
)))))
12080 && regno
< FIRST_PSEUDO_REGISTER
12081 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12083 unsigned int ourend
12084 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12085 unsigned int i
, offset
;
12089 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12093 for (i
= regno
+ offset
; i
< ourend
; i
++)
12094 move_deaths (regno_reg_rtx
[i
],
12095 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12098 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12100 XEXP (note
, 1) = *pnotes
;
12104 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12106 REG_N_DEATHS (regno
)++;
12112 else if (GET_CODE (x
) == SET
)
12114 rtx dest
= SET_DEST (x
);
12116 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12118 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12119 that accesses one word of a multi-word item, some
12120 piece of everything register in the expression is used by
12121 this insn, so remove any old death. */
12122 /* ??? So why do we test for equality of the sizes? */
12124 if (GET_CODE (dest
) == ZERO_EXTRACT
12125 || GET_CODE (dest
) == STRICT_LOW_PART
12126 || (GET_CODE (dest
) == SUBREG
12127 && (((GET_MODE_SIZE (GET_MODE (dest
))
12128 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12129 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12130 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12132 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12136 /* If this is some other SUBREG, we know it replaces the entire
12137 value, so use that as the destination. */
12138 if (GET_CODE (dest
) == SUBREG
)
12139 dest
= SUBREG_REG (dest
);
12141 /* If this is a MEM, adjust deaths of anything used in the address.
12142 For a REG (the only other possibility), the entire value is
12143 being replaced so the old value is not used in this insn. */
12145 if (GET_CODE (dest
) == MEM
)
12146 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12151 else if (GET_CODE (x
) == CLOBBER
)
12154 len
= GET_RTX_LENGTH (code
);
12155 fmt
= GET_RTX_FORMAT (code
);
12157 for (i
= 0; i
< len
; i
++)
12162 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12163 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12166 else if (fmt
[i
] == 'e')
12167 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12171 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12172 pattern of an insn. X must be a REG. */
12175 reg_bitfield_target_p (x
, body
)
12181 if (GET_CODE (body
) == SET
)
12183 rtx dest
= SET_DEST (body
);
12185 unsigned int regno
, tregno
, endregno
, endtregno
;
12187 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12188 target
= XEXP (dest
, 0);
12189 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12190 target
= SUBREG_REG (XEXP (dest
, 0));
12194 if (GET_CODE (target
) == SUBREG
)
12195 target
= SUBREG_REG (target
);
12197 if (GET_CODE (target
) != REG
)
12200 tregno
= REGNO (target
), regno
= REGNO (x
);
12201 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12202 return target
== x
;
12204 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12205 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12207 return endregno
> tregno
&& regno
< endtregno
;
12210 else if (GET_CODE (body
) == PARALLEL
)
12211 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12212 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12218 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12219 as appropriate. I3 and I2 are the insns resulting from the combination
12220 insns including FROM (I2 may be zero).
12222 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12223 not need REG_DEAD notes because they are being substituted for. This
12224 saves searching in the most common cases.
12226 Each note in the list is either ignored or placed on some insns, depending
12227 on the type of note. */
12230 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
12234 rtx elim_i2
, elim_i1
;
12236 rtx note
, next_note
;
12239 for (note
= notes
; note
; note
= next_note
)
12241 rtx place
= 0, place2
= 0;
12243 /* If this NOTE references a pseudo register, ensure it references
12244 the latest copy of that register. */
12245 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12246 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12247 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12249 next_note
= XEXP (note
, 1);
12250 switch (REG_NOTE_KIND (note
))
12254 case REG_EXEC_COUNT
:
12255 /* Doesn't matter much where we put this, as long as it's somewhere.
12256 It is preferable to keep these notes on branches, which is most
12257 likely to be i3. */
12261 case REG_VTABLE_REF
:
12262 /* ??? Should remain with *a particular* memory load. Given the
12263 nature of vtable data, the last insn seems relatively safe. */
12267 case REG_NON_LOCAL_GOTO
:
12268 if (GET_CODE (i3
) == JUMP_INSN
)
12270 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12276 case REG_EH_REGION
:
12277 /* These notes must remain with the call or trapping instruction. */
12278 if (GET_CODE (i3
) == CALL_INSN
)
12280 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12282 else if (flag_non_call_exceptions
)
12284 if (may_trap_p (i3
))
12286 else if (i2
&& may_trap_p (i2
))
12288 /* ??? Otherwise assume we've combined things such that we
12289 can now prove that the instructions can't trap. Drop the
12290 note in this case. */
12298 /* These notes must remain with the call. It should not be
12299 possible for both I2 and I3 to be a call. */
12300 if (GET_CODE (i3
) == CALL_INSN
)
12302 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12309 /* Any clobbers for i3 may still exist, and so we must process
12310 REG_UNUSED notes from that insn.
12312 Any clobbers from i2 or i1 can only exist if they were added by
12313 recog_for_combine. In that case, recog_for_combine created the
12314 necessary REG_UNUSED notes. Trying to keep any original
12315 REG_UNUSED notes from these insns can cause incorrect output
12316 if it is for the same register as the original i3 dest.
12317 In that case, we will notice that the register is set in i3,
12318 and then add a REG_UNUSED note for the destination of i3, which
12319 is wrong. However, it is possible to have REG_UNUSED notes from
12320 i2 or i1 for register which were both used and clobbered, so
12321 we keep notes from i2 or i1 if they will turn into REG_DEAD
12324 /* If this register is set or clobbered in I3, put the note there
12325 unless there is one already. */
12326 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12328 if (from_insn
!= i3
)
12331 if (! (GET_CODE (XEXP (note
, 0)) == REG
12332 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12333 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12336 /* Otherwise, if this register is used by I3, then this register
12337 now dies here, so we must put a REG_DEAD note here unless there
12339 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12340 && ! (GET_CODE (XEXP (note
, 0)) == REG
12341 ? find_regno_note (i3
, REG_DEAD
,
12342 REGNO (XEXP (note
, 0)))
12343 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12345 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12353 /* These notes say something about results of an insn. We can
12354 only support them if they used to be on I3 in which case they
12355 remain on I3. Otherwise they are ignored.
12357 If the note refers to an expression that is not a constant, we
12358 must also ignore the note since we cannot tell whether the
12359 equivalence is still true. It might be possible to do
12360 slightly better than this (we only have a problem if I2DEST
12361 or I1DEST is present in the expression), but it doesn't
12362 seem worth the trouble. */
12364 if (from_insn
== i3
12365 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12370 case REG_NO_CONFLICT
:
12371 /* These notes say something about how a register is used. They must
12372 be present on any use of the register in I2 or I3. */
12373 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12376 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12386 /* This can show up in several ways -- either directly in the
12387 pattern, or hidden off in the constant pool with (or without?)
12388 a REG_EQUAL note. */
12389 /* ??? Ignore the without-reg_equal-note problem for now. */
12390 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12391 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12392 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12393 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12397 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12398 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12399 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12400 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12408 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12409 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12410 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12412 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12414 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12415 LABEL_NUSES (JUMP_LABEL (place
))--;
12418 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12420 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12422 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12423 LABEL_NUSES (JUMP_LABEL (place2
))--;
12430 /* These notes say something about the value of a register prior
12431 to the execution of an insn. It is too much trouble to see
12432 if the note is still correct in all situations. It is better
12433 to simply delete it. */
12437 /* If the insn previously containing this note still exists,
12438 put it back where it was. Otherwise move it to the previous
12439 insn. Adjust the corresponding REG_LIBCALL note. */
12440 if (GET_CODE (from_insn
) != NOTE
)
12444 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12445 place
= prev_real_insn (from_insn
);
12447 XEXP (tem
, 0) = place
;
12448 /* If we're deleting the last remaining instruction of a
12449 libcall sequence, don't add the notes. */
12450 else if (XEXP (note
, 0) == from_insn
)
12456 /* This is handled similarly to REG_RETVAL. */
12457 if (GET_CODE (from_insn
) != NOTE
)
12461 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12462 place
= next_real_insn (from_insn
);
12464 XEXP (tem
, 0) = place
;
12465 /* If we're deleting the last remaining instruction of a
12466 libcall sequence, don't add the notes. */
12467 else if (XEXP (note
, 0) == from_insn
)
12473 /* If the register is used as an input in I3, it dies there.
12474 Similarly for I2, if it is nonzero and adjacent to I3.
12476 If the register is not used as an input in either I3 or I2
12477 and it is not one of the registers we were supposed to eliminate,
12478 there are two possibilities. We might have a non-adjacent I2
12479 or we might have somehow eliminated an additional register
12480 from a computation. For example, we might have had A & B where
12481 we discover that B will always be zero. In this case we will
12482 eliminate the reference to A.
12484 In both cases, we must search to see if we can find a previous
12485 use of A and put the death note there. */
12488 && GET_CODE (from_insn
) == CALL_INSN
12489 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12491 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12493 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12494 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12497 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12498 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12503 basic_block bb
= this_basic_block
;
12505 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12507 if (! INSN_P (tem
))
12509 if (tem
== bb
->head
)
12514 /* If the register is being set at TEM, see if that is all
12515 TEM is doing. If so, delete TEM. Otherwise, make this
12516 into a REG_UNUSED note instead. */
12517 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12519 rtx set
= single_set (tem
);
12520 rtx inner_dest
= 0;
12522 rtx cc0_setter
= NULL_RTX
;
12526 for (inner_dest
= SET_DEST (set
);
12527 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12528 || GET_CODE (inner_dest
) == SUBREG
12529 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12530 inner_dest
= XEXP (inner_dest
, 0))
12533 /* Verify that it was the set, and not a clobber that
12534 modified the register.
12536 CC0 targets must be careful to maintain setter/user
12537 pairs. If we cannot delete the setter due to side
12538 effects, mark the user with an UNUSED note instead
12541 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12542 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12544 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12545 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12546 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12550 /* Move the notes and links of TEM elsewhere.
12551 This might delete other dead insns recursively.
12552 First set the pattern to something that won't use
12555 PATTERN (tem
) = pc_rtx
;
12557 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12558 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12559 distribute_links (LOG_LINKS (tem
));
12561 PUT_CODE (tem
, NOTE
);
12562 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12563 NOTE_SOURCE_FILE (tem
) = 0;
12566 /* Delete the setter too. */
12569 PATTERN (cc0_setter
) = pc_rtx
;
12571 distribute_notes (REG_NOTES (cc0_setter
),
12572 cc0_setter
, cc0_setter
,
12573 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12574 distribute_links (LOG_LINKS (cc0_setter
));
12576 PUT_CODE (cc0_setter
, NOTE
);
12577 NOTE_LINE_NUMBER (cc0_setter
)
12578 = NOTE_INSN_DELETED
;
12579 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12583 /* If the register is both set and used here, put the
12584 REG_DEAD note here, but place a REG_UNUSED note
12585 here too unless there already is one. */
12586 else if (reg_referenced_p (XEXP (note
, 0),
12591 if (! find_regno_note (tem
, REG_UNUSED
,
12592 REGNO (XEXP (note
, 0))))
12594 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12599 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12601 /* If there isn't already a REG_UNUSED note, put one
12603 if (! find_regno_note (tem
, REG_UNUSED
,
12604 REGNO (XEXP (note
, 0))))
12609 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12610 || (GET_CODE (tem
) == CALL_INSN
12611 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12615 /* If we are doing a 3->2 combination, and we have a
12616 register which formerly died in i3 and was not used
12617 by i2, which now no longer dies in i3 and is used in
12618 i2 but does not die in i2, and place is between i2
12619 and i3, then we may need to move a link from place to
12621 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12622 && INSN_CUID (place
) > INSN_CUID (i2
)
12624 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12625 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12627 rtx links
= LOG_LINKS (place
);
12628 LOG_LINKS (place
) = 0;
12629 distribute_links (links
);
12634 if (tem
== bb
->head
)
12638 /* We haven't found an insn for the death note and it
12639 is still a REG_DEAD note, but we have hit the beginning
12640 of the block. If the existing life info says the reg
12641 was dead, there's nothing left to do. Otherwise, we'll
12642 need to do a global life update after combine. */
12643 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12644 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12645 REGNO (XEXP (note
, 0))))
12647 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12652 /* If the register is set or already dead at PLACE, we needn't do
12653 anything with this note if it is still a REG_DEAD note.
12654 We can here if it is set at all, not if is it totally replace,
12655 which is what `dead_or_set_p' checks, so also check for it being
12658 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12660 unsigned int regno
= REGNO (XEXP (note
, 0));
12662 /* Similarly, if the instruction on which we want to place
12663 the note is a noop, we'll need do a global live update
12664 after we remove them in delete_noop_moves. */
12665 if (noop_move_p (place
))
12667 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12671 if (dead_or_set_p (place
, XEXP (note
, 0))
12672 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12674 /* Unless the register previously died in PLACE, clear
12675 reg_last_death. [I no longer understand why this is
12677 if (reg_last_death
[regno
] != place
)
12678 reg_last_death
[regno
] = 0;
12682 reg_last_death
[regno
] = place
;
12684 /* If this is a death note for a hard reg that is occupying
12685 multiple registers, ensure that we are still using all
12686 parts of the object. If we find a piece of the object
12687 that is unused, we must arrange for an appropriate REG_DEAD
12688 note to be added for it. However, we can't just emit a USE
12689 and tag the note to it, since the register might actually
12690 be dead; so we recourse, and the recursive call then finds
12691 the previous insn that used this register. */
12693 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12694 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12696 unsigned int endregno
12697 = regno
+ HARD_REGNO_NREGS (regno
,
12698 GET_MODE (XEXP (note
, 0)));
12702 for (i
= regno
; i
< endregno
; i
++)
12703 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12704 && ! find_regno_fusage (place
, USE
, i
))
12705 || dead_or_set_regno_p (place
, i
))
12710 /* Put only REG_DEAD notes for pieces that are
12711 not already dead or set. */
12713 for (i
= regno
; i
< endregno
;
12714 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12716 rtx piece
= regno_reg_rtx
[i
];
12717 basic_block bb
= this_basic_block
;
12719 if (! dead_or_set_p (place
, piece
)
12720 && ! reg_bitfield_target_p (piece
,
12724 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12726 distribute_notes (new_note
, place
, place
,
12727 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12729 else if (! refers_to_regno_p (i
, i
+ 1,
12730 PATTERN (place
), 0)
12731 && ! find_regno_fusage (place
, USE
, i
))
12732 for (tem
= PREV_INSN (place
); ;
12733 tem
= PREV_INSN (tem
))
12735 if (! INSN_P (tem
))
12737 if (tem
== bb
->head
)
12739 SET_BIT (refresh_blocks
,
12740 this_basic_block
->index
);
12746 if (dead_or_set_p (tem
, piece
)
12747 || reg_bitfield_target_p (piece
,
12751 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12766 /* Any other notes should not be present at this point in the
12773 XEXP (note
, 1) = REG_NOTES (place
);
12774 REG_NOTES (place
) = note
;
12776 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12777 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12778 && GET_CODE (XEXP (note
, 0)) == REG
)
12779 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12783 if ((REG_NOTE_KIND (note
) == REG_DEAD
12784 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12785 && GET_CODE (XEXP (note
, 0)) == REG
)
12786 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12788 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12789 REG_NOTE_KIND (note
),
12791 REG_NOTES (place2
));
12796 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12797 I3, I2, and I1 to new locations. This is also called in one case to
12798 add a link pointing at I3 when I3's destination is changed. */
12801 distribute_links (links
)
12804 rtx link
, next_link
;
12806 for (link
= links
; link
; link
= next_link
)
12812 next_link
= XEXP (link
, 1);
12814 /* If the insn that this link points to is a NOTE or isn't a single
12815 set, ignore it. In the latter case, it isn't clear what we
12816 can do other than ignore the link, since we can't tell which
12817 register it was for. Such links wouldn't be used by combine
12820 It is not possible for the destination of the target of the link to
12821 have been changed by combine. The only potential of this is if we
12822 replace I3, I2, and I1 by I3 and I2. But in that case the
12823 destination of I2 also remains unchanged. */
12825 if (GET_CODE (XEXP (link
, 0)) == NOTE
12826 || (set
= single_set (XEXP (link
, 0))) == 0)
12829 reg
= SET_DEST (set
);
12830 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12831 || GET_CODE (reg
) == SIGN_EXTRACT
12832 || GET_CODE (reg
) == STRICT_LOW_PART
)
12833 reg
= XEXP (reg
, 0);
12835 /* A LOG_LINK is defined as being placed on the first insn that uses
12836 a register and points to the insn that sets the register. Start
12837 searching at the next insn after the target of the link and stop
12838 when we reach a set of the register or the end of the basic block.
12840 Note that this correctly handles the link that used to point from
12841 I3 to I2. Also note that not much searching is typically done here
12842 since most links don't point very far away. */
12844 for (insn
= NEXT_INSN (XEXP (link
, 0));
12845 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12846 || this_basic_block
->next_bb
->head
!= insn
));
12847 insn
= NEXT_INSN (insn
))
12848 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12850 if (reg_referenced_p (reg
, PATTERN (insn
)))
12854 else if (GET_CODE (insn
) == CALL_INSN
12855 && find_reg_fusage (insn
, USE
, reg
))
12861 /* If we found a place to put the link, place it there unless there
12862 is already a link to the same insn as LINK at that point. */
12868 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12869 if (XEXP (link2
, 0) == XEXP (link
, 0))
12874 XEXP (link
, 1) = LOG_LINKS (place
);
12875 LOG_LINKS (place
) = link
;
12877 /* Set added_links_insn to the earliest insn we added a
12879 if (added_links_insn
== 0
12880 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12881 added_links_insn
= place
;
12887 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12893 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12894 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12895 insn
= NEXT_INSN (insn
);
12897 if (INSN_UID (insn
) > max_uid_cuid
)
12900 return INSN_CUID (insn
);
12904 dump_combine_stats (file
)
12909 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12910 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12914 dump_combine_total_stats (file
)
12919 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12920 total_attempts
, total_merges
, total_extras
, total_successes
);