1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #ifndef SHIFT_COUNT_TRUNCATED
95 #define SHIFT_COUNT_TRUNCATED 0
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 #define nonzero_bits(X, M) \
141 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
143 #define num_sign_bit_copies(X, M) \
144 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno
;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx
*reg_last_death
;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx
*reg_last_set
;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set
;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid
;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn
;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid
;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs
;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn
;
196 /* Basic block in which we are performing combines. */
197 static basic_block this_basic_block
;
199 /* A bitmap indicating which blocks had registers go dead at entry.
200 After combine, we'll need to re-do global life analysis with
201 those blocks as starting points. */
202 static sbitmap refresh_blocks
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if an
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; int i
;} old_contents
;
318 union {rtx
*r
; int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST (rtx
*, rtx
);
342 static void do_SUBST_INT (int *, int);
343 static void init_reg_last_arrays (void);
344 static void setup_incoming_promotions (void);
345 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
346 static int cant_combine_insn_p (rtx
);
347 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
348 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
349 static int contains_muldiv (rtx
);
350 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
351 static void undo_all (void);
352 static void undo_commit (void);
353 static rtx
*find_split_point (rtx
*, rtx
);
354 static rtx
subst (rtx
, rtx
, rtx
, int, int);
355 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
356 static rtx
simplify_if_then_else (rtx
);
357 static rtx
simplify_set (rtx
);
358 static rtx
simplify_logical (rtx
, int);
359 static rtx
expand_compound_operation (rtx
);
360 static rtx
expand_field_assignment (rtx
);
361 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
362 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
363 static rtx
extract_left_shift (rtx
, int);
364 static rtx
make_compound_operation (rtx
, enum rtx_code
);
365 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
366 unsigned HOST_WIDE_INT
*);
367 static rtx
force_to_mode (rtx
, enum machine_mode
,
368 unsigned HOST_WIDE_INT
, rtx
, int);
369 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
370 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
371 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
372 static rtx
make_field_assignment (rtx
);
373 static rtx
apply_distributive_law (rtx
);
374 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
375 unsigned HOST_WIDE_INT
);
376 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
377 rtx
, enum machine_mode
,
378 unsigned HOST_WIDE_INT
);
379 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
381 unsigned HOST_WIDE_INT
);
382 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
385 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
386 enum machine_mode
, unsigned int);
387 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
388 HOST_WIDE_INT
, enum machine_mode
, int *);
389 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
391 static int recog_for_combine (rtx
*, rtx
, rtx
*);
392 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
393 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
394 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
395 static void update_table_tick (rtx
);
396 static void record_value_for_reg (rtx
, rtx
, rtx
);
397 static void check_promoted_subreg (rtx
, rtx
);
398 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
399 static void record_dead_and_set_regs (rtx
);
400 static int get_last_value_validate (rtx
*, rtx
, int, int);
401 static rtx
get_last_value (rtx
);
402 static int use_crosses_set_p (rtx
, int);
403 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
404 static int reg_dead_at_p (rtx
, rtx
);
405 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
406 static int reg_bitfield_target_p (rtx
, rtx
);
407 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
408 static void distribute_links (rtx
);
409 static void mark_used_regs_combine (rtx
);
410 static int insn_cuid (rtx
);
411 static void record_promoted_value (rtx
, rtx
);
412 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
413 static enum rtx_code
combine_reversed_comparison_code (rtx
);
415 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
416 insn. The substitution can be undone by undo_all. If INTO is already
417 set to NEWVAL, do not record this change. Because computing NEWVAL might
418 also call SUBST, we have to compute it before we put anything into
422 do_SUBST (rtx
*into
, rtx newval
)
427 if (oldval
== newval
)
430 /* We'd like to catch as many invalid transformations here as
431 possible. Unfortunately, there are way too many mode changes
432 that are perfectly valid, so we'd waste too much effort for
433 little gain doing the checks here. Focus on catching invalid
434 transformations involving integer constants. */
435 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
436 && GET_CODE (newval
) == CONST_INT
)
438 /* Sanity check that we're replacing oldval with a CONST_INT
439 that is a valid sign-extension for the original mode. */
440 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
444 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
445 CONST_INT is not valid, because after the replacement, the
446 original mode would be gone. Unfortunately, we can't tell
447 when do_SUBST is called to replace the operand thereof, so we
448 perform this test on oldval instead, checking whether an
449 invalid replacement took place before we got here. */
450 if ((GET_CODE (oldval
) == SUBREG
451 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
452 || (GET_CODE (oldval
) == ZERO_EXTEND
453 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
458 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
460 buf
= xmalloc (sizeof (struct undo
));
464 buf
->old_contents
.r
= oldval
;
467 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
470 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
472 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
473 for the value of a HOST_WIDE_INT value (including CONST_INT) is
477 do_SUBST_INT (int *into
, int newval
)
482 if (oldval
== newval
)
486 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
488 buf
= xmalloc (sizeof (struct undo
));
492 buf
->old_contents
.i
= oldval
;
495 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
498 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
500 /* Main entry point for combiner. F is the first insn of the function.
501 NREGS is the first unused pseudo-reg number.
503 Return nonzero if the combiner has turned an indirect jump
504 instruction into a direct jump. */
506 combine_instructions (rtx f
, unsigned int nregs
)
513 rtx links
, nextlinks
;
515 int new_direct_jump_p
= 0;
517 combine_attempts
= 0;
520 combine_successes
= 0;
522 combine_max_regno
= nregs
;
524 /* It is not safe to use ordinary gen_lowpart in combine.
525 See comments in gen_lowpart_for_combine. */
526 gen_lowpart
= gen_lowpart_for_combine
;
528 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
529 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
531 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
532 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
533 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
534 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
535 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
536 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
537 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
538 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
539 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
548 if (INSN_UID (insn
) > i
)
551 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
554 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid
= 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 setup_incoming_promotions ();
576 refresh_blocks
= sbitmap_alloc (last_basic_block
);
577 sbitmap_zero (refresh_blocks
);
579 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
581 uid_cuid
[INSN_UID (insn
)] = ++i
;
587 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
589 record_dead_and_set_regs (insn
);
592 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
593 if (REG_NOTE_KIND (links
) == REG_INC
)
594 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
599 if (GET_CODE (insn
) == CODE_LABEL
)
603 nonzero_sign_valid
= 1;
605 /* Now scan all the insns in forward order. */
610 init_reg_last_arrays ();
611 setup_incoming_promotions ();
613 FOR_EACH_BB (this_basic_block
)
615 for (insn
= BB_HEAD (this_basic_block
);
616 insn
!= NEXT_INSN (BB_END (this_basic_block
));
617 insn
= next
? next
: NEXT_INSN (insn
))
621 if (GET_CODE (insn
) == CODE_LABEL
)
624 else if (INSN_P (insn
))
626 /* See if we know about function return values before this
627 insn based upon SUBREG flags. */
628 check_promoted_subreg (insn
, PATTERN (insn
));
630 /* Try this insn with each insn it links back to. */
632 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
633 if ((next
= try_combine (insn
, XEXP (links
, 0),
634 NULL_RTX
, &new_direct_jump_p
)) != 0)
637 /* Try each sequence of three linked insns ending with this one. */
639 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
641 rtx link
= XEXP (links
, 0);
643 /* If the linked insn has been replaced by a note, then there
644 is no point in pursuing this chain any further. */
645 if (GET_CODE (link
) == NOTE
)
648 for (nextlinks
= LOG_LINKS (link
);
650 nextlinks
= XEXP (nextlinks
, 1))
651 if ((next
= try_combine (insn
, link
,
653 &new_direct_jump_p
)) != 0)
658 /* Try to combine a jump insn that uses CC0
659 with a preceding insn that sets CC0, and maybe with its
660 logical predecessor as well.
661 This is how we make decrement-and-branch insns.
662 We need this special code because data flow connections
663 via CC0 do not get entered in LOG_LINKS. */
665 if (GET_CODE (insn
) == JUMP_INSN
666 && (prev
= prev_nonnote_insn (insn
)) != 0
667 && GET_CODE (prev
) == INSN
668 && sets_cc0_p (PATTERN (prev
)))
670 if ((next
= try_combine (insn
, prev
,
671 NULL_RTX
, &new_direct_jump_p
)) != 0)
674 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
675 nextlinks
= XEXP (nextlinks
, 1))
676 if ((next
= try_combine (insn
, prev
,
678 &new_direct_jump_p
)) != 0)
682 /* Do the same for an insn that explicitly references CC0. */
683 if (GET_CODE (insn
) == INSN
684 && (prev
= prev_nonnote_insn (insn
)) != 0
685 && GET_CODE (prev
) == INSN
686 && sets_cc0_p (PATTERN (prev
))
687 && GET_CODE (PATTERN (insn
)) == SET
688 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
690 if ((next
= try_combine (insn
, prev
,
691 NULL_RTX
, &new_direct_jump_p
)) != 0)
694 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
695 nextlinks
= XEXP (nextlinks
, 1))
696 if ((next
= try_combine (insn
, prev
,
698 &new_direct_jump_p
)) != 0)
702 /* Finally, see if any of the insns that this insn links to
703 explicitly references CC0. If so, try this insn, that insn,
704 and its predecessor if it sets CC0. */
705 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
706 if (GET_CODE (XEXP (links
, 0)) == INSN
707 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
708 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
709 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
710 && GET_CODE (prev
) == INSN
711 && sets_cc0_p (PATTERN (prev
))
712 && (next
= try_combine (insn
, XEXP (links
, 0),
713 prev
, &new_direct_jump_p
)) != 0)
717 /* Try combining an insn with two different insns whose results it
719 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
720 for (nextlinks
= XEXP (links
, 1); nextlinks
;
721 nextlinks
= XEXP (nextlinks
, 1))
722 if ((next
= try_combine (insn
, XEXP (links
, 0),
724 &new_direct_jump_p
)) != 0)
727 if (GET_CODE (insn
) != NOTE
)
728 record_dead_and_set_regs (insn
);
737 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
738 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
739 new_direct_jump_p
|= purge_all_dead_edges (0);
740 delete_noop_moves (f
);
742 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
743 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
744 | PROP_KILL_DEAD_CODE
);
747 sbitmap_free (refresh_blocks
);
748 free (reg_nonzero_bits
);
749 free (reg_sign_bit_copies
);
750 free (reg_last_death
);
752 free (reg_last_set_value
);
753 free (reg_last_set_table_tick
);
754 free (reg_last_set_label
);
755 free (reg_last_set_invalid
);
756 free (reg_last_set_mode
);
757 free (reg_last_set_nonzero_bits
);
758 free (reg_last_set_sign_bit_copies
);
762 struct undo
*undo
, *next
;
763 for (undo
= undobuf
.frees
; undo
; undo
= next
)
771 total_attempts
+= combine_attempts
;
772 total_merges
+= combine_merges
;
773 total_extras
+= combine_extras
;
774 total_successes
+= combine_successes
;
776 nonzero_sign_valid
= 0;
777 gen_lowpart
= gen_lowpart_general
;
779 /* Make recognizer allow volatile MEMs again. */
782 return new_direct_jump_p
;
785 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
788 init_reg_last_arrays (void)
790 unsigned int nregs
= combine_max_regno
;
792 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
793 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
794 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
795 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
796 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
797 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
798 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
799 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
800 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
803 /* Set up any promoted values for incoming argument registers. */
806 setup_incoming_promotions (void)
810 enum machine_mode mode
;
812 rtx first
= get_insns ();
814 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
816 #ifndef OUTGOING_REGNO
817 #define OUTGOING_REGNO(N) N
819 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
820 /* Check whether this register can hold an incoming pointer
821 argument. FUNCTION_ARG_REGNO_P tests outgoing register
822 numbers, so translate if necessary due to register windows. */
823 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
824 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
827 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
830 gen_rtx_CLOBBER (mode
, const0_rtx
)));
835 /* Called via note_stores. If X is a pseudo that is narrower than
836 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
838 If we are setting only a portion of X and we can't figure out what
839 portion, assume all bits will be used since we don't know what will
842 Similarly, set how many bits of X are known to be copies of the sign bit
843 at all locations in the function. This is the smallest number implied
847 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
848 void *data ATTRIBUTE_UNUSED
)
852 if (GET_CODE (x
) == REG
853 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
854 /* If this register is undefined at the start of the file, we can't
855 say what its contents were. */
856 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
857 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
859 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
861 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
862 reg_sign_bit_copies
[REGNO (x
)] = 1;
866 /* If this is a complex assignment, see if we can convert it into a
867 simple assignment. */
868 set
= expand_field_assignment (set
);
870 /* If this is a simple assignment, or we have a paradoxical SUBREG,
871 set what we know about X. */
873 if (SET_DEST (set
) == x
874 || (GET_CODE (SET_DEST (set
)) == SUBREG
875 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
876 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
877 && SUBREG_REG (SET_DEST (set
)) == x
))
879 rtx src
= SET_SRC (set
);
881 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
882 /* If X is narrower than a word and SRC is a non-negative
883 constant that would appear negative in the mode of X,
884 sign-extend it for use in reg_nonzero_bits because some
885 machines (maybe most) will actually do the sign-extension
886 and this is the conservative approach.
888 ??? For 2.5, try to tighten up the MD files in this regard
889 instead of this kludge. */
891 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
892 && GET_CODE (src
) == CONST_INT
894 && 0 != (INTVAL (src
)
896 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
897 src
= GEN_INT (INTVAL (src
)
898 | ((HOST_WIDE_INT
) (-1)
899 << GET_MODE_BITSIZE (GET_MODE (x
))));
902 /* Don't call nonzero_bits if it cannot change anything. */
903 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
904 reg_nonzero_bits
[REGNO (x
)]
905 |= nonzero_bits (src
, nonzero_bits_mode
);
906 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
907 if (reg_sign_bit_copies
[REGNO (x
)] == 0
908 || reg_sign_bit_copies
[REGNO (x
)] > num
)
909 reg_sign_bit_copies
[REGNO (x
)] = num
;
913 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
914 reg_sign_bit_copies
[REGNO (x
)] = 1;
919 /* See if INSN can be combined into I3. PRED and SUCC are optionally
920 insns that were previously combined into I3 or that will be combined
921 into the merger of INSN and I3.
923 Return 0 if the combination is not allowed for any reason.
925 If the combination is allowed, *PDEST will be set to the single
926 destination of INSN and *PSRC to the single source, and this function
930 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
931 rtx
*pdest
, rtx
*psrc
)
934 rtx set
= 0, src
, dest
;
939 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
940 && next_active_insn (succ
) == i3
)
941 : next_active_insn (insn
) == i3
);
943 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
944 or a PARALLEL consisting of such a SET and CLOBBERs.
946 If INSN has CLOBBER parallel parts, ignore them for our processing.
947 By definition, these happen during the execution of the insn. When it
948 is merged with another insn, all bets are off. If they are, in fact,
949 needed and aren't also supplied in I3, they may be added by
950 recog_for_combine. Otherwise, it won't match.
952 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
955 Get the source and destination of INSN. If more than one, can't
958 if (GET_CODE (PATTERN (insn
)) == SET
)
959 set
= PATTERN (insn
);
960 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
961 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
963 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
965 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
967 switch (GET_CODE (elt
))
969 /* This is important to combine floating point insns
972 /* Combining an isolated USE doesn't make sense.
973 We depend here on combinable_i3pat to reject them. */
974 /* The code below this loop only verifies that the inputs of
975 the SET in INSN do not change. We call reg_set_between_p
976 to verify that the REG in the USE does not change between
978 If the USE in INSN was for a pseudo register, the matching
979 insn pattern will likely match any register; combining this
980 with any other USE would only be safe if we knew that the
981 used registers have identical values, or if there was
982 something to tell them apart, e.g. different modes. For
983 now, we forgo such complicated tests and simply disallow
984 combining of USES of pseudo registers with any other USE. */
985 if (GET_CODE (XEXP (elt
, 0)) == REG
986 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
988 rtx i3pat
= PATTERN (i3
);
989 int i
= XVECLEN (i3pat
, 0) - 1;
990 unsigned int regno
= REGNO (XEXP (elt
, 0));
994 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
996 if (GET_CODE (i3elt
) == USE
997 && GET_CODE (XEXP (i3elt
, 0)) == REG
998 && (REGNO (XEXP (i3elt
, 0)) == regno
999 ? reg_set_between_p (XEXP (elt
, 0),
1000 PREV_INSN (insn
), i3
)
1001 : regno
>= FIRST_PSEUDO_REGISTER
))
1008 /* We can ignore CLOBBERs. */
1013 /* Ignore SETs whose result isn't used but not those that
1014 have side-effects. */
1015 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1016 && ! side_effects_p (elt
))
1019 /* If we have already found a SET, this is a second one and
1020 so we cannot combine with this insn. */
1028 /* Anything else means we can't combine. */
1034 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1035 so don't do anything with it. */
1036 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1045 set
= expand_field_assignment (set
);
1046 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1048 /* Don't eliminate a store in the stack pointer. */
1049 if (dest
== stack_pointer_rtx
1050 /* Don't combine with an insn that sets a register to itself if it has
1051 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1052 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1053 /* Can't merge an ASM_OPERANDS. */
1054 || GET_CODE (src
) == ASM_OPERANDS
1055 /* Can't merge a function call. */
1056 || GET_CODE (src
) == CALL
1057 /* Don't eliminate a function call argument. */
1058 || (GET_CODE (i3
) == CALL_INSN
1059 && (find_reg_fusage (i3
, USE
, dest
)
1060 || (GET_CODE (dest
) == REG
1061 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1062 && global_regs
[REGNO (dest
)])))
1063 /* Don't substitute into an incremented register. */
1064 || FIND_REG_INC_NOTE (i3
, dest
)
1065 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1067 /* Don't combine the end of a libcall into anything. */
1068 /* ??? This gives worse code, and appears to be unnecessary, since no
1069 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1070 use REG_RETVAL notes for noconflict blocks, but other code here
1071 makes sure that those insns don't disappear. */
1072 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1074 /* Make sure that DEST is not used after SUCC but before I3. */
1075 || (succ
&& ! all_adjacent
1076 && reg_used_between_p (dest
, succ
, i3
))
1077 /* Make sure that the value that is to be substituted for the register
1078 does not use any registers whose values alter in between. However,
1079 If the insns are adjacent, a use can't cross a set even though we
1080 think it might (this can happen for a sequence of insns each setting
1081 the same destination; reg_last_set of that register might point to
1082 a NOTE). If INSN has a REG_EQUIV note, the register is always
1083 equivalent to the memory so the substitution is valid even if there
1084 are intervening stores. Also, don't move a volatile asm or
1085 UNSPEC_VOLATILE across any other insns. */
1087 && (((GET_CODE (src
) != MEM
1088 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1089 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1090 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1091 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1092 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1093 better register allocation by not doing the combine. */
1094 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1095 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1096 /* Don't combine across a CALL_INSN, because that would possibly
1097 change whether the life span of some REGs crosses calls or not,
1098 and it is a pain to update that information.
1099 Exception: if source is a constant, moving it later can't hurt.
1100 Accept that special case, because it helps -fforce-addr a lot. */
1101 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1104 /* DEST must either be a REG or CC0. */
1105 if (GET_CODE (dest
) == REG
)
1107 /* If register alignment is being enforced for multi-word items in all
1108 cases except for parameters, it is possible to have a register copy
1109 insn referencing a hard register that is not allowed to contain the
1110 mode being copied and which would not be valid as an operand of most
1111 insns. Eliminate this problem by not combining with such an insn.
1113 Also, on some machines we don't want to extend the life of a hard
1116 if (GET_CODE (src
) == REG
1117 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1118 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1119 /* Don't extend the life of a hard register unless it is
1120 user variable (if we have few registers) or it can't
1121 fit into the desired register (meaning something special
1123 Also avoid substituting a return register into I3, because
1124 reload can't handle a conflict with constraints of other
1126 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1127 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1130 else if (GET_CODE (dest
) != CC0
)
1133 /* Don't substitute for a register intended as a clobberable operand.
1134 Similarly, don't substitute an expression containing a register that
1135 will be clobbered in I3. */
1136 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1137 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1138 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1139 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1141 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1144 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1145 or not), reject, unless nothing volatile comes between it and I3 */
1147 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1149 /* Make sure succ doesn't contain a volatile reference. */
1150 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1153 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1154 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1158 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1159 to be an explicit register variable, and was chosen for a reason. */
1161 if (GET_CODE (src
) == ASM_OPERANDS
1162 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1165 /* If there are any volatile insns between INSN and I3, reject, because
1166 they might affect machine state. */
1168 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1169 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1172 /* If INSN or I2 contains an autoincrement or autodecrement,
1173 make sure that register is not used between there and I3,
1174 and not already used in I3 either.
1175 Also insist that I3 not be a jump; if it were one
1176 and the incremented register were spilled, we would lose. */
1179 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1180 if (REG_NOTE_KIND (link
) == REG_INC
1181 && (GET_CODE (i3
) == JUMP_INSN
1182 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1183 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1188 /* Don't combine an insn that follows a CC0-setting insn.
1189 An insn that uses CC0 must not be separated from the one that sets it.
1190 We do, however, allow I2 to follow a CC0-setting insn if that insn
1191 is passed as I1; in that case it will be deleted also.
1192 We also allow combining in this case if all the insns are adjacent
1193 because that would leave the two CC0 insns adjacent as well.
1194 It would be more logical to test whether CC0 occurs inside I1 or I2,
1195 but that would be much slower, and this ought to be equivalent. */
1197 p
= prev_nonnote_insn (insn
);
1198 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1203 /* If we get here, we have passed all the tests and the combination is
1212 /* LOC is the location within I3 that contains its pattern or the component
1213 of a PARALLEL of the pattern. We validate that it is valid for combining.
1215 One problem is if I3 modifies its output, as opposed to replacing it
1216 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1217 so would produce an insn that is not equivalent to the original insns.
1221 (set (reg:DI 101) (reg:DI 100))
1222 (set (subreg:SI (reg:DI 101) 0) <foo>)
1224 This is NOT equivalent to:
1226 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1227 (set (reg:DI 101) (reg:DI 100))])
1229 Not only does this modify 100 (in which case it might still be valid
1230 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1232 We can also run into a problem if I2 sets a register that I1
1233 uses and I1 gets directly substituted into I3 (not via I2). In that
1234 case, we would be getting the wrong value of I2DEST into I3, so we
1235 must reject the combination. This case occurs when I2 and I1 both
1236 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1237 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1238 of a SET must prevent combination from occurring.
1240 Before doing the above check, we first try to expand a field assignment
1241 into a set of logical operations.
1243 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1244 we place a register that is both set and used within I3. If more than one
1245 such register is detected, we fail.
1247 Return 1 if the combination is valid, zero otherwise. */
1250 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1251 int i1_not_in_src
, rtx
*pi3dest_killed
)
1255 if (GET_CODE (x
) == SET
)
1258 rtx dest
= SET_DEST (set
);
1259 rtx src
= SET_SRC (set
);
1260 rtx inner_dest
= dest
;
1262 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1263 || GET_CODE (inner_dest
) == SUBREG
1264 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1265 inner_dest
= XEXP (inner_dest
, 0);
1267 /* Check for the case where I3 modifies its output, as discussed
1268 above. We don't want to prevent pseudos from being combined
1269 into the address of a MEM, so only prevent the combination if
1270 i1 or i2 set the same MEM. */
1271 if ((inner_dest
!= dest
&&
1272 (GET_CODE (inner_dest
) != MEM
1273 || rtx_equal_p (i2dest
, inner_dest
)
1274 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1275 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1276 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1278 /* This is the same test done in can_combine_p except we can't test
1279 all_adjacent; we don't have to, since this instruction will stay
1280 in place, thus we are not considering increasing the lifetime of
1283 Also, if this insn sets a function argument, combining it with
1284 something that might need a spill could clobber a previous
1285 function argument; the all_adjacent test in can_combine_p also
1286 checks this; here, we do a more specific test for this case. */
1288 || (GET_CODE (inner_dest
) == REG
1289 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1290 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1291 GET_MODE (inner_dest
))))
1292 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1295 /* If DEST is used in I3, it is being killed in this insn,
1296 so record that for later.
1297 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1298 STACK_POINTER_REGNUM, since these are always considered to be
1299 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1300 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1301 && reg_referenced_p (dest
, PATTERN (i3
))
1302 && REGNO (dest
) != FRAME_POINTER_REGNUM
1303 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1304 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1306 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1307 && (REGNO (dest
) != ARG_POINTER_REGNUM
1308 || ! fixed_regs
[REGNO (dest
)])
1310 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1312 if (*pi3dest_killed
)
1315 *pi3dest_killed
= dest
;
1319 else if (GET_CODE (x
) == PARALLEL
)
1323 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1324 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1325 i1_not_in_src
, pi3dest_killed
))
1332 /* Return 1 if X is an arithmetic expression that contains a multiplication
1333 and division. We don't count multiplications by powers of two here. */
1336 contains_muldiv (rtx x
)
1338 switch (GET_CODE (x
))
1340 case MOD
: case DIV
: case UMOD
: case UDIV
:
1344 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1345 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1347 switch (GET_RTX_CLASS (GET_CODE (x
)))
1349 case 'c': case '<': case '2':
1350 return contains_muldiv (XEXP (x
, 0))
1351 || contains_muldiv (XEXP (x
, 1));
1354 return contains_muldiv (XEXP (x
, 0));
1362 /* Determine whether INSN can be used in a combination. Return nonzero if
1363 not. This is used in try_combine to detect early some cases where we
1364 can't perform combinations. */
1367 cant_combine_insn_p (rtx insn
)
1372 /* If this isn't really an insn, we can't do anything.
1373 This can occur when flow deletes an insn that it has merged into an
1374 auto-increment address. */
1375 if (! INSN_P (insn
))
1378 /* Never combine loads and stores involving hard regs that are likely
1379 to be spilled. The register allocator can usually handle such
1380 reg-reg moves by tying. If we allow the combiner to make
1381 substitutions of likely-spilled regs, we may abort in reload.
1382 As an exception, we allow combinations involving fixed regs; these are
1383 not available to the register allocator so there's no risk involved. */
1385 set
= single_set (insn
);
1388 src
= SET_SRC (set
);
1389 dest
= SET_DEST (set
);
1390 if (GET_CODE (src
) == SUBREG
)
1391 src
= SUBREG_REG (src
);
1392 if (GET_CODE (dest
) == SUBREG
)
1393 dest
= SUBREG_REG (dest
);
1394 if (REG_P (src
) && REG_P (dest
)
1395 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1396 && ! fixed_regs
[REGNO (src
)]
1397 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1398 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1399 && ! fixed_regs
[REGNO (dest
)]
1400 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1406 /* Adjust INSN after we made a change to its destination.
1408 Changing the destination can invalidate notes that say something about
1409 the results of the insn and a LOG_LINK pointing to the insn. */
1412 adjust_for_new_dest (rtx insn
)
1416 /* For notes, be conservative and simply remove them. */
1417 loc
= ®_NOTES (insn
);
1420 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1421 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1422 *loc
= XEXP (*loc
, 1);
1424 loc
= &XEXP (*loc
, 1);
1427 /* The new insn will have a destination that was previously the destination
1428 of an insn just above it. Call distribute_links to make a LOG_LINK from
1429 the next use of that destination. */
1430 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1433 /* Try to combine the insns I1 and I2 into I3.
1434 Here I1 and I2 appear earlier than I3.
1435 I1 can be zero; then we combine just I2 into I3.
1437 If we are combining three insns and the resulting insn is not recognized,
1438 try splitting it into two insns. If that happens, I2 and I3 are retained
1439 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1442 Return 0 if the combination does not work. Then nothing is changed.
1443 If we did the combination, return the insn at which combine should
1446 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1447 new direct jump instruction. */
1450 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1452 /* New patterns for I3 and I2, respectively. */
1453 rtx newpat
, newi2pat
= 0;
1454 int substed_i2
= 0, substed_i1
= 0;
1455 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1456 int added_sets_1
, added_sets_2
;
1457 /* Total number of SETs to put into I3. */
1459 /* Nonzero is I2's body now appears in I3. */
1461 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1462 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1463 /* Contains I3 if the destination of I3 is used in its source, which means
1464 that the old life of I3 is being killed. If that usage is placed into
1465 I2 and not in I3, a REG_DEAD note must be made. */
1466 rtx i3dest_killed
= 0;
1467 /* SET_DEST and SET_SRC of I2 and I1. */
1468 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1469 /* PATTERN (I2), or a copy of it in certain cases. */
1471 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1472 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1473 int i1_feeds_i3
= 0;
1474 /* Notes that must be added to REG_NOTES in I3 and I2. */
1475 rtx new_i3_notes
, new_i2_notes
;
1476 /* Notes that we substituted I3 into I2 instead of the normal case. */
1477 int i3_subst_into_i2
= 0;
1478 /* Notes that I1, I2 or I3 is a MULT operation. */
1486 /* Exit early if one of the insns involved can't be used for
1488 if (cant_combine_insn_p (i3
)
1489 || cant_combine_insn_p (i2
)
1490 || (i1
&& cant_combine_insn_p (i1
))
1491 /* We also can't do anything if I3 has a
1492 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1495 /* ??? This gives worse code, and appears to be unnecessary, since no
1496 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1497 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1503 undobuf
.other_insn
= 0;
1505 /* Reset the hard register usage information. */
1506 CLEAR_HARD_REG_SET (newpat_used_regs
);
1508 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1509 code below, set I1 to be the earlier of the two insns. */
1510 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1511 temp
= i1
, i1
= i2
, i2
= temp
;
1513 added_links_insn
= 0;
1515 /* First check for one important special-case that the code below will
1516 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1517 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1518 we may be able to replace that destination with the destination of I3.
1519 This occurs in the common code where we compute both a quotient and
1520 remainder into a structure, in which case we want to do the computation
1521 directly into the structure to avoid register-register copies.
1523 Note that this case handles both multiple sets in I2 and also
1524 cases where I2 has a number of CLOBBER or PARALLELs.
1526 We make very conservative checks below and only try to handle the
1527 most common cases of this. For example, we only handle the case
1528 where I2 and I3 are adjacent to avoid making difficult register
1531 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1532 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1533 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1534 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1535 && GET_CODE (PATTERN (i2
)) == PARALLEL
1536 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1537 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1538 below would need to check what is inside (and reg_overlap_mentioned_p
1539 doesn't support those codes anyway). Don't allow those destinations;
1540 the resulting insn isn't likely to be recognized anyway. */
1541 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1542 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1543 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1544 SET_DEST (PATTERN (i3
)))
1545 && next_real_insn (i2
) == i3
)
1547 rtx p2
= PATTERN (i2
);
1549 /* Make sure that the destination of I3,
1550 which we are going to substitute into one output of I2,
1551 is not used within another output of I2. We must avoid making this:
1552 (parallel [(set (mem (reg 69)) ...)
1553 (set (reg 69) ...)])
1554 which is not well-defined as to order of actions.
1555 (Besides, reload can't handle output reloads for this.)
1557 The problem can also happen if the dest of I3 is a memory ref,
1558 if another dest in I2 is an indirect memory ref. */
1559 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1560 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1561 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1562 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1563 SET_DEST (XVECEXP (p2
, 0, i
))))
1566 if (i
== XVECLEN (p2
, 0))
1567 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1568 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1569 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1570 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1575 subst_low_cuid
= INSN_CUID (i2
);
1577 added_sets_2
= added_sets_1
= 0;
1578 i2dest
= SET_SRC (PATTERN (i3
));
1580 /* Replace the dest in I2 with our dest and make the resulting
1581 insn the new pattern for I3. Then skip to where we
1582 validate the pattern. Everything was set up above. */
1583 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1584 SET_DEST (PATTERN (i3
)));
1587 i3_subst_into_i2
= 1;
1588 goto validate_replacement
;
1592 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1593 one of those words to another constant, merge them by making a new
1596 && (temp
= single_set (i2
)) != 0
1597 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1598 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1599 && GET_CODE (SET_DEST (temp
)) == REG
1600 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1601 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1602 && GET_CODE (PATTERN (i3
)) == SET
1603 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1604 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1605 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1606 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1607 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1609 HOST_WIDE_INT lo
, hi
;
1611 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1612 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1615 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1616 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1619 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1621 /* We don't handle the case of the target word being wider
1622 than a host wide int. */
1623 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1626 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1627 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1628 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1630 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1631 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1632 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1634 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1635 >> (HOST_BITS_PER_WIDE_INT
- 1));
1637 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1638 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1639 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1640 (INTVAL (SET_SRC (PATTERN (i3
)))));
1642 hi
= lo
< 0 ? -1 : 0;
1645 /* We don't handle the case of the higher word not fitting
1646 entirely in either hi or lo. */
1651 subst_low_cuid
= INSN_CUID (i2
);
1652 added_sets_2
= added_sets_1
= 0;
1653 i2dest
= SET_DEST (temp
);
1655 SUBST (SET_SRC (temp
),
1656 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1658 newpat
= PATTERN (i2
);
1659 goto validate_replacement
;
1663 /* If we have no I1 and I2 looks like:
1664 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1666 make up a dummy I1 that is
1669 (set (reg:CC X) (compare:CC Y (const_int 0)))
1671 (We can ignore any trailing CLOBBERs.)
1673 This undoes a previous combination and allows us to match a branch-and-
1676 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1677 && XVECLEN (PATTERN (i2
), 0) >= 2
1678 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1679 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1681 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1682 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1683 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1684 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1685 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1686 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1688 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1689 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1694 /* We make I1 with the same INSN_UID as I2. This gives it
1695 the same INSN_CUID for value tracking. Our fake I1 will
1696 never appear in the insn stream so giving it the same INSN_UID
1697 as I2 will not cause a problem. */
1699 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1700 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1701 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1704 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1705 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1706 SET_DEST (PATTERN (i1
)));
1711 /* Verify that I2 and I1 are valid for combining. */
1712 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1713 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1719 /* Record whether I2DEST is used in I2SRC and similarly for the other
1720 cases. Knowing this will help in register status updating below. */
1721 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1722 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1723 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1725 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1727 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1729 /* Ensure that I3's pattern can be the destination of combines. */
1730 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1731 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1738 /* See if any of the insns is a MULT operation. Unless one is, we will
1739 reject a combination that is, since it must be slower. Be conservative
1741 if (GET_CODE (i2src
) == MULT
1742 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1743 || (GET_CODE (PATTERN (i3
)) == SET
1744 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1747 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1748 We used to do this EXCEPT in one case: I3 has a post-inc in an
1749 output operand. However, that exception can give rise to insns like
1751 which is a famous insn on the PDP-11 where the value of r3 used as the
1752 source was model-dependent. Avoid this sort of thing. */
1755 if (!(GET_CODE (PATTERN (i3
)) == SET
1756 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1757 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1758 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1759 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1760 /* It's not the exception. */
1763 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1764 if (REG_NOTE_KIND (link
) == REG_INC
1765 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1767 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1774 /* See if the SETs in I1 or I2 need to be kept around in the merged
1775 instruction: whenever the value set there is still needed past I3.
1776 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1778 For the SET in I1, we have two cases: If I1 and I2 independently
1779 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1780 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1781 in I1 needs to be kept around unless I1DEST dies or is set in either
1782 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1783 I1DEST. If so, we know I1 feeds into I2. */
1785 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1788 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1789 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1791 /* If the set in I2 needs to be kept around, we must make a copy of
1792 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1793 PATTERN (I2), we are only substituting for the original I1DEST, not into
1794 an already-substituted copy. This also prevents making self-referential
1795 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1798 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1799 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1803 i2pat
= copy_rtx (i2pat
);
1807 /* Substitute in the latest insn for the regs set by the earlier ones. */
1809 maxreg
= max_reg_num ();
1813 /* It is possible that the source of I2 or I1 may be performing an
1814 unneeded operation, such as a ZERO_EXTEND of something that is known
1815 to have the high part zero. Handle that case by letting subst look at
1816 the innermost one of them.
1818 Another way to do this would be to have a function that tries to
1819 simplify a single insn instead of merging two or more insns. We don't
1820 do this because of the potential of infinite loops and because
1821 of the potential extra memory required. However, doing it the way
1822 we are is a bit of a kludge and doesn't catch all cases.
1824 But only do this if -fexpensive-optimizations since it slows things down
1825 and doesn't usually win. */
1827 if (flag_expensive_optimizations
)
1829 /* Pass pc_rtx so no substitutions are done, just simplifications.
1830 The cases that we are interested in here do not involve the few
1831 cases were is_replaced is checked. */
1834 subst_low_cuid
= INSN_CUID (i1
);
1835 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1839 subst_low_cuid
= INSN_CUID (i2
);
1840 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1845 /* Many machines that don't use CC0 have insns that can both perform an
1846 arithmetic operation and set the condition code. These operations will
1847 be represented as a PARALLEL with the first element of the vector
1848 being a COMPARE of an arithmetic operation with the constant zero.
1849 The second element of the vector will set some pseudo to the result
1850 of the same arithmetic operation. If we simplify the COMPARE, we won't
1851 match such a pattern and so will generate an extra insn. Here we test
1852 for this case, where both the comparison and the operation result are
1853 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1854 I2SRC. Later we will make the PARALLEL that contains I2. */
1856 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1857 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1858 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1859 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1861 #ifdef SELECT_CC_MODE
1863 enum machine_mode compare_mode
;
1866 newpat
= PATTERN (i3
);
1867 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1871 #ifdef SELECT_CC_MODE
1872 /* See if a COMPARE with the operand we substituted in should be done
1873 with the mode that is currently being used. If not, do the same
1874 processing we do in `subst' for a SET; namely, if the destination
1875 is used only once, try to replace it with a register of the proper
1876 mode and also replace the COMPARE. */
1877 if (undobuf
.other_insn
== 0
1878 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1879 &undobuf
.other_insn
))
1880 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1882 != GET_MODE (SET_DEST (newpat
))))
1884 unsigned int regno
= REGNO (SET_DEST (newpat
));
1885 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1887 if (regno
< FIRST_PSEUDO_REGISTER
1888 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1889 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1891 if (regno
>= FIRST_PSEUDO_REGISTER
)
1892 SUBST (regno_reg_rtx
[regno
], new_dest
);
1894 SUBST (SET_DEST (newpat
), new_dest
);
1895 SUBST (XEXP (*cc_use
, 0), new_dest
);
1896 SUBST (SET_SRC (newpat
),
1897 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1900 undobuf
.other_insn
= 0;
1907 n_occurrences
= 0; /* `subst' counts here */
1909 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1910 need to make a unique copy of I2SRC each time we substitute it
1911 to avoid self-referential rtl. */
1913 subst_low_cuid
= INSN_CUID (i2
);
1914 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1915 ! i1_feeds_i3
&& i1dest_in_i1src
);
1918 /* Record whether i2's body now appears within i3's body. */
1919 i2_is_used
= n_occurrences
;
1922 /* If we already got a failure, don't try to do more. Otherwise,
1923 try to substitute in I1 if we have it. */
1925 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1927 /* Before we can do this substitution, we must redo the test done
1928 above (see detailed comments there) that ensures that I1DEST
1929 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1931 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1939 subst_low_cuid
= INSN_CUID (i1
);
1940 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1944 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1945 to count all the ways that I2SRC and I1SRC can be used. */
1946 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1947 && i2_is_used
+ added_sets_2
> 1)
1948 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1949 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1951 /* Fail if we tried to make a new register (we used to abort, but there's
1952 really no reason to). */
1953 || max_reg_num () != maxreg
1954 /* Fail if we couldn't do something and have a CLOBBER. */
1955 || GET_CODE (newpat
) == CLOBBER
1956 /* Fail if this new pattern is a MULT and we didn't have one before
1957 at the outer level. */
1958 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1965 /* If the actions of the earlier insns must be kept
1966 in addition to substituting them into the latest one,
1967 we must make a new PARALLEL for the latest insn
1968 to hold additional the SETs. */
1970 if (added_sets_1
|| added_sets_2
)
1974 if (GET_CODE (newpat
) == PARALLEL
)
1976 rtvec old
= XVEC (newpat
, 0);
1977 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1978 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1979 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1980 sizeof (old
->elem
[0]) * old
->num_elem
);
1985 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1986 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1987 XVECEXP (newpat
, 0, 0) = old
;
1991 XVECEXP (newpat
, 0, --total_sets
)
1992 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1993 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1997 /* If there is no I1, use I2's body as is. We used to also not do
1998 the subst call below if I2 was substituted into I3,
1999 but that could lose a simplification. */
2001 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2003 /* See comment where i2pat is assigned. */
2004 XVECEXP (newpat
, 0, --total_sets
)
2005 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2009 /* We come here when we are replacing a destination in I2 with the
2010 destination of I3. */
2011 validate_replacement
:
2013 /* Note which hard regs this insn has as inputs. */
2014 mark_used_regs_combine (newpat
);
2016 /* Is the result of combination a valid instruction? */
2017 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2019 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2020 the second SET's destination is a register that is unused and isn't
2021 marked as an instruction that might trap in an EH region. In that case,
2022 we just need the first SET. This can occur when simplifying a divmod
2023 insn. We *must* test for this case here because the code below that
2024 splits two independent SETs doesn't handle this case correctly when it
2025 updates the register status. Also check the case where the first
2026 SET's destination is unused. That would not cause incorrect code, but
2027 does cause an unneeded insn to remain. */
2029 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2030 && XVECLEN (newpat
, 0) == 2
2031 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2032 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2033 && asm_noperands (newpat
) < 0)
2035 rtx set0
= XVECEXP (newpat
, 0, 0);
2036 rtx set1
= XVECEXP (newpat
, 0, 1);
2039 if (((GET_CODE (SET_DEST (set1
)) == REG
2040 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2041 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2042 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2043 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2044 || INTVAL (XEXP (note
, 0)) <= 0)
2045 && ! side_effects_p (SET_SRC (set1
)))
2048 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2051 else if (((GET_CODE (SET_DEST (set0
)) == REG
2052 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2053 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2054 && find_reg_note (i3
, REG_UNUSED
,
2055 SUBREG_REG (SET_DEST (set0
)))))
2056 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2057 || INTVAL (XEXP (note
, 0)) <= 0)
2058 && ! side_effects_p (SET_SRC (set0
)))
2061 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2063 if (insn_code_number
>= 0)
2065 /* If we will be able to accept this, we have made a
2066 change to the destination of I3. This requires us to
2067 do a few adjustments. */
2069 PATTERN (i3
) = newpat
;
2070 adjust_for_new_dest (i3
);
2075 /* If we were combining three insns and the result is a simple SET
2076 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2077 insns. There are two ways to do this. It can be split using a
2078 machine-specific method (like when you have an addition of a large
2079 constant) or by combine in the function find_split_point. */
2081 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2082 && asm_noperands (newpat
) < 0)
2084 rtx m_split
, *split
;
2085 rtx ni2dest
= i2dest
;
2087 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2088 use I2DEST as a scratch register will help. In the latter case,
2089 convert I2DEST to the mode of the source of NEWPAT if we can. */
2091 m_split
= split_insns (newpat
, i3
);
2093 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2094 inputs of NEWPAT. */
2096 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2097 possible to try that as a scratch reg. This would require adding
2098 more code to make it work though. */
2100 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2102 /* If I2DEST is a hard register or the only use of a pseudo,
2103 we can change its mode. */
2104 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2105 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2106 && GET_CODE (i2dest
) == REG
2107 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2108 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2109 && ! REG_USERVAR_P (i2dest
))))
2110 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2113 m_split
= split_insns (gen_rtx_PARALLEL
2115 gen_rtvec (2, newpat
,
2116 gen_rtx_CLOBBER (VOIDmode
,
2119 /* If the split with the mode-changed register didn't work, try
2120 the original register. */
2121 if (! m_split
&& ni2dest
!= i2dest
)
2124 m_split
= split_insns (gen_rtx_PARALLEL
2126 gen_rtvec (2, newpat
,
2127 gen_rtx_CLOBBER (VOIDmode
,
2133 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2135 m_split
= PATTERN (m_split
);
2136 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2137 if (insn_code_number
>= 0)
2140 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2141 && (next_real_insn (i2
) == i3
2142 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2145 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2146 newi2pat
= PATTERN (m_split
);
2148 i3set
= single_set (NEXT_INSN (m_split
));
2149 i2set
= single_set (m_split
);
2151 /* In case we changed the mode of I2DEST, replace it in the
2152 pseudo-register table here. We can't do it above in case this
2153 code doesn't get executed and we do a split the other way. */
2155 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2156 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2158 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2160 /* If I2 or I3 has multiple SETs, we won't know how to track
2161 register status, so don't use these insns. If I2's destination
2162 is used between I2 and I3, we also can't use these insns. */
2164 if (i2_code_number
>= 0 && i2set
&& i3set
2165 && (next_real_insn (i2
) == i3
2166 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2167 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2169 if (insn_code_number
>= 0)
2172 /* It is possible that both insns now set the destination of I3.
2173 If so, we must show an extra use of it. */
2175 if (insn_code_number
>= 0)
2177 rtx new_i3_dest
= SET_DEST (i3set
);
2178 rtx new_i2_dest
= SET_DEST (i2set
);
2180 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2181 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2182 || GET_CODE (new_i3_dest
) == SUBREG
)
2183 new_i3_dest
= XEXP (new_i3_dest
, 0);
2185 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2186 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2187 || GET_CODE (new_i2_dest
) == SUBREG
)
2188 new_i2_dest
= XEXP (new_i2_dest
, 0);
2190 if (GET_CODE (new_i3_dest
) == REG
2191 && GET_CODE (new_i2_dest
) == REG
2192 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2193 REG_N_SETS (REGNO (new_i2_dest
))++;
2197 /* If we can split it and use I2DEST, go ahead and see if that
2198 helps things be recognized. Verify that none of the registers
2199 are set between I2 and I3. */
2200 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2202 && GET_CODE (i2dest
) == REG
2204 /* We need I2DEST in the proper mode. If it is a hard register
2205 or the only use of a pseudo, we can change its mode. */
2206 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2207 || GET_MODE (*split
) == VOIDmode
2208 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2209 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2210 && ! REG_USERVAR_P (i2dest
)))
2211 && (next_real_insn (i2
) == i3
2212 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2213 /* We can't overwrite I2DEST if its value is still used by
2215 && ! reg_referenced_p (i2dest
, newpat
))
2217 rtx newdest
= i2dest
;
2218 enum rtx_code split_code
= GET_CODE (*split
);
2219 enum machine_mode split_mode
= GET_MODE (*split
);
2221 /* Get NEWDEST as a register in the proper mode. We have already
2222 validated that we can do this. */
2223 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2225 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2227 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2228 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2231 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2232 an ASHIFT. This can occur if it was inside a PLUS and hence
2233 appeared to be a memory address. This is a kludge. */
2234 if (split_code
== MULT
2235 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2236 && INTVAL (XEXP (*split
, 1)) > 0
2237 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2239 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2240 XEXP (*split
, 0), GEN_INT (i
)));
2241 /* Update split_code because we may not have a multiply
2243 split_code
= GET_CODE (*split
);
2246 #ifdef INSN_SCHEDULING
2247 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2248 be written as a ZERO_EXTEND. */
2249 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2251 #ifdef LOAD_EXTEND_OP
2252 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2253 what it really is. */
2254 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2256 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2257 SUBREG_REG (*split
)));
2260 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2261 SUBREG_REG (*split
)));
2265 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2266 SUBST (*split
, newdest
);
2267 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2269 /* If the split point was a MULT and we didn't have one before,
2270 don't use one now. */
2271 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2272 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2276 /* Check for a case where we loaded from memory in a narrow mode and
2277 then sign extended it, but we need both registers. In that case,
2278 we have a PARALLEL with both loads from the same memory location.
2279 We can split this into a load from memory followed by a register-register
2280 copy. This saves at least one insn, more if register allocation can
2283 We cannot do this if the destination of the first assignment is a
2284 condition code register or cc0. We eliminate this case by making sure
2285 the SET_DEST and SET_SRC have the same mode.
2287 We cannot do this if the destination of the second assignment is
2288 a register that we have already assumed is zero-extended. Similarly
2289 for a SUBREG of such a register. */
2291 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2292 && GET_CODE (newpat
) == PARALLEL
2293 && XVECLEN (newpat
, 0) == 2
2294 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2295 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2296 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2297 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2298 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2299 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2300 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2301 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2303 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2304 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2305 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2306 (GET_CODE (temp
) == REG
2307 && reg_nonzero_bits
[REGNO (temp
)] != 0
2308 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2309 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2310 && (reg_nonzero_bits
[REGNO (temp
)]
2311 != GET_MODE_MASK (word_mode
))))
2312 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2313 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2314 (GET_CODE (temp
) == REG
2315 && reg_nonzero_bits
[REGNO (temp
)] != 0
2316 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2317 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2318 && (reg_nonzero_bits
[REGNO (temp
)]
2319 != GET_MODE_MASK (word_mode
)))))
2320 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2321 SET_SRC (XVECEXP (newpat
, 0, 1)))
2322 && ! find_reg_note (i3
, REG_UNUSED
,
2323 SET_DEST (XVECEXP (newpat
, 0, 0))))
2327 newi2pat
= XVECEXP (newpat
, 0, 0);
2328 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2329 newpat
= XVECEXP (newpat
, 0, 1);
2330 SUBST (SET_SRC (newpat
),
2331 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2332 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2334 if (i2_code_number
>= 0)
2335 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2337 if (insn_code_number
>= 0)
2342 /* If we will be able to accept this, we have made a change to the
2343 destination of I3. This requires us to do a few adjustments. */
2344 PATTERN (i3
) = newpat
;
2345 adjust_for_new_dest (i3
);
2347 /* I3 now uses what used to be its destination and which is
2348 now I2's destination. That means we need a LOG_LINK from
2349 I3 to I2. But we used to have one, so we still will.
2351 However, some later insn might be using I2's dest and have
2352 a LOG_LINK pointing at I3. We must remove this link.
2353 The simplest way to remove the link is to point it at I1,
2354 which we know will be a NOTE. */
2356 for (insn
= NEXT_INSN (i3
);
2357 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2358 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2359 insn
= NEXT_INSN (insn
))
2361 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2363 for (link
= LOG_LINKS (insn
); link
;
2364 link
= XEXP (link
, 1))
2365 if (XEXP (link
, 0) == i3
)
2366 XEXP (link
, 0) = i1
;
2374 /* Similarly, check for a case where we have a PARALLEL of two independent
2375 SETs but we started with three insns. In this case, we can do the sets
2376 as two separate insns. This case occurs when some SET allows two
2377 other insns to combine, but the destination of that SET is still live. */
2379 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2380 && GET_CODE (newpat
) == PARALLEL
2381 && XVECLEN (newpat
, 0) == 2
2382 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2383 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2384 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2385 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2386 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2387 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2388 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2390 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2391 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2392 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2393 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2394 XVECEXP (newpat
, 0, 0))
2395 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2396 XVECEXP (newpat
, 0, 1))
2397 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2398 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2400 /* Normally, it doesn't matter which of the two is done first,
2401 but it does if one references cc0. In that case, it has to
2404 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2406 newi2pat
= XVECEXP (newpat
, 0, 0);
2407 newpat
= XVECEXP (newpat
, 0, 1);
2412 newi2pat
= XVECEXP (newpat
, 0, 1);
2413 newpat
= XVECEXP (newpat
, 0, 0);
2416 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2418 if (i2_code_number
>= 0)
2419 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2422 /* If it still isn't recognized, fail and change things back the way they
2424 if ((insn_code_number
< 0
2425 /* Is the result a reasonable ASM_OPERANDS? */
2426 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2432 /* If we had to change another insn, make sure it is valid also. */
2433 if (undobuf
.other_insn
)
2435 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2436 rtx new_other_notes
;
2439 CLEAR_HARD_REG_SET (newpat_used_regs
);
2441 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2444 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2450 PATTERN (undobuf
.other_insn
) = other_pat
;
2452 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2453 are still valid. Then add any non-duplicate notes added by
2454 recog_for_combine. */
2455 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2457 next
= XEXP (note
, 1);
2459 if (REG_NOTE_KIND (note
) == REG_UNUSED
2460 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2462 if (GET_CODE (XEXP (note
, 0)) == REG
)
2463 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2465 remove_note (undobuf
.other_insn
, note
);
2469 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2470 if (GET_CODE (XEXP (note
, 0)) == REG
)
2471 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2473 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2474 undobuf
.other_insn
, NULL_RTX
);
2477 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2478 they are adjacent to each other or not. */
2480 rtx p
= prev_nonnote_insn (i3
);
2481 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2482 && sets_cc0_p (newi2pat
))
2490 /* We now know that we can do this combination. Merge the insns and
2491 update the status of registers and LOG_LINKS. */
2494 rtx i3notes
, i2notes
, i1notes
= 0;
2495 rtx i3links
, i2links
, i1links
= 0;
2499 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2501 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2502 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2504 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2506 /* Ensure that we do not have something that should not be shared but
2507 occurs multiple times in the new insns. Check this by first
2508 resetting all the `used' flags and then copying anything is shared. */
2510 reset_used_flags (i3notes
);
2511 reset_used_flags (i2notes
);
2512 reset_used_flags (i1notes
);
2513 reset_used_flags (newpat
);
2514 reset_used_flags (newi2pat
);
2515 if (undobuf
.other_insn
)
2516 reset_used_flags (PATTERN (undobuf
.other_insn
));
2518 i3notes
= copy_rtx_if_shared (i3notes
);
2519 i2notes
= copy_rtx_if_shared (i2notes
);
2520 i1notes
= copy_rtx_if_shared (i1notes
);
2521 newpat
= copy_rtx_if_shared (newpat
);
2522 newi2pat
= copy_rtx_if_shared (newi2pat
);
2523 if (undobuf
.other_insn
)
2524 reset_used_flags (PATTERN (undobuf
.other_insn
));
2526 INSN_CODE (i3
) = insn_code_number
;
2527 PATTERN (i3
) = newpat
;
2529 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2531 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2533 reset_used_flags (call_usage
);
2534 call_usage
= copy_rtx (call_usage
);
2537 replace_rtx (call_usage
, i2dest
, i2src
);
2540 replace_rtx (call_usage
, i1dest
, i1src
);
2542 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2545 if (undobuf
.other_insn
)
2546 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2548 /* We had one special case above where I2 had more than one set and
2549 we replaced a destination of one of those sets with the destination
2550 of I3. In that case, we have to update LOG_LINKS of insns later
2551 in this basic block. Note that this (expensive) case is rare.
2553 Also, in this case, we must pretend that all REG_NOTEs for I2
2554 actually came from I3, so that REG_UNUSED notes from I2 will be
2555 properly handled. */
2557 if (i3_subst_into_i2
)
2559 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2560 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2561 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2562 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2563 && ! find_reg_note (i2
, REG_UNUSED
,
2564 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2565 for (temp
= NEXT_INSN (i2
);
2566 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2567 || BB_HEAD (this_basic_block
) != temp
);
2568 temp
= NEXT_INSN (temp
))
2569 if (temp
!= i3
&& INSN_P (temp
))
2570 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2571 if (XEXP (link
, 0) == i2
)
2572 XEXP (link
, 0) = i3
;
2577 while (XEXP (link
, 1))
2578 link
= XEXP (link
, 1);
2579 XEXP (link
, 1) = i2notes
;
2593 INSN_CODE (i2
) = i2_code_number
;
2594 PATTERN (i2
) = newi2pat
;
2598 PUT_CODE (i2
, NOTE
);
2599 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2600 NOTE_SOURCE_FILE (i2
) = 0;
2607 PUT_CODE (i1
, NOTE
);
2608 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2609 NOTE_SOURCE_FILE (i1
) = 0;
2612 /* Get death notes for everything that is now used in either I3 or
2613 I2 and used to die in a previous insn. If we built two new
2614 patterns, move from I1 to I2 then I2 to I3 so that we get the
2615 proper movement on registers that I2 modifies. */
2619 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2620 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2623 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2626 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2628 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2630 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2632 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2634 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2636 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2637 know these are REG_UNUSED and want them to go to the desired insn,
2638 so we always pass it as i3. We have not counted the notes in
2639 reg_n_deaths yet, so we need to do so now. */
2641 if (newi2pat
&& new_i2_notes
)
2643 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2644 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2645 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2647 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2652 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2653 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2654 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2656 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2659 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2660 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2661 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2662 in that case, it might delete I2. Similarly for I2 and I1.
2663 Show an additional death due to the REG_DEAD note we make here. If
2664 we discard it in distribute_notes, we will decrement it again. */
2668 if (GET_CODE (i3dest_killed
) == REG
)
2669 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2671 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2672 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2674 NULL_RTX
, i2
, NULL_RTX
);
2676 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2678 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2681 if (i2dest_in_i2src
)
2683 if (GET_CODE (i2dest
) == REG
)
2684 REG_N_DEATHS (REGNO (i2dest
))++;
2686 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2687 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2688 NULL_RTX
, i2
, NULL_RTX
);
2690 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2691 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2694 if (i1dest_in_i1src
)
2696 if (GET_CODE (i1dest
) == REG
)
2697 REG_N_DEATHS (REGNO (i1dest
))++;
2699 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2700 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2701 NULL_RTX
, i2
, NULL_RTX
);
2703 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2704 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2707 distribute_links (i3links
);
2708 distribute_links (i2links
);
2709 distribute_links (i1links
);
2711 if (GET_CODE (i2dest
) == REG
)
2714 rtx i2_insn
= 0, i2_val
= 0, set
;
2716 /* The insn that used to set this register doesn't exist, and
2717 this life of the register may not exist either. See if one of
2718 I3's links points to an insn that sets I2DEST. If it does,
2719 that is now the last known value for I2DEST. If we don't update
2720 this and I2 set the register to a value that depended on its old
2721 contents, we will get confused. If this insn is used, thing
2722 will be set correctly in combine_instructions. */
2724 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2725 if ((set
= single_set (XEXP (link
, 0))) != 0
2726 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2727 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2729 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2731 /* If the reg formerly set in I2 died only once and that was in I3,
2732 zero its use count so it won't make `reload' do any work. */
2734 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2735 && ! i2dest_in_i2src
)
2737 regno
= REGNO (i2dest
);
2738 REG_N_SETS (regno
)--;
2742 if (i1
&& GET_CODE (i1dest
) == REG
)
2745 rtx i1_insn
= 0, i1_val
= 0, set
;
2747 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2748 if ((set
= single_set (XEXP (link
, 0))) != 0
2749 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2750 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2752 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2754 regno
= REGNO (i1dest
);
2755 if (! added_sets_1
&& ! i1dest_in_i1src
)
2756 REG_N_SETS (regno
)--;
2759 /* Update reg_nonzero_bits et al for any changes that may have been made
2760 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2761 important. Because newi2pat can affect nonzero_bits of newpat */
2763 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2764 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2766 /* Set new_direct_jump_p if a new return or simple jump instruction
2769 If I3 is now an unconditional jump, ensure that it has a
2770 BARRIER following it since it may have initially been a
2771 conditional jump. It may also be the last nonnote insn. */
2773 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2775 *new_direct_jump_p
= 1;
2776 mark_jump_label (PATTERN (i3
), i3
, 0);
2778 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2779 || GET_CODE (temp
) != BARRIER
)
2780 emit_barrier_after (i3
);
2783 if (undobuf
.other_insn
!= NULL_RTX
2784 && (returnjump_p (undobuf
.other_insn
)
2785 || any_uncondjump_p (undobuf
.other_insn
)))
2787 *new_direct_jump_p
= 1;
2789 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2790 || GET_CODE (temp
) != BARRIER
)
2791 emit_barrier_after (undobuf
.other_insn
);
2794 /* An NOOP jump does not need barrier, but it does need cleaning up
2796 if (GET_CODE (newpat
) == SET
2797 && SET_SRC (newpat
) == pc_rtx
2798 && SET_DEST (newpat
) == pc_rtx
)
2799 *new_direct_jump_p
= 1;
2802 combine_successes
++;
2805 if (added_links_insn
2806 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2807 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2808 return added_links_insn
;
2810 return newi2pat
? i2
: i3
;
2813 /* Undo all the modifications recorded in undobuf. */
2818 struct undo
*undo
, *next
;
2820 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2824 *undo
->where
.i
= undo
->old_contents
.i
;
2826 *undo
->where
.r
= undo
->old_contents
.r
;
2828 undo
->next
= undobuf
.frees
;
2829 undobuf
.frees
= undo
;
2835 /* We've committed to accepting the changes we made. Move all
2836 of the undos to the free list. */
2841 struct undo
*undo
, *next
;
2843 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2846 undo
->next
= undobuf
.frees
;
2847 undobuf
.frees
= undo
;
2853 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2854 where we have an arithmetic expression and return that point. LOC will
2857 try_combine will call this function to see if an insn can be split into
2861 find_split_point (rtx
*loc
, rtx insn
)
2864 enum rtx_code code
= GET_CODE (x
);
2866 unsigned HOST_WIDE_INT len
= 0;
2867 HOST_WIDE_INT pos
= 0;
2869 rtx inner
= NULL_RTX
;
2871 /* First special-case some codes. */
2875 #ifdef INSN_SCHEDULING
2876 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2878 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2881 return find_split_point (&SUBREG_REG (x
), insn
);
2885 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2886 using LO_SUM and HIGH. */
2887 if (GET_CODE (XEXP (x
, 0)) == CONST
2888 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2891 gen_rtx_LO_SUM (Pmode
,
2892 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2894 return &XEXP (XEXP (x
, 0), 0);
2898 /* If we have a PLUS whose second operand is a constant and the
2899 address is not valid, perhaps will can split it up using
2900 the machine-specific way to split large constants. We use
2901 the first pseudo-reg (one of the virtual regs) as a placeholder;
2902 it will not remain in the result. */
2903 if (GET_CODE (XEXP (x
, 0)) == PLUS
2904 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2905 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2907 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2908 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2911 /* This should have produced two insns, each of which sets our
2912 placeholder. If the source of the second is a valid address,
2913 we can make put both sources together and make a split point
2917 && NEXT_INSN (seq
) != NULL_RTX
2918 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2919 && GET_CODE (seq
) == INSN
2920 && GET_CODE (PATTERN (seq
)) == SET
2921 && SET_DEST (PATTERN (seq
)) == reg
2922 && ! reg_mentioned_p (reg
,
2923 SET_SRC (PATTERN (seq
)))
2924 && GET_CODE (NEXT_INSN (seq
)) == INSN
2925 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2926 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2927 && memory_address_p (GET_MODE (x
),
2928 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2930 rtx src1
= SET_SRC (PATTERN (seq
));
2931 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2933 /* Replace the placeholder in SRC2 with SRC1. If we can
2934 find where in SRC2 it was placed, that can become our
2935 split point and we can replace this address with SRC2.
2936 Just try two obvious places. */
2938 src2
= replace_rtx (src2
, reg
, src1
);
2940 if (XEXP (src2
, 0) == src1
)
2941 split
= &XEXP (src2
, 0);
2942 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2943 && XEXP (XEXP (src2
, 0), 0) == src1
)
2944 split
= &XEXP (XEXP (src2
, 0), 0);
2948 SUBST (XEXP (x
, 0), src2
);
2953 /* If that didn't work, perhaps the first operand is complex and
2954 needs to be computed separately, so make a split point there.
2955 This will occur on machines that just support REG + CONST
2956 and have a constant moved through some previous computation. */
2958 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2959 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2960 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2962 return &XEXP (XEXP (x
, 0), 0);
2968 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2969 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2970 we need to put the operand into a register. So split at that
2973 if (SET_DEST (x
) == cc0_rtx
2974 && GET_CODE (SET_SRC (x
)) != COMPARE
2975 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2976 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2977 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2978 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2979 return &SET_SRC (x
);
2982 /* See if we can split SET_SRC as it stands. */
2983 split
= find_split_point (&SET_SRC (x
), insn
);
2984 if (split
&& split
!= &SET_SRC (x
))
2987 /* See if we can split SET_DEST as it stands. */
2988 split
= find_split_point (&SET_DEST (x
), insn
);
2989 if (split
&& split
!= &SET_DEST (x
))
2992 /* See if this is a bitfield assignment with everything constant. If
2993 so, this is an IOR of an AND, so split it into that. */
2994 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2995 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2996 <= HOST_BITS_PER_WIDE_INT
)
2997 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2998 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2999 && GET_CODE (SET_SRC (x
)) == CONST_INT
3000 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3001 + INTVAL (XEXP (SET_DEST (x
), 2)))
3002 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3003 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3005 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3006 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3007 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3008 rtx dest
= XEXP (SET_DEST (x
), 0);
3009 enum machine_mode mode
= GET_MODE (dest
);
3010 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3012 if (BITS_BIG_ENDIAN
)
3013 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3017 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3020 gen_binary (IOR
, mode
,
3021 gen_binary (AND
, mode
, dest
,
3022 gen_int_mode (~(mask
<< pos
),
3024 GEN_INT (src
<< pos
)));
3026 SUBST (SET_DEST (x
), dest
);
3028 split
= find_split_point (&SET_SRC (x
), insn
);
3029 if (split
&& split
!= &SET_SRC (x
))
3033 /* Otherwise, see if this is an operation that we can split into two.
3034 If so, try to split that. */
3035 code
= GET_CODE (SET_SRC (x
));
3040 /* If we are AND'ing with a large constant that is only a single
3041 bit and the result is only being used in a context where we
3042 need to know if it is zero or nonzero, replace it with a bit
3043 extraction. This will avoid the large constant, which might
3044 have taken more than one insn to make. If the constant were
3045 not a valid argument to the AND but took only one insn to make,
3046 this is no worse, but if it took more than one insn, it will
3049 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3050 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3051 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3052 && GET_CODE (SET_DEST (x
)) == REG
3053 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3054 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3055 && XEXP (*split
, 0) == SET_DEST (x
)
3056 && XEXP (*split
, 1) == const0_rtx
)
3058 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3059 XEXP (SET_SRC (x
), 0),
3060 pos
, NULL_RTX
, 1, 1, 0, 0);
3061 if (extraction
!= 0)
3063 SUBST (SET_SRC (x
), extraction
);
3064 return find_split_point (loc
, insn
);
3070 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3071 is known to be on, this can be converted into a NEG of a shift. */
3072 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3073 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3074 && 1 <= (pos
= exact_log2
3075 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3076 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3078 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3082 gen_rtx_LSHIFTRT (mode
,
3083 XEXP (SET_SRC (x
), 0),
3086 split
= find_split_point (&SET_SRC (x
), insn
);
3087 if (split
&& split
!= &SET_SRC (x
))
3093 inner
= XEXP (SET_SRC (x
), 0);
3095 /* We can't optimize if either mode is a partial integer
3096 mode as we don't know how many bits are significant
3098 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3099 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3103 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3109 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3110 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3112 inner
= XEXP (SET_SRC (x
), 0);
3113 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3114 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3116 if (BITS_BIG_ENDIAN
)
3117 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3118 unsignedp
= (code
== ZERO_EXTRACT
);
3126 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3128 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3130 /* For unsigned, we have a choice of a shift followed by an
3131 AND or two shifts. Use two shifts for field sizes where the
3132 constant might be too large. We assume here that we can
3133 always at least get 8-bit constants in an AND insn, which is
3134 true for every current RISC. */
3136 if (unsignedp
&& len
<= 8)
3141 (mode
, gen_lowpart (mode
, inner
),
3143 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3145 split
= find_split_point (&SET_SRC (x
), insn
);
3146 if (split
&& split
!= &SET_SRC (x
))
3153 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3154 gen_rtx_ASHIFT (mode
,
3155 gen_lowpart (mode
, inner
),
3156 GEN_INT (GET_MODE_BITSIZE (mode
)
3158 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3160 split
= find_split_point (&SET_SRC (x
), insn
);
3161 if (split
&& split
!= &SET_SRC (x
))
3166 /* See if this is a simple operation with a constant as the second
3167 operand. It might be that this constant is out of range and hence
3168 could be used as a split point. */
3169 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3170 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3171 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3172 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3173 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3174 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3175 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3177 return &XEXP (SET_SRC (x
), 1);
3179 /* Finally, see if this is a simple operation with its first operand
3180 not in a register. The operation might require this operand in a
3181 register, so return it as a split point. We can always do this
3182 because if the first operand were another operation, we would have
3183 already found it as a split point. */
3184 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3185 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3186 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3187 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3188 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3189 return &XEXP (SET_SRC (x
), 0);
3195 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3196 it is better to write this as (not (ior A B)) so we can split it.
3197 Similarly for IOR. */
3198 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3201 gen_rtx_NOT (GET_MODE (x
),
3202 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3204 XEXP (XEXP (x
, 0), 0),
3205 XEXP (XEXP (x
, 1), 0))));
3206 return find_split_point (loc
, insn
);
3209 /* Many RISC machines have a large set of logical insns. If the
3210 second operand is a NOT, put it first so we will try to split the
3211 other operand first. */
3212 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3214 rtx tem
= XEXP (x
, 0);
3215 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3216 SUBST (XEXP (x
, 1), tem
);
3224 /* Otherwise, select our actions depending on our rtx class. */
3225 switch (GET_RTX_CLASS (code
))
3227 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3229 split
= find_split_point (&XEXP (x
, 2), insn
);
3232 /* ... fall through ... */
3236 split
= find_split_point (&XEXP (x
, 1), insn
);
3239 /* ... fall through ... */
3241 /* Some machines have (and (shift ...) ...) insns. If X is not
3242 an AND, but XEXP (X, 0) is, use it as our split point. */
3243 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3244 return &XEXP (x
, 0);
3246 split
= find_split_point (&XEXP (x
, 0), insn
);
3252 /* Otherwise, we don't have a split point. */
3256 /* Throughout X, replace FROM with TO, and return the result.
3257 The result is TO if X is FROM;
3258 otherwise the result is X, but its contents may have been modified.
3259 If they were modified, a record was made in undobuf so that
3260 undo_all will (among other things) return X to its original state.
3262 If the number of changes necessary is too much to record to undo,
3263 the excess changes are not made, so the result is invalid.
3264 The changes already made can still be undone.
3265 undobuf.num_undo is incremented for such changes, so by testing that
3266 the caller can tell whether the result is valid.
3268 `n_occurrences' is incremented each time FROM is replaced.
3270 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3272 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3273 by copying if `n_occurrences' is nonzero. */
3276 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3278 enum rtx_code code
= GET_CODE (x
);
3279 enum machine_mode op0_mode
= VOIDmode
;
3284 /* Two expressions are equal if they are identical copies of a shared
3285 RTX or if they are both registers with the same register number
3288 #define COMBINE_RTX_EQUAL_P(X,Y) \
3290 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3291 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3293 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3296 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3299 /* If X and FROM are the same register but different modes, they will
3300 not have been seen as equal above. However, flow.c will make a
3301 LOG_LINKS entry for that case. If we do nothing, we will try to
3302 rerecognize our original insn and, when it succeeds, we will
3303 delete the feeding insn, which is incorrect.
3305 So force this insn not to match in this (rare) case. */
3306 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3307 && REGNO (x
) == REGNO (from
))
3308 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3310 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3311 of which may contain things that can be combined. */
3312 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3315 /* It is possible to have a subexpression appear twice in the insn.
3316 Suppose that FROM is a register that appears within TO.
3317 Then, after that subexpression has been scanned once by `subst',
3318 the second time it is scanned, TO may be found. If we were
3319 to scan TO here, we would find FROM within it and create a
3320 self-referent rtl structure which is completely wrong. */
3321 if (COMBINE_RTX_EQUAL_P (x
, to
))
3324 /* Parallel asm_operands need special attention because all of the
3325 inputs are shared across the arms. Furthermore, unsharing the
3326 rtl results in recognition failures. Failure to handle this case
3327 specially can result in circular rtl.
3329 Solve this by doing a normal pass across the first entry of the
3330 parallel, and only processing the SET_DESTs of the subsequent
3333 if (code
== PARALLEL
3334 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3335 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3337 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3339 /* If this substitution failed, this whole thing fails. */
3340 if (GET_CODE (new) == CLOBBER
3341 && XEXP (new, 0) == const0_rtx
)
3344 SUBST (XVECEXP (x
, 0, 0), new);
3346 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3348 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3350 if (GET_CODE (dest
) != REG
3351 && GET_CODE (dest
) != CC0
3352 && GET_CODE (dest
) != PC
)
3354 new = subst (dest
, from
, to
, 0, unique_copy
);
3356 /* If this substitution failed, this whole thing fails. */
3357 if (GET_CODE (new) == CLOBBER
3358 && XEXP (new, 0) == const0_rtx
)
3361 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3367 len
= GET_RTX_LENGTH (code
);
3368 fmt
= GET_RTX_FORMAT (code
);
3370 /* We don't need to process a SET_DEST that is a register, CC0,
3371 or PC, so set up to skip this common case. All other cases
3372 where we want to suppress replacing something inside a
3373 SET_SRC are handled via the IN_DEST operand. */
3375 && (GET_CODE (SET_DEST (x
)) == REG
3376 || GET_CODE (SET_DEST (x
)) == CC0
3377 || GET_CODE (SET_DEST (x
)) == PC
))
3380 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3383 op0_mode
= GET_MODE (XEXP (x
, 0));
3385 for (i
= 0; i
< len
; i
++)
3390 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3392 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3394 new = (unique_copy
&& n_occurrences
3395 ? copy_rtx (to
) : to
);
3400 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3403 /* If this substitution failed, this whole thing
3405 if (GET_CODE (new) == CLOBBER
3406 && XEXP (new, 0) == const0_rtx
)
3410 SUBST (XVECEXP (x
, i
, j
), new);
3413 else if (fmt
[i
] == 'e')
3415 /* If this is a register being set, ignore it. */
3418 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3419 || code
== ZERO_EXTRACT
)
3421 && GET_CODE (new) == REG
)
3424 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3426 /* In general, don't install a subreg involving two
3427 modes not tieable. It can worsen register
3428 allocation, and can even make invalid reload
3429 insns, since the reg inside may need to be copied
3430 from in the outside mode, and that may be invalid
3431 if it is an fp reg copied in integer mode.
3433 We allow two exceptions to this: It is valid if
3434 it is inside another SUBREG and the mode of that
3435 SUBREG and the mode of the inside of TO is
3436 tieable and it is valid if X is a SET that copies
3439 if (GET_CODE (to
) == SUBREG
3440 && ! MODES_TIEABLE_P (GET_MODE (to
),
3441 GET_MODE (SUBREG_REG (to
)))
3442 && ! (code
== SUBREG
3443 && MODES_TIEABLE_P (GET_MODE (x
),
3444 GET_MODE (SUBREG_REG (to
))))
3446 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3449 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3451 #ifdef CANNOT_CHANGE_MODE_CLASS
3453 && GET_CODE (to
) == REG
3454 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3455 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3458 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3461 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3465 /* If we are in a SET_DEST, suppress most cases unless we
3466 have gone inside a MEM, in which case we want to
3467 simplify the address. We assume here that things that
3468 are actually part of the destination have their inner
3469 parts in the first expression. This is true for SUBREG,
3470 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3471 things aside from REG and MEM that should appear in a
3473 new = subst (XEXP (x
, i
), from
, to
,
3475 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3476 || code
== ZERO_EXTRACT
))
3478 && i
== 0), unique_copy
);
3480 /* If we found that we will have to reject this combination,
3481 indicate that by returning the CLOBBER ourselves, rather than
3482 an expression containing it. This will speed things up as
3483 well as prevent accidents where two CLOBBERs are considered
3484 to be equal, thus producing an incorrect simplification. */
3486 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3489 if (GET_CODE (x
) == SUBREG
3490 && (GET_CODE (new) == CONST_INT
3491 || GET_CODE (new) == CONST_DOUBLE
))
3493 enum machine_mode mode
= GET_MODE (x
);
3495 x
= simplify_subreg (GET_MODE (x
), new,
3496 GET_MODE (SUBREG_REG (x
)),
3499 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3501 else if (GET_CODE (new) == CONST_INT
3502 && GET_CODE (x
) == ZERO_EXTEND
)
3504 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3505 new, GET_MODE (XEXP (x
, 0)));
3510 SUBST (XEXP (x
, i
), new);
3515 /* Try to simplify X. If the simplification changed the code, it is likely
3516 that further simplification will help, so loop, but limit the number
3517 of repetitions that will be performed. */
3519 for (i
= 0; i
< 4; i
++)
3521 /* If X is sufficiently simple, don't bother trying to do anything
3523 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3524 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3526 if (GET_CODE (x
) == code
)
3529 code
= GET_CODE (x
);
3531 /* We no longer know the original mode of operand 0 since we
3532 have changed the form of X) */
3533 op0_mode
= VOIDmode
;
3539 /* Simplify X, a piece of RTL. We just operate on the expression at the
3540 outer level; call `subst' to simplify recursively. Return the new
3543 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3544 will be the iteration even if an expression with a code different from
3545 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3548 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3551 enum rtx_code code
= GET_CODE (x
);
3552 enum machine_mode mode
= GET_MODE (x
);
3557 /* If this is a commutative operation, put a constant last and a complex
3558 expression first. We don't need to do this for comparisons here. */
3559 if (GET_RTX_CLASS (code
) == 'c'
3560 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3563 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3564 SUBST (XEXP (x
, 1), temp
);
3567 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3568 sign extension of a PLUS with a constant, reverse the order of the sign
3569 extension and the addition. Note that this not the same as the original
3570 code, but overflow is undefined for signed values. Also note that the
3571 PLUS will have been partially moved "inside" the sign-extension, so that
3572 the first operand of X will really look like:
3573 (ashiftrt (plus (ashift A C4) C5) C4).
3575 (plus (ashiftrt (ashift A C4) C2) C4)
3576 and replace the first operand of X with that expression. Later parts
3577 of this function may simplify the expression further.
3579 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3580 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3581 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3583 We do this to simplify address expressions. */
3585 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3586 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3587 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3588 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3589 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3590 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3591 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3592 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3593 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3594 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3595 XEXP (XEXP (x
, 0), 1))) != 0)
3598 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3599 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3600 INTVAL (XEXP (XEXP (x
, 0), 1)));
3602 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3603 INTVAL (XEXP (XEXP (x
, 0), 1)));
3605 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3608 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3609 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3610 things. Check for cases where both arms are testing the same
3613 Don't do anything if all operands are very simple. */
3615 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3616 || GET_RTX_CLASS (code
) == '<')
3617 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3618 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3619 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3621 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3622 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3623 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3625 || (GET_RTX_CLASS (code
) == '1'
3626 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3627 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3628 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3631 rtx cond
, true_rtx
, false_rtx
;
3633 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3635 /* If everything is a comparison, what we have is highly unlikely
3636 to be simpler, so don't use it. */
3637 && ! (GET_RTX_CLASS (code
) == '<'
3638 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3639 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3641 rtx cop1
= const0_rtx
;
3642 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3644 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3647 /* Simplify the alternative arms; this may collapse the true and
3648 false arms to store-flag values. Be careful to use copy_rtx
3649 here since true_rtx or false_rtx might share RTL with x as a
3650 result of the if_then_else_cond call above. */
3651 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3652 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3654 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3655 is unlikely to be simpler. */
3656 if (general_operand (true_rtx
, VOIDmode
)
3657 && general_operand (false_rtx
, VOIDmode
))
3659 enum rtx_code reversed
;
3661 /* Restarting if we generate a store-flag expression will cause
3662 us to loop. Just drop through in this case. */
3664 /* If the result values are STORE_FLAG_VALUE and zero, we can
3665 just make the comparison operation. */
3666 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3667 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3668 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3669 && ((reversed
= reversed_comparison_code_parts
3670 (cond_code
, cond
, cop1
, NULL
))
3672 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3674 /* Likewise, we can make the negate of a comparison operation
3675 if the result values are - STORE_FLAG_VALUE and zero. */
3676 else if (GET_CODE (true_rtx
) == CONST_INT
3677 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3678 && false_rtx
== const0_rtx
)
3679 x
= simplify_gen_unary (NEG
, mode
,
3680 gen_binary (cond_code
, mode
, cond
,
3683 else if (GET_CODE (false_rtx
) == CONST_INT
3684 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3685 && true_rtx
== const0_rtx
3686 && ((reversed
= reversed_comparison_code_parts
3687 (cond_code
, cond
, cop1
, NULL
))
3689 x
= simplify_gen_unary (NEG
, mode
,
3690 gen_binary (reversed
, mode
,
3694 return gen_rtx_IF_THEN_ELSE (mode
,
3695 gen_binary (cond_code
, VOIDmode
,
3697 true_rtx
, false_rtx
);
3699 code
= GET_CODE (x
);
3700 op0_mode
= VOIDmode
;
3705 /* Try to fold this expression in case we have constants that weren't
3708 switch (GET_RTX_CLASS (code
))
3711 if (op0_mode
== VOIDmode
)
3712 op0_mode
= GET_MODE (XEXP (x
, 0));
3713 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3717 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3718 if (cmp_mode
== VOIDmode
)
3720 cmp_mode
= GET_MODE (XEXP (x
, 1));
3721 if (cmp_mode
== VOIDmode
)
3722 cmp_mode
= op0_mode
;
3724 temp
= simplify_relational_operation (code
, cmp_mode
,
3725 XEXP (x
, 0), XEXP (x
, 1));
3727 #ifdef FLOAT_STORE_FLAG_VALUE
3728 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3730 if (temp
== const0_rtx
)
3731 temp
= CONST0_RTX (mode
);
3733 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3740 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3744 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3745 XEXP (x
, 1), XEXP (x
, 2));
3752 code
= GET_CODE (temp
);
3753 op0_mode
= VOIDmode
;
3754 mode
= GET_MODE (temp
);
3757 /* First see if we can apply the inverse distributive law. */
3758 if (code
== PLUS
|| code
== MINUS
3759 || code
== AND
|| code
== IOR
|| code
== XOR
)
3761 x
= apply_distributive_law (x
);
3762 code
= GET_CODE (x
);
3763 op0_mode
= VOIDmode
;
3766 /* If CODE is an associative operation not otherwise handled, see if we
3767 can associate some operands. This can win if they are constants or
3768 if they are logically related (i.e. (a & b) & a). */
3769 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3770 || code
== AND
|| code
== IOR
|| code
== XOR
3771 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3772 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3773 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3775 if (GET_CODE (XEXP (x
, 0)) == code
)
3777 rtx other
= XEXP (XEXP (x
, 0), 0);
3778 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3779 rtx inner_op1
= XEXP (x
, 1);
3782 /* Make sure we pass the constant operand if any as the second
3783 one if this is a commutative operation. */
3784 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3786 rtx tem
= inner_op0
;
3787 inner_op0
= inner_op1
;
3790 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3791 : code
== DIV
? MULT
3793 mode
, inner_op0
, inner_op1
);
3795 /* For commutative operations, try the other pair if that one
3797 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3799 other
= XEXP (XEXP (x
, 0), 1);
3800 inner
= simplify_binary_operation (code
, mode
,
3801 XEXP (XEXP (x
, 0), 0),
3806 return gen_binary (code
, mode
, other
, inner
);
3810 /* A little bit of algebraic simplification here. */
3814 /* Ensure that our address has any ASHIFTs converted to MULT in case
3815 address-recognizing predicates are called later. */
3816 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3817 SUBST (XEXP (x
, 0), temp
);
3821 if (op0_mode
== VOIDmode
)
3822 op0_mode
= GET_MODE (SUBREG_REG (x
));
3824 /* See if this can be moved to simplify_subreg. */
3825 if (CONSTANT_P (SUBREG_REG (x
))
3826 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3827 /* Don't call gen_lowpart if the inner mode
3828 is VOIDmode and we cannot simplify it, as SUBREG without
3829 inner mode is invalid. */
3830 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3831 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3832 return gen_lowpart (mode
, SUBREG_REG (x
));
3834 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3838 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3844 /* Don't change the mode of the MEM if that would change the meaning
3846 if (GET_CODE (SUBREG_REG (x
)) == MEM
3847 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3848 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3849 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3851 /* Note that we cannot do any narrowing for non-constants since
3852 we might have been counting on using the fact that some bits were
3853 zero. We now do this in the SET. */
3858 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3859 && subreg_lowpart_p (XEXP (x
, 0))
3860 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3861 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3862 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3863 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3865 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3867 x
= gen_rtx_ROTATE (inner_mode
,
3868 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3870 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3871 return gen_lowpart (mode
, x
);
3874 /* Apply De Morgan's laws to reduce number of patterns for machines
3875 with negating logical insns (and-not, nand, etc.). If result has
3876 only one NOT, put it first, since that is how the patterns are
3879 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3881 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3882 enum machine_mode op_mode
;
3884 op_mode
= GET_MODE (in1
);
3885 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3887 op_mode
= GET_MODE (in2
);
3888 if (op_mode
== VOIDmode
)
3890 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3892 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3895 in2
= in1
; in1
= tem
;
3898 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3904 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3905 if (GET_CODE (XEXP (x
, 0)) == XOR
3906 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3907 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3908 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3910 temp
= expand_compound_operation (XEXP (x
, 0));
3912 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3913 replaced by (lshiftrt X C). This will convert
3914 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3916 if (GET_CODE (temp
) == ASHIFTRT
3917 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3918 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3919 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3920 INTVAL (XEXP (temp
, 1)));
3922 /* If X has only a single bit that might be nonzero, say, bit I, convert
3923 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3924 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3925 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3926 or a SUBREG of one since we'd be making the expression more
3927 complex if it was just a register. */
3929 if (GET_CODE (temp
) != REG
3930 && ! (GET_CODE (temp
) == SUBREG
3931 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3932 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3934 rtx temp1
= simplify_shift_const
3935 (NULL_RTX
, ASHIFTRT
, mode
,
3936 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3937 GET_MODE_BITSIZE (mode
) - 1 - i
),
3938 GET_MODE_BITSIZE (mode
) - 1 - i
);
3940 /* If all we did was surround TEMP with the two shifts, we
3941 haven't improved anything, so don't use it. Otherwise,
3942 we are better off with TEMP1. */
3943 if (GET_CODE (temp1
) != ASHIFTRT
3944 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3945 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3951 /* We can't handle truncation to a partial integer mode here
3952 because we don't know the real bitsize of the partial
3954 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3957 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3958 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3959 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3961 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3962 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3964 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3965 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3966 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3967 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3968 return XEXP (XEXP (x
, 0), 0);
3970 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3971 (OP:SI foo:SI) if OP is NEG or ABS. */
3972 if ((GET_CODE (XEXP (x
, 0)) == ABS
3973 || GET_CODE (XEXP (x
, 0)) == NEG
)
3974 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3975 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3976 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3977 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3978 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3980 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3982 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3983 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3984 && subreg_lowpart_p (XEXP (x
, 0)))
3985 return SUBREG_REG (XEXP (x
, 0));
3987 /* If we know that the value is already truncated, we can
3988 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3989 is nonzero for the corresponding modes. But don't do this
3990 for an (LSHIFTRT (MULT ...)) since this will cause problems
3991 with the umulXi3_highpart patterns. */
3992 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3993 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3994 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3995 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
3996 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3997 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
3998 return gen_lowpart (mode
, XEXP (x
, 0));
4000 /* A truncate of a comparison can be replaced with a subreg if
4001 STORE_FLAG_VALUE permits. This is like the previous test,
4002 but it works even if the comparison is done in a mode larger
4003 than HOST_BITS_PER_WIDE_INT. */
4004 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4005 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4006 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4007 return gen_lowpart (mode
, XEXP (x
, 0));
4009 /* Similarly, a truncate of a register whose value is a
4010 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4012 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4013 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4014 && (temp
= get_last_value (XEXP (x
, 0)))
4015 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4016 return gen_lowpart (mode
, XEXP (x
, 0));
4020 case FLOAT_TRUNCATE
:
4021 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4022 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4023 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4024 return XEXP (XEXP (x
, 0), 0);
4026 /* (float_truncate:SF (float_truncate:DF foo:XF))
4027 = (float_truncate:SF foo:XF).
4028 This may eliminate double rounding, so it is unsafe.
4030 (float_truncate:SF (float_extend:XF foo:DF))
4031 = (float_truncate:SF foo:DF).
4033 (float_truncate:DF (float_extend:XF foo:SF))
4034 = (float_extend:SF foo:DF). */
4035 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4036 && flag_unsafe_math_optimizations
)
4037 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4038 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4040 > GET_MODE_SIZE (mode
)
4041 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4043 XEXP (XEXP (x
, 0), 0), mode
);
4045 /* (float_truncate (float x)) is (float x) */
4046 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4047 && (flag_unsafe_math_optimizations
4048 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4049 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4050 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4051 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4052 return simplify_gen_unary (FLOAT
, mode
,
4053 XEXP (XEXP (x
, 0), 0),
4054 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4056 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4057 (OP:SF foo:SF) if OP is NEG or ABS. */
4058 if ((GET_CODE (XEXP (x
, 0)) == ABS
4059 || GET_CODE (XEXP (x
, 0)) == NEG
)
4060 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4061 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4062 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4063 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4065 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4066 is (float_truncate:SF x). */
4067 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4068 && subreg_lowpart_p (XEXP (x
, 0))
4069 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4070 return SUBREG_REG (XEXP (x
, 0));
4073 /* (float_extend (float_extend x)) is (float_extend x)
4075 (float_extend (float x)) is (float x) assuming that double
4076 rounding can't happen.
4078 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4079 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4080 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4081 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4082 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4083 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4084 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4085 XEXP (XEXP (x
, 0), 0),
4086 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4091 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4092 using cc0, in which case we want to leave it as a COMPARE
4093 so we can distinguish it from a register-register-copy. */
4094 if (XEXP (x
, 1) == const0_rtx
)
4097 /* x - 0 is the same as x unless x's mode has signed zeros and
4098 allows rounding towards -infinity. Under those conditions,
4100 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4101 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4102 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4108 /* (const (const X)) can become (const X). Do it this way rather than
4109 returning the inner CONST since CONST can be shared with a
4111 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4112 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4117 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4118 can add in an offset. find_split_point will split this address up
4119 again if it doesn't match. */
4120 if (GET_CODE (XEXP (x
, 0)) == HIGH
4121 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4127 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4129 if (GET_CODE (XEXP (x
, 0)) == MULT
4130 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4134 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4135 in2
= XEXP (XEXP (x
, 0), 1);
4136 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4137 gen_binary (MULT
, mode
, in1
, in2
));
4140 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4141 outermost. That's because that's the way indexed addresses are
4142 supposed to appear. This code used to check many more cases, but
4143 they are now checked elsewhere. */
4144 if (GET_CODE (XEXP (x
, 0)) == PLUS
4145 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4146 return gen_binary (PLUS
, mode
,
4147 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4149 XEXP (XEXP (x
, 0), 1));
4151 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4152 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4153 bit-field and can be replaced by either a sign_extend or a
4154 sign_extract. The `and' may be a zero_extend and the two
4155 <c>, -<c> constants may be reversed. */
4156 if (GET_CODE (XEXP (x
, 0)) == XOR
4157 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4158 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4159 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4160 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4161 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4162 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4163 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4164 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4165 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4166 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4167 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4168 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4169 == (unsigned int) i
+ 1))))
4170 return simplify_shift_const
4171 (NULL_RTX
, ASHIFTRT
, mode
,
4172 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4173 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4174 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4175 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4177 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4178 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4179 is 1. This produces better code than the alternative immediately
4181 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4182 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4183 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4184 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4185 XEXP (XEXP (x
, 0), 0),
4186 XEXP (XEXP (x
, 0), 1))))
4188 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4190 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4191 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4192 the bitsize of the mode - 1. This allows simplification of
4193 "a = (b & 8) == 0;" */
4194 if (XEXP (x
, 1) == constm1_rtx
4195 && GET_CODE (XEXP (x
, 0)) != REG
4196 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4197 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4198 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4199 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4200 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4201 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4202 GET_MODE_BITSIZE (mode
) - 1),
4203 GET_MODE_BITSIZE (mode
) - 1);
4205 /* If we are adding two things that have no bits in common, convert
4206 the addition into an IOR. This will often be further simplified,
4207 for example in cases like ((a & 1) + (a & 2)), which can
4210 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4211 && (nonzero_bits (XEXP (x
, 0), mode
)
4212 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4214 /* Try to simplify the expression further. */
4215 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4216 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4218 /* If we could, great. If not, do not go ahead with the IOR
4219 replacement, since PLUS appears in many special purpose
4220 address arithmetic instructions. */
4221 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4227 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4228 by reversing the comparison code if valid. */
4229 if (STORE_FLAG_VALUE
== 1
4230 && XEXP (x
, 0) == const1_rtx
4231 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4232 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4233 XEXP (XEXP (x
, 1), 0),
4234 XEXP (XEXP (x
, 1), 1))))
4237 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4238 (and <foo> (const_int pow2-1)) */
4239 if (GET_CODE (XEXP (x
, 1)) == AND
4240 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4241 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4242 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4243 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4244 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4246 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4248 if (GET_CODE (XEXP (x
, 1)) == MULT
4249 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4253 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4254 in2
= XEXP (XEXP (x
, 1), 1);
4255 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4259 /* Canonicalize (minus (neg A) (mult B C)) to
4260 (minus (mult (neg B) C) A). */
4261 if (GET_CODE (XEXP (x
, 1)) == MULT
4262 && GET_CODE (XEXP (x
, 0)) == NEG
)
4266 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4267 in2
= XEXP (XEXP (x
, 1), 1);
4268 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4269 XEXP (XEXP (x
, 0), 0));
4272 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4274 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4275 return gen_binary (MINUS
, mode
,
4276 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4277 XEXP (XEXP (x
, 1), 0)),
4278 XEXP (XEXP (x
, 1), 1));
4282 /* If we have (mult (plus A B) C), apply the distributive law and then
4283 the inverse distributive law to see if things simplify. This
4284 occurs mostly in addresses, often when unrolling loops. */
4286 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4288 x
= apply_distributive_law
4289 (gen_binary (PLUS
, mode
,
4290 gen_binary (MULT
, mode
,
4291 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4292 gen_binary (MULT
, mode
,
4293 XEXP (XEXP (x
, 0), 1),
4294 copy_rtx (XEXP (x
, 1)))));
4296 if (GET_CODE (x
) != MULT
)
4299 /* Try simplify a*(b/c) as (a*b)/c. */
4300 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4301 && GET_CODE (XEXP (x
, 0)) == DIV
)
4303 rtx tem
= simplify_binary_operation (MULT
, mode
,
4304 XEXP (XEXP (x
, 0), 0),
4307 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4312 /* If this is a divide by a power of two, treat it as a shift if
4313 its first operand is a shift. */
4314 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4315 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4316 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4317 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4318 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4319 || GET_CODE (XEXP (x
, 0)) == ROTATE
4320 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4321 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4325 case GT
: case GTU
: case GE
: case GEU
:
4326 case LT
: case LTU
: case LE
: case LEU
:
4327 case UNEQ
: case LTGT
:
4328 case UNGT
: case UNGE
:
4329 case UNLT
: case UNLE
:
4330 case UNORDERED
: case ORDERED
:
4331 /* If the first operand is a condition code, we can't do anything
4333 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4334 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4335 && ! CC0_P (XEXP (x
, 0))))
4337 rtx op0
= XEXP (x
, 0);
4338 rtx op1
= XEXP (x
, 1);
4339 enum rtx_code new_code
;
4341 if (GET_CODE (op0
) == COMPARE
)
4342 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4344 /* Simplify our comparison, if possible. */
4345 new_code
= simplify_comparison (code
, &op0
, &op1
);
4347 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4348 if only the low-order bit is possibly nonzero in X (such as when
4349 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4350 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4351 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4354 Remove any ZERO_EXTRACT we made when thinking this was a
4355 comparison. It may now be simpler to use, e.g., an AND. If a
4356 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4357 the call to make_compound_operation in the SET case. */
4359 if (STORE_FLAG_VALUE
== 1
4360 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4361 && op1
== const0_rtx
4362 && mode
== GET_MODE (op0
)
4363 && nonzero_bits (op0
, mode
) == 1)
4364 return gen_lowpart (mode
,
4365 expand_compound_operation (op0
));
4367 else if (STORE_FLAG_VALUE
== 1
4368 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4369 && op1
== const0_rtx
4370 && mode
== GET_MODE (op0
)
4371 && (num_sign_bit_copies (op0
, mode
)
4372 == GET_MODE_BITSIZE (mode
)))
4374 op0
= expand_compound_operation (op0
);
4375 return simplify_gen_unary (NEG
, mode
,
4376 gen_lowpart (mode
, op0
),
4380 else if (STORE_FLAG_VALUE
== 1
4381 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4382 && op1
== const0_rtx
4383 && mode
== GET_MODE (op0
)
4384 && nonzero_bits (op0
, mode
) == 1)
4386 op0
= expand_compound_operation (op0
);
4387 return gen_binary (XOR
, mode
,
4388 gen_lowpart (mode
, op0
),
4392 else if (STORE_FLAG_VALUE
== 1
4393 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4394 && op1
== const0_rtx
4395 && mode
== GET_MODE (op0
)
4396 && (num_sign_bit_copies (op0
, mode
)
4397 == GET_MODE_BITSIZE (mode
)))
4399 op0
= expand_compound_operation (op0
);
4400 return plus_constant (gen_lowpart (mode
, op0
), 1);
4403 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4405 if (STORE_FLAG_VALUE
== -1
4406 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4407 && op1
== const0_rtx
4408 && (num_sign_bit_copies (op0
, mode
)
4409 == GET_MODE_BITSIZE (mode
)))
4410 return gen_lowpart (mode
,
4411 expand_compound_operation (op0
));
4413 else if (STORE_FLAG_VALUE
== -1
4414 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4415 && op1
== const0_rtx
4416 && mode
== GET_MODE (op0
)
4417 && nonzero_bits (op0
, mode
) == 1)
4419 op0
= expand_compound_operation (op0
);
4420 return simplify_gen_unary (NEG
, mode
,
4421 gen_lowpart (mode
, op0
),
4425 else if (STORE_FLAG_VALUE
== -1
4426 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4427 && op1
== const0_rtx
4428 && mode
== GET_MODE (op0
)
4429 && (num_sign_bit_copies (op0
, mode
)
4430 == GET_MODE_BITSIZE (mode
)))
4432 op0
= expand_compound_operation (op0
);
4433 return simplify_gen_unary (NOT
, mode
,
4434 gen_lowpart (mode
, op0
),
4438 /* If X is 0/1, (eq X 0) is X-1. */
4439 else if (STORE_FLAG_VALUE
== -1
4440 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4441 && op1
== const0_rtx
4442 && mode
== GET_MODE (op0
)
4443 && nonzero_bits (op0
, mode
) == 1)
4445 op0
= expand_compound_operation (op0
);
4446 return plus_constant (gen_lowpart (mode
, op0
), -1);
4449 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4450 one bit that might be nonzero, we can convert (ne x 0) to
4451 (ashift x c) where C puts the bit in the sign bit. Remove any
4452 AND with STORE_FLAG_VALUE when we are done, since we are only
4453 going to test the sign bit. */
4454 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4455 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4456 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4457 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4458 && op1
== const0_rtx
4459 && mode
== GET_MODE (op0
)
4460 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4462 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4463 expand_compound_operation (op0
),
4464 GET_MODE_BITSIZE (mode
) - 1 - i
);
4465 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4471 /* If the code changed, return a whole new comparison. */
4472 if (new_code
!= code
)
4473 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4475 /* Otherwise, keep this operation, but maybe change its operands.
4476 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4477 SUBST (XEXP (x
, 0), op0
);
4478 SUBST (XEXP (x
, 1), op1
);
4483 return simplify_if_then_else (x
);
4489 /* If we are processing SET_DEST, we are done. */
4493 return expand_compound_operation (x
);
4496 return simplify_set (x
);
4501 return simplify_logical (x
, last
);
4504 /* (abs (neg <foo>)) -> (abs <foo>) */
4505 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4506 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4508 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4510 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4513 /* If operand is something known to be positive, ignore the ABS. */
4514 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4515 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4516 <= HOST_BITS_PER_WIDE_INT
)
4517 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4518 & ((HOST_WIDE_INT
) 1
4519 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4523 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4524 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4525 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4530 /* (ffs (*_extend <X>)) = (ffs <X>) */
4531 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4532 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4533 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4538 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4539 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4540 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4544 /* (float (sign_extend <X>)) = (float <X>). */
4545 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4546 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4554 /* If this is a shift by a constant amount, simplify it. */
4555 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4556 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4557 INTVAL (XEXP (x
, 1)));
4559 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4561 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4563 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4570 rtx op0
= XEXP (x
, 0);
4571 rtx op1
= XEXP (x
, 1);
4574 if (GET_CODE (op1
) != PARALLEL
)
4576 len
= XVECLEN (op1
, 0);
4578 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4579 && GET_CODE (op0
) == VEC_CONCAT
)
4581 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4583 /* Try to find the element in the VEC_CONCAT. */
4586 if (GET_MODE (op0
) == GET_MODE (x
))
4588 if (GET_CODE (op0
) == VEC_CONCAT
)
4590 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4591 if (op0_size
< offset
)
4592 op0
= XEXP (op0
, 0);
4596 op0
= XEXP (op0
, 1);
4614 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4617 simplify_if_then_else (rtx x
)
4619 enum machine_mode mode
= GET_MODE (x
);
4620 rtx cond
= XEXP (x
, 0);
4621 rtx true_rtx
= XEXP (x
, 1);
4622 rtx false_rtx
= XEXP (x
, 2);
4623 enum rtx_code true_code
= GET_CODE (cond
);
4624 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4627 enum rtx_code false_code
;
4630 /* Simplify storing of the truth value. */
4631 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4632 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4634 /* Also when the truth value has to be reversed. */
4636 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4637 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4641 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4642 in it is being compared against certain values. Get the true and false
4643 comparisons and see if that says anything about the value of each arm. */
4646 && ((false_code
= combine_reversed_comparison_code (cond
))
4648 && GET_CODE (XEXP (cond
, 0)) == REG
)
4651 rtx from
= XEXP (cond
, 0);
4652 rtx true_val
= XEXP (cond
, 1);
4653 rtx false_val
= true_val
;
4656 /* If FALSE_CODE is EQ, swap the codes and arms. */
4658 if (false_code
== EQ
)
4660 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4661 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4664 /* If we are comparing against zero and the expression being tested has
4665 only a single bit that might be nonzero, that is its value when it is
4666 not equal to zero. Similarly if it is known to be -1 or 0. */
4668 if (true_code
== EQ
&& true_val
== const0_rtx
4669 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4670 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4671 else if (true_code
== EQ
&& true_val
== const0_rtx
4672 && (num_sign_bit_copies (from
, GET_MODE (from
))
4673 == GET_MODE_BITSIZE (GET_MODE (from
))))
4674 false_code
= EQ
, false_val
= constm1_rtx
;
4676 /* Now simplify an arm if we know the value of the register in the
4677 branch and it is used in the arm. Be careful due to the potential
4678 of locally-shared RTL. */
4680 if (reg_mentioned_p (from
, true_rtx
))
4681 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4683 pc_rtx
, pc_rtx
, 0, 0);
4684 if (reg_mentioned_p (from
, false_rtx
))
4685 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4687 pc_rtx
, pc_rtx
, 0, 0);
4689 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4690 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4692 true_rtx
= XEXP (x
, 1);
4693 false_rtx
= XEXP (x
, 2);
4694 true_code
= GET_CODE (cond
);
4697 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4698 reversed, do so to avoid needing two sets of patterns for
4699 subtract-and-branch insns. Similarly if we have a constant in the true
4700 arm, the false arm is the same as the first operand of the comparison, or
4701 the false arm is more complicated than the true arm. */
4704 && combine_reversed_comparison_code (cond
) != UNKNOWN
4705 && (true_rtx
== pc_rtx
4706 || (CONSTANT_P (true_rtx
)
4707 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4708 || true_rtx
== const0_rtx
4709 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4710 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4711 || (GET_CODE (true_rtx
) == SUBREG
4712 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4713 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4714 || reg_mentioned_p (true_rtx
, false_rtx
)
4715 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4717 true_code
= reversed_comparison_code (cond
, NULL
);
4719 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4722 SUBST (XEXP (x
, 1), false_rtx
);
4723 SUBST (XEXP (x
, 2), true_rtx
);
4725 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4728 /* It is possible that the conditional has been simplified out. */
4729 true_code
= GET_CODE (cond
);
4730 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4733 /* If the two arms are identical, we don't need the comparison. */
4735 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4738 /* Convert a == b ? b : a to "a". */
4739 if (true_code
== EQ
&& ! side_effects_p (cond
)
4740 && !HONOR_NANS (mode
)
4741 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4742 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4744 else if (true_code
== NE
&& ! side_effects_p (cond
)
4745 && !HONOR_NANS (mode
)
4746 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4747 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4750 /* Look for cases where we have (abs x) or (neg (abs X)). */
4752 if (GET_MODE_CLASS (mode
) == MODE_INT
4753 && GET_CODE (false_rtx
) == NEG
4754 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4756 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4757 && ! side_effects_p (true_rtx
))
4762 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4766 simplify_gen_unary (NEG
, mode
,
4767 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4773 /* Look for MIN or MAX. */
4775 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4777 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4778 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4779 && ! side_effects_p (cond
))
4784 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4787 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4790 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4793 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4798 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4799 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4800 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4801 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4802 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4803 neither 1 or -1, but it isn't worth checking for. */
4805 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4807 && GET_MODE_CLASS (mode
) == MODE_INT
4808 && ! side_effects_p (x
))
4810 rtx t
= make_compound_operation (true_rtx
, SET
);
4811 rtx f
= make_compound_operation (false_rtx
, SET
);
4812 rtx cond_op0
= XEXP (cond
, 0);
4813 rtx cond_op1
= XEXP (cond
, 1);
4814 enum rtx_code op
= NIL
, extend_op
= NIL
;
4815 enum machine_mode m
= mode
;
4816 rtx z
= 0, c1
= NULL_RTX
;
4818 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4819 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4820 || GET_CODE (t
) == ASHIFT
4821 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4822 && rtx_equal_p (XEXP (t
, 0), f
))
4823 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4825 /* If an identity-zero op is commutative, check whether there
4826 would be a match if we swapped the operands. */
4827 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4828 || GET_CODE (t
) == XOR
)
4829 && rtx_equal_p (XEXP (t
, 1), f
))
4830 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4831 else if (GET_CODE (t
) == SIGN_EXTEND
4832 && (GET_CODE (XEXP (t
, 0)) == PLUS
4833 || GET_CODE (XEXP (t
, 0)) == MINUS
4834 || GET_CODE (XEXP (t
, 0)) == IOR
4835 || GET_CODE (XEXP (t
, 0)) == XOR
4836 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4837 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4838 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4839 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4840 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4841 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4842 && (num_sign_bit_copies (f
, GET_MODE (f
))
4844 (GET_MODE_BITSIZE (mode
)
4845 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4847 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4848 extend_op
= SIGN_EXTEND
;
4849 m
= GET_MODE (XEXP (t
, 0));
4851 else if (GET_CODE (t
) == SIGN_EXTEND
4852 && (GET_CODE (XEXP (t
, 0)) == PLUS
4853 || GET_CODE (XEXP (t
, 0)) == IOR
4854 || GET_CODE (XEXP (t
, 0)) == XOR
)
4855 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4856 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4857 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4858 && (num_sign_bit_copies (f
, GET_MODE (f
))
4860 (GET_MODE_BITSIZE (mode
)
4861 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4863 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4864 extend_op
= SIGN_EXTEND
;
4865 m
= GET_MODE (XEXP (t
, 0));
4867 else if (GET_CODE (t
) == ZERO_EXTEND
4868 && (GET_CODE (XEXP (t
, 0)) == PLUS
4869 || GET_CODE (XEXP (t
, 0)) == MINUS
4870 || GET_CODE (XEXP (t
, 0)) == IOR
4871 || GET_CODE (XEXP (t
, 0)) == XOR
4872 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4873 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4874 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4875 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4876 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4877 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4878 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4879 && ((nonzero_bits (f
, GET_MODE (f
))
4880 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4883 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4884 extend_op
= ZERO_EXTEND
;
4885 m
= GET_MODE (XEXP (t
, 0));
4887 else if (GET_CODE (t
) == ZERO_EXTEND
4888 && (GET_CODE (XEXP (t
, 0)) == PLUS
4889 || GET_CODE (XEXP (t
, 0)) == IOR
4890 || GET_CODE (XEXP (t
, 0)) == XOR
)
4891 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4892 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4893 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4894 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4895 && ((nonzero_bits (f
, GET_MODE (f
))
4896 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4899 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4900 extend_op
= ZERO_EXTEND
;
4901 m
= GET_MODE (XEXP (t
, 0));
4906 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4907 pc_rtx
, pc_rtx
, 0, 0);
4908 temp
= gen_binary (MULT
, m
, temp
,
4909 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4910 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4911 temp
= gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
4913 if (extend_op
!= NIL
)
4914 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4920 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4921 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4922 negation of a single bit, we can convert this operation to a shift. We
4923 can actually do this more generally, but it doesn't seem worth it. */
4925 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4926 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4927 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4928 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4929 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4930 == GET_MODE_BITSIZE (mode
))
4931 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4933 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4934 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
4936 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4937 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4938 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4939 && GET_MODE (XEXP (cond
, 0)) == mode
4940 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4941 == nonzero_bits (XEXP (cond
, 0), mode
)
4942 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4943 return XEXP (cond
, 0);
4948 /* Simplify X, a SET expression. Return the new expression. */
4951 simplify_set (rtx x
)
4953 rtx src
= SET_SRC (x
);
4954 rtx dest
= SET_DEST (x
);
4955 enum machine_mode mode
4956 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4960 /* (set (pc) (return)) gets written as (return). */
4961 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4964 /* Now that we know for sure which bits of SRC we are using, see if we can
4965 simplify the expression for the object knowing that we only need the
4968 if (GET_MODE_CLASS (mode
) == MODE_INT
4969 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4971 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4972 SUBST (SET_SRC (x
), src
);
4975 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4976 the comparison result and try to simplify it unless we already have used
4977 undobuf.other_insn. */
4978 if ((GET_MODE_CLASS (mode
) == MODE_CC
4979 || GET_CODE (src
) == COMPARE
4981 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4982 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4983 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4984 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4986 enum rtx_code old_code
= GET_CODE (*cc_use
);
4987 enum rtx_code new_code
;
4989 int other_changed
= 0;
4990 enum machine_mode compare_mode
= GET_MODE (dest
);
4991 enum machine_mode tmp_mode
;
4993 if (GET_CODE (src
) == COMPARE
)
4994 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4996 op0
= src
, op1
= const0_rtx
;
4998 /* Check whether the comparison is known at compile time. */
4999 if (GET_MODE (op0
) != VOIDmode
)
5000 tmp_mode
= GET_MODE (op0
);
5001 else if (GET_MODE (op1
) != VOIDmode
)
5002 tmp_mode
= GET_MODE (op1
);
5004 tmp_mode
= compare_mode
;
5005 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5006 if (tmp
!= NULL_RTX
)
5008 rtx pat
= PATTERN (other_insn
);
5009 undobuf
.other_insn
= other_insn
;
5010 SUBST (*cc_use
, tmp
);
5012 /* Attempt to simplify CC user. */
5013 if (GET_CODE (pat
) == SET
)
5015 rtx
new = simplify_rtx (SET_SRC (pat
));
5016 if (new != NULL_RTX
)
5017 SUBST (SET_SRC (pat
), new);
5020 /* Convert X into a no-op move. */
5021 SUBST (SET_DEST (x
), pc_rtx
);
5022 SUBST (SET_SRC (x
), pc_rtx
);
5026 /* Simplify our comparison, if possible. */
5027 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5029 #ifdef SELECT_CC_MODE
5030 /* If this machine has CC modes other than CCmode, check to see if we
5031 need to use a different CC mode here. */
5032 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5035 /* If the mode changed, we have to change SET_DEST, the mode in the
5036 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5037 a hard register, just build new versions with the proper mode. If it
5038 is a pseudo, we lose unless it is only time we set the pseudo, in
5039 which case we can safely change its mode. */
5040 if (compare_mode
!= GET_MODE (dest
))
5042 unsigned int regno
= REGNO (dest
);
5043 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5045 if (regno
< FIRST_PSEUDO_REGISTER
5046 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5048 if (regno
>= FIRST_PSEUDO_REGISTER
)
5049 SUBST (regno_reg_rtx
[regno
], new_dest
);
5051 SUBST (SET_DEST (x
), new_dest
);
5052 SUBST (XEXP (*cc_use
, 0), new_dest
);
5059 #endif /* SELECT_CC_MODE */
5061 /* If the code changed, we have to build a new comparison in
5062 undobuf.other_insn. */
5063 if (new_code
!= old_code
)
5065 int other_changed_previously
= other_changed
;
5066 unsigned HOST_WIDE_INT mask
;
5068 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5072 /* If the only change we made was to change an EQ into an NE or
5073 vice versa, OP0 has only one bit that might be nonzero, and OP1
5074 is zero, check if changing the user of the condition code will
5075 produce a valid insn. If it won't, we can keep the original code
5076 in that insn by surrounding our operation with an XOR. */
5078 if (((old_code
== NE
&& new_code
== EQ
)
5079 || (old_code
== EQ
&& new_code
== NE
))
5080 && ! other_changed_previously
&& op1
== const0_rtx
5081 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5082 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5084 rtx pat
= PATTERN (other_insn
), note
= 0;
5086 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5087 && ! check_asm_operands (pat
)))
5089 PUT_CODE (*cc_use
, old_code
);
5092 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5098 undobuf
.other_insn
= other_insn
;
5101 /* If we are now comparing against zero, change our source if
5102 needed. If we do not use cc0, we always have a COMPARE. */
5103 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5105 SUBST (SET_SRC (x
), op0
);
5111 /* Otherwise, if we didn't previously have a COMPARE in the
5112 correct mode, we need one. */
5113 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5115 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5120 /* Otherwise, update the COMPARE if needed. */
5121 SUBST (XEXP (src
, 0), op0
);
5122 SUBST (XEXP (src
, 1), op1
);
5127 /* Get SET_SRC in a form where we have placed back any
5128 compound expressions. Then do the checks below. */
5129 src
= make_compound_operation (src
, SET
);
5130 SUBST (SET_SRC (x
), src
);
5133 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5134 and X being a REG or (subreg (reg)), we may be able to convert this to
5135 (set (subreg:m2 x) (op)).
5137 We can always do this if M1 is narrower than M2 because that means that
5138 we only care about the low bits of the result.
5140 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5141 perform a narrower operation than requested since the high-order bits will
5142 be undefined. On machine where it is defined, this transformation is safe
5143 as long as M1 and M2 have the same number of words. */
5145 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5146 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5147 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5149 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5150 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5151 #ifndef WORD_REGISTER_OPERATIONS
5152 && (GET_MODE_SIZE (GET_MODE (src
))
5153 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5155 #ifdef CANNOT_CHANGE_MODE_CLASS
5156 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5157 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5158 GET_MODE (SUBREG_REG (src
)),
5161 && (GET_CODE (dest
) == REG
5162 || (GET_CODE (dest
) == SUBREG
5163 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5165 SUBST (SET_DEST (x
),
5166 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5168 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5170 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5174 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5177 && GET_CODE (src
) == SUBREG
5178 && subreg_lowpart_p (src
)
5179 && (GET_MODE_BITSIZE (GET_MODE (src
))
5180 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5182 rtx inner
= SUBREG_REG (src
);
5183 enum machine_mode inner_mode
= GET_MODE (inner
);
5185 /* Here we make sure that we don't have a sign bit on. */
5186 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5187 && (nonzero_bits (inner
, inner_mode
)
5188 < ((unsigned HOST_WIDE_INT
) 1
5189 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5191 SUBST (SET_SRC (x
), inner
);
5197 #ifdef LOAD_EXTEND_OP
5198 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5199 would require a paradoxical subreg. Replace the subreg with a
5200 zero_extend to avoid the reload that would otherwise be required. */
5202 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5203 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5204 && SUBREG_BYTE (src
) == 0
5205 && (GET_MODE_SIZE (GET_MODE (src
))
5206 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5207 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5210 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5211 GET_MODE (src
), SUBREG_REG (src
)));
5217 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5218 are comparing an item known to be 0 or -1 against 0, use a logical
5219 operation instead. Check for one of the arms being an IOR of the other
5220 arm with some value. We compute three terms to be IOR'ed together. In
5221 practice, at most two will be nonzero. Then we do the IOR's. */
5223 if (GET_CODE (dest
) != PC
5224 && GET_CODE (src
) == IF_THEN_ELSE
5225 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5226 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5227 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5228 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5229 #ifdef HAVE_conditional_move
5230 && ! can_conditionally_move_p (GET_MODE (src
))
5232 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5233 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5234 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5235 && ! side_effects_p (src
))
5237 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5238 ? XEXP (src
, 1) : XEXP (src
, 2));
5239 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5240 ? XEXP (src
, 2) : XEXP (src
, 1));
5241 rtx term1
= const0_rtx
, term2
, term3
;
5243 if (GET_CODE (true_rtx
) == IOR
5244 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5245 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5246 else if (GET_CODE (true_rtx
) == IOR
5247 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5248 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5249 else if (GET_CODE (false_rtx
) == IOR
5250 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5251 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5252 else if (GET_CODE (false_rtx
) == IOR
5253 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5254 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5256 term2
= gen_binary (AND
, GET_MODE (src
),
5257 XEXP (XEXP (src
, 0), 0), true_rtx
);
5258 term3
= gen_binary (AND
, GET_MODE (src
),
5259 simplify_gen_unary (NOT
, GET_MODE (src
),
5260 XEXP (XEXP (src
, 0), 0),
5265 gen_binary (IOR
, GET_MODE (src
),
5266 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5272 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5273 whole thing fail. */
5274 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5276 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5279 /* Convert this into a field assignment operation, if possible. */
5280 return make_field_assignment (x
);
5283 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5284 result. LAST is nonzero if this is the last retry. */
5287 simplify_logical (rtx x
, int last
)
5289 enum machine_mode mode
= GET_MODE (x
);
5290 rtx op0
= XEXP (x
, 0);
5291 rtx op1
= XEXP (x
, 1);
5294 switch (GET_CODE (x
))
5297 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5298 insn (and may simplify more). */
5299 if (GET_CODE (op0
) == XOR
5300 && rtx_equal_p (XEXP (op0
, 0), op1
)
5301 && ! side_effects_p (op1
))
5302 x
= gen_binary (AND
, mode
,
5303 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5306 if (GET_CODE (op0
) == XOR
5307 && rtx_equal_p (XEXP (op0
, 1), op1
)
5308 && ! side_effects_p (op1
))
5309 x
= gen_binary (AND
, mode
,
5310 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5313 /* Similarly for (~(A ^ B)) & A. */
5314 if (GET_CODE (op0
) == NOT
5315 && GET_CODE (XEXP (op0
, 0)) == XOR
5316 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5317 && ! side_effects_p (op1
))
5318 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5320 if (GET_CODE (op0
) == NOT
5321 && GET_CODE (XEXP (op0
, 0)) == XOR
5322 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5323 && ! side_effects_p (op1
))
5324 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5326 /* We can call simplify_and_const_int only if we don't lose
5327 any (sign) bits when converting INTVAL (op1) to
5328 "unsigned HOST_WIDE_INT". */
5329 if (GET_CODE (op1
) == CONST_INT
5330 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5331 || INTVAL (op1
) > 0))
5333 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5335 /* If we have (ior (and (X C1) C2)) and the next restart would be
5336 the last, simplify this by making C1 as small as possible
5339 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5340 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5341 && GET_CODE (op1
) == CONST_INT
)
5342 return gen_binary (IOR
, mode
,
5343 gen_binary (AND
, mode
, XEXP (op0
, 0),
5344 GEN_INT (INTVAL (XEXP (op0
, 1))
5345 & ~INTVAL (op1
))), op1
);
5347 if (GET_CODE (x
) != AND
)
5350 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5351 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5352 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5355 /* Convert (A | B) & A to A. */
5356 if (GET_CODE (op0
) == IOR
5357 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5358 || rtx_equal_p (XEXP (op0
, 1), op1
))
5359 && ! side_effects_p (XEXP (op0
, 0))
5360 && ! side_effects_p (XEXP (op0
, 1)))
5363 /* In the following group of tests (and those in case IOR below),
5364 we start with some combination of logical operations and apply
5365 the distributive law followed by the inverse distributive law.
5366 Most of the time, this results in no change. However, if some of
5367 the operands are the same or inverses of each other, simplifications
5370 For example, (and (ior A B) (not B)) can occur as the result of
5371 expanding a bit field assignment. When we apply the distributive
5372 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5373 which then simplifies to (and (A (not B))).
5375 If we have (and (ior A B) C), apply the distributive law and then
5376 the inverse distributive law to see if things simplify. */
5378 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5380 x
= apply_distributive_law
5381 (gen_binary (GET_CODE (op0
), mode
,
5382 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5383 gen_binary (AND
, mode
, XEXP (op0
, 1),
5385 if (GET_CODE (x
) != AND
)
5389 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5390 return apply_distributive_law
5391 (gen_binary (GET_CODE (op1
), mode
,
5392 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5393 gen_binary (AND
, mode
, XEXP (op1
, 1),
5396 /* Similarly, taking advantage of the fact that
5397 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5399 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5400 return apply_distributive_law
5401 (gen_binary (XOR
, mode
,
5402 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5403 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5406 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5407 return apply_distributive_law
5408 (gen_binary (XOR
, mode
,
5409 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5410 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5414 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5415 if (GET_CODE (op1
) == CONST_INT
5416 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5417 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5420 /* Convert (A & B) | A to A. */
5421 if (GET_CODE (op0
) == AND
5422 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5423 || rtx_equal_p (XEXP (op0
, 1), op1
))
5424 && ! side_effects_p (XEXP (op0
, 0))
5425 && ! side_effects_p (XEXP (op0
, 1)))
5428 /* If we have (ior (and A B) C), apply the distributive law and then
5429 the inverse distributive law to see if things simplify. */
5431 if (GET_CODE (op0
) == AND
)
5433 x
= apply_distributive_law
5434 (gen_binary (AND
, mode
,
5435 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5436 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5439 if (GET_CODE (x
) != IOR
)
5443 if (GET_CODE (op1
) == AND
)
5445 x
= apply_distributive_law
5446 (gen_binary (AND
, mode
,
5447 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5448 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5451 if (GET_CODE (x
) != IOR
)
5455 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5456 mode size to (rotate A CX). */
5458 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5459 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5460 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5461 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5462 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5463 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5464 == GET_MODE_BITSIZE (mode
)))
5465 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5466 (GET_CODE (op0
) == ASHIFT
5467 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5469 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5470 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5471 does not affect any of the bits in OP1, it can really be done
5472 as a PLUS and we can associate. We do this by seeing if OP1
5473 can be safely shifted left C bits. */
5474 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5475 && GET_CODE (XEXP (op0
, 0)) == PLUS
5476 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5477 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5478 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5480 int count
= INTVAL (XEXP (op0
, 1));
5481 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5483 if (mask
>> count
== INTVAL (op1
)
5484 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5486 SUBST (XEXP (XEXP (op0
, 0), 1),
5487 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5494 /* If we are XORing two things that have no bits in common,
5495 convert them into an IOR. This helps to detect rotation encoded
5496 using those methods and possibly other simplifications. */
5498 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5499 && (nonzero_bits (op0
, mode
)
5500 & nonzero_bits (op1
, mode
)) == 0)
5501 return (gen_binary (IOR
, mode
, op0
, op1
));
5503 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5504 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5507 int num_negated
= 0;
5509 if (GET_CODE (op0
) == NOT
)
5510 num_negated
++, op0
= XEXP (op0
, 0);
5511 if (GET_CODE (op1
) == NOT
)
5512 num_negated
++, op1
= XEXP (op1
, 0);
5514 if (num_negated
== 2)
5516 SUBST (XEXP (x
, 0), op0
);
5517 SUBST (XEXP (x
, 1), op1
);
5519 else if (num_negated
== 1)
5521 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5525 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5526 correspond to a machine insn or result in further simplifications
5527 if B is a constant. */
5529 if (GET_CODE (op0
) == AND
5530 && rtx_equal_p (XEXP (op0
, 1), op1
)
5531 && ! side_effects_p (op1
))
5532 return gen_binary (AND
, mode
,
5533 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5536 else if (GET_CODE (op0
) == AND
5537 && rtx_equal_p (XEXP (op0
, 0), op1
)
5538 && ! side_effects_p (op1
))
5539 return gen_binary (AND
, mode
,
5540 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5543 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5544 comparison if STORE_FLAG_VALUE is 1. */
5545 if (STORE_FLAG_VALUE
== 1
5546 && op1
== const1_rtx
5547 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5548 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5552 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5553 is (lt foo (const_int 0)), so we can perform the above
5554 simplification if STORE_FLAG_VALUE is 1. */
5556 if (STORE_FLAG_VALUE
== 1
5557 && op1
== const1_rtx
5558 && GET_CODE (op0
) == LSHIFTRT
5559 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5560 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5561 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5563 /* (xor (comparison foo bar) (const_int sign-bit))
5564 when STORE_FLAG_VALUE is the sign bit. */
5565 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5566 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5567 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5568 && op1
== const_true_rtx
5569 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5570 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5583 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5584 operations" because they can be replaced with two more basic operations.
5585 ZERO_EXTEND is also considered "compound" because it can be replaced with
5586 an AND operation, which is simpler, though only one operation.
5588 The function expand_compound_operation is called with an rtx expression
5589 and will convert it to the appropriate shifts and AND operations,
5590 simplifying at each stage.
5592 The function make_compound_operation is called to convert an expression
5593 consisting of shifts and ANDs into the equivalent compound expression.
5594 It is the inverse of this function, loosely speaking. */
5597 expand_compound_operation (rtx x
)
5599 unsigned HOST_WIDE_INT pos
= 0, len
;
5601 unsigned int modewidth
;
5604 switch (GET_CODE (x
))
5609 /* We can't necessarily use a const_int for a multiword mode;
5610 it depends on implicitly extending the value.
5611 Since we don't know the right way to extend it,
5612 we can't tell whether the implicit way is right.
5614 Even for a mode that is no wider than a const_int,
5615 we can't win, because we need to sign extend one of its bits through
5616 the rest of it, and we don't know which bit. */
5617 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5620 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5621 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5622 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5623 reloaded. If not for that, MEM's would very rarely be safe.
5625 Reject MODEs bigger than a word, because we might not be able
5626 to reference a two-register group starting with an arbitrary register
5627 (and currently gen_lowpart might crash for a SUBREG). */
5629 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5632 /* Reject MODEs that aren't scalar integers because turning vector
5633 or complex modes into shifts causes problems. */
5635 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5638 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5639 /* If the inner object has VOIDmode (the only way this can happen
5640 is if it is an ASM_OPERANDS), we can't do anything since we don't
5641 know how much masking to do. */
5650 /* If the operand is a CLOBBER, just return it. */
5651 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5654 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5655 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5656 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5659 /* Reject MODEs that aren't scalar integers because turning vector
5660 or complex modes into shifts causes problems. */
5662 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5665 len
= INTVAL (XEXP (x
, 1));
5666 pos
= INTVAL (XEXP (x
, 2));
5668 /* If this goes outside the object being extracted, replace the object
5669 with a (use (mem ...)) construct that only combine understands
5670 and is used only for this purpose. */
5671 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5672 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5674 if (BITS_BIG_ENDIAN
)
5675 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5682 /* Convert sign extension to zero extension, if we know that the high
5683 bit is not set, as this is easier to optimize. It will be converted
5684 back to cheaper alternative in make_extraction. */
5685 if (GET_CODE (x
) == SIGN_EXTEND
5686 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5687 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5688 & ~(((unsigned HOST_WIDE_INT
)
5689 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5693 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5694 rtx temp2
= expand_compound_operation (temp
);
5696 /* Make sure this is a profitable operation. */
5697 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5699 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5705 /* We can optimize some special cases of ZERO_EXTEND. */
5706 if (GET_CODE (x
) == ZERO_EXTEND
)
5708 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5709 know that the last value didn't have any inappropriate bits
5711 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5712 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5713 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5714 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5715 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5716 return XEXP (XEXP (x
, 0), 0);
5718 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5719 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5720 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5721 && subreg_lowpart_p (XEXP (x
, 0))
5722 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5723 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5724 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5725 return SUBREG_REG (XEXP (x
, 0));
5727 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5728 is a comparison and STORE_FLAG_VALUE permits. This is like
5729 the first case, but it works even when GET_MODE (x) is larger
5730 than HOST_WIDE_INT. */
5731 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5732 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5733 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5734 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5735 <= HOST_BITS_PER_WIDE_INT
)
5736 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5737 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5738 return XEXP (XEXP (x
, 0), 0);
5740 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5741 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5742 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5743 && subreg_lowpart_p (XEXP (x
, 0))
5744 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5745 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5746 <= HOST_BITS_PER_WIDE_INT
)
5747 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5748 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5749 return SUBREG_REG (XEXP (x
, 0));
5753 /* If we reach here, we want to return a pair of shifts. The inner
5754 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5755 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5756 logical depending on the value of UNSIGNEDP.
5758 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5759 converted into an AND of a shift.
5761 We must check for the case where the left shift would have a negative
5762 count. This can happen in a case like (x >> 31) & 255 on machines
5763 that can't shift by a constant. On those machines, we would first
5764 combine the shift with the AND to produce a variable-position
5765 extraction. Then the constant of 31 would be substituted in to produce
5766 a such a position. */
5768 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5769 if (modewidth
+ len
>= pos
)
5770 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5772 simplify_shift_const (NULL_RTX
, ASHIFT
,
5775 modewidth
- pos
- len
),
5778 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5779 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5780 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5783 ((HOST_WIDE_INT
) 1 << len
) - 1);
5785 /* Any other cases we can't handle. */
5788 /* If we couldn't do this for some reason, return the original
5790 if (GET_CODE (tem
) == CLOBBER
)
5796 /* X is a SET which contains an assignment of one object into
5797 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5798 or certain SUBREGS). If possible, convert it into a series of
5801 We half-heartedly support variable positions, but do not at all
5802 support variable lengths. */
5805 expand_field_assignment (rtx x
)
5808 rtx pos
; /* Always counts from low bit. */
5811 enum machine_mode compute_mode
;
5813 /* Loop until we find something we can't simplify. */
5816 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5817 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5819 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5820 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5821 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5823 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5824 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5826 inner
= XEXP (SET_DEST (x
), 0);
5827 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5828 pos
= XEXP (SET_DEST (x
), 2);
5830 /* If the position is constant and spans the width of INNER,
5831 surround INNER with a USE to indicate this. */
5832 if (GET_CODE (pos
) == CONST_INT
5833 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5834 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5836 if (BITS_BIG_ENDIAN
)
5838 if (GET_CODE (pos
) == CONST_INT
)
5839 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5841 else if (GET_CODE (pos
) == MINUS
5842 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5843 && (INTVAL (XEXP (pos
, 1))
5844 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5845 /* If position is ADJUST - X, new position is X. */
5846 pos
= XEXP (pos
, 0);
5848 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5849 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5855 /* A SUBREG between two modes that occupy the same numbers of words
5856 can be done by moving the SUBREG to the source. */
5857 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5858 /* We need SUBREGs to compute nonzero_bits properly. */
5859 && nonzero_sign_valid
5860 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5861 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5862 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5863 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5865 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5867 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5874 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5875 inner
= SUBREG_REG (inner
);
5877 compute_mode
= GET_MODE (inner
);
5879 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5880 if (! SCALAR_INT_MODE_P (compute_mode
))
5882 enum machine_mode imode
;
5884 /* Don't do anything for vector or complex integral types. */
5885 if (! FLOAT_MODE_P (compute_mode
))
5888 /* Try to find an integral mode to pun with. */
5889 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5890 if (imode
== BLKmode
)
5893 compute_mode
= imode
;
5894 inner
= gen_lowpart (imode
, inner
);
5897 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5898 if (len
< HOST_BITS_PER_WIDE_INT
)
5899 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5903 /* Now compute the equivalent expression. Make a copy of INNER
5904 for the SET_DEST in case it is a MEM into which we will substitute;
5905 we don't want shared RTL in that case. */
5907 (VOIDmode
, copy_rtx (inner
),
5908 gen_binary (IOR
, compute_mode
,
5909 gen_binary (AND
, compute_mode
,
5910 simplify_gen_unary (NOT
, compute_mode
,
5916 gen_binary (ASHIFT
, compute_mode
,
5917 gen_binary (AND
, compute_mode
,
5919 (compute_mode
, SET_SRC (x
)),
5927 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5928 it is an RTX that represents a variable starting position; otherwise,
5929 POS is the (constant) starting bit position (counted from the LSB).
5931 INNER may be a USE. This will occur when we started with a bitfield
5932 that went outside the boundary of the object in memory, which is
5933 allowed on most machines. To isolate this case, we produce a USE
5934 whose mode is wide enough and surround the MEM with it. The only
5935 code that understands the USE is this routine. If it is not removed,
5936 it will cause the resulting insn not to match.
5938 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5941 IN_DEST is nonzero if this is a reference in the destination of a
5942 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5943 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5946 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5947 ZERO_EXTRACT should be built even for bits starting at bit 0.
5949 MODE is the desired mode of the result (if IN_DEST == 0).
5951 The result is an RTX for the extraction or NULL_RTX if the target
5955 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5956 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5957 int in_dest
, int in_compare
)
5959 /* This mode describes the size of the storage area
5960 to fetch the overall value from. Within that, we
5961 ignore the POS lowest bits, etc. */
5962 enum machine_mode is_mode
= GET_MODE (inner
);
5963 enum machine_mode inner_mode
;
5964 enum machine_mode wanted_inner_mode
= byte_mode
;
5965 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5966 enum machine_mode pos_mode
= word_mode
;
5967 enum machine_mode extraction_mode
= word_mode
;
5968 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5971 rtx orig_pos_rtx
= pos_rtx
;
5972 HOST_WIDE_INT orig_pos
;
5974 /* Get some information about INNER and get the innermost object. */
5975 if (GET_CODE (inner
) == USE
)
5976 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5977 /* We don't need to adjust the position because we set up the USE
5978 to pretend that it was a full-word object. */
5979 spans_byte
= 1, inner
= XEXP (inner
, 0);
5980 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5982 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5983 consider just the QI as the memory to extract from.
5984 The subreg adds or removes high bits; its mode is
5985 irrelevant to the meaning of this extraction,
5986 since POS and LEN count from the lsb. */
5987 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5988 is_mode
= GET_MODE (SUBREG_REG (inner
));
5989 inner
= SUBREG_REG (inner
);
5991 else if (GET_CODE (inner
) == ASHIFT
5992 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5993 && pos_rtx
== 0 && pos
== 0
5994 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
5996 /* We're extracting the least significant bits of an rtx
5997 (ashift X (const_int C)), where LEN > C. Extract the
5998 least significant (LEN - C) bits of X, giving an rtx
5999 whose mode is MODE, then shift it left C times. */
6000 new = make_extraction (mode
, XEXP (inner
, 0),
6001 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6002 unsignedp
, in_dest
, in_compare
);
6004 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6007 inner_mode
= GET_MODE (inner
);
6009 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6010 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6012 /* See if this can be done without an extraction. We never can if the
6013 width of the field is not the same as that of some integer mode. For
6014 registers, we can only avoid the extraction if the position is at the
6015 low-order bit and this is either not in the destination or we have the
6016 appropriate STRICT_LOW_PART operation available.
6018 For MEM, we can avoid an extract if the field starts on an appropriate
6019 boundary and we can change the mode of the memory reference. However,
6020 we cannot directly access the MEM if we have a USE and the underlying
6021 MEM is not TMODE. This combination means that MEM was being used in a
6022 context where bits outside its mode were being referenced; that is only
6023 valid in bit-field insns. */
6025 if (tmode
!= BLKmode
6026 && ! (spans_byte
&& inner_mode
!= tmode
)
6027 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6028 && GET_CODE (inner
) != MEM
6030 || (GET_CODE (inner
) == REG
6031 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6032 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6034 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6035 : BITS_PER_UNIT
)) == 0
6036 /* We can't do this if we are widening INNER_MODE (it
6037 may not be aligned, for one thing). */
6038 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6039 && (inner_mode
== tmode
6040 || (! mode_dependent_address_p (XEXP (inner
, 0))
6041 && ! MEM_VOLATILE_P (inner
))))))
6043 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6044 field. If the original and current mode are the same, we need not
6045 adjust the offset. Otherwise, we do if bytes big endian.
6047 If INNER is not a MEM, get a piece consisting of just the field
6048 of interest (in this case POS % BITS_PER_WORD must be 0). */
6050 if (GET_CODE (inner
) == MEM
)
6052 HOST_WIDE_INT offset
;
6054 /* POS counts from lsb, but make OFFSET count in memory order. */
6055 if (BYTES_BIG_ENDIAN
)
6056 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6058 offset
= pos
/ BITS_PER_UNIT
;
6060 new = adjust_address_nv (inner
, tmode
, offset
);
6062 else if (GET_CODE (inner
) == REG
)
6064 if (tmode
!= inner_mode
)
6066 /* We can't call gen_lowpart in a DEST since we
6067 always want a SUBREG (see below) and it would sometimes
6068 return a new hard register. */
6071 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6073 if (WORDS_BIG_ENDIAN
6074 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6075 final_word
= ((GET_MODE_SIZE (inner_mode
)
6076 - GET_MODE_SIZE (tmode
))
6077 / UNITS_PER_WORD
) - final_word
;
6079 final_word
*= UNITS_PER_WORD
;
6080 if (BYTES_BIG_ENDIAN
&&
6081 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6082 final_word
+= (GET_MODE_SIZE (inner_mode
)
6083 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6085 /* Avoid creating invalid subregs, for example when
6086 simplifying (x>>32)&255. */
6087 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6090 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6093 new = gen_lowpart (tmode
, inner
);
6099 new = force_to_mode (inner
, tmode
,
6100 len
>= HOST_BITS_PER_WIDE_INT
6101 ? ~(unsigned HOST_WIDE_INT
) 0
6102 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6105 /* If this extraction is going into the destination of a SET,
6106 make a STRICT_LOW_PART unless we made a MEM. */
6109 return (GET_CODE (new) == MEM
? new
6110 : (GET_CODE (new) != SUBREG
6111 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6112 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6117 if (GET_CODE (new) == CONST_INT
)
6118 return gen_int_mode (INTVAL (new), mode
);
6120 /* If we know that no extraneous bits are set, and that the high
6121 bit is not set, convert the extraction to the cheaper of
6122 sign and zero extension, that are equivalent in these cases. */
6123 if (flag_expensive_optimizations
6124 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6125 && ((nonzero_bits (new, tmode
)
6126 & ~(((unsigned HOST_WIDE_INT
)
6127 GET_MODE_MASK (tmode
))
6131 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6132 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6134 /* Prefer ZERO_EXTENSION, since it gives more information to
6136 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6141 /* Otherwise, sign- or zero-extend unless we already are in the
6144 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6148 /* Unless this is a COMPARE or we have a funny memory reference,
6149 don't do anything with zero-extending field extracts starting at
6150 the low-order bit since they are simple AND operations. */
6151 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6152 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6155 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6156 we would be spanning bytes or if the position is not a constant and the
6157 length is not 1. In all other cases, we would only be going outside
6158 our object in cases when an original shift would have been
6160 if (! spans_byte
&& GET_CODE (inner
) == MEM
6161 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6162 || (pos_rtx
!= 0 && len
!= 1)))
6165 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6166 and the mode for the result. */
6167 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6169 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6170 pos_mode
= mode_for_extraction (EP_insv
, 2);
6171 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6174 if (! in_dest
&& unsignedp
6175 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6177 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6178 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6179 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6182 if (! in_dest
&& ! unsignedp
6183 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6185 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6186 pos_mode
= mode_for_extraction (EP_extv
, 3);
6187 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6190 /* Never narrow an object, since that might not be safe. */
6192 if (mode
!= VOIDmode
6193 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6194 extraction_mode
= mode
;
6196 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6197 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6198 pos_mode
= GET_MODE (pos_rtx
);
6200 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6201 if we have to change the mode of memory and cannot, the desired mode is
6203 if (GET_CODE (inner
) != MEM
)
6204 wanted_inner_mode
= wanted_inner_reg_mode
;
6205 else if (inner_mode
!= wanted_inner_mode
6206 && (mode_dependent_address_p (XEXP (inner
, 0))
6207 || MEM_VOLATILE_P (inner
)))
6208 wanted_inner_mode
= extraction_mode
;
6212 if (BITS_BIG_ENDIAN
)
6214 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6215 BITS_BIG_ENDIAN style. If position is constant, compute new
6216 position. Otherwise, build subtraction.
6217 Note that POS is relative to the mode of the original argument.
6218 If it's a MEM we need to recompute POS relative to that.
6219 However, if we're extracting from (or inserting into) a register,
6220 we want to recompute POS relative to wanted_inner_mode. */
6221 int width
= (GET_CODE (inner
) == MEM
6222 ? GET_MODE_BITSIZE (is_mode
)
6223 : GET_MODE_BITSIZE (wanted_inner_mode
));
6226 pos
= width
- len
- pos
;
6229 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6230 /* POS may be less than 0 now, but we check for that below.
6231 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6234 /* If INNER has a wider mode, make it smaller. If this is a constant
6235 extract, try to adjust the byte to point to the byte containing
6237 if (wanted_inner_mode
!= VOIDmode
6238 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6239 && ((GET_CODE (inner
) == MEM
6240 && (inner_mode
== wanted_inner_mode
6241 || (! mode_dependent_address_p (XEXP (inner
, 0))
6242 && ! MEM_VOLATILE_P (inner
))))))
6246 /* The computations below will be correct if the machine is big
6247 endian in both bits and bytes or little endian in bits and bytes.
6248 If it is mixed, we must adjust. */
6250 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6251 adjust OFFSET to compensate. */
6252 if (BYTES_BIG_ENDIAN
6254 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6255 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6257 /* If this is a constant position, we can move to the desired byte. */
6260 offset
+= pos
/ BITS_PER_UNIT
;
6261 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6264 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6266 && is_mode
!= wanted_inner_mode
)
6267 offset
= (GET_MODE_SIZE (is_mode
)
6268 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6270 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6271 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6274 /* If INNER is not memory, we can always get it into the proper mode. If we
6275 are changing its mode, POS must be a constant and smaller than the size
6277 else if (GET_CODE (inner
) != MEM
)
6279 if (GET_MODE (inner
) != wanted_inner_mode
6281 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6284 inner
= force_to_mode (inner
, wanted_inner_mode
,
6286 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6287 ? ~(unsigned HOST_WIDE_INT
) 0
6288 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6293 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6294 have to zero extend. Otherwise, we can just use a SUBREG. */
6296 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6298 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6300 /* If we know that no extraneous bits are set, and that the high
6301 bit is not set, convert extraction to cheaper one - either
6302 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6304 if (flag_expensive_optimizations
6305 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6306 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6307 & ~(((unsigned HOST_WIDE_INT
)
6308 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6312 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6314 /* Prefer ZERO_EXTENSION, since it gives more information to
6316 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6321 else if (pos_rtx
!= 0
6322 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6323 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6325 /* Make POS_RTX unless we already have it and it is correct. If we don't
6326 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6328 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6329 pos_rtx
= orig_pos_rtx
;
6331 else if (pos_rtx
== 0)
6332 pos_rtx
= GEN_INT (pos
);
6334 /* Make the required operation. See if we can use existing rtx. */
6335 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6336 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6338 new = gen_lowpart (mode
, new);
6343 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6344 with any other operations in X. Return X without that shift if so. */
6347 extract_left_shift (rtx x
, int count
)
6349 enum rtx_code code
= GET_CODE (x
);
6350 enum machine_mode mode
= GET_MODE (x
);
6356 /* This is the shift itself. If it is wide enough, we will return
6357 either the value being shifted if the shift count is equal to
6358 COUNT or a shift for the difference. */
6359 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6360 && INTVAL (XEXP (x
, 1)) >= count
)
6361 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6362 INTVAL (XEXP (x
, 1)) - count
);
6366 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6367 return simplify_gen_unary (code
, mode
, tem
, mode
);
6371 case PLUS
: case IOR
: case XOR
: case AND
:
6372 /* If we can safely shift this constant and we find the inner shift,
6373 make a new operation. */
6374 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6375 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6376 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6377 return gen_binary (code
, mode
, tem
,
6378 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6389 /* Look at the expression rooted at X. Look for expressions
6390 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6391 Form these expressions.
6393 Return the new rtx, usually just X.
6395 Also, for machines like the VAX that don't have logical shift insns,
6396 try to convert logical to arithmetic shift operations in cases where
6397 they are equivalent. This undoes the canonicalizations to logical
6398 shifts done elsewhere.
6400 We try, as much as possible, to re-use rtl expressions to save memory.
6402 IN_CODE says what kind of expression we are processing. Normally, it is
6403 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6404 being kludges), it is MEM. When processing the arguments of a comparison
6405 or a COMPARE against zero, it is COMPARE. */
6408 make_compound_operation (rtx x
, enum rtx_code in_code
)
6410 enum rtx_code code
= GET_CODE (x
);
6411 enum machine_mode mode
= GET_MODE (x
);
6412 int mode_width
= GET_MODE_BITSIZE (mode
);
6414 enum rtx_code next_code
;
6420 /* Select the code to be used in recursive calls. Once we are inside an
6421 address, we stay there. If we have a comparison, set to COMPARE,
6422 but once inside, go back to our default of SET. */
6424 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6425 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6426 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6427 : in_code
== COMPARE
? SET
: in_code
);
6429 /* Process depending on the code of this operation. If NEW is set
6430 nonzero, it will be returned. */
6435 /* Convert shifts by constants into multiplications if inside
6437 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6438 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6439 && INTVAL (XEXP (x
, 1)) >= 0)
6441 new = make_compound_operation (XEXP (x
, 0), next_code
);
6442 new = gen_rtx_MULT (mode
, new,
6443 GEN_INT ((HOST_WIDE_INT
) 1
6444 << INTVAL (XEXP (x
, 1))));
6449 /* If the second operand is not a constant, we can't do anything
6451 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6454 /* If the constant is a power of two minus one and the first operand
6455 is a logical right shift, make an extraction. */
6456 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6457 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6459 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6460 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6461 0, in_code
== COMPARE
);
6464 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6465 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6466 && subreg_lowpart_p (XEXP (x
, 0))
6467 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6468 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6470 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6472 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6473 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6474 0, in_code
== COMPARE
);
6476 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6477 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6478 || GET_CODE (XEXP (x
, 0)) == IOR
)
6479 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6480 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6481 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6483 /* Apply the distributive law, and then try to make extractions. */
6484 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6485 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6487 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6489 new = make_compound_operation (new, in_code
);
6492 /* If we are have (and (rotate X C) M) and C is larger than the number
6493 of bits in M, this is an extraction. */
6495 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6496 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6497 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6498 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6500 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6501 new = make_extraction (mode
, new,
6502 (GET_MODE_BITSIZE (mode
)
6503 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6504 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6507 /* On machines without logical shifts, if the operand of the AND is
6508 a logical shift and our mask turns off all the propagated sign
6509 bits, we can replace the logical shift with an arithmetic shift. */
6510 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6511 && !have_insn_for (LSHIFTRT
, mode
)
6512 && have_insn_for (ASHIFTRT
, mode
)
6513 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6514 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6515 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6516 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6518 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6520 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6521 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6523 gen_rtx_ASHIFTRT (mode
,
6524 make_compound_operation
6525 (XEXP (XEXP (x
, 0), 0), next_code
),
6526 XEXP (XEXP (x
, 0), 1)));
6529 /* If the constant is one less than a power of two, this might be
6530 representable by an extraction even if no shift is present.
6531 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6532 we are in a COMPARE. */
6533 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6534 new = make_extraction (mode
,
6535 make_compound_operation (XEXP (x
, 0),
6537 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6539 /* If we are in a comparison and this is an AND with a power of two,
6540 convert this into the appropriate bit extract. */
6541 else if (in_code
== COMPARE
6542 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6543 new = make_extraction (mode
,
6544 make_compound_operation (XEXP (x
, 0),
6546 i
, NULL_RTX
, 1, 1, 0, 1);
6551 /* If the sign bit is known to be zero, replace this with an
6552 arithmetic shift. */
6553 if (have_insn_for (ASHIFTRT
, mode
)
6554 && ! have_insn_for (LSHIFTRT
, mode
)
6555 && mode_width
<= HOST_BITS_PER_WIDE_INT
6556 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6558 new = gen_rtx_ASHIFTRT (mode
,
6559 make_compound_operation (XEXP (x
, 0),
6565 /* ... fall through ... */
6571 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6572 this is a SIGN_EXTRACT. */
6573 if (GET_CODE (rhs
) == CONST_INT
6574 && GET_CODE (lhs
) == ASHIFT
6575 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6576 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6578 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6579 new = make_extraction (mode
, new,
6580 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6581 NULL_RTX
, mode_width
- INTVAL (rhs
),
6582 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6586 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6587 If so, try to merge the shifts into a SIGN_EXTEND. We could
6588 also do this for some cases of SIGN_EXTRACT, but it doesn't
6589 seem worth the effort; the case checked for occurs on Alpha. */
6591 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6592 && ! (GET_CODE (lhs
) == SUBREG
6593 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6594 && GET_CODE (rhs
) == CONST_INT
6595 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6596 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6597 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6598 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6599 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6604 /* Call ourselves recursively on the inner expression. If we are
6605 narrowing the object and it has a different RTL code from
6606 what it originally did, do this SUBREG as a force_to_mode. */
6608 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6609 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6610 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6611 && subreg_lowpart_p (x
))
6613 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6616 /* If we have something other than a SUBREG, we might have
6617 done an expansion, so rerun ourselves. */
6618 if (GET_CODE (newer
) != SUBREG
)
6619 newer
= make_compound_operation (newer
, in_code
);
6624 /* If this is a paradoxical subreg, and the new code is a sign or
6625 zero extension, omit the subreg and widen the extension. If it
6626 is a regular subreg, we can still get rid of the subreg by not
6627 widening so much, or in fact removing the extension entirely. */
6628 if ((GET_CODE (tem
) == SIGN_EXTEND
6629 || GET_CODE (tem
) == ZERO_EXTEND
)
6630 && subreg_lowpart_p (x
))
6632 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6633 || (GET_MODE_SIZE (mode
) >
6634 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6636 if (! SCALAR_INT_MODE_P (mode
))
6638 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6641 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6652 x
= gen_lowpart (mode
, new);
6653 code
= GET_CODE (x
);
6656 /* Now recursively process each operand of this operation. */
6657 fmt
= GET_RTX_FORMAT (code
);
6658 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6661 new = make_compound_operation (XEXP (x
, i
), next_code
);
6662 SUBST (XEXP (x
, i
), new);
6668 /* Given M see if it is a value that would select a field of bits
6669 within an item, but not the entire word. Return -1 if not.
6670 Otherwise, return the starting position of the field, where 0 is the
6673 *PLEN is set to the length of the field. */
6676 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6678 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6679 int pos
= exact_log2 (m
& -m
);
6685 /* Now shift off the low-order zero bits and see if we have a power of
6687 len
= exact_log2 ((m
>> pos
) + 1);
6696 /* See if X can be simplified knowing that we will only refer to it in
6697 MODE and will only refer to those bits that are nonzero in MASK.
6698 If other bits are being computed or if masking operations are done
6699 that select a superset of the bits in MASK, they can sometimes be
6702 Return a possibly simplified expression, but always convert X to
6703 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6705 Also, if REG is nonzero and X is a register equal in value to REG,
6708 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6709 are all off in X. This is used when X will be complemented, by either
6710 NOT, NEG, or XOR. */
6713 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6714 rtx reg
, int just_select
)
6716 enum rtx_code code
= GET_CODE (x
);
6717 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6718 enum machine_mode op_mode
;
6719 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6722 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6723 code below will do the wrong thing since the mode of such an
6724 expression is VOIDmode.
6726 Also do nothing if X is a CLOBBER; this can happen if X was
6727 the return value from a call to gen_lowpart. */
6728 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6731 /* We want to perform the operation is its present mode unless we know
6732 that the operation is valid in MODE, in which case we do the operation
6734 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6735 && have_insn_for (code
, mode
))
6736 ? mode
: GET_MODE (x
));
6738 /* It is not valid to do a right-shift in a narrower mode
6739 than the one it came in with. */
6740 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6741 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6742 op_mode
= GET_MODE (x
);
6744 /* Truncate MASK to fit OP_MODE. */
6746 mask
&= GET_MODE_MASK (op_mode
);
6748 /* When we have an arithmetic operation, or a shift whose count we
6749 do not know, we need to assume that all bits up to the highest-order
6750 bit in MASK will be needed. This is how we form such a mask. */
6751 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6752 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6754 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6757 /* Determine what bits of X are guaranteed to be (non)zero. */
6758 nonzero
= nonzero_bits (x
, mode
);
6760 /* If none of the bits in X are needed, return a zero. */
6761 if (! just_select
&& (nonzero
& mask
) == 0)
6764 /* If X is a CONST_INT, return a new one. Do this here since the
6765 test below will fail. */
6766 if (GET_CODE (x
) == CONST_INT
)
6768 if (SCALAR_INT_MODE_P (mode
))
6769 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6772 x
= GEN_INT (INTVAL (x
) & mask
);
6773 return gen_lowpart_common (mode
, x
);
6777 /* If X is narrower than MODE and we want all the bits in X's mode, just
6778 get X in the proper mode. */
6779 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6780 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6781 return gen_lowpart (mode
, x
);
6783 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6784 MASK are already known to be zero in X, we need not do anything. */
6785 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6791 /* If X is a (clobber (const_int)), return it since we know we are
6792 generating something that won't match. */
6796 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6797 spanned the boundary of the MEM. If we are now masking so it is
6798 within that boundary, we don't need the USE any more. */
6799 if (! BITS_BIG_ENDIAN
6800 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6801 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6808 x
= expand_compound_operation (x
);
6809 if (GET_CODE (x
) != code
)
6810 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6814 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6815 || rtx_equal_p (reg
, get_last_value (x
))))
6820 if (subreg_lowpart_p (x
)
6821 /* We can ignore the effect of this SUBREG if it narrows the mode or
6822 if the constant masks to zero all the bits the mode doesn't
6824 && ((GET_MODE_SIZE (GET_MODE (x
))
6825 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6827 & GET_MODE_MASK (GET_MODE (x
))
6828 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6829 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6833 /* If this is an AND with a constant, convert it into an AND
6834 whose constant is the AND of that constant with MASK. If it
6835 remains an AND of MASK, delete it since it is redundant. */
6837 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6839 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6840 mask
& INTVAL (XEXP (x
, 1)));
6842 /* If X is still an AND, see if it is an AND with a mask that
6843 is just some low-order bits. If so, and it is MASK, we don't
6846 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6847 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6851 /* If it remains an AND, try making another AND with the bits
6852 in the mode mask that aren't in MASK turned on. If the
6853 constant in the AND is wide enough, this might make a
6854 cheaper constant. */
6856 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6857 && GET_MODE_MASK (GET_MODE (x
)) != mask
6858 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6860 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6861 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6862 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6865 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6866 number, sign extend it. */
6867 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6868 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6869 cval
|= (HOST_WIDE_INT
) -1 << width
;
6871 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6872 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6882 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6883 low-order bits (as in an alignment operation) and FOO is already
6884 aligned to that boundary, mask C1 to that boundary as well.
6885 This may eliminate that PLUS and, later, the AND. */
6888 unsigned int width
= GET_MODE_BITSIZE (mode
);
6889 unsigned HOST_WIDE_INT smask
= mask
;
6891 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6892 number, sign extend it. */
6894 if (width
< HOST_BITS_PER_WIDE_INT
6895 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6896 smask
|= (HOST_WIDE_INT
) -1 << width
;
6898 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6899 && exact_log2 (- smask
) >= 0
6900 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6901 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6902 return force_to_mode (plus_constant (XEXP (x
, 0),
6903 (INTVAL (XEXP (x
, 1)) & smask
)),
6904 mode
, smask
, reg
, next_select
);
6907 /* ... fall through ... */
6910 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6911 most significant bit in MASK since carries from those bits will
6912 affect the bits we are interested in. */
6917 /* If X is (minus C Y) where C's least set bit is larger than any bit
6918 in the mask, then we may replace with (neg Y). */
6919 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6920 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6921 & -INTVAL (XEXP (x
, 0))))
6924 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6926 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6929 /* Similarly, if C contains every bit in the fuller_mask, then we may
6930 replace with (not Y). */
6931 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6932 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6933 == INTVAL (XEXP (x
, 0))))
6935 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6936 XEXP (x
, 1), GET_MODE (x
));
6937 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6945 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6946 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6947 operation which may be a bitfield extraction. Ensure that the
6948 constant we form is not wider than the mode of X. */
6950 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6951 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6952 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6953 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6954 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6955 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6956 + floor_log2 (INTVAL (XEXP (x
, 1))))
6957 < GET_MODE_BITSIZE (GET_MODE (x
)))
6958 && (INTVAL (XEXP (x
, 1))
6959 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6961 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6962 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6963 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6964 XEXP (XEXP (x
, 0), 0), temp
);
6965 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6966 XEXP (XEXP (x
, 0), 1));
6967 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6971 /* For most binary operations, just propagate into the operation and
6972 change the mode if we have an operation of that mode. */
6974 op0
= gen_lowpart (op_mode
,
6975 force_to_mode (XEXP (x
, 0), mode
, mask
,
6977 op1
= gen_lowpart (op_mode
,
6978 force_to_mode (XEXP (x
, 1), mode
, mask
,
6981 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6982 x
= gen_binary (code
, op_mode
, op0
, op1
);
6986 /* For left shifts, do the same, but just for the first operand.
6987 However, we cannot do anything with shifts where we cannot
6988 guarantee that the counts are smaller than the size of the mode
6989 because such a count will have a different meaning in a
6992 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6993 && INTVAL (XEXP (x
, 1)) >= 0
6994 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6995 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6996 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6997 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7000 /* If the shift count is a constant and we can do arithmetic in
7001 the mode of the shift, refine which bits we need. Otherwise, use the
7002 conservative form of the mask. */
7003 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7004 && INTVAL (XEXP (x
, 1)) >= 0
7005 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7006 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7007 mask
>>= INTVAL (XEXP (x
, 1));
7011 op0
= gen_lowpart (op_mode
,
7012 force_to_mode (XEXP (x
, 0), op_mode
,
7013 mask
, reg
, next_select
));
7015 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7016 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7020 /* Here we can only do something if the shift count is a constant,
7021 this shift constant is valid for the host, and we can do arithmetic
7024 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7025 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7026 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7028 rtx inner
= XEXP (x
, 0);
7029 unsigned HOST_WIDE_INT inner_mask
;
7031 /* Select the mask of the bits we need for the shift operand. */
7032 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7034 /* We can only change the mode of the shift if we can do arithmetic
7035 in the mode of the shift and INNER_MASK is no wider than the
7036 width of OP_MODE. */
7037 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7038 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7039 op_mode
= GET_MODE (x
);
7041 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7043 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7044 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7047 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7048 shift and AND produces only copies of the sign bit (C2 is one less
7049 than a power of two), we can do this with just a shift. */
7051 if (GET_CODE (x
) == LSHIFTRT
7052 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7053 /* The shift puts one of the sign bit copies in the least significant
7055 && ((INTVAL (XEXP (x
, 1))
7056 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7057 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7058 && exact_log2 (mask
+ 1) >= 0
7059 /* Number of bits left after the shift must be more than the mask
7061 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7062 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7063 /* Must be more sign bit copies than the mask needs. */
7064 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7065 >= exact_log2 (mask
+ 1)))
7066 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7067 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7068 - exact_log2 (mask
+ 1)));
7073 /* If we are just looking for the sign bit, we don't need this shift at
7074 all, even if it has a variable count. */
7075 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7076 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7077 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7078 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7080 /* If this is a shift by a constant, get a mask that contains those bits
7081 that are not copies of the sign bit. We then have two cases: If
7082 MASK only includes those bits, this can be a logical shift, which may
7083 allow simplifications. If MASK is a single-bit field not within
7084 those bits, we are requesting a copy of the sign bit and hence can
7085 shift the sign bit to the appropriate location. */
7087 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7088 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7092 /* If the considered data is wider than HOST_WIDE_INT, we can't
7093 represent a mask for all its bits in a single scalar.
7094 But we only care about the lower bits, so calculate these. */
7096 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7098 nonzero
= ~(HOST_WIDE_INT
) 0;
7100 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7101 is the number of bits a full-width mask would have set.
7102 We need only shift if these are fewer than nonzero can
7103 hold. If not, we must keep all bits set in nonzero. */
7105 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7106 < HOST_BITS_PER_WIDE_INT
)
7107 nonzero
>>= INTVAL (XEXP (x
, 1))
7108 + HOST_BITS_PER_WIDE_INT
7109 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7113 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7114 nonzero
>>= INTVAL (XEXP (x
, 1));
7117 if ((mask
& ~nonzero
) == 0
7118 || (i
= exact_log2 (mask
)) >= 0)
7120 x
= simplify_shift_const
7121 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7122 i
< 0 ? INTVAL (XEXP (x
, 1))
7123 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7125 if (GET_CODE (x
) != ASHIFTRT
)
7126 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7130 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7131 even if the shift count isn't a constant. */
7133 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7137 /* If this is a zero- or sign-extension operation that just affects bits
7138 we don't care about, remove it. Be sure the call above returned
7139 something that is still a shift. */
7141 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7142 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7143 && INTVAL (XEXP (x
, 1)) >= 0
7144 && (INTVAL (XEXP (x
, 1))
7145 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7146 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7147 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7148 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7155 /* If the shift count is constant and we can do computations
7156 in the mode of X, compute where the bits we care about are.
7157 Otherwise, we can't do anything. Don't change the mode of
7158 the shift or propagate MODE into the shift, though. */
7159 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7160 && INTVAL (XEXP (x
, 1)) >= 0)
7162 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7163 GET_MODE (x
), GEN_INT (mask
),
7165 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7167 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7168 INTVAL (temp
), reg
, next_select
));
7173 /* If we just want the low-order bit, the NEG isn't needed since it
7174 won't change the low-order bit. */
7176 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7178 /* We need any bits less significant than the most significant bit in
7179 MASK since carries from those bits will affect the bits we are
7185 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7186 same as the XOR case above. Ensure that the constant we form is not
7187 wider than the mode of X. */
7189 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7190 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7191 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7192 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7193 < GET_MODE_BITSIZE (GET_MODE (x
)))
7194 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7196 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7198 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7199 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7201 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7204 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7205 use the full mask inside the NOT. */
7209 op0
= gen_lowpart (op_mode
,
7210 force_to_mode (XEXP (x
, 0), mode
, mask
,
7212 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7213 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7217 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7218 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7219 which is equal to STORE_FLAG_VALUE. */
7220 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7221 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7222 && (nonzero_bits (XEXP (x
, 0), mode
)
7223 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7224 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7229 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7230 written in a narrower mode. We play it safe and do not do so. */
7233 gen_lowpart (GET_MODE (x
),
7234 force_to_mode (XEXP (x
, 1), mode
,
7235 mask
, reg
, next_select
)));
7237 gen_lowpart (GET_MODE (x
),
7238 force_to_mode (XEXP (x
, 2), mode
,
7239 mask
, reg
, next_select
)));
7246 /* Ensure we return a value of the proper mode. */
7247 return gen_lowpart (mode
, x
);
7250 /* Return nonzero if X is an expression that has one of two values depending on
7251 whether some other value is zero or nonzero. In that case, we return the
7252 value that is being tested, *PTRUE is set to the value if the rtx being
7253 returned has a nonzero value, and *PFALSE is set to the other alternative.
7255 If we return zero, we set *PTRUE and *PFALSE to X. */
7258 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7260 enum machine_mode mode
= GET_MODE (x
);
7261 enum rtx_code code
= GET_CODE (x
);
7262 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7263 unsigned HOST_WIDE_INT nz
;
7265 /* If we are comparing a value against zero, we are done. */
7266 if ((code
== NE
|| code
== EQ
)
7267 && XEXP (x
, 1) == const0_rtx
)
7269 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7270 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7274 /* If this is a unary operation whose operand has one of two values, apply
7275 our opcode to compute those values. */
7276 else if (GET_RTX_CLASS (code
) == '1'
7277 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7279 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7280 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7281 GET_MODE (XEXP (x
, 0)));
7285 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7286 make can't possibly match and would suppress other optimizations. */
7287 else if (code
== COMPARE
)
7290 /* If this is a binary operation, see if either side has only one of two
7291 values. If either one does or if both do and they are conditional on
7292 the same value, compute the new true and false values. */
7293 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7294 || GET_RTX_CLASS (code
) == '<')
7296 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7297 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7299 if ((cond0
!= 0 || cond1
!= 0)
7300 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7302 /* If if_then_else_cond returned zero, then true/false are the
7303 same rtl. We must copy one of them to prevent invalid rtl
7306 true0
= copy_rtx (true0
);
7307 else if (cond1
== 0)
7308 true1
= copy_rtx (true1
);
7310 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7311 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7312 return cond0
? cond0
: cond1
;
7315 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7316 operands is zero when the other is nonzero, and vice-versa,
7317 and STORE_FLAG_VALUE is 1 or -1. */
7319 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7320 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7322 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7324 rtx op0
= XEXP (XEXP (x
, 0), 1);
7325 rtx op1
= XEXP (XEXP (x
, 1), 1);
7327 cond0
= XEXP (XEXP (x
, 0), 0);
7328 cond1
= XEXP (XEXP (x
, 1), 0);
7330 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7331 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7332 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7333 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7334 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7335 || ((swap_condition (GET_CODE (cond0
))
7336 == combine_reversed_comparison_code (cond1
))
7337 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7338 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7339 && ! side_effects_p (x
))
7341 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7342 *pfalse
= gen_binary (MULT
, mode
,
7344 ? simplify_gen_unary (NEG
, mode
, op1
,
7352 /* Similarly for MULT, AND and UMIN, except that for these the result
7354 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7355 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7356 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7358 cond0
= XEXP (XEXP (x
, 0), 0);
7359 cond1
= XEXP (XEXP (x
, 1), 0);
7361 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7362 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7363 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7364 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7365 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7366 || ((swap_condition (GET_CODE (cond0
))
7367 == combine_reversed_comparison_code (cond1
))
7368 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7369 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7370 && ! side_effects_p (x
))
7372 *ptrue
= *pfalse
= const0_rtx
;
7378 else if (code
== IF_THEN_ELSE
)
7380 /* If we have IF_THEN_ELSE already, extract the condition and
7381 canonicalize it if it is NE or EQ. */
7382 cond0
= XEXP (x
, 0);
7383 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7384 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7385 return XEXP (cond0
, 0);
7386 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7388 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7389 return XEXP (cond0
, 0);
7395 /* If X is a SUBREG, we can narrow both the true and false values
7396 if the inner expression, if there is a condition. */
7397 else if (code
== SUBREG
7398 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7401 *ptrue
= simplify_gen_subreg (mode
, true0
,
7402 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7403 *pfalse
= simplify_gen_subreg (mode
, false0
,
7404 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7409 /* If X is a constant, this isn't special and will cause confusions
7410 if we treat it as such. Likewise if it is equivalent to a constant. */
7411 else if (CONSTANT_P (x
)
7412 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7415 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7416 will be least confusing to the rest of the compiler. */
7417 else if (mode
== BImode
)
7419 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7423 /* If X is known to be either 0 or -1, those are the true and
7424 false values when testing X. */
7425 else if (x
== constm1_rtx
|| x
== const0_rtx
7426 || (mode
!= VOIDmode
7427 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7429 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7433 /* Likewise for 0 or a single bit. */
7434 else if (SCALAR_INT_MODE_P (mode
)
7435 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7436 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7438 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7442 /* Otherwise fail; show no condition with true and false values the same. */
7443 *ptrue
= *pfalse
= x
;
7447 /* Return the value of expression X given the fact that condition COND
7448 is known to be true when applied to REG as its first operand and VAL
7449 as its second. X is known to not be shared and so can be modified in
7452 We only handle the simplest cases, and specifically those cases that
7453 arise with IF_THEN_ELSE expressions. */
7456 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7458 enum rtx_code code
= GET_CODE (x
);
7463 if (side_effects_p (x
))
7466 /* If either operand of the condition is a floating point value,
7467 then we have to avoid collapsing an EQ comparison. */
7469 && rtx_equal_p (x
, reg
)
7470 && ! FLOAT_MODE_P (GET_MODE (x
))
7471 && ! FLOAT_MODE_P (GET_MODE (val
)))
7474 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7477 /* If X is (abs REG) and we know something about REG's relationship
7478 with zero, we may be able to simplify this. */
7480 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7483 case GE
: case GT
: case EQ
:
7486 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7488 GET_MODE (XEXP (x
, 0)));
7493 /* The only other cases we handle are MIN, MAX, and comparisons if the
7494 operands are the same as REG and VAL. */
7496 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7498 if (rtx_equal_p (XEXP (x
, 0), val
))
7499 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7501 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7503 if (GET_RTX_CLASS (code
) == '<')
7505 if (comparison_dominates_p (cond
, code
))
7506 return const_true_rtx
;
7508 code
= combine_reversed_comparison_code (x
);
7510 && comparison_dominates_p (cond
, code
))
7515 else if (code
== SMAX
|| code
== SMIN
7516 || code
== UMIN
|| code
== UMAX
)
7518 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7520 /* Do not reverse the condition when it is NE or EQ.
7521 This is because we cannot conclude anything about
7522 the value of 'SMAX (x, y)' when x is not equal to y,
7523 but we can when x equals y. */
7524 if ((code
== SMAX
|| code
== UMAX
)
7525 && ! (cond
== EQ
|| cond
== NE
))
7526 cond
= reverse_condition (cond
);
7531 return unsignedp
? x
: XEXP (x
, 1);
7533 return unsignedp
? x
: XEXP (x
, 0);
7535 return unsignedp
? XEXP (x
, 1) : x
;
7537 return unsignedp
? XEXP (x
, 0) : x
;
7544 else if (code
== SUBREG
)
7546 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7547 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7549 if (SUBREG_REG (x
) != r
)
7551 /* We must simplify subreg here, before we lose track of the
7552 original inner_mode. */
7553 new = simplify_subreg (GET_MODE (x
), r
,
7554 inner_mode
, SUBREG_BYTE (x
));
7558 SUBST (SUBREG_REG (x
), r
);
7563 /* We don't have to handle SIGN_EXTEND here, because even in the
7564 case of replacing something with a modeless CONST_INT, a
7565 CONST_INT is already (supposed to be) a valid sign extension for
7566 its narrower mode, which implies it's already properly
7567 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7568 story is different. */
7569 else if (code
== ZERO_EXTEND
)
7571 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7572 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7574 if (XEXP (x
, 0) != r
)
7576 /* We must simplify the zero_extend here, before we lose
7577 track of the original inner_mode. */
7578 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7583 SUBST (XEXP (x
, 0), r
);
7589 fmt
= GET_RTX_FORMAT (code
);
7590 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7593 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7594 else if (fmt
[i
] == 'E')
7595 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7596 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7603 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7604 assignment as a field assignment. */
7607 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7609 if (x
== y
|| rtx_equal_p (x
, y
))
7612 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7615 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7616 Note that all SUBREGs of MEM are paradoxical; otherwise they
7617 would have been rewritten. */
7618 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7619 && GET_CODE (SUBREG_REG (y
)) == MEM
7620 && rtx_equal_p (SUBREG_REG (y
),
7621 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7624 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7625 && GET_CODE (SUBREG_REG (x
)) == MEM
7626 && rtx_equal_p (SUBREG_REG (x
),
7627 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7630 /* We used to see if get_last_value of X and Y were the same but that's
7631 not correct. In one direction, we'll cause the assignment to have
7632 the wrong destination and in the case, we'll import a register into this
7633 insn that might have already have been dead. So fail if none of the
7634 above cases are true. */
7638 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7639 Return that assignment if so.
7641 We only handle the most common cases. */
7644 make_field_assignment (rtx x
)
7646 rtx dest
= SET_DEST (x
);
7647 rtx src
= SET_SRC (x
);
7652 unsigned HOST_WIDE_INT len
;
7654 enum machine_mode mode
;
7656 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7657 a clear of a one-bit field. We will have changed it to
7658 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7661 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7662 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7663 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7664 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7666 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7669 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7673 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7674 && subreg_lowpart_p (XEXP (src
, 0))
7675 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7676 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7677 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7678 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7679 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7680 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7682 assign
= make_extraction (VOIDmode
, dest
, 0,
7683 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7686 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7690 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7692 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7693 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7694 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7696 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7699 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7703 /* The other case we handle is assignments into a constant-position
7704 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7705 a mask that has all one bits except for a group of zero bits and
7706 OTHER is known to have zeros where C1 has ones, this is such an
7707 assignment. Compute the position and length from C1. Shift OTHER
7708 to the appropriate position, force it to the required mode, and
7709 make the extraction. Check for the AND in both operands. */
7711 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7714 rhs
= expand_compound_operation (XEXP (src
, 0));
7715 lhs
= expand_compound_operation (XEXP (src
, 1));
7717 if (GET_CODE (rhs
) == AND
7718 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7719 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7720 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7721 else if (GET_CODE (lhs
) == AND
7722 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7723 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7724 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7728 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7729 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7730 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7731 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7734 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7738 /* The mode to use for the source is the mode of the assignment, or of
7739 what is inside a possible STRICT_LOW_PART. */
7740 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7741 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7743 /* Shift OTHER right POS places and make it the source, restricting it
7744 to the proper length and mode. */
7746 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7747 GET_MODE (src
), other
, pos
),
7749 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7750 ? ~(unsigned HOST_WIDE_INT
) 0
7751 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7754 /* If SRC is masked by an AND that does not make a difference in
7755 the value being stored, strip it. */
7756 if (GET_CODE (assign
) == ZERO_EXTRACT
7757 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7758 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7759 && GET_CODE (src
) == AND
7760 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7761 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7762 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7763 src
= XEXP (src
, 0);
7765 return gen_rtx_SET (VOIDmode
, assign
, src
);
7768 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7772 apply_distributive_law (rtx x
)
7774 enum rtx_code code
= GET_CODE (x
);
7775 enum rtx_code inner_code
;
7776 rtx lhs
, rhs
, other
;
7779 /* Distributivity is not true for floating point as it can change the
7780 value. So we don't do it unless -funsafe-math-optimizations. */
7781 if (FLOAT_MODE_P (GET_MODE (x
))
7782 && ! flag_unsafe_math_optimizations
)
7785 /* The outer operation can only be one of the following: */
7786 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7787 && code
!= PLUS
&& code
!= MINUS
)
7793 /* If either operand is a primitive we can't do anything, so get out
7795 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7796 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7799 lhs
= expand_compound_operation (lhs
);
7800 rhs
= expand_compound_operation (rhs
);
7801 inner_code
= GET_CODE (lhs
);
7802 if (inner_code
!= GET_CODE (rhs
))
7805 /* See if the inner and outer operations distribute. */
7812 /* These all distribute except over PLUS. */
7813 if (code
== PLUS
|| code
== MINUS
)
7818 if (code
!= PLUS
&& code
!= MINUS
)
7823 /* This is also a multiply, so it distributes over everything. */
7827 /* Non-paradoxical SUBREGs distributes over all operations, provided
7828 the inner modes and byte offsets are the same, this is an extraction
7829 of a low-order part, we don't convert an fp operation to int or
7830 vice versa, and we would not be converting a single-word
7831 operation into a multi-word operation. The latter test is not
7832 required, but it prevents generating unneeded multi-word operations.
7833 Some of the previous tests are redundant given the latter test, but
7834 are retained because they are required for correctness.
7836 We produce the result slightly differently in this case. */
7838 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7839 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7840 || ! subreg_lowpart_p (lhs
)
7841 || (GET_MODE_CLASS (GET_MODE (lhs
))
7842 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7843 || (GET_MODE_SIZE (GET_MODE (lhs
))
7844 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7845 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7848 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7849 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7850 return gen_lowpart (GET_MODE (x
), tem
);
7856 /* Set LHS and RHS to the inner operands (A and B in the example
7857 above) and set OTHER to the common operand (C in the example).
7858 These is only one way to do this unless the inner operation is
7860 if (GET_RTX_CLASS (inner_code
) == 'c'
7861 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7862 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7863 else if (GET_RTX_CLASS (inner_code
) == 'c'
7864 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7865 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7866 else if (GET_RTX_CLASS (inner_code
) == 'c'
7867 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7868 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7869 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7870 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7874 /* Form the new inner operation, seeing if it simplifies first. */
7875 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7877 /* There is one exception to the general way of distributing:
7878 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7879 if (code
== XOR
&& inner_code
== IOR
)
7882 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7885 /* We may be able to continuing distributing the result, so call
7886 ourselves recursively on the inner operation before forming the
7887 outer operation, which we return. */
7888 return gen_binary (inner_code
, GET_MODE (x
),
7889 apply_distributive_law (tem
), other
);
7892 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7895 Return an equivalent form, if different from X. Otherwise, return X. If
7896 X is zero, we are to always construct the equivalent form. */
7899 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7900 unsigned HOST_WIDE_INT constop
)
7902 unsigned HOST_WIDE_INT nonzero
;
7905 /* Simplify VAROP knowing that we will be only looking at some of the
7908 Note by passing in CONSTOP, we guarantee that the bits not set in
7909 CONSTOP are not significant and will never be examined. We must
7910 ensure that is the case by explicitly masking out those bits
7911 before returning. */
7912 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7914 /* If VAROP is a CLOBBER, we will fail so return it. */
7915 if (GET_CODE (varop
) == CLOBBER
)
7918 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7919 to VAROP and return the new constant. */
7920 if (GET_CODE (varop
) == CONST_INT
)
7921 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7923 /* See what bits may be nonzero in VAROP. Unlike the general case of
7924 a call to nonzero_bits, here we don't care about bits outside
7927 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7929 /* Turn off all bits in the constant that are known to already be zero.
7930 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7931 which is tested below. */
7935 /* If we don't have any bits left, return zero. */
7939 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7940 a power of two, we can replace this with an ASHIFT. */
7941 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7942 && (i
= exact_log2 (constop
)) >= 0)
7943 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7945 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7946 or XOR, then try to apply the distributive law. This may eliminate
7947 operations if either branch can be simplified because of the AND.
7948 It may also make some cases more complex, but those cases probably
7949 won't match a pattern either with or without this. */
7951 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7955 apply_distributive_law
7956 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7957 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7958 XEXP (varop
, 0), constop
),
7959 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7960 XEXP (varop
, 1), constop
))));
7962 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7963 the AND and see if one of the operands simplifies to zero. If so, we
7964 may eliminate it. */
7966 if (GET_CODE (varop
) == PLUS
7967 && exact_log2 (constop
+ 1) >= 0)
7971 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7972 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7973 if (o0
== const0_rtx
)
7975 if (o1
== const0_rtx
)
7979 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7980 if we already had one (just check for the simplest cases). */
7981 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7982 && GET_MODE (XEXP (x
, 0)) == mode
7983 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7984 varop
= XEXP (x
, 0);
7986 varop
= gen_lowpart (mode
, varop
);
7988 /* If we can't make the SUBREG, try to return what we were given. */
7989 if (GET_CODE (varop
) == CLOBBER
)
7990 return x
? x
: varop
;
7992 /* If we are only masking insignificant bits, return VAROP. */
7993 if (constop
== nonzero
)
7997 /* Otherwise, return an AND. */
7998 constop
= trunc_int_for_mode (constop
, mode
);
7999 /* See how much, if any, of X we can use. */
8000 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8001 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8005 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8006 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8007 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8009 SUBST (XEXP (x
, 0), varop
);
8016 #define nonzero_bits_with_known(X, MODE) \
8017 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8019 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8020 It avoids exponential behavior in nonzero_bits1 when X has
8021 identical subexpressions on the first or the second level. */
8023 static unsigned HOST_WIDE_INT
8024 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8025 enum machine_mode known_mode
,
8026 unsigned HOST_WIDE_INT known_ret
)
8028 if (x
== known_x
&& mode
== known_mode
)
8031 /* Try to find identical subexpressions. If found call
8032 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8033 precomputed value for the subexpression as KNOWN_RET. */
8035 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8036 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8038 rtx x0
= XEXP (x
, 0);
8039 rtx x1
= XEXP (x
, 1);
8041 /* Check the first level. */
8043 return nonzero_bits1 (x
, mode
, x0
, mode
,
8044 nonzero_bits_with_known (x0
, mode
));
8046 /* Check the second level. */
8047 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8048 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8049 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8050 return nonzero_bits1 (x
, mode
, x1
, mode
,
8051 nonzero_bits_with_known (x1
, mode
));
8053 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8054 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8055 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8056 return nonzero_bits1 (x
, mode
, x0
, mode
,
8057 nonzero_bits_with_known (x0
, mode
));
8060 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8063 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8064 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8065 is less useful. We can't allow both, because that results in exponential
8066 run time recursion. There is a nullstone testcase that triggered
8067 this. This macro avoids accidental uses of num_sign_bit_copies. */
8068 #define cached_num_sign_bit_copies()
8070 /* Given an expression, X, compute which bits in X can be nonzero.
8071 We don't care about bits outside of those defined in MODE.
8073 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8074 a shift, AND, or zero_extract, we can do better. */
8076 static unsigned HOST_WIDE_INT
8077 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8078 enum machine_mode known_mode
,
8079 unsigned HOST_WIDE_INT known_ret
)
8081 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8082 unsigned HOST_WIDE_INT inner_nz
;
8084 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8087 /* For floating-point values, assume all bits are needed. */
8088 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8091 /* If X is wider than MODE, use its mode instead. */
8092 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8094 mode
= GET_MODE (x
);
8095 nonzero
= GET_MODE_MASK (mode
);
8096 mode_width
= GET_MODE_BITSIZE (mode
);
8099 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8100 /* Our only callers in this case look for single bit values. So
8101 just return the mode mask. Those tests will then be false. */
8104 #ifndef WORD_REGISTER_OPERATIONS
8105 /* If MODE is wider than X, but both are a single word for both the host
8106 and target machines, we can compute this from which bits of the
8107 object might be nonzero in its own mode, taking into account the fact
8108 that on many CISC machines, accessing an object in a wider mode
8109 causes the high-order bits to become undefined. So they are
8110 not known to be zero. */
8112 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8113 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8114 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8115 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8117 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8118 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8123 code
= GET_CODE (x
);
8127 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8128 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8129 all the bits above ptr_mode are known to be zero. */
8130 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8132 nonzero
&= GET_MODE_MASK (ptr_mode
);
8135 /* Include declared information about alignment of pointers. */
8136 /* ??? We don't properly preserve REG_POINTER changes across
8137 pointer-to-integer casts, so we can't trust it except for
8138 things that we know must be pointers. See execute/960116-1.c. */
8139 if ((x
== stack_pointer_rtx
8140 || x
== frame_pointer_rtx
8141 || x
== arg_pointer_rtx
)
8142 && REGNO_POINTER_ALIGN (REGNO (x
)))
8144 unsigned HOST_WIDE_INT alignment
8145 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8147 #ifdef PUSH_ROUNDING
8148 /* If PUSH_ROUNDING is defined, it is possible for the
8149 stack to be momentarily aligned only to that amount,
8150 so we pick the least alignment. */
8151 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8152 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8156 nonzero
&= ~(alignment
- 1);
8159 /* If X is a register whose nonzero bits value is current, use it.
8160 Otherwise, if X is a register whose value we can find, use that
8161 value. Otherwise, use the previously-computed global nonzero bits
8162 for this register. */
8164 if (reg_last_set_value
[REGNO (x
)] != 0
8165 && (reg_last_set_mode
[REGNO (x
)] == mode
8166 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8167 && GET_MODE_CLASS (mode
) == MODE_INT
))
8168 && (reg_last_set_label
[REGNO (x
)] == label_tick
8169 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8170 && REG_N_SETS (REGNO (x
)) == 1
8171 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8173 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8174 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8176 tem
= get_last_value (x
);
8180 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8181 /* If X is narrower than MODE and TEM is a non-negative
8182 constant that would appear negative in the mode of X,
8183 sign-extend it for use in reg_nonzero_bits because some
8184 machines (maybe most) will actually do the sign-extension
8185 and this is the conservative approach.
8187 ??? For 2.5, try to tighten up the MD files in this regard
8188 instead of this kludge. */
8190 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8191 && GET_CODE (tem
) == CONST_INT
8193 && 0 != (INTVAL (tem
)
8194 & ((HOST_WIDE_INT
) 1
8195 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8196 tem
= GEN_INT (INTVAL (tem
)
8197 | ((HOST_WIDE_INT
) (-1)
8198 << GET_MODE_BITSIZE (GET_MODE (x
))));
8200 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8202 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8204 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8206 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8207 /* We don't know anything about the upper bits. */
8208 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8209 return nonzero
& mask
;
8215 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8216 /* If X is negative in MODE, sign-extend the value. */
8217 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8218 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8219 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8225 #ifdef LOAD_EXTEND_OP
8226 /* In many, if not most, RISC machines, reading a byte from memory
8227 zeros the rest of the register. Noticing that fact saves a lot
8228 of extra zero-extends. */
8229 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8230 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8235 case UNEQ
: case LTGT
:
8236 case GT
: case GTU
: case UNGT
:
8237 case LT
: case LTU
: case UNLT
:
8238 case GE
: case GEU
: case UNGE
:
8239 case LE
: case LEU
: case UNLE
:
8240 case UNORDERED
: case ORDERED
:
8242 /* If this produces an integer result, we know which bits are set.
8243 Code here used to clear bits outside the mode of X, but that is
8246 if (GET_MODE_CLASS (mode
) == MODE_INT
8247 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8248 nonzero
= STORE_FLAG_VALUE
;
8253 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8254 and num_sign_bit_copies. */
8255 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8256 == GET_MODE_BITSIZE (GET_MODE (x
)))
8260 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8261 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8266 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8267 and num_sign_bit_copies. */
8268 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8269 == GET_MODE_BITSIZE (GET_MODE (x
)))
8275 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8276 & GET_MODE_MASK (mode
));
8280 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8281 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8282 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8286 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8287 Otherwise, show all the bits in the outer mode but not the inner
8289 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8290 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8292 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8294 & (((HOST_WIDE_INT
) 1
8295 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8296 inner_nz
|= (GET_MODE_MASK (mode
)
8297 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8300 nonzero
&= inner_nz
;
8304 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8305 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8309 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8311 unsigned HOST_WIDE_INT nonzero0
=
8312 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8314 /* Don't call nonzero_bits for the second time if it cannot change
8316 if ((nonzero
& nonzero0
) != nonzero
)
8317 nonzero
&= (nonzero0
8318 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8322 case PLUS
: case MINUS
:
8324 case DIV
: case UDIV
:
8325 case MOD
: case UMOD
:
8326 /* We can apply the rules of arithmetic to compute the number of
8327 high- and low-order zero bits of these operations. We start by
8328 computing the width (position of the highest-order nonzero bit)
8329 and the number of low-order zero bits for each value. */
8331 unsigned HOST_WIDE_INT nz0
=
8332 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8333 unsigned HOST_WIDE_INT nz1
=
8334 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8335 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8336 int width0
= floor_log2 (nz0
) + 1;
8337 int width1
= floor_log2 (nz1
) + 1;
8338 int low0
= floor_log2 (nz0
& -nz0
);
8339 int low1
= floor_log2 (nz1
& -nz1
);
8340 HOST_WIDE_INT op0_maybe_minusp
8341 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8342 HOST_WIDE_INT op1_maybe_minusp
8343 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8344 unsigned int result_width
= mode_width
;
8350 result_width
= MAX (width0
, width1
) + 1;
8351 result_low
= MIN (low0
, low1
);
8354 result_low
= MIN (low0
, low1
);
8357 result_width
= width0
+ width1
;
8358 result_low
= low0
+ low1
;
8363 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8364 result_width
= width0
;
8369 result_width
= width0
;
8374 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8375 result_width
= MIN (width0
, width1
);
8376 result_low
= MIN (low0
, low1
);
8381 result_width
= MIN (width0
, width1
);
8382 result_low
= MIN (low0
, low1
);
8388 if (result_width
< mode_width
)
8389 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8392 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8394 #ifdef POINTERS_EXTEND_UNSIGNED
8395 /* If pointers extend unsigned and this is an addition or subtraction
8396 to a pointer in Pmode, all the bits above ptr_mode are known to be
8398 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8399 && (code
== PLUS
|| code
== MINUS
)
8400 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8401 nonzero
&= GET_MODE_MASK (ptr_mode
);
8407 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8408 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8409 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8413 /* If this is a SUBREG formed for a promoted variable that has
8414 been zero-extended, we know that at least the high-order bits
8415 are zero, though others might be too. */
8417 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8418 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8419 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8421 /* If the inner mode is a single word for both the host and target
8422 machines, we can compute this from which bits of the inner
8423 object might be nonzero. */
8424 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8425 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8426 <= HOST_BITS_PER_WIDE_INT
))
8428 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8430 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8431 /* If this is a typical RISC machine, we only have to worry
8432 about the way loads are extended. */
8433 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8435 & (((unsigned HOST_WIDE_INT
) 1
8436 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8438 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8439 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8442 /* On many CISC machines, accessing an object in a wider mode
8443 causes the high-order bits to become undefined. So they are
8444 not known to be zero. */
8445 if (GET_MODE_SIZE (GET_MODE (x
))
8446 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8447 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8448 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8457 /* The nonzero bits are in two classes: any bits within MODE
8458 that aren't in GET_MODE (x) are always significant. The rest of the
8459 nonzero bits are those that are significant in the operand of
8460 the shift when shifted the appropriate number of bits. This
8461 shows that high-order bits are cleared by the right shift and
8462 low-order bits by left shifts. */
8463 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8464 && INTVAL (XEXP (x
, 1)) >= 0
8465 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8467 enum machine_mode inner_mode
= GET_MODE (x
);
8468 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8469 int count
= INTVAL (XEXP (x
, 1));
8470 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8471 unsigned HOST_WIDE_INT op_nonzero
=
8472 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8473 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8474 unsigned HOST_WIDE_INT outer
= 0;
8476 if (mode_width
> width
)
8477 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8479 if (code
== LSHIFTRT
)
8481 else if (code
== ASHIFTRT
)
8485 /* If the sign bit may have been nonzero before the shift, we
8486 need to mark all the places it could have been copied to
8487 by the shift as possibly nonzero. */
8488 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8489 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8491 else if (code
== ASHIFT
)
8494 inner
= ((inner
<< (count
% width
)
8495 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8497 nonzero
&= (outer
| inner
);
8503 /* This is at most the number of bits in the mode. */
8504 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8508 /* If CLZ has a known value at zero, then the nonzero bits are
8509 that value, plus the number of bits in the mode minus one. */
8510 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8511 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8517 /* If CTZ has a known value at zero, then the nonzero bits are
8518 that value, plus the number of bits in the mode minus one. */
8519 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8520 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8530 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8531 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8541 /* See the macro definition above. */
8542 #undef cached_num_sign_bit_copies
8544 #define num_sign_bit_copies_with_known(X, M) \
8545 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8547 /* The function cached_num_sign_bit_copies is a wrapper around
8548 num_sign_bit_copies1. It avoids exponential behavior in
8549 num_sign_bit_copies1 when X has identical subexpressions on the
8550 first or the second level. */
8553 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8554 enum machine_mode known_mode
,
8555 unsigned int known_ret
)
8557 if (x
== known_x
&& mode
== known_mode
)
8560 /* Try to find identical subexpressions. If found call
8561 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8562 the precomputed value for the subexpression as KNOWN_RET. */
8564 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8565 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8567 rtx x0
= XEXP (x
, 0);
8568 rtx x1
= XEXP (x
, 1);
8570 /* Check the first level. */
8573 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8574 num_sign_bit_copies_with_known (x0
, mode
));
8576 /* Check the second level. */
8577 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8578 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8579 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8581 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8582 num_sign_bit_copies_with_known (x1
, mode
));
8584 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8585 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8586 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8588 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8589 num_sign_bit_copies_with_known (x0
, mode
));
8592 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8595 /* Return the number of bits at the high-order end of X that are known to
8596 be equal to the sign bit. X will be used in mode MODE; if MODE is
8597 VOIDmode, X will be used in its own mode. The returned value will always
8598 be between 1 and the number of bits in MODE. */
8601 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8602 enum machine_mode known_mode
,
8603 unsigned int known_ret
)
8605 enum rtx_code code
= GET_CODE (x
);
8606 unsigned int bitwidth
;
8607 int num0
, num1
, result
;
8608 unsigned HOST_WIDE_INT nonzero
;
8611 /* If we weren't given a mode, use the mode of X. If the mode is still
8612 VOIDmode, we don't know anything. Likewise if one of the modes is
8615 if (mode
== VOIDmode
)
8616 mode
= GET_MODE (x
);
8618 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8621 bitwidth
= GET_MODE_BITSIZE (mode
);
8623 /* For a smaller object, just ignore the high bits. */
8624 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8626 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8628 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8631 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8633 #ifndef WORD_REGISTER_OPERATIONS
8634 /* If this machine does not do all register operations on the entire
8635 register and MODE is wider than the mode of X, we can say nothing
8636 at all about the high-order bits. */
8639 /* Likewise on machines that do, if the mode of the object is smaller
8640 than a word and loads of that size don't sign extend, we can say
8641 nothing about the high order bits. */
8642 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8643 #ifdef LOAD_EXTEND_OP
8644 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8655 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8656 /* If pointers extend signed and this is a pointer in Pmode, say that
8657 all the bits above ptr_mode are known to be sign bit copies. */
8658 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8660 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8663 if (reg_last_set_value
[REGNO (x
)] != 0
8664 && reg_last_set_mode
[REGNO (x
)] == mode
8665 && (reg_last_set_label
[REGNO (x
)] == label_tick
8666 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8667 && REG_N_SETS (REGNO (x
)) == 1
8668 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8670 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8671 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8673 tem
= get_last_value (x
);
8675 return num_sign_bit_copies_with_known (tem
, mode
);
8677 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8678 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8679 return reg_sign_bit_copies
[REGNO (x
)];
8683 #ifdef LOAD_EXTEND_OP
8684 /* Some RISC machines sign-extend all loads of smaller than a word. */
8685 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8686 return MAX (1, ((int) bitwidth
8687 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8692 /* If the constant is negative, take its 1's complement and remask.
8693 Then see how many zero bits we have. */
8694 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8695 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8696 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8697 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8699 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8702 /* If this is a SUBREG for a promoted object that is sign-extended
8703 and we are looking at it in a wider mode, we know that at least the
8704 high-order bits are known to be sign bit copies. */
8706 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8708 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8709 return MAX ((int) bitwidth
8710 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8714 /* For a smaller object, just ignore the high bits. */
8715 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8717 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8718 return MAX (1, (num0
8719 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8723 #ifdef WORD_REGISTER_OPERATIONS
8724 #ifdef LOAD_EXTEND_OP
8725 /* For paradoxical SUBREGs on machines where all register operations
8726 affect the entire register, just look inside. Note that we are
8727 passing MODE to the recursive call, so the number of sign bit copies
8728 will remain relative to that mode, not the inner mode. */
8730 /* This works only if loads sign extend. Otherwise, if we get a
8731 reload for the inner part, it may be loaded from the stack, and
8732 then we lose all sign bit copies that existed before the store
8735 if ((GET_MODE_SIZE (GET_MODE (x
))
8736 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8737 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8738 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8739 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8745 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8746 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8750 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8751 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8754 /* For a smaller object, just ignore the high bits. */
8755 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8756 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8760 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8762 case ROTATE
: case ROTATERT
:
8763 /* If we are rotating left by a number of bits less than the number
8764 of sign bit copies, we can just subtract that amount from the
8766 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8767 && INTVAL (XEXP (x
, 1)) >= 0
8768 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8770 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8771 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8772 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8777 /* In general, this subtracts one sign bit copy. But if the value
8778 is known to be positive, the number of sign bit copies is the
8779 same as that of the input. Finally, if the input has just one bit
8780 that might be nonzero, all the bits are copies of the sign bit. */
8781 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8782 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8783 return num0
> 1 ? num0
- 1 : 1;
8785 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8790 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8795 case IOR
: case AND
: case XOR
:
8796 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8797 /* Logical operations will preserve the number of sign-bit copies.
8798 MIN and MAX operations always return one of the operands. */
8799 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8800 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8801 return MIN (num0
, num1
);
8803 case PLUS
: case MINUS
:
8804 /* For addition and subtraction, we can have a 1-bit carry. However,
8805 if we are subtracting 1 from a positive number, there will not
8806 be such a carry. Furthermore, if the positive number is known to
8807 be 0 or 1, we know the result is either -1 or 0. */
8809 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8810 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8812 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8813 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8814 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8815 : bitwidth
- floor_log2 (nonzero
) - 1);
8818 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8819 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8820 result
= MAX (1, MIN (num0
, num1
) - 1);
8822 #ifdef POINTERS_EXTEND_UNSIGNED
8823 /* If pointers extend signed and this is an addition or subtraction
8824 to a pointer in Pmode, all the bits above ptr_mode are known to be
8826 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8827 && (code
== PLUS
|| code
== MINUS
)
8828 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8829 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8830 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8836 /* The number of bits of the product is the sum of the number of
8837 bits of both terms. However, unless one of the terms if known
8838 to be positive, we must allow for an additional bit since negating
8839 a negative number can remove one sign bit copy. */
8841 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8842 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8844 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8846 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8847 || (((nonzero_bits (XEXP (x
, 0), mode
)
8848 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8849 && ((nonzero_bits (XEXP (x
, 1), mode
)
8850 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8853 return MAX (1, result
);
8856 /* The result must be <= the first operand. If the first operand
8857 has the high bit set, we know nothing about the number of sign
8859 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8861 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8862 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8865 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8868 /* The result must be <= the second operand. */
8869 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8872 /* Similar to unsigned division, except that we have to worry about
8873 the case where the divisor is negative, in which case we have
8875 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8877 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8878 || (nonzero_bits (XEXP (x
, 1), mode
)
8879 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8885 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8887 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8888 || (nonzero_bits (XEXP (x
, 1), mode
)
8889 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8895 /* Shifts by a constant add to the number of bits equal to the
8897 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8898 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8899 && INTVAL (XEXP (x
, 1)) > 0)
8900 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8905 /* Left shifts destroy copies. */
8906 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8907 || INTVAL (XEXP (x
, 1)) < 0
8908 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8911 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8912 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8915 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8916 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8917 return MIN (num0
, num1
);
8919 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8920 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8921 case GEU
: case GTU
: case LEU
: case LTU
:
8922 case UNORDERED
: case ORDERED
:
8923 /* If the constant is negative, take its 1's complement and remask.
8924 Then see how many zero bits we have. */
8925 nonzero
= STORE_FLAG_VALUE
;
8926 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8927 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8928 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8930 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8937 /* If we haven't been able to figure it out by one of the above rules,
8938 see if some of the high-order bits are known to be zero. If so,
8939 count those bits and return one less than that amount. If we can't
8940 safely compute the mask for this mode, always return BITWIDTH. */
8942 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8945 nonzero
= nonzero_bits (x
, mode
);
8946 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8947 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8950 /* Return the number of "extended" bits there are in X, when interpreted
8951 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8952 unsigned quantities, this is the number of high-order zero bits.
8953 For signed quantities, this is the number of copies of the sign bit
8954 minus 1. In both case, this function returns the number of "spare"
8955 bits. For example, if two quantities for which this function returns
8956 at least 1 are added, the addition is known not to overflow.
8958 This function will always return 0 unless called during combine, which
8959 implies that it must be called from a define_split. */
8962 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8964 if (nonzero_sign_valid
== 0)
8968 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8969 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8970 - floor_log2 (nonzero_bits (x
, mode
)))
8972 : num_sign_bit_copies (x
, mode
) - 1);
8975 /* This function is called from `simplify_shift_const' to merge two
8976 outer operations. Specifically, we have already found that we need
8977 to perform operation *POP0 with constant *PCONST0 at the outermost
8978 position. We would now like to also perform OP1 with constant CONST1
8979 (with *POP0 being done last).
8981 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8982 the resulting operation. *PCOMP_P is set to 1 if we would need to
8983 complement the innermost operand, otherwise it is unchanged.
8985 MODE is the mode in which the operation will be done. No bits outside
8986 the width of this mode matter. It is assumed that the width of this mode
8987 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8989 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8990 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8991 result is simply *PCONST0.
8993 If the resulting operation cannot be expressed as one operation, we
8994 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8997 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8999 enum rtx_code op0
= *pop0
;
9000 HOST_WIDE_INT const0
= *pconst0
;
9002 const0
&= GET_MODE_MASK (mode
);
9003 const1
&= GET_MODE_MASK (mode
);
9005 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9009 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9012 if (op1
== NIL
|| op0
== SET
)
9015 else if (op0
== NIL
)
9016 op0
= op1
, const0
= const1
;
9018 else if (op0
== op1
)
9042 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9043 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9046 /* If the two constants aren't the same, we can't do anything. The
9047 remaining six cases can all be done. */
9048 else if (const0
!= const1
)
9056 /* (a & b) | b == b */
9058 else /* op1 == XOR */
9059 /* (a ^ b) | b == a | b */
9065 /* (a & b) ^ b == (~a) & b */
9066 op0
= AND
, *pcomp_p
= 1;
9067 else /* op1 == IOR */
9068 /* (a | b) ^ b == a & ~b */
9069 op0
= AND
, const0
= ~const0
;
9074 /* (a | b) & b == b */
9076 else /* op1 == XOR */
9077 /* (a ^ b) & b) == (~a) & b */
9084 /* Check for NO-OP cases. */
9085 const0
&= GET_MODE_MASK (mode
);
9087 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9089 else if (const0
== 0 && op0
== AND
)
9091 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9095 /* ??? Slightly redundant with the above mask, but not entirely.
9096 Moving this above means we'd have to sign-extend the mode mask
9097 for the final test. */
9098 const0
= trunc_int_for_mode (const0
, mode
);
9106 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9107 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9108 that we started with.
9110 The shift is normally computed in the widest mode we find in VAROP, as
9111 long as it isn't a different number of words than RESULT_MODE. Exceptions
9112 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9115 simplify_shift_const (rtx x
, enum rtx_code code
,
9116 enum machine_mode result_mode
, rtx varop
,
9119 enum rtx_code orig_code
= code
;
9122 enum machine_mode mode
= result_mode
;
9123 enum machine_mode shift_mode
, tmode
;
9124 unsigned int mode_words
9125 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9126 /* We form (outer_op (code varop count) (outer_const)). */
9127 enum rtx_code outer_op
= NIL
;
9128 HOST_WIDE_INT outer_const
= 0;
9130 int complement_p
= 0;
9133 /* Make sure and truncate the "natural" shift on the way in. We don't
9134 want to do this inside the loop as it makes it more difficult to
9136 if (SHIFT_COUNT_TRUNCATED
)
9137 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9139 /* If we were given an invalid count, don't do anything except exactly
9140 what was requested. */
9142 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9147 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9152 /* Unless one of the branches of the `if' in this loop does a `continue',
9153 we will `break' the loop after the `if'. */
9157 /* If we have an operand of (clobber (const_int 0)), just return that
9159 if (GET_CODE (varop
) == CLOBBER
)
9162 /* If we discovered we had to complement VAROP, leave. Making a NOT
9163 here would cause an infinite loop. */
9167 /* Convert ROTATERT to ROTATE. */
9168 if (code
== ROTATERT
)
9170 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9172 if (VECTOR_MODE_P (result_mode
))
9173 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9175 count
= bitsize
- count
;
9178 /* We need to determine what mode we will do the shift in. If the
9179 shift is a right shift or a ROTATE, we must always do it in the mode
9180 it was originally done in. Otherwise, we can do it in MODE, the
9181 widest mode encountered. */
9183 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9184 ? result_mode
: mode
);
9186 /* Handle cases where the count is greater than the size of the mode
9187 minus 1. For ASHIFT, use the size minus one as the count (this can
9188 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9189 take the count modulo the size. For other shifts, the result is
9192 Since these shifts are being produced by the compiler by combining
9193 multiple operations, each of which are defined, we know what the
9194 result is supposed to be. */
9196 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9198 if (code
== ASHIFTRT
)
9199 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9200 else if (code
== ROTATE
|| code
== ROTATERT
)
9201 count
%= GET_MODE_BITSIZE (shift_mode
);
9204 /* We can't simply return zero because there may be an
9212 /* An arithmetic right shift of a quantity known to be -1 or 0
9214 if (code
== ASHIFTRT
9215 && (num_sign_bit_copies (varop
, shift_mode
)
9216 == GET_MODE_BITSIZE (shift_mode
)))
9222 /* If we are doing an arithmetic right shift and discarding all but
9223 the sign bit copies, this is equivalent to doing a shift by the
9224 bitsize minus one. Convert it into that shift because it will often
9225 allow other simplifications. */
9227 if (code
== ASHIFTRT
9228 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9229 >= GET_MODE_BITSIZE (shift_mode
)))
9230 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9232 /* We simplify the tests below and elsewhere by converting
9233 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9234 `make_compound_operation' will convert it to an ASHIFTRT for
9235 those machines (such as VAX) that don't have an LSHIFTRT. */
9236 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9238 && ((nonzero_bits (varop
, shift_mode
)
9239 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9243 if (code
== LSHIFTRT
9244 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9245 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9248 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9249 && !((nonzero_bits (varop
, shift_mode
) << count
)
9250 & GET_MODE_MASK (shift_mode
)))
9253 switch (GET_CODE (varop
))
9259 new = expand_compound_operation (varop
);
9268 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9269 minus the width of a smaller mode, we can do this with a
9270 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9271 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9272 && ! mode_dependent_address_p (XEXP (varop
, 0))
9273 && ! MEM_VOLATILE_P (varop
)
9274 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9275 MODE_INT
, 1)) != BLKmode
)
9277 new = adjust_address_nv (varop
, tmode
,
9278 BYTES_BIG_ENDIAN
? 0
9279 : count
/ BITS_PER_UNIT
);
9281 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9282 : ZERO_EXTEND
, mode
, new);
9289 /* Similar to the case above, except that we can only do this if
9290 the resulting mode is the same as that of the underlying
9291 MEM and adjust the address depending on the *bits* endianness
9292 because of the way that bit-field extract insns are defined. */
9293 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9294 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9295 MODE_INT
, 1)) != BLKmode
9296 && tmode
== GET_MODE (XEXP (varop
, 0)))
9298 if (BITS_BIG_ENDIAN
)
9299 new = XEXP (varop
, 0);
9302 new = copy_rtx (XEXP (varop
, 0));
9303 SUBST (XEXP (new, 0),
9304 plus_constant (XEXP (new, 0),
9305 count
/ BITS_PER_UNIT
));
9308 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9309 : ZERO_EXTEND
, mode
, new);
9316 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9317 the same number of words as what we've seen so far. Then store
9318 the widest mode in MODE. */
9319 if (subreg_lowpart_p (varop
)
9320 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9321 > GET_MODE_SIZE (GET_MODE (varop
)))
9322 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9323 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9326 varop
= SUBREG_REG (varop
);
9327 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9328 mode
= GET_MODE (varop
);
9334 /* Some machines use MULT instead of ASHIFT because MULT
9335 is cheaper. But it is still better on those machines to
9336 merge two shifts into one. */
9337 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9338 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9341 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9342 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9348 /* Similar, for when divides are cheaper. */
9349 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9350 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9353 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9354 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9360 /* If we are extracting just the sign bit of an arithmetic
9361 right shift, that shift is not needed. However, the sign
9362 bit of a wider mode may be different from what would be
9363 interpreted as the sign bit in a narrower mode, so, if
9364 the result is narrower, don't discard the shift. */
9365 if (code
== LSHIFTRT
9366 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9367 && (GET_MODE_BITSIZE (result_mode
)
9368 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9370 varop
= XEXP (varop
, 0);
9374 /* ... fall through ... */
9379 /* Here we have two nested shifts. The result is usually the
9380 AND of a new shift with a mask. We compute the result below. */
9381 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9382 && INTVAL (XEXP (varop
, 1)) >= 0
9383 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9384 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9385 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9387 enum rtx_code first_code
= GET_CODE (varop
);
9388 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9389 unsigned HOST_WIDE_INT mask
;
9392 /* We have one common special case. We can't do any merging if
9393 the inner code is an ASHIFTRT of a smaller mode. However, if
9394 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9395 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9396 we can convert it to
9397 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9398 This simplifies certain SIGN_EXTEND operations. */
9399 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9400 && count
== (unsigned int)
9401 (GET_MODE_BITSIZE (result_mode
)
9402 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9404 /* C3 has the low-order C1 bits zero. */
9406 mask
= (GET_MODE_MASK (mode
)
9407 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9409 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9410 XEXP (varop
, 0), mask
);
9411 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9413 count
= first_count
;
9418 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9419 than C1 high-order bits equal to the sign bit, we can convert
9420 this to either an ASHIFT or an ASHIFTRT depending on the
9423 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9425 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9426 && GET_MODE (varop
) == shift_mode
9427 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9430 varop
= XEXP (varop
, 0);
9432 signed_count
= count
- first_count
;
9433 if (signed_count
< 0)
9434 count
= -signed_count
, code
= ASHIFT
;
9436 count
= signed_count
;
9441 /* There are some cases we can't do. If CODE is ASHIFTRT,
9442 we can only do this if FIRST_CODE is also ASHIFTRT.
9444 We can't do the case when CODE is ROTATE and FIRST_CODE is
9447 If the mode of this shift is not the mode of the outer shift,
9448 we can't do this if either shift is a right shift or ROTATE.
9450 Finally, we can't do any of these if the mode is too wide
9451 unless the codes are the same.
9453 Handle the case where the shift codes are the same
9456 if (code
== first_code
)
9458 if (GET_MODE (varop
) != result_mode
9459 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9463 count
+= first_count
;
9464 varop
= XEXP (varop
, 0);
9468 if (code
== ASHIFTRT
9469 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9470 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9471 || (GET_MODE (varop
) != result_mode
9472 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9473 || first_code
== ROTATE
9474 || code
== ROTATE
)))
9477 /* To compute the mask to apply after the shift, shift the
9478 nonzero bits of the inner shift the same way the
9479 outer shift will. */
9481 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9484 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9487 /* Give up if we can't compute an outer operation to use. */
9489 || GET_CODE (mask_rtx
) != CONST_INT
9490 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9492 result_mode
, &complement_p
))
9495 /* If the shifts are in the same direction, we add the
9496 counts. Otherwise, we subtract them. */
9497 signed_count
= count
;
9498 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9499 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9500 signed_count
+= first_count
;
9502 signed_count
-= first_count
;
9504 /* If COUNT is positive, the new shift is usually CODE,
9505 except for the two exceptions below, in which case it is
9506 FIRST_CODE. If the count is negative, FIRST_CODE should
9508 if (signed_count
> 0
9509 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9510 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9511 code
= first_code
, count
= signed_count
;
9512 else if (signed_count
< 0)
9513 code
= first_code
, count
= -signed_count
;
9515 count
= signed_count
;
9517 varop
= XEXP (varop
, 0);
9521 /* If we have (A << B << C) for any shift, we can convert this to
9522 (A << C << B). This wins if A is a constant. Only try this if
9523 B is not a constant. */
9525 else if (GET_CODE (varop
) == code
9526 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9528 = simplify_binary_operation (code
, mode
,
9532 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9539 /* Make this fit the case below. */
9540 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9541 GEN_INT (GET_MODE_MASK (mode
)));
9547 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9548 with C the size of VAROP - 1 and the shift is logical if
9549 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9550 we have an (le X 0) operation. If we have an arithmetic shift
9551 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9552 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9554 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9555 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9556 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9557 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9558 && count
== (unsigned int)
9559 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9560 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9563 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9566 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9567 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9572 /* If we have (shift (logical)), move the logical to the outside
9573 to allow it to possibly combine with another logical and the
9574 shift to combine with another shift. This also canonicalizes to
9575 what a ZERO_EXTRACT looks like. Also, some machines have
9576 (and (shift)) insns. */
9578 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9579 /* We can't do this if we have (ashiftrt (xor)) and the
9580 constant has its sign bit set in shift_mode. */
9581 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9582 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9584 && (new = simplify_binary_operation (code
, result_mode
,
9586 GEN_INT (count
))) != 0
9587 && GET_CODE (new) == CONST_INT
9588 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9589 INTVAL (new), result_mode
, &complement_p
))
9591 varop
= XEXP (varop
, 0);
9595 /* If we can't do that, try to simplify the shift in each arm of the
9596 logical expression, make a new logical expression, and apply
9597 the inverse distributive law. This also can't be done
9598 for some (ashiftrt (xor)). */
9599 if (code
!= ASHIFTRT
|| GET_CODE (varop
)!= XOR
9600 || 0 <= trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9603 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9604 XEXP (varop
, 0), count
);
9605 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9606 XEXP (varop
, 1), count
);
9608 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9609 varop
= apply_distributive_law (varop
);
9616 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9617 says that the sign bit can be tested, FOO has mode MODE, C is
9618 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9619 that may be nonzero. */
9620 if (code
== LSHIFTRT
9621 && XEXP (varop
, 1) == const0_rtx
9622 && GET_MODE (XEXP (varop
, 0)) == result_mode
9623 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9624 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9625 && ((STORE_FLAG_VALUE
9626 & ((HOST_WIDE_INT
) 1
9627 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9628 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9629 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9630 (HOST_WIDE_INT
) 1, result_mode
,
9633 varop
= XEXP (varop
, 0);
9640 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9641 than the number of bits in the mode is equivalent to A. */
9642 if (code
== LSHIFTRT
9643 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9644 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9646 varop
= XEXP (varop
, 0);
9651 /* NEG commutes with ASHIFT since it is multiplication. Move the
9652 NEG outside to allow shifts to combine. */
9654 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9655 (HOST_WIDE_INT
) 0, result_mode
,
9658 varop
= XEXP (varop
, 0);
9664 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9665 is one less than the number of bits in the mode is
9666 equivalent to (xor A 1). */
9667 if (code
== LSHIFTRT
9668 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9669 && XEXP (varop
, 1) == constm1_rtx
9670 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9671 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9672 (HOST_WIDE_INT
) 1, result_mode
,
9676 varop
= XEXP (varop
, 0);
9680 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9681 that might be nonzero in BAR are those being shifted out and those
9682 bits are known zero in FOO, we can replace the PLUS with FOO.
9683 Similarly in the other operand order. This code occurs when
9684 we are computing the size of a variable-size array. */
9686 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9687 && count
< HOST_BITS_PER_WIDE_INT
9688 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9689 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9690 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9692 varop
= XEXP (varop
, 0);
9695 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9696 && count
< HOST_BITS_PER_WIDE_INT
9697 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9698 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9700 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9701 & nonzero_bits (XEXP (varop
, 1),
9704 varop
= XEXP (varop
, 1);
9708 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9710 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9711 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9713 GEN_INT (count
))) != 0
9714 && GET_CODE (new) == CONST_INT
9715 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9716 INTVAL (new), result_mode
, &complement_p
))
9718 varop
= XEXP (varop
, 0);
9724 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9725 with C the size of VAROP - 1 and the shift is logical if
9726 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9727 we have a (gt X 0) operation. If the shift is arithmetic with
9728 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9729 we have a (neg (gt X 0)) operation. */
9731 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9732 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9733 && count
== (unsigned int)
9734 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9735 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9736 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9737 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9739 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9742 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9745 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9746 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9753 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9754 if the truncate does not affect the value. */
9755 if (code
== LSHIFTRT
9756 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9757 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9758 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9759 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9760 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9762 rtx varop_inner
= XEXP (varop
, 0);
9765 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9766 XEXP (varop_inner
, 0),
9768 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9769 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9782 /* We need to determine what mode to do the shift in. If the shift is
9783 a right shift or ROTATE, we must always do it in the mode it was
9784 originally done in. Otherwise, we can do it in MODE, the widest mode
9785 encountered. The code we care about is that of the shift that will
9786 actually be done, not the shift that was originally requested. */
9788 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9789 ? result_mode
: mode
);
9791 /* We have now finished analyzing the shift. The result should be
9792 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9793 OUTER_OP is non-NIL, it is an operation that needs to be applied
9794 to the result of the shift. OUTER_CONST is the relevant constant,
9795 but we must turn off all bits turned off in the shift.
9797 If we were passed a value for X, see if we can use any pieces of
9798 it. If not, make new rtx. */
9800 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9801 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9802 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9803 const_rtx
= XEXP (x
, 1);
9805 const_rtx
= GEN_INT (count
);
9807 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9808 && GET_MODE (XEXP (x
, 0)) == shift_mode
9809 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9810 varop
= XEXP (x
, 0);
9811 else if (GET_MODE (varop
) != shift_mode
)
9812 varop
= gen_lowpart (shift_mode
, varop
);
9814 /* If we can't make the SUBREG, try to return what we were given. */
9815 if (GET_CODE (varop
) == CLOBBER
)
9816 return x
? x
: varop
;
9818 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9822 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9824 /* If we have an outer operation and we just made a shift, it is
9825 possible that we could have simplified the shift were it not
9826 for the outer operation. So try to do the simplification
9829 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9830 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9831 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9832 INTVAL (XEXP (x
, 1)));
9834 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9835 turn off all the bits that the shift would have turned off. */
9836 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9837 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9838 GET_MODE_MASK (result_mode
) >> orig_count
);
9840 /* Do the remainder of the processing in RESULT_MODE. */
9841 x
= gen_lowpart (result_mode
, x
);
9843 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9846 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9848 if (outer_op
!= NIL
)
9850 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9851 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9853 if (outer_op
== AND
)
9854 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9855 else if (outer_op
== SET
)
9856 /* This means that we have determined that the result is
9857 equivalent to a constant. This should be rare. */
9858 x
= GEN_INT (outer_const
);
9859 else if (GET_RTX_CLASS (outer_op
) == '1')
9860 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9862 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9868 /* Like recog, but we receive the address of a pointer to a new pattern.
9869 We try to match the rtx that the pointer points to.
9870 If that fails, we may try to modify or replace the pattern,
9871 storing the replacement into the same pointer object.
9873 Modifications include deletion or addition of CLOBBERs.
9875 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9876 the CLOBBERs are placed.
9878 The value is the final insn code from the pattern ultimately matched,
9882 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9885 int insn_code_number
;
9886 int num_clobbers_to_add
= 0;
9889 rtx old_notes
, old_pat
;
9891 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9892 we use to indicate that something didn't match. If we find such a
9893 thing, force rejection. */
9894 if (GET_CODE (pat
) == PARALLEL
)
9895 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9896 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9897 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9900 old_pat
= PATTERN (insn
);
9901 old_notes
= REG_NOTES (insn
);
9902 PATTERN (insn
) = pat
;
9903 REG_NOTES (insn
) = 0;
9905 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9907 /* If it isn't, there is the possibility that we previously had an insn
9908 that clobbered some register as a side effect, but the combined
9909 insn doesn't need to do that. So try once more without the clobbers
9910 unless this represents an ASM insn. */
9912 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9913 && GET_CODE (pat
) == PARALLEL
)
9917 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9918 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9921 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9925 SUBST_INT (XVECLEN (pat
, 0), pos
);
9928 pat
= XVECEXP (pat
, 0, 0);
9930 PATTERN (insn
) = pat
;
9931 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9933 PATTERN (insn
) = old_pat
;
9934 REG_NOTES (insn
) = old_notes
;
9936 /* Recognize all noop sets, these will be killed by followup pass. */
9937 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9938 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9940 /* If we had any clobbers to add, make a new pattern than contains
9941 them. Then check to make sure that all of them are dead. */
9942 if (num_clobbers_to_add
)
9944 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9945 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9947 + num_clobbers_to_add
)
9948 : num_clobbers_to_add
+ 1));
9950 if (GET_CODE (pat
) == PARALLEL
)
9951 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9952 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9954 XVECEXP (newpat
, 0, 0) = pat
;
9956 add_clobbers (newpat
, insn_code_number
);
9958 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9959 i
< XVECLEN (newpat
, 0); i
++)
9961 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9962 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9964 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9965 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9973 return insn_code_number
;
9976 /* Like gen_lowpart_general but for use by combine. In combine it
9977 is not possible to create any new pseudoregs. However, it is
9978 safe to create invalid memory addresses, because combine will
9979 try to recognize them and all they will do is make the combine
9982 If for some reason this cannot do its job, an rtx
9983 (clobber (const_int 0)) is returned.
9984 An insn containing that will not be recognized. */
9987 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
9991 if (GET_MODE (x
) == mode
)
9994 /* Return identity if this is a CONST or symbolic
9997 && (GET_CODE (x
) == CONST
9998 || GET_CODE (x
) == SYMBOL_REF
9999 || GET_CODE (x
) == LABEL_REF
))
10002 /* We can only support MODE being wider than a word if X is a
10003 constant integer or has a mode the same size. */
10005 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
10006 && ! ((GET_MODE (x
) == VOIDmode
10007 && (GET_CODE (x
) == CONST_INT
10008 || GET_CODE (x
) == CONST_DOUBLE
))
10009 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
10010 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10012 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10013 won't know what to do. So we will strip off the SUBREG here and
10014 process normally. */
10015 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
10017 x
= SUBREG_REG (x
);
10018 if (GET_MODE (x
) == mode
)
10022 result
= gen_lowpart_common (mode
, x
);
10023 #ifdef CANNOT_CHANGE_MODE_CLASS
10025 && GET_CODE (result
) == SUBREG
10026 && GET_CODE (SUBREG_REG (result
)) == REG
10027 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10028 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10030 + GET_MODE (result
));
10036 if (GET_CODE (x
) == MEM
)
10040 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10042 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10043 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10045 /* If we want to refer to something bigger than the original memref,
10046 generate a perverse subreg instead. That will force a reload
10047 of the original memref X. */
10048 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10049 return gen_rtx_SUBREG (mode
, x
, 0);
10051 if (WORDS_BIG_ENDIAN
)
10052 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10053 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10055 if (BYTES_BIG_ENDIAN
)
10057 /* Adjust the address so that the address-after-the-data is
10059 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10060 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10063 return adjust_address_nv (x
, mode
, offset
);
10066 /* If X is a comparison operator, rewrite it in a new mode. This
10067 probably won't match, but may allow further simplifications. */
10068 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10069 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10071 /* If we couldn't simplify X any other way, just enclose it in a
10072 SUBREG. Normally, this SUBREG won't match, but some patterns may
10073 include an explicit SUBREG or we may simplify it further in combine. */
10078 enum machine_mode sub_mode
= GET_MODE (x
);
10080 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10081 if (sub_mode
== VOIDmode
)
10083 sub_mode
= int_mode_for_mode (mode
);
10084 x
= gen_lowpart_common (sub_mode
, x
);
10086 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10088 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10091 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10095 /* These routines make binary and unary operations by first seeing if they
10096 fold; if not, a new expression is allocated. */
10099 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10104 if (GET_CODE (op0
) == CLOBBER
)
10106 else if (GET_CODE (op1
) == CLOBBER
)
10109 if (GET_RTX_CLASS (code
) == 'c'
10110 && swap_commutative_operands_p (op0
, op1
))
10111 tem
= op0
, op0
= op1
, op1
= tem
;
10113 if (GET_RTX_CLASS (code
) == '<')
10115 enum machine_mode op_mode
= GET_MODE (op0
);
10117 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10118 just (REL_OP X Y). */
10119 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10121 op1
= XEXP (op0
, 1);
10122 op0
= XEXP (op0
, 0);
10123 op_mode
= GET_MODE (op0
);
10126 if (op_mode
== VOIDmode
)
10127 op_mode
= GET_MODE (op1
);
10128 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10131 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10136 /* Put complex operands first and constants second. */
10137 if (GET_RTX_CLASS (code
) == 'c'
10138 && swap_commutative_operands_p (op0
, op1
))
10139 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10141 /* If we are turning off bits already known off in OP0, we need not do
10143 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10144 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10145 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10148 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10151 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10152 comparison code that will be tested.
10154 The result is a possibly different comparison code to use. *POP0 and
10155 *POP1 may be updated.
10157 It is possible that we might detect that a comparison is either always
10158 true or always false. However, we do not perform general constant
10159 folding in combine, so this knowledge isn't useful. Such tautologies
10160 should have been detected earlier. Hence we ignore all such cases. */
10162 static enum rtx_code
10163 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10169 enum machine_mode mode
, tmode
;
10171 /* Try a few ways of applying the same transformation to both operands. */
10174 #ifndef WORD_REGISTER_OPERATIONS
10175 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10176 so check specially. */
10177 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10178 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10179 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10180 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10181 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10182 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10183 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10184 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10185 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10186 && XEXP (op0
, 1) == XEXP (op1
, 1)
10187 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10188 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10189 && (INTVAL (XEXP (op0
, 1))
10190 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10191 - (GET_MODE_BITSIZE
10192 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10194 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10195 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10199 /* If both operands are the same constant shift, see if we can ignore the
10200 shift. We can if the shift is a rotate or if the bits shifted out of
10201 this shift are known to be zero for both inputs and if the type of
10202 comparison is compatible with the shift. */
10203 if (GET_CODE (op0
) == GET_CODE (op1
)
10204 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10205 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10206 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10207 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10208 || (GET_CODE (op0
) == ASHIFTRT
10209 && (code
!= GTU
&& code
!= LTU
10210 && code
!= GEU
&& code
!= LEU
)))
10211 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10212 && INTVAL (XEXP (op0
, 1)) >= 0
10213 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10214 && XEXP (op0
, 1) == XEXP (op1
, 1))
10216 enum machine_mode mode
= GET_MODE (op0
);
10217 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10218 int shift_count
= INTVAL (XEXP (op0
, 1));
10220 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10221 mask
&= (mask
>> shift_count
) << shift_count
;
10222 else if (GET_CODE (op0
) == ASHIFT
)
10223 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10225 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10226 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10227 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10232 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10233 SUBREGs are of the same mode, and, in both cases, the AND would
10234 be redundant if the comparison was done in the narrower mode,
10235 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10236 and the operand's possibly nonzero bits are 0xffffff01; in that case
10237 if we only care about QImode, we don't need the AND). This case
10238 occurs if the output mode of an scc insn is not SImode and
10239 STORE_FLAG_VALUE == 1 (e.g., the 386).
10241 Similarly, check for a case where the AND's are ZERO_EXTEND
10242 operations from some narrower mode even though a SUBREG is not
10245 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10246 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10247 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10249 rtx inner_op0
= XEXP (op0
, 0);
10250 rtx inner_op1
= XEXP (op1
, 0);
10251 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10252 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10255 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10256 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10257 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10258 && (GET_MODE (SUBREG_REG (inner_op0
))
10259 == GET_MODE (SUBREG_REG (inner_op1
)))
10260 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10261 <= HOST_BITS_PER_WIDE_INT
)
10262 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10263 GET_MODE (SUBREG_REG (inner_op0
)))))
10264 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10265 GET_MODE (SUBREG_REG (inner_op1
))))))
10267 op0
= SUBREG_REG (inner_op0
);
10268 op1
= SUBREG_REG (inner_op1
);
10270 /* The resulting comparison is always unsigned since we masked
10271 off the original sign bit. */
10272 code
= unsigned_condition (code
);
10278 for (tmode
= GET_CLASS_NARROWEST_MODE
10279 (GET_MODE_CLASS (GET_MODE (op0
)));
10280 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10281 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10283 op0
= gen_lowpart (tmode
, inner_op0
);
10284 op1
= gen_lowpart (tmode
, inner_op1
);
10285 code
= unsigned_condition (code
);
10294 /* If both operands are NOT, we can strip off the outer operation
10295 and adjust the comparison code for swapped operands; similarly for
10296 NEG, except that this must be an equality comparison. */
10297 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10298 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10299 && (code
== EQ
|| code
== NE
)))
10300 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10306 /* If the first operand is a constant, swap the operands and adjust the
10307 comparison code appropriately, but don't do this if the second operand
10308 is already a constant integer. */
10309 if (swap_commutative_operands_p (op0
, op1
))
10311 tem
= op0
, op0
= op1
, op1
= tem
;
10312 code
= swap_condition (code
);
10315 /* We now enter a loop during which we will try to simplify the comparison.
10316 For the most part, we only are concerned with comparisons with zero,
10317 but some things may really be comparisons with zero but not start
10318 out looking that way. */
10320 while (GET_CODE (op1
) == CONST_INT
)
10322 enum machine_mode mode
= GET_MODE (op0
);
10323 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10324 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10325 int equality_comparison_p
;
10326 int sign_bit_comparison_p
;
10327 int unsigned_comparison_p
;
10328 HOST_WIDE_INT const_op
;
10330 /* We only want to handle integral modes. This catches VOIDmode,
10331 CCmode, and the floating-point modes. An exception is that we
10332 can handle VOIDmode if OP0 is a COMPARE or a comparison
10335 if (GET_MODE_CLASS (mode
) != MODE_INT
10336 && ! (mode
== VOIDmode
10337 && (GET_CODE (op0
) == COMPARE
10338 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10341 /* Get the constant we are comparing against and turn off all bits
10342 not on in our mode. */
10343 const_op
= INTVAL (op1
);
10344 if (mode
!= VOIDmode
)
10345 const_op
= trunc_int_for_mode (const_op
, mode
);
10346 op1
= GEN_INT (const_op
);
10348 /* If we are comparing against a constant power of two and the value
10349 being compared can only have that single bit nonzero (e.g., it was
10350 `and'ed with that bit), we can replace this with a comparison
10353 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10354 || code
== LT
|| code
== LTU
)
10355 && mode_width
<= HOST_BITS_PER_WIDE_INT
10356 && exact_log2 (const_op
) >= 0
10357 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10359 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10360 op1
= const0_rtx
, const_op
= 0;
10363 /* Similarly, if we are comparing a value known to be either -1 or
10364 0 with -1, change it to the opposite comparison against zero. */
10367 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10368 || code
== GEU
|| code
== LTU
)
10369 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10371 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10372 op1
= const0_rtx
, const_op
= 0;
10375 /* Do some canonicalizations based on the comparison code. We prefer
10376 comparisons against zero and then prefer equality comparisons.
10377 If we can reduce the size of a constant, we will do that too. */
10382 /* < C is equivalent to <= (C - 1) */
10386 op1
= GEN_INT (const_op
);
10388 /* ... fall through to LE case below. */
10394 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10398 op1
= GEN_INT (const_op
);
10402 /* If we are doing a <= 0 comparison on a value known to have
10403 a zero sign bit, we can replace this with == 0. */
10404 else if (const_op
== 0
10405 && mode_width
<= HOST_BITS_PER_WIDE_INT
10406 && (nonzero_bits (op0
, mode
)
10407 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10412 /* >= C is equivalent to > (C - 1). */
10416 op1
= GEN_INT (const_op
);
10418 /* ... fall through to GT below. */
10424 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10428 op1
= GEN_INT (const_op
);
10432 /* If we are doing a > 0 comparison on a value known to have
10433 a zero sign bit, we can replace this with != 0. */
10434 else if (const_op
== 0
10435 && mode_width
<= HOST_BITS_PER_WIDE_INT
10436 && (nonzero_bits (op0
, mode
)
10437 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10442 /* < C is equivalent to <= (C - 1). */
10446 op1
= GEN_INT (const_op
);
10448 /* ... fall through ... */
10451 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10452 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10453 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10455 const_op
= 0, op1
= const0_rtx
;
10463 /* unsigned <= 0 is equivalent to == 0 */
10467 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10468 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10469 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10471 const_op
= 0, op1
= const0_rtx
;
10477 /* >= C is equivalent to < (C - 1). */
10481 op1
= GEN_INT (const_op
);
10483 /* ... fall through ... */
10486 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10487 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10488 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10490 const_op
= 0, op1
= const0_rtx
;
10498 /* unsigned > 0 is equivalent to != 0 */
10502 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10503 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10504 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10506 const_op
= 0, op1
= const0_rtx
;
10515 /* Compute some predicates to simplify code below. */
10517 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10518 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10519 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10522 /* If this is a sign bit comparison and we can do arithmetic in
10523 MODE, say that we will only be needing the sign bit of OP0. */
10524 if (sign_bit_comparison_p
10525 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10526 op0
= force_to_mode (op0
, mode
,
10528 << (GET_MODE_BITSIZE (mode
) - 1)),
10531 /* Now try cases based on the opcode of OP0. If none of the cases
10532 does a "continue", we exit this loop immediately after the
10535 switch (GET_CODE (op0
))
10538 /* If we are extracting a single bit from a variable position in
10539 a constant that has only a single bit set and are comparing it
10540 with zero, we can convert this into an equality comparison
10541 between the position and the location of the single bit. */
10542 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10543 have already reduced the shift count modulo the word size. */
10544 if (!SHIFT_COUNT_TRUNCATED
10545 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10546 && XEXP (op0
, 1) == const1_rtx
10547 && equality_comparison_p
&& const_op
== 0
10548 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10550 if (BITS_BIG_ENDIAN
)
10552 enum machine_mode new_mode
10553 = mode_for_extraction (EP_extzv
, 1);
10554 if (new_mode
== MAX_MACHINE_MODE
)
10555 i
= BITS_PER_WORD
- 1 - i
;
10559 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10563 op0
= XEXP (op0
, 2);
10567 /* Result is nonzero iff shift count is equal to I. */
10568 code
= reverse_condition (code
);
10572 /* ... fall through ... */
10575 tem
= expand_compound_operation (op0
);
10584 /* If testing for equality, we can take the NOT of the constant. */
10585 if (equality_comparison_p
10586 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10588 op0
= XEXP (op0
, 0);
10593 /* If just looking at the sign bit, reverse the sense of the
10595 if (sign_bit_comparison_p
)
10597 op0
= XEXP (op0
, 0);
10598 code
= (code
== GE
? LT
: GE
);
10604 /* If testing for equality, we can take the NEG of the constant. */
10605 if (equality_comparison_p
10606 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10608 op0
= XEXP (op0
, 0);
10613 /* The remaining cases only apply to comparisons with zero. */
10617 /* When X is ABS or is known positive,
10618 (neg X) is < 0 if and only if X != 0. */
10620 if (sign_bit_comparison_p
10621 && (GET_CODE (XEXP (op0
, 0)) == ABS
10622 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10623 && (nonzero_bits (XEXP (op0
, 0), mode
)
10624 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10626 op0
= XEXP (op0
, 0);
10627 code
= (code
== LT
? NE
: EQ
);
10631 /* If we have NEG of something whose two high-order bits are the
10632 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10633 if (num_sign_bit_copies (op0
, mode
) >= 2)
10635 op0
= XEXP (op0
, 0);
10636 code
= swap_condition (code
);
10642 /* If we are testing equality and our count is a constant, we
10643 can perform the inverse operation on our RHS. */
10644 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10645 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10646 op1
, XEXP (op0
, 1))) != 0)
10648 op0
= XEXP (op0
, 0);
10653 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10654 a particular bit. Convert it to an AND of a constant of that
10655 bit. This will be converted into a ZERO_EXTRACT. */
10656 if (const_op
== 0 && sign_bit_comparison_p
10657 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10658 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10660 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10663 - INTVAL (XEXP (op0
, 1)))));
10664 code
= (code
== LT
? NE
: EQ
);
10668 /* Fall through. */
10671 /* ABS is ignorable inside an equality comparison with zero. */
10672 if (const_op
== 0 && equality_comparison_p
)
10674 op0
= XEXP (op0
, 0);
10680 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10681 to (compare FOO CONST) if CONST fits in FOO's mode and we
10682 are either testing inequality or have an unsigned comparison
10683 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10684 if (! unsigned_comparison_p
10685 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10686 <= HOST_BITS_PER_WIDE_INT
)
10687 && ((unsigned HOST_WIDE_INT
) const_op
10688 < (((unsigned HOST_WIDE_INT
) 1
10689 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10691 op0
= XEXP (op0
, 0);
10697 /* Check for the case where we are comparing A - C1 with C2,
10698 both constants are smaller than 1/2 the maximum positive
10699 value in MODE, and the comparison is equality or unsigned.
10700 In that case, if A is either zero-extended to MODE or has
10701 sufficient sign bits so that the high-order bit in MODE
10702 is a copy of the sign in the inner mode, we can prove that it is
10703 safe to do the operation in the wider mode. This simplifies
10704 many range checks. */
10706 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10707 && subreg_lowpart_p (op0
)
10708 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10709 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10710 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10711 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10712 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10713 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10714 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10715 GET_MODE (SUBREG_REG (op0
)))
10716 & ~GET_MODE_MASK (mode
))
10717 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10718 GET_MODE (SUBREG_REG (op0
)))
10720 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10721 - GET_MODE_BITSIZE (mode
)))))
10723 op0
= SUBREG_REG (op0
);
10727 /* If the inner mode is narrower and we are extracting the low part,
10728 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10729 if (subreg_lowpart_p (op0
)
10730 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10731 /* Fall through */ ;
10735 /* ... fall through ... */
10738 if ((unsigned_comparison_p
|| equality_comparison_p
)
10739 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10740 <= HOST_BITS_PER_WIDE_INT
)
10741 && ((unsigned HOST_WIDE_INT
) const_op
10742 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10744 op0
= XEXP (op0
, 0);
10750 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10751 this for equality comparisons due to pathological cases involving
10753 if (equality_comparison_p
10754 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10755 op1
, XEXP (op0
, 1))))
10757 op0
= XEXP (op0
, 0);
10762 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10763 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10764 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10766 op0
= XEXP (XEXP (op0
, 0), 0);
10767 code
= (code
== LT
? EQ
: NE
);
10773 /* We used to optimize signed comparisons against zero, but that
10774 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10775 arrive here as equality comparisons, or (GEU, LTU) are
10776 optimized away. No need to special-case them. */
10778 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10779 (eq B (minus A C)), whichever simplifies. We can only do
10780 this for equality comparisons due to pathological cases involving
10782 if (equality_comparison_p
10783 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10784 XEXP (op0
, 1), op1
)))
10786 op0
= XEXP (op0
, 0);
10791 if (equality_comparison_p
10792 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10793 XEXP (op0
, 0), op1
)))
10795 op0
= XEXP (op0
, 1);
10800 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10801 of bits in X minus 1, is one iff X > 0. */
10802 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10803 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10804 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10806 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10808 op0
= XEXP (op0
, 1);
10809 code
= (code
== GE
? LE
: GT
);
10815 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10816 if C is zero or B is a constant. */
10817 if (equality_comparison_p
10818 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10819 XEXP (op0
, 1), op1
)))
10821 op0
= XEXP (op0
, 0);
10828 case UNEQ
: case LTGT
:
10829 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10830 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10831 case UNORDERED
: case ORDERED
:
10832 /* We can't do anything if OP0 is a condition code value, rather
10833 than an actual data value. */
10835 || CC0_P (XEXP (op0
, 0))
10836 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10839 /* Get the two operands being compared. */
10840 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10841 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10843 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10845 /* Check for the cases where we simply want the result of the
10846 earlier test or the opposite of that result. */
10847 if (code
== NE
|| code
== EQ
10848 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10849 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10850 && (STORE_FLAG_VALUE
10851 & (((HOST_WIDE_INT
) 1
10852 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10853 && (code
== LT
|| code
== GE
)))
10855 enum rtx_code new_code
;
10856 if (code
== LT
|| code
== NE
)
10857 new_code
= GET_CODE (op0
);
10859 new_code
= combine_reversed_comparison_code (op0
);
10861 if (new_code
!= UNKNOWN
)
10872 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10874 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10875 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10876 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10878 op0
= XEXP (op0
, 1);
10879 code
= (code
== GE
? GT
: LE
);
10885 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10886 will be converted to a ZERO_EXTRACT later. */
10887 if (const_op
== 0 && equality_comparison_p
10888 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10889 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10891 op0
= simplify_and_const_int
10892 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10894 XEXP (XEXP (op0
, 0), 1)),
10895 (HOST_WIDE_INT
) 1);
10899 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10900 zero and X is a comparison and C1 and C2 describe only bits set
10901 in STORE_FLAG_VALUE, we can compare with X. */
10902 if (const_op
== 0 && equality_comparison_p
10903 && mode_width
<= HOST_BITS_PER_WIDE_INT
10904 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10905 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10906 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10907 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10908 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10910 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10911 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10912 if ((~STORE_FLAG_VALUE
& mask
) == 0
10913 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10914 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10915 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10917 op0
= XEXP (XEXP (op0
, 0), 0);
10922 /* If we are doing an equality comparison of an AND of a bit equal
10923 to the sign bit, replace this with a LT or GE comparison of
10924 the underlying value. */
10925 if (equality_comparison_p
10927 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10928 && mode_width
<= HOST_BITS_PER_WIDE_INT
10929 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10930 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10932 op0
= XEXP (op0
, 0);
10933 code
= (code
== EQ
? GE
: LT
);
10937 /* If this AND operation is really a ZERO_EXTEND from a narrower
10938 mode, the constant fits within that mode, and this is either an
10939 equality or unsigned comparison, try to do this comparison in
10940 the narrower mode. */
10941 if ((equality_comparison_p
|| unsigned_comparison_p
)
10942 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10943 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10944 & GET_MODE_MASK (mode
))
10946 && const_op
>> i
== 0
10947 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10949 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10953 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10954 fits in both M1 and M2 and the SUBREG is either paradoxical
10955 or represents the low part, permute the SUBREG and the AND
10957 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10959 unsigned HOST_WIDE_INT c1
;
10960 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10961 /* Require an integral mode, to avoid creating something like
10963 if (SCALAR_INT_MODE_P (tmode
)
10964 /* It is unsafe to commute the AND into the SUBREG if the
10965 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10966 not defined. As originally written the upper bits
10967 have a defined value due to the AND operation.
10968 However, if we commute the AND inside the SUBREG then
10969 they no longer have defined values and the meaning of
10970 the code has been changed. */
10972 #ifdef WORD_REGISTER_OPERATIONS
10973 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10974 && mode_width
<= BITS_PER_WORD
)
10976 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10977 && subreg_lowpart_p (XEXP (op0
, 0))))
10978 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10979 && mode_width
<= HOST_BITS_PER_WIDE_INT
10980 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10981 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10982 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10984 && c1
!= GET_MODE_MASK (tmode
))
10986 op0
= gen_binary (AND
, tmode
,
10987 SUBREG_REG (XEXP (op0
, 0)),
10988 gen_int_mode (c1
, tmode
));
10989 op0
= gen_lowpart (mode
, op0
);
10994 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10995 if (const_op
== 0 && equality_comparison_p
10996 && XEXP (op0
, 1) == const1_rtx
10997 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10999 op0
= simplify_and_const_int
11000 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
11001 code
= (code
== NE
? EQ
: NE
);
11005 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11006 (eq (and (lshiftrt X) 1) 0).
11007 Also handle the case where (not X) is expressed using xor. */
11008 if (const_op
== 0 && equality_comparison_p
11009 && XEXP (op0
, 1) == const1_rtx
11010 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11012 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11013 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11015 if (GET_CODE (shift_op
) == NOT
11016 || (GET_CODE (shift_op
) == XOR
11017 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
11018 && GET_CODE (shift_count
) == CONST_INT
11019 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11020 && (INTVAL (XEXP (shift_op
, 1))
11021 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11023 op0
= simplify_and_const_int
11025 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11026 (HOST_WIDE_INT
) 1);
11027 code
= (code
== NE
? EQ
: NE
);
11034 /* If we have (compare (ashift FOO N) (const_int C)) and
11035 the high order N bits of FOO (N+1 if an inequality comparison)
11036 are known to be zero, we can do this by comparing FOO with C
11037 shifted right N bits so long as the low-order N bits of C are
11039 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11040 && INTVAL (XEXP (op0
, 1)) >= 0
11041 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11042 < HOST_BITS_PER_WIDE_INT
)
11044 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11045 && mode_width
<= HOST_BITS_PER_WIDE_INT
11046 && (nonzero_bits (XEXP (op0
, 0), mode
)
11047 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11048 + ! equality_comparison_p
))) == 0)
11050 /* We must perform a logical shift, not an arithmetic one,
11051 as we want the top N bits of C to be zero. */
11052 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11054 temp
>>= INTVAL (XEXP (op0
, 1));
11055 op1
= gen_int_mode (temp
, mode
);
11056 op0
= XEXP (op0
, 0);
11060 /* If we are doing a sign bit comparison, it means we are testing
11061 a particular bit. Convert it to the appropriate AND. */
11062 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11063 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11065 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11068 - INTVAL (XEXP (op0
, 1)))));
11069 code
= (code
== LT
? NE
: EQ
);
11073 /* If this an equality comparison with zero and we are shifting
11074 the low bit to the sign bit, we can convert this to an AND of the
11076 if (const_op
== 0 && equality_comparison_p
11077 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11078 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11081 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11082 (HOST_WIDE_INT
) 1);
11088 /* If this is an equality comparison with zero, we can do this
11089 as a logical shift, which might be much simpler. */
11090 if (equality_comparison_p
&& const_op
== 0
11091 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11093 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11095 INTVAL (XEXP (op0
, 1)));
11099 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11100 do the comparison in a narrower mode. */
11101 if (! unsigned_comparison_p
11102 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11103 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11104 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11105 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11106 MODE_INT
, 1)) != BLKmode
11107 && (((unsigned HOST_WIDE_INT
) const_op
11108 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11109 <= GET_MODE_MASK (tmode
)))
11111 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11115 /* Likewise if OP0 is a PLUS of a sign extension with a
11116 constant, which is usually represented with the PLUS
11117 between the shifts. */
11118 if (! unsigned_comparison_p
11119 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11120 && GET_CODE (XEXP (op0
, 0)) == PLUS
11121 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11122 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11123 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11124 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11125 MODE_INT
, 1)) != BLKmode
11126 && (((unsigned HOST_WIDE_INT
) const_op
11127 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11128 <= GET_MODE_MASK (tmode
)))
11130 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11131 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11132 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11135 op0
= gen_binary (PLUS
, tmode
,
11136 gen_lowpart (tmode
, inner
),
11141 /* ... fall through ... */
11143 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11144 the low order N bits of FOO are known to be zero, we can do this
11145 by comparing FOO with C shifted left N bits so long as no
11146 overflow occurs. */
11147 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11148 && INTVAL (XEXP (op0
, 1)) >= 0
11149 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11150 && mode_width
<= HOST_BITS_PER_WIDE_INT
11151 && (nonzero_bits (XEXP (op0
, 0), mode
)
11152 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11153 && (((unsigned HOST_WIDE_INT
) const_op
11154 + (GET_CODE (op0
) != LSHIFTRT
11155 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11158 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11160 /* If the shift was logical, then we must make the condition
11162 if (GET_CODE (op0
) == LSHIFTRT
)
11163 code
= unsigned_condition (code
);
11165 const_op
<<= INTVAL (XEXP (op0
, 1));
11166 op1
= GEN_INT (const_op
);
11167 op0
= XEXP (op0
, 0);
11171 /* If we are using this shift to extract just the sign bit, we
11172 can replace this with an LT or GE comparison. */
11174 && (equality_comparison_p
|| sign_bit_comparison_p
)
11175 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11176 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11179 op0
= XEXP (op0
, 0);
11180 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11192 /* Now make any compound operations involved in this comparison. Then,
11193 check for an outmost SUBREG on OP0 that is not doing anything or is
11194 paradoxical. The latter transformation must only be performed when
11195 it is known that the "extra" bits will be the same in op0 and op1 or
11196 that they don't matter. There are three cases to consider:
11198 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11199 care bits and we can assume they have any convenient value. So
11200 making the transformation is safe.
11202 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11203 In this case the upper bits of op0 are undefined. We should not make
11204 the simplification in that case as we do not know the contents of
11207 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11208 NIL. In that case we know those bits are zeros or ones. We must
11209 also be sure that they are the same as the upper bits of op1.
11211 We can never remove a SUBREG for a non-equality comparison because
11212 the sign bit is in a different place in the underlying object. */
11214 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11215 op1
= make_compound_operation (op1
, SET
);
11217 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11218 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11219 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11220 && (code
== NE
|| code
== EQ
))
11222 if (GET_MODE_SIZE (GET_MODE (op0
))
11223 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11225 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11227 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
11229 op0
= SUBREG_REG (op0
);
11230 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11233 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11234 <= HOST_BITS_PER_WIDE_INT
)
11235 && (nonzero_bits (SUBREG_REG (op0
),
11236 GET_MODE (SUBREG_REG (op0
)))
11237 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11239 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11241 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11242 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11243 op0
= SUBREG_REG (op0
), op1
= tem
;
11247 /* We now do the opposite procedure: Some machines don't have compare
11248 insns in all modes. If OP0's mode is an integer mode smaller than a
11249 word and we can't do a compare in that mode, see if there is a larger
11250 mode for which we can do the compare. There are a number of cases in
11251 which we can use the wider mode. */
11253 mode
= GET_MODE (op0
);
11254 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11255 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11256 && ! have_insn_for (COMPARE
, mode
))
11257 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11259 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11260 tmode
= GET_MODE_WIDER_MODE (tmode
))
11261 if (have_insn_for (COMPARE
, tmode
))
11265 /* If the only nonzero bits in OP0 and OP1 are those in the
11266 narrower mode and this is an equality or unsigned comparison,
11267 we can use the wider mode. Similarly for sign-extended
11268 values, in which case it is true for all comparisons. */
11269 zero_extended
= ((code
== EQ
|| code
== NE
11270 || code
== GEU
|| code
== GTU
11271 || code
== LEU
|| code
== LTU
)
11272 && (nonzero_bits (op0
, tmode
)
11273 & ~GET_MODE_MASK (mode
)) == 0
11274 && ((GET_CODE (op1
) == CONST_INT
11275 || (nonzero_bits (op1
, tmode
)
11276 & ~GET_MODE_MASK (mode
)) == 0)));
11279 || ((num_sign_bit_copies (op0
, tmode
)
11280 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11281 - GET_MODE_BITSIZE (mode
)))
11282 && (num_sign_bit_copies (op1
, tmode
)
11283 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11284 - GET_MODE_BITSIZE (mode
)))))
11286 /* If OP0 is an AND and we don't have an AND in MODE either,
11287 make a new AND in the proper mode. */
11288 if (GET_CODE (op0
) == AND
11289 && !have_insn_for (AND
, mode
))
11290 op0
= gen_binary (AND
, tmode
,
11291 gen_lowpart (tmode
,
11293 gen_lowpart (tmode
,
11296 op0
= gen_lowpart (tmode
, op0
);
11297 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11298 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11299 op1
= gen_lowpart (tmode
, op1
);
11303 /* If this is a test for negative, we can make an explicit
11304 test of the sign bit. */
11306 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11307 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11309 op0
= gen_binary (AND
, tmode
,
11310 gen_lowpart (tmode
, op0
),
11311 GEN_INT ((HOST_WIDE_INT
) 1
11312 << (GET_MODE_BITSIZE (mode
) - 1)));
11313 code
= (code
== LT
) ? NE
: EQ
;
11318 #ifdef CANONICALIZE_COMPARISON
11319 /* If this machine only supports a subset of valid comparisons, see if we
11320 can convert an unsupported one into a supported one. */
11321 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11330 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11331 searching backward. */
11332 static enum rtx_code
11333 combine_reversed_comparison_code (rtx exp
)
11335 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11338 if (code1
!= UNKNOWN
11339 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11341 /* Otherwise try and find where the condition codes were last set and
11343 x
= get_last_value (XEXP (exp
, 0));
11344 if (!x
|| GET_CODE (x
) != COMPARE
)
11346 return reversed_comparison_code_parts (GET_CODE (exp
),
11347 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11350 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11351 Return NULL_RTX in case we fail to do the reversal. */
11353 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11355 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11356 if (reversed_code
== UNKNOWN
)
11359 return gen_binary (reversed_code
, mode
, op0
, op1
);
11362 /* Utility function for following routine. Called when X is part of a value
11363 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11364 for each register mentioned. Similar to mention_regs in cse.c */
11367 update_table_tick (rtx x
)
11369 enum rtx_code code
= GET_CODE (x
);
11370 const char *fmt
= GET_RTX_FORMAT (code
);
11375 unsigned int regno
= REGNO (x
);
11376 unsigned int endregno
11377 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11378 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11381 for (r
= regno
; r
< endregno
; r
++)
11382 reg_last_set_table_tick
[r
] = label_tick
;
11387 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11388 /* Note that we can't have an "E" in values stored; see
11389 get_last_value_validate. */
11392 /* Check for identical subexpressions. If x contains
11393 identical subexpression we only have to traverse one of
11396 && (GET_RTX_CLASS (code
) == '2'
11397 || GET_RTX_CLASS (code
) == 'c'))
11399 /* Note that at this point x1 has already been
11401 rtx x0
= XEXP (x
, 0);
11402 rtx x1
= XEXP (x
, 1);
11404 /* If x0 and x1 are identical then there is no need to
11409 /* If x0 is identical to a subexpression of x1 then while
11410 processing x1, x0 has already been processed. Thus we
11411 are done with x. */
11412 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11413 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11414 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11417 /* If x1 is identical to a subexpression of x0 then we
11418 still have to process the rest of x0. */
11419 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11420 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11421 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11423 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11428 update_table_tick (XEXP (x
, i
));
11432 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11433 are saying that the register is clobbered and we no longer know its
11434 value. If INSN is zero, don't update reg_last_set; this is only permitted
11435 with VALUE also zero and is used to invalidate the register. */
11438 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11440 unsigned int regno
= REGNO (reg
);
11441 unsigned int endregno
11442 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11443 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
11446 /* If VALUE contains REG and we have a previous value for REG, substitute
11447 the previous value. */
11448 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11452 /* Set things up so get_last_value is allowed to see anything set up to
11454 subst_low_cuid
= INSN_CUID (insn
);
11455 tem
= get_last_value (reg
);
11457 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11458 it isn't going to be useful and will take a lot of time to process,
11459 so just use the CLOBBER. */
11463 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11464 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11465 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11466 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11467 tem
= XEXP (tem
, 0);
11469 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11473 /* For each register modified, show we don't know its value, that
11474 we don't know about its bitwise content, that its value has been
11475 updated, and that we don't know the location of the death of the
11477 for (i
= regno
; i
< endregno
; i
++)
11480 reg_last_set
[i
] = insn
;
11482 reg_last_set_value
[i
] = 0;
11483 reg_last_set_mode
[i
] = 0;
11484 reg_last_set_nonzero_bits
[i
] = 0;
11485 reg_last_set_sign_bit_copies
[i
] = 0;
11486 reg_last_death
[i
] = 0;
11489 /* Mark registers that are being referenced in this value. */
11491 update_table_tick (value
);
11493 /* Now update the status of each register being set.
11494 If someone is using this register in this block, set this register
11495 to invalid since we will get confused between the two lives in this
11496 basic block. This makes using this register always invalid. In cse, we
11497 scan the table to invalidate all entries using this register, but this
11498 is too much work for us. */
11500 for (i
= regno
; i
< endregno
; i
++)
11502 reg_last_set_label
[i
] = label_tick
;
11503 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11504 reg_last_set_invalid
[i
] = 1;
11506 reg_last_set_invalid
[i
] = 0;
11509 /* The value being assigned might refer to X (like in "x++;"). In that
11510 case, we must replace it with (clobber (const_int 0)) to prevent
11512 if (value
&& ! get_last_value_validate (&value
, insn
,
11513 reg_last_set_label
[regno
], 0))
11515 value
= copy_rtx (value
);
11516 if (! get_last_value_validate (&value
, insn
,
11517 reg_last_set_label
[regno
], 1))
11521 /* For the main register being modified, update the value, the mode, the
11522 nonzero bits, and the number of sign bit copies. */
11524 reg_last_set_value
[regno
] = value
;
11528 enum machine_mode mode
= GET_MODE (reg
);
11529 subst_low_cuid
= INSN_CUID (insn
);
11530 reg_last_set_mode
[regno
] = mode
;
11531 if (GET_MODE_CLASS (mode
) == MODE_INT
11532 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11533 mode
= nonzero_bits_mode
;
11534 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11535 reg_last_set_sign_bit_copies
[regno
]
11536 = num_sign_bit_copies (value
, GET_MODE (reg
));
11540 /* Called via note_stores from record_dead_and_set_regs to handle one
11541 SET or CLOBBER in an insn. DATA is the instruction in which the
11542 set is occurring. */
11545 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11547 rtx record_dead_insn
= (rtx
) data
;
11549 if (GET_CODE (dest
) == SUBREG
)
11550 dest
= SUBREG_REG (dest
);
11552 if (GET_CODE (dest
) == REG
)
11554 /* If we are setting the whole register, we know its value. Otherwise
11555 show that we don't know the value. We can handle SUBREG in
11557 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11558 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11559 else if (GET_CODE (setter
) == SET
11560 && GET_CODE (SET_DEST (setter
)) == SUBREG
11561 && SUBREG_REG (SET_DEST (setter
)) == dest
11562 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11563 && subreg_lowpart_p (SET_DEST (setter
)))
11564 record_value_for_reg (dest
, record_dead_insn
,
11565 gen_lowpart (GET_MODE (dest
),
11566 SET_SRC (setter
)));
11568 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11570 else if (GET_CODE (dest
) == MEM
11571 /* Ignore pushes, they clobber nothing. */
11572 && ! push_operand (dest
, GET_MODE (dest
)))
11573 mem_last_set
= INSN_CUID (record_dead_insn
);
11576 /* Update the records of when each REG was most recently set or killed
11577 for the things done by INSN. This is the last thing done in processing
11578 INSN in the combiner loop.
11580 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11581 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11582 and also the similar information mem_last_set (which insn most recently
11583 modified memory) and last_call_cuid (which insn was the most recent
11584 subroutine call). */
11587 record_dead_and_set_regs (rtx insn
)
11592 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11594 if (REG_NOTE_KIND (link
) == REG_DEAD
11595 && GET_CODE (XEXP (link
, 0)) == REG
)
11597 unsigned int regno
= REGNO (XEXP (link
, 0));
11598 unsigned int endregno
11599 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11600 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11603 for (i
= regno
; i
< endregno
; i
++)
11604 reg_last_death
[i
] = insn
;
11606 else if (REG_NOTE_KIND (link
) == REG_INC
)
11607 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11610 if (GET_CODE (insn
) == CALL_INSN
)
11612 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11613 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11615 reg_last_set_value
[i
] = 0;
11616 reg_last_set_mode
[i
] = 0;
11617 reg_last_set_nonzero_bits
[i
] = 0;
11618 reg_last_set_sign_bit_copies
[i
] = 0;
11619 reg_last_death
[i
] = 0;
11622 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11624 /* Don't bother recording what this insn does. It might set the
11625 return value register, but we can't combine into a call
11626 pattern anyway, so there's no point trying (and it may cause
11627 a crash, if e.g. we wind up asking for last_set_value of a
11628 SUBREG of the return value register). */
11632 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11635 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11636 register present in the SUBREG, so for each such SUBREG go back and
11637 adjust nonzero and sign bit information of the registers that are
11638 known to have some zero/sign bits set.
11640 This is needed because when combine blows the SUBREGs away, the
11641 information on zero/sign bits is lost and further combines can be
11642 missed because of that. */
11645 record_promoted_value (rtx insn
, rtx subreg
)
11648 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11649 enum machine_mode mode
= GET_MODE (subreg
);
11651 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11654 for (links
= LOG_LINKS (insn
); links
;)
11656 insn
= XEXP (links
, 0);
11657 set
= single_set (insn
);
11659 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11660 || REGNO (SET_DEST (set
)) != regno
11661 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11663 links
= XEXP (links
, 1);
11667 if (reg_last_set
[regno
] == insn
)
11669 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11670 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11673 if (GET_CODE (SET_SRC (set
)) == REG
)
11675 regno
= REGNO (SET_SRC (set
));
11676 links
= LOG_LINKS (insn
);
11683 /* Scan X for promoted SUBREGs. For each one found,
11684 note what it implies to the registers used in it. */
11687 check_promoted_subreg (rtx insn
, rtx x
)
11689 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11690 && GET_CODE (SUBREG_REG (x
)) == REG
)
11691 record_promoted_value (insn
, x
);
11694 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11697 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11701 check_promoted_subreg (insn
, XEXP (x
, i
));
11705 if (XVEC (x
, i
) != 0)
11706 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11707 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11713 /* Utility routine for the following function. Verify that all the registers
11714 mentioned in *LOC are valid when *LOC was part of a value set when
11715 label_tick == TICK. Return 0 if some are not.
11717 If REPLACE is nonzero, replace the invalid reference with
11718 (clobber (const_int 0)) and return 1. This replacement is useful because
11719 we often can get useful information about the form of a value (e.g., if
11720 it was produced by a shift that always produces -1 or 0) even though
11721 we don't know exactly what registers it was produced from. */
11724 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11727 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11728 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11731 if (GET_CODE (x
) == REG
)
11733 unsigned int regno
= REGNO (x
);
11734 unsigned int endregno
11735 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11736 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11739 for (j
= regno
; j
< endregno
; j
++)
11740 if (reg_last_set_invalid
[j
]
11741 /* If this is a pseudo-register that was only set once and not
11742 live at the beginning of the function, it is always valid. */
11743 || (! (regno
>= FIRST_PSEUDO_REGISTER
11744 && REG_N_SETS (regno
) == 1
11745 && (! REGNO_REG_SET_P
11746 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11747 && reg_last_set_label
[j
] > tick
))
11750 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11756 /* If this is a memory reference, make sure that there were
11757 no stores after it that might have clobbered the value. We don't
11758 have alias info, so we assume any store invalidates it. */
11759 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11760 && INSN_CUID (insn
) <= mem_last_set
)
11763 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11767 for (i
= 0; i
< len
; i
++)
11771 /* Check for identical subexpressions. If x contains
11772 identical subexpression we only have to traverse one of
11775 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11776 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11778 /* Note that at this point x0 has already been checked
11779 and found valid. */
11780 rtx x0
= XEXP (x
, 0);
11781 rtx x1
= XEXP (x
, 1);
11783 /* If x0 and x1 are identical then x is also valid. */
11787 /* If x1 is identical to a subexpression of x0 then
11788 while checking x0, x1 has already been checked. Thus
11789 it is valid and so as x. */
11790 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11791 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11792 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11795 /* If x0 is identical to a subexpression of x1 then x is
11796 valid iff the rest of x1 is valid. */
11797 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11798 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11799 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11801 get_last_value_validate (&XEXP (x1
,
11802 x0
== XEXP (x1
, 0) ? 1 : 0),
11803 insn
, tick
, replace
);
11806 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11810 /* Don't bother with these. They shouldn't occur anyway. */
11811 else if (fmt
[i
] == 'E')
11815 /* If we haven't found a reason for it to be invalid, it is valid. */
11819 /* Get the last value assigned to X, if known. Some registers
11820 in the value may be replaced with (clobber (const_int 0)) if their value
11821 is known longer known reliably. */
11824 get_last_value (rtx x
)
11826 unsigned int regno
;
11829 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11830 then convert it to the desired mode. If this is a paradoxical SUBREG,
11831 we cannot predict what values the "extra" bits might have. */
11832 if (GET_CODE (x
) == SUBREG
11833 && subreg_lowpart_p (x
)
11834 && (GET_MODE_SIZE (GET_MODE (x
))
11835 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11836 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11837 return gen_lowpart (GET_MODE (x
), value
);
11839 if (GET_CODE (x
) != REG
)
11843 value
= reg_last_set_value
[regno
];
11845 /* If we don't have a value, or if it isn't for this basic block and
11846 it's either a hard register, set more than once, or it's a live
11847 at the beginning of the function, return 0.
11849 Because if it's not live at the beginning of the function then the reg
11850 is always set before being used (is never used without being set).
11851 And, if it's set only once, and it's always set before use, then all
11852 uses must have the same last value, even if it's not from this basic
11856 || (reg_last_set_label
[regno
] != label_tick
11857 && (regno
< FIRST_PSEUDO_REGISTER
11858 || REG_N_SETS (regno
) != 1
11859 || (REGNO_REG_SET_P
11860 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11863 /* If the value was set in a later insn than the ones we are processing,
11864 we can't use it even if the register was only set once. */
11865 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11868 /* If the value has all its registers valid, return it. */
11869 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11870 reg_last_set_label
[regno
], 0))
11873 /* Otherwise, make a copy and replace any invalid register with
11874 (clobber (const_int 0)). If that fails for some reason, return 0. */
11876 value
= copy_rtx (value
);
11877 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11878 reg_last_set_label
[regno
], 1))
11884 /* Return nonzero if expression X refers to a REG or to memory
11885 that is set in an instruction more recent than FROM_CUID. */
11888 use_crosses_set_p (rtx x
, int from_cuid
)
11892 enum rtx_code code
= GET_CODE (x
);
11896 unsigned int regno
= REGNO (x
);
11897 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11898 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11900 #ifdef PUSH_ROUNDING
11901 /* Don't allow uses of the stack pointer to be moved,
11902 because we don't know whether the move crosses a push insn. */
11903 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11906 for (; regno
< endreg
; regno
++)
11907 if (reg_last_set
[regno
]
11908 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11913 if (code
== MEM
&& mem_last_set
> from_cuid
)
11916 fmt
= GET_RTX_FORMAT (code
);
11918 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11923 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11924 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11927 else if (fmt
[i
] == 'e'
11928 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11934 /* Define three variables used for communication between the following
11937 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11938 static int reg_dead_flag
;
11940 /* Function called via note_stores from reg_dead_at_p.
11942 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11943 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11946 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11948 unsigned int regno
, endregno
;
11950 if (GET_CODE (dest
) != REG
)
11953 regno
= REGNO (dest
);
11954 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11955 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11957 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11958 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11961 /* Return nonzero if REG is known to be dead at INSN.
11963 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11964 referencing REG, it is dead. If we hit a SET referencing REG, it is
11965 live. Otherwise, see if it is live or dead at the start of the basic
11966 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11967 must be assumed to be always live. */
11970 reg_dead_at_p (rtx reg
, rtx insn
)
11975 /* Set variables for reg_dead_at_p_1. */
11976 reg_dead_regno
= REGNO (reg
);
11977 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11978 ? hard_regno_nregs
[reg_dead_regno
]
11984 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11985 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11987 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11988 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11992 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11993 beginning of function. */
11994 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11995 insn
= prev_nonnote_insn (insn
))
11997 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11999 return reg_dead_flag
== 1 ? 1 : 0;
12001 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12005 /* Get the basic block that we were in. */
12007 block
= ENTRY_BLOCK_PTR
->next_bb
;
12010 FOR_EACH_BB (block
)
12011 if (insn
== BB_HEAD (block
))
12014 if (block
== EXIT_BLOCK_PTR
)
12018 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12019 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
12025 /* Note hard registers in X that are used. This code is similar to
12026 that in flow.c, but much simpler since we don't care about pseudos. */
12029 mark_used_regs_combine (rtx x
)
12031 RTX_CODE code
= GET_CODE (x
);
12032 unsigned int regno
;
12045 case ADDR_DIFF_VEC
:
12048 /* CC0 must die in the insn after it is set, so we don't need to take
12049 special note of it here. */
12055 /* If we are clobbering a MEM, mark any hard registers inside the
12056 address as used. */
12057 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12058 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12063 /* A hard reg in a wide mode may really be multiple registers.
12064 If so, mark all of them just like the first. */
12065 if (regno
< FIRST_PSEUDO_REGISTER
)
12067 unsigned int endregno
, r
;
12069 /* None of this applies to the stack, frame or arg pointers. */
12070 if (regno
== STACK_POINTER_REGNUM
12071 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12072 || regno
== HARD_FRAME_POINTER_REGNUM
12074 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12075 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12077 || regno
== FRAME_POINTER_REGNUM
)
12080 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12081 for (r
= regno
; r
< endregno
; r
++)
12082 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12088 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12090 rtx testreg
= SET_DEST (x
);
12092 while (GET_CODE (testreg
) == SUBREG
12093 || GET_CODE (testreg
) == ZERO_EXTRACT
12094 || GET_CODE (testreg
) == SIGN_EXTRACT
12095 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12096 testreg
= XEXP (testreg
, 0);
12098 if (GET_CODE (testreg
) == MEM
)
12099 mark_used_regs_combine (XEXP (testreg
, 0));
12101 mark_used_regs_combine (SET_SRC (x
));
12109 /* Recursively scan the operands of this expression. */
12112 const char *fmt
= GET_RTX_FORMAT (code
);
12114 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12117 mark_used_regs_combine (XEXP (x
, i
));
12118 else if (fmt
[i
] == 'E')
12122 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12123 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12129 /* Remove register number REGNO from the dead registers list of INSN.
12131 Return the note used to record the death, if there was one. */
12134 remove_death (unsigned int regno
, rtx insn
)
12136 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12140 REG_N_DEATHS (regno
)--;
12141 remove_note (insn
, note
);
12147 /* For each register (hardware or pseudo) used within expression X, if its
12148 death is in an instruction with cuid between FROM_CUID (inclusive) and
12149 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12150 list headed by PNOTES.
12152 That said, don't move registers killed by maybe_kill_insn.
12154 This is done when X is being merged by combination into TO_INSN. These
12155 notes will then be distributed as needed. */
12158 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12163 enum rtx_code code
= GET_CODE (x
);
12167 unsigned int regno
= REGNO (x
);
12168 rtx where_dead
= reg_last_death
[regno
];
12169 rtx before_dead
, after_dead
;
12171 /* Don't move the register if it gets killed in between from and to. */
12172 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12173 && ! reg_referenced_p (x
, maybe_kill_insn
))
12176 /* WHERE_DEAD could be a USE insn made by combine, so first we
12177 make sure that we have insns with valid INSN_CUID values. */
12178 before_dead
= where_dead
;
12179 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12180 before_dead
= PREV_INSN (before_dead
);
12182 after_dead
= where_dead
;
12183 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12184 after_dead
= NEXT_INSN (after_dead
);
12186 if (before_dead
&& after_dead
12187 && INSN_CUID (before_dead
) >= from_cuid
12188 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12189 || (where_dead
!= after_dead
12190 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12192 rtx note
= remove_death (regno
, where_dead
);
12194 /* It is possible for the call above to return 0. This can occur
12195 when reg_last_death points to I2 or I1 that we combined with.
12196 In that case make a new note.
12198 We must also check for the case where X is a hard register
12199 and NOTE is a death note for a range of hard registers
12200 including X. In that case, we must put REG_DEAD notes for
12201 the remaining registers in place of NOTE. */
12203 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12204 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12205 > GET_MODE_SIZE (GET_MODE (x
))))
12207 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12208 unsigned int deadend
12209 = (deadregno
+ hard_regno_nregs
[deadregno
]
12210 [GET_MODE (XEXP (note
, 0))]);
12211 unsigned int ourend
12212 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12215 for (i
= deadregno
; i
< deadend
; i
++)
12216 if (i
< regno
|| i
>= ourend
)
12217 REG_NOTES (where_dead
)
12218 = gen_rtx_EXPR_LIST (REG_DEAD
,
12220 REG_NOTES (where_dead
));
12223 /* If we didn't find any note, or if we found a REG_DEAD note that
12224 covers only part of the given reg, and we have a multi-reg hard
12225 register, then to be safe we must check for REG_DEAD notes
12226 for each register other than the first. They could have
12227 their own REG_DEAD notes lying around. */
12228 else if ((note
== 0
12230 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12231 < GET_MODE_SIZE (GET_MODE (x
)))))
12232 && regno
< FIRST_PSEUDO_REGISTER
12233 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12235 unsigned int ourend
12236 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12237 unsigned int i
, offset
;
12241 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12245 for (i
= regno
+ offset
; i
< ourend
; i
++)
12246 move_deaths (regno_reg_rtx
[i
],
12247 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12250 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12252 XEXP (note
, 1) = *pnotes
;
12256 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12258 REG_N_DEATHS (regno
)++;
12264 else if (GET_CODE (x
) == SET
)
12266 rtx dest
= SET_DEST (x
);
12268 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12270 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12271 that accesses one word of a multi-word item, some
12272 piece of everything register in the expression is used by
12273 this insn, so remove any old death. */
12274 /* ??? So why do we test for equality of the sizes? */
12276 if (GET_CODE (dest
) == ZERO_EXTRACT
12277 || GET_CODE (dest
) == STRICT_LOW_PART
12278 || (GET_CODE (dest
) == SUBREG
12279 && (((GET_MODE_SIZE (GET_MODE (dest
))
12280 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12281 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12282 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12284 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12288 /* If this is some other SUBREG, we know it replaces the entire
12289 value, so use that as the destination. */
12290 if (GET_CODE (dest
) == SUBREG
)
12291 dest
= SUBREG_REG (dest
);
12293 /* If this is a MEM, adjust deaths of anything used in the address.
12294 For a REG (the only other possibility), the entire value is
12295 being replaced so the old value is not used in this insn. */
12297 if (GET_CODE (dest
) == MEM
)
12298 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12303 else if (GET_CODE (x
) == CLOBBER
)
12306 len
= GET_RTX_LENGTH (code
);
12307 fmt
= GET_RTX_FORMAT (code
);
12309 for (i
= 0; i
< len
; i
++)
12314 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12315 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12318 else if (fmt
[i
] == 'e')
12319 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12323 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12324 pattern of an insn. X must be a REG. */
12327 reg_bitfield_target_p (rtx x
, rtx body
)
12331 if (GET_CODE (body
) == SET
)
12333 rtx dest
= SET_DEST (body
);
12335 unsigned int regno
, tregno
, endregno
, endtregno
;
12337 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12338 target
= XEXP (dest
, 0);
12339 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12340 target
= SUBREG_REG (XEXP (dest
, 0));
12344 if (GET_CODE (target
) == SUBREG
)
12345 target
= SUBREG_REG (target
);
12347 if (GET_CODE (target
) != REG
)
12350 tregno
= REGNO (target
), regno
= REGNO (x
);
12351 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12352 return target
== x
;
12354 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
12355 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12357 return endregno
> tregno
&& regno
< endtregno
;
12360 else if (GET_CODE (body
) == PARALLEL
)
12361 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12362 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12368 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12369 as appropriate. I3 and I2 are the insns resulting from the combination
12370 insns including FROM (I2 may be zero).
12372 Each note in the list is either ignored or placed on some insns, depending
12373 on the type of note. */
12376 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12378 rtx note
, next_note
;
12381 for (note
= notes
; note
; note
= next_note
)
12383 rtx place
= 0, place2
= 0;
12385 /* If this NOTE references a pseudo register, ensure it references
12386 the latest copy of that register. */
12387 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12388 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12389 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12391 next_note
= XEXP (note
, 1);
12392 switch (REG_NOTE_KIND (note
))
12396 /* Doesn't matter much where we put this, as long as it's somewhere.
12397 It is preferable to keep these notes on branches, which is most
12398 likely to be i3. */
12402 case REG_VALUE_PROFILE
:
12403 /* Just get rid of this note, as it is unused later anyway. */
12406 case REG_VTABLE_REF
:
12407 /* ??? Should remain with *a particular* memory load. Given the
12408 nature of vtable data, the last insn seems relatively safe. */
12412 case REG_NON_LOCAL_GOTO
:
12413 if (GET_CODE (i3
) == JUMP_INSN
)
12415 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12421 case REG_EH_REGION
:
12422 /* These notes must remain with the call or trapping instruction. */
12423 if (GET_CODE (i3
) == CALL_INSN
)
12425 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12427 else if (flag_non_call_exceptions
)
12429 if (may_trap_p (i3
))
12431 else if (i2
&& may_trap_p (i2
))
12433 /* ??? Otherwise assume we've combined things such that we
12434 can now prove that the instructions can't trap. Drop the
12435 note in this case. */
12441 case REG_ALWAYS_RETURN
:
12444 /* These notes must remain with the call. It should not be
12445 possible for both I2 and I3 to be a call. */
12446 if (GET_CODE (i3
) == CALL_INSN
)
12448 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12455 /* Any clobbers for i3 may still exist, and so we must process
12456 REG_UNUSED notes from that insn.
12458 Any clobbers from i2 or i1 can only exist if they were added by
12459 recog_for_combine. In that case, recog_for_combine created the
12460 necessary REG_UNUSED notes. Trying to keep any original
12461 REG_UNUSED notes from these insns can cause incorrect output
12462 if it is for the same register as the original i3 dest.
12463 In that case, we will notice that the register is set in i3,
12464 and then add a REG_UNUSED note for the destination of i3, which
12465 is wrong. However, it is possible to have REG_UNUSED notes from
12466 i2 or i1 for register which were both used and clobbered, so
12467 we keep notes from i2 or i1 if they will turn into REG_DEAD
12470 /* If this register is set or clobbered in I3, put the note there
12471 unless there is one already. */
12472 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12474 if (from_insn
!= i3
)
12477 if (! (GET_CODE (XEXP (note
, 0)) == REG
12478 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12479 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12482 /* Otherwise, if this register is used by I3, then this register
12483 now dies here, so we must put a REG_DEAD note here unless there
12485 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12486 && ! (GET_CODE (XEXP (note
, 0)) == REG
12487 ? find_regno_note (i3
, REG_DEAD
,
12488 REGNO (XEXP (note
, 0)))
12489 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12491 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12499 /* These notes say something about results of an insn. We can
12500 only support them if they used to be on I3 in which case they
12501 remain on I3. Otherwise they are ignored.
12503 If the note refers to an expression that is not a constant, we
12504 must also ignore the note since we cannot tell whether the
12505 equivalence is still true. It might be possible to do
12506 slightly better than this (we only have a problem if I2DEST
12507 or I1DEST is present in the expression), but it doesn't
12508 seem worth the trouble. */
12510 if (from_insn
== i3
12511 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12516 case REG_NO_CONFLICT
:
12517 /* These notes say something about how a register is used. They must
12518 be present on any use of the register in I2 or I3. */
12519 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12522 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12532 /* This can show up in several ways -- either directly in the
12533 pattern, or hidden off in the constant pool with (or without?)
12534 a REG_EQUAL note. */
12535 /* ??? Ignore the without-reg_equal-note problem for now. */
12536 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12537 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12538 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12539 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12543 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12544 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12545 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12546 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12554 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12555 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12556 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12558 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12560 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12561 LABEL_NUSES (JUMP_LABEL (place
))--;
12564 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12566 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12568 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12569 LABEL_NUSES (JUMP_LABEL (place2
))--;
12575 /* This note says something about the value of a register prior
12576 to the execution of an insn. It is too much trouble to see
12577 if the note is still correct in all situations. It is better
12578 to simply delete it. */
12582 /* If the insn previously containing this note still exists,
12583 put it back where it was. Otherwise move it to the previous
12584 insn. Adjust the corresponding REG_LIBCALL note. */
12585 if (GET_CODE (from_insn
) != NOTE
)
12589 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12590 place
= prev_real_insn (from_insn
);
12592 XEXP (tem
, 0) = place
;
12593 /* If we're deleting the last remaining instruction of a
12594 libcall sequence, don't add the notes. */
12595 else if (XEXP (note
, 0) == from_insn
)
12601 /* This is handled similarly to REG_RETVAL. */
12602 if (GET_CODE (from_insn
) != NOTE
)
12606 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12607 place
= next_real_insn (from_insn
);
12609 XEXP (tem
, 0) = place
;
12610 /* If we're deleting the last remaining instruction of a
12611 libcall sequence, don't add the notes. */
12612 else if (XEXP (note
, 0) == from_insn
)
12618 /* If the register is used as an input in I3, it dies there.
12619 Similarly for I2, if it is nonzero and adjacent to I3.
12621 If the register is not used as an input in either I3 or I2
12622 and it is not one of the registers we were supposed to eliminate,
12623 there are two possibilities. We might have a non-adjacent I2
12624 or we might have somehow eliminated an additional register
12625 from a computation. For example, we might have had A & B where
12626 we discover that B will always be zero. In this case we will
12627 eliminate the reference to A.
12629 In both cases, we must search to see if we can find a previous
12630 use of A and put the death note there. */
12633 && GET_CODE (from_insn
) == CALL_INSN
12634 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12636 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12638 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12639 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12644 basic_block bb
= this_basic_block
;
12646 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12648 if (! INSN_P (tem
))
12650 if (tem
== BB_HEAD (bb
))
12655 /* If the register is being set at TEM, see if that is all
12656 TEM is doing. If so, delete TEM. Otherwise, make this
12657 into a REG_UNUSED note instead. */
12658 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12660 rtx set
= single_set (tem
);
12661 rtx inner_dest
= 0;
12663 rtx cc0_setter
= NULL_RTX
;
12667 for (inner_dest
= SET_DEST (set
);
12668 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12669 || GET_CODE (inner_dest
) == SUBREG
12670 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12671 inner_dest
= XEXP (inner_dest
, 0))
12674 /* Verify that it was the set, and not a clobber that
12675 modified the register.
12677 CC0 targets must be careful to maintain setter/user
12678 pairs. If we cannot delete the setter due to side
12679 effects, mark the user with an UNUSED note instead
12682 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12683 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12685 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12686 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12687 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12691 /* Move the notes and links of TEM elsewhere.
12692 This might delete other dead insns recursively.
12693 First set the pattern to something that won't use
12695 rtx old_notes
= REG_NOTES (tem
);
12697 PATTERN (tem
) = pc_rtx
;
12698 REG_NOTES (tem
) = NULL
;
12700 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12701 distribute_links (LOG_LINKS (tem
));
12703 PUT_CODE (tem
, NOTE
);
12704 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12705 NOTE_SOURCE_FILE (tem
) = 0;
12708 /* Delete the setter too. */
12711 PATTERN (cc0_setter
) = pc_rtx
;
12712 old_notes
= REG_NOTES (cc0_setter
);
12713 REG_NOTES (cc0_setter
) = NULL
;
12715 distribute_notes (old_notes
, cc0_setter
,
12716 cc0_setter
, NULL_RTX
);
12717 distribute_links (LOG_LINKS (cc0_setter
));
12719 PUT_CODE (cc0_setter
, NOTE
);
12720 NOTE_LINE_NUMBER (cc0_setter
)
12721 = NOTE_INSN_DELETED
;
12722 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12726 /* If the register is both set and used here, put the
12727 REG_DEAD note here, but place a REG_UNUSED note
12728 here too unless there already is one. */
12729 else if (reg_referenced_p (XEXP (note
, 0),
12734 if (! find_regno_note (tem
, REG_UNUSED
,
12735 REGNO (XEXP (note
, 0))))
12737 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12742 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12744 /* If there isn't already a REG_UNUSED note, put one
12746 if (! find_regno_note (tem
, REG_UNUSED
,
12747 REGNO (XEXP (note
, 0))))
12752 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12753 || (GET_CODE (tem
) == CALL_INSN
12754 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12758 /* If we are doing a 3->2 combination, and we have a
12759 register which formerly died in i3 and was not used
12760 by i2, which now no longer dies in i3 and is used in
12761 i2 but does not die in i2, and place is between i2
12762 and i3, then we may need to move a link from place to
12764 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12765 && INSN_CUID (place
) > INSN_CUID (i2
)
12767 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12768 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12770 rtx links
= LOG_LINKS (place
);
12771 LOG_LINKS (place
) = 0;
12772 distribute_links (links
);
12777 if (tem
== BB_HEAD (bb
))
12781 /* We haven't found an insn for the death note and it
12782 is still a REG_DEAD note, but we have hit the beginning
12783 of the block. If the existing life info says the reg
12784 was dead, there's nothing left to do. Otherwise, we'll
12785 need to do a global life update after combine. */
12786 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12787 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12788 REGNO (XEXP (note
, 0))))
12789 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12792 /* If the register is set or already dead at PLACE, we needn't do
12793 anything with this note if it is still a REG_DEAD note.
12794 We can here if it is set at all, not if is it totally replace,
12795 which is what `dead_or_set_p' checks, so also check for it being
12798 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12800 unsigned int regno
= REGNO (XEXP (note
, 0));
12802 /* Similarly, if the instruction on which we want to place
12803 the note is a noop, we'll need do a global live update
12804 after we remove them in delete_noop_moves. */
12805 if (noop_move_p (place
))
12806 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12808 if (dead_or_set_p (place
, XEXP (note
, 0))
12809 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12811 /* Unless the register previously died in PLACE, clear
12812 reg_last_death. [I no longer understand why this is
12814 if (reg_last_death
[regno
] != place
)
12815 reg_last_death
[regno
] = 0;
12819 reg_last_death
[regno
] = place
;
12821 /* If this is a death note for a hard reg that is occupying
12822 multiple registers, ensure that we are still using all
12823 parts of the object. If we find a piece of the object
12824 that is unused, we must arrange for an appropriate REG_DEAD
12825 note to be added for it. However, we can't just emit a USE
12826 and tag the note to it, since the register might actually
12827 be dead; so we recourse, and the recursive call then finds
12828 the previous insn that used this register. */
12830 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12831 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12833 unsigned int endregno
12834 = regno
+ hard_regno_nregs
[regno
]
12835 [GET_MODE (XEXP (note
, 0))];
12839 for (i
= regno
; i
< endregno
; i
++)
12840 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12841 && ! find_regno_fusage (place
, USE
, i
))
12842 || dead_or_set_regno_p (place
, i
))
12847 /* Put only REG_DEAD notes for pieces that are
12848 not already dead or set. */
12850 for (i
= regno
; i
< endregno
;
12851 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12853 rtx piece
= regno_reg_rtx
[i
];
12854 basic_block bb
= this_basic_block
;
12856 if (! dead_or_set_p (place
, piece
)
12857 && ! reg_bitfield_target_p (piece
,
12861 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12863 distribute_notes (new_note
, place
, place
,
12866 else if (! refers_to_regno_p (i
, i
+ 1,
12867 PATTERN (place
), 0)
12868 && ! find_regno_fusage (place
, USE
, i
))
12869 for (tem
= PREV_INSN (place
); ;
12870 tem
= PREV_INSN (tem
))
12872 if (! INSN_P (tem
))
12874 if (tem
== BB_HEAD (bb
))
12876 SET_BIT (refresh_blocks
,
12877 this_basic_block
->index
);
12882 if (dead_or_set_p (tem
, piece
)
12883 || reg_bitfield_target_p (piece
,
12887 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12902 /* Any other notes should not be present at this point in the
12909 XEXP (note
, 1) = REG_NOTES (place
);
12910 REG_NOTES (place
) = note
;
12912 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12913 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12914 && GET_CODE (XEXP (note
, 0)) == REG
)
12915 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12919 if ((REG_NOTE_KIND (note
) == REG_DEAD
12920 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12921 && GET_CODE (XEXP (note
, 0)) == REG
)
12922 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12924 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12925 REG_NOTE_KIND (note
),
12927 REG_NOTES (place2
));
12932 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12933 I3, I2, and I1 to new locations. This is also called to add a link
12934 pointing at I3 when I3's destination is changed. */
12937 distribute_links (rtx links
)
12939 rtx link
, next_link
;
12941 for (link
= links
; link
; link
= next_link
)
12947 next_link
= XEXP (link
, 1);
12949 /* If the insn that this link points to is a NOTE or isn't a single
12950 set, ignore it. In the latter case, it isn't clear what we
12951 can do other than ignore the link, since we can't tell which
12952 register it was for. Such links wouldn't be used by combine
12955 It is not possible for the destination of the target of the link to
12956 have been changed by combine. The only potential of this is if we
12957 replace I3, I2, and I1 by I3 and I2. But in that case the
12958 destination of I2 also remains unchanged. */
12960 if (GET_CODE (XEXP (link
, 0)) == NOTE
12961 || (set
= single_set (XEXP (link
, 0))) == 0)
12964 reg
= SET_DEST (set
);
12965 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12966 || GET_CODE (reg
) == SIGN_EXTRACT
12967 || GET_CODE (reg
) == STRICT_LOW_PART
)
12968 reg
= XEXP (reg
, 0);
12970 /* A LOG_LINK is defined as being placed on the first insn that uses
12971 a register and points to the insn that sets the register. Start
12972 searching at the next insn after the target of the link and stop
12973 when we reach a set of the register or the end of the basic block.
12975 Note that this correctly handles the link that used to point from
12976 I3 to I2. Also note that not much searching is typically done here
12977 since most links don't point very far away. */
12979 for (insn
= NEXT_INSN (XEXP (link
, 0));
12980 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12981 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12982 insn
= NEXT_INSN (insn
))
12983 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12985 if (reg_referenced_p (reg
, PATTERN (insn
)))
12989 else if (GET_CODE (insn
) == CALL_INSN
12990 && find_reg_fusage (insn
, USE
, reg
))
12995 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12998 /* If we found a place to put the link, place it there unless there
12999 is already a link to the same insn as LINK at that point. */
13005 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13006 if (XEXP (link2
, 0) == XEXP (link
, 0))
13011 XEXP (link
, 1) = LOG_LINKS (place
);
13012 LOG_LINKS (place
) = link
;
13014 /* Set added_links_insn to the earliest insn we added a
13016 if (added_links_insn
== 0
13017 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
13018 added_links_insn
= place
;
13024 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13027 insn_cuid (rtx insn
)
13029 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13030 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13031 insn
= NEXT_INSN (insn
);
13033 if (INSN_UID (insn
) > max_uid_cuid
)
13036 return INSN_CUID (insn
);
13040 dump_combine_stats (FILE *file
)
13044 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13045 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13049 dump_combine_total_stats (FILE *file
)
13053 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13054 total_attempts
, total_merges
, total_extras
, total_successes
);