1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
85 #include "hard-reg-set.h"
86 #include "basic-block.h"
87 #include "insn-config.h"
89 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
91 #include "insn-attr.h"
96 /* It is not safe to use ordinary gen_lowpart in combine.
97 Use gen_lowpart_for_combine instead. See comments there. */
98 #define gen_lowpart dont_use_gen_lowpart_you_dummy
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts
;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges
;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras
;
112 /* Number of instructions combined in this function. */
114 static int combine_successes
;
116 /* Totals over entire compilation. */
118 static int total_attempts
, total_merges
, total_extras
, total_successes
;
121 /* Vector mapping INSN_UIDs to cuids.
122 The cuids are like uids but increase monotonically always.
123 Combine always uses cuids so that it can compare them.
124 But actually renumbering the uids, which we used to do,
125 proves to be a bad idea because it makes it hard to compare
126 the dumps produced by earlier passes with those from later passes. */
128 static int *uid_cuid
;
129 static int max_uid_cuid
;
131 /* Get the cuid of an insn. */
133 #define INSN_CUID(INSN) \
134 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
136 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
137 BITS_PER_WORD would invoke undefined behavior. Work around it. */
139 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
140 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
142 #define nonzero_bits(X, M) \
143 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
145 #define num_sign_bit_copies(X, M) \
146 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
148 /* Maximum register number, which is the size of the tables below. */
150 static unsigned int combine_max_regno
;
152 /* Record last point of death of (hard or pseudo) register n. */
154 static rtx
*reg_last_death
;
156 /* Record last point of modification of (hard or pseudo) register n. */
158 static rtx
*reg_last_set
;
160 /* Record the cuid of the last insn that invalidated memory
161 (anything that writes memory, and subroutine calls, but not pushes). */
163 static int mem_last_set
;
165 /* Record the cuid of the last CALL_INSN
166 so we can tell whether a potential combination crosses any calls. */
168 static int last_call_cuid
;
170 /* When `subst' is called, this is the insn that is being modified
171 (by combining in a previous insn). The PATTERN of this insn
172 is still the old pattern partially modified and it should not be
173 looked at, but this may be used to examine the successors of the insn
174 to judge whether a simplification is valid. */
176 static rtx subst_insn
;
178 /* This is the lowest CUID that `subst' is currently dealing with.
179 get_last_value will not return a value if the register was set at or
180 after this CUID. If not for this mechanism, we could get confused if
181 I2 or I1 in try_combine were an insn that used the old value of a register
182 to obtain a new value. In that case, we might erroneously get the
183 new value of the register when we wanted the old one. */
185 static int subst_low_cuid
;
187 /* This contains any hard registers that are used in newpat; reg_dead_at_p
188 must consider all these registers to be always live. */
190 static HARD_REG_SET newpat_used_regs
;
192 /* This is an insn to which a LOG_LINKS entry has been added. If this
193 insn is the earlier than I2 or I3, combine should rescan starting at
196 static rtx added_links_insn
;
198 /* Basic block in which we are performing combines. */
199 static basic_block this_basic_block
;
201 /* A bitmap indicating which blocks had registers go dead at entry.
202 After combine, we'll need to re-do global life analysis with
203 those blocks as starting points. */
204 static sbitmap refresh_blocks
;
206 /* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if an
208 operation being processed is redundant given a prior operation performed
209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.
212 We use an approach similar to that used by cse, but change it in the
215 (1) We do not want to reinitialize at each label.
216 (2) It is useful, but not critical, to know the actual value assigned
217 to a register. Often just its form is helpful.
219 Therefore, we maintain the following arrays:
221 reg_last_set_value the last value assigned
222 reg_last_set_label records the value of label_tick when the
223 register was assigned
224 reg_last_set_table_tick records the value of label_tick when a
225 value using the register is assigned
226 reg_last_set_invalid set to nonzero when it is not valid
227 to use the value of this register in some
230 To understand the usage of these tables, it is important to understand
231 the distinction between the value in reg_last_set_value being valid
232 and the register being validly contained in some other expression in the
235 Entry I in reg_last_set_value is valid if it is nonzero, and either
236 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
238 Register I may validly appear in any expression returned for the value
239 of another register if reg_n_sets[i] is 1. It may also appear in the
240 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
241 reg_last_set_invalid[j] is zero.
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
247 reg_last_set_invalid[i] is set nonzero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
250 /* Record last value assigned to (hard or pseudo) register n. */
252 static rtx
*reg_last_set_value
;
254 /* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
257 static int *reg_last_set_label
;
259 /* Record the value of label_tick when an expression involving register n
260 is placed in reg_last_set_value. */
262 static int *reg_last_set_table_tick
;
264 /* Set nonzero if references to register n in expressions should not be
267 static char *reg_last_set_invalid
;
269 /* Incremented for each label. */
271 static int label_tick
;
273 /* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
278 We record in the following array what we know about the nonzero
279 bits of a register, specifically which bits are known to be zero.
281 If an entry is zero, it means that we don't know anything special. */
283 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
285 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
286 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
288 static enum machine_mode nonzero_bits_mode
;
290 /* Nonzero if we know that a register has some leading bits that are always
291 equal to the sign bit. */
293 static unsigned char *reg_sign_bit_copies
;
295 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
296 It is zero while computing them and after combine has completed. This
297 former test prevents propagating values based on previously set values,
298 which can be incorrect if a variable is modified in a loop. */
300 static int nonzero_sign_valid
;
302 /* These arrays are maintained in parallel with reg_last_set_value
303 and are used to store the mode in which the register was last set,
304 the bits that were known to be zero when it was last set, and the
305 number of sign bits copies it was known to have when it was last set. */
307 static enum machine_mode
*reg_last_set_mode
;
308 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
309 static char *reg_last_set_sign_bit_copies
;
311 /* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
319 union {rtx r
; int i
;} old_contents
;
320 union {rtx
*r
; int *i
;} where
;
323 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
326 other_insn is nonzero if we have modified some other insn in the process
327 of working on subst_insn. It must be verified too. */
336 static struct undobuf undobuf
;
338 /* Number of times the pseudo being substituted for
339 was found and replaced. */
341 static int n_occurrences
;
343 static void do_SUBST
PARAMS ((rtx
*, rtx
));
344 static void do_SUBST_INT
PARAMS ((int *, int));
345 static void init_reg_last_arrays
PARAMS ((void));
346 static void setup_incoming_promotions
PARAMS ((void));
347 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
348 static int cant_combine_insn_p
PARAMS ((rtx
));
349 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
350 static int sets_function_arg_p
PARAMS ((rtx
));
351 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
352 static int contains_muldiv
PARAMS ((rtx
));
353 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
354 static void undo_all
PARAMS ((void));
355 static void undo_commit
PARAMS ((void));
356 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
357 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
358 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
359 static rtx simplify_if_then_else
PARAMS ((rtx
));
360 static rtx simplify_set
PARAMS ((rtx
));
361 static rtx simplify_logical
PARAMS ((rtx
, int));
362 static rtx expand_compound_operation
PARAMS ((rtx
));
363 static rtx expand_field_assignment
PARAMS ((rtx
));
364 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
365 rtx
, unsigned HOST_WIDE_INT
, int,
367 static rtx extract_left_shift
PARAMS ((rtx
, int));
368 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
369 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
370 unsigned HOST_WIDE_INT
*));
371 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
372 unsigned HOST_WIDE_INT
, rtx
, int));
373 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
374 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
375 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
376 static rtx make_field_assignment
PARAMS ((rtx
));
377 static rtx apply_distributive_law
PARAMS ((rtx
));
378 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
379 unsigned HOST_WIDE_INT
));
380 static unsigned HOST_WIDE_INT cached_nonzero_bits
381 PARAMS ((rtx
, enum machine_mode
, rtx
,
383 unsigned HOST_WIDE_INT
));
384 static unsigned HOST_WIDE_INT nonzero_bits1
385 PARAMS ((rtx
, enum machine_mode
, rtx
,
387 unsigned HOST_WIDE_INT
));
388 static unsigned int cached_num_sign_bit_copies
389 PARAMS ((rtx
, enum machine_mode
, rtx
,
390 enum machine_mode
, unsigned int));
391 static unsigned int num_sign_bit_copies1
392 PARAMS ((rtx
, enum machine_mode
, rtx
,
393 enum machine_mode
, unsigned int));
394 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
395 enum rtx_code
, HOST_WIDE_INT
,
396 enum machine_mode
, int *));
397 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
399 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
400 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
401 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
403 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
404 static void update_table_tick
PARAMS ((rtx
));
405 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
406 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
407 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
408 static void record_dead_and_set_regs
PARAMS ((rtx
));
409 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
410 static rtx get_last_value
PARAMS ((rtx
));
411 static int use_crosses_set_p
PARAMS ((rtx
, int));
412 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
413 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
414 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
415 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
416 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
417 static void distribute_links
PARAMS ((rtx
));
418 static void mark_used_regs_combine
PARAMS ((rtx
));
419 static int insn_cuid
PARAMS ((rtx
));
420 static void record_promoted_value
PARAMS ((rtx
, rtx
));
421 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
422 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
424 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
425 insn. The substitution can be undone by undo_all. If INTO is already
426 set to NEWVAL, do not record this change. Because computing NEWVAL might
427 also call SUBST, we have to compute it before we put anything into
431 do_SUBST (into
, newval
)
437 if (oldval
== newval
)
440 /* We'd like to catch as many invalid transformations here as
441 possible. Unfortunately, there are way too many mode changes
442 that are perfectly valid, so we'd waste too much effort for
443 little gain doing the checks here. Focus on catching invalid
444 transformations involving integer constants. */
445 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
446 && GET_CODE (newval
) == CONST_INT
)
448 /* Sanity check that we're replacing oldval with a CONST_INT
449 that is a valid sign-extension for the original mode. */
450 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
454 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
455 CONST_INT is not valid, because after the replacement, the
456 original mode would be gone. Unfortunately, we can't tell
457 when do_SUBST is called to replace the operand thereof, so we
458 perform this test on oldval instead, checking whether an
459 invalid replacement took place before we got here. */
460 if ((GET_CODE (oldval
) == SUBREG
461 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
462 || (GET_CODE (oldval
) == ZERO_EXTEND
463 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
468 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
470 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
474 buf
->old_contents
.r
= oldval
;
477 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
480 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
482 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
483 for the value of a HOST_WIDE_INT value (including CONST_INT) is
487 do_SUBST_INT (into
, newval
)
493 if (oldval
== newval
)
497 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
499 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
503 buf
->old_contents
.i
= oldval
;
506 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
509 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
511 /* Main entry point for combiner. F is the first insn of the function.
512 NREGS is the first unused pseudo-reg number.
514 Return nonzero if the combiner has turned an indirect jump
515 instruction into a direct jump. */
517 combine_instructions (f
, nregs
)
526 rtx links
, nextlinks
;
528 int new_direct_jump_p
= 0;
530 combine_attempts
= 0;
533 combine_successes
= 0;
535 combine_max_regno
= nregs
;
537 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
538 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
540 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
542 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
543 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
544 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
545 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
546 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
547 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
549 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
550 reg_last_set_nonzero_bits
551 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
552 reg_last_set_sign_bit_copies
553 = (char *) xmalloc (nregs
* sizeof (char));
555 init_reg_last_arrays ();
557 init_recog_no_volatile ();
559 /* Compute maximum uid value so uid_cuid can be allocated. */
561 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
562 if (INSN_UID (insn
) > i
)
565 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
568 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
570 /* Don't use reg_nonzero_bits when computing it. This can cause problems
571 when, for example, we have j <<= 1 in a loop. */
573 nonzero_sign_valid
= 0;
575 /* Compute the mapping from uids to cuids.
576 Cuids are numbers assigned to insns, like uids,
577 except that cuids increase monotonically through the code.
579 Scan all SETs and see if we can deduce anything about what
580 bits are known to be zero for some registers and how many copies
581 of the sign bit are known to exist for those registers.
583 Also set any known values so that we can use it while searching
584 for what bits are known to be set. */
588 setup_incoming_promotions ();
590 refresh_blocks
= sbitmap_alloc (last_basic_block
);
591 sbitmap_zero (refresh_blocks
);
593 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
595 uid_cuid
[INSN_UID (insn
)] = ++i
;
601 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
603 record_dead_and_set_regs (insn
);
606 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
607 if (REG_NOTE_KIND (links
) == REG_INC
)
608 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
613 if (GET_CODE (insn
) == CODE_LABEL
)
617 nonzero_sign_valid
= 1;
619 /* Now scan all the insns in forward order. */
624 init_reg_last_arrays ();
625 setup_incoming_promotions ();
627 FOR_EACH_BB (this_basic_block
)
629 for (insn
= this_basic_block
->head
;
630 insn
!= NEXT_INSN (this_basic_block
->end
);
631 insn
= next
? next
: NEXT_INSN (insn
))
635 if (GET_CODE (insn
) == CODE_LABEL
)
638 else if (INSN_P (insn
))
640 /* See if we know about function return values before this
641 insn based upon SUBREG flags. */
642 check_promoted_subreg (insn
, PATTERN (insn
));
644 /* Try this insn with each insn it links back to. */
646 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
647 if ((next
= try_combine (insn
, XEXP (links
, 0),
648 NULL_RTX
, &new_direct_jump_p
)) != 0)
651 /* Try each sequence of three linked insns ending with this one. */
653 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
655 rtx link
= XEXP (links
, 0);
657 /* If the linked insn has been replaced by a note, then there
658 is no point in pursuing this chain any further. */
659 if (GET_CODE (link
) == NOTE
)
662 for (nextlinks
= LOG_LINKS (link
);
664 nextlinks
= XEXP (nextlinks
, 1))
665 if ((next
= try_combine (insn
, link
,
667 &new_direct_jump_p
)) != 0)
672 /* Try to combine a jump insn that uses CC0
673 with a preceding insn that sets CC0, and maybe with its
674 logical predecessor as well.
675 This is how we make decrement-and-branch insns.
676 We need this special code because data flow connections
677 via CC0 do not get entered in LOG_LINKS. */
679 if (GET_CODE (insn
) == JUMP_INSN
680 && (prev
= prev_nonnote_insn (insn
)) != 0
681 && GET_CODE (prev
) == INSN
682 && sets_cc0_p (PATTERN (prev
)))
684 if ((next
= try_combine (insn
, prev
,
685 NULL_RTX
, &new_direct_jump_p
)) != 0)
688 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
689 nextlinks
= XEXP (nextlinks
, 1))
690 if ((next
= try_combine (insn
, prev
,
692 &new_direct_jump_p
)) != 0)
696 /* Do the same for an insn that explicitly references CC0. */
697 if (GET_CODE (insn
) == INSN
698 && (prev
= prev_nonnote_insn (insn
)) != 0
699 && GET_CODE (prev
) == INSN
700 && sets_cc0_p (PATTERN (prev
))
701 && GET_CODE (PATTERN (insn
)) == SET
702 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
704 if ((next
= try_combine (insn
, prev
,
705 NULL_RTX
, &new_direct_jump_p
)) != 0)
708 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
709 nextlinks
= XEXP (nextlinks
, 1))
710 if ((next
= try_combine (insn
, prev
,
712 &new_direct_jump_p
)) != 0)
716 /* Finally, see if any of the insns that this insn links to
717 explicitly references CC0. If so, try this insn, that insn,
718 and its predecessor if it sets CC0. */
719 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
720 if (GET_CODE (XEXP (links
, 0)) == INSN
721 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
722 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
723 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
724 && GET_CODE (prev
) == INSN
725 && sets_cc0_p (PATTERN (prev
))
726 && (next
= try_combine (insn
, XEXP (links
, 0),
727 prev
, &new_direct_jump_p
)) != 0)
731 /* Try combining an insn with two different insns whose results it
733 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
734 for (nextlinks
= XEXP (links
, 1); nextlinks
;
735 nextlinks
= XEXP (nextlinks
, 1))
736 if ((next
= try_combine (insn
, XEXP (links
, 0),
738 &new_direct_jump_p
)) != 0)
741 if (GET_CODE (insn
) != NOTE
)
742 record_dead_and_set_regs (insn
);
751 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
752 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
753 new_direct_jump_p
|= purge_all_dead_edges (0);
754 delete_noop_moves (f
);
756 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
757 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
758 | PROP_KILL_DEAD_CODE
);
761 sbitmap_free (refresh_blocks
);
762 free (reg_nonzero_bits
);
763 free (reg_sign_bit_copies
);
764 free (reg_last_death
);
766 free (reg_last_set_value
);
767 free (reg_last_set_table_tick
);
768 free (reg_last_set_label
);
769 free (reg_last_set_invalid
);
770 free (reg_last_set_mode
);
771 free (reg_last_set_nonzero_bits
);
772 free (reg_last_set_sign_bit_copies
);
776 struct undo
*undo
, *next
;
777 for (undo
= undobuf
.frees
; undo
; undo
= next
)
785 total_attempts
+= combine_attempts
;
786 total_merges
+= combine_merges
;
787 total_extras
+= combine_extras
;
788 total_successes
+= combine_successes
;
790 nonzero_sign_valid
= 0;
792 /* Make recognizer allow volatile MEMs again. */
795 return new_direct_jump_p
;
798 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
801 init_reg_last_arrays ()
803 unsigned int nregs
= combine_max_regno
;
805 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
806 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
807 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
808 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
809 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
810 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
811 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
812 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
813 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
816 /* Set up any promoted values for incoming argument registers. */
819 setup_incoming_promotions ()
821 #ifdef PROMOTE_FUNCTION_ARGS
824 enum machine_mode mode
;
826 rtx first
= get_insns ();
828 #ifndef OUTGOING_REGNO
829 #define OUTGOING_REGNO(N) N
831 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
832 /* Check whether this register can hold an incoming pointer
833 argument. FUNCTION_ARG_REGNO_P tests outgoing register
834 numbers, so translate if necessary due to register windows. */
835 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
836 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
839 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
842 gen_rtx_CLOBBER (mode
, const0_rtx
)));
847 /* Called via note_stores. If X is a pseudo that is narrower than
848 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
850 If we are setting only a portion of X and we can't figure out what
851 portion, assume all bits will be used since we don't know what will
854 Similarly, set how many bits of X are known to be copies of the sign bit
855 at all locations in the function. This is the smallest number implied
859 set_nonzero_bits_and_sign_copies (x
, set
, data
)
862 void *data ATTRIBUTE_UNUSED
;
866 if (GET_CODE (x
) == REG
867 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
868 /* If this register is undefined at the start of the file, we can't
869 say what its contents were. */
870 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
871 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
873 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
875 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
876 reg_sign_bit_copies
[REGNO (x
)] = 1;
880 /* If this is a complex assignment, see if we can convert it into a
881 simple assignment. */
882 set
= expand_field_assignment (set
);
884 /* If this is a simple assignment, or we have a paradoxical SUBREG,
885 set what we know about X. */
887 if (SET_DEST (set
) == x
888 || (GET_CODE (SET_DEST (set
)) == SUBREG
889 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
890 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
891 && SUBREG_REG (SET_DEST (set
)) == x
))
893 rtx src
= SET_SRC (set
);
895 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
896 /* If X is narrower than a word and SRC is a non-negative
897 constant that would appear negative in the mode of X,
898 sign-extend it for use in reg_nonzero_bits because some
899 machines (maybe most) will actually do the sign-extension
900 and this is the conservative approach.
902 ??? For 2.5, try to tighten up the MD files in this regard
903 instead of this kludge. */
905 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
906 && GET_CODE (src
) == CONST_INT
908 && 0 != (INTVAL (src
)
910 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
911 src
= GEN_INT (INTVAL (src
)
912 | ((HOST_WIDE_INT
) (-1)
913 << GET_MODE_BITSIZE (GET_MODE (x
))));
916 /* Don't call nonzero_bits if it cannot change anything. */
917 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
918 reg_nonzero_bits
[REGNO (x
)]
919 |= nonzero_bits (src
, nonzero_bits_mode
);
920 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
921 if (reg_sign_bit_copies
[REGNO (x
)] == 0
922 || reg_sign_bit_copies
[REGNO (x
)] > num
)
923 reg_sign_bit_copies
[REGNO (x
)] = num
;
927 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
928 reg_sign_bit_copies
[REGNO (x
)] = 1;
933 /* See if INSN can be combined into I3. PRED and SUCC are optionally
934 insns that were previously combined into I3 or that will be combined
935 into the merger of INSN and I3.
937 Return 0 if the combination is not allowed for any reason.
939 If the combination is allowed, *PDEST will be set to the single
940 destination of INSN and *PSRC to the single source, and this function
944 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
947 rtx pred ATTRIBUTE_UNUSED
;
952 rtx set
= 0, src
, dest
;
957 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
958 && next_active_insn (succ
) == i3
)
959 : next_active_insn (insn
) == i3
);
961 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
962 or a PARALLEL consisting of such a SET and CLOBBERs.
964 If INSN has CLOBBER parallel parts, ignore them for our processing.
965 By definition, these happen during the execution of the insn. When it
966 is merged with another insn, all bets are off. If they are, in fact,
967 needed and aren't also supplied in I3, they may be added by
968 recog_for_combine. Otherwise, it won't match.
970 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
973 Get the source and destination of INSN. If more than one, can't
976 if (GET_CODE (PATTERN (insn
)) == SET
)
977 set
= PATTERN (insn
);
978 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
979 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
981 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
983 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
985 switch (GET_CODE (elt
))
987 /* This is important to combine floating point insns
990 /* Combining an isolated USE doesn't make sense.
991 We depend here on combinable_i3pat to reject them. */
992 /* The code below this loop only verifies that the inputs of
993 the SET in INSN do not change. We call reg_set_between_p
994 to verify that the REG in the USE does not change between
996 If the USE in INSN was for a pseudo register, the matching
997 insn pattern will likely match any register; combining this
998 with any other USE would only be safe if we knew that the
999 used registers have identical values, or if there was
1000 something to tell them apart, e.g. different modes. For
1001 now, we forgo such complicated tests and simply disallow
1002 combining of USES of pseudo registers with any other USE. */
1003 if (GET_CODE (XEXP (elt
, 0)) == REG
1004 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1006 rtx i3pat
= PATTERN (i3
);
1007 int i
= XVECLEN (i3pat
, 0) - 1;
1008 unsigned int regno
= REGNO (XEXP (elt
, 0));
1012 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1014 if (GET_CODE (i3elt
) == USE
1015 && GET_CODE (XEXP (i3elt
, 0)) == REG
1016 && (REGNO (XEXP (i3elt
, 0)) == regno
1017 ? reg_set_between_p (XEXP (elt
, 0),
1018 PREV_INSN (insn
), i3
)
1019 : regno
>= FIRST_PSEUDO_REGISTER
))
1026 /* We can ignore CLOBBERs. */
1031 /* Ignore SETs whose result isn't used but not those that
1032 have side-effects. */
1033 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1034 && ! side_effects_p (elt
))
1037 /* If we have already found a SET, this is a second one and
1038 so we cannot combine with this insn. */
1046 /* Anything else means we can't combine. */
1052 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1053 so don't do anything with it. */
1054 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1063 set
= expand_field_assignment (set
);
1064 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1066 /* Don't eliminate a store in the stack pointer. */
1067 if (dest
== stack_pointer_rtx
1068 /* If we couldn't eliminate a field assignment, we can't combine. */
1069 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1070 /* Don't combine with an insn that sets a register to itself if it has
1071 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1072 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1073 /* Can't merge an ASM_OPERANDS. */
1074 || GET_CODE (src
) == ASM_OPERANDS
1075 /* Can't merge a function call. */
1076 || GET_CODE (src
) == CALL
1077 /* Don't eliminate a function call argument. */
1078 || (GET_CODE (i3
) == CALL_INSN
1079 && (find_reg_fusage (i3
, USE
, dest
)
1080 || (GET_CODE (dest
) == REG
1081 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1082 && global_regs
[REGNO (dest
)])))
1083 /* Don't substitute into an incremented register. */
1084 || FIND_REG_INC_NOTE (i3
, dest
)
1085 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1087 /* Don't combine the end of a libcall into anything. */
1088 /* ??? This gives worse code, and appears to be unnecessary, since no
1089 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1090 use REG_RETVAL notes for noconflict blocks, but other code here
1091 makes sure that those insns don't disappear. */
1092 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1094 /* Make sure that DEST is not used after SUCC but before I3. */
1095 || (succ
&& ! all_adjacent
1096 && reg_used_between_p (dest
, succ
, i3
))
1097 /* Make sure that the value that is to be substituted for the register
1098 does not use any registers whose values alter in between. However,
1099 If the insns are adjacent, a use can't cross a set even though we
1100 think it might (this can happen for a sequence of insns each setting
1101 the same destination; reg_last_set of that register might point to
1102 a NOTE). If INSN has a REG_EQUIV note, the register is always
1103 equivalent to the memory so the substitution is valid even if there
1104 are intervening stores. Also, don't move a volatile asm or
1105 UNSPEC_VOLATILE across any other insns. */
1107 && (((GET_CODE (src
) != MEM
1108 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1109 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1110 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1111 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1112 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1113 better register allocation by not doing the combine. */
1114 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1115 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1116 /* Don't combine across a CALL_INSN, because that would possibly
1117 change whether the life span of some REGs crosses calls or not,
1118 and it is a pain to update that information.
1119 Exception: if source is a constant, moving it later can't hurt.
1120 Accept that special case, because it helps -fforce-addr a lot. */
1121 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1124 /* DEST must either be a REG or CC0. */
1125 if (GET_CODE (dest
) == REG
)
1127 /* If register alignment is being enforced for multi-word items in all
1128 cases except for parameters, it is possible to have a register copy
1129 insn referencing a hard register that is not allowed to contain the
1130 mode being copied and which would not be valid as an operand of most
1131 insns. Eliminate this problem by not combining with such an insn.
1133 Also, on some machines we don't want to extend the life of a hard
1136 if (GET_CODE (src
) == REG
1137 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1138 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1139 /* Don't extend the life of a hard register unless it is
1140 user variable (if we have few registers) or it can't
1141 fit into the desired register (meaning something special
1143 Also avoid substituting a return register into I3, because
1144 reload can't handle a conflict with constraints of other
1146 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1147 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1150 else if (GET_CODE (dest
) != CC0
)
1153 /* Don't substitute for a register intended as a clobberable operand.
1154 Similarly, don't substitute an expression containing a register that
1155 will be clobbered in I3. */
1156 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1157 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1158 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1159 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1161 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1164 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1165 or not), reject, unless nothing volatile comes between it and I3 */
1167 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1169 /* Make sure succ doesn't contain a volatile reference. */
1170 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1173 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1174 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1178 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1179 to be an explicit register variable, and was chosen for a reason. */
1181 if (GET_CODE (src
) == ASM_OPERANDS
1182 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1185 /* If there are any volatile insns between INSN and I3, reject, because
1186 they might affect machine state. */
1188 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1189 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1192 /* If INSN or I2 contains an autoincrement or autodecrement,
1193 make sure that register is not used between there and I3,
1194 and not already used in I3 either.
1195 Also insist that I3 not be a jump; if it were one
1196 and the incremented register were spilled, we would lose. */
1199 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1200 if (REG_NOTE_KIND (link
) == REG_INC
1201 && (GET_CODE (i3
) == JUMP_INSN
1202 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1203 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1208 /* Don't combine an insn that follows a CC0-setting insn.
1209 An insn that uses CC0 must not be separated from the one that sets it.
1210 We do, however, allow I2 to follow a CC0-setting insn if that insn
1211 is passed as I1; in that case it will be deleted also.
1212 We also allow combining in this case if all the insns are adjacent
1213 because that would leave the two CC0 insns adjacent as well.
1214 It would be more logical to test whether CC0 occurs inside I1 or I2,
1215 but that would be much slower, and this ought to be equivalent. */
1217 p
= prev_nonnote_insn (insn
);
1218 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1223 /* If we get here, we have passed all the tests and the combination is
1232 /* Check if PAT is an insn - or a part of it - used to set up an
1233 argument for a function in a hard register. */
1236 sets_function_arg_p (pat
)
1242 switch (GET_CODE (pat
))
1245 return sets_function_arg_p (PATTERN (pat
));
1248 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1249 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1255 inner_dest
= SET_DEST (pat
);
1256 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1257 || GET_CODE (inner_dest
) == SUBREG
1258 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1259 inner_dest
= XEXP (inner_dest
, 0);
1261 return (GET_CODE (inner_dest
) == REG
1262 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1263 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1272 /* LOC is the location within I3 that contains its pattern or the component
1273 of a PARALLEL of the pattern. We validate that it is valid for combining.
1275 One problem is if I3 modifies its output, as opposed to replacing it
1276 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1277 so would produce an insn that is not equivalent to the original insns.
1281 (set (reg:DI 101) (reg:DI 100))
1282 (set (subreg:SI (reg:DI 101) 0) <foo>)
1284 This is NOT equivalent to:
1286 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1287 (set (reg:DI 101) (reg:DI 100))])
1289 Not only does this modify 100 (in which case it might still be valid
1290 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1292 We can also run into a problem if I2 sets a register that I1
1293 uses and I1 gets directly substituted into I3 (not via I2). In that
1294 case, we would be getting the wrong value of I2DEST into I3, so we
1295 must reject the combination. This case occurs when I2 and I1 both
1296 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1297 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1298 of a SET must prevent combination from occurring.
1300 Before doing the above check, we first try to expand a field assignment
1301 into a set of logical operations.
1303 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1304 we place a register that is both set and used within I3. If more than one
1305 such register is detected, we fail.
1307 Return 1 if the combination is valid, zero otherwise. */
1310 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1316 rtx
*pi3dest_killed
;
1320 if (GET_CODE (x
) == SET
)
1322 rtx set
= expand_field_assignment (x
);
1323 rtx dest
= SET_DEST (set
);
1324 rtx src
= SET_SRC (set
);
1325 rtx inner_dest
= dest
;
1328 rtx inner_src
= src
;
1333 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1334 || GET_CODE (inner_dest
) == SUBREG
1335 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1336 inner_dest
= XEXP (inner_dest
, 0);
1338 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1341 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1342 || GET_CODE (inner_src
) == SUBREG
1343 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1344 inner_src
= XEXP (inner_src
, 0);
1346 /* If it is better that two different modes keep two different pseudos,
1347 avoid combining them. This avoids producing the following pattern
1349 (set (subreg:SI (reg/v:QI 21) 0)
1350 (lshiftrt:SI (reg/v:SI 20)
1352 If that were made, reload could not handle the pair of
1353 reg 20/21, since it would try to get any GENERAL_REGS
1354 but some of them don't handle QImode. */
1356 if (rtx_equal_p (inner_src
, i2dest
)
1357 && GET_CODE (inner_dest
) == REG
1358 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1362 /* Check for the case where I3 modifies its output, as
1364 if ((inner_dest
!= dest
1365 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1366 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1368 /* This is the same test done in can_combine_p except we can't test
1369 all_adjacent; we don't have to, since this instruction will stay
1370 in place, thus we are not considering increasing the lifetime of
1373 Also, if this insn sets a function argument, combining it with
1374 something that might need a spill could clobber a previous
1375 function argument; the all_adjacent test in can_combine_p also
1376 checks this; here, we do a more specific test for this case. */
1378 || (GET_CODE (inner_dest
) == REG
1379 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1380 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1381 GET_MODE (inner_dest
))))
1382 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1385 /* If DEST is used in I3, it is being killed in this insn,
1386 so record that for later.
1387 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1388 STACK_POINTER_REGNUM, since these are always considered to be
1389 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1390 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1391 && reg_referenced_p (dest
, PATTERN (i3
))
1392 && REGNO (dest
) != FRAME_POINTER_REGNUM
1393 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1394 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1396 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1397 && (REGNO (dest
) != ARG_POINTER_REGNUM
1398 || ! fixed_regs
[REGNO (dest
)])
1400 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1402 if (*pi3dest_killed
)
1405 *pi3dest_killed
= dest
;
1409 else if (GET_CODE (x
) == PARALLEL
)
1413 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1414 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1415 i1_not_in_src
, pi3dest_killed
))
1422 /* Return 1 if X is an arithmetic expression that contains a multiplication
1423 and division. We don't count multiplications by powers of two here. */
1429 switch (GET_CODE (x
))
1431 case MOD
: case DIV
: case UMOD
: case UDIV
:
1435 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1436 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1438 switch (GET_RTX_CLASS (GET_CODE (x
)))
1440 case 'c': case '<': case '2':
1441 return contains_muldiv (XEXP (x
, 0))
1442 || contains_muldiv (XEXP (x
, 1));
1445 return contains_muldiv (XEXP (x
, 0));
1453 /* Determine whether INSN can be used in a combination. Return nonzero if
1454 not. This is used in try_combine to detect early some cases where we
1455 can't perform combinations. */
1458 cant_combine_insn_p (insn
)
1464 /* If this isn't really an insn, we can't do anything.
1465 This can occur when flow deletes an insn that it has merged into an
1466 auto-increment address. */
1467 if (! INSN_P (insn
))
1470 /* Never combine loads and stores involving hard regs. The register
1471 allocator can usually handle such reg-reg moves by tying. If we allow
1472 the combiner to make substitutions of hard regs, we risk aborting in
1473 reload on machines that have SMALL_REGISTER_CLASSES.
1474 As an exception, we allow combinations involving fixed regs; these are
1475 not available to the register allocator so there's no risk involved. */
1477 set
= single_set (insn
);
1480 src
= SET_SRC (set
);
1481 dest
= SET_DEST (set
);
1482 if (GET_CODE (src
) == SUBREG
)
1483 src
= SUBREG_REG (src
);
1484 if (GET_CODE (dest
) == SUBREG
)
1485 dest
= SUBREG_REG (dest
);
1486 if (REG_P (src
) && REG_P (dest
)
1487 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1488 && ! fixed_regs
[REGNO (src
)])
1489 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1490 && ! fixed_regs
[REGNO (dest
)])))
1496 /* Try to combine the insns I1 and I2 into I3.
1497 Here I1 and I2 appear earlier than I3.
1498 I1 can be zero; then we combine just I2 into I3.
1500 If we are combining three insns and the resulting insn is not recognized,
1501 try splitting it into two insns. If that happens, I2 and I3 are retained
1502 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1505 Return 0 if the combination does not work. Then nothing is changed.
1506 If we did the combination, return the insn at which combine should
1509 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1510 new direct jump instruction. */
1513 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1515 int *new_direct_jump_p
;
1517 /* New patterns for I3 and I2, respectively. */
1518 rtx newpat
, newi2pat
= 0;
1519 int substed_i2
= 0, substed_i1
= 0;
1520 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1521 int added_sets_1
, added_sets_2
;
1522 /* Total number of SETs to put into I3. */
1524 /* Nonzero is I2's body now appears in I3. */
1526 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1527 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1528 /* Contains I3 if the destination of I3 is used in its source, which means
1529 that the old life of I3 is being killed. If that usage is placed into
1530 I2 and not in I3, a REG_DEAD note must be made. */
1531 rtx i3dest_killed
= 0;
1532 /* SET_DEST and SET_SRC of I2 and I1. */
1533 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1534 /* PATTERN (I2), or a copy of it in certain cases. */
1536 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1537 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1538 int i1_feeds_i3
= 0;
1539 /* Notes that must be added to REG_NOTES in I3 and I2. */
1540 rtx new_i3_notes
, new_i2_notes
;
1541 /* Notes that we substituted I3 into I2 instead of the normal case. */
1542 int i3_subst_into_i2
= 0;
1543 /* Notes that I1, I2 or I3 is a MULT operation. */
1551 /* Exit early if one of the insns involved can't be used for
1553 if (cant_combine_insn_p (i3
)
1554 || cant_combine_insn_p (i2
)
1555 || (i1
&& cant_combine_insn_p (i1
))
1556 /* We also can't do anything if I3 has a
1557 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1560 /* ??? This gives worse code, and appears to be unnecessary, since no
1561 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1562 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1568 undobuf
.other_insn
= 0;
1570 /* Reset the hard register usage information. */
1571 CLEAR_HARD_REG_SET (newpat_used_regs
);
1573 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1574 code below, set I1 to be the earlier of the two insns. */
1575 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1576 temp
= i1
, i1
= i2
, i2
= temp
;
1578 added_links_insn
= 0;
1580 /* First check for one important special-case that the code below will
1581 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1582 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1583 we may be able to replace that destination with the destination of I3.
1584 This occurs in the common code where we compute both a quotient and
1585 remainder into a structure, in which case we want to do the computation
1586 directly into the structure to avoid register-register copies.
1588 Note that this case handles both multiple sets in I2 and also
1589 cases where I2 has a number of CLOBBER or PARALLELs.
1591 We make very conservative checks below and only try to handle the
1592 most common cases of this. For example, we only handle the case
1593 where I2 and I3 are adjacent to avoid making difficult register
1596 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1597 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1598 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1599 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1600 && GET_CODE (PATTERN (i2
)) == PARALLEL
1601 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1602 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1603 below would need to check what is inside (and reg_overlap_mentioned_p
1604 doesn't support those codes anyway). Don't allow those destinations;
1605 the resulting insn isn't likely to be recognized anyway. */
1606 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1607 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1608 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1609 SET_DEST (PATTERN (i3
)))
1610 && next_real_insn (i2
) == i3
)
1612 rtx p2
= PATTERN (i2
);
1614 /* Make sure that the destination of I3,
1615 which we are going to substitute into one output of I2,
1616 is not used within another output of I2. We must avoid making this:
1617 (parallel [(set (mem (reg 69)) ...)
1618 (set (reg 69) ...)])
1619 which is not well-defined as to order of actions.
1620 (Besides, reload can't handle output reloads for this.)
1622 The problem can also happen if the dest of I3 is a memory ref,
1623 if another dest in I2 is an indirect memory ref. */
1624 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1625 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1626 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1627 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1628 SET_DEST (XVECEXP (p2
, 0, i
))))
1631 if (i
== XVECLEN (p2
, 0))
1632 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1633 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1634 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1635 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1640 subst_low_cuid
= INSN_CUID (i2
);
1642 added_sets_2
= added_sets_1
= 0;
1643 i2dest
= SET_SRC (PATTERN (i3
));
1645 /* Replace the dest in I2 with our dest and make the resulting
1646 insn the new pattern for I3. Then skip to where we
1647 validate the pattern. Everything was set up above. */
1648 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1649 SET_DEST (PATTERN (i3
)));
1652 i3_subst_into_i2
= 1;
1653 goto validate_replacement
;
1657 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1658 one of those words to another constant, merge them by making a new
1661 && (temp
= single_set (i2
)) != 0
1662 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1663 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1664 && GET_CODE (SET_DEST (temp
)) == REG
1665 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1666 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1667 && GET_CODE (PATTERN (i3
)) == SET
1668 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1669 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1670 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1671 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1672 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1674 HOST_WIDE_INT lo
, hi
;
1676 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1677 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1680 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1681 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1684 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1686 /* We don't handle the case of the target word being wider
1687 than a host wide int. */
1688 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1691 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1692 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1693 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1695 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1696 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1697 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1699 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1700 >> (HOST_BITS_PER_WIDE_INT
- 1));
1702 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1703 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1704 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1705 (INTVAL (SET_SRC (PATTERN (i3
)))));
1707 hi
= lo
< 0 ? -1 : 0;
1710 /* We don't handle the case of the higher word not fitting
1711 entirely in either hi or lo. */
1716 subst_low_cuid
= INSN_CUID (i2
);
1717 added_sets_2
= added_sets_1
= 0;
1718 i2dest
= SET_DEST (temp
);
1720 SUBST (SET_SRC (temp
),
1721 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1723 newpat
= PATTERN (i2
);
1724 goto validate_replacement
;
1728 /* If we have no I1 and I2 looks like:
1729 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1731 make up a dummy I1 that is
1734 (set (reg:CC X) (compare:CC Y (const_int 0)))
1736 (We can ignore any trailing CLOBBERs.)
1738 This undoes a previous combination and allows us to match a branch-and-
1741 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1742 && XVECLEN (PATTERN (i2
), 0) >= 2
1743 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1744 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1746 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1747 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1748 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1749 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1750 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1751 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1753 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1754 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1759 /* We make I1 with the same INSN_UID as I2. This gives it
1760 the same INSN_CUID for value tracking. Our fake I1 will
1761 never appear in the insn stream so giving it the same INSN_UID
1762 as I2 will not cause a problem. */
1764 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1765 BLOCK_FOR_INSN (i2
), INSN_SCOPE (i2
),
1766 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1769 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1770 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1771 SET_DEST (PATTERN (i1
)));
1776 /* Verify that I2 and I1 are valid for combining. */
1777 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1778 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1784 /* Record whether I2DEST is used in I2SRC and similarly for the other
1785 cases. Knowing this will help in register status updating below. */
1786 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1787 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1788 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1790 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1792 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1794 /* Ensure that I3's pattern can be the destination of combines. */
1795 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1796 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1803 /* See if any of the insns is a MULT operation. Unless one is, we will
1804 reject a combination that is, since it must be slower. Be conservative
1806 if (GET_CODE (i2src
) == MULT
1807 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1808 || (GET_CODE (PATTERN (i3
)) == SET
1809 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1812 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1813 We used to do this EXCEPT in one case: I3 has a post-inc in an
1814 output operand. However, that exception can give rise to insns like
1816 which is a famous insn on the PDP-11 where the value of r3 used as the
1817 source was model-dependent. Avoid this sort of thing. */
1820 if (!(GET_CODE (PATTERN (i3
)) == SET
1821 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1822 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1823 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1824 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1825 /* It's not the exception. */
1828 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1829 if (REG_NOTE_KIND (link
) == REG_INC
1830 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1832 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1839 /* See if the SETs in I1 or I2 need to be kept around in the merged
1840 instruction: whenever the value set there is still needed past I3.
1841 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1843 For the SET in I1, we have two cases: If I1 and I2 independently
1844 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1845 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1846 in I1 needs to be kept around unless I1DEST dies or is set in either
1847 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1848 I1DEST. If so, we know I1 feeds into I2. */
1850 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1853 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1854 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1856 /* If the set in I2 needs to be kept around, we must make a copy of
1857 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1858 PATTERN (I2), we are only substituting for the original I1DEST, not into
1859 an already-substituted copy. This also prevents making self-referential
1860 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1863 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1864 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1868 i2pat
= copy_rtx (i2pat
);
1872 /* Substitute in the latest insn for the regs set by the earlier ones. */
1874 maxreg
= max_reg_num ();
1878 /* It is possible that the source of I2 or I1 may be performing an
1879 unneeded operation, such as a ZERO_EXTEND of something that is known
1880 to have the high part zero. Handle that case by letting subst look at
1881 the innermost one of them.
1883 Another way to do this would be to have a function that tries to
1884 simplify a single insn instead of merging two or more insns. We don't
1885 do this because of the potential of infinite loops and because
1886 of the potential extra memory required. However, doing it the way
1887 we are is a bit of a kludge and doesn't catch all cases.
1889 But only do this if -fexpensive-optimizations since it slows things down
1890 and doesn't usually win. */
1892 if (flag_expensive_optimizations
)
1894 /* Pass pc_rtx so no substitutions are done, just simplifications.
1895 The cases that we are interested in here do not involve the few
1896 cases were is_replaced is checked. */
1899 subst_low_cuid
= INSN_CUID (i1
);
1900 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1904 subst_low_cuid
= INSN_CUID (i2
);
1905 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1910 /* Many machines that don't use CC0 have insns that can both perform an
1911 arithmetic operation and set the condition code. These operations will
1912 be represented as a PARALLEL with the first element of the vector
1913 being a COMPARE of an arithmetic operation with the constant zero.
1914 The second element of the vector will set some pseudo to the result
1915 of the same arithmetic operation. If we simplify the COMPARE, we won't
1916 match such a pattern and so will generate an extra insn. Here we test
1917 for this case, where both the comparison and the operation result are
1918 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1919 I2SRC. Later we will make the PARALLEL that contains I2. */
1921 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1922 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1923 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1924 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1926 #ifdef EXTRA_CC_MODES
1928 enum machine_mode compare_mode
;
1931 newpat
= PATTERN (i3
);
1932 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1936 #ifdef EXTRA_CC_MODES
1937 /* See if a COMPARE with the operand we substituted in should be done
1938 with the mode that is currently being used. If not, do the same
1939 processing we do in `subst' for a SET; namely, if the destination
1940 is used only once, try to replace it with a register of the proper
1941 mode and also replace the COMPARE. */
1942 if (undobuf
.other_insn
== 0
1943 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1944 &undobuf
.other_insn
))
1945 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1947 != GET_MODE (SET_DEST (newpat
))))
1949 unsigned int regno
= REGNO (SET_DEST (newpat
));
1950 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1952 if (regno
< FIRST_PSEUDO_REGISTER
1953 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1954 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1956 if (regno
>= FIRST_PSEUDO_REGISTER
)
1957 SUBST (regno_reg_rtx
[regno
], new_dest
);
1959 SUBST (SET_DEST (newpat
), new_dest
);
1960 SUBST (XEXP (*cc_use
, 0), new_dest
);
1961 SUBST (SET_SRC (newpat
),
1962 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1965 undobuf
.other_insn
= 0;
1972 n_occurrences
= 0; /* `subst' counts here */
1974 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1975 need to make a unique copy of I2SRC each time we substitute it
1976 to avoid self-referential rtl. */
1978 subst_low_cuid
= INSN_CUID (i2
);
1979 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1980 ! i1_feeds_i3
&& i1dest_in_i1src
);
1983 /* Record whether i2's body now appears within i3's body. */
1984 i2_is_used
= n_occurrences
;
1987 /* If we already got a failure, don't try to do more. Otherwise,
1988 try to substitute in I1 if we have it. */
1990 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1992 /* Before we can do this substitution, we must redo the test done
1993 above (see detailed comments there) that ensures that I1DEST
1994 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1996 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
2004 subst_low_cuid
= INSN_CUID (i1
);
2005 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2009 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2010 to count all the ways that I2SRC and I1SRC can be used. */
2011 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2012 && i2_is_used
+ added_sets_2
> 1)
2013 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2014 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2016 /* Fail if we tried to make a new register (we used to abort, but there's
2017 really no reason to). */
2018 || max_reg_num () != maxreg
2019 /* Fail if we couldn't do something and have a CLOBBER. */
2020 || GET_CODE (newpat
) == CLOBBER
2021 /* Fail if this new pattern is a MULT and we didn't have one before
2022 at the outer level. */
2023 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2030 /* If the actions of the earlier insns must be kept
2031 in addition to substituting them into the latest one,
2032 we must make a new PARALLEL for the latest insn
2033 to hold additional the SETs. */
2035 if (added_sets_1
|| added_sets_2
)
2039 if (GET_CODE (newpat
) == PARALLEL
)
2041 rtvec old
= XVEC (newpat
, 0);
2042 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2043 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2044 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2045 sizeof (old
->elem
[0]) * old
->num_elem
);
2050 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2051 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2052 XVECEXP (newpat
, 0, 0) = old
;
2056 XVECEXP (newpat
, 0, --total_sets
)
2057 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2058 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2062 /* If there is no I1, use I2's body as is. We used to also not do
2063 the subst call below if I2 was substituted into I3,
2064 but that could lose a simplification. */
2066 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2068 /* See comment where i2pat is assigned. */
2069 XVECEXP (newpat
, 0, --total_sets
)
2070 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2074 /* We come here when we are replacing a destination in I2 with the
2075 destination of I3. */
2076 validate_replacement
:
2078 /* Note which hard regs this insn has as inputs. */
2079 mark_used_regs_combine (newpat
);
2081 /* Is the result of combination a valid instruction? */
2082 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2084 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2085 the second SET's destination is a register that is unused. In that case,
2086 we just need the first SET. This can occur when simplifying a divmod
2087 insn. We *must* test for this case here because the code below that
2088 splits two independent SETs doesn't handle this case correctly when it
2089 updates the register status. Also check the case where the first
2090 SET's destination is unused. That would not cause incorrect code, but
2091 does cause an unneeded insn to remain. */
2093 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2094 && XVECLEN (newpat
, 0) == 2
2095 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2096 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2097 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2098 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2099 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2100 && asm_noperands (newpat
) < 0)
2102 newpat
= XVECEXP (newpat
, 0, 0);
2103 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2106 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2107 && XVECLEN (newpat
, 0) == 2
2108 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2109 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2110 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2111 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2112 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2113 && asm_noperands (newpat
) < 0)
2115 newpat
= XVECEXP (newpat
, 0, 1);
2116 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2119 /* If we were combining three insns and the result is a simple SET
2120 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2121 insns. There are two ways to do this. It can be split using a
2122 machine-specific method (like when you have an addition of a large
2123 constant) or by combine in the function find_split_point. */
2125 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2126 && asm_noperands (newpat
) < 0)
2128 rtx m_split
, *split
;
2129 rtx ni2dest
= i2dest
;
2131 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2132 use I2DEST as a scratch register will help. In the latter case,
2133 convert I2DEST to the mode of the source of NEWPAT if we can. */
2135 m_split
= split_insns (newpat
, i3
);
2137 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2138 inputs of NEWPAT. */
2140 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2141 possible to try that as a scratch reg. This would require adding
2142 more code to make it work though. */
2144 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2146 /* If I2DEST is a hard register or the only use of a pseudo,
2147 we can change its mode. */
2148 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2149 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2150 && GET_CODE (i2dest
) == REG
2151 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2152 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2153 && ! REG_USERVAR_P (i2dest
))))
2154 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2157 m_split
= split_insns (gen_rtx_PARALLEL
2159 gen_rtvec (2, newpat
,
2160 gen_rtx_CLOBBER (VOIDmode
,
2163 /* If the split with the mode-changed register didn't work, try
2164 the original register. */
2165 if (! m_split
&& ni2dest
!= i2dest
)
2168 m_split
= split_insns (gen_rtx_PARALLEL
2170 gen_rtvec (2, newpat
,
2171 gen_rtx_CLOBBER (VOIDmode
,
2177 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2179 m_split
= PATTERN (m_split
);
2180 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2181 if (insn_code_number
>= 0)
2184 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2185 && (next_real_insn (i2
) == i3
2186 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2189 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2190 newi2pat
= PATTERN (m_split
);
2192 i3set
= single_set (NEXT_INSN (m_split
));
2193 i2set
= single_set (m_split
);
2195 /* In case we changed the mode of I2DEST, replace it in the
2196 pseudo-register table here. We can't do it above in case this
2197 code doesn't get executed and we do a split the other way. */
2199 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2200 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2202 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2204 /* If I2 or I3 has multiple SETs, we won't know how to track
2205 register status, so don't use these insns. If I2's destination
2206 is used between I2 and I3, we also can't use these insns. */
2208 if (i2_code_number
>= 0 && i2set
&& i3set
2209 && (next_real_insn (i2
) == i3
2210 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2211 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2213 if (insn_code_number
>= 0)
2216 /* It is possible that both insns now set the destination of I3.
2217 If so, we must show an extra use of it. */
2219 if (insn_code_number
>= 0)
2221 rtx new_i3_dest
= SET_DEST (i3set
);
2222 rtx new_i2_dest
= SET_DEST (i2set
);
2224 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2225 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2226 || GET_CODE (new_i3_dest
) == SUBREG
)
2227 new_i3_dest
= XEXP (new_i3_dest
, 0);
2229 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2230 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2231 || GET_CODE (new_i2_dest
) == SUBREG
)
2232 new_i2_dest
= XEXP (new_i2_dest
, 0);
2234 if (GET_CODE (new_i3_dest
) == REG
2235 && GET_CODE (new_i2_dest
) == REG
2236 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2237 REG_N_SETS (REGNO (new_i2_dest
))++;
2241 /* If we can split it and use I2DEST, go ahead and see if that
2242 helps things be recognized. Verify that none of the registers
2243 are set between I2 and I3. */
2244 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2246 && GET_CODE (i2dest
) == REG
2248 /* We need I2DEST in the proper mode. If it is a hard register
2249 or the only use of a pseudo, we can change its mode. */
2250 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2251 || GET_MODE (*split
) == VOIDmode
2252 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2253 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2254 && ! REG_USERVAR_P (i2dest
)))
2255 && (next_real_insn (i2
) == i3
2256 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2257 /* We can't overwrite I2DEST if its value is still used by
2259 && ! reg_referenced_p (i2dest
, newpat
))
2261 rtx newdest
= i2dest
;
2262 enum rtx_code split_code
= GET_CODE (*split
);
2263 enum machine_mode split_mode
= GET_MODE (*split
);
2265 /* Get NEWDEST as a register in the proper mode. We have already
2266 validated that we can do this. */
2267 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2269 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2271 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2272 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2275 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2276 an ASHIFT. This can occur if it was inside a PLUS and hence
2277 appeared to be a memory address. This is a kludge. */
2278 if (split_code
== MULT
2279 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2280 && INTVAL (XEXP (*split
, 1)) > 0
2281 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2283 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2284 XEXP (*split
, 0), GEN_INT (i
)));
2285 /* Update split_code because we may not have a multiply
2287 split_code
= GET_CODE (*split
);
2290 #ifdef INSN_SCHEDULING
2291 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2292 be written as a ZERO_EXTEND. */
2293 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2295 #ifdef LOAD_EXTEND_OP
2296 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2297 what it really is. */
2298 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2300 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2301 SUBREG_REG (*split
)));
2304 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2305 SUBREG_REG (*split
)));
2309 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2310 SUBST (*split
, newdest
);
2311 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2313 /* If the split point was a MULT and we didn't have one before,
2314 don't use one now. */
2315 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2316 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2320 /* Check for a case where we loaded from memory in a narrow mode and
2321 then sign extended it, but we need both registers. In that case,
2322 we have a PARALLEL with both loads from the same memory location.
2323 We can split this into a load from memory followed by a register-register
2324 copy. This saves at least one insn, more if register allocation can
2327 We cannot do this if the destination of the first assignment is a
2328 condition code register or cc0. We eliminate this case by making sure
2329 the SET_DEST and SET_SRC have the same mode.
2331 We cannot do this if the destination of the second assignment is
2332 a register that we have already assumed is zero-extended. Similarly
2333 for a SUBREG of such a register. */
2335 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2336 && GET_CODE (newpat
) == PARALLEL
2337 && XVECLEN (newpat
, 0) == 2
2338 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2339 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2340 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2341 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2342 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2343 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2344 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2345 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2347 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2348 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2349 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2350 (GET_CODE (temp
) == REG
2351 && reg_nonzero_bits
[REGNO (temp
)] != 0
2352 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2353 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2354 && (reg_nonzero_bits
[REGNO (temp
)]
2355 != GET_MODE_MASK (word_mode
))))
2356 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2357 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2358 (GET_CODE (temp
) == REG
2359 && reg_nonzero_bits
[REGNO (temp
)] != 0
2360 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2361 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2362 && (reg_nonzero_bits
[REGNO (temp
)]
2363 != GET_MODE_MASK (word_mode
)))))
2364 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2365 SET_SRC (XVECEXP (newpat
, 0, 1)))
2366 && ! find_reg_note (i3
, REG_UNUSED
,
2367 SET_DEST (XVECEXP (newpat
, 0, 0))))
2371 newi2pat
= XVECEXP (newpat
, 0, 0);
2372 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2373 newpat
= XVECEXP (newpat
, 0, 1);
2374 SUBST (SET_SRC (newpat
),
2375 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2376 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2378 if (i2_code_number
>= 0)
2379 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2381 if (insn_code_number
>= 0)
2386 /* If we will be able to accept this, we have made a change to the
2387 destination of I3. This can invalidate a LOG_LINKS pointing
2388 to I3. No other part of combine.c makes such a transformation.
2390 The new I3 will have a destination that was previously the
2391 destination of I1 or I2 and which was used in i2 or I3. Call
2392 distribute_links to make a LOG_LINK from the next use of
2393 that destination. */
2395 PATTERN (i3
) = newpat
;
2396 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2398 /* I3 now uses what used to be its destination and which is
2399 now I2's destination. That means we need a LOG_LINK from
2400 I3 to I2. But we used to have one, so we still will.
2402 However, some later insn might be using I2's dest and have
2403 a LOG_LINK pointing at I3. We must remove this link.
2404 The simplest way to remove the link is to point it at I1,
2405 which we know will be a NOTE. */
2407 for (insn
= NEXT_INSN (i3
);
2408 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2409 || insn
!= this_basic_block
->next_bb
->head
);
2410 insn
= NEXT_INSN (insn
))
2412 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2414 for (link
= LOG_LINKS (insn
); link
;
2415 link
= XEXP (link
, 1))
2416 if (XEXP (link
, 0) == i3
)
2417 XEXP (link
, 0) = i1
;
2425 /* Similarly, check for a case where we have a PARALLEL of two independent
2426 SETs but we started with three insns. In this case, we can do the sets
2427 as two separate insns. This case occurs when some SET allows two
2428 other insns to combine, but the destination of that SET is still live. */
2430 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2431 && GET_CODE (newpat
) == PARALLEL
2432 && XVECLEN (newpat
, 0) == 2
2433 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2434 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2435 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2436 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2437 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2438 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2439 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2441 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2442 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2443 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2444 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2445 XVECEXP (newpat
, 0, 0))
2446 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2447 XVECEXP (newpat
, 0, 1))
2448 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2449 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2451 /* Normally, it doesn't matter which of the two is done first,
2452 but it does if one references cc0. In that case, it has to
2455 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2457 newi2pat
= XVECEXP (newpat
, 0, 0);
2458 newpat
= XVECEXP (newpat
, 0, 1);
2463 newi2pat
= XVECEXP (newpat
, 0, 1);
2464 newpat
= XVECEXP (newpat
, 0, 0);
2467 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2469 if (i2_code_number
>= 0)
2470 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2473 /* If it still isn't recognized, fail and change things back the way they
2475 if ((insn_code_number
< 0
2476 /* Is the result a reasonable ASM_OPERANDS? */
2477 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2483 /* If we had to change another insn, make sure it is valid also. */
2484 if (undobuf
.other_insn
)
2486 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2487 rtx new_other_notes
;
2490 CLEAR_HARD_REG_SET (newpat_used_regs
);
2492 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2495 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2501 PATTERN (undobuf
.other_insn
) = other_pat
;
2503 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2504 are still valid. Then add any non-duplicate notes added by
2505 recog_for_combine. */
2506 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2508 next
= XEXP (note
, 1);
2510 if (REG_NOTE_KIND (note
) == REG_UNUSED
2511 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2513 if (GET_CODE (XEXP (note
, 0)) == REG
)
2514 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2516 remove_note (undobuf
.other_insn
, note
);
2520 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2521 if (GET_CODE (XEXP (note
, 0)) == REG
)
2522 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2524 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2525 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2528 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2529 they are adjacent to each other or not. */
2531 rtx p
= prev_nonnote_insn (i3
);
2532 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2533 && sets_cc0_p (newi2pat
))
2541 /* We now know that we can do this combination. Merge the insns and
2542 update the status of registers and LOG_LINKS. */
2545 rtx i3notes
, i2notes
, i1notes
= 0;
2546 rtx i3links
, i2links
, i1links
= 0;
2549 /* Compute which registers we expect to eliminate. newi2pat may be setting
2550 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2551 same as i3dest, in which case newi2pat may be setting i1dest. */
2552 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2553 || i2dest_in_i2src
|| i2dest_in_i1src
2555 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2556 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2559 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2561 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2562 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2564 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2566 /* Ensure that we do not have something that should not be shared but
2567 occurs multiple times in the new insns. Check this by first
2568 resetting all the `used' flags and then copying anything is shared. */
2570 reset_used_flags (i3notes
);
2571 reset_used_flags (i2notes
);
2572 reset_used_flags (i1notes
);
2573 reset_used_flags (newpat
);
2574 reset_used_flags (newi2pat
);
2575 if (undobuf
.other_insn
)
2576 reset_used_flags (PATTERN (undobuf
.other_insn
));
2578 i3notes
= copy_rtx_if_shared (i3notes
);
2579 i2notes
= copy_rtx_if_shared (i2notes
);
2580 i1notes
= copy_rtx_if_shared (i1notes
);
2581 newpat
= copy_rtx_if_shared (newpat
);
2582 newi2pat
= copy_rtx_if_shared (newi2pat
);
2583 if (undobuf
.other_insn
)
2584 reset_used_flags (PATTERN (undobuf
.other_insn
));
2586 INSN_CODE (i3
) = insn_code_number
;
2587 PATTERN (i3
) = newpat
;
2589 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2591 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2593 reset_used_flags (call_usage
);
2594 call_usage
= copy_rtx (call_usage
);
2597 replace_rtx (call_usage
, i2dest
, i2src
);
2600 replace_rtx (call_usage
, i1dest
, i1src
);
2602 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2605 if (undobuf
.other_insn
)
2606 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2608 /* We had one special case above where I2 had more than one set and
2609 we replaced a destination of one of those sets with the destination
2610 of I3. In that case, we have to update LOG_LINKS of insns later
2611 in this basic block. Note that this (expensive) case is rare.
2613 Also, in this case, we must pretend that all REG_NOTEs for I2
2614 actually came from I3, so that REG_UNUSED notes from I2 will be
2615 properly handled. */
2617 if (i3_subst_into_i2
)
2619 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2620 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2621 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2622 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2623 && ! find_reg_note (i2
, REG_UNUSED
,
2624 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2625 for (temp
= NEXT_INSN (i2
);
2626 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2627 || this_basic_block
->head
!= temp
);
2628 temp
= NEXT_INSN (temp
))
2629 if (temp
!= i3
&& INSN_P (temp
))
2630 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2631 if (XEXP (link
, 0) == i2
)
2632 XEXP (link
, 0) = i3
;
2637 while (XEXP (link
, 1))
2638 link
= XEXP (link
, 1);
2639 XEXP (link
, 1) = i2notes
;
2653 INSN_CODE (i2
) = i2_code_number
;
2654 PATTERN (i2
) = newi2pat
;
2658 PUT_CODE (i2
, NOTE
);
2659 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2660 NOTE_SOURCE_FILE (i2
) = 0;
2667 PUT_CODE (i1
, NOTE
);
2668 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2669 NOTE_SOURCE_FILE (i1
) = 0;
2672 /* Get death notes for everything that is now used in either I3 or
2673 I2 and used to die in a previous insn. If we built two new
2674 patterns, move from I1 to I2 then I2 to I3 so that we get the
2675 proper movement on registers that I2 modifies. */
2679 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2680 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2683 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2686 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2688 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2691 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2694 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2697 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2700 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2701 know these are REG_UNUSED and want them to go to the desired insn,
2702 so we always pass it as i3. We have not counted the notes in
2703 reg_n_deaths yet, so we need to do so now. */
2705 if (newi2pat
&& new_i2_notes
)
2707 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2708 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2709 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2711 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2716 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2717 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2718 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2720 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2723 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2724 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2725 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2726 in that case, it might delete I2. Similarly for I2 and I1.
2727 Show an additional death due to the REG_DEAD note we make here. If
2728 we discard it in distribute_notes, we will decrement it again. */
2732 if (GET_CODE (i3dest_killed
) == REG
)
2733 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2735 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2736 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2738 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2740 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2742 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2746 if (i2dest_in_i2src
)
2748 if (GET_CODE (i2dest
) == REG
)
2749 REG_N_DEATHS (REGNO (i2dest
))++;
2751 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2752 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2753 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2755 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2756 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2757 NULL_RTX
, NULL_RTX
);
2760 if (i1dest_in_i1src
)
2762 if (GET_CODE (i1dest
) == REG
)
2763 REG_N_DEATHS (REGNO (i1dest
))++;
2765 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2766 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2767 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2769 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2770 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2771 NULL_RTX
, NULL_RTX
);
2774 distribute_links (i3links
);
2775 distribute_links (i2links
);
2776 distribute_links (i1links
);
2778 if (GET_CODE (i2dest
) == REG
)
2781 rtx i2_insn
= 0, i2_val
= 0, set
;
2783 /* The insn that used to set this register doesn't exist, and
2784 this life of the register may not exist either. See if one of
2785 I3's links points to an insn that sets I2DEST. If it does,
2786 that is now the last known value for I2DEST. If we don't update
2787 this and I2 set the register to a value that depended on its old
2788 contents, we will get confused. If this insn is used, thing
2789 will be set correctly in combine_instructions. */
2791 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2792 if ((set
= single_set (XEXP (link
, 0))) != 0
2793 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2794 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2796 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2798 /* If the reg formerly set in I2 died only once and that was in I3,
2799 zero its use count so it won't make `reload' do any work. */
2801 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2802 && ! i2dest_in_i2src
)
2804 regno
= REGNO (i2dest
);
2805 REG_N_SETS (regno
)--;
2809 if (i1
&& GET_CODE (i1dest
) == REG
)
2812 rtx i1_insn
= 0, i1_val
= 0, set
;
2814 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2815 if ((set
= single_set (XEXP (link
, 0))) != 0
2816 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2817 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2819 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2821 regno
= REGNO (i1dest
);
2822 if (! added_sets_1
&& ! i1dest_in_i1src
)
2823 REG_N_SETS (regno
)--;
2826 /* Update reg_nonzero_bits et al for any changes that may have been made
2827 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2828 important. Because newi2pat can affect nonzero_bits of newpat */
2830 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2831 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2833 /* Set new_direct_jump_p if a new return or simple jump instruction
2836 If I3 is now an unconditional jump, ensure that it has a
2837 BARRIER following it since it may have initially been a
2838 conditional jump. It may also be the last nonnote insn. */
2840 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2842 *new_direct_jump_p
= 1;
2844 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2845 || GET_CODE (temp
) != BARRIER
)
2846 emit_barrier_after (i3
);
2849 if (undobuf
.other_insn
!= NULL_RTX
2850 && (returnjump_p (undobuf
.other_insn
)
2851 || any_uncondjump_p (undobuf
.other_insn
)))
2853 *new_direct_jump_p
= 1;
2855 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2856 || GET_CODE (temp
) != BARRIER
)
2857 emit_barrier_after (undobuf
.other_insn
);
2860 /* An NOOP jump does not need barrier, but it does need cleaning up
2862 if (GET_CODE (newpat
) == SET
2863 && SET_SRC (newpat
) == pc_rtx
2864 && SET_DEST (newpat
) == pc_rtx
)
2865 *new_direct_jump_p
= 1;
2868 combine_successes
++;
2871 if (added_links_insn
2872 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2873 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2874 return added_links_insn
;
2876 return newi2pat
? i2
: i3
;
2879 /* Undo all the modifications recorded in undobuf. */
2884 struct undo
*undo
, *next
;
2886 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2890 *undo
->where
.i
= undo
->old_contents
.i
;
2892 *undo
->where
.r
= undo
->old_contents
.r
;
2894 undo
->next
= undobuf
.frees
;
2895 undobuf
.frees
= undo
;
2901 /* We've committed to accepting the changes we made. Move all
2902 of the undos to the free list. */
2907 struct undo
*undo
, *next
;
2909 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2912 undo
->next
= undobuf
.frees
;
2913 undobuf
.frees
= undo
;
2919 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2920 where we have an arithmetic expression and return that point. LOC will
2923 try_combine will call this function to see if an insn can be split into
2927 find_split_point (loc
, insn
)
2932 enum rtx_code code
= GET_CODE (x
);
2934 unsigned HOST_WIDE_INT len
= 0;
2935 HOST_WIDE_INT pos
= 0;
2937 rtx inner
= NULL_RTX
;
2939 /* First special-case some codes. */
2943 #ifdef INSN_SCHEDULING
2944 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2946 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2949 return find_split_point (&SUBREG_REG (x
), insn
);
2953 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2954 using LO_SUM and HIGH. */
2955 if (GET_CODE (XEXP (x
, 0)) == CONST
2956 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2959 gen_rtx_LO_SUM (Pmode
,
2960 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2962 return &XEXP (XEXP (x
, 0), 0);
2966 /* If we have a PLUS whose second operand is a constant and the
2967 address is not valid, perhaps will can split it up using
2968 the machine-specific way to split large constants. We use
2969 the first pseudo-reg (one of the virtual regs) as a placeholder;
2970 it will not remain in the result. */
2971 if (GET_CODE (XEXP (x
, 0)) == PLUS
2972 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2973 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2975 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2976 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2979 /* This should have produced two insns, each of which sets our
2980 placeholder. If the source of the second is a valid address,
2981 we can make put both sources together and make a split point
2985 && NEXT_INSN (seq
) != NULL_RTX
2986 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2987 && GET_CODE (seq
) == INSN
2988 && GET_CODE (PATTERN (seq
)) == SET
2989 && SET_DEST (PATTERN (seq
)) == reg
2990 && ! reg_mentioned_p (reg
,
2991 SET_SRC (PATTERN (seq
)))
2992 && GET_CODE (NEXT_INSN (seq
)) == INSN
2993 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2994 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2995 && memory_address_p (GET_MODE (x
),
2996 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2998 rtx src1
= SET_SRC (PATTERN (seq
));
2999 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3001 /* Replace the placeholder in SRC2 with SRC1. If we can
3002 find where in SRC2 it was placed, that can become our
3003 split point and we can replace this address with SRC2.
3004 Just try two obvious places. */
3006 src2
= replace_rtx (src2
, reg
, src1
);
3008 if (XEXP (src2
, 0) == src1
)
3009 split
= &XEXP (src2
, 0);
3010 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3011 && XEXP (XEXP (src2
, 0), 0) == src1
)
3012 split
= &XEXP (XEXP (src2
, 0), 0);
3016 SUBST (XEXP (x
, 0), src2
);
3021 /* If that didn't work, perhaps the first operand is complex and
3022 needs to be computed separately, so make a split point there.
3023 This will occur on machines that just support REG + CONST
3024 and have a constant moved through some previous computation. */
3026 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
3027 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3028 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
3030 return &XEXP (XEXP (x
, 0), 0);
3036 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3037 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3038 we need to put the operand into a register. So split at that
3041 if (SET_DEST (x
) == cc0_rtx
3042 && GET_CODE (SET_SRC (x
)) != COMPARE
3043 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3044 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
3045 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3046 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
3047 return &SET_SRC (x
);
3050 /* See if we can split SET_SRC as it stands. */
3051 split
= find_split_point (&SET_SRC (x
), insn
);
3052 if (split
&& split
!= &SET_SRC (x
))
3055 /* See if we can split SET_DEST as it stands. */
3056 split
= find_split_point (&SET_DEST (x
), insn
);
3057 if (split
&& split
!= &SET_DEST (x
))
3060 /* See if this is a bitfield assignment with everything constant. If
3061 so, this is an IOR of an AND, so split it into that. */
3062 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3063 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3064 <= HOST_BITS_PER_WIDE_INT
)
3065 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3066 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3067 && GET_CODE (SET_SRC (x
)) == CONST_INT
3068 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3069 + INTVAL (XEXP (SET_DEST (x
), 2)))
3070 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3071 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3073 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3074 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3075 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3076 rtx dest
= XEXP (SET_DEST (x
), 0);
3077 enum machine_mode mode
= GET_MODE (dest
);
3078 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3080 if (BITS_BIG_ENDIAN
)
3081 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3085 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3088 gen_binary (IOR
, mode
,
3089 gen_binary (AND
, mode
, dest
,
3090 gen_int_mode (~(mask
<< pos
),
3092 GEN_INT (src
<< pos
)));
3094 SUBST (SET_DEST (x
), dest
);
3096 split
= find_split_point (&SET_SRC (x
), insn
);
3097 if (split
&& split
!= &SET_SRC (x
))
3101 /* Otherwise, see if this is an operation that we can split into two.
3102 If so, try to split that. */
3103 code
= GET_CODE (SET_SRC (x
));
3108 /* If we are AND'ing with a large constant that is only a single
3109 bit and the result is only being used in a context where we
3110 need to know if it is zero or nonzero, replace it with a bit
3111 extraction. This will avoid the large constant, which might
3112 have taken more than one insn to make. If the constant were
3113 not a valid argument to the AND but took only one insn to make,
3114 this is no worse, but if it took more than one insn, it will
3117 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3118 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3119 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3120 && GET_CODE (SET_DEST (x
)) == REG
3121 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3122 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3123 && XEXP (*split
, 0) == SET_DEST (x
)
3124 && XEXP (*split
, 1) == const0_rtx
)
3126 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3127 XEXP (SET_SRC (x
), 0),
3128 pos
, NULL_RTX
, 1, 1, 0, 0);
3129 if (extraction
!= 0)
3131 SUBST (SET_SRC (x
), extraction
);
3132 return find_split_point (loc
, insn
);
3138 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3139 is known to be on, this can be converted into a NEG of a shift. */
3140 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3141 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3142 && 1 <= (pos
= exact_log2
3143 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3144 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3146 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3150 gen_rtx_LSHIFTRT (mode
,
3151 XEXP (SET_SRC (x
), 0),
3154 split
= find_split_point (&SET_SRC (x
), insn
);
3155 if (split
&& split
!= &SET_SRC (x
))
3161 inner
= XEXP (SET_SRC (x
), 0);
3163 /* We can't optimize if either mode is a partial integer
3164 mode as we don't know how many bits are significant
3166 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3167 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3171 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3177 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3178 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3180 inner
= XEXP (SET_SRC (x
), 0);
3181 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3182 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3184 if (BITS_BIG_ENDIAN
)
3185 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3186 unsignedp
= (code
== ZERO_EXTRACT
);
3194 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3196 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3198 /* For unsigned, we have a choice of a shift followed by an
3199 AND or two shifts. Use two shifts for field sizes where the
3200 constant might be too large. We assume here that we can
3201 always at least get 8-bit constants in an AND insn, which is
3202 true for every current RISC. */
3204 if (unsignedp
&& len
<= 8)
3209 (mode
, gen_lowpart_for_combine (mode
, inner
),
3211 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3213 split
= find_split_point (&SET_SRC (x
), insn
);
3214 if (split
&& split
!= &SET_SRC (x
))
3221 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3222 gen_rtx_ASHIFT (mode
,
3223 gen_lowpart_for_combine (mode
, inner
),
3224 GEN_INT (GET_MODE_BITSIZE (mode
)
3226 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3228 split
= find_split_point (&SET_SRC (x
), insn
);
3229 if (split
&& split
!= &SET_SRC (x
))
3234 /* See if this is a simple operation with a constant as the second
3235 operand. It might be that this constant is out of range and hence
3236 could be used as a split point. */
3237 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3238 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3239 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3240 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3241 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3242 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3243 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3245 return &XEXP (SET_SRC (x
), 1);
3247 /* Finally, see if this is a simple operation with its first operand
3248 not in a register. The operation might require this operand in a
3249 register, so return it as a split point. We can always do this
3250 because if the first operand were another operation, we would have
3251 already found it as a split point. */
3252 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3253 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3254 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3255 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3256 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3257 return &XEXP (SET_SRC (x
), 0);
3263 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3264 it is better to write this as (not (ior A B)) so we can split it.
3265 Similarly for IOR. */
3266 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3269 gen_rtx_NOT (GET_MODE (x
),
3270 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3272 XEXP (XEXP (x
, 0), 0),
3273 XEXP (XEXP (x
, 1), 0))));
3274 return find_split_point (loc
, insn
);
3277 /* Many RISC machines have a large set of logical insns. If the
3278 second operand is a NOT, put it first so we will try to split the
3279 other operand first. */
3280 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3282 rtx tem
= XEXP (x
, 0);
3283 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3284 SUBST (XEXP (x
, 1), tem
);
3292 /* Otherwise, select our actions depending on our rtx class. */
3293 switch (GET_RTX_CLASS (code
))
3295 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3297 split
= find_split_point (&XEXP (x
, 2), insn
);
3300 /* ... fall through ... */
3304 split
= find_split_point (&XEXP (x
, 1), insn
);
3307 /* ... fall through ... */
3309 /* Some machines have (and (shift ...) ...) insns. If X is not
3310 an AND, but XEXP (X, 0) is, use it as our split point. */
3311 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3312 return &XEXP (x
, 0);
3314 split
= find_split_point (&XEXP (x
, 0), insn
);
3320 /* Otherwise, we don't have a split point. */
3324 /* Throughout X, replace FROM with TO, and return the result.
3325 The result is TO if X is FROM;
3326 otherwise the result is X, but its contents may have been modified.
3327 If they were modified, a record was made in undobuf so that
3328 undo_all will (among other things) return X to its original state.
3330 If the number of changes necessary is too much to record to undo,
3331 the excess changes are not made, so the result is invalid.
3332 The changes already made can still be undone.
3333 undobuf.num_undo is incremented for such changes, so by testing that
3334 the caller can tell whether the result is valid.
3336 `n_occurrences' is incremented each time FROM is replaced.
3338 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3340 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3341 by copying if `n_occurrences' is nonzero. */
3344 subst (x
, from
, to
, in_dest
, unique_copy
)
3349 enum rtx_code code
= GET_CODE (x
);
3350 enum machine_mode op0_mode
= VOIDmode
;
3355 /* Two expressions are equal if they are identical copies of a shared
3356 RTX or if they are both registers with the same register number
3359 #define COMBINE_RTX_EQUAL_P(X,Y) \
3361 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3362 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3364 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3367 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3370 /* If X and FROM are the same register but different modes, they will
3371 not have been seen as equal above. However, flow.c will make a
3372 LOG_LINKS entry for that case. If we do nothing, we will try to
3373 rerecognize our original insn and, when it succeeds, we will
3374 delete the feeding insn, which is incorrect.
3376 So force this insn not to match in this (rare) case. */
3377 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3378 && REGNO (x
) == REGNO (from
))
3379 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3381 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3382 of which may contain things that can be combined. */
3383 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3386 /* It is possible to have a subexpression appear twice in the insn.
3387 Suppose that FROM is a register that appears within TO.
3388 Then, after that subexpression has been scanned once by `subst',
3389 the second time it is scanned, TO may be found. If we were
3390 to scan TO here, we would find FROM within it and create a
3391 self-referent rtl structure which is completely wrong. */
3392 if (COMBINE_RTX_EQUAL_P (x
, to
))
3395 /* Parallel asm_operands need special attention because all of the
3396 inputs are shared across the arms. Furthermore, unsharing the
3397 rtl results in recognition failures. Failure to handle this case
3398 specially can result in circular rtl.
3400 Solve this by doing a normal pass across the first entry of the
3401 parallel, and only processing the SET_DESTs of the subsequent
3404 if (code
== PARALLEL
3405 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3406 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3408 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3410 /* If this substitution failed, this whole thing fails. */
3411 if (GET_CODE (new) == CLOBBER
3412 && XEXP (new, 0) == const0_rtx
)
3415 SUBST (XVECEXP (x
, 0, 0), new);
3417 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3419 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3421 if (GET_CODE (dest
) != REG
3422 && GET_CODE (dest
) != CC0
3423 && GET_CODE (dest
) != PC
)
3425 new = subst (dest
, from
, to
, 0, unique_copy
);
3427 /* If this substitution failed, this whole thing fails. */
3428 if (GET_CODE (new) == CLOBBER
3429 && XEXP (new, 0) == const0_rtx
)
3432 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3438 len
= GET_RTX_LENGTH (code
);
3439 fmt
= GET_RTX_FORMAT (code
);
3441 /* We don't need to process a SET_DEST that is a register, CC0,
3442 or PC, so set up to skip this common case. All other cases
3443 where we want to suppress replacing something inside a
3444 SET_SRC are handled via the IN_DEST operand. */
3446 && (GET_CODE (SET_DEST (x
)) == REG
3447 || GET_CODE (SET_DEST (x
)) == CC0
3448 || GET_CODE (SET_DEST (x
)) == PC
))
3451 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3454 op0_mode
= GET_MODE (XEXP (x
, 0));
3456 for (i
= 0; i
< len
; i
++)
3461 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3463 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3465 new = (unique_copy
&& n_occurrences
3466 ? copy_rtx (to
) : to
);
3471 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3474 /* If this substitution failed, this whole thing
3476 if (GET_CODE (new) == CLOBBER
3477 && XEXP (new, 0) == const0_rtx
)
3481 SUBST (XVECEXP (x
, i
, j
), new);
3484 else if (fmt
[i
] == 'e')
3486 /* If this is a register being set, ignore it. */
3489 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3490 || code
== ZERO_EXTRACT
)
3492 && GET_CODE (new) == REG
)
3495 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3497 /* In general, don't install a subreg involving two
3498 modes not tieable. It can worsen register
3499 allocation, and can even make invalid reload
3500 insns, since the reg inside may need to be copied
3501 from in the outside mode, and that may be invalid
3502 if it is an fp reg copied in integer mode.
3504 We allow two exceptions to this: It is valid if
3505 it is inside another SUBREG and the mode of that
3506 SUBREG and the mode of the inside of TO is
3507 tieable and it is valid if X is a SET that copies
3510 if (GET_CODE (to
) == SUBREG
3511 && ! MODES_TIEABLE_P (GET_MODE (to
),
3512 GET_MODE (SUBREG_REG (to
)))
3513 && ! (code
== SUBREG
3514 && MODES_TIEABLE_P (GET_MODE (x
),
3515 GET_MODE (SUBREG_REG (to
))))
3517 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3520 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3522 #ifdef CANNOT_CHANGE_MODE_CLASS
3524 && GET_CODE (to
) == REG
3525 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3526 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3529 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3532 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3536 /* If we are in a SET_DEST, suppress most cases unless we
3537 have gone inside a MEM, in which case we want to
3538 simplify the address. We assume here that things that
3539 are actually part of the destination have their inner
3540 parts in the first expression. This is true for SUBREG,
3541 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3542 things aside from REG and MEM that should appear in a
3544 new = subst (XEXP (x
, i
), from
, to
,
3546 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3547 || code
== ZERO_EXTRACT
))
3549 && i
== 0), unique_copy
);
3551 /* If we found that we will have to reject this combination,
3552 indicate that by returning the CLOBBER ourselves, rather than
3553 an expression containing it. This will speed things up as
3554 well as prevent accidents where two CLOBBERs are considered
3555 to be equal, thus producing an incorrect simplification. */
3557 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3560 if (GET_CODE (new) == CONST_INT
&& GET_CODE (x
) == SUBREG
)
3562 enum machine_mode mode
= GET_MODE (x
);
3564 x
= simplify_subreg (GET_MODE (x
), new,
3565 GET_MODE (SUBREG_REG (x
)),
3568 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3570 else if (GET_CODE (new) == CONST_INT
3571 && GET_CODE (x
) == ZERO_EXTEND
)
3573 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3574 new, GET_MODE (XEXP (x
, 0)));
3579 SUBST (XEXP (x
, i
), new);
3584 /* Try to simplify X. If the simplification changed the code, it is likely
3585 that further simplification will help, so loop, but limit the number
3586 of repetitions that will be performed. */
3588 for (i
= 0; i
< 4; i
++)
3590 /* If X is sufficiently simple, don't bother trying to do anything
3592 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3593 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3595 if (GET_CODE (x
) == code
)
3598 code
= GET_CODE (x
);
3600 /* We no longer know the original mode of operand 0 since we
3601 have changed the form of X) */
3602 op0_mode
= VOIDmode
;
3608 /* Simplify X, a piece of RTL. We just operate on the expression at the
3609 outer level; call `subst' to simplify recursively. Return the new
3612 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3613 will be the iteration even if an expression with a code different from
3614 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3617 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3619 enum machine_mode op0_mode
;
3623 enum rtx_code code
= GET_CODE (x
);
3624 enum machine_mode mode
= GET_MODE (x
);
3629 /* If this is a commutative operation, put a constant last and a complex
3630 expression first. We don't need to do this for comparisons here. */
3631 if (GET_RTX_CLASS (code
) == 'c'
3632 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3635 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3636 SUBST (XEXP (x
, 1), temp
);
3639 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3640 sign extension of a PLUS with a constant, reverse the order of the sign
3641 extension and the addition. Note that this not the same as the original
3642 code, but overflow is undefined for signed values. Also note that the
3643 PLUS will have been partially moved "inside" the sign-extension, so that
3644 the first operand of X will really look like:
3645 (ashiftrt (plus (ashift A C4) C5) C4).
3647 (plus (ashiftrt (ashift A C4) C2) C4)
3648 and replace the first operand of X with that expression. Later parts
3649 of this function may simplify the expression further.
3651 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3652 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3653 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3655 We do this to simplify address expressions. */
3657 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3658 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3659 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3660 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3661 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3662 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3663 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3664 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3665 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3666 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3667 XEXP (XEXP (x
, 0), 1))) != 0)
3670 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3671 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3672 INTVAL (XEXP (XEXP (x
, 0), 1)));
3674 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3675 INTVAL (XEXP (XEXP (x
, 0), 1)));
3677 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3680 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3681 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3682 things. Check for cases where both arms are testing the same
3685 Don't do anything if all operands are very simple. */
3687 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3688 || GET_RTX_CLASS (code
) == '<')
3689 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3690 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3691 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3693 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3694 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3695 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3697 || (GET_RTX_CLASS (code
) == '1'
3698 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3699 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3700 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3703 rtx cond
, true_rtx
, false_rtx
;
3705 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3707 /* If everything is a comparison, what we have is highly unlikely
3708 to be simpler, so don't use it. */
3709 && ! (GET_RTX_CLASS (code
) == '<'
3710 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3711 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3713 rtx cop1
= const0_rtx
;
3714 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3716 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3719 /* Simplify the alternative arms; this may collapse the true and
3720 false arms to store-flag values. */
3721 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3722 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3724 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3725 is unlikely to be simpler. */
3726 if (general_operand (true_rtx
, VOIDmode
)
3727 && general_operand (false_rtx
, VOIDmode
))
3729 enum rtx_code reversed
;
3731 /* Restarting if we generate a store-flag expression will cause
3732 us to loop. Just drop through in this case. */
3734 /* If the result values are STORE_FLAG_VALUE and zero, we can
3735 just make the comparison operation. */
3736 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3737 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3738 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3739 && ((reversed
= reversed_comparison_code_parts
3740 (cond_code
, cond
, cop1
, NULL
))
3742 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3744 /* Likewise, we can make the negate of a comparison operation
3745 if the result values are - STORE_FLAG_VALUE and zero. */
3746 else if (GET_CODE (true_rtx
) == CONST_INT
3747 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3748 && false_rtx
== const0_rtx
)
3749 x
= simplify_gen_unary (NEG
, mode
,
3750 gen_binary (cond_code
, mode
, cond
,
3753 else if (GET_CODE (false_rtx
) == CONST_INT
3754 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3755 && true_rtx
== const0_rtx
3756 && ((reversed
= reversed_comparison_code_parts
3757 (cond_code
, cond
, cop1
, NULL
))
3759 x
= simplify_gen_unary (NEG
, mode
,
3760 gen_binary (reversed
, mode
,
3764 return gen_rtx_IF_THEN_ELSE (mode
,
3765 gen_binary (cond_code
, VOIDmode
,
3767 true_rtx
, false_rtx
);
3769 code
= GET_CODE (x
);
3770 op0_mode
= VOIDmode
;
3775 /* Try to fold this expression in case we have constants that weren't
3778 switch (GET_RTX_CLASS (code
))
3781 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3785 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3786 if (cmp_mode
== VOIDmode
)
3788 cmp_mode
= GET_MODE (XEXP (x
, 1));
3789 if (cmp_mode
== VOIDmode
)
3790 cmp_mode
= op0_mode
;
3792 temp
= simplify_relational_operation (code
, cmp_mode
,
3793 XEXP (x
, 0), XEXP (x
, 1));
3795 #ifdef FLOAT_STORE_FLAG_VALUE
3796 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3798 if (temp
== const0_rtx
)
3799 temp
= CONST0_RTX (mode
);
3801 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3808 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3812 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3813 XEXP (x
, 1), XEXP (x
, 2));
3820 code
= GET_CODE (temp
);
3821 op0_mode
= VOIDmode
;
3822 mode
= GET_MODE (temp
);
3825 /* First see if we can apply the inverse distributive law. */
3826 if (code
== PLUS
|| code
== MINUS
3827 || code
== AND
|| code
== IOR
|| code
== XOR
)
3829 x
= apply_distributive_law (x
);
3830 code
= GET_CODE (x
);
3831 op0_mode
= VOIDmode
;
3834 /* If CODE is an associative operation not otherwise handled, see if we
3835 can associate some operands. This can win if they are constants or
3836 if they are logically related (i.e. (a & b) & a). */
3837 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3838 || code
== AND
|| code
== IOR
|| code
== XOR
3839 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3840 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3841 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3843 if (GET_CODE (XEXP (x
, 0)) == code
)
3845 rtx other
= XEXP (XEXP (x
, 0), 0);
3846 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3847 rtx inner_op1
= XEXP (x
, 1);
3850 /* Make sure we pass the constant operand if any as the second
3851 one if this is a commutative operation. */
3852 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3854 rtx tem
= inner_op0
;
3855 inner_op0
= inner_op1
;
3858 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3859 : code
== DIV
? MULT
3861 mode
, inner_op0
, inner_op1
);
3863 /* For commutative operations, try the other pair if that one
3865 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3867 other
= XEXP (XEXP (x
, 0), 1);
3868 inner
= simplify_binary_operation (code
, mode
,
3869 XEXP (XEXP (x
, 0), 0),
3874 return gen_binary (code
, mode
, other
, inner
);
3878 /* A little bit of algebraic simplification here. */
3882 /* Ensure that our address has any ASHIFTs converted to MULT in case
3883 address-recognizing predicates are called later. */
3884 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3885 SUBST (XEXP (x
, 0), temp
);
3889 if (op0_mode
== VOIDmode
)
3890 op0_mode
= GET_MODE (SUBREG_REG (x
));
3892 /* simplify_subreg can't use gen_lowpart_for_combine. */
3893 if (CONSTANT_P (SUBREG_REG (x
))
3894 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3895 /* Don't call gen_lowpart_for_combine if the inner mode
3896 is VOIDmode and we cannot simplify it, as SUBREG without
3897 inner mode is invalid. */
3898 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3899 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3900 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3902 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3906 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3912 /* Don't change the mode of the MEM if that would change the meaning
3914 if (GET_CODE (SUBREG_REG (x
)) == MEM
3915 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3916 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3917 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3919 /* Note that we cannot do any narrowing for non-constants since
3920 we might have been counting on using the fact that some bits were
3921 zero. We now do this in the SET. */
3926 /* (not (plus X -1)) can become (neg X). */
3927 if (GET_CODE (XEXP (x
, 0)) == PLUS
3928 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3929 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3931 /* Similarly, (not (neg X)) is (plus X -1). */
3932 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3933 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3935 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3936 if (GET_CODE (XEXP (x
, 0)) == XOR
3937 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3938 && (temp
= simplify_unary_operation (NOT
, mode
,
3939 XEXP (XEXP (x
, 0), 1),
3941 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3943 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3944 other than 1, but that is not valid. We could do a similar
3945 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3946 but this doesn't seem common enough to bother with. */
3947 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3948 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3949 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3951 XEXP (XEXP (x
, 0), 1));
3953 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3954 && subreg_lowpart_p (XEXP (x
, 0))
3955 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3956 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3957 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3958 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3960 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3962 x
= gen_rtx_ROTATE (inner_mode
,
3963 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3965 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3966 return gen_lowpart_for_combine (mode
, x
);
3969 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3970 reversing the comparison code if valid. */
3971 if (STORE_FLAG_VALUE
== -1
3972 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3973 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3974 XEXP (XEXP (x
, 0), 1))))
3977 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3978 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3979 perform the above simplification. */
3981 if (STORE_FLAG_VALUE
== -1
3982 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3983 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3984 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3985 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3987 /* Apply De Morgan's laws to reduce number of patterns for machines
3988 with negating logical insns (and-not, nand, etc.). If result has
3989 only one NOT, put it first, since that is how the patterns are
3992 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3994 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3995 enum machine_mode op_mode
;
3997 op_mode
= GET_MODE (in1
);
3998 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
4000 op_mode
= GET_MODE (in2
);
4001 if (op_mode
== VOIDmode
)
4003 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4005 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4008 in2
= in1
; in1
= tem
;
4011 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4017 /* (neg (plus X 1)) can become (not X). */
4018 if (GET_CODE (XEXP (x
, 0)) == PLUS
4019 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
4020 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
4022 /* Similarly, (neg (not X)) is (plus X 1). */
4023 if (GET_CODE (XEXP (x
, 0)) == NOT
)
4024 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
4026 /* (neg (minus X Y)) can become (minus Y X). This transformation
4027 isn't safe for modes with signed zeros, since if X and Y are
4028 both +0, (minus Y X) is the same as (minus X Y). If the rounding
4029 mode is towards +infinity (or -infinity) then the two expressions
4030 will be rounded differently. */
4031 if (GET_CODE (XEXP (x
, 0)) == MINUS
4032 && !HONOR_SIGNED_ZEROS (mode
)
4033 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
4034 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
4035 XEXP (XEXP (x
, 0), 0));
4037 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
4038 if (GET_CODE (XEXP (x
, 0)) == PLUS
4039 && !HONOR_SIGNED_ZEROS (mode
)
4040 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
4042 temp
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 0), 0), mode
);
4043 temp
= combine_simplify_rtx (temp
, mode
, last
, in_dest
);
4044 return gen_binary (MINUS
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
4047 /* (neg (mult A B)) becomes (mult (neg A) B).
4048 This works even for floating-point values. */
4049 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4051 temp
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 0), 0), mode
);
4052 return gen_binary (MULT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
4055 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4056 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
4057 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4058 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4060 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4061 if we can then eliminate the NEG (e.g.,
4062 if the operand is a constant). */
4064 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
4066 temp
= simplify_unary_operation (NEG
, mode
,
4067 XEXP (XEXP (x
, 0), 0), mode
);
4069 return gen_binary (ASHIFT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
4072 temp
= expand_compound_operation (XEXP (x
, 0));
4074 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4075 replaced by (lshiftrt X C). This will convert
4076 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4078 if (GET_CODE (temp
) == ASHIFTRT
4079 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4080 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4081 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4082 INTVAL (XEXP (temp
, 1)));
4084 /* If X has only a single bit that might be nonzero, say, bit I, convert
4085 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4086 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4087 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4088 or a SUBREG of one since we'd be making the expression more
4089 complex if it was just a register. */
4091 if (GET_CODE (temp
) != REG
4092 && ! (GET_CODE (temp
) == SUBREG
4093 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4094 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4096 rtx temp1
= simplify_shift_const
4097 (NULL_RTX
, ASHIFTRT
, mode
,
4098 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4099 GET_MODE_BITSIZE (mode
) - 1 - i
),
4100 GET_MODE_BITSIZE (mode
) - 1 - i
);
4102 /* If all we did was surround TEMP with the two shifts, we
4103 haven't improved anything, so don't use it. Otherwise,
4104 we are better off with TEMP1. */
4105 if (GET_CODE (temp1
) != ASHIFTRT
4106 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4107 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4113 /* We can't handle truncation to a partial integer mode here
4114 because we don't know the real bitsize of the partial
4116 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4119 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4120 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4121 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4123 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4124 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4126 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4127 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4128 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4129 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4130 return XEXP (XEXP (x
, 0), 0);
4132 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4133 (OP:SI foo:SI) if OP is NEG or ABS. */
4134 if ((GET_CODE (XEXP (x
, 0)) == ABS
4135 || GET_CODE (XEXP (x
, 0)) == NEG
)
4136 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4137 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4138 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4139 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4140 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4142 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4144 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4145 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4146 && subreg_lowpart_p (XEXP (x
, 0)))
4147 return SUBREG_REG (XEXP (x
, 0));
4149 /* If we know that the value is already truncated, we can
4150 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4151 is nonzero for the corresponding modes. But don't do this
4152 for an (LSHIFTRT (MULT ...)) since this will cause problems
4153 with the umulXi3_highpart patterns. */
4154 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4155 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4156 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4157 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4158 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4159 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4160 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4162 /* A truncate of a comparison can be replaced with a subreg if
4163 STORE_FLAG_VALUE permits. This is like the previous test,
4164 but it works even if the comparison is done in a mode larger
4165 than HOST_BITS_PER_WIDE_INT. */
4166 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4167 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4168 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4169 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4171 /* Similarly, a truncate of a register whose value is a
4172 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4174 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4175 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4176 && (temp
= get_last_value (XEXP (x
, 0)))
4177 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4178 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4182 case FLOAT_TRUNCATE
:
4183 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4184 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4185 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4186 return XEXP (XEXP (x
, 0), 0);
4188 /* (float_truncate:SF (float_truncate:DF foo:XF))
4189 = (float_truncate:SF foo:XF).
4190 This may elliminate double rounding, so it is unsafe.
4192 (float_truncate:SF (float_extend:XF foo:DF))
4193 = (float_truncate:SF foo:DF).
4195 (float_truncate:DF (float_extend:XF foo:SF))
4196 = (float_extend:SF foo:DF). */
4197 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4198 && flag_unsafe_math_optimizations
)
4199 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4200 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4202 > GET_MODE_SIZE (mode
)
4203 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4205 XEXP (XEXP (x
, 0), 0), mode
);
4207 /* (float_truncate (float x)) is (float x) */
4208 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4209 && (flag_unsafe_math_optimizations
4210 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4211 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4212 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4213 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4214 return simplify_gen_unary (FLOAT
, mode
,
4215 XEXP (XEXP (x
, 0), 0),
4216 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4218 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4219 (OP:SF foo:SF) if OP is NEG or ABS. */
4220 if ((GET_CODE (XEXP (x
, 0)) == ABS
4221 || GET_CODE (XEXP (x
, 0)) == NEG
)
4222 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4223 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4224 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4225 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4227 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4228 is (float_truncate:SF x). */
4229 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4230 && subreg_lowpart_p (XEXP (x
, 0))
4231 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4232 return SUBREG_REG (XEXP (x
, 0));
4235 /* (float_extend (float_extend x)) is (float_extend x)
4237 (float_extend (float x)) is (float x) assuming that double
4238 rounding can't happen.
4240 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4241 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4242 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4243 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4244 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4245 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4246 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4247 XEXP (XEXP (x
, 0), 0),
4248 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4253 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4254 using cc0, in which case we want to leave it as a COMPARE
4255 so we can distinguish it from a register-register-copy. */
4256 if (XEXP (x
, 1) == const0_rtx
)
4259 /* x - 0 is the same as x unless x's mode has signed zeros and
4260 allows rounding towards -infinity. Under those conditions,
4262 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4263 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4264 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4270 /* (const (const X)) can become (const X). Do it this way rather than
4271 returning the inner CONST since CONST can be shared with a
4273 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4274 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4279 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4280 can add in an offset. find_split_point will split this address up
4281 again if it doesn't match. */
4282 if (GET_CODE (XEXP (x
, 0)) == HIGH
4283 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4289 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4291 if (GET_CODE (XEXP (x
, 0)) == MULT
4292 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4296 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4297 in2
= XEXP (XEXP (x
, 0), 1);
4298 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4299 gen_binary (MULT
, mode
, in1
, in2
));
4302 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4303 outermost. That's because that's the way indexed addresses are
4304 supposed to appear. This code used to check many more cases, but
4305 they are now checked elsewhere. */
4306 if (GET_CODE (XEXP (x
, 0)) == PLUS
4307 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4308 return gen_binary (PLUS
, mode
,
4309 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4311 XEXP (XEXP (x
, 0), 1));
4313 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4314 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4315 bit-field and can be replaced by either a sign_extend or a
4316 sign_extract. The `and' may be a zero_extend and the two
4317 <c>, -<c> constants may be reversed. */
4318 if (GET_CODE (XEXP (x
, 0)) == XOR
4319 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4320 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4321 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4322 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4323 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4324 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4325 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4326 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4327 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4328 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4329 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4330 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4331 == (unsigned int) i
+ 1))))
4332 return simplify_shift_const
4333 (NULL_RTX
, ASHIFTRT
, mode
,
4334 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4335 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4336 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4337 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4339 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4340 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4341 is 1. This produces better code than the alternative immediately
4343 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4344 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4345 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4346 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4347 XEXP (XEXP (x
, 0), 0),
4348 XEXP (XEXP (x
, 0), 1))))
4350 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4352 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4353 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4354 the bitsize of the mode - 1. This allows simplification of
4355 "a = (b & 8) == 0;" */
4356 if (XEXP (x
, 1) == constm1_rtx
4357 && GET_CODE (XEXP (x
, 0)) != REG
4358 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4359 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4360 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4361 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4362 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4363 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4364 GET_MODE_BITSIZE (mode
) - 1),
4365 GET_MODE_BITSIZE (mode
) - 1);
4367 /* If we are adding two things that have no bits in common, convert
4368 the addition into an IOR. This will often be further simplified,
4369 for example in cases like ((a & 1) + (a & 2)), which can
4372 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4373 && (nonzero_bits (XEXP (x
, 0), mode
)
4374 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4376 /* Try to simplify the expression further. */
4377 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4378 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4380 /* If we could, great. If not, do not go ahead with the IOR
4381 replacement, since PLUS appears in many special purpose
4382 address arithmetic instructions. */
4383 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4389 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4390 by reversing the comparison code if valid. */
4391 if (STORE_FLAG_VALUE
== 1
4392 && XEXP (x
, 0) == const1_rtx
4393 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4394 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4395 XEXP (XEXP (x
, 1), 0),
4396 XEXP (XEXP (x
, 1), 1))))
4399 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4400 (and <foo> (const_int pow2-1)) */
4401 if (GET_CODE (XEXP (x
, 1)) == AND
4402 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4403 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4404 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4405 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4406 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4408 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4410 if (GET_CODE (XEXP (x
, 1)) == MULT
4411 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4415 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4416 in2
= XEXP (XEXP (x
, 1), 1);
4417 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4421 /* Canonicalize (minus (neg A) (mult B C)) to
4422 (minus (mult (neg B) C) A). */
4423 if (GET_CODE (XEXP (x
, 1)) == MULT
4424 && GET_CODE (XEXP (x
, 0)) == NEG
)
4428 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4429 in2
= XEXP (XEXP (x
, 1), 1);
4430 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4431 XEXP (XEXP (x
, 0), 0));
4434 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4436 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4437 return gen_binary (MINUS
, mode
,
4438 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4439 XEXP (XEXP (x
, 1), 0)),
4440 XEXP (XEXP (x
, 1), 1));
4444 /* If we have (mult (plus A B) C), apply the distributive law and then
4445 the inverse distributive law to see if things simplify. This
4446 occurs mostly in addresses, often when unrolling loops. */
4448 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4450 x
= apply_distributive_law
4451 (gen_binary (PLUS
, mode
,
4452 gen_binary (MULT
, mode
,
4453 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4454 gen_binary (MULT
, mode
,
4455 XEXP (XEXP (x
, 0), 1),
4456 copy_rtx (XEXP (x
, 1)))));
4458 if (GET_CODE (x
) != MULT
)
4461 /* Try simplify a*(b/c) as (a*b)/c. */
4462 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4463 && GET_CODE (XEXP (x
, 0)) == DIV
)
4465 rtx tem
= simplify_binary_operation (MULT
, mode
,
4466 XEXP (XEXP (x
, 0), 0),
4469 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4474 /* If this is a divide by a power of two, treat it as a shift if
4475 its first operand is a shift. */
4476 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4477 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4478 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4479 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4480 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4481 || GET_CODE (XEXP (x
, 0)) == ROTATE
4482 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4483 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4487 case GT
: case GTU
: case GE
: case GEU
:
4488 case LT
: case LTU
: case LE
: case LEU
:
4489 case UNEQ
: case LTGT
:
4490 case UNGT
: case UNGE
:
4491 case UNLT
: case UNLE
:
4492 case UNORDERED
: case ORDERED
:
4493 /* If the first operand is a condition code, we can't do anything
4495 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4496 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4497 && ! CC0_P (XEXP (x
, 0))))
4499 rtx op0
= XEXP (x
, 0);
4500 rtx op1
= XEXP (x
, 1);
4501 enum rtx_code new_code
;
4503 if (GET_CODE (op0
) == COMPARE
)
4504 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4506 /* Simplify our comparison, if possible. */
4507 new_code
= simplify_comparison (code
, &op0
, &op1
);
4509 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4510 if only the low-order bit is possibly nonzero in X (such as when
4511 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4512 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4513 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4516 Remove any ZERO_EXTRACT we made when thinking this was a
4517 comparison. It may now be simpler to use, e.g., an AND. If a
4518 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4519 the call to make_compound_operation in the SET case. */
4521 if (STORE_FLAG_VALUE
== 1
4522 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4523 && op1
== const0_rtx
4524 && mode
== GET_MODE (op0
)
4525 && nonzero_bits (op0
, mode
) == 1)
4526 return gen_lowpart_for_combine (mode
,
4527 expand_compound_operation (op0
));
4529 else if (STORE_FLAG_VALUE
== 1
4530 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4531 && op1
== const0_rtx
4532 && mode
== GET_MODE (op0
)
4533 && (num_sign_bit_copies (op0
, mode
)
4534 == GET_MODE_BITSIZE (mode
)))
4536 op0
= expand_compound_operation (op0
);
4537 return simplify_gen_unary (NEG
, mode
,
4538 gen_lowpart_for_combine (mode
, op0
),
4542 else if (STORE_FLAG_VALUE
== 1
4543 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4544 && op1
== const0_rtx
4545 && mode
== GET_MODE (op0
)
4546 && nonzero_bits (op0
, mode
) == 1)
4548 op0
= expand_compound_operation (op0
);
4549 return gen_binary (XOR
, mode
,
4550 gen_lowpart_for_combine (mode
, op0
),
4554 else if (STORE_FLAG_VALUE
== 1
4555 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4556 && op1
== const0_rtx
4557 && mode
== GET_MODE (op0
)
4558 && (num_sign_bit_copies (op0
, mode
)
4559 == GET_MODE_BITSIZE (mode
)))
4561 op0
= expand_compound_operation (op0
);
4562 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4565 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4567 if (STORE_FLAG_VALUE
== -1
4568 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4569 && op1
== const0_rtx
4570 && (num_sign_bit_copies (op0
, mode
)
4571 == GET_MODE_BITSIZE (mode
)))
4572 return gen_lowpart_for_combine (mode
,
4573 expand_compound_operation (op0
));
4575 else if (STORE_FLAG_VALUE
== -1
4576 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4577 && op1
== const0_rtx
4578 && mode
== GET_MODE (op0
)
4579 && nonzero_bits (op0
, mode
) == 1)
4581 op0
= expand_compound_operation (op0
);
4582 return simplify_gen_unary (NEG
, mode
,
4583 gen_lowpart_for_combine (mode
, op0
),
4587 else if (STORE_FLAG_VALUE
== -1
4588 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4589 && op1
== const0_rtx
4590 && mode
== GET_MODE (op0
)
4591 && (num_sign_bit_copies (op0
, mode
)
4592 == GET_MODE_BITSIZE (mode
)))
4594 op0
= expand_compound_operation (op0
);
4595 return simplify_gen_unary (NOT
, mode
,
4596 gen_lowpart_for_combine (mode
, op0
),
4600 /* If X is 0/1, (eq X 0) is X-1. */
4601 else if (STORE_FLAG_VALUE
== -1
4602 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4603 && op1
== const0_rtx
4604 && mode
== GET_MODE (op0
)
4605 && nonzero_bits (op0
, mode
) == 1)
4607 op0
= expand_compound_operation (op0
);
4608 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4611 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4612 one bit that might be nonzero, we can convert (ne x 0) to
4613 (ashift x c) where C puts the bit in the sign bit. Remove any
4614 AND with STORE_FLAG_VALUE when we are done, since we are only
4615 going to test the sign bit. */
4616 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4617 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4618 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4619 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4620 && op1
== const0_rtx
4621 && mode
== GET_MODE (op0
)
4622 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4624 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4625 expand_compound_operation (op0
),
4626 GET_MODE_BITSIZE (mode
) - 1 - i
);
4627 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4633 /* If the code changed, return a whole new comparison. */
4634 if (new_code
!= code
)
4635 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4637 /* Otherwise, keep this operation, but maybe change its operands.
4638 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4639 SUBST (XEXP (x
, 0), op0
);
4640 SUBST (XEXP (x
, 1), op1
);
4645 return simplify_if_then_else (x
);
4651 /* If we are processing SET_DEST, we are done. */
4655 return expand_compound_operation (x
);
4658 return simplify_set (x
);
4663 return simplify_logical (x
, last
);
4666 /* (abs (neg <foo>)) -> (abs <foo>) */
4667 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4668 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4670 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4672 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4675 /* If operand is something known to be positive, ignore the ABS. */
4676 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4677 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4678 <= HOST_BITS_PER_WIDE_INT
)
4679 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4680 & ((HOST_WIDE_INT
) 1
4681 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4685 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4686 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4687 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4692 /* (ffs (*_extend <X>)) = (ffs <X>) */
4693 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4694 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4695 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4700 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4701 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4702 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4706 /* (float (sign_extend <X>)) = (float <X>). */
4707 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4708 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4716 /* If this is a shift by a constant amount, simplify it. */
4717 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4718 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4719 INTVAL (XEXP (x
, 1)));
4721 #ifdef SHIFT_COUNT_TRUNCATED
4722 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4724 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4726 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4735 rtx op0
= XEXP (x
, 0);
4736 rtx op1
= XEXP (x
, 1);
4739 if (GET_CODE (op1
) != PARALLEL
)
4741 len
= XVECLEN (op1
, 0);
4743 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4744 && GET_CODE (op0
) == VEC_CONCAT
)
4746 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4748 /* Try to find the element in the VEC_CONCAT. */
4751 if (GET_MODE (op0
) == GET_MODE (x
))
4753 if (GET_CODE (op0
) == VEC_CONCAT
)
4755 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4756 if (op0_size
< offset
)
4757 op0
= XEXP (op0
, 0);
4761 op0
= XEXP (op0
, 1);
4779 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4782 simplify_if_then_else (x
)
4785 enum machine_mode mode
= GET_MODE (x
);
4786 rtx cond
= XEXP (x
, 0);
4787 rtx true_rtx
= XEXP (x
, 1);
4788 rtx false_rtx
= XEXP (x
, 2);
4789 enum rtx_code true_code
= GET_CODE (cond
);
4790 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4793 enum rtx_code false_code
;
4796 /* Simplify storing of the truth value. */
4797 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4798 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4800 /* Also when the truth value has to be reversed. */
4802 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4803 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4807 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4808 in it is being compared against certain values. Get the true and false
4809 comparisons and see if that says anything about the value of each arm. */
4812 && ((false_code
= combine_reversed_comparison_code (cond
))
4814 && GET_CODE (XEXP (cond
, 0)) == REG
)
4817 rtx from
= XEXP (cond
, 0);
4818 rtx true_val
= XEXP (cond
, 1);
4819 rtx false_val
= true_val
;
4822 /* If FALSE_CODE is EQ, swap the codes and arms. */
4824 if (false_code
== EQ
)
4826 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4827 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4830 /* If we are comparing against zero and the expression being tested has
4831 only a single bit that might be nonzero, that is its value when it is
4832 not equal to zero. Similarly if it is known to be -1 or 0. */
4834 if (true_code
== EQ
&& true_val
== const0_rtx
4835 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4836 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4837 else if (true_code
== EQ
&& true_val
== const0_rtx
4838 && (num_sign_bit_copies (from
, GET_MODE (from
))
4839 == GET_MODE_BITSIZE (GET_MODE (from
))))
4840 false_code
= EQ
, false_val
= constm1_rtx
;
4842 /* Now simplify an arm if we know the value of the register in the
4843 branch and it is used in the arm. Be careful due to the potential
4844 of locally-shared RTL. */
4846 if (reg_mentioned_p (from
, true_rtx
))
4847 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4849 pc_rtx
, pc_rtx
, 0, 0);
4850 if (reg_mentioned_p (from
, false_rtx
))
4851 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4853 pc_rtx
, pc_rtx
, 0, 0);
4855 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4856 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4858 true_rtx
= XEXP (x
, 1);
4859 false_rtx
= XEXP (x
, 2);
4860 true_code
= GET_CODE (cond
);
4863 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4864 reversed, do so to avoid needing two sets of patterns for
4865 subtract-and-branch insns. Similarly if we have a constant in the true
4866 arm, the false arm is the same as the first operand of the comparison, or
4867 the false arm is more complicated than the true arm. */
4870 && combine_reversed_comparison_code (cond
) != UNKNOWN
4871 && (true_rtx
== pc_rtx
4872 || (CONSTANT_P (true_rtx
)
4873 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4874 || true_rtx
== const0_rtx
4875 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4876 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4877 || (GET_CODE (true_rtx
) == SUBREG
4878 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4879 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4880 || reg_mentioned_p (true_rtx
, false_rtx
)
4881 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4883 true_code
= reversed_comparison_code (cond
, NULL
);
4885 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4888 SUBST (XEXP (x
, 1), false_rtx
);
4889 SUBST (XEXP (x
, 2), true_rtx
);
4891 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4894 /* It is possible that the conditional has been simplified out. */
4895 true_code
= GET_CODE (cond
);
4896 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4899 /* If the two arms are identical, we don't need the comparison. */
4901 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4904 /* Convert a == b ? b : a to "a". */
4905 if (true_code
== EQ
&& ! side_effects_p (cond
)
4906 && !HONOR_NANS (mode
)
4907 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4908 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4910 else if (true_code
== NE
&& ! side_effects_p (cond
)
4911 && !HONOR_NANS (mode
)
4912 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4913 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4916 /* Look for cases where we have (abs x) or (neg (abs X)). */
4918 if (GET_MODE_CLASS (mode
) == MODE_INT
4919 && GET_CODE (false_rtx
) == NEG
4920 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4922 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4923 && ! side_effects_p (true_rtx
))
4928 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4932 simplify_gen_unary (NEG
, mode
,
4933 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4939 /* Look for MIN or MAX. */
4941 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4943 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4944 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4945 && ! side_effects_p (cond
))
4950 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4953 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4956 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4959 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4964 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4965 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4966 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4967 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4968 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4969 neither 1 or -1, but it isn't worth checking for. */
4971 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4972 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4974 rtx t
= make_compound_operation (true_rtx
, SET
);
4975 rtx f
= make_compound_operation (false_rtx
, SET
);
4976 rtx cond_op0
= XEXP (cond
, 0);
4977 rtx cond_op1
= XEXP (cond
, 1);
4978 enum rtx_code op
= NIL
, extend_op
= NIL
;
4979 enum machine_mode m
= mode
;
4980 rtx z
= 0, c1
= NULL_RTX
;
4982 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4983 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4984 || GET_CODE (t
) == ASHIFT
4985 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4986 && rtx_equal_p (XEXP (t
, 0), f
))
4987 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4989 /* If an identity-zero op is commutative, check whether there
4990 would be a match if we swapped the operands. */
4991 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4992 || GET_CODE (t
) == XOR
)
4993 && rtx_equal_p (XEXP (t
, 1), f
))
4994 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4995 else if (GET_CODE (t
) == SIGN_EXTEND
4996 && (GET_CODE (XEXP (t
, 0)) == PLUS
4997 || GET_CODE (XEXP (t
, 0)) == MINUS
4998 || GET_CODE (XEXP (t
, 0)) == IOR
4999 || GET_CODE (XEXP (t
, 0)) == XOR
5000 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5001 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5002 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5003 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5004 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5005 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5006 && (num_sign_bit_copies (f
, GET_MODE (f
))
5008 (GET_MODE_BITSIZE (mode
)
5009 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
5011 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5012 extend_op
= SIGN_EXTEND
;
5013 m
= GET_MODE (XEXP (t
, 0));
5015 else if (GET_CODE (t
) == SIGN_EXTEND
5016 && (GET_CODE (XEXP (t
, 0)) == PLUS
5017 || GET_CODE (XEXP (t
, 0)) == IOR
5018 || GET_CODE (XEXP (t
, 0)) == XOR
)
5019 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5020 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5021 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5022 && (num_sign_bit_copies (f
, GET_MODE (f
))
5024 (GET_MODE_BITSIZE (mode
)
5025 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5027 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5028 extend_op
= SIGN_EXTEND
;
5029 m
= GET_MODE (XEXP (t
, 0));
5031 else if (GET_CODE (t
) == ZERO_EXTEND
5032 && (GET_CODE (XEXP (t
, 0)) == PLUS
5033 || GET_CODE (XEXP (t
, 0)) == MINUS
5034 || GET_CODE (XEXP (t
, 0)) == IOR
5035 || GET_CODE (XEXP (t
, 0)) == XOR
5036 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5037 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5038 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5039 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5040 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5041 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5042 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5043 && ((nonzero_bits (f
, GET_MODE (f
))
5044 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5047 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5048 extend_op
= ZERO_EXTEND
;
5049 m
= GET_MODE (XEXP (t
, 0));
5051 else if (GET_CODE (t
) == ZERO_EXTEND
5052 && (GET_CODE (XEXP (t
, 0)) == PLUS
5053 || GET_CODE (XEXP (t
, 0)) == IOR
5054 || GET_CODE (XEXP (t
, 0)) == XOR
)
5055 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5056 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5057 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5058 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5059 && ((nonzero_bits (f
, GET_MODE (f
))
5060 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5063 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5064 extend_op
= ZERO_EXTEND
;
5065 m
= GET_MODE (XEXP (t
, 0));
5070 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
5071 pc_rtx
, pc_rtx
, 0, 0);
5072 temp
= gen_binary (MULT
, m
, temp
,
5073 gen_binary (MULT
, m
, c1
, const_true_rtx
));
5074 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5075 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
5077 if (extend_op
!= NIL
)
5078 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5084 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5085 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5086 negation of a single bit, we can convert this operation to a shift. We
5087 can actually do this more generally, but it doesn't seem worth it. */
5089 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5090 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5091 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5092 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5093 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5094 == GET_MODE_BITSIZE (mode
))
5095 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5097 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5098 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
5103 /* Simplify X, a SET expression. Return the new expression. */
5109 rtx src
= SET_SRC (x
);
5110 rtx dest
= SET_DEST (x
);
5111 enum machine_mode mode
5112 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5116 /* (set (pc) (return)) gets written as (return). */
5117 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5120 /* Now that we know for sure which bits of SRC we are using, see if we can
5121 simplify the expression for the object knowing that we only need the
5124 if (GET_MODE_CLASS (mode
) == MODE_INT
5125 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5127 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5128 SUBST (SET_SRC (x
), src
);
5131 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5132 the comparison result and try to simplify it unless we already have used
5133 undobuf.other_insn. */
5134 if ((GET_MODE_CLASS (mode
) == MODE_CC
5135 || GET_CODE (src
) == COMPARE
5137 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5138 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5139 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
5140 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5142 enum rtx_code old_code
= GET_CODE (*cc_use
);
5143 enum rtx_code new_code
;
5145 int other_changed
= 0;
5146 enum machine_mode compare_mode
= GET_MODE (dest
);
5147 enum machine_mode tmp_mode
;
5149 if (GET_CODE (src
) == COMPARE
)
5150 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5152 op0
= src
, op1
= const0_rtx
;
5154 /* Check whether the comparison is known at compile time. */
5155 if (GET_MODE (op0
) != VOIDmode
)
5156 tmp_mode
= GET_MODE (op0
);
5157 else if (GET_MODE (op1
) != VOIDmode
)
5158 tmp_mode
= GET_MODE (op1
);
5160 tmp_mode
= compare_mode
;
5161 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5162 if (tmp
!= NULL_RTX
)
5164 rtx pat
= PATTERN (other_insn
);
5165 undobuf
.other_insn
= other_insn
;
5166 SUBST (*cc_use
, tmp
);
5168 /* Attempt to simplify CC user. */
5169 if (GET_CODE (pat
) == SET
)
5171 rtx
new = simplify_rtx (SET_SRC (pat
));
5172 if (new != NULL_RTX
)
5173 SUBST (SET_SRC (pat
), new);
5176 /* Convert X into a no-op move. */
5177 SUBST (SET_DEST (x
), pc_rtx
);
5178 SUBST (SET_SRC (x
), pc_rtx
);
5182 /* Simplify our comparison, if possible. */
5183 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5185 #ifdef EXTRA_CC_MODES
5186 /* If this machine has CC modes other than CCmode, check to see if we
5187 need to use a different CC mode here. */
5188 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5189 #endif /* EXTRA_CC_MODES */
5191 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5192 /* If the mode changed, we have to change SET_DEST, the mode in the
5193 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5194 a hard register, just build new versions with the proper mode. If it
5195 is a pseudo, we lose unless it is only time we set the pseudo, in
5196 which case we can safely change its mode. */
5197 if (compare_mode
!= GET_MODE (dest
))
5199 unsigned int regno
= REGNO (dest
);
5200 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5202 if (regno
< FIRST_PSEUDO_REGISTER
5203 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5205 if (regno
>= FIRST_PSEUDO_REGISTER
)
5206 SUBST (regno_reg_rtx
[regno
], new_dest
);
5208 SUBST (SET_DEST (x
), new_dest
);
5209 SUBST (XEXP (*cc_use
, 0), new_dest
);
5217 /* If the code changed, we have to build a new comparison in
5218 undobuf.other_insn. */
5219 if (new_code
!= old_code
)
5221 unsigned HOST_WIDE_INT mask
;
5223 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5226 /* If the only change we made was to change an EQ into an NE or
5227 vice versa, OP0 has only one bit that might be nonzero, and OP1
5228 is zero, check if changing the user of the condition code will
5229 produce a valid insn. If it won't, we can keep the original code
5230 in that insn by surrounding our operation with an XOR. */
5232 if (((old_code
== NE
&& new_code
== EQ
)
5233 || (old_code
== EQ
&& new_code
== NE
))
5234 && ! other_changed
&& op1
== const0_rtx
5235 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5236 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5238 rtx pat
= PATTERN (other_insn
), note
= 0;
5240 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5241 && ! check_asm_operands (pat
)))
5243 PUT_CODE (*cc_use
, old_code
);
5246 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5254 undobuf
.other_insn
= other_insn
;
5257 /* If we are now comparing against zero, change our source if
5258 needed. If we do not use cc0, we always have a COMPARE. */
5259 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5261 SUBST (SET_SRC (x
), op0
);
5267 /* Otherwise, if we didn't previously have a COMPARE in the
5268 correct mode, we need one. */
5269 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5271 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5276 /* Otherwise, update the COMPARE if needed. */
5277 SUBST (XEXP (src
, 0), op0
);
5278 SUBST (XEXP (src
, 1), op1
);
5283 /* Get SET_SRC in a form where we have placed back any
5284 compound expressions. Then do the checks below. */
5285 src
= make_compound_operation (src
, SET
);
5286 SUBST (SET_SRC (x
), src
);
5289 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5290 and X being a REG or (subreg (reg)), we may be able to convert this to
5291 (set (subreg:m2 x) (op)).
5293 We can always do this if M1 is narrower than M2 because that means that
5294 we only care about the low bits of the result.
5296 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5297 perform a narrower operation than requested since the high-order bits will
5298 be undefined. On machine where it is defined, this transformation is safe
5299 as long as M1 and M2 have the same number of words. */
5301 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5302 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5303 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5305 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5306 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5307 #ifndef WORD_REGISTER_OPERATIONS
5308 && (GET_MODE_SIZE (GET_MODE (src
))
5309 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5311 #ifdef CANNOT_CHANGE_MODE_CLASS
5312 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5313 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5314 GET_MODE (SUBREG_REG (src
)),
5317 && (GET_CODE (dest
) == REG
5318 || (GET_CODE (dest
) == SUBREG
5319 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5321 SUBST (SET_DEST (x
),
5322 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5324 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5326 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5330 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5333 && GET_CODE (src
) == SUBREG
5334 && subreg_lowpart_p (src
)
5335 && (GET_MODE_BITSIZE (GET_MODE (src
))
5336 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5338 rtx inner
= SUBREG_REG (src
);
5339 enum machine_mode inner_mode
= GET_MODE (inner
);
5341 /* Here we make sure that we don't have a sign bit on. */
5342 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5343 && (nonzero_bits (inner
, inner_mode
)
5344 < ((unsigned HOST_WIDE_INT
) 1
5345 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5347 SUBST (SET_SRC (x
), inner
);
5353 #ifdef LOAD_EXTEND_OP
5354 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5355 would require a paradoxical subreg. Replace the subreg with a
5356 zero_extend to avoid the reload that would otherwise be required. */
5358 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5359 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5360 && SUBREG_BYTE (src
) == 0
5361 && (GET_MODE_SIZE (GET_MODE (src
))
5362 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5363 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5366 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5367 GET_MODE (src
), SUBREG_REG (src
)));
5373 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5374 are comparing an item known to be 0 or -1 against 0, use a logical
5375 operation instead. Check for one of the arms being an IOR of the other
5376 arm with some value. We compute three terms to be IOR'ed together. In
5377 practice, at most two will be nonzero. Then we do the IOR's. */
5379 if (GET_CODE (dest
) != PC
5380 && GET_CODE (src
) == IF_THEN_ELSE
5381 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5382 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5383 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5384 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5385 #ifdef HAVE_conditional_move
5386 && ! can_conditionally_move_p (GET_MODE (src
))
5388 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5389 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5390 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5391 && ! side_effects_p (src
))
5393 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5394 ? XEXP (src
, 1) : XEXP (src
, 2));
5395 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5396 ? XEXP (src
, 2) : XEXP (src
, 1));
5397 rtx term1
= const0_rtx
, term2
, term3
;
5399 if (GET_CODE (true_rtx
) == IOR
5400 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5401 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5402 else if (GET_CODE (true_rtx
) == IOR
5403 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5404 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5405 else if (GET_CODE (false_rtx
) == IOR
5406 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5407 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5408 else if (GET_CODE (false_rtx
) == IOR
5409 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5410 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5412 term2
= gen_binary (AND
, GET_MODE (src
),
5413 XEXP (XEXP (src
, 0), 0), true_rtx
);
5414 term3
= gen_binary (AND
, GET_MODE (src
),
5415 simplify_gen_unary (NOT
, GET_MODE (src
),
5416 XEXP (XEXP (src
, 0), 0),
5421 gen_binary (IOR
, GET_MODE (src
),
5422 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5428 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5429 whole thing fail. */
5430 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5432 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5435 /* Convert this into a field assignment operation, if possible. */
5436 return make_field_assignment (x
);
5439 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5440 result. LAST is nonzero if this is the last retry. */
5443 simplify_logical (x
, last
)
5447 enum machine_mode mode
= GET_MODE (x
);
5448 rtx op0
= XEXP (x
, 0);
5449 rtx op1
= XEXP (x
, 1);
5452 switch (GET_CODE (x
))
5455 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5456 insn (and may simplify more). */
5457 if (GET_CODE (op0
) == XOR
5458 && rtx_equal_p (XEXP (op0
, 0), op1
)
5459 && ! side_effects_p (op1
))
5460 x
= gen_binary (AND
, mode
,
5461 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5464 if (GET_CODE (op0
) == XOR
5465 && rtx_equal_p (XEXP (op0
, 1), op1
)
5466 && ! side_effects_p (op1
))
5467 x
= gen_binary (AND
, mode
,
5468 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5471 /* Similarly for (~(A ^ B)) & A. */
5472 if (GET_CODE (op0
) == NOT
5473 && GET_CODE (XEXP (op0
, 0)) == XOR
5474 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5475 && ! side_effects_p (op1
))
5476 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5478 if (GET_CODE (op0
) == NOT
5479 && GET_CODE (XEXP (op0
, 0)) == XOR
5480 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5481 && ! side_effects_p (op1
))
5482 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5484 /* We can call simplify_and_const_int only if we don't lose
5485 any (sign) bits when converting INTVAL (op1) to
5486 "unsigned HOST_WIDE_INT". */
5487 if (GET_CODE (op1
) == CONST_INT
5488 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5489 || INTVAL (op1
) > 0))
5491 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5493 /* If we have (ior (and (X C1) C2)) and the next restart would be
5494 the last, simplify this by making C1 as small as possible
5497 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5498 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5499 && GET_CODE (op1
) == CONST_INT
)
5500 return gen_binary (IOR
, mode
,
5501 gen_binary (AND
, mode
, XEXP (op0
, 0),
5502 GEN_INT (INTVAL (XEXP (op0
, 1))
5503 & ~INTVAL (op1
))), op1
);
5505 if (GET_CODE (x
) != AND
)
5508 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5509 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5510 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5513 /* Convert (A | B) & A to A. */
5514 if (GET_CODE (op0
) == IOR
5515 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5516 || rtx_equal_p (XEXP (op0
, 1), op1
))
5517 && ! side_effects_p (XEXP (op0
, 0))
5518 && ! side_effects_p (XEXP (op0
, 1)))
5521 /* In the following group of tests (and those in case IOR below),
5522 we start with some combination of logical operations and apply
5523 the distributive law followed by the inverse distributive law.
5524 Most of the time, this results in no change. However, if some of
5525 the operands are the same or inverses of each other, simplifications
5528 For example, (and (ior A B) (not B)) can occur as the result of
5529 expanding a bit field assignment. When we apply the distributive
5530 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5531 which then simplifies to (and (A (not B))).
5533 If we have (and (ior A B) C), apply the distributive law and then
5534 the inverse distributive law to see if things simplify. */
5536 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5538 x
= apply_distributive_law
5539 (gen_binary (GET_CODE (op0
), mode
,
5540 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5541 gen_binary (AND
, mode
, XEXP (op0
, 1),
5543 if (GET_CODE (x
) != AND
)
5547 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5548 return apply_distributive_law
5549 (gen_binary (GET_CODE (op1
), mode
,
5550 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5551 gen_binary (AND
, mode
, XEXP (op1
, 1),
5554 /* Similarly, taking advantage of the fact that
5555 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5557 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5558 return apply_distributive_law
5559 (gen_binary (XOR
, mode
,
5560 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5561 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5564 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5565 return apply_distributive_law
5566 (gen_binary (XOR
, mode
,
5567 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5568 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5572 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5573 if (GET_CODE (op1
) == CONST_INT
5574 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5575 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5578 /* Convert (A & B) | A to A. */
5579 if (GET_CODE (op0
) == AND
5580 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5581 || rtx_equal_p (XEXP (op0
, 1), op1
))
5582 && ! side_effects_p (XEXP (op0
, 0))
5583 && ! side_effects_p (XEXP (op0
, 1)))
5586 /* If we have (ior (and A B) C), apply the distributive law and then
5587 the inverse distributive law to see if things simplify. */
5589 if (GET_CODE (op0
) == AND
)
5591 x
= apply_distributive_law
5592 (gen_binary (AND
, mode
,
5593 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5594 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5597 if (GET_CODE (x
) != IOR
)
5601 if (GET_CODE (op1
) == AND
)
5603 x
= apply_distributive_law
5604 (gen_binary (AND
, mode
,
5605 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5606 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5609 if (GET_CODE (x
) != IOR
)
5613 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5614 mode size to (rotate A CX). */
5616 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5617 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5618 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5619 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5620 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5621 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5622 == GET_MODE_BITSIZE (mode
)))
5623 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5624 (GET_CODE (op0
) == ASHIFT
5625 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5627 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5628 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5629 does not affect any of the bits in OP1, it can really be done
5630 as a PLUS and we can associate. We do this by seeing if OP1
5631 can be safely shifted left C bits. */
5632 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5633 && GET_CODE (XEXP (op0
, 0)) == PLUS
5634 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5635 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5636 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5638 int count
= INTVAL (XEXP (op0
, 1));
5639 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5641 if (mask
>> count
== INTVAL (op1
)
5642 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5644 SUBST (XEXP (XEXP (op0
, 0), 1),
5645 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5652 /* If we are XORing two things that have no bits in common,
5653 convert them into an IOR. This helps to detect rotation encoded
5654 using those methods and possibly other simplifications. */
5656 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5657 && (nonzero_bits (op0
, mode
)
5658 & nonzero_bits (op1
, mode
)) == 0)
5659 return (gen_binary (IOR
, mode
, op0
, op1
));
5661 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5662 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5665 int num_negated
= 0;
5667 if (GET_CODE (op0
) == NOT
)
5668 num_negated
++, op0
= XEXP (op0
, 0);
5669 if (GET_CODE (op1
) == NOT
)
5670 num_negated
++, op1
= XEXP (op1
, 0);
5672 if (num_negated
== 2)
5674 SUBST (XEXP (x
, 0), op0
);
5675 SUBST (XEXP (x
, 1), op1
);
5677 else if (num_negated
== 1)
5679 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5683 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5684 correspond to a machine insn or result in further simplifications
5685 if B is a constant. */
5687 if (GET_CODE (op0
) == AND
5688 && rtx_equal_p (XEXP (op0
, 1), op1
)
5689 && ! side_effects_p (op1
))
5690 return gen_binary (AND
, mode
,
5691 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5694 else if (GET_CODE (op0
) == AND
5695 && rtx_equal_p (XEXP (op0
, 0), op1
)
5696 && ! side_effects_p (op1
))
5697 return gen_binary (AND
, mode
,
5698 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5701 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5702 comparison if STORE_FLAG_VALUE is 1. */
5703 if (STORE_FLAG_VALUE
== 1
5704 && op1
== const1_rtx
5705 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5706 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5710 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5711 is (lt foo (const_int 0)), so we can perform the above
5712 simplification if STORE_FLAG_VALUE is 1. */
5714 if (STORE_FLAG_VALUE
== 1
5715 && op1
== const1_rtx
5716 && GET_CODE (op0
) == LSHIFTRT
5717 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5718 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5719 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5721 /* (xor (comparison foo bar) (const_int sign-bit))
5722 when STORE_FLAG_VALUE is the sign bit. */
5723 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5724 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5725 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5726 && op1
== const_true_rtx
5727 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5728 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5741 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5742 operations" because they can be replaced with two more basic operations.
5743 ZERO_EXTEND is also considered "compound" because it can be replaced with
5744 an AND operation, which is simpler, though only one operation.
5746 The function expand_compound_operation is called with an rtx expression
5747 and will convert it to the appropriate shifts and AND operations,
5748 simplifying at each stage.
5750 The function make_compound_operation is called to convert an expression
5751 consisting of shifts and ANDs into the equivalent compound expression.
5752 It is the inverse of this function, loosely speaking. */
5755 expand_compound_operation (x
)
5758 unsigned HOST_WIDE_INT pos
= 0, len
;
5760 unsigned int modewidth
;
5763 switch (GET_CODE (x
))
5768 /* We can't necessarily use a const_int for a multiword mode;
5769 it depends on implicitly extending the value.
5770 Since we don't know the right way to extend it,
5771 we can't tell whether the implicit way is right.
5773 Even for a mode that is no wider than a const_int,
5774 we can't win, because we need to sign extend one of its bits through
5775 the rest of it, and we don't know which bit. */
5776 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5779 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5780 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5781 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5782 reloaded. If not for that, MEM's would very rarely be safe.
5784 Reject MODEs bigger than a word, because we might not be able
5785 to reference a two-register group starting with an arbitrary register
5786 (and currently gen_lowpart might crash for a SUBREG). */
5788 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5791 /* Reject MODEs that aren't scalar integers because turning vector
5792 or complex modes into shifts causes problems. */
5794 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5797 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5798 /* If the inner object has VOIDmode (the only way this can happen
5799 is if it is an ASM_OPERANDS), we can't do anything since we don't
5800 know how much masking to do. */
5809 /* If the operand is a CLOBBER, just return it. */
5810 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5813 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5814 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5815 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5818 /* Reject MODEs that aren't scalar integers because turning vector
5819 or complex modes into shifts causes problems. */
5821 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5824 len
= INTVAL (XEXP (x
, 1));
5825 pos
= INTVAL (XEXP (x
, 2));
5827 /* If this goes outside the object being extracted, replace the object
5828 with a (use (mem ...)) construct that only combine understands
5829 and is used only for this purpose. */
5830 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5831 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5833 if (BITS_BIG_ENDIAN
)
5834 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5841 /* Convert sign extension to zero extension, if we know that the high
5842 bit is not set, as this is easier to optimize. It will be converted
5843 back to cheaper alternative in make_extraction. */
5844 if (GET_CODE (x
) == SIGN_EXTEND
5845 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5846 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5847 & ~(((unsigned HOST_WIDE_INT
)
5848 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5852 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5853 return expand_compound_operation (temp
);
5856 /* We can optimize some special cases of ZERO_EXTEND. */
5857 if (GET_CODE (x
) == ZERO_EXTEND
)
5859 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5860 know that the last value didn't have any inappropriate bits
5862 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5863 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5864 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5865 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5866 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5867 return XEXP (XEXP (x
, 0), 0);
5869 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5870 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5871 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5872 && subreg_lowpart_p (XEXP (x
, 0))
5873 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5874 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5875 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5876 return SUBREG_REG (XEXP (x
, 0));
5878 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5879 is a comparison and STORE_FLAG_VALUE permits. This is like
5880 the first case, but it works even when GET_MODE (x) is larger
5881 than HOST_WIDE_INT. */
5882 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5883 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5884 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5885 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5886 <= HOST_BITS_PER_WIDE_INT
)
5887 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5888 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5889 return XEXP (XEXP (x
, 0), 0);
5891 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5892 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5893 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5894 && subreg_lowpart_p (XEXP (x
, 0))
5895 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5896 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5897 <= HOST_BITS_PER_WIDE_INT
)
5898 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5899 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5900 return SUBREG_REG (XEXP (x
, 0));
5904 /* If we reach here, we want to return a pair of shifts. The inner
5905 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5906 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5907 logical depending on the value of UNSIGNEDP.
5909 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5910 converted into an AND of a shift.
5912 We must check for the case where the left shift would have a negative
5913 count. This can happen in a case like (x >> 31) & 255 on machines
5914 that can't shift by a constant. On those machines, we would first
5915 combine the shift with the AND to produce a variable-position
5916 extraction. Then the constant of 31 would be substituted in to produce
5917 a such a position. */
5919 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5920 if (modewidth
+ len
>= pos
)
5921 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5923 simplify_shift_const (NULL_RTX
, ASHIFT
,
5926 modewidth
- pos
- len
),
5929 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5930 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5931 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5934 ((HOST_WIDE_INT
) 1 << len
) - 1);
5936 /* Any other cases we can't handle. */
5939 /* If we couldn't do this for some reason, return the original
5941 if (GET_CODE (tem
) == CLOBBER
)
5947 /* X is a SET which contains an assignment of one object into
5948 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5949 or certain SUBREGS). If possible, convert it into a series of
5952 We half-heartedly support variable positions, but do not at all
5953 support variable lengths. */
5956 expand_field_assignment (x
)
5960 rtx pos
; /* Always counts from low bit. */
5963 enum machine_mode compute_mode
;
5965 /* Loop until we find something we can't simplify. */
5968 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5969 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5971 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5972 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5973 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5975 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5976 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5978 inner
= XEXP (SET_DEST (x
), 0);
5979 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5980 pos
= XEXP (SET_DEST (x
), 2);
5982 /* If the position is constant and spans the width of INNER,
5983 surround INNER with a USE to indicate this. */
5984 if (GET_CODE (pos
) == CONST_INT
5985 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5986 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5988 if (BITS_BIG_ENDIAN
)
5990 if (GET_CODE (pos
) == CONST_INT
)
5991 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5993 else if (GET_CODE (pos
) == MINUS
5994 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5995 && (INTVAL (XEXP (pos
, 1))
5996 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5997 /* If position is ADJUST - X, new position is X. */
5998 pos
= XEXP (pos
, 0);
6000 pos
= gen_binary (MINUS
, GET_MODE (pos
),
6001 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
6007 /* A SUBREG between two modes that occupy the same numbers of words
6008 can be done by moving the SUBREG to the source. */
6009 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6010 /* We need SUBREGs to compute nonzero_bits properly. */
6011 && nonzero_sign_valid
6012 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6013 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6014 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6015 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6017 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6018 gen_lowpart_for_combine
6019 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6026 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6027 inner
= SUBREG_REG (inner
);
6029 compute_mode
= GET_MODE (inner
);
6031 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6032 if (! SCALAR_INT_MODE_P (compute_mode
))
6034 enum machine_mode imode
;
6036 /* Don't do anything for vector or complex integral types. */
6037 if (! FLOAT_MODE_P (compute_mode
))
6040 /* Try to find an integral mode to pun with. */
6041 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6042 if (imode
== BLKmode
)
6045 compute_mode
= imode
;
6046 inner
= gen_lowpart_for_combine (imode
, inner
);
6049 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6050 if (len
< HOST_BITS_PER_WIDE_INT
)
6051 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6055 /* Now compute the equivalent expression. Make a copy of INNER
6056 for the SET_DEST in case it is a MEM into which we will substitute;
6057 we don't want shared RTL in that case. */
6059 (VOIDmode
, copy_rtx (inner
),
6060 gen_binary (IOR
, compute_mode
,
6061 gen_binary (AND
, compute_mode
,
6062 simplify_gen_unary (NOT
, compute_mode
,
6068 gen_binary (ASHIFT
, compute_mode
,
6069 gen_binary (AND
, compute_mode
,
6070 gen_lowpart_for_combine
6071 (compute_mode
, SET_SRC (x
)),
6079 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6080 it is an RTX that represents a variable starting position; otherwise,
6081 POS is the (constant) starting bit position (counted from the LSB).
6083 INNER may be a USE. This will occur when we started with a bitfield
6084 that went outside the boundary of the object in memory, which is
6085 allowed on most machines. To isolate this case, we produce a USE
6086 whose mode is wide enough and surround the MEM with it. The only
6087 code that understands the USE is this routine. If it is not removed,
6088 it will cause the resulting insn not to match.
6090 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6093 IN_DEST is nonzero if this is a reference in the destination of a
6094 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6095 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6098 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6099 ZERO_EXTRACT should be built even for bits starting at bit 0.
6101 MODE is the desired mode of the result (if IN_DEST == 0).
6103 The result is an RTX for the extraction or NULL_RTX if the target
6107 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
6108 unsignedp
, in_dest
, in_compare
)
6109 enum machine_mode mode
;
6113 unsigned HOST_WIDE_INT len
;
6115 int in_dest
, in_compare
;
6117 /* This mode describes the size of the storage area
6118 to fetch the overall value from. Within that, we
6119 ignore the POS lowest bits, etc. */
6120 enum machine_mode is_mode
= GET_MODE (inner
);
6121 enum machine_mode inner_mode
;
6122 enum machine_mode wanted_inner_mode
= byte_mode
;
6123 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6124 enum machine_mode pos_mode
= word_mode
;
6125 enum machine_mode extraction_mode
= word_mode
;
6126 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6129 rtx orig_pos_rtx
= pos_rtx
;
6130 HOST_WIDE_INT orig_pos
;
6132 /* Get some information about INNER and get the innermost object. */
6133 if (GET_CODE (inner
) == USE
)
6134 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6135 /* We don't need to adjust the position because we set up the USE
6136 to pretend that it was a full-word object. */
6137 spans_byte
= 1, inner
= XEXP (inner
, 0);
6138 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6140 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6141 consider just the QI as the memory to extract from.
6142 The subreg adds or removes high bits; its mode is
6143 irrelevant to the meaning of this extraction,
6144 since POS and LEN count from the lsb. */
6145 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
6146 is_mode
= GET_MODE (SUBREG_REG (inner
));
6147 inner
= SUBREG_REG (inner
);
6149 else if (GET_CODE (inner
) == ASHIFT
6150 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6151 && pos_rtx
== 0 && pos
== 0
6152 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6154 /* We're extracting the least significant bits of an rtx
6155 (ashift X (const_int C)), where LEN > C. Extract the
6156 least significant (LEN - C) bits of X, giving an rtx
6157 whose mode is MODE, then shift it left C times. */
6158 new = make_extraction (mode
, XEXP (inner
, 0),
6159 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6160 unsignedp
, in_dest
, in_compare
);
6162 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6165 inner_mode
= GET_MODE (inner
);
6167 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6168 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6170 /* See if this can be done without an extraction. We never can if the
6171 width of the field is not the same as that of some integer mode. For
6172 registers, we can only avoid the extraction if the position is at the
6173 low-order bit and this is either not in the destination or we have the
6174 appropriate STRICT_LOW_PART operation available.
6176 For MEM, we can avoid an extract if the field starts on an appropriate
6177 boundary and we can change the mode of the memory reference. However,
6178 we cannot directly access the MEM if we have a USE and the underlying
6179 MEM is not TMODE. This combination means that MEM was being used in a
6180 context where bits outside its mode were being referenced; that is only
6181 valid in bit-field insns. */
6183 if (tmode
!= BLKmode
6184 && ! (spans_byte
&& inner_mode
!= tmode
)
6185 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6186 && GET_CODE (inner
) != MEM
6188 || (GET_CODE (inner
) == REG
6189 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6190 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6192 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6193 : BITS_PER_UNIT
)) == 0
6194 /* We can't do this if we are widening INNER_MODE (it
6195 may not be aligned, for one thing). */
6196 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6197 && (inner_mode
== tmode
6198 || (! mode_dependent_address_p (XEXP (inner
, 0))
6199 && ! MEM_VOLATILE_P (inner
))))))
6201 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6202 field. If the original and current mode are the same, we need not
6203 adjust the offset. Otherwise, we do if bytes big endian.
6205 If INNER is not a MEM, get a piece consisting of just the field
6206 of interest (in this case POS % BITS_PER_WORD must be 0). */
6208 if (GET_CODE (inner
) == MEM
)
6210 HOST_WIDE_INT offset
;
6212 /* POS counts from lsb, but make OFFSET count in memory order. */
6213 if (BYTES_BIG_ENDIAN
)
6214 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6216 offset
= pos
/ BITS_PER_UNIT
;
6218 new = adjust_address_nv (inner
, tmode
, offset
);
6220 else if (GET_CODE (inner
) == REG
)
6222 /* We can't call gen_lowpart_for_combine here since we always want
6223 a SUBREG and it would sometimes return a new hard register. */
6224 if (tmode
!= inner_mode
)
6226 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6228 if (WORDS_BIG_ENDIAN
6229 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6230 final_word
= ((GET_MODE_SIZE (inner_mode
)
6231 - GET_MODE_SIZE (tmode
))
6232 / UNITS_PER_WORD
) - final_word
;
6234 final_word
*= UNITS_PER_WORD
;
6235 if (BYTES_BIG_ENDIAN
&&
6236 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6237 final_word
+= (GET_MODE_SIZE (inner_mode
)
6238 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6240 /* Avoid creating invalid subregs, for example when
6241 simplifying (x>>32)&255. */
6242 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6245 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6251 new = force_to_mode (inner
, tmode
,
6252 len
>= HOST_BITS_PER_WIDE_INT
6253 ? ~(unsigned HOST_WIDE_INT
) 0
6254 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6257 /* If this extraction is going into the destination of a SET,
6258 make a STRICT_LOW_PART unless we made a MEM. */
6261 return (GET_CODE (new) == MEM
? new
6262 : (GET_CODE (new) != SUBREG
6263 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6264 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6269 if (GET_CODE (new) == CONST_INT
)
6270 return gen_int_mode (INTVAL (new), mode
);
6272 /* If we know that no extraneous bits are set, and that the high
6273 bit is not set, convert the extraction to the cheaper of
6274 sign and zero extension, that are equivalent in these cases. */
6275 if (flag_expensive_optimizations
6276 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6277 && ((nonzero_bits (new, tmode
)
6278 & ~(((unsigned HOST_WIDE_INT
)
6279 GET_MODE_MASK (tmode
))
6283 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6284 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6286 /* Prefer ZERO_EXTENSION, since it gives more information to
6288 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6293 /* Otherwise, sign- or zero-extend unless we already are in the
6296 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6300 /* Unless this is a COMPARE or we have a funny memory reference,
6301 don't do anything with zero-extending field extracts starting at
6302 the low-order bit since they are simple AND operations. */
6303 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6304 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6307 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6308 we would be spanning bytes or if the position is not a constant and the
6309 length is not 1. In all other cases, we would only be going outside
6310 our object in cases when an original shift would have been
6312 if (! spans_byte
&& GET_CODE (inner
) == MEM
6313 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6314 || (pos_rtx
!= 0 && len
!= 1)))
6317 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6318 and the mode for the result. */
6319 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6321 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6322 pos_mode
= mode_for_extraction (EP_insv
, 2);
6323 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6326 if (! in_dest
&& unsignedp
6327 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6329 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6330 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6331 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6334 if (! in_dest
&& ! unsignedp
6335 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6337 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6338 pos_mode
= mode_for_extraction (EP_extv
, 3);
6339 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6342 /* Never narrow an object, since that might not be safe. */
6344 if (mode
!= VOIDmode
6345 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6346 extraction_mode
= mode
;
6348 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6349 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6350 pos_mode
= GET_MODE (pos_rtx
);
6352 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6353 if we have to change the mode of memory and cannot, the desired mode is
6355 if (GET_CODE (inner
) != MEM
)
6356 wanted_inner_mode
= wanted_inner_reg_mode
;
6357 else if (inner_mode
!= wanted_inner_mode
6358 && (mode_dependent_address_p (XEXP (inner
, 0))
6359 || MEM_VOLATILE_P (inner
)))
6360 wanted_inner_mode
= extraction_mode
;
6364 if (BITS_BIG_ENDIAN
)
6366 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6367 BITS_BIG_ENDIAN style. If position is constant, compute new
6368 position. Otherwise, build subtraction.
6369 Note that POS is relative to the mode of the original argument.
6370 If it's a MEM we need to recompute POS relative to that.
6371 However, if we're extracting from (or inserting into) a register,
6372 we want to recompute POS relative to wanted_inner_mode. */
6373 int width
= (GET_CODE (inner
) == MEM
6374 ? GET_MODE_BITSIZE (is_mode
)
6375 : GET_MODE_BITSIZE (wanted_inner_mode
));
6378 pos
= width
- len
- pos
;
6381 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6382 /* POS may be less than 0 now, but we check for that below.
6383 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6386 /* If INNER has a wider mode, make it smaller. If this is a constant
6387 extract, try to adjust the byte to point to the byte containing
6389 if (wanted_inner_mode
!= VOIDmode
6390 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6391 && ((GET_CODE (inner
) == MEM
6392 && (inner_mode
== wanted_inner_mode
6393 || (! mode_dependent_address_p (XEXP (inner
, 0))
6394 && ! MEM_VOLATILE_P (inner
))))))
6398 /* The computations below will be correct if the machine is big
6399 endian in both bits and bytes or little endian in bits and bytes.
6400 If it is mixed, we must adjust. */
6402 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6403 adjust OFFSET to compensate. */
6404 if (BYTES_BIG_ENDIAN
6406 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6407 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6409 /* If this is a constant position, we can move to the desired byte. */
6412 offset
+= pos
/ BITS_PER_UNIT
;
6413 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6416 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6418 && is_mode
!= wanted_inner_mode
)
6419 offset
= (GET_MODE_SIZE (is_mode
)
6420 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6422 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6423 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6426 /* If INNER is not memory, we can always get it into the proper mode. If we
6427 are changing its mode, POS must be a constant and smaller than the size
6429 else if (GET_CODE (inner
) != MEM
)
6431 if (GET_MODE (inner
) != wanted_inner_mode
6433 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6436 inner
= force_to_mode (inner
, wanted_inner_mode
,
6438 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6439 ? ~(unsigned HOST_WIDE_INT
) 0
6440 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6445 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6446 have to zero extend. Otherwise, we can just use a SUBREG. */
6448 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6450 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6452 /* If we know that no extraneous bits are set, and that the high
6453 bit is not set, convert extraction to cheaper one - either
6454 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6456 if (flag_expensive_optimizations
6457 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6458 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6459 & ~(((unsigned HOST_WIDE_INT
)
6460 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6464 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6466 /* Prefer ZERO_EXTENSION, since it gives more information to
6468 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6473 else if (pos_rtx
!= 0
6474 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6475 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6477 /* Make POS_RTX unless we already have it and it is correct. If we don't
6478 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6480 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6481 pos_rtx
= orig_pos_rtx
;
6483 else if (pos_rtx
== 0)
6484 pos_rtx
= GEN_INT (pos
);
6486 /* Make the required operation. See if we can use existing rtx. */
6487 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6488 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6490 new = gen_lowpart_for_combine (mode
, new);
6495 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6496 with any other operations in X. Return X without that shift if so. */
6499 extract_left_shift (x
, count
)
6503 enum rtx_code code
= GET_CODE (x
);
6504 enum machine_mode mode
= GET_MODE (x
);
6510 /* This is the shift itself. If it is wide enough, we will return
6511 either the value being shifted if the shift count is equal to
6512 COUNT or a shift for the difference. */
6513 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6514 && INTVAL (XEXP (x
, 1)) >= count
)
6515 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6516 INTVAL (XEXP (x
, 1)) - count
);
6520 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6521 return simplify_gen_unary (code
, mode
, tem
, mode
);
6525 case PLUS
: case IOR
: case XOR
: case AND
:
6526 /* If we can safely shift this constant and we find the inner shift,
6527 make a new operation. */
6528 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6529 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6530 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6531 return gen_binary (code
, mode
, tem
,
6532 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6543 /* Look at the expression rooted at X. Look for expressions
6544 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6545 Form these expressions.
6547 Return the new rtx, usually just X.
6549 Also, for machines like the VAX that don't have logical shift insns,
6550 try to convert logical to arithmetic shift operations in cases where
6551 they are equivalent. This undoes the canonicalizations to logical
6552 shifts done elsewhere.
6554 We try, as much as possible, to re-use rtl expressions to save memory.
6556 IN_CODE says what kind of expression we are processing. Normally, it is
6557 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6558 being kludges), it is MEM. When processing the arguments of a comparison
6559 or a COMPARE against zero, it is COMPARE. */
6562 make_compound_operation (x
, in_code
)
6564 enum rtx_code in_code
;
6566 enum rtx_code code
= GET_CODE (x
);
6567 enum machine_mode mode
= GET_MODE (x
);
6568 int mode_width
= GET_MODE_BITSIZE (mode
);
6570 enum rtx_code next_code
;
6576 /* Select the code to be used in recursive calls. Once we are inside an
6577 address, we stay there. If we have a comparison, set to COMPARE,
6578 but once inside, go back to our default of SET. */
6580 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6581 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6582 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6583 : in_code
== COMPARE
? SET
: in_code
);
6585 /* Process depending on the code of this operation. If NEW is set
6586 nonzero, it will be returned. */
6591 /* Convert shifts by constants into multiplications if inside
6593 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6594 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6595 && INTVAL (XEXP (x
, 1)) >= 0)
6597 new = make_compound_operation (XEXP (x
, 0), next_code
);
6598 new = gen_rtx_MULT (mode
, new,
6599 GEN_INT ((HOST_WIDE_INT
) 1
6600 << INTVAL (XEXP (x
, 1))));
6605 /* If the second operand is not a constant, we can't do anything
6607 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6610 /* If the constant is a power of two minus one and the first operand
6611 is a logical right shift, make an extraction. */
6612 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6613 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6615 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6616 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6617 0, in_code
== COMPARE
);
6620 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6621 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6622 && subreg_lowpart_p (XEXP (x
, 0))
6623 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6624 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6626 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6628 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6629 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6630 0, in_code
== COMPARE
);
6632 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6633 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6634 || GET_CODE (XEXP (x
, 0)) == IOR
)
6635 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6636 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6637 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6639 /* Apply the distributive law, and then try to make extractions. */
6640 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6641 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6643 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6645 new = make_compound_operation (new, in_code
);
6648 /* If we are have (and (rotate X C) M) and C is larger than the number
6649 of bits in M, this is an extraction. */
6651 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6652 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6653 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6654 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6656 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6657 new = make_extraction (mode
, new,
6658 (GET_MODE_BITSIZE (mode
)
6659 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6660 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6663 /* On machines without logical shifts, if the operand of the AND is
6664 a logical shift and our mask turns off all the propagated sign
6665 bits, we can replace the logical shift with an arithmetic shift. */
6666 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6667 && !have_insn_for (LSHIFTRT
, mode
)
6668 && have_insn_for (ASHIFTRT
, mode
)
6669 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6670 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6671 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6672 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6674 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6676 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6677 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6679 gen_rtx_ASHIFTRT (mode
,
6680 make_compound_operation
6681 (XEXP (XEXP (x
, 0), 0), next_code
),
6682 XEXP (XEXP (x
, 0), 1)));
6685 /* If the constant is one less than a power of two, this might be
6686 representable by an extraction even if no shift is present.
6687 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6688 we are in a COMPARE. */
6689 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6690 new = make_extraction (mode
,
6691 make_compound_operation (XEXP (x
, 0),
6693 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6695 /* If we are in a comparison and this is an AND with a power of two,
6696 convert this into the appropriate bit extract. */
6697 else if (in_code
== COMPARE
6698 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6699 new = make_extraction (mode
,
6700 make_compound_operation (XEXP (x
, 0),
6702 i
, NULL_RTX
, 1, 1, 0, 1);
6707 /* If the sign bit is known to be zero, replace this with an
6708 arithmetic shift. */
6709 if (have_insn_for (ASHIFTRT
, mode
)
6710 && ! have_insn_for (LSHIFTRT
, mode
)
6711 && mode_width
<= HOST_BITS_PER_WIDE_INT
6712 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6714 new = gen_rtx_ASHIFTRT (mode
,
6715 make_compound_operation (XEXP (x
, 0),
6721 /* ... fall through ... */
6727 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6728 this is a SIGN_EXTRACT. */
6729 if (GET_CODE (rhs
) == CONST_INT
6730 && GET_CODE (lhs
) == ASHIFT
6731 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6732 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6734 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6735 new = make_extraction (mode
, new,
6736 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6737 NULL_RTX
, mode_width
- INTVAL (rhs
),
6738 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6742 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6743 If so, try to merge the shifts into a SIGN_EXTEND. We could
6744 also do this for some cases of SIGN_EXTRACT, but it doesn't
6745 seem worth the effort; the case checked for occurs on Alpha. */
6747 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6748 && ! (GET_CODE (lhs
) == SUBREG
6749 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6750 && GET_CODE (rhs
) == CONST_INT
6751 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6752 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6753 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6754 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6755 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6760 /* Call ourselves recursively on the inner expression. If we are
6761 narrowing the object and it has a different RTL code from
6762 what it originally did, do this SUBREG as a force_to_mode. */
6764 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6765 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6766 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6767 && subreg_lowpart_p (x
))
6769 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6772 /* If we have something other than a SUBREG, we might have
6773 done an expansion, so rerun ourselves. */
6774 if (GET_CODE (newer
) != SUBREG
)
6775 newer
= make_compound_operation (newer
, in_code
);
6780 /* If this is a paradoxical subreg, and the new code is a sign or
6781 zero extension, omit the subreg and widen the extension. If it
6782 is a regular subreg, we can still get rid of the subreg by not
6783 widening so much, or in fact removing the extension entirely. */
6784 if ((GET_CODE (tem
) == SIGN_EXTEND
6785 || GET_CODE (tem
) == ZERO_EXTEND
)
6786 && subreg_lowpart_p (x
))
6788 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6789 || (GET_MODE_SIZE (mode
) >
6790 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6792 if (! SCALAR_INT_MODE_P (mode
))
6794 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6797 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6808 x
= gen_lowpart_for_combine (mode
, new);
6809 code
= GET_CODE (x
);
6812 /* Now recursively process each operand of this operation. */
6813 fmt
= GET_RTX_FORMAT (code
);
6814 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6817 new = make_compound_operation (XEXP (x
, i
), next_code
);
6818 SUBST (XEXP (x
, i
), new);
6824 /* Given M see if it is a value that would select a field of bits
6825 within an item, but not the entire word. Return -1 if not.
6826 Otherwise, return the starting position of the field, where 0 is the
6829 *PLEN is set to the length of the field. */
6832 get_pos_from_mask (m
, plen
)
6833 unsigned HOST_WIDE_INT m
;
6834 unsigned HOST_WIDE_INT
*plen
;
6836 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6837 int pos
= exact_log2 (m
& -m
);
6843 /* Now shift off the low-order zero bits and see if we have a power of
6845 len
= exact_log2 ((m
>> pos
) + 1);
6854 /* See if X can be simplified knowing that we will only refer to it in
6855 MODE and will only refer to those bits that are nonzero in MASK.
6856 If other bits are being computed or if masking operations are done
6857 that select a superset of the bits in MASK, they can sometimes be
6860 Return a possibly simplified expression, but always convert X to
6861 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6863 Also, if REG is nonzero and X is a register equal in value to REG,
6866 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6867 are all off in X. This is used when X will be complemented, by either
6868 NOT, NEG, or XOR. */
6871 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6873 enum machine_mode mode
;
6874 unsigned HOST_WIDE_INT mask
;
6878 enum rtx_code code
= GET_CODE (x
);
6879 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6880 enum machine_mode op_mode
;
6881 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6884 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6885 code below will do the wrong thing since the mode of such an
6886 expression is VOIDmode.
6888 Also do nothing if X is a CLOBBER; this can happen if X was
6889 the return value from a call to gen_lowpart_for_combine. */
6890 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6893 /* We want to perform the operation is its present mode unless we know
6894 that the operation is valid in MODE, in which case we do the operation
6896 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6897 && have_insn_for (code
, mode
))
6898 ? mode
: GET_MODE (x
));
6900 /* It is not valid to do a right-shift in a narrower mode
6901 than the one it came in with. */
6902 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6903 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6904 op_mode
= GET_MODE (x
);
6906 /* Truncate MASK to fit OP_MODE. */
6908 mask
&= GET_MODE_MASK (op_mode
);
6910 /* When we have an arithmetic operation, or a shift whose count we
6911 do not know, we need to assume that all bit the up to the highest-order
6912 bit in MASK will be needed. This is how we form such a mask. */
6914 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6915 ? GET_MODE_MASK (op_mode
)
6916 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6919 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6921 /* Determine what bits of X are guaranteed to be (non)zero. */
6922 nonzero
= nonzero_bits (x
, mode
);
6924 /* If none of the bits in X are needed, return a zero. */
6925 if (! just_select
&& (nonzero
& mask
) == 0)
6928 /* If X is a CONST_INT, return a new one. Do this here since the
6929 test below will fail. */
6930 if (GET_CODE (x
) == CONST_INT
)
6932 if (SCALAR_INT_MODE_P (mode
))
6933 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6936 x
= GEN_INT (INTVAL (x
) & mask
);
6937 return gen_lowpart_common (mode
, x
);
6941 /* If X is narrower than MODE and we want all the bits in X's mode, just
6942 get X in the proper mode. */
6943 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6944 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6945 return gen_lowpart_for_combine (mode
, x
);
6947 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6948 MASK are already known to be zero in X, we need not do anything. */
6949 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6955 /* If X is a (clobber (const_int)), return it since we know we are
6956 generating something that won't match. */
6960 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6961 spanned the boundary of the MEM. If we are now masking so it is
6962 within that boundary, we don't need the USE any more. */
6963 if (! BITS_BIG_ENDIAN
6964 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6965 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6972 x
= expand_compound_operation (x
);
6973 if (GET_CODE (x
) != code
)
6974 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6978 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6979 || rtx_equal_p (reg
, get_last_value (x
))))
6984 if (subreg_lowpart_p (x
)
6985 /* We can ignore the effect of this SUBREG if it narrows the mode or
6986 if the constant masks to zero all the bits the mode doesn't
6988 && ((GET_MODE_SIZE (GET_MODE (x
))
6989 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6991 & GET_MODE_MASK (GET_MODE (x
))
6992 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6993 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6997 /* If this is an AND with a constant, convert it into an AND
6998 whose constant is the AND of that constant with MASK. If it
6999 remains an AND of MASK, delete it since it is redundant. */
7001 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7003 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
7004 mask
& INTVAL (XEXP (x
, 1)));
7006 /* If X is still an AND, see if it is an AND with a mask that
7007 is just some low-order bits. If so, and it is MASK, we don't
7010 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7011 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
7015 /* If it remains an AND, try making another AND with the bits
7016 in the mode mask that aren't in MASK turned on. If the
7017 constant in the AND is wide enough, this might make a
7018 cheaper constant. */
7020 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7021 && GET_MODE_MASK (GET_MODE (x
)) != mask
7022 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
7024 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
7025 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
7026 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
7029 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
7030 number, sign extend it. */
7031 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
7032 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7033 cval
|= (HOST_WIDE_INT
) -1 << width
;
7035 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
7036 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
7046 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7047 low-order bits (as in an alignment operation) and FOO is already
7048 aligned to that boundary, mask C1 to that boundary as well.
7049 This may eliminate that PLUS and, later, the AND. */
7052 unsigned int width
= GET_MODE_BITSIZE (mode
);
7053 unsigned HOST_WIDE_INT smask
= mask
;
7055 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7056 number, sign extend it. */
7058 if (width
< HOST_BITS_PER_WIDE_INT
7059 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7060 smask
|= (HOST_WIDE_INT
) -1 << width
;
7062 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7063 && exact_log2 (- smask
) >= 0
7064 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7065 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7066 return force_to_mode (plus_constant (XEXP (x
, 0),
7067 (INTVAL (XEXP (x
, 1)) & smask
)),
7068 mode
, smask
, reg
, next_select
);
7071 /* ... fall through ... */
7074 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7075 most significant bit in MASK since carries from those bits will
7076 affect the bits we are interested in. */
7081 /* If X is (minus C Y) where C's least set bit is larger than any bit
7082 in the mask, then we may replace with (neg Y). */
7083 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7084 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7085 & -INTVAL (XEXP (x
, 0))))
7088 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7090 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7093 /* Similarly, if C contains every bit in the fuller_mask, then we may
7094 replace with (not Y). */
7095 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7096 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7097 == INTVAL (XEXP (x
, 0))))
7099 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7100 XEXP (x
, 1), GET_MODE (x
));
7101 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7109 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7110 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7111 operation which may be a bitfield extraction. Ensure that the
7112 constant we form is not wider than the mode of X. */
7114 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7115 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7116 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7117 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7118 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7119 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7120 + floor_log2 (INTVAL (XEXP (x
, 1))))
7121 < GET_MODE_BITSIZE (GET_MODE (x
)))
7122 && (INTVAL (XEXP (x
, 1))
7123 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7125 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7126 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7127 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
7128 XEXP (XEXP (x
, 0), 0), temp
);
7129 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7130 XEXP (XEXP (x
, 0), 1));
7131 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7135 /* For most binary operations, just propagate into the operation and
7136 change the mode if we have an operation of that mode. */
7138 op0
= gen_lowpart_for_combine (op_mode
,
7139 force_to_mode (XEXP (x
, 0), mode
, mask
,
7141 op1
= gen_lowpart_for_combine (op_mode
,
7142 force_to_mode (XEXP (x
, 1), mode
, mask
,
7145 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7146 x
= gen_binary (code
, op_mode
, op0
, op1
);
7150 /* For left shifts, do the same, but just for the first operand.
7151 However, we cannot do anything with shifts where we cannot
7152 guarantee that the counts are smaller than the size of the mode
7153 because such a count will have a different meaning in a
7156 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7157 && INTVAL (XEXP (x
, 1)) >= 0
7158 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7159 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7160 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7161 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7164 /* If the shift count is a constant and we can do arithmetic in
7165 the mode of the shift, refine which bits we need. Otherwise, use the
7166 conservative form of the mask. */
7167 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7168 && INTVAL (XEXP (x
, 1)) >= 0
7169 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7170 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7171 mask
>>= INTVAL (XEXP (x
, 1));
7175 op0
= gen_lowpart_for_combine (op_mode
,
7176 force_to_mode (XEXP (x
, 0), op_mode
,
7177 mask
, reg
, next_select
));
7179 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7180 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7184 /* Here we can only do something if the shift count is a constant,
7185 this shift constant is valid for the host, and we can do arithmetic
7188 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7189 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7190 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7192 rtx inner
= XEXP (x
, 0);
7193 unsigned HOST_WIDE_INT inner_mask
;
7195 /* Select the mask of the bits we need for the shift operand. */
7196 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7198 /* We can only change the mode of the shift if we can do arithmetic
7199 in the mode of the shift and INNER_MASK is no wider than the
7200 width of OP_MODE. */
7201 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7202 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7203 op_mode
= GET_MODE (x
);
7205 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7207 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7208 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7211 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7212 shift and AND produces only copies of the sign bit (C2 is one less
7213 than a power of two), we can do this with just a shift. */
7215 if (GET_CODE (x
) == LSHIFTRT
7216 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7217 /* The shift puts one of the sign bit copies in the least significant
7219 && ((INTVAL (XEXP (x
, 1))
7220 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7221 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7222 && exact_log2 (mask
+ 1) >= 0
7223 /* Number of bits left after the shift must be more than the mask
7225 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7226 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7227 /* Must be more sign bit copies than the mask needs. */
7228 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7229 >= exact_log2 (mask
+ 1)))
7230 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7231 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7232 - exact_log2 (mask
+ 1)));
7237 /* If we are just looking for the sign bit, we don't need this shift at
7238 all, even if it has a variable count. */
7239 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7240 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7241 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7242 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7244 /* If this is a shift by a constant, get a mask that contains those bits
7245 that are not copies of the sign bit. We then have two cases: If
7246 MASK only includes those bits, this can be a logical shift, which may
7247 allow simplifications. If MASK is a single-bit field not within
7248 those bits, we are requesting a copy of the sign bit and hence can
7249 shift the sign bit to the appropriate location. */
7251 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7252 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7256 /* If the considered data is wider than HOST_WIDE_INT, we can't
7257 represent a mask for all its bits in a single scalar.
7258 But we only care about the lower bits, so calculate these. */
7260 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7262 nonzero
= ~(HOST_WIDE_INT
) 0;
7264 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7265 is the number of bits a full-width mask would have set.
7266 We need only shift if these are fewer than nonzero can
7267 hold. If not, we must keep all bits set in nonzero. */
7269 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7270 < HOST_BITS_PER_WIDE_INT
)
7271 nonzero
>>= INTVAL (XEXP (x
, 1))
7272 + HOST_BITS_PER_WIDE_INT
7273 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7277 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7278 nonzero
>>= INTVAL (XEXP (x
, 1));
7281 if ((mask
& ~nonzero
) == 0
7282 || (i
= exact_log2 (mask
)) >= 0)
7284 x
= simplify_shift_const
7285 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7286 i
< 0 ? INTVAL (XEXP (x
, 1))
7287 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7289 if (GET_CODE (x
) != ASHIFTRT
)
7290 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7294 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7295 even if the shift count isn't a constant. */
7297 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7301 /* If this is a zero- or sign-extension operation that just affects bits
7302 we don't care about, remove it. Be sure the call above returned
7303 something that is still a shift. */
7305 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7306 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7307 && INTVAL (XEXP (x
, 1)) >= 0
7308 && (INTVAL (XEXP (x
, 1))
7309 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7310 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7311 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7312 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7313 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7320 /* If the shift count is constant and we can do computations
7321 in the mode of X, compute where the bits we care about are.
7322 Otherwise, we can't do anything. Don't change the mode of
7323 the shift or propagate MODE into the shift, though. */
7324 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7325 && INTVAL (XEXP (x
, 1)) >= 0)
7327 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7328 GET_MODE (x
), GEN_INT (mask
),
7330 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7332 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7333 INTVAL (temp
), reg
, next_select
));
7338 /* If we just want the low-order bit, the NEG isn't needed since it
7339 won't change the low-order bit. */
7341 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7343 /* We need any bits less significant than the most significant bit in
7344 MASK since carries from those bits will affect the bits we are
7350 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7351 same as the XOR case above. Ensure that the constant we form is not
7352 wider than the mode of X. */
7354 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7355 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7356 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7357 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7358 < GET_MODE_BITSIZE (GET_MODE (x
)))
7359 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7361 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7363 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7364 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7366 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7369 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7370 use the full mask inside the NOT. */
7374 op0
= gen_lowpart_for_combine (op_mode
,
7375 force_to_mode (XEXP (x
, 0), mode
, mask
,
7377 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7378 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7382 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7383 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7384 which is equal to STORE_FLAG_VALUE. */
7385 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7386 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7387 && (nonzero_bits (XEXP (x
, 0), mode
)
7388 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7389 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7394 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7395 written in a narrower mode. We play it safe and do not do so. */
7398 gen_lowpart_for_combine (GET_MODE (x
),
7399 force_to_mode (XEXP (x
, 1), mode
,
7400 mask
, reg
, next_select
)));
7402 gen_lowpart_for_combine (GET_MODE (x
),
7403 force_to_mode (XEXP (x
, 2), mode
,
7404 mask
, reg
, next_select
)));
7411 /* Ensure we return a value of the proper mode. */
7412 return gen_lowpart_for_combine (mode
, x
);
7415 /* Return nonzero if X is an expression that has one of two values depending on
7416 whether some other value is zero or nonzero. In that case, we return the
7417 value that is being tested, *PTRUE is set to the value if the rtx being
7418 returned has a nonzero value, and *PFALSE is set to the other alternative.
7420 If we return zero, we set *PTRUE and *PFALSE to X. */
7423 if_then_else_cond (x
, ptrue
, pfalse
)
7425 rtx
*ptrue
, *pfalse
;
7427 enum machine_mode mode
= GET_MODE (x
);
7428 enum rtx_code code
= GET_CODE (x
);
7429 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7430 unsigned HOST_WIDE_INT nz
;
7432 /* If we are comparing a value against zero, we are done. */
7433 if ((code
== NE
|| code
== EQ
)
7434 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7436 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7437 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7441 /* If this is a unary operation whose operand has one of two values, apply
7442 our opcode to compute those values. */
7443 else if (GET_RTX_CLASS (code
) == '1'
7444 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7446 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7447 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7448 GET_MODE (XEXP (x
, 0)));
7452 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7453 make can't possibly match and would suppress other optimizations. */
7454 else if (code
== COMPARE
)
7457 /* If this is a binary operation, see if either side has only one of two
7458 values. If either one does or if both do and they are conditional on
7459 the same value, compute the new true and false values. */
7460 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7461 || GET_RTX_CLASS (code
) == '<')
7463 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7464 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7466 if ((cond0
!= 0 || cond1
!= 0)
7467 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7469 /* If if_then_else_cond returned zero, then true/false are the
7470 same rtl. We must copy one of them to prevent invalid rtl
7473 true0
= copy_rtx (true0
);
7474 else if (cond1
== 0)
7475 true1
= copy_rtx (true1
);
7477 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7478 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7479 return cond0
? cond0
: cond1
;
7482 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7483 operands is zero when the other is nonzero, and vice-versa,
7484 and STORE_FLAG_VALUE is 1 or -1. */
7486 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7487 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7489 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7491 rtx op0
= XEXP (XEXP (x
, 0), 1);
7492 rtx op1
= XEXP (XEXP (x
, 1), 1);
7494 cond0
= XEXP (XEXP (x
, 0), 0);
7495 cond1
= XEXP (XEXP (x
, 1), 0);
7497 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7498 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7499 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7500 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7501 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7502 || ((swap_condition (GET_CODE (cond0
))
7503 == combine_reversed_comparison_code (cond1
))
7504 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7505 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7506 && ! side_effects_p (x
))
7508 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7509 *pfalse
= gen_binary (MULT
, mode
,
7511 ? simplify_gen_unary (NEG
, mode
, op1
,
7519 /* Similarly for MULT, AND and UMIN, except that for these the result
7521 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7522 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7523 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7525 cond0
= XEXP (XEXP (x
, 0), 0);
7526 cond1
= XEXP (XEXP (x
, 1), 0);
7528 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7529 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7530 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7531 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7532 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7533 || ((swap_condition (GET_CODE (cond0
))
7534 == combine_reversed_comparison_code (cond1
))
7535 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7536 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7537 && ! side_effects_p (x
))
7539 *ptrue
= *pfalse
= const0_rtx
;
7545 else if (code
== IF_THEN_ELSE
)
7547 /* If we have IF_THEN_ELSE already, extract the condition and
7548 canonicalize it if it is NE or EQ. */
7549 cond0
= XEXP (x
, 0);
7550 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7551 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7552 return XEXP (cond0
, 0);
7553 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7555 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7556 return XEXP (cond0
, 0);
7562 /* If X is a SUBREG, we can narrow both the true and false values
7563 if the inner expression, if there is a condition. */
7564 else if (code
== SUBREG
7565 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7568 *ptrue
= simplify_gen_subreg (mode
, true0
,
7569 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7570 *pfalse
= simplify_gen_subreg (mode
, false0
,
7571 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7576 /* If X is a constant, this isn't special and will cause confusions
7577 if we treat it as such. Likewise if it is equivalent to a constant. */
7578 else if (CONSTANT_P (x
)
7579 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7582 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7583 will be least confusing to the rest of the compiler. */
7584 else if (mode
== BImode
)
7586 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7590 /* If X is known to be either 0 or -1, those are the true and
7591 false values when testing X. */
7592 else if (x
== constm1_rtx
|| x
== const0_rtx
7593 || (mode
!= VOIDmode
7594 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7596 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7600 /* Likewise for 0 or a single bit. */
7601 else if (mode
!= VOIDmode
7602 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7603 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7605 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7609 /* Otherwise fail; show no condition with true and false values the same. */
7610 *ptrue
= *pfalse
= x
;
7614 /* Return the value of expression X given the fact that condition COND
7615 is known to be true when applied to REG as its first operand and VAL
7616 as its second. X is known to not be shared and so can be modified in
7619 We only handle the simplest cases, and specifically those cases that
7620 arise with IF_THEN_ELSE expressions. */
7623 known_cond (x
, cond
, reg
, val
)
7628 enum rtx_code code
= GET_CODE (x
);
7633 if (side_effects_p (x
))
7636 /* If either operand of the condition is a floating point value,
7637 then we have to avoid collapsing an EQ comparison. */
7639 && rtx_equal_p (x
, reg
)
7640 && ! FLOAT_MODE_P (GET_MODE (x
))
7641 && ! FLOAT_MODE_P (GET_MODE (val
)))
7644 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7647 /* If X is (abs REG) and we know something about REG's relationship
7648 with zero, we may be able to simplify this. */
7650 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7653 case GE
: case GT
: case EQ
:
7656 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7658 GET_MODE (XEXP (x
, 0)));
7663 /* The only other cases we handle are MIN, MAX, and comparisons if the
7664 operands are the same as REG and VAL. */
7666 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7668 if (rtx_equal_p (XEXP (x
, 0), val
))
7669 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7671 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7673 if (GET_RTX_CLASS (code
) == '<')
7675 if (comparison_dominates_p (cond
, code
))
7676 return const_true_rtx
;
7678 code
= combine_reversed_comparison_code (x
);
7680 && comparison_dominates_p (cond
, code
))
7685 else if (code
== SMAX
|| code
== SMIN
7686 || code
== UMIN
|| code
== UMAX
)
7688 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7690 /* Do not reverse the condition when it is NE or EQ.
7691 This is because we cannot conclude anything about
7692 the value of 'SMAX (x, y)' when x is not equal to y,
7693 but we can when x equals y. */
7694 if ((code
== SMAX
|| code
== UMAX
)
7695 && ! (cond
== EQ
|| cond
== NE
))
7696 cond
= reverse_condition (cond
);
7701 return unsignedp
? x
: XEXP (x
, 1);
7703 return unsignedp
? x
: XEXP (x
, 0);
7705 return unsignedp
? XEXP (x
, 1) : x
;
7707 return unsignedp
? XEXP (x
, 0) : x
;
7714 else if (code
== SUBREG
)
7716 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7717 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7719 if (SUBREG_REG (x
) != r
)
7721 /* We must simplify subreg here, before we lose track of the
7722 original inner_mode. */
7723 new = simplify_subreg (GET_MODE (x
), r
,
7724 inner_mode
, SUBREG_BYTE (x
));
7728 SUBST (SUBREG_REG (x
), r
);
7733 /* We don't have to handle SIGN_EXTEND here, because even in the
7734 case of replacing something with a modeless CONST_INT, a
7735 CONST_INT is already (supposed to be) a valid sign extension for
7736 its narrower mode, which implies it's already properly
7737 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7738 story is different. */
7739 else if (code
== ZERO_EXTEND
)
7741 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7742 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7744 if (XEXP (x
, 0) != r
)
7746 /* We must simplify the zero_extend here, before we lose
7747 track of the original inner_mode. */
7748 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7753 SUBST (XEXP (x
, 0), r
);
7759 fmt
= GET_RTX_FORMAT (code
);
7760 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7763 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7764 else if (fmt
[i
] == 'E')
7765 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7766 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7773 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7774 assignment as a field assignment. */
7777 rtx_equal_for_field_assignment_p (x
, y
)
7781 if (x
== y
|| rtx_equal_p (x
, y
))
7784 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7787 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7788 Note that all SUBREGs of MEM are paradoxical; otherwise they
7789 would have been rewritten. */
7790 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7791 && GET_CODE (SUBREG_REG (y
)) == MEM
7792 && rtx_equal_p (SUBREG_REG (y
),
7793 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7796 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7797 && GET_CODE (SUBREG_REG (x
)) == MEM
7798 && rtx_equal_p (SUBREG_REG (x
),
7799 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7802 /* We used to see if get_last_value of X and Y were the same but that's
7803 not correct. In one direction, we'll cause the assignment to have
7804 the wrong destination and in the case, we'll import a register into this
7805 insn that might have already have been dead. So fail if none of the
7806 above cases are true. */
7810 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7811 Return that assignment if so.
7813 We only handle the most common cases. */
7816 make_field_assignment (x
)
7819 rtx dest
= SET_DEST (x
);
7820 rtx src
= SET_SRC (x
);
7825 unsigned HOST_WIDE_INT len
;
7827 enum machine_mode mode
;
7829 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7830 a clear of a one-bit field. We will have changed it to
7831 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7834 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7835 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7836 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7837 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7839 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7842 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7846 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7847 && subreg_lowpart_p (XEXP (src
, 0))
7848 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7849 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7850 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7851 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7852 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7854 assign
= make_extraction (VOIDmode
, dest
, 0,
7855 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7858 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7862 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7864 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7865 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7866 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7868 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7871 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7875 /* The other case we handle is assignments into a constant-position
7876 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7877 a mask that has all one bits except for a group of zero bits and
7878 OTHER is known to have zeros where C1 has ones, this is such an
7879 assignment. Compute the position and length from C1. Shift OTHER
7880 to the appropriate position, force it to the required mode, and
7881 make the extraction. Check for the AND in both operands. */
7883 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7886 rhs
= expand_compound_operation (XEXP (src
, 0));
7887 lhs
= expand_compound_operation (XEXP (src
, 1));
7889 if (GET_CODE (rhs
) == AND
7890 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7891 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7892 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7893 else if (GET_CODE (lhs
) == AND
7894 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7895 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7896 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7900 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7901 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7902 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7903 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7906 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7910 /* The mode to use for the source is the mode of the assignment, or of
7911 what is inside a possible STRICT_LOW_PART. */
7912 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7913 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7915 /* Shift OTHER right POS places and make it the source, restricting it
7916 to the proper length and mode. */
7918 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7919 GET_MODE (src
), other
, pos
),
7921 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7922 ? ~(unsigned HOST_WIDE_INT
) 0
7923 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7926 return gen_rtx_SET (VOIDmode
, assign
, src
);
7929 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7933 apply_distributive_law (x
)
7936 enum rtx_code code
= GET_CODE (x
);
7937 rtx lhs
, rhs
, other
;
7939 enum rtx_code inner_code
;
7941 /* Distributivity is not true for floating point.
7942 It can change the value. So don't do it.
7943 -- rms and moshier@world.std.com. */
7944 if (FLOAT_MODE_P (GET_MODE (x
)))
7947 /* The outer operation can only be one of the following: */
7948 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7949 && code
!= PLUS
&& code
!= MINUS
)
7952 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7954 /* If either operand is a primitive we can't do anything, so get out
7956 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7957 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7960 lhs
= expand_compound_operation (lhs
);
7961 rhs
= expand_compound_operation (rhs
);
7962 inner_code
= GET_CODE (lhs
);
7963 if (inner_code
!= GET_CODE (rhs
))
7966 /* See if the inner and outer operations distribute. */
7973 /* These all distribute except over PLUS. */
7974 if (code
== PLUS
|| code
== MINUS
)
7979 if (code
!= PLUS
&& code
!= MINUS
)
7984 /* This is also a multiply, so it distributes over everything. */
7988 /* Non-paradoxical SUBREGs distributes over all operations, provided
7989 the inner modes and byte offsets are the same, this is an extraction
7990 of a low-order part, we don't convert an fp operation to int or
7991 vice versa, and we would not be converting a single-word
7992 operation into a multi-word operation. The latter test is not
7993 required, but it prevents generating unneeded multi-word operations.
7994 Some of the previous tests are redundant given the latter test, but
7995 are retained because they are required for correctness.
7997 We produce the result slightly differently in this case. */
7999 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
8000 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
8001 || ! subreg_lowpart_p (lhs
)
8002 || (GET_MODE_CLASS (GET_MODE (lhs
))
8003 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
8004 || (GET_MODE_SIZE (GET_MODE (lhs
))
8005 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
8006 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
8009 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
8010 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
8011 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
8017 /* Set LHS and RHS to the inner operands (A and B in the example
8018 above) and set OTHER to the common operand (C in the example).
8019 These is only one way to do this unless the inner operation is
8021 if (GET_RTX_CLASS (inner_code
) == 'c'
8022 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8023 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8024 else if (GET_RTX_CLASS (inner_code
) == 'c'
8025 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8026 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8027 else if (GET_RTX_CLASS (inner_code
) == 'c'
8028 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8029 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8030 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8031 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8035 /* Form the new inner operation, seeing if it simplifies first. */
8036 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8038 /* There is one exception to the general way of distributing:
8039 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
8040 if (code
== XOR
&& inner_code
== IOR
)
8043 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8046 /* We may be able to continuing distributing the result, so call
8047 ourselves recursively on the inner operation before forming the
8048 outer operation, which we return. */
8049 return gen_binary (inner_code
, GET_MODE (x
),
8050 apply_distributive_law (tem
), other
);
8053 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8056 Return an equivalent form, if different from X. Otherwise, return X. If
8057 X is zero, we are to always construct the equivalent form. */
8060 simplify_and_const_int (x
, mode
, varop
, constop
)
8062 enum machine_mode mode
;
8064 unsigned HOST_WIDE_INT constop
;
8066 unsigned HOST_WIDE_INT nonzero
;
8069 /* Simplify VAROP knowing that we will be only looking at some of the
8072 Note by passing in CONSTOP, we guarantee that the bits not set in
8073 CONSTOP are not significant and will never be examined. We must
8074 ensure that is the case by explicitly masking out those bits
8075 before returning. */
8076 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
8078 /* If VAROP is a CLOBBER, we will fail so return it. */
8079 if (GET_CODE (varop
) == CLOBBER
)
8082 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8083 to VAROP and return the new constant. */
8084 if (GET_CODE (varop
) == CONST_INT
)
8085 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
8087 /* See what bits may be nonzero in VAROP. Unlike the general case of
8088 a call to nonzero_bits, here we don't care about bits outside
8091 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8093 /* Turn off all bits in the constant that are known to already be zero.
8094 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8095 which is tested below. */
8099 /* If we don't have any bits left, return zero. */
8103 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8104 a power of two, we can replace this with an ASHIFT. */
8105 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8106 && (i
= exact_log2 (constop
)) >= 0)
8107 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8109 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8110 or XOR, then try to apply the distributive law. This may eliminate
8111 operations if either branch can be simplified because of the AND.
8112 It may also make some cases more complex, but those cases probably
8113 won't match a pattern either with or without this. */
8115 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8117 gen_lowpart_for_combine
8119 apply_distributive_law
8120 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8121 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8122 XEXP (varop
, 0), constop
),
8123 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8124 XEXP (varop
, 1), constop
))));
8126 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8127 the AND and see if one of the operands simplifies to zero. If so, we
8128 may eliminate it. */
8130 if (GET_CODE (varop
) == PLUS
8131 && exact_log2 (constop
+ 1) >= 0)
8135 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8136 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8137 if (o0
== const0_rtx
)
8139 if (o1
== const0_rtx
)
8143 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8144 if we already had one (just check for the simplest cases). */
8145 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8146 && GET_MODE (XEXP (x
, 0)) == mode
8147 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8148 varop
= XEXP (x
, 0);
8150 varop
= gen_lowpart_for_combine (mode
, varop
);
8152 /* If we can't make the SUBREG, try to return what we were given. */
8153 if (GET_CODE (varop
) == CLOBBER
)
8154 return x
? x
: varop
;
8156 /* If we are only masking insignificant bits, return VAROP. */
8157 if (constop
== nonzero
)
8161 /* Otherwise, return an AND. */
8162 constop
= trunc_int_for_mode (constop
, mode
);
8163 /* See how much, if any, of X we can use. */
8164 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8165 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8169 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8170 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8171 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8173 SUBST (XEXP (x
, 0), varop
);
8180 #define nonzero_bits_with_known(X, MODE) \
8181 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8183 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8184 It avoids exponential behavior in nonzero_bits1 when X has
8185 identical subexpressions on the first or the second level. */
8187 static unsigned HOST_WIDE_INT
8188 cached_nonzero_bits (x
, mode
, known_x
, known_mode
, known_ret
)
8190 enum machine_mode mode
;
8192 enum machine_mode known_mode
;
8193 unsigned HOST_WIDE_INT known_ret
;
8195 if (x
== known_x
&& mode
== known_mode
)
8198 /* Try to find identical subexpressions. If found call
8199 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8200 precomputed value for the subexpression as KNOWN_RET. */
8202 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8203 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8205 rtx x0
= XEXP (x
, 0);
8206 rtx x1
= XEXP (x
, 1);
8208 /* Check the first level. */
8210 return nonzero_bits1 (x
, mode
, x0
, mode
,
8211 nonzero_bits_with_known (x0
, mode
));
8213 /* Check the second level. */
8214 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8215 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8216 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8217 return nonzero_bits1 (x
, mode
, x1
, mode
,
8218 nonzero_bits_with_known (x1
, mode
));
8220 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8221 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8222 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8223 return nonzero_bits1 (x
, mode
, x0
, mode
,
8224 nonzero_bits_with_known (x0
, mode
));
8227 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8230 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8231 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8232 is less useful. We can't allow both, because that results in exponential
8233 run time recursion. There is a nullstone testcase that triggered
8234 this. This macro avoids accidental uses of num_sign_bit_copies. */
8235 #define cached_num_sign_bit_copies()
8237 /* Given an expression, X, compute which bits in X can be nonzero.
8238 We don't care about bits outside of those defined in MODE.
8240 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8241 a shift, AND, or zero_extract, we can do better. */
8243 static unsigned HOST_WIDE_INT
8244 nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
)
8246 enum machine_mode mode
;
8248 enum machine_mode known_mode
;
8249 unsigned HOST_WIDE_INT known_ret
;
8251 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8252 unsigned HOST_WIDE_INT inner_nz
;
8254 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8257 /* For floating-point values, assume all bits are needed. */
8258 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8261 /* If X is wider than MODE, use its mode instead. */
8262 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8264 mode
= GET_MODE (x
);
8265 nonzero
= GET_MODE_MASK (mode
);
8266 mode_width
= GET_MODE_BITSIZE (mode
);
8269 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8270 /* Our only callers in this case look for single bit values. So
8271 just return the mode mask. Those tests will then be false. */
8274 #ifndef WORD_REGISTER_OPERATIONS
8275 /* If MODE is wider than X, but both are a single word for both the host
8276 and target machines, we can compute this from which bits of the
8277 object might be nonzero in its own mode, taking into account the fact
8278 that on many CISC machines, accessing an object in a wider mode
8279 causes the high-order bits to become undefined. So they are
8280 not known to be zero. */
8282 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8283 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8284 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8285 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8287 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8288 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8293 code
= GET_CODE (x
);
8297 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8298 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8299 all the bits above ptr_mode are known to be zero. */
8300 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8302 nonzero
&= GET_MODE_MASK (ptr_mode
);
8305 /* Include declared information about alignment of pointers. */
8306 /* ??? We don't properly preserve REG_POINTER changes across
8307 pointer-to-integer casts, so we can't trust it except for
8308 things that we know must be pointers. See execute/960116-1.c. */
8309 if ((x
== stack_pointer_rtx
8310 || x
== frame_pointer_rtx
8311 || x
== arg_pointer_rtx
)
8312 && REGNO_POINTER_ALIGN (REGNO (x
)))
8314 unsigned HOST_WIDE_INT alignment
8315 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8317 #ifdef PUSH_ROUNDING
8318 /* If PUSH_ROUNDING is defined, it is possible for the
8319 stack to be momentarily aligned only to that amount,
8320 so we pick the least alignment. */
8321 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8322 alignment
= MIN (PUSH_ROUNDING (1), alignment
);
8325 nonzero
&= ~(alignment
- 1);
8328 /* If X is a register whose nonzero bits value is current, use it.
8329 Otherwise, if X is a register whose value we can find, use that
8330 value. Otherwise, use the previously-computed global nonzero bits
8331 for this register. */
8333 if (reg_last_set_value
[REGNO (x
)] != 0
8334 && (reg_last_set_mode
[REGNO (x
)] == mode
8335 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8336 && GET_MODE_CLASS (mode
) == MODE_INT
))
8337 && (reg_last_set_label
[REGNO (x
)] == label_tick
8338 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8339 && REG_N_SETS (REGNO (x
)) == 1
8340 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8342 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8343 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8345 tem
= get_last_value (x
);
8349 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8350 /* If X is narrower than MODE and TEM is a non-negative
8351 constant that would appear negative in the mode of X,
8352 sign-extend it for use in reg_nonzero_bits because some
8353 machines (maybe most) will actually do the sign-extension
8354 and this is the conservative approach.
8356 ??? For 2.5, try to tighten up the MD files in this regard
8357 instead of this kludge. */
8359 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8360 && GET_CODE (tem
) == CONST_INT
8362 && 0 != (INTVAL (tem
)
8363 & ((HOST_WIDE_INT
) 1
8364 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8365 tem
= GEN_INT (INTVAL (tem
)
8366 | ((HOST_WIDE_INT
) (-1)
8367 << GET_MODE_BITSIZE (GET_MODE (x
))));
8369 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8371 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8373 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8375 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8376 /* We don't know anything about the upper bits. */
8377 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8378 return nonzero
& mask
;
8384 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8385 /* If X is negative in MODE, sign-extend the value. */
8386 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8387 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8388 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8394 #ifdef LOAD_EXTEND_OP
8395 /* In many, if not most, RISC machines, reading a byte from memory
8396 zeros the rest of the register. Noticing that fact saves a lot
8397 of extra zero-extends. */
8398 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8399 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8404 case UNEQ
: case LTGT
:
8405 case GT
: case GTU
: case UNGT
:
8406 case LT
: case LTU
: case UNLT
:
8407 case GE
: case GEU
: case UNGE
:
8408 case LE
: case LEU
: case UNLE
:
8409 case UNORDERED
: case ORDERED
:
8411 /* If this produces an integer result, we know which bits are set.
8412 Code here used to clear bits outside the mode of X, but that is
8415 if (GET_MODE_CLASS (mode
) == MODE_INT
8416 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8417 nonzero
= STORE_FLAG_VALUE
;
8422 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8423 and num_sign_bit_copies. */
8424 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8425 == GET_MODE_BITSIZE (GET_MODE (x
)))
8429 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8430 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8435 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8436 and num_sign_bit_copies. */
8437 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8438 == GET_MODE_BITSIZE (GET_MODE (x
)))
8444 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8445 & GET_MODE_MASK (mode
));
8449 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8450 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8451 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8455 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8456 Otherwise, show all the bits in the outer mode but not the inner
8458 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8459 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8461 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8463 & (((HOST_WIDE_INT
) 1
8464 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8465 inner_nz
|= (GET_MODE_MASK (mode
)
8466 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8469 nonzero
&= inner_nz
;
8473 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8474 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8478 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8480 unsigned HOST_WIDE_INT nonzero0
=
8481 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8483 /* Don't call nonzero_bits for the second time if it cannot change
8485 if ((nonzero
& nonzero0
) != nonzero
)
8486 nonzero
&= (nonzero0
8487 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8491 case PLUS
: case MINUS
:
8493 case DIV
: case UDIV
:
8494 case MOD
: case UMOD
:
8495 /* We can apply the rules of arithmetic to compute the number of
8496 high- and low-order zero bits of these operations. We start by
8497 computing the width (position of the highest-order nonzero bit)
8498 and the number of low-order zero bits for each value. */
8500 unsigned HOST_WIDE_INT nz0
=
8501 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8502 unsigned HOST_WIDE_INT nz1
=
8503 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8504 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8505 int width0
= floor_log2 (nz0
) + 1;
8506 int width1
= floor_log2 (nz1
) + 1;
8507 int low0
= floor_log2 (nz0
& -nz0
);
8508 int low1
= floor_log2 (nz1
& -nz1
);
8509 HOST_WIDE_INT op0_maybe_minusp
8510 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8511 HOST_WIDE_INT op1_maybe_minusp
8512 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8513 unsigned int result_width
= mode_width
;
8519 result_width
= MAX (width0
, width1
) + 1;
8520 result_low
= MIN (low0
, low1
);
8523 result_low
= MIN (low0
, low1
);
8526 result_width
= width0
+ width1
;
8527 result_low
= low0
+ low1
;
8532 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8533 result_width
= width0
;
8538 result_width
= width0
;
8543 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8544 result_width
= MIN (width0
, width1
);
8545 result_low
= MIN (low0
, low1
);
8550 result_width
= MIN (width0
, width1
);
8551 result_low
= MIN (low0
, low1
);
8557 if (result_width
< mode_width
)
8558 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8561 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8563 #ifdef POINTERS_EXTEND_UNSIGNED
8564 /* If pointers extend unsigned and this is an addition or subtraction
8565 to a pointer in Pmode, all the bits above ptr_mode are known to be
8567 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8568 && (code
== PLUS
|| code
== MINUS
)
8569 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8570 nonzero
&= GET_MODE_MASK (ptr_mode
);
8576 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8577 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8578 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8582 /* If this is a SUBREG formed for a promoted variable that has
8583 been zero-extended, we know that at least the high-order bits
8584 are zero, though others might be too. */
8586 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8587 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8588 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8590 /* If the inner mode is a single word for both the host and target
8591 machines, we can compute this from which bits of the inner
8592 object might be nonzero. */
8593 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8594 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8595 <= HOST_BITS_PER_WIDE_INT
))
8597 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8599 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8600 /* If this is a typical RISC machine, we only have to worry
8601 about the way loads are extended. */
8602 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8604 & (((unsigned HOST_WIDE_INT
) 1
8605 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8607 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8608 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8611 /* On many CISC machines, accessing an object in a wider mode
8612 causes the high-order bits to become undefined. So they are
8613 not known to be zero. */
8614 if (GET_MODE_SIZE (GET_MODE (x
))
8615 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8616 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8617 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8626 /* The nonzero bits are in two classes: any bits within MODE
8627 that aren't in GET_MODE (x) are always significant. The rest of the
8628 nonzero bits are those that are significant in the operand of
8629 the shift when shifted the appropriate number of bits. This
8630 shows that high-order bits are cleared by the right shift and
8631 low-order bits by left shifts. */
8632 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8633 && INTVAL (XEXP (x
, 1)) >= 0
8634 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8636 enum machine_mode inner_mode
= GET_MODE (x
);
8637 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8638 int count
= INTVAL (XEXP (x
, 1));
8639 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8640 unsigned HOST_WIDE_INT op_nonzero
=
8641 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8642 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8643 unsigned HOST_WIDE_INT outer
= 0;
8645 if (mode_width
> width
)
8646 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8648 if (code
== LSHIFTRT
)
8650 else if (code
== ASHIFTRT
)
8654 /* If the sign bit may have been nonzero before the shift, we
8655 need to mark all the places it could have been copied to
8656 by the shift as possibly nonzero. */
8657 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8658 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8660 else if (code
== ASHIFT
)
8663 inner
= ((inner
<< (count
% width
)
8664 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8666 nonzero
&= (outer
| inner
);
8672 /* This is at most the number of bits in the mode. */
8673 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8677 /* If CLZ has a known value at zero, then the nonzero bits are
8678 that value, plus the number of bits in the mode minus one. */
8679 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8680 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8686 /* If CTZ has a known value at zero, then the nonzero bits are
8687 that value, plus the number of bits in the mode minus one. */
8688 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8689 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8699 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8700 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8710 /* See the macro definition above. */
8711 #undef cached_num_sign_bit_copies
8713 #define num_sign_bit_copies_with_known(X, M) \
8714 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8716 /* The function cached_num_sign_bit_copies is a wrapper around
8717 num_sign_bit_copies1. It avoids exponential behavior in
8718 num_sign_bit_copies1 when X has identical subexpressions on the
8719 first or the second level. */
8722 cached_num_sign_bit_copies (x
, mode
, known_x
, known_mode
, known_ret
)
8724 enum machine_mode mode
;
8726 enum machine_mode known_mode
;
8727 unsigned int known_ret
;
8729 if (x
== known_x
&& mode
== known_mode
)
8732 /* Try to find identical subexpressions. If found call
8733 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8734 the precomputed value for the subexpression as KNOWN_RET. */
8736 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8737 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8739 rtx x0
= XEXP (x
, 0);
8740 rtx x1
= XEXP (x
, 1);
8742 /* Check the first level. */
8745 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8746 num_sign_bit_copies_with_known (x0
, mode
));
8748 /* Check the second level. */
8749 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8750 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8751 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8753 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8754 num_sign_bit_copies_with_known (x1
, mode
));
8756 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8757 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8758 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8760 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8761 num_sign_bit_copies_with_known (x0
, mode
));
8764 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8767 /* Return the number of bits at the high-order end of X that are known to
8768 be equal to the sign bit. X will be used in mode MODE; if MODE is
8769 VOIDmode, X will be used in its own mode. The returned value will always
8770 be between 1 and the number of bits in MODE. */
8773 num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
)
8775 enum machine_mode mode
;
8777 enum machine_mode known_mode
;
8778 unsigned int known_ret
;
8780 enum rtx_code code
= GET_CODE (x
);
8781 unsigned int bitwidth
;
8782 int num0
, num1
, result
;
8783 unsigned HOST_WIDE_INT nonzero
;
8786 /* If we weren't given a mode, use the mode of X. If the mode is still
8787 VOIDmode, we don't know anything. Likewise if one of the modes is
8790 if (mode
== VOIDmode
)
8791 mode
= GET_MODE (x
);
8793 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8796 bitwidth
= GET_MODE_BITSIZE (mode
);
8798 /* For a smaller object, just ignore the high bits. */
8799 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8801 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8803 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8806 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8808 #ifndef WORD_REGISTER_OPERATIONS
8809 /* If this machine does not do all register operations on the entire
8810 register and MODE is wider than the mode of X, we can say nothing
8811 at all about the high-order bits. */
8814 /* Likewise on machines that do, if the mode of the object is smaller
8815 than a word and loads of that size don't sign extend, we can say
8816 nothing about the high order bits. */
8817 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8818 #ifdef LOAD_EXTEND_OP
8819 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8830 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8831 /* If pointers extend signed and this is a pointer in Pmode, say that
8832 all the bits above ptr_mode are known to be sign bit copies. */
8833 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8835 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8838 if (reg_last_set_value
[REGNO (x
)] != 0
8839 && reg_last_set_mode
[REGNO (x
)] == mode
8840 && (reg_last_set_label
[REGNO (x
)] == label_tick
8841 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8842 && REG_N_SETS (REGNO (x
)) == 1
8843 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8845 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8846 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8848 tem
= get_last_value (x
);
8850 return num_sign_bit_copies_with_known (tem
, mode
);
8852 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8853 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8854 return reg_sign_bit_copies
[REGNO (x
)];
8858 #ifdef LOAD_EXTEND_OP
8859 /* Some RISC machines sign-extend all loads of smaller than a word. */
8860 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8861 return MAX (1, ((int) bitwidth
8862 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8867 /* If the constant is negative, take its 1's complement and remask.
8868 Then see how many zero bits we have. */
8869 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8870 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8871 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8872 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8874 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8877 /* If this is a SUBREG for a promoted object that is sign-extended
8878 and we are looking at it in a wider mode, we know that at least the
8879 high-order bits are known to be sign bit copies. */
8881 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8883 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8884 return MAX ((int) bitwidth
8885 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8889 /* For a smaller object, just ignore the high bits. */
8890 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8892 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8893 return MAX (1, (num0
8894 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8898 #ifdef WORD_REGISTER_OPERATIONS
8899 #ifdef LOAD_EXTEND_OP
8900 /* For paradoxical SUBREGs on machines where all register operations
8901 affect the entire register, just look inside. Note that we are
8902 passing MODE to the recursive call, so the number of sign bit copies
8903 will remain relative to that mode, not the inner mode. */
8905 /* This works only if loads sign extend. Otherwise, if we get a
8906 reload for the inner part, it may be loaded from the stack, and
8907 then we lose all sign bit copies that existed before the store
8910 if ((GET_MODE_SIZE (GET_MODE (x
))
8911 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8912 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8913 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8914 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8920 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8921 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8925 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8926 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8929 /* For a smaller object, just ignore the high bits. */
8930 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8931 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8935 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8937 case ROTATE
: case ROTATERT
:
8938 /* If we are rotating left by a number of bits less than the number
8939 of sign bit copies, we can just subtract that amount from the
8941 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8942 && INTVAL (XEXP (x
, 1)) >= 0
8943 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8945 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8946 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8947 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8952 /* In general, this subtracts one sign bit copy. But if the value
8953 is known to be positive, the number of sign bit copies is the
8954 same as that of the input. Finally, if the input has just one bit
8955 that might be nonzero, all the bits are copies of the sign bit. */
8956 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8957 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8958 return num0
> 1 ? num0
- 1 : 1;
8960 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8965 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8970 case IOR
: case AND
: case XOR
:
8971 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8972 /* Logical operations will preserve the number of sign-bit copies.
8973 MIN and MAX operations always return one of the operands. */
8974 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8975 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8976 return MIN (num0
, num1
);
8978 case PLUS
: case MINUS
:
8979 /* For addition and subtraction, we can have a 1-bit carry. However,
8980 if we are subtracting 1 from a positive number, there will not
8981 be such a carry. Furthermore, if the positive number is known to
8982 be 0 or 1, we know the result is either -1 or 0. */
8984 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8985 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8987 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8988 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8989 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8990 : bitwidth
- floor_log2 (nonzero
) - 1);
8993 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8994 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8995 result
= MAX (1, MIN (num0
, num1
) - 1);
8997 #ifdef POINTERS_EXTEND_UNSIGNED
8998 /* If pointers extend signed and this is an addition or subtraction
8999 to a pointer in Pmode, all the bits above ptr_mode are known to be
9001 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
9002 && (code
== PLUS
|| code
== MINUS
)
9003 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
9004 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
9005 - GET_MODE_BITSIZE (ptr_mode
) + 1),
9011 /* The number of bits of the product is the sum of the number of
9012 bits of both terms. However, unless one of the terms if known
9013 to be positive, we must allow for an additional bit since negating
9014 a negative number can remove one sign bit copy. */
9016 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
9017 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
9019 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
9021 && (bitwidth
> HOST_BITS_PER_WIDE_INT
9022 || (((nonzero_bits (XEXP (x
, 0), mode
)
9023 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
9024 && ((nonzero_bits (XEXP (x
, 1), mode
)
9025 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
9028 return MAX (1, result
);
9031 /* The result must be <= the first operand. If the first operand
9032 has the high bit set, we know nothing about the number of sign
9034 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
9036 else if ((nonzero_bits (XEXP (x
, 0), mode
)
9037 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
9040 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
9043 /* The result must be <= the second operand. */
9044 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
9047 /* Similar to unsigned division, except that we have to worry about
9048 the case where the divisor is negative, in which case we have
9050 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
9052 && (bitwidth
> HOST_BITS_PER_WIDE_INT
9053 || (nonzero_bits (XEXP (x
, 1), mode
)
9054 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
9060 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
9062 && (bitwidth
> HOST_BITS_PER_WIDE_INT
9063 || (nonzero_bits (XEXP (x
, 1), mode
)
9064 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
9070 /* Shifts by a constant add to the number of bits equal to the
9072 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
9073 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
9074 && INTVAL (XEXP (x
, 1)) > 0)
9075 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
9080 /* Left shifts destroy copies. */
9081 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
9082 || INTVAL (XEXP (x
, 1)) < 0
9083 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
9086 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
9087 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
9090 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
9091 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
9092 return MIN (num0
, num1
);
9094 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
9095 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
9096 case GEU
: case GTU
: case LEU
: case LTU
:
9097 case UNORDERED
: case ORDERED
:
9098 /* If the constant is negative, take its 1's complement and remask.
9099 Then see how many zero bits we have. */
9100 nonzero
= STORE_FLAG_VALUE
;
9101 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
9102 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
9103 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
9105 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
9112 /* If we haven't been able to figure it out by one of the above rules,
9113 see if some of the high-order bits are known to be zero. If so,
9114 count those bits and return one less than that amount. If we can't
9115 safely compute the mask for this mode, always return BITWIDTH. */
9117 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
9120 nonzero
= nonzero_bits (x
, mode
);
9121 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
9122 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
9125 /* Return the number of "extended" bits there are in X, when interpreted
9126 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9127 unsigned quantities, this is the number of high-order zero bits.
9128 For signed quantities, this is the number of copies of the sign bit
9129 minus 1. In both case, this function returns the number of "spare"
9130 bits. For example, if two quantities for which this function returns
9131 at least 1 are added, the addition is known not to overflow.
9133 This function will always return 0 unless called during combine, which
9134 implies that it must be called from a define_split. */
9137 extended_count (x
, mode
, unsignedp
)
9139 enum machine_mode mode
;
9142 if (nonzero_sign_valid
== 0)
9146 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9147 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
9148 - floor_log2 (nonzero_bits (x
, mode
)))
9150 : num_sign_bit_copies (x
, mode
) - 1);
9153 /* This function is called from `simplify_shift_const' to merge two
9154 outer operations. Specifically, we have already found that we need
9155 to perform operation *POP0 with constant *PCONST0 at the outermost
9156 position. We would now like to also perform OP1 with constant CONST1
9157 (with *POP0 being done last).
9159 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9160 the resulting operation. *PCOMP_P is set to 1 if we would need to
9161 complement the innermost operand, otherwise it is unchanged.
9163 MODE is the mode in which the operation will be done. No bits outside
9164 the width of this mode matter. It is assumed that the width of this mode
9165 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9167 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9168 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9169 result is simply *PCONST0.
9171 If the resulting operation cannot be expressed as one operation, we
9172 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9175 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
9176 enum rtx_code
*pop0
;
9177 HOST_WIDE_INT
*pconst0
;
9179 HOST_WIDE_INT const1
;
9180 enum machine_mode mode
;
9183 enum rtx_code op0
= *pop0
;
9184 HOST_WIDE_INT const0
= *pconst0
;
9186 const0
&= GET_MODE_MASK (mode
);
9187 const1
&= GET_MODE_MASK (mode
);
9189 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9193 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9196 if (op1
== NIL
|| op0
== SET
)
9199 else if (op0
== NIL
)
9200 op0
= op1
, const0
= const1
;
9202 else if (op0
== op1
)
9226 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9227 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9230 /* If the two constants aren't the same, we can't do anything. The
9231 remaining six cases can all be done. */
9232 else if (const0
!= const1
)
9240 /* (a & b) | b == b */
9242 else /* op1 == XOR */
9243 /* (a ^ b) | b == a | b */
9249 /* (a & b) ^ b == (~a) & b */
9250 op0
= AND
, *pcomp_p
= 1;
9251 else /* op1 == IOR */
9252 /* (a | b) ^ b == a & ~b */
9253 op0
= AND
, *pconst0
= ~const0
;
9258 /* (a | b) & b == b */
9260 else /* op1 == XOR */
9261 /* (a ^ b) & b) == (~a) & b */
9268 /* Check for NO-OP cases. */
9269 const0
&= GET_MODE_MASK (mode
);
9271 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9273 else if (const0
== 0 && op0
== AND
)
9275 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9279 /* ??? Slightly redundant with the above mask, but not entirely.
9280 Moving this above means we'd have to sign-extend the mode mask
9281 for the final test. */
9282 const0
= trunc_int_for_mode (const0
, mode
);
9290 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9291 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9292 that we started with.
9294 The shift is normally computed in the widest mode we find in VAROP, as
9295 long as it isn't a different number of words than RESULT_MODE. Exceptions
9296 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9299 simplify_shift_const (x
, code
, result_mode
, varop
, orig_count
)
9302 enum machine_mode result_mode
;
9306 enum rtx_code orig_code
= code
;
9309 enum machine_mode mode
= result_mode
;
9310 enum machine_mode shift_mode
, tmode
;
9311 unsigned int mode_words
9312 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9313 /* We form (outer_op (code varop count) (outer_const)). */
9314 enum rtx_code outer_op
= NIL
;
9315 HOST_WIDE_INT outer_const
= 0;
9317 int complement_p
= 0;
9320 /* Make sure and truncate the "natural" shift on the way in. We don't
9321 want to do this inside the loop as it makes it more difficult to
9323 #ifdef SHIFT_COUNT_TRUNCATED
9324 if (SHIFT_COUNT_TRUNCATED
)
9325 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9328 /* If we were given an invalid count, don't do anything except exactly
9329 what was requested. */
9331 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9336 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9341 /* Unless one of the branches of the `if' in this loop does a `continue',
9342 we will `break' the loop after the `if'. */
9346 /* If we have an operand of (clobber (const_int 0)), just return that
9348 if (GET_CODE (varop
) == CLOBBER
)
9351 /* If we discovered we had to complement VAROP, leave. Making a NOT
9352 here would cause an infinite loop. */
9356 /* Convert ROTATERT to ROTATE. */
9357 if (code
== ROTATERT
)
9359 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9361 if (VECTOR_MODE_P (result_mode
))
9362 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9364 count
= bitsize
- count
;
9367 /* We need to determine what mode we will do the shift in. If the
9368 shift is a right shift or a ROTATE, we must always do it in the mode
9369 it was originally done in. Otherwise, we can do it in MODE, the
9370 widest mode encountered. */
9372 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9373 ? result_mode
: mode
);
9375 /* Handle cases where the count is greater than the size of the mode
9376 minus 1. For ASHIFT, use the size minus one as the count (this can
9377 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9378 take the count modulo the size. For other shifts, the result is
9381 Since these shifts are being produced by the compiler by combining
9382 multiple operations, each of which are defined, we know what the
9383 result is supposed to be. */
9385 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9387 if (code
== ASHIFTRT
)
9388 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9389 else if (code
== ROTATE
|| code
== ROTATERT
)
9390 count
%= GET_MODE_BITSIZE (shift_mode
);
9393 /* We can't simply return zero because there may be an
9401 /* An arithmetic right shift of a quantity known to be -1 or 0
9403 if (code
== ASHIFTRT
9404 && (num_sign_bit_copies (varop
, shift_mode
)
9405 == GET_MODE_BITSIZE (shift_mode
)))
9411 /* If we are doing an arithmetic right shift and discarding all but
9412 the sign bit copies, this is equivalent to doing a shift by the
9413 bitsize minus one. Convert it into that shift because it will often
9414 allow other simplifications. */
9416 if (code
== ASHIFTRT
9417 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9418 >= GET_MODE_BITSIZE (shift_mode
)))
9419 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9421 /* We simplify the tests below and elsewhere by converting
9422 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9423 `make_compound_operation' will convert it to an ASHIFTRT for
9424 those machines (such as VAX) that don't have an LSHIFTRT. */
9425 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9427 && ((nonzero_bits (varop
, shift_mode
)
9428 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9432 if (code
== LSHIFTRT
9433 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9434 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9437 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9438 && !((nonzero_bits (varop
, shift_mode
) << count
)
9439 & GET_MODE_MASK (shift_mode
)))
9442 switch (GET_CODE (varop
))
9448 new = expand_compound_operation (varop
);
9457 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9458 minus the width of a smaller mode, we can do this with a
9459 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9460 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9461 && ! mode_dependent_address_p (XEXP (varop
, 0))
9462 && ! MEM_VOLATILE_P (varop
)
9463 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9464 MODE_INT
, 1)) != BLKmode
)
9466 new = adjust_address_nv (varop
, tmode
,
9467 BYTES_BIG_ENDIAN
? 0
9468 : count
/ BITS_PER_UNIT
);
9470 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9471 : ZERO_EXTEND
, mode
, new);
9478 /* Similar to the case above, except that we can only do this if
9479 the resulting mode is the same as that of the underlying
9480 MEM and adjust the address depending on the *bits* endianness
9481 because of the way that bit-field extract insns are defined. */
9482 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9483 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9484 MODE_INT
, 1)) != BLKmode
9485 && tmode
== GET_MODE (XEXP (varop
, 0)))
9487 if (BITS_BIG_ENDIAN
)
9488 new = XEXP (varop
, 0);
9491 new = copy_rtx (XEXP (varop
, 0));
9492 SUBST (XEXP (new, 0),
9493 plus_constant (XEXP (new, 0),
9494 count
/ BITS_PER_UNIT
));
9497 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9498 : ZERO_EXTEND
, mode
, new);
9505 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9506 the same number of words as what we've seen so far. Then store
9507 the widest mode in MODE. */
9508 if (subreg_lowpart_p (varop
)
9509 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9510 > GET_MODE_SIZE (GET_MODE (varop
)))
9511 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9512 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9515 varop
= SUBREG_REG (varop
);
9516 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9517 mode
= GET_MODE (varop
);
9523 /* Some machines use MULT instead of ASHIFT because MULT
9524 is cheaper. But it is still better on those machines to
9525 merge two shifts into one. */
9526 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9527 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9530 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9531 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9537 /* Similar, for when divides are cheaper. */
9538 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9539 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9542 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9543 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9549 /* If we are extracting just the sign bit of an arithmetic
9550 right shift, that shift is not needed. However, the sign
9551 bit of a wider mode may be different from what would be
9552 interpreted as the sign bit in a narrower mode, so, if
9553 the result is narrower, don't discard the shift. */
9554 if (code
== LSHIFTRT
9555 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9556 && (GET_MODE_BITSIZE (result_mode
)
9557 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9559 varop
= XEXP (varop
, 0);
9563 /* ... fall through ... */
9568 /* Here we have two nested shifts. The result is usually the
9569 AND of a new shift with a mask. We compute the result below. */
9570 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9571 && INTVAL (XEXP (varop
, 1)) >= 0
9572 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9573 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9574 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9576 enum rtx_code first_code
= GET_CODE (varop
);
9577 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9578 unsigned HOST_WIDE_INT mask
;
9581 /* We have one common special case. We can't do any merging if
9582 the inner code is an ASHIFTRT of a smaller mode. However, if
9583 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9584 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9585 we can convert it to
9586 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9587 This simplifies certain SIGN_EXTEND operations. */
9588 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9589 && count
== (unsigned int)
9590 (GET_MODE_BITSIZE (result_mode
)
9591 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9593 /* C3 has the low-order C1 bits zero. */
9595 mask
= (GET_MODE_MASK (mode
)
9596 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9598 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9599 XEXP (varop
, 0), mask
);
9600 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9602 count
= first_count
;
9607 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9608 than C1 high-order bits equal to the sign bit, we can convert
9609 this to either an ASHIFT or an ASHIFTRT depending on the
9612 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9614 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9615 && GET_MODE (varop
) == shift_mode
9616 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9619 varop
= XEXP (varop
, 0);
9621 signed_count
= count
- first_count
;
9622 if (signed_count
< 0)
9623 count
= -signed_count
, code
= ASHIFT
;
9625 count
= signed_count
;
9630 /* There are some cases we can't do. If CODE is ASHIFTRT,
9631 we can only do this if FIRST_CODE is also ASHIFTRT.
9633 We can't do the case when CODE is ROTATE and FIRST_CODE is
9636 If the mode of this shift is not the mode of the outer shift,
9637 we can't do this if either shift is a right shift or ROTATE.
9639 Finally, we can't do any of these if the mode is too wide
9640 unless the codes are the same.
9642 Handle the case where the shift codes are the same
9645 if (code
== first_code
)
9647 if (GET_MODE (varop
) != result_mode
9648 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9652 count
+= first_count
;
9653 varop
= XEXP (varop
, 0);
9657 if (code
== ASHIFTRT
9658 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9659 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9660 || (GET_MODE (varop
) != result_mode
9661 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9662 || first_code
== ROTATE
9663 || code
== ROTATE
)))
9666 /* To compute the mask to apply after the shift, shift the
9667 nonzero bits of the inner shift the same way the
9668 outer shift will. */
9670 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9673 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9676 /* Give up if we can't compute an outer operation to use. */
9678 || GET_CODE (mask_rtx
) != CONST_INT
9679 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9681 result_mode
, &complement_p
))
9684 /* If the shifts are in the same direction, we add the
9685 counts. Otherwise, we subtract them. */
9686 signed_count
= count
;
9687 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9688 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9689 signed_count
+= first_count
;
9691 signed_count
-= first_count
;
9693 /* If COUNT is positive, the new shift is usually CODE,
9694 except for the two exceptions below, in which case it is
9695 FIRST_CODE. If the count is negative, FIRST_CODE should
9697 if (signed_count
> 0
9698 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9699 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9700 code
= first_code
, count
= signed_count
;
9701 else if (signed_count
< 0)
9702 code
= first_code
, count
= -signed_count
;
9704 count
= signed_count
;
9706 varop
= XEXP (varop
, 0);
9710 /* If we have (A << B << C) for any shift, we can convert this to
9711 (A << C << B). This wins if A is a constant. Only try this if
9712 B is not a constant. */
9714 else if (GET_CODE (varop
) == code
9715 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9717 = simplify_binary_operation (code
, mode
,
9721 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9728 /* Make this fit the case below. */
9729 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9730 GEN_INT (GET_MODE_MASK (mode
)));
9736 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9737 with C the size of VAROP - 1 and the shift is logical if
9738 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9739 we have an (le X 0) operation. If we have an arithmetic shift
9740 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9741 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9743 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9744 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9745 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9746 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9747 && count
== (unsigned int)
9748 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9749 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9752 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9755 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9756 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9761 /* If we have (shift (logical)), move the logical to the outside
9762 to allow it to possibly combine with another logical and the
9763 shift to combine with another shift. This also canonicalizes to
9764 what a ZERO_EXTRACT looks like. Also, some machines have
9765 (and (shift)) insns. */
9767 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9768 && (new = simplify_binary_operation (code
, result_mode
,
9770 GEN_INT (count
))) != 0
9771 && GET_CODE (new) == CONST_INT
9772 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9773 INTVAL (new), result_mode
, &complement_p
))
9775 varop
= XEXP (varop
, 0);
9779 /* If we can't do that, try to simplify the shift in each arm of the
9780 logical expression, make a new logical expression, and apply
9781 the inverse distributive law. */
9783 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9784 XEXP (varop
, 0), count
);
9785 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9786 XEXP (varop
, 1), count
);
9788 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9789 varop
= apply_distributive_law (varop
);
9796 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9797 says that the sign bit can be tested, FOO has mode MODE, C is
9798 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9799 that may be nonzero. */
9800 if (code
== LSHIFTRT
9801 && XEXP (varop
, 1) == const0_rtx
9802 && GET_MODE (XEXP (varop
, 0)) == result_mode
9803 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9804 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9805 && ((STORE_FLAG_VALUE
9806 & ((HOST_WIDE_INT
) 1
9807 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9808 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9809 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9810 (HOST_WIDE_INT
) 1, result_mode
,
9813 varop
= XEXP (varop
, 0);
9820 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9821 than the number of bits in the mode is equivalent to A. */
9822 if (code
== LSHIFTRT
9823 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9824 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9826 varop
= XEXP (varop
, 0);
9831 /* NEG commutes with ASHIFT since it is multiplication. Move the
9832 NEG outside to allow shifts to combine. */
9834 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9835 (HOST_WIDE_INT
) 0, result_mode
,
9838 varop
= XEXP (varop
, 0);
9844 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9845 is one less than the number of bits in the mode is
9846 equivalent to (xor A 1). */
9847 if (code
== LSHIFTRT
9848 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9849 && XEXP (varop
, 1) == constm1_rtx
9850 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9851 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9852 (HOST_WIDE_INT
) 1, result_mode
,
9856 varop
= XEXP (varop
, 0);
9860 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9861 that might be nonzero in BAR are those being shifted out and those
9862 bits are known zero in FOO, we can replace the PLUS with FOO.
9863 Similarly in the other operand order. This code occurs when
9864 we are computing the size of a variable-size array. */
9866 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9867 && count
< HOST_BITS_PER_WIDE_INT
9868 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9869 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9870 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9872 varop
= XEXP (varop
, 0);
9875 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9876 && count
< HOST_BITS_PER_WIDE_INT
9877 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9878 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9880 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9881 & nonzero_bits (XEXP (varop
, 1),
9884 varop
= XEXP (varop
, 1);
9888 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9890 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9891 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9893 GEN_INT (count
))) != 0
9894 && GET_CODE (new) == CONST_INT
9895 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9896 INTVAL (new), result_mode
, &complement_p
))
9898 varop
= XEXP (varop
, 0);
9904 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9905 with C the size of VAROP - 1 and the shift is logical if
9906 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9907 we have a (gt X 0) operation. If the shift is arithmetic with
9908 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9909 we have a (neg (gt X 0)) operation. */
9911 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9912 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9913 && count
== (unsigned int)
9914 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9915 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9916 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9917 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9919 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9922 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9925 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9926 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9933 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9934 if the truncate does not affect the value. */
9935 if (code
== LSHIFTRT
9936 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9937 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9938 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9939 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9940 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9942 rtx varop_inner
= XEXP (varop
, 0);
9945 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9946 XEXP (varop_inner
, 0),
9948 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9949 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9962 /* We need to determine what mode to do the shift in. If the shift is
9963 a right shift or ROTATE, we must always do it in the mode it was
9964 originally done in. Otherwise, we can do it in MODE, the widest mode
9965 encountered. The code we care about is that of the shift that will
9966 actually be done, not the shift that was originally requested. */
9968 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9969 ? result_mode
: mode
);
9971 /* We have now finished analyzing the shift. The result should be
9972 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9973 OUTER_OP is non-NIL, it is an operation that needs to be applied
9974 to the result of the shift. OUTER_CONST is the relevant constant,
9975 but we must turn off all bits turned off in the shift.
9977 If we were passed a value for X, see if we can use any pieces of
9978 it. If not, make new rtx. */
9980 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9981 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9982 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9983 const_rtx
= XEXP (x
, 1);
9985 const_rtx
= GEN_INT (count
);
9987 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9988 && GET_MODE (XEXP (x
, 0)) == shift_mode
9989 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9990 varop
= XEXP (x
, 0);
9991 else if (GET_MODE (varop
) != shift_mode
)
9992 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9994 /* If we can't make the SUBREG, try to return what we were given. */
9995 if (GET_CODE (varop
) == CLOBBER
)
9996 return x
? x
: varop
;
9998 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
10002 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
10004 /* If we have an outer operation and we just made a shift, it is
10005 possible that we could have simplified the shift were it not
10006 for the outer operation. So try to do the simplification
10009 if (outer_op
!= NIL
&& GET_CODE (x
) == code
10010 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
10011 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
10012 INTVAL (XEXP (x
, 1)));
10014 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10015 turn off all the bits that the shift would have turned off. */
10016 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10017 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10018 GET_MODE_MASK (result_mode
) >> orig_count
);
10020 /* Do the remainder of the processing in RESULT_MODE. */
10021 x
= gen_lowpart_for_combine (result_mode
, x
);
10023 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10026 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10028 if (outer_op
!= NIL
)
10030 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10031 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10033 if (outer_op
== AND
)
10034 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10035 else if (outer_op
== SET
)
10036 /* This means that we have determined that the result is
10037 equivalent to a constant. This should be rare. */
10038 x
= GEN_INT (outer_const
);
10039 else if (GET_RTX_CLASS (outer_op
) == '1')
10040 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10042 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
10048 /* Like recog, but we receive the address of a pointer to a new pattern.
10049 We try to match the rtx that the pointer points to.
10050 If that fails, we may try to modify or replace the pattern,
10051 storing the replacement into the same pointer object.
10053 Modifications include deletion or addition of CLOBBERs.
10055 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10056 the CLOBBERs are placed.
10058 The value is the final insn code from the pattern ultimately matched,
10062 recog_for_combine (pnewpat
, insn
, pnotes
)
10067 rtx pat
= *pnewpat
;
10068 int insn_code_number
;
10069 int num_clobbers_to_add
= 0;
10074 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10075 we use to indicate that something didn't match. If we find such a
10076 thing, force rejection. */
10077 if (GET_CODE (pat
) == PARALLEL
)
10078 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10079 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10080 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10083 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
10084 instruction for pattern recognition. */
10085 dummy_insn
= shallow_copy_rtx (insn
);
10086 PATTERN (dummy_insn
) = pat
;
10087 REG_NOTES (dummy_insn
) = 0;
10089 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
10091 /* If it isn't, there is the possibility that we previously had an insn
10092 that clobbered some register as a side effect, but the combined
10093 insn doesn't need to do that. So try once more without the clobbers
10094 unless this represents an ASM insn. */
10096 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10097 && GET_CODE (pat
) == PARALLEL
)
10101 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10102 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10105 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10109 SUBST_INT (XVECLEN (pat
, 0), pos
);
10112 pat
= XVECEXP (pat
, 0, 0);
10114 PATTERN (dummy_insn
) = pat
;
10115 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
10118 /* Recognize all noop sets, these will be killed by followup pass. */
10119 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10120 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10122 /* If we had any clobbers to add, make a new pattern than contains
10123 them. Then check to make sure that all of them are dead. */
10124 if (num_clobbers_to_add
)
10126 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10127 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10128 ? (XVECLEN (pat
, 0)
10129 + num_clobbers_to_add
)
10130 : num_clobbers_to_add
+ 1));
10132 if (GET_CODE (pat
) == PARALLEL
)
10133 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10134 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10136 XVECEXP (newpat
, 0, 0) = pat
;
10138 add_clobbers (newpat
, insn_code_number
);
10140 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10141 i
< XVECLEN (newpat
, 0); i
++)
10143 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
10144 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10146 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
10147 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10155 return insn_code_number
;
10158 /* Like gen_lowpart but for use by combine. In combine it is not possible
10159 to create any new pseudoregs. However, it is safe to create
10160 invalid memory addresses, because combine will try to recognize
10161 them and all they will do is make the combine attempt fail.
10163 If for some reason this cannot do its job, an rtx
10164 (clobber (const_int 0)) is returned.
10165 An insn containing that will not be recognized. */
10170 gen_lowpart_for_combine (mode
, x
)
10171 enum machine_mode mode
;
10176 if (GET_MODE (x
) == mode
)
10179 /* We can only support MODE being wider than a word if X is a
10180 constant integer or has a mode the same size. */
10182 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
10183 && ! ((GET_MODE (x
) == VOIDmode
10184 && (GET_CODE (x
) == CONST_INT
10185 || GET_CODE (x
) == CONST_DOUBLE
))
10186 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
10187 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10189 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10190 won't know what to do. So we will strip off the SUBREG here and
10191 process normally. */
10192 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
10194 x
= SUBREG_REG (x
);
10195 if (GET_MODE (x
) == mode
)
10199 result
= gen_lowpart_common (mode
, x
);
10200 #ifdef CANNOT_CHANGE_MODE_CLASS
10202 && GET_CODE (result
) == SUBREG
10203 && GET_CODE (SUBREG_REG (result
)) == REG
10204 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10205 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10207 + GET_MODE (result
));
10213 if (GET_CODE (x
) == MEM
)
10217 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10219 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10220 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10222 /* If we want to refer to something bigger than the original memref,
10223 generate a perverse subreg instead. That will force a reload
10224 of the original memref X. */
10225 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10226 return gen_rtx_SUBREG (mode
, x
, 0);
10228 if (WORDS_BIG_ENDIAN
)
10229 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10230 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10232 if (BYTES_BIG_ENDIAN
)
10234 /* Adjust the address so that the address-after-the-data is
10236 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10237 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10240 return adjust_address_nv (x
, mode
, offset
);
10243 /* If X is a comparison operator, rewrite it in a new mode. This
10244 probably won't match, but may allow further simplifications. */
10245 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10246 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10248 /* If we couldn't simplify X any other way, just enclose it in a
10249 SUBREG. Normally, this SUBREG won't match, but some patterns may
10250 include an explicit SUBREG or we may simplify it further in combine. */
10255 enum machine_mode sub_mode
= GET_MODE (x
);
10257 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10258 if (sub_mode
== VOIDmode
)
10260 sub_mode
= int_mode_for_mode (mode
);
10261 x
= gen_lowpart_common (sub_mode
, x
);
10263 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10266 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10270 /* These routines make binary and unary operations by first seeing if they
10271 fold; if not, a new expression is allocated. */
10274 gen_binary (code
, mode
, op0
, op1
)
10275 enum rtx_code code
;
10276 enum machine_mode mode
;
10282 if (GET_RTX_CLASS (code
) == 'c'
10283 && swap_commutative_operands_p (op0
, op1
))
10284 tem
= op0
, op0
= op1
, op1
= tem
;
10286 if (GET_RTX_CLASS (code
) == '<')
10288 enum machine_mode op_mode
= GET_MODE (op0
);
10290 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10291 just (REL_OP X Y). */
10292 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10294 op1
= XEXP (op0
, 1);
10295 op0
= XEXP (op0
, 0);
10296 op_mode
= GET_MODE (op0
);
10299 if (op_mode
== VOIDmode
)
10300 op_mode
= GET_MODE (op1
);
10301 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10304 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10309 /* Put complex operands first and constants second. */
10310 if (GET_RTX_CLASS (code
) == 'c'
10311 && swap_commutative_operands_p (op0
, op1
))
10312 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10314 /* If we are turning off bits already known off in OP0, we need not do
10316 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10317 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10318 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10321 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10324 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10325 comparison code that will be tested.
10327 The result is a possibly different comparison code to use. *POP0 and
10328 *POP1 may be updated.
10330 It is possible that we might detect that a comparison is either always
10331 true or always false. However, we do not perform general constant
10332 folding in combine, so this knowledge isn't useful. Such tautologies
10333 should have been detected earlier. Hence we ignore all such cases. */
10335 static enum rtx_code
10336 simplify_comparison (code
, pop0
, pop1
)
10337 enum rtx_code code
;
10345 enum machine_mode mode
, tmode
;
10347 /* Try a few ways of applying the same transformation to both operands. */
10350 #ifndef WORD_REGISTER_OPERATIONS
10351 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10352 so check specially. */
10353 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10354 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10355 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10356 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10357 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10358 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10359 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10360 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10361 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10362 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
10363 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10364 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
10365 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
10366 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
10367 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
10368 && (INTVAL (XEXP (op0
, 1))
10369 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10370 - (GET_MODE_BITSIZE
10371 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10373 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10374 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10378 /* If both operands are the same constant shift, see if we can ignore the
10379 shift. We can if the shift is a rotate or if the bits shifted out of
10380 this shift are known to be zero for both inputs and if the type of
10381 comparison is compatible with the shift. */
10382 if (GET_CODE (op0
) == GET_CODE (op1
)
10383 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10384 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10385 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10386 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10387 || (GET_CODE (op0
) == ASHIFTRT
10388 && (code
!= GTU
&& code
!= LTU
10389 && code
!= GEU
&& code
!= LEU
)))
10390 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10391 && INTVAL (XEXP (op0
, 1)) >= 0
10392 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10393 && XEXP (op0
, 1) == XEXP (op1
, 1))
10395 enum machine_mode mode
= GET_MODE (op0
);
10396 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10397 int shift_count
= INTVAL (XEXP (op0
, 1));
10399 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10400 mask
&= (mask
>> shift_count
) << shift_count
;
10401 else if (GET_CODE (op0
) == ASHIFT
)
10402 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10404 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10405 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10406 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10411 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10412 SUBREGs are of the same mode, and, in both cases, the AND would
10413 be redundant if the comparison was done in the narrower mode,
10414 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10415 and the operand's possibly nonzero bits are 0xffffff01; in that case
10416 if we only care about QImode, we don't need the AND). This case
10417 occurs if the output mode of an scc insn is not SImode and
10418 STORE_FLAG_VALUE == 1 (e.g., the 386).
10420 Similarly, check for a case where the AND's are ZERO_EXTEND
10421 operations from some narrower mode even though a SUBREG is not
10424 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10425 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10426 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10428 rtx inner_op0
= XEXP (op0
, 0);
10429 rtx inner_op1
= XEXP (op1
, 0);
10430 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10431 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10434 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10435 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10436 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10437 && (GET_MODE (SUBREG_REG (inner_op0
))
10438 == GET_MODE (SUBREG_REG (inner_op1
)))
10439 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10440 <= HOST_BITS_PER_WIDE_INT
)
10441 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10442 GET_MODE (SUBREG_REG (inner_op0
)))))
10443 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10444 GET_MODE (SUBREG_REG (inner_op1
))))))
10446 op0
= SUBREG_REG (inner_op0
);
10447 op1
= SUBREG_REG (inner_op1
);
10449 /* The resulting comparison is always unsigned since we masked
10450 off the original sign bit. */
10451 code
= unsigned_condition (code
);
10457 for (tmode
= GET_CLASS_NARROWEST_MODE
10458 (GET_MODE_CLASS (GET_MODE (op0
)));
10459 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10460 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10462 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10463 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10464 code
= unsigned_condition (code
);
10473 /* If both operands are NOT, we can strip off the outer operation
10474 and adjust the comparison code for swapped operands; similarly for
10475 NEG, except that this must be an equality comparison. */
10476 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10477 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10478 && (code
== EQ
|| code
== NE
)))
10479 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10485 /* If the first operand is a constant, swap the operands and adjust the
10486 comparison code appropriately, but don't do this if the second operand
10487 is already a constant integer. */
10488 if (swap_commutative_operands_p (op0
, op1
))
10490 tem
= op0
, op0
= op1
, op1
= tem
;
10491 code
= swap_condition (code
);
10494 /* We now enter a loop during which we will try to simplify the comparison.
10495 For the most part, we only are concerned with comparisons with zero,
10496 but some things may really be comparisons with zero but not start
10497 out looking that way. */
10499 while (GET_CODE (op1
) == CONST_INT
)
10501 enum machine_mode mode
= GET_MODE (op0
);
10502 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10503 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10504 int equality_comparison_p
;
10505 int sign_bit_comparison_p
;
10506 int unsigned_comparison_p
;
10507 HOST_WIDE_INT const_op
;
10509 /* We only want to handle integral modes. This catches VOIDmode,
10510 CCmode, and the floating-point modes. An exception is that we
10511 can handle VOIDmode if OP0 is a COMPARE or a comparison
10514 if (GET_MODE_CLASS (mode
) != MODE_INT
10515 && ! (mode
== VOIDmode
10516 && (GET_CODE (op0
) == COMPARE
10517 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10520 /* Get the constant we are comparing against and turn off all bits
10521 not on in our mode. */
10522 const_op
= INTVAL (op1
);
10523 if (mode
!= VOIDmode
)
10524 const_op
= trunc_int_for_mode (const_op
, mode
);
10525 op1
= GEN_INT (const_op
);
10527 /* If we are comparing against a constant power of two and the value
10528 being compared can only have that single bit nonzero (e.g., it was
10529 `and'ed with that bit), we can replace this with a comparison
10532 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10533 || code
== LT
|| code
== LTU
)
10534 && mode_width
<= HOST_BITS_PER_WIDE_INT
10535 && exact_log2 (const_op
) >= 0
10536 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10538 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10539 op1
= const0_rtx
, const_op
= 0;
10542 /* Similarly, if we are comparing a value known to be either -1 or
10543 0 with -1, change it to the opposite comparison against zero. */
10546 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10547 || code
== GEU
|| code
== LTU
)
10548 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10550 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10551 op1
= const0_rtx
, const_op
= 0;
10554 /* Do some canonicalizations based on the comparison code. We prefer
10555 comparisons against zero and then prefer equality comparisons.
10556 If we can reduce the size of a constant, we will do that too. */
10561 /* < C is equivalent to <= (C - 1) */
10565 op1
= GEN_INT (const_op
);
10567 /* ... fall through to LE case below. */
10573 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10577 op1
= GEN_INT (const_op
);
10581 /* If we are doing a <= 0 comparison on a value known to have
10582 a zero sign bit, we can replace this with == 0. */
10583 else if (const_op
== 0
10584 && mode_width
<= HOST_BITS_PER_WIDE_INT
10585 && (nonzero_bits (op0
, mode
)
10586 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10591 /* >= C is equivalent to > (C - 1). */
10595 op1
= GEN_INT (const_op
);
10597 /* ... fall through to GT below. */
10603 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10607 op1
= GEN_INT (const_op
);
10611 /* If we are doing a > 0 comparison on a value known to have
10612 a zero sign bit, we can replace this with != 0. */
10613 else if (const_op
== 0
10614 && mode_width
<= HOST_BITS_PER_WIDE_INT
10615 && (nonzero_bits (op0
, mode
)
10616 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10621 /* < C is equivalent to <= (C - 1). */
10625 op1
= GEN_INT (const_op
);
10627 /* ... fall through ... */
10630 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10631 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10632 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10634 const_op
= 0, op1
= const0_rtx
;
10642 /* unsigned <= 0 is equivalent to == 0 */
10646 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10647 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10648 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10650 const_op
= 0, op1
= const0_rtx
;
10656 /* >= C is equivalent to < (C - 1). */
10660 op1
= GEN_INT (const_op
);
10662 /* ... fall through ... */
10665 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10666 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10667 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10669 const_op
= 0, op1
= const0_rtx
;
10677 /* unsigned > 0 is equivalent to != 0 */
10681 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10682 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10683 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10685 const_op
= 0, op1
= const0_rtx
;
10694 /* Compute some predicates to simplify code below. */
10696 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10697 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10698 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10701 /* If this is a sign bit comparison and we can do arithmetic in
10702 MODE, say that we will only be needing the sign bit of OP0. */
10703 if (sign_bit_comparison_p
10704 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10705 op0
= force_to_mode (op0
, mode
,
10707 << (GET_MODE_BITSIZE (mode
) - 1)),
10710 /* Now try cases based on the opcode of OP0. If none of the cases
10711 does a "continue", we exit this loop immediately after the
10714 switch (GET_CODE (op0
))
10717 /* If we are extracting a single bit from a variable position in
10718 a constant that has only a single bit set and are comparing it
10719 with zero, we can convert this into an equality comparison
10720 between the position and the location of the single bit. */
10722 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10723 && XEXP (op0
, 1) == const1_rtx
10724 && equality_comparison_p
&& const_op
== 0
10725 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10727 if (BITS_BIG_ENDIAN
)
10729 enum machine_mode new_mode
10730 = mode_for_extraction (EP_extzv
, 1);
10731 if (new_mode
== MAX_MACHINE_MODE
)
10732 i
= BITS_PER_WORD
- 1 - i
;
10736 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10740 op0
= XEXP (op0
, 2);
10744 /* Result is nonzero iff shift count is equal to I. */
10745 code
= reverse_condition (code
);
10749 /* ... fall through ... */
10752 tem
= expand_compound_operation (op0
);
10761 /* If testing for equality, we can take the NOT of the constant. */
10762 if (equality_comparison_p
10763 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10765 op0
= XEXP (op0
, 0);
10770 /* If just looking at the sign bit, reverse the sense of the
10772 if (sign_bit_comparison_p
)
10774 op0
= XEXP (op0
, 0);
10775 code
= (code
== GE
? LT
: GE
);
10781 /* If testing for equality, we can take the NEG of the constant. */
10782 if (equality_comparison_p
10783 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10785 op0
= XEXP (op0
, 0);
10790 /* The remaining cases only apply to comparisons with zero. */
10794 /* When X is ABS or is known positive,
10795 (neg X) is < 0 if and only if X != 0. */
10797 if (sign_bit_comparison_p
10798 && (GET_CODE (XEXP (op0
, 0)) == ABS
10799 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10800 && (nonzero_bits (XEXP (op0
, 0), mode
)
10801 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10803 op0
= XEXP (op0
, 0);
10804 code
= (code
== LT
? NE
: EQ
);
10808 /* If we have NEG of something whose two high-order bits are the
10809 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10810 if (num_sign_bit_copies (op0
, mode
) >= 2)
10812 op0
= XEXP (op0
, 0);
10813 code
= swap_condition (code
);
10819 /* If we are testing equality and our count is a constant, we
10820 can perform the inverse operation on our RHS. */
10821 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10822 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10823 op1
, XEXP (op0
, 1))) != 0)
10825 op0
= XEXP (op0
, 0);
10830 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10831 a particular bit. Convert it to an AND of a constant of that
10832 bit. This will be converted into a ZERO_EXTRACT. */
10833 if (const_op
== 0 && sign_bit_comparison_p
10834 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10835 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10837 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10840 - INTVAL (XEXP (op0
, 1)))));
10841 code
= (code
== LT
? NE
: EQ
);
10845 /* Fall through. */
10848 /* ABS is ignorable inside an equality comparison with zero. */
10849 if (const_op
== 0 && equality_comparison_p
)
10851 op0
= XEXP (op0
, 0);
10857 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10858 to (compare FOO CONST) if CONST fits in FOO's mode and we
10859 are either testing inequality or have an unsigned comparison
10860 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10861 if (! unsigned_comparison_p
10862 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10863 <= HOST_BITS_PER_WIDE_INT
)
10864 && ((unsigned HOST_WIDE_INT
) const_op
10865 < (((unsigned HOST_WIDE_INT
) 1
10866 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10868 op0
= XEXP (op0
, 0);
10874 /* Check for the case where we are comparing A - C1 with C2,
10875 both constants are smaller than 1/2 the maximum positive
10876 value in MODE, and the comparison is equality or unsigned.
10877 In that case, if A is either zero-extended to MODE or has
10878 sufficient sign bits so that the high-order bit in MODE
10879 is a copy of the sign in the inner mode, we can prove that it is
10880 safe to do the operation in the wider mode. This simplifies
10881 many range checks. */
10883 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10884 && subreg_lowpart_p (op0
)
10885 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10886 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10887 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10888 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10889 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10890 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10891 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10892 GET_MODE (SUBREG_REG (op0
)))
10893 & ~GET_MODE_MASK (mode
))
10894 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10895 GET_MODE (SUBREG_REG (op0
)))
10897 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10898 - GET_MODE_BITSIZE (mode
)))))
10900 op0
= SUBREG_REG (op0
);
10904 /* If the inner mode is narrower and we are extracting the low part,
10905 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10906 if (subreg_lowpart_p (op0
)
10907 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10908 /* Fall through */ ;
10912 /* ... fall through ... */
10915 if ((unsigned_comparison_p
|| equality_comparison_p
)
10916 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10917 <= HOST_BITS_PER_WIDE_INT
)
10918 && ((unsigned HOST_WIDE_INT
) const_op
10919 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10921 op0
= XEXP (op0
, 0);
10927 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10928 this for equality comparisons due to pathological cases involving
10930 if (equality_comparison_p
10931 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10932 op1
, XEXP (op0
, 1))))
10934 op0
= XEXP (op0
, 0);
10939 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10940 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10941 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10943 op0
= XEXP (XEXP (op0
, 0), 0);
10944 code
= (code
== LT
? EQ
: NE
);
10950 /* We used to optimize signed comparisons against zero, but that
10951 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10952 arrive here as equality comparisons, or (GEU, LTU) are
10953 optimized away. No need to special-case them. */
10955 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10956 (eq B (minus A C)), whichever simplifies. We can only do
10957 this for equality comparisons due to pathological cases involving
10959 if (equality_comparison_p
10960 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10961 XEXP (op0
, 1), op1
)))
10963 op0
= XEXP (op0
, 0);
10968 if (equality_comparison_p
10969 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10970 XEXP (op0
, 0), op1
)))
10972 op0
= XEXP (op0
, 1);
10977 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10978 of bits in X minus 1, is one iff X > 0. */
10979 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10980 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10981 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10983 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10985 op0
= XEXP (op0
, 1);
10986 code
= (code
== GE
? LE
: GT
);
10992 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10993 if C is zero or B is a constant. */
10994 if (equality_comparison_p
10995 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10996 XEXP (op0
, 1), op1
)))
10998 op0
= XEXP (op0
, 0);
11005 case UNEQ
: case LTGT
:
11006 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11007 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11008 case UNORDERED
: case ORDERED
:
11009 /* We can't do anything if OP0 is a condition code value, rather
11010 than an actual data value. */
11012 || CC0_P (XEXP (op0
, 0))
11013 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11016 /* Get the two operands being compared. */
11017 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11018 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11020 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11022 /* Check for the cases where we simply want the result of the
11023 earlier test or the opposite of that result. */
11024 if (code
== NE
|| code
== EQ
11025 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
11026 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11027 && (STORE_FLAG_VALUE
11028 & (((HOST_WIDE_INT
) 1
11029 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
11030 && (code
== LT
|| code
== GE
)))
11032 enum rtx_code new_code
;
11033 if (code
== LT
|| code
== NE
)
11034 new_code
= GET_CODE (op0
);
11036 new_code
= combine_reversed_comparison_code (op0
);
11038 if (new_code
!= UNKNOWN
)
11049 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11051 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11052 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11053 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11055 op0
= XEXP (op0
, 1);
11056 code
= (code
== GE
? GT
: LE
);
11062 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11063 will be converted to a ZERO_EXTRACT later. */
11064 if (const_op
== 0 && equality_comparison_p
11065 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11066 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11068 op0
= simplify_and_const_int
11069 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
11071 XEXP (XEXP (op0
, 0), 1)),
11072 (HOST_WIDE_INT
) 1);
11076 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11077 zero and X is a comparison and C1 and C2 describe only bits set
11078 in STORE_FLAG_VALUE, we can compare with X. */
11079 if (const_op
== 0 && equality_comparison_p
11080 && mode_width
<= HOST_BITS_PER_WIDE_INT
11081 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11082 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11083 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11084 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11085 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11087 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11088 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11089 if ((~STORE_FLAG_VALUE
& mask
) == 0
11090 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
11091 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11092 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
11094 op0
= XEXP (XEXP (op0
, 0), 0);
11099 /* If we are doing an equality comparison of an AND of a bit equal
11100 to the sign bit, replace this with a LT or GE comparison of
11101 the underlying value. */
11102 if (equality_comparison_p
11104 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11105 && mode_width
<= HOST_BITS_PER_WIDE_INT
11106 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11107 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11109 op0
= XEXP (op0
, 0);
11110 code
= (code
== EQ
? GE
: LT
);
11114 /* If this AND operation is really a ZERO_EXTEND from a narrower
11115 mode, the constant fits within that mode, and this is either an
11116 equality or unsigned comparison, try to do this comparison in
11117 the narrower mode. */
11118 if ((equality_comparison_p
|| unsigned_comparison_p
)
11119 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11120 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
11121 & GET_MODE_MASK (mode
))
11123 && const_op
>> i
== 0
11124 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
11126 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
11130 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
11131 in both M1 and M2 and the SUBREG is either paradoxical or
11132 represents the low part, permute the SUBREG and the AND and
11134 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
11135 /* Require an integral mode, to avoid creating something like
11137 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
11138 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
11139 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
11140 As originally written the upper bits have a defined value
11141 due to the AND operation. However, if we commute the AND
11142 inside the SUBREG then they no longer have defined values
11143 and the meaning of the code has been changed. */
11145 #ifdef WORD_REGISTER_OPERATIONS
11147 > (GET_MODE_BITSIZE
11148 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
11149 && mode_width
<= BITS_PER_WORD
)
11152 <= (GET_MODE_BITSIZE
11153 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
11154 && subreg_lowpart_p (XEXP (op0
, 0))))
11155 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11156 && mode_width
<= HOST_BITS_PER_WIDE_INT
11157 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
11158 <= HOST_BITS_PER_WIDE_INT
)
11159 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
11160 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
11161 & INTVAL (XEXP (op0
, 1)))
11162 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
11163 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11164 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
11168 = gen_lowpart_for_combine
11170 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
11171 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
11175 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11176 (eq (and (lshiftrt X) 1) 0). */
11177 if (const_op
== 0 && equality_comparison_p
11178 && XEXP (op0
, 1) == const1_rtx
11179 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11180 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
11182 op0
= simplify_and_const_int
11184 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
11185 XEXP (XEXP (op0
, 0), 1)),
11186 (HOST_WIDE_INT
) 1);
11187 code
= (code
== NE
? EQ
: NE
);
11193 /* If we have (compare (ashift FOO N) (const_int C)) and
11194 the high order N bits of FOO (N+1 if an inequality comparison)
11195 are known to be zero, we can do this by comparing FOO with C
11196 shifted right N bits so long as the low-order N bits of C are
11198 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11199 && INTVAL (XEXP (op0
, 1)) >= 0
11200 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11201 < HOST_BITS_PER_WIDE_INT
)
11203 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11204 && mode_width
<= HOST_BITS_PER_WIDE_INT
11205 && (nonzero_bits (XEXP (op0
, 0), mode
)
11206 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11207 + ! equality_comparison_p
))) == 0)
11209 /* We must perform a logical shift, not an arithmetic one,
11210 as we want the top N bits of C to be zero. */
11211 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11213 temp
>>= INTVAL (XEXP (op0
, 1));
11214 op1
= gen_int_mode (temp
, mode
);
11215 op0
= XEXP (op0
, 0);
11219 /* If we are doing a sign bit comparison, it means we are testing
11220 a particular bit. Convert it to the appropriate AND. */
11221 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11222 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11224 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11227 - INTVAL (XEXP (op0
, 1)))));
11228 code
= (code
== LT
? NE
: EQ
);
11232 /* If this an equality comparison with zero and we are shifting
11233 the low bit to the sign bit, we can convert this to an AND of the
11235 if (const_op
== 0 && equality_comparison_p
11236 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11237 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11240 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11241 (HOST_WIDE_INT
) 1);
11247 /* If this is an equality comparison with zero, we can do this
11248 as a logical shift, which might be much simpler. */
11249 if (equality_comparison_p
&& const_op
== 0
11250 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11252 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11254 INTVAL (XEXP (op0
, 1)));
11258 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11259 do the comparison in a narrower mode. */
11260 if (! unsigned_comparison_p
11261 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11262 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11263 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11264 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11265 MODE_INT
, 1)) != BLKmode
11266 && (((unsigned HOST_WIDE_INT
) const_op
11267 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11268 <= GET_MODE_MASK (tmode
)))
11270 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11274 /* Likewise if OP0 is a PLUS of a sign extension with a
11275 constant, which is usually represented with the PLUS
11276 between the shifts. */
11277 if (! unsigned_comparison_p
11278 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11279 && GET_CODE (XEXP (op0
, 0)) == PLUS
11280 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11281 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11282 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11283 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11284 MODE_INT
, 1)) != BLKmode
11285 && (((unsigned HOST_WIDE_INT
) const_op
11286 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11287 <= GET_MODE_MASK (tmode
)))
11289 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11290 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11291 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11294 op0
= gen_binary (PLUS
, tmode
,
11295 gen_lowpart_for_combine (tmode
, inner
),
11300 /* ... fall through ... */
11302 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11303 the low order N bits of FOO are known to be zero, we can do this
11304 by comparing FOO with C shifted left N bits so long as no
11305 overflow occurs. */
11306 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11307 && INTVAL (XEXP (op0
, 1)) >= 0
11308 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11309 && mode_width
<= HOST_BITS_PER_WIDE_INT
11310 && (nonzero_bits (XEXP (op0
, 0), mode
)
11311 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11312 && (((unsigned HOST_WIDE_INT
) const_op
11313 + (GET_CODE (op0
) != LSHIFTRT
11314 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11317 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11319 /* If the shift was logical, then we must make the condition
11321 if (GET_CODE (op0
) == LSHIFTRT
)
11322 code
= unsigned_condition (code
);
11324 const_op
<<= INTVAL (XEXP (op0
, 1));
11325 op1
= GEN_INT (const_op
);
11326 op0
= XEXP (op0
, 0);
11330 /* If we are using this shift to extract just the sign bit, we
11331 can replace this with an LT or GE comparison. */
11333 && (equality_comparison_p
|| sign_bit_comparison_p
)
11334 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11335 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11338 op0
= XEXP (op0
, 0);
11339 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11351 /* Now make any compound operations involved in this comparison. Then,
11352 check for an outmost SUBREG on OP0 that is not doing anything or is
11353 paradoxical. The latter transformation must only be performed when
11354 it is known that the "extra" bits will be the same in op0 and op1 or
11355 that they don't matter. There are three cases to consider:
11357 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11358 care bits and we can assume they have any convenient value. So
11359 making the transformation is safe.
11361 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11362 In this case the upper bits of op0 are undefined. We should not make
11363 the simplification in that case as we do not know the contents of
11366 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11367 NIL. In that case we know those bits are zeros or ones. We must
11368 also be sure that they are the same as the upper bits of op1.
11370 We can never remove a SUBREG for a non-equality comparison because
11371 the sign bit is in a different place in the underlying object. */
11373 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11374 op1
= make_compound_operation (op1
, SET
);
11376 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11377 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11379 && GET_CODE (SUBREG_REG (op0
)) == REG
11380 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11381 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11382 && (code
== NE
|| code
== EQ
))
11384 if (GET_MODE_SIZE (GET_MODE (op0
))
11385 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11387 op0
= SUBREG_REG (op0
);
11388 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11390 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11391 <= HOST_BITS_PER_WIDE_INT
)
11392 && (nonzero_bits (SUBREG_REG (op0
),
11393 GET_MODE (SUBREG_REG (op0
)))
11394 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11396 tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)), op1
);
11398 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11399 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11400 op0
= SUBREG_REG (op0
), op1
= tem
;
11404 /* We now do the opposite procedure: Some machines don't have compare
11405 insns in all modes. If OP0's mode is an integer mode smaller than a
11406 word and we can't do a compare in that mode, see if there is a larger
11407 mode for which we can do the compare. There are a number of cases in
11408 which we can use the wider mode. */
11410 mode
= GET_MODE (op0
);
11411 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11412 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11413 && ! have_insn_for (COMPARE
, mode
))
11414 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11416 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11417 tmode
= GET_MODE_WIDER_MODE (tmode
))
11418 if (have_insn_for (COMPARE
, tmode
))
11422 /* If the only nonzero bits in OP0 and OP1 are those in the
11423 narrower mode and this is an equality or unsigned comparison,
11424 we can use the wider mode. Similarly for sign-extended
11425 values, in which case it is true for all comparisons. */
11426 zero_extended
= ((code
== EQ
|| code
== NE
11427 || code
== GEU
|| code
== GTU
11428 || code
== LEU
|| code
== LTU
)
11429 && (nonzero_bits (op0
, tmode
)
11430 & ~GET_MODE_MASK (mode
)) == 0
11431 && ((GET_CODE (op1
) == CONST_INT
11432 || (nonzero_bits (op1
, tmode
)
11433 & ~GET_MODE_MASK (mode
)) == 0)));
11436 || ((num_sign_bit_copies (op0
, tmode
)
11437 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11438 - GET_MODE_BITSIZE (mode
)))
11439 && (num_sign_bit_copies (op1
, tmode
)
11440 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11441 - GET_MODE_BITSIZE (mode
)))))
11443 /* If OP0 is an AND and we don't have an AND in MODE either,
11444 make a new AND in the proper mode. */
11445 if (GET_CODE (op0
) == AND
11446 && !have_insn_for (AND
, mode
))
11447 op0
= gen_binary (AND
, tmode
,
11448 gen_lowpart_for_combine (tmode
,
11450 gen_lowpart_for_combine (tmode
,
11453 op0
= gen_lowpart_for_combine (tmode
, op0
);
11454 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11455 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11456 op1
= gen_lowpart_for_combine (tmode
, op1
);
11460 /* If this is a test for negative, we can make an explicit
11461 test of the sign bit. */
11463 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11464 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11466 op0
= gen_binary (AND
, tmode
,
11467 gen_lowpart_for_combine (tmode
, op0
),
11468 GEN_INT ((HOST_WIDE_INT
) 1
11469 << (GET_MODE_BITSIZE (mode
) - 1)));
11470 code
= (code
== LT
) ? NE
: EQ
;
11475 #ifdef CANONICALIZE_COMPARISON
11476 /* If this machine only supports a subset of valid comparisons, see if we
11477 can convert an unsupported one into a supported one. */
11478 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11487 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11488 searching backward. */
11489 static enum rtx_code
11490 combine_reversed_comparison_code (exp
)
11493 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11496 if (code1
!= UNKNOWN
11497 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11499 /* Otherwise try and find where the condition codes were last set and
11501 x
= get_last_value (XEXP (exp
, 0));
11502 if (!x
|| GET_CODE (x
) != COMPARE
)
11504 return reversed_comparison_code_parts (GET_CODE (exp
),
11505 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11508 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11509 Return NULL_RTX in case we fail to do the reversal. */
11511 reversed_comparison (exp
, mode
, op0
, op1
)
11513 enum machine_mode mode
;
11515 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11516 if (reversed_code
== UNKNOWN
)
11519 return gen_binary (reversed_code
, mode
, op0
, op1
);
11522 /* Utility function for following routine. Called when X is part of a value
11523 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11524 for each register mentioned. Similar to mention_regs in cse.c */
11527 update_table_tick (x
)
11530 enum rtx_code code
= GET_CODE (x
);
11531 const char *fmt
= GET_RTX_FORMAT (code
);
11536 unsigned int regno
= REGNO (x
);
11537 unsigned int endregno
11538 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11539 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11542 for (r
= regno
; r
< endregno
; r
++)
11543 reg_last_set_table_tick
[r
] = label_tick
;
11548 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11549 /* Note that we can't have an "E" in values stored; see
11550 get_last_value_validate. */
11553 /* Check for identical subexpressions. If x contains
11554 identical subexpression we only have to traverse one of
11557 && (GET_RTX_CLASS (code
) == '2'
11558 || GET_RTX_CLASS (code
) == 'c'))
11560 /* Note that at this point x1 has already been
11562 rtx x0
= XEXP (x
, 0);
11563 rtx x1
= XEXP (x
, 1);
11565 /* If x0 and x1 are identical then there is no need to
11570 /* If x0 is identical to a subexpression of x1 then while
11571 processing x1, x0 has already been processed. Thus we
11572 are done with x. */
11573 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11574 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11575 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11578 /* If x1 is identical to a subexpression of x0 then we
11579 still have to process the rest of x0. */
11580 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11581 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11582 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11584 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11589 update_table_tick (XEXP (x
, i
));
11593 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11594 are saying that the register is clobbered and we no longer know its
11595 value. If INSN is zero, don't update reg_last_set; this is only permitted
11596 with VALUE also zero and is used to invalidate the register. */
11599 record_value_for_reg (reg
, insn
, value
)
11604 unsigned int regno
= REGNO (reg
);
11605 unsigned int endregno
11606 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11607 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11610 /* If VALUE contains REG and we have a previous value for REG, substitute
11611 the previous value. */
11612 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11616 /* Set things up so get_last_value is allowed to see anything set up to
11618 subst_low_cuid
= INSN_CUID (insn
);
11619 tem
= get_last_value (reg
);
11621 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11622 it isn't going to be useful and will take a lot of time to process,
11623 so just use the CLOBBER. */
11627 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11628 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11629 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11630 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11631 tem
= XEXP (tem
, 0);
11633 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11637 /* For each register modified, show we don't know its value, that
11638 we don't know about its bitwise content, that its value has been
11639 updated, and that we don't know the location of the death of the
11641 for (i
= regno
; i
< endregno
; i
++)
11644 reg_last_set
[i
] = insn
;
11646 reg_last_set_value
[i
] = 0;
11647 reg_last_set_mode
[i
] = 0;
11648 reg_last_set_nonzero_bits
[i
] = 0;
11649 reg_last_set_sign_bit_copies
[i
] = 0;
11650 reg_last_death
[i
] = 0;
11653 /* Mark registers that are being referenced in this value. */
11655 update_table_tick (value
);
11657 /* Now update the status of each register being set.
11658 If someone is using this register in this block, set this register
11659 to invalid since we will get confused between the two lives in this
11660 basic block. This makes using this register always invalid. In cse, we
11661 scan the table to invalidate all entries using this register, but this
11662 is too much work for us. */
11664 for (i
= regno
; i
< endregno
; i
++)
11666 reg_last_set_label
[i
] = label_tick
;
11667 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11668 reg_last_set_invalid
[i
] = 1;
11670 reg_last_set_invalid
[i
] = 0;
11673 /* The value being assigned might refer to X (like in "x++;"). In that
11674 case, we must replace it with (clobber (const_int 0)) to prevent
11676 if (value
&& ! get_last_value_validate (&value
, insn
,
11677 reg_last_set_label
[regno
], 0))
11679 value
= copy_rtx (value
);
11680 if (! get_last_value_validate (&value
, insn
,
11681 reg_last_set_label
[regno
], 1))
11685 /* For the main register being modified, update the value, the mode, the
11686 nonzero bits, and the number of sign bit copies. */
11688 reg_last_set_value
[regno
] = value
;
11692 enum machine_mode mode
= GET_MODE (reg
);
11693 subst_low_cuid
= INSN_CUID (insn
);
11694 reg_last_set_mode
[regno
] = mode
;
11695 if (GET_MODE_CLASS (mode
) == MODE_INT
11696 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11697 mode
= nonzero_bits_mode
;
11698 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11699 reg_last_set_sign_bit_copies
[regno
]
11700 = num_sign_bit_copies (value
, GET_MODE (reg
));
11704 /* Called via note_stores from record_dead_and_set_regs to handle one
11705 SET or CLOBBER in an insn. DATA is the instruction in which the
11706 set is occurring. */
11709 record_dead_and_set_regs_1 (dest
, setter
, data
)
11713 rtx record_dead_insn
= (rtx
) data
;
11715 if (GET_CODE (dest
) == SUBREG
)
11716 dest
= SUBREG_REG (dest
);
11718 if (GET_CODE (dest
) == REG
)
11720 /* If we are setting the whole register, we know its value. Otherwise
11721 show that we don't know the value. We can handle SUBREG in
11723 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11724 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11725 else if (GET_CODE (setter
) == SET
11726 && GET_CODE (SET_DEST (setter
)) == SUBREG
11727 && SUBREG_REG (SET_DEST (setter
)) == dest
11728 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11729 && subreg_lowpart_p (SET_DEST (setter
)))
11730 record_value_for_reg (dest
, record_dead_insn
,
11731 gen_lowpart_for_combine (GET_MODE (dest
),
11732 SET_SRC (setter
)));
11734 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11736 else if (GET_CODE (dest
) == MEM
11737 /* Ignore pushes, they clobber nothing. */
11738 && ! push_operand (dest
, GET_MODE (dest
)))
11739 mem_last_set
= INSN_CUID (record_dead_insn
);
11742 /* Update the records of when each REG was most recently set or killed
11743 for the things done by INSN. This is the last thing done in processing
11744 INSN in the combiner loop.
11746 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11747 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11748 and also the similar information mem_last_set (which insn most recently
11749 modified memory) and last_call_cuid (which insn was the most recent
11750 subroutine call). */
11753 record_dead_and_set_regs (insn
)
11759 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11761 if (REG_NOTE_KIND (link
) == REG_DEAD
11762 && GET_CODE (XEXP (link
, 0)) == REG
)
11764 unsigned int regno
= REGNO (XEXP (link
, 0));
11765 unsigned int endregno
11766 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11767 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11770 for (i
= regno
; i
< endregno
; i
++)
11771 reg_last_death
[i
] = insn
;
11773 else if (REG_NOTE_KIND (link
) == REG_INC
)
11774 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11777 if (GET_CODE (insn
) == CALL_INSN
)
11779 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11780 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11782 reg_last_set_value
[i
] = 0;
11783 reg_last_set_mode
[i
] = 0;
11784 reg_last_set_nonzero_bits
[i
] = 0;
11785 reg_last_set_sign_bit_copies
[i
] = 0;
11786 reg_last_death
[i
] = 0;
11789 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11791 /* Don't bother recording what this insn does. It might set the
11792 return value register, but we can't combine into a call
11793 pattern anyway, so there's no point trying (and it may cause
11794 a crash, if e.g. we wind up asking for last_set_value of a
11795 SUBREG of the return value register). */
11799 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11802 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11803 register present in the SUBREG, so for each such SUBREG go back and
11804 adjust nonzero and sign bit information of the registers that are
11805 known to have some zero/sign bits set.
11807 This is needed because when combine blows the SUBREGs away, the
11808 information on zero/sign bits is lost and further combines can be
11809 missed because of that. */
11812 record_promoted_value (insn
, subreg
)
11817 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11818 enum machine_mode mode
= GET_MODE (subreg
);
11820 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11823 for (links
= LOG_LINKS (insn
); links
;)
11825 insn
= XEXP (links
, 0);
11826 set
= single_set (insn
);
11828 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11829 || REGNO (SET_DEST (set
)) != regno
11830 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11832 links
= XEXP (links
, 1);
11836 if (reg_last_set
[regno
] == insn
)
11838 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11839 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11842 if (GET_CODE (SET_SRC (set
)) == REG
)
11844 regno
= REGNO (SET_SRC (set
));
11845 links
= LOG_LINKS (insn
);
11852 /* Scan X for promoted SUBREGs. For each one found,
11853 note what it implies to the registers used in it. */
11856 check_promoted_subreg (insn
, x
)
11860 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11861 && GET_CODE (SUBREG_REG (x
)) == REG
)
11862 record_promoted_value (insn
, x
);
11865 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11868 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11872 check_promoted_subreg (insn
, XEXP (x
, i
));
11876 if (XVEC (x
, i
) != 0)
11877 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11878 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11884 /* Utility routine for the following function. Verify that all the registers
11885 mentioned in *LOC are valid when *LOC was part of a value set when
11886 label_tick == TICK. Return 0 if some are not.
11888 If REPLACE is nonzero, replace the invalid reference with
11889 (clobber (const_int 0)) and return 1. This replacement is useful because
11890 we often can get useful information about the form of a value (e.g., if
11891 it was produced by a shift that always produces -1 or 0) even though
11892 we don't know exactly what registers it was produced from. */
11895 get_last_value_validate (loc
, insn
, tick
, replace
)
11902 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11903 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11906 if (GET_CODE (x
) == REG
)
11908 unsigned int regno
= REGNO (x
);
11909 unsigned int endregno
11910 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11911 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11914 for (j
= regno
; j
< endregno
; j
++)
11915 if (reg_last_set_invalid
[j
]
11916 /* If this is a pseudo-register that was only set once and not
11917 live at the beginning of the function, it is always valid. */
11918 || (! (regno
>= FIRST_PSEUDO_REGISTER
11919 && REG_N_SETS (regno
) == 1
11920 && (! REGNO_REG_SET_P
11921 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11922 && reg_last_set_label
[j
] > tick
))
11925 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11931 /* If this is a memory reference, make sure that there were
11932 no stores after it that might have clobbered the value. We don't
11933 have alias info, so we assume any store invalidates it. */
11934 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11935 && INSN_CUID (insn
) <= mem_last_set
)
11938 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11942 for (i
= 0; i
< len
; i
++)
11946 /* Check for identical subexpressions. If x contains
11947 identical subexpression we only have to traverse one of
11950 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11951 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11953 /* Note that at this point x0 has already been checked
11954 and found valid. */
11955 rtx x0
= XEXP (x
, 0);
11956 rtx x1
= XEXP (x
, 1);
11958 /* If x0 and x1 are identical then x is also valid. */
11962 /* If x1 is identical to a subexpression of x0 then
11963 while checking x0, x1 has already been checked. Thus
11964 it is valid and so as x. */
11965 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11966 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11967 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11970 /* If x0 is identical to a subexpression of x1 then x is
11971 valid iff the rest of x1 is valid. */
11972 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11973 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11974 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11976 get_last_value_validate (&XEXP (x1
,
11977 x0
== XEXP (x1
, 0) ? 1 : 0),
11978 insn
, tick
, replace
);
11981 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11985 /* Don't bother with these. They shouldn't occur anyway. */
11986 else if (fmt
[i
] == 'E')
11990 /* If we haven't found a reason for it to be invalid, it is valid. */
11994 /* Get the last value assigned to X, if known. Some registers
11995 in the value may be replaced with (clobber (const_int 0)) if their value
11996 is known longer known reliably. */
12002 unsigned int regno
;
12005 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12006 then convert it to the desired mode. If this is a paradoxical SUBREG,
12007 we cannot predict what values the "extra" bits might have. */
12008 if (GET_CODE (x
) == SUBREG
12009 && subreg_lowpart_p (x
)
12010 && (GET_MODE_SIZE (GET_MODE (x
))
12011 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
12012 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12013 return gen_lowpart_for_combine (GET_MODE (x
), value
);
12015 if (GET_CODE (x
) != REG
)
12019 value
= reg_last_set_value
[regno
];
12021 /* If we don't have a value, or if it isn't for this basic block and
12022 it's either a hard register, set more than once, or it's a live
12023 at the beginning of the function, return 0.
12025 Because if it's not live at the beginning of the function then the reg
12026 is always set before being used (is never used without being set).
12027 And, if it's set only once, and it's always set before use, then all
12028 uses must have the same last value, even if it's not from this basic
12032 || (reg_last_set_label
[regno
] != label_tick
12033 && (regno
< FIRST_PSEUDO_REGISTER
12034 || REG_N_SETS (regno
) != 1
12035 || (REGNO_REG_SET_P
12036 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
12039 /* If the value was set in a later insn than the ones we are processing,
12040 we can't use it even if the register was only set once. */
12041 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
12044 /* If the value has all its registers valid, return it. */
12045 if (get_last_value_validate (&value
, reg_last_set
[regno
],
12046 reg_last_set_label
[regno
], 0))
12049 /* Otherwise, make a copy and replace any invalid register with
12050 (clobber (const_int 0)). If that fails for some reason, return 0. */
12052 value
= copy_rtx (value
);
12053 if (get_last_value_validate (&value
, reg_last_set
[regno
],
12054 reg_last_set_label
[regno
], 1))
12060 /* Return nonzero if expression X refers to a REG or to memory
12061 that is set in an instruction more recent than FROM_CUID. */
12064 use_crosses_set_p (x
, from_cuid
)
12070 enum rtx_code code
= GET_CODE (x
);
12074 unsigned int regno
= REGNO (x
);
12075 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
12076 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
12078 #ifdef PUSH_ROUNDING
12079 /* Don't allow uses of the stack pointer to be moved,
12080 because we don't know whether the move crosses a push insn. */
12081 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12084 for (; regno
< endreg
; regno
++)
12085 if (reg_last_set
[regno
]
12086 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
12091 if (code
== MEM
&& mem_last_set
> from_cuid
)
12094 fmt
= GET_RTX_FORMAT (code
);
12096 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12101 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12102 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
12105 else if (fmt
[i
] == 'e'
12106 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
12112 /* Define three variables used for communication between the following
12115 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12116 static int reg_dead_flag
;
12118 /* Function called via note_stores from reg_dead_at_p.
12120 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12121 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12124 reg_dead_at_p_1 (dest
, x
, data
)
12127 void *data ATTRIBUTE_UNUSED
;
12129 unsigned int regno
, endregno
;
12131 if (GET_CODE (dest
) != REG
)
12134 regno
= REGNO (dest
);
12135 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
12136 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
12138 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12139 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12142 /* Return nonzero if REG is known to be dead at INSN.
12144 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12145 referencing REG, it is dead. If we hit a SET referencing REG, it is
12146 live. Otherwise, see if it is live or dead at the start of the basic
12147 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12148 must be assumed to be always live. */
12151 reg_dead_at_p (reg
, insn
)
12158 /* Set variables for reg_dead_at_p_1. */
12159 reg_dead_regno
= REGNO (reg
);
12160 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
12161 ? HARD_REGNO_NREGS (reg_dead_regno
,
12167 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
12168 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12170 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12171 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12175 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12176 beginning of function. */
12177 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
12178 insn
= prev_nonnote_insn (insn
))
12180 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12182 return reg_dead_flag
== 1 ? 1 : 0;
12184 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12188 /* Get the basic block that we were in. */
12190 block
= ENTRY_BLOCK_PTR
->next_bb
;
12193 FOR_EACH_BB (block
)
12194 if (insn
== block
->head
)
12197 if (block
== EXIT_BLOCK_PTR
)
12201 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12202 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
12208 /* Note hard registers in X that are used. This code is similar to
12209 that in flow.c, but much simpler since we don't care about pseudos. */
12212 mark_used_regs_combine (x
)
12215 RTX_CODE code
= GET_CODE (x
);
12216 unsigned int regno
;
12229 case ADDR_DIFF_VEC
:
12232 /* CC0 must die in the insn after it is set, so we don't need to take
12233 special note of it here. */
12239 /* If we are clobbering a MEM, mark any hard registers inside the
12240 address as used. */
12241 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12242 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12247 /* A hard reg in a wide mode may really be multiple registers.
12248 If so, mark all of them just like the first. */
12249 if (regno
< FIRST_PSEUDO_REGISTER
)
12251 unsigned int endregno
, r
;
12253 /* None of this applies to the stack, frame or arg pointers. */
12254 if (regno
== STACK_POINTER_REGNUM
12255 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12256 || regno
== HARD_FRAME_POINTER_REGNUM
12258 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12259 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12261 || regno
== FRAME_POINTER_REGNUM
)
12264 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12265 for (r
= regno
; r
< endregno
; r
++)
12266 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12272 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12274 rtx testreg
= SET_DEST (x
);
12276 while (GET_CODE (testreg
) == SUBREG
12277 || GET_CODE (testreg
) == ZERO_EXTRACT
12278 || GET_CODE (testreg
) == SIGN_EXTRACT
12279 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12280 testreg
= XEXP (testreg
, 0);
12282 if (GET_CODE (testreg
) == MEM
)
12283 mark_used_regs_combine (XEXP (testreg
, 0));
12285 mark_used_regs_combine (SET_SRC (x
));
12293 /* Recursively scan the operands of this expression. */
12296 const char *fmt
= GET_RTX_FORMAT (code
);
12298 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12301 mark_used_regs_combine (XEXP (x
, i
));
12302 else if (fmt
[i
] == 'E')
12306 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12307 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12313 /* Remove register number REGNO from the dead registers list of INSN.
12315 Return the note used to record the death, if there was one. */
12318 remove_death (regno
, insn
)
12319 unsigned int regno
;
12322 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12326 REG_N_DEATHS (regno
)--;
12327 remove_note (insn
, note
);
12333 /* For each register (hardware or pseudo) used within expression X, if its
12334 death is in an instruction with cuid between FROM_CUID (inclusive) and
12335 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12336 list headed by PNOTES.
12338 That said, don't move registers killed by maybe_kill_insn.
12340 This is done when X is being merged by combination into TO_INSN. These
12341 notes will then be distributed as needed. */
12344 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
12346 rtx maybe_kill_insn
;
12353 enum rtx_code code
= GET_CODE (x
);
12357 unsigned int regno
= REGNO (x
);
12358 rtx where_dead
= reg_last_death
[regno
];
12359 rtx before_dead
, after_dead
;
12361 /* Don't move the register if it gets killed in between from and to. */
12362 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12363 && ! reg_referenced_p (x
, maybe_kill_insn
))
12366 /* WHERE_DEAD could be a USE insn made by combine, so first we
12367 make sure that we have insns with valid INSN_CUID values. */
12368 before_dead
= where_dead
;
12369 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12370 before_dead
= PREV_INSN (before_dead
);
12372 after_dead
= where_dead
;
12373 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12374 after_dead
= NEXT_INSN (after_dead
);
12376 if (before_dead
&& after_dead
12377 && INSN_CUID (before_dead
) >= from_cuid
12378 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12379 || (where_dead
!= after_dead
12380 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12382 rtx note
= remove_death (regno
, where_dead
);
12384 /* It is possible for the call above to return 0. This can occur
12385 when reg_last_death points to I2 or I1 that we combined with.
12386 In that case make a new note.
12388 We must also check for the case where X is a hard register
12389 and NOTE is a death note for a range of hard registers
12390 including X. In that case, we must put REG_DEAD notes for
12391 the remaining registers in place of NOTE. */
12393 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12394 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12395 > GET_MODE_SIZE (GET_MODE (x
))))
12397 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12398 unsigned int deadend
12399 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12400 GET_MODE (XEXP (note
, 0))));
12401 unsigned int ourend
12402 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12405 for (i
= deadregno
; i
< deadend
; i
++)
12406 if (i
< regno
|| i
>= ourend
)
12407 REG_NOTES (where_dead
)
12408 = gen_rtx_EXPR_LIST (REG_DEAD
,
12410 REG_NOTES (where_dead
));
12413 /* If we didn't find any note, or if we found a REG_DEAD note that
12414 covers only part of the given reg, and we have a multi-reg hard
12415 register, then to be safe we must check for REG_DEAD notes
12416 for each register other than the first. They could have
12417 their own REG_DEAD notes lying around. */
12418 else if ((note
== 0
12420 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12421 < GET_MODE_SIZE (GET_MODE (x
)))))
12422 && regno
< FIRST_PSEUDO_REGISTER
12423 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12425 unsigned int ourend
12426 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12427 unsigned int i
, offset
;
12431 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12435 for (i
= regno
+ offset
; i
< ourend
; i
++)
12436 move_deaths (regno_reg_rtx
[i
],
12437 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12440 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12442 XEXP (note
, 1) = *pnotes
;
12446 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12448 REG_N_DEATHS (regno
)++;
12454 else if (GET_CODE (x
) == SET
)
12456 rtx dest
= SET_DEST (x
);
12458 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12460 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12461 that accesses one word of a multi-word item, some
12462 piece of everything register in the expression is used by
12463 this insn, so remove any old death. */
12464 /* ??? So why do we test for equality of the sizes? */
12466 if (GET_CODE (dest
) == ZERO_EXTRACT
12467 || GET_CODE (dest
) == STRICT_LOW_PART
12468 || (GET_CODE (dest
) == SUBREG
12469 && (((GET_MODE_SIZE (GET_MODE (dest
))
12470 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12471 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12472 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12474 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12478 /* If this is some other SUBREG, we know it replaces the entire
12479 value, so use that as the destination. */
12480 if (GET_CODE (dest
) == SUBREG
)
12481 dest
= SUBREG_REG (dest
);
12483 /* If this is a MEM, adjust deaths of anything used in the address.
12484 For a REG (the only other possibility), the entire value is
12485 being replaced so the old value is not used in this insn. */
12487 if (GET_CODE (dest
) == MEM
)
12488 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12493 else if (GET_CODE (x
) == CLOBBER
)
12496 len
= GET_RTX_LENGTH (code
);
12497 fmt
= GET_RTX_FORMAT (code
);
12499 for (i
= 0; i
< len
; i
++)
12504 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12505 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12508 else if (fmt
[i
] == 'e')
12509 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12513 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12514 pattern of an insn. X must be a REG. */
12517 reg_bitfield_target_p (x
, body
)
12523 if (GET_CODE (body
) == SET
)
12525 rtx dest
= SET_DEST (body
);
12527 unsigned int regno
, tregno
, endregno
, endtregno
;
12529 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12530 target
= XEXP (dest
, 0);
12531 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12532 target
= SUBREG_REG (XEXP (dest
, 0));
12536 if (GET_CODE (target
) == SUBREG
)
12537 target
= SUBREG_REG (target
);
12539 if (GET_CODE (target
) != REG
)
12542 tregno
= REGNO (target
), regno
= REGNO (x
);
12543 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12544 return target
== x
;
12546 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12547 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12549 return endregno
> tregno
&& regno
< endtregno
;
12552 else if (GET_CODE (body
) == PARALLEL
)
12553 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12554 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12560 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12561 as appropriate. I3 and I2 are the insns resulting from the combination
12562 insns including FROM (I2 may be zero).
12564 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12565 not need REG_DEAD notes because they are being substituted for. This
12566 saves searching in the most common cases.
12568 Each note in the list is either ignored or placed on some insns, depending
12569 on the type of note. */
12572 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
12576 rtx elim_i2
, elim_i1
;
12578 rtx note
, next_note
;
12581 for (note
= notes
; note
; note
= next_note
)
12583 rtx place
= 0, place2
= 0;
12585 /* If this NOTE references a pseudo register, ensure it references
12586 the latest copy of that register. */
12587 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12588 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12589 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12591 next_note
= XEXP (note
, 1);
12592 switch (REG_NOTE_KIND (note
))
12596 /* Doesn't matter much where we put this, as long as it's somewhere.
12597 It is preferable to keep these notes on branches, which is most
12598 likely to be i3. */
12602 case REG_VTABLE_REF
:
12603 /* ??? Should remain with *a particular* memory load. Given the
12604 nature of vtable data, the last insn seems relatively safe. */
12608 case REG_NON_LOCAL_GOTO
:
12609 if (GET_CODE (i3
) == JUMP_INSN
)
12611 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12617 case REG_EH_REGION
:
12618 /* These notes must remain with the call or trapping instruction. */
12619 if (GET_CODE (i3
) == CALL_INSN
)
12621 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12623 else if (flag_non_call_exceptions
)
12625 if (may_trap_p (i3
))
12627 else if (i2
&& may_trap_p (i2
))
12629 /* ??? Otherwise assume we've combined things such that we
12630 can now prove that the instructions can't trap. Drop the
12631 note in this case. */
12639 /* These notes must remain with the call. It should not be
12640 possible for both I2 and I3 to be a call. */
12641 if (GET_CODE (i3
) == CALL_INSN
)
12643 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12650 /* Any clobbers for i3 may still exist, and so we must process
12651 REG_UNUSED notes from that insn.
12653 Any clobbers from i2 or i1 can only exist if they were added by
12654 recog_for_combine. In that case, recog_for_combine created the
12655 necessary REG_UNUSED notes. Trying to keep any original
12656 REG_UNUSED notes from these insns can cause incorrect output
12657 if it is for the same register as the original i3 dest.
12658 In that case, we will notice that the register is set in i3,
12659 and then add a REG_UNUSED note for the destination of i3, which
12660 is wrong. However, it is possible to have REG_UNUSED notes from
12661 i2 or i1 for register which were both used and clobbered, so
12662 we keep notes from i2 or i1 if they will turn into REG_DEAD
12665 /* If this register is set or clobbered in I3, put the note there
12666 unless there is one already. */
12667 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12669 if (from_insn
!= i3
)
12672 if (! (GET_CODE (XEXP (note
, 0)) == REG
12673 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12674 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12677 /* Otherwise, if this register is used by I3, then this register
12678 now dies here, so we must put a REG_DEAD note here unless there
12680 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12681 && ! (GET_CODE (XEXP (note
, 0)) == REG
12682 ? find_regno_note (i3
, REG_DEAD
,
12683 REGNO (XEXP (note
, 0)))
12684 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12686 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12694 /* These notes say something about results of an insn. We can
12695 only support them if they used to be on I3 in which case they
12696 remain on I3. Otherwise they are ignored.
12698 If the note refers to an expression that is not a constant, we
12699 must also ignore the note since we cannot tell whether the
12700 equivalence is still true. It might be possible to do
12701 slightly better than this (we only have a problem if I2DEST
12702 or I1DEST is present in the expression), but it doesn't
12703 seem worth the trouble. */
12705 if (from_insn
== i3
12706 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12711 case REG_NO_CONFLICT
:
12712 /* These notes say something about how a register is used. They must
12713 be present on any use of the register in I2 or I3. */
12714 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12717 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12727 /* This can show up in several ways -- either directly in the
12728 pattern, or hidden off in the constant pool with (or without?)
12729 a REG_EQUAL note. */
12730 /* ??? Ignore the without-reg_equal-note problem for now. */
12731 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12732 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12733 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12734 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12738 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12739 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12740 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12741 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12749 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12750 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12751 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12753 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12755 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12756 LABEL_NUSES (JUMP_LABEL (place
))--;
12759 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12761 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12763 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12764 LABEL_NUSES (JUMP_LABEL (place2
))--;
12771 /* These notes say something about the value of a register prior
12772 to the execution of an insn. It is too much trouble to see
12773 if the note is still correct in all situations. It is better
12774 to simply delete it. */
12778 /* If the insn previously containing this note still exists,
12779 put it back where it was. Otherwise move it to the previous
12780 insn. Adjust the corresponding REG_LIBCALL note. */
12781 if (GET_CODE (from_insn
) != NOTE
)
12785 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12786 place
= prev_real_insn (from_insn
);
12788 XEXP (tem
, 0) = place
;
12789 /* If we're deleting the last remaining instruction of a
12790 libcall sequence, don't add the notes. */
12791 else if (XEXP (note
, 0) == from_insn
)
12797 /* This is handled similarly to REG_RETVAL. */
12798 if (GET_CODE (from_insn
) != NOTE
)
12802 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12803 place
= next_real_insn (from_insn
);
12805 XEXP (tem
, 0) = place
;
12806 /* If we're deleting the last remaining instruction of a
12807 libcall sequence, don't add the notes. */
12808 else if (XEXP (note
, 0) == from_insn
)
12814 /* If the register is used as an input in I3, it dies there.
12815 Similarly for I2, if it is nonzero and adjacent to I3.
12817 If the register is not used as an input in either I3 or I2
12818 and it is not one of the registers we were supposed to eliminate,
12819 there are two possibilities. We might have a non-adjacent I2
12820 or we might have somehow eliminated an additional register
12821 from a computation. For example, we might have had A & B where
12822 we discover that B will always be zero. In this case we will
12823 eliminate the reference to A.
12825 In both cases, we must search to see if we can find a previous
12826 use of A and put the death note there. */
12829 && GET_CODE (from_insn
) == CALL_INSN
12830 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12832 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12834 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12835 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12838 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12839 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12844 basic_block bb
= this_basic_block
;
12846 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12848 if (! INSN_P (tem
))
12850 if (tem
== bb
->head
)
12855 /* If the register is being set at TEM, see if that is all
12856 TEM is doing. If so, delete TEM. Otherwise, make this
12857 into a REG_UNUSED note instead. */
12858 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12860 rtx set
= single_set (tem
);
12861 rtx inner_dest
= 0;
12863 rtx cc0_setter
= NULL_RTX
;
12867 for (inner_dest
= SET_DEST (set
);
12868 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12869 || GET_CODE (inner_dest
) == SUBREG
12870 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12871 inner_dest
= XEXP (inner_dest
, 0))
12874 /* Verify that it was the set, and not a clobber that
12875 modified the register.
12877 CC0 targets must be careful to maintain setter/user
12878 pairs. If we cannot delete the setter due to side
12879 effects, mark the user with an UNUSED note instead
12882 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12883 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12885 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12886 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12887 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12891 /* Move the notes and links of TEM elsewhere.
12892 This might delete other dead insns recursively.
12893 First set the pattern to something that won't use
12896 PATTERN (tem
) = pc_rtx
;
12898 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12899 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12900 distribute_links (LOG_LINKS (tem
));
12902 PUT_CODE (tem
, NOTE
);
12903 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12904 NOTE_SOURCE_FILE (tem
) = 0;
12907 /* Delete the setter too. */
12910 PATTERN (cc0_setter
) = pc_rtx
;
12912 distribute_notes (REG_NOTES (cc0_setter
),
12913 cc0_setter
, cc0_setter
,
12914 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12915 distribute_links (LOG_LINKS (cc0_setter
));
12917 PUT_CODE (cc0_setter
, NOTE
);
12918 NOTE_LINE_NUMBER (cc0_setter
)
12919 = NOTE_INSN_DELETED
;
12920 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12924 /* If the register is both set and used here, put the
12925 REG_DEAD note here, but place a REG_UNUSED note
12926 here too unless there already is one. */
12927 else if (reg_referenced_p (XEXP (note
, 0),
12932 if (! find_regno_note (tem
, REG_UNUSED
,
12933 REGNO (XEXP (note
, 0))))
12935 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12940 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12942 /* If there isn't already a REG_UNUSED note, put one
12944 if (! find_regno_note (tem
, REG_UNUSED
,
12945 REGNO (XEXP (note
, 0))))
12950 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12951 || (GET_CODE (tem
) == CALL_INSN
12952 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12956 /* If we are doing a 3->2 combination, and we have a
12957 register which formerly died in i3 and was not used
12958 by i2, which now no longer dies in i3 and is used in
12959 i2 but does not die in i2, and place is between i2
12960 and i3, then we may need to move a link from place to
12962 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12963 && INSN_CUID (place
) > INSN_CUID (i2
)
12965 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12966 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12968 rtx links
= LOG_LINKS (place
);
12969 LOG_LINKS (place
) = 0;
12970 distribute_links (links
);
12975 if (tem
== bb
->head
)
12979 /* We haven't found an insn for the death note and it
12980 is still a REG_DEAD note, but we have hit the beginning
12981 of the block. If the existing life info says the reg
12982 was dead, there's nothing left to do. Otherwise, we'll
12983 need to do a global life update after combine. */
12984 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12985 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12986 REGNO (XEXP (note
, 0))))
12987 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12990 /* If the register is set or already dead at PLACE, we needn't do
12991 anything with this note if it is still a REG_DEAD note.
12992 We can here if it is set at all, not if is it totally replace,
12993 which is what `dead_or_set_p' checks, so also check for it being
12996 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12998 unsigned int regno
= REGNO (XEXP (note
, 0));
13000 /* Similarly, if the instruction on which we want to place
13001 the note is a noop, we'll need do a global live update
13002 after we remove them in delete_noop_moves. */
13003 if (noop_move_p (place
))
13004 SET_BIT (refresh_blocks
, this_basic_block
->index
);
13006 if (dead_or_set_p (place
, XEXP (note
, 0))
13007 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13009 /* Unless the register previously died in PLACE, clear
13010 reg_last_death. [I no longer understand why this is
13012 if (reg_last_death
[regno
] != place
)
13013 reg_last_death
[regno
] = 0;
13017 reg_last_death
[regno
] = place
;
13019 /* If this is a death note for a hard reg that is occupying
13020 multiple registers, ensure that we are still using all
13021 parts of the object. If we find a piece of the object
13022 that is unused, we must arrange for an appropriate REG_DEAD
13023 note to be added for it. However, we can't just emit a USE
13024 and tag the note to it, since the register might actually
13025 be dead; so we recourse, and the recursive call then finds
13026 the previous insn that used this register. */
13028 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13029 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
13031 unsigned int endregno
13032 = regno
+ HARD_REGNO_NREGS (regno
,
13033 GET_MODE (XEXP (note
, 0)));
13037 for (i
= regno
; i
< endregno
; i
++)
13038 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13039 && ! find_regno_fusage (place
, USE
, i
))
13040 || dead_or_set_regno_p (place
, i
))
13045 /* Put only REG_DEAD notes for pieces that are
13046 not already dead or set. */
13048 for (i
= regno
; i
< endregno
;
13049 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
13051 rtx piece
= regno_reg_rtx
[i
];
13052 basic_block bb
= this_basic_block
;
13054 if (! dead_or_set_p (place
, piece
)
13055 && ! reg_bitfield_target_p (piece
,
13059 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
13061 distribute_notes (new_note
, place
, place
,
13062 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13064 else if (! refers_to_regno_p (i
, i
+ 1,
13065 PATTERN (place
), 0)
13066 && ! find_regno_fusage (place
, USE
, i
))
13067 for (tem
= PREV_INSN (place
); ;
13068 tem
= PREV_INSN (tem
))
13070 if (! INSN_P (tem
))
13072 if (tem
== bb
->head
)
13074 SET_BIT (refresh_blocks
,
13075 this_basic_block
->index
);
13080 if (dead_or_set_p (tem
, piece
)
13081 || reg_bitfield_target_p (piece
,
13085 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
13100 /* Any other notes should not be present at this point in the
13107 XEXP (note
, 1) = REG_NOTES (place
);
13108 REG_NOTES (place
) = note
;
13110 else if ((REG_NOTE_KIND (note
) == REG_DEAD
13111 || REG_NOTE_KIND (note
) == REG_UNUSED
)
13112 && GET_CODE (XEXP (note
, 0)) == REG
)
13113 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
13117 if ((REG_NOTE_KIND (note
) == REG_DEAD
13118 || REG_NOTE_KIND (note
) == REG_UNUSED
)
13119 && GET_CODE (XEXP (note
, 0)) == REG
)
13120 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
13122 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
13123 REG_NOTE_KIND (note
),
13125 REG_NOTES (place2
));
13130 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13131 I3, I2, and I1 to new locations. This is also called in one case to
13132 add a link pointing at I3 when I3's destination is changed. */
13135 distribute_links (links
)
13138 rtx link
, next_link
;
13140 for (link
= links
; link
; link
= next_link
)
13146 next_link
= XEXP (link
, 1);
13148 /* If the insn that this link points to is a NOTE or isn't a single
13149 set, ignore it. In the latter case, it isn't clear what we
13150 can do other than ignore the link, since we can't tell which
13151 register it was for. Such links wouldn't be used by combine
13154 It is not possible for the destination of the target of the link to
13155 have been changed by combine. The only potential of this is if we
13156 replace I3, I2, and I1 by I3 and I2. But in that case the
13157 destination of I2 also remains unchanged. */
13159 if (GET_CODE (XEXP (link
, 0)) == NOTE
13160 || (set
= single_set (XEXP (link
, 0))) == 0)
13163 reg
= SET_DEST (set
);
13164 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13165 || GET_CODE (reg
) == SIGN_EXTRACT
13166 || GET_CODE (reg
) == STRICT_LOW_PART
)
13167 reg
= XEXP (reg
, 0);
13169 /* A LOG_LINK is defined as being placed on the first insn that uses
13170 a register and points to the insn that sets the register. Start
13171 searching at the next insn after the target of the link and stop
13172 when we reach a set of the register or the end of the basic block.
13174 Note that this correctly handles the link that used to point from
13175 I3 to I2. Also note that not much searching is typically done here
13176 since most links don't point very far away. */
13178 for (insn
= NEXT_INSN (XEXP (link
, 0));
13179 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13180 || this_basic_block
->next_bb
->head
!= insn
));
13181 insn
= NEXT_INSN (insn
))
13182 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13184 if (reg_referenced_p (reg
, PATTERN (insn
)))
13188 else if (GET_CODE (insn
) == CALL_INSN
13189 && find_reg_fusage (insn
, USE
, reg
))
13195 /* If we found a place to put the link, place it there unless there
13196 is already a link to the same insn as LINK at that point. */
13202 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13203 if (XEXP (link2
, 0) == XEXP (link
, 0))
13208 XEXP (link
, 1) = LOG_LINKS (place
);
13209 LOG_LINKS (place
) = link
;
13211 /* Set added_links_insn to the earliest insn we added a
13213 if (added_links_insn
== 0
13214 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
13215 added_links_insn
= place
;
13221 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13227 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13228 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13229 insn
= NEXT_INSN (insn
);
13231 if (INSN_UID (insn
) > max_uid_cuid
)
13234 return INSN_CUID (insn
);
13238 dump_combine_stats (file
)
13243 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13244 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13248 dump_combine_total_stats (file
)
13253 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13254 total_attempts
, total_merges
, total_extras
, total_successes
);