1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx
*reg_last_death
;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx
*reg_last_set
;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set
;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid
;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn
;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn
;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid
;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs
;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn
;
195 /* Basic block in which we are performing combines. */
196 static basic_block this_basic_block
;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks
;
202 static int need_refresh
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; int i
;} old_contents
;
318 union {rtx
*r
; int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST
PARAMS ((rtx
*, rtx
));
342 static void do_SUBST_INT
PARAMS ((int *, int));
343 static void init_reg_last_arrays
PARAMS ((void));
344 static void setup_incoming_promotions
PARAMS ((void));
345 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
346 static int cant_combine_insn_p
PARAMS ((rtx
));
347 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
348 static int sets_function_arg_p
PARAMS ((rtx
));
349 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
350 static int contains_muldiv
PARAMS ((rtx
));
351 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
352 static void undo_all
PARAMS ((void));
353 static void undo_commit
PARAMS ((void));
354 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
355 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
356 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
357 static rtx simplify_if_then_else
PARAMS ((rtx
));
358 static rtx simplify_set
PARAMS ((rtx
));
359 static rtx simplify_logical
PARAMS ((rtx
, int));
360 static rtx expand_compound_operation
PARAMS ((rtx
));
361 static rtx expand_field_assignment
PARAMS ((rtx
));
362 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
363 rtx
, unsigned HOST_WIDE_INT
, int,
365 static rtx extract_left_shift
PARAMS ((rtx
, int));
366 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
367 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
368 unsigned HOST_WIDE_INT
*));
369 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
370 unsigned HOST_WIDE_INT
, rtx
, int));
371 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
372 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
373 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
374 static rtx make_field_assignment
PARAMS ((rtx
));
375 static rtx apply_distributive_law
PARAMS ((rtx
));
376 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
377 unsigned HOST_WIDE_INT
));
378 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
379 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
380 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
381 enum rtx_code
, HOST_WIDE_INT
,
382 enum machine_mode
, int *));
383 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
385 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
386 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
387 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
389 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
390 static void update_table_tick
PARAMS ((rtx
));
391 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
392 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
393 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
394 static void record_dead_and_set_regs
PARAMS ((rtx
));
395 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
396 static rtx get_last_value
PARAMS ((rtx
));
397 static int use_crosses_set_p
PARAMS ((rtx
, int));
398 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
399 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
400 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
401 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
402 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
403 static void distribute_links
PARAMS ((rtx
));
404 static void mark_used_regs_combine
PARAMS ((rtx
));
405 static int insn_cuid
PARAMS ((rtx
));
406 static void record_promoted_value
PARAMS ((rtx
, rtx
));
407 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
408 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
410 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
411 insn. The substitution can be undone by undo_all. If INTO is already
412 set to NEWVAL, do not record this change. Because computing NEWVAL might
413 also call SUBST, we have to compute it before we put anything into
417 do_SUBST (into
, newval
)
423 if (oldval
== newval
)
426 /* We'd like to catch as many invalid transformations here as
427 possible. Unfortunately, there are way too many mode changes
428 that are perfectly valid, so we'd waste too much effort for
429 little gain doing the checks here. Focus on catching invalid
430 transformations involving integer constants. */
431 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
432 && GET_CODE (newval
) == CONST_INT
)
434 /* Sanity check that we're replacing oldval with a CONST_INT
435 that is a valid sign-extension for the original mode. */
436 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
440 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
441 CONST_INT is not valid, because after the replacement, the
442 original mode would be gone. Unfortunately, we can't tell
443 when do_SUBST is called to replace the operand thereof, so we
444 perform this test on oldval instead, checking whether an
445 invalid replacement took place before we got here. */
446 if ((GET_CODE (oldval
) == SUBREG
447 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
448 || (GET_CODE (oldval
) == ZERO_EXTEND
449 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
454 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
456 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
460 buf
->old_contents
.r
= oldval
;
463 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
466 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
468 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
469 for the value of a HOST_WIDE_INT value (including CONST_INT) is
473 do_SUBST_INT (into
, newval
)
479 if (oldval
== newval
)
483 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
485 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
489 buf
->old_contents
.i
= oldval
;
492 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
495 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
497 /* Main entry point for combiner. F is the first insn of the function.
498 NREGS is the first unused pseudo-reg number.
500 Return non-zero if the combiner has turned an indirect jump
501 instruction into a direct jump. */
503 combine_instructions (f
, nregs
)
512 rtx links
, nextlinks
;
514 int new_direct_jump_p
= 0;
516 combine_attempts
= 0;
519 combine_successes
= 0;
521 combine_max_regno
= nregs
;
523 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
524 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
526 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
528 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
530 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
531 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
532 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
533 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
535 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
536 reg_last_set_nonzero_bits
537 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
538 reg_last_set_sign_bit_copies
539 = (char *) xmalloc (nregs
* sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
548 if (INSN_UID (insn
) > i
)
551 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
554 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid
= 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 /* We need to initialize it here, because record_dead_and_set_regs may call
576 subst_prev_insn
= NULL_RTX
;
578 setup_incoming_promotions ();
580 refresh_blocks
= sbitmap_alloc (last_basic_block
);
581 sbitmap_zero (refresh_blocks
);
584 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
586 uid_cuid
[INSN_UID (insn
)] = ++i
;
592 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
594 record_dead_and_set_regs (insn
);
597 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
598 if (REG_NOTE_KIND (links
) == REG_INC
)
599 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
604 if (GET_CODE (insn
) == CODE_LABEL
)
608 nonzero_sign_valid
= 1;
610 /* Now scan all the insns in forward order. */
615 init_reg_last_arrays ();
616 setup_incoming_promotions ();
618 FOR_EACH_BB (this_basic_block
)
620 for (insn
= this_basic_block
->head
;
621 insn
!= NEXT_INSN (this_basic_block
->end
);
622 insn
= next
? next
: NEXT_INSN (insn
))
626 if (GET_CODE (insn
) == CODE_LABEL
)
629 else if (INSN_P (insn
))
631 /* See if we know about function return values before this
632 insn based upon SUBREG flags. */
633 check_promoted_subreg (insn
, PATTERN (insn
));
635 /* Try this insn with each insn it links back to. */
637 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
638 if ((next
= try_combine (insn
, XEXP (links
, 0),
639 NULL_RTX
, &new_direct_jump_p
)) != 0)
642 /* Try each sequence of three linked insns ending with this one. */
644 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
646 rtx link
= XEXP (links
, 0);
648 /* If the linked insn has been replaced by a note, then there
649 is no point in pursuing this chain any further. */
650 if (GET_CODE (link
) == NOTE
)
653 for (nextlinks
= LOG_LINKS (link
);
655 nextlinks
= XEXP (nextlinks
, 1))
656 if ((next
= try_combine (insn
, link
,
658 &new_direct_jump_p
)) != 0)
663 /* Try to combine a jump insn that uses CC0
664 with a preceding insn that sets CC0, and maybe with its
665 logical predecessor as well.
666 This is how we make decrement-and-branch insns.
667 We need this special code because data flow connections
668 via CC0 do not get entered in LOG_LINKS. */
670 if (GET_CODE (insn
) == JUMP_INSN
671 && (prev
= prev_nonnote_insn (insn
)) != 0
672 && GET_CODE (prev
) == INSN
673 && sets_cc0_p (PATTERN (prev
)))
675 if ((next
= try_combine (insn
, prev
,
676 NULL_RTX
, &new_direct_jump_p
)) != 0)
679 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
680 nextlinks
= XEXP (nextlinks
, 1))
681 if ((next
= try_combine (insn
, prev
,
683 &new_direct_jump_p
)) != 0)
687 /* Do the same for an insn that explicitly references CC0. */
688 if (GET_CODE (insn
) == INSN
689 && (prev
= prev_nonnote_insn (insn
)) != 0
690 && GET_CODE (prev
) == INSN
691 && sets_cc0_p (PATTERN (prev
))
692 && GET_CODE (PATTERN (insn
)) == SET
693 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
695 if ((next
= try_combine (insn
, prev
,
696 NULL_RTX
, &new_direct_jump_p
)) != 0)
699 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
700 nextlinks
= XEXP (nextlinks
, 1))
701 if ((next
= try_combine (insn
, prev
,
703 &new_direct_jump_p
)) != 0)
707 /* Finally, see if any of the insns that this insn links to
708 explicitly references CC0. If so, try this insn, that insn,
709 and its predecessor if it sets CC0. */
710 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
711 if (GET_CODE (XEXP (links
, 0)) == INSN
712 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
713 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
714 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
715 && GET_CODE (prev
) == INSN
716 && sets_cc0_p (PATTERN (prev
))
717 && (next
= try_combine (insn
, XEXP (links
, 0),
718 prev
, &new_direct_jump_p
)) != 0)
722 /* Try combining an insn with two different insns whose results it
724 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
725 for (nextlinks
= XEXP (links
, 1); nextlinks
;
726 nextlinks
= XEXP (nextlinks
, 1))
727 if ((next
= try_combine (insn
, XEXP (links
, 0),
729 &new_direct_jump_p
)) != 0)
732 if (GET_CODE (insn
) != NOTE
)
733 record_dead_and_set_regs (insn
);
742 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
743 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
744 new_direct_jump_p
|= purge_all_dead_edges (0);
745 delete_noop_moves (f
);
747 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
748 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
749 | PROP_KILL_DEAD_CODE
);
752 sbitmap_free (refresh_blocks
);
753 free (reg_nonzero_bits
);
754 free (reg_sign_bit_copies
);
755 free (reg_last_death
);
757 free (reg_last_set_value
);
758 free (reg_last_set_table_tick
);
759 free (reg_last_set_label
);
760 free (reg_last_set_invalid
);
761 free (reg_last_set_mode
);
762 free (reg_last_set_nonzero_bits
);
763 free (reg_last_set_sign_bit_copies
);
767 struct undo
*undo
, *next
;
768 for (undo
= undobuf
.frees
; undo
; undo
= next
)
776 total_attempts
+= combine_attempts
;
777 total_merges
+= combine_merges
;
778 total_extras
+= combine_extras
;
779 total_successes
+= combine_successes
;
781 nonzero_sign_valid
= 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p
;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs
= combine_max_regno
;
796 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
797 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
798 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
799 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
800 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
801 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
802 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
803 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
804 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode
;
817 rtx first
= get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
827 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
830 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode
, const0_rtx
)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x
, set
, data
)
853 void *data ATTRIBUTE_UNUSED
;
857 if (GET_CODE (x
) == REG
858 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
862 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
864 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
866 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
867 reg_sign_bit_copies
[REGNO (x
)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set
= expand_field_assignment (set
);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set
) == x
879 || (GET_CODE (SET_DEST (set
)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
882 && SUBREG_REG (SET_DEST (set
)) == x
))
884 rtx src
= SET_SRC (set
);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
897 && GET_CODE (src
) == CONST_INT
899 && 0 != (INTVAL (src
)
901 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
902 src
= GEN_INT (INTVAL (src
)
903 | ((HOST_WIDE_INT
) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x
))));
907 /* Don't call nonzero_bits if it cannot change anything. */
908 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
909 reg_nonzero_bits
[REGNO (x
)]
910 |= nonzero_bits (src
, nonzero_bits_mode
);
911 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
912 if (reg_sign_bit_copies
[REGNO (x
)] == 0
913 || reg_sign_bit_copies
[REGNO (x
)] > num
)
914 reg_sign_bit_copies
[REGNO (x
)] = num
;
918 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
919 reg_sign_bit_copies
[REGNO (x
)] = 1;
924 /* See if INSN can be combined into I3. PRED and SUCC are optionally
925 insns that were previously combined into I3 or that will be combined
926 into the merger of INSN and I3.
928 Return 0 if the combination is not allowed for any reason.
930 If the combination is allowed, *PDEST will be set to the single
931 destination of INSN and *PSRC to the single source, and this function
935 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
938 rtx pred ATTRIBUTE_UNUSED
;
943 rtx set
= 0, src
, dest
;
948 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
949 && next_active_insn (succ
) == i3
)
950 : next_active_insn (insn
) == i3
);
952 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
953 or a PARALLEL consisting of such a SET and CLOBBERs.
955 If INSN has CLOBBER parallel parts, ignore them for our processing.
956 By definition, these happen during the execution of the insn. When it
957 is merged with another insn, all bets are off. If they are, in fact,
958 needed and aren't also supplied in I3, they may be added by
959 recog_for_combine. Otherwise, it won't match.
961 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
964 Get the source and destination of INSN. If more than one, can't
967 if (GET_CODE (PATTERN (insn
)) == SET
)
968 set
= PATTERN (insn
);
969 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
970 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
972 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
974 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
976 switch (GET_CODE (elt
))
978 /* This is important to combine floating point insns
981 /* Combining an isolated USE doesn't make sense.
982 We depend here on combinable_i3pat to reject them. */
983 /* The code below this loop only verifies that the inputs of
984 the SET in INSN do not change. We call reg_set_between_p
985 to verify that the REG in the USE does not change between
987 If the USE in INSN was for a pseudo register, the matching
988 insn pattern will likely match any register; combining this
989 with any other USE would only be safe if we knew that the
990 used registers have identical values, or if there was
991 something to tell them apart, e.g. different modes. For
992 now, we forgo such complicated tests and simply disallow
993 combining of USES of pseudo registers with any other USE. */
994 if (GET_CODE (XEXP (elt
, 0)) == REG
995 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
997 rtx i3pat
= PATTERN (i3
);
998 int i
= XVECLEN (i3pat
, 0) - 1;
999 unsigned int regno
= REGNO (XEXP (elt
, 0));
1003 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1005 if (GET_CODE (i3elt
) == USE
1006 && GET_CODE (XEXP (i3elt
, 0)) == REG
1007 && (REGNO (XEXP (i3elt
, 0)) == regno
1008 ? reg_set_between_p (XEXP (elt
, 0),
1009 PREV_INSN (insn
), i3
)
1010 : regno
>= FIRST_PSEUDO_REGISTER
))
1017 /* We can ignore CLOBBERs. */
1022 /* Ignore SETs whose result isn't used but not those that
1023 have side-effects. */
1024 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1025 && ! side_effects_p (elt
))
1028 /* If we have already found a SET, this is a second one and
1029 so we cannot combine with this insn. */
1037 /* Anything else means we can't combine. */
1043 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1044 so don't do anything with it. */
1045 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1054 set
= expand_field_assignment (set
);
1055 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1057 /* Don't eliminate a store in the stack pointer. */
1058 if (dest
== stack_pointer_rtx
1059 /* If we couldn't eliminate a field assignment, we can't combine. */
1060 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1061 /* Don't combine with an insn that sets a register to itself if it has
1062 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1063 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1064 /* Can't merge an ASM_OPERANDS. */
1065 || GET_CODE (src
) == ASM_OPERANDS
1066 /* Can't merge a function call. */
1067 || GET_CODE (src
) == CALL
1068 /* Don't eliminate a function call argument. */
1069 || (GET_CODE (i3
) == CALL_INSN
1070 && (find_reg_fusage (i3
, USE
, dest
)
1071 || (GET_CODE (dest
) == REG
1072 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1073 && global_regs
[REGNO (dest
)])))
1074 /* Don't substitute into an incremented register. */
1075 || FIND_REG_INC_NOTE (i3
, dest
)
1076 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1078 /* Don't combine the end of a libcall into anything. */
1079 /* ??? This gives worse code, and appears to be unnecessary, since no
1080 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1081 use REG_RETVAL notes for noconflict blocks, but other code here
1082 makes sure that those insns don't disappear. */
1083 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1085 /* Make sure that DEST is not used after SUCC but before I3. */
1086 || (succ
&& ! all_adjacent
1087 && reg_used_between_p (dest
, succ
, i3
))
1088 /* Make sure that the value that is to be substituted for the register
1089 does not use any registers whose values alter in between. However,
1090 If the insns are adjacent, a use can't cross a set even though we
1091 think it might (this can happen for a sequence of insns each setting
1092 the same destination; reg_last_set of that register might point to
1093 a NOTE). If INSN has a REG_EQUIV note, the register is always
1094 equivalent to the memory so the substitution is valid even if there
1095 are intervening stores. Also, don't move a volatile asm or
1096 UNSPEC_VOLATILE across any other insns. */
1098 && (((GET_CODE (src
) != MEM
1099 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1100 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1101 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1102 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1103 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1104 better register allocation by not doing the combine. */
1105 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1106 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1107 /* Don't combine across a CALL_INSN, because that would possibly
1108 change whether the life span of some REGs crosses calls or not,
1109 and it is a pain to update that information.
1110 Exception: if source is a constant, moving it later can't hurt.
1111 Accept that special case, because it helps -fforce-addr a lot. */
1112 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1115 /* DEST must either be a REG or CC0. */
1116 if (GET_CODE (dest
) == REG
)
1118 /* If register alignment is being enforced for multi-word items in all
1119 cases except for parameters, it is possible to have a register copy
1120 insn referencing a hard register that is not allowed to contain the
1121 mode being copied and which would not be valid as an operand of most
1122 insns. Eliminate this problem by not combining with such an insn.
1124 Also, on some machines we don't want to extend the life of a hard
1127 if (GET_CODE (src
) == REG
1128 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1130 /* Don't extend the life of a hard register unless it is
1131 user variable (if we have few registers) or it can't
1132 fit into the desired register (meaning something special
1134 Also avoid substituting a return register into I3, because
1135 reload can't handle a conflict with constraints of other
1137 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1138 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1141 else if (GET_CODE (dest
) != CC0
)
1144 /* Don't substitute for a register intended as a clobberable operand.
1145 Similarly, don't substitute an expression containing a register that
1146 will be clobbered in I3. */
1147 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1148 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1149 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1150 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1152 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1155 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1156 or not), reject, unless nothing volatile comes between it and I3 */
1158 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1160 /* Make sure succ doesn't contain a volatile reference. */
1161 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1164 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1165 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1169 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1170 to be an explicit register variable, and was chosen for a reason. */
1172 if (GET_CODE (src
) == ASM_OPERANDS
1173 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1176 /* If there are any volatile insns between INSN and I3, reject, because
1177 they might affect machine state. */
1179 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1180 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1183 /* If INSN or I2 contains an autoincrement or autodecrement,
1184 make sure that register is not used between there and I3,
1185 and not already used in I3 either.
1186 Also insist that I3 not be a jump; if it were one
1187 and the incremented register were spilled, we would lose. */
1190 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1191 if (REG_NOTE_KIND (link
) == REG_INC
1192 && (GET_CODE (i3
) == JUMP_INSN
1193 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1194 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1199 /* Don't combine an insn that follows a CC0-setting insn.
1200 An insn that uses CC0 must not be separated from the one that sets it.
1201 We do, however, allow I2 to follow a CC0-setting insn if that insn
1202 is passed as I1; in that case it will be deleted also.
1203 We also allow combining in this case if all the insns are adjacent
1204 because that would leave the two CC0 insns adjacent as well.
1205 It would be more logical to test whether CC0 occurs inside I1 or I2,
1206 but that would be much slower, and this ought to be equivalent. */
1208 p
= prev_nonnote_insn (insn
);
1209 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1214 /* If we get here, we have passed all the tests and the combination is
1223 /* Check if PAT is an insn - or a part of it - used to set up an
1224 argument for a function in a hard register. */
1227 sets_function_arg_p (pat
)
1233 switch (GET_CODE (pat
))
1236 return sets_function_arg_p (PATTERN (pat
));
1239 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1240 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1246 inner_dest
= SET_DEST (pat
);
1247 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1248 || GET_CODE (inner_dest
) == SUBREG
1249 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1250 inner_dest
= XEXP (inner_dest
, 0);
1252 return (GET_CODE (inner_dest
) == REG
1253 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1254 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1263 /* LOC is the location within I3 that contains its pattern or the component
1264 of a PARALLEL of the pattern. We validate that it is valid for combining.
1266 One problem is if I3 modifies its output, as opposed to replacing it
1267 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1268 so would produce an insn that is not equivalent to the original insns.
1272 (set (reg:DI 101) (reg:DI 100))
1273 (set (subreg:SI (reg:DI 101) 0) <foo>)
1275 This is NOT equivalent to:
1277 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1278 (set (reg:DI 101) (reg:DI 100))])
1280 Not only does this modify 100 (in which case it might still be valid
1281 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1283 We can also run into a problem if I2 sets a register that I1
1284 uses and I1 gets directly substituted into I3 (not via I2). In that
1285 case, we would be getting the wrong value of I2DEST into I3, so we
1286 must reject the combination. This case occurs when I2 and I1 both
1287 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1288 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1289 of a SET must prevent combination from occurring.
1291 Before doing the above check, we first try to expand a field assignment
1292 into a set of logical operations.
1294 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1295 we place a register that is both set and used within I3. If more than one
1296 such register is detected, we fail.
1298 Return 1 if the combination is valid, zero otherwise. */
1301 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1307 rtx
*pi3dest_killed
;
1311 if (GET_CODE (x
) == SET
)
1313 rtx set
= expand_field_assignment (x
);
1314 rtx dest
= SET_DEST (set
);
1315 rtx src
= SET_SRC (set
);
1316 rtx inner_dest
= dest
;
1319 rtx inner_src
= src
;
1324 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1325 || GET_CODE (inner_dest
) == SUBREG
1326 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1327 inner_dest
= XEXP (inner_dest
, 0);
1329 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1332 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1333 || GET_CODE (inner_src
) == SUBREG
1334 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1335 inner_src
= XEXP (inner_src
, 0);
1337 /* If it is better that two different modes keep two different pseudos,
1338 avoid combining them. This avoids producing the following pattern
1340 (set (subreg:SI (reg/v:QI 21) 0)
1341 (lshiftrt:SI (reg/v:SI 20)
1343 If that were made, reload could not handle the pair of
1344 reg 20/21, since it would try to get any GENERAL_REGS
1345 but some of them don't handle QImode. */
1347 if (rtx_equal_p (inner_src
, i2dest
)
1348 && GET_CODE (inner_dest
) == REG
1349 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1353 /* Check for the case where I3 modifies its output, as
1355 if ((inner_dest
!= dest
1356 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1357 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1359 /* This is the same test done in can_combine_p except we can't test
1360 all_adjacent; we don't have to, since this instruction will stay
1361 in place, thus we are not considering increasing the lifetime of
1364 Also, if this insn sets a function argument, combining it with
1365 something that might need a spill could clobber a previous
1366 function argument; the all_adjacent test in can_combine_p also
1367 checks this; here, we do a more specific test for this case. */
1369 || (GET_CODE (inner_dest
) == REG
1370 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1371 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1372 GET_MODE (inner_dest
))))
1373 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1376 /* If DEST is used in I3, it is being killed in this insn,
1377 so record that for later.
1378 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1379 STACK_POINTER_REGNUM, since these are always considered to be
1380 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1381 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1382 && reg_referenced_p (dest
, PATTERN (i3
))
1383 && REGNO (dest
) != FRAME_POINTER_REGNUM
1384 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1385 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1387 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1388 && (REGNO (dest
) != ARG_POINTER_REGNUM
1389 || ! fixed_regs
[REGNO (dest
)])
1391 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1393 if (*pi3dest_killed
)
1396 *pi3dest_killed
= dest
;
1400 else if (GET_CODE (x
) == PARALLEL
)
1404 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1405 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1406 i1_not_in_src
, pi3dest_killed
))
1413 /* Return 1 if X is an arithmetic expression that contains a multiplication
1414 and division. We don't count multiplications by powers of two here. */
1420 switch (GET_CODE (x
))
1422 case MOD
: case DIV
: case UMOD
: case UDIV
:
1426 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1427 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1429 switch (GET_RTX_CLASS (GET_CODE (x
)))
1431 case 'c': case '<': case '2':
1432 return contains_muldiv (XEXP (x
, 0))
1433 || contains_muldiv (XEXP (x
, 1));
1436 return contains_muldiv (XEXP (x
, 0));
1444 /* Determine whether INSN can be used in a combination. Return nonzero if
1445 not. This is used in try_combine to detect early some cases where we
1446 can't perform combinations. */
1449 cant_combine_insn_p (insn
)
1455 /* If this isn't really an insn, we can't do anything.
1456 This can occur when flow deletes an insn that it has merged into an
1457 auto-increment address. */
1458 if (! INSN_P (insn
))
1461 /* Never combine loads and stores involving hard regs. The register
1462 allocator can usually handle such reg-reg moves by tying. If we allow
1463 the combiner to make substitutions of hard regs, we risk aborting in
1464 reload on machines that have SMALL_REGISTER_CLASSES.
1465 As an exception, we allow combinations involving fixed regs; these are
1466 not available to the register allocator so there's no risk involved. */
1468 set
= single_set (insn
);
1471 src
= SET_SRC (set
);
1472 dest
= SET_DEST (set
);
1473 if (GET_CODE (src
) == SUBREG
)
1474 src
= SUBREG_REG (src
);
1475 if (GET_CODE (dest
) == SUBREG
)
1476 dest
= SUBREG_REG (dest
);
1477 if (REG_P (src
) && REG_P (dest
)
1478 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1479 && ! fixed_regs
[REGNO (src
)])
1480 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1481 && ! fixed_regs
[REGNO (dest
)])))
1487 /* Try to combine the insns I1 and I2 into I3.
1488 Here I1 and I2 appear earlier than I3.
1489 I1 can be zero; then we combine just I2 into I3.
1491 If we are combining three insns and the resulting insn is not recognized,
1492 try splitting it into two insns. If that happens, I2 and I3 are retained
1493 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1496 Return 0 if the combination does not work. Then nothing is changed.
1497 If we did the combination, return the insn at which combine should
1500 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1501 new direct jump instruction. */
1504 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1506 int *new_direct_jump_p
;
1508 /* New patterns for I3 and I2, respectively. */
1509 rtx newpat
, newi2pat
= 0;
1510 int substed_i2
= 0, substed_i1
= 0;
1511 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1512 int added_sets_1
, added_sets_2
;
1513 /* Total number of SETs to put into I3. */
1515 /* Nonzero is I2's body now appears in I3. */
1517 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1518 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1519 /* Contains I3 if the destination of I3 is used in its source, which means
1520 that the old life of I3 is being killed. If that usage is placed into
1521 I2 and not in I3, a REG_DEAD note must be made. */
1522 rtx i3dest_killed
= 0;
1523 /* SET_DEST and SET_SRC of I2 and I1. */
1524 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1525 /* PATTERN (I2), or a copy of it in certain cases. */
1527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1528 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1529 int i1_feeds_i3
= 0;
1530 /* Notes that must be added to REG_NOTES in I3 and I2. */
1531 rtx new_i3_notes
, new_i2_notes
;
1532 /* Notes that we substituted I3 into I2 instead of the normal case. */
1533 int i3_subst_into_i2
= 0;
1534 /* Notes that I1, I2 or I3 is a MULT operation. */
1542 /* Exit early if one of the insns involved can't be used for
1544 if (cant_combine_insn_p (i3
)
1545 || cant_combine_insn_p (i2
)
1546 || (i1
&& cant_combine_insn_p (i1
))
1547 /* We also can't do anything if I3 has a
1548 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1551 /* ??? This gives worse code, and appears to be unnecessary, since no
1552 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1553 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1559 undobuf
.other_insn
= 0;
1561 /* Reset the hard register usage information. */
1562 CLEAR_HARD_REG_SET (newpat_used_regs
);
1564 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1565 code below, set I1 to be the earlier of the two insns. */
1566 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1567 temp
= i1
, i1
= i2
, i2
= temp
;
1569 added_links_insn
= 0;
1571 /* First check for one important special-case that the code below will
1572 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1573 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1574 we may be able to replace that destination with the destination of I3.
1575 This occurs in the common code where we compute both a quotient and
1576 remainder into a structure, in which case we want to do the computation
1577 directly into the structure to avoid register-register copies.
1579 Note that this case handles both multiple sets in I2 and also
1580 cases where I2 has a number of CLOBBER or PARALLELs.
1582 We make very conservative checks below and only try to handle the
1583 most common cases of this. For example, we only handle the case
1584 where I2 and I3 are adjacent to avoid making difficult register
1587 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1588 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1589 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1590 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1591 && GET_CODE (PATTERN (i2
)) == PARALLEL
1592 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1593 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1594 below would need to check what is inside (and reg_overlap_mentioned_p
1595 doesn't support those codes anyway). Don't allow those destinations;
1596 the resulting insn isn't likely to be recognized anyway. */
1597 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1598 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1599 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1600 SET_DEST (PATTERN (i3
)))
1601 && next_real_insn (i2
) == i3
)
1603 rtx p2
= PATTERN (i2
);
1605 /* Make sure that the destination of I3,
1606 which we are going to substitute into one output of I2,
1607 is not used within another output of I2. We must avoid making this:
1608 (parallel [(set (mem (reg 69)) ...)
1609 (set (reg 69) ...)])
1610 which is not well-defined as to order of actions.
1611 (Besides, reload can't handle output reloads for this.)
1613 The problem can also happen if the dest of I3 is a memory ref,
1614 if another dest in I2 is an indirect memory ref. */
1615 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1616 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1617 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1618 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1619 SET_DEST (XVECEXP (p2
, 0, i
))))
1622 if (i
== XVECLEN (p2
, 0))
1623 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1624 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1625 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1626 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1631 subst_low_cuid
= INSN_CUID (i2
);
1633 added_sets_2
= added_sets_1
= 0;
1634 i2dest
= SET_SRC (PATTERN (i3
));
1636 /* Replace the dest in I2 with our dest and make the resulting
1637 insn the new pattern for I3. Then skip to where we
1638 validate the pattern. Everything was set up above. */
1639 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1640 SET_DEST (PATTERN (i3
)));
1643 i3_subst_into_i2
= 1;
1644 goto validate_replacement
;
1648 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1649 one of those words to another constant, merge them by making a new
1652 && (temp
= single_set (i2
)) != 0
1653 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1654 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1655 && GET_CODE (SET_DEST (temp
)) == REG
1656 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1657 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1658 && GET_CODE (PATTERN (i3
)) == SET
1659 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1660 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1661 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1662 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1663 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1665 HOST_WIDE_INT lo
, hi
;
1667 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1668 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1671 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1672 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1675 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1677 /* We don't handle the case of the target word being wider
1678 than a host wide int. */
1679 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1682 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1683 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1684 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1686 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1687 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1688 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1690 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1691 >> (HOST_BITS_PER_WIDE_INT
- 1));
1693 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1694 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1695 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1696 (INTVAL (SET_SRC (PATTERN (i3
)))));
1698 hi
= lo
< 0 ? -1 : 0;
1701 /* We don't handle the case of the higher word not fitting
1702 entirely in either hi or lo. */
1707 subst_low_cuid
= INSN_CUID (i2
);
1708 added_sets_2
= added_sets_1
= 0;
1709 i2dest
= SET_DEST (temp
);
1711 SUBST (SET_SRC (temp
),
1712 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1714 newpat
= PATTERN (i2
);
1715 goto validate_replacement
;
1719 /* If we have no I1 and I2 looks like:
1720 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1722 make up a dummy I1 that is
1725 (set (reg:CC X) (compare:CC Y (const_int 0)))
1727 (We can ignore any trailing CLOBBERs.)
1729 This undoes a previous combination and allows us to match a branch-and-
1732 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1733 && XVECLEN (PATTERN (i2
), 0) >= 2
1734 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1735 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1737 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1738 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1739 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1740 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1741 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1742 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1744 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1745 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1750 /* We make I1 with the same INSN_UID as I2. This gives it
1751 the same INSN_CUID for value tracking. Our fake I1 will
1752 never appear in the insn stream so giving it the same INSN_UID
1753 as I2 will not cause a problem. */
1755 subst_prev_insn
= i1
1756 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1757 BLOCK_FOR_INSN (i2
), INSN_SCOPE (i2
),
1758 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1761 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1762 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1763 SET_DEST (PATTERN (i1
)));
1768 /* Verify that I2 and I1 are valid for combining. */
1769 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1770 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1776 /* Record whether I2DEST is used in I2SRC and similarly for the other
1777 cases. Knowing this will help in register status updating below. */
1778 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1779 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1780 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1782 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1784 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1786 /* Ensure that I3's pattern can be the destination of combines. */
1787 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1788 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1795 /* See if any of the insns is a MULT operation. Unless one is, we will
1796 reject a combination that is, since it must be slower. Be conservative
1798 if (GET_CODE (i2src
) == MULT
1799 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1800 || (GET_CODE (PATTERN (i3
)) == SET
1801 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1804 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1805 We used to do this EXCEPT in one case: I3 has a post-inc in an
1806 output operand. However, that exception can give rise to insns like
1808 which is a famous insn on the PDP-11 where the value of r3 used as the
1809 source was model-dependent. Avoid this sort of thing. */
1812 if (!(GET_CODE (PATTERN (i3
)) == SET
1813 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1814 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1815 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1816 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1817 /* It's not the exception. */
1820 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1821 if (REG_NOTE_KIND (link
) == REG_INC
1822 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1824 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1831 /* See if the SETs in I1 or I2 need to be kept around in the merged
1832 instruction: whenever the value set there is still needed past I3.
1833 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1835 For the SET in I1, we have two cases: If I1 and I2 independently
1836 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1837 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1838 in I1 needs to be kept around unless I1DEST dies or is set in either
1839 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1840 I1DEST. If so, we know I1 feeds into I2. */
1842 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1845 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1846 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1848 /* If the set in I2 needs to be kept around, we must make a copy of
1849 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1850 PATTERN (I2), we are only substituting for the original I1DEST, not into
1851 an already-substituted copy. This also prevents making self-referential
1852 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1855 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1856 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1860 i2pat
= copy_rtx (i2pat
);
1864 /* Substitute in the latest insn for the regs set by the earlier ones. */
1866 maxreg
= max_reg_num ();
1870 /* It is possible that the source of I2 or I1 may be performing an
1871 unneeded operation, such as a ZERO_EXTEND of something that is known
1872 to have the high part zero. Handle that case by letting subst look at
1873 the innermost one of them.
1875 Another way to do this would be to have a function that tries to
1876 simplify a single insn instead of merging two or more insns. We don't
1877 do this because of the potential of infinite loops and because
1878 of the potential extra memory required. However, doing it the way
1879 we are is a bit of a kludge and doesn't catch all cases.
1881 But only do this if -fexpensive-optimizations since it slows things down
1882 and doesn't usually win. */
1884 if (flag_expensive_optimizations
)
1886 /* Pass pc_rtx so no substitutions are done, just simplifications.
1887 The cases that we are interested in here do not involve the few
1888 cases were is_replaced is checked. */
1891 subst_low_cuid
= INSN_CUID (i1
);
1892 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1896 subst_low_cuid
= INSN_CUID (i2
);
1897 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1902 /* Many machines that don't use CC0 have insns that can both perform an
1903 arithmetic operation and set the condition code. These operations will
1904 be represented as a PARALLEL with the first element of the vector
1905 being a COMPARE of an arithmetic operation with the constant zero.
1906 The second element of the vector will set some pseudo to the result
1907 of the same arithmetic operation. If we simplify the COMPARE, we won't
1908 match such a pattern and so will generate an extra insn. Here we test
1909 for this case, where both the comparison and the operation result are
1910 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1911 I2SRC. Later we will make the PARALLEL that contains I2. */
1913 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1914 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1915 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1916 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1918 #ifdef EXTRA_CC_MODES
1920 enum machine_mode compare_mode
;
1923 newpat
= PATTERN (i3
);
1924 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1928 #ifdef EXTRA_CC_MODES
1929 /* See if a COMPARE with the operand we substituted in should be done
1930 with the mode that is currently being used. If not, do the same
1931 processing we do in `subst' for a SET; namely, if the destination
1932 is used only once, try to replace it with a register of the proper
1933 mode and also replace the COMPARE. */
1934 if (undobuf
.other_insn
== 0
1935 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1936 &undobuf
.other_insn
))
1937 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1939 != GET_MODE (SET_DEST (newpat
))))
1941 unsigned int regno
= REGNO (SET_DEST (newpat
));
1942 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1944 if (regno
< FIRST_PSEUDO_REGISTER
1945 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1946 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1948 if (regno
>= FIRST_PSEUDO_REGISTER
)
1949 SUBST (regno_reg_rtx
[regno
], new_dest
);
1951 SUBST (SET_DEST (newpat
), new_dest
);
1952 SUBST (XEXP (*cc_use
, 0), new_dest
);
1953 SUBST (SET_SRC (newpat
),
1954 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1957 undobuf
.other_insn
= 0;
1964 n_occurrences
= 0; /* `subst' counts here */
1966 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1967 need to make a unique copy of I2SRC each time we substitute it
1968 to avoid self-referential rtl. */
1970 subst_low_cuid
= INSN_CUID (i2
);
1971 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1972 ! i1_feeds_i3
&& i1dest_in_i1src
);
1975 /* Record whether i2's body now appears within i3's body. */
1976 i2_is_used
= n_occurrences
;
1979 /* If we already got a failure, don't try to do more. Otherwise,
1980 try to substitute in I1 if we have it. */
1982 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1984 /* Before we can do this substitution, we must redo the test done
1985 above (see detailed comments there) that ensures that I1DEST
1986 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1988 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1996 subst_low_cuid
= INSN_CUID (i1
);
1997 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2001 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2002 to count all the ways that I2SRC and I1SRC can be used. */
2003 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2004 && i2_is_used
+ added_sets_2
> 1)
2005 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2006 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2008 /* Fail if we tried to make a new register (we used to abort, but there's
2009 really no reason to). */
2010 || max_reg_num () != maxreg
2011 /* Fail if we couldn't do something and have a CLOBBER. */
2012 || GET_CODE (newpat
) == CLOBBER
2013 /* Fail if this new pattern is a MULT and we didn't have one before
2014 at the outer level. */
2015 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2022 /* If the actions of the earlier insns must be kept
2023 in addition to substituting them into the latest one,
2024 we must make a new PARALLEL for the latest insn
2025 to hold additional the SETs. */
2027 if (added_sets_1
|| added_sets_2
)
2031 if (GET_CODE (newpat
) == PARALLEL
)
2033 rtvec old
= XVEC (newpat
, 0);
2034 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2035 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2036 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2037 sizeof (old
->elem
[0]) * old
->num_elem
);
2042 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2043 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2044 XVECEXP (newpat
, 0, 0) = old
;
2048 XVECEXP (newpat
, 0, --total_sets
)
2049 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2050 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2054 /* If there is no I1, use I2's body as is. We used to also not do
2055 the subst call below if I2 was substituted into I3,
2056 but that could lose a simplification. */
2058 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2060 /* See comment where i2pat is assigned. */
2061 XVECEXP (newpat
, 0, --total_sets
)
2062 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2066 /* We come here when we are replacing a destination in I2 with the
2067 destination of I3. */
2068 validate_replacement
:
2070 /* Note which hard regs this insn has as inputs. */
2071 mark_used_regs_combine (newpat
);
2073 /* Is the result of combination a valid instruction? */
2074 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2076 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2077 the second SET's destination is a register that is unused. In that case,
2078 we just need the first SET. This can occur when simplifying a divmod
2079 insn. We *must* test for this case here because the code below that
2080 splits two independent SETs doesn't handle this case correctly when it
2081 updates the register status. Also check the case where the first
2082 SET's destination is unused. That would not cause incorrect code, but
2083 does cause an unneeded insn to remain. */
2085 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2086 && XVECLEN (newpat
, 0) == 2
2087 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2088 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2089 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2090 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2091 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2092 && asm_noperands (newpat
) < 0)
2094 newpat
= XVECEXP (newpat
, 0, 0);
2095 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2098 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2099 && XVECLEN (newpat
, 0) == 2
2100 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2101 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2102 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2103 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2104 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2105 && asm_noperands (newpat
) < 0)
2107 newpat
= XVECEXP (newpat
, 0, 1);
2108 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2111 /* If we were combining three insns and the result is a simple SET
2112 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2113 insns. There are two ways to do this. It can be split using a
2114 machine-specific method (like when you have an addition of a large
2115 constant) or by combine in the function find_split_point. */
2117 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2118 && asm_noperands (newpat
) < 0)
2120 rtx m_split
, *split
;
2121 rtx ni2dest
= i2dest
;
2123 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2124 use I2DEST as a scratch register will help. In the latter case,
2125 convert I2DEST to the mode of the source of NEWPAT if we can. */
2127 m_split
= split_insns (newpat
, i3
);
2129 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2130 inputs of NEWPAT. */
2132 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2133 possible to try that as a scratch reg. This would require adding
2134 more code to make it work though. */
2136 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2138 /* If I2DEST is a hard register or the only use of a pseudo,
2139 we can change its mode. */
2140 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2141 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2142 && GET_CODE (i2dest
) == REG
2143 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2144 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2145 && ! REG_USERVAR_P (i2dest
))))
2146 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2149 m_split
= split_insns (gen_rtx_PARALLEL
2151 gen_rtvec (2, newpat
,
2152 gen_rtx_CLOBBER (VOIDmode
,
2155 /* If the split with the mode-changed register didn't work, try
2156 the original register. */
2157 if (! m_split
&& ni2dest
!= i2dest
)
2160 m_split
= split_insns (gen_rtx_PARALLEL
2162 gen_rtvec (2, newpat
,
2163 gen_rtx_CLOBBER (VOIDmode
,
2169 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2171 m_split
= PATTERN (m_split
);
2172 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2173 if (insn_code_number
>= 0)
2176 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2177 && (next_real_insn (i2
) == i3
2178 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2181 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2182 newi2pat
= PATTERN (m_split
);
2184 i3set
= single_set (NEXT_INSN (m_split
));
2185 i2set
= single_set (m_split
);
2187 /* In case we changed the mode of I2DEST, replace it in the
2188 pseudo-register table here. We can't do it above in case this
2189 code doesn't get executed and we do a split the other way. */
2191 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2192 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2194 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2196 /* If I2 or I3 has multiple SETs, we won't know how to track
2197 register status, so don't use these insns. If I2's destination
2198 is used between I2 and I3, we also can't use these insns. */
2200 if (i2_code_number
>= 0 && i2set
&& i3set
2201 && (next_real_insn (i2
) == i3
2202 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2203 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2205 if (insn_code_number
>= 0)
2208 /* It is possible that both insns now set the destination of I3.
2209 If so, we must show an extra use of it. */
2211 if (insn_code_number
>= 0)
2213 rtx new_i3_dest
= SET_DEST (i3set
);
2214 rtx new_i2_dest
= SET_DEST (i2set
);
2216 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2217 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2218 || GET_CODE (new_i3_dest
) == SUBREG
)
2219 new_i3_dest
= XEXP (new_i3_dest
, 0);
2221 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2222 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2223 || GET_CODE (new_i2_dest
) == SUBREG
)
2224 new_i2_dest
= XEXP (new_i2_dest
, 0);
2226 if (GET_CODE (new_i3_dest
) == REG
2227 && GET_CODE (new_i2_dest
) == REG
2228 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2229 REG_N_SETS (REGNO (new_i2_dest
))++;
2233 /* If we can split it and use I2DEST, go ahead and see if that
2234 helps things be recognized. Verify that none of the registers
2235 are set between I2 and I3. */
2236 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2238 && GET_CODE (i2dest
) == REG
2240 /* We need I2DEST in the proper mode. If it is a hard register
2241 or the only use of a pseudo, we can change its mode. */
2242 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2243 || GET_MODE (*split
) == VOIDmode
2244 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2245 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2246 && ! REG_USERVAR_P (i2dest
)))
2247 && (next_real_insn (i2
) == i3
2248 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2249 /* We can't overwrite I2DEST if its value is still used by
2251 && ! reg_referenced_p (i2dest
, newpat
))
2253 rtx newdest
= i2dest
;
2254 enum rtx_code split_code
= GET_CODE (*split
);
2255 enum machine_mode split_mode
= GET_MODE (*split
);
2257 /* Get NEWDEST as a register in the proper mode. We have already
2258 validated that we can do this. */
2259 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2261 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2263 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2264 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2267 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2268 an ASHIFT. This can occur if it was inside a PLUS and hence
2269 appeared to be a memory address. This is a kludge. */
2270 if (split_code
== MULT
2271 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2272 && INTVAL (XEXP (*split
, 1)) > 0
2273 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2275 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2276 XEXP (*split
, 0), GEN_INT (i
)));
2277 /* Update split_code because we may not have a multiply
2279 split_code
= GET_CODE (*split
);
2282 #ifdef INSN_SCHEDULING
2283 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2284 be written as a ZERO_EXTEND. */
2285 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2287 #ifdef LOAD_EXTEND_OP
2288 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2289 what it really is. */
2290 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2292 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2293 SUBREG_REG (*split
)));
2296 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2297 SUBREG_REG (*split
)));
2301 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2302 SUBST (*split
, newdest
);
2303 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2305 /* If the split point was a MULT and we didn't have one before,
2306 don't use one now. */
2307 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2308 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2312 /* Check for a case where we loaded from memory in a narrow mode and
2313 then sign extended it, but we need both registers. In that case,
2314 we have a PARALLEL with both loads from the same memory location.
2315 We can split this into a load from memory followed by a register-register
2316 copy. This saves at least one insn, more if register allocation can
2319 We cannot do this if the destination of the second assignment is
2320 a register that we have already assumed is zero-extended. Similarly
2321 for a SUBREG of such a register. */
2323 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2324 && GET_CODE (newpat
) == PARALLEL
2325 && XVECLEN (newpat
, 0) == 2
2326 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2327 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2328 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2329 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2330 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2331 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2333 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2334 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2335 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2336 (GET_CODE (temp
) == REG
2337 && reg_nonzero_bits
[REGNO (temp
)] != 0
2338 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2339 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2340 && (reg_nonzero_bits
[REGNO (temp
)]
2341 != GET_MODE_MASK (word_mode
))))
2342 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2343 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2344 (GET_CODE (temp
) == REG
2345 && reg_nonzero_bits
[REGNO (temp
)] != 0
2346 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2347 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2348 && (reg_nonzero_bits
[REGNO (temp
)]
2349 != GET_MODE_MASK (word_mode
)))))
2350 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2351 SET_SRC (XVECEXP (newpat
, 0, 1)))
2352 && ! find_reg_note (i3
, REG_UNUSED
,
2353 SET_DEST (XVECEXP (newpat
, 0, 0))))
2357 newi2pat
= XVECEXP (newpat
, 0, 0);
2358 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2359 newpat
= XVECEXP (newpat
, 0, 1);
2360 SUBST (SET_SRC (newpat
),
2361 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2362 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2364 if (i2_code_number
>= 0)
2365 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2367 if (insn_code_number
>= 0)
2372 /* If we will be able to accept this, we have made a change to the
2373 destination of I3. This can invalidate a LOG_LINKS pointing
2374 to I3. No other part of combine.c makes such a transformation.
2376 The new I3 will have a destination that was previously the
2377 destination of I1 or I2 and which was used in i2 or I3. Call
2378 distribute_links to make a LOG_LINK from the next use of
2379 that destination. */
2381 PATTERN (i3
) = newpat
;
2382 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2384 /* I3 now uses what used to be its destination and which is
2385 now I2's destination. That means we need a LOG_LINK from
2386 I3 to I2. But we used to have one, so we still will.
2388 However, some later insn might be using I2's dest and have
2389 a LOG_LINK pointing at I3. We must remove this link.
2390 The simplest way to remove the link is to point it at I1,
2391 which we know will be a NOTE. */
2393 for (insn
= NEXT_INSN (i3
);
2394 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2395 || insn
!= this_basic_block
->next_bb
->head
);
2396 insn
= NEXT_INSN (insn
))
2398 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2400 for (link
= LOG_LINKS (insn
); link
;
2401 link
= XEXP (link
, 1))
2402 if (XEXP (link
, 0) == i3
)
2403 XEXP (link
, 0) = i1
;
2411 /* Similarly, check for a case where we have a PARALLEL of two independent
2412 SETs but we started with three insns. In this case, we can do the sets
2413 as two separate insns. This case occurs when some SET allows two
2414 other insns to combine, but the destination of that SET is still live. */
2416 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2417 && GET_CODE (newpat
) == PARALLEL
2418 && XVECLEN (newpat
, 0) == 2
2419 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2420 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2421 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2422 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2423 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2424 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2425 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2427 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2428 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2429 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2430 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2431 XVECEXP (newpat
, 0, 0))
2432 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2433 XVECEXP (newpat
, 0, 1))
2434 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2435 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2437 /* Normally, it doesn't matter which of the two is done first,
2438 but it does if one references cc0. In that case, it has to
2441 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2443 newi2pat
= XVECEXP (newpat
, 0, 0);
2444 newpat
= XVECEXP (newpat
, 0, 1);
2449 newi2pat
= XVECEXP (newpat
, 0, 1);
2450 newpat
= XVECEXP (newpat
, 0, 0);
2453 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2455 if (i2_code_number
>= 0)
2456 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2459 /* If it still isn't recognized, fail and change things back the way they
2461 if ((insn_code_number
< 0
2462 /* Is the result a reasonable ASM_OPERANDS? */
2463 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2469 /* If we had to change another insn, make sure it is valid also. */
2470 if (undobuf
.other_insn
)
2472 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2473 rtx new_other_notes
;
2476 CLEAR_HARD_REG_SET (newpat_used_regs
);
2478 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2481 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2487 PATTERN (undobuf
.other_insn
) = other_pat
;
2489 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2490 are still valid. Then add any non-duplicate notes added by
2491 recog_for_combine. */
2492 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2494 next
= XEXP (note
, 1);
2496 if (REG_NOTE_KIND (note
) == REG_UNUSED
2497 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2499 if (GET_CODE (XEXP (note
, 0)) == REG
)
2500 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2502 remove_note (undobuf
.other_insn
, note
);
2506 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2507 if (GET_CODE (XEXP (note
, 0)) == REG
)
2508 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2510 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2511 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2514 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2515 they are adjacent to each other or not. */
2517 rtx p
= prev_nonnote_insn (i3
);
2518 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2519 && sets_cc0_p (newi2pat
))
2527 /* We now know that we can do this combination. Merge the insns and
2528 update the status of registers and LOG_LINKS. */
2531 rtx i3notes
, i2notes
, i1notes
= 0;
2532 rtx i3links
, i2links
, i1links
= 0;
2535 /* Compute which registers we expect to eliminate. newi2pat may be setting
2536 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2537 same as i3dest, in which case newi2pat may be setting i1dest. */
2538 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2539 || i2dest_in_i2src
|| i2dest_in_i1src
2541 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2542 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2545 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2547 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2548 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2550 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2552 /* Ensure that we do not have something that should not be shared but
2553 occurs multiple times in the new insns. Check this by first
2554 resetting all the `used' flags and then copying anything is shared. */
2556 reset_used_flags (i3notes
);
2557 reset_used_flags (i2notes
);
2558 reset_used_flags (i1notes
);
2559 reset_used_flags (newpat
);
2560 reset_used_flags (newi2pat
);
2561 if (undobuf
.other_insn
)
2562 reset_used_flags (PATTERN (undobuf
.other_insn
));
2564 i3notes
= copy_rtx_if_shared (i3notes
);
2565 i2notes
= copy_rtx_if_shared (i2notes
);
2566 i1notes
= copy_rtx_if_shared (i1notes
);
2567 newpat
= copy_rtx_if_shared (newpat
);
2568 newi2pat
= copy_rtx_if_shared (newi2pat
);
2569 if (undobuf
.other_insn
)
2570 reset_used_flags (PATTERN (undobuf
.other_insn
));
2572 INSN_CODE (i3
) = insn_code_number
;
2573 PATTERN (i3
) = newpat
;
2575 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2577 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2579 reset_used_flags (call_usage
);
2580 call_usage
= copy_rtx (call_usage
);
2583 replace_rtx (call_usage
, i2dest
, i2src
);
2586 replace_rtx (call_usage
, i1dest
, i1src
);
2588 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2591 if (undobuf
.other_insn
)
2592 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2594 /* We had one special case above where I2 had more than one set and
2595 we replaced a destination of one of those sets with the destination
2596 of I3. In that case, we have to update LOG_LINKS of insns later
2597 in this basic block. Note that this (expensive) case is rare.
2599 Also, in this case, we must pretend that all REG_NOTEs for I2
2600 actually came from I3, so that REG_UNUSED notes from I2 will be
2601 properly handled. */
2603 if (i3_subst_into_i2
)
2605 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2606 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2607 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2608 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2609 && ! find_reg_note (i2
, REG_UNUSED
,
2610 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2611 for (temp
= NEXT_INSN (i2
);
2612 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2613 || this_basic_block
->head
!= temp
);
2614 temp
= NEXT_INSN (temp
))
2615 if (temp
!= i3
&& INSN_P (temp
))
2616 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2617 if (XEXP (link
, 0) == i2
)
2618 XEXP (link
, 0) = i3
;
2623 while (XEXP (link
, 1))
2624 link
= XEXP (link
, 1);
2625 XEXP (link
, 1) = i2notes
;
2639 INSN_CODE (i2
) = i2_code_number
;
2640 PATTERN (i2
) = newi2pat
;
2644 PUT_CODE (i2
, NOTE
);
2645 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2646 NOTE_SOURCE_FILE (i2
) = 0;
2653 PUT_CODE (i1
, NOTE
);
2654 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2655 NOTE_SOURCE_FILE (i1
) = 0;
2658 /* Get death notes for everything that is now used in either I3 or
2659 I2 and used to die in a previous insn. If we built two new
2660 patterns, move from I1 to I2 then I2 to I3 so that we get the
2661 proper movement on registers that I2 modifies. */
2665 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2666 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2669 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2672 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2674 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2677 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2680 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2683 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2686 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2687 know these are REG_UNUSED and want them to go to the desired insn,
2688 so we always pass it as i3. We have not counted the notes in
2689 reg_n_deaths yet, so we need to do so now. */
2691 if (newi2pat
&& new_i2_notes
)
2693 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2694 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2695 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2697 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2702 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2703 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2704 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2706 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2709 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2710 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2711 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2712 in that case, it might delete I2. Similarly for I2 and I1.
2713 Show an additional death due to the REG_DEAD note we make here. If
2714 we discard it in distribute_notes, we will decrement it again. */
2718 if (GET_CODE (i3dest_killed
) == REG
)
2719 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2721 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2722 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2724 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2726 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2728 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2732 if (i2dest_in_i2src
)
2734 if (GET_CODE (i2dest
) == REG
)
2735 REG_N_DEATHS (REGNO (i2dest
))++;
2737 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2738 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2739 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2741 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2742 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2743 NULL_RTX
, NULL_RTX
);
2746 if (i1dest_in_i1src
)
2748 if (GET_CODE (i1dest
) == REG
)
2749 REG_N_DEATHS (REGNO (i1dest
))++;
2751 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2752 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2753 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2755 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2756 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2757 NULL_RTX
, NULL_RTX
);
2760 distribute_links (i3links
);
2761 distribute_links (i2links
);
2762 distribute_links (i1links
);
2764 if (GET_CODE (i2dest
) == REG
)
2767 rtx i2_insn
= 0, i2_val
= 0, set
;
2769 /* The insn that used to set this register doesn't exist, and
2770 this life of the register may not exist either. See if one of
2771 I3's links points to an insn that sets I2DEST. If it does,
2772 that is now the last known value for I2DEST. If we don't update
2773 this and I2 set the register to a value that depended on its old
2774 contents, we will get confused. If this insn is used, thing
2775 will be set correctly in combine_instructions. */
2777 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2778 if ((set
= single_set (XEXP (link
, 0))) != 0
2779 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2780 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2782 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2784 /* If the reg formerly set in I2 died only once and that was in I3,
2785 zero its use count so it won't make `reload' do any work. */
2787 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2788 && ! i2dest_in_i2src
)
2790 regno
= REGNO (i2dest
);
2791 REG_N_SETS (regno
)--;
2795 if (i1
&& GET_CODE (i1dest
) == REG
)
2798 rtx i1_insn
= 0, i1_val
= 0, set
;
2800 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2801 if ((set
= single_set (XEXP (link
, 0))) != 0
2802 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2803 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2805 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2807 regno
= REGNO (i1dest
);
2808 if (! added_sets_1
&& ! i1dest_in_i1src
)
2809 REG_N_SETS (regno
)--;
2812 /* Update reg_nonzero_bits et al for any changes that may have been made
2813 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2814 important. Because newi2pat can affect nonzero_bits of newpat */
2816 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2817 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2819 /* Set new_direct_jump_p if a new return or simple jump instruction
2822 If I3 is now an unconditional jump, ensure that it has a
2823 BARRIER following it since it may have initially been a
2824 conditional jump. It may also be the last nonnote insn. */
2826 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2828 *new_direct_jump_p
= 1;
2830 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2831 || GET_CODE (temp
) != BARRIER
)
2832 emit_barrier_after (i3
);
2835 if (undobuf
.other_insn
!= NULL_RTX
2836 && (returnjump_p (undobuf
.other_insn
)
2837 || any_uncondjump_p (undobuf
.other_insn
)))
2839 *new_direct_jump_p
= 1;
2841 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2842 || GET_CODE (temp
) != BARRIER
)
2843 emit_barrier_after (undobuf
.other_insn
);
2846 /* An NOOP jump does not need barrier, but it does need cleaning up
2848 if (GET_CODE (newpat
) == SET
2849 && SET_SRC (newpat
) == pc_rtx
2850 && SET_DEST (newpat
) == pc_rtx
)
2851 *new_direct_jump_p
= 1;
2854 combine_successes
++;
2857 /* Clear this here, so that subsequent get_last_value calls are not
2859 subst_prev_insn
= NULL_RTX
;
2861 if (added_links_insn
2862 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2863 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2864 return added_links_insn
;
2866 return newi2pat
? i2
: i3
;
2869 /* Undo all the modifications recorded in undobuf. */
2874 struct undo
*undo
, *next
;
2876 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2880 *undo
->where
.i
= undo
->old_contents
.i
;
2882 *undo
->where
.r
= undo
->old_contents
.r
;
2884 undo
->next
= undobuf
.frees
;
2885 undobuf
.frees
= undo
;
2890 /* Clear this here, so that subsequent get_last_value calls are not
2892 subst_prev_insn
= NULL_RTX
;
2895 /* We've committed to accepting the changes we made. Move all
2896 of the undos to the free list. */
2901 struct undo
*undo
, *next
;
2903 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2906 undo
->next
= undobuf
.frees
;
2907 undobuf
.frees
= undo
;
2913 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2914 where we have an arithmetic expression and return that point. LOC will
2917 try_combine will call this function to see if an insn can be split into
2921 find_split_point (loc
, insn
)
2926 enum rtx_code code
= GET_CODE (x
);
2928 unsigned HOST_WIDE_INT len
= 0;
2929 HOST_WIDE_INT pos
= 0;
2931 rtx inner
= NULL_RTX
;
2933 /* First special-case some codes. */
2937 #ifdef INSN_SCHEDULING
2938 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2940 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2943 return find_split_point (&SUBREG_REG (x
), insn
);
2947 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2948 using LO_SUM and HIGH. */
2949 if (GET_CODE (XEXP (x
, 0)) == CONST
2950 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2953 gen_rtx_LO_SUM (Pmode
,
2954 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2956 return &XEXP (XEXP (x
, 0), 0);
2960 /* If we have a PLUS whose second operand is a constant and the
2961 address is not valid, perhaps will can split it up using
2962 the machine-specific way to split large constants. We use
2963 the first pseudo-reg (one of the virtual regs) as a placeholder;
2964 it will not remain in the result. */
2965 if (GET_CODE (XEXP (x
, 0)) == PLUS
2966 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2967 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2969 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2970 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2973 /* This should have produced two insns, each of which sets our
2974 placeholder. If the source of the second is a valid address,
2975 we can make put both sources together and make a split point
2979 && NEXT_INSN (seq
) != NULL_RTX
2980 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2981 && GET_CODE (seq
) == INSN
2982 && GET_CODE (PATTERN (seq
)) == SET
2983 && SET_DEST (PATTERN (seq
)) == reg
2984 && ! reg_mentioned_p (reg
,
2985 SET_SRC (PATTERN (seq
)))
2986 && GET_CODE (NEXT_INSN (seq
)) == INSN
2987 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2988 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2989 && memory_address_p (GET_MODE (x
),
2990 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2992 rtx src1
= SET_SRC (PATTERN (seq
));
2993 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2995 /* Replace the placeholder in SRC2 with SRC1. If we can
2996 find where in SRC2 it was placed, that can become our
2997 split point and we can replace this address with SRC2.
2998 Just try two obvious places. */
3000 src2
= replace_rtx (src2
, reg
, src1
);
3002 if (XEXP (src2
, 0) == src1
)
3003 split
= &XEXP (src2
, 0);
3004 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3005 && XEXP (XEXP (src2
, 0), 0) == src1
)
3006 split
= &XEXP (XEXP (src2
, 0), 0);
3010 SUBST (XEXP (x
, 0), src2
);
3015 /* If that didn't work, perhaps the first operand is complex and
3016 needs to be computed separately, so make a split point there.
3017 This will occur on machines that just support REG + CONST
3018 and have a constant moved through some previous computation. */
3020 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
3021 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3022 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
3024 return &XEXP (XEXP (x
, 0), 0);
3030 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3031 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3032 we need to put the operand into a register. So split at that
3035 if (SET_DEST (x
) == cc0_rtx
3036 && GET_CODE (SET_SRC (x
)) != COMPARE
3037 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3038 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
3039 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3040 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
3041 return &SET_SRC (x
);
3044 /* See if we can split SET_SRC as it stands. */
3045 split
= find_split_point (&SET_SRC (x
), insn
);
3046 if (split
&& split
!= &SET_SRC (x
))
3049 /* See if we can split SET_DEST as it stands. */
3050 split
= find_split_point (&SET_DEST (x
), insn
);
3051 if (split
&& split
!= &SET_DEST (x
))
3054 /* See if this is a bitfield assignment with everything constant. If
3055 so, this is an IOR of an AND, so split it into that. */
3056 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3057 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3058 <= HOST_BITS_PER_WIDE_INT
)
3059 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3060 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3061 && GET_CODE (SET_SRC (x
)) == CONST_INT
3062 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3063 + INTVAL (XEXP (SET_DEST (x
), 2)))
3064 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3065 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3067 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3068 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3069 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3070 rtx dest
= XEXP (SET_DEST (x
), 0);
3071 enum machine_mode mode
= GET_MODE (dest
);
3072 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3074 if (BITS_BIG_ENDIAN
)
3075 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3079 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3082 gen_binary (IOR
, mode
,
3083 gen_binary (AND
, mode
, dest
,
3084 gen_int_mode (~(mask
<< pos
),
3086 GEN_INT (src
<< pos
)));
3088 SUBST (SET_DEST (x
), dest
);
3090 split
= find_split_point (&SET_SRC (x
), insn
);
3091 if (split
&& split
!= &SET_SRC (x
))
3095 /* Otherwise, see if this is an operation that we can split into two.
3096 If so, try to split that. */
3097 code
= GET_CODE (SET_SRC (x
));
3102 /* If we are AND'ing with a large constant that is only a single
3103 bit and the result is only being used in a context where we
3104 need to know if it is zero or non-zero, replace it with a bit
3105 extraction. This will avoid the large constant, which might
3106 have taken more than one insn to make. If the constant were
3107 not a valid argument to the AND but took only one insn to make,
3108 this is no worse, but if it took more than one insn, it will
3111 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3112 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3113 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3114 && GET_CODE (SET_DEST (x
)) == REG
3115 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3116 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3117 && XEXP (*split
, 0) == SET_DEST (x
)
3118 && XEXP (*split
, 1) == const0_rtx
)
3120 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3121 XEXP (SET_SRC (x
), 0),
3122 pos
, NULL_RTX
, 1, 1, 0, 0);
3123 if (extraction
!= 0)
3125 SUBST (SET_SRC (x
), extraction
);
3126 return find_split_point (loc
, insn
);
3132 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3133 is known to be on, this can be converted into a NEG of a shift. */
3134 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3135 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3136 && 1 <= (pos
= exact_log2
3137 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3138 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3140 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3144 gen_rtx_LSHIFTRT (mode
,
3145 XEXP (SET_SRC (x
), 0),
3148 split
= find_split_point (&SET_SRC (x
), insn
);
3149 if (split
&& split
!= &SET_SRC (x
))
3155 inner
= XEXP (SET_SRC (x
), 0);
3157 /* We can't optimize if either mode is a partial integer
3158 mode as we don't know how many bits are significant
3160 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3161 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3165 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3171 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3172 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3174 inner
= XEXP (SET_SRC (x
), 0);
3175 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3176 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3178 if (BITS_BIG_ENDIAN
)
3179 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3180 unsignedp
= (code
== ZERO_EXTRACT
);
3188 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3190 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3192 /* For unsigned, we have a choice of a shift followed by an
3193 AND or two shifts. Use two shifts for field sizes where the
3194 constant might be too large. We assume here that we can
3195 always at least get 8-bit constants in an AND insn, which is
3196 true for every current RISC. */
3198 if (unsignedp
&& len
<= 8)
3203 (mode
, gen_lowpart_for_combine (mode
, inner
),
3205 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3207 split
= find_split_point (&SET_SRC (x
), insn
);
3208 if (split
&& split
!= &SET_SRC (x
))
3215 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3216 gen_rtx_ASHIFT (mode
,
3217 gen_lowpart_for_combine (mode
, inner
),
3218 GEN_INT (GET_MODE_BITSIZE (mode
)
3220 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3222 split
= find_split_point (&SET_SRC (x
), insn
);
3223 if (split
&& split
!= &SET_SRC (x
))
3228 /* See if this is a simple operation with a constant as the second
3229 operand. It might be that this constant is out of range and hence
3230 could be used as a split point. */
3231 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3232 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3233 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3234 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3235 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3236 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3237 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3239 return &XEXP (SET_SRC (x
), 1);
3241 /* Finally, see if this is a simple operation with its first operand
3242 not in a register. The operation might require this operand in a
3243 register, so return it as a split point. We can always do this
3244 because if the first operand were another operation, we would have
3245 already found it as a split point. */
3246 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3247 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3248 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3249 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3250 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3251 return &XEXP (SET_SRC (x
), 0);
3257 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3258 it is better to write this as (not (ior A B)) so we can split it.
3259 Similarly for IOR. */
3260 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3263 gen_rtx_NOT (GET_MODE (x
),
3264 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3266 XEXP (XEXP (x
, 0), 0),
3267 XEXP (XEXP (x
, 1), 0))));
3268 return find_split_point (loc
, insn
);
3271 /* Many RISC machines have a large set of logical insns. If the
3272 second operand is a NOT, put it first so we will try to split the
3273 other operand first. */
3274 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3276 rtx tem
= XEXP (x
, 0);
3277 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3278 SUBST (XEXP (x
, 1), tem
);
3286 /* Otherwise, select our actions depending on our rtx class. */
3287 switch (GET_RTX_CLASS (code
))
3289 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3291 split
= find_split_point (&XEXP (x
, 2), insn
);
3294 /* ... fall through ... */
3298 split
= find_split_point (&XEXP (x
, 1), insn
);
3301 /* ... fall through ... */
3303 /* Some machines have (and (shift ...) ...) insns. If X is not
3304 an AND, but XEXP (X, 0) is, use it as our split point. */
3305 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3306 return &XEXP (x
, 0);
3308 split
= find_split_point (&XEXP (x
, 0), insn
);
3314 /* Otherwise, we don't have a split point. */
3318 /* Throughout X, replace FROM with TO, and return the result.
3319 The result is TO if X is FROM;
3320 otherwise the result is X, but its contents may have been modified.
3321 If they were modified, a record was made in undobuf so that
3322 undo_all will (among other things) return X to its original state.
3324 If the number of changes necessary is too much to record to undo,
3325 the excess changes are not made, so the result is invalid.
3326 The changes already made can still be undone.
3327 undobuf.num_undo is incremented for such changes, so by testing that
3328 the caller can tell whether the result is valid.
3330 `n_occurrences' is incremented each time FROM is replaced.
3332 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3334 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3335 by copying if `n_occurrences' is non-zero. */
3338 subst (x
, from
, to
, in_dest
, unique_copy
)
3343 enum rtx_code code
= GET_CODE (x
);
3344 enum machine_mode op0_mode
= VOIDmode
;
3349 /* Two expressions are equal if they are identical copies of a shared
3350 RTX or if they are both registers with the same register number
3353 #define COMBINE_RTX_EQUAL_P(X,Y) \
3355 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3356 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3358 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3361 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3364 /* If X and FROM are the same register but different modes, they will
3365 not have been seen as equal above. However, flow.c will make a
3366 LOG_LINKS entry for that case. If we do nothing, we will try to
3367 rerecognize our original insn and, when it succeeds, we will
3368 delete the feeding insn, which is incorrect.
3370 So force this insn not to match in this (rare) case. */
3371 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3372 && REGNO (x
) == REGNO (from
))
3373 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3375 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3376 of which may contain things that can be combined. */
3377 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3380 /* It is possible to have a subexpression appear twice in the insn.
3381 Suppose that FROM is a register that appears within TO.
3382 Then, after that subexpression has been scanned once by `subst',
3383 the second time it is scanned, TO may be found. If we were
3384 to scan TO here, we would find FROM within it and create a
3385 self-referent rtl structure which is completely wrong. */
3386 if (COMBINE_RTX_EQUAL_P (x
, to
))
3389 /* Parallel asm_operands need special attention because all of the
3390 inputs are shared across the arms. Furthermore, unsharing the
3391 rtl results in recognition failures. Failure to handle this case
3392 specially can result in circular rtl.
3394 Solve this by doing a normal pass across the first entry of the
3395 parallel, and only processing the SET_DESTs of the subsequent
3398 if (code
== PARALLEL
3399 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3400 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3402 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3404 /* If this substitution failed, this whole thing fails. */
3405 if (GET_CODE (new) == CLOBBER
3406 && XEXP (new, 0) == const0_rtx
)
3409 SUBST (XVECEXP (x
, 0, 0), new);
3411 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3413 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3415 if (GET_CODE (dest
) != REG
3416 && GET_CODE (dest
) != CC0
3417 && GET_CODE (dest
) != PC
)
3419 new = subst (dest
, from
, to
, 0, unique_copy
);
3421 /* If this substitution failed, this whole thing fails. */
3422 if (GET_CODE (new) == CLOBBER
3423 && XEXP (new, 0) == const0_rtx
)
3426 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3432 len
= GET_RTX_LENGTH (code
);
3433 fmt
= GET_RTX_FORMAT (code
);
3435 /* We don't need to process a SET_DEST that is a register, CC0,
3436 or PC, so set up to skip this common case. All other cases
3437 where we want to suppress replacing something inside a
3438 SET_SRC are handled via the IN_DEST operand. */
3440 && (GET_CODE (SET_DEST (x
)) == REG
3441 || GET_CODE (SET_DEST (x
)) == CC0
3442 || GET_CODE (SET_DEST (x
)) == PC
))
3445 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3448 op0_mode
= GET_MODE (XEXP (x
, 0));
3450 for (i
= 0; i
< len
; i
++)
3455 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3457 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3459 new = (unique_copy
&& n_occurrences
3460 ? copy_rtx (to
) : to
);
3465 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3468 /* If this substitution failed, this whole thing
3470 if (GET_CODE (new) == CLOBBER
3471 && XEXP (new, 0) == const0_rtx
)
3475 SUBST (XVECEXP (x
, i
, j
), new);
3478 else if (fmt
[i
] == 'e')
3480 /* If this is a register being set, ignore it. */
3483 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3484 || code
== ZERO_EXTRACT
)
3486 && GET_CODE (new) == REG
)
3489 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3491 /* In general, don't install a subreg involving two
3492 modes not tieable. It can worsen register
3493 allocation, and can even make invalid reload
3494 insns, since the reg inside may need to be copied
3495 from in the outside mode, and that may be invalid
3496 if it is an fp reg copied in integer mode.
3498 We allow two exceptions to this: It is valid if
3499 it is inside another SUBREG and the mode of that
3500 SUBREG and the mode of the inside of TO is
3501 tieable and it is valid if X is a SET that copies
3504 if (GET_CODE (to
) == SUBREG
3505 && ! MODES_TIEABLE_P (GET_MODE (to
),
3506 GET_MODE (SUBREG_REG (to
)))
3507 && ! (code
== SUBREG
3508 && MODES_TIEABLE_P (GET_MODE (x
),
3509 GET_MODE (SUBREG_REG (to
))))
3511 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3514 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3516 #ifdef CLASS_CANNOT_CHANGE_MODE
3518 && GET_CODE (to
) == REG
3519 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3520 && (TEST_HARD_REG_BIT
3521 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3523 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3525 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3528 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3532 /* If we are in a SET_DEST, suppress most cases unless we
3533 have gone inside a MEM, in which case we want to
3534 simplify the address. We assume here that things that
3535 are actually part of the destination have their inner
3536 parts in the first expression. This is true for SUBREG,
3537 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3538 things aside from REG and MEM that should appear in a
3540 new = subst (XEXP (x
, i
), from
, to
,
3542 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3543 || code
== ZERO_EXTRACT
))
3545 && i
== 0), unique_copy
);
3547 /* If we found that we will have to reject this combination,
3548 indicate that by returning the CLOBBER ourselves, rather than
3549 an expression containing it. This will speed things up as
3550 well as prevent accidents where two CLOBBERs are considered
3551 to be equal, thus producing an incorrect simplification. */
3553 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3556 if (GET_CODE (new) == CONST_INT
&& GET_CODE (x
) == SUBREG
)
3558 enum machine_mode mode
= GET_MODE (x
);
3560 x
= simplify_subreg (GET_MODE (x
), new,
3561 GET_MODE (SUBREG_REG (x
)),
3564 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3566 else if (GET_CODE (new) == CONST_INT
3567 && GET_CODE (x
) == ZERO_EXTEND
)
3569 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3570 new, GET_MODE (XEXP (x
, 0)));
3575 SUBST (XEXP (x
, i
), new);
3580 /* Try to simplify X. If the simplification changed the code, it is likely
3581 that further simplification will help, so loop, but limit the number
3582 of repetitions that will be performed. */
3584 for (i
= 0; i
< 4; i
++)
3586 /* If X is sufficiently simple, don't bother trying to do anything
3588 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3589 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3591 if (GET_CODE (x
) == code
)
3594 code
= GET_CODE (x
);
3596 /* We no longer know the original mode of operand 0 since we
3597 have changed the form of X) */
3598 op0_mode
= VOIDmode
;
3604 /* Simplify X, a piece of RTL. We just operate on the expression at the
3605 outer level; call `subst' to simplify recursively. Return the new
3608 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3609 will be the iteration even if an expression with a code different from
3610 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3613 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3615 enum machine_mode op0_mode
;
3619 enum rtx_code code
= GET_CODE (x
);
3620 enum machine_mode mode
= GET_MODE (x
);
3625 /* If this is a commutative operation, put a constant last and a complex
3626 expression first. We don't need to do this for comparisons here. */
3627 if (GET_RTX_CLASS (code
) == 'c'
3628 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3631 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3632 SUBST (XEXP (x
, 1), temp
);
3635 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3636 sign extension of a PLUS with a constant, reverse the order of the sign
3637 extension and the addition. Note that this not the same as the original
3638 code, but overflow is undefined for signed values. Also note that the
3639 PLUS will have been partially moved "inside" the sign-extension, so that
3640 the first operand of X will really look like:
3641 (ashiftrt (plus (ashift A C4) C5) C4).
3643 (plus (ashiftrt (ashift A C4) C2) C4)
3644 and replace the first operand of X with that expression. Later parts
3645 of this function may simplify the expression further.
3647 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3648 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3649 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3651 We do this to simplify address expressions. */
3653 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3654 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3655 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3656 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3657 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3658 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3659 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3660 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3661 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3662 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3663 XEXP (XEXP (x
, 0), 1))) != 0)
3666 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3667 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3668 INTVAL (XEXP (XEXP (x
, 0), 1)));
3670 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3671 INTVAL (XEXP (XEXP (x
, 0), 1)));
3673 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3676 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3677 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3678 things. Check for cases where both arms are testing the same
3681 Don't do anything if all operands are very simple. */
3683 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3684 || GET_RTX_CLASS (code
) == '<')
3685 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3686 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3687 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3689 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3690 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3691 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3693 || (GET_RTX_CLASS (code
) == '1'
3694 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3695 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3696 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3699 rtx cond
, true_rtx
, false_rtx
;
3701 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3703 /* If everything is a comparison, what we have is highly unlikely
3704 to be simpler, so don't use it. */
3705 && ! (GET_RTX_CLASS (code
) == '<'
3706 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3707 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3709 rtx cop1
= const0_rtx
;
3710 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3712 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3715 /* Simplify the alternative arms; this may collapse the true and
3716 false arms to store-flag values. */
3717 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3718 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3720 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3721 is unlikely to be simpler. */
3722 if (general_operand (true_rtx
, VOIDmode
)
3723 && general_operand (false_rtx
, VOIDmode
))
3725 /* Restarting if we generate a store-flag expression will cause
3726 us to loop. Just drop through in this case. */
3728 /* If the result values are STORE_FLAG_VALUE and zero, we can
3729 just make the comparison operation. */
3730 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3731 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3732 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3733 && reverse_condition (cond_code
) != UNKNOWN
)
3734 x
= gen_binary (reverse_condition (cond_code
),
3737 /* Likewise, we can make the negate of a comparison operation
3738 if the result values are - STORE_FLAG_VALUE and zero. */
3739 else if (GET_CODE (true_rtx
) == CONST_INT
3740 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3741 && false_rtx
== const0_rtx
)
3742 x
= simplify_gen_unary (NEG
, mode
,
3743 gen_binary (cond_code
, mode
, cond
,
3746 else if (GET_CODE (false_rtx
) == CONST_INT
3747 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3748 && true_rtx
== const0_rtx
)
3749 x
= simplify_gen_unary (NEG
, mode
,
3750 gen_binary (reverse_condition
3755 return gen_rtx_IF_THEN_ELSE (mode
,
3756 gen_binary (cond_code
, VOIDmode
,
3758 true_rtx
, false_rtx
);
3760 code
= GET_CODE (x
);
3761 op0_mode
= VOIDmode
;
3766 /* Try to fold this expression in case we have constants that weren't
3769 switch (GET_RTX_CLASS (code
))
3772 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3776 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3777 if (cmp_mode
== VOIDmode
)
3779 cmp_mode
= GET_MODE (XEXP (x
, 1));
3780 if (cmp_mode
== VOIDmode
)
3781 cmp_mode
= op0_mode
;
3783 temp
= simplify_relational_operation (code
, cmp_mode
,
3784 XEXP (x
, 0), XEXP (x
, 1));
3786 #ifdef FLOAT_STORE_FLAG_VALUE
3787 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3789 if (temp
== const0_rtx
)
3790 temp
= CONST0_RTX (mode
);
3792 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3799 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3803 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3804 XEXP (x
, 1), XEXP (x
, 2));
3811 code
= GET_CODE (temp
);
3812 op0_mode
= VOIDmode
;
3813 mode
= GET_MODE (temp
);
3816 /* First see if we can apply the inverse distributive law. */
3817 if (code
== PLUS
|| code
== MINUS
3818 || code
== AND
|| code
== IOR
|| code
== XOR
)
3820 x
= apply_distributive_law (x
);
3821 code
= GET_CODE (x
);
3822 op0_mode
= VOIDmode
;
3825 /* If CODE is an associative operation not otherwise handled, see if we
3826 can associate some operands. This can win if they are constants or
3827 if they are logically related (i.e. (a & b) & a). */
3828 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3829 || code
== AND
|| code
== IOR
|| code
== XOR
3830 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3831 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3832 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3834 if (GET_CODE (XEXP (x
, 0)) == code
)
3836 rtx other
= XEXP (XEXP (x
, 0), 0);
3837 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3838 rtx inner_op1
= XEXP (x
, 1);
3841 /* Make sure we pass the constant operand if any as the second
3842 one if this is a commutative operation. */
3843 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3845 rtx tem
= inner_op0
;
3846 inner_op0
= inner_op1
;
3849 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3850 : code
== DIV
? MULT
3852 mode
, inner_op0
, inner_op1
);
3854 /* For commutative operations, try the other pair if that one
3856 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3858 other
= XEXP (XEXP (x
, 0), 1);
3859 inner
= simplify_binary_operation (code
, mode
,
3860 XEXP (XEXP (x
, 0), 0),
3865 return gen_binary (code
, mode
, other
, inner
);
3869 /* A little bit of algebraic simplification here. */
3873 /* Ensure that our address has any ASHIFTs converted to MULT in case
3874 address-recognizing predicates are called later. */
3875 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3876 SUBST (XEXP (x
, 0), temp
);
3880 if (op0_mode
== VOIDmode
)
3881 op0_mode
= GET_MODE (SUBREG_REG (x
));
3883 /* simplify_subreg can't use gen_lowpart_for_combine. */
3884 if (CONSTANT_P (SUBREG_REG (x
))
3885 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3886 /* Don't call gen_lowpart_for_combine if the inner mode
3887 is VOIDmode and we cannot simplify it, as SUBREG without
3888 inner mode is invalid. */
3889 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3890 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3891 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3893 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3897 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3903 /* Don't change the mode of the MEM if that would change the meaning
3905 if (GET_CODE (SUBREG_REG (x
)) == MEM
3906 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3907 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3908 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3910 /* Note that we cannot do any narrowing for non-constants since
3911 we might have been counting on using the fact that some bits were
3912 zero. We now do this in the SET. */
3917 /* (not (plus X -1)) can become (neg X). */
3918 if (GET_CODE (XEXP (x
, 0)) == PLUS
3919 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3920 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3922 /* Similarly, (not (neg X)) is (plus X -1). */
3923 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3924 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3926 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3927 if (GET_CODE (XEXP (x
, 0)) == XOR
3928 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3929 && (temp
= simplify_unary_operation (NOT
, mode
,
3930 XEXP (XEXP (x
, 0), 1),
3932 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3934 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3935 other than 1, but that is not valid. We could do a similar
3936 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3937 but this doesn't seem common enough to bother with. */
3938 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3939 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3940 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3942 XEXP (XEXP (x
, 0), 1));
3944 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3945 && subreg_lowpart_p (XEXP (x
, 0))
3946 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3947 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3948 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3949 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3951 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3953 x
= gen_rtx_ROTATE (inner_mode
,
3954 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3956 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3957 return gen_lowpart_for_combine (mode
, x
);
3960 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3961 reversing the comparison code if valid. */
3962 if (STORE_FLAG_VALUE
== -1
3963 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3964 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3965 XEXP (XEXP (x
, 0), 1))))
3968 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3969 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3970 perform the above simplification. */
3972 if (STORE_FLAG_VALUE
== -1
3973 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3974 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3975 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3976 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3978 /* Apply De Morgan's laws to reduce number of patterns for machines
3979 with negating logical insns (and-not, nand, etc.). If result has
3980 only one NOT, put it first, since that is how the patterns are
3983 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3985 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3986 enum machine_mode op_mode
;
3988 op_mode
= GET_MODE (in1
);
3989 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3991 op_mode
= GET_MODE (in2
);
3992 if (op_mode
== VOIDmode
)
3994 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3996 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3999 in2
= in1
; in1
= tem
;
4002 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4008 /* (neg (plus X 1)) can become (not X). */
4009 if (GET_CODE (XEXP (x
, 0)) == PLUS
4010 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
4011 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
4013 /* Similarly, (neg (not X)) is (plus X 1). */
4014 if (GET_CODE (XEXP (x
, 0)) == NOT
)
4015 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
4017 /* (neg (minus X Y)) can become (minus Y X). This transformation
4018 isn't safe for modes with signed zeros, since if X and Y are
4019 both +0, (minus Y X) is the same as (minus X Y). If the rounding
4020 mode is towards +infinity (or -infinity) then the two expressions
4021 will be rounded differently. */
4022 if (GET_CODE (XEXP (x
, 0)) == MINUS
4023 && !HONOR_SIGNED_ZEROS (mode
)
4024 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
4025 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
4026 XEXP (XEXP (x
, 0), 0));
4028 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4029 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
4030 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4031 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4033 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4034 if we can then eliminate the NEG (e.g.,
4035 if the operand is a constant). */
4037 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
4039 temp
= simplify_unary_operation (NEG
, mode
,
4040 XEXP (XEXP (x
, 0), 0), mode
);
4042 return gen_binary (ASHIFT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
4045 temp
= expand_compound_operation (XEXP (x
, 0));
4047 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4048 replaced by (lshiftrt X C). This will convert
4049 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4051 if (GET_CODE (temp
) == ASHIFTRT
4052 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4053 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4054 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4055 INTVAL (XEXP (temp
, 1)));
4057 /* If X has only a single bit that might be nonzero, say, bit I, convert
4058 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4059 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4060 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4061 or a SUBREG of one since we'd be making the expression more
4062 complex if it was just a register. */
4064 if (GET_CODE (temp
) != REG
4065 && ! (GET_CODE (temp
) == SUBREG
4066 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4067 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4069 rtx temp1
= simplify_shift_const
4070 (NULL_RTX
, ASHIFTRT
, mode
,
4071 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4072 GET_MODE_BITSIZE (mode
) - 1 - i
),
4073 GET_MODE_BITSIZE (mode
) - 1 - i
);
4075 /* If all we did was surround TEMP with the two shifts, we
4076 haven't improved anything, so don't use it. Otherwise,
4077 we are better off with TEMP1. */
4078 if (GET_CODE (temp1
) != ASHIFTRT
4079 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4080 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4086 /* We can't handle truncation to a partial integer mode here
4087 because we don't know the real bitsize of the partial
4089 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4092 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4093 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4094 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4096 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4097 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4099 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4100 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4101 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4102 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4103 return XEXP (XEXP (x
, 0), 0);
4105 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4106 (OP:SI foo:SI) if OP is NEG or ABS. */
4107 if ((GET_CODE (XEXP (x
, 0)) == ABS
4108 || GET_CODE (XEXP (x
, 0)) == NEG
)
4109 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4110 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4111 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4112 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4113 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4115 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4117 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4118 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4119 && subreg_lowpart_p (XEXP (x
, 0)))
4120 return SUBREG_REG (XEXP (x
, 0));
4122 /* If we know that the value is already truncated, we can
4123 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4124 is nonzero for the corresponding modes. But don't do this
4125 for an (LSHIFTRT (MULT ...)) since this will cause problems
4126 with the umulXi3_highpart patterns. */
4127 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4128 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4129 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4130 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4131 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4132 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4133 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4135 /* A truncate of a comparison can be replaced with a subreg if
4136 STORE_FLAG_VALUE permits. This is like the previous test,
4137 but it works even if the comparison is done in a mode larger
4138 than HOST_BITS_PER_WIDE_INT. */
4139 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4140 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4141 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4142 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4144 /* Similarly, a truncate of a register whose value is a
4145 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4147 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4148 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4149 && (temp
= get_last_value (XEXP (x
, 0)))
4150 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4151 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4155 case FLOAT_TRUNCATE
:
4156 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4157 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4158 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4159 return XEXP (XEXP (x
, 0), 0);
4161 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4162 (OP:SF foo:SF) if OP is NEG or ABS. */
4163 if ((GET_CODE (XEXP (x
, 0)) == ABS
4164 || GET_CODE (XEXP (x
, 0)) == NEG
)
4165 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4166 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4167 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4168 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4170 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4171 is (float_truncate:SF x). */
4172 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4173 && subreg_lowpart_p (XEXP (x
, 0))
4174 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4175 return SUBREG_REG (XEXP (x
, 0));
4180 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4181 using cc0, in which case we want to leave it as a COMPARE
4182 so we can distinguish it from a register-register-copy. */
4183 if (XEXP (x
, 1) == const0_rtx
)
4186 /* x - 0 is the same as x unless x's mode has signed zeros and
4187 allows rounding towards -infinity. Under those conditions,
4189 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4190 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4191 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4197 /* (const (const X)) can become (const X). Do it this way rather than
4198 returning the inner CONST since CONST can be shared with a
4200 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4201 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4206 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4207 can add in an offset. find_split_point will split this address up
4208 again if it doesn't match. */
4209 if (GET_CODE (XEXP (x
, 0)) == HIGH
4210 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4216 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4217 outermost. That's because that's the way indexed addresses are
4218 supposed to appear. This code used to check many more cases, but
4219 they are now checked elsewhere. */
4220 if (GET_CODE (XEXP (x
, 0)) == PLUS
4221 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4222 return gen_binary (PLUS
, mode
,
4223 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4225 XEXP (XEXP (x
, 0), 1));
4227 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4228 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4229 bit-field and can be replaced by either a sign_extend or a
4230 sign_extract. The `and' may be a zero_extend and the two
4231 <c>, -<c> constants may be reversed. */
4232 if (GET_CODE (XEXP (x
, 0)) == XOR
4233 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4234 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4235 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4236 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4237 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4238 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4239 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4240 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4241 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4242 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4243 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4244 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4245 == (unsigned int) i
+ 1))))
4246 return simplify_shift_const
4247 (NULL_RTX
, ASHIFTRT
, mode
,
4248 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4249 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4250 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4251 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4253 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4254 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4255 is 1. This produces better code than the alternative immediately
4257 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4258 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4259 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4260 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4261 XEXP (XEXP (x
, 0), 0),
4262 XEXP (XEXP (x
, 0), 1))))
4264 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4266 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4267 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4268 the bitsize of the mode - 1. This allows simplification of
4269 "a = (b & 8) == 0;" */
4270 if (XEXP (x
, 1) == constm1_rtx
4271 && GET_CODE (XEXP (x
, 0)) != REG
4272 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4273 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4274 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4275 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4276 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4277 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4278 GET_MODE_BITSIZE (mode
) - 1),
4279 GET_MODE_BITSIZE (mode
) - 1);
4281 /* If we are adding two things that have no bits in common, convert
4282 the addition into an IOR. This will often be further simplified,
4283 for example in cases like ((a & 1) + (a & 2)), which can
4286 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4287 && (nonzero_bits (XEXP (x
, 0), mode
)
4288 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4290 /* Try to simplify the expression further. */
4291 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4292 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4294 /* If we could, great. If not, do not go ahead with the IOR
4295 replacement, since PLUS appears in many special purpose
4296 address arithmetic instructions. */
4297 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4303 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4304 by reversing the comparison code if valid. */
4305 if (STORE_FLAG_VALUE
== 1
4306 && XEXP (x
, 0) == const1_rtx
4307 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4308 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4309 XEXP (XEXP (x
, 1), 0),
4310 XEXP (XEXP (x
, 1), 1))))
4313 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4314 (and <foo> (const_int pow2-1)) */
4315 if (GET_CODE (XEXP (x
, 1)) == AND
4316 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4317 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4318 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4319 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4320 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4322 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4324 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4325 return gen_binary (MINUS
, mode
,
4326 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4327 XEXP (XEXP (x
, 1), 0)),
4328 XEXP (XEXP (x
, 1), 1));
4332 /* If we have (mult (plus A B) C), apply the distributive law and then
4333 the inverse distributive law to see if things simplify. This
4334 occurs mostly in addresses, often when unrolling loops. */
4336 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4338 x
= apply_distributive_law
4339 (gen_binary (PLUS
, mode
,
4340 gen_binary (MULT
, mode
,
4341 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4342 gen_binary (MULT
, mode
,
4343 XEXP (XEXP (x
, 0), 1),
4344 copy_rtx (XEXP (x
, 1)))));
4346 if (GET_CODE (x
) != MULT
)
4349 /* Try simplify a*(b/c) as (a*b)/c. */
4350 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4351 && GET_CODE (XEXP (x
, 0)) == DIV
)
4353 rtx tem
= simplify_binary_operation (MULT
, mode
,
4354 XEXP (XEXP (x
, 0), 0),
4357 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4362 /* If this is a divide by a power of two, treat it as a shift if
4363 its first operand is a shift. */
4364 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4365 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4366 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4367 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4368 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4369 || GET_CODE (XEXP (x
, 0)) == ROTATE
4370 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4371 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4375 case GT
: case GTU
: case GE
: case GEU
:
4376 case LT
: case LTU
: case LE
: case LEU
:
4377 case UNEQ
: case LTGT
:
4378 case UNGT
: case UNGE
:
4379 case UNLT
: case UNLE
:
4380 case UNORDERED
: case ORDERED
:
4381 /* If the first operand is a condition code, we can't do anything
4383 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4384 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4386 && XEXP (x
, 0) != cc0_rtx
4390 rtx op0
= XEXP (x
, 0);
4391 rtx op1
= XEXP (x
, 1);
4392 enum rtx_code new_code
;
4394 if (GET_CODE (op0
) == COMPARE
)
4395 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4397 /* Simplify our comparison, if possible. */
4398 new_code
= simplify_comparison (code
, &op0
, &op1
);
4400 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4401 if only the low-order bit is possibly nonzero in X (such as when
4402 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4403 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4404 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4407 Remove any ZERO_EXTRACT we made when thinking this was a
4408 comparison. It may now be simpler to use, e.g., an AND. If a
4409 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4410 the call to make_compound_operation in the SET case. */
4412 if (STORE_FLAG_VALUE
== 1
4413 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4414 && op1
== const0_rtx
4415 && mode
== GET_MODE (op0
)
4416 && nonzero_bits (op0
, mode
) == 1)
4417 return gen_lowpart_for_combine (mode
,
4418 expand_compound_operation (op0
));
4420 else if (STORE_FLAG_VALUE
== 1
4421 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4422 && op1
== const0_rtx
4423 && mode
== GET_MODE (op0
)
4424 && (num_sign_bit_copies (op0
, mode
)
4425 == GET_MODE_BITSIZE (mode
)))
4427 op0
= expand_compound_operation (op0
);
4428 return simplify_gen_unary (NEG
, mode
,
4429 gen_lowpart_for_combine (mode
, op0
),
4433 else if (STORE_FLAG_VALUE
== 1
4434 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4435 && op1
== const0_rtx
4436 && mode
== GET_MODE (op0
)
4437 && nonzero_bits (op0
, mode
) == 1)
4439 op0
= expand_compound_operation (op0
);
4440 return gen_binary (XOR
, mode
,
4441 gen_lowpart_for_combine (mode
, op0
),
4445 else if (STORE_FLAG_VALUE
== 1
4446 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4447 && op1
== const0_rtx
4448 && mode
== GET_MODE (op0
)
4449 && (num_sign_bit_copies (op0
, mode
)
4450 == GET_MODE_BITSIZE (mode
)))
4452 op0
= expand_compound_operation (op0
);
4453 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4456 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4458 if (STORE_FLAG_VALUE
== -1
4459 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4460 && op1
== const0_rtx
4461 && (num_sign_bit_copies (op0
, mode
)
4462 == GET_MODE_BITSIZE (mode
)))
4463 return gen_lowpart_for_combine (mode
,
4464 expand_compound_operation (op0
));
4466 else if (STORE_FLAG_VALUE
== -1
4467 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4468 && op1
== const0_rtx
4469 && mode
== GET_MODE (op0
)
4470 && nonzero_bits (op0
, mode
) == 1)
4472 op0
= expand_compound_operation (op0
);
4473 return simplify_gen_unary (NEG
, mode
,
4474 gen_lowpart_for_combine (mode
, op0
),
4478 else if (STORE_FLAG_VALUE
== -1
4479 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4480 && op1
== const0_rtx
4481 && mode
== GET_MODE (op0
)
4482 && (num_sign_bit_copies (op0
, mode
)
4483 == GET_MODE_BITSIZE (mode
)))
4485 op0
= expand_compound_operation (op0
);
4486 return simplify_gen_unary (NOT
, mode
,
4487 gen_lowpart_for_combine (mode
, op0
),
4491 /* If X is 0/1, (eq X 0) is X-1. */
4492 else if (STORE_FLAG_VALUE
== -1
4493 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4494 && op1
== const0_rtx
4495 && mode
== GET_MODE (op0
)
4496 && nonzero_bits (op0
, mode
) == 1)
4498 op0
= expand_compound_operation (op0
);
4499 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4502 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4503 one bit that might be nonzero, we can convert (ne x 0) to
4504 (ashift x c) where C puts the bit in the sign bit. Remove any
4505 AND with STORE_FLAG_VALUE when we are done, since we are only
4506 going to test the sign bit. */
4507 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4508 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4509 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4510 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4511 && op1
== const0_rtx
4512 && mode
== GET_MODE (op0
)
4513 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4515 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4516 expand_compound_operation (op0
),
4517 GET_MODE_BITSIZE (mode
) - 1 - i
);
4518 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4524 /* If the code changed, return a whole new comparison. */
4525 if (new_code
!= code
)
4526 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4528 /* Otherwise, keep this operation, but maybe change its operands.
4529 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4530 SUBST (XEXP (x
, 0), op0
);
4531 SUBST (XEXP (x
, 1), op1
);
4536 return simplify_if_then_else (x
);
4542 /* If we are processing SET_DEST, we are done. */
4546 return expand_compound_operation (x
);
4549 return simplify_set (x
);
4554 return simplify_logical (x
, last
);
4557 /* (abs (neg <foo>)) -> (abs <foo>) */
4558 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4559 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4561 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4563 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4566 /* If operand is something known to be positive, ignore the ABS. */
4567 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4568 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4569 <= HOST_BITS_PER_WIDE_INT
)
4570 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4571 & ((HOST_WIDE_INT
) 1
4572 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4576 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4577 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4578 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4583 /* (ffs (*_extend <X>)) = (ffs <X>) */
4584 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4585 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4586 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4590 /* (float (sign_extend <X>)) = (float <X>). */
4591 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4592 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4600 /* If this is a shift by a constant amount, simplify it. */
4601 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4602 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4603 INTVAL (XEXP (x
, 1)));
4605 #ifdef SHIFT_COUNT_TRUNCATED
4606 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4608 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4610 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4619 rtx op0
= XEXP (x
, 0);
4620 rtx op1
= XEXP (x
, 1);
4623 if (GET_CODE (op1
) != PARALLEL
)
4625 len
= XVECLEN (op1
, 0);
4627 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4628 && GET_CODE (op0
) == VEC_CONCAT
)
4630 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4632 /* Try to find the element in the VEC_CONCAT. */
4635 if (GET_MODE (op0
) == GET_MODE (x
))
4637 if (GET_CODE (op0
) == VEC_CONCAT
)
4639 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4640 if (op0_size
< offset
)
4641 op0
= XEXP (op0
, 0);
4645 op0
= XEXP (op0
, 1);
4663 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4666 simplify_if_then_else (x
)
4669 enum machine_mode mode
= GET_MODE (x
);
4670 rtx cond
= XEXP (x
, 0);
4671 rtx true_rtx
= XEXP (x
, 1);
4672 rtx false_rtx
= XEXP (x
, 2);
4673 enum rtx_code true_code
= GET_CODE (cond
);
4674 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4677 enum rtx_code false_code
;
4680 /* Simplify storing of the truth value. */
4681 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4682 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4684 /* Also when the truth value has to be reversed. */
4686 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4687 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4691 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4692 in it is being compared against certain values. Get the true and false
4693 comparisons and see if that says anything about the value of each arm. */
4696 && ((false_code
= combine_reversed_comparison_code (cond
))
4698 && GET_CODE (XEXP (cond
, 0)) == REG
)
4701 rtx from
= XEXP (cond
, 0);
4702 rtx true_val
= XEXP (cond
, 1);
4703 rtx false_val
= true_val
;
4706 /* If FALSE_CODE is EQ, swap the codes and arms. */
4708 if (false_code
== EQ
)
4710 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4711 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4714 /* If we are comparing against zero and the expression being tested has
4715 only a single bit that might be nonzero, that is its value when it is
4716 not equal to zero. Similarly if it is known to be -1 or 0. */
4718 if (true_code
== EQ
&& true_val
== const0_rtx
4719 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4720 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4721 else if (true_code
== EQ
&& true_val
== const0_rtx
4722 && (num_sign_bit_copies (from
, GET_MODE (from
))
4723 == GET_MODE_BITSIZE (GET_MODE (from
))))
4724 false_code
= EQ
, false_val
= constm1_rtx
;
4726 /* Now simplify an arm if we know the value of the register in the
4727 branch and it is used in the arm. Be careful due to the potential
4728 of locally-shared RTL. */
4730 if (reg_mentioned_p (from
, true_rtx
))
4731 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4733 pc_rtx
, pc_rtx
, 0, 0);
4734 if (reg_mentioned_p (from
, false_rtx
))
4735 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4737 pc_rtx
, pc_rtx
, 0, 0);
4739 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4740 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4742 true_rtx
= XEXP (x
, 1);
4743 false_rtx
= XEXP (x
, 2);
4744 true_code
= GET_CODE (cond
);
4747 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4748 reversed, do so to avoid needing two sets of patterns for
4749 subtract-and-branch insns. Similarly if we have a constant in the true
4750 arm, the false arm is the same as the first operand of the comparison, or
4751 the false arm is more complicated than the true arm. */
4754 && combine_reversed_comparison_code (cond
) != UNKNOWN
4755 && (true_rtx
== pc_rtx
4756 || (CONSTANT_P (true_rtx
)
4757 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4758 || true_rtx
== const0_rtx
4759 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4760 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4761 || (GET_CODE (true_rtx
) == SUBREG
4762 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4763 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4764 || reg_mentioned_p (true_rtx
, false_rtx
)
4765 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4767 true_code
= reversed_comparison_code (cond
, NULL
);
4769 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4772 SUBST (XEXP (x
, 1), false_rtx
);
4773 SUBST (XEXP (x
, 2), true_rtx
);
4775 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4778 /* It is possible that the conditional has been simplified out. */
4779 true_code
= GET_CODE (cond
);
4780 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4783 /* If the two arms are identical, we don't need the comparison. */
4785 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4788 /* Convert a == b ? b : a to "a". */
4789 if (true_code
== EQ
&& ! side_effects_p (cond
)
4790 && !HONOR_NANS (mode
)
4791 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4792 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4794 else if (true_code
== NE
&& ! side_effects_p (cond
)
4795 && !HONOR_NANS (mode
)
4796 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4797 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4800 /* Look for cases where we have (abs x) or (neg (abs X)). */
4802 if (GET_MODE_CLASS (mode
) == MODE_INT
4803 && GET_CODE (false_rtx
) == NEG
4804 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4806 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4807 && ! side_effects_p (true_rtx
))
4812 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4816 simplify_gen_unary (NEG
, mode
,
4817 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4823 /* Look for MIN or MAX. */
4825 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4827 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4828 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4829 && ! side_effects_p (cond
))
4834 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4837 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4840 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4843 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4848 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4849 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4850 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4851 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4852 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4853 neither 1 or -1, but it isn't worth checking for. */
4855 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4856 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4858 rtx t
= make_compound_operation (true_rtx
, SET
);
4859 rtx f
= make_compound_operation (false_rtx
, SET
);
4860 rtx cond_op0
= XEXP (cond
, 0);
4861 rtx cond_op1
= XEXP (cond
, 1);
4862 enum rtx_code op
= NIL
, extend_op
= NIL
;
4863 enum machine_mode m
= mode
;
4864 rtx z
= 0, c1
= NULL_RTX
;
4866 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4867 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4868 || GET_CODE (t
) == ASHIFT
4869 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4870 && rtx_equal_p (XEXP (t
, 0), f
))
4871 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4873 /* If an identity-zero op is commutative, check whether there
4874 would be a match if we swapped the operands. */
4875 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4876 || GET_CODE (t
) == XOR
)
4877 && rtx_equal_p (XEXP (t
, 1), f
))
4878 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4879 else if (GET_CODE (t
) == SIGN_EXTEND
4880 && (GET_CODE (XEXP (t
, 0)) == PLUS
4881 || GET_CODE (XEXP (t
, 0)) == MINUS
4882 || GET_CODE (XEXP (t
, 0)) == IOR
4883 || GET_CODE (XEXP (t
, 0)) == XOR
4884 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4885 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4886 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4887 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4888 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4889 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4890 && (num_sign_bit_copies (f
, GET_MODE (f
))
4892 (GET_MODE_BITSIZE (mode
)
4893 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4895 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4896 extend_op
= SIGN_EXTEND
;
4897 m
= GET_MODE (XEXP (t
, 0));
4899 else if (GET_CODE (t
) == SIGN_EXTEND
4900 && (GET_CODE (XEXP (t
, 0)) == PLUS
4901 || GET_CODE (XEXP (t
, 0)) == IOR
4902 || GET_CODE (XEXP (t
, 0)) == XOR
)
4903 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4904 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4905 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4906 && (num_sign_bit_copies (f
, GET_MODE (f
))
4908 (GET_MODE_BITSIZE (mode
)
4909 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4911 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4912 extend_op
= SIGN_EXTEND
;
4913 m
= GET_MODE (XEXP (t
, 0));
4915 else if (GET_CODE (t
) == ZERO_EXTEND
4916 && (GET_CODE (XEXP (t
, 0)) == PLUS
4917 || GET_CODE (XEXP (t
, 0)) == MINUS
4918 || GET_CODE (XEXP (t
, 0)) == IOR
4919 || GET_CODE (XEXP (t
, 0)) == XOR
4920 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4921 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4922 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4923 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4924 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4925 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4926 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4927 && ((nonzero_bits (f
, GET_MODE (f
))
4928 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4931 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4932 extend_op
= ZERO_EXTEND
;
4933 m
= GET_MODE (XEXP (t
, 0));
4935 else if (GET_CODE (t
) == ZERO_EXTEND
4936 && (GET_CODE (XEXP (t
, 0)) == PLUS
4937 || GET_CODE (XEXP (t
, 0)) == IOR
4938 || GET_CODE (XEXP (t
, 0)) == XOR
)
4939 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4940 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4941 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4942 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4943 && ((nonzero_bits (f
, GET_MODE (f
))
4944 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4947 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4948 extend_op
= ZERO_EXTEND
;
4949 m
= GET_MODE (XEXP (t
, 0));
4954 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4955 pc_rtx
, pc_rtx
, 0, 0);
4956 temp
= gen_binary (MULT
, m
, temp
,
4957 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4958 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4959 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4961 if (extend_op
!= NIL
)
4962 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4968 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4969 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4970 negation of a single bit, we can convert this operation to a shift. We
4971 can actually do this more generally, but it doesn't seem worth it. */
4973 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4974 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4975 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4976 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4977 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4978 == GET_MODE_BITSIZE (mode
))
4979 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4981 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4982 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4987 /* Simplify X, a SET expression. Return the new expression. */
4993 rtx src
= SET_SRC (x
);
4994 rtx dest
= SET_DEST (x
);
4995 enum machine_mode mode
4996 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5000 /* (set (pc) (return)) gets written as (return). */
5001 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5004 /* Now that we know for sure which bits of SRC we are using, see if we can
5005 simplify the expression for the object knowing that we only need the
5008 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5010 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5011 SUBST (SET_SRC (x
), src
);
5014 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5015 the comparison result and try to simplify it unless we already have used
5016 undobuf.other_insn. */
5017 if ((GET_CODE (src
) == COMPARE
5022 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5023 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5024 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
5025 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5027 enum rtx_code old_code
= GET_CODE (*cc_use
);
5028 enum rtx_code new_code
;
5030 int other_changed
= 0;
5031 enum machine_mode compare_mode
= GET_MODE (dest
);
5032 enum machine_mode tmp_mode
;
5034 if (GET_CODE (src
) == COMPARE
)
5035 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5037 op0
= src
, op1
= const0_rtx
;
5039 /* Check whether the comparison is known at compile time. */
5040 if (GET_MODE (op0
) != VOIDmode
)
5041 tmp_mode
= GET_MODE (op0
);
5042 else if (GET_MODE (op1
) != VOIDmode
)
5043 tmp_mode
= GET_MODE (op1
);
5045 tmp_mode
= compare_mode
;
5046 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5047 if (tmp
!= NULL_RTX
)
5049 rtx pat
= PATTERN (other_insn
);
5050 undobuf
.other_insn
= other_insn
;
5051 SUBST (*cc_use
, tmp
);
5053 /* Attempt to simplify CC user. */
5054 if (GET_CODE (pat
) == SET
)
5056 rtx
new = simplify_rtx (SET_SRC (pat
));
5057 if (new != NULL_RTX
)
5058 SUBST (SET_SRC (pat
), new);
5061 /* Convert X into a no-op move. */
5062 SUBST (SET_DEST (x
), pc_rtx
);
5063 SUBST (SET_SRC (x
), pc_rtx
);
5067 /* Simplify our comparison, if possible. */
5068 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5070 #ifdef EXTRA_CC_MODES
5071 /* If this machine has CC modes other than CCmode, check to see if we
5072 need to use a different CC mode here. */
5073 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5074 #endif /* EXTRA_CC_MODES */
5076 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5077 /* If the mode changed, we have to change SET_DEST, the mode in the
5078 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5079 a hard register, just build new versions with the proper mode. If it
5080 is a pseudo, we lose unless it is only time we set the pseudo, in
5081 which case we can safely change its mode. */
5082 if (compare_mode
!= GET_MODE (dest
))
5084 unsigned int regno
= REGNO (dest
);
5085 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5087 if (regno
< FIRST_PSEUDO_REGISTER
5088 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5090 if (regno
>= FIRST_PSEUDO_REGISTER
)
5091 SUBST (regno_reg_rtx
[regno
], new_dest
);
5093 SUBST (SET_DEST (x
), new_dest
);
5094 SUBST (XEXP (*cc_use
, 0), new_dest
);
5102 /* If the code changed, we have to build a new comparison in
5103 undobuf.other_insn. */
5104 if (new_code
!= old_code
)
5106 unsigned HOST_WIDE_INT mask
;
5108 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5111 /* If the only change we made was to change an EQ into an NE or
5112 vice versa, OP0 has only one bit that might be nonzero, and OP1
5113 is zero, check if changing the user of the condition code will
5114 produce a valid insn. If it won't, we can keep the original code
5115 in that insn by surrounding our operation with an XOR. */
5117 if (((old_code
== NE
&& new_code
== EQ
)
5118 || (old_code
== EQ
&& new_code
== NE
))
5119 && ! other_changed
&& op1
== const0_rtx
5120 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5121 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5123 rtx pat
= PATTERN (other_insn
), note
= 0;
5125 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5126 && ! check_asm_operands (pat
)))
5128 PUT_CODE (*cc_use
, old_code
);
5131 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5139 undobuf
.other_insn
= other_insn
;
5142 /* If we are now comparing against zero, change our source if
5143 needed. If we do not use cc0, we always have a COMPARE. */
5144 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5146 SUBST (SET_SRC (x
), op0
);
5152 /* Otherwise, if we didn't previously have a COMPARE in the
5153 correct mode, we need one. */
5154 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5156 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5161 /* Otherwise, update the COMPARE if needed. */
5162 SUBST (XEXP (src
, 0), op0
);
5163 SUBST (XEXP (src
, 1), op1
);
5168 /* Get SET_SRC in a form where we have placed back any
5169 compound expressions. Then do the checks below. */
5170 src
= make_compound_operation (src
, SET
);
5171 SUBST (SET_SRC (x
), src
);
5174 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5175 and X being a REG or (subreg (reg)), we may be able to convert this to
5176 (set (subreg:m2 x) (op)).
5178 We can always do this if M1 is narrower than M2 because that means that
5179 we only care about the low bits of the result.
5181 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5182 perform a narrower operation than requested since the high-order bits will
5183 be undefined. On machine where it is defined, this transformation is safe
5184 as long as M1 and M2 have the same number of words. */
5186 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5187 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5188 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5190 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5191 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5192 #ifndef WORD_REGISTER_OPERATIONS
5193 && (GET_MODE_SIZE (GET_MODE (src
))
5194 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5196 #ifdef CLASS_CANNOT_CHANGE_MODE
5197 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5198 && (TEST_HARD_REG_BIT
5199 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5201 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5202 GET_MODE (SUBREG_REG (src
))))
5204 && (GET_CODE (dest
) == REG
5205 || (GET_CODE (dest
) == SUBREG
5206 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5208 SUBST (SET_DEST (x
),
5209 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5211 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5213 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5217 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5220 && GET_CODE (src
) == SUBREG
5221 && subreg_lowpart_p (src
)
5222 && (GET_MODE_BITSIZE (GET_MODE (src
))
5223 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5225 rtx inner
= SUBREG_REG (src
);
5226 enum machine_mode inner_mode
= GET_MODE (inner
);
5228 /* Here we make sure that we don't have a sign bit on. */
5229 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5230 && (nonzero_bits (inner
, inner_mode
)
5231 < ((unsigned HOST_WIDE_INT
) 1
5232 << (GET_MODE_BITSIZE (inner_mode
) - 1))))
5234 SUBST (SET_SRC (x
), inner
);
5240 #ifdef LOAD_EXTEND_OP
5241 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5242 would require a paradoxical subreg. Replace the subreg with a
5243 zero_extend to avoid the reload that would otherwise be required. */
5245 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5246 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5247 && SUBREG_BYTE (src
) == 0
5248 && (GET_MODE_SIZE (GET_MODE (src
))
5249 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5250 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5253 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5254 GET_MODE (src
), SUBREG_REG (src
)));
5260 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5261 are comparing an item known to be 0 or -1 against 0, use a logical
5262 operation instead. Check for one of the arms being an IOR of the other
5263 arm with some value. We compute three terms to be IOR'ed together. In
5264 practice, at most two will be nonzero. Then we do the IOR's. */
5266 if (GET_CODE (dest
) != PC
5267 && GET_CODE (src
) == IF_THEN_ELSE
5268 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5269 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5270 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5271 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5272 #ifdef HAVE_conditional_move
5273 && ! can_conditionally_move_p (GET_MODE (src
))
5275 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5276 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5277 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5278 && ! side_effects_p (src
))
5280 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5281 ? XEXP (src
, 1) : XEXP (src
, 2));
5282 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5283 ? XEXP (src
, 2) : XEXP (src
, 1));
5284 rtx term1
= const0_rtx
, term2
, term3
;
5286 if (GET_CODE (true_rtx
) == IOR
5287 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5288 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5289 else if (GET_CODE (true_rtx
) == IOR
5290 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5291 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5292 else if (GET_CODE (false_rtx
) == IOR
5293 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5294 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5295 else if (GET_CODE (false_rtx
) == IOR
5296 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5297 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5299 term2
= gen_binary (AND
, GET_MODE (src
),
5300 XEXP (XEXP (src
, 0), 0), true_rtx
);
5301 term3
= gen_binary (AND
, GET_MODE (src
),
5302 simplify_gen_unary (NOT
, GET_MODE (src
),
5303 XEXP (XEXP (src
, 0), 0),
5308 gen_binary (IOR
, GET_MODE (src
),
5309 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5315 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5316 whole thing fail. */
5317 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5319 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5322 /* Convert this into a field assignment operation, if possible. */
5323 return make_field_assignment (x
);
5326 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5327 result. LAST is nonzero if this is the last retry. */
5330 simplify_logical (x
, last
)
5334 enum machine_mode mode
= GET_MODE (x
);
5335 rtx op0
= XEXP (x
, 0);
5336 rtx op1
= XEXP (x
, 1);
5339 switch (GET_CODE (x
))
5342 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5343 insn (and may simplify more). */
5344 if (GET_CODE (op0
) == XOR
5345 && rtx_equal_p (XEXP (op0
, 0), op1
)
5346 && ! side_effects_p (op1
))
5347 x
= gen_binary (AND
, mode
,
5348 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5351 if (GET_CODE (op0
) == XOR
5352 && rtx_equal_p (XEXP (op0
, 1), op1
)
5353 && ! side_effects_p (op1
))
5354 x
= gen_binary (AND
, mode
,
5355 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5358 /* Similarly for (~(A ^ B)) & A. */
5359 if (GET_CODE (op0
) == NOT
5360 && GET_CODE (XEXP (op0
, 0)) == XOR
5361 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5362 && ! side_effects_p (op1
))
5363 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5365 if (GET_CODE (op0
) == NOT
5366 && GET_CODE (XEXP (op0
, 0)) == XOR
5367 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5368 && ! side_effects_p (op1
))
5369 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5371 /* We can call simplify_and_const_int only if we don't lose
5372 any (sign) bits when converting INTVAL (op1) to
5373 "unsigned HOST_WIDE_INT". */
5374 if (GET_CODE (op1
) == CONST_INT
5375 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5376 || INTVAL (op1
) > 0))
5378 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5380 /* If we have (ior (and (X C1) C2)) and the next restart would be
5381 the last, simplify this by making C1 as small as possible
5384 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5385 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5386 && GET_CODE (op1
) == CONST_INT
)
5387 return gen_binary (IOR
, mode
,
5388 gen_binary (AND
, mode
, XEXP (op0
, 0),
5389 GEN_INT (INTVAL (XEXP (op0
, 1))
5390 & ~INTVAL (op1
))), op1
);
5392 if (GET_CODE (x
) != AND
)
5395 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5396 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5397 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5400 /* Convert (A | B) & A to A. */
5401 if (GET_CODE (op0
) == IOR
5402 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5403 || rtx_equal_p (XEXP (op0
, 1), op1
))
5404 && ! side_effects_p (XEXP (op0
, 0))
5405 && ! side_effects_p (XEXP (op0
, 1)))
5408 /* In the following group of tests (and those in case IOR below),
5409 we start with some combination of logical operations and apply
5410 the distributive law followed by the inverse distributive law.
5411 Most of the time, this results in no change. However, if some of
5412 the operands are the same or inverses of each other, simplifications
5415 For example, (and (ior A B) (not B)) can occur as the result of
5416 expanding a bit field assignment. When we apply the distributive
5417 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5418 which then simplifies to (and (A (not B))).
5420 If we have (and (ior A B) C), apply the distributive law and then
5421 the inverse distributive law to see if things simplify. */
5423 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5425 x
= apply_distributive_law
5426 (gen_binary (GET_CODE (op0
), mode
,
5427 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5428 gen_binary (AND
, mode
, XEXP (op0
, 1),
5430 if (GET_CODE (x
) != AND
)
5434 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5435 return apply_distributive_law
5436 (gen_binary (GET_CODE (op1
), mode
,
5437 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5438 gen_binary (AND
, mode
, XEXP (op1
, 1),
5441 /* Similarly, taking advantage of the fact that
5442 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5444 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5445 return apply_distributive_law
5446 (gen_binary (XOR
, mode
,
5447 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5448 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5451 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5452 return apply_distributive_law
5453 (gen_binary (XOR
, mode
,
5454 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5455 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5459 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5460 if (GET_CODE (op1
) == CONST_INT
5461 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5462 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5465 /* Convert (A & B) | A to A. */
5466 if (GET_CODE (op0
) == AND
5467 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5468 || rtx_equal_p (XEXP (op0
, 1), op1
))
5469 && ! side_effects_p (XEXP (op0
, 0))
5470 && ! side_effects_p (XEXP (op0
, 1)))
5473 /* If we have (ior (and A B) C), apply the distributive law and then
5474 the inverse distributive law to see if things simplify. */
5476 if (GET_CODE (op0
) == AND
)
5478 x
= apply_distributive_law
5479 (gen_binary (AND
, mode
,
5480 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5481 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5484 if (GET_CODE (x
) != IOR
)
5488 if (GET_CODE (op1
) == AND
)
5490 x
= apply_distributive_law
5491 (gen_binary (AND
, mode
,
5492 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5493 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5496 if (GET_CODE (x
) != IOR
)
5500 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5501 mode size to (rotate A CX). */
5503 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5504 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5505 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5506 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5507 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5508 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5509 == GET_MODE_BITSIZE (mode
)))
5510 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5511 (GET_CODE (op0
) == ASHIFT
5512 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5514 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5515 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5516 does not affect any of the bits in OP1, it can really be done
5517 as a PLUS and we can associate. We do this by seeing if OP1
5518 can be safely shifted left C bits. */
5519 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5520 && GET_CODE (XEXP (op0
, 0)) == PLUS
5521 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5522 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5523 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5525 int count
= INTVAL (XEXP (op0
, 1));
5526 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5528 if (mask
>> count
== INTVAL (op1
)
5529 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5531 SUBST (XEXP (XEXP (op0
, 0), 1),
5532 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5539 /* If we are XORing two things that have no bits in common,
5540 convert them into an IOR. This helps to detect rotation encoded
5541 using those methods and possibly other simplifications. */
5543 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5544 && (nonzero_bits (op0
, mode
)
5545 & nonzero_bits (op1
, mode
)) == 0)
5546 return (gen_binary (IOR
, mode
, op0
, op1
));
5548 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5549 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5552 int num_negated
= 0;
5554 if (GET_CODE (op0
) == NOT
)
5555 num_negated
++, op0
= XEXP (op0
, 0);
5556 if (GET_CODE (op1
) == NOT
)
5557 num_negated
++, op1
= XEXP (op1
, 0);
5559 if (num_negated
== 2)
5561 SUBST (XEXP (x
, 0), op0
);
5562 SUBST (XEXP (x
, 1), op1
);
5564 else if (num_negated
== 1)
5566 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5570 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5571 correspond to a machine insn or result in further simplifications
5572 if B is a constant. */
5574 if (GET_CODE (op0
) == AND
5575 && rtx_equal_p (XEXP (op0
, 1), op1
)
5576 && ! side_effects_p (op1
))
5577 return gen_binary (AND
, mode
,
5578 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5581 else if (GET_CODE (op0
) == AND
5582 && rtx_equal_p (XEXP (op0
, 0), op1
)
5583 && ! side_effects_p (op1
))
5584 return gen_binary (AND
, mode
,
5585 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5588 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5589 comparison if STORE_FLAG_VALUE is 1. */
5590 if (STORE_FLAG_VALUE
== 1
5591 && op1
== const1_rtx
5592 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5593 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5597 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5598 is (lt foo (const_int 0)), so we can perform the above
5599 simplification if STORE_FLAG_VALUE is 1. */
5601 if (STORE_FLAG_VALUE
== 1
5602 && op1
== const1_rtx
5603 && GET_CODE (op0
) == LSHIFTRT
5604 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5605 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5606 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5608 /* (xor (comparison foo bar) (const_int sign-bit))
5609 when STORE_FLAG_VALUE is the sign bit. */
5610 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5611 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5612 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5613 && op1
== const_true_rtx
5614 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5615 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5628 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5629 operations" because they can be replaced with two more basic operations.
5630 ZERO_EXTEND is also considered "compound" because it can be replaced with
5631 an AND operation, which is simpler, though only one operation.
5633 The function expand_compound_operation is called with an rtx expression
5634 and will convert it to the appropriate shifts and AND operations,
5635 simplifying at each stage.
5637 The function make_compound_operation is called to convert an expression
5638 consisting of shifts and ANDs into the equivalent compound expression.
5639 It is the inverse of this function, loosely speaking. */
5642 expand_compound_operation (x
)
5645 unsigned HOST_WIDE_INT pos
= 0, len
;
5647 unsigned int modewidth
;
5650 switch (GET_CODE (x
))
5655 /* We can't necessarily use a const_int for a multiword mode;
5656 it depends on implicitly extending the value.
5657 Since we don't know the right way to extend it,
5658 we can't tell whether the implicit way is right.
5660 Even for a mode that is no wider than a const_int,
5661 we can't win, because we need to sign extend one of its bits through
5662 the rest of it, and we don't know which bit. */
5663 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5666 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5667 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5668 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5669 reloaded. If not for that, MEM's would very rarely be safe.
5671 Reject MODEs bigger than a word, because we might not be able
5672 to reference a two-register group starting with an arbitrary register
5673 (and currently gen_lowpart might crash for a SUBREG). */
5675 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5678 /* Reject MODEs that aren't scalar integers because turning vector
5679 or complex modes into shifts causes problems. */
5681 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5684 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5685 /* If the inner object has VOIDmode (the only way this can happen
5686 is if it is an ASM_OPERANDS), we can't do anything since we don't
5687 know how much masking to do. */
5696 /* If the operand is a CLOBBER, just return it. */
5697 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5700 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5701 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5702 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5705 /* Reject MODEs that aren't scalar integers because turning vector
5706 or complex modes into shifts causes problems. */
5708 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5711 len
= INTVAL (XEXP (x
, 1));
5712 pos
= INTVAL (XEXP (x
, 2));
5714 /* If this goes outside the object being extracted, replace the object
5715 with a (use (mem ...)) construct that only combine understands
5716 and is used only for this purpose. */
5717 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5718 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5720 if (BITS_BIG_ENDIAN
)
5721 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5728 /* Convert sign extension to zero extension, if we know that the high
5729 bit is not set, as this is easier to optimize. It will be converted
5730 back to cheaper alternative in make_extraction. */
5731 if (GET_CODE (x
) == SIGN_EXTEND
5732 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5733 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5734 & ~(((unsigned HOST_WIDE_INT
)
5735 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5739 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5740 return expand_compound_operation (temp
);
5743 /* We can optimize some special cases of ZERO_EXTEND. */
5744 if (GET_CODE (x
) == ZERO_EXTEND
)
5746 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5747 know that the last value didn't have any inappropriate bits
5749 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5750 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5751 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5752 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5753 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5754 return XEXP (XEXP (x
, 0), 0);
5756 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5757 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5758 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5759 && subreg_lowpart_p (XEXP (x
, 0))
5760 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5761 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5762 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5763 return SUBREG_REG (XEXP (x
, 0));
5765 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5766 is a comparison and STORE_FLAG_VALUE permits. This is like
5767 the first case, but it works even when GET_MODE (x) is larger
5768 than HOST_WIDE_INT. */
5769 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5770 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5771 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5772 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5773 <= HOST_BITS_PER_WIDE_INT
)
5774 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5775 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5776 return XEXP (XEXP (x
, 0), 0);
5778 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5779 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5780 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5781 && subreg_lowpart_p (XEXP (x
, 0))
5782 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5783 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5784 <= HOST_BITS_PER_WIDE_INT
)
5785 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5786 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5787 return SUBREG_REG (XEXP (x
, 0));
5791 /* If we reach here, we want to return a pair of shifts. The inner
5792 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5793 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5794 logical depending on the value of UNSIGNEDP.
5796 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5797 converted into an AND of a shift.
5799 We must check for the case where the left shift would have a negative
5800 count. This can happen in a case like (x >> 31) & 255 on machines
5801 that can't shift by a constant. On those machines, we would first
5802 combine the shift with the AND to produce a variable-position
5803 extraction. Then the constant of 31 would be substituted in to produce
5804 a such a position. */
5806 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5807 if (modewidth
+ len
>= pos
)
5808 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5810 simplify_shift_const (NULL_RTX
, ASHIFT
,
5813 modewidth
- pos
- len
),
5816 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5817 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5818 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5821 ((HOST_WIDE_INT
) 1 << len
) - 1);
5823 /* Any other cases we can't handle. */
5826 /* If we couldn't do this for some reason, return the original
5828 if (GET_CODE (tem
) == CLOBBER
)
5834 /* X is a SET which contains an assignment of one object into
5835 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5836 or certain SUBREGS). If possible, convert it into a series of
5839 We half-heartedly support variable positions, but do not at all
5840 support variable lengths. */
5843 expand_field_assignment (x
)
5847 rtx pos
; /* Always counts from low bit. */
5850 enum machine_mode compute_mode
;
5852 /* Loop until we find something we can't simplify. */
5855 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5856 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5858 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5859 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5860 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5862 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5863 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5865 inner
= XEXP (SET_DEST (x
), 0);
5866 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5867 pos
= XEXP (SET_DEST (x
), 2);
5869 /* If the position is constant and spans the width of INNER,
5870 surround INNER with a USE to indicate this. */
5871 if (GET_CODE (pos
) == CONST_INT
5872 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5873 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5875 if (BITS_BIG_ENDIAN
)
5877 if (GET_CODE (pos
) == CONST_INT
)
5878 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5880 else if (GET_CODE (pos
) == MINUS
5881 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5882 && (INTVAL (XEXP (pos
, 1))
5883 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5884 /* If position is ADJUST - X, new position is X. */
5885 pos
= XEXP (pos
, 0);
5887 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5888 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5894 /* A SUBREG between two modes that occupy the same numbers of words
5895 can be done by moving the SUBREG to the source. */
5896 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5897 /* We need SUBREGs to compute nonzero_bits properly. */
5898 && nonzero_sign_valid
5899 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5900 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5901 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5902 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5904 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5905 gen_lowpart_for_combine
5906 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5913 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5914 inner
= SUBREG_REG (inner
);
5916 compute_mode
= GET_MODE (inner
);
5918 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5919 if (! SCALAR_INT_MODE_P (compute_mode
))
5921 enum machine_mode imode
;
5923 /* Don't do anything for vector or complex integral types. */
5924 if (! FLOAT_MODE_P (compute_mode
))
5927 /* Try to find an integral mode to pun with. */
5928 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5929 if (imode
== BLKmode
)
5932 compute_mode
= imode
;
5933 inner
= gen_lowpart_for_combine (imode
, inner
);
5936 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5937 if (len
< HOST_BITS_PER_WIDE_INT
)
5938 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5942 /* Now compute the equivalent expression. Make a copy of INNER
5943 for the SET_DEST in case it is a MEM into which we will substitute;
5944 we don't want shared RTL in that case. */
5946 (VOIDmode
, copy_rtx (inner
),
5947 gen_binary (IOR
, compute_mode
,
5948 gen_binary (AND
, compute_mode
,
5949 simplify_gen_unary (NOT
, compute_mode
,
5955 gen_binary (ASHIFT
, compute_mode
,
5956 gen_binary (AND
, compute_mode
,
5957 gen_lowpart_for_combine
5958 (compute_mode
, SET_SRC (x
)),
5966 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5967 it is an RTX that represents a variable starting position; otherwise,
5968 POS is the (constant) starting bit position (counted from the LSB).
5970 INNER may be a USE. This will occur when we started with a bitfield
5971 that went outside the boundary of the object in memory, which is
5972 allowed on most machines. To isolate this case, we produce a USE
5973 whose mode is wide enough and surround the MEM with it. The only
5974 code that understands the USE is this routine. If it is not removed,
5975 it will cause the resulting insn not to match.
5977 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5980 IN_DEST is non-zero if this is a reference in the destination of a
5981 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5982 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5985 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5986 ZERO_EXTRACT should be built even for bits starting at bit 0.
5988 MODE is the desired mode of the result (if IN_DEST == 0).
5990 The result is an RTX for the extraction or NULL_RTX if the target
5994 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5995 unsignedp
, in_dest
, in_compare
)
5996 enum machine_mode mode
;
6000 unsigned HOST_WIDE_INT len
;
6002 int in_dest
, in_compare
;
6004 /* This mode describes the size of the storage area
6005 to fetch the overall value from. Within that, we
6006 ignore the POS lowest bits, etc. */
6007 enum machine_mode is_mode
= GET_MODE (inner
);
6008 enum machine_mode inner_mode
;
6009 enum machine_mode wanted_inner_mode
= byte_mode
;
6010 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6011 enum machine_mode pos_mode
= word_mode
;
6012 enum machine_mode extraction_mode
= word_mode
;
6013 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6016 rtx orig_pos_rtx
= pos_rtx
;
6017 HOST_WIDE_INT orig_pos
;
6019 /* Get some information about INNER and get the innermost object. */
6020 if (GET_CODE (inner
) == USE
)
6021 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6022 /* We don't need to adjust the position because we set up the USE
6023 to pretend that it was a full-word object. */
6024 spans_byte
= 1, inner
= XEXP (inner
, 0);
6025 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6027 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6028 consider just the QI as the memory to extract from.
6029 The subreg adds or removes high bits; its mode is
6030 irrelevant to the meaning of this extraction,
6031 since POS and LEN count from the lsb. */
6032 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
6033 is_mode
= GET_MODE (SUBREG_REG (inner
));
6034 inner
= SUBREG_REG (inner
);
6036 else if (GET_CODE (inner
) == ASHIFT
6037 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6038 && pos_rtx
== 0 && pos
== 0
6039 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6041 /* We're extracting the least significant bits of an rtx
6042 (ashift X (const_int C)), where LEN > C. Extract the
6043 least significant (LEN - C) bits of X, giving an rtx
6044 whose mode is MODE, then shift it left C times. */
6045 new = make_extraction (mode
, XEXP (inner
, 0),
6046 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6047 unsignedp
, in_dest
, in_compare
);
6049 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6052 inner_mode
= GET_MODE (inner
);
6054 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6055 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6057 /* See if this can be done without an extraction. We never can if the
6058 width of the field is not the same as that of some integer mode. For
6059 registers, we can only avoid the extraction if the position is at the
6060 low-order bit and this is either not in the destination or we have the
6061 appropriate STRICT_LOW_PART operation available.
6063 For MEM, we can avoid an extract if the field starts on an appropriate
6064 boundary and we can change the mode of the memory reference. However,
6065 we cannot directly access the MEM if we have a USE and the underlying
6066 MEM is not TMODE. This combination means that MEM was being used in a
6067 context where bits outside its mode were being referenced; that is only
6068 valid in bit-field insns. */
6070 if (tmode
!= BLKmode
6071 && ! (spans_byte
&& inner_mode
!= tmode
)
6072 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6073 && GET_CODE (inner
) != MEM
6075 || (GET_CODE (inner
) == REG
6076 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6077 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6079 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6080 : BITS_PER_UNIT
)) == 0
6081 /* We can't do this if we are widening INNER_MODE (it
6082 may not be aligned, for one thing). */
6083 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6084 && (inner_mode
== tmode
6085 || (! mode_dependent_address_p (XEXP (inner
, 0))
6086 && ! MEM_VOLATILE_P (inner
))))))
6088 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6089 field. If the original and current mode are the same, we need not
6090 adjust the offset. Otherwise, we do if bytes big endian.
6092 If INNER is not a MEM, get a piece consisting of just the field
6093 of interest (in this case POS % BITS_PER_WORD must be 0). */
6095 if (GET_CODE (inner
) == MEM
)
6097 HOST_WIDE_INT offset
;
6099 /* POS counts from lsb, but make OFFSET count in memory order. */
6100 if (BYTES_BIG_ENDIAN
)
6101 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6103 offset
= pos
/ BITS_PER_UNIT
;
6105 new = adjust_address_nv (inner
, tmode
, offset
);
6107 else if (GET_CODE (inner
) == REG
)
6109 /* We can't call gen_lowpart_for_combine here since we always want
6110 a SUBREG and it would sometimes return a new hard register. */
6111 if (tmode
!= inner_mode
)
6113 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6115 if (WORDS_BIG_ENDIAN
6116 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6117 final_word
= ((GET_MODE_SIZE (inner_mode
)
6118 - GET_MODE_SIZE (tmode
))
6119 / UNITS_PER_WORD
) - final_word
;
6121 final_word
*= UNITS_PER_WORD
;
6122 if (BYTES_BIG_ENDIAN
&&
6123 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6124 final_word
+= (GET_MODE_SIZE (inner_mode
)
6125 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6127 /* Avoid creating invalid subregs, for example when
6128 simplifying (x>>32)&255. */
6129 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6132 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6138 new = force_to_mode (inner
, tmode
,
6139 len
>= HOST_BITS_PER_WIDE_INT
6140 ? ~(unsigned HOST_WIDE_INT
) 0
6141 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6144 /* If this extraction is going into the destination of a SET,
6145 make a STRICT_LOW_PART unless we made a MEM. */
6148 return (GET_CODE (new) == MEM
? new
6149 : (GET_CODE (new) != SUBREG
6150 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6151 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6156 if (GET_CODE (new) == CONST_INT
)
6157 return gen_int_mode (INTVAL (new), mode
);
6159 /* If we know that no extraneous bits are set, and that the high
6160 bit is not set, convert the extraction to the cheaper of
6161 sign and zero extension, that are equivalent in these cases. */
6162 if (flag_expensive_optimizations
6163 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6164 && ((nonzero_bits (new, tmode
)
6165 & ~(((unsigned HOST_WIDE_INT
)
6166 GET_MODE_MASK (tmode
))
6170 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6171 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6173 /* Prefer ZERO_EXTENSION, since it gives more information to
6175 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6180 /* Otherwise, sign- or zero-extend unless we already are in the
6183 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6187 /* Unless this is a COMPARE or we have a funny memory reference,
6188 don't do anything with zero-extending field extracts starting at
6189 the low-order bit since they are simple AND operations. */
6190 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6191 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6194 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6195 we would be spanning bytes or if the position is not a constant and the
6196 length is not 1. In all other cases, we would only be going outside
6197 our object in cases when an original shift would have been
6199 if (! spans_byte
&& GET_CODE (inner
) == MEM
6200 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6201 || (pos_rtx
!= 0 && len
!= 1)))
6204 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6205 and the mode for the result. */
6206 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6208 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6209 pos_mode
= mode_for_extraction (EP_insv
, 2);
6210 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6213 if (! in_dest
&& unsignedp
6214 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6216 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6217 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6218 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6221 if (! in_dest
&& ! unsignedp
6222 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6224 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6225 pos_mode
= mode_for_extraction (EP_extv
, 3);
6226 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6229 /* Never narrow an object, since that might not be safe. */
6231 if (mode
!= VOIDmode
6232 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6233 extraction_mode
= mode
;
6235 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6236 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6237 pos_mode
= GET_MODE (pos_rtx
);
6239 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6240 if we have to change the mode of memory and cannot, the desired mode is
6242 if (GET_CODE (inner
) != MEM
)
6243 wanted_inner_mode
= wanted_inner_reg_mode
;
6244 else if (inner_mode
!= wanted_inner_mode
6245 && (mode_dependent_address_p (XEXP (inner
, 0))
6246 || MEM_VOLATILE_P (inner
)))
6247 wanted_inner_mode
= extraction_mode
;
6251 if (BITS_BIG_ENDIAN
)
6253 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6254 BITS_BIG_ENDIAN style. If position is constant, compute new
6255 position. Otherwise, build subtraction.
6256 Note that POS is relative to the mode of the original argument.
6257 If it's a MEM we need to recompute POS relative to that.
6258 However, if we're extracting from (or inserting into) a register,
6259 we want to recompute POS relative to wanted_inner_mode. */
6260 int width
= (GET_CODE (inner
) == MEM
6261 ? GET_MODE_BITSIZE (is_mode
)
6262 : GET_MODE_BITSIZE (wanted_inner_mode
));
6265 pos
= width
- len
- pos
;
6268 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6269 /* POS may be less than 0 now, but we check for that below.
6270 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6273 /* If INNER has a wider mode, make it smaller. If this is a constant
6274 extract, try to adjust the byte to point to the byte containing
6276 if (wanted_inner_mode
!= VOIDmode
6277 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6278 && ((GET_CODE (inner
) == MEM
6279 && (inner_mode
== wanted_inner_mode
6280 || (! mode_dependent_address_p (XEXP (inner
, 0))
6281 && ! MEM_VOLATILE_P (inner
))))))
6285 /* The computations below will be correct if the machine is big
6286 endian in both bits and bytes or little endian in bits and bytes.
6287 If it is mixed, we must adjust. */
6289 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6290 adjust OFFSET to compensate. */
6291 if (BYTES_BIG_ENDIAN
6293 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6294 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6296 /* If this is a constant position, we can move to the desired byte. */
6299 offset
+= pos
/ BITS_PER_UNIT
;
6300 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6303 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6305 && is_mode
!= wanted_inner_mode
)
6306 offset
= (GET_MODE_SIZE (is_mode
)
6307 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6309 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6310 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6313 /* If INNER is not memory, we can always get it into the proper mode. If we
6314 are changing its mode, POS must be a constant and smaller than the size
6316 else if (GET_CODE (inner
) != MEM
)
6318 if (GET_MODE (inner
) != wanted_inner_mode
6320 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6323 inner
= force_to_mode (inner
, wanted_inner_mode
,
6325 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6326 ? ~(unsigned HOST_WIDE_INT
) 0
6327 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6332 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6333 have to zero extend. Otherwise, we can just use a SUBREG. */
6335 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6337 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6339 /* If we know that no extraneous bits are set, and that the high
6340 bit is not set, convert extraction to cheaper one - either
6341 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6343 if (flag_expensive_optimizations
6344 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6345 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6346 & ~(((unsigned HOST_WIDE_INT
)
6347 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6351 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6353 /* Prefer ZERO_EXTENSION, since it gives more information to
6355 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6360 else if (pos_rtx
!= 0
6361 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6362 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6364 /* Make POS_RTX unless we already have it and it is correct. If we don't
6365 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6367 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6368 pos_rtx
= orig_pos_rtx
;
6370 else if (pos_rtx
== 0)
6371 pos_rtx
= GEN_INT (pos
);
6373 /* Make the required operation. See if we can use existing rtx. */
6374 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6375 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6377 new = gen_lowpart_for_combine (mode
, new);
6382 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6383 with any other operations in X. Return X without that shift if so. */
6386 extract_left_shift (x
, count
)
6390 enum rtx_code code
= GET_CODE (x
);
6391 enum machine_mode mode
= GET_MODE (x
);
6397 /* This is the shift itself. If it is wide enough, we will return
6398 either the value being shifted if the shift count is equal to
6399 COUNT or a shift for the difference. */
6400 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6401 && INTVAL (XEXP (x
, 1)) >= count
)
6402 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6403 INTVAL (XEXP (x
, 1)) - count
);
6407 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6408 return simplify_gen_unary (code
, mode
, tem
, mode
);
6412 case PLUS
: case IOR
: case XOR
: case AND
:
6413 /* If we can safely shift this constant and we find the inner shift,
6414 make a new operation. */
6415 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6416 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6417 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6418 return gen_binary (code
, mode
, tem
,
6419 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6430 /* Look at the expression rooted at X. Look for expressions
6431 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6432 Form these expressions.
6434 Return the new rtx, usually just X.
6436 Also, for machines like the VAX that don't have logical shift insns,
6437 try to convert logical to arithmetic shift operations in cases where
6438 they are equivalent. This undoes the canonicalizations to logical
6439 shifts done elsewhere.
6441 We try, as much as possible, to re-use rtl expressions to save memory.
6443 IN_CODE says what kind of expression we are processing. Normally, it is
6444 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6445 being kludges), it is MEM. When processing the arguments of a comparison
6446 or a COMPARE against zero, it is COMPARE. */
6449 make_compound_operation (x
, in_code
)
6451 enum rtx_code in_code
;
6453 enum rtx_code code
= GET_CODE (x
);
6454 enum machine_mode mode
= GET_MODE (x
);
6455 int mode_width
= GET_MODE_BITSIZE (mode
);
6457 enum rtx_code next_code
;
6463 /* Select the code to be used in recursive calls. Once we are inside an
6464 address, we stay there. If we have a comparison, set to COMPARE,
6465 but once inside, go back to our default of SET. */
6467 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6468 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6469 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6470 : in_code
== COMPARE
? SET
: in_code
);
6472 /* Process depending on the code of this operation. If NEW is set
6473 non-zero, it will be returned. */
6478 /* Convert shifts by constants into multiplications if inside
6480 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6481 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6482 && INTVAL (XEXP (x
, 1)) >= 0)
6484 new = make_compound_operation (XEXP (x
, 0), next_code
);
6485 new = gen_rtx_MULT (mode
, new,
6486 GEN_INT ((HOST_WIDE_INT
) 1
6487 << INTVAL (XEXP (x
, 1))));
6492 /* If the second operand is not a constant, we can't do anything
6494 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6497 /* If the constant is a power of two minus one and the first operand
6498 is a logical right shift, make an extraction. */
6499 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6500 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6502 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6503 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6504 0, in_code
== COMPARE
);
6507 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6508 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6509 && subreg_lowpart_p (XEXP (x
, 0))
6510 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6511 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6513 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6515 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6516 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6517 0, in_code
== COMPARE
);
6519 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6520 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6521 || GET_CODE (XEXP (x
, 0)) == IOR
)
6522 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6523 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6524 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6526 /* Apply the distributive law, and then try to make extractions. */
6527 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6528 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6530 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6532 new = make_compound_operation (new, in_code
);
6535 /* If we are have (and (rotate X C) M) and C is larger than the number
6536 of bits in M, this is an extraction. */
6538 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6539 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6540 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6541 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6543 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6544 new = make_extraction (mode
, new,
6545 (GET_MODE_BITSIZE (mode
)
6546 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6547 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6550 /* On machines without logical shifts, if the operand of the AND is
6551 a logical shift and our mask turns off all the propagated sign
6552 bits, we can replace the logical shift with an arithmetic shift. */
6553 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6554 && !have_insn_for (LSHIFTRT
, mode
)
6555 && have_insn_for (ASHIFTRT
, mode
)
6556 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6557 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6558 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6559 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6561 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6563 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6564 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6566 gen_rtx_ASHIFTRT (mode
,
6567 make_compound_operation
6568 (XEXP (XEXP (x
, 0), 0), next_code
),
6569 XEXP (XEXP (x
, 0), 1)));
6572 /* If the constant is one less than a power of two, this might be
6573 representable by an extraction even if no shift is present.
6574 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6575 we are in a COMPARE. */
6576 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6577 new = make_extraction (mode
,
6578 make_compound_operation (XEXP (x
, 0),
6580 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6582 /* If we are in a comparison and this is an AND with a power of two,
6583 convert this into the appropriate bit extract. */
6584 else if (in_code
== COMPARE
6585 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6586 new = make_extraction (mode
,
6587 make_compound_operation (XEXP (x
, 0),
6589 i
, NULL_RTX
, 1, 1, 0, 1);
6594 /* If the sign bit is known to be zero, replace this with an
6595 arithmetic shift. */
6596 if (have_insn_for (ASHIFTRT
, mode
)
6597 && ! have_insn_for (LSHIFTRT
, mode
)
6598 && mode_width
<= HOST_BITS_PER_WIDE_INT
6599 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6601 new = gen_rtx_ASHIFTRT (mode
,
6602 make_compound_operation (XEXP (x
, 0),
6608 /* ... fall through ... */
6614 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6615 this is a SIGN_EXTRACT. */
6616 if (GET_CODE (rhs
) == CONST_INT
6617 && GET_CODE (lhs
) == ASHIFT
6618 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6619 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6621 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6622 new = make_extraction (mode
, new,
6623 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6624 NULL_RTX
, mode_width
- INTVAL (rhs
),
6625 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6629 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6630 If so, try to merge the shifts into a SIGN_EXTEND. We could
6631 also do this for some cases of SIGN_EXTRACT, but it doesn't
6632 seem worth the effort; the case checked for occurs on Alpha. */
6634 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6635 && ! (GET_CODE (lhs
) == SUBREG
6636 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6637 && GET_CODE (rhs
) == CONST_INT
6638 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6639 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6640 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6641 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6642 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6647 /* Call ourselves recursively on the inner expression. If we are
6648 narrowing the object and it has a different RTL code from
6649 what it originally did, do this SUBREG as a force_to_mode. */
6651 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6652 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6653 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6654 && subreg_lowpart_p (x
))
6656 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6659 /* If we have something other than a SUBREG, we might have
6660 done an expansion, so rerun ourselves. */
6661 if (GET_CODE (newer
) != SUBREG
)
6662 newer
= make_compound_operation (newer
, in_code
);
6667 /* If this is a paradoxical subreg, and the new code is a sign or
6668 zero extension, omit the subreg and widen the extension. If it
6669 is a regular subreg, we can still get rid of the subreg by not
6670 widening so much, or in fact removing the extension entirely. */
6671 if ((GET_CODE (tem
) == SIGN_EXTEND
6672 || GET_CODE (tem
) == ZERO_EXTEND
)
6673 && subreg_lowpart_p (x
))
6675 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6676 || (GET_MODE_SIZE (mode
) >
6677 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6679 if (! INTEGRAL_MODE_P (mode
))
6681 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6684 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6695 x
= gen_lowpart_for_combine (mode
, new);
6696 code
= GET_CODE (x
);
6699 /* Now recursively process each operand of this operation. */
6700 fmt
= GET_RTX_FORMAT (code
);
6701 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6704 new = make_compound_operation (XEXP (x
, i
), next_code
);
6705 SUBST (XEXP (x
, i
), new);
6711 /* Given M see if it is a value that would select a field of bits
6712 within an item, but not the entire word. Return -1 if not.
6713 Otherwise, return the starting position of the field, where 0 is the
6716 *PLEN is set to the length of the field. */
6719 get_pos_from_mask (m
, plen
)
6720 unsigned HOST_WIDE_INT m
;
6721 unsigned HOST_WIDE_INT
*plen
;
6723 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6724 int pos
= exact_log2 (m
& -m
);
6730 /* Now shift off the low-order zero bits and see if we have a power of
6732 len
= exact_log2 ((m
>> pos
) + 1);
6741 /* See if X can be simplified knowing that we will only refer to it in
6742 MODE and will only refer to those bits that are nonzero in MASK.
6743 If other bits are being computed or if masking operations are done
6744 that select a superset of the bits in MASK, they can sometimes be
6747 Return a possibly simplified expression, but always convert X to
6748 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6750 Also, if REG is non-zero and X is a register equal in value to REG,
6753 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6754 are all off in X. This is used when X will be complemented, by either
6755 NOT, NEG, or XOR. */
6758 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6760 enum machine_mode mode
;
6761 unsigned HOST_WIDE_INT mask
;
6765 enum rtx_code code
= GET_CODE (x
);
6766 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6767 enum machine_mode op_mode
;
6768 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6771 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6772 code below will do the wrong thing since the mode of such an
6773 expression is VOIDmode.
6775 Also do nothing if X is a CLOBBER; this can happen if X was
6776 the return value from a call to gen_lowpart_for_combine. */
6777 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6780 /* We want to perform the operation is its present mode unless we know
6781 that the operation is valid in MODE, in which case we do the operation
6783 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6784 && have_insn_for (code
, mode
))
6785 ? mode
: GET_MODE (x
));
6787 /* It is not valid to do a right-shift in a narrower mode
6788 than the one it came in with. */
6789 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6790 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6791 op_mode
= GET_MODE (x
);
6793 /* Truncate MASK to fit OP_MODE. */
6795 mask
&= GET_MODE_MASK (op_mode
);
6797 /* When we have an arithmetic operation, or a shift whose count we
6798 do not know, we need to assume that all bit the up to the highest-order
6799 bit in MASK will be needed. This is how we form such a mask. */
6801 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6802 ? GET_MODE_MASK (op_mode
)
6803 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6806 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6808 /* Determine what bits of X are guaranteed to be (non)zero. */
6809 nonzero
= nonzero_bits (x
, mode
);
6811 /* If none of the bits in X are needed, return a zero. */
6812 if (! just_select
&& (nonzero
& mask
) == 0)
6815 /* If X is a CONST_INT, return a new one. Do this here since the
6816 test below will fail. */
6817 if (GET_CODE (x
) == CONST_INT
)
6818 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6820 /* If X is narrower than MODE and we want all the bits in X's mode, just
6821 get X in the proper mode. */
6822 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6823 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6824 return gen_lowpart_for_combine (mode
, x
);
6826 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6827 MASK are already known to be zero in X, we need not do anything. */
6828 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6834 /* If X is a (clobber (const_int)), return it since we know we are
6835 generating something that won't match. */
6839 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6840 spanned the boundary of the MEM. If we are now masking so it is
6841 within that boundary, we don't need the USE any more. */
6842 if (! BITS_BIG_ENDIAN
6843 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6844 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6851 x
= expand_compound_operation (x
);
6852 if (GET_CODE (x
) != code
)
6853 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6857 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6858 || rtx_equal_p (reg
, get_last_value (x
))))
6863 if (subreg_lowpart_p (x
)
6864 /* We can ignore the effect of this SUBREG if it narrows the mode or
6865 if the constant masks to zero all the bits the mode doesn't
6867 && ((GET_MODE_SIZE (GET_MODE (x
))
6868 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6870 & GET_MODE_MASK (GET_MODE (x
))
6871 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6872 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6876 /* If this is an AND with a constant, convert it into an AND
6877 whose constant is the AND of that constant with MASK. If it
6878 remains an AND of MASK, delete it since it is redundant. */
6880 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6882 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6883 mask
& INTVAL (XEXP (x
, 1)));
6885 /* If X is still an AND, see if it is an AND with a mask that
6886 is just some low-order bits. If so, and it is MASK, we don't
6889 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6890 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6894 /* If it remains an AND, try making another AND with the bits
6895 in the mode mask that aren't in MASK turned on. If the
6896 constant in the AND is wide enough, this might make a
6897 cheaper constant. */
6899 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6900 && GET_MODE_MASK (GET_MODE (x
)) != mask
6901 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6903 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6904 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6905 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6908 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6909 number, sign extend it. */
6910 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6911 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6912 cval
|= (HOST_WIDE_INT
) -1 << width
;
6914 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6915 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6925 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6926 low-order bits (as in an alignment operation) and FOO is already
6927 aligned to that boundary, mask C1 to that boundary as well.
6928 This may eliminate that PLUS and, later, the AND. */
6931 unsigned int width
= GET_MODE_BITSIZE (mode
);
6932 unsigned HOST_WIDE_INT smask
= mask
;
6934 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6935 number, sign extend it. */
6937 if (width
< HOST_BITS_PER_WIDE_INT
6938 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6939 smask
|= (HOST_WIDE_INT
) -1 << width
;
6941 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6942 && exact_log2 (- smask
) >= 0
6943 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6944 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6945 return force_to_mode (plus_constant (XEXP (x
, 0),
6946 (INTVAL (XEXP (x
, 1)) & smask
)),
6947 mode
, smask
, reg
, next_select
);
6950 /* ... fall through ... */
6953 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6954 most significant bit in MASK since carries from those bits will
6955 affect the bits we are interested in. */
6960 /* If X is (minus C Y) where C's least set bit is larger than any bit
6961 in the mask, then we may replace with (neg Y). */
6962 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6963 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6964 & -INTVAL (XEXP (x
, 0))))
6967 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6969 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6972 /* Similarly, if C contains every bit in the mask, then we may
6973 replace with (not Y). */
6974 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6975 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6976 == INTVAL (XEXP (x
, 0))))
6978 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6979 XEXP (x
, 1), GET_MODE (x
));
6980 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6988 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6989 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6990 operation which may be a bitfield extraction. Ensure that the
6991 constant we form is not wider than the mode of X. */
6993 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6994 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6995 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6996 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6997 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6998 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6999 + floor_log2 (INTVAL (XEXP (x
, 1))))
7000 < GET_MODE_BITSIZE (GET_MODE (x
)))
7001 && (INTVAL (XEXP (x
, 1))
7002 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7004 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7005 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7006 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
7007 XEXP (XEXP (x
, 0), 0), temp
);
7008 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7009 XEXP (XEXP (x
, 0), 1));
7010 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7014 /* For most binary operations, just propagate into the operation and
7015 change the mode if we have an operation of that mode. */
7017 op0
= gen_lowpart_for_combine (op_mode
,
7018 force_to_mode (XEXP (x
, 0), mode
, mask
,
7020 op1
= gen_lowpart_for_combine (op_mode
,
7021 force_to_mode (XEXP (x
, 1), mode
, mask
,
7024 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7025 x
= gen_binary (code
, op_mode
, op0
, op1
);
7029 /* For left shifts, do the same, but just for the first operand.
7030 However, we cannot do anything with shifts where we cannot
7031 guarantee that the counts are smaller than the size of the mode
7032 because such a count will have a different meaning in a
7035 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7036 && INTVAL (XEXP (x
, 1)) >= 0
7037 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7038 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7039 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7040 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7043 /* If the shift count is a constant and we can do arithmetic in
7044 the mode of the shift, refine which bits we need. Otherwise, use the
7045 conservative form of the mask. */
7046 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7047 && INTVAL (XEXP (x
, 1)) >= 0
7048 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7049 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7050 mask
>>= INTVAL (XEXP (x
, 1));
7054 op0
= gen_lowpart_for_combine (op_mode
,
7055 force_to_mode (XEXP (x
, 0), op_mode
,
7056 mask
, reg
, next_select
));
7058 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7059 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7063 /* Here we can only do something if the shift count is a constant,
7064 this shift constant is valid for the host, and we can do arithmetic
7067 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7068 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7069 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7071 rtx inner
= XEXP (x
, 0);
7072 unsigned HOST_WIDE_INT inner_mask
;
7074 /* Select the mask of the bits we need for the shift operand. */
7075 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7077 /* We can only change the mode of the shift if we can do arithmetic
7078 in the mode of the shift and INNER_MASK is no wider than the
7079 width of OP_MODE. */
7080 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7081 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7082 op_mode
= GET_MODE (x
);
7084 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7086 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7087 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7090 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7091 shift and AND produces only copies of the sign bit (C2 is one less
7092 than a power of two), we can do this with just a shift. */
7094 if (GET_CODE (x
) == LSHIFTRT
7095 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7096 /* The shift puts one of the sign bit copies in the least significant
7098 && ((INTVAL (XEXP (x
, 1))
7099 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7100 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7101 && exact_log2 (mask
+ 1) >= 0
7102 /* Number of bits left after the shift must be more than the mask
7104 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7105 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7106 /* Must be more sign bit copies than the mask needs. */
7107 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7108 >= exact_log2 (mask
+ 1)))
7109 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7110 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7111 - exact_log2 (mask
+ 1)));
7116 /* If we are just looking for the sign bit, we don't need this shift at
7117 all, even if it has a variable count. */
7118 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7119 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7120 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7121 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7123 /* If this is a shift by a constant, get a mask that contains those bits
7124 that are not copies of the sign bit. We then have two cases: If
7125 MASK only includes those bits, this can be a logical shift, which may
7126 allow simplifications. If MASK is a single-bit field not within
7127 those bits, we are requesting a copy of the sign bit and hence can
7128 shift the sign bit to the appropriate location. */
7130 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7131 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7135 /* If the considered data is wider than HOST_WIDE_INT, we can't
7136 represent a mask for all its bits in a single scalar.
7137 But we only care about the lower bits, so calculate these. */
7139 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7141 nonzero
= ~(HOST_WIDE_INT
) 0;
7143 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7144 is the number of bits a full-width mask would have set.
7145 We need only shift if these are fewer than nonzero can
7146 hold. If not, we must keep all bits set in nonzero. */
7148 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7149 < HOST_BITS_PER_WIDE_INT
)
7150 nonzero
>>= INTVAL (XEXP (x
, 1))
7151 + HOST_BITS_PER_WIDE_INT
7152 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7156 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7157 nonzero
>>= INTVAL (XEXP (x
, 1));
7160 if ((mask
& ~nonzero
) == 0
7161 || (i
= exact_log2 (mask
)) >= 0)
7163 x
= simplify_shift_const
7164 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7165 i
< 0 ? INTVAL (XEXP (x
, 1))
7166 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7168 if (GET_CODE (x
) != ASHIFTRT
)
7169 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7173 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7174 even if the shift count isn't a constant. */
7176 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7180 /* If this is a zero- or sign-extension operation that just affects bits
7181 we don't care about, remove it. Be sure the call above returned
7182 something that is still a shift. */
7184 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7185 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7186 && INTVAL (XEXP (x
, 1)) >= 0
7187 && (INTVAL (XEXP (x
, 1))
7188 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7189 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7190 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7191 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7192 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7199 /* If the shift count is constant and we can do computations
7200 in the mode of X, compute where the bits we care about are.
7201 Otherwise, we can't do anything. Don't change the mode of
7202 the shift or propagate MODE into the shift, though. */
7203 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7204 && INTVAL (XEXP (x
, 1)) >= 0)
7206 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7207 GET_MODE (x
), GEN_INT (mask
),
7209 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7211 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7212 INTVAL (temp
), reg
, next_select
));
7217 /* If we just want the low-order bit, the NEG isn't needed since it
7218 won't change the low-order bit. */
7220 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7222 /* We need any bits less significant than the most significant bit in
7223 MASK since carries from those bits will affect the bits we are
7229 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7230 same as the XOR case above. Ensure that the constant we form is not
7231 wider than the mode of X. */
7233 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7234 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7235 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7236 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7237 < GET_MODE_BITSIZE (GET_MODE (x
)))
7238 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7240 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7241 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7242 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7244 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7247 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7248 use the full mask inside the NOT. */
7252 op0
= gen_lowpart_for_combine (op_mode
,
7253 force_to_mode (XEXP (x
, 0), mode
, mask
,
7255 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7256 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7260 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7261 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7262 which is equal to STORE_FLAG_VALUE. */
7263 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7264 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7265 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7266 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7271 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7272 written in a narrower mode. We play it safe and do not do so. */
7275 gen_lowpart_for_combine (GET_MODE (x
),
7276 force_to_mode (XEXP (x
, 1), mode
,
7277 mask
, reg
, next_select
)));
7279 gen_lowpart_for_combine (GET_MODE (x
),
7280 force_to_mode (XEXP (x
, 2), mode
,
7281 mask
, reg
,next_select
)));
7288 /* Ensure we return a value of the proper mode. */
7289 return gen_lowpart_for_combine (mode
, x
);
7292 /* Return nonzero if X is an expression that has one of two values depending on
7293 whether some other value is zero or nonzero. In that case, we return the
7294 value that is being tested, *PTRUE is set to the value if the rtx being
7295 returned has a nonzero value, and *PFALSE is set to the other alternative.
7297 If we return zero, we set *PTRUE and *PFALSE to X. */
7300 if_then_else_cond (x
, ptrue
, pfalse
)
7302 rtx
*ptrue
, *pfalse
;
7304 enum machine_mode mode
= GET_MODE (x
);
7305 enum rtx_code code
= GET_CODE (x
);
7306 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7307 unsigned HOST_WIDE_INT nz
;
7309 /* If we are comparing a value against zero, we are done. */
7310 if ((code
== NE
|| code
== EQ
)
7311 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7313 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7314 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7318 /* If this is a unary operation whose operand has one of two values, apply
7319 our opcode to compute those values. */
7320 else if (GET_RTX_CLASS (code
) == '1'
7321 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7323 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7324 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7325 GET_MODE (XEXP (x
, 0)));
7329 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7330 make can't possibly match and would suppress other optimizations. */
7331 else if (code
== COMPARE
)
7334 /* If this is a binary operation, see if either side has only one of two
7335 values. If either one does or if both do and they are conditional on
7336 the same value, compute the new true and false values. */
7337 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7338 || GET_RTX_CLASS (code
) == '<')
7340 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7341 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7343 if ((cond0
!= 0 || cond1
!= 0)
7344 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7346 /* If if_then_else_cond returned zero, then true/false are the
7347 same rtl. We must copy one of them to prevent invalid rtl
7350 true0
= copy_rtx (true0
);
7351 else if (cond1
== 0)
7352 true1
= copy_rtx (true1
);
7354 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7355 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7356 return cond0
? cond0
: cond1
;
7359 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7360 operands is zero when the other is non-zero, and vice-versa,
7361 and STORE_FLAG_VALUE is 1 or -1. */
7363 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7364 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7366 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7368 rtx op0
= XEXP (XEXP (x
, 0), 1);
7369 rtx op1
= XEXP (XEXP (x
, 1), 1);
7371 cond0
= XEXP (XEXP (x
, 0), 0);
7372 cond1
= XEXP (XEXP (x
, 1), 0);
7374 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7375 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7376 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7377 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7378 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7379 || ((swap_condition (GET_CODE (cond0
))
7380 == combine_reversed_comparison_code (cond1
))
7381 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7382 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7383 && ! side_effects_p (x
))
7385 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7386 *pfalse
= gen_binary (MULT
, mode
,
7388 ? simplify_gen_unary (NEG
, mode
, op1
,
7396 /* Similarly for MULT, AND and UMIN, except that for these the result
7398 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7399 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7400 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7402 cond0
= XEXP (XEXP (x
, 0), 0);
7403 cond1
= XEXP (XEXP (x
, 1), 0);
7405 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7406 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7407 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7408 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7409 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7410 || ((swap_condition (GET_CODE (cond0
))
7411 == combine_reversed_comparison_code (cond1
))
7412 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7413 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7414 && ! side_effects_p (x
))
7416 *ptrue
= *pfalse
= const0_rtx
;
7422 else if (code
== IF_THEN_ELSE
)
7424 /* If we have IF_THEN_ELSE already, extract the condition and
7425 canonicalize it if it is NE or EQ. */
7426 cond0
= XEXP (x
, 0);
7427 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7428 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7429 return XEXP (cond0
, 0);
7430 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7432 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7433 return XEXP (cond0
, 0);
7439 /* If X is a SUBREG, we can narrow both the true and false values
7440 if the inner expression, if there is a condition. */
7441 else if (code
== SUBREG
7442 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7445 *ptrue
= simplify_gen_subreg (mode
, true0
,
7446 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7447 *pfalse
= simplify_gen_subreg (mode
, false0
,
7448 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7453 /* If X is a constant, this isn't special and will cause confusions
7454 if we treat it as such. Likewise if it is equivalent to a constant. */
7455 else if (CONSTANT_P (x
)
7456 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7459 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7460 will be least confusing to the rest of the compiler. */
7461 else if (mode
== BImode
)
7463 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7467 /* If X is known to be either 0 or -1, those are the true and
7468 false values when testing X. */
7469 else if (x
== constm1_rtx
|| x
== const0_rtx
7470 || (mode
!= VOIDmode
7471 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7473 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7477 /* Likewise for 0 or a single bit. */
7478 else if (mode
!= VOIDmode
7479 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7480 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7482 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7486 /* Otherwise fail; show no condition with true and false values the same. */
7487 *ptrue
= *pfalse
= x
;
7491 /* Return the value of expression X given the fact that condition COND
7492 is known to be true when applied to REG as its first operand and VAL
7493 as its second. X is known to not be shared and so can be modified in
7496 We only handle the simplest cases, and specifically those cases that
7497 arise with IF_THEN_ELSE expressions. */
7500 known_cond (x
, cond
, reg
, val
)
7505 enum rtx_code code
= GET_CODE (x
);
7510 if (side_effects_p (x
))
7513 /* If either operand of the condition is a floating point value,
7514 then we have to avoid collapsing an EQ comparison. */
7516 && rtx_equal_p (x
, reg
)
7517 && ! FLOAT_MODE_P (GET_MODE (x
))
7518 && ! FLOAT_MODE_P (GET_MODE (val
)))
7521 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7524 /* If X is (abs REG) and we know something about REG's relationship
7525 with zero, we may be able to simplify this. */
7527 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7530 case GE
: case GT
: case EQ
:
7533 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7535 GET_MODE (XEXP (x
, 0)));
7540 /* The only other cases we handle are MIN, MAX, and comparisons if the
7541 operands are the same as REG and VAL. */
7543 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7545 if (rtx_equal_p (XEXP (x
, 0), val
))
7546 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7548 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7550 if (GET_RTX_CLASS (code
) == '<')
7552 if (comparison_dominates_p (cond
, code
))
7553 return const_true_rtx
;
7555 code
= combine_reversed_comparison_code (x
);
7557 && comparison_dominates_p (cond
, code
))
7562 else if (code
== SMAX
|| code
== SMIN
7563 || code
== UMIN
|| code
== UMAX
)
7565 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7567 /* Do not reverse the condition when it is NE or EQ.
7568 This is because we cannot conclude anything about
7569 the value of 'SMAX (x, y)' when x is not equal to y,
7570 but we can when x equals y. */
7571 if ((code
== SMAX
|| code
== UMAX
)
7572 && ! (cond
== EQ
|| cond
== NE
))
7573 cond
= reverse_condition (cond
);
7578 return unsignedp
? x
: XEXP (x
, 1);
7580 return unsignedp
? x
: XEXP (x
, 0);
7582 return unsignedp
? XEXP (x
, 1) : x
;
7584 return unsignedp
? XEXP (x
, 0) : x
;
7591 else if (code
== SUBREG
)
7593 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7594 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7596 if (SUBREG_REG (x
) != r
)
7598 /* We must simplify subreg here, before we lose track of the
7599 original inner_mode. */
7600 new = simplify_subreg (GET_MODE (x
), r
,
7601 inner_mode
, SUBREG_BYTE (x
));
7605 SUBST (SUBREG_REG (x
), r
);
7610 /* We don't have to handle SIGN_EXTEND here, because even in the
7611 case of replacing something with a modeless CONST_INT, a
7612 CONST_INT is already (supposed to be) a valid sign extension for
7613 its narrower mode, which implies it's already properly
7614 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7615 story is different. */
7616 else if (code
== ZERO_EXTEND
)
7618 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7619 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7621 if (XEXP (x
, 0) != r
)
7623 /* We must simplify the zero_extend here, before we lose
7624 track of the original inner_mode. */
7625 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7630 SUBST (XEXP (x
, 0), r
);
7636 fmt
= GET_RTX_FORMAT (code
);
7637 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7640 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7641 else if (fmt
[i
] == 'E')
7642 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7643 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7650 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7651 assignment as a field assignment. */
7654 rtx_equal_for_field_assignment_p (x
, y
)
7658 if (x
== y
|| rtx_equal_p (x
, y
))
7661 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7664 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7665 Note that all SUBREGs of MEM are paradoxical; otherwise they
7666 would have been rewritten. */
7667 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7668 && GET_CODE (SUBREG_REG (y
)) == MEM
7669 && rtx_equal_p (SUBREG_REG (y
),
7670 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7673 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7674 && GET_CODE (SUBREG_REG (x
)) == MEM
7675 && rtx_equal_p (SUBREG_REG (x
),
7676 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7679 /* We used to see if get_last_value of X and Y were the same but that's
7680 not correct. In one direction, we'll cause the assignment to have
7681 the wrong destination and in the case, we'll import a register into this
7682 insn that might have already have been dead. So fail if none of the
7683 above cases are true. */
7687 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7688 Return that assignment if so.
7690 We only handle the most common cases. */
7693 make_field_assignment (x
)
7696 rtx dest
= SET_DEST (x
);
7697 rtx src
= SET_SRC (x
);
7702 unsigned HOST_WIDE_INT len
;
7704 enum machine_mode mode
;
7706 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7707 a clear of a one-bit field. We will have changed it to
7708 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7711 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7712 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7713 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7714 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7716 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7719 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7723 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7724 && subreg_lowpart_p (XEXP (src
, 0))
7725 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7726 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7727 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7728 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7729 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7731 assign
= make_extraction (VOIDmode
, dest
, 0,
7732 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7735 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7739 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7741 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7742 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7743 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7745 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7748 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7752 /* The other case we handle is assignments into a constant-position
7753 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7754 a mask that has all one bits except for a group of zero bits and
7755 OTHER is known to have zeros where C1 has ones, this is such an
7756 assignment. Compute the position and length from C1. Shift OTHER
7757 to the appropriate position, force it to the required mode, and
7758 make the extraction. Check for the AND in both operands. */
7760 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7763 rhs
= expand_compound_operation (XEXP (src
, 0));
7764 lhs
= expand_compound_operation (XEXP (src
, 1));
7766 if (GET_CODE (rhs
) == AND
7767 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7768 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7769 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7770 else if (GET_CODE (lhs
) == AND
7771 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7772 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7773 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7777 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7778 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7779 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7780 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7783 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7787 /* The mode to use for the source is the mode of the assignment, or of
7788 what is inside a possible STRICT_LOW_PART. */
7789 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7790 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7792 /* Shift OTHER right POS places and make it the source, restricting it
7793 to the proper length and mode. */
7795 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7796 GET_MODE (src
), other
, pos
),
7798 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7799 ? ~(unsigned HOST_WIDE_INT
) 0
7800 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7803 return gen_rtx_SET (VOIDmode
, assign
, src
);
7806 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7810 apply_distributive_law (x
)
7813 enum rtx_code code
= GET_CODE (x
);
7814 rtx lhs
, rhs
, other
;
7816 enum rtx_code inner_code
;
7818 /* Distributivity is not true for floating point.
7819 It can change the value. So don't do it.
7820 -- rms and moshier@world.std.com. */
7821 if (FLOAT_MODE_P (GET_MODE (x
)))
7824 /* The outer operation can only be one of the following: */
7825 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7826 && code
!= PLUS
&& code
!= MINUS
)
7829 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7831 /* If either operand is a primitive we can't do anything, so get out
7833 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7834 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7837 lhs
= expand_compound_operation (lhs
);
7838 rhs
= expand_compound_operation (rhs
);
7839 inner_code
= GET_CODE (lhs
);
7840 if (inner_code
!= GET_CODE (rhs
))
7843 /* See if the inner and outer operations distribute. */
7850 /* These all distribute except over PLUS. */
7851 if (code
== PLUS
|| code
== MINUS
)
7856 if (code
!= PLUS
&& code
!= MINUS
)
7861 /* This is also a multiply, so it distributes over everything. */
7865 /* Non-paradoxical SUBREGs distributes over all operations, provided
7866 the inner modes and byte offsets are the same, this is an extraction
7867 of a low-order part, we don't convert an fp operation to int or
7868 vice versa, and we would not be converting a single-word
7869 operation into a multi-word operation. The latter test is not
7870 required, but it prevents generating unneeded multi-word operations.
7871 Some of the previous tests are redundant given the latter test, but
7872 are retained because they are required for correctness.
7874 We produce the result slightly differently in this case. */
7876 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7877 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7878 || ! subreg_lowpart_p (lhs
)
7879 || (GET_MODE_CLASS (GET_MODE (lhs
))
7880 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7881 || (GET_MODE_SIZE (GET_MODE (lhs
))
7882 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7883 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7886 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7887 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7888 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7894 /* Set LHS and RHS to the inner operands (A and B in the example
7895 above) and set OTHER to the common operand (C in the example).
7896 These is only one way to do this unless the inner operation is
7898 if (GET_RTX_CLASS (inner_code
) == 'c'
7899 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7900 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7901 else if (GET_RTX_CLASS (inner_code
) == 'c'
7902 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7903 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7904 else if (GET_RTX_CLASS (inner_code
) == 'c'
7905 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7906 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7907 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7908 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7912 /* Form the new inner operation, seeing if it simplifies first. */
7913 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7915 /* There is one exception to the general way of distributing:
7916 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7917 if (code
== XOR
&& inner_code
== IOR
)
7920 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7923 /* We may be able to continuing distributing the result, so call
7924 ourselves recursively on the inner operation before forming the
7925 outer operation, which we return. */
7926 return gen_binary (inner_code
, GET_MODE (x
),
7927 apply_distributive_law (tem
), other
);
7930 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7933 Return an equivalent form, if different from X. Otherwise, return X. If
7934 X is zero, we are to always construct the equivalent form. */
7937 simplify_and_const_int (x
, mode
, varop
, constop
)
7939 enum machine_mode mode
;
7941 unsigned HOST_WIDE_INT constop
;
7943 unsigned HOST_WIDE_INT nonzero
;
7946 /* Simplify VAROP knowing that we will be only looking at some of the
7949 Note by passing in CONSTOP, we guarantee that the bits not set in
7950 CONSTOP are not significant and will never be examined. We must
7951 ensure that is the case by explicitly masking out those bits
7952 before returning. */
7953 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7955 /* If VAROP is a CLOBBER, we will fail so return it. */
7956 if (GET_CODE (varop
) == CLOBBER
)
7959 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7960 to VAROP and return the new constant. */
7961 if (GET_CODE (varop
) == CONST_INT
)
7962 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7964 /* See what bits may be nonzero in VAROP. Unlike the general case of
7965 a call to nonzero_bits, here we don't care about bits outside
7968 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7970 /* Turn off all bits in the constant that are known to already be zero.
7971 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7972 which is tested below. */
7976 /* If we don't have any bits left, return zero. */
7980 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7981 a power of two, we can replace this with an ASHIFT. */
7982 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7983 && (i
= exact_log2 (constop
)) >= 0)
7984 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7986 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7987 or XOR, then try to apply the distributive law. This may eliminate
7988 operations if either branch can be simplified because of the AND.
7989 It may also make some cases more complex, but those cases probably
7990 won't match a pattern either with or without this. */
7992 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7994 gen_lowpart_for_combine
7996 apply_distributive_law
7997 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7998 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7999 XEXP (varop
, 0), constop
),
8000 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8001 XEXP (varop
, 1), constop
))));
8003 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8004 the AND and see if one of the operands simplifies to zero. If so, we
8005 may eliminate it. */
8007 if (GET_CODE (varop
) == PLUS
8008 && exact_log2 (constop
+ 1) >= 0)
8012 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8013 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8014 if (o0
== const0_rtx
)
8016 if (o1
== const0_rtx
)
8020 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8021 if we already had one (just check for the simplest cases). */
8022 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8023 && GET_MODE (XEXP (x
, 0)) == mode
8024 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8025 varop
= XEXP (x
, 0);
8027 varop
= gen_lowpart_for_combine (mode
, varop
);
8029 /* If we can't make the SUBREG, try to return what we were given. */
8030 if (GET_CODE (varop
) == CLOBBER
)
8031 return x
? x
: varop
;
8033 /* If we are only masking insignificant bits, return VAROP. */
8034 if (constop
== nonzero
)
8038 /* Otherwise, return an AND. */
8039 constop
= trunc_int_for_mode (constop
, mode
);
8040 /* See how much, if any, of X we can use. */
8041 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8042 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8046 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8047 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8048 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8050 SUBST (XEXP (x
, 0), varop
);
8057 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8058 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8059 is less useful. We can't allow both, because that results in exponential
8060 run time recursion. There is a nullstone testcase that triggered
8061 this. This macro avoids accidental uses of num_sign_bit_copies. */
8062 #define num_sign_bit_copies()
8064 /* Given an expression, X, compute which bits in X can be non-zero.
8065 We don't care about bits outside of those defined in MODE.
8067 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8068 a shift, AND, or zero_extract, we can do better. */
8070 static unsigned HOST_WIDE_INT
8071 nonzero_bits (x
, mode
)
8073 enum machine_mode mode
;
8075 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8076 unsigned HOST_WIDE_INT inner_nz
;
8078 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8081 /* For floating-point values, assume all bits are needed. */
8082 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8085 /* If X is wider than MODE, use its mode instead. */
8086 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8088 mode
= GET_MODE (x
);
8089 nonzero
= GET_MODE_MASK (mode
);
8090 mode_width
= GET_MODE_BITSIZE (mode
);
8093 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8094 /* Our only callers in this case look for single bit values. So
8095 just return the mode mask. Those tests will then be false. */
8098 #ifndef WORD_REGISTER_OPERATIONS
8099 /* If MODE is wider than X, but both are a single word for both the host
8100 and target machines, we can compute this from which bits of the
8101 object might be nonzero in its own mode, taking into account the fact
8102 that on many CISC machines, accessing an object in a wider mode
8103 causes the high-order bits to become undefined. So they are
8104 not known to be zero. */
8106 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8107 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8108 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8109 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8111 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
8112 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8117 code
= GET_CODE (x
);
8121 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8122 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8123 all the bits above ptr_mode are known to be zero. */
8124 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8126 nonzero
&= GET_MODE_MASK (ptr_mode
);
8129 /* Include declared information about alignment of pointers. */
8130 /* ??? We don't properly preserve REG_POINTER changes across
8131 pointer-to-integer casts, so we can't trust it except for
8132 things that we know must be pointers. See execute/960116-1.c. */
8133 if ((x
== stack_pointer_rtx
8134 || x
== frame_pointer_rtx
8135 || x
== arg_pointer_rtx
)
8136 && REGNO_POINTER_ALIGN (REGNO (x
)))
8138 unsigned HOST_WIDE_INT alignment
8139 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8141 #ifdef PUSH_ROUNDING
8142 /* If PUSH_ROUNDING is defined, it is possible for the
8143 stack to be momentarily aligned only to that amount,
8144 so we pick the least alignment. */
8145 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8146 alignment
= MIN (PUSH_ROUNDING (1), alignment
);
8149 nonzero
&= ~(alignment
- 1);
8152 /* If X is a register whose nonzero bits value is current, use it.
8153 Otherwise, if X is a register whose value we can find, use that
8154 value. Otherwise, use the previously-computed global nonzero bits
8155 for this register. */
8157 if (reg_last_set_value
[REGNO (x
)] != 0
8158 && (reg_last_set_mode
[REGNO (x
)] == mode
8159 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8160 && GET_MODE_CLASS (mode
) == MODE_INT
))
8161 && (reg_last_set_label
[REGNO (x
)] == label_tick
8162 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8163 && REG_N_SETS (REGNO (x
)) == 1
8164 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8166 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8167 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8169 tem
= get_last_value (x
);
8173 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8174 /* If X is narrower than MODE and TEM is a non-negative
8175 constant that would appear negative in the mode of X,
8176 sign-extend it for use in reg_nonzero_bits because some
8177 machines (maybe most) will actually do the sign-extension
8178 and this is the conservative approach.
8180 ??? For 2.5, try to tighten up the MD files in this regard
8181 instead of this kludge. */
8183 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8184 && GET_CODE (tem
) == CONST_INT
8186 && 0 != (INTVAL (tem
)
8187 & ((HOST_WIDE_INT
) 1
8188 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8189 tem
= GEN_INT (INTVAL (tem
)
8190 | ((HOST_WIDE_INT
) (-1)
8191 << GET_MODE_BITSIZE (GET_MODE (x
))));
8193 return nonzero_bits (tem
, mode
) & nonzero
;
8195 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8197 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8199 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8200 /* We don't know anything about the upper bits. */
8201 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8202 return nonzero
& mask
;
8208 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8209 /* If X is negative in MODE, sign-extend the value. */
8210 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8211 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8212 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8218 #ifdef LOAD_EXTEND_OP
8219 /* In many, if not most, RISC machines, reading a byte from memory
8220 zeros the rest of the register. Noticing that fact saves a lot
8221 of extra zero-extends. */
8222 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8223 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8228 case UNEQ
: case LTGT
:
8229 case GT
: case GTU
: case UNGT
:
8230 case LT
: case LTU
: case UNLT
:
8231 case GE
: case GEU
: case UNGE
:
8232 case LE
: case LEU
: case UNLE
:
8233 case UNORDERED
: case ORDERED
:
8235 /* If this produces an integer result, we know which bits are set.
8236 Code here used to clear bits outside the mode of X, but that is
8239 if (GET_MODE_CLASS (mode
) == MODE_INT
8240 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8241 nonzero
= STORE_FLAG_VALUE
;
8246 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8247 and num_sign_bit_copies. */
8248 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8249 == GET_MODE_BITSIZE (GET_MODE (x
)))
8253 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8254 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8259 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8260 and num_sign_bit_copies. */
8261 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8262 == GET_MODE_BITSIZE (GET_MODE (x
)))
8268 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8272 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8273 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8274 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8278 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8279 Otherwise, show all the bits in the outer mode but not the inner
8281 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8282 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8284 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8286 & (((HOST_WIDE_INT
) 1
8287 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8288 inner_nz
|= (GET_MODE_MASK (mode
)
8289 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8292 nonzero
&= inner_nz
;
8296 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8297 & nonzero_bits (XEXP (x
, 1), mode
));
8301 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8303 unsigned HOST_WIDE_INT nonzero0
= nonzero_bits (XEXP (x
, 0), mode
);
8305 /* Don't call nonzero_bits for the second time if it cannot change
8307 if ((nonzero
& nonzero0
) != nonzero
)
8308 nonzero
&= (nonzero0
| nonzero_bits (XEXP (x
, 1), mode
));
8312 case PLUS
: case MINUS
:
8314 case DIV
: case UDIV
:
8315 case MOD
: case UMOD
:
8316 /* We can apply the rules of arithmetic to compute the number of
8317 high- and low-order zero bits of these operations. We start by
8318 computing the width (position of the highest-order non-zero bit)
8319 and the number of low-order zero bits for each value. */
8321 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8322 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8323 int width0
= floor_log2 (nz0
) + 1;
8324 int width1
= floor_log2 (nz1
) + 1;
8325 int low0
= floor_log2 (nz0
& -nz0
);
8326 int low1
= floor_log2 (nz1
& -nz1
);
8327 HOST_WIDE_INT op0_maybe_minusp
8328 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8329 HOST_WIDE_INT op1_maybe_minusp
8330 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8331 unsigned int result_width
= mode_width
;
8337 result_width
= MAX (width0
, width1
) + 1;
8338 result_low
= MIN (low0
, low1
);
8341 result_low
= MIN (low0
, low1
);
8344 result_width
= width0
+ width1
;
8345 result_low
= low0
+ low1
;
8350 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8351 result_width
= width0
;
8356 result_width
= width0
;
8361 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8362 result_width
= MIN (width0
, width1
);
8363 result_low
= MIN (low0
, low1
);
8368 result_width
= MIN (width0
, width1
);
8369 result_low
= MIN (low0
, low1
);
8375 if (result_width
< mode_width
)
8376 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8379 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8381 #ifdef POINTERS_EXTEND_UNSIGNED
8382 /* If pointers extend unsigned and this is an addition or subtraction
8383 to a pointer in Pmode, all the bits above ptr_mode are known to be
8385 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8386 && (code
== PLUS
|| code
== MINUS
)
8387 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8388 nonzero
&= GET_MODE_MASK (ptr_mode
);
8394 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8395 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8396 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8400 /* If this is a SUBREG formed for a promoted variable that has
8401 been zero-extended, we know that at least the high-order bits
8402 are zero, though others might be too. */
8404 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8405 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8406 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8408 /* If the inner mode is a single word for both the host and target
8409 machines, we can compute this from which bits of the inner
8410 object might be nonzero. */
8411 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8412 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8413 <= HOST_BITS_PER_WIDE_INT
))
8415 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8417 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8418 /* If this is a typical RISC machine, we only have to worry
8419 about the way loads are extended. */
8420 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8422 & (((unsigned HOST_WIDE_INT
) 1
8423 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8425 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8426 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8429 /* On many CISC machines, accessing an object in a wider mode
8430 causes the high-order bits to become undefined. So they are
8431 not known to be zero. */
8432 if (GET_MODE_SIZE (GET_MODE (x
))
8433 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8434 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8435 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8444 /* The nonzero bits are in two classes: any bits within MODE
8445 that aren't in GET_MODE (x) are always significant. The rest of the
8446 nonzero bits are those that are significant in the operand of
8447 the shift when shifted the appropriate number of bits. This
8448 shows that high-order bits are cleared by the right shift and
8449 low-order bits by left shifts. */
8450 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8451 && INTVAL (XEXP (x
, 1)) >= 0
8452 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8454 enum machine_mode inner_mode
= GET_MODE (x
);
8455 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8456 int count
= INTVAL (XEXP (x
, 1));
8457 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8458 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8459 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8460 unsigned HOST_WIDE_INT outer
= 0;
8462 if (mode_width
> width
)
8463 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8465 if (code
== LSHIFTRT
)
8467 else if (code
== ASHIFTRT
)
8471 /* If the sign bit may have been nonzero before the shift, we
8472 need to mark all the places it could have been copied to
8473 by the shift as possibly nonzero. */
8474 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8475 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8477 else if (code
== ASHIFT
)
8480 inner
= ((inner
<< (count
% width
)
8481 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8483 nonzero
&= (outer
| inner
);
8488 /* This is at most the number of bits in the mode. */
8489 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8493 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8494 | nonzero_bits (XEXP (x
, 2), mode
));
8504 /* See the macro definition above. */
8505 #undef num_sign_bit_copies
8507 /* Return the number of bits at the high-order end of X that are known to
8508 be equal to the sign bit. X will be used in mode MODE; if MODE is
8509 VOIDmode, X will be used in its own mode. The returned value will always
8510 be between 1 and the number of bits in MODE. */
8513 num_sign_bit_copies (x
, mode
)
8515 enum machine_mode mode
;
8517 enum rtx_code code
= GET_CODE (x
);
8518 unsigned int bitwidth
;
8519 int num0
, num1
, result
;
8520 unsigned HOST_WIDE_INT nonzero
;
8523 /* If we weren't given a mode, use the mode of X. If the mode is still
8524 VOIDmode, we don't know anything. Likewise if one of the modes is
8527 if (mode
== VOIDmode
)
8528 mode
= GET_MODE (x
);
8530 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8533 bitwidth
= GET_MODE_BITSIZE (mode
);
8535 /* For a smaller object, just ignore the high bits. */
8536 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8538 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8540 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8543 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8545 #ifndef WORD_REGISTER_OPERATIONS
8546 /* If this machine does not do all register operations on the entire
8547 register and MODE is wider than the mode of X, we can say nothing
8548 at all about the high-order bits. */
8551 /* Likewise on machines that do, if the mode of the object is smaller
8552 than a word and loads of that size don't sign extend, we can say
8553 nothing about the high order bits. */
8554 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8555 #ifdef LOAD_EXTEND_OP
8556 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8567 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8568 /* If pointers extend signed and this is a pointer in Pmode, say that
8569 all the bits above ptr_mode are known to be sign bit copies. */
8570 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8572 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8575 if (reg_last_set_value
[REGNO (x
)] != 0
8576 && reg_last_set_mode
[REGNO (x
)] == mode
8577 && (reg_last_set_label
[REGNO (x
)] == label_tick
8578 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8579 && REG_N_SETS (REGNO (x
)) == 1
8580 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8582 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8583 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8585 tem
= get_last_value (x
);
8587 return num_sign_bit_copies (tem
, mode
);
8589 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8590 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8591 return reg_sign_bit_copies
[REGNO (x
)];
8595 #ifdef LOAD_EXTEND_OP
8596 /* Some RISC machines sign-extend all loads of smaller than a word. */
8597 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8598 return MAX (1, ((int) bitwidth
8599 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8604 /* If the constant is negative, take its 1's complement and remask.
8605 Then see how many zero bits we have. */
8606 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8607 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8608 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8609 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8611 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8614 /* If this is a SUBREG for a promoted object that is sign-extended
8615 and we are looking at it in a wider mode, we know that at least the
8616 high-order bits are known to be sign bit copies. */
8618 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8620 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8621 return MAX ((int) bitwidth
8622 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8626 /* For a smaller object, just ignore the high bits. */
8627 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8629 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8630 return MAX (1, (num0
8631 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8635 #ifdef WORD_REGISTER_OPERATIONS
8636 #ifdef LOAD_EXTEND_OP
8637 /* For paradoxical SUBREGs on machines where all register operations
8638 affect the entire register, just look inside. Note that we are
8639 passing MODE to the recursive call, so the number of sign bit copies
8640 will remain relative to that mode, not the inner mode. */
8642 /* This works only if loads sign extend. Otherwise, if we get a
8643 reload for the inner part, it may be loaded from the stack, and
8644 then we lose all sign bit copies that existed before the store
8647 if ((GET_MODE_SIZE (GET_MODE (x
))
8648 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8649 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8650 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8651 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8657 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8658 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8662 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8663 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8666 /* For a smaller object, just ignore the high bits. */
8667 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8668 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8672 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8674 case ROTATE
: case ROTATERT
:
8675 /* If we are rotating left by a number of bits less than the number
8676 of sign bit copies, we can just subtract that amount from the
8678 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8679 && INTVAL (XEXP (x
, 1)) >= 0
8680 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8682 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8683 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8684 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8689 /* In general, this subtracts one sign bit copy. But if the value
8690 is known to be positive, the number of sign bit copies is the
8691 same as that of the input. Finally, if the input has just one bit
8692 that might be nonzero, all the bits are copies of the sign bit. */
8693 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8694 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8695 return num0
> 1 ? num0
- 1 : 1;
8697 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8702 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8707 case IOR
: case AND
: case XOR
:
8708 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8709 /* Logical operations will preserve the number of sign-bit copies.
8710 MIN and MAX operations always return one of the operands. */
8711 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8712 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8713 return MIN (num0
, num1
);
8715 case PLUS
: case MINUS
:
8716 /* For addition and subtraction, we can have a 1-bit carry. However,
8717 if we are subtracting 1 from a positive number, there will not
8718 be such a carry. Furthermore, if the positive number is known to
8719 be 0 or 1, we know the result is either -1 or 0. */
8721 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8722 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8724 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8725 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8726 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8727 : bitwidth
- floor_log2 (nonzero
) - 1);
8730 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8731 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8732 result
= MAX (1, MIN (num0
, num1
) - 1);
8734 #ifdef POINTERS_EXTEND_UNSIGNED
8735 /* If pointers extend signed and this is an addition or subtraction
8736 to a pointer in Pmode, all the bits above ptr_mode are known to be
8738 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8739 && (code
== PLUS
|| code
== MINUS
)
8740 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8741 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8742 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8748 /* The number of bits of the product is the sum of the number of
8749 bits of both terms. However, unless one of the terms if known
8750 to be positive, we must allow for an additional bit since negating
8751 a negative number can remove one sign bit copy. */
8753 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8754 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8756 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8758 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8759 || (((nonzero_bits (XEXP (x
, 0), mode
)
8760 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8761 && ((nonzero_bits (XEXP (x
, 1), mode
)
8762 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8765 return MAX (1, result
);
8768 /* The result must be <= the first operand. If the first operand
8769 has the high bit set, we know nothing about the number of sign
8771 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8773 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8774 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8777 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8780 /* The result must be <= the second operand. */
8781 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8784 /* Similar to unsigned division, except that we have to worry about
8785 the case where the divisor is negative, in which case we have
8787 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8789 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8790 || (nonzero_bits (XEXP (x
, 1), mode
)
8791 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8797 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8799 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8800 || (nonzero_bits (XEXP (x
, 1), mode
)
8801 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8807 /* Shifts by a constant add to the number of bits equal to the
8809 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8810 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8811 && INTVAL (XEXP (x
, 1)) > 0)
8812 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8817 /* Left shifts destroy copies. */
8818 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8819 || INTVAL (XEXP (x
, 1)) < 0
8820 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8823 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8824 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8827 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8828 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8829 return MIN (num0
, num1
);
8831 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8832 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8833 case GEU
: case GTU
: case LEU
: case LTU
:
8834 case UNORDERED
: case ORDERED
:
8835 /* If the constant is negative, take its 1's complement and remask.
8836 Then see how many zero bits we have. */
8837 nonzero
= STORE_FLAG_VALUE
;
8838 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8839 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8840 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8842 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8849 /* If we haven't been able to figure it out by one of the above rules,
8850 see if some of the high-order bits are known to be zero. If so,
8851 count those bits and return one less than that amount. If we can't
8852 safely compute the mask for this mode, always return BITWIDTH. */
8854 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8857 nonzero
= nonzero_bits (x
, mode
);
8858 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8859 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8862 /* Return the number of "extended" bits there are in X, when interpreted
8863 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8864 unsigned quantities, this is the number of high-order zero bits.
8865 For signed quantities, this is the number of copies of the sign bit
8866 minus 1. In both case, this function returns the number of "spare"
8867 bits. For example, if two quantities for which this function returns
8868 at least 1 are added, the addition is known not to overflow.
8870 This function will always return 0 unless called during combine, which
8871 implies that it must be called from a define_split. */
8874 extended_count (x
, mode
, unsignedp
)
8876 enum machine_mode mode
;
8879 if (nonzero_sign_valid
== 0)
8883 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8884 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8885 - floor_log2 (nonzero_bits (x
, mode
)))
8887 : num_sign_bit_copies (x
, mode
) - 1);
8890 /* This function is called from `simplify_shift_const' to merge two
8891 outer operations. Specifically, we have already found that we need
8892 to perform operation *POP0 with constant *PCONST0 at the outermost
8893 position. We would now like to also perform OP1 with constant CONST1
8894 (with *POP0 being done last).
8896 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8897 the resulting operation. *PCOMP_P is set to 1 if we would need to
8898 complement the innermost operand, otherwise it is unchanged.
8900 MODE is the mode in which the operation will be done. No bits outside
8901 the width of this mode matter. It is assumed that the width of this mode
8902 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8904 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8905 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8906 result is simply *PCONST0.
8908 If the resulting operation cannot be expressed as one operation, we
8909 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8912 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8913 enum rtx_code
*pop0
;
8914 HOST_WIDE_INT
*pconst0
;
8916 HOST_WIDE_INT const1
;
8917 enum machine_mode mode
;
8920 enum rtx_code op0
= *pop0
;
8921 HOST_WIDE_INT const0
= *pconst0
;
8923 const0
&= GET_MODE_MASK (mode
);
8924 const1
&= GET_MODE_MASK (mode
);
8926 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8930 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8933 if (op1
== NIL
|| op0
== SET
)
8936 else if (op0
== NIL
)
8937 op0
= op1
, const0
= const1
;
8939 else if (op0
== op1
)
8963 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8964 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8967 /* If the two constants aren't the same, we can't do anything. The
8968 remaining six cases can all be done. */
8969 else if (const0
!= const1
)
8977 /* (a & b) | b == b */
8979 else /* op1 == XOR */
8980 /* (a ^ b) | b == a | b */
8986 /* (a & b) ^ b == (~a) & b */
8987 op0
= AND
, *pcomp_p
= 1;
8988 else /* op1 == IOR */
8989 /* (a | b) ^ b == a & ~b */
8990 op0
= AND
, *pconst0
= ~const0
;
8995 /* (a | b) & b == b */
8997 else /* op1 == XOR */
8998 /* (a ^ b) & b) == (~a) & b */
9005 /* Check for NO-OP cases. */
9006 const0
&= GET_MODE_MASK (mode
);
9008 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9010 else if (const0
== 0 && op0
== AND
)
9012 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9016 /* ??? Slightly redundant with the above mask, but not entirely.
9017 Moving this above means we'd have to sign-extend the mode mask
9018 for the final test. */
9019 const0
= trunc_int_for_mode (const0
, mode
);
9027 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9028 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
9029 that we started with.
9031 The shift is normally computed in the widest mode we find in VAROP, as
9032 long as it isn't a different number of words than RESULT_MODE. Exceptions
9033 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9036 simplify_shift_const (x
, code
, result_mode
, varop
, orig_count
)
9039 enum machine_mode result_mode
;
9043 enum rtx_code orig_code
= code
;
9046 enum machine_mode mode
= result_mode
;
9047 enum machine_mode shift_mode
, tmode
;
9048 unsigned int mode_words
9049 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9050 /* We form (outer_op (code varop count) (outer_const)). */
9051 enum rtx_code outer_op
= NIL
;
9052 HOST_WIDE_INT outer_const
= 0;
9054 int complement_p
= 0;
9057 /* Make sure and truncate the "natural" shift on the way in. We don't
9058 want to do this inside the loop as it makes it more difficult to
9060 #ifdef SHIFT_COUNT_TRUNCATED
9061 if (SHIFT_COUNT_TRUNCATED
)
9062 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9065 /* If we were given an invalid count, don't do anything except exactly
9066 what was requested. */
9068 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9073 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9078 /* Unless one of the branches of the `if' in this loop does a `continue',
9079 we will `break' the loop after the `if'. */
9083 /* If we have an operand of (clobber (const_int 0)), just return that
9085 if (GET_CODE (varop
) == CLOBBER
)
9088 /* If we discovered we had to complement VAROP, leave. Making a NOT
9089 here would cause an infinite loop. */
9093 /* Convert ROTATERT to ROTATE. */
9094 if (code
== ROTATERT
)
9096 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9098 if (VECTOR_MODE_P (result_mode
))
9099 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9101 count
= bitsize
- count
;
9104 /* We need to determine what mode we will do the shift in. If the
9105 shift is a right shift or a ROTATE, we must always do it in the mode
9106 it was originally done in. Otherwise, we can do it in MODE, the
9107 widest mode encountered. */
9109 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9110 ? result_mode
: mode
);
9112 /* Handle cases where the count is greater than the size of the mode
9113 minus 1. For ASHIFT, use the size minus one as the count (this can
9114 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9115 take the count modulo the size. For other shifts, the result is
9118 Since these shifts are being produced by the compiler by combining
9119 multiple operations, each of which are defined, we know what the
9120 result is supposed to be. */
9122 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9124 if (code
== ASHIFTRT
)
9125 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9126 else if (code
== ROTATE
|| code
== ROTATERT
)
9127 count
%= GET_MODE_BITSIZE (shift_mode
);
9130 /* We can't simply return zero because there may be an
9138 /* An arithmetic right shift of a quantity known to be -1 or 0
9140 if (code
== ASHIFTRT
9141 && (num_sign_bit_copies (varop
, shift_mode
)
9142 == GET_MODE_BITSIZE (shift_mode
)))
9148 /* If we are doing an arithmetic right shift and discarding all but
9149 the sign bit copies, this is equivalent to doing a shift by the
9150 bitsize minus one. Convert it into that shift because it will often
9151 allow other simplifications. */
9153 if (code
== ASHIFTRT
9154 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9155 >= GET_MODE_BITSIZE (shift_mode
)))
9156 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9158 /* We simplify the tests below and elsewhere by converting
9159 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9160 `make_compound_operation' will convert it to an ASHIFTRT for
9161 those machines (such as VAX) that don't have an LSHIFTRT. */
9162 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9164 && ((nonzero_bits (varop
, shift_mode
)
9165 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9169 switch (GET_CODE (varop
))
9175 new = expand_compound_operation (varop
);
9184 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9185 minus the width of a smaller mode, we can do this with a
9186 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9187 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9188 && ! mode_dependent_address_p (XEXP (varop
, 0))
9189 && ! MEM_VOLATILE_P (varop
)
9190 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9191 MODE_INT
, 1)) != BLKmode
)
9193 new = adjust_address_nv (varop
, tmode
,
9194 BYTES_BIG_ENDIAN
? 0
9195 : count
/ BITS_PER_UNIT
);
9197 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9198 : ZERO_EXTEND
, mode
, new);
9205 /* Similar to the case above, except that we can only do this if
9206 the resulting mode is the same as that of the underlying
9207 MEM and adjust the address depending on the *bits* endianness
9208 because of the way that bit-field extract insns are defined. */
9209 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9210 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9211 MODE_INT
, 1)) != BLKmode
9212 && tmode
== GET_MODE (XEXP (varop
, 0)))
9214 if (BITS_BIG_ENDIAN
)
9215 new = XEXP (varop
, 0);
9218 new = copy_rtx (XEXP (varop
, 0));
9219 SUBST (XEXP (new, 0),
9220 plus_constant (XEXP (new, 0),
9221 count
/ BITS_PER_UNIT
));
9224 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9225 : ZERO_EXTEND
, mode
, new);
9232 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9233 the same number of words as what we've seen so far. Then store
9234 the widest mode in MODE. */
9235 if (subreg_lowpart_p (varop
)
9236 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9237 > GET_MODE_SIZE (GET_MODE (varop
)))
9238 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9239 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9242 varop
= SUBREG_REG (varop
);
9243 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9244 mode
= GET_MODE (varop
);
9250 /* Some machines use MULT instead of ASHIFT because MULT
9251 is cheaper. But it is still better on those machines to
9252 merge two shifts into one. */
9253 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9254 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9257 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9258 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9264 /* Similar, for when divides are cheaper. */
9265 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9266 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9269 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9270 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9276 /* If we are extracting just the sign bit of an arithmetic
9277 right shift, that shift is not needed. However, the sign
9278 bit of a wider mode may be different from what would be
9279 interpreted as the sign bit in a narrower mode, so, if
9280 the result is narrower, don't discard the shift. */
9281 if (code
== LSHIFTRT
9282 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9283 && (GET_MODE_BITSIZE (result_mode
)
9284 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9286 varop
= XEXP (varop
, 0);
9290 /* ... fall through ... */
9295 /* Here we have two nested shifts. The result is usually the
9296 AND of a new shift with a mask. We compute the result below. */
9297 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9298 && INTVAL (XEXP (varop
, 1)) >= 0
9299 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9300 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9301 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9303 enum rtx_code first_code
= GET_CODE (varop
);
9304 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9305 unsigned HOST_WIDE_INT mask
;
9308 /* We have one common special case. We can't do any merging if
9309 the inner code is an ASHIFTRT of a smaller mode. However, if
9310 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9311 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9312 we can convert it to
9313 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9314 This simplifies certain SIGN_EXTEND operations. */
9315 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9316 && count
== (unsigned int)
9317 (GET_MODE_BITSIZE (result_mode
)
9318 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9320 /* C3 has the low-order C1 bits zero. */
9322 mask
= (GET_MODE_MASK (mode
)
9323 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9325 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9326 XEXP (varop
, 0), mask
);
9327 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9329 count
= first_count
;
9334 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9335 than C1 high-order bits equal to the sign bit, we can convert
9336 this to either an ASHIFT or an ASHIFTRT depending on the
9339 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9341 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9342 && GET_MODE (varop
) == shift_mode
9343 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9346 varop
= XEXP (varop
, 0);
9348 signed_count
= count
- first_count
;
9349 if (signed_count
< 0)
9350 count
= -signed_count
, code
= ASHIFT
;
9352 count
= signed_count
;
9357 /* There are some cases we can't do. If CODE is ASHIFTRT,
9358 we can only do this if FIRST_CODE is also ASHIFTRT.
9360 We can't do the case when CODE is ROTATE and FIRST_CODE is
9363 If the mode of this shift is not the mode of the outer shift,
9364 we can't do this if either shift is a right shift or ROTATE.
9366 Finally, we can't do any of these if the mode is too wide
9367 unless the codes are the same.
9369 Handle the case where the shift codes are the same
9372 if (code
== first_code
)
9374 if (GET_MODE (varop
) != result_mode
9375 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9379 count
+= first_count
;
9380 varop
= XEXP (varop
, 0);
9384 if (code
== ASHIFTRT
9385 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9386 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9387 || (GET_MODE (varop
) != result_mode
9388 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9389 || first_code
== ROTATE
9390 || code
== ROTATE
)))
9393 /* To compute the mask to apply after the shift, shift the
9394 nonzero bits of the inner shift the same way the
9395 outer shift will. */
9397 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9400 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9403 /* Give up if we can't compute an outer operation to use. */
9405 || GET_CODE (mask_rtx
) != CONST_INT
9406 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9408 result_mode
, &complement_p
))
9411 /* If the shifts are in the same direction, we add the
9412 counts. Otherwise, we subtract them. */
9413 signed_count
= count
;
9414 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9415 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9416 signed_count
+= first_count
;
9418 signed_count
-= first_count
;
9420 /* If COUNT is positive, the new shift is usually CODE,
9421 except for the two exceptions below, in which case it is
9422 FIRST_CODE. If the count is negative, FIRST_CODE should
9424 if (signed_count
> 0
9425 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9426 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9427 code
= first_code
, count
= signed_count
;
9428 else if (signed_count
< 0)
9429 code
= first_code
, count
= -signed_count
;
9431 count
= signed_count
;
9433 varop
= XEXP (varop
, 0);
9437 /* If we have (A << B << C) for any shift, we can convert this to
9438 (A << C << B). This wins if A is a constant. Only try this if
9439 B is not a constant. */
9441 else if (GET_CODE (varop
) == code
9442 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9444 = simplify_binary_operation (code
, mode
,
9448 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9455 /* Make this fit the case below. */
9456 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9457 GEN_INT (GET_MODE_MASK (mode
)));
9463 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9464 with C the size of VAROP - 1 and the shift is logical if
9465 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9466 we have an (le X 0) operation. If we have an arithmetic shift
9467 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9468 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9470 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9471 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9472 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9473 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9474 && count
== (unsigned int)
9475 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9476 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9479 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9482 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9483 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9488 /* If we have (shift (logical)), move the logical to the outside
9489 to allow it to possibly combine with another logical and the
9490 shift to combine with another shift. This also canonicalizes to
9491 what a ZERO_EXTRACT looks like. Also, some machines have
9492 (and (shift)) insns. */
9494 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9495 && (new = simplify_binary_operation (code
, result_mode
,
9497 GEN_INT (count
))) != 0
9498 && GET_CODE (new) == CONST_INT
9499 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9500 INTVAL (new), result_mode
, &complement_p
))
9502 varop
= XEXP (varop
, 0);
9506 /* If we can't do that, try to simplify the shift in each arm of the
9507 logical expression, make a new logical expression, and apply
9508 the inverse distributive law. */
9510 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9511 XEXP (varop
, 0), count
);
9512 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9513 XEXP (varop
, 1), count
);
9515 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9516 varop
= apply_distributive_law (varop
);
9523 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9524 says that the sign bit can be tested, FOO has mode MODE, C is
9525 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9526 that may be nonzero. */
9527 if (code
== LSHIFTRT
9528 && XEXP (varop
, 1) == const0_rtx
9529 && GET_MODE (XEXP (varop
, 0)) == result_mode
9530 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9531 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9532 && ((STORE_FLAG_VALUE
9533 & ((HOST_WIDE_INT
) 1
9534 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9535 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9536 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9537 (HOST_WIDE_INT
) 1, result_mode
,
9540 varop
= XEXP (varop
, 0);
9547 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9548 than the number of bits in the mode is equivalent to A. */
9549 if (code
== LSHIFTRT
9550 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9551 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9553 varop
= XEXP (varop
, 0);
9558 /* NEG commutes with ASHIFT since it is multiplication. Move the
9559 NEG outside to allow shifts to combine. */
9561 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9562 (HOST_WIDE_INT
) 0, result_mode
,
9565 varop
= XEXP (varop
, 0);
9571 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9572 is one less than the number of bits in the mode is
9573 equivalent to (xor A 1). */
9574 if (code
== LSHIFTRT
9575 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9576 && XEXP (varop
, 1) == constm1_rtx
9577 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9578 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9579 (HOST_WIDE_INT
) 1, result_mode
,
9583 varop
= XEXP (varop
, 0);
9587 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9588 that might be nonzero in BAR are those being shifted out and those
9589 bits are known zero in FOO, we can replace the PLUS with FOO.
9590 Similarly in the other operand order. This code occurs when
9591 we are computing the size of a variable-size array. */
9593 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9594 && count
< HOST_BITS_PER_WIDE_INT
9595 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9596 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9597 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9599 varop
= XEXP (varop
, 0);
9602 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9603 && count
< HOST_BITS_PER_WIDE_INT
9604 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9605 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9607 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9608 & nonzero_bits (XEXP (varop
, 1),
9611 varop
= XEXP (varop
, 1);
9615 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9617 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9618 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9620 GEN_INT (count
))) != 0
9621 && GET_CODE (new) == CONST_INT
9622 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9623 INTVAL (new), result_mode
, &complement_p
))
9625 varop
= XEXP (varop
, 0);
9631 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9632 with C the size of VAROP - 1 and the shift is logical if
9633 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9634 we have a (gt X 0) operation. If the shift is arithmetic with
9635 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9636 we have a (neg (gt X 0)) operation. */
9638 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9639 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9640 && count
== (unsigned int)
9641 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9642 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9643 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9644 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9646 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9649 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9652 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9653 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9660 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9661 if the truncate does not affect the value. */
9662 if (code
== LSHIFTRT
9663 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9664 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9665 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9666 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9667 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9669 rtx varop_inner
= XEXP (varop
, 0);
9672 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9673 XEXP (varop_inner
, 0),
9675 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9676 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9689 /* We need to determine what mode to do the shift in. If the shift is
9690 a right shift or ROTATE, we must always do it in the mode it was
9691 originally done in. Otherwise, we can do it in MODE, the widest mode
9692 encountered. The code we care about is that of the shift that will
9693 actually be done, not the shift that was originally requested. */
9695 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9696 ? result_mode
: mode
);
9698 /* We have now finished analyzing the shift. The result should be
9699 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9700 OUTER_OP is non-NIL, it is an operation that needs to be applied
9701 to the result of the shift. OUTER_CONST is the relevant constant,
9702 but we must turn off all bits turned off in the shift.
9704 If we were passed a value for X, see if we can use any pieces of
9705 it. If not, make new rtx. */
9707 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9708 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9709 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9710 const_rtx
= XEXP (x
, 1);
9712 const_rtx
= GEN_INT (count
);
9714 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9715 && GET_MODE (XEXP (x
, 0)) == shift_mode
9716 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9717 varop
= XEXP (x
, 0);
9718 else if (GET_MODE (varop
) != shift_mode
)
9719 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9721 /* If we can't make the SUBREG, try to return what we were given. */
9722 if (GET_CODE (varop
) == CLOBBER
)
9723 return x
? x
: varop
;
9725 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9729 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9731 /* If we have an outer operation and we just made a shift, it is
9732 possible that we could have simplified the shift were it not
9733 for the outer operation. So try to do the simplification
9736 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9737 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9738 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9739 INTVAL (XEXP (x
, 1)));
9741 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9742 turn off all the bits that the shift would have turned off. */
9743 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9744 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9745 GET_MODE_MASK (result_mode
) >> orig_count
);
9747 /* Do the remainder of the processing in RESULT_MODE. */
9748 x
= gen_lowpart_for_combine (result_mode
, x
);
9750 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9753 x
=simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9755 if (outer_op
!= NIL
)
9757 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9758 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9760 if (outer_op
== AND
)
9761 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9762 else if (outer_op
== SET
)
9763 /* This means that we have determined that the result is
9764 equivalent to a constant. This should be rare. */
9765 x
= GEN_INT (outer_const
);
9766 else if (GET_RTX_CLASS (outer_op
) == '1')
9767 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9769 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9775 /* Like recog, but we receive the address of a pointer to a new pattern.
9776 We try to match the rtx that the pointer points to.
9777 If that fails, we may try to modify or replace the pattern,
9778 storing the replacement into the same pointer object.
9780 Modifications include deletion or addition of CLOBBERs.
9782 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9783 the CLOBBERs are placed.
9785 The value is the final insn code from the pattern ultimately matched,
9789 recog_for_combine (pnewpat
, insn
, pnotes
)
9795 int insn_code_number
;
9796 int num_clobbers_to_add
= 0;
9801 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9802 we use to indicate that something didn't match. If we find such a
9803 thing, force rejection. */
9804 if (GET_CODE (pat
) == PARALLEL
)
9805 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9806 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9807 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9810 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9811 instruction for pattern recognition. */
9812 dummy_insn
= shallow_copy_rtx (insn
);
9813 PATTERN (dummy_insn
) = pat
;
9814 REG_NOTES (dummy_insn
) = 0;
9816 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9818 /* If it isn't, there is the possibility that we previously had an insn
9819 that clobbered some register as a side effect, but the combined
9820 insn doesn't need to do that. So try once more without the clobbers
9821 unless this represents an ASM insn. */
9823 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9824 && GET_CODE (pat
) == PARALLEL
)
9828 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9829 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9832 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9836 SUBST_INT (XVECLEN (pat
, 0), pos
);
9839 pat
= XVECEXP (pat
, 0, 0);
9841 PATTERN (dummy_insn
) = pat
;
9842 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9845 /* Recognize all noop sets, these will be killed by followup pass. */
9846 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9847 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9849 /* If we had any clobbers to add, make a new pattern than contains
9850 them. Then check to make sure that all of them are dead. */
9851 if (num_clobbers_to_add
)
9853 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9854 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9856 + num_clobbers_to_add
)
9857 : num_clobbers_to_add
+ 1));
9859 if (GET_CODE (pat
) == PARALLEL
)
9860 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9861 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9863 XVECEXP (newpat
, 0, 0) = pat
;
9865 add_clobbers (newpat
, insn_code_number
);
9867 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9868 i
< XVECLEN (newpat
, 0); i
++)
9870 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9871 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9873 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9874 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9882 return insn_code_number
;
9885 /* Like gen_lowpart but for use by combine. In combine it is not possible
9886 to create any new pseudoregs. However, it is safe to create
9887 invalid memory addresses, because combine will try to recognize
9888 them and all they will do is make the combine attempt fail.
9890 If for some reason this cannot do its job, an rtx
9891 (clobber (const_int 0)) is returned.
9892 An insn containing that will not be recognized. */
9897 gen_lowpart_for_combine (mode
, x
)
9898 enum machine_mode mode
;
9903 if (GET_MODE (x
) == mode
)
9906 /* We can only support MODE being wider than a word if X is a
9907 constant integer or has a mode the same size. */
9909 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9910 && ! ((GET_MODE (x
) == VOIDmode
9911 && (GET_CODE (x
) == CONST_INT
9912 || GET_CODE (x
) == CONST_DOUBLE
))
9913 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9914 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9916 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9917 won't know what to do. So we will strip off the SUBREG here and
9918 process normally. */
9919 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9922 if (GET_MODE (x
) == mode
)
9926 result
= gen_lowpart_common (mode
, x
);
9927 #ifdef CLASS_CANNOT_CHANGE_MODE
9929 && GET_CODE (result
) == SUBREG
9930 && GET_CODE (SUBREG_REG (result
)) == REG
9931 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9932 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9933 GET_MODE (SUBREG_REG (result
))))
9934 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9940 if (GET_CODE (x
) == MEM
)
9944 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9946 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9947 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9949 /* If we want to refer to something bigger than the original memref,
9950 generate a perverse subreg instead. That will force a reload
9951 of the original memref X. */
9952 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9953 return gen_rtx_SUBREG (mode
, x
, 0);
9955 if (WORDS_BIG_ENDIAN
)
9956 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9957 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9959 if (BYTES_BIG_ENDIAN
)
9961 /* Adjust the address so that the address-after-the-data is
9963 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9964 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9967 return adjust_address_nv (x
, mode
, offset
);
9970 /* If X is a comparison operator, rewrite it in a new mode. This
9971 probably won't match, but may allow further simplifications. */
9972 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9973 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9975 /* If we couldn't simplify X any other way, just enclose it in a
9976 SUBREG. Normally, this SUBREG won't match, but some patterns may
9977 include an explicit SUBREG or we may simplify it further in combine. */
9982 enum machine_mode sub_mode
= GET_MODE (x
);
9984 offset
= subreg_lowpart_offset (mode
, sub_mode
);
9985 if (sub_mode
== VOIDmode
)
9987 sub_mode
= int_mode_for_mode (mode
);
9988 x
= gen_lowpart_common (sub_mode
, x
);
9990 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
9993 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9997 /* These routines make binary and unary operations by first seeing if they
9998 fold; if not, a new expression is allocated. */
10001 gen_binary (code
, mode
, op0
, op1
)
10002 enum rtx_code code
;
10003 enum machine_mode mode
;
10009 if (GET_RTX_CLASS (code
) == 'c'
10010 && swap_commutative_operands_p (op0
, op1
))
10011 tem
= op0
, op0
= op1
, op1
= tem
;
10013 if (GET_RTX_CLASS (code
) == '<')
10015 enum machine_mode op_mode
= GET_MODE (op0
);
10017 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10018 just (REL_OP X Y). */
10019 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10021 op1
= XEXP (op0
, 1);
10022 op0
= XEXP (op0
, 0);
10023 op_mode
= GET_MODE (op0
);
10026 if (op_mode
== VOIDmode
)
10027 op_mode
= GET_MODE (op1
);
10028 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10031 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10036 /* Put complex operands first and constants second. */
10037 if (GET_RTX_CLASS (code
) == 'c'
10038 && swap_commutative_operands_p (op0
, op1
))
10039 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10041 /* If we are turning off bits already known off in OP0, we need not do
10043 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10044 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10045 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10048 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10051 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10052 comparison code that will be tested.
10054 The result is a possibly different comparison code to use. *POP0 and
10055 *POP1 may be updated.
10057 It is possible that we might detect that a comparison is either always
10058 true or always false. However, we do not perform general constant
10059 folding in combine, so this knowledge isn't useful. Such tautologies
10060 should have been detected earlier. Hence we ignore all such cases. */
10062 static enum rtx_code
10063 simplify_comparison (code
, pop0
, pop1
)
10064 enum rtx_code code
;
10072 enum machine_mode mode
, tmode
;
10074 /* Try a few ways of applying the same transformation to both operands. */
10077 #ifndef WORD_REGISTER_OPERATIONS
10078 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10079 so check specially. */
10080 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10081 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10082 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10083 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10084 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10085 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10086 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10087 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10088 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10089 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
10090 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10091 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
10092 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
10093 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
10094 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
10095 && (INTVAL (XEXP (op0
, 1))
10096 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10097 - (GET_MODE_BITSIZE
10098 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10100 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10101 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10105 /* If both operands are the same constant shift, see if we can ignore the
10106 shift. We can if the shift is a rotate or if the bits shifted out of
10107 this shift are known to be zero for both inputs and if the type of
10108 comparison is compatible with the shift. */
10109 if (GET_CODE (op0
) == GET_CODE (op1
)
10110 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10111 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10112 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10113 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10114 || (GET_CODE (op0
) == ASHIFTRT
10115 && (code
!= GTU
&& code
!= LTU
10116 && code
!= GEU
&& code
!= LEU
)))
10117 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10118 && INTVAL (XEXP (op0
, 1)) >= 0
10119 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10120 && XEXP (op0
, 1) == XEXP (op1
, 1))
10122 enum machine_mode mode
= GET_MODE (op0
);
10123 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10124 int shift_count
= INTVAL (XEXP (op0
, 1));
10126 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10127 mask
&= (mask
>> shift_count
) << shift_count
;
10128 else if (GET_CODE (op0
) == ASHIFT
)
10129 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10131 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10132 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10133 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10138 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10139 SUBREGs are of the same mode, and, in both cases, the AND would
10140 be redundant if the comparison was done in the narrower mode,
10141 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10142 and the operand's possibly nonzero bits are 0xffffff01; in that case
10143 if we only care about QImode, we don't need the AND). This case
10144 occurs if the output mode of an scc insn is not SImode and
10145 STORE_FLAG_VALUE == 1 (e.g., the 386).
10147 Similarly, check for a case where the AND's are ZERO_EXTEND
10148 operations from some narrower mode even though a SUBREG is not
10151 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10152 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10153 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10155 rtx inner_op0
= XEXP (op0
, 0);
10156 rtx inner_op1
= XEXP (op1
, 0);
10157 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10158 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10161 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10162 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10163 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10164 && (GET_MODE (SUBREG_REG (inner_op0
))
10165 == GET_MODE (SUBREG_REG (inner_op1
)))
10166 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10167 <= HOST_BITS_PER_WIDE_INT
)
10168 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10169 GET_MODE (SUBREG_REG (inner_op0
)))))
10170 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10171 GET_MODE (SUBREG_REG (inner_op1
))))))
10173 op0
= SUBREG_REG (inner_op0
);
10174 op1
= SUBREG_REG (inner_op1
);
10176 /* The resulting comparison is always unsigned since we masked
10177 off the original sign bit. */
10178 code
= unsigned_condition (code
);
10184 for (tmode
= GET_CLASS_NARROWEST_MODE
10185 (GET_MODE_CLASS (GET_MODE (op0
)));
10186 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10187 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10189 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10190 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10191 code
= unsigned_condition (code
);
10200 /* If both operands are NOT, we can strip off the outer operation
10201 and adjust the comparison code for swapped operands; similarly for
10202 NEG, except that this must be an equality comparison. */
10203 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10204 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10205 && (code
== EQ
|| code
== NE
)))
10206 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10212 /* If the first operand is a constant, swap the operands and adjust the
10213 comparison code appropriately, but don't do this if the second operand
10214 is already a constant integer. */
10215 if (swap_commutative_operands_p (op0
, op1
))
10217 tem
= op0
, op0
= op1
, op1
= tem
;
10218 code
= swap_condition (code
);
10221 /* We now enter a loop during which we will try to simplify the comparison.
10222 For the most part, we only are concerned with comparisons with zero,
10223 but some things may really be comparisons with zero but not start
10224 out looking that way. */
10226 while (GET_CODE (op1
) == CONST_INT
)
10228 enum machine_mode mode
= GET_MODE (op0
);
10229 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10230 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10231 int equality_comparison_p
;
10232 int sign_bit_comparison_p
;
10233 int unsigned_comparison_p
;
10234 HOST_WIDE_INT const_op
;
10236 /* We only want to handle integral modes. This catches VOIDmode,
10237 CCmode, and the floating-point modes. An exception is that we
10238 can handle VOIDmode if OP0 is a COMPARE or a comparison
10241 if (GET_MODE_CLASS (mode
) != MODE_INT
10242 && ! (mode
== VOIDmode
10243 && (GET_CODE (op0
) == COMPARE
10244 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10247 /* Get the constant we are comparing against and turn off all bits
10248 not on in our mode. */
10249 const_op
= INTVAL (op1
);
10250 if (mode
!= VOIDmode
)
10251 const_op
= trunc_int_for_mode (const_op
, mode
);
10252 op1
= GEN_INT (const_op
);
10254 /* If we are comparing against a constant power of two and the value
10255 being compared can only have that single bit nonzero (e.g., it was
10256 `and'ed with that bit), we can replace this with a comparison
10259 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10260 || code
== LT
|| code
== LTU
)
10261 && mode_width
<= HOST_BITS_PER_WIDE_INT
10262 && exact_log2 (const_op
) >= 0
10263 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10265 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10266 op1
= const0_rtx
, const_op
= 0;
10269 /* Similarly, if we are comparing a value known to be either -1 or
10270 0 with -1, change it to the opposite comparison against zero. */
10273 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10274 || code
== GEU
|| code
== LTU
)
10275 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10277 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10278 op1
= const0_rtx
, const_op
= 0;
10281 /* Do some canonicalizations based on the comparison code. We prefer
10282 comparisons against zero and then prefer equality comparisons.
10283 If we can reduce the size of a constant, we will do that too. */
10288 /* < C is equivalent to <= (C - 1) */
10292 op1
= GEN_INT (const_op
);
10294 /* ... fall through to LE case below. */
10300 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10304 op1
= GEN_INT (const_op
);
10308 /* If we are doing a <= 0 comparison on a value known to have
10309 a zero sign bit, we can replace this with == 0. */
10310 else if (const_op
== 0
10311 && mode_width
<= HOST_BITS_PER_WIDE_INT
10312 && (nonzero_bits (op0
, mode
)
10313 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10318 /* >= C is equivalent to > (C - 1). */
10322 op1
= GEN_INT (const_op
);
10324 /* ... fall through to GT below. */
10330 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10334 op1
= GEN_INT (const_op
);
10338 /* If we are doing a > 0 comparison on a value known to have
10339 a zero sign bit, we can replace this with != 0. */
10340 else if (const_op
== 0
10341 && mode_width
<= HOST_BITS_PER_WIDE_INT
10342 && (nonzero_bits (op0
, mode
)
10343 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10348 /* < C is equivalent to <= (C - 1). */
10352 op1
= GEN_INT (const_op
);
10354 /* ... fall through ... */
10357 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10358 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10359 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10361 const_op
= 0, op1
= const0_rtx
;
10369 /* unsigned <= 0 is equivalent to == 0 */
10373 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10374 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10375 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10377 const_op
= 0, op1
= const0_rtx
;
10383 /* >= C is equivalent to < (C - 1). */
10387 op1
= GEN_INT (const_op
);
10389 /* ... fall through ... */
10392 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10393 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10394 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10396 const_op
= 0, op1
= const0_rtx
;
10404 /* unsigned > 0 is equivalent to != 0 */
10408 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10409 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10410 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10412 const_op
= 0, op1
= const0_rtx
;
10421 /* Compute some predicates to simplify code below. */
10423 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10424 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10425 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10428 /* If this is a sign bit comparison and we can do arithmetic in
10429 MODE, say that we will only be needing the sign bit of OP0. */
10430 if (sign_bit_comparison_p
10431 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10432 op0
= force_to_mode (op0
, mode
,
10434 << (GET_MODE_BITSIZE (mode
) - 1)),
10437 /* Now try cases based on the opcode of OP0. If none of the cases
10438 does a "continue", we exit this loop immediately after the
10441 switch (GET_CODE (op0
))
10444 /* If we are extracting a single bit from a variable position in
10445 a constant that has only a single bit set and are comparing it
10446 with zero, we can convert this into an equality comparison
10447 between the position and the location of the single bit. */
10449 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10450 && XEXP (op0
, 1) == const1_rtx
10451 && equality_comparison_p
&& const_op
== 0
10452 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10454 if (BITS_BIG_ENDIAN
)
10456 enum machine_mode new_mode
10457 = mode_for_extraction (EP_extzv
, 1);
10458 if (new_mode
== MAX_MACHINE_MODE
)
10459 i
= BITS_PER_WORD
- 1 - i
;
10463 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10467 op0
= XEXP (op0
, 2);
10471 /* Result is nonzero iff shift count is equal to I. */
10472 code
= reverse_condition (code
);
10476 /* ... fall through ... */
10479 tem
= expand_compound_operation (op0
);
10488 /* If testing for equality, we can take the NOT of the constant. */
10489 if (equality_comparison_p
10490 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10492 op0
= XEXP (op0
, 0);
10497 /* If just looking at the sign bit, reverse the sense of the
10499 if (sign_bit_comparison_p
)
10501 op0
= XEXP (op0
, 0);
10502 code
= (code
== GE
? LT
: GE
);
10508 /* If testing for equality, we can take the NEG of the constant. */
10509 if (equality_comparison_p
10510 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10512 op0
= XEXP (op0
, 0);
10517 /* The remaining cases only apply to comparisons with zero. */
10521 /* When X is ABS or is known positive,
10522 (neg X) is < 0 if and only if X != 0. */
10524 if (sign_bit_comparison_p
10525 && (GET_CODE (XEXP (op0
, 0)) == ABS
10526 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10527 && (nonzero_bits (XEXP (op0
, 0), mode
)
10528 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10530 op0
= XEXP (op0
, 0);
10531 code
= (code
== LT
? NE
: EQ
);
10535 /* If we have NEG of something whose two high-order bits are the
10536 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10537 if (num_sign_bit_copies (op0
, mode
) >= 2)
10539 op0
= XEXP (op0
, 0);
10540 code
= swap_condition (code
);
10546 /* If we are testing equality and our count is a constant, we
10547 can perform the inverse operation on our RHS. */
10548 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10549 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10550 op1
, XEXP (op0
, 1))) != 0)
10552 op0
= XEXP (op0
, 0);
10557 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10558 a particular bit. Convert it to an AND of a constant of that
10559 bit. This will be converted into a ZERO_EXTRACT. */
10560 if (const_op
== 0 && sign_bit_comparison_p
10561 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10562 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10564 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10567 - INTVAL (XEXP (op0
, 1)))));
10568 code
= (code
== LT
? NE
: EQ
);
10572 /* Fall through. */
10575 /* ABS is ignorable inside an equality comparison with zero. */
10576 if (const_op
== 0 && equality_comparison_p
)
10578 op0
= XEXP (op0
, 0);
10584 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10585 to (compare FOO CONST) if CONST fits in FOO's mode and we
10586 are either testing inequality or have an unsigned comparison
10587 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10588 if (! unsigned_comparison_p
10589 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10590 <= HOST_BITS_PER_WIDE_INT
)
10591 && ((unsigned HOST_WIDE_INT
) const_op
10592 < (((unsigned HOST_WIDE_INT
) 1
10593 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10595 op0
= XEXP (op0
, 0);
10601 /* Check for the case where we are comparing A - C1 with C2,
10602 both constants are smaller than 1/2 the maximum positive
10603 value in MODE, and the comparison is equality or unsigned.
10604 In that case, if A is either zero-extended to MODE or has
10605 sufficient sign bits so that the high-order bit in MODE
10606 is a copy of the sign in the inner mode, we can prove that it is
10607 safe to do the operation in the wider mode. This simplifies
10608 many range checks. */
10610 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10611 && subreg_lowpart_p (op0
)
10612 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10613 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10614 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10615 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10616 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10617 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10618 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10619 GET_MODE (SUBREG_REG (op0
)))
10620 & ~GET_MODE_MASK (mode
))
10621 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10622 GET_MODE (SUBREG_REG (op0
)))
10624 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10625 - GET_MODE_BITSIZE (mode
)))))
10627 op0
= SUBREG_REG (op0
);
10631 /* If the inner mode is narrower and we are extracting the low part,
10632 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10633 if (subreg_lowpart_p (op0
)
10634 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10635 /* Fall through */ ;
10639 /* ... fall through ... */
10642 if ((unsigned_comparison_p
|| equality_comparison_p
)
10643 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10644 <= HOST_BITS_PER_WIDE_INT
)
10645 && ((unsigned HOST_WIDE_INT
) const_op
10646 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10648 op0
= XEXP (op0
, 0);
10654 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10655 this for equality comparisons due to pathological cases involving
10657 if (equality_comparison_p
10658 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10659 op1
, XEXP (op0
, 1))))
10661 op0
= XEXP (op0
, 0);
10666 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10667 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10668 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10670 op0
= XEXP (XEXP (op0
, 0), 0);
10671 code
= (code
== LT
? EQ
: NE
);
10677 /* We used to optimize signed comparisons against zero, but that
10678 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10679 arrive here as equality comparisons, or (GEU, LTU) are
10680 optimized away. No need to special-case them. */
10682 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10683 (eq B (minus A C)), whichever simplifies. We can only do
10684 this for equality comparisons due to pathological cases involving
10686 if (equality_comparison_p
10687 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10688 XEXP (op0
, 1), op1
)))
10690 op0
= XEXP (op0
, 0);
10695 if (equality_comparison_p
10696 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10697 XEXP (op0
, 0), op1
)))
10699 op0
= XEXP (op0
, 1);
10704 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10705 of bits in X minus 1, is one iff X > 0. */
10706 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10707 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10708 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10710 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10712 op0
= XEXP (op0
, 1);
10713 code
= (code
== GE
? LE
: GT
);
10719 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10720 if C is zero or B is a constant. */
10721 if (equality_comparison_p
10722 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10723 XEXP (op0
, 1), op1
)))
10725 op0
= XEXP (op0
, 0);
10732 case UNEQ
: case LTGT
:
10733 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10734 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10735 case UNORDERED
: case ORDERED
:
10736 /* We can't do anything if OP0 is a condition code value, rather
10737 than an actual data value. */
10740 || XEXP (op0
, 0) == cc0_rtx
10742 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10745 /* Get the two operands being compared. */
10746 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10747 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10749 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10751 /* Check for the cases where we simply want the result of the
10752 earlier test or the opposite of that result. */
10753 if (code
== NE
|| code
== EQ
10754 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10755 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10756 && (STORE_FLAG_VALUE
10757 & (((HOST_WIDE_INT
) 1
10758 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10759 && (code
== LT
|| code
== GE
)))
10761 enum rtx_code new_code
;
10762 if (code
== LT
|| code
== NE
)
10763 new_code
= GET_CODE (op0
);
10765 new_code
= combine_reversed_comparison_code (op0
);
10767 if (new_code
!= UNKNOWN
)
10778 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10780 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10781 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10782 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10784 op0
= XEXP (op0
, 1);
10785 code
= (code
== GE
? GT
: LE
);
10791 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10792 will be converted to a ZERO_EXTRACT later. */
10793 if (const_op
== 0 && equality_comparison_p
10794 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10795 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10797 op0
= simplify_and_const_int
10798 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10800 XEXP (XEXP (op0
, 0), 1)),
10801 (HOST_WIDE_INT
) 1);
10805 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10806 zero and X is a comparison and C1 and C2 describe only bits set
10807 in STORE_FLAG_VALUE, we can compare with X. */
10808 if (const_op
== 0 && equality_comparison_p
10809 && mode_width
<= HOST_BITS_PER_WIDE_INT
10810 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10811 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10812 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10813 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10814 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10816 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10817 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10818 if ((~STORE_FLAG_VALUE
& mask
) == 0
10819 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10820 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10821 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10823 op0
= XEXP (XEXP (op0
, 0), 0);
10828 /* If we are doing an equality comparison of an AND of a bit equal
10829 to the sign bit, replace this with a LT or GE comparison of
10830 the underlying value. */
10831 if (equality_comparison_p
10833 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10834 && mode_width
<= HOST_BITS_PER_WIDE_INT
10835 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10836 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10838 op0
= XEXP (op0
, 0);
10839 code
= (code
== EQ
? GE
: LT
);
10843 /* If this AND operation is really a ZERO_EXTEND from a narrower
10844 mode, the constant fits within that mode, and this is either an
10845 equality or unsigned comparison, try to do this comparison in
10846 the narrower mode. */
10847 if ((equality_comparison_p
|| unsigned_comparison_p
)
10848 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10849 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10850 & GET_MODE_MASK (mode
))
10852 && const_op
>> i
== 0
10853 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10855 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10859 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10860 in both M1 and M2 and the SUBREG is either paradoxical or
10861 represents the low part, permute the SUBREG and the AND and
10863 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10865 #ifdef WORD_REGISTER_OPERATIONS
10867 > (GET_MODE_BITSIZE
10868 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10869 && mode_width
<= BITS_PER_WORD
)
10872 <= (GET_MODE_BITSIZE
10873 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10874 && subreg_lowpart_p (XEXP (op0
, 0))))
10875 #ifndef WORD_REGISTER_OPERATIONS
10876 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10877 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10878 As originally written the upper bits have a defined value
10879 due to the AND operation. However, if we commute the AND
10880 inside the SUBREG then they no longer have defined values
10881 and the meaning of the code has been changed. */
10882 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10883 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10885 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10886 && mode_width
<= HOST_BITS_PER_WIDE_INT
10887 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10888 <= HOST_BITS_PER_WIDE_INT
)
10889 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10890 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10891 & INTVAL (XEXP (op0
, 1)))
10892 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10893 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10894 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10898 = gen_lowpart_for_combine
10900 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10901 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10905 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10906 (eq (and (lshiftrt X) 1) 0). */
10907 if (const_op
== 0 && equality_comparison_p
10908 && XEXP (op0
, 1) == const1_rtx
10909 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10910 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10912 op0
= simplify_and_const_int
10914 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10915 XEXP (XEXP (op0
, 0), 1)),
10916 (HOST_WIDE_INT
) 1);
10917 code
= (code
== NE
? EQ
: NE
);
10923 /* If we have (compare (ashift FOO N) (const_int C)) and
10924 the high order N bits of FOO (N+1 if an inequality comparison)
10925 are known to be zero, we can do this by comparing FOO with C
10926 shifted right N bits so long as the low-order N bits of C are
10928 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10929 && INTVAL (XEXP (op0
, 1)) >= 0
10930 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10931 < HOST_BITS_PER_WIDE_INT
)
10933 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10934 && mode_width
<= HOST_BITS_PER_WIDE_INT
10935 && (nonzero_bits (XEXP (op0
, 0), mode
)
10936 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10937 + ! equality_comparison_p
))) == 0)
10939 /* We must perform a logical shift, not an arithmetic one,
10940 as we want the top N bits of C to be zero. */
10941 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10943 temp
>>= INTVAL (XEXP (op0
, 1));
10944 op1
= gen_int_mode (temp
, mode
);
10945 op0
= XEXP (op0
, 0);
10949 /* If we are doing a sign bit comparison, it means we are testing
10950 a particular bit. Convert it to the appropriate AND. */
10951 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10952 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10954 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10957 - INTVAL (XEXP (op0
, 1)))));
10958 code
= (code
== LT
? NE
: EQ
);
10962 /* If this an equality comparison with zero and we are shifting
10963 the low bit to the sign bit, we can convert this to an AND of the
10965 if (const_op
== 0 && equality_comparison_p
10966 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10967 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10970 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10971 (HOST_WIDE_INT
) 1);
10977 /* If this is an equality comparison with zero, we can do this
10978 as a logical shift, which might be much simpler. */
10979 if (equality_comparison_p
&& const_op
== 0
10980 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10982 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10984 INTVAL (XEXP (op0
, 1)));
10988 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10989 do the comparison in a narrower mode. */
10990 if (! unsigned_comparison_p
10991 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10992 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10993 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10994 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10995 MODE_INT
, 1)) != BLKmode
10996 && (((unsigned HOST_WIDE_INT
) const_op
10997 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10998 <= GET_MODE_MASK (tmode
)))
11000 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11004 /* Likewise if OP0 is a PLUS of a sign extension with a
11005 constant, which is usually represented with the PLUS
11006 between the shifts. */
11007 if (! unsigned_comparison_p
11008 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11009 && GET_CODE (XEXP (op0
, 0)) == PLUS
11010 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11011 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11012 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11013 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11014 MODE_INT
, 1)) != BLKmode
11015 && (((unsigned HOST_WIDE_INT
) const_op
11016 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11017 <= GET_MODE_MASK (tmode
)))
11019 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11020 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11021 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11024 op0
= gen_binary (PLUS
, tmode
,
11025 gen_lowpart_for_combine (tmode
, inner
),
11030 /* ... fall through ... */
11032 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11033 the low order N bits of FOO are known to be zero, we can do this
11034 by comparing FOO with C shifted left N bits so long as no
11035 overflow occurs. */
11036 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11037 && INTVAL (XEXP (op0
, 1)) >= 0
11038 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11039 && mode_width
<= HOST_BITS_PER_WIDE_INT
11040 && (nonzero_bits (XEXP (op0
, 0), mode
)
11041 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11042 && (((unsigned HOST_WIDE_INT
) const_op
11043 + (GET_CODE (op0
) != LSHIFTRT
11044 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11047 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11049 /* If the shift was logical, then we must make the condition
11051 if (GET_CODE (op0
) == LSHIFTRT
)
11052 code
= unsigned_condition (code
);
11054 const_op
<<= INTVAL (XEXP (op0
, 1));
11055 op1
= GEN_INT (const_op
);
11056 op0
= XEXP (op0
, 0);
11060 /* If we are using this shift to extract just the sign bit, we
11061 can replace this with an LT or GE comparison. */
11063 && (equality_comparison_p
|| sign_bit_comparison_p
)
11064 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11065 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11068 op0
= XEXP (op0
, 0);
11069 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11081 /* Now make any compound operations involved in this comparison. Then,
11082 check for an outmost SUBREG on OP0 that is not doing anything or is
11083 paradoxical. The latter transformation must only be performed when
11084 it is known that the "extra" bits will be the same in op0 and op1 or
11085 that they don't matter. There are three cases to consider:
11087 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11088 care bits and we can assume they have any convenient value. So
11089 making the transformation is safe.
11091 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11092 In this case the upper bits of op0 are undefined. We should not make
11093 the simplification in that case as we do not know the contents of
11096 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11097 NIL. In that case we know those bits are zeros or ones. We must
11098 also be sure that they are the same as the upper bits of op1.
11100 We can never remove a SUBREG for a non-equality comparison because
11101 the sign bit is in a different place in the underlying object. */
11103 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11104 op1
= make_compound_operation (op1
, SET
);
11106 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11107 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11109 && GET_CODE (SUBREG_REG (op0
)) == REG
11110 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11111 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11112 && (code
== NE
|| code
== EQ
))
11114 if (GET_MODE_SIZE (GET_MODE (op0
))
11115 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11117 op0
= SUBREG_REG (op0
);
11118 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11120 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11121 <= HOST_BITS_PER_WIDE_INT
)
11122 && (nonzero_bits (SUBREG_REG (op0
),
11123 GET_MODE (SUBREG_REG (op0
)))
11124 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11126 tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)), op1
);
11128 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11129 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11130 op0
= SUBREG_REG (op0
), op1
= tem
;
11134 /* We now do the opposite procedure: Some machines don't have compare
11135 insns in all modes. If OP0's mode is an integer mode smaller than a
11136 word and we can't do a compare in that mode, see if there is a larger
11137 mode for which we can do the compare. There are a number of cases in
11138 which we can use the wider mode. */
11140 mode
= GET_MODE (op0
);
11141 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11142 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11143 && ! have_insn_for (COMPARE
, mode
))
11144 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11146 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11147 tmode
= GET_MODE_WIDER_MODE (tmode
))
11148 if (have_insn_for (COMPARE
, tmode
))
11152 /* If the only nonzero bits in OP0 and OP1 are those in the
11153 narrower mode and this is an equality or unsigned comparison,
11154 we can use the wider mode. Similarly for sign-extended
11155 values, in which case it is true for all comparisons. */
11156 zero_extended
= ((code
== EQ
|| code
== NE
11157 || code
== GEU
|| code
== GTU
11158 || code
== LEU
|| code
== LTU
)
11159 && (nonzero_bits (op0
, tmode
)
11160 & ~GET_MODE_MASK (mode
)) == 0
11161 && ((GET_CODE (op1
) == CONST_INT
11162 || (nonzero_bits (op1
, tmode
)
11163 & ~GET_MODE_MASK (mode
)) == 0)));
11166 || ((num_sign_bit_copies (op0
, tmode
)
11167 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11168 - GET_MODE_BITSIZE (mode
)))
11169 && (num_sign_bit_copies (op1
, tmode
)
11170 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11171 - GET_MODE_BITSIZE (mode
)))))
11173 /* If OP0 is an AND and we don't have an AND in MODE either,
11174 make a new AND in the proper mode. */
11175 if (GET_CODE (op0
) == AND
11176 && !have_insn_for (AND
, mode
))
11177 op0
= gen_binary (AND
, tmode
,
11178 gen_lowpart_for_combine (tmode
,
11180 gen_lowpart_for_combine (tmode
,
11183 op0
= gen_lowpart_for_combine (tmode
, op0
);
11184 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11185 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11186 op1
= gen_lowpart_for_combine (tmode
, op1
);
11190 /* If this is a test for negative, we can make an explicit
11191 test of the sign bit. */
11193 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11194 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11196 op0
= gen_binary (AND
, tmode
,
11197 gen_lowpart_for_combine (tmode
, op0
),
11198 GEN_INT ((HOST_WIDE_INT
) 1
11199 << (GET_MODE_BITSIZE (mode
) - 1)));
11200 code
= (code
== LT
) ? NE
: EQ
;
11205 #ifdef CANONICALIZE_COMPARISON
11206 /* If this machine only supports a subset of valid comparisons, see if we
11207 can convert an unsupported one into a supported one. */
11208 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11217 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11218 searching backward. */
11219 static enum rtx_code
11220 combine_reversed_comparison_code (exp
)
11223 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11226 if (code1
!= UNKNOWN
11227 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11229 /* Otherwise try and find where the condition codes were last set and
11231 x
= get_last_value (XEXP (exp
, 0));
11232 if (!x
|| GET_CODE (x
) != COMPARE
)
11234 return reversed_comparison_code_parts (GET_CODE (exp
),
11235 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11237 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11238 Return NULL_RTX in case we fail to do the reversal. */
11240 reversed_comparison (exp
, mode
, op0
, op1
)
11242 enum machine_mode mode
;
11244 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11245 if (reversed_code
== UNKNOWN
)
11248 return gen_binary (reversed_code
, mode
, op0
, op1
);
11251 /* Utility function for following routine. Called when X is part of a value
11252 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11253 for each register mentioned. Similar to mention_regs in cse.c */
11256 update_table_tick (x
)
11259 enum rtx_code code
= GET_CODE (x
);
11260 const char *fmt
= GET_RTX_FORMAT (code
);
11265 unsigned int regno
= REGNO (x
);
11266 unsigned int endregno
11267 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11268 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11271 for (r
= regno
; r
< endregno
; r
++)
11272 reg_last_set_table_tick
[r
] = label_tick
;
11277 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11278 /* Note that we can't have an "E" in values stored; see
11279 get_last_value_validate. */
11281 update_table_tick (XEXP (x
, i
));
11284 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11285 are saying that the register is clobbered and we no longer know its
11286 value. If INSN is zero, don't update reg_last_set; this is only permitted
11287 with VALUE also zero and is used to invalidate the register. */
11290 record_value_for_reg (reg
, insn
, value
)
11295 unsigned int regno
= REGNO (reg
);
11296 unsigned int endregno
11297 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11298 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11301 /* If VALUE contains REG and we have a previous value for REG, substitute
11302 the previous value. */
11303 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11307 /* Set things up so get_last_value is allowed to see anything set up to
11309 subst_low_cuid
= INSN_CUID (insn
);
11310 tem
= get_last_value (reg
);
11312 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11313 it isn't going to be useful and will take a lot of time to process,
11314 so just use the CLOBBER. */
11318 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11319 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11320 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11321 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11322 tem
= XEXP (tem
, 0);
11324 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11328 /* For each register modified, show we don't know its value, that
11329 we don't know about its bitwise content, that its value has been
11330 updated, and that we don't know the location of the death of the
11332 for (i
= regno
; i
< endregno
; i
++)
11335 reg_last_set
[i
] = insn
;
11337 reg_last_set_value
[i
] = 0;
11338 reg_last_set_mode
[i
] = 0;
11339 reg_last_set_nonzero_bits
[i
] = 0;
11340 reg_last_set_sign_bit_copies
[i
] = 0;
11341 reg_last_death
[i
] = 0;
11344 /* Mark registers that are being referenced in this value. */
11346 update_table_tick (value
);
11348 /* Now update the status of each register being set.
11349 If someone is using this register in this block, set this register
11350 to invalid since we will get confused between the two lives in this
11351 basic block. This makes using this register always invalid. In cse, we
11352 scan the table to invalidate all entries using this register, but this
11353 is too much work for us. */
11355 for (i
= regno
; i
< endregno
; i
++)
11357 reg_last_set_label
[i
] = label_tick
;
11358 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11359 reg_last_set_invalid
[i
] = 1;
11361 reg_last_set_invalid
[i
] = 0;
11364 /* The value being assigned might refer to X (like in "x++;"). In that
11365 case, we must replace it with (clobber (const_int 0)) to prevent
11367 if (value
&& ! get_last_value_validate (&value
, insn
,
11368 reg_last_set_label
[regno
], 0))
11370 value
= copy_rtx (value
);
11371 if (! get_last_value_validate (&value
, insn
,
11372 reg_last_set_label
[regno
], 1))
11376 /* For the main register being modified, update the value, the mode, the
11377 nonzero bits, and the number of sign bit copies. */
11379 reg_last_set_value
[regno
] = value
;
11383 enum machine_mode mode
= GET_MODE (reg
);
11384 subst_low_cuid
= INSN_CUID (insn
);
11385 reg_last_set_mode
[regno
] = mode
;
11386 if (GET_MODE_CLASS (mode
) == MODE_INT
11387 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11388 mode
= nonzero_bits_mode
;
11389 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11390 reg_last_set_sign_bit_copies
[regno
]
11391 = num_sign_bit_copies (value
, GET_MODE (reg
));
11395 /* Called via note_stores from record_dead_and_set_regs to handle one
11396 SET or CLOBBER in an insn. DATA is the instruction in which the
11397 set is occurring. */
11400 record_dead_and_set_regs_1 (dest
, setter
, data
)
11404 rtx record_dead_insn
= (rtx
) data
;
11406 if (GET_CODE (dest
) == SUBREG
)
11407 dest
= SUBREG_REG (dest
);
11409 if (GET_CODE (dest
) == REG
)
11411 /* If we are setting the whole register, we know its value. Otherwise
11412 show that we don't know the value. We can handle SUBREG in
11414 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11415 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11416 else if (GET_CODE (setter
) == SET
11417 && GET_CODE (SET_DEST (setter
)) == SUBREG
11418 && SUBREG_REG (SET_DEST (setter
)) == dest
11419 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11420 && subreg_lowpart_p (SET_DEST (setter
)))
11421 record_value_for_reg (dest
, record_dead_insn
,
11422 gen_lowpart_for_combine (GET_MODE (dest
),
11423 SET_SRC (setter
)));
11425 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11427 else if (GET_CODE (dest
) == MEM
11428 /* Ignore pushes, they clobber nothing. */
11429 && ! push_operand (dest
, GET_MODE (dest
)))
11430 mem_last_set
= INSN_CUID (record_dead_insn
);
11433 /* Update the records of when each REG was most recently set or killed
11434 for the things done by INSN. This is the last thing done in processing
11435 INSN in the combiner loop.
11437 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11438 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11439 and also the similar information mem_last_set (which insn most recently
11440 modified memory) and last_call_cuid (which insn was the most recent
11441 subroutine call). */
11444 record_dead_and_set_regs (insn
)
11450 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11452 if (REG_NOTE_KIND (link
) == REG_DEAD
11453 && GET_CODE (XEXP (link
, 0)) == REG
)
11455 unsigned int regno
= REGNO (XEXP (link
, 0));
11456 unsigned int endregno
11457 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11458 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11461 for (i
= regno
; i
< endregno
; i
++)
11462 reg_last_death
[i
] = insn
;
11464 else if (REG_NOTE_KIND (link
) == REG_INC
)
11465 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11468 if (GET_CODE (insn
) == CALL_INSN
)
11470 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11471 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11473 reg_last_set_value
[i
] = 0;
11474 reg_last_set_mode
[i
] = 0;
11475 reg_last_set_nonzero_bits
[i
] = 0;
11476 reg_last_set_sign_bit_copies
[i
] = 0;
11477 reg_last_death
[i
] = 0;
11480 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11482 /* Don't bother recording what this insn does. It might set the
11483 return value register, but we can't combine into a call
11484 pattern anyway, so there's no point trying (and it may cause
11485 a crash, if e.g. we wind up asking for last_set_value of a
11486 SUBREG of the return value register). */
11490 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11493 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11494 register present in the SUBREG, so for each such SUBREG go back and
11495 adjust nonzero and sign bit information of the registers that are
11496 known to have some zero/sign bits set.
11498 This is needed because when combine blows the SUBREGs away, the
11499 information on zero/sign bits is lost and further combines can be
11500 missed because of that. */
11503 record_promoted_value (insn
, subreg
)
11508 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11509 enum machine_mode mode
= GET_MODE (subreg
);
11511 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11514 for (links
= LOG_LINKS (insn
); links
;)
11516 insn
= XEXP (links
, 0);
11517 set
= single_set (insn
);
11519 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11520 || REGNO (SET_DEST (set
)) != regno
11521 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11523 links
= XEXP (links
, 1);
11527 if (reg_last_set
[regno
] == insn
)
11529 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11530 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11533 if (GET_CODE (SET_SRC (set
)) == REG
)
11535 regno
= REGNO (SET_SRC (set
));
11536 links
= LOG_LINKS (insn
);
11543 /* Scan X for promoted SUBREGs. For each one found,
11544 note what it implies to the registers used in it. */
11547 check_promoted_subreg (insn
, x
)
11551 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11552 && GET_CODE (SUBREG_REG (x
)) == REG
)
11553 record_promoted_value (insn
, x
);
11556 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11559 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11563 check_promoted_subreg (insn
, XEXP (x
, i
));
11567 if (XVEC (x
, i
) != 0)
11568 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11569 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11575 /* Utility routine for the following function. Verify that all the registers
11576 mentioned in *LOC are valid when *LOC was part of a value set when
11577 label_tick == TICK. Return 0 if some are not.
11579 If REPLACE is non-zero, replace the invalid reference with
11580 (clobber (const_int 0)) and return 1. This replacement is useful because
11581 we often can get useful information about the form of a value (e.g., if
11582 it was produced by a shift that always produces -1 or 0) even though
11583 we don't know exactly what registers it was produced from. */
11586 get_last_value_validate (loc
, insn
, tick
, replace
)
11593 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11594 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11597 if (GET_CODE (x
) == REG
)
11599 unsigned int regno
= REGNO (x
);
11600 unsigned int endregno
11601 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11602 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11605 for (j
= regno
; j
< endregno
; j
++)
11606 if (reg_last_set_invalid
[j
]
11607 /* If this is a pseudo-register that was only set once and not
11608 live at the beginning of the function, it is always valid. */
11609 || (! (regno
>= FIRST_PSEUDO_REGISTER
11610 && REG_N_SETS (regno
) == 1
11611 && (! REGNO_REG_SET_P
11612 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11613 && reg_last_set_label
[j
] > tick
))
11616 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11622 /* If this is a memory reference, make sure that there were
11623 no stores after it that might have clobbered the value. We don't
11624 have alias info, so we assume any store invalidates it. */
11625 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11626 && INSN_CUID (insn
) <= mem_last_set
)
11629 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11633 for (i
= 0; i
< len
; i
++)
11635 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11636 /* Don't bother with these. They shouldn't occur anyway. */
11640 /* If we haven't found a reason for it to be invalid, it is valid. */
11644 /* Get the last value assigned to X, if known. Some registers
11645 in the value may be replaced with (clobber (const_int 0)) if their value
11646 is known longer known reliably. */
11652 unsigned int regno
;
11655 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11656 then convert it to the desired mode. If this is a paradoxical SUBREG,
11657 we cannot predict what values the "extra" bits might have. */
11658 if (GET_CODE (x
) == SUBREG
11659 && subreg_lowpart_p (x
)
11660 && (GET_MODE_SIZE (GET_MODE (x
))
11661 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11662 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11663 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11665 if (GET_CODE (x
) != REG
)
11669 value
= reg_last_set_value
[regno
];
11671 /* If we don't have a value, or if it isn't for this basic block and
11672 it's either a hard register, set more than once, or it's a live
11673 at the beginning of the function, return 0.
11675 Because if it's not live at the beginning of the function then the reg
11676 is always set before being used (is never used without being set).
11677 And, if it's set only once, and it's always set before use, then all
11678 uses must have the same last value, even if it's not from this basic
11682 || (reg_last_set_label
[regno
] != label_tick
11683 && (regno
< FIRST_PSEUDO_REGISTER
11684 || REG_N_SETS (regno
) != 1
11685 || (REGNO_REG_SET_P
11686 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11689 /* If the value was set in a later insn than the ones we are processing,
11690 we can't use it even if the register was only set once. */
11691 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11694 /* If the value has all its registers valid, return it. */
11695 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11696 reg_last_set_label
[regno
], 0))
11699 /* Otherwise, make a copy and replace any invalid register with
11700 (clobber (const_int 0)). If that fails for some reason, return 0. */
11702 value
= copy_rtx (value
);
11703 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11704 reg_last_set_label
[regno
], 1))
11710 /* Return nonzero if expression X refers to a REG or to memory
11711 that is set in an instruction more recent than FROM_CUID. */
11714 use_crosses_set_p (x
, from_cuid
)
11720 enum rtx_code code
= GET_CODE (x
);
11724 unsigned int regno
= REGNO (x
);
11725 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11726 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11728 #ifdef PUSH_ROUNDING
11729 /* Don't allow uses of the stack pointer to be moved,
11730 because we don't know whether the move crosses a push insn. */
11731 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11734 for (; regno
< endreg
; regno
++)
11735 if (reg_last_set
[regno
]
11736 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11741 if (code
== MEM
&& mem_last_set
> from_cuid
)
11744 fmt
= GET_RTX_FORMAT (code
);
11746 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11751 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11752 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11755 else if (fmt
[i
] == 'e'
11756 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11762 /* Define three variables used for communication between the following
11765 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11766 static int reg_dead_flag
;
11768 /* Function called via note_stores from reg_dead_at_p.
11770 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11771 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11774 reg_dead_at_p_1 (dest
, x
, data
)
11777 void *data ATTRIBUTE_UNUSED
;
11779 unsigned int regno
, endregno
;
11781 if (GET_CODE (dest
) != REG
)
11784 regno
= REGNO (dest
);
11785 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11786 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11788 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11789 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11792 /* Return non-zero if REG is known to be dead at INSN.
11794 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11795 referencing REG, it is dead. If we hit a SET referencing REG, it is
11796 live. Otherwise, see if it is live or dead at the start of the basic
11797 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11798 must be assumed to be always live. */
11801 reg_dead_at_p (reg
, insn
)
11808 /* Set variables for reg_dead_at_p_1. */
11809 reg_dead_regno
= REGNO (reg
);
11810 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11811 ? HARD_REGNO_NREGS (reg_dead_regno
,
11817 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11818 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11820 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11821 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11825 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11826 beginning of function. */
11827 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11828 insn
= prev_nonnote_insn (insn
))
11830 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11832 return reg_dead_flag
== 1 ? 1 : 0;
11834 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11838 /* Get the basic block that we were in. */
11840 block
= ENTRY_BLOCK_PTR
->next_bb
;
11843 FOR_EACH_BB (block
)
11844 if (insn
== block
->head
)
11847 if (block
== EXIT_BLOCK_PTR
)
11851 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11852 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11858 /* Note hard registers in X that are used. This code is similar to
11859 that in flow.c, but much simpler since we don't care about pseudos. */
11862 mark_used_regs_combine (x
)
11865 RTX_CODE code
= GET_CODE (x
);
11866 unsigned int regno
;
11879 case ADDR_DIFF_VEC
:
11882 /* CC0 must die in the insn after it is set, so we don't need to take
11883 special note of it here. */
11889 /* If we are clobbering a MEM, mark any hard registers inside the
11890 address as used. */
11891 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11892 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11897 /* A hard reg in a wide mode may really be multiple registers.
11898 If so, mark all of them just like the first. */
11899 if (regno
< FIRST_PSEUDO_REGISTER
)
11901 unsigned int endregno
, r
;
11903 /* None of this applies to the stack, frame or arg pointers */
11904 if (regno
== STACK_POINTER_REGNUM
11905 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11906 || regno
== HARD_FRAME_POINTER_REGNUM
11908 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11909 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11911 || regno
== FRAME_POINTER_REGNUM
)
11914 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11915 for (r
= regno
; r
< endregno
; r
++)
11916 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11922 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11924 rtx testreg
= SET_DEST (x
);
11926 while (GET_CODE (testreg
) == SUBREG
11927 || GET_CODE (testreg
) == ZERO_EXTRACT
11928 || GET_CODE (testreg
) == SIGN_EXTRACT
11929 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11930 testreg
= XEXP (testreg
, 0);
11932 if (GET_CODE (testreg
) == MEM
)
11933 mark_used_regs_combine (XEXP (testreg
, 0));
11935 mark_used_regs_combine (SET_SRC (x
));
11943 /* Recursively scan the operands of this expression. */
11946 const char *fmt
= GET_RTX_FORMAT (code
);
11948 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11951 mark_used_regs_combine (XEXP (x
, i
));
11952 else if (fmt
[i
] == 'E')
11956 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11957 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11963 /* Remove register number REGNO from the dead registers list of INSN.
11965 Return the note used to record the death, if there was one. */
11968 remove_death (regno
, insn
)
11969 unsigned int regno
;
11972 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11976 REG_N_DEATHS (regno
)--;
11977 remove_note (insn
, note
);
11983 /* For each register (hardware or pseudo) used within expression X, if its
11984 death is in an instruction with cuid between FROM_CUID (inclusive) and
11985 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11986 list headed by PNOTES.
11988 That said, don't move registers killed by maybe_kill_insn.
11990 This is done when X is being merged by combination into TO_INSN. These
11991 notes will then be distributed as needed. */
11994 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11996 rtx maybe_kill_insn
;
12003 enum rtx_code code
= GET_CODE (x
);
12007 unsigned int regno
= REGNO (x
);
12008 rtx where_dead
= reg_last_death
[regno
];
12009 rtx before_dead
, after_dead
;
12011 /* Don't move the register if it gets killed in between from and to */
12012 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12013 && ! reg_referenced_p (x
, maybe_kill_insn
))
12016 /* WHERE_DEAD could be a USE insn made by combine, so first we
12017 make sure that we have insns with valid INSN_CUID values. */
12018 before_dead
= where_dead
;
12019 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12020 before_dead
= PREV_INSN (before_dead
);
12022 after_dead
= where_dead
;
12023 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12024 after_dead
= NEXT_INSN (after_dead
);
12026 if (before_dead
&& after_dead
12027 && INSN_CUID (before_dead
) >= from_cuid
12028 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12029 || (where_dead
!= after_dead
12030 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12032 rtx note
= remove_death (regno
, where_dead
);
12034 /* It is possible for the call above to return 0. This can occur
12035 when reg_last_death points to I2 or I1 that we combined with.
12036 In that case make a new note.
12038 We must also check for the case where X is a hard register
12039 and NOTE is a death note for a range of hard registers
12040 including X. In that case, we must put REG_DEAD notes for
12041 the remaining registers in place of NOTE. */
12043 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12044 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12045 > GET_MODE_SIZE (GET_MODE (x
))))
12047 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12048 unsigned int deadend
12049 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12050 GET_MODE (XEXP (note
, 0))));
12051 unsigned int ourend
12052 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12055 for (i
= deadregno
; i
< deadend
; i
++)
12056 if (i
< regno
|| i
>= ourend
)
12057 REG_NOTES (where_dead
)
12058 = gen_rtx_EXPR_LIST (REG_DEAD
,
12060 REG_NOTES (where_dead
));
12063 /* If we didn't find any note, or if we found a REG_DEAD note that
12064 covers only part of the given reg, and we have a multi-reg hard
12065 register, then to be safe we must check for REG_DEAD notes
12066 for each register other than the first. They could have
12067 their own REG_DEAD notes lying around. */
12068 else if ((note
== 0
12070 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12071 < GET_MODE_SIZE (GET_MODE (x
)))))
12072 && regno
< FIRST_PSEUDO_REGISTER
12073 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12075 unsigned int ourend
12076 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12077 unsigned int i
, offset
;
12081 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12085 for (i
= regno
+ offset
; i
< ourend
; i
++)
12086 move_deaths (regno_reg_rtx
[i
],
12087 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12090 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12092 XEXP (note
, 1) = *pnotes
;
12096 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12098 REG_N_DEATHS (regno
)++;
12104 else if (GET_CODE (x
) == SET
)
12106 rtx dest
= SET_DEST (x
);
12108 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12110 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12111 that accesses one word of a multi-word item, some
12112 piece of everything register in the expression is used by
12113 this insn, so remove any old death. */
12114 /* ??? So why do we test for equality of the sizes? */
12116 if (GET_CODE (dest
) == ZERO_EXTRACT
12117 || GET_CODE (dest
) == STRICT_LOW_PART
12118 || (GET_CODE (dest
) == SUBREG
12119 && (((GET_MODE_SIZE (GET_MODE (dest
))
12120 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12121 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12122 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12124 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12128 /* If this is some other SUBREG, we know it replaces the entire
12129 value, so use that as the destination. */
12130 if (GET_CODE (dest
) == SUBREG
)
12131 dest
= SUBREG_REG (dest
);
12133 /* If this is a MEM, adjust deaths of anything used in the address.
12134 For a REG (the only other possibility), the entire value is
12135 being replaced so the old value is not used in this insn. */
12137 if (GET_CODE (dest
) == MEM
)
12138 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12143 else if (GET_CODE (x
) == CLOBBER
)
12146 len
= GET_RTX_LENGTH (code
);
12147 fmt
= GET_RTX_FORMAT (code
);
12149 for (i
= 0; i
< len
; i
++)
12154 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12155 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12158 else if (fmt
[i
] == 'e')
12159 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12163 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12164 pattern of an insn. X must be a REG. */
12167 reg_bitfield_target_p (x
, body
)
12173 if (GET_CODE (body
) == SET
)
12175 rtx dest
= SET_DEST (body
);
12177 unsigned int regno
, tregno
, endregno
, endtregno
;
12179 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12180 target
= XEXP (dest
, 0);
12181 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12182 target
= SUBREG_REG (XEXP (dest
, 0));
12186 if (GET_CODE (target
) == SUBREG
)
12187 target
= SUBREG_REG (target
);
12189 if (GET_CODE (target
) != REG
)
12192 tregno
= REGNO (target
), regno
= REGNO (x
);
12193 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12194 return target
== x
;
12196 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12197 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12199 return endregno
> tregno
&& regno
< endtregno
;
12202 else if (GET_CODE (body
) == PARALLEL
)
12203 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12204 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12210 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12211 as appropriate. I3 and I2 are the insns resulting from the combination
12212 insns including FROM (I2 may be zero).
12214 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12215 not need REG_DEAD notes because they are being substituted for. This
12216 saves searching in the most common cases.
12218 Each note in the list is either ignored or placed on some insns, depending
12219 on the type of note. */
12222 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
12226 rtx elim_i2
, elim_i1
;
12228 rtx note
, next_note
;
12231 for (note
= notes
; note
; note
= next_note
)
12233 rtx place
= 0, place2
= 0;
12235 /* If this NOTE references a pseudo register, ensure it references
12236 the latest copy of that register. */
12237 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12238 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12239 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12241 next_note
= XEXP (note
, 1);
12242 switch (REG_NOTE_KIND (note
))
12246 case REG_EXEC_COUNT
:
12247 /* Doesn't matter much where we put this, as long as it's somewhere.
12248 It is preferable to keep these notes on branches, which is most
12249 likely to be i3. */
12253 case REG_VTABLE_REF
:
12254 /* ??? Should remain with *a particular* memory load. Given the
12255 nature of vtable data, the last insn seems relatively safe. */
12259 case REG_NON_LOCAL_GOTO
:
12260 if (GET_CODE (i3
) == JUMP_INSN
)
12262 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12268 case REG_EH_REGION
:
12269 /* These notes must remain with the call or trapping instruction. */
12270 if (GET_CODE (i3
) == CALL_INSN
)
12272 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12274 else if (flag_non_call_exceptions
)
12276 if (may_trap_p (i3
))
12278 else if (i2
&& may_trap_p (i2
))
12280 /* ??? Otherwise assume we've combined things such that we
12281 can now prove that the instructions can't trap. Drop the
12282 note in this case. */
12290 /* These notes must remain with the call. It should not be
12291 possible for both I2 and I3 to be a call. */
12292 if (GET_CODE (i3
) == CALL_INSN
)
12294 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12301 /* Any clobbers for i3 may still exist, and so we must process
12302 REG_UNUSED notes from that insn.
12304 Any clobbers from i2 or i1 can only exist if they were added by
12305 recog_for_combine. In that case, recog_for_combine created the
12306 necessary REG_UNUSED notes. Trying to keep any original
12307 REG_UNUSED notes from these insns can cause incorrect output
12308 if it is for the same register as the original i3 dest.
12309 In that case, we will notice that the register is set in i3,
12310 and then add a REG_UNUSED note for the destination of i3, which
12311 is wrong. However, it is possible to have REG_UNUSED notes from
12312 i2 or i1 for register which were both used and clobbered, so
12313 we keep notes from i2 or i1 if they will turn into REG_DEAD
12316 /* If this register is set or clobbered in I3, put the note there
12317 unless there is one already. */
12318 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12320 if (from_insn
!= i3
)
12323 if (! (GET_CODE (XEXP (note
, 0)) == REG
12324 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12325 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12328 /* Otherwise, if this register is used by I3, then this register
12329 now dies here, so we must put a REG_DEAD note here unless there
12331 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12332 && ! (GET_CODE (XEXP (note
, 0)) == REG
12333 ? find_regno_note (i3
, REG_DEAD
,
12334 REGNO (XEXP (note
, 0)))
12335 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12337 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12345 /* These notes say something about results of an insn. We can
12346 only support them if they used to be on I3 in which case they
12347 remain on I3. Otherwise they are ignored.
12349 If the note refers to an expression that is not a constant, we
12350 must also ignore the note since we cannot tell whether the
12351 equivalence is still true. It might be possible to do
12352 slightly better than this (we only have a problem if I2DEST
12353 or I1DEST is present in the expression), but it doesn't
12354 seem worth the trouble. */
12356 if (from_insn
== i3
12357 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12362 case REG_NO_CONFLICT
:
12363 /* These notes say something about how a register is used. They must
12364 be present on any use of the register in I2 or I3. */
12365 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12368 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12378 /* This can show up in several ways -- either directly in the
12379 pattern, or hidden off in the constant pool with (or without?)
12380 a REG_EQUAL note. */
12381 /* ??? Ignore the without-reg_equal-note problem for now. */
12382 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12383 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12384 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12385 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12389 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12390 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12391 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12392 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12400 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12401 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12402 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12404 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12406 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12407 LABEL_NUSES (JUMP_LABEL (place
))--;
12410 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12412 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12414 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12415 LABEL_NUSES (JUMP_LABEL (place2
))--;
12422 /* These notes say something about the value of a register prior
12423 to the execution of an insn. It is too much trouble to see
12424 if the note is still correct in all situations. It is better
12425 to simply delete it. */
12429 /* If the insn previously containing this note still exists,
12430 put it back where it was. Otherwise move it to the previous
12431 insn. Adjust the corresponding REG_LIBCALL note. */
12432 if (GET_CODE (from_insn
) != NOTE
)
12436 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12437 place
= prev_real_insn (from_insn
);
12439 XEXP (tem
, 0) = place
;
12440 /* If we're deleting the last remaining instruction of a
12441 libcall sequence, don't add the notes. */
12442 else if (XEXP (note
, 0) == from_insn
)
12448 /* This is handled similarly to REG_RETVAL. */
12449 if (GET_CODE (from_insn
) != NOTE
)
12453 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12454 place
= next_real_insn (from_insn
);
12456 XEXP (tem
, 0) = place
;
12457 /* If we're deleting the last remaining instruction of a
12458 libcall sequence, don't add the notes. */
12459 else if (XEXP (note
, 0) == from_insn
)
12465 /* If the register is used as an input in I3, it dies there.
12466 Similarly for I2, if it is non-zero and adjacent to I3.
12468 If the register is not used as an input in either I3 or I2
12469 and it is not one of the registers we were supposed to eliminate,
12470 there are two possibilities. We might have a non-adjacent I2
12471 or we might have somehow eliminated an additional register
12472 from a computation. For example, we might have had A & B where
12473 we discover that B will always be zero. In this case we will
12474 eliminate the reference to A.
12476 In both cases, we must search to see if we can find a previous
12477 use of A and put the death note there. */
12480 && GET_CODE (from_insn
) == CALL_INSN
12481 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12483 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12485 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12486 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12489 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12490 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12495 basic_block bb
= this_basic_block
;
12497 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12499 if (! INSN_P (tem
))
12501 if (tem
== bb
->head
)
12506 /* If the register is being set at TEM, see if that is all
12507 TEM is doing. If so, delete TEM. Otherwise, make this
12508 into a REG_UNUSED note instead. */
12509 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12511 rtx set
= single_set (tem
);
12512 rtx inner_dest
= 0;
12514 rtx cc0_setter
= NULL_RTX
;
12518 for (inner_dest
= SET_DEST (set
);
12519 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12520 || GET_CODE (inner_dest
) == SUBREG
12521 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12522 inner_dest
= XEXP (inner_dest
, 0))
12525 /* Verify that it was the set, and not a clobber that
12526 modified the register.
12528 CC0 targets must be careful to maintain setter/user
12529 pairs. If we cannot delete the setter due to side
12530 effects, mark the user with an UNUSED note instead
12533 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12534 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12536 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12537 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12538 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12542 /* Move the notes and links of TEM elsewhere.
12543 This might delete other dead insns recursively.
12544 First set the pattern to something that won't use
12547 PATTERN (tem
) = pc_rtx
;
12549 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12550 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12551 distribute_links (LOG_LINKS (tem
));
12553 PUT_CODE (tem
, NOTE
);
12554 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12555 NOTE_SOURCE_FILE (tem
) = 0;
12558 /* Delete the setter too. */
12561 PATTERN (cc0_setter
) = pc_rtx
;
12563 distribute_notes (REG_NOTES (cc0_setter
),
12564 cc0_setter
, cc0_setter
,
12565 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12566 distribute_links (LOG_LINKS (cc0_setter
));
12568 PUT_CODE (cc0_setter
, NOTE
);
12569 NOTE_LINE_NUMBER (cc0_setter
)
12570 = NOTE_INSN_DELETED
;
12571 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12575 /* If the register is both set and used here, put the
12576 REG_DEAD note here, but place a REG_UNUSED note
12577 here too unless there already is one. */
12578 else if (reg_referenced_p (XEXP (note
, 0),
12583 if (! find_regno_note (tem
, REG_UNUSED
,
12584 REGNO (XEXP (note
, 0))))
12586 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12591 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12593 /* If there isn't already a REG_UNUSED note, put one
12595 if (! find_regno_note (tem
, REG_UNUSED
,
12596 REGNO (XEXP (note
, 0))))
12601 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12602 || (GET_CODE (tem
) == CALL_INSN
12603 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12607 /* If we are doing a 3->2 combination, and we have a
12608 register which formerly died in i3 and was not used
12609 by i2, which now no longer dies in i3 and is used in
12610 i2 but does not die in i2, and place is between i2
12611 and i3, then we may need to move a link from place to
12613 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12614 && INSN_CUID (place
) > INSN_CUID (i2
)
12616 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12617 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12619 rtx links
= LOG_LINKS (place
);
12620 LOG_LINKS (place
) = 0;
12621 distribute_links (links
);
12626 if (tem
== bb
->head
)
12630 /* We haven't found an insn for the death note and it
12631 is still a REG_DEAD note, but we have hit the beginning
12632 of the block. If the existing life info says the reg
12633 was dead, there's nothing left to do. Otherwise, we'll
12634 need to do a global life update after combine. */
12635 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12636 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12637 REGNO (XEXP (note
, 0))))
12639 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12644 /* If the register is set or already dead at PLACE, we needn't do
12645 anything with this note if it is still a REG_DEAD note.
12646 We can here if it is set at all, not if is it totally replace,
12647 which is what `dead_or_set_p' checks, so also check for it being
12650 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12652 unsigned int regno
= REGNO (XEXP (note
, 0));
12654 /* Similarly, if the instruction on which we want to place
12655 the note is a noop, we'll need do a global live update
12656 after we remove them in delete_noop_moves. */
12657 if (noop_move_p (place
))
12659 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12663 if (dead_or_set_p (place
, XEXP (note
, 0))
12664 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12666 /* Unless the register previously died in PLACE, clear
12667 reg_last_death. [I no longer understand why this is
12669 if (reg_last_death
[regno
] != place
)
12670 reg_last_death
[regno
] = 0;
12674 reg_last_death
[regno
] = place
;
12676 /* If this is a death note for a hard reg that is occupying
12677 multiple registers, ensure that we are still using all
12678 parts of the object. If we find a piece of the object
12679 that is unused, we must arrange for an appropriate REG_DEAD
12680 note to be added for it. However, we can't just emit a USE
12681 and tag the note to it, since the register might actually
12682 be dead; so we recourse, and the recursive call then finds
12683 the previous insn that used this register. */
12685 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12686 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12688 unsigned int endregno
12689 = regno
+ HARD_REGNO_NREGS (regno
,
12690 GET_MODE (XEXP (note
, 0)));
12694 for (i
= regno
; i
< endregno
; i
++)
12695 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12696 && ! find_regno_fusage (place
, USE
, i
))
12697 || dead_or_set_regno_p (place
, i
))
12702 /* Put only REG_DEAD notes for pieces that are
12703 not already dead or set. */
12705 for (i
= regno
; i
< endregno
;
12706 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12708 rtx piece
= regno_reg_rtx
[i
];
12709 basic_block bb
= this_basic_block
;
12711 if (! dead_or_set_p (place
, piece
)
12712 && ! reg_bitfield_target_p (piece
,
12716 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12718 distribute_notes (new_note
, place
, place
,
12719 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12721 else if (! refers_to_regno_p (i
, i
+ 1,
12722 PATTERN (place
), 0)
12723 && ! find_regno_fusage (place
, USE
, i
))
12724 for (tem
= PREV_INSN (place
); ;
12725 tem
= PREV_INSN (tem
))
12727 if (! INSN_P (tem
))
12729 if (tem
== bb
->head
)
12731 SET_BIT (refresh_blocks
,
12732 this_basic_block
->index
);
12738 if (dead_or_set_p (tem
, piece
)
12739 || reg_bitfield_target_p (piece
,
12743 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12758 /* Any other notes should not be present at this point in the
12765 XEXP (note
, 1) = REG_NOTES (place
);
12766 REG_NOTES (place
) = note
;
12768 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12769 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12770 && GET_CODE (XEXP (note
, 0)) == REG
)
12771 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12775 if ((REG_NOTE_KIND (note
) == REG_DEAD
12776 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12777 && GET_CODE (XEXP (note
, 0)) == REG
)
12778 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12780 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12781 REG_NOTE_KIND (note
),
12783 REG_NOTES (place2
));
12788 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12789 I3, I2, and I1 to new locations. This is also called in one case to
12790 add a link pointing at I3 when I3's destination is changed. */
12793 distribute_links (links
)
12796 rtx link
, next_link
;
12798 for (link
= links
; link
; link
= next_link
)
12804 next_link
= XEXP (link
, 1);
12806 /* If the insn that this link points to is a NOTE or isn't a single
12807 set, ignore it. In the latter case, it isn't clear what we
12808 can do other than ignore the link, since we can't tell which
12809 register it was for. Such links wouldn't be used by combine
12812 It is not possible for the destination of the target of the link to
12813 have been changed by combine. The only potential of this is if we
12814 replace I3, I2, and I1 by I3 and I2. But in that case the
12815 destination of I2 also remains unchanged. */
12817 if (GET_CODE (XEXP (link
, 0)) == NOTE
12818 || (set
= single_set (XEXP (link
, 0))) == 0)
12821 reg
= SET_DEST (set
);
12822 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12823 || GET_CODE (reg
) == SIGN_EXTRACT
12824 || GET_CODE (reg
) == STRICT_LOW_PART
)
12825 reg
= XEXP (reg
, 0);
12827 /* A LOG_LINK is defined as being placed on the first insn that uses
12828 a register and points to the insn that sets the register. Start
12829 searching at the next insn after the target of the link and stop
12830 when we reach a set of the register or the end of the basic block.
12832 Note that this correctly handles the link that used to point from
12833 I3 to I2. Also note that not much searching is typically done here
12834 since most links don't point very far away. */
12836 for (insn
= NEXT_INSN (XEXP (link
, 0));
12837 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12838 || this_basic_block
->next_bb
->head
!= insn
));
12839 insn
= NEXT_INSN (insn
))
12840 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12842 if (reg_referenced_p (reg
, PATTERN (insn
)))
12846 else if (GET_CODE (insn
) == CALL_INSN
12847 && find_reg_fusage (insn
, USE
, reg
))
12853 /* If we found a place to put the link, place it there unless there
12854 is already a link to the same insn as LINK at that point. */
12860 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12861 if (XEXP (link2
, 0) == XEXP (link
, 0))
12866 XEXP (link
, 1) = LOG_LINKS (place
);
12867 LOG_LINKS (place
) = link
;
12869 /* Set added_links_insn to the earliest insn we added a
12871 if (added_links_insn
== 0
12872 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12873 added_links_insn
= place
;
12879 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12885 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12886 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12887 insn
= NEXT_INSN (insn
);
12889 if (INSN_UID (insn
) > max_uid_cuid
)
12892 return INSN_CUID (insn
);
12896 dump_combine_stats (file
)
12901 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12902 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12906 dump_combine_total_stats (file
)
12911 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12912 total_attempts
, total_merges
, total_extras
, total_successes
);