1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx
*reg_last_death
;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx
*reg_last_set
;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set
;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid
;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn
;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn
;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid
;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs
;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn
;
195 /* Basic block in which we are performing combines. */
196 static basic_block this_basic_block
;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks
;
202 static int need_refresh
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; int i
;} old_contents
;
318 union {rtx
*r
; int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST
PARAMS ((rtx
*, rtx
));
342 static void do_SUBST_INT
PARAMS ((int *, int));
343 static void init_reg_last_arrays
PARAMS ((void));
344 static void setup_incoming_promotions
PARAMS ((void));
345 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
346 static int cant_combine_insn_p
PARAMS ((rtx
));
347 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
348 static int sets_function_arg_p
PARAMS ((rtx
));
349 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
350 static int contains_muldiv
PARAMS ((rtx
));
351 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
352 static void undo_all
PARAMS ((void));
353 static void undo_commit
PARAMS ((void));
354 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
355 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
356 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
357 static rtx simplify_if_then_else
PARAMS ((rtx
));
358 static rtx simplify_set
PARAMS ((rtx
));
359 static rtx simplify_logical
PARAMS ((rtx
, int));
360 static rtx expand_compound_operation
PARAMS ((rtx
));
361 static rtx expand_field_assignment
PARAMS ((rtx
));
362 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
363 rtx
, unsigned HOST_WIDE_INT
, int,
365 static rtx extract_left_shift
PARAMS ((rtx
, int));
366 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
367 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
368 unsigned HOST_WIDE_INT
*));
369 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
370 unsigned HOST_WIDE_INT
, rtx
, int));
371 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
372 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
373 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
374 static rtx make_field_assignment
PARAMS ((rtx
));
375 static rtx apply_distributive_law
PARAMS ((rtx
));
376 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
377 unsigned HOST_WIDE_INT
));
378 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
379 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
380 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
381 enum rtx_code
, HOST_WIDE_INT
,
382 enum machine_mode
, int *));
383 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
385 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
386 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
387 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
389 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
390 static void update_table_tick
PARAMS ((rtx
));
391 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
392 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
393 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
394 static void record_dead_and_set_regs
PARAMS ((rtx
));
395 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
396 static rtx get_last_value
PARAMS ((rtx
));
397 static int use_crosses_set_p
PARAMS ((rtx
, int));
398 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
399 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
400 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
401 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
402 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
403 static void distribute_links
PARAMS ((rtx
));
404 static void mark_used_regs_combine
PARAMS ((rtx
));
405 static int insn_cuid
PARAMS ((rtx
));
406 static void record_promoted_value
PARAMS ((rtx
, rtx
));
407 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
408 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
410 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
411 insn. The substitution can be undone by undo_all. If INTO is already
412 set to NEWVAL, do not record this change. Because computing NEWVAL might
413 also call SUBST, we have to compute it before we put anything into
417 do_SUBST (into
, newval
)
423 if (oldval
== newval
)
426 /* We'd like to catch as many invalid transformations here as
427 possible. Unfortunately, there are way too many mode changes
428 that are perfectly valid, so we'd waste too much effort for
429 little gain doing the checks here. Focus on catching invalid
430 transformations involving integer constants. */
431 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
432 && GET_CODE (newval
) == CONST_INT
)
434 /* Sanity check that we're replacing oldval with a CONST_INT
435 that is a valid sign-extension for the original mode. */
436 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
440 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
441 CONST_INT is not valid, because after the replacement, the
442 original mode would be gone. Unfortunately, we can't tell
443 when do_SUBST is called to replace the operand thereof, so we
444 perform this test on oldval instead, checking whether an
445 invalid replacement took place before we got here. */
446 if ((GET_CODE (oldval
) == SUBREG
447 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
448 || (GET_CODE (oldval
) == ZERO_EXTEND
449 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
454 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
456 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
460 buf
->old_contents
.r
= oldval
;
463 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
466 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
468 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
469 for the value of a HOST_WIDE_INT value (including CONST_INT) is
473 do_SUBST_INT (into
, newval
)
479 if (oldval
== newval
)
483 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
485 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
489 buf
->old_contents
.i
= oldval
;
492 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
495 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
497 /* Main entry point for combiner. F is the first insn of the function.
498 NREGS is the first unused pseudo-reg number.
500 Return nonzero if the combiner has turned an indirect jump
501 instruction into a direct jump. */
503 combine_instructions (f
, nregs
)
512 rtx links
, nextlinks
;
514 int new_direct_jump_p
= 0;
516 combine_attempts
= 0;
519 combine_successes
= 0;
521 combine_max_regno
= nregs
;
523 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
524 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
526 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
528 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
530 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
531 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
532 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
533 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
535 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
536 reg_last_set_nonzero_bits
537 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
538 reg_last_set_sign_bit_copies
539 = (char *) xmalloc (nregs
* sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
548 if (INSN_UID (insn
) > i
)
551 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
554 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid
= 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 /* We need to initialize it here, because record_dead_and_set_regs may call
576 subst_prev_insn
= NULL_RTX
;
578 setup_incoming_promotions ();
580 refresh_blocks
= sbitmap_alloc (last_basic_block
);
581 sbitmap_zero (refresh_blocks
);
584 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
586 uid_cuid
[INSN_UID (insn
)] = ++i
;
592 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
594 record_dead_and_set_regs (insn
);
597 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
598 if (REG_NOTE_KIND (links
) == REG_INC
)
599 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
604 if (GET_CODE (insn
) == CODE_LABEL
)
608 nonzero_sign_valid
= 1;
610 /* Now scan all the insns in forward order. */
615 init_reg_last_arrays ();
616 setup_incoming_promotions ();
618 FOR_EACH_BB (this_basic_block
)
620 for (insn
= this_basic_block
->head
;
621 insn
!= NEXT_INSN (this_basic_block
->end
);
622 insn
= next
? next
: NEXT_INSN (insn
))
626 if (GET_CODE (insn
) == CODE_LABEL
)
629 else if (INSN_P (insn
))
631 /* See if we know about function return values before this
632 insn based upon SUBREG flags. */
633 check_promoted_subreg (insn
, PATTERN (insn
));
635 /* Try this insn with each insn it links back to. */
637 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
638 if ((next
= try_combine (insn
, XEXP (links
, 0),
639 NULL_RTX
, &new_direct_jump_p
)) != 0)
642 /* Try each sequence of three linked insns ending with this one. */
644 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
646 rtx link
= XEXP (links
, 0);
648 /* If the linked insn has been replaced by a note, then there
649 is no point in pursuing this chain any further. */
650 if (GET_CODE (link
) == NOTE
)
653 for (nextlinks
= LOG_LINKS (link
);
655 nextlinks
= XEXP (nextlinks
, 1))
656 if ((next
= try_combine (insn
, link
,
658 &new_direct_jump_p
)) != 0)
663 /* Try to combine a jump insn that uses CC0
664 with a preceding insn that sets CC0, and maybe with its
665 logical predecessor as well.
666 This is how we make decrement-and-branch insns.
667 We need this special code because data flow connections
668 via CC0 do not get entered in LOG_LINKS. */
670 if (GET_CODE (insn
) == JUMP_INSN
671 && (prev
= prev_nonnote_insn (insn
)) != 0
672 && GET_CODE (prev
) == INSN
673 && sets_cc0_p (PATTERN (prev
)))
675 if ((next
= try_combine (insn
, prev
,
676 NULL_RTX
, &new_direct_jump_p
)) != 0)
679 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
680 nextlinks
= XEXP (nextlinks
, 1))
681 if ((next
= try_combine (insn
, prev
,
683 &new_direct_jump_p
)) != 0)
687 /* Do the same for an insn that explicitly references CC0. */
688 if (GET_CODE (insn
) == INSN
689 && (prev
= prev_nonnote_insn (insn
)) != 0
690 && GET_CODE (prev
) == INSN
691 && sets_cc0_p (PATTERN (prev
))
692 && GET_CODE (PATTERN (insn
)) == SET
693 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
695 if ((next
= try_combine (insn
, prev
,
696 NULL_RTX
, &new_direct_jump_p
)) != 0)
699 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
700 nextlinks
= XEXP (nextlinks
, 1))
701 if ((next
= try_combine (insn
, prev
,
703 &new_direct_jump_p
)) != 0)
707 /* Finally, see if any of the insns that this insn links to
708 explicitly references CC0. If so, try this insn, that insn,
709 and its predecessor if it sets CC0. */
710 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
711 if (GET_CODE (XEXP (links
, 0)) == INSN
712 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
713 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
714 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
715 && GET_CODE (prev
) == INSN
716 && sets_cc0_p (PATTERN (prev
))
717 && (next
= try_combine (insn
, XEXP (links
, 0),
718 prev
, &new_direct_jump_p
)) != 0)
722 /* Try combining an insn with two different insns whose results it
724 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
725 for (nextlinks
= XEXP (links
, 1); nextlinks
;
726 nextlinks
= XEXP (nextlinks
, 1))
727 if ((next
= try_combine (insn
, XEXP (links
, 0),
729 &new_direct_jump_p
)) != 0)
732 if (GET_CODE (insn
) != NOTE
)
733 record_dead_and_set_regs (insn
);
742 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
743 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
744 new_direct_jump_p
|= purge_all_dead_edges (0);
745 delete_noop_moves (f
);
747 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
748 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
749 | PROP_KILL_DEAD_CODE
);
752 sbitmap_free (refresh_blocks
);
753 free (reg_nonzero_bits
);
754 free (reg_sign_bit_copies
);
755 free (reg_last_death
);
757 free (reg_last_set_value
);
758 free (reg_last_set_table_tick
);
759 free (reg_last_set_label
);
760 free (reg_last_set_invalid
);
761 free (reg_last_set_mode
);
762 free (reg_last_set_nonzero_bits
);
763 free (reg_last_set_sign_bit_copies
);
767 struct undo
*undo
, *next
;
768 for (undo
= undobuf
.frees
; undo
; undo
= next
)
776 total_attempts
+= combine_attempts
;
777 total_merges
+= combine_merges
;
778 total_extras
+= combine_extras
;
779 total_successes
+= combine_successes
;
781 nonzero_sign_valid
= 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p
;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs
= combine_max_regno
;
796 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
797 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
798 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
799 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
800 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
801 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
802 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
803 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
804 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode
;
817 rtx first
= get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
827 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
830 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode
, const0_rtx
)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x
, set
, data
)
853 void *data ATTRIBUTE_UNUSED
;
857 if (GET_CODE (x
) == REG
858 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
862 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
864 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
866 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
867 reg_sign_bit_copies
[REGNO (x
)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set
= expand_field_assignment (set
);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set
) == x
879 || (GET_CODE (SET_DEST (set
)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
882 && SUBREG_REG (SET_DEST (set
)) == x
))
884 rtx src
= SET_SRC (set
);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
897 && GET_CODE (src
) == CONST_INT
899 && 0 != (INTVAL (src
)
901 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
902 src
= GEN_INT (INTVAL (src
)
903 | ((HOST_WIDE_INT
) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x
))));
907 /* Don't call nonzero_bits if it cannot change anything. */
908 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
909 reg_nonzero_bits
[REGNO (x
)]
910 |= nonzero_bits (src
, nonzero_bits_mode
);
911 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
912 if (reg_sign_bit_copies
[REGNO (x
)] == 0
913 || reg_sign_bit_copies
[REGNO (x
)] > num
)
914 reg_sign_bit_copies
[REGNO (x
)] = num
;
918 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
919 reg_sign_bit_copies
[REGNO (x
)] = 1;
924 /* See if INSN can be combined into I3. PRED and SUCC are optionally
925 insns that were previously combined into I3 or that will be combined
926 into the merger of INSN and I3.
928 Return 0 if the combination is not allowed for any reason.
930 If the combination is allowed, *PDEST will be set to the single
931 destination of INSN and *PSRC to the single source, and this function
935 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
938 rtx pred ATTRIBUTE_UNUSED
;
943 rtx set
= 0, src
, dest
;
948 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
949 && next_active_insn (succ
) == i3
)
950 : next_active_insn (insn
) == i3
);
952 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
953 or a PARALLEL consisting of such a SET and CLOBBERs.
955 If INSN has CLOBBER parallel parts, ignore them for our processing.
956 By definition, these happen during the execution of the insn. When it
957 is merged with another insn, all bets are off. If they are, in fact,
958 needed and aren't also supplied in I3, they may be added by
959 recog_for_combine. Otherwise, it won't match.
961 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
964 Get the source and destination of INSN. If more than one, can't
967 if (GET_CODE (PATTERN (insn
)) == SET
)
968 set
= PATTERN (insn
);
969 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
970 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
972 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
974 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
976 switch (GET_CODE (elt
))
978 /* This is important to combine floating point insns
981 /* Combining an isolated USE doesn't make sense.
982 We depend here on combinable_i3pat to reject them. */
983 /* The code below this loop only verifies that the inputs of
984 the SET in INSN do not change. We call reg_set_between_p
985 to verify that the REG in the USE does not change between
987 If the USE in INSN was for a pseudo register, the matching
988 insn pattern will likely match any register; combining this
989 with any other USE would only be safe if we knew that the
990 used registers have identical values, or if there was
991 something to tell them apart, e.g. different modes. For
992 now, we forgo such complicated tests and simply disallow
993 combining of USES of pseudo registers with any other USE. */
994 if (GET_CODE (XEXP (elt
, 0)) == REG
995 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
997 rtx i3pat
= PATTERN (i3
);
998 int i
= XVECLEN (i3pat
, 0) - 1;
999 unsigned int regno
= REGNO (XEXP (elt
, 0));
1003 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1005 if (GET_CODE (i3elt
) == USE
1006 && GET_CODE (XEXP (i3elt
, 0)) == REG
1007 && (REGNO (XEXP (i3elt
, 0)) == regno
1008 ? reg_set_between_p (XEXP (elt
, 0),
1009 PREV_INSN (insn
), i3
)
1010 : regno
>= FIRST_PSEUDO_REGISTER
))
1017 /* We can ignore CLOBBERs. */
1022 /* Ignore SETs whose result isn't used but not those that
1023 have side-effects. */
1024 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1025 && ! side_effects_p (elt
))
1028 /* If we have already found a SET, this is a second one and
1029 so we cannot combine with this insn. */
1037 /* Anything else means we can't combine. */
1043 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1044 so don't do anything with it. */
1045 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1054 set
= expand_field_assignment (set
);
1055 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1057 /* Don't eliminate a store in the stack pointer. */
1058 if (dest
== stack_pointer_rtx
1059 /* If we couldn't eliminate a field assignment, we can't combine. */
1060 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1061 /* Don't combine with an insn that sets a register to itself if it has
1062 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1063 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1064 /* Can't merge an ASM_OPERANDS. */
1065 || GET_CODE (src
) == ASM_OPERANDS
1066 /* Can't merge a function call. */
1067 || GET_CODE (src
) == CALL
1068 /* Don't eliminate a function call argument. */
1069 || (GET_CODE (i3
) == CALL_INSN
1070 && (find_reg_fusage (i3
, USE
, dest
)
1071 || (GET_CODE (dest
) == REG
1072 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1073 && global_regs
[REGNO (dest
)])))
1074 /* Don't substitute into an incremented register. */
1075 || FIND_REG_INC_NOTE (i3
, dest
)
1076 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1078 /* Don't combine the end of a libcall into anything. */
1079 /* ??? This gives worse code, and appears to be unnecessary, since no
1080 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1081 use REG_RETVAL notes for noconflict blocks, but other code here
1082 makes sure that those insns don't disappear. */
1083 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1085 /* Make sure that DEST is not used after SUCC but before I3. */
1086 || (succ
&& ! all_adjacent
1087 && reg_used_between_p (dest
, succ
, i3
))
1088 /* Make sure that the value that is to be substituted for the register
1089 does not use any registers whose values alter in between. However,
1090 If the insns are adjacent, a use can't cross a set even though we
1091 think it might (this can happen for a sequence of insns each setting
1092 the same destination; reg_last_set of that register might point to
1093 a NOTE). If INSN has a REG_EQUIV note, the register is always
1094 equivalent to the memory so the substitution is valid even if there
1095 are intervening stores. Also, don't move a volatile asm or
1096 UNSPEC_VOLATILE across any other insns. */
1098 && (((GET_CODE (src
) != MEM
1099 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1100 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1101 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1102 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1103 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1104 better register allocation by not doing the combine. */
1105 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1106 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1107 /* Don't combine across a CALL_INSN, because that would possibly
1108 change whether the life span of some REGs crosses calls or not,
1109 and it is a pain to update that information.
1110 Exception: if source is a constant, moving it later can't hurt.
1111 Accept that special case, because it helps -fforce-addr a lot. */
1112 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1115 /* DEST must either be a REG or CC0. */
1116 if (GET_CODE (dest
) == REG
)
1118 /* If register alignment is being enforced for multi-word items in all
1119 cases except for parameters, it is possible to have a register copy
1120 insn referencing a hard register that is not allowed to contain the
1121 mode being copied and which would not be valid as an operand of most
1122 insns. Eliminate this problem by not combining with such an insn.
1124 Also, on some machines we don't want to extend the life of a hard
1127 if (GET_CODE (src
) == REG
1128 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1130 /* Don't extend the life of a hard register unless it is
1131 user variable (if we have few registers) or it can't
1132 fit into the desired register (meaning something special
1134 Also avoid substituting a return register into I3, because
1135 reload can't handle a conflict with constraints of other
1137 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1138 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1141 else if (GET_CODE (dest
) != CC0
)
1144 /* Don't substitute for a register intended as a clobberable operand.
1145 Similarly, don't substitute an expression containing a register that
1146 will be clobbered in I3. */
1147 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1148 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1149 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1150 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1152 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1155 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1156 or not), reject, unless nothing volatile comes between it and I3 */
1158 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1160 /* Make sure succ doesn't contain a volatile reference. */
1161 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1164 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1165 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1169 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1170 to be an explicit register variable, and was chosen for a reason. */
1172 if (GET_CODE (src
) == ASM_OPERANDS
1173 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1176 /* If there are any volatile insns between INSN and I3, reject, because
1177 they might affect machine state. */
1179 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1180 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1183 /* If INSN or I2 contains an autoincrement or autodecrement,
1184 make sure that register is not used between there and I3,
1185 and not already used in I3 either.
1186 Also insist that I3 not be a jump; if it were one
1187 and the incremented register were spilled, we would lose. */
1190 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1191 if (REG_NOTE_KIND (link
) == REG_INC
1192 && (GET_CODE (i3
) == JUMP_INSN
1193 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1194 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1199 /* Don't combine an insn that follows a CC0-setting insn.
1200 An insn that uses CC0 must not be separated from the one that sets it.
1201 We do, however, allow I2 to follow a CC0-setting insn if that insn
1202 is passed as I1; in that case it will be deleted also.
1203 We also allow combining in this case if all the insns are adjacent
1204 because that would leave the two CC0 insns adjacent as well.
1205 It would be more logical to test whether CC0 occurs inside I1 or I2,
1206 but that would be much slower, and this ought to be equivalent. */
1208 p
= prev_nonnote_insn (insn
);
1209 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1214 /* If we get here, we have passed all the tests and the combination is
1223 /* Check if PAT is an insn - or a part of it - used to set up an
1224 argument for a function in a hard register. */
1227 sets_function_arg_p (pat
)
1233 switch (GET_CODE (pat
))
1236 return sets_function_arg_p (PATTERN (pat
));
1239 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1240 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1246 inner_dest
= SET_DEST (pat
);
1247 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1248 || GET_CODE (inner_dest
) == SUBREG
1249 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1250 inner_dest
= XEXP (inner_dest
, 0);
1252 return (GET_CODE (inner_dest
) == REG
1253 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1254 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1263 /* LOC is the location within I3 that contains its pattern or the component
1264 of a PARALLEL of the pattern. We validate that it is valid for combining.
1266 One problem is if I3 modifies its output, as opposed to replacing it
1267 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1268 so would produce an insn that is not equivalent to the original insns.
1272 (set (reg:DI 101) (reg:DI 100))
1273 (set (subreg:SI (reg:DI 101) 0) <foo>)
1275 This is NOT equivalent to:
1277 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1278 (set (reg:DI 101) (reg:DI 100))])
1280 Not only does this modify 100 (in which case it might still be valid
1281 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1283 We can also run into a problem if I2 sets a register that I1
1284 uses and I1 gets directly substituted into I3 (not via I2). In that
1285 case, we would be getting the wrong value of I2DEST into I3, so we
1286 must reject the combination. This case occurs when I2 and I1 both
1287 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1288 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1289 of a SET must prevent combination from occurring.
1291 Before doing the above check, we first try to expand a field assignment
1292 into a set of logical operations.
1294 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1295 we place a register that is both set and used within I3. If more than one
1296 such register is detected, we fail.
1298 Return 1 if the combination is valid, zero otherwise. */
1301 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1307 rtx
*pi3dest_killed
;
1311 if (GET_CODE (x
) == SET
)
1313 rtx set
= expand_field_assignment (x
);
1314 rtx dest
= SET_DEST (set
);
1315 rtx src
= SET_SRC (set
);
1316 rtx inner_dest
= dest
;
1319 rtx inner_src
= src
;
1324 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1325 || GET_CODE (inner_dest
) == SUBREG
1326 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1327 inner_dest
= XEXP (inner_dest
, 0);
1329 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1332 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1333 || GET_CODE (inner_src
) == SUBREG
1334 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1335 inner_src
= XEXP (inner_src
, 0);
1337 /* If it is better that two different modes keep two different pseudos,
1338 avoid combining them. This avoids producing the following pattern
1340 (set (subreg:SI (reg/v:QI 21) 0)
1341 (lshiftrt:SI (reg/v:SI 20)
1343 If that were made, reload could not handle the pair of
1344 reg 20/21, since it would try to get any GENERAL_REGS
1345 but some of them don't handle QImode. */
1347 if (rtx_equal_p (inner_src
, i2dest
)
1348 && GET_CODE (inner_dest
) == REG
1349 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1353 /* Check for the case where I3 modifies its output, as
1355 if ((inner_dest
!= dest
1356 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1357 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1359 /* This is the same test done in can_combine_p except we can't test
1360 all_adjacent; we don't have to, since this instruction will stay
1361 in place, thus we are not considering increasing the lifetime of
1364 Also, if this insn sets a function argument, combining it with
1365 something that might need a spill could clobber a previous
1366 function argument; the all_adjacent test in can_combine_p also
1367 checks this; here, we do a more specific test for this case. */
1369 || (GET_CODE (inner_dest
) == REG
1370 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1371 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1372 GET_MODE (inner_dest
))))
1373 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1376 /* If DEST is used in I3, it is being killed in this insn,
1377 so record that for later.
1378 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1379 STACK_POINTER_REGNUM, since these are always considered to be
1380 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1381 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1382 && reg_referenced_p (dest
, PATTERN (i3
))
1383 && REGNO (dest
) != FRAME_POINTER_REGNUM
1384 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1385 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1387 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1388 && (REGNO (dest
) != ARG_POINTER_REGNUM
1389 || ! fixed_regs
[REGNO (dest
)])
1391 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1393 if (*pi3dest_killed
)
1396 *pi3dest_killed
= dest
;
1400 else if (GET_CODE (x
) == PARALLEL
)
1404 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1405 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1406 i1_not_in_src
, pi3dest_killed
))
1413 /* Return 1 if X is an arithmetic expression that contains a multiplication
1414 and division. We don't count multiplications by powers of two here. */
1420 switch (GET_CODE (x
))
1422 case MOD
: case DIV
: case UMOD
: case UDIV
:
1426 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1427 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1429 switch (GET_RTX_CLASS (GET_CODE (x
)))
1431 case 'c': case '<': case '2':
1432 return contains_muldiv (XEXP (x
, 0))
1433 || contains_muldiv (XEXP (x
, 1));
1436 return contains_muldiv (XEXP (x
, 0));
1444 /* Determine whether INSN can be used in a combination. Return nonzero if
1445 not. This is used in try_combine to detect early some cases where we
1446 can't perform combinations. */
1449 cant_combine_insn_p (insn
)
1455 /* If this isn't really an insn, we can't do anything.
1456 This can occur when flow deletes an insn that it has merged into an
1457 auto-increment address. */
1458 if (! INSN_P (insn
))
1461 /* Never combine loads and stores involving hard regs. The register
1462 allocator can usually handle such reg-reg moves by tying. If we allow
1463 the combiner to make substitutions of hard regs, we risk aborting in
1464 reload on machines that have SMALL_REGISTER_CLASSES.
1465 As an exception, we allow combinations involving fixed regs; these are
1466 not available to the register allocator so there's no risk involved. */
1468 set
= single_set (insn
);
1471 src
= SET_SRC (set
);
1472 dest
= SET_DEST (set
);
1473 if (GET_CODE (src
) == SUBREG
)
1474 src
= SUBREG_REG (src
);
1475 if (GET_CODE (dest
) == SUBREG
)
1476 dest
= SUBREG_REG (dest
);
1477 if (REG_P (src
) && REG_P (dest
)
1478 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1479 && ! fixed_regs
[REGNO (src
)])
1480 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1481 && ! fixed_regs
[REGNO (dest
)])))
1487 /* Try to combine the insns I1 and I2 into I3.
1488 Here I1 and I2 appear earlier than I3.
1489 I1 can be zero; then we combine just I2 into I3.
1491 If we are combining three insns and the resulting insn is not recognized,
1492 try splitting it into two insns. If that happens, I2 and I3 are retained
1493 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1496 Return 0 if the combination does not work. Then nothing is changed.
1497 If we did the combination, return the insn at which combine should
1500 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1501 new direct jump instruction. */
1504 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1506 int *new_direct_jump_p
;
1508 /* New patterns for I3 and I2, respectively. */
1509 rtx newpat
, newi2pat
= 0;
1510 int substed_i2
= 0, substed_i1
= 0;
1511 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1512 int added_sets_1
, added_sets_2
;
1513 /* Total number of SETs to put into I3. */
1515 /* Nonzero is I2's body now appears in I3. */
1517 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1518 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1519 /* Contains I3 if the destination of I3 is used in its source, which means
1520 that the old life of I3 is being killed. If that usage is placed into
1521 I2 and not in I3, a REG_DEAD note must be made. */
1522 rtx i3dest_killed
= 0;
1523 /* SET_DEST and SET_SRC of I2 and I1. */
1524 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1525 /* PATTERN (I2), or a copy of it in certain cases. */
1527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1528 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1529 int i1_feeds_i3
= 0;
1530 /* Notes that must be added to REG_NOTES in I3 and I2. */
1531 rtx new_i3_notes
, new_i2_notes
;
1532 /* Notes that we substituted I3 into I2 instead of the normal case. */
1533 int i3_subst_into_i2
= 0;
1534 /* Notes that I1, I2 or I3 is a MULT operation. */
1542 /* Exit early if one of the insns involved can't be used for
1544 if (cant_combine_insn_p (i3
)
1545 || cant_combine_insn_p (i2
)
1546 || (i1
&& cant_combine_insn_p (i1
))
1547 /* We also can't do anything if I3 has a
1548 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1551 /* ??? This gives worse code, and appears to be unnecessary, since no
1552 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1553 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1559 undobuf
.other_insn
= 0;
1561 /* Reset the hard register usage information. */
1562 CLEAR_HARD_REG_SET (newpat_used_regs
);
1564 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1565 code below, set I1 to be the earlier of the two insns. */
1566 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1567 temp
= i1
, i1
= i2
, i2
= temp
;
1569 added_links_insn
= 0;
1571 /* First check for one important special-case that the code below will
1572 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1573 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1574 we may be able to replace that destination with the destination of I3.
1575 This occurs in the common code where we compute both a quotient and
1576 remainder into a structure, in which case we want to do the computation
1577 directly into the structure to avoid register-register copies.
1579 Note that this case handles both multiple sets in I2 and also
1580 cases where I2 has a number of CLOBBER or PARALLELs.
1582 We make very conservative checks below and only try to handle the
1583 most common cases of this. For example, we only handle the case
1584 where I2 and I3 are adjacent to avoid making difficult register
1587 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1588 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1589 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1590 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1591 && GET_CODE (PATTERN (i2
)) == PARALLEL
1592 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1593 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1594 below would need to check what is inside (and reg_overlap_mentioned_p
1595 doesn't support those codes anyway). Don't allow those destinations;
1596 the resulting insn isn't likely to be recognized anyway. */
1597 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1598 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1599 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1600 SET_DEST (PATTERN (i3
)))
1601 && next_real_insn (i2
) == i3
)
1603 rtx p2
= PATTERN (i2
);
1605 /* Make sure that the destination of I3,
1606 which we are going to substitute into one output of I2,
1607 is not used within another output of I2. We must avoid making this:
1608 (parallel [(set (mem (reg 69)) ...)
1609 (set (reg 69) ...)])
1610 which is not well-defined as to order of actions.
1611 (Besides, reload can't handle output reloads for this.)
1613 The problem can also happen if the dest of I3 is a memory ref,
1614 if another dest in I2 is an indirect memory ref. */
1615 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1616 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1617 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1618 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1619 SET_DEST (XVECEXP (p2
, 0, i
))))
1622 if (i
== XVECLEN (p2
, 0))
1623 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1624 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1625 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1626 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1631 subst_low_cuid
= INSN_CUID (i2
);
1633 added_sets_2
= added_sets_1
= 0;
1634 i2dest
= SET_SRC (PATTERN (i3
));
1636 /* Replace the dest in I2 with our dest and make the resulting
1637 insn the new pattern for I3. Then skip to where we
1638 validate the pattern. Everything was set up above. */
1639 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1640 SET_DEST (PATTERN (i3
)));
1643 i3_subst_into_i2
= 1;
1644 goto validate_replacement
;
1648 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1649 one of those words to another constant, merge them by making a new
1652 && (temp
= single_set (i2
)) != 0
1653 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1654 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1655 && GET_CODE (SET_DEST (temp
)) == REG
1656 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1657 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1658 && GET_CODE (PATTERN (i3
)) == SET
1659 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1660 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1661 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1662 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1663 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1665 HOST_WIDE_INT lo
, hi
;
1667 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1668 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1671 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1672 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1675 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1677 /* We don't handle the case of the target word being wider
1678 than a host wide int. */
1679 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1682 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1683 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1684 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1686 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1687 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1688 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1690 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1691 >> (HOST_BITS_PER_WIDE_INT
- 1));
1693 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1694 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1695 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1696 (INTVAL (SET_SRC (PATTERN (i3
)))));
1698 hi
= lo
< 0 ? -1 : 0;
1701 /* We don't handle the case of the higher word not fitting
1702 entirely in either hi or lo. */
1707 subst_low_cuid
= INSN_CUID (i2
);
1708 added_sets_2
= added_sets_1
= 0;
1709 i2dest
= SET_DEST (temp
);
1711 SUBST (SET_SRC (temp
),
1712 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1714 newpat
= PATTERN (i2
);
1715 goto validate_replacement
;
1719 /* If we have no I1 and I2 looks like:
1720 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1722 make up a dummy I1 that is
1725 (set (reg:CC X) (compare:CC Y (const_int 0)))
1727 (We can ignore any trailing CLOBBERs.)
1729 This undoes a previous combination and allows us to match a branch-and-
1732 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1733 && XVECLEN (PATTERN (i2
), 0) >= 2
1734 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1735 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1737 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1738 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1739 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1740 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1741 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1742 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1744 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1745 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1750 /* We make I1 with the same INSN_UID as I2. This gives it
1751 the same INSN_CUID for value tracking. Our fake I1 will
1752 never appear in the insn stream so giving it the same INSN_UID
1753 as I2 will not cause a problem. */
1755 subst_prev_insn
= i1
1756 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1757 BLOCK_FOR_INSN (i2
), INSN_SCOPE (i2
),
1758 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1761 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1762 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1763 SET_DEST (PATTERN (i1
)));
1768 /* Verify that I2 and I1 are valid for combining. */
1769 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1770 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1776 /* Record whether I2DEST is used in I2SRC and similarly for the other
1777 cases. Knowing this will help in register status updating below. */
1778 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1779 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1780 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1782 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1784 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1786 /* Ensure that I3's pattern can be the destination of combines. */
1787 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1788 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1795 /* See if any of the insns is a MULT operation. Unless one is, we will
1796 reject a combination that is, since it must be slower. Be conservative
1798 if (GET_CODE (i2src
) == MULT
1799 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1800 || (GET_CODE (PATTERN (i3
)) == SET
1801 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1804 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1805 We used to do this EXCEPT in one case: I3 has a post-inc in an
1806 output operand. However, that exception can give rise to insns like
1808 which is a famous insn on the PDP-11 where the value of r3 used as the
1809 source was model-dependent. Avoid this sort of thing. */
1812 if (!(GET_CODE (PATTERN (i3
)) == SET
1813 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1814 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1815 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1816 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1817 /* It's not the exception. */
1820 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1821 if (REG_NOTE_KIND (link
) == REG_INC
1822 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1824 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1831 /* See if the SETs in I1 or I2 need to be kept around in the merged
1832 instruction: whenever the value set there is still needed past I3.
1833 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1835 For the SET in I1, we have two cases: If I1 and I2 independently
1836 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1837 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1838 in I1 needs to be kept around unless I1DEST dies or is set in either
1839 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1840 I1DEST. If so, we know I1 feeds into I2. */
1842 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1845 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1846 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1848 /* If the set in I2 needs to be kept around, we must make a copy of
1849 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1850 PATTERN (I2), we are only substituting for the original I1DEST, not into
1851 an already-substituted copy. This also prevents making self-referential
1852 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1855 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1856 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1860 i2pat
= copy_rtx (i2pat
);
1864 /* Substitute in the latest insn for the regs set by the earlier ones. */
1866 maxreg
= max_reg_num ();
1870 /* It is possible that the source of I2 or I1 may be performing an
1871 unneeded operation, such as a ZERO_EXTEND of something that is known
1872 to have the high part zero. Handle that case by letting subst look at
1873 the innermost one of them.
1875 Another way to do this would be to have a function that tries to
1876 simplify a single insn instead of merging two or more insns. We don't
1877 do this because of the potential of infinite loops and because
1878 of the potential extra memory required. However, doing it the way
1879 we are is a bit of a kludge and doesn't catch all cases.
1881 But only do this if -fexpensive-optimizations since it slows things down
1882 and doesn't usually win. */
1884 if (flag_expensive_optimizations
)
1886 /* Pass pc_rtx so no substitutions are done, just simplifications.
1887 The cases that we are interested in here do not involve the few
1888 cases were is_replaced is checked. */
1891 subst_low_cuid
= INSN_CUID (i1
);
1892 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1896 subst_low_cuid
= INSN_CUID (i2
);
1897 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1902 /* Many machines that don't use CC0 have insns that can both perform an
1903 arithmetic operation and set the condition code. These operations will
1904 be represented as a PARALLEL with the first element of the vector
1905 being a COMPARE of an arithmetic operation with the constant zero.
1906 The second element of the vector will set some pseudo to the result
1907 of the same arithmetic operation. If we simplify the COMPARE, we won't
1908 match such a pattern and so will generate an extra insn. Here we test
1909 for this case, where both the comparison and the operation result are
1910 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1911 I2SRC. Later we will make the PARALLEL that contains I2. */
1913 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1914 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1915 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1916 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1918 #ifdef EXTRA_CC_MODES
1920 enum machine_mode compare_mode
;
1923 newpat
= PATTERN (i3
);
1924 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1928 #ifdef EXTRA_CC_MODES
1929 /* See if a COMPARE with the operand we substituted in should be done
1930 with the mode that is currently being used. If not, do the same
1931 processing we do in `subst' for a SET; namely, if the destination
1932 is used only once, try to replace it with a register of the proper
1933 mode and also replace the COMPARE. */
1934 if (undobuf
.other_insn
== 0
1935 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1936 &undobuf
.other_insn
))
1937 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1939 != GET_MODE (SET_DEST (newpat
))))
1941 unsigned int regno
= REGNO (SET_DEST (newpat
));
1942 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1944 if (regno
< FIRST_PSEUDO_REGISTER
1945 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1946 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1948 if (regno
>= FIRST_PSEUDO_REGISTER
)
1949 SUBST (regno_reg_rtx
[regno
], new_dest
);
1951 SUBST (SET_DEST (newpat
), new_dest
);
1952 SUBST (XEXP (*cc_use
, 0), new_dest
);
1953 SUBST (SET_SRC (newpat
),
1954 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1957 undobuf
.other_insn
= 0;
1964 n_occurrences
= 0; /* `subst' counts here */
1966 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1967 need to make a unique copy of I2SRC each time we substitute it
1968 to avoid self-referential rtl. */
1970 subst_low_cuid
= INSN_CUID (i2
);
1971 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1972 ! i1_feeds_i3
&& i1dest_in_i1src
);
1975 /* Record whether i2's body now appears within i3's body. */
1976 i2_is_used
= n_occurrences
;
1979 /* If we already got a failure, don't try to do more. Otherwise,
1980 try to substitute in I1 if we have it. */
1982 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1984 /* Before we can do this substitution, we must redo the test done
1985 above (see detailed comments there) that ensures that I1DEST
1986 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1988 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1996 subst_low_cuid
= INSN_CUID (i1
);
1997 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2001 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2002 to count all the ways that I2SRC and I1SRC can be used. */
2003 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2004 && i2_is_used
+ added_sets_2
> 1)
2005 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2006 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2008 /* Fail if we tried to make a new register (we used to abort, but there's
2009 really no reason to). */
2010 || max_reg_num () != maxreg
2011 /* Fail if we couldn't do something and have a CLOBBER. */
2012 || GET_CODE (newpat
) == CLOBBER
2013 /* Fail if this new pattern is a MULT and we didn't have one before
2014 at the outer level. */
2015 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2022 /* If the actions of the earlier insns must be kept
2023 in addition to substituting them into the latest one,
2024 we must make a new PARALLEL for the latest insn
2025 to hold additional the SETs. */
2027 if (added_sets_1
|| added_sets_2
)
2031 if (GET_CODE (newpat
) == PARALLEL
)
2033 rtvec old
= XVEC (newpat
, 0);
2034 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2035 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2036 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2037 sizeof (old
->elem
[0]) * old
->num_elem
);
2042 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2043 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2044 XVECEXP (newpat
, 0, 0) = old
;
2048 XVECEXP (newpat
, 0, --total_sets
)
2049 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2050 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2054 /* If there is no I1, use I2's body as is. We used to also not do
2055 the subst call below if I2 was substituted into I3,
2056 but that could lose a simplification. */
2058 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2060 /* See comment where i2pat is assigned. */
2061 XVECEXP (newpat
, 0, --total_sets
)
2062 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2066 /* We come here when we are replacing a destination in I2 with the
2067 destination of I3. */
2068 validate_replacement
:
2070 /* Note which hard regs this insn has as inputs. */
2071 mark_used_regs_combine (newpat
);
2073 /* Is the result of combination a valid instruction? */
2074 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2076 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2077 the second SET's destination is a register that is unused. In that case,
2078 we just need the first SET. This can occur when simplifying a divmod
2079 insn. We *must* test for this case here because the code below that
2080 splits two independent SETs doesn't handle this case correctly when it
2081 updates the register status. Also check the case where the first
2082 SET's destination is unused. That would not cause incorrect code, but
2083 does cause an unneeded insn to remain. */
2085 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2086 && XVECLEN (newpat
, 0) == 2
2087 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2088 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2089 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2090 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2091 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2092 && asm_noperands (newpat
) < 0)
2094 newpat
= XVECEXP (newpat
, 0, 0);
2095 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2098 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2099 && XVECLEN (newpat
, 0) == 2
2100 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2101 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2102 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2103 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2104 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2105 && asm_noperands (newpat
) < 0)
2107 newpat
= XVECEXP (newpat
, 0, 1);
2108 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2111 /* If we were combining three insns and the result is a simple SET
2112 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2113 insns. There are two ways to do this. It can be split using a
2114 machine-specific method (like when you have an addition of a large
2115 constant) or by combine in the function find_split_point. */
2117 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2118 && asm_noperands (newpat
) < 0)
2120 rtx m_split
, *split
;
2121 rtx ni2dest
= i2dest
;
2123 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2124 use I2DEST as a scratch register will help. In the latter case,
2125 convert I2DEST to the mode of the source of NEWPAT if we can. */
2127 m_split
= split_insns (newpat
, i3
);
2129 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2130 inputs of NEWPAT. */
2132 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2133 possible to try that as a scratch reg. This would require adding
2134 more code to make it work though. */
2136 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2138 /* If I2DEST is a hard register or the only use of a pseudo,
2139 we can change its mode. */
2140 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2141 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2142 && GET_CODE (i2dest
) == REG
2143 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2144 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2145 && ! REG_USERVAR_P (i2dest
))))
2146 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2149 m_split
= split_insns (gen_rtx_PARALLEL
2151 gen_rtvec (2, newpat
,
2152 gen_rtx_CLOBBER (VOIDmode
,
2155 /* If the split with the mode-changed register didn't work, try
2156 the original register. */
2157 if (! m_split
&& ni2dest
!= i2dest
)
2160 m_split
= split_insns (gen_rtx_PARALLEL
2162 gen_rtvec (2, newpat
,
2163 gen_rtx_CLOBBER (VOIDmode
,
2169 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2171 m_split
= PATTERN (m_split
);
2172 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2173 if (insn_code_number
>= 0)
2176 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2177 && (next_real_insn (i2
) == i3
2178 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2181 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2182 newi2pat
= PATTERN (m_split
);
2184 i3set
= single_set (NEXT_INSN (m_split
));
2185 i2set
= single_set (m_split
);
2187 /* In case we changed the mode of I2DEST, replace it in the
2188 pseudo-register table here. We can't do it above in case this
2189 code doesn't get executed and we do a split the other way. */
2191 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2192 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2194 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2196 /* If I2 or I3 has multiple SETs, we won't know how to track
2197 register status, so don't use these insns. If I2's destination
2198 is used between I2 and I3, we also can't use these insns. */
2200 if (i2_code_number
>= 0 && i2set
&& i3set
2201 && (next_real_insn (i2
) == i3
2202 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2203 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2205 if (insn_code_number
>= 0)
2208 /* It is possible that both insns now set the destination of I3.
2209 If so, we must show an extra use of it. */
2211 if (insn_code_number
>= 0)
2213 rtx new_i3_dest
= SET_DEST (i3set
);
2214 rtx new_i2_dest
= SET_DEST (i2set
);
2216 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2217 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2218 || GET_CODE (new_i3_dest
) == SUBREG
)
2219 new_i3_dest
= XEXP (new_i3_dest
, 0);
2221 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2222 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2223 || GET_CODE (new_i2_dest
) == SUBREG
)
2224 new_i2_dest
= XEXP (new_i2_dest
, 0);
2226 if (GET_CODE (new_i3_dest
) == REG
2227 && GET_CODE (new_i2_dest
) == REG
2228 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2229 REG_N_SETS (REGNO (new_i2_dest
))++;
2233 /* If we can split it and use I2DEST, go ahead and see if that
2234 helps things be recognized. Verify that none of the registers
2235 are set between I2 and I3. */
2236 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2238 && GET_CODE (i2dest
) == REG
2240 /* We need I2DEST in the proper mode. If it is a hard register
2241 or the only use of a pseudo, we can change its mode. */
2242 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2243 || GET_MODE (*split
) == VOIDmode
2244 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2245 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2246 && ! REG_USERVAR_P (i2dest
)))
2247 && (next_real_insn (i2
) == i3
2248 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2249 /* We can't overwrite I2DEST if its value is still used by
2251 && ! reg_referenced_p (i2dest
, newpat
))
2253 rtx newdest
= i2dest
;
2254 enum rtx_code split_code
= GET_CODE (*split
);
2255 enum machine_mode split_mode
= GET_MODE (*split
);
2257 /* Get NEWDEST as a register in the proper mode. We have already
2258 validated that we can do this. */
2259 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2261 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2263 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2264 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2267 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2268 an ASHIFT. This can occur if it was inside a PLUS and hence
2269 appeared to be a memory address. This is a kludge. */
2270 if (split_code
== MULT
2271 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2272 && INTVAL (XEXP (*split
, 1)) > 0
2273 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2275 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2276 XEXP (*split
, 0), GEN_INT (i
)));
2277 /* Update split_code because we may not have a multiply
2279 split_code
= GET_CODE (*split
);
2282 #ifdef INSN_SCHEDULING
2283 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2284 be written as a ZERO_EXTEND. */
2285 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2287 #ifdef LOAD_EXTEND_OP
2288 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2289 what it really is. */
2290 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2292 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2293 SUBREG_REG (*split
)));
2296 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2297 SUBREG_REG (*split
)));
2301 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2302 SUBST (*split
, newdest
);
2303 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2305 /* If the split point was a MULT and we didn't have one before,
2306 don't use one now. */
2307 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2308 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2312 /* Check for a case where we loaded from memory in a narrow mode and
2313 then sign extended it, but we need both registers. In that case,
2314 we have a PARALLEL with both loads from the same memory location.
2315 We can split this into a load from memory followed by a register-register
2316 copy. This saves at least one insn, more if register allocation can
2319 We cannot do this if the destination of the first assignment is a
2320 condition code register or cc0. We eliminate this case by making sure
2321 the SET_DEST and SET_SRC have the same mode.
2323 We cannot do this if the destination of the second assignment is
2324 a register that we have already assumed is zero-extended. Similarly
2325 for a SUBREG of such a register. */
2327 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2328 && GET_CODE (newpat
) == PARALLEL
2329 && XVECLEN (newpat
, 0) == 2
2330 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2331 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2332 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2333 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2334 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2335 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2336 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2337 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2339 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2340 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2341 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2342 (GET_CODE (temp
) == REG
2343 && reg_nonzero_bits
[REGNO (temp
)] != 0
2344 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2345 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2346 && (reg_nonzero_bits
[REGNO (temp
)]
2347 != GET_MODE_MASK (word_mode
))))
2348 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2349 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2350 (GET_CODE (temp
) == REG
2351 && reg_nonzero_bits
[REGNO (temp
)] != 0
2352 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2353 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2354 && (reg_nonzero_bits
[REGNO (temp
)]
2355 != GET_MODE_MASK (word_mode
)))))
2356 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2357 SET_SRC (XVECEXP (newpat
, 0, 1)))
2358 && ! find_reg_note (i3
, REG_UNUSED
,
2359 SET_DEST (XVECEXP (newpat
, 0, 0))))
2363 newi2pat
= XVECEXP (newpat
, 0, 0);
2364 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2365 newpat
= XVECEXP (newpat
, 0, 1);
2366 SUBST (SET_SRC (newpat
),
2367 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2368 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2370 if (i2_code_number
>= 0)
2371 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2373 if (insn_code_number
>= 0)
2378 /* If we will be able to accept this, we have made a change to the
2379 destination of I3. This can invalidate a LOG_LINKS pointing
2380 to I3. No other part of combine.c makes such a transformation.
2382 The new I3 will have a destination that was previously the
2383 destination of I1 or I2 and which was used in i2 or I3. Call
2384 distribute_links to make a LOG_LINK from the next use of
2385 that destination. */
2387 PATTERN (i3
) = newpat
;
2388 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2390 /* I3 now uses what used to be its destination and which is
2391 now I2's destination. That means we need a LOG_LINK from
2392 I3 to I2. But we used to have one, so we still will.
2394 However, some later insn might be using I2's dest and have
2395 a LOG_LINK pointing at I3. We must remove this link.
2396 The simplest way to remove the link is to point it at I1,
2397 which we know will be a NOTE. */
2399 for (insn
= NEXT_INSN (i3
);
2400 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2401 || insn
!= this_basic_block
->next_bb
->head
);
2402 insn
= NEXT_INSN (insn
))
2404 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2406 for (link
= LOG_LINKS (insn
); link
;
2407 link
= XEXP (link
, 1))
2408 if (XEXP (link
, 0) == i3
)
2409 XEXP (link
, 0) = i1
;
2417 /* Similarly, check for a case where we have a PARALLEL of two independent
2418 SETs but we started with three insns. In this case, we can do the sets
2419 as two separate insns. This case occurs when some SET allows two
2420 other insns to combine, but the destination of that SET is still live. */
2422 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2423 && GET_CODE (newpat
) == PARALLEL
2424 && XVECLEN (newpat
, 0) == 2
2425 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2426 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2427 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2428 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2429 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2430 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2431 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2433 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2434 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2435 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2436 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2437 XVECEXP (newpat
, 0, 0))
2438 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2439 XVECEXP (newpat
, 0, 1))
2440 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2441 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2443 /* Normally, it doesn't matter which of the two is done first,
2444 but it does if one references cc0. In that case, it has to
2447 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2449 newi2pat
= XVECEXP (newpat
, 0, 0);
2450 newpat
= XVECEXP (newpat
, 0, 1);
2455 newi2pat
= XVECEXP (newpat
, 0, 1);
2456 newpat
= XVECEXP (newpat
, 0, 0);
2459 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2461 if (i2_code_number
>= 0)
2462 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2465 /* If it still isn't recognized, fail and change things back the way they
2467 if ((insn_code_number
< 0
2468 /* Is the result a reasonable ASM_OPERANDS? */
2469 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2475 /* If we had to change another insn, make sure it is valid also. */
2476 if (undobuf
.other_insn
)
2478 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2479 rtx new_other_notes
;
2482 CLEAR_HARD_REG_SET (newpat_used_regs
);
2484 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2487 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2493 PATTERN (undobuf
.other_insn
) = other_pat
;
2495 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2496 are still valid. Then add any non-duplicate notes added by
2497 recog_for_combine. */
2498 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2500 next
= XEXP (note
, 1);
2502 if (REG_NOTE_KIND (note
) == REG_UNUSED
2503 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2505 if (GET_CODE (XEXP (note
, 0)) == REG
)
2506 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2508 remove_note (undobuf
.other_insn
, note
);
2512 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2513 if (GET_CODE (XEXP (note
, 0)) == REG
)
2514 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2516 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2517 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2520 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2521 they are adjacent to each other or not. */
2523 rtx p
= prev_nonnote_insn (i3
);
2524 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2525 && sets_cc0_p (newi2pat
))
2533 /* We now know that we can do this combination. Merge the insns and
2534 update the status of registers and LOG_LINKS. */
2537 rtx i3notes
, i2notes
, i1notes
= 0;
2538 rtx i3links
, i2links
, i1links
= 0;
2541 /* Compute which registers we expect to eliminate. newi2pat may be setting
2542 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2543 same as i3dest, in which case newi2pat may be setting i1dest. */
2544 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2545 || i2dest_in_i2src
|| i2dest_in_i1src
2547 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2548 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2551 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2553 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2554 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2556 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2558 /* Ensure that we do not have something that should not be shared but
2559 occurs multiple times in the new insns. Check this by first
2560 resetting all the `used' flags and then copying anything is shared. */
2562 reset_used_flags (i3notes
);
2563 reset_used_flags (i2notes
);
2564 reset_used_flags (i1notes
);
2565 reset_used_flags (newpat
);
2566 reset_used_flags (newi2pat
);
2567 if (undobuf
.other_insn
)
2568 reset_used_flags (PATTERN (undobuf
.other_insn
));
2570 i3notes
= copy_rtx_if_shared (i3notes
);
2571 i2notes
= copy_rtx_if_shared (i2notes
);
2572 i1notes
= copy_rtx_if_shared (i1notes
);
2573 newpat
= copy_rtx_if_shared (newpat
);
2574 newi2pat
= copy_rtx_if_shared (newi2pat
);
2575 if (undobuf
.other_insn
)
2576 reset_used_flags (PATTERN (undobuf
.other_insn
));
2578 INSN_CODE (i3
) = insn_code_number
;
2579 PATTERN (i3
) = newpat
;
2581 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2583 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2585 reset_used_flags (call_usage
);
2586 call_usage
= copy_rtx (call_usage
);
2589 replace_rtx (call_usage
, i2dest
, i2src
);
2592 replace_rtx (call_usage
, i1dest
, i1src
);
2594 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2597 if (undobuf
.other_insn
)
2598 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2600 /* We had one special case above where I2 had more than one set and
2601 we replaced a destination of one of those sets with the destination
2602 of I3. In that case, we have to update LOG_LINKS of insns later
2603 in this basic block. Note that this (expensive) case is rare.
2605 Also, in this case, we must pretend that all REG_NOTEs for I2
2606 actually came from I3, so that REG_UNUSED notes from I2 will be
2607 properly handled. */
2609 if (i3_subst_into_i2
)
2611 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2612 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2613 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2614 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2615 && ! find_reg_note (i2
, REG_UNUSED
,
2616 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2617 for (temp
= NEXT_INSN (i2
);
2618 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2619 || this_basic_block
->head
!= temp
);
2620 temp
= NEXT_INSN (temp
))
2621 if (temp
!= i3
&& INSN_P (temp
))
2622 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2623 if (XEXP (link
, 0) == i2
)
2624 XEXP (link
, 0) = i3
;
2629 while (XEXP (link
, 1))
2630 link
= XEXP (link
, 1);
2631 XEXP (link
, 1) = i2notes
;
2645 INSN_CODE (i2
) = i2_code_number
;
2646 PATTERN (i2
) = newi2pat
;
2650 PUT_CODE (i2
, NOTE
);
2651 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2652 NOTE_SOURCE_FILE (i2
) = 0;
2659 PUT_CODE (i1
, NOTE
);
2660 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2661 NOTE_SOURCE_FILE (i1
) = 0;
2664 /* Get death notes for everything that is now used in either I3 or
2665 I2 and used to die in a previous insn. If we built two new
2666 patterns, move from I1 to I2 then I2 to I3 so that we get the
2667 proper movement on registers that I2 modifies. */
2671 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2672 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2675 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2678 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2680 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2683 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2686 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2689 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2692 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2693 know these are REG_UNUSED and want them to go to the desired insn,
2694 so we always pass it as i3. We have not counted the notes in
2695 reg_n_deaths yet, so we need to do so now. */
2697 if (newi2pat
&& new_i2_notes
)
2699 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2700 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2701 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2703 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2708 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2709 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2710 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2712 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2715 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2716 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2717 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2718 in that case, it might delete I2. Similarly for I2 and I1.
2719 Show an additional death due to the REG_DEAD note we make here. If
2720 we discard it in distribute_notes, we will decrement it again. */
2724 if (GET_CODE (i3dest_killed
) == REG
)
2725 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2727 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2728 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2730 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2732 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2734 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2738 if (i2dest_in_i2src
)
2740 if (GET_CODE (i2dest
) == REG
)
2741 REG_N_DEATHS (REGNO (i2dest
))++;
2743 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2744 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2745 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2747 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2748 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2749 NULL_RTX
, NULL_RTX
);
2752 if (i1dest_in_i1src
)
2754 if (GET_CODE (i1dest
) == REG
)
2755 REG_N_DEATHS (REGNO (i1dest
))++;
2757 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2758 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2759 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2761 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2762 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2763 NULL_RTX
, NULL_RTX
);
2766 distribute_links (i3links
);
2767 distribute_links (i2links
);
2768 distribute_links (i1links
);
2770 if (GET_CODE (i2dest
) == REG
)
2773 rtx i2_insn
= 0, i2_val
= 0, set
;
2775 /* The insn that used to set this register doesn't exist, and
2776 this life of the register may not exist either. See if one of
2777 I3's links points to an insn that sets I2DEST. If it does,
2778 that is now the last known value for I2DEST. If we don't update
2779 this and I2 set the register to a value that depended on its old
2780 contents, we will get confused. If this insn is used, thing
2781 will be set correctly in combine_instructions. */
2783 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2784 if ((set
= single_set (XEXP (link
, 0))) != 0
2785 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2786 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2788 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2790 /* If the reg formerly set in I2 died only once and that was in I3,
2791 zero its use count so it won't make `reload' do any work. */
2793 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2794 && ! i2dest_in_i2src
)
2796 regno
= REGNO (i2dest
);
2797 REG_N_SETS (regno
)--;
2801 if (i1
&& GET_CODE (i1dest
) == REG
)
2804 rtx i1_insn
= 0, i1_val
= 0, set
;
2806 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2807 if ((set
= single_set (XEXP (link
, 0))) != 0
2808 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2809 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2811 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2813 regno
= REGNO (i1dest
);
2814 if (! added_sets_1
&& ! i1dest_in_i1src
)
2815 REG_N_SETS (regno
)--;
2818 /* Update reg_nonzero_bits et al for any changes that may have been made
2819 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2820 important. Because newi2pat can affect nonzero_bits of newpat */
2822 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2823 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2825 /* Set new_direct_jump_p if a new return or simple jump instruction
2828 If I3 is now an unconditional jump, ensure that it has a
2829 BARRIER following it since it may have initially been a
2830 conditional jump. It may also be the last nonnote insn. */
2832 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2834 *new_direct_jump_p
= 1;
2836 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2837 || GET_CODE (temp
) != BARRIER
)
2838 emit_barrier_after (i3
);
2841 if (undobuf
.other_insn
!= NULL_RTX
2842 && (returnjump_p (undobuf
.other_insn
)
2843 || any_uncondjump_p (undobuf
.other_insn
)))
2845 *new_direct_jump_p
= 1;
2847 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2848 || GET_CODE (temp
) != BARRIER
)
2849 emit_barrier_after (undobuf
.other_insn
);
2852 /* An NOOP jump does not need barrier, but it does need cleaning up
2854 if (GET_CODE (newpat
) == SET
2855 && SET_SRC (newpat
) == pc_rtx
2856 && SET_DEST (newpat
) == pc_rtx
)
2857 *new_direct_jump_p
= 1;
2860 combine_successes
++;
2863 /* Clear this here, so that subsequent get_last_value calls are not
2865 subst_prev_insn
= NULL_RTX
;
2867 if (added_links_insn
2868 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2869 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2870 return added_links_insn
;
2872 return newi2pat
? i2
: i3
;
2875 /* Undo all the modifications recorded in undobuf. */
2880 struct undo
*undo
, *next
;
2882 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2886 *undo
->where
.i
= undo
->old_contents
.i
;
2888 *undo
->where
.r
= undo
->old_contents
.r
;
2890 undo
->next
= undobuf
.frees
;
2891 undobuf
.frees
= undo
;
2896 /* Clear this here, so that subsequent get_last_value calls are not
2898 subst_prev_insn
= NULL_RTX
;
2901 /* We've committed to accepting the changes we made. Move all
2902 of the undos to the free list. */
2907 struct undo
*undo
, *next
;
2909 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2912 undo
->next
= undobuf
.frees
;
2913 undobuf
.frees
= undo
;
2919 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2920 where we have an arithmetic expression and return that point. LOC will
2923 try_combine will call this function to see if an insn can be split into
2927 find_split_point (loc
, insn
)
2932 enum rtx_code code
= GET_CODE (x
);
2934 unsigned HOST_WIDE_INT len
= 0;
2935 HOST_WIDE_INT pos
= 0;
2937 rtx inner
= NULL_RTX
;
2939 /* First special-case some codes. */
2943 #ifdef INSN_SCHEDULING
2944 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2946 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2949 return find_split_point (&SUBREG_REG (x
), insn
);
2953 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2954 using LO_SUM and HIGH. */
2955 if (GET_CODE (XEXP (x
, 0)) == CONST
2956 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2959 gen_rtx_LO_SUM (Pmode
,
2960 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2962 return &XEXP (XEXP (x
, 0), 0);
2966 /* If we have a PLUS whose second operand is a constant and the
2967 address is not valid, perhaps will can split it up using
2968 the machine-specific way to split large constants. We use
2969 the first pseudo-reg (one of the virtual regs) as a placeholder;
2970 it will not remain in the result. */
2971 if (GET_CODE (XEXP (x
, 0)) == PLUS
2972 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2973 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2975 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2976 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2979 /* This should have produced two insns, each of which sets our
2980 placeholder. If the source of the second is a valid address,
2981 we can make put both sources together and make a split point
2985 && NEXT_INSN (seq
) != NULL_RTX
2986 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2987 && GET_CODE (seq
) == INSN
2988 && GET_CODE (PATTERN (seq
)) == SET
2989 && SET_DEST (PATTERN (seq
)) == reg
2990 && ! reg_mentioned_p (reg
,
2991 SET_SRC (PATTERN (seq
)))
2992 && GET_CODE (NEXT_INSN (seq
)) == INSN
2993 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2994 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2995 && memory_address_p (GET_MODE (x
),
2996 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2998 rtx src1
= SET_SRC (PATTERN (seq
));
2999 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3001 /* Replace the placeholder in SRC2 with SRC1. If we can
3002 find where in SRC2 it was placed, that can become our
3003 split point and we can replace this address with SRC2.
3004 Just try two obvious places. */
3006 src2
= replace_rtx (src2
, reg
, src1
);
3008 if (XEXP (src2
, 0) == src1
)
3009 split
= &XEXP (src2
, 0);
3010 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3011 && XEXP (XEXP (src2
, 0), 0) == src1
)
3012 split
= &XEXP (XEXP (src2
, 0), 0);
3016 SUBST (XEXP (x
, 0), src2
);
3021 /* If that didn't work, perhaps the first operand is complex and
3022 needs to be computed separately, so make a split point there.
3023 This will occur on machines that just support REG + CONST
3024 and have a constant moved through some previous computation. */
3026 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
3027 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3028 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
3030 return &XEXP (XEXP (x
, 0), 0);
3036 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3037 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3038 we need to put the operand into a register. So split at that
3041 if (SET_DEST (x
) == cc0_rtx
3042 && GET_CODE (SET_SRC (x
)) != COMPARE
3043 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3044 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
3045 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3046 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
3047 return &SET_SRC (x
);
3050 /* See if we can split SET_SRC as it stands. */
3051 split
= find_split_point (&SET_SRC (x
), insn
);
3052 if (split
&& split
!= &SET_SRC (x
))
3055 /* See if we can split SET_DEST as it stands. */
3056 split
= find_split_point (&SET_DEST (x
), insn
);
3057 if (split
&& split
!= &SET_DEST (x
))
3060 /* See if this is a bitfield assignment with everything constant. If
3061 so, this is an IOR of an AND, so split it into that. */
3062 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3063 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3064 <= HOST_BITS_PER_WIDE_INT
)
3065 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3066 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3067 && GET_CODE (SET_SRC (x
)) == CONST_INT
3068 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3069 + INTVAL (XEXP (SET_DEST (x
), 2)))
3070 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3071 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3073 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3074 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3075 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3076 rtx dest
= XEXP (SET_DEST (x
), 0);
3077 enum machine_mode mode
= GET_MODE (dest
);
3078 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3080 if (BITS_BIG_ENDIAN
)
3081 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3085 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3088 gen_binary (IOR
, mode
,
3089 gen_binary (AND
, mode
, dest
,
3090 gen_int_mode (~(mask
<< pos
),
3092 GEN_INT (src
<< pos
)));
3094 SUBST (SET_DEST (x
), dest
);
3096 split
= find_split_point (&SET_SRC (x
), insn
);
3097 if (split
&& split
!= &SET_SRC (x
))
3101 /* Otherwise, see if this is an operation that we can split into two.
3102 If so, try to split that. */
3103 code
= GET_CODE (SET_SRC (x
));
3108 /* If we are AND'ing with a large constant that is only a single
3109 bit and the result is only being used in a context where we
3110 need to know if it is zero or nonzero, replace it with a bit
3111 extraction. This will avoid the large constant, which might
3112 have taken more than one insn to make. If the constant were
3113 not a valid argument to the AND but took only one insn to make,
3114 this is no worse, but if it took more than one insn, it will
3117 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3118 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3119 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3120 && GET_CODE (SET_DEST (x
)) == REG
3121 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3122 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3123 && XEXP (*split
, 0) == SET_DEST (x
)
3124 && XEXP (*split
, 1) == const0_rtx
)
3126 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3127 XEXP (SET_SRC (x
), 0),
3128 pos
, NULL_RTX
, 1, 1, 0, 0);
3129 if (extraction
!= 0)
3131 SUBST (SET_SRC (x
), extraction
);
3132 return find_split_point (loc
, insn
);
3138 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3139 is known to be on, this can be converted into a NEG of a shift. */
3140 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3141 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3142 && 1 <= (pos
= exact_log2
3143 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3144 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3146 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3150 gen_rtx_LSHIFTRT (mode
,
3151 XEXP (SET_SRC (x
), 0),
3154 split
= find_split_point (&SET_SRC (x
), insn
);
3155 if (split
&& split
!= &SET_SRC (x
))
3161 inner
= XEXP (SET_SRC (x
), 0);
3163 /* We can't optimize if either mode is a partial integer
3164 mode as we don't know how many bits are significant
3166 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3167 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3171 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3177 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3178 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3180 inner
= XEXP (SET_SRC (x
), 0);
3181 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3182 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3184 if (BITS_BIG_ENDIAN
)
3185 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3186 unsignedp
= (code
== ZERO_EXTRACT
);
3194 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3196 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3198 /* For unsigned, we have a choice of a shift followed by an
3199 AND or two shifts. Use two shifts for field sizes where the
3200 constant might be too large. We assume here that we can
3201 always at least get 8-bit constants in an AND insn, which is
3202 true for every current RISC. */
3204 if (unsignedp
&& len
<= 8)
3209 (mode
, gen_lowpart_for_combine (mode
, inner
),
3211 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3213 split
= find_split_point (&SET_SRC (x
), insn
);
3214 if (split
&& split
!= &SET_SRC (x
))
3221 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3222 gen_rtx_ASHIFT (mode
,
3223 gen_lowpart_for_combine (mode
, inner
),
3224 GEN_INT (GET_MODE_BITSIZE (mode
)
3226 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3228 split
= find_split_point (&SET_SRC (x
), insn
);
3229 if (split
&& split
!= &SET_SRC (x
))
3234 /* See if this is a simple operation with a constant as the second
3235 operand. It might be that this constant is out of range and hence
3236 could be used as a split point. */
3237 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3238 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3239 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3240 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3241 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3242 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3243 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3245 return &XEXP (SET_SRC (x
), 1);
3247 /* Finally, see if this is a simple operation with its first operand
3248 not in a register. The operation might require this operand in a
3249 register, so return it as a split point. We can always do this
3250 because if the first operand were another operation, we would have
3251 already found it as a split point. */
3252 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3253 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3254 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3255 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3256 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3257 return &XEXP (SET_SRC (x
), 0);
3263 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3264 it is better to write this as (not (ior A B)) so we can split it.
3265 Similarly for IOR. */
3266 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3269 gen_rtx_NOT (GET_MODE (x
),
3270 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3272 XEXP (XEXP (x
, 0), 0),
3273 XEXP (XEXP (x
, 1), 0))));
3274 return find_split_point (loc
, insn
);
3277 /* Many RISC machines have a large set of logical insns. If the
3278 second operand is a NOT, put it first so we will try to split the
3279 other operand first. */
3280 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3282 rtx tem
= XEXP (x
, 0);
3283 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3284 SUBST (XEXP (x
, 1), tem
);
3292 /* Otherwise, select our actions depending on our rtx class. */
3293 switch (GET_RTX_CLASS (code
))
3295 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3297 split
= find_split_point (&XEXP (x
, 2), insn
);
3300 /* ... fall through ... */
3304 split
= find_split_point (&XEXP (x
, 1), insn
);
3307 /* ... fall through ... */
3309 /* Some machines have (and (shift ...) ...) insns. If X is not
3310 an AND, but XEXP (X, 0) is, use it as our split point. */
3311 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3312 return &XEXP (x
, 0);
3314 split
= find_split_point (&XEXP (x
, 0), insn
);
3320 /* Otherwise, we don't have a split point. */
3324 /* Throughout X, replace FROM with TO, and return the result.
3325 The result is TO if X is FROM;
3326 otherwise the result is X, but its contents may have been modified.
3327 If they were modified, a record was made in undobuf so that
3328 undo_all will (among other things) return X to its original state.
3330 If the number of changes necessary is too much to record to undo,
3331 the excess changes are not made, so the result is invalid.
3332 The changes already made can still be undone.
3333 undobuf.num_undo is incremented for such changes, so by testing that
3334 the caller can tell whether the result is valid.
3336 `n_occurrences' is incremented each time FROM is replaced.
3338 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3340 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3341 by copying if `n_occurrences' is nonzero. */
3344 subst (x
, from
, to
, in_dest
, unique_copy
)
3349 enum rtx_code code
= GET_CODE (x
);
3350 enum machine_mode op0_mode
= VOIDmode
;
3355 /* Two expressions are equal if they are identical copies of a shared
3356 RTX or if they are both registers with the same register number
3359 #define COMBINE_RTX_EQUAL_P(X,Y) \
3361 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3362 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3364 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3367 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3370 /* If X and FROM are the same register but different modes, they will
3371 not have been seen as equal above. However, flow.c will make a
3372 LOG_LINKS entry for that case. If we do nothing, we will try to
3373 rerecognize our original insn and, when it succeeds, we will
3374 delete the feeding insn, which is incorrect.
3376 So force this insn not to match in this (rare) case. */
3377 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3378 && REGNO (x
) == REGNO (from
))
3379 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3381 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3382 of which may contain things that can be combined. */
3383 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3386 /* It is possible to have a subexpression appear twice in the insn.
3387 Suppose that FROM is a register that appears within TO.
3388 Then, after that subexpression has been scanned once by `subst',
3389 the second time it is scanned, TO may be found. If we were
3390 to scan TO here, we would find FROM within it and create a
3391 self-referent rtl structure which is completely wrong. */
3392 if (COMBINE_RTX_EQUAL_P (x
, to
))
3395 /* Parallel asm_operands need special attention because all of the
3396 inputs are shared across the arms. Furthermore, unsharing the
3397 rtl results in recognition failures. Failure to handle this case
3398 specially can result in circular rtl.
3400 Solve this by doing a normal pass across the first entry of the
3401 parallel, and only processing the SET_DESTs of the subsequent
3404 if (code
== PARALLEL
3405 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3406 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3408 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3410 /* If this substitution failed, this whole thing fails. */
3411 if (GET_CODE (new) == CLOBBER
3412 && XEXP (new, 0) == const0_rtx
)
3415 SUBST (XVECEXP (x
, 0, 0), new);
3417 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3419 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3421 if (GET_CODE (dest
) != REG
3422 && GET_CODE (dest
) != CC0
3423 && GET_CODE (dest
) != PC
)
3425 new = subst (dest
, from
, to
, 0, unique_copy
);
3427 /* If this substitution failed, this whole thing fails. */
3428 if (GET_CODE (new) == CLOBBER
3429 && XEXP (new, 0) == const0_rtx
)
3432 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3438 len
= GET_RTX_LENGTH (code
);
3439 fmt
= GET_RTX_FORMAT (code
);
3441 /* We don't need to process a SET_DEST that is a register, CC0,
3442 or PC, so set up to skip this common case. All other cases
3443 where we want to suppress replacing something inside a
3444 SET_SRC are handled via the IN_DEST operand. */
3446 && (GET_CODE (SET_DEST (x
)) == REG
3447 || GET_CODE (SET_DEST (x
)) == CC0
3448 || GET_CODE (SET_DEST (x
)) == PC
))
3451 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3454 op0_mode
= GET_MODE (XEXP (x
, 0));
3456 for (i
= 0; i
< len
; i
++)
3461 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3463 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3465 new = (unique_copy
&& n_occurrences
3466 ? copy_rtx (to
) : to
);
3471 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3474 /* If this substitution failed, this whole thing
3476 if (GET_CODE (new) == CLOBBER
3477 && XEXP (new, 0) == const0_rtx
)
3481 SUBST (XVECEXP (x
, i
, j
), new);
3484 else if (fmt
[i
] == 'e')
3486 /* If this is a register being set, ignore it. */
3489 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3490 || code
== ZERO_EXTRACT
)
3492 && GET_CODE (new) == REG
)
3495 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3497 /* In general, don't install a subreg involving two
3498 modes not tieable. It can worsen register
3499 allocation, and can even make invalid reload
3500 insns, since the reg inside may need to be copied
3501 from in the outside mode, and that may be invalid
3502 if it is an fp reg copied in integer mode.
3504 We allow two exceptions to this: It is valid if
3505 it is inside another SUBREG and the mode of that
3506 SUBREG and the mode of the inside of TO is
3507 tieable and it is valid if X is a SET that copies
3510 if (GET_CODE (to
) == SUBREG
3511 && ! MODES_TIEABLE_P (GET_MODE (to
),
3512 GET_MODE (SUBREG_REG (to
)))
3513 && ! (code
== SUBREG
3514 && MODES_TIEABLE_P (GET_MODE (x
),
3515 GET_MODE (SUBREG_REG (to
))))
3517 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3520 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3522 #ifdef CLASS_CANNOT_CHANGE_MODE
3524 && GET_CODE (to
) == REG
3525 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3526 && (TEST_HARD_REG_BIT
3527 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3529 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3531 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3534 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3538 /* If we are in a SET_DEST, suppress most cases unless we
3539 have gone inside a MEM, in which case we want to
3540 simplify the address. We assume here that things that
3541 are actually part of the destination have their inner
3542 parts in the first expression. This is true for SUBREG,
3543 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3544 things aside from REG and MEM that should appear in a
3546 new = subst (XEXP (x
, i
), from
, to
,
3548 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3549 || code
== ZERO_EXTRACT
))
3551 && i
== 0), unique_copy
);
3553 /* If we found that we will have to reject this combination,
3554 indicate that by returning the CLOBBER ourselves, rather than
3555 an expression containing it. This will speed things up as
3556 well as prevent accidents where two CLOBBERs are considered
3557 to be equal, thus producing an incorrect simplification. */
3559 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3562 if (GET_CODE (new) == CONST_INT
&& GET_CODE (x
) == SUBREG
)
3564 enum machine_mode mode
= GET_MODE (x
);
3566 x
= simplify_subreg (GET_MODE (x
), new,
3567 GET_MODE (SUBREG_REG (x
)),
3570 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3572 else if (GET_CODE (new) == CONST_INT
3573 && GET_CODE (x
) == ZERO_EXTEND
)
3575 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3576 new, GET_MODE (XEXP (x
, 0)));
3581 SUBST (XEXP (x
, i
), new);
3586 /* Try to simplify X. If the simplification changed the code, it is likely
3587 that further simplification will help, so loop, but limit the number
3588 of repetitions that will be performed. */
3590 for (i
= 0; i
< 4; i
++)
3592 /* If X is sufficiently simple, don't bother trying to do anything
3594 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3595 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3597 if (GET_CODE (x
) == code
)
3600 code
= GET_CODE (x
);
3602 /* We no longer know the original mode of operand 0 since we
3603 have changed the form of X) */
3604 op0_mode
= VOIDmode
;
3610 /* Simplify X, a piece of RTL. We just operate on the expression at the
3611 outer level; call `subst' to simplify recursively. Return the new
3614 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3615 will be the iteration even if an expression with a code different from
3616 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3619 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3621 enum machine_mode op0_mode
;
3625 enum rtx_code code
= GET_CODE (x
);
3626 enum machine_mode mode
= GET_MODE (x
);
3631 /* If this is a commutative operation, put a constant last and a complex
3632 expression first. We don't need to do this for comparisons here. */
3633 if (GET_RTX_CLASS (code
) == 'c'
3634 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3637 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3638 SUBST (XEXP (x
, 1), temp
);
3641 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3642 sign extension of a PLUS with a constant, reverse the order of the sign
3643 extension and the addition. Note that this not the same as the original
3644 code, but overflow is undefined for signed values. Also note that the
3645 PLUS will have been partially moved "inside" the sign-extension, so that
3646 the first operand of X will really look like:
3647 (ashiftrt (plus (ashift A C4) C5) C4).
3649 (plus (ashiftrt (ashift A C4) C2) C4)
3650 and replace the first operand of X with that expression. Later parts
3651 of this function may simplify the expression further.
3653 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3654 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3655 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3657 We do this to simplify address expressions. */
3659 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3660 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3661 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3662 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3663 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3664 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3665 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3666 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3667 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3668 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3669 XEXP (XEXP (x
, 0), 1))) != 0)
3672 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3673 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3674 INTVAL (XEXP (XEXP (x
, 0), 1)));
3676 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3677 INTVAL (XEXP (XEXP (x
, 0), 1)));
3679 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3682 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3683 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3684 things. Check for cases where both arms are testing the same
3687 Don't do anything if all operands are very simple. */
3689 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3690 || GET_RTX_CLASS (code
) == '<')
3691 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3692 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3693 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3695 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3696 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3697 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3699 || (GET_RTX_CLASS (code
) == '1'
3700 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3701 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3702 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3705 rtx cond
, true_rtx
, false_rtx
;
3707 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3709 /* If everything is a comparison, what we have is highly unlikely
3710 to be simpler, so don't use it. */
3711 && ! (GET_RTX_CLASS (code
) == '<'
3712 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3713 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3715 rtx cop1
= const0_rtx
;
3716 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3718 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3721 /* Simplify the alternative arms; this may collapse the true and
3722 false arms to store-flag values. */
3723 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3724 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3726 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3727 is unlikely to be simpler. */
3728 if (general_operand (true_rtx
, VOIDmode
)
3729 && general_operand (false_rtx
, VOIDmode
))
3731 /* Restarting if we generate a store-flag expression will cause
3732 us to loop. Just drop through in this case. */
3734 /* If the result values are STORE_FLAG_VALUE and zero, we can
3735 just make the comparison operation. */
3736 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3737 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3738 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3739 && reverse_condition (cond_code
) != UNKNOWN
)
3740 x
= gen_binary (reverse_condition (cond_code
),
3743 /* Likewise, we can make the negate of a comparison operation
3744 if the result values are - STORE_FLAG_VALUE and zero. */
3745 else if (GET_CODE (true_rtx
) == CONST_INT
3746 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3747 && false_rtx
== const0_rtx
)
3748 x
= simplify_gen_unary (NEG
, mode
,
3749 gen_binary (cond_code
, mode
, cond
,
3752 else if (GET_CODE (false_rtx
) == CONST_INT
3753 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3754 && true_rtx
== const0_rtx
)
3755 x
= simplify_gen_unary (NEG
, mode
,
3756 gen_binary (reverse_condition
3761 return gen_rtx_IF_THEN_ELSE (mode
,
3762 gen_binary (cond_code
, VOIDmode
,
3764 true_rtx
, false_rtx
);
3766 code
= GET_CODE (x
);
3767 op0_mode
= VOIDmode
;
3772 /* Try to fold this expression in case we have constants that weren't
3775 switch (GET_RTX_CLASS (code
))
3778 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3782 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3783 if (cmp_mode
== VOIDmode
)
3785 cmp_mode
= GET_MODE (XEXP (x
, 1));
3786 if (cmp_mode
== VOIDmode
)
3787 cmp_mode
= op0_mode
;
3789 temp
= simplify_relational_operation (code
, cmp_mode
,
3790 XEXP (x
, 0), XEXP (x
, 1));
3792 #ifdef FLOAT_STORE_FLAG_VALUE
3793 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3795 if (temp
== const0_rtx
)
3796 temp
= CONST0_RTX (mode
);
3798 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3805 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3809 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3810 XEXP (x
, 1), XEXP (x
, 2));
3817 code
= GET_CODE (temp
);
3818 op0_mode
= VOIDmode
;
3819 mode
= GET_MODE (temp
);
3822 /* First see if we can apply the inverse distributive law. */
3823 if (code
== PLUS
|| code
== MINUS
3824 || code
== AND
|| code
== IOR
|| code
== XOR
)
3826 x
= apply_distributive_law (x
);
3827 code
= GET_CODE (x
);
3828 op0_mode
= VOIDmode
;
3831 /* If CODE is an associative operation not otherwise handled, see if we
3832 can associate some operands. This can win if they are constants or
3833 if they are logically related (i.e. (a & b) & a). */
3834 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3835 || code
== AND
|| code
== IOR
|| code
== XOR
3836 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3837 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3838 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3840 if (GET_CODE (XEXP (x
, 0)) == code
)
3842 rtx other
= XEXP (XEXP (x
, 0), 0);
3843 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3844 rtx inner_op1
= XEXP (x
, 1);
3847 /* Make sure we pass the constant operand if any as the second
3848 one if this is a commutative operation. */
3849 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3851 rtx tem
= inner_op0
;
3852 inner_op0
= inner_op1
;
3855 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3856 : code
== DIV
? MULT
3858 mode
, inner_op0
, inner_op1
);
3860 /* For commutative operations, try the other pair if that one
3862 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3864 other
= XEXP (XEXP (x
, 0), 1);
3865 inner
= simplify_binary_operation (code
, mode
,
3866 XEXP (XEXP (x
, 0), 0),
3871 return gen_binary (code
, mode
, other
, inner
);
3875 /* A little bit of algebraic simplification here. */
3879 /* Ensure that our address has any ASHIFTs converted to MULT in case
3880 address-recognizing predicates are called later. */
3881 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3882 SUBST (XEXP (x
, 0), temp
);
3886 if (op0_mode
== VOIDmode
)
3887 op0_mode
= GET_MODE (SUBREG_REG (x
));
3889 /* simplify_subreg can't use gen_lowpart_for_combine. */
3890 if (CONSTANT_P (SUBREG_REG (x
))
3891 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3892 /* Don't call gen_lowpart_for_combine if the inner mode
3893 is VOIDmode and we cannot simplify it, as SUBREG without
3894 inner mode is invalid. */
3895 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3896 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3897 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3899 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3903 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3909 /* Don't change the mode of the MEM if that would change the meaning
3911 if (GET_CODE (SUBREG_REG (x
)) == MEM
3912 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3913 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3914 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3916 /* Note that we cannot do any narrowing for non-constants since
3917 we might have been counting on using the fact that some bits were
3918 zero. We now do this in the SET. */
3923 /* (not (plus X -1)) can become (neg X). */
3924 if (GET_CODE (XEXP (x
, 0)) == PLUS
3925 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3926 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3928 /* Similarly, (not (neg X)) is (plus X -1). */
3929 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3930 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3932 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3933 if (GET_CODE (XEXP (x
, 0)) == XOR
3934 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3935 && (temp
= simplify_unary_operation (NOT
, mode
,
3936 XEXP (XEXP (x
, 0), 1),
3938 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3940 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3941 other than 1, but that is not valid. We could do a similar
3942 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3943 but this doesn't seem common enough to bother with. */
3944 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3945 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3946 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3948 XEXP (XEXP (x
, 0), 1));
3950 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3951 && subreg_lowpart_p (XEXP (x
, 0))
3952 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3953 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3954 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3955 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3957 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3959 x
= gen_rtx_ROTATE (inner_mode
,
3960 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3962 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3963 return gen_lowpart_for_combine (mode
, x
);
3966 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3967 reversing the comparison code if valid. */
3968 if (STORE_FLAG_VALUE
== -1
3969 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3970 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3971 XEXP (XEXP (x
, 0), 1))))
3974 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3975 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3976 perform the above simplification. */
3978 if (STORE_FLAG_VALUE
== -1
3979 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3980 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3981 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3982 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3984 /* Apply De Morgan's laws to reduce number of patterns for machines
3985 with negating logical insns (and-not, nand, etc.). If result has
3986 only one NOT, put it first, since that is how the patterns are
3989 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3991 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3992 enum machine_mode op_mode
;
3994 op_mode
= GET_MODE (in1
);
3995 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3997 op_mode
= GET_MODE (in2
);
3998 if (op_mode
== VOIDmode
)
4000 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4002 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4005 in2
= in1
; in1
= tem
;
4008 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4014 /* (neg (plus X 1)) can become (not X). */
4015 if (GET_CODE (XEXP (x
, 0)) == PLUS
4016 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
4017 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
4019 /* Similarly, (neg (not X)) is (plus X 1). */
4020 if (GET_CODE (XEXP (x
, 0)) == NOT
)
4021 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
4023 /* (neg (minus X Y)) can become (minus Y X). This transformation
4024 isn't safe for modes with signed zeros, since if X and Y are
4025 both +0, (minus Y X) is the same as (minus X Y). If the rounding
4026 mode is towards +infinity (or -infinity) then the two expressions
4027 will be rounded differently. */
4028 if (GET_CODE (XEXP (x
, 0)) == MINUS
4029 && !HONOR_SIGNED_ZEROS (mode
)
4030 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
4031 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
4032 XEXP (XEXP (x
, 0), 0));
4034 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4035 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
4036 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4037 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4039 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4040 if we can then eliminate the NEG (e.g.,
4041 if the operand is a constant). */
4043 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
4045 temp
= simplify_unary_operation (NEG
, mode
,
4046 XEXP (XEXP (x
, 0), 0), mode
);
4048 return gen_binary (ASHIFT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
4051 temp
= expand_compound_operation (XEXP (x
, 0));
4053 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4054 replaced by (lshiftrt X C). This will convert
4055 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4057 if (GET_CODE (temp
) == ASHIFTRT
4058 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4059 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4060 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4061 INTVAL (XEXP (temp
, 1)));
4063 /* If X has only a single bit that might be nonzero, say, bit I, convert
4064 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4065 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4066 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4067 or a SUBREG of one since we'd be making the expression more
4068 complex if it was just a register. */
4070 if (GET_CODE (temp
) != REG
4071 && ! (GET_CODE (temp
) == SUBREG
4072 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4073 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4075 rtx temp1
= simplify_shift_const
4076 (NULL_RTX
, ASHIFTRT
, mode
,
4077 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4078 GET_MODE_BITSIZE (mode
) - 1 - i
),
4079 GET_MODE_BITSIZE (mode
) - 1 - i
);
4081 /* If all we did was surround TEMP with the two shifts, we
4082 haven't improved anything, so don't use it. Otherwise,
4083 we are better off with TEMP1. */
4084 if (GET_CODE (temp1
) != ASHIFTRT
4085 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4086 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4092 /* We can't handle truncation to a partial integer mode here
4093 because we don't know the real bitsize of the partial
4095 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4098 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4099 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4100 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4102 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4103 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4105 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4106 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4107 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4108 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4109 return XEXP (XEXP (x
, 0), 0);
4111 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4112 (OP:SI foo:SI) if OP is NEG or ABS. */
4113 if ((GET_CODE (XEXP (x
, 0)) == ABS
4114 || GET_CODE (XEXP (x
, 0)) == NEG
)
4115 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4116 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4117 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4118 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4119 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4121 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4123 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4124 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4125 && subreg_lowpart_p (XEXP (x
, 0)))
4126 return SUBREG_REG (XEXP (x
, 0));
4128 /* If we know that the value is already truncated, we can
4129 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4130 is nonzero for the corresponding modes. But don't do this
4131 for an (LSHIFTRT (MULT ...)) since this will cause problems
4132 with the umulXi3_highpart patterns. */
4133 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4134 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4135 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4136 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4137 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4138 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4139 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4141 /* A truncate of a comparison can be replaced with a subreg if
4142 STORE_FLAG_VALUE permits. This is like the previous test,
4143 but it works even if the comparison is done in a mode larger
4144 than HOST_BITS_PER_WIDE_INT. */
4145 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4146 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4147 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4148 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4150 /* Similarly, a truncate of a register whose value is a
4151 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4153 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4154 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4155 && (temp
= get_last_value (XEXP (x
, 0)))
4156 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4157 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4161 case FLOAT_TRUNCATE
:
4162 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4163 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4164 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4165 return XEXP (XEXP (x
, 0), 0);
4167 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4168 (OP:SF foo:SF) if OP is NEG or ABS. */
4169 if ((GET_CODE (XEXP (x
, 0)) == ABS
4170 || GET_CODE (XEXP (x
, 0)) == NEG
)
4171 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4172 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4173 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4174 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4176 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4177 is (float_truncate:SF x). */
4178 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4179 && subreg_lowpart_p (XEXP (x
, 0))
4180 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4181 return SUBREG_REG (XEXP (x
, 0));
4186 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4187 using cc0, in which case we want to leave it as a COMPARE
4188 so we can distinguish it from a register-register-copy. */
4189 if (XEXP (x
, 1) == const0_rtx
)
4192 /* x - 0 is the same as x unless x's mode has signed zeros and
4193 allows rounding towards -infinity. Under those conditions,
4195 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4196 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4197 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4203 /* (const (const X)) can become (const X). Do it this way rather than
4204 returning the inner CONST since CONST can be shared with a
4206 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4207 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4212 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4213 can add in an offset. find_split_point will split this address up
4214 again if it doesn't match. */
4215 if (GET_CODE (XEXP (x
, 0)) == HIGH
4216 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4222 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4223 outermost. That's because that's the way indexed addresses are
4224 supposed to appear. This code used to check many more cases, but
4225 they are now checked elsewhere. */
4226 if (GET_CODE (XEXP (x
, 0)) == PLUS
4227 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4228 return gen_binary (PLUS
, mode
,
4229 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4231 XEXP (XEXP (x
, 0), 1));
4233 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4234 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4235 bit-field and can be replaced by either a sign_extend or a
4236 sign_extract. The `and' may be a zero_extend and the two
4237 <c>, -<c> constants may be reversed. */
4238 if (GET_CODE (XEXP (x
, 0)) == XOR
4239 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4240 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4241 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4242 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4243 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4244 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4245 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4246 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4247 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4248 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4249 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4250 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4251 == (unsigned int) i
+ 1))))
4252 return simplify_shift_const
4253 (NULL_RTX
, ASHIFTRT
, mode
,
4254 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4255 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4256 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4257 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4259 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4260 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4261 is 1. This produces better code than the alternative immediately
4263 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4264 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4265 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4266 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4267 XEXP (XEXP (x
, 0), 0),
4268 XEXP (XEXP (x
, 0), 1))))
4270 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4272 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4273 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4274 the bitsize of the mode - 1. This allows simplification of
4275 "a = (b & 8) == 0;" */
4276 if (XEXP (x
, 1) == constm1_rtx
4277 && GET_CODE (XEXP (x
, 0)) != REG
4278 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4279 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4280 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4281 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4282 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4283 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4284 GET_MODE_BITSIZE (mode
) - 1),
4285 GET_MODE_BITSIZE (mode
) - 1);
4287 /* If we are adding two things that have no bits in common, convert
4288 the addition into an IOR. This will often be further simplified,
4289 for example in cases like ((a & 1) + (a & 2)), which can
4292 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4293 && (nonzero_bits (XEXP (x
, 0), mode
)
4294 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4296 /* Try to simplify the expression further. */
4297 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4298 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4300 /* If we could, great. If not, do not go ahead with the IOR
4301 replacement, since PLUS appears in many special purpose
4302 address arithmetic instructions. */
4303 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4309 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4310 by reversing the comparison code if valid. */
4311 if (STORE_FLAG_VALUE
== 1
4312 && XEXP (x
, 0) == const1_rtx
4313 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4314 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4315 XEXP (XEXP (x
, 1), 0),
4316 XEXP (XEXP (x
, 1), 1))))
4319 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4320 (and <foo> (const_int pow2-1)) */
4321 if (GET_CODE (XEXP (x
, 1)) == AND
4322 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4323 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4324 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4325 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4326 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4328 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4330 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4331 return gen_binary (MINUS
, mode
,
4332 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4333 XEXP (XEXP (x
, 1), 0)),
4334 XEXP (XEXP (x
, 1), 1));
4338 /* If we have (mult (plus A B) C), apply the distributive law and then
4339 the inverse distributive law to see if things simplify. This
4340 occurs mostly in addresses, often when unrolling loops. */
4342 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4344 x
= apply_distributive_law
4345 (gen_binary (PLUS
, mode
,
4346 gen_binary (MULT
, mode
,
4347 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4348 gen_binary (MULT
, mode
,
4349 XEXP (XEXP (x
, 0), 1),
4350 copy_rtx (XEXP (x
, 1)))));
4352 if (GET_CODE (x
) != MULT
)
4355 /* Try simplify a*(b/c) as (a*b)/c. */
4356 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4357 && GET_CODE (XEXP (x
, 0)) == DIV
)
4359 rtx tem
= simplify_binary_operation (MULT
, mode
,
4360 XEXP (XEXP (x
, 0), 0),
4363 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4368 /* If this is a divide by a power of two, treat it as a shift if
4369 its first operand is a shift. */
4370 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4371 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4372 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4373 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4374 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4375 || GET_CODE (XEXP (x
, 0)) == ROTATE
4376 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4377 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4381 case GT
: case GTU
: case GE
: case GEU
:
4382 case LT
: case LTU
: case LE
: case LEU
:
4383 case UNEQ
: case LTGT
:
4384 case UNGT
: case UNGE
:
4385 case UNLT
: case UNLE
:
4386 case UNORDERED
: case ORDERED
:
4387 /* If the first operand is a condition code, we can't do anything
4389 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4390 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4392 && XEXP (x
, 0) != cc0_rtx
4396 rtx op0
= XEXP (x
, 0);
4397 rtx op1
= XEXP (x
, 1);
4398 enum rtx_code new_code
;
4400 if (GET_CODE (op0
) == COMPARE
)
4401 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4403 /* Simplify our comparison, if possible. */
4404 new_code
= simplify_comparison (code
, &op0
, &op1
);
4406 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4407 if only the low-order bit is possibly nonzero in X (such as when
4408 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4409 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4410 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4413 Remove any ZERO_EXTRACT we made when thinking this was a
4414 comparison. It may now be simpler to use, e.g., an AND. If a
4415 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4416 the call to make_compound_operation in the SET case. */
4418 if (STORE_FLAG_VALUE
== 1
4419 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4420 && op1
== const0_rtx
4421 && mode
== GET_MODE (op0
)
4422 && nonzero_bits (op0
, mode
) == 1)
4423 return gen_lowpart_for_combine (mode
,
4424 expand_compound_operation (op0
));
4426 else if (STORE_FLAG_VALUE
== 1
4427 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4428 && op1
== const0_rtx
4429 && mode
== GET_MODE (op0
)
4430 && (num_sign_bit_copies (op0
, mode
)
4431 == GET_MODE_BITSIZE (mode
)))
4433 op0
= expand_compound_operation (op0
);
4434 return simplify_gen_unary (NEG
, mode
,
4435 gen_lowpart_for_combine (mode
, op0
),
4439 else if (STORE_FLAG_VALUE
== 1
4440 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4441 && op1
== const0_rtx
4442 && mode
== GET_MODE (op0
)
4443 && nonzero_bits (op0
, mode
) == 1)
4445 op0
= expand_compound_operation (op0
);
4446 return gen_binary (XOR
, mode
,
4447 gen_lowpart_for_combine (mode
, op0
),
4451 else if (STORE_FLAG_VALUE
== 1
4452 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4453 && op1
== const0_rtx
4454 && mode
== GET_MODE (op0
)
4455 && (num_sign_bit_copies (op0
, mode
)
4456 == GET_MODE_BITSIZE (mode
)))
4458 op0
= expand_compound_operation (op0
);
4459 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4462 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4464 if (STORE_FLAG_VALUE
== -1
4465 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4466 && op1
== const0_rtx
4467 && (num_sign_bit_copies (op0
, mode
)
4468 == GET_MODE_BITSIZE (mode
)))
4469 return gen_lowpart_for_combine (mode
,
4470 expand_compound_operation (op0
));
4472 else if (STORE_FLAG_VALUE
== -1
4473 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4474 && op1
== const0_rtx
4475 && mode
== GET_MODE (op0
)
4476 && nonzero_bits (op0
, mode
) == 1)
4478 op0
= expand_compound_operation (op0
);
4479 return simplify_gen_unary (NEG
, mode
,
4480 gen_lowpart_for_combine (mode
, op0
),
4484 else if (STORE_FLAG_VALUE
== -1
4485 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4486 && op1
== const0_rtx
4487 && mode
== GET_MODE (op0
)
4488 && (num_sign_bit_copies (op0
, mode
)
4489 == GET_MODE_BITSIZE (mode
)))
4491 op0
= expand_compound_operation (op0
);
4492 return simplify_gen_unary (NOT
, mode
,
4493 gen_lowpart_for_combine (mode
, op0
),
4497 /* If X is 0/1, (eq X 0) is X-1. */
4498 else if (STORE_FLAG_VALUE
== -1
4499 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4500 && op1
== const0_rtx
4501 && mode
== GET_MODE (op0
)
4502 && nonzero_bits (op0
, mode
) == 1)
4504 op0
= expand_compound_operation (op0
);
4505 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4508 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4509 one bit that might be nonzero, we can convert (ne x 0) to
4510 (ashift x c) where C puts the bit in the sign bit. Remove any
4511 AND with STORE_FLAG_VALUE when we are done, since we are only
4512 going to test the sign bit. */
4513 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4514 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4515 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4516 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4517 && op1
== const0_rtx
4518 && mode
== GET_MODE (op0
)
4519 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4521 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4522 expand_compound_operation (op0
),
4523 GET_MODE_BITSIZE (mode
) - 1 - i
);
4524 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4530 /* If the code changed, return a whole new comparison. */
4531 if (new_code
!= code
)
4532 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4534 /* Otherwise, keep this operation, but maybe change its operands.
4535 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4536 SUBST (XEXP (x
, 0), op0
);
4537 SUBST (XEXP (x
, 1), op1
);
4542 return simplify_if_then_else (x
);
4548 /* If we are processing SET_DEST, we are done. */
4552 return expand_compound_operation (x
);
4555 return simplify_set (x
);
4560 return simplify_logical (x
, last
);
4563 /* (abs (neg <foo>)) -> (abs <foo>) */
4564 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4565 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4567 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4569 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4572 /* If operand is something known to be positive, ignore the ABS. */
4573 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4574 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4575 <= HOST_BITS_PER_WIDE_INT
)
4576 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4577 & ((HOST_WIDE_INT
) 1
4578 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4582 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4583 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4584 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4589 /* (ffs (*_extend <X>)) = (ffs <X>) */
4590 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4591 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4592 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4596 /* (float (sign_extend <X>)) = (float <X>). */
4597 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4598 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4606 /* If this is a shift by a constant amount, simplify it. */
4607 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4608 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4609 INTVAL (XEXP (x
, 1)));
4611 #ifdef SHIFT_COUNT_TRUNCATED
4612 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4614 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4616 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4625 rtx op0
= XEXP (x
, 0);
4626 rtx op1
= XEXP (x
, 1);
4629 if (GET_CODE (op1
) != PARALLEL
)
4631 len
= XVECLEN (op1
, 0);
4633 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4634 && GET_CODE (op0
) == VEC_CONCAT
)
4636 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4638 /* Try to find the element in the VEC_CONCAT. */
4641 if (GET_MODE (op0
) == GET_MODE (x
))
4643 if (GET_CODE (op0
) == VEC_CONCAT
)
4645 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4646 if (op0_size
< offset
)
4647 op0
= XEXP (op0
, 0);
4651 op0
= XEXP (op0
, 1);
4669 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4672 simplify_if_then_else (x
)
4675 enum machine_mode mode
= GET_MODE (x
);
4676 rtx cond
= XEXP (x
, 0);
4677 rtx true_rtx
= XEXP (x
, 1);
4678 rtx false_rtx
= XEXP (x
, 2);
4679 enum rtx_code true_code
= GET_CODE (cond
);
4680 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4683 enum rtx_code false_code
;
4686 /* Simplify storing of the truth value. */
4687 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4688 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4690 /* Also when the truth value has to be reversed. */
4692 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4693 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4697 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4698 in it is being compared against certain values. Get the true and false
4699 comparisons and see if that says anything about the value of each arm. */
4702 && ((false_code
= combine_reversed_comparison_code (cond
))
4704 && GET_CODE (XEXP (cond
, 0)) == REG
)
4707 rtx from
= XEXP (cond
, 0);
4708 rtx true_val
= XEXP (cond
, 1);
4709 rtx false_val
= true_val
;
4712 /* If FALSE_CODE is EQ, swap the codes and arms. */
4714 if (false_code
== EQ
)
4716 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4717 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4720 /* If we are comparing against zero and the expression being tested has
4721 only a single bit that might be nonzero, that is its value when it is
4722 not equal to zero. Similarly if it is known to be -1 or 0. */
4724 if (true_code
== EQ
&& true_val
== const0_rtx
4725 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4726 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4727 else if (true_code
== EQ
&& true_val
== const0_rtx
4728 && (num_sign_bit_copies (from
, GET_MODE (from
))
4729 == GET_MODE_BITSIZE (GET_MODE (from
))))
4730 false_code
= EQ
, false_val
= constm1_rtx
;
4732 /* Now simplify an arm if we know the value of the register in the
4733 branch and it is used in the arm. Be careful due to the potential
4734 of locally-shared RTL. */
4736 if (reg_mentioned_p (from
, true_rtx
))
4737 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4739 pc_rtx
, pc_rtx
, 0, 0);
4740 if (reg_mentioned_p (from
, false_rtx
))
4741 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4743 pc_rtx
, pc_rtx
, 0, 0);
4745 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4746 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4748 true_rtx
= XEXP (x
, 1);
4749 false_rtx
= XEXP (x
, 2);
4750 true_code
= GET_CODE (cond
);
4753 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4754 reversed, do so to avoid needing two sets of patterns for
4755 subtract-and-branch insns. Similarly if we have a constant in the true
4756 arm, the false arm is the same as the first operand of the comparison, or
4757 the false arm is more complicated than the true arm. */
4760 && combine_reversed_comparison_code (cond
) != UNKNOWN
4761 && (true_rtx
== pc_rtx
4762 || (CONSTANT_P (true_rtx
)
4763 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4764 || true_rtx
== const0_rtx
4765 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4766 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4767 || (GET_CODE (true_rtx
) == SUBREG
4768 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4769 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4770 || reg_mentioned_p (true_rtx
, false_rtx
)
4771 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4773 true_code
= reversed_comparison_code (cond
, NULL
);
4775 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4778 SUBST (XEXP (x
, 1), false_rtx
);
4779 SUBST (XEXP (x
, 2), true_rtx
);
4781 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4784 /* It is possible that the conditional has been simplified out. */
4785 true_code
= GET_CODE (cond
);
4786 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4789 /* If the two arms are identical, we don't need the comparison. */
4791 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4794 /* Convert a == b ? b : a to "a". */
4795 if (true_code
== EQ
&& ! side_effects_p (cond
)
4796 && !HONOR_NANS (mode
)
4797 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4798 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4800 else if (true_code
== NE
&& ! side_effects_p (cond
)
4801 && !HONOR_NANS (mode
)
4802 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4803 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4806 /* Look for cases where we have (abs x) or (neg (abs X)). */
4808 if (GET_MODE_CLASS (mode
) == MODE_INT
4809 && GET_CODE (false_rtx
) == NEG
4810 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4812 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4813 && ! side_effects_p (true_rtx
))
4818 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4822 simplify_gen_unary (NEG
, mode
,
4823 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4829 /* Look for MIN or MAX. */
4831 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4833 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4834 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4835 && ! side_effects_p (cond
))
4840 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4843 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4846 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4849 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4854 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4855 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4856 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4857 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4858 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4859 neither 1 or -1, but it isn't worth checking for. */
4861 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4862 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4864 rtx t
= make_compound_operation (true_rtx
, SET
);
4865 rtx f
= make_compound_operation (false_rtx
, SET
);
4866 rtx cond_op0
= XEXP (cond
, 0);
4867 rtx cond_op1
= XEXP (cond
, 1);
4868 enum rtx_code op
= NIL
, extend_op
= NIL
;
4869 enum machine_mode m
= mode
;
4870 rtx z
= 0, c1
= NULL_RTX
;
4872 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4873 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4874 || GET_CODE (t
) == ASHIFT
4875 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4876 && rtx_equal_p (XEXP (t
, 0), f
))
4877 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4879 /* If an identity-zero op is commutative, check whether there
4880 would be a match if we swapped the operands. */
4881 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4882 || GET_CODE (t
) == XOR
)
4883 && rtx_equal_p (XEXP (t
, 1), f
))
4884 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4885 else if (GET_CODE (t
) == SIGN_EXTEND
4886 && (GET_CODE (XEXP (t
, 0)) == PLUS
4887 || GET_CODE (XEXP (t
, 0)) == MINUS
4888 || GET_CODE (XEXP (t
, 0)) == IOR
4889 || GET_CODE (XEXP (t
, 0)) == XOR
4890 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4891 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4892 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4893 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4894 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4895 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4896 && (num_sign_bit_copies (f
, GET_MODE (f
))
4898 (GET_MODE_BITSIZE (mode
)
4899 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4901 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4902 extend_op
= SIGN_EXTEND
;
4903 m
= GET_MODE (XEXP (t
, 0));
4905 else if (GET_CODE (t
) == SIGN_EXTEND
4906 && (GET_CODE (XEXP (t
, 0)) == PLUS
4907 || GET_CODE (XEXP (t
, 0)) == IOR
4908 || GET_CODE (XEXP (t
, 0)) == XOR
)
4909 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4910 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4911 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4912 && (num_sign_bit_copies (f
, GET_MODE (f
))
4914 (GET_MODE_BITSIZE (mode
)
4915 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4917 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4918 extend_op
= SIGN_EXTEND
;
4919 m
= GET_MODE (XEXP (t
, 0));
4921 else if (GET_CODE (t
) == ZERO_EXTEND
4922 && (GET_CODE (XEXP (t
, 0)) == PLUS
4923 || GET_CODE (XEXP (t
, 0)) == MINUS
4924 || GET_CODE (XEXP (t
, 0)) == IOR
4925 || GET_CODE (XEXP (t
, 0)) == XOR
4926 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4927 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4928 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4929 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4930 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4931 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4932 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4933 && ((nonzero_bits (f
, GET_MODE (f
))
4934 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4937 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4938 extend_op
= ZERO_EXTEND
;
4939 m
= GET_MODE (XEXP (t
, 0));
4941 else if (GET_CODE (t
) == ZERO_EXTEND
4942 && (GET_CODE (XEXP (t
, 0)) == PLUS
4943 || GET_CODE (XEXP (t
, 0)) == IOR
4944 || GET_CODE (XEXP (t
, 0)) == XOR
)
4945 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4946 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4947 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4948 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4949 && ((nonzero_bits (f
, GET_MODE (f
))
4950 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4953 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4954 extend_op
= ZERO_EXTEND
;
4955 m
= GET_MODE (XEXP (t
, 0));
4960 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4961 pc_rtx
, pc_rtx
, 0, 0);
4962 temp
= gen_binary (MULT
, m
, temp
,
4963 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4964 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4965 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4967 if (extend_op
!= NIL
)
4968 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4974 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4975 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4976 negation of a single bit, we can convert this operation to a shift. We
4977 can actually do this more generally, but it doesn't seem worth it. */
4979 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4980 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4981 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4982 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4983 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4984 == GET_MODE_BITSIZE (mode
))
4985 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4987 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4988 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4993 /* Simplify X, a SET expression. Return the new expression. */
4999 rtx src
= SET_SRC (x
);
5000 rtx dest
= SET_DEST (x
);
5001 enum machine_mode mode
5002 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5006 /* (set (pc) (return)) gets written as (return). */
5007 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5010 /* Now that we know for sure which bits of SRC we are using, see if we can
5011 simplify the expression for the object knowing that we only need the
5014 if (GET_MODE_CLASS (mode
) == MODE_INT
5015 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5017 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5018 SUBST (SET_SRC (x
), src
);
5021 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5022 the comparison result and try to simplify it unless we already have used
5023 undobuf.other_insn. */
5024 if ((GET_MODE_CLASS (mode
) == MODE_CC
5025 || GET_CODE (src
) == COMPARE
5027 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5028 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5029 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
5030 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5032 enum rtx_code old_code
= GET_CODE (*cc_use
);
5033 enum rtx_code new_code
;
5035 int other_changed
= 0;
5036 enum machine_mode compare_mode
= GET_MODE (dest
);
5037 enum machine_mode tmp_mode
;
5039 if (GET_CODE (src
) == COMPARE
)
5040 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5042 op0
= src
, op1
= const0_rtx
;
5044 /* Check whether the comparison is known at compile time. */
5045 if (GET_MODE (op0
) != VOIDmode
)
5046 tmp_mode
= GET_MODE (op0
);
5047 else if (GET_MODE (op1
) != VOIDmode
)
5048 tmp_mode
= GET_MODE (op1
);
5050 tmp_mode
= compare_mode
;
5051 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5052 if (tmp
!= NULL_RTX
)
5054 rtx pat
= PATTERN (other_insn
);
5055 undobuf
.other_insn
= other_insn
;
5056 SUBST (*cc_use
, tmp
);
5058 /* Attempt to simplify CC user. */
5059 if (GET_CODE (pat
) == SET
)
5061 rtx
new = simplify_rtx (SET_SRC (pat
));
5062 if (new != NULL_RTX
)
5063 SUBST (SET_SRC (pat
), new);
5066 /* Convert X into a no-op move. */
5067 SUBST (SET_DEST (x
), pc_rtx
);
5068 SUBST (SET_SRC (x
), pc_rtx
);
5072 /* Simplify our comparison, if possible. */
5073 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5075 #ifdef EXTRA_CC_MODES
5076 /* If this machine has CC modes other than CCmode, check to see if we
5077 need to use a different CC mode here. */
5078 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5079 #endif /* EXTRA_CC_MODES */
5081 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5082 /* If the mode changed, we have to change SET_DEST, the mode in the
5083 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5084 a hard register, just build new versions with the proper mode. If it
5085 is a pseudo, we lose unless it is only time we set the pseudo, in
5086 which case we can safely change its mode. */
5087 if (compare_mode
!= GET_MODE (dest
))
5089 unsigned int regno
= REGNO (dest
);
5090 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5092 if (regno
< FIRST_PSEUDO_REGISTER
5093 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5095 if (regno
>= FIRST_PSEUDO_REGISTER
)
5096 SUBST (regno_reg_rtx
[regno
], new_dest
);
5098 SUBST (SET_DEST (x
), new_dest
);
5099 SUBST (XEXP (*cc_use
, 0), new_dest
);
5107 /* If the code changed, we have to build a new comparison in
5108 undobuf.other_insn. */
5109 if (new_code
!= old_code
)
5111 unsigned HOST_WIDE_INT mask
;
5113 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5116 /* If the only change we made was to change an EQ into an NE or
5117 vice versa, OP0 has only one bit that might be nonzero, and OP1
5118 is zero, check if changing the user of the condition code will
5119 produce a valid insn. If it won't, we can keep the original code
5120 in that insn by surrounding our operation with an XOR. */
5122 if (((old_code
== NE
&& new_code
== EQ
)
5123 || (old_code
== EQ
&& new_code
== NE
))
5124 && ! other_changed
&& op1
== const0_rtx
5125 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5126 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5128 rtx pat
= PATTERN (other_insn
), note
= 0;
5130 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5131 && ! check_asm_operands (pat
)))
5133 PUT_CODE (*cc_use
, old_code
);
5136 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5144 undobuf
.other_insn
= other_insn
;
5147 /* If we are now comparing against zero, change our source if
5148 needed. If we do not use cc0, we always have a COMPARE. */
5149 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5151 SUBST (SET_SRC (x
), op0
);
5157 /* Otherwise, if we didn't previously have a COMPARE in the
5158 correct mode, we need one. */
5159 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5161 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5166 /* Otherwise, update the COMPARE if needed. */
5167 SUBST (XEXP (src
, 0), op0
);
5168 SUBST (XEXP (src
, 1), op1
);
5173 /* Get SET_SRC in a form where we have placed back any
5174 compound expressions. Then do the checks below. */
5175 src
= make_compound_operation (src
, SET
);
5176 SUBST (SET_SRC (x
), src
);
5179 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5180 and X being a REG or (subreg (reg)), we may be able to convert this to
5181 (set (subreg:m2 x) (op)).
5183 We can always do this if M1 is narrower than M2 because that means that
5184 we only care about the low bits of the result.
5186 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5187 perform a narrower operation than requested since the high-order bits will
5188 be undefined. On machine where it is defined, this transformation is safe
5189 as long as M1 and M2 have the same number of words. */
5191 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5192 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5193 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5195 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5196 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5197 #ifndef WORD_REGISTER_OPERATIONS
5198 && (GET_MODE_SIZE (GET_MODE (src
))
5199 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5201 #ifdef CLASS_CANNOT_CHANGE_MODE
5202 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5203 && (TEST_HARD_REG_BIT
5204 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5206 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5207 GET_MODE (SUBREG_REG (src
))))
5209 && (GET_CODE (dest
) == REG
5210 || (GET_CODE (dest
) == SUBREG
5211 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5213 SUBST (SET_DEST (x
),
5214 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5216 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5218 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5222 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5225 && GET_CODE (src
) == SUBREG
5226 && subreg_lowpart_p (src
)
5227 && (GET_MODE_BITSIZE (GET_MODE (src
))
5228 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5230 rtx inner
= SUBREG_REG (src
);
5231 enum machine_mode inner_mode
= GET_MODE (inner
);
5233 /* Here we make sure that we don't have a sign bit on. */
5234 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5235 && (nonzero_bits (inner
, inner_mode
)
5236 < ((unsigned HOST_WIDE_INT
) 1
5237 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5239 SUBST (SET_SRC (x
), inner
);
5245 #ifdef LOAD_EXTEND_OP
5246 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5247 would require a paradoxical subreg. Replace the subreg with a
5248 zero_extend to avoid the reload that would otherwise be required. */
5250 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5251 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5252 && SUBREG_BYTE (src
) == 0
5253 && (GET_MODE_SIZE (GET_MODE (src
))
5254 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5255 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5258 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5259 GET_MODE (src
), SUBREG_REG (src
)));
5265 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5266 are comparing an item known to be 0 or -1 against 0, use a logical
5267 operation instead. Check for one of the arms being an IOR of the other
5268 arm with some value. We compute three terms to be IOR'ed together. In
5269 practice, at most two will be nonzero. Then we do the IOR's. */
5271 if (GET_CODE (dest
) != PC
5272 && GET_CODE (src
) == IF_THEN_ELSE
5273 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5274 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5275 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5276 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5277 #ifdef HAVE_conditional_move
5278 && ! can_conditionally_move_p (GET_MODE (src
))
5280 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5281 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5282 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5283 && ! side_effects_p (src
))
5285 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5286 ? XEXP (src
, 1) : XEXP (src
, 2));
5287 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5288 ? XEXP (src
, 2) : XEXP (src
, 1));
5289 rtx term1
= const0_rtx
, term2
, term3
;
5291 if (GET_CODE (true_rtx
) == IOR
5292 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5293 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5294 else if (GET_CODE (true_rtx
) == IOR
5295 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5296 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5297 else if (GET_CODE (false_rtx
) == IOR
5298 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5299 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5300 else if (GET_CODE (false_rtx
) == IOR
5301 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5302 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5304 term2
= gen_binary (AND
, GET_MODE (src
),
5305 XEXP (XEXP (src
, 0), 0), true_rtx
);
5306 term3
= gen_binary (AND
, GET_MODE (src
),
5307 simplify_gen_unary (NOT
, GET_MODE (src
),
5308 XEXP (XEXP (src
, 0), 0),
5313 gen_binary (IOR
, GET_MODE (src
),
5314 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5320 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5321 whole thing fail. */
5322 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5324 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5327 /* Convert this into a field assignment operation, if possible. */
5328 return make_field_assignment (x
);
5331 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5332 result. LAST is nonzero if this is the last retry. */
5335 simplify_logical (x
, last
)
5339 enum machine_mode mode
= GET_MODE (x
);
5340 rtx op0
= XEXP (x
, 0);
5341 rtx op1
= XEXP (x
, 1);
5344 switch (GET_CODE (x
))
5347 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5348 insn (and may simplify more). */
5349 if (GET_CODE (op0
) == XOR
5350 && rtx_equal_p (XEXP (op0
, 0), op1
)
5351 && ! side_effects_p (op1
))
5352 x
= gen_binary (AND
, mode
,
5353 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5356 if (GET_CODE (op0
) == XOR
5357 && rtx_equal_p (XEXP (op0
, 1), op1
)
5358 && ! side_effects_p (op1
))
5359 x
= gen_binary (AND
, mode
,
5360 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5363 /* Similarly for (~(A ^ B)) & A. */
5364 if (GET_CODE (op0
) == NOT
5365 && GET_CODE (XEXP (op0
, 0)) == XOR
5366 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5367 && ! side_effects_p (op1
))
5368 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5370 if (GET_CODE (op0
) == NOT
5371 && GET_CODE (XEXP (op0
, 0)) == XOR
5372 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5373 && ! side_effects_p (op1
))
5374 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5376 /* We can call simplify_and_const_int only if we don't lose
5377 any (sign) bits when converting INTVAL (op1) to
5378 "unsigned HOST_WIDE_INT". */
5379 if (GET_CODE (op1
) == CONST_INT
5380 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5381 || INTVAL (op1
) > 0))
5383 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5385 /* If we have (ior (and (X C1) C2)) and the next restart would be
5386 the last, simplify this by making C1 as small as possible
5389 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5390 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5391 && GET_CODE (op1
) == CONST_INT
)
5392 return gen_binary (IOR
, mode
,
5393 gen_binary (AND
, mode
, XEXP (op0
, 0),
5394 GEN_INT (INTVAL (XEXP (op0
, 1))
5395 & ~INTVAL (op1
))), op1
);
5397 if (GET_CODE (x
) != AND
)
5400 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5401 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5402 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5405 /* Convert (A | B) & A to A. */
5406 if (GET_CODE (op0
) == IOR
5407 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5408 || rtx_equal_p (XEXP (op0
, 1), op1
))
5409 && ! side_effects_p (XEXP (op0
, 0))
5410 && ! side_effects_p (XEXP (op0
, 1)))
5413 /* In the following group of tests (and those in case IOR below),
5414 we start with some combination of logical operations and apply
5415 the distributive law followed by the inverse distributive law.
5416 Most of the time, this results in no change. However, if some of
5417 the operands are the same or inverses of each other, simplifications
5420 For example, (and (ior A B) (not B)) can occur as the result of
5421 expanding a bit field assignment. When we apply the distributive
5422 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5423 which then simplifies to (and (A (not B))).
5425 If we have (and (ior A B) C), apply the distributive law and then
5426 the inverse distributive law to see if things simplify. */
5428 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5430 x
= apply_distributive_law
5431 (gen_binary (GET_CODE (op0
), mode
,
5432 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5433 gen_binary (AND
, mode
, XEXP (op0
, 1),
5435 if (GET_CODE (x
) != AND
)
5439 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5440 return apply_distributive_law
5441 (gen_binary (GET_CODE (op1
), mode
,
5442 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5443 gen_binary (AND
, mode
, XEXP (op1
, 1),
5446 /* Similarly, taking advantage of the fact that
5447 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5449 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5450 return apply_distributive_law
5451 (gen_binary (XOR
, mode
,
5452 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5453 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5456 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5457 return apply_distributive_law
5458 (gen_binary (XOR
, mode
,
5459 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5460 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5464 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5465 if (GET_CODE (op1
) == CONST_INT
5466 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5467 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5470 /* Convert (A & B) | A to A. */
5471 if (GET_CODE (op0
) == AND
5472 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5473 || rtx_equal_p (XEXP (op0
, 1), op1
))
5474 && ! side_effects_p (XEXP (op0
, 0))
5475 && ! side_effects_p (XEXP (op0
, 1)))
5478 /* If we have (ior (and A B) C), apply the distributive law and then
5479 the inverse distributive law to see if things simplify. */
5481 if (GET_CODE (op0
) == AND
)
5483 x
= apply_distributive_law
5484 (gen_binary (AND
, mode
,
5485 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5486 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5489 if (GET_CODE (x
) != IOR
)
5493 if (GET_CODE (op1
) == AND
)
5495 x
= apply_distributive_law
5496 (gen_binary (AND
, mode
,
5497 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5498 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5501 if (GET_CODE (x
) != IOR
)
5505 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5506 mode size to (rotate A CX). */
5508 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5509 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5510 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5511 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5512 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5513 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5514 == GET_MODE_BITSIZE (mode
)))
5515 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5516 (GET_CODE (op0
) == ASHIFT
5517 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5519 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5520 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5521 does not affect any of the bits in OP1, it can really be done
5522 as a PLUS and we can associate. We do this by seeing if OP1
5523 can be safely shifted left C bits. */
5524 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5525 && GET_CODE (XEXP (op0
, 0)) == PLUS
5526 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5527 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5528 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5530 int count
= INTVAL (XEXP (op0
, 1));
5531 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5533 if (mask
>> count
== INTVAL (op1
)
5534 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5536 SUBST (XEXP (XEXP (op0
, 0), 1),
5537 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5544 /* If we are XORing two things that have no bits in common,
5545 convert them into an IOR. This helps to detect rotation encoded
5546 using those methods and possibly other simplifications. */
5548 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5549 && (nonzero_bits (op0
, mode
)
5550 & nonzero_bits (op1
, mode
)) == 0)
5551 return (gen_binary (IOR
, mode
, op0
, op1
));
5553 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5554 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5557 int num_negated
= 0;
5559 if (GET_CODE (op0
) == NOT
)
5560 num_negated
++, op0
= XEXP (op0
, 0);
5561 if (GET_CODE (op1
) == NOT
)
5562 num_negated
++, op1
= XEXP (op1
, 0);
5564 if (num_negated
== 2)
5566 SUBST (XEXP (x
, 0), op0
);
5567 SUBST (XEXP (x
, 1), op1
);
5569 else if (num_negated
== 1)
5571 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5575 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5576 correspond to a machine insn or result in further simplifications
5577 if B is a constant. */
5579 if (GET_CODE (op0
) == AND
5580 && rtx_equal_p (XEXP (op0
, 1), op1
)
5581 && ! side_effects_p (op1
))
5582 return gen_binary (AND
, mode
,
5583 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5586 else if (GET_CODE (op0
) == AND
5587 && rtx_equal_p (XEXP (op0
, 0), op1
)
5588 && ! side_effects_p (op1
))
5589 return gen_binary (AND
, mode
,
5590 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5593 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5594 comparison if STORE_FLAG_VALUE is 1. */
5595 if (STORE_FLAG_VALUE
== 1
5596 && op1
== const1_rtx
5597 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5598 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5602 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5603 is (lt foo (const_int 0)), so we can perform the above
5604 simplification if STORE_FLAG_VALUE is 1. */
5606 if (STORE_FLAG_VALUE
== 1
5607 && op1
== const1_rtx
5608 && GET_CODE (op0
) == LSHIFTRT
5609 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5610 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5611 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5613 /* (xor (comparison foo bar) (const_int sign-bit))
5614 when STORE_FLAG_VALUE is the sign bit. */
5615 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5616 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5617 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5618 && op1
== const_true_rtx
5619 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5620 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5633 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5634 operations" because they can be replaced with two more basic operations.
5635 ZERO_EXTEND is also considered "compound" because it can be replaced with
5636 an AND operation, which is simpler, though only one operation.
5638 The function expand_compound_operation is called with an rtx expression
5639 and will convert it to the appropriate shifts and AND operations,
5640 simplifying at each stage.
5642 The function make_compound_operation is called to convert an expression
5643 consisting of shifts and ANDs into the equivalent compound expression.
5644 It is the inverse of this function, loosely speaking. */
5647 expand_compound_operation (x
)
5650 unsigned HOST_WIDE_INT pos
= 0, len
;
5652 unsigned int modewidth
;
5655 switch (GET_CODE (x
))
5660 /* We can't necessarily use a const_int for a multiword mode;
5661 it depends on implicitly extending the value.
5662 Since we don't know the right way to extend it,
5663 we can't tell whether the implicit way is right.
5665 Even for a mode that is no wider than a const_int,
5666 we can't win, because we need to sign extend one of its bits through
5667 the rest of it, and we don't know which bit. */
5668 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5671 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5672 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5673 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5674 reloaded. If not for that, MEM's would very rarely be safe.
5676 Reject MODEs bigger than a word, because we might not be able
5677 to reference a two-register group starting with an arbitrary register
5678 (and currently gen_lowpart might crash for a SUBREG). */
5680 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5683 /* Reject MODEs that aren't scalar integers because turning vector
5684 or complex modes into shifts causes problems. */
5686 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5689 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5690 /* If the inner object has VOIDmode (the only way this can happen
5691 is if it is an ASM_OPERANDS), we can't do anything since we don't
5692 know how much masking to do. */
5701 /* If the operand is a CLOBBER, just return it. */
5702 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5705 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5706 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5707 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5710 /* Reject MODEs that aren't scalar integers because turning vector
5711 or complex modes into shifts causes problems. */
5713 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5716 len
= INTVAL (XEXP (x
, 1));
5717 pos
= INTVAL (XEXP (x
, 2));
5719 /* If this goes outside the object being extracted, replace the object
5720 with a (use (mem ...)) construct that only combine understands
5721 and is used only for this purpose. */
5722 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5723 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5725 if (BITS_BIG_ENDIAN
)
5726 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5733 /* Convert sign extension to zero extension, if we know that the high
5734 bit is not set, as this is easier to optimize. It will be converted
5735 back to cheaper alternative in make_extraction. */
5736 if (GET_CODE (x
) == SIGN_EXTEND
5737 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5738 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5739 & ~(((unsigned HOST_WIDE_INT
)
5740 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5744 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5745 return expand_compound_operation (temp
);
5748 /* We can optimize some special cases of ZERO_EXTEND. */
5749 if (GET_CODE (x
) == ZERO_EXTEND
)
5751 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5752 know that the last value didn't have any inappropriate bits
5754 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5755 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5756 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5757 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5758 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5759 return XEXP (XEXP (x
, 0), 0);
5761 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5762 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5763 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5764 && subreg_lowpart_p (XEXP (x
, 0))
5765 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5766 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5767 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5768 return SUBREG_REG (XEXP (x
, 0));
5770 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5771 is a comparison and STORE_FLAG_VALUE permits. This is like
5772 the first case, but it works even when GET_MODE (x) is larger
5773 than HOST_WIDE_INT. */
5774 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5775 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5776 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5777 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5778 <= HOST_BITS_PER_WIDE_INT
)
5779 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5780 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5781 return XEXP (XEXP (x
, 0), 0);
5783 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5784 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5785 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5786 && subreg_lowpart_p (XEXP (x
, 0))
5787 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5788 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5789 <= HOST_BITS_PER_WIDE_INT
)
5790 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5791 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5792 return SUBREG_REG (XEXP (x
, 0));
5796 /* If we reach here, we want to return a pair of shifts. The inner
5797 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5798 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5799 logical depending on the value of UNSIGNEDP.
5801 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5802 converted into an AND of a shift.
5804 We must check for the case where the left shift would have a negative
5805 count. This can happen in a case like (x >> 31) & 255 on machines
5806 that can't shift by a constant. On those machines, we would first
5807 combine the shift with the AND to produce a variable-position
5808 extraction. Then the constant of 31 would be substituted in to produce
5809 a such a position. */
5811 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5812 if (modewidth
+ len
>= pos
)
5813 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5815 simplify_shift_const (NULL_RTX
, ASHIFT
,
5818 modewidth
- pos
- len
),
5821 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5822 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5823 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5826 ((HOST_WIDE_INT
) 1 << len
) - 1);
5828 /* Any other cases we can't handle. */
5831 /* If we couldn't do this for some reason, return the original
5833 if (GET_CODE (tem
) == CLOBBER
)
5839 /* X is a SET which contains an assignment of one object into
5840 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5841 or certain SUBREGS). If possible, convert it into a series of
5844 We half-heartedly support variable positions, but do not at all
5845 support variable lengths. */
5848 expand_field_assignment (x
)
5852 rtx pos
; /* Always counts from low bit. */
5855 enum machine_mode compute_mode
;
5857 /* Loop until we find something we can't simplify. */
5860 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5861 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5863 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5864 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5865 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5867 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5868 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5870 inner
= XEXP (SET_DEST (x
), 0);
5871 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5872 pos
= XEXP (SET_DEST (x
), 2);
5874 /* If the position is constant and spans the width of INNER,
5875 surround INNER with a USE to indicate this. */
5876 if (GET_CODE (pos
) == CONST_INT
5877 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5878 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5880 if (BITS_BIG_ENDIAN
)
5882 if (GET_CODE (pos
) == CONST_INT
)
5883 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5885 else if (GET_CODE (pos
) == MINUS
5886 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5887 && (INTVAL (XEXP (pos
, 1))
5888 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5889 /* If position is ADJUST - X, new position is X. */
5890 pos
= XEXP (pos
, 0);
5892 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5893 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5899 /* A SUBREG between two modes that occupy the same numbers of words
5900 can be done by moving the SUBREG to the source. */
5901 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5902 /* We need SUBREGs to compute nonzero_bits properly. */
5903 && nonzero_sign_valid
5904 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5905 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5906 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5907 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5909 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5910 gen_lowpart_for_combine
5911 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5918 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5919 inner
= SUBREG_REG (inner
);
5921 compute_mode
= GET_MODE (inner
);
5923 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5924 if (! SCALAR_INT_MODE_P (compute_mode
))
5926 enum machine_mode imode
;
5928 /* Don't do anything for vector or complex integral types. */
5929 if (! FLOAT_MODE_P (compute_mode
))
5932 /* Try to find an integral mode to pun with. */
5933 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5934 if (imode
== BLKmode
)
5937 compute_mode
= imode
;
5938 inner
= gen_lowpart_for_combine (imode
, inner
);
5941 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5942 if (len
< HOST_BITS_PER_WIDE_INT
)
5943 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5947 /* Now compute the equivalent expression. Make a copy of INNER
5948 for the SET_DEST in case it is a MEM into which we will substitute;
5949 we don't want shared RTL in that case. */
5951 (VOIDmode
, copy_rtx (inner
),
5952 gen_binary (IOR
, compute_mode
,
5953 gen_binary (AND
, compute_mode
,
5954 simplify_gen_unary (NOT
, compute_mode
,
5960 gen_binary (ASHIFT
, compute_mode
,
5961 gen_binary (AND
, compute_mode
,
5962 gen_lowpart_for_combine
5963 (compute_mode
, SET_SRC (x
)),
5971 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5972 it is an RTX that represents a variable starting position; otherwise,
5973 POS is the (constant) starting bit position (counted from the LSB).
5975 INNER may be a USE. This will occur when we started with a bitfield
5976 that went outside the boundary of the object in memory, which is
5977 allowed on most machines. To isolate this case, we produce a USE
5978 whose mode is wide enough and surround the MEM with it. The only
5979 code that understands the USE is this routine. If it is not removed,
5980 it will cause the resulting insn not to match.
5982 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5985 IN_DEST is nonzero if this is a reference in the destination of a
5986 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5987 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5990 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5991 ZERO_EXTRACT should be built even for bits starting at bit 0.
5993 MODE is the desired mode of the result (if IN_DEST == 0).
5995 The result is an RTX for the extraction or NULL_RTX if the target
5999 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
6000 unsignedp
, in_dest
, in_compare
)
6001 enum machine_mode mode
;
6005 unsigned HOST_WIDE_INT len
;
6007 int in_dest
, in_compare
;
6009 /* This mode describes the size of the storage area
6010 to fetch the overall value from. Within that, we
6011 ignore the POS lowest bits, etc. */
6012 enum machine_mode is_mode
= GET_MODE (inner
);
6013 enum machine_mode inner_mode
;
6014 enum machine_mode wanted_inner_mode
= byte_mode
;
6015 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6016 enum machine_mode pos_mode
= word_mode
;
6017 enum machine_mode extraction_mode
= word_mode
;
6018 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6021 rtx orig_pos_rtx
= pos_rtx
;
6022 HOST_WIDE_INT orig_pos
;
6024 /* Get some information about INNER and get the innermost object. */
6025 if (GET_CODE (inner
) == USE
)
6026 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6027 /* We don't need to adjust the position because we set up the USE
6028 to pretend that it was a full-word object. */
6029 spans_byte
= 1, inner
= XEXP (inner
, 0);
6030 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6032 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6033 consider just the QI as the memory to extract from.
6034 The subreg adds or removes high bits; its mode is
6035 irrelevant to the meaning of this extraction,
6036 since POS and LEN count from the lsb. */
6037 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
6038 is_mode
= GET_MODE (SUBREG_REG (inner
));
6039 inner
= SUBREG_REG (inner
);
6041 else if (GET_CODE (inner
) == ASHIFT
6042 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6043 && pos_rtx
== 0 && pos
== 0
6044 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6046 /* We're extracting the least significant bits of an rtx
6047 (ashift X (const_int C)), where LEN > C. Extract the
6048 least significant (LEN - C) bits of X, giving an rtx
6049 whose mode is MODE, then shift it left C times. */
6050 new = make_extraction (mode
, XEXP (inner
, 0),
6051 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6052 unsignedp
, in_dest
, in_compare
);
6054 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6057 inner_mode
= GET_MODE (inner
);
6059 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6060 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6062 /* See if this can be done without an extraction. We never can if the
6063 width of the field is not the same as that of some integer mode. For
6064 registers, we can only avoid the extraction if the position is at the
6065 low-order bit and this is either not in the destination or we have the
6066 appropriate STRICT_LOW_PART operation available.
6068 For MEM, we can avoid an extract if the field starts on an appropriate
6069 boundary and we can change the mode of the memory reference. However,
6070 we cannot directly access the MEM if we have a USE and the underlying
6071 MEM is not TMODE. This combination means that MEM was being used in a
6072 context where bits outside its mode were being referenced; that is only
6073 valid in bit-field insns. */
6075 if (tmode
!= BLKmode
6076 && ! (spans_byte
&& inner_mode
!= tmode
)
6077 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6078 && GET_CODE (inner
) != MEM
6080 || (GET_CODE (inner
) == REG
6081 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6082 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6084 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6085 : BITS_PER_UNIT
)) == 0
6086 /* We can't do this if we are widening INNER_MODE (it
6087 may not be aligned, for one thing). */
6088 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6089 && (inner_mode
== tmode
6090 || (! mode_dependent_address_p (XEXP (inner
, 0))
6091 && ! MEM_VOLATILE_P (inner
))))))
6093 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6094 field. If the original and current mode are the same, we need not
6095 adjust the offset. Otherwise, we do if bytes big endian.
6097 If INNER is not a MEM, get a piece consisting of just the field
6098 of interest (in this case POS % BITS_PER_WORD must be 0). */
6100 if (GET_CODE (inner
) == MEM
)
6102 HOST_WIDE_INT offset
;
6104 /* POS counts from lsb, but make OFFSET count in memory order. */
6105 if (BYTES_BIG_ENDIAN
)
6106 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6108 offset
= pos
/ BITS_PER_UNIT
;
6110 new = adjust_address_nv (inner
, tmode
, offset
);
6112 else if (GET_CODE (inner
) == REG
)
6114 /* We can't call gen_lowpart_for_combine here since we always want
6115 a SUBREG and it would sometimes return a new hard register. */
6116 if (tmode
!= inner_mode
)
6118 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6120 if (WORDS_BIG_ENDIAN
6121 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6122 final_word
= ((GET_MODE_SIZE (inner_mode
)
6123 - GET_MODE_SIZE (tmode
))
6124 / UNITS_PER_WORD
) - final_word
;
6126 final_word
*= UNITS_PER_WORD
;
6127 if (BYTES_BIG_ENDIAN
&&
6128 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6129 final_word
+= (GET_MODE_SIZE (inner_mode
)
6130 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6132 /* Avoid creating invalid subregs, for example when
6133 simplifying (x>>32)&255. */
6134 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6137 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6143 new = force_to_mode (inner
, tmode
,
6144 len
>= HOST_BITS_PER_WIDE_INT
6145 ? ~(unsigned HOST_WIDE_INT
) 0
6146 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6149 /* If this extraction is going into the destination of a SET,
6150 make a STRICT_LOW_PART unless we made a MEM. */
6153 return (GET_CODE (new) == MEM
? new
6154 : (GET_CODE (new) != SUBREG
6155 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6156 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6161 if (GET_CODE (new) == CONST_INT
)
6162 return gen_int_mode (INTVAL (new), mode
);
6164 /* If we know that no extraneous bits are set, and that the high
6165 bit is not set, convert the extraction to the cheaper of
6166 sign and zero extension, that are equivalent in these cases. */
6167 if (flag_expensive_optimizations
6168 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6169 && ((nonzero_bits (new, tmode
)
6170 & ~(((unsigned HOST_WIDE_INT
)
6171 GET_MODE_MASK (tmode
))
6175 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6176 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6178 /* Prefer ZERO_EXTENSION, since it gives more information to
6180 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6185 /* Otherwise, sign- or zero-extend unless we already are in the
6188 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6192 /* Unless this is a COMPARE or we have a funny memory reference,
6193 don't do anything with zero-extending field extracts starting at
6194 the low-order bit since they are simple AND operations. */
6195 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6196 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6199 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6200 we would be spanning bytes or if the position is not a constant and the
6201 length is not 1. In all other cases, we would only be going outside
6202 our object in cases when an original shift would have been
6204 if (! spans_byte
&& GET_CODE (inner
) == MEM
6205 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6206 || (pos_rtx
!= 0 && len
!= 1)))
6209 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6210 and the mode for the result. */
6211 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6213 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6214 pos_mode
= mode_for_extraction (EP_insv
, 2);
6215 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6218 if (! in_dest
&& unsignedp
6219 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6221 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6222 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6223 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6226 if (! in_dest
&& ! unsignedp
6227 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6229 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6230 pos_mode
= mode_for_extraction (EP_extv
, 3);
6231 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6234 /* Never narrow an object, since that might not be safe. */
6236 if (mode
!= VOIDmode
6237 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6238 extraction_mode
= mode
;
6240 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6241 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6242 pos_mode
= GET_MODE (pos_rtx
);
6244 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6245 if we have to change the mode of memory and cannot, the desired mode is
6247 if (GET_CODE (inner
) != MEM
)
6248 wanted_inner_mode
= wanted_inner_reg_mode
;
6249 else if (inner_mode
!= wanted_inner_mode
6250 && (mode_dependent_address_p (XEXP (inner
, 0))
6251 || MEM_VOLATILE_P (inner
)))
6252 wanted_inner_mode
= extraction_mode
;
6256 if (BITS_BIG_ENDIAN
)
6258 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6259 BITS_BIG_ENDIAN style. If position is constant, compute new
6260 position. Otherwise, build subtraction.
6261 Note that POS is relative to the mode of the original argument.
6262 If it's a MEM we need to recompute POS relative to that.
6263 However, if we're extracting from (or inserting into) a register,
6264 we want to recompute POS relative to wanted_inner_mode. */
6265 int width
= (GET_CODE (inner
) == MEM
6266 ? GET_MODE_BITSIZE (is_mode
)
6267 : GET_MODE_BITSIZE (wanted_inner_mode
));
6270 pos
= width
- len
- pos
;
6273 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6274 /* POS may be less than 0 now, but we check for that below.
6275 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6278 /* If INNER has a wider mode, make it smaller. If this is a constant
6279 extract, try to adjust the byte to point to the byte containing
6281 if (wanted_inner_mode
!= VOIDmode
6282 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6283 && ((GET_CODE (inner
) == MEM
6284 && (inner_mode
== wanted_inner_mode
6285 || (! mode_dependent_address_p (XEXP (inner
, 0))
6286 && ! MEM_VOLATILE_P (inner
))))))
6290 /* The computations below will be correct if the machine is big
6291 endian in both bits and bytes or little endian in bits and bytes.
6292 If it is mixed, we must adjust. */
6294 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6295 adjust OFFSET to compensate. */
6296 if (BYTES_BIG_ENDIAN
6298 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6299 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6301 /* If this is a constant position, we can move to the desired byte. */
6304 offset
+= pos
/ BITS_PER_UNIT
;
6305 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6308 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6310 && is_mode
!= wanted_inner_mode
)
6311 offset
= (GET_MODE_SIZE (is_mode
)
6312 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6314 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6315 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6318 /* If INNER is not memory, we can always get it into the proper mode. If we
6319 are changing its mode, POS must be a constant and smaller than the size
6321 else if (GET_CODE (inner
) != MEM
)
6323 if (GET_MODE (inner
) != wanted_inner_mode
6325 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6328 inner
= force_to_mode (inner
, wanted_inner_mode
,
6330 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6331 ? ~(unsigned HOST_WIDE_INT
) 0
6332 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6337 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6338 have to zero extend. Otherwise, we can just use a SUBREG. */
6340 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6342 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6344 /* If we know that no extraneous bits are set, and that the high
6345 bit is not set, convert extraction to cheaper one - either
6346 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6348 if (flag_expensive_optimizations
6349 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6350 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6351 & ~(((unsigned HOST_WIDE_INT
)
6352 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6356 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6358 /* Prefer ZERO_EXTENSION, since it gives more information to
6360 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6365 else if (pos_rtx
!= 0
6366 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6367 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6369 /* Make POS_RTX unless we already have it and it is correct. If we don't
6370 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6372 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6373 pos_rtx
= orig_pos_rtx
;
6375 else if (pos_rtx
== 0)
6376 pos_rtx
= GEN_INT (pos
);
6378 /* Make the required operation. See if we can use existing rtx. */
6379 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6380 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6382 new = gen_lowpart_for_combine (mode
, new);
6387 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6388 with any other operations in X. Return X without that shift if so. */
6391 extract_left_shift (x
, count
)
6395 enum rtx_code code
= GET_CODE (x
);
6396 enum machine_mode mode
= GET_MODE (x
);
6402 /* This is the shift itself. If it is wide enough, we will return
6403 either the value being shifted if the shift count is equal to
6404 COUNT or a shift for the difference. */
6405 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6406 && INTVAL (XEXP (x
, 1)) >= count
)
6407 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6408 INTVAL (XEXP (x
, 1)) - count
);
6412 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6413 return simplify_gen_unary (code
, mode
, tem
, mode
);
6417 case PLUS
: case IOR
: case XOR
: case AND
:
6418 /* If we can safely shift this constant and we find the inner shift,
6419 make a new operation. */
6420 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6421 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6422 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6423 return gen_binary (code
, mode
, tem
,
6424 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6435 /* Look at the expression rooted at X. Look for expressions
6436 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6437 Form these expressions.
6439 Return the new rtx, usually just X.
6441 Also, for machines like the VAX that don't have logical shift insns,
6442 try to convert logical to arithmetic shift operations in cases where
6443 they are equivalent. This undoes the canonicalizations to logical
6444 shifts done elsewhere.
6446 We try, as much as possible, to re-use rtl expressions to save memory.
6448 IN_CODE says what kind of expression we are processing. Normally, it is
6449 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6450 being kludges), it is MEM. When processing the arguments of a comparison
6451 or a COMPARE against zero, it is COMPARE. */
6454 make_compound_operation (x
, in_code
)
6456 enum rtx_code in_code
;
6458 enum rtx_code code
= GET_CODE (x
);
6459 enum machine_mode mode
= GET_MODE (x
);
6460 int mode_width
= GET_MODE_BITSIZE (mode
);
6462 enum rtx_code next_code
;
6468 /* Select the code to be used in recursive calls. Once we are inside an
6469 address, we stay there. If we have a comparison, set to COMPARE,
6470 but once inside, go back to our default of SET. */
6472 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6473 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6474 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6475 : in_code
== COMPARE
? SET
: in_code
);
6477 /* Process depending on the code of this operation. If NEW is set
6478 nonzero, it will be returned. */
6483 /* Convert shifts by constants into multiplications if inside
6485 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6486 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6487 && INTVAL (XEXP (x
, 1)) >= 0)
6489 new = make_compound_operation (XEXP (x
, 0), next_code
);
6490 new = gen_rtx_MULT (mode
, new,
6491 GEN_INT ((HOST_WIDE_INT
) 1
6492 << INTVAL (XEXP (x
, 1))));
6497 /* If the second operand is not a constant, we can't do anything
6499 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6502 /* If the constant is a power of two minus one and the first operand
6503 is a logical right shift, make an extraction. */
6504 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6505 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6507 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6508 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6509 0, in_code
== COMPARE
);
6512 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6513 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6514 && subreg_lowpart_p (XEXP (x
, 0))
6515 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6516 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6518 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6520 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6521 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6522 0, in_code
== COMPARE
);
6524 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6525 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6526 || GET_CODE (XEXP (x
, 0)) == IOR
)
6527 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6528 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6529 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6531 /* Apply the distributive law, and then try to make extractions. */
6532 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6533 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6535 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6537 new = make_compound_operation (new, in_code
);
6540 /* If we are have (and (rotate X C) M) and C is larger than the number
6541 of bits in M, this is an extraction. */
6543 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6544 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6545 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6546 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6548 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6549 new = make_extraction (mode
, new,
6550 (GET_MODE_BITSIZE (mode
)
6551 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6552 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6555 /* On machines without logical shifts, if the operand of the AND is
6556 a logical shift and our mask turns off all the propagated sign
6557 bits, we can replace the logical shift with an arithmetic shift. */
6558 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6559 && !have_insn_for (LSHIFTRT
, mode
)
6560 && have_insn_for (ASHIFTRT
, mode
)
6561 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6562 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6563 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6564 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6566 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6568 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6569 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6571 gen_rtx_ASHIFTRT (mode
,
6572 make_compound_operation
6573 (XEXP (XEXP (x
, 0), 0), next_code
),
6574 XEXP (XEXP (x
, 0), 1)));
6577 /* If the constant is one less than a power of two, this might be
6578 representable by an extraction even if no shift is present.
6579 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6580 we are in a COMPARE. */
6581 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6582 new = make_extraction (mode
,
6583 make_compound_operation (XEXP (x
, 0),
6585 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6587 /* If we are in a comparison and this is an AND with a power of two,
6588 convert this into the appropriate bit extract. */
6589 else if (in_code
== COMPARE
6590 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6591 new = make_extraction (mode
,
6592 make_compound_operation (XEXP (x
, 0),
6594 i
, NULL_RTX
, 1, 1, 0, 1);
6599 /* If the sign bit is known to be zero, replace this with an
6600 arithmetic shift. */
6601 if (have_insn_for (ASHIFTRT
, mode
)
6602 && ! have_insn_for (LSHIFTRT
, mode
)
6603 && mode_width
<= HOST_BITS_PER_WIDE_INT
6604 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6606 new = gen_rtx_ASHIFTRT (mode
,
6607 make_compound_operation (XEXP (x
, 0),
6613 /* ... fall through ... */
6619 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6620 this is a SIGN_EXTRACT. */
6621 if (GET_CODE (rhs
) == CONST_INT
6622 && GET_CODE (lhs
) == ASHIFT
6623 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6624 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6626 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6627 new = make_extraction (mode
, new,
6628 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6629 NULL_RTX
, mode_width
- INTVAL (rhs
),
6630 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6634 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6635 If so, try to merge the shifts into a SIGN_EXTEND. We could
6636 also do this for some cases of SIGN_EXTRACT, but it doesn't
6637 seem worth the effort; the case checked for occurs on Alpha. */
6639 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6640 && ! (GET_CODE (lhs
) == SUBREG
6641 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6642 && GET_CODE (rhs
) == CONST_INT
6643 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6644 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6645 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6646 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6647 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6652 /* Call ourselves recursively on the inner expression. If we are
6653 narrowing the object and it has a different RTL code from
6654 what it originally did, do this SUBREG as a force_to_mode. */
6656 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6657 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6658 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6659 && subreg_lowpart_p (x
))
6661 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6664 /* If we have something other than a SUBREG, we might have
6665 done an expansion, so rerun ourselves. */
6666 if (GET_CODE (newer
) != SUBREG
)
6667 newer
= make_compound_operation (newer
, in_code
);
6672 /* If this is a paradoxical subreg, and the new code is a sign or
6673 zero extension, omit the subreg and widen the extension. If it
6674 is a regular subreg, we can still get rid of the subreg by not
6675 widening so much, or in fact removing the extension entirely. */
6676 if ((GET_CODE (tem
) == SIGN_EXTEND
6677 || GET_CODE (tem
) == ZERO_EXTEND
)
6678 && subreg_lowpart_p (x
))
6680 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6681 || (GET_MODE_SIZE (mode
) >
6682 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6684 if (! INTEGRAL_MODE_P (mode
))
6686 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6689 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6700 x
= gen_lowpart_for_combine (mode
, new);
6701 code
= GET_CODE (x
);
6704 /* Now recursively process each operand of this operation. */
6705 fmt
= GET_RTX_FORMAT (code
);
6706 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6709 new = make_compound_operation (XEXP (x
, i
), next_code
);
6710 SUBST (XEXP (x
, i
), new);
6716 /* Given M see if it is a value that would select a field of bits
6717 within an item, but not the entire word. Return -1 if not.
6718 Otherwise, return the starting position of the field, where 0 is the
6721 *PLEN is set to the length of the field. */
6724 get_pos_from_mask (m
, plen
)
6725 unsigned HOST_WIDE_INT m
;
6726 unsigned HOST_WIDE_INT
*plen
;
6728 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6729 int pos
= exact_log2 (m
& -m
);
6735 /* Now shift off the low-order zero bits and see if we have a power of
6737 len
= exact_log2 ((m
>> pos
) + 1);
6746 /* See if X can be simplified knowing that we will only refer to it in
6747 MODE and will only refer to those bits that are nonzero in MASK.
6748 If other bits are being computed or if masking operations are done
6749 that select a superset of the bits in MASK, they can sometimes be
6752 Return a possibly simplified expression, but always convert X to
6753 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6755 Also, if REG is nonzero and X is a register equal in value to REG,
6758 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6759 are all off in X. This is used when X will be complemented, by either
6760 NOT, NEG, or XOR. */
6763 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6765 enum machine_mode mode
;
6766 unsigned HOST_WIDE_INT mask
;
6770 enum rtx_code code
= GET_CODE (x
);
6771 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6772 enum machine_mode op_mode
;
6773 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6776 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6777 code below will do the wrong thing since the mode of such an
6778 expression is VOIDmode.
6780 Also do nothing if X is a CLOBBER; this can happen if X was
6781 the return value from a call to gen_lowpart_for_combine. */
6782 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6785 /* We want to perform the operation is its present mode unless we know
6786 that the operation is valid in MODE, in which case we do the operation
6788 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6789 && have_insn_for (code
, mode
))
6790 ? mode
: GET_MODE (x
));
6792 /* It is not valid to do a right-shift in a narrower mode
6793 than the one it came in with. */
6794 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6795 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6796 op_mode
= GET_MODE (x
);
6798 /* Truncate MASK to fit OP_MODE. */
6800 mask
&= GET_MODE_MASK (op_mode
);
6802 /* When we have an arithmetic operation, or a shift whose count we
6803 do not know, we need to assume that all bit the up to the highest-order
6804 bit in MASK will be needed. This is how we form such a mask. */
6806 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6807 ? GET_MODE_MASK (op_mode
)
6808 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6811 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6813 /* Determine what bits of X are guaranteed to be (non)zero. */
6814 nonzero
= nonzero_bits (x
, mode
);
6816 /* If none of the bits in X are needed, return a zero. */
6817 if (! just_select
&& (nonzero
& mask
) == 0)
6820 /* If X is a CONST_INT, return a new one. Do this here since the
6821 test below will fail. */
6822 if (GET_CODE (x
) == CONST_INT
)
6824 if (SCALAR_INT_MODE_P (mode
))
6825 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6828 x
= GEN_INT (INTVAL (x
) & mask
);
6829 return gen_lowpart_common (mode
, x
);
6833 /* If X is narrower than MODE and we want all the bits in X's mode, just
6834 get X in the proper mode. */
6835 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6836 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6837 return gen_lowpart_for_combine (mode
, x
);
6839 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6840 MASK are already known to be zero in X, we need not do anything. */
6841 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6847 /* If X is a (clobber (const_int)), return it since we know we are
6848 generating something that won't match. */
6852 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6853 spanned the boundary of the MEM. If we are now masking so it is
6854 within that boundary, we don't need the USE any more. */
6855 if (! BITS_BIG_ENDIAN
6856 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6857 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6864 x
= expand_compound_operation (x
);
6865 if (GET_CODE (x
) != code
)
6866 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6870 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6871 || rtx_equal_p (reg
, get_last_value (x
))))
6876 if (subreg_lowpart_p (x
)
6877 /* We can ignore the effect of this SUBREG if it narrows the mode or
6878 if the constant masks to zero all the bits the mode doesn't
6880 && ((GET_MODE_SIZE (GET_MODE (x
))
6881 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6883 & GET_MODE_MASK (GET_MODE (x
))
6884 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6885 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6889 /* If this is an AND with a constant, convert it into an AND
6890 whose constant is the AND of that constant with MASK. If it
6891 remains an AND of MASK, delete it since it is redundant. */
6893 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6895 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6896 mask
& INTVAL (XEXP (x
, 1)));
6898 /* If X is still an AND, see if it is an AND with a mask that
6899 is just some low-order bits. If so, and it is MASK, we don't
6902 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6903 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6907 /* If it remains an AND, try making another AND with the bits
6908 in the mode mask that aren't in MASK turned on. If the
6909 constant in the AND is wide enough, this might make a
6910 cheaper constant. */
6912 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6913 && GET_MODE_MASK (GET_MODE (x
)) != mask
6914 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6916 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6917 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6918 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6921 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6922 number, sign extend it. */
6923 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6924 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6925 cval
|= (HOST_WIDE_INT
) -1 << width
;
6927 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6928 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6938 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6939 low-order bits (as in an alignment operation) and FOO is already
6940 aligned to that boundary, mask C1 to that boundary as well.
6941 This may eliminate that PLUS and, later, the AND. */
6944 unsigned int width
= GET_MODE_BITSIZE (mode
);
6945 unsigned HOST_WIDE_INT smask
= mask
;
6947 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6948 number, sign extend it. */
6950 if (width
< HOST_BITS_PER_WIDE_INT
6951 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6952 smask
|= (HOST_WIDE_INT
) -1 << width
;
6954 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6955 && exact_log2 (- smask
) >= 0
6956 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6957 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6958 return force_to_mode (plus_constant (XEXP (x
, 0),
6959 (INTVAL (XEXP (x
, 1)) & smask
)),
6960 mode
, smask
, reg
, next_select
);
6963 /* ... fall through ... */
6966 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6967 most significant bit in MASK since carries from those bits will
6968 affect the bits we are interested in. */
6973 /* If X is (minus C Y) where C's least set bit is larger than any bit
6974 in the mask, then we may replace with (neg Y). */
6975 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6976 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6977 & -INTVAL (XEXP (x
, 0))))
6980 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6982 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6985 /* Similarly, if C contains every bit in the mask, then we may
6986 replace with (not Y). */
6987 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6988 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6989 == INTVAL (XEXP (x
, 0))))
6991 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6992 XEXP (x
, 1), GET_MODE (x
));
6993 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7001 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7002 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7003 operation which may be a bitfield extraction. Ensure that the
7004 constant we form is not wider than the mode of X. */
7006 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7007 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7008 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7009 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7010 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7011 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7012 + floor_log2 (INTVAL (XEXP (x
, 1))))
7013 < GET_MODE_BITSIZE (GET_MODE (x
)))
7014 && (INTVAL (XEXP (x
, 1))
7015 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7017 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7018 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7019 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
7020 XEXP (XEXP (x
, 0), 0), temp
);
7021 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7022 XEXP (XEXP (x
, 0), 1));
7023 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7027 /* For most binary operations, just propagate into the operation and
7028 change the mode if we have an operation of that mode. */
7030 op0
= gen_lowpart_for_combine (op_mode
,
7031 force_to_mode (XEXP (x
, 0), mode
, mask
,
7033 op1
= gen_lowpart_for_combine (op_mode
,
7034 force_to_mode (XEXP (x
, 1), mode
, mask
,
7037 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7038 x
= gen_binary (code
, op_mode
, op0
, op1
);
7042 /* For left shifts, do the same, but just for the first operand.
7043 However, we cannot do anything with shifts where we cannot
7044 guarantee that the counts are smaller than the size of the mode
7045 because such a count will have a different meaning in a
7048 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7049 && INTVAL (XEXP (x
, 1)) >= 0
7050 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7051 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7052 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7053 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7056 /* If the shift count is a constant and we can do arithmetic in
7057 the mode of the shift, refine which bits we need. Otherwise, use the
7058 conservative form of the mask. */
7059 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7060 && INTVAL (XEXP (x
, 1)) >= 0
7061 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7062 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7063 mask
>>= INTVAL (XEXP (x
, 1));
7067 op0
= gen_lowpart_for_combine (op_mode
,
7068 force_to_mode (XEXP (x
, 0), op_mode
,
7069 mask
, reg
, next_select
));
7071 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7072 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7076 /* Here we can only do something if the shift count is a constant,
7077 this shift constant is valid for the host, and we can do arithmetic
7080 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7081 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7082 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7084 rtx inner
= XEXP (x
, 0);
7085 unsigned HOST_WIDE_INT inner_mask
;
7087 /* Select the mask of the bits we need for the shift operand. */
7088 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7090 /* We can only change the mode of the shift if we can do arithmetic
7091 in the mode of the shift and INNER_MASK is no wider than the
7092 width of OP_MODE. */
7093 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7094 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7095 op_mode
= GET_MODE (x
);
7097 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7099 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7100 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7103 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7104 shift and AND produces only copies of the sign bit (C2 is one less
7105 than a power of two), we can do this with just a shift. */
7107 if (GET_CODE (x
) == LSHIFTRT
7108 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7109 /* The shift puts one of the sign bit copies in the least significant
7111 && ((INTVAL (XEXP (x
, 1))
7112 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7113 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7114 && exact_log2 (mask
+ 1) >= 0
7115 /* Number of bits left after the shift must be more than the mask
7117 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7118 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7119 /* Must be more sign bit copies than the mask needs. */
7120 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7121 >= exact_log2 (mask
+ 1)))
7122 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7123 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7124 - exact_log2 (mask
+ 1)));
7129 /* If we are just looking for the sign bit, we don't need this shift at
7130 all, even if it has a variable count. */
7131 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7132 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7133 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7134 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7136 /* If this is a shift by a constant, get a mask that contains those bits
7137 that are not copies of the sign bit. We then have two cases: If
7138 MASK only includes those bits, this can be a logical shift, which may
7139 allow simplifications. If MASK is a single-bit field not within
7140 those bits, we are requesting a copy of the sign bit and hence can
7141 shift the sign bit to the appropriate location. */
7143 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7144 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7148 /* If the considered data is wider than HOST_WIDE_INT, we can't
7149 represent a mask for all its bits in a single scalar.
7150 But we only care about the lower bits, so calculate these. */
7152 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7154 nonzero
= ~(HOST_WIDE_INT
) 0;
7156 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7157 is the number of bits a full-width mask would have set.
7158 We need only shift if these are fewer than nonzero can
7159 hold. If not, we must keep all bits set in nonzero. */
7161 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7162 < HOST_BITS_PER_WIDE_INT
)
7163 nonzero
>>= INTVAL (XEXP (x
, 1))
7164 + HOST_BITS_PER_WIDE_INT
7165 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7169 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7170 nonzero
>>= INTVAL (XEXP (x
, 1));
7173 if ((mask
& ~nonzero
) == 0
7174 || (i
= exact_log2 (mask
)) >= 0)
7176 x
= simplify_shift_const
7177 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7178 i
< 0 ? INTVAL (XEXP (x
, 1))
7179 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7181 if (GET_CODE (x
) != ASHIFTRT
)
7182 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7186 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7187 even if the shift count isn't a constant. */
7189 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7193 /* If this is a zero- or sign-extension operation that just affects bits
7194 we don't care about, remove it. Be sure the call above returned
7195 something that is still a shift. */
7197 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7198 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7199 && INTVAL (XEXP (x
, 1)) >= 0
7200 && (INTVAL (XEXP (x
, 1))
7201 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7202 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7203 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7204 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7205 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7212 /* If the shift count is constant and we can do computations
7213 in the mode of X, compute where the bits we care about are.
7214 Otherwise, we can't do anything. Don't change the mode of
7215 the shift or propagate MODE into the shift, though. */
7216 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7217 && INTVAL (XEXP (x
, 1)) >= 0)
7219 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7220 GET_MODE (x
), GEN_INT (mask
),
7222 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7224 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7225 INTVAL (temp
), reg
, next_select
));
7230 /* If we just want the low-order bit, the NEG isn't needed since it
7231 won't change the low-order bit. */
7233 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7235 /* We need any bits less significant than the most significant bit in
7236 MASK since carries from those bits will affect the bits we are
7242 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7243 same as the XOR case above. Ensure that the constant we form is not
7244 wider than the mode of X. */
7246 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7247 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7248 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7249 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7250 < GET_MODE_BITSIZE (GET_MODE (x
)))
7251 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7253 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7254 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7255 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7257 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7260 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7261 use the full mask inside the NOT. */
7265 op0
= gen_lowpart_for_combine (op_mode
,
7266 force_to_mode (XEXP (x
, 0), mode
, mask
,
7268 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7269 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7273 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7274 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7275 which is equal to STORE_FLAG_VALUE. */
7276 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7277 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7278 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7279 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7284 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7285 written in a narrower mode. We play it safe and do not do so. */
7288 gen_lowpart_for_combine (GET_MODE (x
),
7289 force_to_mode (XEXP (x
, 1), mode
,
7290 mask
, reg
, next_select
)));
7292 gen_lowpart_for_combine (GET_MODE (x
),
7293 force_to_mode (XEXP (x
, 2), mode
,
7294 mask
, reg
,next_select
)));
7301 /* Ensure we return a value of the proper mode. */
7302 return gen_lowpart_for_combine (mode
, x
);
7305 /* Return nonzero if X is an expression that has one of two values depending on
7306 whether some other value is zero or nonzero. In that case, we return the
7307 value that is being tested, *PTRUE is set to the value if the rtx being
7308 returned has a nonzero value, and *PFALSE is set to the other alternative.
7310 If we return zero, we set *PTRUE and *PFALSE to X. */
7313 if_then_else_cond (x
, ptrue
, pfalse
)
7315 rtx
*ptrue
, *pfalse
;
7317 enum machine_mode mode
= GET_MODE (x
);
7318 enum rtx_code code
= GET_CODE (x
);
7319 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7320 unsigned HOST_WIDE_INT nz
;
7322 /* If we are comparing a value against zero, we are done. */
7323 if ((code
== NE
|| code
== EQ
)
7324 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7326 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7327 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7331 /* If this is a unary operation whose operand has one of two values, apply
7332 our opcode to compute those values. */
7333 else if (GET_RTX_CLASS (code
) == '1'
7334 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7336 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7337 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7338 GET_MODE (XEXP (x
, 0)));
7342 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7343 make can't possibly match and would suppress other optimizations. */
7344 else if (code
== COMPARE
)
7347 /* If this is a binary operation, see if either side has only one of two
7348 values. If either one does or if both do and they are conditional on
7349 the same value, compute the new true and false values. */
7350 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7351 || GET_RTX_CLASS (code
) == '<')
7353 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7354 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7356 if ((cond0
!= 0 || cond1
!= 0)
7357 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7359 /* If if_then_else_cond returned zero, then true/false are the
7360 same rtl. We must copy one of them to prevent invalid rtl
7363 true0
= copy_rtx (true0
);
7364 else if (cond1
== 0)
7365 true1
= copy_rtx (true1
);
7367 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7368 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7369 return cond0
? cond0
: cond1
;
7372 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7373 operands is zero when the other is nonzero, and vice-versa,
7374 and STORE_FLAG_VALUE is 1 or -1. */
7376 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7377 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7379 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7381 rtx op0
= XEXP (XEXP (x
, 0), 1);
7382 rtx op1
= XEXP (XEXP (x
, 1), 1);
7384 cond0
= XEXP (XEXP (x
, 0), 0);
7385 cond1
= XEXP (XEXP (x
, 1), 0);
7387 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7388 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7389 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7390 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7391 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7392 || ((swap_condition (GET_CODE (cond0
))
7393 == combine_reversed_comparison_code (cond1
))
7394 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7395 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7396 && ! side_effects_p (x
))
7398 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7399 *pfalse
= gen_binary (MULT
, mode
,
7401 ? simplify_gen_unary (NEG
, mode
, op1
,
7409 /* Similarly for MULT, AND and UMIN, except that for these the result
7411 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7412 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7413 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7415 cond0
= XEXP (XEXP (x
, 0), 0);
7416 cond1
= XEXP (XEXP (x
, 1), 0);
7418 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7419 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7420 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7421 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7422 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7423 || ((swap_condition (GET_CODE (cond0
))
7424 == combine_reversed_comparison_code (cond1
))
7425 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7426 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7427 && ! side_effects_p (x
))
7429 *ptrue
= *pfalse
= const0_rtx
;
7435 else if (code
== IF_THEN_ELSE
)
7437 /* If we have IF_THEN_ELSE already, extract the condition and
7438 canonicalize it if it is NE or EQ. */
7439 cond0
= XEXP (x
, 0);
7440 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7441 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7442 return XEXP (cond0
, 0);
7443 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7445 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7446 return XEXP (cond0
, 0);
7452 /* If X is a SUBREG, we can narrow both the true and false values
7453 if the inner expression, if there is a condition. */
7454 else if (code
== SUBREG
7455 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7458 *ptrue
= simplify_gen_subreg (mode
, true0
,
7459 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7460 *pfalse
= simplify_gen_subreg (mode
, false0
,
7461 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7466 /* If X is a constant, this isn't special and will cause confusions
7467 if we treat it as such. Likewise if it is equivalent to a constant. */
7468 else if (CONSTANT_P (x
)
7469 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7472 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7473 will be least confusing to the rest of the compiler. */
7474 else if (mode
== BImode
)
7476 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7480 /* If X is known to be either 0 or -1, those are the true and
7481 false values when testing X. */
7482 else if (x
== constm1_rtx
|| x
== const0_rtx
7483 || (mode
!= VOIDmode
7484 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7486 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7490 /* Likewise for 0 or a single bit. */
7491 else if (mode
!= VOIDmode
7492 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7493 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7495 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7499 /* Otherwise fail; show no condition with true and false values the same. */
7500 *ptrue
= *pfalse
= x
;
7504 /* Return the value of expression X given the fact that condition COND
7505 is known to be true when applied to REG as its first operand and VAL
7506 as its second. X is known to not be shared and so can be modified in
7509 We only handle the simplest cases, and specifically those cases that
7510 arise with IF_THEN_ELSE expressions. */
7513 known_cond (x
, cond
, reg
, val
)
7518 enum rtx_code code
= GET_CODE (x
);
7523 if (side_effects_p (x
))
7526 /* If either operand of the condition is a floating point value,
7527 then we have to avoid collapsing an EQ comparison. */
7529 && rtx_equal_p (x
, reg
)
7530 && ! FLOAT_MODE_P (GET_MODE (x
))
7531 && ! FLOAT_MODE_P (GET_MODE (val
)))
7534 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7537 /* If X is (abs REG) and we know something about REG's relationship
7538 with zero, we may be able to simplify this. */
7540 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7543 case GE
: case GT
: case EQ
:
7546 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7548 GET_MODE (XEXP (x
, 0)));
7553 /* The only other cases we handle are MIN, MAX, and comparisons if the
7554 operands are the same as REG and VAL. */
7556 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7558 if (rtx_equal_p (XEXP (x
, 0), val
))
7559 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7561 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7563 if (GET_RTX_CLASS (code
) == '<')
7565 if (comparison_dominates_p (cond
, code
))
7566 return const_true_rtx
;
7568 code
= combine_reversed_comparison_code (x
);
7570 && comparison_dominates_p (cond
, code
))
7575 else if (code
== SMAX
|| code
== SMIN
7576 || code
== UMIN
|| code
== UMAX
)
7578 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7580 /* Do not reverse the condition when it is NE or EQ.
7581 This is because we cannot conclude anything about
7582 the value of 'SMAX (x, y)' when x is not equal to y,
7583 but we can when x equals y. */
7584 if ((code
== SMAX
|| code
== UMAX
)
7585 && ! (cond
== EQ
|| cond
== NE
))
7586 cond
= reverse_condition (cond
);
7591 return unsignedp
? x
: XEXP (x
, 1);
7593 return unsignedp
? x
: XEXP (x
, 0);
7595 return unsignedp
? XEXP (x
, 1) : x
;
7597 return unsignedp
? XEXP (x
, 0) : x
;
7604 else if (code
== SUBREG
)
7606 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7607 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7609 if (SUBREG_REG (x
) != r
)
7611 /* We must simplify subreg here, before we lose track of the
7612 original inner_mode. */
7613 new = simplify_subreg (GET_MODE (x
), r
,
7614 inner_mode
, SUBREG_BYTE (x
));
7618 SUBST (SUBREG_REG (x
), r
);
7623 /* We don't have to handle SIGN_EXTEND here, because even in the
7624 case of replacing something with a modeless CONST_INT, a
7625 CONST_INT is already (supposed to be) a valid sign extension for
7626 its narrower mode, which implies it's already properly
7627 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7628 story is different. */
7629 else if (code
== ZERO_EXTEND
)
7631 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7632 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7634 if (XEXP (x
, 0) != r
)
7636 /* We must simplify the zero_extend here, before we lose
7637 track of the original inner_mode. */
7638 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7643 SUBST (XEXP (x
, 0), r
);
7649 fmt
= GET_RTX_FORMAT (code
);
7650 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7653 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7654 else if (fmt
[i
] == 'E')
7655 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7656 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7663 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7664 assignment as a field assignment. */
7667 rtx_equal_for_field_assignment_p (x
, y
)
7671 if (x
== y
|| rtx_equal_p (x
, y
))
7674 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7677 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7678 Note that all SUBREGs of MEM are paradoxical; otherwise they
7679 would have been rewritten. */
7680 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7681 && GET_CODE (SUBREG_REG (y
)) == MEM
7682 && rtx_equal_p (SUBREG_REG (y
),
7683 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7686 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7687 && GET_CODE (SUBREG_REG (x
)) == MEM
7688 && rtx_equal_p (SUBREG_REG (x
),
7689 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7692 /* We used to see if get_last_value of X and Y were the same but that's
7693 not correct. In one direction, we'll cause the assignment to have
7694 the wrong destination and in the case, we'll import a register into this
7695 insn that might have already have been dead. So fail if none of the
7696 above cases are true. */
7700 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7701 Return that assignment if so.
7703 We only handle the most common cases. */
7706 make_field_assignment (x
)
7709 rtx dest
= SET_DEST (x
);
7710 rtx src
= SET_SRC (x
);
7715 unsigned HOST_WIDE_INT len
;
7717 enum machine_mode mode
;
7719 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7720 a clear of a one-bit field. We will have changed it to
7721 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7724 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7725 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7726 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7727 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7729 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7732 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7736 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7737 && subreg_lowpart_p (XEXP (src
, 0))
7738 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7739 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7740 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7741 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7742 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7744 assign
= make_extraction (VOIDmode
, dest
, 0,
7745 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7748 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7752 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7754 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7755 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7756 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7758 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7761 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7765 /* The other case we handle is assignments into a constant-position
7766 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7767 a mask that has all one bits except for a group of zero bits and
7768 OTHER is known to have zeros where C1 has ones, this is such an
7769 assignment. Compute the position and length from C1. Shift OTHER
7770 to the appropriate position, force it to the required mode, and
7771 make the extraction. Check for the AND in both operands. */
7773 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7776 rhs
= expand_compound_operation (XEXP (src
, 0));
7777 lhs
= expand_compound_operation (XEXP (src
, 1));
7779 if (GET_CODE (rhs
) == AND
7780 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7781 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7782 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7783 else if (GET_CODE (lhs
) == AND
7784 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7785 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7786 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7790 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7791 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7792 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7793 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7796 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7800 /* The mode to use for the source is the mode of the assignment, or of
7801 what is inside a possible STRICT_LOW_PART. */
7802 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7803 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7805 /* Shift OTHER right POS places and make it the source, restricting it
7806 to the proper length and mode. */
7808 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7809 GET_MODE (src
), other
, pos
),
7811 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7812 ? ~(unsigned HOST_WIDE_INT
) 0
7813 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7816 return gen_rtx_SET (VOIDmode
, assign
, src
);
7819 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7823 apply_distributive_law (x
)
7826 enum rtx_code code
= GET_CODE (x
);
7827 rtx lhs
, rhs
, other
;
7829 enum rtx_code inner_code
;
7831 /* Distributivity is not true for floating point.
7832 It can change the value. So don't do it.
7833 -- rms and moshier@world.std.com. */
7834 if (FLOAT_MODE_P (GET_MODE (x
)))
7837 /* The outer operation can only be one of the following: */
7838 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7839 && code
!= PLUS
&& code
!= MINUS
)
7842 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7844 /* If either operand is a primitive we can't do anything, so get out
7846 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7847 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7850 lhs
= expand_compound_operation (lhs
);
7851 rhs
= expand_compound_operation (rhs
);
7852 inner_code
= GET_CODE (lhs
);
7853 if (inner_code
!= GET_CODE (rhs
))
7856 /* See if the inner and outer operations distribute. */
7863 /* These all distribute except over PLUS. */
7864 if (code
== PLUS
|| code
== MINUS
)
7869 if (code
!= PLUS
&& code
!= MINUS
)
7874 /* This is also a multiply, so it distributes over everything. */
7878 /* Non-paradoxical SUBREGs distributes over all operations, provided
7879 the inner modes and byte offsets are the same, this is an extraction
7880 of a low-order part, we don't convert an fp operation to int or
7881 vice versa, and we would not be converting a single-word
7882 operation into a multi-word operation. The latter test is not
7883 required, but it prevents generating unneeded multi-word operations.
7884 Some of the previous tests are redundant given the latter test, but
7885 are retained because they are required for correctness.
7887 We produce the result slightly differently in this case. */
7889 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7890 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7891 || ! subreg_lowpart_p (lhs
)
7892 || (GET_MODE_CLASS (GET_MODE (lhs
))
7893 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7894 || (GET_MODE_SIZE (GET_MODE (lhs
))
7895 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7896 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7899 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7900 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7901 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7907 /* Set LHS and RHS to the inner operands (A and B in the example
7908 above) and set OTHER to the common operand (C in the example).
7909 These is only one way to do this unless the inner operation is
7911 if (GET_RTX_CLASS (inner_code
) == 'c'
7912 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7913 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7914 else if (GET_RTX_CLASS (inner_code
) == 'c'
7915 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7916 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7917 else if (GET_RTX_CLASS (inner_code
) == 'c'
7918 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7919 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7920 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7921 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7925 /* Form the new inner operation, seeing if it simplifies first. */
7926 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7928 /* There is one exception to the general way of distributing:
7929 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7930 if (code
== XOR
&& inner_code
== IOR
)
7933 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7936 /* We may be able to continuing distributing the result, so call
7937 ourselves recursively on the inner operation before forming the
7938 outer operation, which we return. */
7939 return gen_binary (inner_code
, GET_MODE (x
),
7940 apply_distributive_law (tem
), other
);
7943 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7946 Return an equivalent form, if different from X. Otherwise, return X. If
7947 X is zero, we are to always construct the equivalent form. */
7950 simplify_and_const_int (x
, mode
, varop
, constop
)
7952 enum machine_mode mode
;
7954 unsigned HOST_WIDE_INT constop
;
7956 unsigned HOST_WIDE_INT nonzero
;
7959 /* Simplify VAROP knowing that we will be only looking at some of the
7962 Note by passing in CONSTOP, we guarantee that the bits not set in
7963 CONSTOP are not significant and will never be examined. We must
7964 ensure that is the case by explicitly masking out those bits
7965 before returning. */
7966 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7968 /* If VAROP is a CLOBBER, we will fail so return it. */
7969 if (GET_CODE (varop
) == CLOBBER
)
7972 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7973 to VAROP and return the new constant. */
7974 if (GET_CODE (varop
) == CONST_INT
)
7975 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7977 /* See what bits may be nonzero in VAROP. Unlike the general case of
7978 a call to nonzero_bits, here we don't care about bits outside
7981 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7983 /* Turn off all bits in the constant that are known to already be zero.
7984 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7985 which is tested below. */
7989 /* If we don't have any bits left, return zero. */
7993 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7994 a power of two, we can replace this with an ASHIFT. */
7995 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7996 && (i
= exact_log2 (constop
)) >= 0)
7997 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7999 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8000 or XOR, then try to apply the distributive law. This may eliminate
8001 operations if either branch can be simplified because of the AND.
8002 It may also make some cases more complex, but those cases probably
8003 won't match a pattern either with or without this. */
8005 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8007 gen_lowpart_for_combine
8009 apply_distributive_law
8010 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8011 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8012 XEXP (varop
, 0), constop
),
8013 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8014 XEXP (varop
, 1), constop
))));
8016 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8017 the AND and see if one of the operands simplifies to zero. If so, we
8018 may eliminate it. */
8020 if (GET_CODE (varop
) == PLUS
8021 && exact_log2 (constop
+ 1) >= 0)
8025 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8026 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8027 if (o0
== const0_rtx
)
8029 if (o1
== const0_rtx
)
8033 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8034 if we already had one (just check for the simplest cases). */
8035 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8036 && GET_MODE (XEXP (x
, 0)) == mode
8037 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8038 varop
= XEXP (x
, 0);
8040 varop
= gen_lowpart_for_combine (mode
, varop
);
8042 /* If we can't make the SUBREG, try to return what we were given. */
8043 if (GET_CODE (varop
) == CLOBBER
)
8044 return x
? x
: varop
;
8046 /* If we are only masking insignificant bits, return VAROP. */
8047 if (constop
== nonzero
)
8051 /* Otherwise, return an AND. */
8052 constop
= trunc_int_for_mode (constop
, mode
);
8053 /* See how much, if any, of X we can use. */
8054 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8055 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8059 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8060 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8061 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8063 SUBST (XEXP (x
, 0), varop
);
8070 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8071 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8072 is less useful. We can't allow both, because that results in exponential
8073 run time recursion. There is a nullstone testcase that triggered
8074 this. This macro avoids accidental uses of num_sign_bit_copies. */
8075 #define num_sign_bit_copies()
8077 /* Given an expression, X, compute which bits in X can be nonzero.
8078 We don't care about bits outside of those defined in MODE.
8080 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8081 a shift, AND, or zero_extract, we can do better. */
8083 static unsigned HOST_WIDE_INT
8084 nonzero_bits (x
, mode
)
8086 enum machine_mode mode
;
8088 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8089 unsigned HOST_WIDE_INT inner_nz
;
8091 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8094 /* For floating-point values, assume all bits are needed. */
8095 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8098 /* If X is wider than MODE, use its mode instead. */
8099 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8101 mode
= GET_MODE (x
);
8102 nonzero
= GET_MODE_MASK (mode
);
8103 mode_width
= GET_MODE_BITSIZE (mode
);
8106 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8107 /* Our only callers in this case look for single bit values. So
8108 just return the mode mask. Those tests will then be false. */
8111 #ifndef WORD_REGISTER_OPERATIONS
8112 /* If MODE is wider than X, but both are a single word for both the host
8113 and target machines, we can compute this from which bits of the
8114 object might be nonzero in its own mode, taking into account the fact
8115 that on many CISC machines, accessing an object in a wider mode
8116 causes the high-order bits to become undefined. So they are
8117 not known to be zero. */
8119 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8120 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8121 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8122 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8124 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
8125 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8130 code
= GET_CODE (x
);
8134 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8135 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8136 all the bits above ptr_mode are known to be zero. */
8137 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8139 nonzero
&= GET_MODE_MASK (ptr_mode
);
8142 /* Include declared information about alignment of pointers. */
8143 /* ??? We don't properly preserve REG_POINTER changes across
8144 pointer-to-integer casts, so we can't trust it except for
8145 things that we know must be pointers. See execute/960116-1.c. */
8146 if ((x
== stack_pointer_rtx
8147 || x
== frame_pointer_rtx
8148 || x
== arg_pointer_rtx
)
8149 && REGNO_POINTER_ALIGN (REGNO (x
)))
8151 unsigned HOST_WIDE_INT alignment
8152 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8154 #ifdef PUSH_ROUNDING
8155 /* If PUSH_ROUNDING is defined, it is possible for the
8156 stack to be momentarily aligned only to that amount,
8157 so we pick the least alignment. */
8158 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8159 alignment
= MIN (PUSH_ROUNDING (1), alignment
);
8162 nonzero
&= ~(alignment
- 1);
8165 /* If X is a register whose nonzero bits value is current, use it.
8166 Otherwise, if X is a register whose value we can find, use that
8167 value. Otherwise, use the previously-computed global nonzero bits
8168 for this register. */
8170 if (reg_last_set_value
[REGNO (x
)] != 0
8171 && (reg_last_set_mode
[REGNO (x
)] == mode
8172 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8173 && GET_MODE_CLASS (mode
) == MODE_INT
))
8174 && (reg_last_set_label
[REGNO (x
)] == label_tick
8175 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8176 && REG_N_SETS (REGNO (x
)) == 1
8177 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8179 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8180 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8182 tem
= get_last_value (x
);
8186 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8187 /* If X is narrower than MODE and TEM is a non-negative
8188 constant that would appear negative in the mode of X,
8189 sign-extend it for use in reg_nonzero_bits because some
8190 machines (maybe most) will actually do the sign-extension
8191 and this is the conservative approach.
8193 ??? For 2.5, try to tighten up the MD files in this regard
8194 instead of this kludge. */
8196 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8197 && GET_CODE (tem
) == CONST_INT
8199 && 0 != (INTVAL (tem
)
8200 & ((HOST_WIDE_INT
) 1
8201 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8202 tem
= GEN_INT (INTVAL (tem
)
8203 | ((HOST_WIDE_INT
) (-1)
8204 << GET_MODE_BITSIZE (GET_MODE (x
))));
8206 return nonzero_bits (tem
, mode
) & nonzero
;
8208 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8210 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8212 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8213 /* We don't know anything about the upper bits. */
8214 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8215 return nonzero
& mask
;
8221 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8222 /* If X is negative in MODE, sign-extend the value. */
8223 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8224 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8225 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8231 #ifdef LOAD_EXTEND_OP
8232 /* In many, if not most, RISC machines, reading a byte from memory
8233 zeros the rest of the register. Noticing that fact saves a lot
8234 of extra zero-extends. */
8235 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8236 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8241 case UNEQ
: case LTGT
:
8242 case GT
: case GTU
: case UNGT
:
8243 case LT
: case LTU
: case UNLT
:
8244 case GE
: case GEU
: case UNGE
:
8245 case LE
: case LEU
: case UNLE
:
8246 case UNORDERED
: case ORDERED
:
8248 /* If this produces an integer result, we know which bits are set.
8249 Code here used to clear bits outside the mode of X, but that is
8252 if (GET_MODE_CLASS (mode
) == MODE_INT
8253 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8254 nonzero
= STORE_FLAG_VALUE
;
8259 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8260 and num_sign_bit_copies. */
8261 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8262 == GET_MODE_BITSIZE (GET_MODE (x
)))
8266 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8267 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8272 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8273 and num_sign_bit_copies. */
8274 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8275 == GET_MODE_BITSIZE (GET_MODE (x
)))
8281 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8285 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8286 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8287 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8291 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8292 Otherwise, show all the bits in the outer mode but not the inner
8294 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8295 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8297 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8299 & (((HOST_WIDE_INT
) 1
8300 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8301 inner_nz
|= (GET_MODE_MASK (mode
)
8302 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8305 nonzero
&= inner_nz
;
8309 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8310 & nonzero_bits (XEXP (x
, 1), mode
));
8314 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8316 unsigned HOST_WIDE_INT nonzero0
= nonzero_bits (XEXP (x
, 0), mode
);
8318 /* Don't call nonzero_bits for the second time if it cannot change
8320 if ((nonzero
& nonzero0
) != nonzero
)
8321 nonzero
&= (nonzero0
| nonzero_bits (XEXP (x
, 1), mode
));
8325 case PLUS
: case MINUS
:
8327 case DIV
: case UDIV
:
8328 case MOD
: case UMOD
:
8329 /* We can apply the rules of arithmetic to compute the number of
8330 high- and low-order zero bits of these operations. We start by
8331 computing the width (position of the highest-order nonzero bit)
8332 and the number of low-order zero bits for each value. */
8334 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8335 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8336 int width0
= floor_log2 (nz0
) + 1;
8337 int width1
= floor_log2 (nz1
) + 1;
8338 int low0
= floor_log2 (nz0
& -nz0
);
8339 int low1
= floor_log2 (nz1
& -nz1
);
8340 HOST_WIDE_INT op0_maybe_minusp
8341 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8342 HOST_WIDE_INT op1_maybe_minusp
8343 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8344 unsigned int result_width
= mode_width
;
8350 result_width
= MAX (width0
, width1
) + 1;
8351 result_low
= MIN (low0
, low1
);
8354 result_low
= MIN (low0
, low1
);
8357 result_width
= width0
+ width1
;
8358 result_low
= low0
+ low1
;
8363 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8364 result_width
= width0
;
8369 result_width
= width0
;
8374 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8375 result_width
= MIN (width0
, width1
);
8376 result_low
= MIN (low0
, low1
);
8381 result_width
= MIN (width0
, width1
);
8382 result_low
= MIN (low0
, low1
);
8388 if (result_width
< mode_width
)
8389 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8392 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8394 #ifdef POINTERS_EXTEND_UNSIGNED
8395 /* If pointers extend unsigned and this is an addition or subtraction
8396 to a pointer in Pmode, all the bits above ptr_mode are known to be
8398 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8399 && (code
== PLUS
|| code
== MINUS
)
8400 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8401 nonzero
&= GET_MODE_MASK (ptr_mode
);
8407 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8408 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8409 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8413 /* If this is a SUBREG formed for a promoted variable that has
8414 been zero-extended, we know that at least the high-order bits
8415 are zero, though others might be too. */
8417 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8418 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8419 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8421 /* If the inner mode is a single word for both the host and target
8422 machines, we can compute this from which bits of the inner
8423 object might be nonzero. */
8424 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8425 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8426 <= HOST_BITS_PER_WIDE_INT
))
8428 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8430 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8431 /* If this is a typical RISC machine, we only have to worry
8432 about the way loads are extended. */
8433 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8435 & (((unsigned HOST_WIDE_INT
) 1
8436 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8438 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8439 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8442 /* On many CISC machines, accessing an object in a wider mode
8443 causes the high-order bits to become undefined. So they are
8444 not known to be zero. */
8445 if (GET_MODE_SIZE (GET_MODE (x
))
8446 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8447 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8448 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8457 /* The nonzero bits are in two classes: any bits within MODE
8458 that aren't in GET_MODE (x) are always significant. The rest of the
8459 nonzero bits are those that are significant in the operand of
8460 the shift when shifted the appropriate number of bits. This
8461 shows that high-order bits are cleared by the right shift and
8462 low-order bits by left shifts. */
8463 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8464 && INTVAL (XEXP (x
, 1)) >= 0
8465 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8467 enum machine_mode inner_mode
= GET_MODE (x
);
8468 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8469 int count
= INTVAL (XEXP (x
, 1));
8470 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8471 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8472 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8473 unsigned HOST_WIDE_INT outer
= 0;
8475 if (mode_width
> width
)
8476 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8478 if (code
== LSHIFTRT
)
8480 else if (code
== ASHIFTRT
)
8484 /* If the sign bit may have been nonzero before the shift, we
8485 need to mark all the places it could have been copied to
8486 by the shift as possibly nonzero. */
8487 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8488 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8490 else if (code
== ASHIFT
)
8493 inner
= ((inner
<< (count
% width
)
8494 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8496 nonzero
&= (outer
| inner
);
8501 /* This is at most the number of bits in the mode. */
8502 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8506 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8507 | nonzero_bits (XEXP (x
, 2), mode
));
8517 /* See the macro definition above. */
8518 #undef num_sign_bit_copies
8520 /* Return the number of bits at the high-order end of X that are known to
8521 be equal to the sign bit. X will be used in mode MODE; if MODE is
8522 VOIDmode, X will be used in its own mode. The returned value will always
8523 be between 1 and the number of bits in MODE. */
8526 num_sign_bit_copies (x
, mode
)
8528 enum machine_mode mode
;
8530 enum rtx_code code
= GET_CODE (x
);
8531 unsigned int bitwidth
;
8532 int num0
, num1
, result
;
8533 unsigned HOST_WIDE_INT nonzero
;
8536 /* If we weren't given a mode, use the mode of X. If the mode is still
8537 VOIDmode, we don't know anything. Likewise if one of the modes is
8540 if (mode
== VOIDmode
)
8541 mode
= GET_MODE (x
);
8543 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8546 bitwidth
= GET_MODE_BITSIZE (mode
);
8548 /* For a smaller object, just ignore the high bits. */
8549 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8551 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8553 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8556 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8558 #ifndef WORD_REGISTER_OPERATIONS
8559 /* If this machine does not do all register operations on the entire
8560 register and MODE is wider than the mode of X, we can say nothing
8561 at all about the high-order bits. */
8564 /* Likewise on machines that do, if the mode of the object is smaller
8565 than a word and loads of that size don't sign extend, we can say
8566 nothing about the high order bits. */
8567 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8568 #ifdef LOAD_EXTEND_OP
8569 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8580 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8581 /* If pointers extend signed and this is a pointer in Pmode, say that
8582 all the bits above ptr_mode are known to be sign bit copies. */
8583 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8585 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8588 if (reg_last_set_value
[REGNO (x
)] != 0
8589 && reg_last_set_mode
[REGNO (x
)] == mode
8590 && (reg_last_set_label
[REGNO (x
)] == label_tick
8591 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8592 && REG_N_SETS (REGNO (x
)) == 1
8593 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8595 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8596 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8598 tem
= get_last_value (x
);
8600 return num_sign_bit_copies (tem
, mode
);
8602 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8603 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8604 return reg_sign_bit_copies
[REGNO (x
)];
8608 #ifdef LOAD_EXTEND_OP
8609 /* Some RISC machines sign-extend all loads of smaller than a word. */
8610 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8611 return MAX (1, ((int) bitwidth
8612 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8617 /* If the constant is negative, take its 1's complement and remask.
8618 Then see how many zero bits we have. */
8619 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8620 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8621 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8622 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8624 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8627 /* If this is a SUBREG for a promoted object that is sign-extended
8628 and we are looking at it in a wider mode, we know that at least the
8629 high-order bits are known to be sign bit copies. */
8631 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8633 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8634 return MAX ((int) bitwidth
8635 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8639 /* For a smaller object, just ignore the high bits. */
8640 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8642 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8643 return MAX (1, (num0
8644 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8648 #ifdef WORD_REGISTER_OPERATIONS
8649 #ifdef LOAD_EXTEND_OP
8650 /* For paradoxical SUBREGs on machines where all register operations
8651 affect the entire register, just look inside. Note that we are
8652 passing MODE to the recursive call, so the number of sign bit copies
8653 will remain relative to that mode, not the inner mode. */
8655 /* This works only if loads sign extend. Otherwise, if we get a
8656 reload for the inner part, it may be loaded from the stack, and
8657 then we lose all sign bit copies that existed before the store
8660 if ((GET_MODE_SIZE (GET_MODE (x
))
8661 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8662 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8663 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8664 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8670 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8671 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8675 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8676 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8679 /* For a smaller object, just ignore the high bits. */
8680 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8681 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8685 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8687 case ROTATE
: case ROTATERT
:
8688 /* If we are rotating left by a number of bits less than the number
8689 of sign bit copies, we can just subtract that amount from the
8691 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8692 && INTVAL (XEXP (x
, 1)) >= 0
8693 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8695 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8696 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8697 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8702 /* In general, this subtracts one sign bit copy. But if the value
8703 is known to be positive, the number of sign bit copies is the
8704 same as that of the input. Finally, if the input has just one bit
8705 that might be nonzero, all the bits are copies of the sign bit. */
8706 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8707 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8708 return num0
> 1 ? num0
- 1 : 1;
8710 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8715 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8720 case IOR
: case AND
: case XOR
:
8721 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8722 /* Logical operations will preserve the number of sign-bit copies.
8723 MIN and MAX operations always return one of the operands. */
8724 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8725 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8726 return MIN (num0
, num1
);
8728 case PLUS
: case MINUS
:
8729 /* For addition and subtraction, we can have a 1-bit carry. However,
8730 if we are subtracting 1 from a positive number, there will not
8731 be such a carry. Furthermore, if the positive number is known to
8732 be 0 or 1, we know the result is either -1 or 0. */
8734 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8735 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8737 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8738 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8739 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8740 : bitwidth
- floor_log2 (nonzero
) - 1);
8743 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8744 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8745 result
= MAX (1, MIN (num0
, num1
) - 1);
8747 #ifdef POINTERS_EXTEND_UNSIGNED
8748 /* If pointers extend signed and this is an addition or subtraction
8749 to a pointer in Pmode, all the bits above ptr_mode are known to be
8751 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8752 && (code
== PLUS
|| code
== MINUS
)
8753 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8754 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8755 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8761 /* The number of bits of the product is the sum of the number of
8762 bits of both terms. However, unless one of the terms if known
8763 to be positive, we must allow for an additional bit since negating
8764 a negative number can remove one sign bit copy. */
8766 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8767 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8769 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8771 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8772 || (((nonzero_bits (XEXP (x
, 0), mode
)
8773 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8774 && ((nonzero_bits (XEXP (x
, 1), mode
)
8775 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8778 return MAX (1, result
);
8781 /* The result must be <= the first operand. If the first operand
8782 has the high bit set, we know nothing about the number of sign
8784 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8786 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8787 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8790 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8793 /* The result must be <= the second operand. */
8794 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8797 /* Similar to unsigned division, except that we have to worry about
8798 the case where the divisor is negative, in which case we have
8800 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8802 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8803 || (nonzero_bits (XEXP (x
, 1), mode
)
8804 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8810 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8812 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8813 || (nonzero_bits (XEXP (x
, 1), mode
)
8814 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8820 /* Shifts by a constant add to the number of bits equal to the
8822 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8823 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8824 && INTVAL (XEXP (x
, 1)) > 0)
8825 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8830 /* Left shifts destroy copies. */
8831 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8832 || INTVAL (XEXP (x
, 1)) < 0
8833 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8836 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8837 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8840 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8841 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8842 return MIN (num0
, num1
);
8844 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8845 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8846 case GEU
: case GTU
: case LEU
: case LTU
:
8847 case UNORDERED
: case ORDERED
:
8848 /* If the constant is negative, take its 1's complement and remask.
8849 Then see how many zero bits we have. */
8850 nonzero
= STORE_FLAG_VALUE
;
8851 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8852 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8853 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8855 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8862 /* If we haven't been able to figure it out by one of the above rules,
8863 see if some of the high-order bits are known to be zero. If so,
8864 count those bits and return one less than that amount. If we can't
8865 safely compute the mask for this mode, always return BITWIDTH. */
8867 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8870 nonzero
= nonzero_bits (x
, mode
);
8871 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8872 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8875 /* Return the number of "extended" bits there are in X, when interpreted
8876 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8877 unsigned quantities, this is the number of high-order zero bits.
8878 For signed quantities, this is the number of copies of the sign bit
8879 minus 1. In both case, this function returns the number of "spare"
8880 bits. For example, if two quantities for which this function returns
8881 at least 1 are added, the addition is known not to overflow.
8883 This function will always return 0 unless called during combine, which
8884 implies that it must be called from a define_split. */
8887 extended_count (x
, mode
, unsignedp
)
8889 enum machine_mode mode
;
8892 if (nonzero_sign_valid
== 0)
8896 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8897 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8898 - floor_log2 (nonzero_bits (x
, mode
)))
8900 : num_sign_bit_copies (x
, mode
) - 1);
8903 /* This function is called from `simplify_shift_const' to merge two
8904 outer operations. Specifically, we have already found that we need
8905 to perform operation *POP0 with constant *PCONST0 at the outermost
8906 position. We would now like to also perform OP1 with constant CONST1
8907 (with *POP0 being done last).
8909 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8910 the resulting operation. *PCOMP_P is set to 1 if we would need to
8911 complement the innermost operand, otherwise it is unchanged.
8913 MODE is the mode in which the operation will be done. No bits outside
8914 the width of this mode matter. It is assumed that the width of this mode
8915 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8917 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8918 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8919 result is simply *PCONST0.
8921 If the resulting operation cannot be expressed as one operation, we
8922 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8925 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8926 enum rtx_code
*pop0
;
8927 HOST_WIDE_INT
*pconst0
;
8929 HOST_WIDE_INT const1
;
8930 enum machine_mode mode
;
8933 enum rtx_code op0
= *pop0
;
8934 HOST_WIDE_INT const0
= *pconst0
;
8936 const0
&= GET_MODE_MASK (mode
);
8937 const1
&= GET_MODE_MASK (mode
);
8939 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8943 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8946 if (op1
== NIL
|| op0
== SET
)
8949 else if (op0
== NIL
)
8950 op0
= op1
, const0
= const1
;
8952 else if (op0
== op1
)
8976 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8977 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8980 /* If the two constants aren't the same, we can't do anything. The
8981 remaining six cases can all be done. */
8982 else if (const0
!= const1
)
8990 /* (a & b) | b == b */
8992 else /* op1 == XOR */
8993 /* (a ^ b) | b == a | b */
8999 /* (a & b) ^ b == (~a) & b */
9000 op0
= AND
, *pcomp_p
= 1;
9001 else /* op1 == IOR */
9002 /* (a | b) ^ b == a & ~b */
9003 op0
= AND
, *pconst0
= ~const0
;
9008 /* (a | b) & b == b */
9010 else /* op1 == XOR */
9011 /* (a ^ b) & b) == (~a) & b */
9018 /* Check for NO-OP cases. */
9019 const0
&= GET_MODE_MASK (mode
);
9021 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9023 else if (const0
== 0 && op0
== AND
)
9025 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9029 /* ??? Slightly redundant with the above mask, but not entirely.
9030 Moving this above means we'd have to sign-extend the mode mask
9031 for the final test. */
9032 const0
= trunc_int_for_mode (const0
, mode
);
9040 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9041 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9042 that we started with.
9044 The shift is normally computed in the widest mode we find in VAROP, as
9045 long as it isn't a different number of words than RESULT_MODE. Exceptions
9046 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9049 simplify_shift_const (x
, code
, result_mode
, varop
, orig_count
)
9052 enum machine_mode result_mode
;
9056 enum rtx_code orig_code
= code
;
9059 enum machine_mode mode
= result_mode
;
9060 enum machine_mode shift_mode
, tmode
;
9061 unsigned int mode_words
9062 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9063 /* We form (outer_op (code varop count) (outer_const)). */
9064 enum rtx_code outer_op
= NIL
;
9065 HOST_WIDE_INT outer_const
= 0;
9067 int complement_p
= 0;
9070 /* Make sure and truncate the "natural" shift on the way in. We don't
9071 want to do this inside the loop as it makes it more difficult to
9073 #ifdef SHIFT_COUNT_TRUNCATED
9074 if (SHIFT_COUNT_TRUNCATED
)
9075 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9078 /* If we were given an invalid count, don't do anything except exactly
9079 what was requested. */
9081 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9086 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9091 /* Unless one of the branches of the `if' in this loop does a `continue',
9092 we will `break' the loop after the `if'. */
9096 /* If we have an operand of (clobber (const_int 0)), just return that
9098 if (GET_CODE (varop
) == CLOBBER
)
9101 /* If we discovered we had to complement VAROP, leave. Making a NOT
9102 here would cause an infinite loop. */
9106 /* Convert ROTATERT to ROTATE. */
9107 if (code
== ROTATERT
)
9109 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9111 if (VECTOR_MODE_P (result_mode
))
9112 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9114 count
= bitsize
- count
;
9117 /* We need to determine what mode we will do the shift in. If the
9118 shift is a right shift or a ROTATE, we must always do it in the mode
9119 it was originally done in. Otherwise, we can do it in MODE, the
9120 widest mode encountered. */
9122 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9123 ? result_mode
: mode
);
9125 /* Handle cases where the count is greater than the size of the mode
9126 minus 1. For ASHIFT, use the size minus one as the count (this can
9127 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9128 take the count modulo the size. For other shifts, the result is
9131 Since these shifts are being produced by the compiler by combining
9132 multiple operations, each of which are defined, we know what the
9133 result is supposed to be. */
9135 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9137 if (code
== ASHIFTRT
)
9138 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9139 else if (code
== ROTATE
|| code
== ROTATERT
)
9140 count
%= GET_MODE_BITSIZE (shift_mode
);
9143 /* We can't simply return zero because there may be an
9151 /* An arithmetic right shift of a quantity known to be -1 or 0
9153 if (code
== ASHIFTRT
9154 && (num_sign_bit_copies (varop
, shift_mode
)
9155 == GET_MODE_BITSIZE (shift_mode
)))
9161 /* If we are doing an arithmetic right shift and discarding all but
9162 the sign bit copies, this is equivalent to doing a shift by the
9163 bitsize minus one. Convert it into that shift because it will often
9164 allow other simplifications. */
9166 if (code
== ASHIFTRT
9167 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9168 >= GET_MODE_BITSIZE (shift_mode
)))
9169 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9171 /* We simplify the tests below and elsewhere by converting
9172 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9173 `make_compound_operation' will convert it to an ASHIFTRT for
9174 those machines (such as VAX) that don't have an LSHIFTRT. */
9175 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9177 && ((nonzero_bits (varop
, shift_mode
)
9178 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9182 switch (GET_CODE (varop
))
9188 new = expand_compound_operation (varop
);
9197 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9198 minus the width of a smaller mode, we can do this with a
9199 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9200 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9201 && ! mode_dependent_address_p (XEXP (varop
, 0))
9202 && ! MEM_VOLATILE_P (varop
)
9203 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9204 MODE_INT
, 1)) != BLKmode
)
9206 new = adjust_address_nv (varop
, tmode
,
9207 BYTES_BIG_ENDIAN
? 0
9208 : count
/ BITS_PER_UNIT
);
9210 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9211 : ZERO_EXTEND
, mode
, new);
9218 /* Similar to the case above, except that we can only do this if
9219 the resulting mode is the same as that of the underlying
9220 MEM and adjust the address depending on the *bits* endianness
9221 because of the way that bit-field extract insns are defined. */
9222 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9223 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9224 MODE_INT
, 1)) != BLKmode
9225 && tmode
== GET_MODE (XEXP (varop
, 0)))
9227 if (BITS_BIG_ENDIAN
)
9228 new = XEXP (varop
, 0);
9231 new = copy_rtx (XEXP (varop
, 0));
9232 SUBST (XEXP (new, 0),
9233 plus_constant (XEXP (new, 0),
9234 count
/ BITS_PER_UNIT
));
9237 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9238 : ZERO_EXTEND
, mode
, new);
9245 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9246 the same number of words as what we've seen so far. Then store
9247 the widest mode in MODE. */
9248 if (subreg_lowpart_p (varop
)
9249 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9250 > GET_MODE_SIZE (GET_MODE (varop
)))
9251 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9252 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9255 varop
= SUBREG_REG (varop
);
9256 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9257 mode
= GET_MODE (varop
);
9263 /* Some machines use MULT instead of ASHIFT because MULT
9264 is cheaper. But it is still better on those machines to
9265 merge two shifts into one. */
9266 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9267 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9270 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9271 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9277 /* Similar, for when divides are cheaper. */
9278 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9279 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9282 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9283 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9289 /* If we are extracting just the sign bit of an arithmetic
9290 right shift, that shift is not needed. However, the sign
9291 bit of a wider mode may be different from what would be
9292 interpreted as the sign bit in a narrower mode, so, if
9293 the result is narrower, don't discard the shift. */
9294 if (code
== LSHIFTRT
9295 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9296 && (GET_MODE_BITSIZE (result_mode
)
9297 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9299 varop
= XEXP (varop
, 0);
9303 /* ... fall through ... */
9308 /* Here we have two nested shifts. The result is usually the
9309 AND of a new shift with a mask. We compute the result below. */
9310 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9311 && INTVAL (XEXP (varop
, 1)) >= 0
9312 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9313 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9314 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9316 enum rtx_code first_code
= GET_CODE (varop
);
9317 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9318 unsigned HOST_WIDE_INT mask
;
9321 /* We have one common special case. We can't do any merging if
9322 the inner code is an ASHIFTRT of a smaller mode. However, if
9323 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9324 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9325 we can convert it to
9326 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9327 This simplifies certain SIGN_EXTEND operations. */
9328 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9329 && count
== (unsigned int)
9330 (GET_MODE_BITSIZE (result_mode
)
9331 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9333 /* C3 has the low-order C1 bits zero. */
9335 mask
= (GET_MODE_MASK (mode
)
9336 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9338 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9339 XEXP (varop
, 0), mask
);
9340 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9342 count
= first_count
;
9347 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9348 than C1 high-order bits equal to the sign bit, we can convert
9349 this to either an ASHIFT or an ASHIFTRT depending on the
9352 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9354 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9355 && GET_MODE (varop
) == shift_mode
9356 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9359 varop
= XEXP (varop
, 0);
9361 signed_count
= count
- first_count
;
9362 if (signed_count
< 0)
9363 count
= -signed_count
, code
= ASHIFT
;
9365 count
= signed_count
;
9370 /* There are some cases we can't do. If CODE is ASHIFTRT,
9371 we can only do this if FIRST_CODE is also ASHIFTRT.
9373 We can't do the case when CODE is ROTATE and FIRST_CODE is
9376 If the mode of this shift is not the mode of the outer shift,
9377 we can't do this if either shift is a right shift or ROTATE.
9379 Finally, we can't do any of these if the mode is too wide
9380 unless the codes are the same.
9382 Handle the case where the shift codes are the same
9385 if (code
== first_code
)
9387 if (GET_MODE (varop
) != result_mode
9388 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9392 count
+= first_count
;
9393 varop
= XEXP (varop
, 0);
9397 if (code
== ASHIFTRT
9398 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9399 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9400 || (GET_MODE (varop
) != result_mode
9401 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9402 || first_code
== ROTATE
9403 || code
== ROTATE
)))
9406 /* To compute the mask to apply after the shift, shift the
9407 nonzero bits of the inner shift the same way the
9408 outer shift will. */
9410 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9413 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9416 /* Give up if we can't compute an outer operation to use. */
9418 || GET_CODE (mask_rtx
) != CONST_INT
9419 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9421 result_mode
, &complement_p
))
9424 /* If the shifts are in the same direction, we add the
9425 counts. Otherwise, we subtract them. */
9426 signed_count
= count
;
9427 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9428 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9429 signed_count
+= first_count
;
9431 signed_count
-= first_count
;
9433 /* If COUNT is positive, the new shift is usually CODE,
9434 except for the two exceptions below, in which case it is
9435 FIRST_CODE. If the count is negative, FIRST_CODE should
9437 if (signed_count
> 0
9438 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9439 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9440 code
= first_code
, count
= signed_count
;
9441 else if (signed_count
< 0)
9442 code
= first_code
, count
= -signed_count
;
9444 count
= signed_count
;
9446 varop
= XEXP (varop
, 0);
9450 /* If we have (A << B << C) for any shift, we can convert this to
9451 (A << C << B). This wins if A is a constant. Only try this if
9452 B is not a constant. */
9454 else if (GET_CODE (varop
) == code
9455 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9457 = simplify_binary_operation (code
, mode
,
9461 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9468 /* Make this fit the case below. */
9469 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9470 GEN_INT (GET_MODE_MASK (mode
)));
9476 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9477 with C the size of VAROP - 1 and the shift is logical if
9478 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9479 we have an (le X 0) operation. If we have an arithmetic shift
9480 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9481 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9483 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9484 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9485 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9486 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9487 && count
== (unsigned int)
9488 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9489 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9492 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9495 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9496 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9501 /* If we have (shift (logical)), move the logical to the outside
9502 to allow it to possibly combine with another logical and the
9503 shift to combine with another shift. This also canonicalizes to
9504 what a ZERO_EXTRACT looks like. Also, some machines have
9505 (and (shift)) insns. */
9507 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9508 && (new = simplify_binary_operation (code
, result_mode
,
9510 GEN_INT (count
))) != 0
9511 && GET_CODE (new) == CONST_INT
9512 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9513 INTVAL (new), result_mode
, &complement_p
))
9515 varop
= XEXP (varop
, 0);
9519 /* If we can't do that, try to simplify the shift in each arm of the
9520 logical expression, make a new logical expression, and apply
9521 the inverse distributive law. */
9523 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9524 XEXP (varop
, 0), count
);
9525 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9526 XEXP (varop
, 1), count
);
9528 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9529 varop
= apply_distributive_law (varop
);
9536 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9537 says that the sign bit can be tested, FOO has mode MODE, C is
9538 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9539 that may be nonzero. */
9540 if (code
== LSHIFTRT
9541 && XEXP (varop
, 1) == const0_rtx
9542 && GET_MODE (XEXP (varop
, 0)) == result_mode
9543 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9544 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9545 && ((STORE_FLAG_VALUE
9546 & ((HOST_WIDE_INT
) 1
9547 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9548 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9549 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9550 (HOST_WIDE_INT
) 1, result_mode
,
9553 varop
= XEXP (varop
, 0);
9560 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9561 than the number of bits in the mode is equivalent to A. */
9562 if (code
== LSHIFTRT
9563 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9564 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9566 varop
= XEXP (varop
, 0);
9571 /* NEG commutes with ASHIFT since it is multiplication. Move the
9572 NEG outside to allow shifts to combine. */
9574 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9575 (HOST_WIDE_INT
) 0, result_mode
,
9578 varop
= XEXP (varop
, 0);
9584 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9585 is one less than the number of bits in the mode is
9586 equivalent to (xor A 1). */
9587 if (code
== LSHIFTRT
9588 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9589 && XEXP (varop
, 1) == constm1_rtx
9590 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9591 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9592 (HOST_WIDE_INT
) 1, result_mode
,
9596 varop
= XEXP (varop
, 0);
9600 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9601 that might be nonzero in BAR are those being shifted out and those
9602 bits are known zero in FOO, we can replace the PLUS with FOO.
9603 Similarly in the other operand order. This code occurs when
9604 we are computing the size of a variable-size array. */
9606 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9607 && count
< HOST_BITS_PER_WIDE_INT
9608 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9609 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9610 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9612 varop
= XEXP (varop
, 0);
9615 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9616 && count
< HOST_BITS_PER_WIDE_INT
9617 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9618 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9620 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9621 & nonzero_bits (XEXP (varop
, 1),
9624 varop
= XEXP (varop
, 1);
9628 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9630 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9631 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9633 GEN_INT (count
))) != 0
9634 && GET_CODE (new) == CONST_INT
9635 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9636 INTVAL (new), result_mode
, &complement_p
))
9638 varop
= XEXP (varop
, 0);
9644 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9645 with C the size of VAROP - 1 and the shift is logical if
9646 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9647 we have a (gt X 0) operation. If the shift is arithmetic with
9648 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9649 we have a (neg (gt X 0)) operation. */
9651 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9652 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9653 && count
== (unsigned int)
9654 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9655 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9656 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9657 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9659 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9662 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9665 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9666 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9673 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9674 if the truncate does not affect the value. */
9675 if (code
== LSHIFTRT
9676 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9677 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9678 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9679 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9680 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9682 rtx varop_inner
= XEXP (varop
, 0);
9685 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9686 XEXP (varop_inner
, 0),
9688 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9689 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9702 /* We need to determine what mode to do the shift in. If the shift is
9703 a right shift or ROTATE, we must always do it in the mode it was
9704 originally done in. Otherwise, we can do it in MODE, the widest mode
9705 encountered. The code we care about is that of the shift that will
9706 actually be done, not the shift that was originally requested. */
9708 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9709 ? result_mode
: mode
);
9711 /* We have now finished analyzing the shift. The result should be
9712 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9713 OUTER_OP is non-NIL, it is an operation that needs to be applied
9714 to the result of the shift. OUTER_CONST is the relevant constant,
9715 but we must turn off all bits turned off in the shift.
9717 If we were passed a value for X, see if we can use any pieces of
9718 it. If not, make new rtx. */
9720 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9721 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9722 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9723 const_rtx
= XEXP (x
, 1);
9725 const_rtx
= GEN_INT (count
);
9727 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9728 && GET_MODE (XEXP (x
, 0)) == shift_mode
9729 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9730 varop
= XEXP (x
, 0);
9731 else if (GET_MODE (varop
) != shift_mode
)
9732 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9734 /* If we can't make the SUBREG, try to return what we were given. */
9735 if (GET_CODE (varop
) == CLOBBER
)
9736 return x
? x
: varop
;
9738 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9742 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9744 /* If we have an outer operation and we just made a shift, it is
9745 possible that we could have simplified the shift were it not
9746 for the outer operation. So try to do the simplification
9749 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9750 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9751 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9752 INTVAL (XEXP (x
, 1)));
9754 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9755 turn off all the bits that the shift would have turned off. */
9756 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9757 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9758 GET_MODE_MASK (result_mode
) >> orig_count
);
9760 /* Do the remainder of the processing in RESULT_MODE. */
9761 x
= gen_lowpart_for_combine (result_mode
, x
);
9763 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9766 x
=simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9768 if (outer_op
!= NIL
)
9770 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9771 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9773 if (outer_op
== AND
)
9774 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9775 else if (outer_op
== SET
)
9776 /* This means that we have determined that the result is
9777 equivalent to a constant. This should be rare. */
9778 x
= GEN_INT (outer_const
);
9779 else if (GET_RTX_CLASS (outer_op
) == '1')
9780 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9782 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9788 /* Like recog, but we receive the address of a pointer to a new pattern.
9789 We try to match the rtx that the pointer points to.
9790 If that fails, we may try to modify or replace the pattern,
9791 storing the replacement into the same pointer object.
9793 Modifications include deletion or addition of CLOBBERs.
9795 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9796 the CLOBBERs are placed.
9798 The value is the final insn code from the pattern ultimately matched,
9802 recog_for_combine (pnewpat
, insn
, pnotes
)
9808 int insn_code_number
;
9809 int num_clobbers_to_add
= 0;
9814 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9815 we use to indicate that something didn't match. If we find such a
9816 thing, force rejection. */
9817 if (GET_CODE (pat
) == PARALLEL
)
9818 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9819 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9820 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9823 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9824 instruction for pattern recognition. */
9825 dummy_insn
= shallow_copy_rtx (insn
);
9826 PATTERN (dummy_insn
) = pat
;
9827 REG_NOTES (dummy_insn
) = 0;
9829 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9831 /* If it isn't, there is the possibility that we previously had an insn
9832 that clobbered some register as a side effect, but the combined
9833 insn doesn't need to do that. So try once more without the clobbers
9834 unless this represents an ASM insn. */
9836 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9837 && GET_CODE (pat
) == PARALLEL
)
9841 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9842 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9845 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9849 SUBST_INT (XVECLEN (pat
, 0), pos
);
9852 pat
= XVECEXP (pat
, 0, 0);
9854 PATTERN (dummy_insn
) = pat
;
9855 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9858 /* Recognize all noop sets, these will be killed by followup pass. */
9859 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9860 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9862 /* If we had any clobbers to add, make a new pattern than contains
9863 them. Then check to make sure that all of them are dead. */
9864 if (num_clobbers_to_add
)
9866 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9867 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9869 + num_clobbers_to_add
)
9870 : num_clobbers_to_add
+ 1));
9872 if (GET_CODE (pat
) == PARALLEL
)
9873 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9874 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9876 XVECEXP (newpat
, 0, 0) = pat
;
9878 add_clobbers (newpat
, insn_code_number
);
9880 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9881 i
< XVECLEN (newpat
, 0); i
++)
9883 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9884 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9886 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9887 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9895 return insn_code_number
;
9898 /* Like gen_lowpart but for use by combine. In combine it is not possible
9899 to create any new pseudoregs. However, it is safe to create
9900 invalid memory addresses, because combine will try to recognize
9901 them and all they will do is make the combine attempt fail.
9903 If for some reason this cannot do its job, an rtx
9904 (clobber (const_int 0)) is returned.
9905 An insn containing that will not be recognized. */
9910 gen_lowpart_for_combine (mode
, x
)
9911 enum machine_mode mode
;
9916 if (GET_MODE (x
) == mode
)
9919 /* We can only support MODE being wider than a word if X is a
9920 constant integer or has a mode the same size. */
9922 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9923 && ! ((GET_MODE (x
) == VOIDmode
9924 && (GET_CODE (x
) == CONST_INT
9925 || GET_CODE (x
) == CONST_DOUBLE
))
9926 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9927 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9929 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9930 won't know what to do. So we will strip off the SUBREG here and
9931 process normally. */
9932 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9935 if (GET_MODE (x
) == mode
)
9939 result
= gen_lowpart_common (mode
, x
);
9940 #ifdef CLASS_CANNOT_CHANGE_MODE
9942 && GET_CODE (result
) == SUBREG
9943 && GET_CODE (SUBREG_REG (result
)) == REG
9944 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9945 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9946 GET_MODE (SUBREG_REG (result
))))
9947 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9953 if (GET_CODE (x
) == MEM
)
9957 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9959 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9960 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9962 /* If we want to refer to something bigger than the original memref,
9963 generate a perverse subreg instead. That will force a reload
9964 of the original memref X. */
9965 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9966 return gen_rtx_SUBREG (mode
, x
, 0);
9968 if (WORDS_BIG_ENDIAN
)
9969 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9970 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9972 if (BYTES_BIG_ENDIAN
)
9974 /* Adjust the address so that the address-after-the-data is
9976 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9977 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9980 return adjust_address_nv (x
, mode
, offset
);
9983 /* If X is a comparison operator, rewrite it in a new mode. This
9984 probably won't match, but may allow further simplifications. */
9985 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9986 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9988 /* If we couldn't simplify X any other way, just enclose it in a
9989 SUBREG. Normally, this SUBREG won't match, but some patterns may
9990 include an explicit SUBREG or we may simplify it further in combine. */
9995 enum machine_mode sub_mode
= GET_MODE (x
);
9997 offset
= subreg_lowpart_offset (mode
, sub_mode
);
9998 if (sub_mode
== VOIDmode
)
10000 sub_mode
= int_mode_for_mode (mode
);
10001 x
= gen_lowpart_common (sub_mode
, x
);
10003 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10006 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10010 /* These routines make binary and unary operations by first seeing if they
10011 fold; if not, a new expression is allocated. */
10014 gen_binary (code
, mode
, op0
, op1
)
10015 enum rtx_code code
;
10016 enum machine_mode mode
;
10022 if (GET_RTX_CLASS (code
) == 'c'
10023 && swap_commutative_operands_p (op0
, op1
))
10024 tem
= op0
, op0
= op1
, op1
= tem
;
10026 if (GET_RTX_CLASS (code
) == '<')
10028 enum machine_mode op_mode
= GET_MODE (op0
);
10030 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10031 just (REL_OP X Y). */
10032 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10034 op1
= XEXP (op0
, 1);
10035 op0
= XEXP (op0
, 0);
10036 op_mode
= GET_MODE (op0
);
10039 if (op_mode
== VOIDmode
)
10040 op_mode
= GET_MODE (op1
);
10041 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10044 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10049 /* Put complex operands first and constants second. */
10050 if (GET_RTX_CLASS (code
) == 'c'
10051 && swap_commutative_operands_p (op0
, op1
))
10052 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10054 /* If we are turning off bits already known off in OP0, we need not do
10056 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10057 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10058 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10061 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10064 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10065 comparison code that will be tested.
10067 The result is a possibly different comparison code to use. *POP0 and
10068 *POP1 may be updated.
10070 It is possible that we might detect that a comparison is either always
10071 true or always false. However, we do not perform general constant
10072 folding in combine, so this knowledge isn't useful. Such tautologies
10073 should have been detected earlier. Hence we ignore all such cases. */
10075 static enum rtx_code
10076 simplify_comparison (code
, pop0
, pop1
)
10077 enum rtx_code code
;
10085 enum machine_mode mode
, tmode
;
10087 /* Try a few ways of applying the same transformation to both operands. */
10090 #ifndef WORD_REGISTER_OPERATIONS
10091 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10092 so check specially. */
10093 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10094 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10095 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10096 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10097 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10098 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10099 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10100 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10101 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10102 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
10103 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10104 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
10105 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
10106 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
10107 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
10108 && (INTVAL (XEXP (op0
, 1))
10109 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10110 - (GET_MODE_BITSIZE
10111 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10113 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10114 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10118 /* If both operands are the same constant shift, see if we can ignore the
10119 shift. We can if the shift is a rotate or if the bits shifted out of
10120 this shift are known to be zero for both inputs and if the type of
10121 comparison is compatible with the shift. */
10122 if (GET_CODE (op0
) == GET_CODE (op1
)
10123 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10124 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10125 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10126 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10127 || (GET_CODE (op0
) == ASHIFTRT
10128 && (code
!= GTU
&& code
!= LTU
10129 && code
!= GEU
&& code
!= LEU
)))
10130 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10131 && INTVAL (XEXP (op0
, 1)) >= 0
10132 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10133 && XEXP (op0
, 1) == XEXP (op1
, 1))
10135 enum machine_mode mode
= GET_MODE (op0
);
10136 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10137 int shift_count
= INTVAL (XEXP (op0
, 1));
10139 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10140 mask
&= (mask
>> shift_count
) << shift_count
;
10141 else if (GET_CODE (op0
) == ASHIFT
)
10142 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10144 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10145 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10146 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10151 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10152 SUBREGs are of the same mode, and, in both cases, the AND would
10153 be redundant if the comparison was done in the narrower mode,
10154 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10155 and the operand's possibly nonzero bits are 0xffffff01; in that case
10156 if we only care about QImode, we don't need the AND). This case
10157 occurs if the output mode of an scc insn is not SImode and
10158 STORE_FLAG_VALUE == 1 (e.g., the 386).
10160 Similarly, check for a case where the AND's are ZERO_EXTEND
10161 operations from some narrower mode even though a SUBREG is not
10164 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10165 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10166 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10168 rtx inner_op0
= XEXP (op0
, 0);
10169 rtx inner_op1
= XEXP (op1
, 0);
10170 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10171 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10174 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10175 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10176 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10177 && (GET_MODE (SUBREG_REG (inner_op0
))
10178 == GET_MODE (SUBREG_REG (inner_op1
)))
10179 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10180 <= HOST_BITS_PER_WIDE_INT
)
10181 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10182 GET_MODE (SUBREG_REG (inner_op0
)))))
10183 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10184 GET_MODE (SUBREG_REG (inner_op1
))))))
10186 op0
= SUBREG_REG (inner_op0
);
10187 op1
= SUBREG_REG (inner_op1
);
10189 /* The resulting comparison is always unsigned since we masked
10190 off the original sign bit. */
10191 code
= unsigned_condition (code
);
10197 for (tmode
= GET_CLASS_NARROWEST_MODE
10198 (GET_MODE_CLASS (GET_MODE (op0
)));
10199 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10200 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10202 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10203 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10204 code
= unsigned_condition (code
);
10213 /* If both operands are NOT, we can strip off the outer operation
10214 and adjust the comparison code for swapped operands; similarly for
10215 NEG, except that this must be an equality comparison. */
10216 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10217 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10218 && (code
== EQ
|| code
== NE
)))
10219 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10225 /* If the first operand is a constant, swap the operands and adjust the
10226 comparison code appropriately, but don't do this if the second operand
10227 is already a constant integer. */
10228 if (swap_commutative_operands_p (op0
, op1
))
10230 tem
= op0
, op0
= op1
, op1
= tem
;
10231 code
= swap_condition (code
);
10234 /* We now enter a loop during which we will try to simplify the comparison.
10235 For the most part, we only are concerned with comparisons with zero,
10236 but some things may really be comparisons with zero but not start
10237 out looking that way. */
10239 while (GET_CODE (op1
) == CONST_INT
)
10241 enum machine_mode mode
= GET_MODE (op0
);
10242 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10243 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10244 int equality_comparison_p
;
10245 int sign_bit_comparison_p
;
10246 int unsigned_comparison_p
;
10247 HOST_WIDE_INT const_op
;
10249 /* We only want to handle integral modes. This catches VOIDmode,
10250 CCmode, and the floating-point modes. An exception is that we
10251 can handle VOIDmode if OP0 is a COMPARE or a comparison
10254 if (GET_MODE_CLASS (mode
) != MODE_INT
10255 && ! (mode
== VOIDmode
10256 && (GET_CODE (op0
) == COMPARE
10257 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10260 /* Get the constant we are comparing against and turn off all bits
10261 not on in our mode. */
10262 const_op
= INTVAL (op1
);
10263 if (mode
!= VOIDmode
)
10264 const_op
= trunc_int_for_mode (const_op
, mode
);
10265 op1
= GEN_INT (const_op
);
10267 /* If we are comparing against a constant power of two and the value
10268 being compared can only have that single bit nonzero (e.g., it was
10269 `and'ed with that bit), we can replace this with a comparison
10272 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10273 || code
== LT
|| code
== LTU
)
10274 && mode_width
<= HOST_BITS_PER_WIDE_INT
10275 && exact_log2 (const_op
) >= 0
10276 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10278 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10279 op1
= const0_rtx
, const_op
= 0;
10282 /* Similarly, if we are comparing a value known to be either -1 or
10283 0 with -1, change it to the opposite comparison against zero. */
10286 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10287 || code
== GEU
|| code
== LTU
)
10288 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10290 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10291 op1
= const0_rtx
, const_op
= 0;
10294 /* Do some canonicalizations based on the comparison code. We prefer
10295 comparisons against zero and then prefer equality comparisons.
10296 If we can reduce the size of a constant, we will do that too. */
10301 /* < C is equivalent to <= (C - 1) */
10305 op1
= GEN_INT (const_op
);
10307 /* ... fall through to LE case below. */
10313 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10317 op1
= GEN_INT (const_op
);
10321 /* If we are doing a <= 0 comparison on a value known to have
10322 a zero sign bit, we can replace this with == 0. */
10323 else if (const_op
== 0
10324 && mode_width
<= HOST_BITS_PER_WIDE_INT
10325 && (nonzero_bits (op0
, mode
)
10326 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10331 /* >= C is equivalent to > (C - 1). */
10335 op1
= GEN_INT (const_op
);
10337 /* ... fall through to GT below. */
10343 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10347 op1
= GEN_INT (const_op
);
10351 /* If we are doing a > 0 comparison on a value known to have
10352 a zero sign bit, we can replace this with != 0. */
10353 else if (const_op
== 0
10354 && mode_width
<= HOST_BITS_PER_WIDE_INT
10355 && (nonzero_bits (op0
, mode
)
10356 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10361 /* < C is equivalent to <= (C - 1). */
10365 op1
= GEN_INT (const_op
);
10367 /* ... fall through ... */
10370 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10371 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10372 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10374 const_op
= 0, op1
= const0_rtx
;
10382 /* unsigned <= 0 is equivalent to == 0 */
10386 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10387 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10388 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10390 const_op
= 0, op1
= const0_rtx
;
10396 /* >= C is equivalent to < (C - 1). */
10400 op1
= GEN_INT (const_op
);
10402 /* ... fall through ... */
10405 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10406 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10407 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10409 const_op
= 0, op1
= const0_rtx
;
10417 /* unsigned > 0 is equivalent to != 0 */
10421 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10422 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10423 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10425 const_op
= 0, op1
= const0_rtx
;
10434 /* Compute some predicates to simplify code below. */
10436 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10437 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10438 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10441 /* If this is a sign bit comparison and we can do arithmetic in
10442 MODE, say that we will only be needing the sign bit of OP0. */
10443 if (sign_bit_comparison_p
10444 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10445 op0
= force_to_mode (op0
, mode
,
10447 << (GET_MODE_BITSIZE (mode
) - 1)),
10450 /* Now try cases based on the opcode of OP0. If none of the cases
10451 does a "continue", we exit this loop immediately after the
10454 switch (GET_CODE (op0
))
10457 /* If we are extracting a single bit from a variable position in
10458 a constant that has only a single bit set and are comparing it
10459 with zero, we can convert this into an equality comparison
10460 between the position and the location of the single bit. */
10462 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10463 && XEXP (op0
, 1) == const1_rtx
10464 && equality_comparison_p
&& const_op
== 0
10465 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10467 if (BITS_BIG_ENDIAN
)
10469 enum machine_mode new_mode
10470 = mode_for_extraction (EP_extzv
, 1);
10471 if (new_mode
== MAX_MACHINE_MODE
)
10472 i
= BITS_PER_WORD
- 1 - i
;
10476 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10480 op0
= XEXP (op0
, 2);
10484 /* Result is nonzero iff shift count is equal to I. */
10485 code
= reverse_condition (code
);
10489 /* ... fall through ... */
10492 tem
= expand_compound_operation (op0
);
10501 /* If testing for equality, we can take the NOT of the constant. */
10502 if (equality_comparison_p
10503 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10505 op0
= XEXP (op0
, 0);
10510 /* If just looking at the sign bit, reverse the sense of the
10512 if (sign_bit_comparison_p
)
10514 op0
= XEXP (op0
, 0);
10515 code
= (code
== GE
? LT
: GE
);
10521 /* If testing for equality, we can take the NEG of the constant. */
10522 if (equality_comparison_p
10523 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10525 op0
= XEXP (op0
, 0);
10530 /* The remaining cases only apply to comparisons with zero. */
10534 /* When X is ABS or is known positive,
10535 (neg X) is < 0 if and only if X != 0. */
10537 if (sign_bit_comparison_p
10538 && (GET_CODE (XEXP (op0
, 0)) == ABS
10539 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10540 && (nonzero_bits (XEXP (op0
, 0), mode
)
10541 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10543 op0
= XEXP (op0
, 0);
10544 code
= (code
== LT
? NE
: EQ
);
10548 /* If we have NEG of something whose two high-order bits are the
10549 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10550 if (num_sign_bit_copies (op0
, mode
) >= 2)
10552 op0
= XEXP (op0
, 0);
10553 code
= swap_condition (code
);
10559 /* If we are testing equality and our count is a constant, we
10560 can perform the inverse operation on our RHS. */
10561 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10562 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10563 op1
, XEXP (op0
, 1))) != 0)
10565 op0
= XEXP (op0
, 0);
10570 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10571 a particular bit. Convert it to an AND of a constant of that
10572 bit. This will be converted into a ZERO_EXTRACT. */
10573 if (const_op
== 0 && sign_bit_comparison_p
10574 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10575 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10577 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10580 - INTVAL (XEXP (op0
, 1)))));
10581 code
= (code
== LT
? NE
: EQ
);
10585 /* Fall through. */
10588 /* ABS is ignorable inside an equality comparison with zero. */
10589 if (const_op
== 0 && equality_comparison_p
)
10591 op0
= XEXP (op0
, 0);
10597 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10598 to (compare FOO CONST) if CONST fits in FOO's mode and we
10599 are either testing inequality or have an unsigned comparison
10600 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10601 if (! unsigned_comparison_p
10602 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10603 <= HOST_BITS_PER_WIDE_INT
)
10604 && ((unsigned HOST_WIDE_INT
) const_op
10605 < (((unsigned HOST_WIDE_INT
) 1
10606 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10608 op0
= XEXP (op0
, 0);
10614 /* Check for the case where we are comparing A - C1 with C2,
10615 both constants are smaller than 1/2 the maximum positive
10616 value in MODE, and the comparison is equality or unsigned.
10617 In that case, if A is either zero-extended to MODE or has
10618 sufficient sign bits so that the high-order bit in MODE
10619 is a copy of the sign in the inner mode, we can prove that it is
10620 safe to do the operation in the wider mode. This simplifies
10621 many range checks. */
10623 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10624 && subreg_lowpart_p (op0
)
10625 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10626 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10627 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10628 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10629 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10630 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10631 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10632 GET_MODE (SUBREG_REG (op0
)))
10633 & ~GET_MODE_MASK (mode
))
10634 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10635 GET_MODE (SUBREG_REG (op0
)))
10637 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10638 - GET_MODE_BITSIZE (mode
)))))
10640 op0
= SUBREG_REG (op0
);
10644 /* If the inner mode is narrower and we are extracting the low part,
10645 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10646 if (subreg_lowpart_p (op0
)
10647 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10648 /* Fall through */ ;
10652 /* ... fall through ... */
10655 if ((unsigned_comparison_p
|| equality_comparison_p
)
10656 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10657 <= HOST_BITS_PER_WIDE_INT
)
10658 && ((unsigned HOST_WIDE_INT
) const_op
10659 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10661 op0
= XEXP (op0
, 0);
10667 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10668 this for equality comparisons due to pathological cases involving
10670 if (equality_comparison_p
10671 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10672 op1
, XEXP (op0
, 1))))
10674 op0
= XEXP (op0
, 0);
10679 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10680 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10681 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10683 op0
= XEXP (XEXP (op0
, 0), 0);
10684 code
= (code
== LT
? EQ
: NE
);
10690 /* We used to optimize signed comparisons against zero, but that
10691 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10692 arrive here as equality comparisons, or (GEU, LTU) are
10693 optimized away. No need to special-case them. */
10695 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10696 (eq B (minus A C)), whichever simplifies. We can only do
10697 this for equality comparisons due to pathological cases involving
10699 if (equality_comparison_p
10700 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10701 XEXP (op0
, 1), op1
)))
10703 op0
= XEXP (op0
, 0);
10708 if (equality_comparison_p
10709 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10710 XEXP (op0
, 0), op1
)))
10712 op0
= XEXP (op0
, 1);
10717 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10718 of bits in X minus 1, is one iff X > 0. */
10719 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10720 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10721 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10723 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10725 op0
= XEXP (op0
, 1);
10726 code
= (code
== GE
? LE
: GT
);
10732 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10733 if C is zero or B is a constant. */
10734 if (equality_comparison_p
10735 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10736 XEXP (op0
, 1), op1
)))
10738 op0
= XEXP (op0
, 0);
10745 case UNEQ
: case LTGT
:
10746 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10747 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10748 case UNORDERED
: case ORDERED
:
10749 /* We can't do anything if OP0 is a condition code value, rather
10750 than an actual data value. */
10753 || XEXP (op0
, 0) == cc0_rtx
10755 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10758 /* Get the two operands being compared. */
10759 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10760 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10762 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10764 /* Check for the cases where we simply want the result of the
10765 earlier test or the opposite of that result. */
10766 if (code
== NE
|| code
== EQ
10767 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10768 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10769 && (STORE_FLAG_VALUE
10770 & (((HOST_WIDE_INT
) 1
10771 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10772 && (code
== LT
|| code
== GE
)))
10774 enum rtx_code new_code
;
10775 if (code
== LT
|| code
== NE
)
10776 new_code
= GET_CODE (op0
);
10778 new_code
= combine_reversed_comparison_code (op0
);
10780 if (new_code
!= UNKNOWN
)
10791 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10793 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10794 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10795 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10797 op0
= XEXP (op0
, 1);
10798 code
= (code
== GE
? GT
: LE
);
10804 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10805 will be converted to a ZERO_EXTRACT later. */
10806 if (const_op
== 0 && equality_comparison_p
10807 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10808 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10810 op0
= simplify_and_const_int
10811 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10813 XEXP (XEXP (op0
, 0), 1)),
10814 (HOST_WIDE_INT
) 1);
10818 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10819 zero and X is a comparison and C1 and C2 describe only bits set
10820 in STORE_FLAG_VALUE, we can compare with X. */
10821 if (const_op
== 0 && equality_comparison_p
10822 && mode_width
<= HOST_BITS_PER_WIDE_INT
10823 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10824 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10825 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10826 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10827 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10829 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10830 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10831 if ((~STORE_FLAG_VALUE
& mask
) == 0
10832 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10833 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10834 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10836 op0
= XEXP (XEXP (op0
, 0), 0);
10841 /* If we are doing an equality comparison of an AND of a bit equal
10842 to the sign bit, replace this with a LT or GE comparison of
10843 the underlying value. */
10844 if (equality_comparison_p
10846 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10847 && mode_width
<= HOST_BITS_PER_WIDE_INT
10848 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10849 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10851 op0
= XEXP (op0
, 0);
10852 code
= (code
== EQ
? GE
: LT
);
10856 /* If this AND operation is really a ZERO_EXTEND from a narrower
10857 mode, the constant fits within that mode, and this is either an
10858 equality or unsigned comparison, try to do this comparison in
10859 the narrower mode. */
10860 if ((equality_comparison_p
|| unsigned_comparison_p
)
10861 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10862 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10863 & GET_MODE_MASK (mode
))
10865 && const_op
>> i
== 0
10866 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10868 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10872 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10873 in both M1 and M2 and the SUBREG is either paradoxical or
10874 represents the low part, permute the SUBREG and the AND and
10876 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10878 #ifdef WORD_REGISTER_OPERATIONS
10880 > (GET_MODE_BITSIZE
10881 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10882 && mode_width
<= BITS_PER_WORD
)
10885 <= (GET_MODE_BITSIZE
10886 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10887 && subreg_lowpart_p (XEXP (op0
, 0))))
10888 #ifndef WORD_REGISTER_OPERATIONS
10889 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10890 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10891 As originally written the upper bits have a defined value
10892 due to the AND operation. However, if we commute the AND
10893 inside the SUBREG then they no longer have defined values
10894 and the meaning of the code has been changed. */
10895 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10896 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10898 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10899 && mode_width
<= HOST_BITS_PER_WIDE_INT
10900 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10901 <= HOST_BITS_PER_WIDE_INT
)
10902 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10903 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10904 & INTVAL (XEXP (op0
, 1)))
10905 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10906 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10907 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10911 = gen_lowpart_for_combine
10913 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10914 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10918 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10919 (eq (and (lshiftrt X) 1) 0). */
10920 if (const_op
== 0 && equality_comparison_p
10921 && XEXP (op0
, 1) == const1_rtx
10922 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10923 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10925 op0
= simplify_and_const_int
10927 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10928 XEXP (XEXP (op0
, 0), 1)),
10929 (HOST_WIDE_INT
) 1);
10930 code
= (code
== NE
? EQ
: NE
);
10936 /* If we have (compare (ashift FOO N) (const_int C)) and
10937 the high order N bits of FOO (N+1 if an inequality comparison)
10938 are known to be zero, we can do this by comparing FOO with C
10939 shifted right N bits so long as the low-order N bits of C are
10941 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10942 && INTVAL (XEXP (op0
, 1)) >= 0
10943 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10944 < HOST_BITS_PER_WIDE_INT
)
10946 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10947 && mode_width
<= HOST_BITS_PER_WIDE_INT
10948 && (nonzero_bits (XEXP (op0
, 0), mode
)
10949 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10950 + ! equality_comparison_p
))) == 0)
10952 /* We must perform a logical shift, not an arithmetic one,
10953 as we want the top N bits of C to be zero. */
10954 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10956 temp
>>= INTVAL (XEXP (op0
, 1));
10957 op1
= gen_int_mode (temp
, mode
);
10958 op0
= XEXP (op0
, 0);
10962 /* If we are doing a sign bit comparison, it means we are testing
10963 a particular bit. Convert it to the appropriate AND. */
10964 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10965 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10967 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10970 - INTVAL (XEXP (op0
, 1)))));
10971 code
= (code
== LT
? NE
: EQ
);
10975 /* If this an equality comparison with zero and we are shifting
10976 the low bit to the sign bit, we can convert this to an AND of the
10978 if (const_op
== 0 && equality_comparison_p
10979 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10980 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10983 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10984 (HOST_WIDE_INT
) 1);
10990 /* If this is an equality comparison with zero, we can do this
10991 as a logical shift, which might be much simpler. */
10992 if (equality_comparison_p
&& const_op
== 0
10993 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10995 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10997 INTVAL (XEXP (op0
, 1)));
11001 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11002 do the comparison in a narrower mode. */
11003 if (! unsigned_comparison_p
11004 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11005 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11006 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11007 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11008 MODE_INT
, 1)) != BLKmode
11009 && (((unsigned HOST_WIDE_INT
) const_op
11010 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11011 <= GET_MODE_MASK (tmode
)))
11013 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11017 /* Likewise if OP0 is a PLUS of a sign extension with a
11018 constant, which is usually represented with the PLUS
11019 between the shifts. */
11020 if (! unsigned_comparison_p
11021 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11022 && GET_CODE (XEXP (op0
, 0)) == PLUS
11023 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11024 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11025 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11026 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11027 MODE_INT
, 1)) != BLKmode
11028 && (((unsigned HOST_WIDE_INT
) const_op
11029 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11030 <= GET_MODE_MASK (tmode
)))
11032 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11033 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11034 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11037 op0
= gen_binary (PLUS
, tmode
,
11038 gen_lowpart_for_combine (tmode
, inner
),
11043 /* ... fall through ... */
11045 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11046 the low order N bits of FOO are known to be zero, we can do this
11047 by comparing FOO with C shifted left N bits so long as no
11048 overflow occurs. */
11049 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11050 && INTVAL (XEXP (op0
, 1)) >= 0
11051 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11052 && mode_width
<= HOST_BITS_PER_WIDE_INT
11053 && (nonzero_bits (XEXP (op0
, 0), mode
)
11054 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11055 && (((unsigned HOST_WIDE_INT
) const_op
11056 + (GET_CODE (op0
) != LSHIFTRT
11057 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11060 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11062 /* If the shift was logical, then we must make the condition
11064 if (GET_CODE (op0
) == LSHIFTRT
)
11065 code
= unsigned_condition (code
);
11067 const_op
<<= INTVAL (XEXP (op0
, 1));
11068 op1
= GEN_INT (const_op
);
11069 op0
= XEXP (op0
, 0);
11073 /* If we are using this shift to extract just the sign bit, we
11074 can replace this with an LT or GE comparison. */
11076 && (equality_comparison_p
|| sign_bit_comparison_p
)
11077 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11078 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11081 op0
= XEXP (op0
, 0);
11082 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11094 /* Now make any compound operations involved in this comparison. Then,
11095 check for an outmost SUBREG on OP0 that is not doing anything or is
11096 paradoxical. The latter transformation must only be performed when
11097 it is known that the "extra" bits will be the same in op0 and op1 or
11098 that they don't matter. There are three cases to consider:
11100 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11101 care bits and we can assume they have any convenient value. So
11102 making the transformation is safe.
11104 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11105 In this case the upper bits of op0 are undefined. We should not make
11106 the simplification in that case as we do not know the contents of
11109 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11110 NIL. In that case we know those bits are zeros or ones. We must
11111 also be sure that they are the same as the upper bits of op1.
11113 We can never remove a SUBREG for a non-equality comparison because
11114 the sign bit is in a different place in the underlying object. */
11116 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11117 op1
= make_compound_operation (op1
, SET
);
11119 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11120 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11122 && GET_CODE (SUBREG_REG (op0
)) == REG
11123 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11124 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11125 && (code
== NE
|| code
== EQ
))
11127 if (GET_MODE_SIZE (GET_MODE (op0
))
11128 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11130 op0
= SUBREG_REG (op0
);
11131 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11133 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11134 <= HOST_BITS_PER_WIDE_INT
)
11135 && (nonzero_bits (SUBREG_REG (op0
),
11136 GET_MODE (SUBREG_REG (op0
)))
11137 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11139 tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)), op1
);
11141 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11142 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11143 op0
= SUBREG_REG (op0
), op1
= tem
;
11147 /* We now do the opposite procedure: Some machines don't have compare
11148 insns in all modes. If OP0's mode is an integer mode smaller than a
11149 word and we can't do a compare in that mode, see if there is a larger
11150 mode for which we can do the compare. There are a number of cases in
11151 which we can use the wider mode. */
11153 mode
= GET_MODE (op0
);
11154 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11155 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11156 && ! have_insn_for (COMPARE
, mode
))
11157 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11159 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11160 tmode
= GET_MODE_WIDER_MODE (tmode
))
11161 if (have_insn_for (COMPARE
, tmode
))
11165 /* If the only nonzero bits in OP0 and OP1 are those in the
11166 narrower mode and this is an equality or unsigned comparison,
11167 we can use the wider mode. Similarly for sign-extended
11168 values, in which case it is true for all comparisons. */
11169 zero_extended
= ((code
== EQ
|| code
== NE
11170 || code
== GEU
|| code
== GTU
11171 || code
== LEU
|| code
== LTU
)
11172 && (nonzero_bits (op0
, tmode
)
11173 & ~GET_MODE_MASK (mode
)) == 0
11174 && ((GET_CODE (op1
) == CONST_INT
11175 || (nonzero_bits (op1
, tmode
)
11176 & ~GET_MODE_MASK (mode
)) == 0)));
11179 || ((num_sign_bit_copies (op0
, tmode
)
11180 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11181 - GET_MODE_BITSIZE (mode
)))
11182 && (num_sign_bit_copies (op1
, tmode
)
11183 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11184 - GET_MODE_BITSIZE (mode
)))))
11186 /* If OP0 is an AND and we don't have an AND in MODE either,
11187 make a new AND in the proper mode. */
11188 if (GET_CODE (op0
) == AND
11189 && !have_insn_for (AND
, mode
))
11190 op0
= gen_binary (AND
, tmode
,
11191 gen_lowpart_for_combine (tmode
,
11193 gen_lowpart_for_combine (tmode
,
11196 op0
= gen_lowpart_for_combine (tmode
, op0
);
11197 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11198 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11199 op1
= gen_lowpart_for_combine (tmode
, op1
);
11203 /* If this is a test for negative, we can make an explicit
11204 test of the sign bit. */
11206 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11207 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11209 op0
= gen_binary (AND
, tmode
,
11210 gen_lowpart_for_combine (tmode
, op0
),
11211 GEN_INT ((HOST_WIDE_INT
) 1
11212 << (GET_MODE_BITSIZE (mode
) - 1)));
11213 code
= (code
== LT
) ? NE
: EQ
;
11218 #ifdef CANONICALIZE_COMPARISON
11219 /* If this machine only supports a subset of valid comparisons, see if we
11220 can convert an unsupported one into a supported one. */
11221 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11230 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11231 searching backward. */
11232 static enum rtx_code
11233 combine_reversed_comparison_code (exp
)
11236 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11239 if (code1
!= UNKNOWN
11240 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11242 /* Otherwise try and find where the condition codes were last set and
11244 x
= get_last_value (XEXP (exp
, 0));
11245 if (!x
|| GET_CODE (x
) != COMPARE
)
11247 return reversed_comparison_code_parts (GET_CODE (exp
),
11248 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11250 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11251 Return NULL_RTX in case we fail to do the reversal. */
11253 reversed_comparison (exp
, mode
, op0
, op1
)
11255 enum machine_mode mode
;
11257 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11258 if (reversed_code
== UNKNOWN
)
11261 return gen_binary (reversed_code
, mode
, op0
, op1
);
11264 /* Utility function for following routine. Called when X is part of a value
11265 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11266 for each register mentioned. Similar to mention_regs in cse.c */
11269 update_table_tick (x
)
11272 enum rtx_code code
= GET_CODE (x
);
11273 const char *fmt
= GET_RTX_FORMAT (code
);
11278 unsigned int regno
= REGNO (x
);
11279 unsigned int endregno
11280 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11281 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11284 for (r
= regno
; r
< endregno
; r
++)
11285 reg_last_set_table_tick
[r
] = label_tick
;
11290 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11291 /* Note that we can't have an "E" in values stored; see
11292 get_last_value_validate. */
11294 update_table_tick (XEXP (x
, i
));
11297 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11298 are saying that the register is clobbered and we no longer know its
11299 value. If INSN is zero, don't update reg_last_set; this is only permitted
11300 with VALUE also zero and is used to invalidate the register. */
11303 record_value_for_reg (reg
, insn
, value
)
11308 unsigned int regno
= REGNO (reg
);
11309 unsigned int endregno
11310 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11311 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11314 /* If VALUE contains REG and we have a previous value for REG, substitute
11315 the previous value. */
11316 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11320 /* Set things up so get_last_value is allowed to see anything set up to
11322 subst_low_cuid
= INSN_CUID (insn
);
11323 tem
= get_last_value (reg
);
11325 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11326 it isn't going to be useful and will take a lot of time to process,
11327 so just use the CLOBBER. */
11331 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11332 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11333 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11334 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11335 tem
= XEXP (tem
, 0);
11337 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11341 /* For each register modified, show we don't know its value, that
11342 we don't know about its bitwise content, that its value has been
11343 updated, and that we don't know the location of the death of the
11345 for (i
= regno
; i
< endregno
; i
++)
11348 reg_last_set
[i
] = insn
;
11350 reg_last_set_value
[i
] = 0;
11351 reg_last_set_mode
[i
] = 0;
11352 reg_last_set_nonzero_bits
[i
] = 0;
11353 reg_last_set_sign_bit_copies
[i
] = 0;
11354 reg_last_death
[i
] = 0;
11357 /* Mark registers that are being referenced in this value. */
11359 update_table_tick (value
);
11361 /* Now update the status of each register being set.
11362 If someone is using this register in this block, set this register
11363 to invalid since we will get confused between the two lives in this
11364 basic block. This makes using this register always invalid. In cse, we
11365 scan the table to invalidate all entries using this register, but this
11366 is too much work for us. */
11368 for (i
= regno
; i
< endregno
; i
++)
11370 reg_last_set_label
[i
] = label_tick
;
11371 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11372 reg_last_set_invalid
[i
] = 1;
11374 reg_last_set_invalid
[i
] = 0;
11377 /* The value being assigned might refer to X (like in "x++;"). In that
11378 case, we must replace it with (clobber (const_int 0)) to prevent
11380 if (value
&& ! get_last_value_validate (&value
, insn
,
11381 reg_last_set_label
[regno
], 0))
11383 value
= copy_rtx (value
);
11384 if (! get_last_value_validate (&value
, insn
,
11385 reg_last_set_label
[regno
], 1))
11389 /* For the main register being modified, update the value, the mode, the
11390 nonzero bits, and the number of sign bit copies. */
11392 reg_last_set_value
[regno
] = value
;
11396 enum machine_mode mode
= GET_MODE (reg
);
11397 subst_low_cuid
= INSN_CUID (insn
);
11398 reg_last_set_mode
[regno
] = mode
;
11399 if (GET_MODE_CLASS (mode
) == MODE_INT
11400 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11401 mode
= nonzero_bits_mode
;
11402 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11403 reg_last_set_sign_bit_copies
[regno
]
11404 = num_sign_bit_copies (value
, GET_MODE (reg
));
11408 /* Called via note_stores from record_dead_and_set_regs to handle one
11409 SET or CLOBBER in an insn. DATA is the instruction in which the
11410 set is occurring. */
11413 record_dead_and_set_regs_1 (dest
, setter
, data
)
11417 rtx record_dead_insn
= (rtx
) data
;
11419 if (GET_CODE (dest
) == SUBREG
)
11420 dest
= SUBREG_REG (dest
);
11422 if (GET_CODE (dest
) == REG
)
11424 /* If we are setting the whole register, we know its value. Otherwise
11425 show that we don't know the value. We can handle SUBREG in
11427 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11428 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11429 else if (GET_CODE (setter
) == SET
11430 && GET_CODE (SET_DEST (setter
)) == SUBREG
11431 && SUBREG_REG (SET_DEST (setter
)) == dest
11432 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11433 && subreg_lowpart_p (SET_DEST (setter
)))
11434 record_value_for_reg (dest
, record_dead_insn
,
11435 gen_lowpart_for_combine (GET_MODE (dest
),
11436 SET_SRC (setter
)));
11438 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11440 else if (GET_CODE (dest
) == MEM
11441 /* Ignore pushes, they clobber nothing. */
11442 && ! push_operand (dest
, GET_MODE (dest
)))
11443 mem_last_set
= INSN_CUID (record_dead_insn
);
11446 /* Update the records of when each REG was most recently set or killed
11447 for the things done by INSN. This is the last thing done in processing
11448 INSN in the combiner loop.
11450 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11451 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11452 and also the similar information mem_last_set (which insn most recently
11453 modified memory) and last_call_cuid (which insn was the most recent
11454 subroutine call). */
11457 record_dead_and_set_regs (insn
)
11463 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11465 if (REG_NOTE_KIND (link
) == REG_DEAD
11466 && GET_CODE (XEXP (link
, 0)) == REG
)
11468 unsigned int regno
= REGNO (XEXP (link
, 0));
11469 unsigned int endregno
11470 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11471 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11474 for (i
= regno
; i
< endregno
; i
++)
11475 reg_last_death
[i
] = insn
;
11477 else if (REG_NOTE_KIND (link
) == REG_INC
)
11478 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11481 if (GET_CODE (insn
) == CALL_INSN
)
11483 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11484 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11486 reg_last_set_value
[i
] = 0;
11487 reg_last_set_mode
[i
] = 0;
11488 reg_last_set_nonzero_bits
[i
] = 0;
11489 reg_last_set_sign_bit_copies
[i
] = 0;
11490 reg_last_death
[i
] = 0;
11493 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11495 /* Don't bother recording what this insn does. It might set the
11496 return value register, but we can't combine into a call
11497 pattern anyway, so there's no point trying (and it may cause
11498 a crash, if e.g. we wind up asking for last_set_value of a
11499 SUBREG of the return value register). */
11503 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11506 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11507 register present in the SUBREG, so for each such SUBREG go back and
11508 adjust nonzero and sign bit information of the registers that are
11509 known to have some zero/sign bits set.
11511 This is needed because when combine blows the SUBREGs away, the
11512 information on zero/sign bits is lost and further combines can be
11513 missed because of that. */
11516 record_promoted_value (insn
, subreg
)
11521 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11522 enum machine_mode mode
= GET_MODE (subreg
);
11524 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11527 for (links
= LOG_LINKS (insn
); links
;)
11529 insn
= XEXP (links
, 0);
11530 set
= single_set (insn
);
11532 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11533 || REGNO (SET_DEST (set
)) != regno
11534 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11536 links
= XEXP (links
, 1);
11540 if (reg_last_set
[regno
] == insn
)
11542 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11543 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11546 if (GET_CODE (SET_SRC (set
)) == REG
)
11548 regno
= REGNO (SET_SRC (set
));
11549 links
= LOG_LINKS (insn
);
11556 /* Scan X for promoted SUBREGs. For each one found,
11557 note what it implies to the registers used in it. */
11560 check_promoted_subreg (insn
, x
)
11564 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11565 && GET_CODE (SUBREG_REG (x
)) == REG
)
11566 record_promoted_value (insn
, x
);
11569 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11572 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11576 check_promoted_subreg (insn
, XEXP (x
, i
));
11580 if (XVEC (x
, i
) != 0)
11581 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11582 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11588 /* Utility routine for the following function. Verify that all the registers
11589 mentioned in *LOC are valid when *LOC was part of a value set when
11590 label_tick == TICK. Return 0 if some are not.
11592 If REPLACE is nonzero, replace the invalid reference with
11593 (clobber (const_int 0)) and return 1. This replacement is useful because
11594 we often can get useful information about the form of a value (e.g., if
11595 it was produced by a shift that always produces -1 or 0) even though
11596 we don't know exactly what registers it was produced from. */
11599 get_last_value_validate (loc
, insn
, tick
, replace
)
11606 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11607 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11610 if (GET_CODE (x
) == REG
)
11612 unsigned int regno
= REGNO (x
);
11613 unsigned int endregno
11614 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11615 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11618 for (j
= regno
; j
< endregno
; j
++)
11619 if (reg_last_set_invalid
[j
]
11620 /* If this is a pseudo-register that was only set once and not
11621 live at the beginning of the function, it is always valid. */
11622 || (! (regno
>= FIRST_PSEUDO_REGISTER
11623 && REG_N_SETS (regno
) == 1
11624 && (! REGNO_REG_SET_P
11625 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11626 && reg_last_set_label
[j
] > tick
))
11629 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11635 /* If this is a memory reference, make sure that there were
11636 no stores after it that might have clobbered the value. We don't
11637 have alias info, so we assume any store invalidates it. */
11638 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11639 && INSN_CUID (insn
) <= mem_last_set
)
11642 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11646 for (i
= 0; i
< len
; i
++)
11648 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11649 /* Don't bother with these. They shouldn't occur anyway. */
11653 /* If we haven't found a reason for it to be invalid, it is valid. */
11657 /* Get the last value assigned to X, if known. Some registers
11658 in the value may be replaced with (clobber (const_int 0)) if their value
11659 is known longer known reliably. */
11665 unsigned int regno
;
11668 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11669 then convert it to the desired mode. If this is a paradoxical SUBREG,
11670 we cannot predict what values the "extra" bits might have. */
11671 if (GET_CODE (x
) == SUBREG
11672 && subreg_lowpart_p (x
)
11673 && (GET_MODE_SIZE (GET_MODE (x
))
11674 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11675 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11676 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11678 if (GET_CODE (x
) != REG
)
11682 value
= reg_last_set_value
[regno
];
11684 /* If we don't have a value, or if it isn't for this basic block and
11685 it's either a hard register, set more than once, or it's a live
11686 at the beginning of the function, return 0.
11688 Because if it's not live at the beginning of the function then the reg
11689 is always set before being used (is never used without being set).
11690 And, if it's set only once, and it's always set before use, then all
11691 uses must have the same last value, even if it's not from this basic
11695 || (reg_last_set_label
[regno
] != label_tick
11696 && (regno
< FIRST_PSEUDO_REGISTER
11697 || REG_N_SETS (regno
) != 1
11698 || (REGNO_REG_SET_P
11699 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11702 /* If the value was set in a later insn than the ones we are processing,
11703 we can't use it even if the register was only set once. */
11704 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11707 /* If the value has all its registers valid, return it. */
11708 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11709 reg_last_set_label
[regno
], 0))
11712 /* Otherwise, make a copy and replace any invalid register with
11713 (clobber (const_int 0)). If that fails for some reason, return 0. */
11715 value
= copy_rtx (value
);
11716 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11717 reg_last_set_label
[regno
], 1))
11723 /* Return nonzero if expression X refers to a REG or to memory
11724 that is set in an instruction more recent than FROM_CUID. */
11727 use_crosses_set_p (x
, from_cuid
)
11733 enum rtx_code code
= GET_CODE (x
);
11737 unsigned int regno
= REGNO (x
);
11738 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11739 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11741 #ifdef PUSH_ROUNDING
11742 /* Don't allow uses of the stack pointer to be moved,
11743 because we don't know whether the move crosses a push insn. */
11744 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11747 for (; regno
< endreg
; regno
++)
11748 if (reg_last_set
[regno
]
11749 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11754 if (code
== MEM
&& mem_last_set
> from_cuid
)
11757 fmt
= GET_RTX_FORMAT (code
);
11759 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11764 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11765 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11768 else if (fmt
[i
] == 'e'
11769 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11775 /* Define three variables used for communication between the following
11778 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11779 static int reg_dead_flag
;
11781 /* Function called via note_stores from reg_dead_at_p.
11783 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11784 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11787 reg_dead_at_p_1 (dest
, x
, data
)
11790 void *data ATTRIBUTE_UNUSED
;
11792 unsigned int regno
, endregno
;
11794 if (GET_CODE (dest
) != REG
)
11797 regno
= REGNO (dest
);
11798 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11799 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11801 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11802 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11805 /* Return nonzero if REG is known to be dead at INSN.
11807 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11808 referencing REG, it is dead. If we hit a SET referencing REG, it is
11809 live. Otherwise, see if it is live or dead at the start of the basic
11810 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11811 must be assumed to be always live. */
11814 reg_dead_at_p (reg
, insn
)
11821 /* Set variables for reg_dead_at_p_1. */
11822 reg_dead_regno
= REGNO (reg
);
11823 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11824 ? HARD_REGNO_NREGS (reg_dead_regno
,
11830 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11831 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11833 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11834 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11838 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11839 beginning of function. */
11840 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11841 insn
= prev_nonnote_insn (insn
))
11843 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11845 return reg_dead_flag
== 1 ? 1 : 0;
11847 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11851 /* Get the basic block that we were in. */
11853 block
= ENTRY_BLOCK_PTR
->next_bb
;
11856 FOR_EACH_BB (block
)
11857 if (insn
== block
->head
)
11860 if (block
== EXIT_BLOCK_PTR
)
11864 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11865 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11871 /* Note hard registers in X that are used. This code is similar to
11872 that in flow.c, but much simpler since we don't care about pseudos. */
11875 mark_used_regs_combine (x
)
11878 RTX_CODE code
= GET_CODE (x
);
11879 unsigned int regno
;
11892 case ADDR_DIFF_VEC
:
11895 /* CC0 must die in the insn after it is set, so we don't need to take
11896 special note of it here. */
11902 /* If we are clobbering a MEM, mark any hard registers inside the
11903 address as used. */
11904 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11905 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11910 /* A hard reg in a wide mode may really be multiple registers.
11911 If so, mark all of them just like the first. */
11912 if (regno
< FIRST_PSEUDO_REGISTER
)
11914 unsigned int endregno
, r
;
11916 /* None of this applies to the stack, frame or arg pointers. */
11917 if (regno
== STACK_POINTER_REGNUM
11918 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11919 || regno
== HARD_FRAME_POINTER_REGNUM
11921 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11922 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11924 || regno
== FRAME_POINTER_REGNUM
)
11927 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11928 for (r
= regno
; r
< endregno
; r
++)
11929 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11935 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11937 rtx testreg
= SET_DEST (x
);
11939 while (GET_CODE (testreg
) == SUBREG
11940 || GET_CODE (testreg
) == ZERO_EXTRACT
11941 || GET_CODE (testreg
) == SIGN_EXTRACT
11942 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11943 testreg
= XEXP (testreg
, 0);
11945 if (GET_CODE (testreg
) == MEM
)
11946 mark_used_regs_combine (XEXP (testreg
, 0));
11948 mark_used_regs_combine (SET_SRC (x
));
11956 /* Recursively scan the operands of this expression. */
11959 const char *fmt
= GET_RTX_FORMAT (code
);
11961 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11964 mark_used_regs_combine (XEXP (x
, i
));
11965 else if (fmt
[i
] == 'E')
11969 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11970 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11976 /* Remove register number REGNO from the dead registers list of INSN.
11978 Return the note used to record the death, if there was one. */
11981 remove_death (regno
, insn
)
11982 unsigned int regno
;
11985 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11989 REG_N_DEATHS (regno
)--;
11990 remove_note (insn
, note
);
11996 /* For each register (hardware or pseudo) used within expression X, if its
11997 death is in an instruction with cuid between FROM_CUID (inclusive) and
11998 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11999 list headed by PNOTES.
12001 That said, don't move registers killed by maybe_kill_insn.
12003 This is done when X is being merged by combination into TO_INSN. These
12004 notes will then be distributed as needed. */
12007 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
12009 rtx maybe_kill_insn
;
12016 enum rtx_code code
= GET_CODE (x
);
12020 unsigned int regno
= REGNO (x
);
12021 rtx where_dead
= reg_last_death
[regno
];
12022 rtx before_dead
, after_dead
;
12024 /* Don't move the register if it gets killed in between from and to. */
12025 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12026 && ! reg_referenced_p (x
, maybe_kill_insn
))
12029 /* WHERE_DEAD could be a USE insn made by combine, so first we
12030 make sure that we have insns with valid INSN_CUID values. */
12031 before_dead
= where_dead
;
12032 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12033 before_dead
= PREV_INSN (before_dead
);
12035 after_dead
= where_dead
;
12036 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12037 after_dead
= NEXT_INSN (after_dead
);
12039 if (before_dead
&& after_dead
12040 && INSN_CUID (before_dead
) >= from_cuid
12041 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12042 || (where_dead
!= after_dead
12043 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12045 rtx note
= remove_death (regno
, where_dead
);
12047 /* It is possible for the call above to return 0. This can occur
12048 when reg_last_death points to I2 or I1 that we combined with.
12049 In that case make a new note.
12051 We must also check for the case where X is a hard register
12052 and NOTE is a death note for a range of hard registers
12053 including X. In that case, we must put REG_DEAD notes for
12054 the remaining registers in place of NOTE. */
12056 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12057 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12058 > GET_MODE_SIZE (GET_MODE (x
))))
12060 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12061 unsigned int deadend
12062 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12063 GET_MODE (XEXP (note
, 0))));
12064 unsigned int ourend
12065 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12068 for (i
= deadregno
; i
< deadend
; i
++)
12069 if (i
< regno
|| i
>= ourend
)
12070 REG_NOTES (where_dead
)
12071 = gen_rtx_EXPR_LIST (REG_DEAD
,
12073 REG_NOTES (where_dead
));
12076 /* If we didn't find any note, or if we found a REG_DEAD note that
12077 covers only part of the given reg, and we have a multi-reg hard
12078 register, then to be safe we must check for REG_DEAD notes
12079 for each register other than the first. They could have
12080 their own REG_DEAD notes lying around. */
12081 else if ((note
== 0
12083 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12084 < GET_MODE_SIZE (GET_MODE (x
)))))
12085 && regno
< FIRST_PSEUDO_REGISTER
12086 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12088 unsigned int ourend
12089 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12090 unsigned int i
, offset
;
12094 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12098 for (i
= regno
+ offset
; i
< ourend
; i
++)
12099 move_deaths (regno_reg_rtx
[i
],
12100 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12103 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12105 XEXP (note
, 1) = *pnotes
;
12109 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12111 REG_N_DEATHS (regno
)++;
12117 else if (GET_CODE (x
) == SET
)
12119 rtx dest
= SET_DEST (x
);
12121 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12123 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12124 that accesses one word of a multi-word item, some
12125 piece of everything register in the expression is used by
12126 this insn, so remove any old death. */
12127 /* ??? So why do we test for equality of the sizes? */
12129 if (GET_CODE (dest
) == ZERO_EXTRACT
12130 || GET_CODE (dest
) == STRICT_LOW_PART
12131 || (GET_CODE (dest
) == SUBREG
12132 && (((GET_MODE_SIZE (GET_MODE (dest
))
12133 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12134 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12135 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12137 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12141 /* If this is some other SUBREG, we know it replaces the entire
12142 value, so use that as the destination. */
12143 if (GET_CODE (dest
) == SUBREG
)
12144 dest
= SUBREG_REG (dest
);
12146 /* If this is a MEM, adjust deaths of anything used in the address.
12147 For a REG (the only other possibility), the entire value is
12148 being replaced so the old value is not used in this insn. */
12150 if (GET_CODE (dest
) == MEM
)
12151 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12156 else if (GET_CODE (x
) == CLOBBER
)
12159 len
= GET_RTX_LENGTH (code
);
12160 fmt
= GET_RTX_FORMAT (code
);
12162 for (i
= 0; i
< len
; i
++)
12167 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12168 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12171 else if (fmt
[i
] == 'e')
12172 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12176 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12177 pattern of an insn. X must be a REG. */
12180 reg_bitfield_target_p (x
, body
)
12186 if (GET_CODE (body
) == SET
)
12188 rtx dest
= SET_DEST (body
);
12190 unsigned int regno
, tregno
, endregno
, endtregno
;
12192 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12193 target
= XEXP (dest
, 0);
12194 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12195 target
= SUBREG_REG (XEXP (dest
, 0));
12199 if (GET_CODE (target
) == SUBREG
)
12200 target
= SUBREG_REG (target
);
12202 if (GET_CODE (target
) != REG
)
12205 tregno
= REGNO (target
), regno
= REGNO (x
);
12206 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12207 return target
== x
;
12209 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12210 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12212 return endregno
> tregno
&& regno
< endtregno
;
12215 else if (GET_CODE (body
) == PARALLEL
)
12216 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12217 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12223 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12224 as appropriate. I3 and I2 are the insns resulting from the combination
12225 insns including FROM (I2 may be zero).
12227 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12228 not need REG_DEAD notes because they are being substituted for. This
12229 saves searching in the most common cases.
12231 Each note in the list is either ignored or placed on some insns, depending
12232 on the type of note. */
12235 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
12239 rtx elim_i2
, elim_i1
;
12241 rtx note
, next_note
;
12244 for (note
= notes
; note
; note
= next_note
)
12246 rtx place
= 0, place2
= 0;
12248 /* If this NOTE references a pseudo register, ensure it references
12249 the latest copy of that register. */
12250 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12251 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12252 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12254 next_note
= XEXP (note
, 1);
12255 switch (REG_NOTE_KIND (note
))
12259 case REG_EXEC_COUNT
:
12260 /* Doesn't matter much where we put this, as long as it's somewhere.
12261 It is preferable to keep these notes on branches, which is most
12262 likely to be i3. */
12266 case REG_VTABLE_REF
:
12267 /* ??? Should remain with *a particular* memory load. Given the
12268 nature of vtable data, the last insn seems relatively safe. */
12272 case REG_NON_LOCAL_GOTO
:
12273 if (GET_CODE (i3
) == JUMP_INSN
)
12275 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12281 case REG_EH_REGION
:
12282 /* These notes must remain with the call or trapping instruction. */
12283 if (GET_CODE (i3
) == CALL_INSN
)
12285 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12287 else if (flag_non_call_exceptions
)
12289 if (may_trap_p (i3
))
12291 else if (i2
&& may_trap_p (i2
))
12293 /* ??? Otherwise assume we've combined things such that we
12294 can now prove that the instructions can't trap. Drop the
12295 note in this case. */
12303 /* These notes must remain with the call. It should not be
12304 possible for both I2 and I3 to be a call. */
12305 if (GET_CODE (i3
) == CALL_INSN
)
12307 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12314 /* Any clobbers for i3 may still exist, and so we must process
12315 REG_UNUSED notes from that insn.
12317 Any clobbers from i2 or i1 can only exist if they were added by
12318 recog_for_combine. In that case, recog_for_combine created the
12319 necessary REG_UNUSED notes. Trying to keep any original
12320 REG_UNUSED notes from these insns can cause incorrect output
12321 if it is for the same register as the original i3 dest.
12322 In that case, we will notice that the register is set in i3,
12323 and then add a REG_UNUSED note for the destination of i3, which
12324 is wrong. However, it is possible to have REG_UNUSED notes from
12325 i2 or i1 for register which were both used and clobbered, so
12326 we keep notes from i2 or i1 if they will turn into REG_DEAD
12329 /* If this register is set or clobbered in I3, put the note there
12330 unless there is one already. */
12331 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12333 if (from_insn
!= i3
)
12336 if (! (GET_CODE (XEXP (note
, 0)) == REG
12337 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12338 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12341 /* Otherwise, if this register is used by I3, then this register
12342 now dies here, so we must put a REG_DEAD note here unless there
12344 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12345 && ! (GET_CODE (XEXP (note
, 0)) == REG
12346 ? find_regno_note (i3
, REG_DEAD
,
12347 REGNO (XEXP (note
, 0)))
12348 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12350 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12358 /* These notes say something about results of an insn. We can
12359 only support them if they used to be on I3 in which case they
12360 remain on I3. Otherwise they are ignored.
12362 If the note refers to an expression that is not a constant, we
12363 must also ignore the note since we cannot tell whether the
12364 equivalence is still true. It might be possible to do
12365 slightly better than this (we only have a problem if I2DEST
12366 or I1DEST is present in the expression), but it doesn't
12367 seem worth the trouble. */
12369 if (from_insn
== i3
12370 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12375 case REG_NO_CONFLICT
:
12376 /* These notes say something about how a register is used. They must
12377 be present on any use of the register in I2 or I3. */
12378 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12381 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12391 /* This can show up in several ways -- either directly in the
12392 pattern, or hidden off in the constant pool with (or without?)
12393 a REG_EQUAL note. */
12394 /* ??? Ignore the without-reg_equal-note problem for now. */
12395 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12396 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12397 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12398 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12402 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12403 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12404 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12405 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12413 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12414 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12415 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12417 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12419 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12420 LABEL_NUSES (JUMP_LABEL (place
))--;
12423 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12425 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12427 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12428 LABEL_NUSES (JUMP_LABEL (place2
))--;
12435 /* These notes say something about the value of a register prior
12436 to the execution of an insn. It is too much trouble to see
12437 if the note is still correct in all situations. It is better
12438 to simply delete it. */
12442 /* If the insn previously containing this note still exists,
12443 put it back where it was. Otherwise move it to the previous
12444 insn. Adjust the corresponding REG_LIBCALL note. */
12445 if (GET_CODE (from_insn
) != NOTE
)
12449 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12450 place
= prev_real_insn (from_insn
);
12452 XEXP (tem
, 0) = place
;
12453 /* If we're deleting the last remaining instruction of a
12454 libcall sequence, don't add the notes. */
12455 else if (XEXP (note
, 0) == from_insn
)
12461 /* This is handled similarly to REG_RETVAL. */
12462 if (GET_CODE (from_insn
) != NOTE
)
12466 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12467 place
= next_real_insn (from_insn
);
12469 XEXP (tem
, 0) = place
;
12470 /* If we're deleting the last remaining instruction of a
12471 libcall sequence, don't add the notes. */
12472 else if (XEXP (note
, 0) == from_insn
)
12478 /* If the register is used as an input in I3, it dies there.
12479 Similarly for I2, if it is nonzero and adjacent to I3.
12481 If the register is not used as an input in either I3 or I2
12482 and it is not one of the registers we were supposed to eliminate,
12483 there are two possibilities. We might have a non-adjacent I2
12484 or we might have somehow eliminated an additional register
12485 from a computation. For example, we might have had A & B where
12486 we discover that B will always be zero. In this case we will
12487 eliminate the reference to A.
12489 In both cases, we must search to see if we can find a previous
12490 use of A and put the death note there. */
12493 && GET_CODE (from_insn
) == CALL_INSN
12494 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12496 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12498 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12499 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12502 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12503 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12508 basic_block bb
= this_basic_block
;
12510 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12512 if (! INSN_P (tem
))
12514 if (tem
== bb
->head
)
12519 /* If the register is being set at TEM, see if that is all
12520 TEM is doing. If so, delete TEM. Otherwise, make this
12521 into a REG_UNUSED note instead. */
12522 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12524 rtx set
= single_set (tem
);
12525 rtx inner_dest
= 0;
12527 rtx cc0_setter
= NULL_RTX
;
12531 for (inner_dest
= SET_DEST (set
);
12532 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12533 || GET_CODE (inner_dest
) == SUBREG
12534 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12535 inner_dest
= XEXP (inner_dest
, 0))
12538 /* Verify that it was the set, and not a clobber that
12539 modified the register.
12541 CC0 targets must be careful to maintain setter/user
12542 pairs. If we cannot delete the setter due to side
12543 effects, mark the user with an UNUSED note instead
12546 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12547 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12549 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12550 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12551 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12555 /* Move the notes and links of TEM elsewhere.
12556 This might delete other dead insns recursively.
12557 First set the pattern to something that won't use
12560 PATTERN (tem
) = pc_rtx
;
12562 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12563 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12564 distribute_links (LOG_LINKS (tem
));
12566 PUT_CODE (tem
, NOTE
);
12567 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12568 NOTE_SOURCE_FILE (tem
) = 0;
12571 /* Delete the setter too. */
12574 PATTERN (cc0_setter
) = pc_rtx
;
12576 distribute_notes (REG_NOTES (cc0_setter
),
12577 cc0_setter
, cc0_setter
,
12578 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12579 distribute_links (LOG_LINKS (cc0_setter
));
12581 PUT_CODE (cc0_setter
, NOTE
);
12582 NOTE_LINE_NUMBER (cc0_setter
)
12583 = NOTE_INSN_DELETED
;
12584 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12588 /* If the register is both set and used here, put the
12589 REG_DEAD note here, but place a REG_UNUSED note
12590 here too unless there already is one. */
12591 else if (reg_referenced_p (XEXP (note
, 0),
12596 if (! find_regno_note (tem
, REG_UNUSED
,
12597 REGNO (XEXP (note
, 0))))
12599 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12604 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12606 /* If there isn't already a REG_UNUSED note, put one
12608 if (! find_regno_note (tem
, REG_UNUSED
,
12609 REGNO (XEXP (note
, 0))))
12614 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12615 || (GET_CODE (tem
) == CALL_INSN
12616 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12620 /* If we are doing a 3->2 combination, and we have a
12621 register which formerly died in i3 and was not used
12622 by i2, which now no longer dies in i3 and is used in
12623 i2 but does not die in i2, and place is between i2
12624 and i3, then we may need to move a link from place to
12626 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12627 && INSN_CUID (place
) > INSN_CUID (i2
)
12629 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12630 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12632 rtx links
= LOG_LINKS (place
);
12633 LOG_LINKS (place
) = 0;
12634 distribute_links (links
);
12639 if (tem
== bb
->head
)
12643 /* We haven't found an insn for the death note and it
12644 is still a REG_DEAD note, but we have hit the beginning
12645 of the block. If the existing life info says the reg
12646 was dead, there's nothing left to do. Otherwise, we'll
12647 need to do a global life update after combine. */
12648 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12649 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12650 REGNO (XEXP (note
, 0))))
12652 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12657 /* If the register is set or already dead at PLACE, we needn't do
12658 anything with this note if it is still a REG_DEAD note.
12659 We can here if it is set at all, not if is it totally replace,
12660 which is what `dead_or_set_p' checks, so also check for it being
12663 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12665 unsigned int regno
= REGNO (XEXP (note
, 0));
12667 /* Similarly, if the instruction on which we want to place
12668 the note is a noop, we'll need do a global live update
12669 after we remove them in delete_noop_moves. */
12670 if (noop_move_p (place
))
12672 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12676 if (dead_or_set_p (place
, XEXP (note
, 0))
12677 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12679 /* Unless the register previously died in PLACE, clear
12680 reg_last_death. [I no longer understand why this is
12682 if (reg_last_death
[regno
] != place
)
12683 reg_last_death
[regno
] = 0;
12687 reg_last_death
[regno
] = place
;
12689 /* If this is a death note for a hard reg that is occupying
12690 multiple registers, ensure that we are still using all
12691 parts of the object. If we find a piece of the object
12692 that is unused, we must arrange for an appropriate REG_DEAD
12693 note to be added for it. However, we can't just emit a USE
12694 and tag the note to it, since the register might actually
12695 be dead; so we recourse, and the recursive call then finds
12696 the previous insn that used this register. */
12698 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12699 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12701 unsigned int endregno
12702 = regno
+ HARD_REGNO_NREGS (regno
,
12703 GET_MODE (XEXP (note
, 0)));
12707 for (i
= regno
; i
< endregno
; i
++)
12708 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12709 && ! find_regno_fusage (place
, USE
, i
))
12710 || dead_or_set_regno_p (place
, i
))
12715 /* Put only REG_DEAD notes for pieces that are
12716 not already dead or set. */
12718 for (i
= regno
; i
< endregno
;
12719 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12721 rtx piece
= regno_reg_rtx
[i
];
12722 basic_block bb
= this_basic_block
;
12724 if (! dead_or_set_p (place
, piece
)
12725 && ! reg_bitfield_target_p (piece
,
12729 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12731 distribute_notes (new_note
, place
, place
,
12732 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12734 else if (! refers_to_regno_p (i
, i
+ 1,
12735 PATTERN (place
), 0)
12736 && ! find_regno_fusage (place
, USE
, i
))
12737 for (tem
= PREV_INSN (place
); ;
12738 tem
= PREV_INSN (tem
))
12740 if (! INSN_P (tem
))
12742 if (tem
== bb
->head
)
12744 SET_BIT (refresh_blocks
,
12745 this_basic_block
->index
);
12751 if (dead_or_set_p (tem
, piece
)
12752 || reg_bitfield_target_p (piece
,
12756 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12771 /* Any other notes should not be present at this point in the
12778 XEXP (note
, 1) = REG_NOTES (place
);
12779 REG_NOTES (place
) = note
;
12781 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12782 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12783 && GET_CODE (XEXP (note
, 0)) == REG
)
12784 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12788 if ((REG_NOTE_KIND (note
) == REG_DEAD
12789 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12790 && GET_CODE (XEXP (note
, 0)) == REG
)
12791 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12793 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12794 REG_NOTE_KIND (note
),
12796 REG_NOTES (place2
));
12801 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12802 I3, I2, and I1 to new locations. This is also called in one case to
12803 add a link pointing at I3 when I3's destination is changed. */
12806 distribute_links (links
)
12809 rtx link
, next_link
;
12811 for (link
= links
; link
; link
= next_link
)
12817 next_link
= XEXP (link
, 1);
12819 /* If the insn that this link points to is a NOTE or isn't a single
12820 set, ignore it. In the latter case, it isn't clear what we
12821 can do other than ignore the link, since we can't tell which
12822 register it was for. Such links wouldn't be used by combine
12825 It is not possible for the destination of the target of the link to
12826 have been changed by combine. The only potential of this is if we
12827 replace I3, I2, and I1 by I3 and I2. But in that case the
12828 destination of I2 also remains unchanged. */
12830 if (GET_CODE (XEXP (link
, 0)) == NOTE
12831 || (set
= single_set (XEXP (link
, 0))) == 0)
12834 reg
= SET_DEST (set
);
12835 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12836 || GET_CODE (reg
) == SIGN_EXTRACT
12837 || GET_CODE (reg
) == STRICT_LOW_PART
)
12838 reg
= XEXP (reg
, 0);
12840 /* A LOG_LINK is defined as being placed on the first insn that uses
12841 a register and points to the insn that sets the register. Start
12842 searching at the next insn after the target of the link and stop
12843 when we reach a set of the register or the end of the basic block.
12845 Note that this correctly handles the link that used to point from
12846 I3 to I2. Also note that not much searching is typically done here
12847 since most links don't point very far away. */
12849 for (insn
= NEXT_INSN (XEXP (link
, 0));
12850 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12851 || this_basic_block
->next_bb
->head
!= insn
));
12852 insn
= NEXT_INSN (insn
))
12853 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12855 if (reg_referenced_p (reg
, PATTERN (insn
)))
12859 else if (GET_CODE (insn
) == CALL_INSN
12860 && find_reg_fusage (insn
, USE
, reg
))
12866 /* If we found a place to put the link, place it there unless there
12867 is already a link to the same insn as LINK at that point. */
12873 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12874 if (XEXP (link2
, 0) == XEXP (link
, 0))
12879 XEXP (link
, 1) = LOG_LINKS (place
);
12880 LOG_LINKS (place
) = link
;
12882 /* Set added_links_insn to the earliest insn we added a
12884 if (added_links_insn
== 0
12885 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12886 added_links_insn
= place
;
12892 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12898 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12899 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12900 insn
= NEXT_INSN (insn
);
12902 if (INSN_UID (insn
) > max_uid_cuid
)
12905 return INSN_CUID (insn
);
12909 dump_combine_stats (file
)
12914 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12915 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12919 dump_combine_total_stats (file
)
12924 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12925 total_attempts
, total_merges
, total_extras
, total_successes
);