1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
84 #include "stor-layout.h"
88 #include "hard-reg-set.h"
96 #include "dominance.h"
99 #include "cfgcleanup.h"
100 #include "basic-block.h"
101 #include "insn-config.h"
102 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
104 #include "insn-attr.h"
106 #include "diagnostic-core.h"
108 #include "insn-codes.h"
110 #include "rtlhooks-def.h"
112 #include "tree-pass.h"
114 #include "valtrack.h"
115 #include "hash-map.h"
117 #include "plugin-api.h"
121 #include "statistics.h"
123 #include "rtl-iter.h"
125 /* Number of attempts to combine instructions in this function. */
127 static int combine_attempts
;
129 /* Number of attempts that got as far as substitution in this function. */
131 static int combine_merges
;
133 /* Number of instructions combined with added SETs in this function. */
135 static int combine_extras
;
137 /* Number of instructions combined in this function. */
139 static int combine_successes
;
141 /* Totals over entire compilation. */
143 static int total_attempts
, total_merges
, total_extras
, total_successes
;
145 /* combine_instructions may try to replace the right hand side of the
146 second instruction with the value of an associated REG_EQUAL note
147 before throwing it at try_combine. That is problematic when there
148 is a REG_DEAD note for a register used in the old right hand side
149 and can cause distribute_notes to do wrong things. This is the
150 second instruction if it has been so modified, null otherwise. */
152 static rtx_insn
*i2mod
;
154 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
156 static rtx i2mod_old_rhs
;
158 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
160 static rtx i2mod_new_rhs
;
162 typedef struct reg_stat_struct
{
163 /* Record last point of death of (hard or pseudo) register n. */
164 rtx_insn
*last_death
;
166 /* Record last point of modification of (hard or pseudo) register n. */
169 /* The next group of fields allows the recording of the last value assigned
170 to (hard or pseudo) register n. We use this information to see if an
171 operation being processed is redundant given a prior operation performed
172 on the register. For example, an `and' with a constant is redundant if
173 all the zero bits are already known to be turned off.
175 We use an approach similar to that used by cse, but change it in the
178 (1) We do not want to reinitialize at each label.
179 (2) It is useful, but not critical, to know the actual value assigned
180 to a register. Often just its form is helpful.
182 Therefore, we maintain the following fields:
184 last_set_value the last value assigned
185 last_set_label records the value of label_tick when the
186 register was assigned
187 last_set_table_tick records the value of label_tick when a
188 value using the register is assigned
189 last_set_invalid set to nonzero when it is not valid
190 to use the value of this register in some
193 To understand the usage of these tables, it is important to understand
194 the distinction between the value in last_set_value being valid and
195 the register being validly contained in some other expression in the
198 (The next two parameters are out of date).
200 reg_stat[i].last_set_value is valid if it is nonzero, and either
201 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
203 Register I may validly appear in any expression returned for the value
204 of another register if reg_n_sets[i] is 1. It may also appear in the
205 value for register J if reg_stat[j].last_set_invalid is zero, or
206 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
208 If an expression is found in the table containing a register which may
209 not validly appear in an expression, the register is replaced by
210 something that won't match, (clobber (const_int 0)). */
212 /* Record last value assigned to (hard or pseudo) register n. */
216 /* Record the value of label_tick when an expression involving register n
217 is placed in last_set_value. */
219 int last_set_table_tick
;
221 /* Record the value of label_tick when the value for register n is placed in
226 /* These fields are maintained in parallel with last_set_value and are
227 used to store the mode in which the register was last set, the bits
228 that were known to be zero when it was last set, and the number of
229 sign bits copies it was known to have when it was last set. */
231 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
232 char last_set_sign_bit_copies
;
233 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
235 /* Set nonzero if references to register n in expressions should not be
236 used. last_set_invalid is set nonzero when this register is being
237 assigned to and last_set_table_tick == label_tick. */
239 char last_set_invalid
;
241 /* Some registers that are set more than once and used in more than one
242 basic block are nevertheless always set in similar ways. For example,
243 a QImode register may be loaded from memory in two places on a machine
244 where byte loads zero extend.
246 We record in the following fields if a register has some leading bits
247 that are always equal to the sign bit, and what we know about the
248 nonzero bits of a register, specifically which bits are known to be
251 If an entry is zero, it means that we don't know anything special. */
253 unsigned char sign_bit_copies
;
255 unsigned HOST_WIDE_INT nonzero_bits
;
257 /* Record the value of the label_tick when the last truncation
258 happened. The field truncated_to_mode is only valid if
259 truncation_label == label_tick. */
261 int truncation_label
;
263 /* Record the last truncation seen for this register. If truncation
264 is not a nop to this mode we might be able to save an explicit
265 truncation if we know that value already contains a truncated
268 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
272 static vec
<reg_stat_type
> reg_stat
;
274 /* Record the luid of the last insn that invalidated memory
275 (anything that writes memory, and subroutine calls, but not pushes). */
277 static int mem_last_set
;
279 /* Record the luid of the last CALL_INSN
280 so we can tell whether a potential combination crosses any calls. */
282 static int last_call_luid
;
284 /* When `subst' is called, this is the insn that is being modified
285 (by combining in a previous insn). The PATTERN of this insn
286 is still the old pattern partially modified and it should not be
287 looked at, but this may be used to examine the successors of the insn
288 to judge whether a simplification is valid. */
290 static rtx_insn
*subst_insn
;
292 /* This is the lowest LUID that `subst' is currently dealing with.
293 get_last_value will not return a value if the register was set at or
294 after this LUID. If not for this mechanism, we could get confused if
295 I2 or I1 in try_combine were an insn that used the old value of a register
296 to obtain a new value. In that case, we might erroneously get the
297 new value of the register when we wanted the old one. */
299 static int subst_low_luid
;
301 /* This contains any hard registers that are used in newpat; reg_dead_at_p
302 must consider all these registers to be always live. */
304 static HARD_REG_SET newpat_used_regs
;
306 /* This is an insn to which a LOG_LINKS entry has been added. If this
307 insn is the earlier than I2 or I3, combine should rescan starting at
310 static rtx_insn
*added_links_insn
;
312 /* Basic block in which we are performing combines. */
313 static basic_block this_basic_block
;
314 static bool optimize_this_for_speed_p
;
317 /* Length of the currently allocated uid_insn_cost array. */
319 static int max_uid_known
;
321 /* The following array records the insn_rtx_cost for every insn
322 in the instruction stream. */
324 static int *uid_insn_cost
;
326 /* The following array records the LOG_LINKS for every insn in the
327 instruction stream as struct insn_link pointers. */
331 struct insn_link
*next
;
334 static struct insn_link
**uid_log_links
;
336 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
337 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
339 #define FOR_EACH_LOG_LINK(L, INSN) \
340 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
342 /* Links for LOG_LINKS are allocated from this obstack. */
344 static struct obstack insn_link_obstack
;
346 /* Allocate a link. */
348 static inline struct insn_link
*
349 alloc_insn_link (rtx_insn
*insn
, struct insn_link
*next
)
352 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
353 sizeof (struct insn_link
));
359 /* Incremented for each basic block. */
361 static int label_tick
;
363 /* Reset to label_tick for each extended basic block in scanning order. */
365 static int label_tick_ebb_start
;
367 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
368 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
370 static machine_mode nonzero_bits_mode
;
372 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
373 be safely used. It is zero while computing them and after combine has
374 completed. This former test prevents propagating values based on
375 previously set values, which can be incorrect if a variable is modified
378 static int nonzero_sign_valid
;
381 /* Record one modification to rtl structure
382 to be undone by storing old_contents into *where. */
384 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
390 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
391 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
394 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
395 num_undo says how many are currently recorded.
397 other_insn is nonzero if we have modified some other insn in the process
398 of working on subst_insn. It must be verified too. */
404 rtx_insn
*other_insn
;
407 static struct undobuf undobuf
;
409 /* Number of times the pseudo being substituted for
410 was found and replaced. */
412 static int n_occurrences
;
414 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
416 unsigned HOST_WIDE_INT
,
417 unsigned HOST_WIDE_INT
*);
418 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
420 unsigned int, unsigned int *);
421 static void do_SUBST (rtx
*, rtx
);
422 static void do_SUBST_INT (int *, int);
423 static void init_reg_last (void);
424 static void setup_incoming_promotions (rtx_insn
*);
425 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
426 static int cant_combine_insn_p (rtx_insn
*);
427 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
428 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
429 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
430 static int contains_muldiv (rtx
);
431 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
433 static void undo_all (void);
434 static void undo_commit (void);
435 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
436 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
437 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
438 static rtx
simplify_if_then_else (rtx
);
439 static rtx
simplify_set (rtx
);
440 static rtx
simplify_logical (rtx
);
441 static rtx
expand_compound_operation (rtx
);
442 static const_rtx
expand_field_assignment (const_rtx
);
443 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
444 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
445 static rtx
extract_left_shift (rtx
, int);
446 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
447 unsigned HOST_WIDE_INT
*);
448 static rtx
canon_reg_for_combine (rtx
, rtx
);
449 static rtx
force_to_mode (rtx
, machine_mode
,
450 unsigned HOST_WIDE_INT
, int);
451 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
452 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
453 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
454 static rtx
make_field_assignment (rtx
);
455 static rtx
apply_distributive_law (rtx
);
456 static rtx
distribute_and_simplify_rtx (rtx
, int);
457 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
458 unsigned HOST_WIDE_INT
);
459 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
460 unsigned HOST_WIDE_INT
);
461 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
462 HOST_WIDE_INT
, machine_mode
, int *);
463 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
464 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
466 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
467 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
468 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
470 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
471 static void update_table_tick (rtx
);
472 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
473 static void check_promoted_subreg (rtx_insn
*, rtx
);
474 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
475 static void record_dead_and_set_regs (rtx_insn
*);
476 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
477 static rtx
get_last_value (const_rtx
);
478 static int use_crosses_set_p (const_rtx
, int);
479 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
480 static int reg_dead_at_p (rtx
, rtx_insn
*);
481 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
482 static int reg_bitfield_target_p (rtx
, rtx
);
483 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
484 static void distribute_links (struct insn_link
*);
485 static void mark_used_regs_combine (rtx
);
486 static void record_promoted_value (rtx_insn
*, rtx
);
487 static bool unmentioned_reg_p (rtx
, rtx
);
488 static void record_truncated_values (rtx
*, void *);
489 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
490 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
493 /* It is not safe to use ordinary gen_lowpart in combine.
494 See comments in gen_lowpart_for_combine. */
495 #undef RTL_HOOKS_GEN_LOWPART
496 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
498 /* Our implementation of gen_lowpart never emits a new pseudo. */
499 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
500 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
502 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
503 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
505 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
506 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
508 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
509 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
511 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
514 /* Convenience wrapper for the canonicalize_comparison target hook.
515 Target hooks cannot use enum rtx_code. */
517 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
518 bool op0_preserve_value
)
520 int code_int
= (int)*code
;
521 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
522 *code
= (enum rtx_code
)code_int
;
525 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
526 PATTERN can not be split. Otherwise, it returns an insn sequence.
527 This is a wrapper around split_insns which ensures that the
528 reg_stat vector is made larger if the splitter creates a new
532 combine_split_insns (rtx pattern
, rtx insn
)
537 ret
= safe_as_a
<rtx_insn
*> (split_insns (pattern
, insn
));
538 nregs
= max_reg_num ();
539 if (nregs
> reg_stat
.length ())
540 reg_stat
.safe_grow_cleared (nregs
);
544 /* This is used by find_single_use to locate an rtx in LOC that
545 contains exactly one use of DEST, which is typically either a REG
546 or CC0. It returns a pointer to the innermost rtx expression
547 containing DEST. Appearances of DEST that are being used to
548 totally replace it are not counted. */
551 find_single_use_1 (rtx dest
, rtx
*loc
)
554 enum rtx_code code
= GET_CODE (x
);
570 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
571 of a REG that occupies all of the REG, the insn uses DEST if
572 it is mentioned in the destination or the source. Otherwise, we
573 need just check the source. */
574 if (GET_CODE (SET_DEST (x
)) != CC0
575 && GET_CODE (SET_DEST (x
)) != PC
576 && !REG_P (SET_DEST (x
))
577 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
578 && REG_P (SUBREG_REG (SET_DEST (x
)))
579 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
580 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
581 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
582 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
585 return find_single_use_1 (dest
, &SET_SRC (x
));
589 return find_single_use_1 (dest
, &XEXP (x
, 0));
595 /* If it wasn't one of the common cases above, check each expression and
596 vector of this code. Look for a unique usage of DEST. */
598 fmt
= GET_RTX_FORMAT (code
);
599 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
603 if (dest
== XEXP (x
, i
)
604 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
605 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
608 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
611 result
= this_result
;
612 else if (this_result
)
613 /* Duplicate usage. */
616 else if (fmt
[i
] == 'E')
620 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
622 if (XVECEXP (x
, i
, j
) == dest
624 && REG_P (XVECEXP (x
, i
, j
))
625 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
628 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
631 result
= this_result
;
632 else if (this_result
)
642 /* See if DEST, produced in INSN, is used only a single time in the
643 sequel. If so, return a pointer to the innermost rtx expression in which
646 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
648 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
649 care about REG_DEAD notes or LOG_LINKS.
651 Otherwise, we find the single use by finding an insn that has a
652 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
653 only referenced once in that insn, we know that it must be the first
654 and last insn referencing DEST. */
657 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
662 struct insn_link
*link
;
667 next
= NEXT_INSN (insn
);
669 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
672 result
= find_single_use_1 (dest
, &PATTERN (next
));
682 bb
= BLOCK_FOR_INSN (insn
);
683 for (next
= NEXT_INSN (insn
);
684 next
&& BLOCK_FOR_INSN (next
) == bb
;
685 next
= NEXT_INSN (next
))
686 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
688 FOR_EACH_LOG_LINK (link
, next
)
689 if (link
->insn
== insn
)
694 result
= find_single_use_1 (dest
, &PATTERN (next
));
704 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
705 insn. The substitution can be undone by undo_all. If INTO is already
706 set to NEWVAL, do not record this change. Because computing NEWVAL might
707 also call SUBST, we have to compute it before we put anything into
711 do_SUBST (rtx
*into
, rtx newval
)
716 if (oldval
== newval
)
719 /* We'd like to catch as many invalid transformations here as
720 possible. Unfortunately, there are way too many mode changes
721 that are perfectly valid, so we'd waste too much effort for
722 little gain doing the checks here. Focus on catching invalid
723 transformations involving integer constants. */
724 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
725 && CONST_INT_P (newval
))
727 /* Sanity check that we're replacing oldval with a CONST_INT
728 that is a valid sign-extension for the original mode. */
729 gcc_assert (INTVAL (newval
)
730 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
732 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
733 CONST_INT is not valid, because after the replacement, the
734 original mode would be gone. Unfortunately, we can't tell
735 when do_SUBST is called to replace the operand thereof, so we
736 perform this test on oldval instead, checking whether an
737 invalid replacement took place before we got here. */
738 gcc_assert (!(GET_CODE (oldval
) == SUBREG
739 && CONST_INT_P (SUBREG_REG (oldval
))));
740 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
741 && CONST_INT_P (XEXP (oldval
, 0))));
745 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
747 buf
= XNEW (struct undo
);
749 buf
->kind
= UNDO_RTX
;
751 buf
->old_contents
.r
= oldval
;
754 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
757 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
759 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
760 for the value of a HOST_WIDE_INT value (including CONST_INT) is
764 do_SUBST_INT (int *into
, int newval
)
769 if (oldval
== newval
)
773 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
775 buf
= XNEW (struct undo
);
777 buf
->kind
= UNDO_INT
;
779 buf
->old_contents
.i
= oldval
;
782 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
785 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
787 /* Similar to SUBST, but just substitute the mode. This is used when
788 changing the mode of a pseudo-register, so that any other
789 references to the entry in the regno_reg_rtx array will change as
793 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
796 machine_mode oldval
= GET_MODE (*into
);
798 if (oldval
== newval
)
802 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
804 buf
= XNEW (struct undo
);
806 buf
->kind
= UNDO_MODE
;
808 buf
->old_contents
.m
= oldval
;
809 adjust_reg_mode (*into
, newval
);
811 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
814 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
823 struct insn_link
* oldval
= *into
;
825 if (oldval
== newval
)
829 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
831 buf
= XNEW (struct undo
);
833 buf
->kind
= UNDO_LINKS
;
835 buf
->old_contents
.l
= oldval
;
838 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
844 /* Subroutine of try_combine. Determine whether the replacement patterns
845 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
846 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
847 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
848 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
849 of all the instructions can be estimated and the replacements are more
850 expensive than the original sequence. */
853 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
854 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
856 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
857 int new_i2_cost
, new_i3_cost
;
858 int old_cost
, new_cost
;
860 /* Lookup the original insn_rtx_costs. */
861 i2_cost
= INSN_COST (i2
);
862 i3_cost
= INSN_COST (i3
);
866 i1_cost
= INSN_COST (i1
);
869 i0_cost
= INSN_COST (i0
);
870 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
871 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
875 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
876 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
882 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
883 i1_cost
= i0_cost
= 0;
886 /* Calculate the replacement insn_rtx_costs. */
887 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
890 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
891 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
892 ? new_i2_cost
+ new_i3_cost
: 0;
896 new_cost
= new_i3_cost
;
900 if (undobuf
.other_insn
)
902 int old_other_cost
, new_other_cost
;
904 old_other_cost
= INSN_COST (undobuf
.other_insn
);
905 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
906 if (old_other_cost
> 0 && new_other_cost
> 0)
908 old_cost
+= old_other_cost
;
909 new_cost
+= new_other_cost
;
915 /* Disallow this combination if both new_cost and old_cost are greater than
916 zero, and new_cost is greater than old cost. */
917 if (old_cost
> 0 && new_cost
> old_cost
)
924 "rejecting combination of insns %d, %d, %d and %d\n",
925 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
927 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
928 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
933 "rejecting combination of insns %d, %d and %d\n",
934 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
935 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
936 i1_cost
, i2_cost
, i3_cost
, old_cost
);
941 "rejecting combination of insns %d and %d\n",
942 INSN_UID (i2
), INSN_UID (i3
));
943 fprintf (dump_file
, "original costs %d + %d = %d\n",
944 i2_cost
, i3_cost
, old_cost
);
949 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
950 new_i2_cost
, new_i3_cost
, new_cost
);
953 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
959 /* Update the uid_insn_cost array with the replacement costs. */
960 INSN_COST (i2
) = new_i2_cost
;
961 INSN_COST (i3
) = new_i3_cost
;
973 /* Delete any insns that copy a register to itself. */
976 delete_noop_moves (void)
978 rtx_insn
*insn
, *next
;
981 FOR_EACH_BB_FN (bb
, cfun
)
983 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
985 next
= NEXT_INSN (insn
);
986 if (INSN_P (insn
) && noop_move_p (insn
))
989 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
991 delete_insn_and_edges (insn
);
998 /* Fill in log links field for all insns. */
1001 create_log_links (void)
1004 rtx_insn
**next_use
;
1008 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1010 /* Pass through each block from the end, recording the uses of each
1011 register and establishing log links when def is encountered.
1012 Note that we do not clear next_use array in order to save time,
1013 so we have to test whether the use is in the same basic block as def.
1015 There are a few cases below when we do not consider the definition or
1016 usage -- these are taken from original flow.c did. Don't ask me why it is
1017 done this way; I don't know and if it works, I don't want to know. */
1019 FOR_EACH_BB_FN (bb
, cfun
)
1021 FOR_BB_INSNS_REVERSE (bb
, insn
)
1023 if (!NONDEBUG_INSN_P (insn
))
1026 /* Log links are created only once. */
1027 gcc_assert (!LOG_LINKS (insn
));
1029 FOR_EACH_INSN_DEF (def
, insn
)
1031 int regno
= DF_REF_REGNO (def
);
1034 if (!next_use
[regno
])
1037 /* Do not consider if it is pre/post modification in MEM. */
1038 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1041 /* Do not make the log link for frame pointer. */
1042 if ((regno
== FRAME_POINTER_REGNUM
1043 && (! reload_completed
|| frame_pointer_needed
))
1044 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1045 || (regno
== HARD_FRAME_POINTER_REGNUM
1046 && (! reload_completed
|| frame_pointer_needed
))
1048 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1049 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1054 use_insn
= next_use
[regno
];
1055 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1059 We don't build a LOG_LINK for hard registers contained
1060 in ASM_OPERANDs. If these registers get replaced,
1061 we might wind up changing the semantics of the insn,
1062 even if reload can make what appear to be valid
1063 assignments later. */
1064 if (regno
>= FIRST_PSEUDO_REGISTER
1065 || asm_noperands (PATTERN (use_insn
)) < 0)
1067 /* Don't add duplicate links between instructions. */
1068 struct insn_link
*links
;
1069 FOR_EACH_LOG_LINK (links
, use_insn
)
1070 if (insn
== links
->insn
)
1074 LOG_LINKS (use_insn
)
1075 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1078 next_use
[regno
] = NULL
;
1081 FOR_EACH_INSN_USE (use
, insn
)
1083 int regno
= DF_REF_REGNO (use
);
1085 /* Do not consider the usage of the stack pointer
1086 by function call. */
1087 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1090 next_use
[regno
] = insn
;
1098 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1099 true if we found a LOG_LINK that proves that A feeds B. This only works
1100 if there are no instructions between A and B which could have a link
1101 depending on A, since in that case we would not record a link for B.
1102 We also check the implicit dependency created by a cc0 setter/user
1106 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1108 struct insn_link
*links
;
1109 FOR_EACH_LOG_LINK (links
, b
)
1110 if (links
->insn
== a
)
1119 /* Main entry point for combiner. F is the first insn of the function.
1120 NREGS is the first unused pseudo-reg number.
1122 Return nonzero if the combiner has turned an indirect jump
1123 instruction into a direct jump. */
1125 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1127 rtx_insn
*insn
, *next
;
1131 struct insn_link
*links
, *nextlinks
;
1133 basic_block last_bb
;
1135 int new_direct_jump_p
= 0;
1137 for (first
= f
; first
&& !INSN_P (first
); )
1138 first
= NEXT_INSN (first
);
1142 combine_attempts
= 0;
1145 combine_successes
= 0;
1147 rtl_hooks
= combine_rtl_hooks
;
1149 reg_stat
.safe_grow_cleared (nregs
);
1151 init_recog_no_volatile ();
1153 /* Allocate array for insn info. */
1154 max_uid_known
= get_max_uid ();
1155 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1156 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1157 gcc_obstack_init (&insn_link_obstack
);
1159 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1161 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1162 problems when, for example, we have j <<= 1 in a loop. */
1164 nonzero_sign_valid
= 0;
1165 label_tick
= label_tick_ebb_start
= 1;
1167 /* Scan all SETs and see if we can deduce anything about what
1168 bits are known to be zero for some registers and how many copies
1169 of the sign bit are known to exist for those registers.
1171 Also set any known values so that we can use it while searching
1172 for what bits are known to be set. */
1174 setup_incoming_promotions (first
);
1175 /* Allow the entry block and the first block to fall into the same EBB.
1176 Conceptually the incoming promotions are assigned to the entry block. */
1177 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1179 create_log_links ();
1180 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1182 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1187 if (!single_pred_p (this_basic_block
)
1188 || single_pred (this_basic_block
) != last_bb
)
1189 label_tick_ebb_start
= label_tick
;
1190 last_bb
= this_basic_block
;
1192 FOR_BB_INSNS (this_basic_block
, insn
)
1193 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1199 subst_low_luid
= DF_INSN_LUID (insn
);
1202 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1204 record_dead_and_set_regs (insn
);
1207 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1208 if (REG_NOTE_KIND (links
) == REG_INC
)
1209 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1213 /* Record the current insn_rtx_cost of this instruction. */
1214 if (NONJUMP_INSN_P (insn
))
1215 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1216 optimize_this_for_speed_p
);
1218 fprintf (dump_file
, "insn_cost %d: %d\n",
1219 INSN_UID (insn
), INSN_COST (insn
));
1223 nonzero_sign_valid
= 1;
1225 /* Now scan all the insns in forward order. */
1226 label_tick
= label_tick_ebb_start
= 1;
1228 setup_incoming_promotions (first
);
1229 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1230 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1232 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1234 rtx_insn
*last_combined_insn
= NULL
;
1235 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1240 if (!single_pred_p (this_basic_block
)
1241 || single_pred (this_basic_block
) != last_bb
)
1242 label_tick_ebb_start
= label_tick
;
1243 last_bb
= this_basic_block
;
1245 rtl_profile_for_bb (this_basic_block
);
1246 for (insn
= BB_HEAD (this_basic_block
);
1247 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1248 insn
= next
? next
: NEXT_INSN (insn
))
1251 if (!NONDEBUG_INSN_P (insn
))
1254 while (last_combined_insn
1255 && last_combined_insn
->deleted ())
1256 last_combined_insn
= PREV_INSN (last_combined_insn
);
1257 if (last_combined_insn
== NULL_RTX
1258 || BARRIER_P (last_combined_insn
)
1259 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1260 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1261 last_combined_insn
= insn
;
1263 /* See if we know about function return values before this
1264 insn based upon SUBREG flags. */
1265 check_promoted_subreg (insn
, PATTERN (insn
));
1267 /* See if we can find hardregs and subreg of pseudos in
1268 narrower modes. This could help turning TRUNCATEs
1270 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1272 /* Try this insn with each insn it links back to. */
1274 FOR_EACH_LOG_LINK (links
, insn
)
1275 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1276 NULL
, &new_direct_jump_p
,
1277 last_combined_insn
)) != 0)
1279 statistics_counter_event (cfun
, "two-insn combine", 1);
1283 /* Try each sequence of three linked insns ending with this one. */
1285 if (max_combine
>= 3)
1286 FOR_EACH_LOG_LINK (links
, insn
)
1288 rtx_insn
*link
= links
->insn
;
1290 /* If the linked insn has been replaced by a note, then there
1291 is no point in pursuing this chain any further. */
1295 FOR_EACH_LOG_LINK (nextlinks
, link
)
1296 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1297 NULL
, &new_direct_jump_p
,
1298 last_combined_insn
)) != 0)
1300 statistics_counter_event (cfun
, "three-insn combine", 1);
1306 /* Try to combine a jump insn that uses CC0
1307 with a preceding insn that sets CC0, and maybe with its
1308 logical predecessor as well.
1309 This is how we make decrement-and-branch insns.
1310 We need this special code because data flow connections
1311 via CC0 do not get entered in LOG_LINKS. */
1314 && (prev
= prev_nonnote_insn (insn
)) != 0
1315 && NONJUMP_INSN_P (prev
)
1316 && sets_cc0_p (PATTERN (prev
)))
1318 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1320 last_combined_insn
)) != 0)
1323 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1324 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1325 NULL
, &new_direct_jump_p
,
1326 last_combined_insn
)) != 0)
1330 /* Do the same for an insn that explicitly references CC0. */
1331 if (NONJUMP_INSN_P (insn
)
1332 && (prev
= prev_nonnote_insn (insn
)) != 0
1333 && NONJUMP_INSN_P (prev
)
1334 && sets_cc0_p (PATTERN (prev
))
1335 && GET_CODE (PATTERN (insn
)) == SET
1336 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1338 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1340 last_combined_insn
)) != 0)
1343 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1344 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1345 NULL
, &new_direct_jump_p
,
1346 last_combined_insn
)) != 0)
1350 /* Finally, see if any of the insns that this insn links to
1351 explicitly references CC0. If so, try this insn, that insn,
1352 and its predecessor if it sets CC0. */
1353 FOR_EACH_LOG_LINK (links
, insn
)
1354 if (NONJUMP_INSN_P (links
->insn
)
1355 && GET_CODE (PATTERN (links
->insn
)) == SET
1356 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1357 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1358 && NONJUMP_INSN_P (prev
)
1359 && sets_cc0_p (PATTERN (prev
))
1360 && (next
= try_combine (insn
, links
->insn
,
1361 prev
, NULL
, &new_direct_jump_p
,
1362 last_combined_insn
)) != 0)
1366 /* Try combining an insn with two different insns whose results it
1368 if (max_combine
>= 3)
1369 FOR_EACH_LOG_LINK (links
, insn
)
1370 for (nextlinks
= links
->next
; nextlinks
;
1371 nextlinks
= nextlinks
->next
)
1372 if ((next
= try_combine (insn
, links
->insn
,
1373 nextlinks
->insn
, NULL
,
1375 last_combined_insn
)) != 0)
1378 statistics_counter_event (cfun
, "three-insn combine", 1);
1382 /* Try four-instruction combinations. */
1383 if (max_combine
>= 4)
1384 FOR_EACH_LOG_LINK (links
, insn
)
1386 struct insn_link
*next1
;
1387 rtx_insn
*link
= links
->insn
;
1389 /* If the linked insn has been replaced by a note, then there
1390 is no point in pursuing this chain any further. */
1394 FOR_EACH_LOG_LINK (next1
, link
)
1396 rtx_insn
*link1
= next1
->insn
;
1399 /* I0 -> I1 -> I2 -> I3. */
1400 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1401 if ((next
= try_combine (insn
, link
, link1
,
1404 last_combined_insn
)) != 0)
1406 statistics_counter_event (cfun
, "four-insn combine", 1);
1409 /* I0, I1 -> I2, I2 -> I3. */
1410 for (nextlinks
= next1
->next
; nextlinks
;
1411 nextlinks
= nextlinks
->next
)
1412 if ((next
= try_combine (insn
, link
, link1
,
1415 last_combined_insn
)) != 0)
1417 statistics_counter_event (cfun
, "four-insn combine", 1);
1422 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1424 rtx_insn
*link1
= next1
->insn
;
1427 /* I0 -> I2; I1, I2 -> I3. */
1428 FOR_EACH_LOG_LINK (nextlinks
, link
)
1429 if ((next
= try_combine (insn
, link
, link1
,
1432 last_combined_insn
)) != 0)
1434 statistics_counter_event (cfun
, "four-insn combine", 1);
1437 /* I0 -> I1; I1, I2 -> I3. */
1438 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1439 if ((next
= try_combine (insn
, link
, link1
,
1442 last_combined_insn
)) != 0)
1444 statistics_counter_event (cfun
, "four-insn combine", 1);
1450 /* Try this insn with each REG_EQUAL note it links back to. */
1451 FOR_EACH_LOG_LINK (links
, insn
)
1454 rtx_insn
*temp
= links
->insn
;
1455 if ((set
= single_set (temp
)) != 0
1456 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1457 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1458 /* Avoid using a register that may already been marked
1459 dead by an earlier instruction. */
1460 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1461 && (GET_MODE (note
) == VOIDmode
1462 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1463 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1465 /* Temporarily replace the set's source with the
1466 contents of the REG_EQUAL note. The insn will
1467 be deleted or recognized by try_combine. */
1468 rtx orig
= SET_SRC (set
);
1469 SET_SRC (set
) = note
;
1471 i2mod_old_rhs
= copy_rtx (orig
);
1472 i2mod_new_rhs
= copy_rtx (note
);
1473 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1475 last_combined_insn
);
1479 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1482 SET_SRC (set
) = orig
;
1487 record_dead_and_set_regs (insn
);
1494 default_rtl_profile ();
1496 new_direct_jump_p
|= purge_all_dead_edges ();
1497 delete_noop_moves ();
1500 obstack_free (&insn_link_obstack
, NULL
);
1501 free (uid_log_links
);
1502 free (uid_insn_cost
);
1503 reg_stat
.release ();
1506 struct undo
*undo
, *next
;
1507 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1515 total_attempts
+= combine_attempts
;
1516 total_merges
+= combine_merges
;
1517 total_extras
+= combine_extras
;
1518 total_successes
+= combine_successes
;
1520 nonzero_sign_valid
= 0;
1521 rtl_hooks
= general_rtl_hooks
;
1523 /* Make recognizer allow volatile MEMs again. */
1526 return new_direct_jump_p
;
1529 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1532 init_reg_last (void)
1537 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1538 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1541 /* Set up any promoted values for incoming argument registers. */
1544 setup_incoming_promotions (rtx_insn
*first
)
1547 bool strictly_local
= false;
1549 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1550 arg
= DECL_CHAIN (arg
))
1552 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1554 machine_mode mode1
, mode2
, mode3
, mode4
;
1556 /* Only continue if the incoming argument is in a register. */
1560 /* Determine, if possible, whether all call sites of the current
1561 function lie within the current compilation unit. (This does
1562 take into account the exporting of a function via taking its
1563 address, and so forth.) */
1564 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1566 /* The mode and signedness of the argument before any promotions happen
1567 (equal to the mode of the pseudo holding it at that stage). */
1568 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1569 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1571 /* The mode and signedness of the argument after any source language and
1572 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1573 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1574 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1576 /* The mode and signedness of the argument as it is actually passed,
1577 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1578 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1579 TREE_TYPE (cfun
->decl
), 0);
1581 /* The mode of the register in which the argument is being passed. */
1582 mode4
= GET_MODE (reg
);
1584 /* Eliminate sign extensions in the callee when:
1585 (a) A mode promotion has occurred; */
1588 /* (b) The mode of the register is the same as the mode of
1589 the argument as it is passed; */
1592 /* (c) There's no language level extension; */
1595 /* (c.1) All callers are from the current compilation unit. If that's
1596 the case we don't have to rely on an ABI, we only have to know
1597 what we're generating right now, and we know that we will do the
1598 mode1 to mode2 promotion with the given sign. */
1599 else if (!strictly_local
)
1601 /* (c.2) The combination of the two promotions is useful. This is
1602 true when the signs match, or if the first promotion is unsigned.
1603 In the later case, (sign_extend (zero_extend x)) is the same as
1604 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1610 /* Record that the value was promoted from mode1 to mode3,
1611 so that any sign extension at the head of the current
1612 function may be eliminated. */
1613 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1614 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1615 record_value_for_reg (reg
, first
, x
);
1619 /* Called via note_stores. If X is a pseudo that is narrower than
1620 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1622 If we are setting only a portion of X and we can't figure out what
1623 portion, assume all bits will be used since we don't know what will
1626 Similarly, set how many bits of X are known to be copies of the sign bit
1627 at all locations in the function. This is the smallest number implied
1631 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1633 rtx_insn
*insn
= (rtx_insn
*) data
;
1637 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1638 /* If this register is undefined at the start of the file, we can't
1639 say what its contents were. */
1640 && ! REGNO_REG_SET_P
1641 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1642 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1644 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1646 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1648 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1649 rsp
->sign_bit_copies
= 1;
1653 /* If this register is being initialized using itself, and the
1654 register is uninitialized in this basic block, and there are
1655 no LOG_LINKS which set the register, then part of the
1656 register is uninitialized. In that case we can't assume
1657 anything about the number of nonzero bits.
1659 ??? We could do better if we checked this in
1660 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1661 could avoid making assumptions about the insn which initially
1662 sets the register, while still using the information in other
1663 insns. We would have to be careful to check every insn
1664 involved in the combination. */
1667 && reg_referenced_p (x
, PATTERN (insn
))
1668 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1671 struct insn_link
*link
;
1673 FOR_EACH_LOG_LINK (link
, insn
)
1674 if (dead_or_set_p (link
->insn
, x
))
1678 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1679 rsp
->sign_bit_copies
= 1;
1684 /* If this is a complex assignment, see if we can convert it into a
1685 simple assignment. */
1686 set
= expand_field_assignment (set
);
1688 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1689 set what we know about X. */
1691 if (SET_DEST (set
) == x
1692 || (paradoxical_subreg_p (SET_DEST (set
))
1693 && SUBREG_REG (SET_DEST (set
)) == x
))
1695 rtx src
= SET_SRC (set
);
1697 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1698 /* If X is narrower than a word and SRC is a non-negative
1699 constant that would appear negative in the mode of X,
1700 sign-extend it for use in reg_stat[].nonzero_bits because some
1701 machines (maybe most) will actually do the sign-extension
1702 and this is the conservative approach.
1704 ??? For 2.5, try to tighten up the MD files in this regard
1705 instead of this kludge. */
1707 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1708 && CONST_INT_P (src
)
1710 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1711 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1714 /* Don't call nonzero_bits if it cannot change anything. */
1715 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1716 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1717 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1718 if (rsp
->sign_bit_copies
== 0
1719 || rsp
->sign_bit_copies
> num
)
1720 rsp
->sign_bit_copies
= num
;
1724 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1725 rsp
->sign_bit_copies
= 1;
1730 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1731 optionally insns that were previously combined into I3 or that will be
1732 combined into the merger of INSN and I3. The order is PRED, PRED2,
1733 INSN, SUCC, SUCC2, I3.
1735 Return 0 if the combination is not allowed for any reason.
1737 If the combination is allowed, *PDEST will be set to the single
1738 destination of INSN and *PSRC to the single source, and this function
1742 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1743 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1744 rtx
*pdest
, rtx
*psrc
)
1753 bool all_adjacent
= true;
1754 int (*is_volatile_p
) (const_rtx
);
1760 if (next_active_insn (succ2
) != i3
)
1761 all_adjacent
= false;
1762 if (next_active_insn (succ
) != succ2
)
1763 all_adjacent
= false;
1765 else if (next_active_insn (succ
) != i3
)
1766 all_adjacent
= false;
1767 if (next_active_insn (insn
) != succ
)
1768 all_adjacent
= false;
1770 else if (next_active_insn (insn
) != i3
)
1771 all_adjacent
= false;
1773 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1774 or a PARALLEL consisting of such a SET and CLOBBERs.
1776 If INSN has CLOBBER parallel parts, ignore them for our processing.
1777 By definition, these happen during the execution of the insn. When it
1778 is merged with another insn, all bets are off. If they are, in fact,
1779 needed and aren't also supplied in I3, they may be added by
1780 recog_for_combine. Otherwise, it won't match.
1782 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1785 Get the source and destination of INSN. If more than one, can't
1788 if (GET_CODE (PATTERN (insn
)) == SET
)
1789 set
= PATTERN (insn
);
1790 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1791 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1793 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1795 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1797 switch (GET_CODE (elt
))
1799 /* This is important to combine floating point insns
1800 for the SH4 port. */
1802 /* Combining an isolated USE doesn't make sense.
1803 We depend here on combinable_i3pat to reject them. */
1804 /* The code below this loop only verifies that the inputs of
1805 the SET in INSN do not change. We call reg_set_between_p
1806 to verify that the REG in the USE does not change between
1808 If the USE in INSN was for a pseudo register, the matching
1809 insn pattern will likely match any register; combining this
1810 with any other USE would only be safe if we knew that the
1811 used registers have identical values, or if there was
1812 something to tell them apart, e.g. different modes. For
1813 now, we forgo such complicated tests and simply disallow
1814 combining of USES of pseudo registers with any other USE. */
1815 if (REG_P (XEXP (elt
, 0))
1816 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1818 rtx i3pat
= PATTERN (i3
);
1819 int i
= XVECLEN (i3pat
, 0) - 1;
1820 unsigned int regno
= REGNO (XEXP (elt
, 0));
1824 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1826 if (GET_CODE (i3elt
) == USE
1827 && REG_P (XEXP (i3elt
, 0))
1828 && (REGNO (XEXP (i3elt
, 0)) == regno
1829 ? reg_set_between_p (XEXP (elt
, 0),
1830 PREV_INSN (insn
), i3
)
1831 : regno
>= FIRST_PSEUDO_REGISTER
))
1838 /* We can ignore CLOBBERs. */
1843 /* Ignore SETs whose result isn't used but not those that
1844 have side-effects. */
1845 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1846 && insn_nothrow_p (insn
)
1847 && !side_effects_p (elt
))
1850 /* If we have already found a SET, this is a second one and
1851 so we cannot combine with this insn. */
1859 /* Anything else means we can't combine. */
1865 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1866 so don't do anything with it. */
1867 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1876 /* The simplification in expand_field_assignment may call back to
1877 get_last_value, so set safe guard here. */
1878 subst_low_luid
= DF_INSN_LUID (insn
);
1880 set
= expand_field_assignment (set
);
1881 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1883 /* Don't eliminate a store in the stack pointer. */
1884 if (dest
== stack_pointer_rtx
1885 /* Don't combine with an insn that sets a register to itself if it has
1886 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1887 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1888 /* Can't merge an ASM_OPERANDS. */
1889 || GET_CODE (src
) == ASM_OPERANDS
1890 /* Can't merge a function call. */
1891 || GET_CODE (src
) == CALL
1892 /* Don't eliminate a function call argument. */
1894 && (find_reg_fusage (i3
, USE
, dest
)
1896 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1897 && global_regs
[REGNO (dest
)])))
1898 /* Don't substitute into an incremented register. */
1899 || FIND_REG_INC_NOTE (i3
, dest
)
1900 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1901 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1902 /* Don't substitute into a non-local goto, this confuses CFG. */
1903 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1904 /* Make sure that DEST is not used after SUCC but before I3. */
1907 && (reg_used_between_p (dest
, succ2
, i3
)
1908 || reg_used_between_p (dest
, succ
, succ2
)))
1909 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1910 /* Make sure that the value that is to be substituted for the register
1911 does not use any registers whose values alter in between. However,
1912 If the insns are adjacent, a use can't cross a set even though we
1913 think it might (this can happen for a sequence of insns each setting
1914 the same destination; last_set of that register might point to
1915 a NOTE). If INSN has a REG_EQUIV note, the register is always
1916 equivalent to the memory so the substitution is valid even if there
1917 are intervening stores. Also, don't move a volatile asm or
1918 UNSPEC_VOLATILE across any other insns. */
1921 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1922 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1923 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1924 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1925 /* Don't combine across a CALL_INSN, because that would possibly
1926 change whether the life span of some REGs crosses calls or not,
1927 and it is a pain to update that information.
1928 Exception: if source is a constant, moving it later can't hurt.
1929 Accept that as a special case. */
1930 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1933 /* DEST must either be a REG or CC0. */
1936 /* If register alignment is being enforced for multi-word items in all
1937 cases except for parameters, it is possible to have a register copy
1938 insn referencing a hard register that is not allowed to contain the
1939 mode being copied and which would not be valid as an operand of most
1940 insns. Eliminate this problem by not combining with such an insn.
1942 Also, on some machines we don't want to extend the life of a hard
1946 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1947 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1948 /* Don't extend the life of a hard register unless it is
1949 user variable (if we have few registers) or it can't
1950 fit into the desired register (meaning something special
1952 Also avoid substituting a return register into I3, because
1953 reload can't handle a conflict with constraints of other
1955 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1956 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1959 else if (GET_CODE (dest
) != CC0
)
1963 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1964 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1965 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1967 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1969 /* If the clobber represents an earlyclobber operand, we must not
1970 substitute an expression containing the clobbered register.
1971 As we do not analyze the constraint strings here, we have to
1972 make the conservative assumption. However, if the register is
1973 a fixed hard reg, the clobber cannot represent any operand;
1974 we leave it up to the machine description to either accept or
1975 reject use-and-clobber patterns. */
1977 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1978 || !fixed_regs
[REGNO (reg
)])
1979 if (reg_overlap_mentioned_p (reg
, src
))
1983 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1984 or not), reject, unless nothing volatile comes between it and I3 */
1986 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1988 /* Make sure neither succ nor succ2 contains a volatile reference. */
1989 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1991 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1993 /* We'll check insns between INSN and I3 below. */
1996 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1997 to be an explicit register variable, and was chosen for a reason. */
1999 if (GET_CODE (src
) == ASM_OPERANDS
2000 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2003 /* If INSN contains volatile references (specifically volatile MEMs),
2004 we cannot combine across any other volatile references.
2005 Even if INSN doesn't contain volatile references, any intervening
2006 volatile insn might affect machine state. */
2008 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2012 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2013 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2016 /* If INSN contains an autoincrement or autodecrement, make sure that
2017 register is not used between there and I3, and not already used in
2018 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2019 Also insist that I3 not be a jump; if it were one
2020 and the incremented register were spilled, we would lose. */
2023 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2024 if (REG_NOTE_KIND (link
) == REG_INC
2026 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2027 || (pred
!= NULL_RTX
2028 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2029 || (pred2
!= NULL_RTX
2030 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2031 || (succ
!= NULL_RTX
2032 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2033 || (succ2
!= NULL_RTX
2034 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2035 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2040 /* Don't combine an insn that follows a CC0-setting insn.
2041 An insn that uses CC0 must not be separated from the one that sets it.
2042 We do, however, allow I2 to follow a CC0-setting insn if that insn
2043 is passed as I1; in that case it will be deleted also.
2044 We also allow combining in this case if all the insns are adjacent
2045 because that would leave the two CC0 insns adjacent as well.
2046 It would be more logical to test whether CC0 occurs inside I1 or I2,
2047 but that would be much slower, and this ought to be equivalent. */
2049 p
= prev_nonnote_insn (insn
);
2050 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2055 /* If we get here, we have passed all the tests and the combination is
2064 /* LOC is the location within I3 that contains its pattern or the component
2065 of a PARALLEL of the pattern. We validate that it is valid for combining.
2067 One problem is if I3 modifies its output, as opposed to replacing it
2068 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2069 doing so would produce an insn that is not equivalent to the original insns.
2073 (set (reg:DI 101) (reg:DI 100))
2074 (set (subreg:SI (reg:DI 101) 0) <foo>)
2076 This is NOT equivalent to:
2078 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2079 (set (reg:DI 101) (reg:DI 100))])
2081 Not only does this modify 100 (in which case it might still be valid
2082 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2084 We can also run into a problem if I2 sets a register that I1
2085 uses and I1 gets directly substituted into I3 (not via I2). In that
2086 case, we would be getting the wrong value of I2DEST into I3, so we
2087 must reject the combination. This case occurs when I2 and I1 both
2088 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2089 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2090 of a SET must prevent combination from occurring. The same situation
2091 can occur for I0, in which case I0_NOT_IN_SRC is set.
2093 Before doing the above check, we first try to expand a field assignment
2094 into a set of logical operations.
2096 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2097 we place a register that is both set and used within I3. If more than one
2098 such register is detected, we fail.
2100 Return 1 if the combination is valid, zero otherwise. */
2103 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2104 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2108 if (GET_CODE (x
) == SET
)
2111 rtx dest
= SET_DEST (set
);
2112 rtx src
= SET_SRC (set
);
2113 rtx inner_dest
= dest
;
2116 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2117 || GET_CODE (inner_dest
) == SUBREG
2118 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2119 inner_dest
= XEXP (inner_dest
, 0);
2121 /* Check for the case where I3 modifies its output, as discussed
2122 above. We don't want to prevent pseudos from being combined
2123 into the address of a MEM, so only prevent the combination if
2124 i1 or i2 set the same MEM. */
2125 if ((inner_dest
!= dest
&&
2126 (!MEM_P (inner_dest
)
2127 || rtx_equal_p (i2dest
, inner_dest
)
2128 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2129 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2130 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2131 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2132 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2134 /* This is the same test done in can_combine_p except we can't test
2135 all_adjacent; we don't have to, since this instruction will stay
2136 in place, thus we are not considering increasing the lifetime of
2139 Also, if this insn sets a function argument, combining it with
2140 something that might need a spill could clobber a previous
2141 function argument; the all_adjacent test in can_combine_p also
2142 checks this; here, we do a more specific test for this case. */
2144 || (REG_P (inner_dest
)
2145 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2146 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2147 GET_MODE (inner_dest
))))
2148 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2149 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2152 /* If DEST is used in I3, it is being killed in this insn, so
2153 record that for later. We have to consider paradoxical
2154 subregs here, since they kill the whole register, but we
2155 ignore partial subregs, STRICT_LOW_PART, etc.
2156 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2157 STACK_POINTER_REGNUM, since these are always considered to be
2158 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2160 if (GET_CODE (subdest
) == SUBREG
2161 && (GET_MODE_SIZE (GET_MODE (subdest
))
2162 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2163 subdest
= SUBREG_REG (subdest
);
2166 && reg_referenced_p (subdest
, PATTERN (i3
))
2167 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2168 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2169 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2171 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2172 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2173 || ! fixed_regs
[REGNO (subdest
)])
2175 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2177 if (*pi3dest_killed
)
2180 *pi3dest_killed
= subdest
;
2184 else if (GET_CODE (x
) == PARALLEL
)
2188 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2189 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2190 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2197 /* Return 1 if X is an arithmetic expression that contains a multiplication
2198 and division. We don't count multiplications by powers of two here. */
2201 contains_muldiv (rtx x
)
2203 switch (GET_CODE (x
))
2205 case MOD
: case DIV
: case UMOD
: case UDIV
:
2209 return ! (CONST_INT_P (XEXP (x
, 1))
2210 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2213 return contains_muldiv (XEXP (x
, 0))
2214 || contains_muldiv (XEXP (x
, 1));
2217 return contains_muldiv (XEXP (x
, 0));
2223 /* Determine whether INSN can be used in a combination. Return nonzero if
2224 not. This is used in try_combine to detect early some cases where we
2225 can't perform combinations. */
2228 cant_combine_insn_p (rtx_insn
*insn
)
2233 /* If this isn't really an insn, we can't do anything.
2234 This can occur when flow deletes an insn that it has merged into an
2235 auto-increment address. */
2236 if (! INSN_P (insn
))
2239 /* Never combine loads and stores involving hard regs that are likely
2240 to be spilled. The register allocator can usually handle such
2241 reg-reg moves by tying. If we allow the combiner to make
2242 substitutions of likely-spilled regs, reload might die.
2243 As an exception, we allow combinations involving fixed regs; these are
2244 not available to the register allocator so there's no risk involved. */
2246 set
= single_set (insn
);
2249 src
= SET_SRC (set
);
2250 dest
= SET_DEST (set
);
2251 if (GET_CODE (src
) == SUBREG
)
2252 src
= SUBREG_REG (src
);
2253 if (GET_CODE (dest
) == SUBREG
)
2254 dest
= SUBREG_REG (dest
);
2255 if (REG_P (src
) && REG_P (dest
)
2256 && ((HARD_REGISTER_P (src
)
2257 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2258 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2259 || (HARD_REGISTER_P (dest
)
2260 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2261 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2267 struct likely_spilled_retval_info
2269 unsigned regno
, nregs
;
2273 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2274 hard registers that are known to be written to / clobbered in full. */
2276 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2278 struct likely_spilled_retval_info
*const info
=
2279 (struct likely_spilled_retval_info
*) data
;
2280 unsigned regno
, nregs
;
2283 if (!REG_P (XEXP (set
, 0)))
2286 if (regno
>= info
->regno
+ info
->nregs
)
2288 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2289 if (regno
+ nregs
<= info
->regno
)
2291 new_mask
= (2U << (nregs
- 1)) - 1;
2292 if (regno
< info
->regno
)
2293 new_mask
>>= info
->regno
- regno
;
2295 new_mask
<<= regno
- info
->regno
;
2296 info
->mask
&= ~new_mask
;
2299 /* Return nonzero iff part of the return value is live during INSN, and
2300 it is likely spilled. This can happen when more than one insn is needed
2301 to copy the return value, e.g. when we consider to combine into the
2302 second copy insn for a complex value. */
2305 likely_spilled_retval_p (rtx_insn
*insn
)
2307 rtx_insn
*use
= BB_END (this_basic_block
);
2310 unsigned regno
, nregs
;
2311 /* We assume here that no machine mode needs more than
2312 32 hard registers when the value overlaps with a register
2313 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2315 struct likely_spilled_retval_info info
;
2317 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2319 reg
= XEXP (PATTERN (use
), 0);
2320 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2322 regno
= REGNO (reg
);
2323 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2326 mask
= (2U << (nregs
- 1)) - 1;
2328 /* Disregard parts of the return value that are set later. */
2332 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2334 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2337 /* Check if any of the (probably) live return value registers is
2342 if ((mask
& 1 << nregs
)
2343 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2349 /* Adjust INSN after we made a change to its destination.
2351 Changing the destination can invalidate notes that say something about
2352 the results of the insn and a LOG_LINK pointing to the insn. */
2355 adjust_for_new_dest (rtx_insn
*insn
)
2357 /* For notes, be conservative and simply remove them. */
2358 remove_reg_equal_equiv_notes (insn
);
2360 /* The new insn will have a destination that was previously the destination
2361 of an insn just above it. Call distribute_links to make a LOG_LINK from
2362 the next use of that destination. */
2363 distribute_links (alloc_insn_link (insn
, NULL
));
2365 df_insn_rescan (insn
);
2368 /* Return TRUE if combine can reuse reg X in mode MODE.
2369 ADDED_SETS is nonzero if the original set is still required. */
2371 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2379 /* Allow hard registers if the new mode is legal, and occupies no more
2380 registers than the old mode. */
2381 if (regno
< FIRST_PSEUDO_REGISTER
)
2382 return (HARD_REGNO_MODE_OK (regno
, mode
)
2383 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2384 >= hard_regno_nregs
[regno
][mode
]));
2386 /* Or a pseudo that is only used once. */
2387 return (REG_N_SETS (regno
) == 1 && !added_sets
2388 && !REG_USERVAR_P (x
));
2392 /* Check whether X, the destination of a set, refers to part of
2393 the register specified by REG. */
2396 reg_subword_p (rtx x
, rtx reg
)
2398 /* Check that reg is an integer mode register. */
2399 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2402 if (GET_CODE (x
) == STRICT_LOW_PART
2403 || GET_CODE (x
) == ZERO_EXTRACT
)
2406 return GET_CODE (x
) == SUBREG
2407 && SUBREG_REG (x
) == reg
2408 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2411 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2412 Note that the INSN should be deleted *after* removing dead edges, so
2413 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2414 but not for a (set (pc) (label_ref FOO)). */
2417 update_cfg_for_uncondjump (rtx_insn
*insn
)
2419 basic_block bb
= BLOCK_FOR_INSN (insn
);
2420 gcc_assert (BB_END (bb
) == insn
);
2422 purge_dead_edges (bb
);
2425 if (EDGE_COUNT (bb
->succs
) == 1)
2429 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2431 /* Remove barriers from the footer if there are any. */
2432 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2433 if (BARRIER_P (insn
))
2435 if (PREV_INSN (insn
))
2436 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2438 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2439 if (NEXT_INSN (insn
))
2440 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2442 else if (LABEL_P (insn
))
2447 /* Try to combine the insns I0, I1 and I2 into I3.
2448 Here I0, I1 and I2 appear earlier than I3.
2449 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2452 If we are combining more than two insns and the resulting insn is not
2453 recognized, try splitting it into two insns. If that happens, I2 and I3
2454 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2455 Otherwise, I0, I1 and I2 are pseudo-deleted.
2457 Return 0 if the combination does not work. Then nothing is changed.
2458 If we did the combination, return the insn at which combine should
2461 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2462 new direct jump instruction.
2464 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2465 been I3 passed to an earlier try_combine within the same basic
2469 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2470 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2472 /* New patterns for I3 and I2, respectively. */
2473 rtx newpat
, newi2pat
= 0;
2474 rtvec newpat_vec_with_clobbers
= 0;
2475 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2476 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2478 int added_sets_0
, added_sets_1
, added_sets_2
;
2479 /* Total number of SETs to put into I3. */
2481 /* Nonzero if I2's or I1's body now appears in I3. */
2482 int i2_is_used
= 0, i1_is_used
= 0;
2483 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2484 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2485 /* Contains I3 if the destination of I3 is used in its source, which means
2486 that the old life of I3 is being killed. If that usage is placed into
2487 I2 and not in I3, a REG_DEAD note must be made. */
2488 rtx i3dest_killed
= 0;
2489 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2490 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2491 /* Copy of SET_SRC of I1 and I0, if needed. */
2492 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2493 /* Set if I2DEST was reused as a scratch register. */
2494 bool i2scratch
= false;
2495 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2496 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2497 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2498 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2499 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2500 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2501 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2502 /* Notes that must be added to REG_NOTES in I3 and I2. */
2503 rtx new_i3_notes
, new_i2_notes
;
2504 /* Notes that we substituted I3 into I2 instead of the normal case. */
2505 int i3_subst_into_i2
= 0;
2506 /* Notes that I1, I2 or I3 is a MULT operation. */
2509 int changed_i3_dest
= 0;
2512 rtx_insn
*temp_insn
;
2514 struct insn_link
*link
;
2516 rtx new_other_notes
;
2519 /* Only try four-insn combinations when there's high likelihood of
2520 success. Look for simple insns, such as loads of constants or
2521 binary operations involving a constant. */
2528 if (!flag_expensive_optimizations
)
2531 for (i
= 0; i
< 4; i
++)
2533 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2534 rtx set
= single_set (insn
);
2538 src
= SET_SRC (set
);
2539 if (CONSTANT_P (src
))
2544 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2546 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2547 || GET_CODE (src
) == LSHIFTRT
)
2550 if (ngood
< 2 && nshift
< 2)
2554 /* Exit early if one of the insns involved can't be used for
2556 if (cant_combine_insn_p (i3
)
2557 || cant_combine_insn_p (i2
)
2558 || (i1
&& cant_combine_insn_p (i1
))
2559 || (i0
&& cant_combine_insn_p (i0
))
2560 || likely_spilled_retval_p (i3
))
2564 undobuf
.other_insn
= 0;
2566 /* Reset the hard register usage information. */
2567 CLEAR_HARD_REG_SET (newpat_used_regs
);
2569 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2572 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2573 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2575 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2576 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2578 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2579 INSN_UID (i2
), INSN_UID (i3
));
2582 /* If multiple insns feed into one of I2 or I3, they can be in any
2583 order. To simplify the code below, reorder them in sequence. */
2584 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2585 temp_insn
= i2
, i2
= i0
, i0
= temp_insn
;
2586 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2587 temp_insn
= i1
, i1
= i0
, i0
= temp_insn
;
2588 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2589 temp_insn
= i1
, i1
= i2
, i2
= temp_insn
;
2591 added_links_insn
= 0;
2593 /* First check for one important special case that the code below will
2594 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2595 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2596 we may be able to replace that destination with the destination of I3.
2597 This occurs in the common code where we compute both a quotient and
2598 remainder into a structure, in which case we want to do the computation
2599 directly into the structure to avoid register-register copies.
2601 Note that this case handles both multiple sets in I2 and also cases
2602 where I2 has a number of CLOBBERs inside the PARALLEL.
2604 We make very conservative checks below and only try to handle the
2605 most common cases of this. For example, we only handle the case
2606 where I2 and I3 are adjacent to avoid making difficult register
2609 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2610 && REG_P (SET_SRC (PATTERN (i3
)))
2611 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2612 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2613 && GET_CODE (PATTERN (i2
)) == PARALLEL
2614 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2615 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2616 below would need to check what is inside (and reg_overlap_mentioned_p
2617 doesn't support those codes anyway). Don't allow those destinations;
2618 the resulting insn isn't likely to be recognized anyway. */
2619 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2620 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2621 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2622 SET_DEST (PATTERN (i3
)))
2623 && next_active_insn (i2
) == i3
)
2625 rtx p2
= PATTERN (i2
);
2627 /* Make sure that the destination of I3,
2628 which we are going to substitute into one output of I2,
2629 is not used within another output of I2. We must avoid making this:
2630 (parallel [(set (mem (reg 69)) ...)
2631 (set (reg 69) ...)])
2632 which is not well-defined as to order of actions.
2633 (Besides, reload can't handle output reloads for this.)
2635 The problem can also happen if the dest of I3 is a memory ref,
2636 if another dest in I2 is an indirect memory ref. */
2637 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2638 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2639 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2640 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2641 SET_DEST (XVECEXP (p2
, 0, i
))))
2644 if (i
== XVECLEN (p2
, 0))
2645 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2646 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2647 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2652 subst_low_luid
= DF_INSN_LUID (i2
);
2654 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2655 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2656 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2657 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2659 /* Replace the dest in I2 with our dest and make the resulting
2660 insn the new pattern for I3. Then skip to where we validate
2661 the pattern. Everything was set up above. */
2662 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2664 i3_subst_into_i2
= 1;
2665 goto validate_replacement
;
2669 /* If I2 is setting a pseudo to a constant and I3 is setting some
2670 sub-part of it to another constant, merge them by making a new
2673 && (temp_expr
= single_set (i2
)) != 0
2674 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2675 && GET_CODE (PATTERN (i3
)) == SET
2676 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2677 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2679 rtx dest
= SET_DEST (PATTERN (i3
));
2683 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2685 if (CONST_INT_P (XEXP (dest
, 1))
2686 && CONST_INT_P (XEXP (dest
, 2)))
2688 width
= INTVAL (XEXP (dest
, 1));
2689 offset
= INTVAL (XEXP (dest
, 2));
2690 dest
= XEXP (dest
, 0);
2691 if (BITS_BIG_ENDIAN
)
2692 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2697 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2698 dest
= XEXP (dest
, 0);
2699 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2705 /* If this is the low part, we're done. */
2706 if (subreg_lowpart_p (dest
))
2708 /* Handle the case where inner is twice the size of outer. */
2709 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2710 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2711 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2712 /* Otherwise give up for now. */
2719 rtx inner
= SET_SRC (PATTERN (i3
));
2720 rtx outer
= SET_SRC (temp_expr
);
2723 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2724 std::make_pair (inner
, GET_MODE (dest
)),
2729 subst_low_luid
= DF_INSN_LUID (i2
);
2730 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2731 i2dest
= SET_DEST (temp_expr
);
2732 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2734 /* Replace the source in I2 with the new constant and make the
2735 resulting insn the new pattern for I3. Then skip to where we
2736 validate the pattern. Everything was set up above. */
2737 SUBST (SET_SRC (temp_expr
),
2738 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2740 newpat
= PATTERN (i2
);
2742 /* The dest of I3 has been replaced with the dest of I2. */
2743 changed_i3_dest
= 1;
2744 goto validate_replacement
;
2749 /* If we have no I1 and I2 looks like:
2750 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2752 make up a dummy I1 that is
2755 (set (reg:CC X) (compare:CC Y (const_int 0)))
2757 (We can ignore any trailing CLOBBERs.)
2759 This undoes a previous combination and allows us to match a branch-and-
2762 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2763 && XVECLEN (PATTERN (i2
), 0) >= 2
2764 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2765 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2767 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2768 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2769 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2770 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2771 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2772 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2774 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2775 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2780 /* We make I1 with the same INSN_UID as I2. This gives it
2781 the same DF_INSN_LUID for value tracking. Our fake I1 will
2782 never appear in the insn stream so giving it the same INSN_UID
2783 as I2 will not cause a problem. */
2785 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2786 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2788 INSN_UID (i1
) = INSN_UID (i2
);
2790 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2791 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2792 SET_DEST (PATTERN (i1
)));
2793 SUBST_LINK (LOG_LINKS (i2
), alloc_insn_link (i1
, LOG_LINKS (i2
)));
2798 /* Verify that I2 and I1 are valid for combining. */
2799 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2800 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2802 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2809 /* Record whether I2DEST is used in I2SRC and similarly for the other
2810 cases. Knowing this will help in register status updating below. */
2811 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2812 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2813 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2814 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2815 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2816 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2817 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2818 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2819 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2821 /* For the earlier insns, determine which of the subsequent ones they
2823 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2824 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2825 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2826 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2827 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2829 /* Ensure that I3's pattern can be the destination of combines. */
2830 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2831 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2832 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2833 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2840 /* See if any of the insns is a MULT operation. Unless one is, we will
2841 reject a combination that is, since it must be slower. Be conservative
2843 if (GET_CODE (i2src
) == MULT
2844 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2845 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2846 || (GET_CODE (PATTERN (i3
)) == SET
2847 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2850 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2851 We used to do this EXCEPT in one case: I3 has a post-inc in an
2852 output operand. However, that exception can give rise to insns like
2854 which is a famous insn on the PDP-11 where the value of r3 used as the
2855 source was model-dependent. Avoid this sort of thing. */
2858 if (!(GET_CODE (PATTERN (i3
)) == SET
2859 && REG_P (SET_SRC (PATTERN (i3
)))
2860 && MEM_P (SET_DEST (PATTERN (i3
)))
2861 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2862 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2863 /* It's not the exception. */
2868 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2869 if (REG_NOTE_KIND (link
) == REG_INC
2870 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2872 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2880 /* See if the SETs in I1 or I2 need to be kept around in the merged
2881 instruction: whenever the value set there is still needed past I3.
2882 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2884 For the SET in I1, we have two cases: if I1 and I2 independently feed
2885 into I3, the set in I1 needs to be kept around unless I1DEST dies
2886 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2887 in I1 needs to be kept around unless I1DEST dies or is set in either
2888 I2 or I3. The same considerations apply to I0. */
2890 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2893 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2894 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2899 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2900 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
2901 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
2902 && dead_or_set_p (i2
, i0dest
)));
2906 /* We are about to copy insns for the case where they need to be kept
2907 around. Check that they can be copied in the merged instruction. */
2909 if (targetm
.cannot_copy_insn_p
2910 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2911 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2912 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2918 /* If the set in I2 needs to be kept around, we must make a copy of
2919 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2920 PATTERN (I2), we are only substituting for the original I1DEST, not into
2921 an already-substituted copy. This also prevents making self-referential
2922 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2927 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2928 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2930 i2pat
= copy_rtx (PATTERN (i2
));
2935 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2936 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2938 i1pat
= copy_rtx (PATTERN (i1
));
2943 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2944 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2946 i0pat
= copy_rtx (PATTERN (i0
));
2951 /* Substitute in the latest insn for the regs set by the earlier ones. */
2953 maxreg
= max_reg_num ();
2958 /* Many machines that don't use CC0 have insns that can both perform an
2959 arithmetic operation and set the condition code. These operations will
2960 be represented as a PARALLEL with the first element of the vector
2961 being a COMPARE of an arithmetic operation with the constant zero.
2962 The second element of the vector will set some pseudo to the result
2963 of the same arithmetic operation. If we simplify the COMPARE, we won't
2964 match such a pattern and so will generate an extra insn. Here we test
2965 for this case, where both the comparison and the operation result are
2966 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2967 I2SRC. Later we will make the PARALLEL that contains I2. */
2969 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2970 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2971 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
2972 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2975 rtx
*cc_use_loc
= NULL
;
2976 rtx_insn
*cc_use_insn
= NULL
;
2977 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
2978 machine_mode compare_mode
, orig_compare_mode
;
2979 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
2981 newpat
= PATTERN (i3
);
2982 newpat_dest
= SET_DEST (newpat
);
2983 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
2985 if (undobuf
.other_insn
== 0
2986 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
2989 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
2990 compare_code
= simplify_compare_const (compare_code
,
2991 GET_MODE (i2dest
), op0
, &op1
);
2992 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
2995 /* Do the rest only if op1 is const0_rtx, which may be the
2996 result of simplification. */
2997 if (op1
== const0_rtx
)
2999 /* If a single use of the CC is found, prepare to modify it
3000 when SELECT_CC_MODE returns a new CC-class mode, or when
3001 the above simplify_compare_const() returned a new comparison
3002 operator. undobuf.other_insn is assigned the CC use insn
3003 when modifying it. */
3006 #ifdef SELECT_CC_MODE
3007 machine_mode new_mode
3008 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3009 if (new_mode
!= orig_compare_mode
3010 && can_change_dest_mode (SET_DEST (newpat
),
3011 added_sets_2
, new_mode
))
3013 unsigned int regno
= REGNO (newpat_dest
);
3014 compare_mode
= new_mode
;
3015 if (regno
< FIRST_PSEUDO_REGISTER
)
3016 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3019 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3020 newpat_dest
= regno_reg_rtx
[regno
];
3024 /* Cases for modifying the CC-using comparison. */
3025 if (compare_code
!= orig_compare_code
3026 /* ??? Do we need to verify the zero rtx? */
3027 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3029 /* Replace cc_use_loc with entire new RTX. */
3031 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3032 newpat_dest
, const0_rtx
));
3033 undobuf
.other_insn
= cc_use_insn
;
3035 else if (compare_mode
!= orig_compare_mode
)
3037 /* Just replace the CC reg with a new mode. */
3038 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3039 undobuf
.other_insn
= cc_use_insn
;
3043 /* Now we modify the current newpat:
3044 First, SET_DEST(newpat) is updated if the CC mode has been
3045 altered. For targets without SELECT_CC_MODE, this should be
3047 if (compare_mode
!= orig_compare_mode
)
3048 SUBST (SET_DEST (newpat
), newpat_dest
);
3049 /* This is always done to propagate i2src into newpat. */
3050 SUBST (SET_SRC (newpat
),
3051 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3052 /* Create new version of i2pat if needed; the below PARALLEL
3053 creation needs this to work correctly. */
3054 if (! rtx_equal_p (i2src
, op0
))
3055 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3061 if (i2_is_used
== 0)
3063 /* It is possible that the source of I2 or I1 may be performing
3064 an unneeded operation, such as a ZERO_EXTEND of something
3065 that is known to have the high part zero. Handle that case
3066 by letting subst look at the inner insns.
3068 Another way to do this would be to have a function that tries
3069 to simplify a single insn instead of merging two or more
3070 insns. We don't do this because of the potential of infinite
3071 loops and because of the potential extra memory required.
3072 However, doing it the way we are is a bit of a kludge and
3073 doesn't catch all cases.
3075 But only do this if -fexpensive-optimizations since it slows
3076 things down and doesn't usually win.
3078 This is not done in the COMPARE case above because the
3079 unmodified I2PAT is used in the PARALLEL and so a pattern
3080 with a modified I2SRC would not match. */
3082 if (flag_expensive_optimizations
)
3084 /* Pass pc_rtx so no substitutions are done, just
3088 subst_low_luid
= DF_INSN_LUID (i1
);
3089 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3092 subst_low_luid
= DF_INSN_LUID (i2
);
3093 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3096 n_occurrences
= 0; /* `subst' counts here */
3097 subst_low_luid
= DF_INSN_LUID (i2
);
3099 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3100 copy of I2SRC each time we substitute it, in order to avoid creating
3101 self-referential RTL when we will be substituting I1SRC for I1DEST
3102 later. Likewise if I0 feeds into I2, either directly or indirectly
3103 through I1, and I0DEST is in I0SRC. */
3104 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3105 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3106 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3107 && i0dest_in_i0src
));
3110 /* Record whether I2's body now appears within I3's body. */
3111 i2_is_used
= n_occurrences
;
3114 /* If we already got a failure, don't try to do more. Otherwise, try to
3115 substitute I1 if we have it. */
3117 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3119 /* Check that an autoincrement side-effect on I1 has not been lost.
3120 This happens if I1DEST is mentioned in I2 and dies there, and
3121 has disappeared from the new pattern. */
3122 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3124 && dead_or_set_p (i2
, i1dest
)
3125 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3126 /* Before we can do this substitution, we must redo the test done
3127 above (see detailed comments there) that ensures I1DEST isn't
3128 mentioned in any SETs in NEWPAT that are field assignments. */
3129 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3137 subst_low_luid
= DF_INSN_LUID (i1
);
3139 /* If the following substitution will modify I1SRC, make a copy of it
3140 for the case where it is substituted for I1DEST in I2PAT later. */
3141 if (added_sets_2
&& i1_feeds_i2_n
)
3142 i1src_copy
= copy_rtx (i1src
);
3144 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3145 copy of I1SRC each time we substitute it, in order to avoid creating
3146 self-referential RTL when we will be substituting I0SRC for I0DEST
3148 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3149 i0_feeds_i1_n
&& i0dest_in_i0src
);
3152 /* Record whether I1's body now appears within I3's body. */
3153 i1_is_used
= n_occurrences
;
3156 /* Likewise for I0 if we have it. */
3158 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3160 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3161 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3162 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3163 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3164 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3171 /* If the following substitution will modify I0SRC, make a copy of it
3172 for the case where it is substituted for I0DEST in I1PAT later. */
3173 if (added_sets_1
&& i0_feeds_i1_n
)
3174 i0src_copy
= copy_rtx (i0src
);
3175 /* And a copy for I0DEST in I2PAT substitution. */
3176 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3177 || (i0_feeds_i2_n
)))
3178 i0src_copy2
= copy_rtx (i0src
);
3181 subst_low_luid
= DF_INSN_LUID (i0
);
3182 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3186 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3187 to count all the ways that I2SRC and I1SRC can be used. */
3188 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3189 && i2_is_used
+ added_sets_2
> 1)
3190 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3191 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3193 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3194 && (n_occurrences
+ added_sets_0
3195 + (added_sets_1
&& i0_feeds_i1_n
)
3196 + (added_sets_2
&& i0_feeds_i2_n
)
3198 /* Fail if we tried to make a new register. */
3199 || max_reg_num () != maxreg
3200 /* Fail if we couldn't do something and have a CLOBBER. */
3201 || GET_CODE (newpat
) == CLOBBER
3202 /* Fail if this new pattern is a MULT and we didn't have one before
3203 at the outer level. */
3204 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3211 /* If the actions of the earlier insns must be kept
3212 in addition to substituting them into the latest one,
3213 we must make a new PARALLEL for the latest insn
3214 to hold additional the SETs. */
3216 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3218 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3221 if (GET_CODE (newpat
) == PARALLEL
)
3223 rtvec old
= XVEC (newpat
, 0);
3224 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3225 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3226 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3227 sizeof (old
->elem
[0]) * old
->num_elem
);
3232 total_sets
= 1 + extra_sets
;
3233 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3234 XVECEXP (newpat
, 0, 0) = old
;
3238 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3244 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3246 XVECEXP (newpat
, 0, --total_sets
) = t
;
3252 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3253 i0_feeds_i1_n
&& i0dest_in_i0src
);
3254 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3255 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3257 XVECEXP (newpat
, 0, --total_sets
) = t
;
3261 validate_replacement
:
3263 /* Note which hard regs this insn has as inputs. */
3264 mark_used_regs_combine (newpat
);
3266 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3267 consider splitting this pattern, we might need these clobbers. */
3268 if (i1
&& GET_CODE (newpat
) == PARALLEL
3269 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3271 int len
= XVECLEN (newpat
, 0);
3273 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3274 for (i
= 0; i
< len
; i
++)
3275 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3278 /* Is the result of combination a valid instruction? */
3279 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3281 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3282 the second SET's destination is a register that is unused and isn't
3283 marked as an instruction that might trap in an EH region. In that case,
3284 we just need the first SET. This can occur when simplifying a divmod
3285 insn. We *must* test for this case here because the code below that
3286 splits two independent SETs doesn't handle this case correctly when it
3287 updates the register status.
3289 It's pointless doing this if we originally had two sets, one from
3290 i3, and one from i2. Combining then splitting the parallel results
3291 in the original i2 again plus an invalid insn (which we delete).
3292 The net effect is only to move instructions around, which makes
3293 debug info less accurate.
3295 Also check the case where the first SET's destination is unused.
3296 That would not cause incorrect code, but does cause an unneeded
3299 if (insn_code_number
< 0
3300 && !(added_sets_2
&& i1
== 0)
3301 && GET_CODE (newpat
) == PARALLEL
3302 && XVECLEN (newpat
, 0) == 2
3303 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3304 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3305 && asm_noperands (newpat
) < 0)
3307 rtx set0
= XVECEXP (newpat
, 0, 0);
3308 rtx set1
= XVECEXP (newpat
, 0, 1);
3310 if (((REG_P (SET_DEST (set1
))
3311 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3312 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3313 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3314 && insn_nothrow_p (i3
)
3315 && !side_effects_p (SET_SRC (set1
)))
3318 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3321 else if (((REG_P (SET_DEST (set0
))
3322 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3323 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3324 && find_reg_note (i3
, REG_UNUSED
,
3325 SUBREG_REG (SET_DEST (set0
)))))
3326 && insn_nothrow_p (i3
)
3327 && !side_effects_p (SET_SRC (set0
)))
3330 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3332 if (insn_code_number
>= 0)
3333 changed_i3_dest
= 1;
3337 /* If we were combining three insns and the result is a simple SET
3338 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3339 insns. There are two ways to do this. It can be split using a
3340 machine-specific method (like when you have an addition of a large
3341 constant) or by combine in the function find_split_point. */
3343 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3344 && asm_noperands (newpat
) < 0)
3346 rtx parallel
, *split
;
3347 rtx_insn
*m_split_insn
;
3349 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3350 use I2DEST as a scratch register will help. In the latter case,
3351 convert I2DEST to the mode of the source of NEWPAT if we can. */
3353 m_split_insn
= combine_split_insns (newpat
, i3
);
3355 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3356 inputs of NEWPAT. */
3358 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3359 possible to try that as a scratch reg. This would require adding
3360 more code to make it work though. */
3362 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3364 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3366 /* First try to split using the original register as a
3367 scratch register. */
3368 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3369 gen_rtvec (2, newpat
,
3370 gen_rtx_CLOBBER (VOIDmode
,
3372 m_split_insn
= combine_split_insns (parallel
, i3
);
3374 /* If that didn't work, try changing the mode of I2DEST if
3376 if (m_split_insn
== 0
3377 && new_mode
!= GET_MODE (i2dest
)
3378 && new_mode
!= VOIDmode
3379 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3381 machine_mode old_mode
= GET_MODE (i2dest
);
3384 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3385 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3388 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3389 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3392 parallel
= (gen_rtx_PARALLEL
3394 gen_rtvec (2, newpat
,
3395 gen_rtx_CLOBBER (VOIDmode
,
3397 m_split_insn
= combine_split_insns (parallel
, i3
);
3399 if (m_split_insn
== 0
3400 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3404 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3405 buf
= undobuf
.undos
;
3406 undobuf
.undos
= buf
->next
;
3407 buf
->next
= undobuf
.frees
;
3408 undobuf
.frees
= buf
;
3412 i2scratch
= m_split_insn
!= 0;
3415 /* If recog_for_combine has discarded clobbers, try to use them
3416 again for the split. */
3417 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3419 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3420 m_split_insn
= combine_split_insns (parallel
, i3
);
3423 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3425 rtx m_split_pat
= PATTERN (m_split_insn
);
3426 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3427 if (insn_code_number
>= 0)
3428 newpat
= m_split_pat
;
3430 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3431 && (next_nonnote_nondebug_insn (i2
) == i3
3432 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3435 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3436 newi2pat
= PATTERN (m_split_insn
);
3438 i3set
= single_set (NEXT_INSN (m_split_insn
));
3439 i2set
= single_set (m_split_insn
);
3441 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3443 /* If I2 or I3 has multiple SETs, we won't know how to track
3444 register status, so don't use these insns. If I2's destination
3445 is used between I2 and I3, we also can't use these insns. */
3447 if (i2_code_number
>= 0 && i2set
&& i3set
3448 && (next_nonnote_nondebug_insn (i2
) == i3
3449 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3450 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3452 if (insn_code_number
>= 0)
3455 /* It is possible that both insns now set the destination of I3.
3456 If so, we must show an extra use of it. */
3458 if (insn_code_number
>= 0)
3460 rtx new_i3_dest
= SET_DEST (i3set
);
3461 rtx new_i2_dest
= SET_DEST (i2set
);
3463 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3464 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3465 || GET_CODE (new_i3_dest
) == SUBREG
)
3466 new_i3_dest
= XEXP (new_i3_dest
, 0);
3468 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3469 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3470 || GET_CODE (new_i2_dest
) == SUBREG
)
3471 new_i2_dest
= XEXP (new_i2_dest
, 0);
3473 if (REG_P (new_i3_dest
)
3474 && REG_P (new_i2_dest
)
3475 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3476 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3480 /* If we can split it and use I2DEST, go ahead and see if that
3481 helps things be recognized. Verify that none of the registers
3482 are set between I2 and I3. */
3483 if (insn_code_number
< 0
3484 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3488 /* We need I2DEST in the proper mode. If it is a hard register
3489 or the only use of a pseudo, we can change its mode.
3490 Make sure we don't change a hard register to have a mode that
3491 isn't valid for it, or change the number of registers. */
3492 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3493 || GET_MODE (*split
) == VOIDmode
3494 || can_change_dest_mode (i2dest
, added_sets_2
,
3496 && (next_nonnote_nondebug_insn (i2
) == i3
3497 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3498 /* We can't overwrite I2DEST if its value is still used by
3500 && ! reg_referenced_p (i2dest
, newpat
))
3502 rtx newdest
= i2dest
;
3503 enum rtx_code split_code
= GET_CODE (*split
);
3504 machine_mode split_mode
= GET_MODE (*split
);
3505 bool subst_done
= false;
3506 newi2pat
= NULL_RTX
;
3510 /* *SPLIT may be part of I2SRC, so make sure we have the
3511 original expression around for later debug processing.
3512 We should not need I2SRC any more in other cases. */
3513 if (MAY_HAVE_DEBUG_INSNS
)
3514 i2src
= copy_rtx (i2src
);
3518 /* Get NEWDEST as a register in the proper mode. We have already
3519 validated that we can do this. */
3520 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3522 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3523 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3526 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3527 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3531 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3532 an ASHIFT. This can occur if it was inside a PLUS and hence
3533 appeared to be a memory address. This is a kludge. */
3534 if (split_code
== MULT
3535 && CONST_INT_P (XEXP (*split
, 1))
3536 && INTVAL (XEXP (*split
, 1)) > 0
3537 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3539 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3540 XEXP (*split
, 0), GEN_INT (i
)));
3541 /* Update split_code because we may not have a multiply
3543 split_code
= GET_CODE (*split
);
3546 #ifdef INSN_SCHEDULING
3547 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3548 be written as a ZERO_EXTEND. */
3549 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3551 #ifdef LOAD_EXTEND_OP
3552 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3553 what it really is. */
3554 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3556 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3557 SUBREG_REG (*split
)));
3560 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3561 SUBREG_REG (*split
)));
3565 /* Attempt to split binary operators using arithmetic identities. */
3566 if (BINARY_P (SET_SRC (newpat
))
3567 && split_mode
== GET_MODE (SET_SRC (newpat
))
3568 && ! side_effects_p (SET_SRC (newpat
)))
3570 rtx setsrc
= SET_SRC (newpat
);
3571 machine_mode mode
= GET_MODE (setsrc
);
3572 enum rtx_code code
= GET_CODE (setsrc
);
3573 rtx src_op0
= XEXP (setsrc
, 0);
3574 rtx src_op1
= XEXP (setsrc
, 1);
3576 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3577 if (rtx_equal_p (src_op0
, src_op1
))
3579 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3580 SUBST (XEXP (setsrc
, 0), newdest
);
3581 SUBST (XEXP (setsrc
, 1), newdest
);
3584 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3585 else if ((code
== PLUS
|| code
== MULT
)
3586 && GET_CODE (src_op0
) == code
3587 && GET_CODE (XEXP (src_op0
, 0)) == code
3588 && (INTEGRAL_MODE_P (mode
)
3589 || (FLOAT_MODE_P (mode
)
3590 && flag_unsafe_math_optimizations
)))
3592 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3593 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3594 rtx r
= XEXP (src_op0
, 1);
3597 /* Split both "((X op Y) op X) op Y" and
3598 "((X op Y) op Y) op X" as "T op T" where T is
3600 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3601 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3603 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3605 SUBST (XEXP (setsrc
, 0), newdest
);
3606 SUBST (XEXP (setsrc
, 1), newdest
);
3609 /* Split "((X op X) op Y) op Y)" as "T op T" where
3611 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3613 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3614 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3615 SUBST (XEXP (setsrc
, 0), newdest
);
3616 SUBST (XEXP (setsrc
, 1), newdest
);
3624 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3625 SUBST (*split
, newdest
);
3628 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3630 /* recog_for_combine might have added CLOBBERs to newi2pat.
3631 Make sure NEWPAT does not depend on the clobbered regs. */
3632 if (GET_CODE (newi2pat
) == PARALLEL
)
3633 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3634 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3636 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3637 if (reg_overlap_mentioned_p (reg
, newpat
))
3644 /* If the split point was a MULT and we didn't have one before,
3645 don't use one now. */
3646 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3647 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3651 /* Check for a case where we loaded from memory in a narrow mode and
3652 then sign extended it, but we need both registers. In that case,
3653 we have a PARALLEL with both loads from the same memory location.
3654 We can split this into a load from memory followed by a register-register
3655 copy. This saves at least one insn, more if register allocation can
3658 We cannot do this if the destination of the first assignment is a
3659 condition code register or cc0. We eliminate this case by making sure
3660 the SET_DEST and SET_SRC have the same mode.
3662 We cannot do this if the destination of the second assignment is
3663 a register that we have already assumed is zero-extended. Similarly
3664 for a SUBREG of such a register. */
3666 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3667 && GET_CODE (newpat
) == PARALLEL
3668 && XVECLEN (newpat
, 0) == 2
3669 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3670 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3671 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3672 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3673 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3674 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3675 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3676 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3678 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3679 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3680 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3682 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3683 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3684 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3685 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3686 != GET_MODE_MASK (word_mode
))))
3687 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3688 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3690 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3691 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3692 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3693 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3694 != GET_MODE_MASK (word_mode
)))))
3695 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3696 SET_SRC (XVECEXP (newpat
, 0, 1)))
3697 && ! find_reg_note (i3
, REG_UNUSED
,
3698 SET_DEST (XVECEXP (newpat
, 0, 0))))
3702 newi2pat
= XVECEXP (newpat
, 0, 0);
3703 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3704 newpat
= XVECEXP (newpat
, 0, 1);
3705 SUBST (SET_SRC (newpat
),
3706 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3707 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3709 if (i2_code_number
>= 0)
3710 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3712 if (insn_code_number
>= 0)
3716 /* Similarly, check for a case where we have a PARALLEL of two independent
3717 SETs but we started with three insns. In this case, we can do the sets
3718 as two separate insns. This case occurs when some SET allows two
3719 other insns to combine, but the destination of that SET is still live. */
3721 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3722 && GET_CODE (newpat
) == PARALLEL
3723 && XVECLEN (newpat
, 0) == 2
3724 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3725 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3726 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3727 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3728 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3729 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3730 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3731 XVECEXP (newpat
, 0, 0))
3732 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3733 XVECEXP (newpat
, 0, 1))
3734 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3735 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3737 rtx set0
= XVECEXP (newpat
, 0, 0);
3738 rtx set1
= XVECEXP (newpat
, 0, 1);
3740 /* Normally, it doesn't matter which of the two is done first,
3741 but the one that references cc0 can't be the second, and
3742 one which uses any regs/memory set in between i2 and i3 can't
3743 be first. The PARALLEL might also have been pre-existing in i3,
3744 so we need to make sure that we won't wrongly hoist a SET to i2
3745 that would conflict with a death note present in there. */
3746 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3747 && !(REG_P (SET_DEST (set1
))
3748 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3749 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3750 && find_reg_note (i2
, REG_DEAD
,
3751 SUBREG_REG (SET_DEST (set1
))))
3753 && !reg_referenced_p (cc0_rtx
, set0
)
3755 /* If I3 is a jump, ensure that set0 is a jump so that
3756 we do not create invalid RTL. */
3757 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3763 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3764 && !(REG_P (SET_DEST (set0
))
3765 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3766 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3767 && find_reg_note (i2
, REG_DEAD
,
3768 SUBREG_REG (SET_DEST (set0
))))
3770 && !reg_referenced_p (cc0_rtx
, set1
)
3772 /* If I3 is a jump, ensure that set1 is a jump so that
3773 we do not create invalid RTL. */
3774 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3786 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3788 if (i2_code_number
>= 0)
3790 /* recog_for_combine might have added CLOBBERs to newi2pat.
3791 Make sure NEWPAT does not depend on the clobbered regs. */
3792 if (GET_CODE (newi2pat
) == PARALLEL
)
3794 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3795 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3797 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3798 if (reg_overlap_mentioned_p (reg
, newpat
))
3806 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3810 /* If it still isn't recognized, fail and change things back the way they
3812 if ((insn_code_number
< 0
3813 /* Is the result a reasonable ASM_OPERANDS? */
3814 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3820 /* If we had to change another insn, make sure it is valid also. */
3821 if (undobuf
.other_insn
)
3823 CLEAR_HARD_REG_SET (newpat_used_regs
);
3825 other_pat
= PATTERN (undobuf
.other_insn
);
3826 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3829 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3837 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3838 they are adjacent to each other or not. */
3840 rtx_insn
*p
= prev_nonnote_insn (i3
);
3841 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3842 && sets_cc0_p (newi2pat
))
3850 /* Only allow this combination if insn_rtx_costs reports that the
3851 replacement instructions are cheaper than the originals. */
3852 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3858 if (MAY_HAVE_DEBUG_INSNS
)
3862 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3863 if (undo
->kind
== UNDO_MODE
)
3865 rtx reg
= *undo
->where
.r
;
3866 machine_mode new_mode
= GET_MODE (reg
);
3867 machine_mode old_mode
= undo
->old_contents
.m
;
3869 /* Temporarily revert mode back. */
3870 adjust_reg_mode (reg
, old_mode
);
3872 if (reg
== i2dest
&& i2scratch
)
3874 /* If we used i2dest as a scratch register with a
3875 different mode, substitute it for the original
3876 i2src while its original mode is temporarily
3877 restored, and then clear i2scratch so that we don't
3878 do it again later. */
3879 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
3882 /* Put back the new mode. */
3883 adjust_reg_mode (reg
, new_mode
);
3887 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3888 rtx_insn
*first
, *last
;
3893 last
= last_combined_insn
;
3898 last
= undobuf
.other_insn
;
3900 if (DF_INSN_LUID (last
)
3901 < DF_INSN_LUID (last_combined_insn
))
3902 last
= last_combined_insn
;
3905 /* We're dealing with a reg that changed mode but not
3906 meaning, so we want to turn it into a subreg for
3907 the new mode. However, because of REG sharing and
3908 because its mode had already changed, we have to do
3909 it in two steps. First, replace any debug uses of
3910 reg, with its original mode temporarily restored,
3911 with this copy we have created; then, replace the
3912 copy with the SUBREG of the original shared reg,
3913 once again changed to the new mode. */
3914 propagate_for_debug (first
, last
, reg
, tempreg
,
3916 adjust_reg_mode (reg
, new_mode
);
3917 propagate_for_debug (first
, last
, tempreg
,
3918 lowpart_subreg (old_mode
, reg
, new_mode
),
3924 /* If we will be able to accept this, we have made a
3925 change to the destination of I3. This requires us to
3926 do a few adjustments. */
3928 if (changed_i3_dest
)
3930 PATTERN (i3
) = newpat
;
3931 adjust_for_new_dest (i3
);
3934 /* We now know that we can do this combination. Merge the insns and
3935 update the status of registers and LOG_LINKS. */
3937 if (undobuf
.other_insn
)
3941 PATTERN (undobuf
.other_insn
) = other_pat
;
3943 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
3944 ensure that they are still valid. Then add any non-duplicate
3945 notes added by recog_for_combine. */
3946 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3948 next
= XEXP (note
, 1);
3950 if ((REG_NOTE_KIND (note
) == REG_DEAD
3951 && !reg_referenced_p (XEXP (note
, 0),
3952 PATTERN (undobuf
.other_insn
)))
3953 ||(REG_NOTE_KIND (note
) == REG_UNUSED
3954 && !reg_set_p (XEXP (note
, 0),
3955 PATTERN (undobuf
.other_insn
))))
3956 remove_note (undobuf
.other_insn
, note
);
3959 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3960 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
3967 struct insn_link
*link
;
3970 /* I3 now uses what used to be its destination and which is now
3971 I2's destination. This requires us to do a few adjustments. */
3972 PATTERN (i3
) = newpat
;
3973 adjust_for_new_dest (i3
);
3975 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3978 However, some later insn might be using I2's dest and have
3979 a LOG_LINK pointing at I3. We must remove this link.
3980 The simplest way to remove the link is to point it at I1,
3981 which we know will be a NOTE. */
3983 /* newi2pat is usually a SET here; however, recog_for_combine might
3984 have added some clobbers. */
3985 if (GET_CODE (newi2pat
) == PARALLEL
)
3986 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3988 ni2dest
= SET_DEST (newi2pat
);
3990 for (insn
= NEXT_INSN (i3
);
3991 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
3992 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3993 insn
= NEXT_INSN (insn
))
3995 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3997 FOR_EACH_LOG_LINK (link
, insn
)
3998 if (link
->insn
== i3
)
4007 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4008 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4011 /* Compute which registers we expect to eliminate. newi2pat may be setting
4012 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4013 same as i3dest, in which case newi2pat may be setting i1dest. */
4014 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4015 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4018 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4019 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4022 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
4023 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4027 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4029 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4030 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4032 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4034 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4036 /* Ensure that we do not have something that should not be shared but
4037 occurs multiple times in the new insns. Check this by first
4038 resetting all the `used' flags and then copying anything is shared. */
4040 reset_used_flags (i3notes
);
4041 reset_used_flags (i2notes
);
4042 reset_used_flags (i1notes
);
4043 reset_used_flags (i0notes
);
4044 reset_used_flags (newpat
);
4045 reset_used_flags (newi2pat
);
4046 if (undobuf
.other_insn
)
4047 reset_used_flags (PATTERN (undobuf
.other_insn
));
4049 i3notes
= copy_rtx_if_shared (i3notes
);
4050 i2notes
= copy_rtx_if_shared (i2notes
);
4051 i1notes
= copy_rtx_if_shared (i1notes
);
4052 i0notes
= copy_rtx_if_shared (i0notes
);
4053 newpat
= copy_rtx_if_shared (newpat
);
4054 newi2pat
= copy_rtx_if_shared (newi2pat
);
4055 if (undobuf
.other_insn
)
4056 reset_used_flags (PATTERN (undobuf
.other_insn
));
4058 INSN_CODE (i3
) = insn_code_number
;
4059 PATTERN (i3
) = newpat
;
4061 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4063 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4065 reset_used_flags (call_usage
);
4066 call_usage
= copy_rtx (call_usage
);
4070 /* I2SRC must still be meaningful at this point. Some splitting
4071 operations can invalidate I2SRC, but those operations do not
4074 replace_rtx (call_usage
, i2dest
, i2src
);
4078 replace_rtx (call_usage
, i1dest
, i1src
);
4080 replace_rtx (call_usage
, i0dest
, i0src
);
4082 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4085 if (undobuf
.other_insn
)
4086 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4088 /* We had one special case above where I2 had more than one set and
4089 we replaced a destination of one of those sets with the destination
4090 of I3. In that case, we have to update LOG_LINKS of insns later
4091 in this basic block. Note that this (expensive) case is rare.
4093 Also, in this case, we must pretend that all REG_NOTEs for I2
4094 actually came from I3, so that REG_UNUSED notes from I2 will be
4095 properly handled. */
4097 if (i3_subst_into_i2
)
4099 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4100 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4101 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4102 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4103 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4104 && ! find_reg_note (i2
, REG_UNUSED
,
4105 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4106 for (temp_insn
= NEXT_INSN (i2
);
4108 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4109 || BB_HEAD (this_basic_block
) != temp_insn
);
4110 temp_insn
= NEXT_INSN (temp_insn
))
4111 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4112 FOR_EACH_LOG_LINK (link
, temp_insn
)
4113 if (link
->insn
== i2
)
4119 while (XEXP (link
, 1))
4120 link
= XEXP (link
, 1);
4121 XEXP (link
, 1) = i2notes
;
4128 LOG_LINKS (i3
) = NULL
;
4130 LOG_LINKS (i2
) = NULL
;
4135 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4136 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4138 INSN_CODE (i2
) = i2_code_number
;
4139 PATTERN (i2
) = newi2pat
;
4143 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4144 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4146 SET_INSN_DELETED (i2
);
4151 LOG_LINKS (i1
) = NULL
;
4153 if (MAY_HAVE_DEBUG_INSNS
)
4154 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4156 SET_INSN_DELETED (i1
);
4161 LOG_LINKS (i0
) = NULL
;
4163 if (MAY_HAVE_DEBUG_INSNS
)
4164 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4166 SET_INSN_DELETED (i0
);
4169 /* Get death notes for everything that is now used in either I3 or
4170 I2 and used to die in a previous insn. If we built two new
4171 patterns, move from I1 to I2 then I2 to I3 so that we get the
4172 proper movement on registers that I2 modifies. */
4175 from_luid
= DF_INSN_LUID (i0
);
4177 from_luid
= DF_INSN_LUID (i1
);
4179 from_luid
= DF_INSN_LUID (i2
);
4181 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4182 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4184 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4186 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4187 elim_i2
, elim_i1
, elim_i0
);
4189 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4190 elim_i2
, elim_i1
, elim_i0
);
4192 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4193 elim_i2
, elim_i1
, elim_i0
);
4195 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4196 elim_i2
, elim_i1
, elim_i0
);
4198 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4199 elim_i2
, elim_i1
, elim_i0
);
4201 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4202 know these are REG_UNUSED and want them to go to the desired insn,
4203 so we always pass it as i3. */
4205 if (newi2pat
&& new_i2_notes
)
4206 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4210 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4213 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4214 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4215 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4216 in that case, it might delete I2. Similarly for I2 and I1.
4217 Show an additional death due to the REG_DEAD note we make here. If
4218 we discard it in distribute_notes, we will decrement it again. */
4222 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4223 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4224 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4227 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4228 elim_i2
, elim_i1
, elim_i0
);
4231 if (i2dest_in_i2src
)
4233 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4234 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4235 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4236 NULL_RTX
, NULL_RTX
);
4238 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4239 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4242 if (i1dest_in_i1src
)
4244 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4245 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4246 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4247 NULL_RTX
, NULL_RTX
);
4249 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4250 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4253 if (i0dest_in_i0src
)
4255 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4256 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4257 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4258 NULL_RTX
, NULL_RTX
);
4260 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4261 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4264 distribute_links (i3links
);
4265 distribute_links (i2links
);
4266 distribute_links (i1links
);
4267 distribute_links (i0links
);
4271 struct insn_link
*link
;
4272 rtx_insn
*i2_insn
= 0;
4273 rtx i2_val
= 0, set
;
4275 /* The insn that used to set this register doesn't exist, and
4276 this life of the register may not exist either. See if one of
4277 I3's links points to an insn that sets I2DEST. If it does,
4278 that is now the last known value for I2DEST. If we don't update
4279 this and I2 set the register to a value that depended on its old
4280 contents, we will get confused. If this insn is used, thing
4281 will be set correctly in combine_instructions. */
4282 FOR_EACH_LOG_LINK (link
, i3
)
4283 if ((set
= single_set (link
->insn
)) != 0
4284 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4285 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4287 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4289 /* If the reg formerly set in I2 died only once and that was in I3,
4290 zero its use count so it won't make `reload' do any work. */
4292 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4293 && ! i2dest_in_i2src
)
4294 INC_REG_N_SETS (REGNO (i2dest
), -1);
4297 if (i1
&& REG_P (i1dest
))
4299 struct insn_link
*link
;
4300 rtx_insn
*i1_insn
= 0;
4301 rtx i1_val
= 0, set
;
4303 FOR_EACH_LOG_LINK (link
, i3
)
4304 if ((set
= single_set (link
->insn
)) != 0
4305 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4306 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4308 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4310 if (! added_sets_1
&& ! i1dest_in_i1src
)
4311 INC_REG_N_SETS (REGNO (i1dest
), -1);
4314 if (i0
&& REG_P (i0dest
))
4316 struct insn_link
*link
;
4317 rtx_insn
*i0_insn
= 0;
4318 rtx i0_val
= 0, set
;
4320 FOR_EACH_LOG_LINK (link
, i3
)
4321 if ((set
= single_set (link
->insn
)) != 0
4322 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4323 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4325 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4327 if (! added_sets_0
&& ! i0dest_in_i0src
)
4328 INC_REG_N_SETS (REGNO (i0dest
), -1);
4331 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4332 been made to this insn. The order is important, because newi2pat
4333 can affect nonzero_bits of newpat. */
4335 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4336 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4339 if (undobuf
.other_insn
!= NULL_RTX
)
4343 fprintf (dump_file
, "modifying other_insn ");
4344 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4346 df_insn_rescan (undobuf
.other_insn
);
4349 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4353 fprintf (dump_file
, "modifying insn i0 ");
4354 dump_insn_slim (dump_file
, i0
);
4356 df_insn_rescan (i0
);
4359 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4363 fprintf (dump_file
, "modifying insn i1 ");
4364 dump_insn_slim (dump_file
, i1
);
4366 df_insn_rescan (i1
);
4369 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4373 fprintf (dump_file
, "modifying insn i2 ");
4374 dump_insn_slim (dump_file
, i2
);
4376 df_insn_rescan (i2
);
4379 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4383 fprintf (dump_file
, "modifying insn i3 ");
4384 dump_insn_slim (dump_file
, i3
);
4386 df_insn_rescan (i3
);
4389 /* Set new_direct_jump_p if a new return or simple jump instruction
4390 has been created. Adjust the CFG accordingly. */
4391 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4393 *new_direct_jump_p
= 1;
4394 mark_jump_label (PATTERN (i3
), i3
, 0);
4395 update_cfg_for_uncondjump (i3
);
4398 if (undobuf
.other_insn
!= NULL_RTX
4399 && (returnjump_p (undobuf
.other_insn
)
4400 || any_uncondjump_p (undobuf
.other_insn
)))
4402 *new_direct_jump_p
= 1;
4403 update_cfg_for_uncondjump (undobuf
.other_insn
);
4406 /* A noop might also need cleaning up of CFG, if it comes from the
4407 simplification of a jump. */
4409 && GET_CODE (newpat
) == SET
4410 && SET_SRC (newpat
) == pc_rtx
4411 && SET_DEST (newpat
) == pc_rtx
)
4413 *new_direct_jump_p
= 1;
4414 update_cfg_for_uncondjump (i3
);
4417 if (undobuf
.other_insn
!= NULL_RTX
4418 && JUMP_P (undobuf
.other_insn
)
4419 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4420 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4421 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4423 *new_direct_jump_p
= 1;
4424 update_cfg_for_uncondjump (undobuf
.other_insn
);
4427 combine_successes
++;
4430 if (added_links_insn
4431 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4432 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4433 return added_links_insn
;
4435 return newi2pat
? i2
: i3
;
4438 /* Undo all the modifications recorded in undobuf. */
4443 struct undo
*undo
, *next
;
4445 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4451 *undo
->where
.r
= undo
->old_contents
.r
;
4454 *undo
->where
.i
= undo
->old_contents
.i
;
4457 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4460 *undo
->where
.l
= undo
->old_contents
.l
;
4466 undo
->next
= undobuf
.frees
;
4467 undobuf
.frees
= undo
;
4473 /* We've committed to accepting the changes we made. Move all
4474 of the undos to the free list. */
4479 struct undo
*undo
, *next
;
4481 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4484 undo
->next
= undobuf
.frees
;
4485 undobuf
.frees
= undo
;
4490 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4491 where we have an arithmetic expression and return that point. LOC will
4494 try_combine will call this function to see if an insn can be split into
4498 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4501 enum rtx_code code
= GET_CODE (x
);
4503 unsigned HOST_WIDE_INT len
= 0;
4504 HOST_WIDE_INT pos
= 0;
4506 rtx inner
= NULL_RTX
;
4508 /* First special-case some codes. */
4512 #ifdef INSN_SCHEDULING
4513 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4515 if (MEM_P (SUBREG_REG (x
)))
4518 return find_split_point (&SUBREG_REG (x
), insn
, false);
4522 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4523 using LO_SUM and HIGH. */
4524 if (GET_CODE (XEXP (x
, 0)) == CONST
4525 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4527 machine_mode address_mode
= get_address_mode (x
);
4530 gen_rtx_LO_SUM (address_mode
,
4531 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4533 return &XEXP (XEXP (x
, 0), 0);
4537 /* If we have a PLUS whose second operand is a constant and the
4538 address is not valid, perhaps will can split it up using
4539 the machine-specific way to split large constants. We use
4540 the first pseudo-reg (one of the virtual regs) as a placeholder;
4541 it will not remain in the result. */
4542 if (GET_CODE (XEXP (x
, 0)) == PLUS
4543 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4544 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4545 MEM_ADDR_SPACE (x
)))
4547 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4548 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4552 /* This should have produced two insns, each of which sets our
4553 placeholder. If the source of the second is a valid address,
4554 we can make put both sources together and make a split point
4558 && NEXT_INSN (seq
) != NULL_RTX
4559 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4560 && NONJUMP_INSN_P (seq
)
4561 && GET_CODE (PATTERN (seq
)) == SET
4562 && SET_DEST (PATTERN (seq
)) == reg
4563 && ! reg_mentioned_p (reg
,
4564 SET_SRC (PATTERN (seq
)))
4565 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4566 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4567 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4568 && memory_address_addr_space_p
4569 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4570 MEM_ADDR_SPACE (x
)))
4572 rtx src1
= SET_SRC (PATTERN (seq
));
4573 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4575 /* Replace the placeholder in SRC2 with SRC1. If we can
4576 find where in SRC2 it was placed, that can become our
4577 split point and we can replace this address with SRC2.
4578 Just try two obvious places. */
4580 src2
= replace_rtx (src2
, reg
, src1
);
4582 if (XEXP (src2
, 0) == src1
)
4583 split
= &XEXP (src2
, 0);
4584 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4585 && XEXP (XEXP (src2
, 0), 0) == src1
)
4586 split
= &XEXP (XEXP (src2
, 0), 0);
4590 SUBST (XEXP (x
, 0), src2
);
4595 /* If that didn't work, perhaps the first operand is complex and
4596 needs to be computed separately, so make a split point there.
4597 This will occur on machines that just support REG + CONST
4598 and have a constant moved through some previous computation. */
4600 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4601 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4602 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4603 return &XEXP (XEXP (x
, 0), 0);
4606 /* If we have a PLUS whose first operand is complex, try computing it
4607 separately by making a split there. */
4608 if (GET_CODE (XEXP (x
, 0)) == PLUS
4609 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4611 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4612 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4613 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4614 return &XEXP (XEXP (x
, 0), 0);
4619 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4620 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4621 we need to put the operand into a register. So split at that
4624 if (SET_DEST (x
) == cc0_rtx
4625 && GET_CODE (SET_SRC (x
)) != COMPARE
4626 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4627 && !OBJECT_P (SET_SRC (x
))
4628 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4629 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4630 return &SET_SRC (x
);
4633 /* See if we can split SET_SRC as it stands. */
4634 split
= find_split_point (&SET_SRC (x
), insn
, true);
4635 if (split
&& split
!= &SET_SRC (x
))
4638 /* See if we can split SET_DEST as it stands. */
4639 split
= find_split_point (&SET_DEST (x
), insn
, false);
4640 if (split
&& split
!= &SET_DEST (x
))
4643 /* See if this is a bitfield assignment with everything constant. If
4644 so, this is an IOR of an AND, so split it into that. */
4645 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4646 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4647 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4648 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4649 && CONST_INT_P (SET_SRC (x
))
4650 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4651 + INTVAL (XEXP (SET_DEST (x
), 2)))
4652 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4653 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4655 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4656 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4657 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4658 rtx dest
= XEXP (SET_DEST (x
), 0);
4659 machine_mode mode
= GET_MODE (dest
);
4660 unsigned HOST_WIDE_INT mask
4661 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4664 if (BITS_BIG_ENDIAN
)
4665 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4667 or_mask
= gen_int_mode (src
<< pos
, mode
);
4670 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4673 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4675 simplify_gen_binary (IOR
, mode
,
4676 simplify_gen_binary (AND
, mode
,
4681 SUBST (SET_DEST (x
), dest
);
4683 split
= find_split_point (&SET_SRC (x
), insn
, true);
4684 if (split
&& split
!= &SET_SRC (x
))
4688 /* Otherwise, see if this is an operation that we can split into two.
4689 If so, try to split that. */
4690 code
= GET_CODE (SET_SRC (x
));
4695 /* If we are AND'ing with a large constant that is only a single
4696 bit and the result is only being used in a context where we
4697 need to know if it is zero or nonzero, replace it with a bit
4698 extraction. This will avoid the large constant, which might
4699 have taken more than one insn to make. If the constant were
4700 not a valid argument to the AND but took only one insn to make,
4701 this is no worse, but if it took more than one insn, it will
4704 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4705 && REG_P (XEXP (SET_SRC (x
), 0))
4706 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4707 && REG_P (SET_DEST (x
))
4708 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4709 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4710 && XEXP (*split
, 0) == SET_DEST (x
)
4711 && XEXP (*split
, 1) == const0_rtx
)
4713 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4714 XEXP (SET_SRC (x
), 0),
4715 pos
, NULL_RTX
, 1, 1, 0, 0);
4716 if (extraction
!= 0)
4718 SUBST (SET_SRC (x
), extraction
);
4719 return find_split_point (loc
, insn
, false);
4725 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4726 is known to be on, this can be converted into a NEG of a shift. */
4727 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4728 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4729 && 1 <= (pos
= exact_log2
4730 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4731 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4733 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4737 gen_rtx_LSHIFTRT (mode
,
4738 XEXP (SET_SRC (x
), 0),
4741 split
= find_split_point (&SET_SRC (x
), insn
, true);
4742 if (split
&& split
!= &SET_SRC (x
))
4748 inner
= XEXP (SET_SRC (x
), 0);
4750 /* We can't optimize if either mode is a partial integer
4751 mode as we don't know how many bits are significant
4753 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4754 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4758 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4764 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4765 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4767 inner
= XEXP (SET_SRC (x
), 0);
4768 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4769 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4771 if (BITS_BIG_ENDIAN
)
4772 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4773 unsignedp
= (code
== ZERO_EXTRACT
);
4782 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4784 machine_mode mode
= GET_MODE (SET_SRC (x
));
4786 /* For unsigned, we have a choice of a shift followed by an
4787 AND or two shifts. Use two shifts for field sizes where the
4788 constant might be too large. We assume here that we can
4789 always at least get 8-bit constants in an AND insn, which is
4790 true for every current RISC. */
4792 if (unsignedp
&& len
<= 8)
4794 unsigned HOST_WIDE_INT mask
4795 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4799 (mode
, gen_lowpart (mode
, inner
),
4801 gen_int_mode (mask
, mode
)));
4803 split
= find_split_point (&SET_SRC (x
), insn
, true);
4804 if (split
&& split
!= &SET_SRC (x
))
4811 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4812 gen_rtx_ASHIFT (mode
,
4813 gen_lowpart (mode
, inner
),
4814 GEN_INT (GET_MODE_PRECISION (mode
)
4816 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4818 split
= find_split_point (&SET_SRC (x
), insn
, true);
4819 if (split
&& split
!= &SET_SRC (x
))
4824 /* See if this is a simple operation with a constant as the second
4825 operand. It might be that this constant is out of range and hence
4826 could be used as a split point. */
4827 if (BINARY_P (SET_SRC (x
))
4828 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4829 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4830 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4831 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4832 return &XEXP (SET_SRC (x
), 1);
4834 /* Finally, see if this is a simple operation with its first operand
4835 not in a register. The operation might require this operand in a
4836 register, so return it as a split point. We can always do this
4837 because if the first operand were another operation, we would have
4838 already found it as a split point. */
4839 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4840 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4841 return &XEXP (SET_SRC (x
), 0);
4847 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4848 it is better to write this as (not (ior A B)) so we can split it.
4849 Similarly for IOR. */
4850 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4853 gen_rtx_NOT (GET_MODE (x
),
4854 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4856 XEXP (XEXP (x
, 0), 0),
4857 XEXP (XEXP (x
, 1), 0))));
4858 return find_split_point (loc
, insn
, set_src
);
4861 /* Many RISC machines have a large set of logical insns. If the
4862 second operand is a NOT, put it first so we will try to split the
4863 other operand first. */
4864 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4866 rtx tem
= XEXP (x
, 0);
4867 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4868 SUBST (XEXP (x
, 1), tem
);
4874 /* Canonicalization can produce (minus A (mult B C)), where C is a
4875 constant. It may be better to try splitting (plus (mult B -C) A)
4876 instead if this isn't a multiply by a power of two. */
4877 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4878 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4879 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4881 machine_mode mode
= GET_MODE (x
);
4882 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4883 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4884 SUBST (*loc
, gen_rtx_PLUS (mode
,
4886 XEXP (XEXP (x
, 1), 0),
4887 gen_int_mode (other_int
,
4890 return find_split_point (loc
, insn
, set_src
);
4893 /* Split at a multiply-accumulate instruction. However if this is
4894 the SET_SRC, we likely do not have such an instruction and it's
4895 worthless to try this split. */
4896 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4903 /* Otherwise, select our actions depending on our rtx class. */
4904 switch (GET_RTX_CLASS (code
))
4906 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4908 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4911 /* ... fall through ... */
4913 case RTX_COMM_ARITH
:
4915 case RTX_COMM_COMPARE
:
4916 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4919 /* ... fall through ... */
4921 /* Some machines have (and (shift ...) ...) insns. If X is not
4922 an AND, but XEXP (X, 0) is, use it as our split point. */
4923 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4924 return &XEXP (x
, 0);
4926 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4932 /* Otherwise, we don't have a split point. */
4937 /* Throughout X, replace FROM with TO, and return the result.
4938 The result is TO if X is FROM;
4939 otherwise the result is X, but its contents may have been modified.
4940 If they were modified, a record was made in undobuf so that
4941 undo_all will (among other things) return X to its original state.
4943 If the number of changes necessary is too much to record to undo,
4944 the excess changes are not made, so the result is invalid.
4945 The changes already made can still be undone.
4946 undobuf.num_undo is incremented for such changes, so by testing that
4947 the caller can tell whether the result is valid.
4949 `n_occurrences' is incremented each time FROM is replaced.
4951 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4953 IN_COND is nonzero if we are at the top level of a condition.
4955 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4956 by copying if `n_occurrences' is nonzero. */
4959 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
4961 enum rtx_code code
= GET_CODE (x
);
4962 machine_mode op0_mode
= VOIDmode
;
4967 /* Two expressions are equal if they are identical copies of a shared
4968 RTX or if they are both registers with the same register number
4971 #define COMBINE_RTX_EQUAL_P(X,Y) \
4973 || (REG_P (X) && REG_P (Y) \
4974 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4976 /* Do not substitute into clobbers of regs -- this will never result in
4978 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
4981 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4984 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4987 /* If X and FROM are the same register but different modes, they
4988 will not have been seen as equal above. However, the log links code
4989 will make a LOG_LINKS entry for that case. If we do nothing, we
4990 will try to rerecognize our original insn and, when it succeeds,
4991 we will delete the feeding insn, which is incorrect.
4993 So force this insn not to match in this (rare) case. */
4994 if (! in_dest
&& code
== REG
&& REG_P (from
)
4995 && reg_overlap_mentioned_p (x
, from
))
4996 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4998 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4999 of which may contain things that can be combined. */
5000 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5003 /* It is possible to have a subexpression appear twice in the insn.
5004 Suppose that FROM is a register that appears within TO.
5005 Then, after that subexpression has been scanned once by `subst',
5006 the second time it is scanned, TO may be found. If we were
5007 to scan TO here, we would find FROM within it and create a
5008 self-referent rtl structure which is completely wrong. */
5009 if (COMBINE_RTX_EQUAL_P (x
, to
))
5012 /* Parallel asm_operands need special attention because all of the
5013 inputs are shared across the arms. Furthermore, unsharing the
5014 rtl results in recognition failures. Failure to handle this case
5015 specially can result in circular rtl.
5017 Solve this by doing a normal pass across the first entry of the
5018 parallel, and only processing the SET_DESTs of the subsequent
5021 if (code
== PARALLEL
5022 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5023 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5025 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5027 /* If this substitution failed, this whole thing fails. */
5028 if (GET_CODE (new_rtx
) == CLOBBER
5029 && XEXP (new_rtx
, 0) == const0_rtx
)
5032 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5034 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5036 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5039 && GET_CODE (dest
) != CC0
5040 && GET_CODE (dest
) != PC
)
5042 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5044 /* If this substitution failed, this whole thing fails. */
5045 if (GET_CODE (new_rtx
) == CLOBBER
5046 && XEXP (new_rtx
, 0) == const0_rtx
)
5049 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5055 len
= GET_RTX_LENGTH (code
);
5056 fmt
= GET_RTX_FORMAT (code
);
5058 /* We don't need to process a SET_DEST that is a register, CC0,
5059 or PC, so set up to skip this common case. All other cases
5060 where we want to suppress replacing something inside a
5061 SET_SRC are handled via the IN_DEST operand. */
5063 && (REG_P (SET_DEST (x
))
5064 || GET_CODE (SET_DEST (x
)) == CC0
5065 || GET_CODE (SET_DEST (x
)) == PC
))
5068 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5071 op0_mode
= GET_MODE (XEXP (x
, 0));
5073 for (i
= 0; i
< len
; i
++)
5078 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5080 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5082 new_rtx
= (unique_copy
&& n_occurrences
5083 ? copy_rtx (to
) : to
);
5088 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5091 /* If this substitution failed, this whole thing
5093 if (GET_CODE (new_rtx
) == CLOBBER
5094 && XEXP (new_rtx
, 0) == const0_rtx
)
5098 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5101 else if (fmt
[i
] == 'e')
5103 /* If this is a register being set, ignore it. */
5104 new_rtx
= XEXP (x
, i
);
5107 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5109 || code
== STRICT_LOW_PART
))
5112 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5114 /* In general, don't install a subreg involving two
5115 modes not tieable. It can worsen register
5116 allocation, and can even make invalid reload
5117 insns, since the reg inside may need to be copied
5118 from in the outside mode, and that may be invalid
5119 if it is an fp reg copied in integer mode.
5121 We allow two exceptions to this: It is valid if
5122 it is inside another SUBREG and the mode of that
5123 SUBREG and the mode of the inside of TO is
5124 tieable and it is valid if X is a SET that copies
5127 if (GET_CODE (to
) == SUBREG
5128 && ! MODES_TIEABLE_P (GET_MODE (to
),
5129 GET_MODE (SUBREG_REG (to
)))
5130 && ! (code
== SUBREG
5131 && MODES_TIEABLE_P (GET_MODE (x
),
5132 GET_MODE (SUBREG_REG (to
))))
5134 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5137 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5141 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5142 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5145 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5147 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5151 /* If we are in a SET_DEST, suppress most cases unless we
5152 have gone inside a MEM, in which case we want to
5153 simplify the address. We assume here that things that
5154 are actually part of the destination have their inner
5155 parts in the first expression. This is true for SUBREG,
5156 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5157 things aside from REG and MEM that should appear in a
5159 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5161 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5162 || code
== ZERO_EXTRACT
))
5165 code
== IF_THEN_ELSE
&& i
== 0,
5168 /* If we found that we will have to reject this combination,
5169 indicate that by returning the CLOBBER ourselves, rather than
5170 an expression containing it. This will speed things up as
5171 well as prevent accidents where two CLOBBERs are considered
5172 to be equal, thus producing an incorrect simplification. */
5174 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5177 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5179 machine_mode mode
= GET_MODE (x
);
5181 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5182 GET_MODE (SUBREG_REG (x
)),
5185 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5187 else if (CONST_SCALAR_INT_P (new_rtx
)
5188 && GET_CODE (x
) == ZERO_EXTEND
)
5190 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5191 new_rtx
, GET_MODE (XEXP (x
, 0)));
5195 SUBST (XEXP (x
, i
), new_rtx
);
5200 /* Check if we are loading something from the constant pool via float
5201 extension; in this case we would undo compress_float_constant
5202 optimization and degenerate constant load to an immediate value. */
5203 if (GET_CODE (x
) == FLOAT_EXTEND
5204 && MEM_P (XEXP (x
, 0))
5205 && MEM_READONLY_P (XEXP (x
, 0)))
5207 rtx tmp
= avoid_constant_pool_reference (x
);
5212 /* Try to simplify X. If the simplification changed the code, it is likely
5213 that further simplification will help, so loop, but limit the number
5214 of repetitions that will be performed. */
5216 for (i
= 0; i
< 4; i
++)
5218 /* If X is sufficiently simple, don't bother trying to do anything
5220 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5221 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5223 if (GET_CODE (x
) == code
)
5226 code
= GET_CODE (x
);
5228 /* We no longer know the original mode of operand 0 since we
5229 have changed the form of X) */
5230 op0_mode
= VOIDmode
;
5236 /* Simplify X, a piece of RTL. We just operate on the expression at the
5237 outer level; call `subst' to simplify recursively. Return the new
5240 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5241 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5245 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5248 enum rtx_code code
= GET_CODE (x
);
5249 machine_mode mode
= GET_MODE (x
);
5253 /* If this is a commutative operation, put a constant last and a complex
5254 expression first. We don't need to do this for comparisons here. */
5255 if (COMMUTATIVE_ARITH_P (x
)
5256 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5259 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5260 SUBST (XEXP (x
, 1), temp
);
5263 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5264 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5265 things. Check for cases where both arms are testing the same
5268 Don't do anything if all operands are very simple. */
5271 && ((!OBJECT_P (XEXP (x
, 0))
5272 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5273 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5274 || (!OBJECT_P (XEXP (x
, 1))
5275 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5276 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5278 && (!OBJECT_P (XEXP (x
, 0))
5279 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5280 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5282 rtx cond
, true_rtx
, false_rtx
;
5284 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5286 /* If everything is a comparison, what we have is highly unlikely
5287 to be simpler, so don't use it. */
5288 && ! (COMPARISON_P (x
)
5289 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5291 rtx cop1
= const0_rtx
;
5292 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5294 if (cond_code
== NE
&& COMPARISON_P (cond
))
5297 /* Simplify the alternative arms; this may collapse the true and
5298 false arms to store-flag values. Be careful to use copy_rtx
5299 here since true_rtx or false_rtx might share RTL with x as a
5300 result of the if_then_else_cond call above. */
5301 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5302 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5304 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5305 is unlikely to be simpler. */
5306 if (general_operand (true_rtx
, VOIDmode
)
5307 && general_operand (false_rtx
, VOIDmode
))
5309 enum rtx_code reversed
;
5311 /* Restarting if we generate a store-flag expression will cause
5312 us to loop. Just drop through in this case. */
5314 /* If the result values are STORE_FLAG_VALUE and zero, we can
5315 just make the comparison operation. */
5316 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5317 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5319 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5320 && ((reversed
= reversed_comparison_code_parts
5321 (cond_code
, cond
, cop1
, NULL
))
5323 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5326 /* Likewise, we can make the negate of a comparison operation
5327 if the result values are - STORE_FLAG_VALUE and zero. */
5328 else if (CONST_INT_P (true_rtx
)
5329 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5330 && false_rtx
== const0_rtx
)
5331 x
= simplify_gen_unary (NEG
, mode
,
5332 simplify_gen_relational (cond_code
,
5336 else if (CONST_INT_P (false_rtx
)
5337 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5338 && true_rtx
== const0_rtx
5339 && ((reversed
= reversed_comparison_code_parts
5340 (cond_code
, cond
, cop1
, NULL
))
5342 x
= simplify_gen_unary (NEG
, mode
,
5343 simplify_gen_relational (reversed
,
5348 return gen_rtx_IF_THEN_ELSE (mode
,
5349 simplify_gen_relational (cond_code
,
5354 true_rtx
, false_rtx
);
5356 code
= GET_CODE (x
);
5357 op0_mode
= VOIDmode
;
5362 /* Try to fold this expression in case we have constants that weren't
5365 switch (GET_RTX_CLASS (code
))
5368 if (op0_mode
== VOIDmode
)
5369 op0_mode
= GET_MODE (XEXP (x
, 0));
5370 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5373 case RTX_COMM_COMPARE
:
5375 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5376 if (cmp_mode
== VOIDmode
)
5378 cmp_mode
= GET_MODE (XEXP (x
, 1));
5379 if (cmp_mode
== VOIDmode
)
5380 cmp_mode
= op0_mode
;
5382 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5383 XEXP (x
, 0), XEXP (x
, 1));
5386 case RTX_COMM_ARITH
:
5388 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5390 case RTX_BITFIELD_OPS
:
5392 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5393 XEXP (x
, 1), XEXP (x
, 2));
5402 code
= GET_CODE (temp
);
5403 op0_mode
= VOIDmode
;
5404 mode
= GET_MODE (temp
);
5407 /* First see if we can apply the inverse distributive law. */
5408 if (code
== PLUS
|| code
== MINUS
5409 || code
== AND
|| code
== IOR
|| code
== XOR
)
5411 x
= apply_distributive_law (x
);
5412 code
= GET_CODE (x
);
5413 op0_mode
= VOIDmode
;
5416 /* If CODE is an associative operation not otherwise handled, see if we
5417 can associate some operands. This can win if they are constants or
5418 if they are logically related (i.e. (a & b) & a). */
5419 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5420 || code
== AND
|| code
== IOR
|| code
== XOR
5421 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5422 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5423 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5425 if (GET_CODE (XEXP (x
, 0)) == code
)
5427 rtx other
= XEXP (XEXP (x
, 0), 0);
5428 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5429 rtx inner_op1
= XEXP (x
, 1);
5432 /* Make sure we pass the constant operand if any as the second
5433 one if this is a commutative operation. */
5434 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5436 rtx tem
= inner_op0
;
5437 inner_op0
= inner_op1
;
5440 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5441 : code
== DIV
? MULT
5443 mode
, inner_op0
, inner_op1
);
5445 /* For commutative operations, try the other pair if that one
5447 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5449 other
= XEXP (XEXP (x
, 0), 1);
5450 inner
= simplify_binary_operation (code
, mode
,
5451 XEXP (XEXP (x
, 0), 0),
5456 return simplify_gen_binary (code
, mode
, other
, inner
);
5460 /* A little bit of algebraic simplification here. */
5464 /* Ensure that our address has any ASHIFTs converted to MULT in case
5465 address-recognizing predicates are called later. */
5466 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5467 SUBST (XEXP (x
, 0), temp
);
5471 if (op0_mode
== VOIDmode
)
5472 op0_mode
= GET_MODE (SUBREG_REG (x
));
5474 /* See if this can be moved to simplify_subreg. */
5475 if (CONSTANT_P (SUBREG_REG (x
))
5476 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5477 /* Don't call gen_lowpart if the inner mode
5478 is VOIDmode and we cannot simplify it, as SUBREG without
5479 inner mode is invalid. */
5480 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5481 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5482 return gen_lowpart (mode
, SUBREG_REG (x
));
5484 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5488 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5493 /* If op is known to have all lower bits zero, the result is zero. */
5495 && SCALAR_INT_MODE_P (mode
)
5496 && SCALAR_INT_MODE_P (op0_mode
)
5497 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5498 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5499 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5500 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5501 & GET_MODE_MASK (mode
)) == 0)
5502 return CONST0_RTX (mode
);
5505 /* Don't change the mode of the MEM if that would change the meaning
5507 if (MEM_P (SUBREG_REG (x
))
5508 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5509 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5510 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5511 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5513 /* Note that we cannot do any narrowing for non-constants since
5514 we might have been counting on using the fact that some bits were
5515 zero. We now do this in the SET. */
5520 temp
= expand_compound_operation (XEXP (x
, 0));
5522 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5523 replaced by (lshiftrt X C). This will convert
5524 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5526 if (GET_CODE (temp
) == ASHIFTRT
5527 && CONST_INT_P (XEXP (temp
, 1))
5528 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5529 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5530 INTVAL (XEXP (temp
, 1)));
5532 /* If X has only a single bit that might be nonzero, say, bit I, convert
5533 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5534 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5535 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5536 or a SUBREG of one since we'd be making the expression more
5537 complex if it was just a register. */
5540 && ! (GET_CODE (temp
) == SUBREG
5541 && REG_P (SUBREG_REG (temp
)))
5542 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5544 rtx temp1
= simplify_shift_const
5545 (NULL_RTX
, ASHIFTRT
, mode
,
5546 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5547 GET_MODE_PRECISION (mode
) - 1 - i
),
5548 GET_MODE_PRECISION (mode
) - 1 - i
);
5550 /* If all we did was surround TEMP with the two shifts, we
5551 haven't improved anything, so don't use it. Otherwise,
5552 we are better off with TEMP1. */
5553 if (GET_CODE (temp1
) != ASHIFTRT
5554 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5555 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5561 /* We can't handle truncation to a partial integer mode here
5562 because we don't know the real bitsize of the partial
5564 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5567 if (HWI_COMPUTABLE_MODE_P (mode
))
5569 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5570 GET_MODE_MASK (mode
), 0));
5572 /* We can truncate a constant value and return it. */
5573 if (CONST_INT_P (XEXP (x
, 0)))
5574 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5576 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5577 whose value is a comparison can be replaced with a subreg if
5578 STORE_FLAG_VALUE permits. */
5579 if (HWI_COMPUTABLE_MODE_P (mode
)
5580 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5581 && (temp
= get_last_value (XEXP (x
, 0)))
5582 && COMPARISON_P (temp
))
5583 return gen_lowpart (mode
, XEXP (x
, 0));
5587 /* (const (const X)) can become (const X). Do it this way rather than
5588 returning the inner CONST since CONST can be shared with a
5590 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5591 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5596 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5597 can add in an offset. find_split_point will split this address up
5598 again if it doesn't match. */
5599 if (GET_CODE (XEXP (x
, 0)) == HIGH
5600 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5606 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5607 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5608 bit-field and can be replaced by either a sign_extend or a
5609 sign_extract. The `and' may be a zero_extend and the two
5610 <c>, -<c> constants may be reversed. */
5611 if (GET_CODE (XEXP (x
, 0)) == XOR
5612 && CONST_INT_P (XEXP (x
, 1))
5613 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5614 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5615 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5616 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5617 && HWI_COMPUTABLE_MODE_P (mode
)
5618 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5619 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5620 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5621 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5622 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5623 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5624 == (unsigned int) i
+ 1))))
5625 return simplify_shift_const
5626 (NULL_RTX
, ASHIFTRT
, mode
,
5627 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5628 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5629 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5630 GET_MODE_PRECISION (mode
) - (i
+ 1));
5632 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5633 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5634 the bitsize of the mode - 1. This allows simplification of
5635 "a = (b & 8) == 0;" */
5636 if (XEXP (x
, 1) == constm1_rtx
5637 && !REG_P (XEXP (x
, 0))
5638 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5639 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5640 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5641 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5642 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5643 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5644 GET_MODE_PRECISION (mode
) - 1),
5645 GET_MODE_PRECISION (mode
) - 1);
5647 /* If we are adding two things that have no bits in common, convert
5648 the addition into an IOR. This will often be further simplified,
5649 for example in cases like ((a & 1) + (a & 2)), which can
5652 if (HWI_COMPUTABLE_MODE_P (mode
)
5653 && (nonzero_bits (XEXP (x
, 0), mode
)
5654 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5656 /* Try to simplify the expression further. */
5657 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5658 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5660 /* If we could, great. If not, do not go ahead with the IOR
5661 replacement, since PLUS appears in many special purpose
5662 address arithmetic instructions. */
5663 if (GET_CODE (temp
) != CLOBBER
5664 && (GET_CODE (temp
) != IOR
5665 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5666 || XEXP (temp
, 1) != XEXP (x
, 1))
5667 && (XEXP (temp
, 0) != XEXP (x
, 1)
5668 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5674 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5675 (and <foo> (const_int pow2-1)) */
5676 if (GET_CODE (XEXP (x
, 1)) == AND
5677 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5678 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5679 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5680 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5681 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5685 /* If we have (mult (plus A B) C), apply the distributive law and then
5686 the inverse distributive law to see if things simplify. This
5687 occurs mostly in addresses, often when unrolling loops. */
5689 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5691 rtx result
= distribute_and_simplify_rtx (x
, 0);
5696 /* Try simplify a*(b/c) as (a*b)/c. */
5697 if (FLOAT_MODE_P (mode
) && flag_associative_math
5698 && GET_CODE (XEXP (x
, 0)) == DIV
)
5700 rtx tem
= simplify_binary_operation (MULT
, mode
,
5701 XEXP (XEXP (x
, 0), 0),
5704 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5709 /* If this is a divide by a power of two, treat it as a shift if
5710 its first operand is a shift. */
5711 if (CONST_INT_P (XEXP (x
, 1))
5712 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5713 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5714 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5715 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5716 || GET_CODE (XEXP (x
, 0)) == ROTATE
5717 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5718 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5722 case GT
: case GTU
: case GE
: case GEU
:
5723 case LT
: case LTU
: case LE
: case LEU
:
5724 case UNEQ
: case LTGT
:
5725 case UNGT
: case UNGE
:
5726 case UNLT
: case UNLE
:
5727 case UNORDERED
: case ORDERED
:
5728 /* If the first operand is a condition code, we can't do anything
5730 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5731 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5732 && ! CC0_P (XEXP (x
, 0))))
5734 rtx op0
= XEXP (x
, 0);
5735 rtx op1
= XEXP (x
, 1);
5736 enum rtx_code new_code
;
5738 if (GET_CODE (op0
) == COMPARE
)
5739 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5741 /* Simplify our comparison, if possible. */
5742 new_code
= simplify_comparison (code
, &op0
, &op1
);
5744 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5745 if only the low-order bit is possibly nonzero in X (such as when
5746 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5747 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5748 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5751 Remove any ZERO_EXTRACT we made when thinking this was a
5752 comparison. It may now be simpler to use, e.g., an AND. If a
5753 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5754 the call to make_compound_operation in the SET case.
5756 Don't apply these optimizations if the caller would
5757 prefer a comparison rather than a value.
5758 E.g., for the condition in an IF_THEN_ELSE most targets need
5759 an explicit comparison. */
5764 else if (STORE_FLAG_VALUE
== 1
5765 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5766 && op1
== const0_rtx
5767 && mode
== GET_MODE (op0
)
5768 && nonzero_bits (op0
, mode
) == 1)
5769 return gen_lowpart (mode
,
5770 expand_compound_operation (op0
));
5772 else if (STORE_FLAG_VALUE
== 1
5773 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5774 && op1
== const0_rtx
5775 && mode
== GET_MODE (op0
)
5776 && (num_sign_bit_copies (op0
, mode
)
5777 == GET_MODE_PRECISION (mode
)))
5779 op0
= expand_compound_operation (op0
);
5780 return simplify_gen_unary (NEG
, mode
,
5781 gen_lowpart (mode
, op0
),
5785 else if (STORE_FLAG_VALUE
== 1
5786 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5787 && op1
== const0_rtx
5788 && mode
== GET_MODE (op0
)
5789 && nonzero_bits (op0
, mode
) == 1)
5791 op0
= expand_compound_operation (op0
);
5792 return simplify_gen_binary (XOR
, mode
,
5793 gen_lowpart (mode
, op0
),
5797 else if (STORE_FLAG_VALUE
== 1
5798 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5799 && op1
== const0_rtx
5800 && mode
== GET_MODE (op0
)
5801 && (num_sign_bit_copies (op0
, mode
)
5802 == GET_MODE_PRECISION (mode
)))
5804 op0
= expand_compound_operation (op0
);
5805 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5808 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5813 else if (STORE_FLAG_VALUE
== -1
5814 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5815 && op1
== const0_rtx
5816 && mode
== GET_MODE (op0
)
5817 && (num_sign_bit_copies (op0
, mode
)
5818 == GET_MODE_PRECISION (mode
)))
5819 return gen_lowpart (mode
,
5820 expand_compound_operation (op0
));
5822 else if (STORE_FLAG_VALUE
== -1
5823 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5824 && op1
== const0_rtx
5825 && mode
== GET_MODE (op0
)
5826 && nonzero_bits (op0
, mode
) == 1)
5828 op0
= expand_compound_operation (op0
);
5829 return simplify_gen_unary (NEG
, mode
,
5830 gen_lowpart (mode
, op0
),
5834 else if (STORE_FLAG_VALUE
== -1
5835 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5836 && op1
== const0_rtx
5837 && mode
== GET_MODE (op0
)
5838 && (num_sign_bit_copies (op0
, mode
)
5839 == GET_MODE_PRECISION (mode
)))
5841 op0
= expand_compound_operation (op0
);
5842 return simplify_gen_unary (NOT
, mode
,
5843 gen_lowpart (mode
, op0
),
5847 /* If X is 0/1, (eq X 0) is X-1. */
5848 else if (STORE_FLAG_VALUE
== -1
5849 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5850 && op1
== const0_rtx
5851 && mode
== GET_MODE (op0
)
5852 && nonzero_bits (op0
, mode
) == 1)
5854 op0
= expand_compound_operation (op0
);
5855 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5858 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5859 one bit that might be nonzero, we can convert (ne x 0) to
5860 (ashift x c) where C puts the bit in the sign bit. Remove any
5861 AND with STORE_FLAG_VALUE when we are done, since we are only
5862 going to test the sign bit. */
5863 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5864 && HWI_COMPUTABLE_MODE_P (mode
)
5865 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5866 && op1
== const0_rtx
5867 && mode
== GET_MODE (op0
)
5868 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5870 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5871 expand_compound_operation (op0
),
5872 GET_MODE_PRECISION (mode
) - 1 - i
);
5873 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5879 /* If the code changed, return a whole new comparison.
5880 We also need to avoid using SUBST in cases where
5881 simplify_comparison has widened a comparison with a CONST_INT,
5882 since in that case the wider CONST_INT may fail the sanity
5883 checks in do_SUBST. */
5884 if (new_code
!= code
5885 || (CONST_INT_P (op1
)
5886 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
5887 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
5888 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5890 /* Otherwise, keep this operation, but maybe change its operands.
5891 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5892 SUBST (XEXP (x
, 0), op0
);
5893 SUBST (XEXP (x
, 1), op1
);
5898 return simplify_if_then_else (x
);
5904 /* If we are processing SET_DEST, we are done. */
5908 return expand_compound_operation (x
);
5911 return simplify_set (x
);
5915 return simplify_logical (x
);
5922 /* If this is a shift by a constant amount, simplify it. */
5923 if (CONST_INT_P (XEXP (x
, 1)))
5924 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5925 INTVAL (XEXP (x
, 1)));
5927 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5929 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5930 ((unsigned HOST_WIDE_INT
) 1
5931 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5943 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5946 simplify_if_then_else (rtx x
)
5948 machine_mode mode
= GET_MODE (x
);
5949 rtx cond
= XEXP (x
, 0);
5950 rtx true_rtx
= XEXP (x
, 1);
5951 rtx false_rtx
= XEXP (x
, 2);
5952 enum rtx_code true_code
= GET_CODE (cond
);
5953 int comparison_p
= COMPARISON_P (cond
);
5956 enum rtx_code false_code
;
5959 /* Simplify storing of the truth value. */
5960 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5961 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5962 XEXP (cond
, 0), XEXP (cond
, 1));
5964 /* Also when the truth value has to be reversed. */
5966 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5967 && (reversed
= reversed_comparison (cond
, mode
)))
5970 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5971 in it is being compared against certain values. Get the true and false
5972 comparisons and see if that says anything about the value of each arm. */
5975 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5977 && REG_P (XEXP (cond
, 0)))
5980 rtx from
= XEXP (cond
, 0);
5981 rtx true_val
= XEXP (cond
, 1);
5982 rtx false_val
= true_val
;
5985 /* If FALSE_CODE is EQ, swap the codes and arms. */
5987 if (false_code
== EQ
)
5989 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5990 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5993 /* If we are comparing against zero and the expression being tested has
5994 only a single bit that might be nonzero, that is its value when it is
5995 not equal to zero. Similarly if it is known to be -1 or 0. */
5997 if (true_code
== EQ
&& true_val
== const0_rtx
5998 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
6001 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6003 else if (true_code
== EQ
&& true_val
== const0_rtx
6004 && (num_sign_bit_copies (from
, GET_MODE (from
))
6005 == GET_MODE_PRECISION (GET_MODE (from
))))
6008 false_val
= constm1_rtx
;
6011 /* Now simplify an arm if we know the value of the register in the
6012 branch and it is used in the arm. Be careful due to the potential
6013 of locally-shared RTL. */
6015 if (reg_mentioned_p (from
, true_rtx
))
6016 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6018 pc_rtx
, pc_rtx
, 0, 0, 0);
6019 if (reg_mentioned_p (from
, false_rtx
))
6020 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6022 pc_rtx
, pc_rtx
, 0, 0, 0);
6024 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6025 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6027 true_rtx
= XEXP (x
, 1);
6028 false_rtx
= XEXP (x
, 2);
6029 true_code
= GET_CODE (cond
);
6032 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6033 reversed, do so to avoid needing two sets of patterns for
6034 subtract-and-branch insns. Similarly if we have a constant in the true
6035 arm, the false arm is the same as the first operand of the comparison, or
6036 the false arm is more complicated than the true arm. */
6039 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6040 && (true_rtx
== pc_rtx
6041 || (CONSTANT_P (true_rtx
)
6042 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6043 || true_rtx
== const0_rtx
6044 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6045 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6046 && !OBJECT_P (false_rtx
))
6047 || reg_mentioned_p (true_rtx
, false_rtx
)
6048 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6050 true_code
= reversed_comparison_code (cond
, NULL
);
6051 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6052 SUBST (XEXP (x
, 1), false_rtx
);
6053 SUBST (XEXP (x
, 2), true_rtx
);
6055 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6058 /* It is possible that the conditional has been simplified out. */
6059 true_code
= GET_CODE (cond
);
6060 comparison_p
= COMPARISON_P (cond
);
6063 /* If the two arms are identical, we don't need the comparison. */
6065 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6068 /* Convert a == b ? b : a to "a". */
6069 if (true_code
== EQ
&& ! side_effects_p (cond
)
6070 && !HONOR_NANS (mode
)
6071 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6072 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6074 else if (true_code
== NE
&& ! side_effects_p (cond
)
6075 && !HONOR_NANS (mode
)
6076 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6077 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6080 /* Look for cases where we have (abs x) or (neg (abs X)). */
6082 if (GET_MODE_CLASS (mode
) == MODE_INT
6084 && XEXP (cond
, 1) == const0_rtx
6085 && GET_CODE (false_rtx
) == NEG
6086 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6087 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6088 && ! side_effects_p (true_rtx
))
6093 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6097 simplify_gen_unary (NEG
, mode
,
6098 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6104 /* Look for MIN or MAX. */
6106 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6108 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6109 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6110 && ! side_effects_p (cond
))
6115 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6118 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6121 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6124 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6129 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6130 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6131 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6132 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6133 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6134 neither 1 or -1, but it isn't worth checking for. */
6136 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6138 && GET_MODE_CLASS (mode
) == MODE_INT
6139 && ! side_effects_p (x
))
6141 rtx t
= make_compound_operation (true_rtx
, SET
);
6142 rtx f
= make_compound_operation (false_rtx
, SET
);
6143 rtx cond_op0
= XEXP (cond
, 0);
6144 rtx cond_op1
= XEXP (cond
, 1);
6145 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6146 machine_mode m
= mode
;
6147 rtx z
= 0, c1
= NULL_RTX
;
6149 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6150 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6151 || GET_CODE (t
) == ASHIFT
6152 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6153 && rtx_equal_p (XEXP (t
, 0), f
))
6154 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6156 /* If an identity-zero op is commutative, check whether there
6157 would be a match if we swapped the operands. */
6158 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6159 || GET_CODE (t
) == XOR
)
6160 && rtx_equal_p (XEXP (t
, 1), f
))
6161 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6162 else if (GET_CODE (t
) == SIGN_EXTEND
6163 && (GET_CODE (XEXP (t
, 0)) == PLUS
6164 || GET_CODE (XEXP (t
, 0)) == MINUS
6165 || GET_CODE (XEXP (t
, 0)) == IOR
6166 || GET_CODE (XEXP (t
, 0)) == XOR
6167 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6168 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6169 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6170 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6171 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6172 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6173 && (num_sign_bit_copies (f
, GET_MODE (f
))
6175 (GET_MODE_PRECISION (mode
)
6176 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6178 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6179 extend_op
= SIGN_EXTEND
;
6180 m
= GET_MODE (XEXP (t
, 0));
6182 else if (GET_CODE (t
) == SIGN_EXTEND
6183 && (GET_CODE (XEXP (t
, 0)) == PLUS
6184 || GET_CODE (XEXP (t
, 0)) == IOR
6185 || GET_CODE (XEXP (t
, 0)) == XOR
)
6186 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6187 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6188 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6189 && (num_sign_bit_copies (f
, GET_MODE (f
))
6191 (GET_MODE_PRECISION (mode
)
6192 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6194 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6195 extend_op
= SIGN_EXTEND
;
6196 m
= GET_MODE (XEXP (t
, 0));
6198 else if (GET_CODE (t
) == ZERO_EXTEND
6199 && (GET_CODE (XEXP (t
, 0)) == PLUS
6200 || GET_CODE (XEXP (t
, 0)) == MINUS
6201 || GET_CODE (XEXP (t
, 0)) == IOR
6202 || GET_CODE (XEXP (t
, 0)) == XOR
6203 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6204 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6205 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6206 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6207 && HWI_COMPUTABLE_MODE_P (mode
)
6208 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6209 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6210 && ((nonzero_bits (f
, GET_MODE (f
))
6211 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6214 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6215 extend_op
= ZERO_EXTEND
;
6216 m
= GET_MODE (XEXP (t
, 0));
6218 else if (GET_CODE (t
) == ZERO_EXTEND
6219 && (GET_CODE (XEXP (t
, 0)) == PLUS
6220 || GET_CODE (XEXP (t
, 0)) == IOR
6221 || GET_CODE (XEXP (t
, 0)) == XOR
)
6222 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6223 && HWI_COMPUTABLE_MODE_P (mode
)
6224 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6225 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6226 && ((nonzero_bits (f
, GET_MODE (f
))
6227 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6230 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6231 extend_op
= ZERO_EXTEND
;
6232 m
= GET_MODE (XEXP (t
, 0));
6237 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6238 cond_op0
, cond_op1
),
6239 pc_rtx
, pc_rtx
, 0, 0, 0);
6240 temp
= simplify_gen_binary (MULT
, m
, temp
,
6241 simplify_gen_binary (MULT
, m
, c1
,
6243 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6244 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6246 if (extend_op
!= UNKNOWN
)
6247 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6253 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6254 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6255 negation of a single bit, we can convert this operation to a shift. We
6256 can actually do this more generally, but it doesn't seem worth it. */
6258 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6259 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6260 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6261 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6262 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6263 == GET_MODE_PRECISION (mode
))
6264 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6266 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6267 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6269 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6270 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6271 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6272 && GET_MODE (XEXP (cond
, 0)) == mode
6273 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6274 == nonzero_bits (XEXP (cond
, 0), mode
)
6275 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6276 return XEXP (cond
, 0);
6281 /* Simplify X, a SET expression. Return the new expression. */
6284 simplify_set (rtx x
)
6286 rtx src
= SET_SRC (x
);
6287 rtx dest
= SET_DEST (x
);
6289 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6290 rtx_insn
*other_insn
;
6293 /* (set (pc) (return)) gets written as (return). */
6294 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6297 /* Now that we know for sure which bits of SRC we are using, see if we can
6298 simplify the expression for the object knowing that we only need the
6301 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6303 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6304 SUBST (SET_SRC (x
), src
);
6307 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6308 the comparison result and try to simplify it unless we already have used
6309 undobuf.other_insn. */
6310 if ((GET_MODE_CLASS (mode
) == MODE_CC
6311 || GET_CODE (src
) == COMPARE
6313 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6314 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6315 && COMPARISON_P (*cc_use
)
6316 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6318 enum rtx_code old_code
= GET_CODE (*cc_use
);
6319 enum rtx_code new_code
;
6321 int other_changed
= 0;
6322 rtx inner_compare
= NULL_RTX
;
6323 machine_mode compare_mode
= GET_MODE (dest
);
6325 if (GET_CODE (src
) == COMPARE
)
6327 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6328 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6330 inner_compare
= op0
;
6331 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6335 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6337 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6340 new_code
= old_code
;
6341 else if (!CONSTANT_P (tmp
))
6343 new_code
= GET_CODE (tmp
);
6344 op0
= XEXP (tmp
, 0);
6345 op1
= XEXP (tmp
, 1);
6349 rtx pat
= PATTERN (other_insn
);
6350 undobuf
.other_insn
= other_insn
;
6351 SUBST (*cc_use
, tmp
);
6353 /* Attempt to simplify CC user. */
6354 if (GET_CODE (pat
) == SET
)
6356 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6357 if (new_rtx
!= NULL_RTX
)
6358 SUBST (SET_SRC (pat
), new_rtx
);
6361 /* Convert X into a no-op move. */
6362 SUBST (SET_DEST (x
), pc_rtx
);
6363 SUBST (SET_SRC (x
), pc_rtx
);
6367 /* Simplify our comparison, if possible. */
6368 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6370 #ifdef SELECT_CC_MODE
6371 /* If this machine has CC modes other than CCmode, check to see if we
6372 need to use a different CC mode here. */
6373 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6374 compare_mode
= GET_MODE (op0
);
6375 else if (inner_compare
6376 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6377 && new_code
== old_code
6378 && op0
== XEXP (inner_compare
, 0)
6379 && op1
== XEXP (inner_compare
, 1))
6380 compare_mode
= GET_MODE (inner_compare
);
6382 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6385 /* If the mode changed, we have to change SET_DEST, the mode in the
6386 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6387 a hard register, just build new versions with the proper mode. If it
6388 is a pseudo, we lose unless it is only time we set the pseudo, in
6389 which case we can safely change its mode. */
6390 if (compare_mode
!= GET_MODE (dest
))
6392 if (can_change_dest_mode (dest
, 0, compare_mode
))
6394 unsigned int regno
= REGNO (dest
);
6397 if (regno
< FIRST_PSEUDO_REGISTER
)
6398 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6401 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6402 new_dest
= regno_reg_rtx
[regno
];
6405 SUBST (SET_DEST (x
), new_dest
);
6406 SUBST (XEXP (*cc_use
, 0), new_dest
);
6413 #endif /* SELECT_CC_MODE */
6415 /* If the code changed, we have to build a new comparison in
6416 undobuf.other_insn. */
6417 if (new_code
!= old_code
)
6419 int other_changed_previously
= other_changed
;
6420 unsigned HOST_WIDE_INT mask
;
6421 rtx old_cc_use
= *cc_use
;
6423 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6427 /* If the only change we made was to change an EQ into an NE or
6428 vice versa, OP0 has only one bit that might be nonzero, and OP1
6429 is zero, check if changing the user of the condition code will
6430 produce a valid insn. If it won't, we can keep the original code
6431 in that insn by surrounding our operation with an XOR. */
6433 if (((old_code
== NE
&& new_code
== EQ
)
6434 || (old_code
== EQ
&& new_code
== NE
))
6435 && ! other_changed_previously
&& op1
== const0_rtx
6436 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6437 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6439 rtx pat
= PATTERN (other_insn
), note
= 0;
6441 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6442 && ! check_asm_operands (pat
)))
6444 *cc_use
= old_cc_use
;
6447 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6455 undobuf
.other_insn
= other_insn
;
6457 /* Otherwise, if we didn't previously have a COMPARE in the
6458 correct mode, we need one. */
6459 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6461 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6464 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6466 SUBST (SET_SRC (x
), op0
);
6469 /* Otherwise, update the COMPARE if needed. */
6470 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6472 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6478 /* Get SET_SRC in a form where we have placed back any
6479 compound expressions. Then do the checks below. */
6480 src
= make_compound_operation (src
, SET
);
6481 SUBST (SET_SRC (x
), src
);
6484 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6485 and X being a REG or (subreg (reg)), we may be able to convert this to
6486 (set (subreg:m2 x) (op)).
6488 We can always do this if M1 is narrower than M2 because that means that
6489 we only care about the low bits of the result.
6491 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6492 perform a narrower operation than requested since the high-order bits will
6493 be undefined. On machine where it is defined, this transformation is safe
6494 as long as M1 and M2 have the same number of words. */
6496 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6497 && !OBJECT_P (SUBREG_REG (src
))
6498 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6500 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6501 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6502 #ifndef WORD_REGISTER_OPERATIONS
6503 && (GET_MODE_SIZE (GET_MODE (src
))
6504 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6506 #ifdef CANNOT_CHANGE_MODE_CLASS
6507 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6508 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6509 GET_MODE (SUBREG_REG (src
)),
6513 || (GET_CODE (dest
) == SUBREG
6514 && REG_P (SUBREG_REG (dest
)))))
6516 SUBST (SET_DEST (x
),
6517 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6519 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6521 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6525 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6528 && GET_CODE (src
) == SUBREG
6529 && subreg_lowpart_p (src
)
6530 && (GET_MODE_PRECISION (GET_MODE (src
))
6531 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6533 rtx inner
= SUBREG_REG (src
);
6534 machine_mode inner_mode
= GET_MODE (inner
);
6536 /* Here we make sure that we don't have a sign bit on. */
6537 if (val_signbit_known_clear_p (GET_MODE (src
),
6538 nonzero_bits (inner
, inner_mode
)))
6540 SUBST (SET_SRC (x
), inner
);
6546 #ifdef LOAD_EXTEND_OP
6547 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6548 would require a paradoxical subreg. Replace the subreg with a
6549 zero_extend to avoid the reload that would otherwise be required. */
6551 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6552 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6553 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6554 && SUBREG_BYTE (src
) == 0
6555 && paradoxical_subreg_p (src
)
6556 && MEM_P (SUBREG_REG (src
)))
6559 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6560 GET_MODE (src
), SUBREG_REG (src
)));
6566 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6567 are comparing an item known to be 0 or -1 against 0, use a logical
6568 operation instead. Check for one of the arms being an IOR of the other
6569 arm with some value. We compute three terms to be IOR'ed together. In
6570 practice, at most two will be nonzero. Then we do the IOR's. */
6572 if (GET_CODE (dest
) != PC
6573 && GET_CODE (src
) == IF_THEN_ELSE
6574 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6575 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6576 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6577 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6578 #ifdef HAVE_conditional_move
6579 && ! can_conditionally_move_p (GET_MODE (src
))
6581 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6582 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6583 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6584 && ! side_effects_p (src
))
6586 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6587 ? XEXP (src
, 1) : XEXP (src
, 2));
6588 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6589 ? XEXP (src
, 2) : XEXP (src
, 1));
6590 rtx term1
= const0_rtx
, term2
, term3
;
6592 if (GET_CODE (true_rtx
) == IOR
6593 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6594 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6595 else if (GET_CODE (true_rtx
) == IOR
6596 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6597 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6598 else if (GET_CODE (false_rtx
) == IOR
6599 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6600 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6601 else if (GET_CODE (false_rtx
) == IOR
6602 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6603 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6605 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6606 XEXP (XEXP (src
, 0), 0), true_rtx
);
6607 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6608 simplify_gen_unary (NOT
, GET_MODE (src
),
6609 XEXP (XEXP (src
, 0), 0),
6614 simplify_gen_binary (IOR
, GET_MODE (src
),
6615 simplify_gen_binary (IOR
, GET_MODE (src
),
6622 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6623 whole thing fail. */
6624 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6626 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6629 /* Convert this into a field assignment operation, if possible. */
6630 return make_field_assignment (x
);
6633 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6637 simplify_logical (rtx x
)
6639 machine_mode mode
= GET_MODE (x
);
6640 rtx op0
= XEXP (x
, 0);
6641 rtx op1
= XEXP (x
, 1);
6643 switch (GET_CODE (x
))
6646 /* We can call simplify_and_const_int only if we don't lose
6647 any (sign) bits when converting INTVAL (op1) to
6648 "unsigned HOST_WIDE_INT". */
6649 if (CONST_INT_P (op1
)
6650 && (HWI_COMPUTABLE_MODE_P (mode
)
6651 || INTVAL (op1
) > 0))
6653 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6654 if (GET_CODE (x
) != AND
)
6661 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6662 apply the distributive law and then the inverse distributive
6663 law to see if things simplify. */
6664 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6666 rtx result
= distribute_and_simplify_rtx (x
, 0);
6670 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6672 rtx result
= distribute_and_simplify_rtx (x
, 1);
6679 /* If we have (ior (and A B) C), apply the distributive law and then
6680 the inverse distributive law to see if things simplify. */
6682 if (GET_CODE (op0
) == AND
)
6684 rtx result
= distribute_and_simplify_rtx (x
, 0);
6689 if (GET_CODE (op1
) == AND
)
6691 rtx result
= distribute_and_simplify_rtx (x
, 1);
6704 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6705 operations" because they can be replaced with two more basic operations.
6706 ZERO_EXTEND is also considered "compound" because it can be replaced with
6707 an AND operation, which is simpler, though only one operation.
6709 The function expand_compound_operation is called with an rtx expression
6710 and will convert it to the appropriate shifts and AND operations,
6711 simplifying at each stage.
6713 The function make_compound_operation is called to convert an expression
6714 consisting of shifts and ANDs into the equivalent compound expression.
6715 It is the inverse of this function, loosely speaking. */
6718 expand_compound_operation (rtx x
)
6720 unsigned HOST_WIDE_INT pos
= 0, len
;
6722 unsigned int modewidth
;
6725 switch (GET_CODE (x
))
6730 /* We can't necessarily use a const_int for a multiword mode;
6731 it depends on implicitly extending the value.
6732 Since we don't know the right way to extend it,
6733 we can't tell whether the implicit way is right.
6735 Even for a mode that is no wider than a const_int,
6736 we can't win, because we need to sign extend one of its bits through
6737 the rest of it, and we don't know which bit. */
6738 if (CONST_INT_P (XEXP (x
, 0)))
6741 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6742 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6743 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6744 reloaded. If not for that, MEM's would very rarely be safe.
6746 Reject MODEs bigger than a word, because we might not be able
6747 to reference a two-register group starting with an arbitrary register
6748 (and currently gen_lowpart might crash for a SUBREG). */
6750 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6753 /* Reject MODEs that aren't scalar integers because turning vector
6754 or complex modes into shifts causes problems. */
6756 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6759 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6760 /* If the inner object has VOIDmode (the only way this can happen
6761 is if it is an ASM_OPERANDS), we can't do anything since we don't
6762 know how much masking to do. */
6771 /* ... fall through ... */
6774 /* If the operand is a CLOBBER, just return it. */
6775 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6778 if (!CONST_INT_P (XEXP (x
, 1))
6779 || !CONST_INT_P (XEXP (x
, 2))
6780 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6783 /* Reject MODEs that aren't scalar integers because turning vector
6784 or complex modes into shifts causes problems. */
6786 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6789 len
= INTVAL (XEXP (x
, 1));
6790 pos
= INTVAL (XEXP (x
, 2));
6792 /* This should stay within the object being extracted, fail otherwise. */
6793 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6796 if (BITS_BIG_ENDIAN
)
6797 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6804 /* Convert sign extension to zero extension, if we know that the high
6805 bit is not set, as this is easier to optimize. It will be converted
6806 back to cheaper alternative in make_extraction. */
6807 if (GET_CODE (x
) == SIGN_EXTEND
6808 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6809 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6810 & ~(((unsigned HOST_WIDE_INT
)
6811 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6815 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6816 rtx temp2
= expand_compound_operation (temp
);
6818 /* Make sure this is a profitable operation. */
6819 if (set_src_cost (x
, optimize_this_for_speed_p
)
6820 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6822 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6823 > set_src_cost (temp
, optimize_this_for_speed_p
))
6829 /* We can optimize some special cases of ZERO_EXTEND. */
6830 if (GET_CODE (x
) == ZERO_EXTEND
)
6832 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6833 know that the last value didn't have any inappropriate bits
6835 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6836 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6837 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6838 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6839 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6840 return XEXP (XEXP (x
, 0), 0);
6842 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6843 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6844 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6845 && subreg_lowpart_p (XEXP (x
, 0))
6846 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6847 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6848 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6849 return SUBREG_REG (XEXP (x
, 0));
6851 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6852 is a comparison and STORE_FLAG_VALUE permits. This is like
6853 the first case, but it works even when GET_MODE (x) is larger
6854 than HOST_WIDE_INT. */
6855 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6856 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6857 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6858 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6859 <= HOST_BITS_PER_WIDE_INT
)
6860 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6861 return XEXP (XEXP (x
, 0), 0);
6863 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6864 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6865 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6866 && subreg_lowpart_p (XEXP (x
, 0))
6867 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6868 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6869 <= HOST_BITS_PER_WIDE_INT
)
6870 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6871 return SUBREG_REG (XEXP (x
, 0));
6875 /* If we reach here, we want to return a pair of shifts. The inner
6876 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6877 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6878 logical depending on the value of UNSIGNEDP.
6880 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6881 converted into an AND of a shift.
6883 We must check for the case where the left shift would have a negative
6884 count. This can happen in a case like (x >> 31) & 255 on machines
6885 that can't shift by a constant. On those machines, we would first
6886 combine the shift with the AND to produce a variable-position
6887 extraction. Then the constant of 31 would be substituted in
6888 to produce such a position. */
6890 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6891 if (modewidth
>= pos
+ len
)
6893 machine_mode mode
= GET_MODE (x
);
6894 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6895 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6897 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6898 tem
, modewidth
- pos
- len
);
6899 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6900 mode
, tem
, modewidth
- len
);
6902 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6903 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6904 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6907 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6909 /* Any other cases we can't handle. */
6912 /* If we couldn't do this for some reason, return the original
6914 if (GET_CODE (tem
) == CLOBBER
)
6920 /* X is a SET which contains an assignment of one object into
6921 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6922 or certain SUBREGS). If possible, convert it into a series of
6925 We half-heartedly support variable positions, but do not at all
6926 support variable lengths. */
6929 expand_field_assignment (const_rtx x
)
6932 rtx pos
; /* Always counts from low bit. */
6934 rtx mask
, cleared
, masked
;
6935 machine_mode compute_mode
;
6937 /* Loop until we find something we can't simplify. */
6940 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6941 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6943 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6944 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
6945 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6947 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6948 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6950 inner
= XEXP (SET_DEST (x
), 0);
6951 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6952 pos
= XEXP (SET_DEST (x
), 2);
6954 /* A constant position should stay within the width of INNER. */
6955 if (CONST_INT_P (pos
)
6956 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
6959 if (BITS_BIG_ENDIAN
)
6961 if (CONST_INT_P (pos
))
6962 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
6964 else if (GET_CODE (pos
) == MINUS
6965 && CONST_INT_P (XEXP (pos
, 1))
6966 && (INTVAL (XEXP (pos
, 1))
6967 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
6968 /* If position is ADJUST - X, new position is X. */
6969 pos
= XEXP (pos
, 0);
6972 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
6973 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6974 gen_int_mode (prec
- len
,
6981 /* A SUBREG between two modes that occupy the same numbers of words
6982 can be done by moving the SUBREG to the source. */
6983 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6984 /* We need SUBREGs to compute nonzero_bits properly. */
6985 && nonzero_sign_valid
6986 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6987 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6988 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6989 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6991 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6993 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7000 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7001 inner
= SUBREG_REG (inner
);
7003 compute_mode
= GET_MODE (inner
);
7005 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7006 if (! SCALAR_INT_MODE_P (compute_mode
))
7010 /* Don't do anything for vector or complex integral types. */
7011 if (! FLOAT_MODE_P (compute_mode
))
7014 /* Try to find an integral mode to pun with. */
7015 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7016 if (imode
== BLKmode
)
7019 compute_mode
= imode
;
7020 inner
= gen_lowpart (imode
, inner
);
7023 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7024 if (len
>= HOST_BITS_PER_WIDE_INT
)
7027 /* Now compute the equivalent expression. Make a copy of INNER
7028 for the SET_DEST in case it is a MEM into which we will substitute;
7029 we don't want shared RTL in that case. */
7030 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7032 cleared
= simplify_gen_binary (AND
, compute_mode
,
7033 simplify_gen_unary (NOT
, compute_mode
,
7034 simplify_gen_binary (ASHIFT
,
7039 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7040 simplify_gen_binary (
7042 gen_lowpart (compute_mode
, SET_SRC (x
)),
7046 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
7047 simplify_gen_binary (IOR
, compute_mode
,
7054 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7055 it is an RTX that represents the (variable) starting position; otherwise,
7056 POS is the (constant) starting bit position. Both are counted from the LSB.
7058 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7060 IN_DEST is nonzero if this is a reference in the destination of a SET.
7061 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7062 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7065 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7066 ZERO_EXTRACT should be built even for bits starting at bit 0.
7068 MODE is the desired mode of the result (if IN_DEST == 0).
7070 The result is an RTX for the extraction or NULL_RTX if the target
7074 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7075 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7076 int in_dest
, int in_compare
)
7078 /* This mode describes the size of the storage area
7079 to fetch the overall value from. Within that, we
7080 ignore the POS lowest bits, etc. */
7081 machine_mode is_mode
= GET_MODE (inner
);
7082 machine_mode inner_mode
;
7083 machine_mode wanted_inner_mode
;
7084 machine_mode wanted_inner_reg_mode
= word_mode
;
7085 machine_mode pos_mode
= word_mode
;
7086 machine_mode extraction_mode
= word_mode
;
7087 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7089 rtx orig_pos_rtx
= pos_rtx
;
7090 HOST_WIDE_INT orig_pos
;
7092 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7093 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7095 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7097 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7098 consider just the QI as the memory to extract from.
7099 The subreg adds or removes high bits; its mode is
7100 irrelevant to the meaning of this extraction,
7101 since POS and LEN count from the lsb. */
7102 if (MEM_P (SUBREG_REG (inner
)))
7103 is_mode
= GET_MODE (SUBREG_REG (inner
));
7104 inner
= SUBREG_REG (inner
);
7106 else if (GET_CODE (inner
) == ASHIFT
7107 && CONST_INT_P (XEXP (inner
, 1))
7108 && pos_rtx
== 0 && pos
== 0
7109 && len
> UINTVAL (XEXP (inner
, 1)))
7111 /* We're extracting the least significant bits of an rtx
7112 (ashift X (const_int C)), where LEN > C. Extract the
7113 least significant (LEN - C) bits of X, giving an rtx
7114 whose mode is MODE, then shift it left C times. */
7115 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7116 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7117 unsignedp
, in_dest
, in_compare
);
7119 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7121 else if (GET_CODE (inner
) == TRUNCATE
)
7122 inner
= XEXP (inner
, 0);
7124 inner_mode
= GET_MODE (inner
);
7126 /* See if this can be done without an extraction. We never can if the
7127 width of the field is not the same as that of some integer mode. For
7128 registers, we can only avoid the extraction if the position is at the
7129 low-order bit and this is either not in the destination or we have the
7130 appropriate STRICT_LOW_PART operation available.
7132 For MEM, we can avoid an extract if the field starts on an appropriate
7133 boundary and we can change the mode of the memory reference. */
7135 if (tmode
!= BLKmode
7136 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7138 && (inner_mode
== tmode
7140 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7141 || reg_truncated_to_mode (tmode
, inner
))
7144 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7145 || (MEM_P (inner
) && pos_rtx
== 0
7147 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7148 : BITS_PER_UNIT
)) == 0
7149 /* We can't do this if we are widening INNER_MODE (it
7150 may not be aligned, for one thing). */
7151 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7152 && (inner_mode
== tmode
7153 || (! mode_dependent_address_p (XEXP (inner
, 0),
7154 MEM_ADDR_SPACE (inner
))
7155 && ! MEM_VOLATILE_P (inner
))))))
7157 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7158 field. If the original and current mode are the same, we need not
7159 adjust the offset. Otherwise, we do if bytes big endian.
7161 If INNER is not a MEM, get a piece consisting of just the field
7162 of interest (in this case POS % BITS_PER_WORD must be 0). */
7166 HOST_WIDE_INT offset
;
7168 /* POS counts from lsb, but make OFFSET count in memory order. */
7169 if (BYTES_BIG_ENDIAN
)
7170 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7172 offset
= pos
/ BITS_PER_UNIT
;
7174 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7176 else if (REG_P (inner
))
7178 if (tmode
!= inner_mode
)
7180 /* We can't call gen_lowpart in a DEST since we
7181 always want a SUBREG (see below) and it would sometimes
7182 return a new hard register. */
7185 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7187 if (WORDS_BIG_ENDIAN
7188 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7189 final_word
= ((GET_MODE_SIZE (inner_mode
)
7190 - GET_MODE_SIZE (tmode
))
7191 / UNITS_PER_WORD
) - final_word
;
7193 final_word
*= UNITS_PER_WORD
;
7194 if (BYTES_BIG_ENDIAN
&&
7195 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7196 final_word
+= (GET_MODE_SIZE (inner_mode
)
7197 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7199 /* Avoid creating invalid subregs, for example when
7200 simplifying (x>>32)&255. */
7201 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7204 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7207 new_rtx
= gen_lowpart (tmode
, inner
);
7213 new_rtx
= force_to_mode (inner
, tmode
,
7214 len
>= HOST_BITS_PER_WIDE_INT
7215 ? ~(unsigned HOST_WIDE_INT
) 0
7216 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7219 /* If this extraction is going into the destination of a SET,
7220 make a STRICT_LOW_PART unless we made a MEM. */
7223 return (MEM_P (new_rtx
) ? new_rtx
7224 : (GET_CODE (new_rtx
) != SUBREG
7225 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7226 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7231 if (CONST_SCALAR_INT_P (new_rtx
))
7232 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7233 mode
, new_rtx
, tmode
);
7235 /* If we know that no extraneous bits are set, and that the high
7236 bit is not set, convert the extraction to the cheaper of
7237 sign and zero extension, that are equivalent in these cases. */
7238 if (flag_expensive_optimizations
7239 && (HWI_COMPUTABLE_MODE_P (tmode
)
7240 && ((nonzero_bits (new_rtx
, tmode
)
7241 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7244 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7245 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7247 /* Prefer ZERO_EXTENSION, since it gives more information to
7249 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7250 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7255 /* Otherwise, sign- or zero-extend unless we already are in the
7258 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7262 /* Unless this is a COMPARE or we have a funny memory reference,
7263 don't do anything with zero-extending field extracts starting at
7264 the low-order bit since they are simple AND operations. */
7265 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7266 && ! in_compare
&& unsignedp
)
7269 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7270 if the position is not a constant and the length is not 1. In all
7271 other cases, we would only be going outside our object in cases when
7272 an original shift would have been undefined. */
7274 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7275 || (pos_rtx
!= 0 && len
!= 1)))
7278 enum extraction_pattern pattern
= (in_dest
? EP_insv
7279 : unsignedp
? EP_extzv
: EP_extv
);
7281 /* If INNER is not from memory, we want it to have the mode of a register
7282 extraction pattern's structure operand, or word_mode if there is no
7283 such pattern. The same applies to extraction_mode and pos_mode
7284 and their respective operands.
7286 For memory, assume that the desired extraction_mode and pos_mode
7287 are the same as for a register operation, since at present we don't
7288 have named patterns for aligned memory structures. */
7289 struct extraction_insn insn
;
7290 if (get_best_reg_extraction_insn (&insn
, pattern
,
7291 GET_MODE_BITSIZE (inner_mode
), mode
))
7293 wanted_inner_reg_mode
= insn
.struct_mode
;
7294 pos_mode
= insn
.pos_mode
;
7295 extraction_mode
= insn
.field_mode
;
7298 /* Never narrow an object, since that might not be safe. */
7300 if (mode
!= VOIDmode
7301 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7302 extraction_mode
= mode
;
7305 wanted_inner_mode
= wanted_inner_reg_mode
;
7308 /* Be careful not to go beyond the extracted object and maintain the
7309 natural alignment of the memory. */
7310 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7311 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7312 > GET_MODE_BITSIZE (wanted_inner_mode
))
7314 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7315 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7321 if (BITS_BIG_ENDIAN
)
7323 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7324 BITS_BIG_ENDIAN style. If position is constant, compute new
7325 position. Otherwise, build subtraction.
7326 Note that POS is relative to the mode of the original argument.
7327 If it's a MEM we need to recompute POS relative to that.
7328 However, if we're extracting from (or inserting into) a register,
7329 we want to recompute POS relative to wanted_inner_mode. */
7330 int width
= (MEM_P (inner
)
7331 ? GET_MODE_BITSIZE (is_mode
)
7332 : GET_MODE_BITSIZE (wanted_inner_mode
));
7335 pos
= width
- len
- pos
;
7338 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7339 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7341 /* POS may be less than 0 now, but we check for that below.
7342 Note that it can only be less than 0 if !MEM_P (inner). */
7345 /* If INNER has a wider mode, and this is a constant extraction, try to
7346 make it smaller and adjust the byte to point to the byte containing
7348 if (wanted_inner_mode
!= VOIDmode
7349 && inner_mode
!= wanted_inner_mode
7351 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7353 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7354 && ! MEM_VOLATILE_P (inner
))
7358 /* The computations below will be correct if the machine is big
7359 endian in both bits and bytes or little endian in bits and bytes.
7360 If it is mixed, we must adjust. */
7362 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7363 adjust OFFSET to compensate. */
7364 if (BYTES_BIG_ENDIAN
7365 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7366 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7368 /* We can now move to the desired byte. */
7369 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7370 * GET_MODE_SIZE (wanted_inner_mode
);
7371 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7373 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7374 && is_mode
!= wanted_inner_mode
)
7375 offset
= (GET_MODE_SIZE (is_mode
)
7376 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7378 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7381 /* If INNER is not memory, get it into the proper mode. If we are changing
7382 its mode, POS must be a constant and smaller than the size of the new
7384 else if (!MEM_P (inner
))
7386 /* On the LHS, don't create paradoxical subregs implicitely truncating
7387 the register unless TRULY_NOOP_TRUNCATION. */
7389 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7393 if (GET_MODE (inner
) != wanted_inner_mode
7395 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7401 inner
= force_to_mode (inner
, wanted_inner_mode
,
7403 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7404 ? ~(unsigned HOST_WIDE_INT
) 0
7405 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7410 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7411 have to zero extend. Otherwise, we can just use a SUBREG. */
7413 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7415 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7416 GET_MODE (pos_rtx
));
7418 /* If we know that no extraneous bits are set, and that the high
7419 bit is not set, convert extraction to cheaper one - either
7420 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7422 if (flag_expensive_optimizations
7423 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7424 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7425 & ~(((unsigned HOST_WIDE_INT
)
7426 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7430 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7431 GET_MODE (pos_rtx
));
7433 /* Prefer ZERO_EXTENSION, since it gives more information to
7435 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7436 < set_src_cost (temp
, optimize_this_for_speed_p
))
7442 /* Make POS_RTX unless we already have it and it is correct. If we don't
7443 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7445 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7446 pos_rtx
= orig_pos_rtx
;
7448 else if (pos_rtx
== 0)
7449 pos_rtx
= GEN_INT (pos
);
7451 /* Make the required operation. See if we can use existing rtx. */
7452 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7453 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7455 new_rtx
= gen_lowpart (mode
, new_rtx
);
7460 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7461 with any other operations in X. Return X without that shift if so. */
7464 extract_left_shift (rtx x
, int count
)
7466 enum rtx_code code
= GET_CODE (x
);
7467 machine_mode mode
= GET_MODE (x
);
7473 /* This is the shift itself. If it is wide enough, we will return
7474 either the value being shifted if the shift count is equal to
7475 COUNT or a shift for the difference. */
7476 if (CONST_INT_P (XEXP (x
, 1))
7477 && INTVAL (XEXP (x
, 1)) >= count
)
7478 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7479 INTVAL (XEXP (x
, 1)) - count
);
7483 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7484 return simplify_gen_unary (code
, mode
, tem
, mode
);
7488 case PLUS
: case IOR
: case XOR
: case AND
:
7489 /* If we can safely shift this constant and we find the inner shift,
7490 make a new operation. */
7491 if (CONST_INT_P (XEXP (x
, 1))
7492 && (UINTVAL (XEXP (x
, 1))
7493 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7494 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7496 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7497 return simplify_gen_binary (code
, mode
, tem
,
7498 gen_int_mode (val
, mode
));
7509 /* Look at the expression rooted at X. Look for expressions
7510 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7511 Form these expressions.
7513 Return the new rtx, usually just X.
7515 Also, for machines like the VAX that don't have logical shift insns,
7516 try to convert logical to arithmetic shift operations in cases where
7517 they are equivalent. This undoes the canonicalizations to logical
7518 shifts done elsewhere.
7520 We try, as much as possible, to re-use rtl expressions to save memory.
7522 IN_CODE says what kind of expression we are processing. Normally, it is
7523 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7524 being kludges), it is MEM. When processing the arguments of a comparison
7525 or a COMPARE against zero, it is COMPARE. */
7528 make_compound_operation (rtx x
, enum rtx_code in_code
)
7530 enum rtx_code code
= GET_CODE (x
);
7531 machine_mode mode
= GET_MODE (x
);
7532 int mode_width
= GET_MODE_PRECISION (mode
);
7534 enum rtx_code next_code
;
7540 /* Select the code to be used in recursive calls. Once we are inside an
7541 address, we stay there. If we have a comparison, set to COMPARE,
7542 but once inside, go back to our default of SET. */
7544 next_code
= (code
== MEM
? MEM
7545 : ((code
== PLUS
|| code
== MINUS
)
7546 && SCALAR_INT_MODE_P (mode
)) ? MEM
7547 : ((code
== COMPARE
|| COMPARISON_P (x
))
7548 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7549 : in_code
== COMPARE
? SET
: in_code
);
7551 /* Process depending on the code of this operation. If NEW is set
7552 nonzero, it will be returned. */
7557 /* Convert shifts by constants into multiplications if inside
7559 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7560 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7561 && INTVAL (XEXP (x
, 1)) >= 0
7562 && SCALAR_INT_MODE_P (mode
))
7564 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7565 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7567 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7568 if (GET_CODE (new_rtx
) == NEG
)
7570 new_rtx
= XEXP (new_rtx
, 0);
7573 multval
= trunc_int_for_mode (multval
, mode
);
7574 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7581 lhs
= make_compound_operation (lhs
, next_code
);
7582 rhs
= make_compound_operation (rhs
, next_code
);
7583 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7584 && SCALAR_INT_MODE_P (mode
))
7586 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7588 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7590 else if (GET_CODE (lhs
) == MULT
7591 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7593 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7594 simplify_gen_unary (NEG
, mode
,
7597 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7601 SUBST (XEXP (x
, 0), lhs
);
7602 SUBST (XEXP (x
, 1), rhs
);
7605 x
= gen_lowpart (mode
, new_rtx
);
7611 lhs
= make_compound_operation (lhs
, next_code
);
7612 rhs
= make_compound_operation (rhs
, next_code
);
7613 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7614 && SCALAR_INT_MODE_P (mode
))
7616 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7618 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7620 else if (GET_CODE (rhs
) == MULT
7621 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7623 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7624 simplify_gen_unary (NEG
, mode
,
7627 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7631 SUBST (XEXP (x
, 0), lhs
);
7632 SUBST (XEXP (x
, 1), rhs
);
7635 return gen_lowpart (mode
, new_rtx
);
7638 /* If the second operand is not a constant, we can't do anything
7640 if (!CONST_INT_P (XEXP (x
, 1)))
7643 /* If the constant is a power of two minus one and the first operand
7644 is a logical right shift, make an extraction. */
7645 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7646 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7648 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7649 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7650 0, in_code
== COMPARE
);
7653 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7654 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7655 && subreg_lowpart_p (XEXP (x
, 0))
7656 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7657 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7659 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7661 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7662 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7663 0, in_code
== COMPARE
);
7665 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7666 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7667 || GET_CODE (XEXP (x
, 0)) == IOR
)
7668 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7669 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7670 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7672 /* Apply the distributive law, and then try to make extractions. */
7673 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7674 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7676 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7678 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7681 /* If we are have (and (rotate X C) M) and C is larger than the number
7682 of bits in M, this is an extraction. */
7684 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7685 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7686 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7687 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7689 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7690 new_rtx
= make_extraction (mode
, new_rtx
,
7691 (GET_MODE_PRECISION (mode
)
7692 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7693 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7696 /* On machines without logical shifts, if the operand of the AND is
7697 a logical shift and our mask turns off all the propagated sign
7698 bits, we can replace the logical shift with an arithmetic shift. */
7699 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7700 && !have_insn_for (LSHIFTRT
, mode
)
7701 && have_insn_for (ASHIFTRT
, mode
)
7702 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7703 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7704 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7705 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7707 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7709 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7710 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7712 gen_rtx_ASHIFTRT (mode
,
7713 make_compound_operation
7714 (XEXP (XEXP (x
, 0), 0), next_code
),
7715 XEXP (XEXP (x
, 0), 1)));
7718 /* If the constant is one less than a power of two, this might be
7719 representable by an extraction even if no shift is present.
7720 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7721 we are in a COMPARE. */
7722 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7723 new_rtx
= make_extraction (mode
,
7724 make_compound_operation (XEXP (x
, 0),
7726 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7728 /* If we are in a comparison and this is an AND with a power of two,
7729 convert this into the appropriate bit extract. */
7730 else if (in_code
== COMPARE
7731 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7732 new_rtx
= make_extraction (mode
,
7733 make_compound_operation (XEXP (x
, 0),
7735 i
, NULL_RTX
, 1, 1, 0, 1);
7740 /* If the sign bit is known to be zero, replace this with an
7741 arithmetic shift. */
7742 if (have_insn_for (ASHIFTRT
, mode
)
7743 && ! have_insn_for (LSHIFTRT
, mode
)
7744 && mode_width
<= HOST_BITS_PER_WIDE_INT
7745 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7747 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7748 make_compound_operation (XEXP (x
, 0),
7754 /* ... fall through ... */
7760 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7761 this is a SIGN_EXTRACT. */
7762 if (CONST_INT_P (rhs
)
7763 && GET_CODE (lhs
) == ASHIFT
7764 && CONST_INT_P (XEXP (lhs
, 1))
7765 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7766 && INTVAL (XEXP (lhs
, 1)) >= 0
7767 && INTVAL (rhs
) < mode_width
)
7769 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7770 new_rtx
= make_extraction (mode
, new_rtx
,
7771 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7772 NULL_RTX
, mode_width
- INTVAL (rhs
),
7773 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7777 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7778 If so, try to merge the shifts into a SIGN_EXTEND. We could
7779 also do this for some cases of SIGN_EXTRACT, but it doesn't
7780 seem worth the effort; the case checked for occurs on Alpha. */
7783 && ! (GET_CODE (lhs
) == SUBREG
7784 && (OBJECT_P (SUBREG_REG (lhs
))))
7785 && CONST_INT_P (rhs
)
7786 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7787 && INTVAL (rhs
) < mode_width
7788 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7789 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7790 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7791 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7796 /* Call ourselves recursively on the inner expression. If we are
7797 narrowing the object and it has a different RTL code from
7798 what it originally did, do this SUBREG as a force_to_mode. */
7800 rtx inner
= SUBREG_REG (x
), simplified
;
7801 enum rtx_code subreg_code
= in_code
;
7803 /* If in_code is COMPARE, it isn't always safe to pass it through
7804 to the recursive make_compound_operation call. */
7805 if (subreg_code
== COMPARE
7806 && (!subreg_lowpart_p (x
)
7807 || GET_CODE (inner
) == SUBREG
7808 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7809 is (const_int 0), rather than
7810 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7811 || (GET_CODE (inner
) == AND
7812 && CONST_INT_P (XEXP (inner
, 1))
7813 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7814 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
7815 >= GET_MODE_BITSIZE (mode
))))
7818 tem
= make_compound_operation (inner
, subreg_code
);
7821 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7825 if (GET_CODE (tem
) != GET_CODE (inner
)
7826 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7827 && subreg_lowpart_p (x
))
7830 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7832 /* If we have something other than a SUBREG, we might have
7833 done an expansion, so rerun ourselves. */
7834 if (GET_CODE (newer
) != SUBREG
)
7835 newer
= make_compound_operation (newer
, in_code
);
7837 /* force_to_mode can expand compounds. If it just re-expanded the
7838 compound, use gen_lowpart to convert to the desired mode. */
7839 if (rtx_equal_p (newer
, x
)
7840 /* Likewise if it re-expanded the compound only partially.
7841 This happens for SUBREG of ZERO_EXTRACT if they extract
7842 the same number of bits. */
7843 || (GET_CODE (newer
) == SUBREG
7844 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7845 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7846 && GET_CODE (inner
) == AND
7847 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7848 return gen_lowpart (GET_MODE (x
), tem
);
7864 x
= gen_lowpart (mode
, new_rtx
);
7865 code
= GET_CODE (x
);
7868 /* Now recursively process each operand of this operation. We need to
7869 handle ZERO_EXTEND specially so that we don't lose track of the
7871 if (GET_CODE (x
) == ZERO_EXTEND
)
7873 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7874 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7875 new_rtx
, GET_MODE (XEXP (x
, 0)));
7878 SUBST (XEXP (x
, 0), new_rtx
);
7882 fmt
= GET_RTX_FORMAT (code
);
7883 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7886 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7887 SUBST (XEXP (x
, i
), new_rtx
);
7889 else if (fmt
[i
] == 'E')
7890 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7892 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7893 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7897 /* If this is a commutative operation, the changes to the operands
7898 may have made it noncanonical. */
7899 if (COMMUTATIVE_ARITH_P (x
)
7900 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7903 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7904 SUBST (XEXP (x
, 1), tem
);
7910 /* Given M see if it is a value that would select a field of bits
7911 within an item, but not the entire word. Return -1 if not.
7912 Otherwise, return the starting position of the field, where 0 is the
7915 *PLEN is set to the length of the field. */
7918 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7920 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7921 int pos
= m
? ctz_hwi (m
) : -1;
7925 /* Now shift off the low-order zero bits and see if we have a
7926 power of two minus 1. */
7927 len
= exact_log2 ((m
>> pos
) + 1);
7936 /* If X refers to a register that equals REG in value, replace these
7937 references with REG. */
7939 canon_reg_for_combine (rtx x
, rtx reg
)
7946 enum rtx_code code
= GET_CODE (x
);
7947 switch (GET_RTX_CLASS (code
))
7950 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7951 if (op0
!= XEXP (x
, 0))
7952 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7957 case RTX_COMM_ARITH
:
7958 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7959 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7960 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7961 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7965 case RTX_COMM_COMPARE
:
7966 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7967 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7968 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7969 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7970 GET_MODE (op0
), op0
, op1
);
7974 case RTX_BITFIELD_OPS
:
7975 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7976 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7977 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7978 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7979 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7980 GET_MODE (op0
), op0
, op1
, op2
);
7985 if (rtx_equal_p (get_last_value (reg
), x
)
7986 || rtx_equal_p (reg
, get_last_value (x
)))
7995 fmt
= GET_RTX_FORMAT (code
);
7997 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8000 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8001 if (op
!= XEXP (x
, i
))
8011 else if (fmt
[i
] == 'E')
8014 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8016 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8017 if (op
!= XVECEXP (x
, i
, j
))
8024 XVECEXP (x
, i
, j
) = op
;
8035 /* Return X converted to MODE. If the value is already truncated to
8036 MODE we can just return a subreg even though in the general case we
8037 would need an explicit truncation. */
8040 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8042 if (!CONST_INT_P (x
)
8043 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8044 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8045 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8047 /* Bit-cast X into an integer mode. */
8048 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8049 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8050 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8054 return gen_lowpart (mode
, x
);
8057 /* See if X can be simplified knowing that we will only refer to it in
8058 MODE and will only refer to those bits that are nonzero in MASK.
8059 If other bits are being computed or if masking operations are done
8060 that select a superset of the bits in MASK, they can sometimes be
8063 Return a possibly simplified expression, but always convert X to
8064 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8066 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8067 are all off in X. This is used when X will be complemented, by either
8068 NOT, NEG, or XOR. */
8071 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8074 enum rtx_code code
= GET_CODE (x
);
8075 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8076 machine_mode op_mode
;
8077 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8080 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8081 code below will do the wrong thing since the mode of such an
8082 expression is VOIDmode.
8084 Also do nothing if X is a CLOBBER; this can happen if X was
8085 the return value from a call to gen_lowpart. */
8086 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8089 /* We want to perform the operation in its present mode unless we know
8090 that the operation is valid in MODE, in which case we do the operation
8092 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8093 && have_insn_for (code
, mode
))
8094 ? mode
: GET_MODE (x
));
8096 /* It is not valid to do a right-shift in a narrower mode
8097 than the one it came in with. */
8098 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8099 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8100 op_mode
= GET_MODE (x
);
8102 /* Truncate MASK to fit OP_MODE. */
8104 mask
&= GET_MODE_MASK (op_mode
);
8106 /* When we have an arithmetic operation, or a shift whose count we
8107 do not know, we need to assume that all bits up to the highest-order
8108 bit in MASK will be needed. This is how we form such a mask. */
8109 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8110 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8112 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8115 /* Determine what bits of X are guaranteed to be (non)zero. */
8116 nonzero
= nonzero_bits (x
, mode
);
8118 /* If none of the bits in X are needed, return a zero. */
8119 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8122 /* If X is a CONST_INT, return a new one. Do this here since the
8123 test below will fail. */
8124 if (CONST_INT_P (x
))
8126 if (SCALAR_INT_MODE_P (mode
))
8127 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8130 x
= GEN_INT (INTVAL (x
) & mask
);
8131 return gen_lowpart_common (mode
, x
);
8135 /* If X is narrower than MODE and we want all the bits in X's mode, just
8136 get X in the proper mode. */
8137 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8138 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8139 return gen_lowpart (mode
, x
);
8141 /* We can ignore the effect of a SUBREG if it narrows the mode or
8142 if the constant masks to zero all the bits the mode doesn't have. */
8143 if (GET_CODE (x
) == SUBREG
8144 && subreg_lowpart_p (x
)
8145 && ((GET_MODE_SIZE (GET_MODE (x
))
8146 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8148 & GET_MODE_MASK (GET_MODE (x
))
8149 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8150 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8152 /* The arithmetic simplifications here only work for scalar integer modes. */
8153 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8154 return gen_lowpart_or_truncate (mode
, x
);
8159 /* If X is a (clobber (const_int)), return it since we know we are
8160 generating something that won't match. */
8167 x
= expand_compound_operation (x
);
8168 if (GET_CODE (x
) != code
)
8169 return force_to_mode (x
, mode
, mask
, next_select
);
8173 /* Similarly for a truncate. */
8174 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8177 /* If this is an AND with a constant, convert it into an AND
8178 whose constant is the AND of that constant with MASK. If it
8179 remains an AND of MASK, delete it since it is redundant. */
8181 if (CONST_INT_P (XEXP (x
, 1)))
8183 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8184 mask
& INTVAL (XEXP (x
, 1)));
8186 /* If X is still an AND, see if it is an AND with a mask that
8187 is just some low-order bits. If so, and it is MASK, we don't
8190 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8191 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8195 /* If it remains an AND, try making another AND with the bits
8196 in the mode mask that aren't in MASK turned on. If the
8197 constant in the AND is wide enough, this might make a
8198 cheaper constant. */
8200 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8201 && GET_MODE_MASK (GET_MODE (x
)) != mask
8202 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8204 unsigned HOST_WIDE_INT cval
8205 = UINTVAL (XEXP (x
, 1))
8206 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8209 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8210 gen_int_mode (cval
, GET_MODE (x
)));
8211 if (set_src_cost (y
, optimize_this_for_speed_p
)
8212 < set_src_cost (x
, optimize_this_for_speed_p
))
8222 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8223 low-order bits (as in an alignment operation) and FOO is already
8224 aligned to that boundary, mask C1 to that boundary as well.
8225 This may eliminate that PLUS and, later, the AND. */
8228 unsigned int width
= GET_MODE_PRECISION (mode
);
8229 unsigned HOST_WIDE_INT smask
= mask
;
8231 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8232 number, sign extend it. */
8234 if (width
< HOST_BITS_PER_WIDE_INT
8235 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8236 smask
|= HOST_WIDE_INT_M1U
<< width
;
8238 if (CONST_INT_P (XEXP (x
, 1))
8239 && exact_log2 (- smask
) >= 0
8240 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8241 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8242 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8243 (INTVAL (XEXP (x
, 1)) & smask
)),
8244 mode
, smask
, next_select
);
8247 /* ... fall through ... */
8250 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8251 most significant bit in MASK since carries from those bits will
8252 affect the bits we are interested in. */
8257 /* If X is (minus C Y) where C's least set bit is larger than any bit
8258 in the mask, then we may replace with (neg Y). */
8259 if (CONST_INT_P (XEXP (x
, 0))
8260 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8262 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8264 return force_to_mode (x
, mode
, mask
, next_select
);
8267 /* Similarly, if C contains every bit in the fuller_mask, then we may
8268 replace with (not Y). */
8269 if (CONST_INT_P (XEXP (x
, 0))
8270 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8272 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8273 XEXP (x
, 1), GET_MODE (x
));
8274 return force_to_mode (x
, mode
, mask
, next_select
);
8282 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8283 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8284 operation which may be a bitfield extraction. Ensure that the
8285 constant we form is not wider than the mode of X. */
8287 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8288 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8289 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8290 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8291 && CONST_INT_P (XEXP (x
, 1))
8292 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8293 + floor_log2 (INTVAL (XEXP (x
, 1))))
8294 < GET_MODE_PRECISION (GET_MODE (x
)))
8295 && (UINTVAL (XEXP (x
, 1))
8296 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8298 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8299 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8301 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8302 XEXP (XEXP (x
, 0), 0), temp
);
8303 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8304 XEXP (XEXP (x
, 0), 1));
8305 return force_to_mode (x
, mode
, mask
, next_select
);
8309 /* For most binary operations, just propagate into the operation and
8310 change the mode if we have an operation of that mode. */
8312 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8313 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8315 /* If we ended up truncating both operands, truncate the result of the
8316 operation instead. */
8317 if (GET_CODE (op0
) == TRUNCATE
8318 && GET_CODE (op1
) == TRUNCATE
)
8320 op0
= XEXP (op0
, 0);
8321 op1
= XEXP (op1
, 0);
8324 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8325 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8327 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8328 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8332 /* For left shifts, do the same, but just for the first operand.
8333 However, we cannot do anything with shifts where we cannot
8334 guarantee that the counts are smaller than the size of the mode
8335 because such a count will have a different meaning in a
8338 if (! (CONST_INT_P (XEXP (x
, 1))
8339 && INTVAL (XEXP (x
, 1)) >= 0
8340 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8341 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8342 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8343 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8346 /* If the shift count is a constant and we can do arithmetic in
8347 the mode of the shift, refine which bits we need. Otherwise, use the
8348 conservative form of the mask. */
8349 if (CONST_INT_P (XEXP (x
, 1))
8350 && INTVAL (XEXP (x
, 1)) >= 0
8351 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8352 && HWI_COMPUTABLE_MODE_P (op_mode
))
8353 mask
>>= INTVAL (XEXP (x
, 1));
8357 op0
= gen_lowpart_or_truncate (op_mode
,
8358 force_to_mode (XEXP (x
, 0), op_mode
,
8359 mask
, next_select
));
8361 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8362 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8366 /* Here we can only do something if the shift count is a constant,
8367 this shift constant is valid for the host, and we can do arithmetic
8370 if (CONST_INT_P (XEXP (x
, 1))
8371 && INTVAL (XEXP (x
, 1)) >= 0
8372 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8373 && HWI_COMPUTABLE_MODE_P (op_mode
))
8375 rtx inner
= XEXP (x
, 0);
8376 unsigned HOST_WIDE_INT inner_mask
;
8378 /* Select the mask of the bits we need for the shift operand. */
8379 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8381 /* We can only change the mode of the shift if we can do arithmetic
8382 in the mode of the shift and INNER_MASK is no wider than the
8383 width of X's mode. */
8384 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8385 op_mode
= GET_MODE (x
);
8387 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8389 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8390 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8393 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8394 shift and AND produces only copies of the sign bit (C2 is one less
8395 than a power of two), we can do this with just a shift. */
8397 if (GET_CODE (x
) == LSHIFTRT
8398 && CONST_INT_P (XEXP (x
, 1))
8399 /* The shift puts one of the sign bit copies in the least significant
8401 && ((INTVAL (XEXP (x
, 1))
8402 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8403 >= GET_MODE_PRECISION (GET_MODE (x
)))
8404 && exact_log2 (mask
+ 1) >= 0
8405 /* Number of bits left after the shift must be more than the mask
8407 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8408 <= GET_MODE_PRECISION (GET_MODE (x
)))
8409 /* Must be more sign bit copies than the mask needs. */
8410 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8411 >= exact_log2 (mask
+ 1)))
8412 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8413 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8414 - exact_log2 (mask
+ 1)));
8419 /* If we are just looking for the sign bit, we don't need this shift at
8420 all, even if it has a variable count. */
8421 if (val_signbit_p (GET_MODE (x
), mask
))
8422 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8424 /* If this is a shift by a constant, get a mask that contains those bits
8425 that are not copies of the sign bit. We then have two cases: If
8426 MASK only includes those bits, this can be a logical shift, which may
8427 allow simplifications. If MASK is a single-bit field not within
8428 those bits, we are requesting a copy of the sign bit and hence can
8429 shift the sign bit to the appropriate location. */
8431 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8432 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8436 /* If the considered data is wider than HOST_WIDE_INT, we can't
8437 represent a mask for all its bits in a single scalar.
8438 But we only care about the lower bits, so calculate these. */
8440 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8442 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8444 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8445 is the number of bits a full-width mask would have set.
8446 We need only shift if these are fewer than nonzero can
8447 hold. If not, we must keep all bits set in nonzero. */
8449 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8450 < HOST_BITS_PER_WIDE_INT
)
8451 nonzero
>>= INTVAL (XEXP (x
, 1))
8452 + HOST_BITS_PER_WIDE_INT
8453 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8457 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8458 nonzero
>>= INTVAL (XEXP (x
, 1));
8461 if ((mask
& ~nonzero
) == 0)
8463 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8464 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8465 if (GET_CODE (x
) != ASHIFTRT
)
8466 return force_to_mode (x
, mode
, mask
, next_select
);
8469 else if ((i
= exact_log2 (mask
)) >= 0)
8471 x
= simplify_shift_const
8472 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8473 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8475 if (GET_CODE (x
) != ASHIFTRT
)
8476 return force_to_mode (x
, mode
, mask
, next_select
);
8480 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8481 even if the shift count isn't a constant. */
8483 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8484 XEXP (x
, 0), XEXP (x
, 1));
8488 /* If this is a zero- or sign-extension operation that just affects bits
8489 we don't care about, remove it. Be sure the call above returned
8490 something that is still a shift. */
8492 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8493 && CONST_INT_P (XEXP (x
, 1))
8494 && INTVAL (XEXP (x
, 1)) >= 0
8495 && (INTVAL (XEXP (x
, 1))
8496 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8497 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8498 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8499 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8506 /* If the shift count is constant and we can do computations
8507 in the mode of X, compute where the bits we care about are.
8508 Otherwise, we can't do anything. Don't change the mode of
8509 the shift or propagate MODE into the shift, though. */
8510 if (CONST_INT_P (XEXP (x
, 1))
8511 && INTVAL (XEXP (x
, 1)) >= 0)
8513 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8515 gen_int_mode (mask
, GET_MODE (x
)),
8517 if (temp
&& CONST_INT_P (temp
))
8518 x
= simplify_gen_binary (code
, GET_MODE (x
),
8519 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8520 INTVAL (temp
), next_select
),
8526 /* If we just want the low-order bit, the NEG isn't needed since it
8527 won't change the low-order bit. */
8529 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8531 /* We need any bits less significant than the most significant bit in
8532 MASK since carries from those bits will affect the bits we are
8538 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8539 same as the XOR case above. Ensure that the constant we form is not
8540 wider than the mode of X. */
8542 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8543 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8544 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8545 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8546 < GET_MODE_PRECISION (GET_MODE (x
)))
8547 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8549 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8551 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8552 XEXP (XEXP (x
, 0), 0), temp
);
8553 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8554 temp
, XEXP (XEXP (x
, 0), 1));
8556 return force_to_mode (x
, mode
, mask
, next_select
);
8559 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8560 use the full mask inside the NOT. */
8564 op0
= gen_lowpart_or_truncate (op_mode
,
8565 force_to_mode (XEXP (x
, 0), mode
, mask
,
8567 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8568 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8572 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8573 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8574 which is equal to STORE_FLAG_VALUE. */
8575 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8576 && XEXP (x
, 1) == const0_rtx
8577 && GET_MODE (XEXP (x
, 0)) == mode
8578 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8579 && (nonzero_bits (XEXP (x
, 0), mode
)
8580 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8581 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8586 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8587 written in a narrower mode. We play it safe and do not do so. */
8589 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8590 force_to_mode (XEXP (x
, 1), mode
,
8591 mask
, next_select
));
8592 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8593 force_to_mode (XEXP (x
, 2), mode
,
8594 mask
, next_select
));
8595 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8596 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8597 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8605 /* Ensure we return a value of the proper mode. */
8606 return gen_lowpart_or_truncate (mode
, x
);
8609 /* Return nonzero if X is an expression that has one of two values depending on
8610 whether some other value is zero or nonzero. In that case, we return the
8611 value that is being tested, *PTRUE is set to the value if the rtx being
8612 returned has a nonzero value, and *PFALSE is set to the other alternative.
8614 If we return zero, we set *PTRUE and *PFALSE to X. */
8617 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8619 machine_mode mode
= GET_MODE (x
);
8620 enum rtx_code code
= GET_CODE (x
);
8621 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8622 unsigned HOST_WIDE_INT nz
;
8624 /* If we are comparing a value against zero, we are done. */
8625 if ((code
== NE
|| code
== EQ
)
8626 && XEXP (x
, 1) == const0_rtx
)
8628 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8629 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8633 /* If this is a unary operation whose operand has one of two values, apply
8634 our opcode to compute those values. */
8635 else if (UNARY_P (x
)
8636 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8638 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8639 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8640 GET_MODE (XEXP (x
, 0)));
8644 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8645 make can't possibly match and would suppress other optimizations. */
8646 else if (code
== COMPARE
)
8649 /* If this is a binary operation, see if either side has only one of two
8650 values. If either one does or if both do and they are conditional on
8651 the same value, compute the new true and false values. */
8652 else if (BINARY_P (x
))
8654 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8655 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8657 if ((cond0
!= 0 || cond1
!= 0)
8658 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8660 /* If if_then_else_cond returned zero, then true/false are the
8661 same rtl. We must copy one of them to prevent invalid rtl
8664 true0
= copy_rtx (true0
);
8665 else if (cond1
== 0)
8666 true1
= copy_rtx (true1
);
8668 if (COMPARISON_P (x
))
8670 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8672 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8677 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8678 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8681 return cond0
? cond0
: cond1
;
8684 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8685 operands is zero when the other is nonzero, and vice-versa,
8686 and STORE_FLAG_VALUE is 1 or -1. */
8688 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8689 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8691 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8693 rtx op0
= XEXP (XEXP (x
, 0), 1);
8694 rtx op1
= XEXP (XEXP (x
, 1), 1);
8696 cond0
= XEXP (XEXP (x
, 0), 0);
8697 cond1
= XEXP (XEXP (x
, 1), 0);
8699 if (COMPARISON_P (cond0
)
8700 && COMPARISON_P (cond1
)
8701 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8702 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8703 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8704 || ((swap_condition (GET_CODE (cond0
))
8705 == reversed_comparison_code (cond1
, NULL
))
8706 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8707 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8708 && ! side_effects_p (x
))
8710 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8711 *pfalse
= simplify_gen_binary (MULT
, mode
,
8713 ? simplify_gen_unary (NEG
, mode
,
8721 /* Similarly for MULT, AND and UMIN, except that for these the result
8723 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8724 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8725 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8727 cond0
= XEXP (XEXP (x
, 0), 0);
8728 cond1
= XEXP (XEXP (x
, 1), 0);
8730 if (COMPARISON_P (cond0
)
8731 && COMPARISON_P (cond1
)
8732 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8733 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8734 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8735 || ((swap_condition (GET_CODE (cond0
))
8736 == reversed_comparison_code (cond1
, NULL
))
8737 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8738 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8739 && ! side_effects_p (x
))
8741 *ptrue
= *pfalse
= const0_rtx
;
8747 else if (code
== IF_THEN_ELSE
)
8749 /* If we have IF_THEN_ELSE already, extract the condition and
8750 canonicalize it if it is NE or EQ. */
8751 cond0
= XEXP (x
, 0);
8752 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8753 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8754 return XEXP (cond0
, 0);
8755 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8757 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8758 return XEXP (cond0
, 0);
8764 /* If X is a SUBREG, we can narrow both the true and false values
8765 if the inner expression, if there is a condition. */
8766 else if (code
== SUBREG
8767 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8770 true0
= simplify_gen_subreg (mode
, true0
,
8771 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8772 false0
= simplify_gen_subreg (mode
, false0
,
8773 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8774 if (true0
&& false0
)
8782 /* If X is a constant, this isn't special and will cause confusions
8783 if we treat it as such. Likewise if it is equivalent to a constant. */
8784 else if (CONSTANT_P (x
)
8785 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8788 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8789 will be least confusing to the rest of the compiler. */
8790 else if (mode
== BImode
)
8792 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8796 /* If X is known to be either 0 or -1, those are the true and
8797 false values when testing X. */
8798 else if (x
== constm1_rtx
|| x
== const0_rtx
8799 || (mode
!= VOIDmode
8800 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8802 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8806 /* Likewise for 0 or a single bit. */
8807 else if (HWI_COMPUTABLE_MODE_P (mode
)
8808 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8810 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8814 /* Otherwise fail; show no condition with true and false values the same. */
8815 *ptrue
= *pfalse
= x
;
8819 /* Return the value of expression X given the fact that condition COND
8820 is known to be true when applied to REG as its first operand and VAL
8821 as its second. X is known to not be shared and so can be modified in
8824 We only handle the simplest cases, and specifically those cases that
8825 arise with IF_THEN_ELSE expressions. */
8828 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8830 enum rtx_code code
= GET_CODE (x
);
8835 if (side_effects_p (x
))
8838 /* If either operand of the condition is a floating point value,
8839 then we have to avoid collapsing an EQ comparison. */
8841 && rtx_equal_p (x
, reg
)
8842 && ! FLOAT_MODE_P (GET_MODE (x
))
8843 && ! FLOAT_MODE_P (GET_MODE (val
)))
8846 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8849 /* If X is (abs REG) and we know something about REG's relationship
8850 with zero, we may be able to simplify this. */
8852 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8855 case GE
: case GT
: case EQ
:
8858 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8860 GET_MODE (XEXP (x
, 0)));
8865 /* The only other cases we handle are MIN, MAX, and comparisons if the
8866 operands are the same as REG and VAL. */
8868 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8870 if (rtx_equal_p (XEXP (x
, 0), val
))
8871 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8873 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8875 if (COMPARISON_P (x
))
8877 if (comparison_dominates_p (cond
, code
))
8878 return const_true_rtx
;
8880 code
= reversed_comparison_code (x
, NULL
);
8882 && comparison_dominates_p (cond
, code
))
8887 else if (code
== SMAX
|| code
== SMIN
8888 || code
== UMIN
|| code
== UMAX
)
8890 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8892 /* Do not reverse the condition when it is NE or EQ.
8893 This is because we cannot conclude anything about
8894 the value of 'SMAX (x, y)' when x is not equal to y,
8895 but we can when x equals y. */
8896 if ((code
== SMAX
|| code
== UMAX
)
8897 && ! (cond
== EQ
|| cond
== NE
))
8898 cond
= reverse_condition (cond
);
8903 return unsignedp
? x
: XEXP (x
, 1);
8905 return unsignedp
? x
: XEXP (x
, 0);
8907 return unsignedp
? XEXP (x
, 1) : x
;
8909 return unsignedp
? XEXP (x
, 0) : x
;
8916 else if (code
== SUBREG
)
8918 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8919 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8921 if (SUBREG_REG (x
) != r
)
8923 /* We must simplify subreg here, before we lose track of the
8924 original inner_mode. */
8925 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8926 inner_mode
, SUBREG_BYTE (x
));
8930 SUBST (SUBREG_REG (x
), r
);
8935 /* We don't have to handle SIGN_EXTEND here, because even in the
8936 case of replacing something with a modeless CONST_INT, a
8937 CONST_INT is already (supposed to be) a valid sign extension for
8938 its narrower mode, which implies it's already properly
8939 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8940 story is different. */
8941 else if (code
== ZERO_EXTEND
)
8943 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8944 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8946 if (XEXP (x
, 0) != r
)
8948 /* We must simplify the zero_extend here, before we lose
8949 track of the original inner_mode. */
8950 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8955 SUBST (XEXP (x
, 0), r
);
8961 fmt
= GET_RTX_FORMAT (code
);
8962 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8965 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8966 else if (fmt
[i
] == 'E')
8967 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8968 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8975 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8976 assignment as a field assignment. */
8979 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8981 if (x
== y
|| rtx_equal_p (x
, y
))
8984 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8987 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8988 Note that all SUBREGs of MEM are paradoxical; otherwise they
8989 would have been rewritten. */
8990 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8991 && MEM_P (SUBREG_REG (y
))
8992 && rtx_equal_p (SUBREG_REG (y
),
8993 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8996 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8997 && MEM_P (SUBREG_REG (x
))
8998 && rtx_equal_p (SUBREG_REG (x
),
8999 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9002 /* We used to see if get_last_value of X and Y were the same but that's
9003 not correct. In one direction, we'll cause the assignment to have
9004 the wrong destination and in the case, we'll import a register into this
9005 insn that might have already have been dead. So fail if none of the
9006 above cases are true. */
9010 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9011 Return that assignment if so.
9013 We only handle the most common cases. */
9016 make_field_assignment (rtx x
)
9018 rtx dest
= SET_DEST (x
);
9019 rtx src
= SET_SRC (x
);
9024 unsigned HOST_WIDE_INT len
;
9028 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9029 a clear of a one-bit field. We will have changed it to
9030 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9033 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9034 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9035 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9036 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9038 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9041 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9045 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9046 && subreg_lowpart_p (XEXP (src
, 0))
9047 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9048 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9049 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9050 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9051 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9052 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9054 assign
= make_extraction (VOIDmode
, dest
, 0,
9055 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9058 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9062 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9064 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9065 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9066 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9068 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9071 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9075 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9076 SRC is an AND with all bits of that field set, then we can discard
9078 if (GET_CODE (dest
) == ZERO_EXTRACT
9079 && CONST_INT_P (XEXP (dest
, 1))
9080 && GET_CODE (src
) == AND
9081 && CONST_INT_P (XEXP (src
, 1)))
9083 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9084 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9085 unsigned HOST_WIDE_INT ze_mask
;
9087 if (width
>= HOST_BITS_PER_WIDE_INT
)
9090 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9092 /* Complete overlap. We can remove the source AND. */
9093 if ((and_mask
& ze_mask
) == ze_mask
)
9094 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9096 /* Partial overlap. We can reduce the source AND. */
9097 if ((and_mask
& ze_mask
) != and_mask
)
9099 mode
= GET_MODE (src
);
9100 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9101 gen_int_mode (and_mask
& ze_mask
, mode
));
9102 return gen_rtx_SET (VOIDmode
, dest
, src
);
9106 /* The other case we handle is assignments into a constant-position
9107 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9108 a mask that has all one bits except for a group of zero bits and
9109 OTHER is known to have zeros where C1 has ones, this is such an
9110 assignment. Compute the position and length from C1. Shift OTHER
9111 to the appropriate position, force it to the required mode, and
9112 make the extraction. Check for the AND in both operands. */
9114 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9117 rhs
= expand_compound_operation (XEXP (src
, 0));
9118 lhs
= expand_compound_operation (XEXP (src
, 1));
9120 if (GET_CODE (rhs
) == AND
9121 && CONST_INT_P (XEXP (rhs
, 1))
9122 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9123 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9124 else if (GET_CODE (lhs
) == AND
9125 && CONST_INT_P (XEXP (lhs
, 1))
9126 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9127 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9131 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9132 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9133 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9134 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9137 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9141 /* The mode to use for the source is the mode of the assignment, or of
9142 what is inside a possible STRICT_LOW_PART. */
9143 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9144 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9146 /* Shift OTHER right POS places and make it the source, restricting it
9147 to the proper length and mode. */
9149 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9153 src
= force_to_mode (src
, mode
,
9154 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9155 ? ~(unsigned HOST_WIDE_INT
) 0
9156 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9159 /* If SRC is masked by an AND that does not make a difference in
9160 the value being stored, strip it. */
9161 if (GET_CODE (assign
) == ZERO_EXTRACT
9162 && CONST_INT_P (XEXP (assign
, 1))
9163 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9164 && GET_CODE (src
) == AND
9165 && CONST_INT_P (XEXP (src
, 1))
9166 && UINTVAL (XEXP (src
, 1))
9167 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9168 src
= XEXP (src
, 0);
9170 return gen_rtx_SET (VOIDmode
, assign
, src
);
9173 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9177 apply_distributive_law (rtx x
)
9179 enum rtx_code code
= GET_CODE (x
);
9180 enum rtx_code inner_code
;
9181 rtx lhs
, rhs
, other
;
9184 /* Distributivity is not true for floating point as it can change the
9185 value. So we don't do it unless -funsafe-math-optimizations. */
9186 if (FLOAT_MODE_P (GET_MODE (x
))
9187 && ! flag_unsafe_math_optimizations
)
9190 /* The outer operation can only be one of the following: */
9191 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9192 && code
!= PLUS
&& code
!= MINUS
)
9198 /* If either operand is a primitive we can't do anything, so get out
9200 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9203 lhs
= expand_compound_operation (lhs
);
9204 rhs
= expand_compound_operation (rhs
);
9205 inner_code
= GET_CODE (lhs
);
9206 if (inner_code
!= GET_CODE (rhs
))
9209 /* See if the inner and outer operations distribute. */
9216 /* These all distribute except over PLUS. */
9217 if (code
== PLUS
|| code
== MINUS
)
9222 if (code
!= PLUS
&& code
!= MINUS
)
9227 /* This is also a multiply, so it distributes over everything. */
9230 /* This used to handle SUBREG, but this turned out to be counter-
9231 productive, since (subreg (op ...)) usually is not handled by
9232 insn patterns, and this "optimization" therefore transformed
9233 recognizable patterns into unrecognizable ones. Therefore the
9234 SUBREG case was removed from here.
9236 It is possible that distributing SUBREG over arithmetic operations
9237 leads to an intermediate result than can then be optimized further,
9238 e.g. by moving the outer SUBREG to the other side of a SET as done
9239 in simplify_set. This seems to have been the original intent of
9240 handling SUBREGs here.
9242 However, with current GCC this does not appear to actually happen,
9243 at least on major platforms. If some case is found where removing
9244 the SUBREG case here prevents follow-on optimizations, distributing
9245 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9251 /* Set LHS and RHS to the inner operands (A and B in the example
9252 above) and set OTHER to the common operand (C in the example).
9253 There is only one way to do this unless the inner operation is
9255 if (COMMUTATIVE_ARITH_P (lhs
)
9256 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9257 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9258 else if (COMMUTATIVE_ARITH_P (lhs
)
9259 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9260 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9261 else if (COMMUTATIVE_ARITH_P (lhs
)
9262 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9263 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9264 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9265 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9269 /* Form the new inner operation, seeing if it simplifies first. */
9270 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9272 /* There is one exception to the general way of distributing:
9273 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9274 if (code
== XOR
&& inner_code
== IOR
)
9277 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9280 /* We may be able to continuing distributing the result, so call
9281 ourselves recursively on the inner operation before forming the
9282 outer operation, which we return. */
9283 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9284 apply_distributive_law (tem
), other
);
9287 /* See if X is of the form (* (+ A B) C), and if so convert to
9288 (+ (* A C) (* B C)) and try to simplify.
9290 Most of the time, this results in no change. However, if some of
9291 the operands are the same or inverses of each other, simplifications
9294 For example, (and (ior A B) (not B)) can occur as the result of
9295 expanding a bit field assignment. When we apply the distributive
9296 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9297 which then simplifies to (and (A (not B))).
9299 Note that no checks happen on the validity of applying the inverse
9300 distributive law. This is pointless since we can do it in the
9301 few places where this routine is called.
9303 N is the index of the term that is decomposed (the arithmetic operation,
9304 i.e. (+ A B) in the first example above). !N is the index of the term that
9305 is distributed, i.e. of C in the first example above. */
9307 distribute_and_simplify_rtx (rtx x
, int n
)
9310 enum rtx_code outer_code
, inner_code
;
9311 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9313 /* Distributivity is not true for floating point as it can change the
9314 value. So we don't do it unless -funsafe-math-optimizations. */
9315 if (FLOAT_MODE_P (GET_MODE (x
))
9316 && ! flag_unsafe_math_optimizations
)
9319 decomposed
= XEXP (x
, n
);
9320 if (!ARITHMETIC_P (decomposed
))
9323 mode
= GET_MODE (x
);
9324 outer_code
= GET_CODE (x
);
9325 distributed
= XEXP (x
, !n
);
9327 inner_code
= GET_CODE (decomposed
);
9328 inner_op0
= XEXP (decomposed
, 0);
9329 inner_op1
= XEXP (decomposed
, 1);
9331 /* Special case (and (xor B C) (not A)), which is equivalent to
9332 (xor (ior A B) (ior A C)) */
9333 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9335 distributed
= XEXP (distributed
, 0);
9341 /* Distribute the second term. */
9342 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9343 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9347 /* Distribute the first term. */
9348 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9349 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9352 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9354 if (GET_CODE (tmp
) != outer_code
9355 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9356 < set_src_cost (x
, optimize_this_for_speed_p
)))
9362 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9363 in MODE. Return an equivalent form, if different from (and VAROP
9364 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9367 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9368 unsigned HOST_WIDE_INT constop
)
9370 unsigned HOST_WIDE_INT nonzero
;
9371 unsigned HOST_WIDE_INT orig_constop
;
9376 orig_constop
= constop
;
9377 if (GET_CODE (varop
) == CLOBBER
)
9380 /* Simplify VAROP knowing that we will be only looking at some of the
9383 Note by passing in CONSTOP, we guarantee that the bits not set in
9384 CONSTOP are not significant and will never be examined. We must
9385 ensure that is the case by explicitly masking out those bits
9386 before returning. */
9387 varop
= force_to_mode (varop
, mode
, constop
, 0);
9389 /* If VAROP is a CLOBBER, we will fail so return it. */
9390 if (GET_CODE (varop
) == CLOBBER
)
9393 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9394 to VAROP and return the new constant. */
9395 if (CONST_INT_P (varop
))
9396 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9398 /* See what bits may be nonzero in VAROP. Unlike the general case of
9399 a call to nonzero_bits, here we don't care about bits outside
9402 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9404 /* Turn off all bits in the constant that are known to already be zero.
9405 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9406 which is tested below. */
9410 /* If we don't have any bits left, return zero. */
9414 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9415 a power of two, we can replace this with an ASHIFT. */
9416 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9417 && (i
= exact_log2 (constop
)) >= 0)
9418 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9420 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9421 or XOR, then try to apply the distributive law. This may eliminate
9422 operations if either branch can be simplified because of the AND.
9423 It may also make some cases more complex, but those cases probably
9424 won't match a pattern either with or without this. */
9426 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9430 apply_distributive_law
9431 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9432 simplify_and_const_int (NULL_RTX
,
9436 simplify_and_const_int (NULL_RTX
,
9441 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9442 the AND and see if one of the operands simplifies to zero. If so, we
9443 may eliminate it. */
9445 if (GET_CODE (varop
) == PLUS
9446 && exact_log2 (constop
+ 1) >= 0)
9450 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9451 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9452 if (o0
== const0_rtx
)
9454 if (o1
== const0_rtx
)
9458 /* Make a SUBREG if necessary. If we can't make it, fail. */
9459 varop
= gen_lowpart (mode
, varop
);
9460 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9463 /* If we are only masking insignificant bits, return VAROP. */
9464 if (constop
== nonzero
)
9467 if (varop
== orig_varop
&& constop
== orig_constop
)
9470 /* Otherwise, return an AND. */
9471 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9475 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9478 Return an equivalent form, if different from X. Otherwise, return X. If
9479 X is zero, we are to always construct the equivalent form. */
9482 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9483 unsigned HOST_WIDE_INT constop
)
9485 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9490 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9491 gen_int_mode (constop
, mode
));
9492 if (GET_MODE (x
) != mode
)
9493 x
= gen_lowpart (mode
, x
);
9497 /* Given a REG, X, compute which bits in X can be nonzero.
9498 We don't care about bits outside of those defined in MODE.
9500 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9501 a shift, AND, or zero_extract, we can do better. */
9504 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9505 const_rtx known_x ATTRIBUTE_UNUSED
,
9506 machine_mode known_mode ATTRIBUTE_UNUSED
,
9507 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9508 unsigned HOST_WIDE_INT
*nonzero
)
9513 /* If X is a register whose nonzero bits value is current, use it.
9514 Otherwise, if X is a register whose value we can find, use that
9515 value. Otherwise, use the previously-computed global nonzero bits
9516 for this register. */
9518 rsp
= ®_stat
[REGNO (x
)];
9519 if (rsp
->last_set_value
!= 0
9520 && (rsp
->last_set_mode
== mode
9521 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9522 && GET_MODE_CLASS (mode
) == MODE_INT
))
9523 && ((rsp
->last_set_label
>= label_tick_ebb_start
9524 && rsp
->last_set_label
< label_tick
)
9525 || (rsp
->last_set_label
== label_tick
9526 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9527 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9528 && REG_N_SETS (REGNO (x
)) == 1
9530 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9533 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9535 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9536 /* We don't know anything about the upper bits. */
9537 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9543 tem
= get_last_value (x
);
9547 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9548 /* If X is narrower than MODE and TEM is a non-negative
9549 constant that would appear negative in the mode of X,
9550 sign-extend it for use in reg_nonzero_bits because some
9551 machines (maybe most) will actually do the sign-extension
9552 and this is the conservative approach.
9554 ??? For 2.5, try to tighten up the MD files in this regard
9555 instead of this kludge. */
9557 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9558 && CONST_INT_P (tem
)
9560 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9561 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9565 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9567 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9569 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9570 /* We don't know anything about the upper bits. */
9571 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9579 /* Return the number of bits at the high-order end of X that are known to
9580 be equal to the sign bit. X will be used in mode MODE; if MODE is
9581 VOIDmode, X will be used in its own mode. The returned value will always
9582 be between 1 and the number of bits in MODE. */
9585 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
9586 const_rtx known_x ATTRIBUTE_UNUSED
,
9587 machine_mode known_mode
9589 unsigned int known_ret ATTRIBUTE_UNUSED
,
9590 unsigned int *result
)
9595 rsp
= ®_stat
[REGNO (x
)];
9596 if (rsp
->last_set_value
!= 0
9597 && rsp
->last_set_mode
== mode
9598 && ((rsp
->last_set_label
>= label_tick_ebb_start
9599 && rsp
->last_set_label
< label_tick
)
9600 || (rsp
->last_set_label
== label_tick
9601 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9602 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9603 && REG_N_SETS (REGNO (x
)) == 1
9605 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9608 *result
= rsp
->last_set_sign_bit_copies
;
9612 tem
= get_last_value (x
);
9616 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9617 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9618 *result
= rsp
->sign_bit_copies
;
9623 /* Return the number of "extended" bits there are in X, when interpreted
9624 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9625 unsigned quantities, this is the number of high-order zero bits.
9626 For signed quantities, this is the number of copies of the sign bit
9627 minus 1. In both case, this function returns the number of "spare"
9628 bits. For example, if two quantities for which this function returns
9629 at least 1 are added, the addition is known not to overflow.
9631 This function will always return 0 unless called during combine, which
9632 implies that it must be called from a define_split. */
9635 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
9637 if (nonzero_sign_valid
== 0)
9641 ? (HWI_COMPUTABLE_MODE_P (mode
)
9642 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9643 - floor_log2 (nonzero_bits (x
, mode
)))
9645 : num_sign_bit_copies (x
, mode
) - 1);
9648 /* This function is called from `simplify_shift_const' to merge two
9649 outer operations. Specifically, we have already found that we need
9650 to perform operation *POP0 with constant *PCONST0 at the outermost
9651 position. We would now like to also perform OP1 with constant CONST1
9652 (with *POP0 being done last).
9654 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9655 the resulting operation. *PCOMP_P is set to 1 if we would need to
9656 complement the innermost operand, otherwise it is unchanged.
9658 MODE is the mode in which the operation will be done. No bits outside
9659 the width of this mode matter. It is assumed that the width of this mode
9660 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9662 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9663 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9664 result is simply *PCONST0.
9666 If the resulting operation cannot be expressed as one operation, we
9667 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9670 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
9672 enum rtx_code op0
= *pop0
;
9673 HOST_WIDE_INT const0
= *pconst0
;
9675 const0
&= GET_MODE_MASK (mode
);
9676 const1
&= GET_MODE_MASK (mode
);
9678 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9682 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9685 if (op1
== UNKNOWN
|| op0
== SET
)
9688 else if (op0
== UNKNOWN
)
9689 op0
= op1
, const0
= const1
;
9691 else if (op0
== op1
)
9715 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9716 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9719 /* If the two constants aren't the same, we can't do anything. The
9720 remaining six cases can all be done. */
9721 else if (const0
!= const1
)
9729 /* (a & b) | b == b */
9731 else /* op1 == XOR */
9732 /* (a ^ b) | b == a | b */
9738 /* (a & b) ^ b == (~a) & b */
9739 op0
= AND
, *pcomp_p
= 1;
9740 else /* op1 == IOR */
9741 /* (a | b) ^ b == a & ~b */
9742 op0
= AND
, const0
= ~const0
;
9747 /* (a | b) & b == b */
9749 else /* op1 == XOR */
9750 /* (a ^ b) & b) == (~a) & b */
9757 /* Check for NO-OP cases. */
9758 const0
&= GET_MODE_MASK (mode
);
9760 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9762 else if (const0
== 0 && op0
== AND
)
9764 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9770 /* ??? Slightly redundant with the above mask, but not entirely.
9771 Moving this above means we'd have to sign-extend the mode mask
9772 for the final test. */
9773 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9774 *pconst0
= trunc_int_for_mode (const0
, mode
);
9779 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9780 the shift in. The original shift operation CODE is performed on OP in
9781 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9782 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9783 result of the shift is subject to operation OUTER_CODE with operand
9787 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9788 machine_mode orig_mode
, machine_mode mode
,
9789 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9791 if (orig_mode
== mode
)
9793 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9795 /* In general we can't perform in wider mode for right shift and rotate. */
9799 /* We can still widen if the bits brought in from the left are identical
9800 to the sign bit of ORIG_MODE. */
9801 if (num_sign_bit_copies (op
, mode
)
9802 > (unsigned) (GET_MODE_PRECISION (mode
)
9803 - GET_MODE_PRECISION (orig_mode
)))
9808 /* Similarly here but with zero bits. */
9809 if (HWI_COMPUTABLE_MODE_P (mode
)
9810 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9813 /* We can also widen if the bits brought in will be masked off. This
9814 operation is performed in ORIG_MODE. */
9815 if (outer_code
== AND
)
9817 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9820 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9836 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9837 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9838 if we cannot simplify it. Otherwise, return a simplified value.
9840 The shift is normally computed in the widest mode we find in VAROP, as
9841 long as it isn't a different number of words than RESULT_MODE. Exceptions
9842 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9845 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
9846 rtx varop
, int orig_count
)
9848 enum rtx_code orig_code
= code
;
9849 rtx orig_varop
= varop
;
9851 machine_mode mode
= result_mode
;
9852 machine_mode shift_mode
, tmode
;
9853 unsigned int mode_words
9854 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9855 /* We form (outer_op (code varop count) (outer_const)). */
9856 enum rtx_code outer_op
= UNKNOWN
;
9857 HOST_WIDE_INT outer_const
= 0;
9858 int complement_p
= 0;
9861 /* Make sure and truncate the "natural" shift on the way in. We don't
9862 want to do this inside the loop as it makes it more difficult to
9864 if (SHIFT_COUNT_TRUNCATED
)
9865 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9867 /* If we were given an invalid count, don't do anything except exactly
9868 what was requested. */
9870 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9875 /* Unless one of the branches of the `if' in this loop does a `continue',
9876 we will `break' the loop after the `if'. */
9880 /* If we have an operand of (clobber (const_int 0)), fail. */
9881 if (GET_CODE (varop
) == CLOBBER
)
9884 /* Convert ROTATERT to ROTATE. */
9885 if (code
== ROTATERT
)
9887 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9889 if (VECTOR_MODE_P (result_mode
))
9890 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9892 count
= bitsize
- count
;
9895 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9896 mode
, outer_op
, outer_const
);
9898 /* Handle cases where the count is greater than the size of the mode
9899 minus 1. For ASHIFT, use the size minus one as the count (this can
9900 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9901 take the count modulo the size. For other shifts, the result is
9904 Since these shifts are being produced by the compiler by combining
9905 multiple operations, each of which are defined, we know what the
9906 result is supposed to be. */
9908 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9910 if (code
== ASHIFTRT
)
9911 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9912 else if (code
== ROTATE
|| code
== ROTATERT
)
9913 count
%= GET_MODE_PRECISION (shift_mode
);
9916 /* We can't simply return zero because there may be an
9924 /* If we discovered we had to complement VAROP, leave. Making a NOT
9925 here would cause an infinite loop. */
9929 /* An arithmetic right shift of a quantity known to be -1 or 0
9931 if (code
== ASHIFTRT
9932 && (num_sign_bit_copies (varop
, shift_mode
)
9933 == GET_MODE_PRECISION (shift_mode
)))
9939 /* If we are doing an arithmetic right shift and discarding all but
9940 the sign bit copies, this is equivalent to doing a shift by the
9941 bitsize minus one. Convert it into that shift because it will often
9942 allow other simplifications. */
9944 if (code
== ASHIFTRT
9945 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9946 >= GET_MODE_PRECISION (shift_mode
)))
9947 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9949 /* We simplify the tests below and elsewhere by converting
9950 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9951 `make_compound_operation' will convert it to an ASHIFTRT for
9952 those machines (such as VAX) that don't have an LSHIFTRT. */
9953 if (code
== ASHIFTRT
9954 && val_signbit_known_clear_p (shift_mode
,
9955 nonzero_bits (varop
, shift_mode
)))
9958 if (((code
== LSHIFTRT
9959 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9960 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9962 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9963 && !((nonzero_bits (varop
, shift_mode
) << count
)
9964 & GET_MODE_MASK (shift_mode
))))
9965 && !side_effects_p (varop
))
9968 switch (GET_CODE (varop
))
9974 new_rtx
= expand_compound_operation (varop
);
9975 if (new_rtx
!= varop
)
9983 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9984 minus the width of a smaller mode, we can do this with a
9985 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9986 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9987 && ! mode_dependent_address_p (XEXP (varop
, 0),
9988 MEM_ADDR_SPACE (varop
))
9989 && ! MEM_VOLATILE_P (varop
)
9990 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9991 MODE_INT
, 1)) != BLKmode
)
9993 new_rtx
= adjust_address_nv (varop
, tmode
,
9994 BYTES_BIG_ENDIAN
? 0
9995 : count
/ BITS_PER_UNIT
);
9997 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9998 : ZERO_EXTEND
, mode
, new_rtx
);
10005 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10006 the same number of words as what we've seen so far. Then store
10007 the widest mode in MODE. */
10008 if (subreg_lowpart_p (varop
)
10009 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10010 > GET_MODE_SIZE (GET_MODE (varop
)))
10011 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10012 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10014 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10015 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10017 varop
= SUBREG_REG (varop
);
10018 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10019 mode
= GET_MODE (varop
);
10025 /* Some machines use MULT instead of ASHIFT because MULT
10026 is cheaper. But it is still better on those machines to
10027 merge two shifts into one. */
10028 if (CONST_INT_P (XEXP (varop
, 1))
10029 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10032 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10034 GEN_INT (exact_log2 (
10035 UINTVAL (XEXP (varop
, 1)))));
10041 /* Similar, for when divides are cheaper. */
10042 if (CONST_INT_P (XEXP (varop
, 1))
10043 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10046 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10048 GEN_INT (exact_log2 (
10049 UINTVAL (XEXP (varop
, 1)))));
10055 /* If we are extracting just the sign bit of an arithmetic
10056 right shift, that shift is not needed. However, the sign
10057 bit of a wider mode may be different from what would be
10058 interpreted as the sign bit in a narrower mode, so, if
10059 the result is narrower, don't discard the shift. */
10060 if (code
== LSHIFTRT
10061 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10062 && (GET_MODE_BITSIZE (result_mode
)
10063 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10065 varop
= XEXP (varop
, 0);
10069 /* ... fall through ... */
10074 /* Here we have two nested shifts. The result is usually the
10075 AND of a new shift with a mask. We compute the result below. */
10076 if (CONST_INT_P (XEXP (varop
, 1))
10077 && INTVAL (XEXP (varop
, 1)) >= 0
10078 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10079 && HWI_COMPUTABLE_MODE_P (result_mode
)
10080 && HWI_COMPUTABLE_MODE_P (mode
)
10081 && !VECTOR_MODE_P (result_mode
))
10083 enum rtx_code first_code
= GET_CODE (varop
);
10084 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10085 unsigned HOST_WIDE_INT mask
;
10088 /* We have one common special case. We can't do any merging if
10089 the inner code is an ASHIFTRT of a smaller mode. However, if
10090 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10091 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10092 we can convert it to
10093 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10094 This simplifies certain SIGN_EXTEND operations. */
10095 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10096 && count
== (GET_MODE_PRECISION (result_mode
)
10097 - GET_MODE_PRECISION (GET_MODE (varop
))))
10099 /* C3 has the low-order C1 bits zero. */
10101 mask
= GET_MODE_MASK (mode
)
10102 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10104 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10105 XEXP (varop
, 0), mask
);
10106 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10108 count
= first_count
;
10113 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10114 than C1 high-order bits equal to the sign bit, we can convert
10115 this to either an ASHIFT or an ASHIFTRT depending on the
10118 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10120 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10121 && GET_MODE (varop
) == shift_mode
10122 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10125 varop
= XEXP (varop
, 0);
10126 count
-= first_count
;
10136 /* There are some cases we can't do. If CODE is ASHIFTRT,
10137 we can only do this if FIRST_CODE is also ASHIFTRT.
10139 We can't do the case when CODE is ROTATE and FIRST_CODE is
10142 If the mode of this shift is not the mode of the outer shift,
10143 we can't do this if either shift is a right shift or ROTATE.
10145 Finally, we can't do any of these if the mode is too wide
10146 unless the codes are the same.
10148 Handle the case where the shift codes are the same
10151 if (code
== first_code
)
10153 if (GET_MODE (varop
) != result_mode
10154 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10155 || code
== ROTATE
))
10158 count
+= first_count
;
10159 varop
= XEXP (varop
, 0);
10163 if (code
== ASHIFTRT
10164 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10165 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10166 || (GET_MODE (varop
) != result_mode
10167 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10168 || first_code
== ROTATE
10169 || code
== ROTATE
)))
10172 /* To compute the mask to apply after the shift, shift the
10173 nonzero bits of the inner shift the same way the
10174 outer shift will. */
10176 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10180 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10183 /* Give up if we can't compute an outer operation to use. */
10185 || !CONST_INT_P (mask_rtx
)
10186 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10188 result_mode
, &complement_p
))
10191 /* If the shifts are in the same direction, we add the
10192 counts. Otherwise, we subtract them. */
10193 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10194 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10195 count
+= first_count
;
10197 count
-= first_count
;
10199 /* If COUNT is positive, the new shift is usually CODE,
10200 except for the two exceptions below, in which case it is
10201 FIRST_CODE. If the count is negative, FIRST_CODE should
10204 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10205 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10207 else if (count
< 0)
10208 code
= first_code
, count
= -count
;
10210 varop
= XEXP (varop
, 0);
10214 /* If we have (A << B << C) for any shift, we can convert this to
10215 (A << C << B). This wins if A is a constant. Only try this if
10216 B is not a constant. */
10218 else if (GET_CODE (varop
) == code
10219 && CONST_INT_P (XEXP (varop
, 0))
10220 && !CONST_INT_P (XEXP (varop
, 1)))
10222 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10225 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10232 if (VECTOR_MODE_P (mode
))
10235 /* Make this fit the case below. */
10236 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10242 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10243 with C the size of VAROP - 1 and the shift is logical if
10244 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10245 we have an (le X 0) operation. If we have an arithmetic shift
10246 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10247 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10249 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10250 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10251 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10252 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10253 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10254 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10257 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10260 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10261 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10266 /* If we have (shift (logical)), move the logical to the outside
10267 to allow it to possibly combine with another logical and the
10268 shift to combine with another shift. This also canonicalizes to
10269 what a ZERO_EXTRACT looks like. Also, some machines have
10270 (and (shift)) insns. */
10272 if (CONST_INT_P (XEXP (varop
, 1))
10273 /* We can't do this if we have (ashiftrt (xor)) and the
10274 constant has its sign bit set in shift_mode with shift_mode
10275 wider than result_mode. */
10276 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10277 && result_mode
!= shift_mode
10278 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10280 && (new_rtx
= simplify_const_binary_operation
10281 (code
, result_mode
,
10282 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10283 GEN_INT (count
))) != 0
10284 && CONST_INT_P (new_rtx
)
10285 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10286 INTVAL (new_rtx
), result_mode
, &complement_p
))
10288 varop
= XEXP (varop
, 0);
10292 /* If we can't do that, try to simplify the shift in each arm of the
10293 logical expression, make a new logical expression, and apply
10294 the inverse distributive law. This also can't be done for
10295 (ashiftrt (xor)) where we've widened the shift and the constant
10296 changes the sign bit. */
10297 if (CONST_INT_P (XEXP (varop
, 1))
10298 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10299 && result_mode
!= shift_mode
10300 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10303 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10304 XEXP (varop
, 0), count
);
10305 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10306 XEXP (varop
, 1), count
);
10308 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10310 varop
= apply_distributive_law (varop
);
10318 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10319 says that the sign bit can be tested, FOO has mode MODE, C is
10320 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10321 that may be nonzero. */
10322 if (code
== LSHIFTRT
10323 && XEXP (varop
, 1) == const0_rtx
10324 && GET_MODE (XEXP (varop
, 0)) == result_mode
10325 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10326 && HWI_COMPUTABLE_MODE_P (result_mode
)
10327 && STORE_FLAG_VALUE
== -1
10328 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10329 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10332 varop
= XEXP (varop
, 0);
10339 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10340 than the number of bits in the mode is equivalent to A. */
10341 if (code
== LSHIFTRT
10342 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10343 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10345 varop
= XEXP (varop
, 0);
10350 /* NEG commutes with ASHIFT since it is multiplication. Move the
10351 NEG outside to allow shifts to combine. */
10353 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10356 varop
= XEXP (varop
, 0);
10362 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10363 is one less than the number of bits in the mode is
10364 equivalent to (xor A 1). */
10365 if (code
== LSHIFTRT
10366 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10367 && XEXP (varop
, 1) == constm1_rtx
10368 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10369 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10373 varop
= XEXP (varop
, 0);
10377 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10378 that might be nonzero in BAR are those being shifted out and those
10379 bits are known zero in FOO, we can replace the PLUS with FOO.
10380 Similarly in the other operand order. This code occurs when
10381 we are computing the size of a variable-size array. */
10383 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10384 && count
< HOST_BITS_PER_WIDE_INT
10385 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10386 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10387 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10389 varop
= XEXP (varop
, 0);
10392 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10393 && count
< HOST_BITS_PER_WIDE_INT
10394 && HWI_COMPUTABLE_MODE_P (result_mode
)
10395 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10397 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10398 & nonzero_bits (XEXP (varop
, 1),
10401 varop
= XEXP (varop
, 1);
10405 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10407 && CONST_INT_P (XEXP (varop
, 1))
10408 && (new_rtx
= simplify_const_binary_operation
10409 (ASHIFT
, result_mode
,
10410 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10411 GEN_INT (count
))) != 0
10412 && CONST_INT_P (new_rtx
)
10413 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10414 INTVAL (new_rtx
), result_mode
, &complement_p
))
10416 varop
= XEXP (varop
, 0);
10420 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10421 signbit', and attempt to change the PLUS to an XOR and move it to
10422 the outer operation as is done above in the AND/IOR/XOR case
10423 leg for shift(logical). See details in logical handling above
10424 for reasoning in doing so. */
10425 if (code
== LSHIFTRT
10426 && CONST_INT_P (XEXP (varop
, 1))
10427 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10428 && (new_rtx
= simplify_const_binary_operation
10429 (code
, result_mode
,
10430 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10431 GEN_INT (count
))) != 0
10432 && CONST_INT_P (new_rtx
)
10433 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10434 INTVAL (new_rtx
), result_mode
, &complement_p
))
10436 varop
= XEXP (varop
, 0);
10443 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10444 with C the size of VAROP - 1 and the shift is logical if
10445 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10446 we have a (gt X 0) operation. If the shift is arithmetic with
10447 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10448 we have a (neg (gt X 0)) operation. */
10450 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10451 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10452 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10453 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10454 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10455 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10456 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10459 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10462 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10463 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10470 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10471 if the truncate does not affect the value. */
10472 if (code
== LSHIFTRT
10473 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10474 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10475 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10476 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10477 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10479 rtx varop_inner
= XEXP (varop
, 0);
10482 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10483 XEXP (varop_inner
, 0),
10485 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10486 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10499 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10500 outer_op
, outer_const
);
10502 /* We have now finished analyzing the shift. The result should be
10503 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10504 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10505 to the result of the shift. OUTER_CONST is the relevant constant,
10506 but we must turn off all bits turned off in the shift. */
10508 if (outer_op
== UNKNOWN
10509 && orig_code
== code
&& orig_count
== count
10510 && varop
== orig_varop
10511 && shift_mode
== GET_MODE (varop
))
10514 /* Make a SUBREG if necessary. If we can't make it, fail. */
10515 varop
= gen_lowpart (shift_mode
, varop
);
10516 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10519 /* If we have an outer operation and we just made a shift, it is
10520 possible that we could have simplified the shift were it not
10521 for the outer operation. So try to do the simplification
10524 if (outer_op
!= UNKNOWN
)
10525 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10530 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10532 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10533 turn off all the bits that the shift would have turned off. */
10534 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10535 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10536 GET_MODE_MASK (result_mode
) >> orig_count
);
10538 /* Do the remainder of the processing in RESULT_MODE. */
10539 x
= gen_lowpart_or_truncate (result_mode
, x
);
10541 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10544 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10546 if (outer_op
!= UNKNOWN
)
10548 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10549 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10550 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10552 if (outer_op
== AND
)
10553 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10554 else if (outer_op
== SET
)
10556 /* This means that we have determined that the result is
10557 equivalent to a constant. This should be rare. */
10558 if (!side_effects_p (x
))
10559 x
= GEN_INT (outer_const
);
10561 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10562 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10564 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10565 GEN_INT (outer_const
));
10571 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10572 The result of the shift is RESULT_MODE. If we cannot simplify it,
10573 return X or, if it is NULL, synthesize the expression with
10574 simplify_gen_binary. Otherwise, return a simplified value.
10576 The shift is normally computed in the widest mode we find in VAROP, as
10577 long as it isn't a different number of words than RESULT_MODE. Exceptions
10578 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10581 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
10582 rtx varop
, int count
)
10584 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10589 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10590 if (GET_MODE (x
) != result_mode
)
10591 x
= gen_lowpart (result_mode
, x
);
10596 /* Like recog, but we receive the address of a pointer to a new pattern.
10597 We try to match the rtx that the pointer points to.
10598 If that fails, we may try to modify or replace the pattern,
10599 storing the replacement into the same pointer object.
10601 Modifications include deletion or addition of CLOBBERs.
10603 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10604 the CLOBBERs are placed.
10606 The value is the final insn code from the pattern ultimately matched,
10610 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10612 rtx pat
= *pnewpat
;
10613 rtx pat_without_clobbers
;
10614 int insn_code_number
;
10615 int num_clobbers_to_add
= 0;
10617 rtx notes
= NULL_RTX
;
10618 rtx old_notes
, old_pat
;
10621 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10622 we use to indicate that something didn't match. If we find such a
10623 thing, force rejection. */
10624 if (GET_CODE (pat
) == PARALLEL
)
10625 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10626 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10627 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10630 old_pat
= PATTERN (insn
);
10631 old_notes
= REG_NOTES (insn
);
10632 PATTERN (insn
) = pat
;
10633 REG_NOTES (insn
) = NULL_RTX
;
10635 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10636 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10638 if (insn_code_number
< 0)
10639 fputs ("Failed to match this instruction:\n", dump_file
);
10641 fputs ("Successfully matched this instruction:\n", dump_file
);
10642 print_rtl_single (dump_file
, pat
);
10645 /* If it isn't, there is the possibility that we previously had an insn
10646 that clobbered some register as a side effect, but the combined
10647 insn doesn't need to do that. So try once more without the clobbers
10648 unless this represents an ASM insn. */
10650 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10651 && GET_CODE (pat
) == PARALLEL
)
10655 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10656 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10659 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10663 SUBST_INT (XVECLEN (pat
, 0), pos
);
10666 pat
= XVECEXP (pat
, 0, 0);
10668 PATTERN (insn
) = pat
;
10669 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10670 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10672 if (insn_code_number
< 0)
10673 fputs ("Failed to match this instruction:\n", dump_file
);
10675 fputs ("Successfully matched this instruction:\n", dump_file
);
10676 print_rtl_single (dump_file
, pat
);
10680 pat_without_clobbers
= pat
;
10682 PATTERN (insn
) = old_pat
;
10683 REG_NOTES (insn
) = old_notes
;
10685 /* Recognize all noop sets, these will be killed by followup pass. */
10686 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10687 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10689 /* If we had any clobbers to add, make a new pattern than contains
10690 them. Then check to make sure that all of them are dead. */
10691 if (num_clobbers_to_add
)
10693 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10694 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10695 ? (XVECLEN (pat
, 0)
10696 + num_clobbers_to_add
)
10697 : num_clobbers_to_add
+ 1));
10699 if (GET_CODE (pat
) == PARALLEL
)
10700 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10701 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10703 XVECEXP (newpat
, 0, 0) = pat
;
10705 add_clobbers (newpat
, insn_code_number
);
10707 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10708 i
< XVECLEN (newpat
, 0); i
++)
10710 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10711 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10713 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10715 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10716 notes
= alloc_reg_note (REG_UNUSED
,
10717 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10723 if (insn_code_number
>= 0
10724 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10726 old_pat
= PATTERN (insn
);
10727 old_notes
= REG_NOTES (insn
);
10728 old_icode
= INSN_CODE (insn
);
10729 PATTERN (insn
) = pat
;
10730 REG_NOTES (insn
) = notes
;
10732 /* Allow targets to reject combined insn. */
10733 if (!targetm
.legitimate_combined_insn (insn
))
10735 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10736 fputs ("Instruction not appropriate for target.",
10739 /* Callers expect recog_for_combine to strip
10740 clobbers from the pattern on failure. */
10741 pat
= pat_without_clobbers
;
10744 insn_code_number
= -1;
10747 PATTERN (insn
) = old_pat
;
10748 REG_NOTES (insn
) = old_notes
;
10749 INSN_CODE (insn
) = old_icode
;
10755 return insn_code_number
;
10758 /* Like gen_lowpart_general but for use by combine. In combine it
10759 is not possible to create any new pseudoregs. However, it is
10760 safe to create invalid memory addresses, because combine will
10761 try to recognize them and all they will do is make the combine
10764 If for some reason this cannot do its job, an rtx
10765 (clobber (const_int 0)) is returned.
10766 An insn containing that will not be recognized. */
10769 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
10771 machine_mode imode
= GET_MODE (x
);
10772 unsigned int osize
= GET_MODE_SIZE (omode
);
10773 unsigned int isize
= GET_MODE_SIZE (imode
);
10776 if (omode
== imode
)
10779 /* We can only support MODE being wider than a word if X is a
10780 constant integer or has a mode the same size. */
10781 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10782 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
10785 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10786 won't know what to do. So we will strip off the SUBREG here and
10787 process normally. */
10788 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10790 x
= SUBREG_REG (x
);
10792 /* For use in case we fall down into the address adjustments
10793 further below, we need to adjust the known mode and size of
10794 x; imode and isize, since we just adjusted x. */
10795 imode
= GET_MODE (x
);
10797 if (imode
== omode
)
10800 isize
= GET_MODE_SIZE (imode
);
10803 result
= gen_lowpart_common (omode
, x
);
10812 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10814 if (MEM_VOLATILE_P (x
)
10815 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10818 /* If we want to refer to something bigger than the original memref,
10819 generate a paradoxical subreg instead. That will force a reload
10820 of the original memref X. */
10822 return gen_rtx_SUBREG (omode
, x
, 0);
10824 if (WORDS_BIG_ENDIAN
)
10825 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10827 /* Adjust the address so that the address-after-the-data is
10829 if (BYTES_BIG_ENDIAN
)
10830 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10832 return adjust_address_nv (x
, omode
, offset
);
10835 /* If X is a comparison operator, rewrite it in a new mode. This
10836 probably won't match, but may allow further simplifications. */
10837 else if (COMPARISON_P (x
))
10838 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10840 /* If we couldn't simplify X any other way, just enclose it in a
10841 SUBREG. Normally, this SUBREG won't match, but some patterns may
10842 include an explicit SUBREG or we may simplify it further in combine. */
10848 offset
= subreg_lowpart_offset (omode
, imode
);
10849 if (imode
== VOIDmode
)
10851 imode
= int_mode_for_mode (omode
);
10852 x
= gen_lowpart_common (imode
, x
);
10856 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10862 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10865 /* Try to simplify a comparison between OP0 and a constant OP1,
10866 where CODE is the comparison code that will be tested, into a
10867 (CODE OP0 const0_rtx) form.
10869 The result is a possibly different comparison code to use.
10870 *POP1 may be updated. */
10872 static enum rtx_code
10873 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
10874 rtx op0
, rtx
*pop1
)
10876 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10877 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10879 /* Get the constant we are comparing against and turn off all bits
10880 not on in our mode. */
10881 if (mode
!= VOIDmode
)
10882 const_op
= trunc_int_for_mode (const_op
, mode
);
10884 /* If we are comparing against a constant power of two and the value
10885 being compared can only have that single bit nonzero (e.g., it was
10886 `and'ed with that bit), we can replace this with a comparison
10889 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10890 || code
== LT
|| code
== LTU
)
10891 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10892 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
10893 && (nonzero_bits (op0
, mode
)
10894 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
10896 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10900 /* Similarly, if we are comparing a value known to be either -1 or
10901 0 with -1, change it to the opposite comparison against zero. */
10903 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10904 || code
== GEU
|| code
== LTU
)
10905 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10907 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10911 /* Do some canonicalizations based on the comparison code. We prefer
10912 comparisons against zero and then prefer equality comparisons.
10913 If we can reduce the size of a constant, we will do that too. */
10917 /* < C is equivalent to <= (C - 1) */
10922 /* ... fall through to LE case below. */
10928 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10935 /* If we are doing a <= 0 comparison on a value known to have
10936 a zero sign bit, we can replace this with == 0. */
10937 else if (const_op
== 0
10938 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10939 && (nonzero_bits (op0
, mode
)
10940 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10946 /* >= C is equivalent to > (C - 1). */
10951 /* ... fall through to GT below. */
10957 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10964 /* If we are doing a > 0 comparison on a value known to have
10965 a zero sign bit, we can replace this with != 0. */
10966 else if (const_op
== 0
10967 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10968 && (nonzero_bits (op0
, mode
)
10969 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10975 /* < C is equivalent to <= (C - 1). */
10980 /* ... fall through ... */
10982 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10983 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10984 && (unsigned HOST_WIDE_INT
) const_op
10985 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10995 /* unsigned <= 0 is equivalent to == 0 */
10998 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10999 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11000 && (unsigned HOST_WIDE_INT
) const_op
11001 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11009 /* >= C is equivalent to > (C - 1). */
11014 /* ... fall through ... */
11017 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11018 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11019 && (unsigned HOST_WIDE_INT
) const_op
11020 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11030 /* unsigned > 0 is equivalent to != 0 */
11033 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11034 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11035 && (unsigned HOST_WIDE_INT
) const_op
11036 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11047 *pop1
= GEN_INT (const_op
);
11051 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11052 comparison code that will be tested.
11054 The result is a possibly different comparison code to use. *POP0 and
11055 *POP1 may be updated.
11057 It is possible that we might detect that a comparison is either always
11058 true or always false. However, we do not perform general constant
11059 folding in combine, so this knowledge isn't useful. Such tautologies
11060 should have been detected earlier. Hence we ignore all such cases. */
11062 static enum rtx_code
11063 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11069 machine_mode mode
, tmode
;
11071 /* Try a few ways of applying the same transformation to both operands. */
11074 #ifndef WORD_REGISTER_OPERATIONS
11075 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11076 so check specially. */
11077 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11078 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11079 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11080 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11081 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11082 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11083 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11084 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11085 && CONST_INT_P (XEXP (op0
, 1))
11086 && XEXP (op0
, 1) == XEXP (op1
, 1)
11087 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11088 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11089 && (INTVAL (XEXP (op0
, 1))
11090 == (GET_MODE_PRECISION (GET_MODE (op0
))
11091 - (GET_MODE_PRECISION
11092 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11094 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11095 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11099 /* If both operands are the same constant shift, see if we can ignore the
11100 shift. We can if the shift is a rotate or if the bits shifted out of
11101 this shift are known to be zero for both inputs and if the type of
11102 comparison is compatible with the shift. */
11103 if (GET_CODE (op0
) == GET_CODE (op1
)
11104 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11105 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11106 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11107 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11108 || (GET_CODE (op0
) == ASHIFTRT
11109 && (code
!= GTU
&& code
!= LTU
11110 && code
!= GEU
&& code
!= LEU
)))
11111 && CONST_INT_P (XEXP (op0
, 1))
11112 && INTVAL (XEXP (op0
, 1)) >= 0
11113 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11114 && XEXP (op0
, 1) == XEXP (op1
, 1))
11116 machine_mode mode
= GET_MODE (op0
);
11117 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11118 int shift_count
= INTVAL (XEXP (op0
, 1));
11120 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11121 mask
&= (mask
>> shift_count
) << shift_count
;
11122 else if (GET_CODE (op0
) == ASHIFT
)
11123 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11125 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11126 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11127 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11132 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11133 SUBREGs are of the same mode, and, in both cases, the AND would
11134 be redundant if the comparison was done in the narrower mode,
11135 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11136 and the operand's possibly nonzero bits are 0xffffff01; in that case
11137 if we only care about QImode, we don't need the AND). This case
11138 occurs if the output mode of an scc insn is not SImode and
11139 STORE_FLAG_VALUE == 1 (e.g., the 386).
11141 Similarly, check for a case where the AND's are ZERO_EXTEND
11142 operations from some narrower mode even though a SUBREG is not
11145 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11146 && CONST_INT_P (XEXP (op0
, 1))
11147 && CONST_INT_P (XEXP (op1
, 1)))
11149 rtx inner_op0
= XEXP (op0
, 0);
11150 rtx inner_op1
= XEXP (op1
, 0);
11151 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11152 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11155 if (paradoxical_subreg_p (inner_op0
)
11156 && GET_CODE (inner_op1
) == SUBREG
11157 && (GET_MODE (SUBREG_REG (inner_op0
))
11158 == GET_MODE (SUBREG_REG (inner_op1
)))
11159 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11160 <= HOST_BITS_PER_WIDE_INT
)
11161 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11162 GET_MODE (SUBREG_REG (inner_op0
)))))
11163 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11164 GET_MODE (SUBREG_REG (inner_op1
))))))
11166 op0
= SUBREG_REG (inner_op0
);
11167 op1
= SUBREG_REG (inner_op1
);
11169 /* The resulting comparison is always unsigned since we masked
11170 off the original sign bit. */
11171 code
= unsigned_condition (code
);
11177 for (tmode
= GET_CLASS_NARROWEST_MODE
11178 (GET_MODE_CLASS (GET_MODE (op0
)));
11179 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11180 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11182 op0
= gen_lowpart (tmode
, inner_op0
);
11183 op1
= gen_lowpart (tmode
, inner_op1
);
11184 code
= unsigned_condition (code
);
11193 /* If both operands are NOT, we can strip off the outer operation
11194 and adjust the comparison code for swapped operands; similarly for
11195 NEG, except that this must be an equality comparison. */
11196 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11197 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11198 && (code
== EQ
|| code
== NE
)))
11199 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11205 /* If the first operand is a constant, swap the operands and adjust the
11206 comparison code appropriately, but don't do this if the second operand
11207 is already a constant integer. */
11208 if (swap_commutative_operands_p (op0
, op1
))
11210 tem
= op0
, op0
= op1
, op1
= tem
;
11211 code
= swap_condition (code
);
11214 /* We now enter a loop during which we will try to simplify the comparison.
11215 For the most part, we only are concerned with comparisons with zero,
11216 but some things may really be comparisons with zero but not start
11217 out looking that way. */
11219 while (CONST_INT_P (op1
))
11221 machine_mode mode
= GET_MODE (op0
);
11222 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11223 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11224 int equality_comparison_p
;
11225 int sign_bit_comparison_p
;
11226 int unsigned_comparison_p
;
11227 HOST_WIDE_INT const_op
;
11229 /* We only want to handle integral modes. This catches VOIDmode,
11230 CCmode, and the floating-point modes. An exception is that we
11231 can handle VOIDmode if OP0 is a COMPARE or a comparison
11234 if (GET_MODE_CLASS (mode
) != MODE_INT
11235 && ! (mode
== VOIDmode
11236 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11239 /* Try to simplify the compare to constant, possibly changing the
11240 comparison op, and/or changing op1 to zero. */
11241 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11242 const_op
= INTVAL (op1
);
11244 /* Compute some predicates to simplify code below. */
11246 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11247 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11248 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11251 /* If this is a sign bit comparison and we can do arithmetic in
11252 MODE, say that we will only be needing the sign bit of OP0. */
11253 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11254 op0
= force_to_mode (op0
, mode
,
11255 (unsigned HOST_WIDE_INT
) 1
11256 << (GET_MODE_PRECISION (mode
) - 1),
11259 /* Now try cases based on the opcode of OP0. If none of the cases
11260 does a "continue", we exit this loop immediately after the
11263 switch (GET_CODE (op0
))
11266 /* If we are extracting a single bit from a variable position in
11267 a constant that has only a single bit set and are comparing it
11268 with zero, we can convert this into an equality comparison
11269 between the position and the location of the single bit. */
11270 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11271 have already reduced the shift count modulo the word size. */
11272 if (!SHIFT_COUNT_TRUNCATED
11273 && CONST_INT_P (XEXP (op0
, 0))
11274 && XEXP (op0
, 1) == const1_rtx
11275 && equality_comparison_p
&& const_op
== 0
11276 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11278 if (BITS_BIG_ENDIAN
)
11279 i
= BITS_PER_WORD
- 1 - i
;
11281 op0
= XEXP (op0
, 2);
11285 /* Result is nonzero iff shift count is equal to I. */
11286 code
= reverse_condition (code
);
11290 /* ... fall through ... */
11293 tem
= expand_compound_operation (op0
);
11302 /* If testing for equality, we can take the NOT of the constant. */
11303 if (equality_comparison_p
11304 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11306 op0
= XEXP (op0
, 0);
11311 /* If just looking at the sign bit, reverse the sense of the
11313 if (sign_bit_comparison_p
)
11315 op0
= XEXP (op0
, 0);
11316 code
= (code
== GE
? LT
: GE
);
11322 /* If testing for equality, we can take the NEG of the constant. */
11323 if (equality_comparison_p
11324 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11326 op0
= XEXP (op0
, 0);
11331 /* The remaining cases only apply to comparisons with zero. */
11335 /* When X is ABS or is known positive,
11336 (neg X) is < 0 if and only if X != 0. */
11338 if (sign_bit_comparison_p
11339 && (GET_CODE (XEXP (op0
, 0)) == ABS
11340 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11341 && (nonzero_bits (XEXP (op0
, 0), mode
)
11342 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11345 op0
= XEXP (op0
, 0);
11346 code
= (code
== LT
? NE
: EQ
);
11350 /* If we have NEG of something whose two high-order bits are the
11351 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11352 if (num_sign_bit_copies (op0
, mode
) >= 2)
11354 op0
= XEXP (op0
, 0);
11355 code
= swap_condition (code
);
11361 /* If we are testing equality and our count is a constant, we
11362 can perform the inverse operation on our RHS. */
11363 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11364 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11365 op1
, XEXP (op0
, 1))) != 0)
11367 op0
= XEXP (op0
, 0);
11372 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11373 a particular bit. Convert it to an AND of a constant of that
11374 bit. This will be converted into a ZERO_EXTRACT. */
11375 if (const_op
== 0 && sign_bit_comparison_p
11376 && CONST_INT_P (XEXP (op0
, 1))
11377 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11379 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11380 ((unsigned HOST_WIDE_INT
) 1
11382 - INTVAL (XEXP (op0
, 1)))));
11383 code
= (code
== LT
? NE
: EQ
);
11387 /* Fall through. */
11390 /* ABS is ignorable inside an equality comparison with zero. */
11391 if (const_op
== 0 && equality_comparison_p
)
11393 op0
= XEXP (op0
, 0);
11399 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11400 (compare FOO CONST) if CONST fits in FOO's mode and we
11401 are either testing inequality or have an unsigned
11402 comparison with ZERO_EXTEND or a signed comparison with
11403 SIGN_EXTEND. But don't do it if we don't have a compare
11404 insn of the given mode, since we'd have to revert it
11405 later on, and then we wouldn't know whether to sign- or
11407 mode
= GET_MODE (XEXP (op0
, 0));
11408 if (GET_MODE_CLASS (mode
) == MODE_INT
11409 && ! unsigned_comparison_p
11410 && HWI_COMPUTABLE_MODE_P (mode
)
11411 && trunc_int_for_mode (const_op
, mode
) == const_op
11412 && have_insn_for (COMPARE
, mode
))
11414 op0
= XEXP (op0
, 0);
11420 /* Check for the case where we are comparing A - C1 with C2, that is
11422 (subreg:MODE (plus (A) (-C1))) op (C2)
11424 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11425 comparison in the wider mode. One of the following two conditions
11426 must be true in order for this to be valid:
11428 1. The mode extension results in the same bit pattern being added
11429 on both sides and the comparison is equality or unsigned. As
11430 C2 has been truncated to fit in MODE, the pattern can only be
11433 2. The mode extension results in the sign bit being copied on
11436 The difficulty here is that we have predicates for A but not for
11437 (A - C1) so we need to check that C1 is within proper bounds so
11438 as to perturbate A as little as possible. */
11440 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11441 && subreg_lowpart_p (op0
)
11442 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11443 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11444 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11446 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11447 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11448 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11451 && (unsigned HOST_WIDE_INT
) c1
11452 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11453 && (equality_comparison_p
|| unsigned_comparison_p
)
11454 /* (A - C1) zero-extends if it is positive and sign-extends
11455 if it is negative, C2 both zero- and sign-extends. */
11456 && ((0 == (nonzero_bits (a
, inner_mode
)
11457 & ~GET_MODE_MASK (mode
))
11459 /* (A - C1) sign-extends if it is positive and 1-extends
11460 if it is negative, C2 both sign- and 1-extends. */
11461 || (num_sign_bit_copies (a
, inner_mode
)
11462 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11465 || ((unsigned HOST_WIDE_INT
) c1
11466 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11467 /* (A - C1) always sign-extends, like C2. */
11468 && num_sign_bit_copies (a
, inner_mode
)
11469 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11470 - (mode_width
- 1))))
11472 op0
= SUBREG_REG (op0
);
11477 /* If the inner mode is narrower and we are extracting the low part,
11478 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11479 if (subreg_lowpart_p (op0
)
11480 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11481 /* Fall through */ ;
11485 /* ... fall through ... */
11488 mode
= GET_MODE (XEXP (op0
, 0));
11489 if (GET_MODE_CLASS (mode
) == MODE_INT
11490 && (unsigned_comparison_p
|| equality_comparison_p
)
11491 && HWI_COMPUTABLE_MODE_P (mode
)
11492 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11494 && have_insn_for (COMPARE
, mode
))
11496 op0
= XEXP (op0
, 0);
11502 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11503 this for equality comparisons due to pathological cases involving
11505 if (equality_comparison_p
11506 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11507 op1
, XEXP (op0
, 1))))
11509 op0
= XEXP (op0
, 0);
11514 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11515 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11516 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11518 op0
= XEXP (XEXP (op0
, 0), 0);
11519 code
= (code
== LT
? EQ
: NE
);
11525 /* We used to optimize signed comparisons against zero, but that
11526 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11527 arrive here as equality comparisons, or (GEU, LTU) are
11528 optimized away. No need to special-case them. */
11530 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11531 (eq B (minus A C)), whichever simplifies. We can only do
11532 this for equality comparisons due to pathological cases involving
11534 if (equality_comparison_p
11535 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11536 XEXP (op0
, 1), op1
)))
11538 op0
= XEXP (op0
, 0);
11543 if (equality_comparison_p
11544 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11545 XEXP (op0
, 0), op1
)))
11547 op0
= XEXP (op0
, 1);
11552 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11553 of bits in X minus 1, is one iff X > 0. */
11554 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11555 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11556 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11557 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11559 op0
= XEXP (op0
, 1);
11560 code
= (code
== GE
? LE
: GT
);
11566 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11567 if C is zero or B is a constant. */
11568 if (equality_comparison_p
11569 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11570 XEXP (op0
, 1), op1
)))
11572 op0
= XEXP (op0
, 0);
11579 case UNEQ
: case LTGT
:
11580 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11581 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11582 case UNORDERED
: case ORDERED
:
11583 /* We can't do anything if OP0 is a condition code value, rather
11584 than an actual data value. */
11586 || CC0_P (XEXP (op0
, 0))
11587 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11590 /* Get the two operands being compared. */
11591 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11592 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11594 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11596 /* Check for the cases where we simply want the result of the
11597 earlier test or the opposite of that result. */
11598 if (code
== NE
|| code
== EQ
11599 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11600 && (code
== LT
|| code
== GE
)))
11602 enum rtx_code new_code
;
11603 if (code
== LT
|| code
== NE
)
11604 new_code
= GET_CODE (op0
);
11606 new_code
= reversed_comparison_code (op0
, NULL
);
11608 if (new_code
!= UNKNOWN
)
11619 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11621 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11622 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11623 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11625 op0
= XEXP (op0
, 1);
11626 code
= (code
== GE
? GT
: LE
);
11632 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11633 will be converted to a ZERO_EXTRACT later. */
11634 if (const_op
== 0 && equality_comparison_p
11635 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11636 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11638 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11639 XEXP (XEXP (op0
, 0), 1));
11640 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11644 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11645 zero and X is a comparison and C1 and C2 describe only bits set
11646 in STORE_FLAG_VALUE, we can compare with X. */
11647 if (const_op
== 0 && equality_comparison_p
11648 && mode_width
<= HOST_BITS_PER_WIDE_INT
11649 && CONST_INT_P (XEXP (op0
, 1))
11650 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11651 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11652 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11653 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11655 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11656 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11657 if ((~STORE_FLAG_VALUE
& mask
) == 0
11658 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11659 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11660 && COMPARISON_P (tem
))))
11662 op0
= XEXP (XEXP (op0
, 0), 0);
11667 /* If we are doing an equality comparison of an AND of a bit equal
11668 to the sign bit, replace this with a LT or GE comparison of
11669 the underlying value. */
11670 if (equality_comparison_p
11672 && CONST_INT_P (XEXP (op0
, 1))
11673 && mode_width
<= HOST_BITS_PER_WIDE_INT
11674 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11675 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11677 op0
= XEXP (op0
, 0);
11678 code
= (code
== EQ
? GE
: LT
);
11682 /* If this AND operation is really a ZERO_EXTEND from a narrower
11683 mode, the constant fits within that mode, and this is either an
11684 equality or unsigned comparison, try to do this comparison in
11689 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11690 -> (ne:DI (reg:SI 4) (const_int 0))
11692 unless TRULY_NOOP_TRUNCATION allows it or the register is
11693 known to hold a value of the required mode the
11694 transformation is invalid. */
11695 if ((equality_comparison_p
|| unsigned_comparison_p
)
11696 && CONST_INT_P (XEXP (op0
, 1))
11697 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11698 & GET_MODE_MASK (mode
))
11700 && const_op
>> i
== 0
11701 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11702 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11703 || (REG_P (XEXP (op0
, 0))
11704 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11706 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11710 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11711 fits in both M1 and M2 and the SUBREG is either paradoxical
11712 or represents the low part, permute the SUBREG and the AND
11714 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11716 unsigned HOST_WIDE_INT c1
;
11717 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11718 /* Require an integral mode, to avoid creating something like
11720 if (SCALAR_INT_MODE_P (tmode
)
11721 /* It is unsafe to commute the AND into the SUBREG if the
11722 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11723 not defined. As originally written the upper bits
11724 have a defined value due to the AND operation.
11725 However, if we commute the AND inside the SUBREG then
11726 they no longer have defined values and the meaning of
11727 the code has been changed. */
11729 #ifdef WORD_REGISTER_OPERATIONS
11730 || (mode_width
> GET_MODE_PRECISION (tmode
)
11731 && mode_width
<= BITS_PER_WORD
)
11733 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11734 && subreg_lowpart_p (XEXP (op0
, 0))))
11735 && CONST_INT_P (XEXP (op0
, 1))
11736 && mode_width
<= HOST_BITS_PER_WIDE_INT
11737 && HWI_COMPUTABLE_MODE_P (tmode
)
11738 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11739 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11741 && c1
!= GET_MODE_MASK (tmode
))
11743 op0
= simplify_gen_binary (AND
, tmode
,
11744 SUBREG_REG (XEXP (op0
, 0)),
11745 gen_int_mode (c1
, tmode
));
11746 op0
= gen_lowpart (mode
, op0
);
11751 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11752 if (const_op
== 0 && equality_comparison_p
11753 && XEXP (op0
, 1) == const1_rtx
11754 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11756 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11757 XEXP (XEXP (op0
, 0), 0), 1);
11758 code
= (code
== NE
? EQ
: NE
);
11762 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11763 (eq (and (lshiftrt X) 1) 0).
11764 Also handle the case where (not X) is expressed using xor. */
11765 if (const_op
== 0 && equality_comparison_p
11766 && XEXP (op0
, 1) == const1_rtx
11767 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11769 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11770 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11772 if (GET_CODE (shift_op
) == NOT
11773 || (GET_CODE (shift_op
) == XOR
11774 && CONST_INT_P (XEXP (shift_op
, 1))
11775 && CONST_INT_P (shift_count
)
11776 && HWI_COMPUTABLE_MODE_P (mode
)
11777 && (UINTVAL (XEXP (shift_op
, 1))
11778 == (unsigned HOST_WIDE_INT
) 1
11779 << INTVAL (shift_count
))))
11782 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11783 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11784 code
= (code
== NE
? EQ
: NE
);
11791 /* If we have (compare (ashift FOO N) (const_int C)) and
11792 the high order N bits of FOO (N+1 if an inequality comparison)
11793 are known to be zero, we can do this by comparing FOO with C
11794 shifted right N bits so long as the low-order N bits of C are
11796 if (CONST_INT_P (XEXP (op0
, 1))
11797 && INTVAL (XEXP (op0
, 1)) >= 0
11798 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11799 < HOST_BITS_PER_WIDE_INT
)
11800 && (((unsigned HOST_WIDE_INT
) const_op
11801 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11803 && mode_width
<= HOST_BITS_PER_WIDE_INT
11804 && (nonzero_bits (XEXP (op0
, 0), mode
)
11805 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11806 + ! equality_comparison_p
))) == 0)
11808 /* We must perform a logical shift, not an arithmetic one,
11809 as we want the top N bits of C to be zero. */
11810 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11812 temp
>>= INTVAL (XEXP (op0
, 1));
11813 op1
= gen_int_mode (temp
, mode
);
11814 op0
= XEXP (op0
, 0);
11818 /* If we are doing a sign bit comparison, it means we are testing
11819 a particular bit. Convert it to the appropriate AND. */
11820 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11821 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11823 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11824 ((unsigned HOST_WIDE_INT
) 1
11826 - INTVAL (XEXP (op0
, 1)))));
11827 code
= (code
== LT
? NE
: EQ
);
11831 /* If this an equality comparison with zero and we are shifting
11832 the low bit to the sign bit, we can convert this to an AND of the
11834 if (const_op
== 0 && equality_comparison_p
11835 && CONST_INT_P (XEXP (op0
, 1))
11836 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11838 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11844 /* If this is an equality comparison with zero, we can do this
11845 as a logical shift, which might be much simpler. */
11846 if (equality_comparison_p
&& const_op
== 0
11847 && CONST_INT_P (XEXP (op0
, 1)))
11849 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11851 INTVAL (XEXP (op0
, 1)));
11855 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11856 do the comparison in a narrower mode. */
11857 if (! unsigned_comparison_p
11858 && CONST_INT_P (XEXP (op0
, 1))
11859 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11860 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11861 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11862 MODE_INT
, 1)) != BLKmode
11863 && (((unsigned HOST_WIDE_INT
) const_op
11864 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11865 <= GET_MODE_MASK (tmode
)))
11867 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11871 /* Likewise if OP0 is a PLUS of a sign extension with a
11872 constant, which is usually represented with the PLUS
11873 between the shifts. */
11874 if (! unsigned_comparison_p
11875 && CONST_INT_P (XEXP (op0
, 1))
11876 && GET_CODE (XEXP (op0
, 0)) == PLUS
11877 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11878 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11879 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11880 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11881 MODE_INT
, 1)) != BLKmode
11882 && (((unsigned HOST_WIDE_INT
) const_op
11883 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11884 <= GET_MODE_MASK (tmode
)))
11886 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11887 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11888 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11889 add_const
, XEXP (op0
, 1));
11891 op0
= simplify_gen_binary (PLUS
, tmode
,
11892 gen_lowpart (tmode
, inner
),
11897 /* ... fall through ... */
11899 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11900 the low order N bits of FOO are known to be zero, we can do this
11901 by comparing FOO with C shifted left N bits so long as no
11902 overflow occurs. Even if the low order N bits of FOO aren't known
11903 to be zero, if the comparison is >= or < we can use the same
11904 optimization and for > or <= by setting all the low
11905 order N bits in the comparison constant. */
11906 if (CONST_INT_P (XEXP (op0
, 1))
11907 && INTVAL (XEXP (op0
, 1)) > 0
11908 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11909 && mode_width
<= HOST_BITS_PER_WIDE_INT
11910 && (((unsigned HOST_WIDE_INT
) const_op
11911 + (GET_CODE (op0
) != LSHIFTRT
11912 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11915 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11917 unsigned HOST_WIDE_INT low_bits
11918 = (nonzero_bits (XEXP (op0
, 0), mode
)
11919 & (((unsigned HOST_WIDE_INT
) 1
11920 << INTVAL (XEXP (op0
, 1))) - 1));
11921 if (low_bits
== 0 || !equality_comparison_p
)
11923 /* If the shift was logical, then we must make the condition
11925 if (GET_CODE (op0
) == LSHIFTRT
)
11926 code
= unsigned_condition (code
);
11928 const_op
<<= INTVAL (XEXP (op0
, 1));
11930 && (code
== GT
|| code
== GTU
11931 || code
== LE
|| code
== LEU
))
11933 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11934 op1
= GEN_INT (const_op
);
11935 op0
= XEXP (op0
, 0);
11940 /* If we are using this shift to extract just the sign bit, we
11941 can replace this with an LT or GE comparison. */
11943 && (equality_comparison_p
|| sign_bit_comparison_p
)
11944 && CONST_INT_P (XEXP (op0
, 1))
11945 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11947 op0
= XEXP (op0
, 0);
11948 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11960 /* Now make any compound operations involved in this comparison. Then,
11961 check for an outmost SUBREG on OP0 that is not doing anything or is
11962 paradoxical. The latter transformation must only be performed when
11963 it is known that the "extra" bits will be the same in op0 and op1 or
11964 that they don't matter. There are three cases to consider:
11966 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11967 care bits and we can assume they have any convenient value. So
11968 making the transformation is safe.
11970 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11971 In this case the upper bits of op0 are undefined. We should not make
11972 the simplification in that case as we do not know the contents of
11975 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11976 UNKNOWN. In that case we know those bits are zeros or ones. We must
11977 also be sure that they are the same as the upper bits of op1.
11979 We can never remove a SUBREG for a non-equality comparison because
11980 the sign bit is in a different place in the underlying object. */
11982 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11983 op1
= make_compound_operation (op1
, SET
);
11985 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11986 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11987 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11988 && (code
== NE
|| code
== EQ
))
11990 if (paradoxical_subreg_p (op0
))
11992 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11994 if (REG_P (SUBREG_REG (op0
)))
11996 op0
= SUBREG_REG (op0
);
11997 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12000 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12001 <= HOST_BITS_PER_WIDE_INT
)
12002 && (nonzero_bits (SUBREG_REG (op0
),
12003 GET_MODE (SUBREG_REG (op0
)))
12004 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12006 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12008 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12009 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12010 op0
= SUBREG_REG (op0
), op1
= tem
;
12014 /* We now do the opposite procedure: Some machines don't have compare
12015 insns in all modes. If OP0's mode is an integer mode smaller than a
12016 word and we can't do a compare in that mode, see if there is a larger
12017 mode for which we can do the compare. There are a number of cases in
12018 which we can use the wider mode. */
12020 mode
= GET_MODE (op0
);
12021 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12022 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12023 && ! have_insn_for (COMPARE
, mode
))
12024 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12025 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12026 tmode
= GET_MODE_WIDER_MODE (tmode
))
12027 if (have_insn_for (COMPARE
, tmode
))
12031 /* If this is a test for negative, we can make an explicit
12032 test of the sign bit. Test this first so we can use
12033 a paradoxical subreg to extend OP0. */
12035 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12036 && HWI_COMPUTABLE_MODE_P (mode
))
12038 unsigned HOST_WIDE_INT sign
12039 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
12040 op0
= simplify_gen_binary (AND
, tmode
,
12041 gen_lowpart (tmode
, op0
),
12042 gen_int_mode (sign
, tmode
));
12043 code
= (code
== LT
) ? NE
: EQ
;
12047 /* If the only nonzero bits in OP0 and OP1 are those in the
12048 narrower mode and this is an equality or unsigned comparison,
12049 we can use the wider mode. Similarly for sign-extended
12050 values, in which case it is true for all comparisons. */
12051 zero_extended
= ((code
== EQ
|| code
== NE
12052 || code
== GEU
|| code
== GTU
12053 || code
== LEU
|| code
== LTU
)
12054 && (nonzero_bits (op0
, tmode
)
12055 & ~GET_MODE_MASK (mode
)) == 0
12056 && ((CONST_INT_P (op1
)
12057 || (nonzero_bits (op1
, tmode
)
12058 & ~GET_MODE_MASK (mode
)) == 0)));
12061 || ((num_sign_bit_copies (op0
, tmode
)
12062 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12063 - GET_MODE_PRECISION (mode
)))
12064 && (num_sign_bit_copies (op1
, tmode
)
12065 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12066 - GET_MODE_PRECISION (mode
)))))
12068 /* If OP0 is an AND and we don't have an AND in MODE either,
12069 make a new AND in the proper mode. */
12070 if (GET_CODE (op0
) == AND
12071 && !have_insn_for (AND
, mode
))
12072 op0
= simplify_gen_binary (AND
, tmode
,
12073 gen_lowpart (tmode
,
12075 gen_lowpart (tmode
,
12081 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12082 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12086 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12087 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12094 /* We may have changed the comparison operands. Re-canonicalize. */
12095 if (swap_commutative_operands_p (op0
, op1
))
12097 tem
= op0
, op0
= op1
, op1
= tem
;
12098 code
= swap_condition (code
);
12101 /* If this machine only supports a subset of valid comparisons, see if we
12102 can convert an unsupported one into a supported one. */
12103 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12111 /* Utility function for record_value_for_reg. Count number of
12116 enum rtx_code code
= GET_CODE (x
);
12120 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12121 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12123 rtx x0
= XEXP (x
, 0);
12124 rtx x1
= XEXP (x
, 1);
12127 return 1 + 2 * count_rtxs (x0
);
12129 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12130 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12131 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12132 return 2 + 2 * count_rtxs (x0
)
12133 + count_rtxs (x
== XEXP (x1
, 0)
12134 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12136 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12137 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12138 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12139 return 2 + 2 * count_rtxs (x1
)
12140 + count_rtxs (x
== XEXP (x0
, 0)
12141 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12144 fmt
= GET_RTX_FORMAT (code
);
12145 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12147 ret
+= count_rtxs (XEXP (x
, i
));
12148 else if (fmt
[i
] == 'E')
12149 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12150 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12155 /* Utility function for following routine. Called when X is part of a value
12156 being stored into last_set_value. Sets last_set_table_tick
12157 for each register mentioned. Similar to mention_regs in cse.c */
12160 update_table_tick (rtx x
)
12162 enum rtx_code code
= GET_CODE (x
);
12163 const char *fmt
= GET_RTX_FORMAT (code
);
12168 unsigned int regno
= REGNO (x
);
12169 unsigned int endregno
= END_REGNO (x
);
12172 for (r
= regno
; r
< endregno
; r
++)
12174 reg_stat_type
*rsp
= ®_stat
[r
];
12175 rsp
->last_set_table_tick
= label_tick
;
12181 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12184 /* Check for identical subexpressions. If x contains
12185 identical subexpression we only have to traverse one of
12187 if (i
== 0 && ARITHMETIC_P (x
))
12189 /* Note that at this point x1 has already been
12191 rtx x0
= XEXP (x
, 0);
12192 rtx x1
= XEXP (x
, 1);
12194 /* If x0 and x1 are identical then there is no need to
12199 /* If x0 is identical to a subexpression of x1 then while
12200 processing x1, x0 has already been processed. Thus we
12201 are done with x. */
12202 if (ARITHMETIC_P (x1
)
12203 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12206 /* If x1 is identical to a subexpression of x0 then we
12207 still have to process the rest of x0. */
12208 if (ARITHMETIC_P (x0
)
12209 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12211 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12216 update_table_tick (XEXP (x
, i
));
12218 else if (fmt
[i
] == 'E')
12219 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12220 update_table_tick (XVECEXP (x
, i
, j
));
12223 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12224 are saying that the register is clobbered and we no longer know its
12225 value. If INSN is zero, don't update reg_stat[].last_set; this is
12226 only permitted with VALUE also zero and is used to invalidate the
12230 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12232 unsigned int regno
= REGNO (reg
);
12233 unsigned int endregno
= END_REGNO (reg
);
12235 reg_stat_type
*rsp
;
12237 /* If VALUE contains REG and we have a previous value for REG, substitute
12238 the previous value. */
12239 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12243 /* Set things up so get_last_value is allowed to see anything set up to
12245 subst_low_luid
= DF_INSN_LUID (insn
);
12246 tem
= get_last_value (reg
);
12248 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12249 it isn't going to be useful and will take a lot of time to process,
12250 so just use the CLOBBER. */
12254 if (ARITHMETIC_P (tem
)
12255 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12256 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12257 tem
= XEXP (tem
, 0);
12258 else if (count_occurrences (value
, reg
, 1) >= 2)
12260 /* If there are two or more occurrences of REG in VALUE,
12261 prevent the value from growing too much. */
12262 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12263 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12266 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12270 /* For each register modified, show we don't know its value, that
12271 we don't know about its bitwise content, that its value has been
12272 updated, and that we don't know the location of the death of the
12274 for (i
= regno
; i
< endregno
; i
++)
12276 rsp
= ®_stat
[i
];
12279 rsp
->last_set
= insn
;
12281 rsp
->last_set_value
= 0;
12282 rsp
->last_set_mode
= VOIDmode
;
12283 rsp
->last_set_nonzero_bits
= 0;
12284 rsp
->last_set_sign_bit_copies
= 0;
12285 rsp
->last_death
= 0;
12286 rsp
->truncated_to_mode
= VOIDmode
;
12289 /* Mark registers that are being referenced in this value. */
12291 update_table_tick (value
);
12293 /* Now update the status of each register being set.
12294 If someone is using this register in this block, set this register
12295 to invalid since we will get confused between the two lives in this
12296 basic block. This makes using this register always invalid. In cse, we
12297 scan the table to invalidate all entries using this register, but this
12298 is too much work for us. */
12300 for (i
= regno
; i
< endregno
; i
++)
12302 rsp
= ®_stat
[i
];
12303 rsp
->last_set_label
= label_tick
;
12305 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12306 rsp
->last_set_invalid
= 1;
12308 rsp
->last_set_invalid
= 0;
12311 /* The value being assigned might refer to X (like in "x++;"). In that
12312 case, we must replace it with (clobber (const_int 0)) to prevent
12314 rsp
= ®_stat
[regno
];
12315 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12317 value
= copy_rtx (value
);
12318 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12322 /* For the main register being modified, update the value, the mode, the
12323 nonzero bits, and the number of sign bit copies. */
12325 rsp
->last_set_value
= value
;
12329 machine_mode mode
= GET_MODE (reg
);
12330 subst_low_luid
= DF_INSN_LUID (insn
);
12331 rsp
->last_set_mode
= mode
;
12332 if (GET_MODE_CLASS (mode
) == MODE_INT
12333 && HWI_COMPUTABLE_MODE_P (mode
))
12334 mode
= nonzero_bits_mode
;
12335 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12336 rsp
->last_set_sign_bit_copies
12337 = num_sign_bit_copies (value
, GET_MODE (reg
));
12341 /* Called via note_stores from record_dead_and_set_regs to handle one
12342 SET or CLOBBER in an insn. DATA is the instruction in which the
12343 set is occurring. */
12346 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12348 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12350 if (GET_CODE (dest
) == SUBREG
)
12351 dest
= SUBREG_REG (dest
);
12353 if (!record_dead_insn
)
12356 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12362 /* If we are setting the whole register, we know its value. Otherwise
12363 show that we don't know the value. We can handle SUBREG in
12365 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12366 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12367 else if (GET_CODE (setter
) == SET
12368 && GET_CODE (SET_DEST (setter
)) == SUBREG
12369 && SUBREG_REG (SET_DEST (setter
)) == dest
12370 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12371 && subreg_lowpart_p (SET_DEST (setter
)))
12372 record_value_for_reg (dest
, record_dead_insn
,
12373 gen_lowpart (GET_MODE (dest
),
12374 SET_SRC (setter
)));
12376 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12378 else if (MEM_P (dest
)
12379 /* Ignore pushes, they clobber nothing. */
12380 && ! push_operand (dest
, GET_MODE (dest
)))
12381 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12384 /* Update the records of when each REG was most recently set or killed
12385 for the things done by INSN. This is the last thing done in processing
12386 INSN in the combiner loop.
12388 We update reg_stat[], in particular fields last_set, last_set_value,
12389 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12390 last_death, and also the similar information mem_last_set (which insn
12391 most recently modified memory) and last_call_luid (which insn was the
12392 most recent subroutine call). */
12395 record_dead_and_set_regs (rtx_insn
*insn
)
12400 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12402 if (REG_NOTE_KIND (link
) == REG_DEAD
12403 && REG_P (XEXP (link
, 0)))
12405 unsigned int regno
= REGNO (XEXP (link
, 0));
12406 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12408 for (i
= regno
; i
< endregno
; i
++)
12410 reg_stat_type
*rsp
;
12412 rsp
= ®_stat
[i
];
12413 rsp
->last_death
= insn
;
12416 else if (REG_NOTE_KIND (link
) == REG_INC
)
12417 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12422 hard_reg_set_iterator hrsi
;
12423 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12425 reg_stat_type
*rsp
;
12427 rsp
= ®_stat
[i
];
12428 rsp
->last_set_invalid
= 1;
12429 rsp
->last_set
= insn
;
12430 rsp
->last_set_value
= 0;
12431 rsp
->last_set_mode
= VOIDmode
;
12432 rsp
->last_set_nonzero_bits
= 0;
12433 rsp
->last_set_sign_bit_copies
= 0;
12434 rsp
->last_death
= 0;
12435 rsp
->truncated_to_mode
= VOIDmode
;
12438 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12440 /* We can't combine into a call pattern. Remember, though, that
12441 the return value register is set at this LUID. We could
12442 still replace a register with the return value from the
12443 wrong subroutine call! */
12444 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12447 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12450 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12451 register present in the SUBREG, so for each such SUBREG go back and
12452 adjust nonzero and sign bit information of the registers that are
12453 known to have some zero/sign bits set.
12455 This is needed because when combine blows the SUBREGs away, the
12456 information on zero/sign bits is lost and further combines can be
12457 missed because of that. */
12460 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12462 struct insn_link
*links
;
12464 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12465 machine_mode mode
= GET_MODE (subreg
);
12467 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12470 for (links
= LOG_LINKS (insn
); links
;)
12472 reg_stat_type
*rsp
;
12474 insn
= links
->insn
;
12475 set
= single_set (insn
);
12477 if (! set
|| !REG_P (SET_DEST (set
))
12478 || REGNO (SET_DEST (set
)) != regno
12479 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12481 links
= links
->next
;
12485 rsp
= ®_stat
[regno
];
12486 if (rsp
->last_set
== insn
)
12488 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12489 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12492 if (REG_P (SET_SRC (set
)))
12494 regno
= REGNO (SET_SRC (set
));
12495 links
= LOG_LINKS (insn
);
12502 /* Check if X, a register, is known to contain a value already
12503 truncated to MODE. In this case we can use a subreg to refer to
12504 the truncated value even though in the generic case we would need
12505 an explicit truncation. */
12508 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
12510 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12511 machine_mode truncated
= rsp
->truncated_to_mode
;
12514 || rsp
->truncation_label
< label_tick_ebb_start
)
12516 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12518 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12523 /* If X is a hard reg or a subreg record the mode that the register is
12524 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12525 to turn a truncate into a subreg using this information. Return true
12526 if traversing X is complete. */
12529 record_truncated_value (rtx x
)
12531 machine_mode truncated_mode
;
12532 reg_stat_type
*rsp
;
12534 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12536 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12537 truncated_mode
= GET_MODE (x
);
12539 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12542 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12545 x
= SUBREG_REG (x
);
12547 /* ??? For hard-regs we now record everything. We might be able to
12548 optimize this using last_set_mode. */
12549 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12550 truncated_mode
= GET_MODE (x
);
12554 rsp
= ®_stat
[REGNO (x
)];
12555 if (rsp
->truncated_to_mode
== 0
12556 || rsp
->truncation_label
< label_tick_ebb_start
12557 || (GET_MODE_SIZE (truncated_mode
)
12558 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12560 rsp
->truncated_to_mode
= truncated_mode
;
12561 rsp
->truncation_label
= label_tick
;
12567 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12568 the modes they are used in. This can help truning TRUNCATEs into
12572 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12574 subrtx_var_iterator::array_type array
;
12575 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
12576 if (record_truncated_value (*iter
))
12577 iter
.skip_subrtxes ();
12580 /* Scan X for promoted SUBREGs. For each one found,
12581 note what it implies to the registers used in it. */
12584 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
12586 if (GET_CODE (x
) == SUBREG
12587 && SUBREG_PROMOTED_VAR_P (x
)
12588 && REG_P (SUBREG_REG (x
)))
12589 record_promoted_value (insn
, x
);
12592 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12595 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12599 check_promoted_subreg (insn
, XEXP (x
, i
));
12603 if (XVEC (x
, i
) != 0)
12604 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12605 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12611 /* Verify that all the registers and memory references mentioned in *LOC are
12612 still valid. *LOC was part of a value set in INSN when label_tick was
12613 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12614 the invalid references with (clobber (const_int 0)) and return 1. This
12615 replacement is useful because we often can get useful information about
12616 the form of a value (e.g., if it was produced by a shift that always
12617 produces -1 or 0) even though we don't know exactly what registers it
12618 was produced from. */
12621 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
12624 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12625 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12630 unsigned int regno
= REGNO (x
);
12631 unsigned int endregno
= END_REGNO (x
);
12634 for (j
= regno
; j
< endregno
; j
++)
12636 reg_stat_type
*rsp
= ®_stat
[j
];
12637 if (rsp
->last_set_invalid
12638 /* If this is a pseudo-register that was only set once and not
12639 live at the beginning of the function, it is always valid. */
12640 || (! (regno
>= FIRST_PSEUDO_REGISTER
12641 && REG_N_SETS (regno
) == 1
12642 && (!REGNO_REG_SET_P
12643 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
12645 && rsp
->last_set_label
> tick
))
12648 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12655 /* If this is a memory reference, make sure that there were no stores after
12656 it that might have clobbered the value. We don't have alias info, so we
12657 assume any store invalidates it. Moreover, we only have local UIDs, so
12658 we also assume that there were stores in the intervening basic blocks. */
12659 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12660 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12663 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12667 for (i
= 0; i
< len
; i
++)
12671 /* Check for identical subexpressions. If x contains
12672 identical subexpression we only have to traverse one of
12674 if (i
== 1 && ARITHMETIC_P (x
))
12676 /* Note that at this point x0 has already been checked
12677 and found valid. */
12678 rtx x0
= XEXP (x
, 0);
12679 rtx x1
= XEXP (x
, 1);
12681 /* If x0 and x1 are identical then x is also valid. */
12685 /* If x1 is identical to a subexpression of x0 then
12686 while checking x0, x1 has already been checked. Thus
12687 it is valid and so as x. */
12688 if (ARITHMETIC_P (x0
)
12689 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12692 /* If x0 is identical to a subexpression of x1 then x is
12693 valid iff the rest of x1 is valid. */
12694 if (ARITHMETIC_P (x1
)
12695 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12697 get_last_value_validate (&XEXP (x1
,
12698 x0
== XEXP (x1
, 0) ? 1 : 0),
12699 insn
, tick
, replace
);
12702 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12706 else if (fmt
[i
] == 'E')
12707 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12708 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12709 insn
, tick
, replace
) == 0)
12713 /* If we haven't found a reason for it to be invalid, it is valid. */
12717 /* Get the last value assigned to X, if known. Some registers
12718 in the value may be replaced with (clobber (const_int 0)) if their value
12719 is known longer known reliably. */
12722 get_last_value (const_rtx x
)
12724 unsigned int regno
;
12726 reg_stat_type
*rsp
;
12728 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12729 then convert it to the desired mode. If this is a paradoxical SUBREG,
12730 we cannot predict what values the "extra" bits might have. */
12731 if (GET_CODE (x
) == SUBREG
12732 && subreg_lowpart_p (x
)
12733 && !paradoxical_subreg_p (x
)
12734 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12735 return gen_lowpart (GET_MODE (x
), value
);
12741 rsp
= ®_stat
[regno
];
12742 value
= rsp
->last_set_value
;
12744 /* If we don't have a value, or if it isn't for this basic block and
12745 it's either a hard register, set more than once, or it's a live
12746 at the beginning of the function, return 0.
12748 Because if it's not live at the beginning of the function then the reg
12749 is always set before being used (is never used without being set).
12750 And, if it's set only once, and it's always set before use, then all
12751 uses must have the same last value, even if it's not from this basic
12755 || (rsp
->last_set_label
< label_tick_ebb_start
12756 && (regno
< FIRST_PSEUDO_REGISTER
12757 || REG_N_SETS (regno
) != 1
12759 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
12762 /* If the value was set in a later insn than the ones we are processing,
12763 we can't use it even if the register was only set once. */
12764 if (rsp
->last_set_label
== label_tick
12765 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12768 /* If the value has all its registers valid, return it. */
12769 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12772 /* Otherwise, make a copy and replace any invalid register with
12773 (clobber (const_int 0)). If that fails for some reason, return 0. */
12775 value
= copy_rtx (value
);
12776 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12782 /* Return nonzero if expression X refers to a REG or to memory
12783 that is set in an instruction more recent than FROM_LUID. */
12786 use_crosses_set_p (const_rtx x
, int from_luid
)
12790 enum rtx_code code
= GET_CODE (x
);
12794 unsigned int regno
= REGNO (x
);
12795 unsigned endreg
= END_REGNO (x
);
12797 #ifdef PUSH_ROUNDING
12798 /* Don't allow uses of the stack pointer to be moved,
12799 because we don't know whether the move crosses a push insn. */
12800 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12803 for (; regno
< endreg
; regno
++)
12805 reg_stat_type
*rsp
= ®_stat
[regno
];
12807 && rsp
->last_set_label
== label_tick
12808 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12814 if (code
== MEM
&& mem_last_set
> from_luid
)
12817 fmt
= GET_RTX_FORMAT (code
);
12819 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12824 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12825 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12828 else if (fmt
[i
] == 'e'
12829 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12835 /* Define three variables used for communication between the following
12838 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12839 static int reg_dead_flag
;
12841 /* Function called via note_stores from reg_dead_at_p.
12843 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12844 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12847 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12849 unsigned int regno
, endregno
;
12854 regno
= REGNO (dest
);
12855 endregno
= END_REGNO (dest
);
12856 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12857 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12860 /* Return nonzero if REG is known to be dead at INSN.
12862 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12863 referencing REG, it is dead. If we hit a SET referencing REG, it is
12864 live. Otherwise, see if it is live or dead at the start of the basic
12865 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12866 must be assumed to be always live. */
12869 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
12874 /* Set variables for reg_dead_at_p_1. */
12875 reg_dead_regno
= REGNO (reg
);
12876 reg_dead_endregno
= END_REGNO (reg
);
12880 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12881 we allow the machine description to decide whether use-and-clobber
12882 patterns are OK. */
12883 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12885 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12886 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12890 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12891 beginning of basic block. */
12892 block
= BLOCK_FOR_INSN (insn
);
12897 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12899 return reg_dead_flag
== 1 ? 1 : 0;
12901 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12905 if (insn
== BB_HEAD (block
))
12908 insn
= PREV_INSN (insn
);
12911 /* Look at live-in sets for the basic block that we were in. */
12912 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12913 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12919 /* Note hard registers in X that are used. */
12922 mark_used_regs_combine (rtx x
)
12924 RTX_CODE code
= GET_CODE (x
);
12925 unsigned int regno
;
12936 case ADDR_DIFF_VEC
:
12939 /* CC0 must die in the insn after it is set, so we don't need to take
12940 special note of it here. */
12946 /* If we are clobbering a MEM, mark any hard registers inside the
12947 address as used. */
12948 if (MEM_P (XEXP (x
, 0)))
12949 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12954 /* A hard reg in a wide mode may really be multiple registers.
12955 If so, mark all of them just like the first. */
12956 if (regno
< FIRST_PSEUDO_REGISTER
)
12958 /* None of this applies to the stack, frame or arg pointers. */
12959 if (regno
== STACK_POINTER_REGNUM
12960 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12961 || regno
== HARD_FRAME_POINTER_REGNUM
12963 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12964 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12966 || regno
== FRAME_POINTER_REGNUM
)
12969 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12975 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12977 rtx testreg
= SET_DEST (x
);
12979 while (GET_CODE (testreg
) == SUBREG
12980 || GET_CODE (testreg
) == ZERO_EXTRACT
12981 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12982 testreg
= XEXP (testreg
, 0);
12984 if (MEM_P (testreg
))
12985 mark_used_regs_combine (XEXP (testreg
, 0));
12987 mark_used_regs_combine (SET_SRC (x
));
12995 /* Recursively scan the operands of this expression. */
12998 const char *fmt
= GET_RTX_FORMAT (code
);
13000 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13003 mark_used_regs_combine (XEXP (x
, i
));
13004 else if (fmt
[i
] == 'E')
13008 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13009 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13015 /* Remove register number REGNO from the dead registers list of INSN.
13017 Return the note used to record the death, if there was one. */
13020 remove_death (unsigned int regno
, rtx_insn
*insn
)
13022 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13025 remove_note (insn
, note
);
13030 /* For each register (hardware or pseudo) used within expression X, if its
13031 death is in an instruction with luid between FROM_LUID (inclusive) and
13032 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13033 list headed by PNOTES.
13035 That said, don't move registers killed by maybe_kill_insn.
13037 This is done when X is being merged by combination into TO_INSN. These
13038 notes will then be distributed as needed. */
13041 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13046 enum rtx_code code
= GET_CODE (x
);
13050 unsigned int regno
= REGNO (x
);
13051 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13053 /* Don't move the register if it gets killed in between from and to. */
13054 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13055 && ! reg_referenced_p (x
, maybe_kill_insn
))
13059 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13060 && DF_INSN_LUID (where_dead
) >= from_luid
13061 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13063 rtx note
= remove_death (regno
, where_dead
);
13065 /* It is possible for the call above to return 0. This can occur
13066 when last_death points to I2 or I1 that we combined with.
13067 In that case make a new note.
13069 We must also check for the case where X is a hard register
13070 and NOTE is a death note for a range of hard registers
13071 including X. In that case, we must put REG_DEAD notes for
13072 the remaining registers in place of NOTE. */
13074 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13075 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13076 > GET_MODE_SIZE (GET_MODE (x
))))
13078 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13079 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
13080 unsigned int ourend
= END_HARD_REGNO (x
);
13083 for (i
= deadregno
; i
< deadend
; i
++)
13084 if (i
< regno
|| i
>= ourend
)
13085 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13088 /* If we didn't find any note, or if we found a REG_DEAD note that
13089 covers only part of the given reg, and we have a multi-reg hard
13090 register, then to be safe we must check for REG_DEAD notes
13091 for each register other than the first. They could have
13092 their own REG_DEAD notes lying around. */
13093 else if ((note
== 0
13095 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13096 < GET_MODE_SIZE (GET_MODE (x
)))))
13097 && regno
< FIRST_PSEUDO_REGISTER
13098 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13100 unsigned int ourend
= END_HARD_REGNO (x
);
13101 unsigned int i
, offset
;
13105 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13109 for (i
= regno
+ offset
; i
< ourend
; i
++)
13110 move_deaths (regno_reg_rtx
[i
],
13111 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13114 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13116 XEXP (note
, 1) = *pnotes
;
13120 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13126 else if (GET_CODE (x
) == SET
)
13128 rtx dest
= SET_DEST (x
);
13130 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13132 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13133 that accesses one word of a multi-word item, some
13134 piece of everything register in the expression is used by
13135 this insn, so remove any old death. */
13136 /* ??? So why do we test for equality of the sizes? */
13138 if (GET_CODE (dest
) == ZERO_EXTRACT
13139 || GET_CODE (dest
) == STRICT_LOW_PART
13140 || (GET_CODE (dest
) == SUBREG
13141 && (((GET_MODE_SIZE (GET_MODE (dest
))
13142 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13143 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13144 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13146 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13150 /* If this is some other SUBREG, we know it replaces the entire
13151 value, so use that as the destination. */
13152 if (GET_CODE (dest
) == SUBREG
)
13153 dest
= SUBREG_REG (dest
);
13155 /* If this is a MEM, adjust deaths of anything used in the address.
13156 For a REG (the only other possibility), the entire value is
13157 being replaced so the old value is not used in this insn. */
13160 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13165 else if (GET_CODE (x
) == CLOBBER
)
13168 len
= GET_RTX_LENGTH (code
);
13169 fmt
= GET_RTX_FORMAT (code
);
13171 for (i
= 0; i
< len
; i
++)
13176 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13177 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13180 else if (fmt
[i
] == 'e')
13181 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13185 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13186 pattern of an insn. X must be a REG. */
13189 reg_bitfield_target_p (rtx x
, rtx body
)
13193 if (GET_CODE (body
) == SET
)
13195 rtx dest
= SET_DEST (body
);
13197 unsigned int regno
, tregno
, endregno
, endtregno
;
13199 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13200 target
= XEXP (dest
, 0);
13201 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13202 target
= SUBREG_REG (XEXP (dest
, 0));
13206 if (GET_CODE (target
) == SUBREG
)
13207 target
= SUBREG_REG (target
);
13209 if (!REG_P (target
))
13212 tregno
= REGNO (target
), regno
= REGNO (x
);
13213 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13214 return target
== x
;
13216 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13217 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13219 return endregno
> tregno
&& regno
< endtregno
;
13222 else if (GET_CODE (body
) == PARALLEL
)
13223 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13224 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13230 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13231 as appropriate. I3 and I2 are the insns resulting from the combination
13232 insns including FROM (I2 may be zero).
13234 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13235 not need REG_DEAD notes because they are being substituted for. This
13236 saves searching in the most common cases.
13238 Each note in the list is either ignored or placed on some insns, depending
13239 on the type of note. */
13242 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13243 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13245 rtx note
, next_note
;
13247 rtx_insn
*tem_insn
;
13249 for (note
= notes
; note
; note
= next_note
)
13251 rtx_insn
*place
= 0, *place2
= 0;
13253 next_note
= XEXP (note
, 1);
13254 switch (REG_NOTE_KIND (note
))
13258 /* Doesn't matter much where we put this, as long as it's somewhere.
13259 It is preferable to keep these notes on branches, which is most
13260 likely to be i3. */
13264 case REG_NON_LOCAL_GOTO
:
13269 gcc_assert (i2
&& JUMP_P (i2
));
13274 case REG_EH_REGION
:
13275 /* These notes must remain with the call or trapping instruction. */
13278 else if (i2
&& CALL_P (i2
))
13282 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13283 if (may_trap_p (i3
))
13285 else if (i2
&& may_trap_p (i2
))
13287 /* ??? Otherwise assume we've combined things such that we
13288 can now prove that the instructions can't trap. Drop the
13289 note in this case. */
13293 case REG_ARGS_SIZE
:
13294 /* ??? How to distribute between i3-i1. Assume i3 contains the
13295 entire adjustment. Assert i3 contains at least some adjust. */
13296 if (!noop_move_p (i3
))
13298 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13299 /* fixup_args_size_notes looks at REG_NORETURN note,
13300 so ensure the note is placed there first. */
13304 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13305 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13309 XEXP (n
, 1) = REG_NOTES (i3
);
13310 REG_NOTES (i3
) = n
;
13314 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13315 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13316 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13317 gcc_assert (old_size
!= args_size
13319 && !ACCUMULATE_OUTGOING_ARGS
13320 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13327 case REG_CALL_DECL
:
13328 /* These notes must remain with the call. It should not be
13329 possible for both I2 and I3 to be a call. */
13334 gcc_assert (i2
&& CALL_P (i2
));
13340 /* Any clobbers for i3 may still exist, and so we must process
13341 REG_UNUSED notes from that insn.
13343 Any clobbers from i2 or i1 can only exist if they were added by
13344 recog_for_combine. In that case, recog_for_combine created the
13345 necessary REG_UNUSED notes. Trying to keep any original
13346 REG_UNUSED notes from these insns can cause incorrect output
13347 if it is for the same register as the original i3 dest.
13348 In that case, we will notice that the register is set in i3,
13349 and then add a REG_UNUSED note for the destination of i3, which
13350 is wrong. However, it is possible to have REG_UNUSED notes from
13351 i2 or i1 for register which were both used and clobbered, so
13352 we keep notes from i2 or i1 if they will turn into REG_DEAD
13355 /* If this register is set or clobbered in I3, put the note there
13356 unless there is one already. */
13357 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13359 if (from_insn
!= i3
)
13362 if (! (REG_P (XEXP (note
, 0))
13363 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13364 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13367 /* Otherwise, if this register is used by I3, then this register
13368 now dies here, so we must put a REG_DEAD note here unless there
13370 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13371 && ! (REG_P (XEXP (note
, 0))
13372 ? find_regno_note (i3
, REG_DEAD
,
13373 REGNO (XEXP (note
, 0)))
13374 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13376 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13384 /* These notes say something about results of an insn. We can
13385 only support them if they used to be on I3 in which case they
13386 remain on I3. Otherwise they are ignored.
13388 If the note refers to an expression that is not a constant, we
13389 must also ignore the note since we cannot tell whether the
13390 equivalence is still true. It might be possible to do
13391 slightly better than this (we only have a problem if I2DEST
13392 or I1DEST is present in the expression), but it doesn't
13393 seem worth the trouble. */
13395 if (from_insn
== i3
13396 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13401 /* These notes say something about how a register is used. They must
13402 be present on any use of the register in I2 or I3. */
13403 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13406 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13415 case REG_LABEL_TARGET
:
13416 case REG_LABEL_OPERAND
:
13417 /* This can show up in several ways -- either directly in the
13418 pattern, or hidden off in the constant pool with (or without?)
13419 a REG_EQUAL note. */
13420 /* ??? Ignore the without-reg_equal-note problem for now. */
13421 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13422 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13423 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13424 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
13428 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13429 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13430 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13431 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
13439 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13440 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13442 if (place
&& JUMP_P (place
)
13443 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13444 && (JUMP_LABEL (place
) == NULL
13445 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13447 rtx label
= JUMP_LABEL (place
);
13450 JUMP_LABEL (place
) = XEXP (note
, 0);
13451 else if (LABEL_P (label
))
13452 LABEL_NUSES (label
)--;
13455 if (place2
&& JUMP_P (place2
)
13456 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13457 && (JUMP_LABEL (place2
) == NULL
13458 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13460 rtx label
= JUMP_LABEL (place2
);
13463 JUMP_LABEL (place2
) = XEXP (note
, 0);
13464 else if (LABEL_P (label
))
13465 LABEL_NUSES (label
)--;
13471 /* This note says something about the value of a register prior
13472 to the execution of an insn. It is too much trouble to see
13473 if the note is still correct in all situations. It is better
13474 to simply delete it. */
13478 /* If we replaced the right hand side of FROM_INSN with a
13479 REG_EQUAL note, the original use of the dying register
13480 will not have been combined into I3 and I2. In such cases,
13481 FROM_INSN is guaranteed to be the first of the combined
13482 instructions, so we simply need to search back before
13483 FROM_INSN for the previous use or set of this register,
13484 then alter the notes there appropriately.
13486 If the register is used as an input in I3, it dies there.
13487 Similarly for I2, if it is nonzero and adjacent to I3.
13489 If the register is not used as an input in either I3 or I2
13490 and it is not one of the registers we were supposed to eliminate,
13491 there are two possibilities. We might have a non-adjacent I2
13492 or we might have somehow eliminated an additional register
13493 from a computation. For example, we might have had A & B where
13494 we discover that B will always be zero. In this case we will
13495 eliminate the reference to A.
13497 In both cases, we must search to see if we can find a previous
13498 use of A and put the death note there. */
13501 && from_insn
== i2mod
13502 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13503 tem_insn
= from_insn
;
13507 && CALL_P (from_insn
)
13508 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13510 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13512 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13513 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13515 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13517 && reg_overlap_mentioned_p (XEXP (note
, 0),
13519 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13520 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13527 basic_block bb
= this_basic_block
;
13529 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13531 if (!NONDEBUG_INSN_P (tem_insn
))
13533 if (tem_insn
== BB_HEAD (bb
))
13538 /* If the register is being set at TEM_INSN, see if that is all
13539 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13540 into a REG_UNUSED note instead. Don't delete sets to
13541 global register vars. */
13542 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13543 || !global_regs
[REGNO (XEXP (note
, 0))])
13544 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
13546 rtx set
= single_set (tem_insn
);
13547 rtx inner_dest
= 0;
13549 rtx_insn
*cc0_setter
= NULL
;
13553 for (inner_dest
= SET_DEST (set
);
13554 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13555 || GET_CODE (inner_dest
) == SUBREG
13556 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13557 inner_dest
= XEXP (inner_dest
, 0))
13560 /* Verify that it was the set, and not a clobber that
13561 modified the register.
13563 CC0 targets must be careful to maintain setter/user
13564 pairs. If we cannot delete the setter due to side
13565 effects, mark the user with an UNUSED note instead
13568 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13569 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13571 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13572 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
13573 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13577 /* Move the notes and links of TEM_INSN elsewhere.
13578 This might delete other dead insns recursively.
13579 First set the pattern to something that won't use
13581 rtx old_notes
= REG_NOTES (tem_insn
);
13583 PATTERN (tem_insn
) = pc_rtx
;
13584 REG_NOTES (tem_insn
) = NULL
;
13586 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
13587 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13588 distribute_links (LOG_LINKS (tem_insn
));
13590 SET_INSN_DELETED (tem_insn
);
13591 if (tem_insn
== i2
)
13595 /* Delete the setter too. */
13598 PATTERN (cc0_setter
) = pc_rtx
;
13599 old_notes
= REG_NOTES (cc0_setter
);
13600 REG_NOTES (cc0_setter
) = NULL
;
13602 distribute_notes (old_notes
, cc0_setter
,
13604 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13605 distribute_links (LOG_LINKS (cc0_setter
));
13607 SET_INSN_DELETED (cc0_setter
);
13608 if (cc0_setter
== i2
)
13615 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13617 /* If there isn't already a REG_UNUSED note, put one
13618 here. Do not place a REG_DEAD note, even if
13619 the register is also used here; that would not
13620 match the algorithm used in lifetime analysis
13621 and can cause the consistency check in the
13622 scheduler to fail. */
13623 if (! find_regno_note (tem_insn
, REG_UNUSED
,
13624 REGNO (XEXP (note
, 0))))
13629 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
13630 || (CALL_P (tem_insn
)
13631 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
13635 /* If we are doing a 3->2 combination, and we have a
13636 register which formerly died in i3 and was not used
13637 by i2, which now no longer dies in i3 and is used in
13638 i2 but does not die in i2, and place is between i2
13639 and i3, then we may need to move a link from place to
13641 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13643 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13644 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13646 struct insn_link
*links
= LOG_LINKS (place
);
13647 LOG_LINKS (place
) = NULL
;
13648 distribute_links (links
);
13653 if (tem_insn
== BB_HEAD (bb
))
13659 /* If the register is set or already dead at PLACE, we needn't do
13660 anything with this note if it is still a REG_DEAD note.
13661 We check here if it is set at all, not if is it totally replaced,
13662 which is what `dead_or_set_p' checks, so also check for it being
13665 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13667 unsigned int regno
= REGNO (XEXP (note
, 0));
13668 reg_stat_type
*rsp
= ®_stat
[regno
];
13670 if (dead_or_set_p (place
, XEXP (note
, 0))
13671 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13673 /* Unless the register previously died in PLACE, clear
13674 last_death. [I no longer understand why this is
13676 if (rsp
->last_death
!= place
)
13677 rsp
->last_death
= 0;
13681 rsp
->last_death
= place
;
13683 /* If this is a death note for a hard reg that is occupying
13684 multiple registers, ensure that we are still using all
13685 parts of the object. If we find a piece of the object
13686 that is unused, we must arrange for an appropriate REG_DEAD
13687 note to be added for it. However, we can't just emit a USE
13688 and tag the note to it, since the register might actually
13689 be dead; so we recourse, and the recursive call then finds
13690 the previous insn that used this register. */
13692 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13693 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13695 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13696 bool all_used
= true;
13699 for (i
= regno
; i
< endregno
; i
++)
13700 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13701 && ! find_regno_fusage (place
, USE
, i
))
13702 || dead_or_set_regno_p (place
, i
))
13710 /* Put only REG_DEAD notes for pieces that are
13711 not already dead or set. */
13713 for (i
= regno
; i
< endregno
;
13714 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13716 rtx piece
= regno_reg_rtx
[i
];
13717 basic_block bb
= this_basic_block
;
13719 if (! dead_or_set_p (place
, piece
)
13720 && ! reg_bitfield_target_p (piece
,
13723 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13726 distribute_notes (new_note
, place
, place
,
13727 NULL
, NULL_RTX
, NULL_RTX
,
13730 else if (! refers_to_regno_p (i
, i
+ 1,
13731 PATTERN (place
), 0)
13732 && ! find_regno_fusage (place
, USE
, i
))
13733 for (tem_insn
= PREV_INSN (place
); ;
13734 tem_insn
= PREV_INSN (tem_insn
))
13736 if (!NONDEBUG_INSN_P (tem_insn
))
13738 if (tem_insn
== BB_HEAD (bb
))
13742 if (dead_or_set_p (tem_insn
, piece
)
13743 || reg_bitfield_target_p (piece
,
13744 PATTERN (tem_insn
)))
13746 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
13759 /* Any other notes should not be present at this point in the
13761 gcc_unreachable ();
13766 XEXP (note
, 1) = REG_NOTES (place
);
13767 REG_NOTES (place
) = note
;
13771 add_shallow_copy_of_reg_note (place2
, note
);
13775 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13776 I3, I2, and I1 to new locations. This is also called to add a link
13777 pointing at I3 when I3's destination is changed. */
13780 distribute_links (struct insn_link
*links
)
13782 struct insn_link
*link
, *next_link
;
13784 for (link
= links
; link
; link
= next_link
)
13786 rtx_insn
*place
= 0;
13790 next_link
= link
->next
;
13792 /* If the insn that this link points to is a NOTE or isn't a single
13793 set, ignore it. In the latter case, it isn't clear what we
13794 can do other than ignore the link, since we can't tell which
13795 register it was for. Such links wouldn't be used by combine
13798 It is not possible for the destination of the target of the link to
13799 have been changed by combine. The only potential of this is if we
13800 replace I3, I2, and I1 by I3 and I2. But in that case the
13801 destination of I2 also remains unchanged. */
13803 if (NOTE_P (link
->insn
)
13804 || (set
= single_set (link
->insn
)) == 0)
13807 reg
= SET_DEST (set
);
13808 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13809 || GET_CODE (reg
) == STRICT_LOW_PART
)
13810 reg
= XEXP (reg
, 0);
13812 /* A LOG_LINK is defined as being placed on the first insn that uses
13813 a register and points to the insn that sets the register. Start
13814 searching at the next insn after the target of the link and stop
13815 when we reach a set of the register or the end of the basic block.
13817 Note that this correctly handles the link that used to point from
13818 I3 to I2. Also note that not much searching is typically done here
13819 since most links don't point very far away. */
13821 for (insn
= NEXT_INSN (link
->insn
);
13822 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
13823 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13824 insn
= NEXT_INSN (insn
))
13825 if (DEBUG_INSN_P (insn
))
13827 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13829 if (reg_referenced_p (reg
, PATTERN (insn
)))
13833 else if (CALL_P (insn
)
13834 && find_reg_fusage (insn
, USE
, reg
))
13839 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13842 /* If we found a place to put the link, place it there unless there
13843 is already a link to the same insn as LINK at that point. */
13847 struct insn_link
*link2
;
13849 FOR_EACH_LOG_LINK (link2
, place
)
13850 if (link2
->insn
== link
->insn
)
13855 link
->next
= LOG_LINKS (place
);
13856 LOG_LINKS (place
) = link
;
13858 /* Set added_links_insn to the earliest insn we added a
13860 if (added_links_insn
== 0
13861 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13862 added_links_insn
= place
;
13868 /* Check for any register or memory mentioned in EQUIV that is not
13869 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13870 of EXPR where some registers may have been replaced by constants. */
13873 unmentioned_reg_p (rtx equiv
, rtx expr
)
13875 subrtx_iterator::array_type array
;
13876 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
13878 const_rtx x
= *iter
;
13879 if ((REG_P (x
) || MEM_P (x
))
13880 && !reg_mentioned_p (x
, expr
))
13886 DEBUG_FUNCTION
void
13887 dump_combine_stats (FILE *file
)
13891 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13892 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13896 dump_combine_total_stats (FILE *file
)
13900 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13901 total_attempts
, total_merges
, total_extras
, total_successes
);
13904 /* Try combining insns through substitution. */
13905 static unsigned int
13906 rest_of_handle_combine (void)
13908 int rebuild_jump_labels_after_combine
;
13910 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13911 df_note_add_problem ();
13914 regstat_init_n_sets_and_refs ();
13916 rebuild_jump_labels_after_combine
13917 = combine_instructions (get_insns (), max_reg_num ());
13919 /* Combining insns may have turned an indirect jump into a
13920 direct jump. Rebuild the JUMP_LABEL fields of jumping
13922 if (rebuild_jump_labels_after_combine
)
13924 timevar_push (TV_JUMP
);
13925 rebuild_jump_labels (get_insns ());
13927 timevar_pop (TV_JUMP
);
13930 regstat_free_n_sets_and_refs ();
13936 const pass_data pass_data_combine
=
13938 RTL_PASS
, /* type */
13939 "combine", /* name */
13940 OPTGROUP_NONE
, /* optinfo_flags */
13941 TV_COMBINE
, /* tv_id */
13942 PROP_cfglayout
, /* properties_required */
13943 0, /* properties_provided */
13944 0, /* properties_destroyed */
13945 0, /* todo_flags_start */
13946 TODO_df_finish
, /* todo_flags_finish */
13949 class pass_combine
: public rtl_opt_pass
13952 pass_combine (gcc::context
*ctxt
)
13953 : rtl_opt_pass (pass_data_combine
, ctxt
)
13956 /* opt_pass methods: */
13957 virtual bool gate (function
*) { return (optimize
> 0); }
13958 virtual unsigned int execute (function
*)
13960 return rest_of_handle_combine ();
13963 }; // class pass_combine
13965 } // anon namespace
13968 make_pass_combine (gcc::context
*ctxt
)
13970 return new pass_combine (ctxt
);