1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
84 #include "stor-layout.h"
88 #include "hard-reg-set.h"
96 #include "dominance.h"
99 #include "cfgcleanup.h"
100 #include "basic-block.h"
101 #include "insn-config.h"
102 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
104 #include "insn-attr.h"
106 #include "diagnostic-core.h"
108 #include "insn-codes.h"
110 #include "rtlhooks-def.h"
112 #include "tree-pass.h"
114 #include "valtrack.h"
115 #include "hash-map.h"
117 #include "plugin-api.h"
121 #include "statistics.h"
123 #include "rtl-iter.h"
125 /* Number of attempts to combine instructions in this function. */
127 static int combine_attempts
;
129 /* Number of attempts that got as far as substitution in this function. */
131 static int combine_merges
;
133 /* Number of instructions combined with added SETs in this function. */
135 static int combine_extras
;
137 /* Number of instructions combined in this function. */
139 static int combine_successes
;
141 /* Totals over entire compilation. */
143 static int total_attempts
, total_merges
, total_extras
, total_successes
;
145 /* combine_instructions may try to replace the right hand side of the
146 second instruction with the value of an associated REG_EQUAL note
147 before throwing it at try_combine. That is problematic when there
148 is a REG_DEAD note for a register used in the old right hand side
149 and can cause distribute_notes to do wrong things. This is the
150 second instruction if it has been so modified, null otherwise. */
152 static rtx_insn
*i2mod
;
154 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
156 static rtx i2mod_old_rhs
;
158 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
160 static rtx i2mod_new_rhs
;
162 typedef struct reg_stat_struct
{
163 /* Record last point of death of (hard or pseudo) register n. */
164 rtx_insn
*last_death
;
166 /* Record last point of modification of (hard or pseudo) register n. */
169 /* The next group of fields allows the recording of the last value assigned
170 to (hard or pseudo) register n. We use this information to see if an
171 operation being processed is redundant given a prior operation performed
172 on the register. For example, an `and' with a constant is redundant if
173 all the zero bits are already known to be turned off.
175 We use an approach similar to that used by cse, but change it in the
178 (1) We do not want to reinitialize at each label.
179 (2) It is useful, but not critical, to know the actual value assigned
180 to a register. Often just its form is helpful.
182 Therefore, we maintain the following fields:
184 last_set_value the last value assigned
185 last_set_label records the value of label_tick when the
186 register was assigned
187 last_set_table_tick records the value of label_tick when a
188 value using the register is assigned
189 last_set_invalid set to nonzero when it is not valid
190 to use the value of this register in some
193 To understand the usage of these tables, it is important to understand
194 the distinction between the value in last_set_value being valid and
195 the register being validly contained in some other expression in the
198 (The next two parameters are out of date).
200 reg_stat[i].last_set_value is valid if it is nonzero, and either
201 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
203 Register I may validly appear in any expression returned for the value
204 of another register if reg_n_sets[i] is 1. It may also appear in the
205 value for register J if reg_stat[j].last_set_invalid is zero, or
206 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
208 If an expression is found in the table containing a register which may
209 not validly appear in an expression, the register is replaced by
210 something that won't match, (clobber (const_int 0)). */
212 /* Record last value assigned to (hard or pseudo) register n. */
216 /* Record the value of label_tick when an expression involving register n
217 is placed in last_set_value. */
219 int last_set_table_tick
;
221 /* Record the value of label_tick when the value for register n is placed in
226 /* These fields are maintained in parallel with last_set_value and are
227 used to store the mode in which the register was last set, the bits
228 that were known to be zero when it was last set, and the number of
229 sign bits copies it was known to have when it was last set. */
231 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
232 char last_set_sign_bit_copies
;
233 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
235 /* Set nonzero if references to register n in expressions should not be
236 used. last_set_invalid is set nonzero when this register is being
237 assigned to and last_set_table_tick == label_tick. */
239 char last_set_invalid
;
241 /* Some registers that are set more than once and used in more than one
242 basic block are nevertheless always set in similar ways. For example,
243 a QImode register may be loaded from memory in two places on a machine
244 where byte loads zero extend.
246 We record in the following fields if a register has some leading bits
247 that are always equal to the sign bit, and what we know about the
248 nonzero bits of a register, specifically which bits are known to be
251 If an entry is zero, it means that we don't know anything special. */
253 unsigned char sign_bit_copies
;
255 unsigned HOST_WIDE_INT nonzero_bits
;
257 /* Record the value of the label_tick when the last truncation
258 happened. The field truncated_to_mode is only valid if
259 truncation_label == label_tick. */
261 int truncation_label
;
263 /* Record the last truncation seen for this register. If truncation
264 is not a nop to this mode we might be able to save an explicit
265 truncation if we know that value already contains a truncated
268 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
272 static vec
<reg_stat_type
> reg_stat
;
274 /* Record the luid of the last insn that invalidated memory
275 (anything that writes memory, and subroutine calls, but not pushes). */
277 static int mem_last_set
;
279 /* Record the luid of the last CALL_INSN
280 so we can tell whether a potential combination crosses any calls. */
282 static int last_call_luid
;
284 /* When `subst' is called, this is the insn that is being modified
285 (by combining in a previous insn). The PATTERN of this insn
286 is still the old pattern partially modified and it should not be
287 looked at, but this may be used to examine the successors of the insn
288 to judge whether a simplification is valid. */
290 static rtx_insn
*subst_insn
;
292 /* This is the lowest LUID that `subst' is currently dealing with.
293 get_last_value will not return a value if the register was set at or
294 after this LUID. If not for this mechanism, we could get confused if
295 I2 or I1 in try_combine were an insn that used the old value of a register
296 to obtain a new value. In that case, we might erroneously get the
297 new value of the register when we wanted the old one. */
299 static int subst_low_luid
;
301 /* This contains any hard registers that are used in newpat; reg_dead_at_p
302 must consider all these registers to be always live. */
304 static HARD_REG_SET newpat_used_regs
;
306 /* This is an insn to which a LOG_LINKS entry has been added. If this
307 insn is the earlier than I2 or I3, combine should rescan starting at
310 static rtx_insn
*added_links_insn
;
312 /* Basic block in which we are performing combines. */
313 static basic_block this_basic_block
;
314 static bool optimize_this_for_speed_p
;
317 /* Length of the currently allocated uid_insn_cost array. */
319 static int max_uid_known
;
321 /* The following array records the insn_rtx_cost for every insn
322 in the instruction stream. */
324 static int *uid_insn_cost
;
326 /* The following array records the LOG_LINKS for every insn in the
327 instruction stream as struct insn_link pointers. */
332 struct insn_link
*next
;
335 static struct insn_link
**uid_log_links
;
337 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
338 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
340 #define FOR_EACH_LOG_LINK(L, INSN) \
341 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
343 /* Links for LOG_LINKS are allocated from this obstack. */
345 static struct obstack insn_link_obstack
;
347 /* Allocate a link. */
349 static inline struct insn_link
*
350 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
353 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
354 sizeof (struct insn_link
));
361 /* Incremented for each basic block. */
363 static int label_tick
;
365 /* Reset to label_tick for each extended basic block in scanning order. */
367 static int label_tick_ebb_start
;
369 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
370 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
372 static machine_mode nonzero_bits_mode
;
374 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
375 be safely used. It is zero while computing them and after combine has
376 completed. This former test prevents propagating values based on
377 previously set values, which can be incorrect if a variable is modified
380 static int nonzero_sign_valid
;
383 /* Record one modification to rtl structure
384 to be undone by storing old_contents into *where. */
386 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
392 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
393 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
396 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
397 num_undo says how many are currently recorded.
399 other_insn is nonzero if we have modified some other insn in the process
400 of working on subst_insn. It must be verified too. */
406 rtx_insn
*other_insn
;
409 static struct undobuf undobuf
;
411 /* Number of times the pseudo being substituted for
412 was found and replaced. */
414 static int n_occurrences
;
416 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
418 unsigned HOST_WIDE_INT
,
419 unsigned HOST_WIDE_INT
*);
420 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
422 unsigned int, unsigned int *);
423 static void do_SUBST (rtx
*, rtx
);
424 static void do_SUBST_INT (int *, int);
425 static void init_reg_last (void);
426 static void setup_incoming_promotions (rtx_insn
*);
427 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
428 static int cant_combine_insn_p (rtx_insn
*);
429 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
430 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
431 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
432 static int contains_muldiv (rtx
);
433 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
435 static void undo_all (void);
436 static void undo_commit (void);
437 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
438 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
439 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
440 static rtx
simplify_if_then_else (rtx
);
441 static rtx
simplify_set (rtx
);
442 static rtx
simplify_logical (rtx
);
443 static rtx
expand_compound_operation (rtx
);
444 static const_rtx
expand_field_assignment (const_rtx
);
445 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
446 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
447 static rtx
extract_left_shift (rtx
, int);
448 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
449 unsigned HOST_WIDE_INT
*);
450 static rtx
canon_reg_for_combine (rtx
, rtx
);
451 static rtx
force_to_mode (rtx
, machine_mode
,
452 unsigned HOST_WIDE_INT
, int);
453 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
454 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
455 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
456 static rtx
make_field_assignment (rtx
);
457 static rtx
apply_distributive_law (rtx
);
458 static rtx
distribute_and_simplify_rtx (rtx
, int);
459 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
460 unsigned HOST_WIDE_INT
);
461 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
462 unsigned HOST_WIDE_INT
);
463 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
464 HOST_WIDE_INT
, machine_mode
, int *);
465 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
466 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
468 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
469 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
470 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
472 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
473 static void update_table_tick (rtx
);
474 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
475 static void check_promoted_subreg (rtx_insn
*, rtx
);
476 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
477 static void record_dead_and_set_regs (rtx_insn
*);
478 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
479 static rtx
get_last_value (const_rtx
);
480 static int use_crosses_set_p (const_rtx
, int);
481 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
482 static int reg_dead_at_p (rtx
, rtx_insn
*);
483 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
484 static int reg_bitfield_target_p (rtx
, rtx
);
485 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
486 static void distribute_links (struct insn_link
*);
487 static void mark_used_regs_combine (rtx
);
488 static void record_promoted_value (rtx_insn
*, rtx
);
489 static bool unmentioned_reg_p (rtx
, rtx
);
490 static void record_truncated_values (rtx
*, void *);
491 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
492 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
495 /* It is not safe to use ordinary gen_lowpart in combine.
496 See comments in gen_lowpart_for_combine. */
497 #undef RTL_HOOKS_GEN_LOWPART
498 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
500 /* Our implementation of gen_lowpart never emits a new pseudo. */
501 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
502 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
504 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
505 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
507 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
508 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
510 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
511 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
513 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
516 /* Convenience wrapper for the canonicalize_comparison target hook.
517 Target hooks cannot use enum rtx_code. */
519 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
520 bool op0_preserve_value
)
522 int code_int
= (int)*code
;
523 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
524 *code
= (enum rtx_code
)code_int
;
527 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
528 PATTERN can not be split. Otherwise, it returns an insn sequence.
529 This is a wrapper around split_insns which ensures that the
530 reg_stat vector is made larger if the splitter creates a new
534 combine_split_insns (rtx pattern
, rtx insn
)
539 ret
= safe_as_a
<rtx_insn
*> (split_insns (pattern
, insn
));
540 nregs
= max_reg_num ();
541 if (nregs
> reg_stat
.length ())
542 reg_stat
.safe_grow_cleared (nregs
);
546 /* This is used by find_single_use to locate an rtx in LOC that
547 contains exactly one use of DEST, which is typically either a REG
548 or CC0. It returns a pointer to the innermost rtx expression
549 containing DEST. Appearances of DEST that are being used to
550 totally replace it are not counted. */
553 find_single_use_1 (rtx dest
, rtx
*loc
)
556 enum rtx_code code
= GET_CODE (x
);
572 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
573 of a REG that occupies all of the REG, the insn uses DEST if
574 it is mentioned in the destination or the source. Otherwise, we
575 need just check the source. */
576 if (GET_CODE (SET_DEST (x
)) != CC0
577 && GET_CODE (SET_DEST (x
)) != PC
578 && !REG_P (SET_DEST (x
))
579 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
580 && REG_P (SUBREG_REG (SET_DEST (x
)))
581 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
582 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
583 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
584 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
587 return find_single_use_1 (dest
, &SET_SRC (x
));
591 return find_single_use_1 (dest
, &XEXP (x
, 0));
597 /* If it wasn't one of the common cases above, check each expression and
598 vector of this code. Look for a unique usage of DEST. */
600 fmt
= GET_RTX_FORMAT (code
);
601 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
605 if (dest
== XEXP (x
, i
)
606 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
607 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
610 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
613 result
= this_result
;
614 else if (this_result
)
615 /* Duplicate usage. */
618 else if (fmt
[i
] == 'E')
622 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
624 if (XVECEXP (x
, i
, j
) == dest
626 && REG_P (XVECEXP (x
, i
, j
))
627 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
630 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
633 result
= this_result
;
634 else if (this_result
)
644 /* See if DEST, produced in INSN, is used only a single time in the
645 sequel. If so, return a pointer to the innermost rtx expression in which
648 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
650 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
651 care about REG_DEAD notes or LOG_LINKS.
653 Otherwise, we find the single use by finding an insn that has a
654 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
655 only referenced once in that insn, we know that it must be the first
656 and last insn referencing DEST. */
659 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
664 struct insn_link
*link
;
669 next
= NEXT_INSN (insn
);
671 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
674 result
= find_single_use_1 (dest
, &PATTERN (next
));
684 bb
= BLOCK_FOR_INSN (insn
);
685 for (next
= NEXT_INSN (insn
);
686 next
&& BLOCK_FOR_INSN (next
) == bb
;
687 next
= NEXT_INSN (next
))
688 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
690 FOR_EACH_LOG_LINK (link
, next
)
691 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
696 result
= find_single_use_1 (dest
, &PATTERN (next
));
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
713 do_SUBST (rtx
*into
, rtx newval
)
718 if (oldval
== newval
)
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
726 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
727 && CONST_INT_P (newval
))
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
731 gcc_assert (INTVAL (newval
)
732 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
740 gcc_assert (!(GET_CODE (oldval
) == SUBREG
741 && CONST_INT_P (SUBREG_REG (oldval
))));
742 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
743 && CONST_INT_P (XEXP (oldval
, 0))));
747 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
749 buf
= XNEW (struct undo
);
751 buf
->kind
= UNDO_RTX
;
753 buf
->old_contents
.r
= oldval
;
756 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
766 do_SUBST_INT (int *into
, int newval
)
771 if (oldval
== newval
)
775 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
777 buf
= XNEW (struct undo
);
779 buf
->kind
= UNDO_INT
;
781 buf
->old_contents
.i
= oldval
;
784 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
795 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
798 machine_mode oldval
= GET_MODE (*into
);
800 if (oldval
== newval
)
804 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
806 buf
= XNEW (struct undo
);
808 buf
->kind
= UNDO_MODE
;
810 buf
->old_contents
.m
= oldval
;
811 adjust_reg_mode (*into
, newval
);
813 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
819 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
822 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
825 struct insn_link
* oldval
= *into
;
827 if (oldval
== newval
)
831 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
833 buf
= XNEW (struct undo
);
835 buf
->kind
= UNDO_LINKS
;
837 buf
->old_contents
.l
= oldval
;
840 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
843 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
846 /* Subroutine of try_combine. Determine whether the replacement patterns
847 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
848 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
849 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
850 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
851 of all the instructions can be estimated and the replacements are more
852 expensive than the original sequence. */
855 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
856 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
858 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
859 int new_i2_cost
, new_i3_cost
;
860 int old_cost
, new_cost
;
862 /* Lookup the original insn_rtx_costs. */
863 i2_cost
= INSN_COST (i2
);
864 i3_cost
= INSN_COST (i3
);
868 i1_cost
= INSN_COST (i1
);
871 i0_cost
= INSN_COST (i0
);
872 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
873 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
877 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
878 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
884 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
885 i1_cost
= i0_cost
= 0;
888 /* Calculate the replacement insn_rtx_costs. */
889 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
892 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
893 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
894 ? new_i2_cost
+ new_i3_cost
: 0;
898 new_cost
= new_i3_cost
;
902 if (undobuf
.other_insn
)
904 int old_other_cost
, new_other_cost
;
906 old_other_cost
= INSN_COST (undobuf
.other_insn
);
907 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
908 if (old_other_cost
> 0 && new_other_cost
> 0)
910 old_cost
+= old_other_cost
;
911 new_cost
+= new_other_cost
;
917 /* Disallow this combination if both new_cost and old_cost are greater than
918 zero, and new_cost is greater than old cost. */
919 int reject
= old_cost
> 0 && new_cost
> old_cost
;
923 fprintf (dump_file
, "%s combination of insns ",
924 reject
? "rejecting" : "allowing");
926 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
928 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
929 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
931 fprintf (dump_file
, "original costs ");
933 fprintf (dump_file
, "%d + ", i0_cost
);
935 fprintf (dump_file
, "%d + ", i1_cost
);
936 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
939 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
940 new_i2_cost
, new_i3_cost
, new_cost
);
942 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
948 /* Update the uid_insn_cost array with the replacement costs. */
949 INSN_COST (i2
) = new_i2_cost
;
950 INSN_COST (i3
) = new_i3_cost
;
962 /* Delete any insns that copy a register to itself. */
965 delete_noop_moves (void)
967 rtx_insn
*insn
, *next
;
970 FOR_EACH_BB_FN (bb
, cfun
)
972 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
974 next
= NEXT_INSN (insn
);
975 if (INSN_P (insn
) && noop_move_p (insn
))
978 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
980 delete_insn_and_edges (insn
);
987 /* Return false if we do not want to (or cannot) combine DEF. */
989 can_combine_def_p (df_ref def
)
991 /* Do not consider if it is pre/post modification in MEM. */
992 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
995 unsigned int regno
= DF_REF_REGNO (def
);
997 /* Do not combine frame pointer adjustments. */
998 if ((regno
== FRAME_POINTER_REGNUM
999 && (!reload_completed
|| frame_pointer_needed
))
1000 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1001 || (regno
== HARD_FRAME_POINTER_REGNUM
1002 && (!reload_completed
|| frame_pointer_needed
))
1004 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1005 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1013 /* Return false if we do not want to (or cannot) combine USE. */
1015 can_combine_use_p (df_ref use
)
1017 /* Do not consider the usage of the stack pointer by function call. */
1018 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1024 /* Fill in log links field for all insns. */
1027 create_log_links (void)
1030 rtx_insn
**next_use
;
1034 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1045 FOR_EACH_BB_FN (bb
, cfun
)
1047 FOR_BB_INSNS_REVERSE (bb
, insn
)
1049 if (!NONDEBUG_INSN_P (insn
))
1052 /* Log links are created only once. */
1053 gcc_assert (!LOG_LINKS (insn
));
1055 FOR_EACH_INSN_DEF (def
, insn
)
1057 unsigned int regno
= DF_REF_REGNO (def
);
1060 if (!next_use
[regno
])
1063 if (!can_combine_def_p (def
))
1066 use_insn
= next_use
[regno
];
1067 next_use
[regno
] = NULL
;
1069 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1079 if (regno
< FIRST_PSEUDO_REGISTER
1080 && asm_noperands (PATTERN (use_insn
)) >= 0)
1083 /* Don't add duplicate links between instructions. */
1084 struct insn_link
*links
;
1085 FOR_EACH_LOG_LINK (links
, use_insn
)
1086 if (insn
== links
->insn
&& regno
== links
->regno
)
1090 LOG_LINKS (use_insn
)
1091 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1094 FOR_EACH_INSN_USE (use
, insn
)
1095 if (can_combine_use_p (use
))
1096 next_use
[DF_REF_REGNO (use
)] = insn
;
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1111 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1113 struct insn_link
*links
;
1114 FOR_EACH_LOG_LINK (links
, b
)
1115 if (links
->insn
== a
)
1124 /* Main entry point for combiner. F is the first insn of the function.
1125 NREGS is the first unused pseudo-reg number.
1127 Return nonzero if the combiner has turned an indirect jump
1128 instruction into a direct jump. */
1130 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1132 rtx_insn
*insn
, *next
;
1136 struct insn_link
*links
, *nextlinks
;
1138 basic_block last_bb
;
1140 int new_direct_jump_p
= 0;
1142 for (first
= f
; first
&& !INSN_P (first
); )
1143 first
= NEXT_INSN (first
);
1147 combine_attempts
= 0;
1150 combine_successes
= 0;
1152 rtl_hooks
= combine_rtl_hooks
;
1154 reg_stat
.safe_grow_cleared (nregs
);
1156 init_recog_no_volatile ();
1158 /* Allocate array for insn info. */
1159 max_uid_known
= get_max_uid ();
1160 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1161 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1162 gcc_obstack_init (&insn_link_obstack
);
1164 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1166 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1167 problems when, for example, we have j <<= 1 in a loop. */
1169 nonzero_sign_valid
= 0;
1170 label_tick
= label_tick_ebb_start
= 1;
1172 /* Scan all SETs and see if we can deduce anything about what
1173 bits are known to be zero for some registers and how many copies
1174 of the sign bit are known to exist for those registers.
1176 Also set any known values so that we can use it while searching
1177 for what bits are known to be set. */
1179 setup_incoming_promotions (first
);
1180 /* Allow the entry block and the first block to fall into the same EBB.
1181 Conceptually the incoming promotions are assigned to the entry block. */
1182 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1184 create_log_links ();
1185 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1187 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1192 if (!single_pred_p (this_basic_block
)
1193 || single_pred (this_basic_block
) != last_bb
)
1194 label_tick_ebb_start
= label_tick
;
1195 last_bb
= this_basic_block
;
1197 FOR_BB_INSNS (this_basic_block
, insn
)
1198 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1204 subst_low_luid
= DF_INSN_LUID (insn
);
1207 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1209 record_dead_and_set_regs (insn
);
1212 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1213 if (REG_NOTE_KIND (links
) == REG_INC
)
1214 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1218 /* Record the current insn_rtx_cost of this instruction. */
1219 if (NONJUMP_INSN_P (insn
))
1220 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1221 optimize_this_for_speed_p
);
1223 fprintf (dump_file
, "insn_cost %d: %d\n",
1224 INSN_UID (insn
), INSN_COST (insn
));
1228 nonzero_sign_valid
= 1;
1230 /* Now scan all the insns in forward order. */
1231 label_tick
= label_tick_ebb_start
= 1;
1233 setup_incoming_promotions (first
);
1234 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1235 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1237 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1239 rtx_insn
*last_combined_insn
= NULL
;
1240 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1245 if (!single_pred_p (this_basic_block
)
1246 || single_pred (this_basic_block
) != last_bb
)
1247 label_tick_ebb_start
= label_tick
;
1248 last_bb
= this_basic_block
;
1250 rtl_profile_for_bb (this_basic_block
);
1251 for (insn
= BB_HEAD (this_basic_block
);
1252 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1253 insn
= next
? next
: NEXT_INSN (insn
))
1256 if (!NONDEBUG_INSN_P (insn
))
1259 while (last_combined_insn
1260 && last_combined_insn
->deleted ())
1261 last_combined_insn
= PREV_INSN (last_combined_insn
);
1262 if (last_combined_insn
== NULL_RTX
1263 || BARRIER_P (last_combined_insn
)
1264 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1265 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1266 last_combined_insn
= insn
;
1268 /* See if we know about function return values before this
1269 insn based upon SUBREG flags. */
1270 check_promoted_subreg (insn
, PATTERN (insn
));
1272 /* See if we can find hardregs and subreg of pseudos in
1273 narrower modes. This could help turning TRUNCATEs
1275 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1277 /* Try this insn with each insn it links back to. */
1279 FOR_EACH_LOG_LINK (links
, insn
)
1280 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1281 NULL
, &new_direct_jump_p
,
1282 last_combined_insn
)) != 0)
1284 statistics_counter_event (cfun
, "two-insn combine", 1);
1288 /* Try each sequence of three linked insns ending with this one. */
1290 if (max_combine
>= 3)
1291 FOR_EACH_LOG_LINK (links
, insn
)
1293 rtx_insn
*link
= links
->insn
;
1295 /* If the linked insn has been replaced by a note, then there
1296 is no point in pursuing this chain any further. */
1300 FOR_EACH_LOG_LINK (nextlinks
, link
)
1301 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1302 NULL
, &new_direct_jump_p
,
1303 last_combined_insn
)) != 0)
1305 statistics_counter_event (cfun
, "three-insn combine", 1);
1311 /* Try to combine a jump insn that uses CC0
1312 with a preceding insn that sets CC0, and maybe with its
1313 logical predecessor as well.
1314 This is how we make decrement-and-branch insns.
1315 We need this special code because data flow connections
1316 via CC0 do not get entered in LOG_LINKS. */
1319 && (prev
= prev_nonnote_insn (insn
)) != 0
1320 && NONJUMP_INSN_P (prev
)
1321 && sets_cc0_p (PATTERN (prev
)))
1323 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1325 last_combined_insn
)) != 0)
1328 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1329 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1330 NULL
, &new_direct_jump_p
,
1331 last_combined_insn
)) != 0)
1335 /* Do the same for an insn that explicitly references CC0. */
1336 if (NONJUMP_INSN_P (insn
)
1337 && (prev
= prev_nonnote_insn (insn
)) != 0
1338 && NONJUMP_INSN_P (prev
)
1339 && sets_cc0_p (PATTERN (prev
))
1340 && GET_CODE (PATTERN (insn
)) == SET
1341 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1343 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1345 last_combined_insn
)) != 0)
1348 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1349 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1350 NULL
, &new_direct_jump_p
,
1351 last_combined_insn
)) != 0)
1355 /* Finally, see if any of the insns that this insn links to
1356 explicitly references CC0. If so, try this insn, that insn,
1357 and its predecessor if it sets CC0. */
1358 FOR_EACH_LOG_LINK (links
, insn
)
1359 if (NONJUMP_INSN_P (links
->insn
)
1360 && GET_CODE (PATTERN (links
->insn
)) == SET
1361 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1362 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1363 && NONJUMP_INSN_P (prev
)
1364 && sets_cc0_p (PATTERN (prev
))
1365 && (next
= try_combine (insn
, links
->insn
,
1366 prev
, NULL
, &new_direct_jump_p
,
1367 last_combined_insn
)) != 0)
1371 /* Try combining an insn with two different insns whose results it
1373 if (max_combine
>= 3)
1374 FOR_EACH_LOG_LINK (links
, insn
)
1375 for (nextlinks
= links
->next
; nextlinks
;
1376 nextlinks
= nextlinks
->next
)
1377 if ((next
= try_combine (insn
, links
->insn
,
1378 nextlinks
->insn
, NULL
,
1380 last_combined_insn
)) != 0)
1383 statistics_counter_event (cfun
, "three-insn combine", 1);
1387 /* Try four-instruction combinations. */
1388 if (max_combine
>= 4)
1389 FOR_EACH_LOG_LINK (links
, insn
)
1391 struct insn_link
*next1
;
1392 rtx_insn
*link
= links
->insn
;
1394 /* If the linked insn has been replaced by a note, then there
1395 is no point in pursuing this chain any further. */
1399 FOR_EACH_LOG_LINK (next1
, link
)
1401 rtx_insn
*link1
= next1
->insn
;
1404 /* I0 -> I1 -> I2 -> I3. */
1405 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1406 if ((next
= try_combine (insn
, link
, link1
,
1409 last_combined_insn
)) != 0)
1411 statistics_counter_event (cfun
, "four-insn combine", 1);
1414 /* I0, I1 -> I2, I2 -> I3. */
1415 for (nextlinks
= next1
->next
; nextlinks
;
1416 nextlinks
= nextlinks
->next
)
1417 if ((next
= try_combine (insn
, link
, link1
,
1420 last_combined_insn
)) != 0)
1422 statistics_counter_event (cfun
, "four-insn combine", 1);
1427 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1429 rtx_insn
*link1
= next1
->insn
;
1432 /* I0 -> I2; I1, I2 -> I3. */
1433 FOR_EACH_LOG_LINK (nextlinks
, link
)
1434 if ((next
= try_combine (insn
, link
, link1
,
1437 last_combined_insn
)) != 0)
1439 statistics_counter_event (cfun
, "four-insn combine", 1);
1442 /* I0 -> I1; I1, I2 -> I3. */
1443 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1444 if ((next
= try_combine (insn
, link
, link1
,
1447 last_combined_insn
)) != 0)
1449 statistics_counter_event (cfun
, "four-insn combine", 1);
1455 /* Try this insn with each REG_EQUAL note it links back to. */
1456 FOR_EACH_LOG_LINK (links
, insn
)
1459 rtx_insn
*temp
= links
->insn
;
1460 if ((set
= single_set (temp
)) != 0
1461 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1462 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1463 /* Avoid using a register that may already been marked
1464 dead by an earlier instruction. */
1465 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1466 && (GET_MODE (note
) == VOIDmode
1467 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1468 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1470 /* Temporarily replace the set's source with the
1471 contents of the REG_EQUAL note. The insn will
1472 be deleted or recognized by try_combine. */
1473 rtx orig
= SET_SRC (set
);
1474 SET_SRC (set
) = note
;
1476 i2mod_old_rhs
= copy_rtx (orig
);
1477 i2mod_new_rhs
= copy_rtx (note
);
1478 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1480 last_combined_insn
);
1484 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1487 SET_SRC (set
) = orig
;
1492 record_dead_and_set_regs (insn
);
1499 default_rtl_profile ();
1501 new_direct_jump_p
|= purge_all_dead_edges ();
1502 delete_noop_moves ();
1505 obstack_free (&insn_link_obstack
, NULL
);
1506 free (uid_log_links
);
1507 free (uid_insn_cost
);
1508 reg_stat
.release ();
1511 struct undo
*undo
, *next
;
1512 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1520 total_attempts
+= combine_attempts
;
1521 total_merges
+= combine_merges
;
1522 total_extras
+= combine_extras
;
1523 total_successes
+= combine_successes
;
1525 nonzero_sign_valid
= 0;
1526 rtl_hooks
= general_rtl_hooks
;
1528 /* Make recognizer allow volatile MEMs again. */
1531 return new_direct_jump_p
;
1534 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1537 init_reg_last (void)
1542 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1543 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1546 /* Set up any promoted values for incoming argument registers. */
1549 setup_incoming_promotions (rtx_insn
*first
)
1552 bool strictly_local
= false;
1554 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1555 arg
= DECL_CHAIN (arg
))
1557 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1559 machine_mode mode1
, mode2
, mode3
, mode4
;
1561 /* Only continue if the incoming argument is in a register. */
1565 /* Determine, if possible, whether all call sites of the current
1566 function lie within the current compilation unit. (This does
1567 take into account the exporting of a function via taking its
1568 address, and so forth.) */
1569 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1571 /* The mode and signedness of the argument before any promotions happen
1572 (equal to the mode of the pseudo holding it at that stage). */
1573 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1574 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1576 /* The mode and signedness of the argument after any source language and
1577 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1578 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1579 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1581 /* The mode and signedness of the argument as it is actually passed,
1582 see assign_parm_setup_reg in function.c. */
1583 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns1
,
1584 TREE_TYPE (cfun
->decl
), 0);
1586 /* The mode of the register in which the argument is being passed. */
1587 mode4
= GET_MODE (reg
);
1589 /* Eliminate sign extensions in the callee when:
1590 (a) A mode promotion has occurred; */
1593 /* (b) The mode of the register is the same as the mode of
1594 the argument as it is passed; */
1597 /* (c) There's no language level extension; */
1600 /* (c.1) All callers are from the current compilation unit. If that's
1601 the case we don't have to rely on an ABI, we only have to know
1602 what we're generating right now, and we know that we will do the
1603 mode1 to mode2 promotion with the given sign. */
1604 else if (!strictly_local
)
1606 /* (c.2) The combination of the two promotions is useful. This is
1607 true when the signs match, or if the first promotion is unsigned.
1608 In the later case, (sign_extend (zero_extend x)) is the same as
1609 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1615 /* Record that the value was promoted from mode1 to mode3,
1616 so that any sign extension at the head of the current
1617 function may be eliminated. */
1618 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1619 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1620 record_value_for_reg (reg
, first
, x
);
1624 /* Called via note_stores. If X is a pseudo that is narrower than
1625 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1627 If we are setting only a portion of X and we can't figure out what
1628 portion, assume all bits will be used since we don't know what will
1631 Similarly, set how many bits of X are known to be copies of the sign bit
1632 at all locations in the function. This is the smallest number implied
1636 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1638 rtx_insn
*insn
= (rtx_insn
*) data
;
1642 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1643 /* If this register is undefined at the start of the file, we can't
1644 say what its contents were. */
1645 && ! REGNO_REG_SET_P
1646 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1647 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1649 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1651 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1653 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1654 rsp
->sign_bit_copies
= 1;
1658 /* If this register is being initialized using itself, and the
1659 register is uninitialized in this basic block, and there are
1660 no LOG_LINKS which set the register, then part of the
1661 register is uninitialized. In that case we can't assume
1662 anything about the number of nonzero bits.
1664 ??? We could do better if we checked this in
1665 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1666 could avoid making assumptions about the insn which initially
1667 sets the register, while still using the information in other
1668 insns. We would have to be careful to check every insn
1669 involved in the combination. */
1672 && reg_referenced_p (x
, PATTERN (insn
))
1673 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1676 struct insn_link
*link
;
1678 FOR_EACH_LOG_LINK (link
, insn
)
1679 if (dead_or_set_p (link
->insn
, x
))
1683 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1684 rsp
->sign_bit_copies
= 1;
1689 /* If this is a complex assignment, see if we can convert it into a
1690 simple assignment. */
1691 set
= expand_field_assignment (set
);
1693 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1694 set what we know about X. */
1696 if (SET_DEST (set
) == x
1697 || (paradoxical_subreg_p (SET_DEST (set
))
1698 && SUBREG_REG (SET_DEST (set
)) == x
))
1700 rtx src
= SET_SRC (set
);
1702 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1703 /* If X is narrower than a word and SRC is a non-negative
1704 constant that would appear negative in the mode of X,
1705 sign-extend it for use in reg_stat[].nonzero_bits because some
1706 machines (maybe most) will actually do the sign-extension
1707 and this is the conservative approach.
1709 ??? For 2.5, try to tighten up the MD files in this regard
1710 instead of this kludge. */
1712 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1713 && CONST_INT_P (src
)
1715 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1716 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1719 /* Don't call nonzero_bits if it cannot change anything. */
1720 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1721 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1722 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1723 if (rsp
->sign_bit_copies
== 0
1724 || rsp
->sign_bit_copies
> num
)
1725 rsp
->sign_bit_copies
= num
;
1729 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1730 rsp
->sign_bit_copies
= 1;
1735 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1736 optionally insns that were previously combined into I3 or that will be
1737 combined into the merger of INSN and I3. The order is PRED, PRED2,
1738 INSN, SUCC, SUCC2, I3.
1740 Return 0 if the combination is not allowed for any reason.
1742 If the combination is allowed, *PDEST will be set to the single
1743 destination of INSN and *PSRC to the single source, and this function
1747 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1748 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1749 rtx
*pdest
, rtx
*psrc
)
1758 bool all_adjacent
= true;
1759 int (*is_volatile_p
) (const_rtx
);
1765 if (next_active_insn (succ2
) != i3
)
1766 all_adjacent
= false;
1767 if (next_active_insn (succ
) != succ2
)
1768 all_adjacent
= false;
1770 else if (next_active_insn (succ
) != i3
)
1771 all_adjacent
= false;
1772 if (next_active_insn (insn
) != succ
)
1773 all_adjacent
= false;
1775 else if (next_active_insn (insn
) != i3
)
1776 all_adjacent
= false;
1778 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1779 or a PARALLEL consisting of such a SET and CLOBBERs.
1781 If INSN has CLOBBER parallel parts, ignore them for our processing.
1782 By definition, these happen during the execution of the insn. When it
1783 is merged with another insn, all bets are off. If they are, in fact,
1784 needed and aren't also supplied in I3, they may be added by
1785 recog_for_combine. Otherwise, it won't match.
1787 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1790 Get the source and destination of INSN. If more than one, can't
1793 if (GET_CODE (PATTERN (insn
)) == SET
)
1794 set
= PATTERN (insn
);
1795 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1796 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1798 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1800 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1802 switch (GET_CODE (elt
))
1804 /* This is important to combine floating point insns
1805 for the SH4 port. */
1807 /* Combining an isolated USE doesn't make sense.
1808 We depend here on combinable_i3pat to reject them. */
1809 /* The code below this loop only verifies that the inputs of
1810 the SET in INSN do not change. We call reg_set_between_p
1811 to verify that the REG in the USE does not change between
1813 If the USE in INSN was for a pseudo register, the matching
1814 insn pattern will likely match any register; combining this
1815 with any other USE would only be safe if we knew that the
1816 used registers have identical values, or if there was
1817 something to tell them apart, e.g. different modes. For
1818 now, we forgo such complicated tests and simply disallow
1819 combining of USES of pseudo registers with any other USE. */
1820 if (REG_P (XEXP (elt
, 0))
1821 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1823 rtx i3pat
= PATTERN (i3
);
1824 int i
= XVECLEN (i3pat
, 0) - 1;
1825 unsigned int regno
= REGNO (XEXP (elt
, 0));
1829 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1831 if (GET_CODE (i3elt
) == USE
1832 && REG_P (XEXP (i3elt
, 0))
1833 && (REGNO (XEXP (i3elt
, 0)) == regno
1834 ? reg_set_between_p (XEXP (elt
, 0),
1835 PREV_INSN (insn
), i3
)
1836 : regno
>= FIRST_PSEUDO_REGISTER
))
1843 /* We can ignore CLOBBERs. */
1848 /* Ignore SETs whose result isn't used but not those that
1849 have side-effects. */
1850 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1851 && insn_nothrow_p (insn
)
1852 && !side_effects_p (elt
))
1855 /* If we have already found a SET, this is a second one and
1856 so we cannot combine with this insn. */
1864 /* Anything else means we can't combine. */
1870 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1871 so don't do anything with it. */
1872 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1881 /* The simplification in expand_field_assignment may call back to
1882 get_last_value, so set safe guard here. */
1883 subst_low_luid
= DF_INSN_LUID (insn
);
1885 set
= expand_field_assignment (set
);
1886 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1888 /* Don't eliminate a store in the stack pointer. */
1889 if (dest
== stack_pointer_rtx
1890 /* Don't combine with an insn that sets a register to itself if it has
1891 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1892 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1893 /* Can't merge an ASM_OPERANDS. */
1894 || GET_CODE (src
) == ASM_OPERANDS
1895 /* Can't merge a function call. */
1896 || GET_CODE (src
) == CALL
1897 /* Don't eliminate a function call argument. */
1899 && (find_reg_fusage (i3
, USE
, dest
)
1901 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1902 && global_regs
[REGNO (dest
)])))
1903 /* Don't substitute into an incremented register. */
1904 || FIND_REG_INC_NOTE (i3
, dest
)
1905 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1906 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1907 /* Don't substitute into a non-local goto, this confuses CFG. */
1908 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1909 /* Make sure that DEST is not used after SUCC but before I3. */
1912 && (reg_used_between_p (dest
, succ2
, i3
)
1913 || reg_used_between_p (dest
, succ
, succ2
)))
1914 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1915 /* Make sure that the value that is to be substituted for the register
1916 does not use any registers whose values alter in between. However,
1917 If the insns are adjacent, a use can't cross a set even though we
1918 think it might (this can happen for a sequence of insns each setting
1919 the same destination; last_set of that register might point to
1920 a NOTE). If INSN has a REG_EQUIV note, the register is always
1921 equivalent to the memory so the substitution is valid even if there
1922 are intervening stores. Also, don't move a volatile asm or
1923 UNSPEC_VOLATILE across any other insns. */
1926 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1927 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1928 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1929 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1930 /* Don't combine across a CALL_INSN, because that would possibly
1931 change whether the life span of some REGs crosses calls or not,
1932 and it is a pain to update that information.
1933 Exception: if source is a constant, moving it later can't hurt.
1934 Accept that as a special case. */
1935 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1938 /* DEST must either be a REG or CC0. */
1941 /* If register alignment is being enforced for multi-word items in all
1942 cases except for parameters, it is possible to have a register copy
1943 insn referencing a hard register that is not allowed to contain the
1944 mode being copied and which would not be valid as an operand of most
1945 insns. Eliminate this problem by not combining with such an insn.
1947 Also, on some machines we don't want to extend the life of a hard
1951 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1952 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1953 /* Don't extend the life of a hard register unless it is
1954 user variable (if we have few registers) or it can't
1955 fit into the desired register (meaning something special
1957 Also avoid substituting a return register into I3, because
1958 reload can't handle a conflict with constraints of other
1960 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1961 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1964 else if (GET_CODE (dest
) != CC0
)
1968 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1969 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1970 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1972 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1974 /* If the clobber represents an earlyclobber operand, we must not
1975 substitute an expression containing the clobbered register.
1976 As we do not analyze the constraint strings here, we have to
1977 make the conservative assumption. However, if the register is
1978 a fixed hard reg, the clobber cannot represent any operand;
1979 we leave it up to the machine description to either accept or
1980 reject use-and-clobber patterns. */
1982 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1983 || !fixed_regs
[REGNO (reg
)])
1984 if (reg_overlap_mentioned_p (reg
, src
))
1988 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1989 or not), reject, unless nothing volatile comes between it and I3 */
1991 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1993 /* Make sure neither succ nor succ2 contains a volatile reference. */
1994 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1996 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1998 /* We'll check insns between INSN and I3 below. */
2001 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2002 to be an explicit register variable, and was chosen for a reason. */
2004 if (GET_CODE (src
) == ASM_OPERANDS
2005 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2008 /* If INSN contains volatile references (specifically volatile MEMs),
2009 we cannot combine across any other volatile references.
2010 Even if INSN doesn't contain volatile references, any intervening
2011 volatile insn might affect machine state. */
2013 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2017 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2018 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2021 /* If INSN contains an autoincrement or autodecrement, make sure that
2022 register is not used between there and I3, and not already used in
2023 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2024 Also insist that I3 not be a jump; if it were one
2025 and the incremented register were spilled, we would lose. */
2028 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2029 if (REG_NOTE_KIND (link
) == REG_INC
2031 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2032 || (pred
!= NULL_RTX
2033 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2034 || (pred2
!= NULL_RTX
2035 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2036 || (succ
!= NULL_RTX
2037 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2038 || (succ2
!= NULL_RTX
2039 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2040 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2045 /* Don't combine an insn that follows a CC0-setting insn.
2046 An insn that uses CC0 must not be separated from the one that sets it.
2047 We do, however, allow I2 to follow a CC0-setting insn if that insn
2048 is passed as I1; in that case it will be deleted also.
2049 We also allow combining in this case if all the insns are adjacent
2050 because that would leave the two CC0 insns adjacent as well.
2051 It would be more logical to test whether CC0 occurs inside I1 or I2,
2052 but that would be much slower, and this ought to be equivalent. */
2054 p
= prev_nonnote_insn (insn
);
2055 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2060 /* If we get here, we have passed all the tests and the combination is
2069 /* LOC is the location within I3 that contains its pattern or the component
2070 of a PARALLEL of the pattern. We validate that it is valid for combining.
2072 One problem is if I3 modifies its output, as opposed to replacing it
2073 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2074 doing so would produce an insn that is not equivalent to the original insns.
2078 (set (reg:DI 101) (reg:DI 100))
2079 (set (subreg:SI (reg:DI 101) 0) <foo>)
2081 This is NOT equivalent to:
2083 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2084 (set (reg:DI 101) (reg:DI 100))])
2086 Not only does this modify 100 (in which case it might still be valid
2087 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2089 We can also run into a problem if I2 sets a register that I1
2090 uses and I1 gets directly substituted into I3 (not via I2). In that
2091 case, we would be getting the wrong value of I2DEST into I3, so we
2092 must reject the combination. This case occurs when I2 and I1 both
2093 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2094 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2095 of a SET must prevent combination from occurring. The same situation
2096 can occur for I0, in which case I0_NOT_IN_SRC is set.
2098 Before doing the above check, we first try to expand a field assignment
2099 into a set of logical operations.
2101 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2102 we place a register that is both set and used within I3. If more than one
2103 such register is detected, we fail.
2105 Return 1 if the combination is valid, zero otherwise. */
2108 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2109 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2113 if (GET_CODE (x
) == SET
)
2116 rtx dest
= SET_DEST (set
);
2117 rtx src
= SET_SRC (set
);
2118 rtx inner_dest
= dest
;
2121 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2122 || GET_CODE (inner_dest
) == SUBREG
2123 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2124 inner_dest
= XEXP (inner_dest
, 0);
2126 /* Check for the case where I3 modifies its output, as discussed
2127 above. We don't want to prevent pseudos from being combined
2128 into the address of a MEM, so only prevent the combination if
2129 i1 or i2 set the same MEM. */
2130 if ((inner_dest
!= dest
&&
2131 (!MEM_P (inner_dest
)
2132 || rtx_equal_p (i2dest
, inner_dest
)
2133 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2134 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2135 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2136 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2137 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2139 /* This is the same test done in can_combine_p except we can't test
2140 all_adjacent; we don't have to, since this instruction will stay
2141 in place, thus we are not considering increasing the lifetime of
2144 Also, if this insn sets a function argument, combining it with
2145 something that might need a spill could clobber a previous
2146 function argument; the all_adjacent test in can_combine_p also
2147 checks this; here, we do a more specific test for this case. */
2149 || (REG_P (inner_dest
)
2150 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2151 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2152 GET_MODE (inner_dest
))))
2153 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2154 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2157 /* If DEST is used in I3, it is being killed in this insn, so
2158 record that for later. We have to consider paradoxical
2159 subregs here, since they kill the whole register, but we
2160 ignore partial subregs, STRICT_LOW_PART, etc.
2161 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2162 STACK_POINTER_REGNUM, since these are always considered to be
2163 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2165 if (GET_CODE (subdest
) == SUBREG
2166 && (GET_MODE_SIZE (GET_MODE (subdest
))
2167 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2168 subdest
= SUBREG_REG (subdest
);
2171 && reg_referenced_p (subdest
, PATTERN (i3
))
2172 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2173 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2174 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2176 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2177 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2178 || ! fixed_regs
[REGNO (subdest
)])
2180 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2182 if (*pi3dest_killed
)
2185 *pi3dest_killed
= subdest
;
2189 else if (GET_CODE (x
) == PARALLEL
)
2193 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2194 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2195 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2202 /* Return 1 if X is an arithmetic expression that contains a multiplication
2203 and division. We don't count multiplications by powers of two here. */
2206 contains_muldiv (rtx x
)
2208 switch (GET_CODE (x
))
2210 case MOD
: case DIV
: case UMOD
: case UDIV
:
2214 return ! (CONST_INT_P (XEXP (x
, 1))
2215 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2218 return contains_muldiv (XEXP (x
, 0))
2219 || contains_muldiv (XEXP (x
, 1));
2222 return contains_muldiv (XEXP (x
, 0));
2228 /* Determine whether INSN can be used in a combination. Return nonzero if
2229 not. This is used in try_combine to detect early some cases where we
2230 can't perform combinations. */
2233 cant_combine_insn_p (rtx_insn
*insn
)
2238 /* If this isn't really an insn, we can't do anything.
2239 This can occur when flow deletes an insn that it has merged into an
2240 auto-increment address. */
2241 if (! INSN_P (insn
))
2244 /* Never combine loads and stores involving hard regs that are likely
2245 to be spilled. The register allocator can usually handle such
2246 reg-reg moves by tying. If we allow the combiner to make
2247 substitutions of likely-spilled regs, reload might die.
2248 As an exception, we allow combinations involving fixed regs; these are
2249 not available to the register allocator so there's no risk involved. */
2251 set
= single_set (insn
);
2254 src
= SET_SRC (set
);
2255 dest
= SET_DEST (set
);
2256 if (GET_CODE (src
) == SUBREG
)
2257 src
= SUBREG_REG (src
);
2258 if (GET_CODE (dest
) == SUBREG
)
2259 dest
= SUBREG_REG (dest
);
2260 if (REG_P (src
) && REG_P (dest
)
2261 && ((HARD_REGISTER_P (src
)
2262 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2263 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2264 || (HARD_REGISTER_P (dest
)
2265 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2266 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2272 struct likely_spilled_retval_info
2274 unsigned regno
, nregs
;
2278 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2279 hard registers that are known to be written to / clobbered in full. */
2281 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2283 struct likely_spilled_retval_info
*const info
=
2284 (struct likely_spilled_retval_info
*) data
;
2285 unsigned regno
, nregs
;
2288 if (!REG_P (XEXP (set
, 0)))
2291 if (regno
>= info
->regno
+ info
->nregs
)
2293 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2294 if (regno
+ nregs
<= info
->regno
)
2296 new_mask
= (2U << (nregs
- 1)) - 1;
2297 if (regno
< info
->regno
)
2298 new_mask
>>= info
->regno
- regno
;
2300 new_mask
<<= regno
- info
->regno
;
2301 info
->mask
&= ~new_mask
;
2304 /* Return nonzero iff part of the return value is live during INSN, and
2305 it is likely spilled. This can happen when more than one insn is needed
2306 to copy the return value, e.g. when we consider to combine into the
2307 second copy insn for a complex value. */
2310 likely_spilled_retval_p (rtx_insn
*insn
)
2312 rtx_insn
*use
= BB_END (this_basic_block
);
2315 unsigned regno
, nregs
;
2316 /* We assume here that no machine mode needs more than
2317 32 hard registers when the value overlaps with a register
2318 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2320 struct likely_spilled_retval_info info
;
2322 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2324 reg
= XEXP (PATTERN (use
), 0);
2325 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2327 regno
= REGNO (reg
);
2328 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2331 mask
= (2U << (nregs
- 1)) - 1;
2333 /* Disregard parts of the return value that are set later. */
2337 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2339 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2342 /* Check if any of the (probably) live return value registers is
2347 if ((mask
& 1 << nregs
)
2348 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2354 /* Adjust INSN after we made a change to its destination.
2356 Changing the destination can invalidate notes that say something about
2357 the results of the insn and a LOG_LINK pointing to the insn. */
2360 adjust_for_new_dest (rtx_insn
*insn
)
2362 /* For notes, be conservative and simply remove them. */
2363 remove_reg_equal_equiv_notes (insn
);
2365 /* The new insn will have a destination that was previously the destination
2366 of an insn just above it. Call distribute_links to make a LOG_LINK from
2367 the next use of that destination. */
2369 rtx set
= single_set (insn
);
2372 rtx reg
= SET_DEST (set
);
2374 while (GET_CODE (reg
) == ZERO_EXTRACT
2375 || GET_CODE (reg
) == STRICT_LOW_PART
2376 || GET_CODE (reg
) == SUBREG
)
2377 reg
= XEXP (reg
, 0);
2378 gcc_assert (REG_P (reg
));
2380 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2382 df_insn_rescan (insn
);
2385 /* Return TRUE if combine can reuse reg X in mode MODE.
2386 ADDED_SETS is nonzero if the original set is still required. */
2388 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2396 /* Allow hard registers if the new mode is legal, and occupies no more
2397 registers than the old mode. */
2398 if (regno
< FIRST_PSEUDO_REGISTER
)
2399 return (HARD_REGNO_MODE_OK (regno
, mode
)
2400 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2401 >= hard_regno_nregs
[regno
][mode
]));
2403 /* Or a pseudo that is only used once. */
2404 return (REG_N_SETS (regno
) == 1 && !added_sets
2405 && !REG_USERVAR_P (x
));
2409 /* Check whether X, the destination of a set, refers to part of
2410 the register specified by REG. */
2413 reg_subword_p (rtx x
, rtx reg
)
2415 /* Check that reg is an integer mode register. */
2416 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2419 if (GET_CODE (x
) == STRICT_LOW_PART
2420 || GET_CODE (x
) == ZERO_EXTRACT
)
2423 return GET_CODE (x
) == SUBREG
2424 && SUBREG_REG (x
) == reg
2425 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2428 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2429 Note that the INSN should be deleted *after* removing dead edges, so
2430 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2431 but not for a (set (pc) (label_ref FOO)). */
2434 update_cfg_for_uncondjump (rtx_insn
*insn
)
2436 basic_block bb
= BLOCK_FOR_INSN (insn
);
2437 gcc_assert (BB_END (bb
) == insn
);
2439 purge_dead_edges (bb
);
2442 if (EDGE_COUNT (bb
->succs
) == 1)
2446 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2448 /* Remove barriers from the footer if there are any. */
2449 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2450 if (BARRIER_P (insn
))
2452 if (PREV_INSN (insn
))
2453 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2455 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2456 if (NEXT_INSN (insn
))
2457 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2459 else if (LABEL_P (insn
))
2464 /* Return whether INSN is a PARALLEL of exactly N register SETs followed
2465 by an arbitrary number of CLOBBERs. */
2467 is_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2469 rtx pat
= PATTERN (insn
);
2471 if (GET_CODE (pat
) != PARALLEL
)
2474 int len
= XVECLEN (pat
, 0);
2479 for (i
= 0; i
< n
; i
++)
2480 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2481 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2483 for ( ; i
< len
; i
++)
2484 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
2490 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2491 CLOBBERs), can be split into individual SETs in that order, without
2492 changing semantics. */
2494 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2496 if (!insn_nothrow_p (insn
))
2499 rtx pat
= PATTERN (insn
);
2502 for (i
= 0; i
< n
; i
++)
2504 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2507 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2509 for (j
= i
+ 1; j
< n
; j
++)
2510 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2517 /* Try to combine the insns I0, I1 and I2 into I3.
2518 Here I0, I1 and I2 appear earlier than I3.
2519 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2522 If we are combining more than two insns and the resulting insn is not
2523 recognized, try splitting it into two insns. If that happens, I2 and I3
2524 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2525 Otherwise, I0, I1 and I2 are pseudo-deleted.
2527 Return 0 if the combination does not work. Then nothing is changed.
2528 If we did the combination, return the insn at which combine should
2531 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2532 new direct jump instruction.
2534 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2535 been I3 passed to an earlier try_combine within the same basic
2539 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2540 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2542 /* New patterns for I3 and I2, respectively. */
2543 rtx newpat
, newi2pat
= 0;
2544 rtvec newpat_vec_with_clobbers
= 0;
2545 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2546 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2548 int added_sets_0
, added_sets_1
, added_sets_2
;
2549 /* Total number of SETs to put into I3. */
2551 /* Nonzero if I2's or I1's body now appears in I3. */
2552 int i2_is_used
= 0, i1_is_used
= 0;
2553 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2554 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2555 /* Contains I3 if the destination of I3 is used in its source, which means
2556 that the old life of I3 is being killed. If that usage is placed into
2557 I2 and not in I3, a REG_DEAD note must be made. */
2558 rtx i3dest_killed
= 0;
2559 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2560 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2561 /* Copy of SET_SRC of I1 and I0, if needed. */
2562 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2563 /* Set if I2DEST was reused as a scratch register. */
2564 bool i2scratch
= false;
2565 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2566 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2567 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2568 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2569 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2570 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2571 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2572 /* Notes that must be added to REG_NOTES in I3 and I2. */
2573 rtx new_i3_notes
, new_i2_notes
;
2574 /* Notes that we substituted I3 into I2 instead of the normal case. */
2575 int i3_subst_into_i2
= 0;
2576 /* Notes that I1, I2 or I3 is a MULT operation. */
2579 int changed_i3_dest
= 0;
2582 rtx_insn
*temp_insn
;
2584 struct insn_link
*link
;
2586 rtx new_other_notes
;
2589 /* Only try four-insn combinations when there's high likelihood of
2590 success. Look for simple insns, such as loads of constants or
2591 binary operations involving a constant. */
2598 if (!flag_expensive_optimizations
)
2601 for (i
= 0; i
< 4; i
++)
2603 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2604 rtx set
= single_set (insn
);
2608 src
= SET_SRC (set
);
2609 if (CONSTANT_P (src
))
2614 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2616 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2617 || GET_CODE (src
) == LSHIFTRT
)
2620 if (ngood
< 2 && nshift
< 2)
2624 /* Exit early if one of the insns involved can't be used for
2627 || (i1
&& CALL_P (i1
))
2628 || (i0
&& CALL_P (i0
))
2629 || cant_combine_insn_p (i3
)
2630 || cant_combine_insn_p (i2
)
2631 || (i1
&& cant_combine_insn_p (i1
))
2632 || (i0
&& cant_combine_insn_p (i0
))
2633 || likely_spilled_retval_p (i3
))
2637 undobuf
.other_insn
= 0;
2639 /* Reset the hard register usage information. */
2640 CLEAR_HARD_REG_SET (newpat_used_regs
);
2642 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2645 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2646 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2648 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2649 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2651 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2652 INSN_UID (i2
), INSN_UID (i3
));
2655 /* If multiple insns feed into one of I2 or I3, they can be in any
2656 order. To simplify the code below, reorder them in sequence. */
2657 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2658 temp_insn
= i2
, i2
= i0
, i0
= temp_insn
;
2659 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2660 temp_insn
= i1
, i1
= i0
, i0
= temp_insn
;
2661 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2662 temp_insn
= i1
, i1
= i2
, i2
= temp_insn
;
2664 added_links_insn
= 0;
2666 /* First check for one important special case that the code below will
2667 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2668 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2669 we may be able to replace that destination with the destination of I3.
2670 This occurs in the common code where we compute both a quotient and
2671 remainder into a structure, in which case we want to do the computation
2672 directly into the structure to avoid register-register copies.
2674 Note that this case handles both multiple sets in I2 and also cases
2675 where I2 has a number of CLOBBERs inside the PARALLEL.
2677 We make very conservative checks below and only try to handle the
2678 most common cases of this. For example, we only handle the case
2679 where I2 and I3 are adjacent to avoid making difficult register
2682 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2683 && REG_P (SET_SRC (PATTERN (i3
)))
2684 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2685 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2686 && GET_CODE (PATTERN (i2
)) == PARALLEL
2687 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2688 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2689 below would need to check what is inside (and reg_overlap_mentioned_p
2690 doesn't support those codes anyway). Don't allow those destinations;
2691 the resulting insn isn't likely to be recognized anyway. */
2692 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2693 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2694 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2695 SET_DEST (PATTERN (i3
)))
2696 && next_active_insn (i2
) == i3
)
2698 rtx p2
= PATTERN (i2
);
2700 /* Make sure that the destination of I3,
2701 which we are going to substitute into one output of I2,
2702 is not used within another output of I2. We must avoid making this:
2703 (parallel [(set (mem (reg 69)) ...)
2704 (set (reg 69) ...)])
2705 which is not well-defined as to order of actions.
2706 (Besides, reload can't handle output reloads for this.)
2708 The problem can also happen if the dest of I3 is a memory ref,
2709 if another dest in I2 is an indirect memory ref. */
2710 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2711 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2712 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2713 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2714 SET_DEST (XVECEXP (p2
, 0, i
))))
2717 if (i
== XVECLEN (p2
, 0))
2718 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2719 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2720 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2725 subst_low_luid
= DF_INSN_LUID (i2
);
2727 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2728 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2729 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2730 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2732 /* Replace the dest in I2 with our dest and make the resulting
2733 insn the new pattern for I3. Then skip to where we validate
2734 the pattern. Everything was set up above. */
2735 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2737 i3_subst_into_i2
= 1;
2738 goto validate_replacement
;
2742 /* If I2 is setting a pseudo to a constant and I3 is setting some
2743 sub-part of it to another constant, merge them by making a new
2746 && (temp_expr
= single_set (i2
)) != 0
2747 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2748 && GET_CODE (PATTERN (i3
)) == SET
2749 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2750 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2752 rtx dest
= SET_DEST (PATTERN (i3
));
2756 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2758 if (CONST_INT_P (XEXP (dest
, 1))
2759 && CONST_INT_P (XEXP (dest
, 2)))
2761 width
= INTVAL (XEXP (dest
, 1));
2762 offset
= INTVAL (XEXP (dest
, 2));
2763 dest
= XEXP (dest
, 0);
2764 if (BITS_BIG_ENDIAN
)
2765 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2770 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2771 dest
= XEXP (dest
, 0);
2772 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2778 /* If this is the low part, we're done. */
2779 if (subreg_lowpart_p (dest
))
2781 /* Handle the case where inner is twice the size of outer. */
2782 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2783 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2784 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2785 /* Otherwise give up for now. */
2792 rtx inner
= SET_SRC (PATTERN (i3
));
2793 rtx outer
= SET_SRC (temp_expr
);
2796 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2797 std::make_pair (inner
, GET_MODE (dest
)),
2802 subst_low_luid
= DF_INSN_LUID (i2
);
2803 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2804 i2dest
= SET_DEST (temp_expr
);
2805 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2807 /* Replace the source in I2 with the new constant and make the
2808 resulting insn the new pattern for I3. Then skip to where we
2809 validate the pattern. Everything was set up above. */
2810 SUBST (SET_SRC (temp_expr
),
2811 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2813 newpat
= PATTERN (i2
);
2815 /* The dest of I3 has been replaced with the dest of I2. */
2816 changed_i3_dest
= 1;
2817 goto validate_replacement
;
2822 /* If we have no I1 and I2 looks like:
2823 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2825 make up a dummy I1 that is
2828 (set (reg:CC X) (compare:CC Y (const_int 0)))
2830 (We can ignore any trailing CLOBBERs.)
2832 This undoes a previous combination and allows us to match a branch-and-
2836 && is_parallel_of_n_reg_sets (i2
, 2)
2837 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2839 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2840 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2841 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2842 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2843 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2844 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2846 /* We make I1 with the same INSN_UID as I2. This gives it
2847 the same DF_INSN_LUID for value tracking. Our fake I1 will
2848 never appear in the insn stream so giving it the same INSN_UID
2849 as I2 will not cause a problem. */
2851 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2852 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2854 INSN_UID (i1
) = INSN_UID (i2
);
2856 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2857 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2858 SET_DEST (PATTERN (i1
)));
2859 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2860 SUBST_LINK (LOG_LINKS (i2
),
2861 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2864 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2865 make those two SETs separate I1 and I2 insns, and make an I0 that is
2868 && is_parallel_of_n_reg_sets (i2
, 2)
2869 && can_split_parallel_of_n_reg_sets (i2
, 2)
2870 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2871 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2873 /* If there is no I1, there is no I0 either. */
2876 /* We make I1 with the same INSN_UID as I2. This gives it
2877 the same DF_INSN_LUID for value tracking. Our fake I1 will
2878 never appear in the insn stream so giving it the same INSN_UID
2879 as I2 will not cause a problem. */
2881 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2882 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2884 INSN_UID (i1
) = INSN_UID (i2
);
2886 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2890 /* Verify that I2 and I1 are valid for combining. */
2891 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2892 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2894 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2901 /* Record whether I2DEST is used in I2SRC and similarly for the other
2902 cases. Knowing this will help in register status updating below. */
2903 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2904 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2905 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2906 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2907 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2908 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2909 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2910 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2911 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2913 /* For the earlier insns, determine which of the subsequent ones they
2915 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2916 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2917 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2918 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2919 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2921 /* Ensure that I3's pattern can be the destination of combines. */
2922 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2923 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2924 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2925 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2932 /* See if any of the insns is a MULT operation. Unless one is, we will
2933 reject a combination that is, since it must be slower. Be conservative
2935 if (GET_CODE (i2src
) == MULT
2936 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2937 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2938 || (GET_CODE (PATTERN (i3
)) == SET
2939 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2942 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2943 We used to do this EXCEPT in one case: I3 has a post-inc in an
2944 output operand. However, that exception can give rise to insns like
2946 which is a famous insn on the PDP-11 where the value of r3 used as the
2947 source was model-dependent. Avoid this sort of thing. */
2950 if (!(GET_CODE (PATTERN (i3
)) == SET
2951 && REG_P (SET_SRC (PATTERN (i3
)))
2952 && MEM_P (SET_DEST (PATTERN (i3
)))
2953 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2954 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2955 /* It's not the exception. */
2960 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2961 if (REG_NOTE_KIND (link
) == REG_INC
2962 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2964 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2972 /* See if the SETs in I1 or I2 need to be kept around in the merged
2973 instruction: whenever the value set there is still needed past I3.
2974 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2976 For the SET in I1, we have two cases: if I1 and I2 independently feed
2977 into I3, the set in I1 needs to be kept around unless I1DEST dies
2978 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2979 in I1 needs to be kept around unless I1DEST dies or is set in either
2980 I2 or I3. The same considerations apply to I0. */
2982 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2985 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2986 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2991 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2992 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
2993 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
2994 && dead_or_set_p (i2
, i0dest
)));
2998 /* We are about to copy insns for the case where they need to be kept
2999 around. Check that they can be copied in the merged instruction. */
3001 if (targetm
.cannot_copy_insn_p
3002 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3003 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3004 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3010 /* If the set in I2 needs to be kept around, we must make a copy of
3011 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3012 PATTERN (I2), we are only substituting for the original I1DEST, not into
3013 an already-substituted copy. This also prevents making self-referential
3014 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3019 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3020 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
3022 i2pat
= copy_rtx (PATTERN (i2
));
3027 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3028 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
3030 i1pat
= copy_rtx (PATTERN (i1
));
3035 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3036 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
3038 i0pat
= copy_rtx (PATTERN (i0
));
3043 /* Substitute in the latest insn for the regs set by the earlier ones. */
3045 maxreg
= max_reg_num ();
3050 /* Many machines that don't use CC0 have insns that can both perform an
3051 arithmetic operation and set the condition code. These operations will
3052 be represented as a PARALLEL with the first element of the vector
3053 being a COMPARE of an arithmetic operation with the constant zero.
3054 The second element of the vector will set some pseudo to the result
3055 of the same arithmetic operation. If we simplify the COMPARE, we won't
3056 match such a pattern and so will generate an extra insn. Here we test
3057 for this case, where both the comparison and the operation result are
3058 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3059 I2SRC. Later we will make the PARALLEL that contains I2. */
3061 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3062 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3063 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3064 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3067 rtx
*cc_use_loc
= NULL
;
3068 rtx_insn
*cc_use_insn
= NULL
;
3069 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3070 machine_mode compare_mode
, orig_compare_mode
;
3071 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3073 newpat
= PATTERN (i3
);
3074 newpat_dest
= SET_DEST (newpat
);
3075 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3077 if (undobuf
.other_insn
== 0
3078 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3081 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3082 compare_code
= simplify_compare_const (compare_code
,
3083 GET_MODE (i2dest
), op0
, &op1
);
3084 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3087 /* Do the rest only if op1 is const0_rtx, which may be the
3088 result of simplification. */
3089 if (op1
== const0_rtx
)
3091 /* If a single use of the CC is found, prepare to modify it
3092 when SELECT_CC_MODE returns a new CC-class mode, or when
3093 the above simplify_compare_const() returned a new comparison
3094 operator. undobuf.other_insn is assigned the CC use insn
3095 when modifying it. */
3098 #ifdef SELECT_CC_MODE
3099 machine_mode new_mode
3100 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3101 if (new_mode
!= orig_compare_mode
3102 && can_change_dest_mode (SET_DEST (newpat
),
3103 added_sets_2
, new_mode
))
3105 unsigned int regno
= REGNO (newpat_dest
);
3106 compare_mode
= new_mode
;
3107 if (regno
< FIRST_PSEUDO_REGISTER
)
3108 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3111 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3112 newpat_dest
= regno_reg_rtx
[regno
];
3116 /* Cases for modifying the CC-using comparison. */
3117 if (compare_code
!= orig_compare_code
3118 /* ??? Do we need to verify the zero rtx? */
3119 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3121 /* Replace cc_use_loc with entire new RTX. */
3123 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3124 newpat_dest
, const0_rtx
));
3125 undobuf
.other_insn
= cc_use_insn
;
3127 else if (compare_mode
!= orig_compare_mode
)
3129 /* Just replace the CC reg with a new mode. */
3130 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3131 undobuf
.other_insn
= cc_use_insn
;
3135 /* Now we modify the current newpat:
3136 First, SET_DEST(newpat) is updated if the CC mode has been
3137 altered. For targets without SELECT_CC_MODE, this should be
3139 if (compare_mode
!= orig_compare_mode
)
3140 SUBST (SET_DEST (newpat
), newpat_dest
);
3141 /* This is always done to propagate i2src into newpat. */
3142 SUBST (SET_SRC (newpat
),
3143 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3144 /* Create new version of i2pat if needed; the below PARALLEL
3145 creation needs this to work correctly. */
3146 if (! rtx_equal_p (i2src
, op0
))
3147 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3153 if (i2_is_used
== 0)
3155 /* It is possible that the source of I2 or I1 may be performing
3156 an unneeded operation, such as a ZERO_EXTEND of something
3157 that is known to have the high part zero. Handle that case
3158 by letting subst look at the inner insns.
3160 Another way to do this would be to have a function that tries
3161 to simplify a single insn instead of merging two or more
3162 insns. We don't do this because of the potential of infinite
3163 loops and because of the potential extra memory required.
3164 However, doing it the way we are is a bit of a kludge and
3165 doesn't catch all cases.
3167 But only do this if -fexpensive-optimizations since it slows
3168 things down and doesn't usually win.
3170 This is not done in the COMPARE case above because the
3171 unmodified I2PAT is used in the PARALLEL and so a pattern
3172 with a modified I2SRC would not match. */
3174 if (flag_expensive_optimizations
)
3176 /* Pass pc_rtx so no substitutions are done, just
3180 subst_low_luid
= DF_INSN_LUID (i1
);
3181 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3184 subst_low_luid
= DF_INSN_LUID (i2
);
3185 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3188 n_occurrences
= 0; /* `subst' counts here */
3189 subst_low_luid
= DF_INSN_LUID (i2
);
3191 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3192 copy of I2SRC each time we substitute it, in order to avoid creating
3193 self-referential RTL when we will be substituting I1SRC for I1DEST
3194 later. Likewise if I0 feeds into I2, either directly or indirectly
3195 through I1, and I0DEST is in I0SRC. */
3196 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3197 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3198 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3199 && i0dest_in_i0src
));
3202 /* Record whether I2's body now appears within I3's body. */
3203 i2_is_used
= n_occurrences
;
3206 /* If we already got a failure, don't try to do more. Otherwise, try to
3207 substitute I1 if we have it. */
3209 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3211 /* Check that an autoincrement side-effect on I1 has not been lost.
3212 This happens if I1DEST is mentioned in I2 and dies there, and
3213 has disappeared from the new pattern. */
3214 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3216 && dead_or_set_p (i2
, i1dest
)
3217 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3218 /* Before we can do this substitution, we must redo the test done
3219 above (see detailed comments there) that ensures I1DEST isn't
3220 mentioned in any SETs in NEWPAT that are field assignments. */
3221 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3229 subst_low_luid
= DF_INSN_LUID (i1
);
3231 /* If the following substitution will modify I1SRC, make a copy of it
3232 for the case where it is substituted for I1DEST in I2PAT later. */
3233 if (added_sets_2
&& i1_feeds_i2_n
)
3234 i1src_copy
= copy_rtx (i1src
);
3236 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3237 copy of I1SRC each time we substitute it, in order to avoid creating
3238 self-referential RTL when we will be substituting I0SRC for I0DEST
3240 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3241 i0_feeds_i1_n
&& i0dest_in_i0src
);
3244 /* Record whether I1's body now appears within I3's body. */
3245 i1_is_used
= n_occurrences
;
3248 /* Likewise for I0 if we have it. */
3250 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3252 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3253 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3254 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3255 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3256 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3263 /* If the following substitution will modify I0SRC, make a copy of it
3264 for the case where it is substituted for I0DEST in I1PAT later. */
3265 if (added_sets_1
&& i0_feeds_i1_n
)
3266 i0src_copy
= copy_rtx (i0src
);
3267 /* And a copy for I0DEST in I2PAT substitution. */
3268 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3269 || (i0_feeds_i2_n
)))
3270 i0src_copy2
= copy_rtx (i0src
);
3273 subst_low_luid
= DF_INSN_LUID (i0
);
3274 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3278 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3279 to count all the ways that I2SRC and I1SRC can be used. */
3280 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3281 && i2_is_used
+ added_sets_2
> 1)
3282 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3283 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3285 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3286 && (n_occurrences
+ added_sets_0
3287 + (added_sets_1
&& i0_feeds_i1_n
)
3288 + (added_sets_2
&& i0_feeds_i2_n
)
3290 /* Fail if we tried to make a new register. */
3291 || max_reg_num () != maxreg
3292 /* Fail if we couldn't do something and have a CLOBBER. */
3293 || GET_CODE (newpat
) == CLOBBER
3294 /* Fail if this new pattern is a MULT and we didn't have one before
3295 at the outer level. */
3296 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3303 /* If the actions of the earlier insns must be kept
3304 in addition to substituting them into the latest one,
3305 we must make a new PARALLEL for the latest insn
3306 to hold additional the SETs. */
3308 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3310 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3313 if (GET_CODE (newpat
) == PARALLEL
)
3315 rtvec old
= XVEC (newpat
, 0);
3316 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3317 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3318 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3319 sizeof (old
->elem
[0]) * old
->num_elem
);
3324 total_sets
= 1 + extra_sets
;
3325 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3326 XVECEXP (newpat
, 0, 0) = old
;
3330 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3336 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3338 XVECEXP (newpat
, 0, --total_sets
) = t
;
3344 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3345 i0_feeds_i1_n
&& i0dest_in_i0src
);
3346 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3347 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3349 XVECEXP (newpat
, 0, --total_sets
) = t
;
3353 validate_replacement
:
3355 /* Note which hard regs this insn has as inputs. */
3356 mark_used_regs_combine (newpat
);
3358 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3359 consider splitting this pattern, we might need these clobbers. */
3360 if (i1
&& GET_CODE (newpat
) == PARALLEL
3361 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3363 int len
= XVECLEN (newpat
, 0);
3365 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3366 for (i
= 0; i
< len
; i
++)
3367 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3370 /* We have recognized nothing yet. */
3371 insn_code_number
= -1;
3373 /* See if this is a PARALLEL of two SETs where one SET's destination is
3374 a register that is unused and this isn't marked as an instruction that
3375 might trap in an EH region. In that case, we just need the other SET.
3376 We prefer this over the PARALLEL.
3378 This can occur when simplifying a divmod insn. We *must* test for this
3379 case here because the code below that splits two independent SETs doesn't
3380 handle this case correctly when it updates the register status.
3382 It's pointless doing this if we originally had two sets, one from
3383 i3, and one from i2. Combining then splitting the parallel results
3384 in the original i2 again plus an invalid insn (which we delete).
3385 The net effect is only to move instructions around, which makes
3386 debug info less accurate. */
3388 if (!(added_sets_2
&& i1
== 0)
3389 && GET_CODE (newpat
) == PARALLEL
3390 && XVECLEN (newpat
, 0) == 2
3391 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3392 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3393 && asm_noperands (newpat
) < 0)
3395 rtx set0
= XVECEXP (newpat
, 0, 0);
3396 rtx set1
= XVECEXP (newpat
, 0, 1);
3397 rtx oldpat
= newpat
;
3399 if (((REG_P (SET_DEST (set1
))
3400 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3401 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3402 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3403 && insn_nothrow_p (i3
)
3404 && !side_effects_p (SET_SRC (set1
)))
3407 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3410 else if (((REG_P (SET_DEST (set0
))
3411 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3412 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3413 && find_reg_note (i3
, REG_UNUSED
,
3414 SUBREG_REG (SET_DEST (set0
)))))
3415 && insn_nothrow_p (i3
)
3416 && !side_effects_p (SET_SRC (set0
)))
3419 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3421 if (insn_code_number
>= 0)
3422 changed_i3_dest
= 1;
3425 if (insn_code_number
< 0)
3429 /* Is the result of combination a valid instruction? */
3430 if (insn_code_number
< 0)
3431 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3433 /* If we were combining three insns and the result is a simple SET
3434 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3435 insns. There are two ways to do this. It can be split using a
3436 machine-specific method (like when you have an addition of a large
3437 constant) or by combine in the function find_split_point. */
3439 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3440 && asm_noperands (newpat
) < 0)
3442 rtx parallel
, *split
;
3443 rtx_insn
*m_split_insn
;
3445 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3446 use I2DEST as a scratch register will help. In the latter case,
3447 convert I2DEST to the mode of the source of NEWPAT if we can. */
3449 m_split_insn
= combine_split_insns (newpat
, i3
);
3451 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3452 inputs of NEWPAT. */
3454 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3455 possible to try that as a scratch reg. This would require adding
3456 more code to make it work though. */
3458 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3460 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3462 /* First try to split using the original register as a
3463 scratch register. */
3464 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3465 gen_rtvec (2, newpat
,
3466 gen_rtx_CLOBBER (VOIDmode
,
3468 m_split_insn
= combine_split_insns (parallel
, i3
);
3470 /* If that didn't work, try changing the mode of I2DEST if
3472 if (m_split_insn
== 0
3473 && new_mode
!= GET_MODE (i2dest
)
3474 && new_mode
!= VOIDmode
3475 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3477 machine_mode old_mode
= GET_MODE (i2dest
);
3480 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3481 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3484 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3485 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3488 parallel
= (gen_rtx_PARALLEL
3490 gen_rtvec (2, newpat
,
3491 gen_rtx_CLOBBER (VOIDmode
,
3493 m_split_insn
= combine_split_insns (parallel
, i3
);
3495 if (m_split_insn
== 0
3496 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3500 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3501 buf
= undobuf
.undos
;
3502 undobuf
.undos
= buf
->next
;
3503 buf
->next
= undobuf
.frees
;
3504 undobuf
.frees
= buf
;
3508 i2scratch
= m_split_insn
!= 0;
3511 /* If recog_for_combine has discarded clobbers, try to use them
3512 again for the split. */
3513 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3515 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3516 m_split_insn
= combine_split_insns (parallel
, i3
);
3519 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3521 rtx m_split_pat
= PATTERN (m_split_insn
);
3522 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3523 if (insn_code_number
>= 0)
3524 newpat
= m_split_pat
;
3526 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3527 && (next_nonnote_nondebug_insn (i2
) == i3
3528 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3531 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3532 newi2pat
= PATTERN (m_split_insn
);
3534 i3set
= single_set (NEXT_INSN (m_split_insn
));
3535 i2set
= single_set (m_split_insn
);
3537 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3539 /* If I2 or I3 has multiple SETs, we won't know how to track
3540 register status, so don't use these insns. If I2's destination
3541 is used between I2 and I3, we also can't use these insns. */
3543 if (i2_code_number
>= 0 && i2set
&& i3set
3544 && (next_nonnote_nondebug_insn (i2
) == i3
3545 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3546 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3548 if (insn_code_number
>= 0)
3551 /* It is possible that both insns now set the destination of I3.
3552 If so, we must show an extra use of it. */
3554 if (insn_code_number
>= 0)
3556 rtx new_i3_dest
= SET_DEST (i3set
);
3557 rtx new_i2_dest
= SET_DEST (i2set
);
3559 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3560 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3561 || GET_CODE (new_i3_dest
) == SUBREG
)
3562 new_i3_dest
= XEXP (new_i3_dest
, 0);
3564 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3565 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3566 || GET_CODE (new_i2_dest
) == SUBREG
)
3567 new_i2_dest
= XEXP (new_i2_dest
, 0);
3569 if (REG_P (new_i3_dest
)
3570 && REG_P (new_i2_dest
)
3571 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3572 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3576 /* If we can split it and use I2DEST, go ahead and see if that
3577 helps things be recognized. Verify that none of the registers
3578 are set between I2 and I3. */
3579 if (insn_code_number
< 0
3580 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3584 /* We need I2DEST in the proper mode. If it is a hard register
3585 or the only use of a pseudo, we can change its mode.
3586 Make sure we don't change a hard register to have a mode that
3587 isn't valid for it, or change the number of registers. */
3588 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3589 || GET_MODE (*split
) == VOIDmode
3590 || can_change_dest_mode (i2dest
, added_sets_2
,
3592 && (next_nonnote_nondebug_insn (i2
) == i3
3593 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3594 /* We can't overwrite I2DEST if its value is still used by
3596 && ! reg_referenced_p (i2dest
, newpat
))
3598 rtx newdest
= i2dest
;
3599 enum rtx_code split_code
= GET_CODE (*split
);
3600 machine_mode split_mode
= GET_MODE (*split
);
3601 bool subst_done
= false;
3602 newi2pat
= NULL_RTX
;
3606 /* *SPLIT may be part of I2SRC, so make sure we have the
3607 original expression around for later debug processing.
3608 We should not need I2SRC any more in other cases. */
3609 if (MAY_HAVE_DEBUG_INSNS
)
3610 i2src
= copy_rtx (i2src
);
3614 /* Get NEWDEST as a register in the proper mode. We have already
3615 validated that we can do this. */
3616 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3618 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3619 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3622 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3623 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3627 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3628 an ASHIFT. This can occur if it was inside a PLUS and hence
3629 appeared to be a memory address. This is a kludge. */
3630 if (split_code
== MULT
3631 && CONST_INT_P (XEXP (*split
, 1))
3632 && INTVAL (XEXP (*split
, 1)) > 0
3633 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3635 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3636 XEXP (*split
, 0), GEN_INT (i
)));
3637 /* Update split_code because we may not have a multiply
3639 split_code
= GET_CODE (*split
);
3642 #ifdef INSN_SCHEDULING
3643 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3644 be written as a ZERO_EXTEND. */
3645 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3647 #ifdef LOAD_EXTEND_OP
3648 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3649 what it really is. */
3650 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3652 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3653 SUBREG_REG (*split
)));
3656 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3657 SUBREG_REG (*split
)));
3661 /* Attempt to split binary operators using arithmetic identities. */
3662 if (BINARY_P (SET_SRC (newpat
))
3663 && split_mode
== GET_MODE (SET_SRC (newpat
))
3664 && ! side_effects_p (SET_SRC (newpat
)))
3666 rtx setsrc
= SET_SRC (newpat
);
3667 machine_mode mode
= GET_MODE (setsrc
);
3668 enum rtx_code code
= GET_CODE (setsrc
);
3669 rtx src_op0
= XEXP (setsrc
, 0);
3670 rtx src_op1
= XEXP (setsrc
, 1);
3672 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3673 if (rtx_equal_p (src_op0
, src_op1
))
3675 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3676 SUBST (XEXP (setsrc
, 0), newdest
);
3677 SUBST (XEXP (setsrc
, 1), newdest
);
3680 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3681 else if ((code
== PLUS
|| code
== MULT
)
3682 && GET_CODE (src_op0
) == code
3683 && GET_CODE (XEXP (src_op0
, 0)) == code
3684 && (INTEGRAL_MODE_P (mode
)
3685 || (FLOAT_MODE_P (mode
)
3686 && flag_unsafe_math_optimizations
)))
3688 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3689 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3690 rtx r
= XEXP (src_op0
, 1);
3693 /* Split both "((X op Y) op X) op Y" and
3694 "((X op Y) op Y) op X" as "T op T" where T is
3696 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3697 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3699 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3701 SUBST (XEXP (setsrc
, 0), newdest
);
3702 SUBST (XEXP (setsrc
, 1), newdest
);
3705 /* Split "((X op X) op Y) op Y)" as "T op T" where
3707 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3709 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3710 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3711 SUBST (XEXP (setsrc
, 0), newdest
);
3712 SUBST (XEXP (setsrc
, 1), newdest
);
3720 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3721 SUBST (*split
, newdest
);
3724 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3726 /* recog_for_combine might have added CLOBBERs to newi2pat.
3727 Make sure NEWPAT does not depend on the clobbered regs. */
3728 if (GET_CODE (newi2pat
) == PARALLEL
)
3729 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3730 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3732 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3733 if (reg_overlap_mentioned_p (reg
, newpat
))
3740 /* If the split point was a MULT and we didn't have one before,
3741 don't use one now. */
3742 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3743 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3747 /* Check for a case where we loaded from memory in a narrow mode and
3748 then sign extended it, but we need both registers. In that case,
3749 we have a PARALLEL with both loads from the same memory location.
3750 We can split this into a load from memory followed by a register-register
3751 copy. This saves at least one insn, more if register allocation can
3754 We cannot do this if the destination of the first assignment is a
3755 condition code register or cc0. We eliminate this case by making sure
3756 the SET_DEST and SET_SRC have the same mode.
3758 We cannot do this if the destination of the second assignment is
3759 a register that we have already assumed is zero-extended. Similarly
3760 for a SUBREG of such a register. */
3762 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3763 && GET_CODE (newpat
) == PARALLEL
3764 && XVECLEN (newpat
, 0) == 2
3765 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3766 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3767 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3768 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3769 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3770 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3771 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3772 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3774 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3775 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3776 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3778 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3779 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3780 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3781 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3782 != GET_MODE_MASK (word_mode
))))
3783 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3784 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3786 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3787 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3788 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3789 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3790 != GET_MODE_MASK (word_mode
)))))
3791 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3792 SET_SRC (XVECEXP (newpat
, 0, 1)))
3793 && ! find_reg_note (i3
, REG_UNUSED
,
3794 SET_DEST (XVECEXP (newpat
, 0, 0))))
3798 newi2pat
= XVECEXP (newpat
, 0, 0);
3799 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3800 newpat
= XVECEXP (newpat
, 0, 1);
3801 SUBST (SET_SRC (newpat
),
3802 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3803 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3805 if (i2_code_number
>= 0)
3806 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3808 if (insn_code_number
>= 0)
3812 /* Similarly, check for a case where we have a PARALLEL of two independent
3813 SETs but we started with three insns. In this case, we can do the sets
3814 as two separate insns. This case occurs when some SET allows two
3815 other insns to combine, but the destination of that SET is still live.
3817 Also do this if we started with two insns and (at least) one of the
3818 resulting sets is a noop; this noop will be deleted later. */
3820 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3821 && GET_CODE (newpat
) == PARALLEL
3822 && XVECLEN (newpat
, 0) == 2
3823 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3824 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3825 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3826 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3827 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3828 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3829 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3830 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3831 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3832 XVECEXP (newpat
, 0, 0))
3833 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3834 XVECEXP (newpat
, 0, 1))
3835 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3836 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3838 rtx set0
= XVECEXP (newpat
, 0, 0);
3839 rtx set1
= XVECEXP (newpat
, 0, 1);
3841 /* Normally, it doesn't matter which of the two is done first,
3842 but the one that references cc0 can't be the second, and
3843 one which uses any regs/memory set in between i2 and i3 can't
3844 be first. The PARALLEL might also have been pre-existing in i3,
3845 so we need to make sure that we won't wrongly hoist a SET to i2
3846 that would conflict with a death note present in there. */
3847 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3848 && !(REG_P (SET_DEST (set1
))
3849 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3850 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3851 && find_reg_note (i2
, REG_DEAD
,
3852 SUBREG_REG (SET_DEST (set1
))))
3854 && !reg_referenced_p (cc0_rtx
, set0
)
3856 /* If I3 is a jump, ensure that set0 is a jump so that
3857 we do not create invalid RTL. */
3858 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3864 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3865 && !(REG_P (SET_DEST (set0
))
3866 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3867 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3868 && find_reg_note (i2
, REG_DEAD
,
3869 SUBREG_REG (SET_DEST (set0
))))
3871 && !reg_referenced_p (cc0_rtx
, set1
)
3873 /* If I3 is a jump, ensure that set1 is a jump so that
3874 we do not create invalid RTL. */
3875 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3887 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3889 if (i2_code_number
>= 0)
3891 /* recog_for_combine might have added CLOBBERs to newi2pat.
3892 Make sure NEWPAT does not depend on the clobbered regs. */
3893 if (GET_CODE (newi2pat
) == PARALLEL
)
3895 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3896 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3898 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3899 if (reg_overlap_mentioned_p (reg
, newpat
))
3907 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3911 /* If it still isn't recognized, fail and change things back the way they
3913 if ((insn_code_number
< 0
3914 /* Is the result a reasonable ASM_OPERANDS? */
3915 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3921 /* If we had to change another insn, make sure it is valid also. */
3922 if (undobuf
.other_insn
)
3924 CLEAR_HARD_REG_SET (newpat_used_regs
);
3926 other_pat
= PATTERN (undobuf
.other_insn
);
3927 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3930 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3938 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3939 they are adjacent to each other or not. */
3941 rtx_insn
*p
= prev_nonnote_insn (i3
);
3942 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3943 && sets_cc0_p (newi2pat
))
3951 /* Only allow this combination if insn_rtx_costs reports that the
3952 replacement instructions are cheaper than the originals. */
3953 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3959 if (MAY_HAVE_DEBUG_INSNS
)
3963 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3964 if (undo
->kind
== UNDO_MODE
)
3966 rtx reg
= *undo
->where
.r
;
3967 machine_mode new_mode
= GET_MODE (reg
);
3968 machine_mode old_mode
= undo
->old_contents
.m
;
3970 /* Temporarily revert mode back. */
3971 adjust_reg_mode (reg
, old_mode
);
3973 if (reg
== i2dest
&& i2scratch
)
3975 /* If we used i2dest as a scratch register with a
3976 different mode, substitute it for the original
3977 i2src while its original mode is temporarily
3978 restored, and then clear i2scratch so that we don't
3979 do it again later. */
3980 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
3983 /* Put back the new mode. */
3984 adjust_reg_mode (reg
, new_mode
);
3988 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3989 rtx_insn
*first
, *last
;
3994 last
= last_combined_insn
;
3999 last
= undobuf
.other_insn
;
4001 if (DF_INSN_LUID (last
)
4002 < DF_INSN_LUID (last_combined_insn
))
4003 last
= last_combined_insn
;
4006 /* We're dealing with a reg that changed mode but not
4007 meaning, so we want to turn it into a subreg for
4008 the new mode. However, because of REG sharing and
4009 because its mode had already changed, we have to do
4010 it in two steps. First, replace any debug uses of
4011 reg, with its original mode temporarily restored,
4012 with this copy we have created; then, replace the
4013 copy with the SUBREG of the original shared reg,
4014 once again changed to the new mode. */
4015 propagate_for_debug (first
, last
, reg
, tempreg
,
4017 adjust_reg_mode (reg
, new_mode
);
4018 propagate_for_debug (first
, last
, tempreg
,
4019 lowpart_subreg (old_mode
, reg
, new_mode
),
4025 /* If we will be able to accept this, we have made a
4026 change to the destination of I3. This requires us to
4027 do a few adjustments. */
4029 if (changed_i3_dest
)
4031 PATTERN (i3
) = newpat
;
4032 adjust_for_new_dest (i3
);
4035 /* We now know that we can do this combination. Merge the insns and
4036 update the status of registers and LOG_LINKS. */
4038 if (undobuf
.other_insn
)
4042 PATTERN (undobuf
.other_insn
) = other_pat
;
4044 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4045 ensure that they are still valid. Then add any non-duplicate
4046 notes added by recog_for_combine. */
4047 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4049 next
= XEXP (note
, 1);
4051 if ((REG_NOTE_KIND (note
) == REG_DEAD
4052 && !reg_referenced_p (XEXP (note
, 0),
4053 PATTERN (undobuf
.other_insn
)))
4054 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4055 && !reg_set_p (XEXP (note
, 0),
4056 PATTERN (undobuf
.other_insn
))))
4057 remove_note (undobuf
.other_insn
, note
);
4060 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4061 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4068 struct insn_link
*link
;
4071 /* I3 now uses what used to be its destination and which is now
4072 I2's destination. This requires us to do a few adjustments. */
4073 PATTERN (i3
) = newpat
;
4074 adjust_for_new_dest (i3
);
4076 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4079 However, some later insn might be using I2's dest and have
4080 a LOG_LINK pointing at I3. We must remove this link.
4081 The simplest way to remove the link is to point it at I1,
4082 which we know will be a NOTE. */
4084 /* newi2pat is usually a SET here; however, recog_for_combine might
4085 have added some clobbers. */
4086 if (GET_CODE (newi2pat
) == PARALLEL
)
4087 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4089 ni2dest
= SET_DEST (newi2pat
);
4091 for (insn
= NEXT_INSN (i3
);
4092 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4093 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4094 insn
= NEXT_INSN (insn
))
4096 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4098 FOR_EACH_LOG_LINK (link
, insn
)
4099 if (link
->insn
== i3
)
4108 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4109 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4112 /* Compute which registers we expect to eliminate. newi2pat may be setting
4113 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4114 same as i3dest, in which case newi2pat may be setting i1dest. */
4115 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4116 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4119 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4120 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4123 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
4124 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4128 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4130 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4131 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4133 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4135 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4137 /* Ensure that we do not have something that should not be shared but
4138 occurs multiple times in the new insns. Check this by first
4139 resetting all the `used' flags and then copying anything is shared. */
4141 reset_used_flags (i3notes
);
4142 reset_used_flags (i2notes
);
4143 reset_used_flags (i1notes
);
4144 reset_used_flags (i0notes
);
4145 reset_used_flags (newpat
);
4146 reset_used_flags (newi2pat
);
4147 if (undobuf
.other_insn
)
4148 reset_used_flags (PATTERN (undobuf
.other_insn
));
4150 i3notes
= copy_rtx_if_shared (i3notes
);
4151 i2notes
= copy_rtx_if_shared (i2notes
);
4152 i1notes
= copy_rtx_if_shared (i1notes
);
4153 i0notes
= copy_rtx_if_shared (i0notes
);
4154 newpat
= copy_rtx_if_shared (newpat
);
4155 newi2pat
= copy_rtx_if_shared (newi2pat
);
4156 if (undobuf
.other_insn
)
4157 reset_used_flags (PATTERN (undobuf
.other_insn
));
4159 INSN_CODE (i3
) = insn_code_number
;
4160 PATTERN (i3
) = newpat
;
4162 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4164 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4166 reset_used_flags (call_usage
);
4167 call_usage
= copy_rtx (call_usage
);
4171 /* I2SRC must still be meaningful at this point. Some splitting
4172 operations can invalidate I2SRC, but those operations do not
4175 replace_rtx (call_usage
, i2dest
, i2src
);
4179 replace_rtx (call_usage
, i1dest
, i1src
);
4181 replace_rtx (call_usage
, i0dest
, i0src
);
4183 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4186 if (undobuf
.other_insn
)
4187 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4189 /* We had one special case above where I2 had more than one set and
4190 we replaced a destination of one of those sets with the destination
4191 of I3. In that case, we have to update LOG_LINKS of insns later
4192 in this basic block. Note that this (expensive) case is rare.
4194 Also, in this case, we must pretend that all REG_NOTEs for I2
4195 actually came from I3, so that REG_UNUSED notes from I2 will be
4196 properly handled. */
4198 if (i3_subst_into_i2
)
4200 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4201 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4202 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4203 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4204 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4205 && ! find_reg_note (i2
, REG_UNUSED
,
4206 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4207 for (temp_insn
= NEXT_INSN (i2
);
4209 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4210 || BB_HEAD (this_basic_block
) != temp_insn
);
4211 temp_insn
= NEXT_INSN (temp_insn
))
4212 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4213 FOR_EACH_LOG_LINK (link
, temp_insn
)
4214 if (link
->insn
== i2
)
4220 while (XEXP (link
, 1))
4221 link
= XEXP (link
, 1);
4222 XEXP (link
, 1) = i2notes
;
4229 LOG_LINKS (i3
) = NULL
;
4231 LOG_LINKS (i2
) = NULL
;
4236 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4237 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4239 INSN_CODE (i2
) = i2_code_number
;
4240 PATTERN (i2
) = newi2pat
;
4244 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4245 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4247 SET_INSN_DELETED (i2
);
4252 LOG_LINKS (i1
) = NULL
;
4254 if (MAY_HAVE_DEBUG_INSNS
)
4255 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4257 SET_INSN_DELETED (i1
);
4262 LOG_LINKS (i0
) = NULL
;
4264 if (MAY_HAVE_DEBUG_INSNS
)
4265 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4267 SET_INSN_DELETED (i0
);
4270 /* Get death notes for everything that is now used in either I3 or
4271 I2 and used to die in a previous insn. If we built two new
4272 patterns, move from I1 to I2 then I2 to I3 so that we get the
4273 proper movement on registers that I2 modifies. */
4276 from_luid
= DF_INSN_LUID (i0
);
4278 from_luid
= DF_INSN_LUID (i1
);
4280 from_luid
= DF_INSN_LUID (i2
);
4282 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4283 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4285 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4287 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4288 elim_i2
, elim_i1
, elim_i0
);
4290 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4291 elim_i2
, elim_i1
, elim_i0
);
4293 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4294 elim_i2
, elim_i1
, elim_i0
);
4296 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4297 elim_i2
, elim_i1
, elim_i0
);
4299 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4300 elim_i2
, elim_i1
, elim_i0
);
4302 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4303 know these are REG_UNUSED and want them to go to the desired insn,
4304 so we always pass it as i3. */
4306 if (newi2pat
&& new_i2_notes
)
4307 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4311 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4314 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4315 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4316 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4317 in that case, it might delete I2. Similarly for I2 and I1.
4318 Show an additional death due to the REG_DEAD note we make here. If
4319 we discard it in distribute_notes, we will decrement it again. */
4323 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4324 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4325 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4328 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4329 elim_i2
, elim_i1
, elim_i0
);
4332 if (i2dest_in_i2src
)
4334 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4335 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4336 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4337 NULL_RTX
, NULL_RTX
);
4339 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4340 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4343 if (i1dest_in_i1src
)
4345 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4346 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4347 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4348 NULL_RTX
, NULL_RTX
);
4350 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4351 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4354 if (i0dest_in_i0src
)
4356 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4357 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4358 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4359 NULL_RTX
, NULL_RTX
);
4361 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4362 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4365 distribute_links (i3links
);
4366 distribute_links (i2links
);
4367 distribute_links (i1links
);
4368 distribute_links (i0links
);
4372 struct insn_link
*link
;
4373 rtx_insn
*i2_insn
= 0;
4374 rtx i2_val
= 0, set
;
4376 /* The insn that used to set this register doesn't exist, and
4377 this life of the register may not exist either. See if one of
4378 I3's links points to an insn that sets I2DEST. If it does,
4379 that is now the last known value for I2DEST. If we don't update
4380 this and I2 set the register to a value that depended on its old
4381 contents, we will get confused. If this insn is used, thing
4382 will be set correctly in combine_instructions. */
4383 FOR_EACH_LOG_LINK (link
, i3
)
4384 if ((set
= single_set (link
->insn
)) != 0
4385 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4386 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4388 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4390 /* If the reg formerly set in I2 died only once and that was in I3,
4391 zero its use count so it won't make `reload' do any work. */
4393 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4394 && ! i2dest_in_i2src
)
4395 INC_REG_N_SETS (REGNO (i2dest
), -1);
4398 if (i1
&& REG_P (i1dest
))
4400 struct insn_link
*link
;
4401 rtx_insn
*i1_insn
= 0;
4402 rtx i1_val
= 0, set
;
4404 FOR_EACH_LOG_LINK (link
, i3
)
4405 if ((set
= single_set (link
->insn
)) != 0
4406 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4407 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4409 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4411 if (! added_sets_1
&& ! i1dest_in_i1src
)
4412 INC_REG_N_SETS (REGNO (i1dest
), -1);
4415 if (i0
&& REG_P (i0dest
))
4417 struct insn_link
*link
;
4418 rtx_insn
*i0_insn
= 0;
4419 rtx i0_val
= 0, set
;
4421 FOR_EACH_LOG_LINK (link
, i3
)
4422 if ((set
= single_set (link
->insn
)) != 0
4423 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4424 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4426 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4428 if (! added_sets_0
&& ! i0dest_in_i0src
)
4429 INC_REG_N_SETS (REGNO (i0dest
), -1);
4432 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4433 been made to this insn. The order is important, because newi2pat
4434 can affect nonzero_bits of newpat. */
4436 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4437 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4440 if (undobuf
.other_insn
!= NULL_RTX
)
4444 fprintf (dump_file
, "modifying other_insn ");
4445 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4447 df_insn_rescan (undobuf
.other_insn
);
4450 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4454 fprintf (dump_file
, "modifying insn i0 ");
4455 dump_insn_slim (dump_file
, i0
);
4457 df_insn_rescan (i0
);
4460 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4464 fprintf (dump_file
, "modifying insn i1 ");
4465 dump_insn_slim (dump_file
, i1
);
4467 df_insn_rescan (i1
);
4470 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4474 fprintf (dump_file
, "modifying insn i2 ");
4475 dump_insn_slim (dump_file
, i2
);
4477 df_insn_rescan (i2
);
4480 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4484 fprintf (dump_file
, "modifying insn i3 ");
4485 dump_insn_slim (dump_file
, i3
);
4487 df_insn_rescan (i3
);
4490 /* Set new_direct_jump_p if a new return or simple jump instruction
4491 has been created. Adjust the CFG accordingly. */
4492 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4494 *new_direct_jump_p
= 1;
4495 mark_jump_label (PATTERN (i3
), i3
, 0);
4496 update_cfg_for_uncondjump (i3
);
4499 if (undobuf
.other_insn
!= NULL_RTX
4500 && (returnjump_p (undobuf
.other_insn
)
4501 || any_uncondjump_p (undobuf
.other_insn
)))
4503 *new_direct_jump_p
= 1;
4504 update_cfg_for_uncondjump (undobuf
.other_insn
);
4507 /* A noop might also need cleaning up of CFG, if it comes from the
4508 simplification of a jump. */
4510 && GET_CODE (newpat
) == SET
4511 && SET_SRC (newpat
) == pc_rtx
4512 && SET_DEST (newpat
) == pc_rtx
)
4514 *new_direct_jump_p
= 1;
4515 update_cfg_for_uncondjump (i3
);
4518 if (undobuf
.other_insn
!= NULL_RTX
4519 && JUMP_P (undobuf
.other_insn
)
4520 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4521 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4522 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4524 *new_direct_jump_p
= 1;
4525 update_cfg_for_uncondjump (undobuf
.other_insn
);
4528 combine_successes
++;
4531 if (added_links_insn
4532 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4533 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4534 return added_links_insn
;
4536 return newi2pat
? i2
: i3
;
4539 /* Undo all the modifications recorded in undobuf. */
4544 struct undo
*undo
, *next
;
4546 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4552 *undo
->where
.r
= undo
->old_contents
.r
;
4555 *undo
->where
.i
= undo
->old_contents
.i
;
4558 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4561 *undo
->where
.l
= undo
->old_contents
.l
;
4567 undo
->next
= undobuf
.frees
;
4568 undobuf
.frees
= undo
;
4574 /* We've committed to accepting the changes we made. Move all
4575 of the undos to the free list. */
4580 struct undo
*undo
, *next
;
4582 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4585 undo
->next
= undobuf
.frees
;
4586 undobuf
.frees
= undo
;
4591 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4592 where we have an arithmetic expression and return that point. LOC will
4595 try_combine will call this function to see if an insn can be split into
4599 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4602 enum rtx_code code
= GET_CODE (x
);
4604 unsigned HOST_WIDE_INT len
= 0;
4605 HOST_WIDE_INT pos
= 0;
4607 rtx inner
= NULL_RTX
;
4609 /* First special-case some codes. */
4613 #ifdef INSN_SCHEDULING
4614 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4616 if (MEM_P (SUBREG_REG (x
)))
4619 return find_split_point (&SUBREG_REG (x
), insn
, false);
4623 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4624 using LO_SUM and HIGH. */
4625 if (GET_CODE (XEXP (x
, 0)) == CONST
4626 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4628 machine_mode address_mode
= get_address_mode (x
);
4631 gen_rtx_LO_SUM (address_mode
,
4632 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4634 return &XEXP (XEXP (x
, 0), 0);
4638 /* If we have a PLUS whose second operand is a constant and the
4639 address is not valid, perhaps will can split it up using
4640 the machine-specific way to split large constants. We use
4641 the first pseudo-reg (one of the virtual regs) as a placeholder;
4642 it will not remain in the result. */
4643 if (GET_CODE (XEXP (x
, 0)) == PLUS
4644 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4645 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4646 MEM_ADDR_SPACE (x
)))
4648 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4649 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4653 /* This should have produced two insns, each of which sets our
4654 placeholder. If the source of the second is a valid address,
4655 we can make put both sources together and make a split point
4659 && NEXT_INSN (seq
) != NULL_RTX
4660 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4661 && NONJUMP_INSN_P (seq
)
4662 && GET_CODE (PATTERN (seq
)) == SET
4663 && SET_DEST (PATTERN (seq
)) == reg
4664 && ! reg_mentioned_p (reg
,
4665 SET_SRC (PATTERN (seq
)))
4666 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4667 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4668 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4669 && memory_address_addr_space_p
4670 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4671 MEM_ADDR_SPACE (x
)))
4673 rtx src1
= SET_SRC (PATTERN (seq
));
4674 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4676 /* Replace the placeholder in SRC2 with SRC1. If we can
4677 find where in SRC2 it was placed, that can become our
4678 split point and we can replace this address with SRC2.
4679 Just try two obvious places. */
4681 src2
= replace_rtx (src2
, reg
, src1
);
4683 if (XEXP (src2
, 0) == src1
)
4684 split
= &XEXP (src2
, 0);
4685 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4686 && XEXP (XEXP (src2
, 0), 0) == src1
)
4687 split
= &XEXP (XEXP (src2
, 0), 0);
4691 SUBST (XEXP (x
, 0), src2
);
4696 /* If that didn't work, perhaps the first operand is complex and
4697 needs to be computed separately, so make a split point there.
4698 This will occur on machines that just support REG + CONST
4699 and have a constant moved through some previous computation. */
4701 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4702 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4703 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4704 return &XEXP (XEXP (x
, 0), 0);
4707 /* If we have a PLUS whose first operand is complex, try computing it
4708 separately by making a split there. */
4709 if (GET_CODE (XEXP (x
, 0)) == PLUS
4710 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4712 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4713 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4714 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4715 return &XEXP (XEXP (x
, 0), 0);
4720 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4721 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4722 we need to put the operand into a register. So split at that
4725 if (SET_DEST (x
) == cc0_rtx
4726 && GET_CODE (SET_SRC (x
)) != COMPARE
4727 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4728 && !OBJECT_P (SET_SRC (x
))
4729 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4730 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4731 return &SET_SRC (x
);
4734 /* See if we can split SET_SRC as it stands. */
4735 split
= find_split_point (&SET_SRC (x
), insn
, true);
4736 if (split
&& split
!= &SET_SRC (x
))
4739 /* See if we can split SET_DEST as it stands. */
4740 split
= find_split_point (&SET_DEST (x
), insn
, false);
4741 if (split
&& split
!= &SET_DEST (x
))
4744 /* See if this is a bitfield assignment with everything constant. If
4745 so, this is an IOR of an AND, so split it into that. */
4746 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4747 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4748 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4749 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4750 && CONST_INT_P (SET_SRC (x
))
4751 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4752 + INTVAL (XEXP (SET_DEST (x
), 2)))
4753 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4754 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4756 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4757 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4758 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4759 rtx dest
= XEXP (SET_DEST (x
), 0);
4760 machine_mode mode
= GET_MODE (dest
);
4761 unsigned HOST_WIDE_INT mask
4762 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4765 if (BITS_BIG_ENDIAN
)
4766 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4768 or_mask
= gen_int_mode (src
<< pos
, mode
);
4771 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4774 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4776 simplify_gen_binary (IOR
, mode
,
4777 simplify_gen_binary (AND
, mode
,
4782 SUBST (SET_DEST (x
), dest
);
4784 split
= find_split_point (&SET_SRC (x
), insn
, true);
4785 if (split
&& split
!= &SET_SRC (x
))
4789 /* Otherwise, see if this is an operation that we can split into two.
4790 If so, try to split that. */
4791 code
= GET_CODE (SET_SRC (x
));
4796 /* If we are AND'ing with a large constant that is only a single
4797 bit and the result is only being used in a context where we
4798 need to know if it is zero or nonzero, replace it with a bit
4799 extraction. This will avoid the large constant, which might
4800 have taken more than one insn to make. If the constant were
4801 not a valid argument to the AND but took only one insn to make,
4802 this is no worse, but if it took more than one insn, it will
4805 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4806 && REG_P (XEXP (SET_SRC (x
), 0))
4807 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4808 && REG_P (SET_DEST (x
))
4809 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4810 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4811 && XEXP (*split
, 0) == SET_DEST (x
)
4812 && XEXP (*split
, 1) == const0_rtx
)
4814 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4815 XEXP (SET_SRC (x
), 0),
4816 pos
, NULL_RTX
, 1, 1, 0, 0);
4817 if (extraction
!= 0)
4819 SUBST (SET_SRC (x
), extraction
);
4820 return find_split_point (loc
, insn
, false);
4826 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4827 is known to be on, this can be converted into a NEG of a shift. */
4828 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4829 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4830 && 1 <= (pos
= exact_log2
4831 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4832 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4834 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4838 gen_rtx_LSHIFTRT (mode
,
4839 XEXP (SET_SRC (x
), 0),
4842 split
= find_split_point (&SET_SRC (x
), insn
, true);
4843 if (split
&& split
!= &SET_SRC (x
))
4849 inner
= XEXP (SET_SRC (x
), 0);
4851 /* We can't optimize if either mode is a partial integer
4852 mode as we don't know how many bits are significant
4854 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4855 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4859 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4865 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4866 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4868 inner
= XEXP (SET_SRC (x
), 0);
4869 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4870 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4872 if (BITS_BIG_ENDIAN
)
4873 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4874 unsignedp
= (code
== ZERO_EXTRACT
);
4883 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4885 machine_mode mode
= GET_MODE (SET_SRC (x
));
4887 /* For unsigned, we have a choice of a shift followed by an
4888 AND or two shifts. Use two shifts for field sizes where the
4889 constant might be too large. We assume here that we can
4890 always at least get 8-bit constants in an AND insn, which is
4891 true for every current RISC. */
4893 if (unsignedp
&& len
<= 8)
4895 unsigned HOST_WIDE_INT mask
4896 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4900 (mode
, gen_lowpart (mode
, inner
),
4902 gen_int_mode (mask
, mode
)));
4904 split
= find_split_point (&SET_SRC (x
), insn
, true);
4905 if (split
&& split
!= &SET_SRC (x
))
4912 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4913 gen_rtx_ASHIFT (mode
,
4914 gen_lowpart (mode
, inner
),
4915 GEN_INT (GET_MODE_PRECISION (mode
)
4917 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4919 split
= find_split_point (&SET_SRC (x
), insn
, true);
4920 if (split
&& split
!= &SET_SRC (x
))
4925 /* See if this is a simple operation with a constant as the second
4926 operand. It might be that this constant is out of range and hence
4927 could be used as a split point. */
4928 if (BINARY_P (SET_SRC (x
))
4929 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4930 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4931 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4932 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4933 return &XEXP (SET_SRC (x
), 1);
4935 /* Finally, see if this is a simple operation with its first operand
4936 not in a register. The operation might require this operand in a
4937 register, so return it as a split point. We can always do this
4938 because if the first operand were another operation, we would have
4939 already found it as a split point. */
4940 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4941 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4942 return &XEXP (SET_SRC (x
), 0);
4948 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4949 it is better to write this as (not (ior A B)) so we can split it.
4950 Similarly for IOR. */
4951 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4954 gen_rtx_NOT (GET_MODE (x
),
4955 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4957 XEXP (XEXP (x
, 0), 0),
4958 XEXP (XEXP (x
, 1), 0))));
4959 return find_split_point (loc
, insn
, set_src
);
4962 /* Many RISC machines have a large set of logical insns. If the
4963 second operand is a NOT, put it first so we will try to split the
4964 other operand first. */
4965 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4967 rtx tem
= XEXP (x
, 0);
4968 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4969 SUBST (XEXP (x
, 1), tem
);
4975 /* Canonicalization can produce (minus A (mult B C)), where C is a
4976 constant. It may be better to try splitting (plus (mult B -C) A)
4977 instead if this isn't a multiply by a power of two. */
4978 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4979 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4980 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4982 machine_mode mode
= GET_MODE (x
);
4983 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4984 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4985 SUBST (*loc
, gen_rtx_PLUS (mode
,
4987 XEXP (XEXP (x
, 1), 0),
4988 gen_int_mode (other_int
,
4991 return find_split_point (loc
, insn
, set_src
);
4994 /* Split at a multiply-accumulate instruction. However if this is
4995 the SET_SRC, we likely do not have such an instruction and it's
4996 worthless to try this split. */
4997 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
5004 /* Otherwise, select our actions depending on our rtx class. */
5005 switch (GET_RTX_CLASS (code
))
5007 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5009 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5012 /* ... fall through ... */
5014 case RTX_COMM_ARITH
:
5016 case RTX_COMM_COMPARE
:
5017 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5020 /* ... fall through ... */
5022 /* Some machines have (and (shift ...) ...) insns. If X is not
5023 an AND, but XEXP (X, 0) is, use it as our split point. */
5024 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5025 return &XEXP (x
, 0);
5027 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5033 /* Otherwise, we don't have a split point. */
5038 /* Throughout X, replace FROM with TO, and return the result.
5039 The result is TO if X is FROM;
5040 otherwise the result is X, but its contents may have been modified.
5041 If they were modified, a record was made in undobuf so that
5042 undo_all will (among other things) return X to its original state.
5044 If the number of changes necessary is too much to record to undo,
5045 the excess changes are not made, so the result is invalid.
5046 The changes already made can still be undone.
5047 undobuf.num_undo is incremented for such changes, so by testing that
5048 the caller can tell whether the result is valid.
5050 `n_occurrences' is incremented each time FROM is replaced.
5052 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5054 IN_COND is nonzero if we are at the top level of a condition.
5056 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5057 by copying if `n_occurrences' is nonzero. */
5060 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5062 enum rtx_code code
= GET_CODE (x
);
5063 machine_mode op0_mode
= VOIDmode
;
5068 /* Two expressions are equal if they are identical copies of a shared
5069 RTX or if they are both registers with the same register number
5072 #define COMBINE_RTX_EQUAL_P(X,Y) \
5074 || (REG_P (X) && REG_P (Y) \
5075 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5077 /* Do not substitute into clobbers of regs -- this will never result in
5079 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5082 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5085 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5088 /* If X and FROM are the same register but different modes, they
5089 will not have been seen as equal above. However, the log links code
5090 will make a LOG_LINKS entry for that case. If we do nothing, we
5091 will try to rerecognize our original insn and, when it succeeds,
5092 we will delete the feeding insn, which is incorrect.
5094 So force this insn not to match in this (rare) case. */
5095 if (! in_dest
&& code
== REG
&& REG_P (from
)
5096 && reg_overlap_mentioned_p (x
, from
))
5097 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5099 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5100 of which may contain things that can be combined. */
5101 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5104 /* It is possible to have a subexpression appear twice in the insn.
5105 Suppose that FROM is a register that appears within TO.
5106 Then, after that subexpression has been scanned once by `subst',
5107 the second time it is scanned, TO may be found. If we were
5108 to scan TO here, we would find FROM within it and create a
5109 self-referent rtl structure which is completely wrong. */
5110 if (COMBINE_RTX_EQUAL_P (x
, to
))
5113 /* Parallel asm_operands need special attention because all of the
5114 inputs are shared across the arms. Furthermore, unsharing the
5115 rtl results in recognition failures. Failure to handle this case
5116 specially can result in circular rtl.
5118 Solve this by doing a normal pass across the first entry of the
5119 parallel, and only processing the SET_DESTs of the subsequent
5122 if (code
== PARALLEL
5123 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5124 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5126 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5128 /* If this substitution failed, this whole thing fails. */
5129 if (GET_CODE (new_rtx
) == CLOBBER
5130 && XEXP (new_rtx
, 0) == const0_rtx
)
5133 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5135 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5137 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5140 && GET_CODE (dest
) != CC0
5141 && GET_CODE (dest
) != PC
)
5143 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5145 /* If this substitution failed, this whole thing fails. */
5146 if (GET_CODE (new_rtx
) == CLOBBER
5147 && XEXP (new_rtx
, 0) == const0_rtx
)
5150 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5156 len
= GET_RTX_LENGTH (code
);
5157 fmt
= GET_RTX_FORMAT (code
);
5159 /* We don't need to process a SET_DEST that is a register, CC0,
5160 or PC, so set up to skip this common case. All other cases
5161 where we want to suppress replacing something inside a
5162 SET_SRC are handled via the IN_DEST operand. */
5164 && (REG_P (SET_DEST (x
))
5165 || GET_CODE (SET_DEST (x
)) == CC0
5166 || GET_CODE (SET_DEST (x
)) == PC
))
5169 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5172 op0_mode
= GET_MODE (XEXP (x
, 0));
5174 for (i
= 0; i
< len
; i
++)
5179 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5181 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5183 new_rtx
= (unique_copy
&& n_occurrences
5184 ? copy_rtx (to
) : to
);
5189 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5192 /* If this substitution failed, this whole thing
5194 if (GET_CODE (new_rtx
) == CLOBBER
5195 && XEXP (new_rtx
, 0) == const0_rtx
)
5199 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5202 else if (fmt
[i
] == 'e')
5204 /* If this is a register being set, ignore it. */
5205 new_rtx
= XEXP (x
, i
);
5208 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5210 || code
== STRICT_LOW_PART
))
5213 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5215 /* In general, don't install a subreg involving two
5216 modes not tieable. It can worsen register
5217 allocation, and can even make invalid reload
5218 insns, since the reg inside may need to be copied
5219 from in the outside mode, and that may be invalid
5220 if it is an fp reg copied in integer mode.
5222 We allow two exceptions to this: It is valid if
5223 it is inside another SUBREG and the mode of that
5224 SUBREG and the mode of the inside of TO is
5225 tieable and it is valid if X is a SET that copies
5228 if (GET_CODE (to
) == SUBREG
5229 && ! MODES_TIEABLE_P (GET_MODE (to
),
5230 GET_MODE (SUBREG_REG (to
)))
5231 && ! (code
== SUBREG
5232 && MODES_TIEABLE_P (GET_MODE (x
),
5233 GET_MODE (SUBREG_REG (to
))))
5235 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5238 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5242 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5243 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5246 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5248 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5252 /* If we are in a SET_DEST, suppress most cases unless we
5253 have gone inside a MEM, in which case we want to
5254 simplify the address. We assume here that things that
5255 are actually part of the destination have their inner
5256 parts in the first expression. This is true for SUBREG,
5257 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5258 things aside from REG and MEM that should appear in a
5260 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5262 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5263 || code
== ZERO_EXTRACT
))
5266 code
== IF_THEN_ELSE
&& i
== 0,
5269 /* If we found that we will have to reject this combination,
5270 indicate that by returning the CLOBBER ourselves, rather than
5271 an expression containing it. This will speed things up as
5272 well as prevent accidents where two CLOBBERs are considered
5273 to be equal, thus producing an incorrect simplification. */
5275 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5278 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5280 machine_mode mode
= GET_MODE (x
);
5282 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5283 GET_MODE (SUBREG_REG (x
)),
5286 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5288 else if (CONST_SCALAR_INT_P (new_rtx
)
5289 && GET_CODE (x
) == ZERO_EXTEND
)
5291 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5292 new_rtx
, GET_MODE (XEXP (x
, 0)));
5296 SUBST (XEXP (x
, i
), new_rtx
);
5301 /* Check if we are loading something from the constant pool via float
5302 extension; in this case we would undo compress_float_constant
5303 optimization and degenerate constant load to an immediate value. */
5304 if (GET_CODE (x
) == FLOAT_EXTEND
5305 && MEM_P (XEXP (x
, 0))
5306 && MEM_READONLY_P (XEXP (x
, 0)))
5308 rtx tmp
= avoid_constant_pool_reference (x
);
5313 /* Try to simplify X. If the simplification changed the code, it is likely
5314 that further simplification will help, so loop, but limit the number
5315 of repetitions that will be performed. */
5317 for (i
= 0; i
< 4; i
++)
5319 /* If X is sufficiently simple, don't bother trying to do anything
5321 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5322 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5324 if (GET_CODE (x
) == code
)
5327 code
= GET_CODE (x
);
5329 /* We no longer know the original mode of operand 0 since we
5330 have changed the form of X) */
5331 op0_mode
= VOIDmode
;
5337 /* Simplify X, a piece of RTL. We just operate on the expression at the
5338 outer level; call `subst' to simplify recursively. Return the new
5341 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5342 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5346 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5349 enum rtx_code code
= GET_CODE (x
);
5350 machine_mode mode
= GET_MODE (x
);
5354 /* If this is a commutative operation, put a constant last and a complex
5355 expression first. We don't need to do this for comparisons here. */
5356 if (COMMUTATIVE_ARITH_P (x
)
5357 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5360 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5361 SUBST (XEXP (x
, 1), temp
);
5364 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5365 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5366 things. Check for cases where both arms are testing the same
5369 Don't do anything if all operands are very simple. */
5372 && ((!OBJECT_P (XEXP (x
, 0))
5373 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5374 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5375 || (!OBJECT_P (XEXP (x
, 1))
5376 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5377 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5379 && (!OBJECT_P (XEXP (x
, 0))
5380 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5381 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5383 rtx cond
, true_rtx
, false_rtx
;
5385 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5387 /* If everything is a comparison, what we have is highly unlikely
5388 to be simpler, so don't use it. */
5389 && ! (COMPARISON_P (x
)
5390 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5392 rtx cop1
= const0_rtx
;
5393 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5395 if (cond_code
== NE
&& COMPARISON_P (cond
))
5398 /* Simplify the alternative arms; this may collapse the true and
5399 false arms to store-flag values. Be careful to use copy_rtx
5400 here since true_rtx or false_rtx might share RTL with x as a
5401 result of the if_then_else_cond call above. */
5402 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5403 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5405 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5406 is unlikely to be simpler. */
5407 if (general_operand (true_rtx
, VOIDmode
)
5408 && general_operand (false_rtx
, VOIDmode
))
5410 enum rtx_code reversed
;
5412 /* Restarting if we generate a store-flag expression will cause
5413 us to loop. Just drop through in this case. */
5415 /* If the result values are STORE_FLAG_VALUE and zero, we can
5416 just make the comparison operation. */
5417 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5418 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5420 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5421 && ((reversed
= reversed_comparison_code_parts
5422 (cond_code
, cond
, cop1
, NULL
))
5424 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5427 /* Likewise, we can make the negate of a comparison operation
5428 if the result values are - STORE_FLAG_VALUE and zero. */
5429 else if (CONST_INT_P (true_rtx
)
5430 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5431 && false_rtx
== const0_rtx
)
5432 x
= simplify_gen_unary (NEG
, mode
,
5433 simplify_gen_relational (cond_code
,
5437 else if (CONST_INT_P (false_rtx
)
5438 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5439 && true_rtx
== const0_rtx
5440 && ((reversed
= reversed_comparison_code_parts
5441 (cond_code
, cond
, cop1
, NULL
))
5443 x
= simplify_gen_unary (NEG
, mode
,
5444 simplify_gen_relational (reversed
,
5449 return gen_rtx_IF_THEN_ELSE (mode
,
5450 simplify_gen_relational (cond_code
,
5455 true_rtx
, false_rtx
);
5457 code
= GET_CODE (x
);
5458 op0_mode
= VOIDmode
;
5463 /* Try to fold this expression in case we have constants that weren't
5466 switch (GET_RTX_CLASS (code
))
5469 if (op0_mode
== VOIDmode
)
5470 op0_mode
= GET_MODE (XEXP (x
, 0));
5471 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5474 case RTX_COMM_COMPARE
:
5476 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5477 if (cmp_mode
== VOIDmode
)
5479 cmp_mode
= GET_MODE (XEXP (x
, 1));
5480 if (cmp_mode
== VOIDmode
)
5481 cmp_mode
= op0_mode
;
5483 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5484 XEXP (x
, 0), XEXP (x
, 1));
5487 case RTX_COMM_ARITH
:
5489 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5491 case RTX_BITFIELD_OPS
:
5493 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5494 XEXP (x
, 1), XEXP (x
, 2));
5503 code
= GET_CODE (temp
);
5504 op0_mode
= VOIDmode
;
5505 mode
= GET_MODE (temp
);
5508 /* First see if we can apply the inverse distributive law. */
5509 if (code
== PLUS
|| code
== MINUS
5510 || code
== AND
|| code
== IOR
|| code
== XOR
)
5512 x
= apply_distributive_law (x
);
5513 code
= GET_CODE (x
);
5514 op0_mode
= VOIDmode
;
5517 /* If CODE is an associative operation not otherwise handled, see if we
5518 can associate some operands. This can win if they are constants or
5519 if they are logically related (i.e. (a & b) & a). */
5520 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5521 || code
== AND
|| code
== IOR
|| code
== XOR
5522 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5523 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5524 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5526 if (GET_CODE (XEXP (x
, 0)) == code
)
5528 rtx other
= XEXP (XEXP (x
, 0), 0);
5529 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5530 rtx inner_op1
= XEXP (x
, 1);
5533 /* Make sure we pass the constant operand if any as the second
5534 one if this is a commutative operation. */
5535 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5537 rtx tem
= inner_op0
;
5538 inner_op0
= inner_op1
;
5541 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5542 : code
== DIV
? MULT
5544 mode
, inner_op0
, inner_op1
);
5546 /* For commutative operations, try the other pair if that one
5548 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5550 other
= XEXP (XEXP (x
, 0), 1);
5551 inner
= simplify_binary_operation (code
, mode
,
5552 XEXP (XEXP (x
, 0), 0),
5557 return simplify_gen_binary (code
, mode
, other
, inner
);
5561 /* A little bit of algebraic simplification here. */
5565 /* Ensure that our address has any ASHIFTs converted to MULT in case
5566 address-recognizing predicates are called later. */
5567 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5568 SUBST (XEXP (x
, 0), temp
);
5572 if (op0_mode
== VOIDmode
)
5573 op0_mode
= GET_MODE (SUBREG_REG (x
));
5575 /* See if this can be moved to simplify_subreg. */
5576 if (CONSTANT_P (SUBREG_REG (x
))
5577 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5578 /* Don't call gen_lowpart if the inner mode
5579 is VOIDmode and we cannot simplify it, as SUBREG without
5580 inner mode is invalid. */
5581 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5582 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5583 return gen_lowpart (mode
, SUBREG_REG (x
));
5585 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5589 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5594 /* If op is known to have all lower bits zero, the result is zero. */
5596 && SCALAR_INT_MODE_P (mode
)
5597 && SCALAR_INT_MODE_P (op0_mode
)
5598 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5599 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5600 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5601 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5602 & GET_MODE_MASK (mode
)) == 0)
5603 return CONST0_RTX (mode
);
5606 /* Don't change the mode of the MEM if that would change the meaning
5608 if (MEM_P (SUBREG_REG (x
))
5609 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5610 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5611 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5612 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5614 /* Note that we cannot do any narrowing for non-constants since
5615 we might have been counting on using the fact that some bits were
5616 zero. We now do this in the SET. */
5621 temp
= expand_compound_operation (XEXP (x
, 0));
5623 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5624 replaced by (lshiftrt X C). This will convert
5625 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5627 if (GET_CODE (temp
) == ASHIFTRT
5628 && CONST_INT_P (XEXP (temp
, 1))
5629 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5630 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5631 INTVAL (XEXP (temp
, 1)));
5633 /* If X has only a single bit that might be nonzero, say, bit I, convert
5634 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5635 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5636 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5637 or a SUBREG of one since we'd be making the expression more
5638 complex if it was just a register. */
5641 && ! (GET_CODE (temp
) == SUBREG
5642 && REG_P (SUBREG_REG (temp
)))
5643 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5645 rtx temp1
= simplify_shift_const
5646 (NULL_RTX
, ASHIFTRT
, mode
,
5647 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5648 GET_MODE_PRECISION (mode
) - 1 - i
),
5649 GET_MODE_PRECISION (mode
) - 1 - i
);
5651 /* If all we did was surround TEMP with the two shifts, we
5652 haven't improved anything, so don't use it. Otherwise,
5653 we are better off with TEMP1. */
5654 if (GET_CODE (temp1
) != ASHIFTRT
5655 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5656 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5662 /* We can't handle truncation to a partial integer mode here
5663 because we don't know the real bitsize of the partial
5665 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5668 if (HWI_COMPUTABLE_MODE_P (mode
))
5670 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5671 GET_MODE_MASK (mode
), 0));
5673 /* We can truncate a constant value and return it. */
5674 if (CONST_INT_P (XEXP (x
, 0)))
5675 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5677 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5678 whose value is a comparison can be replaced with a subreg if
5679 STORE_FLAG_VALUE permits. */
5680 if (HWI_COMPUTABLE_MODE_P (mode
)
5681 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5682 && (temp
= get_last_value (XEXP (x
, 0)))
5683 && COMPARISON_P (temp
))
5684 return gen_lowpart (mode
, XEXP (x
, 0));
5688 /* (const (const X)) can become (const X). Do it this way rather than
5689 returning the inner CONST since CONST can be shared with a
5691 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5692 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5697 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5698 can add in an offset. find_split_point will split this address up
5699 again if it doesn't match. */
5700 if (GET_CODE (XEXP (x
, 0)) == HIGH
5701 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5707 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5708 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5709 bit-field and can be replaced by either a sign_extend or a
5710 sign_extract. The `and' may be a zero_extend and the two
5711 <c>, -<c> constants may be reversed. */
5712 if (GET_CODE (XEXP (x
, 0)) == XOR
5713 && CONST_INT_P (XEXP (x
, 1))
5714 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5715 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5716 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5717 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5718 && HWI_COMPUTABLE_MODE_P (mode
)
5719 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5720 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5721 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5722 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5723 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5724 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5725 == (unsigned int) i
+ 1))))
5726 return simplify_shift_const
5727 (NULL_RTX
, ASHIFTRT
, mode
,
5728 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5729 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5730 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5731 GET_MODE_PRECISION (mode
) - (i
+ 1));
5733 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5734 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5735 the bitsize of the mode - 1. This allows simplification of
5736 "a = (b & 8) == 0;" */
5737 if (XEXP (x
, 1) == constm1_rtx
5738 && !REG_P (XEXP (x
, 0))
5739 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5740 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5741 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5742 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5743 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5744 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5745 GET_MODE_PRECISION (mode
) - 1),
5746 GET_MODE_PRECISION (mode
) - 1);
5748 /* If we are adding two things that have no bits in common, convert
5749 the addition into an IOR. This will often be further simplified,
5750 for example in cases like ((a & 1) + (a & 2)), which can
5753 if (HWI_COMPUTABLE_MODE_P (mode
)
5754 && (nonzero_bits (XEXP (x
, 0), mode
)
5755 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5757 /* Try to simplify the expression further. */
5758 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5759 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5761 /* If we could, great. If not, do not go ahead with the IOR
5762 replacement, since PLUS appears in many special purpose
5763 address arithmetic instructions. */
5764 if (GET_CODE (temp
) != CLOBBER
5765 && (GET_CODE (temp
) != IOR
5766 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5767 || XEXP (temp
, 1) != XEXP (x
, 1))
5768 && (XEXP (temp
, 0) != XEXP (x
, 1)
5769 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5775 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5776 (and <foo> (const_int pow2-1)) */
5777 if (GET_CODE (XEXP (x
, 1)) == AND
5778 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5779 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5780 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5781 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5782 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5786 /* If we have (mult (plus A B) C), apply the distributive law and then
5787 the inverse distributive law to see if things simplify. This
5788 occurs mostly in addresses, often when unrolling loops. */
5790 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5792 rtx result
= distribute_and_simplify_rtx (x
, 0);
5797 /* Try simplify a*(b/c) as (a*b)/c. */
5798 if (FLOAT_MODE_P (mode
) && flag_associative_math
5799 && GET_CODE (XEXP (x
, 0)) == DIV
)
5801 rtx tem
= simplify_binary_operation (MULT
, mode
,
5802 XEXP (XEXP (x
, 0), 0),
5805 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5810 /* If this is a divide by a power of two, treat it as a shift if
5811 its first operand is a shift. */
5812 if (CONST_INT_P (XEXP (x
, 1))
5813 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5814 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5815 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5816 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5817 || GET_CODE (XEXP (x
, 0)) == ROTATE
5818 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5819 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5823 case GT
: case GTU
: case GE
: case GEU
:
5824 case LT
: case LTU
: case LE
: case LEU
:
5825 case UNEQ
: case LTGT
:
5826 case UNGT
: case UNGE
:
5827 case UNLT
: case UNLE
:
5828 case UNORDERED
: case ORDERED
:
5829 /* If the first operand is a condition code, we can't do anything
5831 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5832 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5833 && ! CC0_P (XEXP (x
, 0))))
5835 rtx op0
= XEXP (x
, 0);
5836 rtx op1
= XEXP (x
, 1);
5837 enum rtx_code new_code
;
5839 if (GET_CODE (op0
) == COMPARE
)
5840 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5842 /* Simplify our comparison, if possible. */
5843 new_code
= simplify_comparison (code
, &op0
, &op1
);
5845 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5846 if only the low-order bit is possibly nonzero in X (such as when
5847 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5848 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5849 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5852 Remove any ZERO_EXTRACT we made when thinking this was a
5853 comparison. It may now be simpler to use, e.g., an AND. If a
5854 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5855 the call to make_compound_operation in the SET case.
5857 Don't apply these optimizations if the caller would
5858 prefer a comparison rather than a value.
5859 E.g., for the condition in an IF_THEN_ELSE most targets need
5860 an explicit comparison. */
5865 else if (STORE_FLAG_VALUE
== 1
5866 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5867 && op1
== const0_rtx
5868 && mode
== GET_MODE (op0
)
5869 && nonzero_bits (op0
, mode
) == 1)
5870 return gen_lowpart (mode
,
5871 expand_compound_operation (op0
));
5873 else if (STORE_FLAG_VALUE
== 1
5874 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5875 && op1
== const0_rtx
5876 && mode
== GET_MODE (op0
)
5877 && (num_sign_bit_copies (op0
, mode
)
5878 == GET_MODE_PRECISION (mode
)))
5880 op0
= expand_compound_operation (op0
);
5881 return simplify_gen_unary (NEG
, mode
,
5882 gen_lowpart (mode
, op0
),
5886 else if (STORE_FLAG_VALUE
== 1
5887 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5888 && op1
== const0_rtx
5889 && mode
== GET_MODE (op0
)
5890 && nonzero_bits (op0
, mode
) == 1)
5892 op0
= expand_compound_operation (op0
);
5893 return simplify_gen_binary (XOR
, mode
,
5894 gen_lowpart (mode
, op0
),
5898 else if (STORE_FLAG_VALUE
== 1
5899 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5900 && op1
== const0_rtx
5901 && mode
== GET_MODE (op0
)
5902 && (num_sign_bit_copies (op0
, mode
)
5903 == GET_MODE_PRECISION (mode
)))
5905 op0
= expand_compound_operation (op0
);
5906 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5909 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5914 else if (STORE_FLAG_VALUE
== -1
5915 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5916 && op1
== const0_rtx
5917 && mode
== GET_MODE (op0
)
5918 && (num_sign_bit_copies (op0
, mode
)
5919 == GET_MODE_PRECISION (mode
)))
5920 return gen_lowpart (mode
,
5921 expand_compound_operation (op0
));
5923 else if (STORE_FLAG_VALUE
== -1
5924 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5925 && op1
== const0_rtx
5926 && mode
== GET_MODE (op0
)
5927 && nonzero_bits (op0
, mode
) == 1)
5929 op0
= expand_compound_operation (op0
);
5930 return simplify_gen_unary (NEG
, mode
,
5931 gen_lowpart (mode
, op0
),
5935 else if (STORE_FLAG_VALUE
== -1
5936 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5937 && op1
== const0_rtx
5938 && mode
== GET_MODE (op0
)
5939 && (num_sign_bit_copies (op0
, mode
)
5940 == GET_MODE_PRECISION (mode
)))
5942 op0
= expand_compound_operation (op0
);
5943 return simplify_gen_unary (NOT
, mode
,
5944 gen_lowpart (mode
, op0
),
5948 /* If X is 0/1, (eq X 0) is X-1. */
5949 else if (STORE_FLAG_VALUE
== -1
5950 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5951 && op1
== const0_rtx
5952 && mode
== GET_MODE (op0
)
5953 && nonzero_bits (op0
, mode
) == 1)
5955 op0
= expand_compound_operation (op0
);
5956 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5959 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5960 one bit that might be nonzero, we can convert (ne x 0) to
5961 (ashift x c) where C puts the bit in the sign bit. Remove any
5962 AND with STORE_FLAG_VALUE when we are done, since we are only
5963 going to test the sign bit. */
5964 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5965 && HWI_COMPUTABLE_MODE_P (mode
)
5966 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5967 && op1
== const0_rtx
5968 && mode
== GET_MODE (op0
)
5969 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5971 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5972 expand_compound_operation (op0
),
5973 GET_MODE_PRECISION (mode
) - 1 - i
);
5974 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5980 /* If the code changed, return a whole new comparison.
5981 We also need to avoid using SUBST in cases where
5982 simplify_comparison has widened a comparison with a CONST_INT,
5983 since in that case the wider CONST_INT may fail the sanity
5984 checks in do_SUBST. */
5985 if (new_code
!= code
5986 || (CONST_INT_P (op1
)
5987 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
5988 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
5989 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5991 /* Otherwise, keep this operation, but maybe change its operands.
5992 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5993 SUBST (XEXP (x
, 0), op0
);
5994 SUBST (XEXP (x
, 1), op1
);
5999 return simplify_if_then_else (x
);
6005 /* If we are processing SET_DEST, we are done. */
6009 return expand_compound_operation (x
);
6012 return simplify_set (x
);
6016 return simplify_logical (x
);
6023 /* If this is a shift by a constant amount, simplify it. */
6024 if (CONST_INT_P (XEXP (x
, 1)))
6025 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6026 INTVAL (XEXP (x
, 1)));
6028 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6030 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6031 ((unsigned HOST_WIDE_INT
) 1
6032 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6044 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6047 simplify_if_then_else (rtx x
)
6049 machine_mode mode
= GET_MODE (x
);
6050 rtx cond
= XEXP (x
, 0);
6051 rtx true_rtx
= XEXP (x
, 1);
6052 rtx false_rtx
= XEXP (x
, 2);
6053 enum rtx_code true_code
= GET_CODE (cond
);
6054 int comparison_p
= COMPARISON_P (cond
);
6057 enum rtx_code false_code
;
6060 /* Simplify storing of the truth value. */
6061 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6062 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6063 XEXP (cond
, 0), XEXP (cond
, 1));
6065 /* Also when the truth value has to be reversed. */
6067 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6068 && (reversed
= reversed_comparison (cond
, mode
)))
6071 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6072 in it is being compared against certain values. Get the true and false
6073 comparisons and see if that says anything about the value of each arm. */
6076 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6078 && REG_P (XEXP (cond
, 0)))
6081 rtx from
= XEXP (cond
, 0);
6082 rtx true_val
= XEXP (cond
, 1);
6083 rtx false_val
= true_val
;
6086 /* If FALSE_CODE is EQ, swap the codes and arms. */
6088 if (false_code
== EQ
)
6090 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6091 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6094 /* If we are comparing against zero and the expression being tested has
6095 only a single bit that might be nonzero, that is its value when it is
6096 not equal to zero. Similarly if it is known to be -1 or 0. */
6098 if (true_code
== EQ
&& true_val
== const0_rtx
6099 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
6102 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6104 else if (true_code
== EQ
&& true_val
== const0_rtx
6105 && (num_sign_bit_copies (from
, GET_MODE (from
))
6106 == GET_MODE_PRECISION (GET_MODE (from
))))
6109 false_val
= constm1_rtx
;
6112 /* Now simplify an arm if we know the value of the register in the
6113 branch and it is used in the arm. Be careful due to the potential
6114 of locally-shared RTL. */
6116 if (reg_mentioned_p (from
, true_rtx
))
6117 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6119 pc_rtx
, pc_rtx
, 0, 0, 0);
6120 if (reg_mentioned_p (from
, false_rtx
))
6121 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6123 pc_rtx
, pc_rtx
, 0, 0, 0);
6125 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6126 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6128 true_rtx
= XEXP (x
, 1);
6129 false_rtx
= XEXP (x
, 2);
6130 true_code
= GET_CODE (cond
);
6133 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6134 reversed, do so to avoid needing two sets of patterns for
6135 subtract-and-branch insns. Similarly if we have a constant in the true
6136 arm, the false arm is the same as the first operand of the comparison, or
6137 the false arm is more complicated than the true arm. */
6140 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6141 && (true_rtx
== pc_rtx
6142 || (CONSTANT_P (true_rtx
)
6143 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6144 || true_rtx
== const0_rtx
6145 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6146 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6147 && !OBJECT_P (false_rtx
))
6148 || reg_mentioned_p (true_rtx
, false_rtx
)
6149 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6151 true_code
= reversed_comparison_code (cond
, NULL
);
6152 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6153 SUBST (XEXP (x
, 1), false_rtx
);
6154 SUBST (XEXP (x
, 2), true_rtx
);
6156 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6159 /* It is possible that the conditional has been simplified out. */
6160 true_code
= GET_CODE (cond
);
6161 comparison_p
= COMPARISON_P (cond
);
6164 /* If the two arms are identical, we don't need the comparison. */
6166 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6169 /* Convert a == b ? b : a to "a". */
6170 if (true_code
== EQ
&& ! side_effects_p (cond
)
6171 && !HONOR_NANS (mode
)
6172 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6173 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6175 else if (true_code
== NE
&& ! side_effects_p (cond
)
6176 && !HONOR_NANS (mode
)
6177 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6178 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6181 /* Look for cases where we have (abs x) or (neg (abs X)). */
6183 if (GET_MODE_CLASS (mode
) == MODE_INT
6185 && XEXP (cond
, 1) == const0_rtx
6186 && GET_CODE (false_rtx
) == NEG
6187 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6188 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6189 && ! side_effects_p (true_rtx
))
6194 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6198 simplify_gen_unary (NEG
, mode
,
6199 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6205 /* Look for MIN or MAX. */
6207 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6209 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6210 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6211 && ! side_effects_p (cond
))
6216 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6219 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6222 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6225 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6230 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6231 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6232 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6233 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6234 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6235 neither 1 or -1, but it isn't worth checking for. */
6237 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6239 && GET_MODE_CLASS (mode
) == MODE_INT
6240 && ! side_effects_p (x
))
6242 rtx t
= make_compound_operation (true_rtx
, SET
);
6243 rtx f
= make_compound_operation (false_rtx
, SET
);
6244 rtx cond_op0
= XEXP (cond
, 0);
6245 rtx cond_op1
= XEXP (cond
, 1);
6246 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6247 machine_mode m
= mode
;
6248 rtx z
= 0, c1
= NULL_RTX
;
6250 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6251 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6252 || GET_CODE (t
) == ASHIFT
6253 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6254 && rtx_equal_p (XEXP (t
, 0), f
))
6255 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6257 /* If an identity-zero op is commutative, check whether there
6258 would be a match if we swapped the operands. */
6259 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6260 || GET_CODE (t
) == XOR
)
6261 && rtx_equal_p (XEXP (t
, 1), f
))
6262 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6263 else if (GET_CODE (t
) == SIGN_EXTEND
6264 && (GET_CODE (XEXP (t
, 0)) == PLUS
6265 || GET_CODE (XEXP (t
, 0)) == MINUS
6266 || GET_CODE (XEXP (t
, 0)) == IOR
6267 || GET_CODE (XEXP (t
, 0)) == XOR
6268 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6269 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6270 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6271 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6272 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6273 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6274 && (num_sign_bit_copies (f
, GET_MODE (f
))
6276 (GET_MODE_PRECISION (mode
)
6277 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6279 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6280 extend_op
= SIGN_EXTEND
;
6281 m
= GET_MODE (XEXP (t
, 0));
6283 else if (GET_CODE (t
) == SIGN_EXTEND
6284 && (GET_CODE (XEXP (t
, 0)) == PLUS
6285 || GET_CODE (XEXP (t
, 0)) == IOR
6286 || GET_CODE (XEXP (t
, 0)) == XOR
)
6287 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6288 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6289 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6290 && (num_sign_bit_copies (f
, GET_MODE (f
))
6292 (GET_MODE_PRECISION (mode
)
6293 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6295 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6296 extend_op
= SIGN_EXTEND
;
6297 m
= GET_MODE (XEXP (t
, 0));
6299 else if (GET_CODE (t
) == ZERO_EXTEND
6300 && (GET_CODE (XEXP (t
, 0)) == PLUS
6301 || GET_CODE (XEXP (t
, 0)) == MINUS
6302 || GET_CODE (XEXP (t
, 0)) == IOR
6303 || GET_CODE (XEXP (t
, 0)) == XOR
6304 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6305 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6306 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6307 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6308 && HWI_COMPUTABLE_MODE_P (mode
)
6309 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6310 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6311 && ((nonzero_bits (f
, GET_MODE (f
))
6312 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6315 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6316 extend_op
= ZERO_EXTEND
;
6317 m
= GET_MODE (XEXP (t
, 0));
6319 else if (GET_CODE (t
) == ZERO_EXTEND
6320 && (GET_CODE (XEXP (t
, 0)) == PLUS
6321 || GET_CODE (XEXP (t
, 0)) == IOR
6322 || GET_CODE (XEXP (t
, 0)) == XOR
)
6323 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6324 && HWI_COMPUTABLE_MODE_P (mode
)
6325 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6326 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6327 && ((nonzero_bits (f
, GET_MODE (f
))
6328 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6331 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6332 extend_op
= ZERO_EXTEND
;
6333 m
= GET_MODE (XEXP (t
, 0));
6338 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6339 cond_op0
, cond_op1
),
6340 pc_rtx
, pc_rtx
, 0, 0, 0);
6341 temp
= simplify_gen_binary (MULT
, m
, temp
,
6342 simplify_gen_binary (MULT
, m
, c1
,
6344 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6345 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6347 if (extend_op
!= UNKNOWN
)
6348 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6354 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6355 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6356 negation of a single bit, we can convert this operation to a shift. We
6357 can actually do this more generally, but it doesn't seem worth it. */
6359 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6360 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6361 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6362 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6363 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6364 == GET_MODE_PRECISION (mode
))
6365 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6367 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6368 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6370 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6371 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6372 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6373 && GET_MODE (XEXP (cond
, 0)) == mode
6374 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6375 == nonzero_bits (XEXP (cond
, 0), mode
)
6376 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6377 return XEXP (cond
, 0);
6382 /* Simplify X, a SET expression. Return the new expression. */
6385 simplify_set (rtx x
)
6387 rtx src
= SET_SRC (x
);
6388 rtx dest
= SET_DEST (x
);
6390 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6391 rtx_insn
*other_insn
;
6394 /* (set (pc) (return)) gets written as (return). */
6395 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6398 /* Now that we know for sure which bits of SRC we are using, see if we can
6399 simplify the expression for the object knowing that we only need the
6402 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6404 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6405 SUBST (SET_SRC (x
), src
);
6408 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6409 the comparison result and try to simplify it unless we already have used
6410 undobuf.other_insn. */
6411 if ((GET_MODE_CLASS (mode
) == MODE_CC
6412 || GET_CODE (src
) == COMPARE
6414 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6415 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6416 && COMPARISON_P (*cc_use
)
6417 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6419 enum rtx_code old_code
= GET_CODE (*cc_use
);
6420 enum rtx_code new_code
;
6422 int other_changed
= 0;
6423 rtx inner_compare
= NULL_RTX
;
6424 machine_mode compare_mode
= GET_MODE (dest
);
6426 if (GET_CODE (src
) == COMPARE
)
6428 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6429 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6431 inner_compare
= op0
;
6432 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6436 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6438 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6441 new_code
= old_code
;
6442 else if (!CONSTANT_P (tmp
))
6444 new_code
= GET_CODE (tmp
);
6445 op0
= XEXP (tmp
, 0);
6446 op1
= XEXP (tmp
, 1);
6450 rtx pat
= PATTERN (other_insn
);
6451 undobuf
.other_insn
= other_insn
;
6452 SUBST (*cc_use
, tmp
);
6454 /* Attempt to simplify CC user. */
6455 if (GET_CODE (pat
) == SET
)
6457 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6458 if (new_rtx
!= NULL_RTX
)
6459 SUBST (SET_SRC (pat
), new_rtx
);
6462 /* Convert X into a no-op move. */
6463 SUBST (SET_DEST (x
), pc_rtx
);
6464 SUBST (SET_SRC (x
), pc_rtx
);
6468 /* Simplify our comparison, if possible. */
6469 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6471 #ifdef SELECT_CC_MODE
6472 /* If this machine has CC modes other than CCmode, check to see if we
6473 need to use a different CC mode here. */
6474 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6475 compare_mode
= GET_MODE (op0
);
6476 else if (inner_compare
6477 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6478 && new_code
== old_code
6479 && op0
== XEXP (inner_compare
, 0)
6480 && op1
== XEXP (inner_compare
, 1))
6481 compare_mode
= GET_MODE (inner_compare
);
6483 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6486 /* If the mode changed, we have to change SET_DEST, the mode in the
6487 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6488 a hard register, just build new versions with the proper mode. If it
6489 is a pseudo, we lose unless it is only time we set the pseudo, in
6490 which case we can safely change its mode. */
6491 if (compare_mode
!= GET_MODE (dest
))
6493 if (can_change_dest_mode (dest
, 0, compare_mode
))
6495 unsigned int regno
= REGNO (dest
);
6498 if (regno
< FIRST_PSEUDO_REGISTER
)
6499 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6502 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6503 new_dest
= regno_reg_rtx
[regno
];
6506 SUBST (SET_DEST (x
), new_dest
);
6507 SUBST (XEXP (*cc_use
, 0), new_dest
);
6514 #endif /* SELECT_CC_MODE */
6516 /* If the code changed, we have to build a new comparison in
6517 undobuf.other_insn. */
6518 if (new_code
!= old_code
)
6520 int other_changed_previously
= other_changed
;
6521 unsigned HOST_WIDE_INT mask
;
6522 rtx old_cc_use
= *cc_use
;
6524 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6528 /* If the only change we made was to change an EQ into an NE or
6529 vice versa, OP0 has only one bit that might be nonzero, and OP1
6530 is zero, check if changing the user of the condition code will
6531 produce a valid insn. If it won't, we can keep the original code
6532 in that insn by surrounding our operation with an XOR. */
6534 if (((old_code
== NE
&& new_code
== EQ
)
6535 || (old_code
== EQ
&& new_code
== NE
))
6536 && ! other_changed_previously
&& op1
== const0_rtx
6537 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6538 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6540 rtx pat
= PATTERN (other_insn
), note
= 0;
6542 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6543 && ! check_asm_operands (pat
)))
6545 *cc_use
= old_cc_use
;
6548 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6556 undobuf
.other_insn
= other_insn
;
6558 /* Otherwise, if we didn't previously have a COMPARE in the
6559 correct mode, we need one. */
6560 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6562 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6565 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6567 SUBST (SET_SRC (x
), op0
);
6570 /* Otherwise, update the COMPARE if needed. */
6571 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6573 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6579 /* Get SET_SRC in a form where we have placed back any
6580 compound expressions. Then do the checks below. */
6581 src
= make_compound_operation (src
, SET
);
6582 SUBST (SET_SRC (x
), src
);
6585 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6586 and X being a REG or (subreg (reg)), we may be able to convert this to
6587 (set (subreg:m2 x) (op)).
6589 We can always do this if M1 is narrower than M2 because that means that
6590 we only care about the low bits of the result.
6592 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6593 perform a narrower operation than requested since the high-order bits will
6594 be undefined. On machine where it is defined, this transformation is safe
6595 as long as M1 and M2 have the same number of words. */
6597 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6598 && !OBJECT_P (SUBREG_REG (src
))
6599 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6601 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6602 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6603 #ifndef WORD_REGISTER_OPERATIONS
6604 && (GET_MODE_SIZE (GET_MODE (src
))
6605 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6607 #ifdef CANNOT_CHANGE_MODE_CLASS
6608 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6609 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6610 GET_MODE (SUBREG_REG (src
)),
6614 || (GET_CODE (dest
) == SUBREG
6615 && REG_P (SUBREG_REG (dest
)))))
6617 SUBST (SET_DEST (x
),
6618 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6620 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6622 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6626 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6629 && GET_CODE (src
) == SUBREG
6630 && subreg_lowpart_p (src
)
6631 && (GET_MODE_PRECISION (GET_MODE (src
))
6632 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6634 rtx inner
= SUBREG_REG (src
);
6635 machine_mode inner_mode
= GET_MODE (inner
);
6637 /* Here we make sure that we don't have a sign bit on. */
6638 if (val_signbit_known_clear_p (GET_MODE (src
),
6639 nonzero_bits (inner
, inner_mode
)))
6641 SUBST (SET_SRC (x
), inner
);
6647 #ifdef LOAD_EXTEND_OP
6648 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6649 would require a paradoxical subreg. Replace the subreg with a
6650 zero_extend to avoid the reload that would otherwise be required. */
6652 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6653 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6654 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6655 && SUBREG_BYTE (src
) == 0
6656 && paradoxical_subreg_p (src
)
6657 && MEM_P (SUBREG_REG (src
)))
6660 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6661 GET_MODE (src
), SUBREG_REG (src
)));
6667 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6668 are comparing an item known to be 0 or -1 against 0, use a logical
6669 operation instead. Check for one of the arms being an IOR of the other
6670 arm with some value. We compute three terms to be IOR'ed together. In
6671 practice, at most two will be nonzero. Then we do the IOR's. */
6673 if (GET_CODE (dest
) != PC
6674 && GET_CODE (src
) == IF_THEN_ELSE
6675 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6676 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6677 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6678 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6679 #ifdef HAVE_conditional_move
6680 && ! can_conditionally_move_p (GET_MODE (src
))
6682 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6683 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6684 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6685 && ! side_effects_p (src
))
6687 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6688 ? XEXP (src
, 1) : XEXP (src
, 2));
6689 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6690 ? XEXP (src
, 2) : XEXP (src
, 1));
6691 rtx term1
= const0_rtx
, term2
, term3
;
6693 if (GET_CODE (true_rtx
) == IOR
6694 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6695 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6696 else if (GET_CODE (true_rtx
) == IOR
6697 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6698 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6699 else if (GET_CODE (false_rtx
) == IOR
6700 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6701 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6702 else if (GET_CODE (false_rtx
) == IOR
6703 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6704 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6706 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6707 XEXP (XEXP (src
, 0), 0), true_rtx
);
6708 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6709 simplify_gen_unary (NOT
, GET_MODE (src
),
6710 XEXP (XEXP (src
, 0), 0),
6715 simplify_gen_binary (IOR
, GET_MODE (src
),
6716 simplify_gen_binary (IOR
, GET_MODE (src
),
6723 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6724 whole thing fail. */
6725 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6727 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6730 /* Convert this into a field assignment operation, if possible. */
6731 return make_field_assignment (x
);
6734 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6738 simplify_logical (rtx x
)
6740 machine_mode mode
= GET_MODE (x
);
6741 rtx op0
= XEXP (x
, 0);
6742 rtx op1
= XEXP (x
, 1);
6744 switch (GET_CODE (x
))
6747 /* We can call simplify_and_const_int only if we don't lose
6748 any (sign) bits when converting INTVAL (op1) to
6749 "unsigned HOST_WIDE_INT". */
6750 if (CONST_INT_P (op1
)
6751 && (HWI_COMPUTABLE_MODE_P (mode
)
6752 || INTVAL (op1
) > 0))
6754 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6755 if (GET_CODE (x
) != AND
)
6762 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6763 apply the distributive law and then the inverse distributive
6764 law to see if things simplify. */
6765 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6767 rtx result
= distribute_and_simplify_rtx (x
, 0);
6771 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6773 rtx result
= distribute_and_simplify_rtx (x
, 1);
6780 /* If we have (ior (and A B) C), apply the distributive law and then
6781 the inverse distributive law to see if things simplify. */
6783 if (GET_CODE (op0
) == AND
)
6785 rtx result
= distribute_and_simplify_rtx (x
, 0);
6790 if (GET_CODE (op1
) == AND
)
6792 rtx result
= distribute_and_simplify_rtx (x
, 1);
6805 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6806 operations" because they can be replaced with two more basic operations.
6807 ZERO_EXTEND is also considered "compound" because it can be replaced with
6808 an AND operation, which is simpler, though only one operation.
6810 The function expand_compound_operation is called with an rtx expression
6811 and will convert it to the appropriate shifts and AND operations,
6812 simplifying at each stage.
6814 The function make_compound_operation is called to convert an expression
6815 consisting of shifts and ANDs into the equivalent compound expression.
6816 It is the inverse of this function, loosely speaking. */
6819 expand_compound_operation (rtx x
)
6821 unsigned HOST_WIDE_INT pos
= 0, len
;
6823 unsigned int modewidth
;
6826 switch (GET_CODE (x
))
6831 /* We can't necessarily use a const_int for a multiword mode;
6832 it depends on implicitly extending the value.
6833 Since we don't know the right way to extend it,
6834 we can't tell whether the implicit way is right.
6836 Even for a mode that is no wider than a const_int,
6837 we can't win, because we need to sign extend one of its bits through
6838 the rest of it, and we don't know which bit. */
6839 if (CONST_INT_P (XEXP (x
, 0)))
6842 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6843 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6844 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6845 reloaded. If not for that, MEM's would very rarely be safe.
6847 Reject MODEs bigger than a word, because we might not be able
6848 to reference a two-register group starting with an arbitrary register
6849 (and currently gen_lowpart might crash for a SUBREG). */
6851 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6854 /* Reject MODEs that aren't scalar integers because turning vector
6855 or complex modes into shifts causes problems. */
6857 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6860 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6861 /* If the inner object has VOIDmode (the only way this can happen
6862 is if it is an ASM_OPERANDS), we can't do anything since we don't
6863 know how much masking to do. */
6872 /* ... fall through ... */
6875 /* If the operand is a CLOBBER, just return it. */
6876 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6879 if (!CONST_INT_P (XEXP (x
, 1))
6880 || !CONST_INT_P (XEXP (x
, 2))
6881 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6884 /* Reject MODEs that aren't scalar integers because turning vector
6885 or complex modes into shifts causes problems. */
6887 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6890 len
= INTVAL (XEXP (x
, 1));
6891 pos
= INTVAL (XEXP (x
, 2));
6893 /* This should stay within the object being extracted, fail otherwise. */
6894 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6897 if (BITS_BIG_ENDIAN
)
6898 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6905 /* Convert sign extension to zero extension, if we know that the high
6906 bit is not set, as this is easier to optimize. It will be converted
6907 back to cheaper alternative in make_extraction. */
6908 if (GET_CODE (x
) == SIGN_EXTEND
6909 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6910 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6911 & ~(((unsigned HOST_WIDE_INT
)
6912 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6916 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6917 rtx temp2
= expand_compound_operation (temp
);
6919 /* Make sure this is a profitable operation. */
6920 if (set_src_cost (x
, optimize_this_for_speed_p
)
6921 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6923 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6924 > set_src_cost (temp
, optimize_this_for_speed_p
))
6930 /* We can optimize some special cases of ZERO_EXTEND. */
6931 if (GET_CODE (x
) == ZERO_EXTEND
)
6933 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6934 know that the last value didn't have any inappropriate bits
6936 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6937 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6938 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6939 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6940 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6941 return XEXP (XEXP (x
, 0), 0);
6943 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6944 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6945 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6946 && subreg_lowpart_p (XEXP (x
, 0))
6947 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6948 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6949 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6950 return SUBREG_REG (XEXP (x
, 0));
6952 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6953 is a comparison and STORE_FLAG_VALUE permits. This is like
6954 the first case, but it works even when GET_MODE (x) is larger
6955 than HOST_WIDE_INT. */
6956 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6957 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6958 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6959 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6960 <= HOST_BITS_PER_WIDE_INT
)
6961 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6962 return XEXP (XEXP (x
, 0), 0);
6964 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6965 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6966 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6967 && subreg_lowpart_p (XEXP (x
, 0))
6968 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6969 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6970 <= HOST_BITS_PER_WIDE_INT
)
6971 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6972 return SUBREG_REG (XEXP (x
, 0));
6976 /* If we reach here, we want to return a pair of shifts. The inner
6977 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6978 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6979 logical depending on the value of UNSIGNEDP.
6981 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6982 converted into an AND of a shift.
6984 We must check for the case where the left shift would have a negative
6985 count. This can happen in a case like (x >> 31) & 255 on machines
6986 that can't shift by a constant. On those machines, we would first
6987 combine the shift with the AND to produce a variable-position
6988 extraction. Then the constant of 31 would be substituted in
6989 to produce such a position. */
6991 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6992 if (modewidth
>= pos
+ len
)
6994 machine_mode mode
= GET_MODE (x
);
6995 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6996 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6998 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6999 tem
, modewidth
- pos
- len
);
7000 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7001 mode
, tem
, modewidth
- len
);
7003 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7004 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7005 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7008 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
7010 /* Any other cases we can't handle. */
7013 /* If we couldn't do this for some reason, return the original
7015 if (GET_CODE (tem
) == CLOBBER
)
7021 /* X is a SET which contains an assignment of one object into
7022 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7023 or certain SUBREGS). If possible, convert it into a series of
7026 We half-heartedly support variable positions, but do not at all
7027 support variable lengths. */
7030 expand_field_assignment (const_rtx x
)
7033 rtx pos
; /* Always counts from low bit. */
7035 rtx mask
, cleared
, masked
;
7036 machine_mode compute_mode
;
7038 /* Loop until we find something we can't simplify. */
7041 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7042 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7044 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7045 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7046 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7048 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7049 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7051 inner
= XEXP (SET_DEST (x
), 0);
7052 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7053 pos
= XEXP (SET_DEST (x
), 2);
7055 /* A constant position should stay within the width of INNER. */
7056 if (CONST_INT_P (pos
)
7057 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7060 if (BITS_BIG_ENDIAN
)
7062 if (CONST_INT_P (pos
))
7063 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7065 else if (GET_CODE (pos
) == MINUS
7066 && CONST_INT_P (XEXP (pos
, 1))
7067 && (INTVAL (XEXP (pos
, 1))
7068 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7069 /* If position is ADJUST - X, new position is X. */
7070 pos
= XEXP (pos
, 0);
7073 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7074 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7075 gen_int_mode (prec
- len
,
7082 /* A SUBREG between two modes that occupy the same numbers of words
7083 can be done by moving the SUBREG to the source. */
7084 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7085 /* We need SUBREGs to compute nonzero_bits properly. */
7086 && nonzero_sign_valid
7087 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7088 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7089 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7090 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7092 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
7094 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7101 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7102 inner
= SUBREG_REG (inner
);
7104 compute_mode
= GET_MODE (inner
);
7106 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7107 if (! SCALAR_INT_MODE_P (compute_mode
))
7111 /* Don't do anything for vector or complex integral types. */
7112 if (! FLOAT_MODE_P (compute_mode
))
7115 /* Try to find an integral mode to pun with. */
7116 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7117 if (imode
== BLKmode
)
7120 compute_mode
= imode
;
7121 inner
= gen_lowpart (imode
, inner
);
7124 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7125 if (len
>= HOST_BITS_PER_WIDE_INT
)
7128 /* Now compute the equivalent expression. Make a copy of INNER
7129 for the SET_DEST in case it is a MEM into which we will substitute;
7130 we don't want shared RTL in that case. */
7131 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7133 cleared
= simplify_gen_binary (AND
, compute_mode
,
7134 simplify_gen_unary (NOT
, compute_mode
,
7135 simplify_gen_binary (ASHIFT
,
7140 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7141 simplify_gen_binary (
7143 gen_lowpart (compute_mode
, SET_SRC (x
)),
7147 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
7148 simplify_gen_binary (IOR
, compute_mode
,
7155 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7156 it is an RTX that represents the (variable) starting position; otherwise,
7157 POS is the (constant) starting bit position. Both are counted from the LSB.
7159 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7161 IN_DEST is nonzero if this is a reference in the destination of a SET.
7162 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7163 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7166 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7167 ZERO_EXTRACT should be built even for bits starting at bit 0.
7169 MODE is the desired mode of the result (if IN_DEST == 0).
7171 The result is an RTX for the extraction or NULL_RTX if the target
7175 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7176 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7177 int in_dest
, int in_compare
)
7179 /* This mode describes the size of the storage area
7180 to fetch the overall value from. Within that, we
7181 ignore the POS lowest bits, etc. */
7182 machine_mode is_mode
= GET_MODE (inner
);
7183 machine_mode inner_mode
;
7184 machine_mode wanted_inner_mode
;
7185 machine_mode wanted_inner_reg_mode
= word_mode
;
7186 machine_mode pos_mode
= word_mode
;
7187 machine_mode extraction_mode
= word_mode
;
7188 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7190 rtx orig_pos_rtx
= pos_rtx
;
7191 HOST_WIDE_INT orig_pos
;
7193 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7194 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7196 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7198 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7199 consider just the QI as the memory to extract from.
7200 The subreg adds or removes high bits; its mode is
7201 irrelevant to the meaning of this extraction,
7202 since POS and LEN count from the lsb. */
7203 if (MEM_P (SUBREG_REG (inner
)))
7204 is_mode
= GET_MODE (SUBREG_REG (inner
));
7205 inner
= SUBREG_REG (inner
);
7207 else if (GET_CODE (inner
) == ASHIFT
7208 && CONST_INT_P (XEXP (inner
, 1))
7209 && pos_rtx
== 0 && pos
== 0
7210 && len
> UINTVAL (XEXP (inner
, 1)))
7212 /* We're extracting the least significant bits of an rtx
7213 (ashift X (const_int C)), where LEN > C. Extract the
7214 least significant (LEN - C) bits of X, giving an rtx
7215 whose mode is MODE, then shift it left C times. */
7216 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7217 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7218 unsignedp
, in_dest
, in_compare
);
7220 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7222 else if (GET_CODE (inner
) == TRUNCATE
)
7223 inner
= XEXP (inner
, 0);
7225 inner_mode
= GET_MODE (inner
);
7227 /* See if this can be done without an extraction. We never can if the
7228 width of the field is not the same as that of some integer mode. For
7229 registers, we can only avoid the extraction if the position is at the
7230 low-order bit and this is either not in the destination or we have the
7231 appropriate STRICT_LOW_PART operation available.
7233 For MEM, we can avoid an extract if the field starts on an appropriate
7234 boundary and we can change the mode of the memory reference. */
7236 if (tmode
!= BLKmode
7237 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7239 && (inner_mode
== tmode
7241 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7242 || reg_truncated_to_mode (tmode
, inner
))
7245 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7246 || (MEM_P (inner
) && pos_rtx
== 0
7248 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7249 : BITS_PER_UNIT
)) == 0
7250 /* We can't do this if we are widening INNER_MODE (it
7251 may not be aligned, for one thing). */
7252 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7253 && (inner_mode
== tmode
7254 || (! mode_dependent_address_p (XEXP (inner
, 0),
7255 MEM_ADDR_SPACE (inner
))
7256 && ! MEM_VOLATILE_P (inner
))))))
7258 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7259 field. If the original and current mode are the same, we need not
7260 adjust the offset. Otherwise, we do if bytes big endian.
7262 If INNER is not a MEM, get a piece consisting of just the field
7263 of interest (in this case POS % BITS_PER_WORD must be 0). */
7267 HOST_WIDE_INT offset
;
7269 /* POS counts from lsb, but make OFFSET count in memory order. */
7270 if (BYTES_BIG_ENDIAN
)
7271 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7273 offset
= pos
/ BITS_PER_UNIT
;
7275 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7277 else if (REG_P (inner
))
7279 if (tmode
!= inner_mode
)
7281 /* We can't call gen_lowpart in a DEST since we
7282 always want a SUBREG (see below) and it would sometimes
7283 return a new hard register. */
7286 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7288 if (WORDS_BIG_ENDIAN
7289 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7290 final_word
= ((GET_MODE_SIZE (inner_mode
)
7291 - GET_MODE_SIZE (tmode
))
7292 / UNITS_PER_WORD
) - final_word
;
7294 final_word
*= UNITS_PER_WORD
;
7295 if (BYTES_BIG_ENDIAN
&&
7296 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7297 final_word
+= (GET_MODE_SIZE (inner_mode
)
7298 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7300 /* Avoid creating invalid subregs, for example when
7301 simplifying (x>>32)&255. */
7302 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7305 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7308 new_rtx
= gen_lowpart (tmode
, inner
);
7314 new_rtx
= force_to_mode (inner
, tmode
,
7315 len
>= HOST_BITS_PER_WIDE_INT
7316 ? ~(unsigned HOST_WIDE_INT
) 0
7317 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7320 /* If this extraction is going into the destination of a SET,
7321 make a STRICT_LOW_PART unless we made a MEM. */
7324 return (MEM_P (new_rtx
) ? new_rtx
7325 : (GET_CODE (new_rtx
) != SUBREG
7326 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7327 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7332 if (CONST_SCALAR_INT_P (new_rtx
))
7333 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7334 mode
, new_rtx
, tmode
);
7336 /* If we know that no extraneous bits are set, and that the high
7337 bit is not set, convert the extraction to the cheaper of
7338 sign and zero extension, that are equivalent in these cases. */
7339 if (flag_expensive_optimizations
7340 && (HWI_COMPUTABLE_MODE_P (tmode
)
7341 && ((nonzero_bits (new_rtx
, tmode
)
7342 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7345 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7346 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7348 /* Prefer ZERO_EXTENSION, since it gives more information to
7350 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7351 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7356 /* Otherwise, sign- or zero-extend unless we already are in the
7359 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7363 /* Unless this is a COMPARE or we have a funny memory reference,
7364 don't do anything with zero-extending field extracts starting at
7365 the low-order bit since they are simple AND operations. */
7366 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7367 && ! in_compare
&& unsignedp
)
7370 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7371 if the position is not a constant and the length is not 1. In all
7372 other cases, we would only be going outside our object in cases when
7373 an original shift would have been undefined. */
7375 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7376 || (pos_rtx
!= 0 && len
!= 1)))
7379 enum extraction_pattern pattern
= (in_dest
? EP_insv
7380 : unsignedp
? EP_extzv
: EP_extv
);
7382 /* If INNER is not from memory, we want it to have the mode of a register
7383 extraction pattern's structure operand, or word_mode if there is no
7384 such pattern. The same applies to extraction_mode and pos_mode
7385 and their respective operands.
7387 For memory, assume that the desired extraction_mode and pos_mode
7388 are the same as for a register operation, since at present we don't
7389 have named patterns for aligned memory structures. */
7390 struct extraction_insn insn
;
7391 if (get_best_reg_extraction_insn (&insn
, pattern
,
7392 GET_MODE_BITSIZE (inner_mode
), mode
))
7394 wanted_inner_reg_mode
= insn
.struct_mode
;
7395 pos_mode
= insn
.pos_mode
;
7396 extraction_mode
= insn
.field_mode
;
7399 /* Never narrow an object, since that might not be safe. */
7401 if (mode
!= VOIDmode
7402 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7403 extraction_mode
= mode
;
7406 wanted_inner_mode
= wanted_inner_reg_mode
;
7409 /* Be careful not to go beyond the extracted object and maintain the
7410 natural alignment of the memory. */
7411 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7412 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7413 > GET_MODE_BITSIZE (wanted_inner_mode
))
7415 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7416 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7422 if (BITS_BIG_ENDIAN
)
7424 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7425 BITS_BIG_ENDIAN style. If position is constant, compute new
7426 position. Otherwise, build subtraction.
7427 Note that POS is relative to the mode of the original argument.
7428 If it's a MEM we need to recompute POS relative to that.
7429 However, if we're extracting from (or inserting into) a register,
7430 we want to recompute POS relative to wanted_inner_mode. */
7431 int width
= (MEM_P (inner
)
7432 ? GET_MODE_BITSIZE (is_mode
)
7433 : GET_MODE_BITSIZE (wanted_inner_mode
));
7436 pos
= width
- len
- pos
;
7439 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7440 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7442 /* POS may be less than 0 now, but we check for that below.
7443 Note that it can only be less than 0 if !MEM_P (inner). */
7446 /* If INNER has a wider mode, and this is a constant extraction, try to
7447 make it smaller and adjust the byte to point to the byte containing
7449 if (wanted_inner_mode
!= VOIDmode
7450 && inner_mode
!= wanted_inner_mode
7452 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7454 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7455 && ! MEM_VOLATILE_P (inner
))
7459 /* The computations below will be correct if the machine is big
7460 endian in both bits and bytes or little endian in bits and bytes.
7461 If it is mixed, we must adjust. */
7463 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7464 adjust OFFSET to compensate. */
7465 if (BYTES_BIG_ENDIAN
7466 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7467 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7469 /* We can now move to the desired byte. */
7470 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7471 * GET_MODE_SIZE (wanted_inner_mode
);
7472 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7474 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7475 && is_mode
!= wanted_inner_mode
)
7476 offset
= (GET_MODE_SIZE (is_mode
)
7477 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7479 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7482 /* If INNER is not memory, get it into the proper mode. If we are changing
7483 its mode, POS must be a constant and smaller than the size of the new
7485 else if (!MEM_P (inner
))
7487 /* On the LHS, don't create paradoxical subregs implicitely truncating
7488 the register unless TRULY_NOOP_TRUNCATION. */
7490 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7494 if (GET_MODE (inner
) != wanted_inner_mode
7496 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7502 inner
= force_to_mode (inner
, wanted_inner_mode
,
7504 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7505 ? ~(unsigned HOST_WIDE_INT
) 0
7506 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7511 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7512 have to zero extend. Otherwise, we can just use a SUBREG. */
7514 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7516 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7517 GET_MODE (pos_rtx
));
7519 /* If we know that no extraneous bits are set, and that the high
7520 bit is not set, convert extraction to cheaper one - either
7521 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7523 if (flag_expensive_optimizations
7524 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7525 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7526 & ~(((unsigned HOST_WIDE_INT
)
7527 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7531 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7532 GET_MODE (pos_rtx
));
7534 /* Prefer ZERO_EXTENSION, since it gives more information to
7536 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7537 < set_src_cost (temp
, optimize_this_for_speed_p
))
7543 /* Make POS_RTX unless we already have it and it is correct. If we don't
7544 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7546 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7547 pos_rtx
= orig_pos_rtx
;
7549 else if (pos_rtx
== 0)
7550 pos_rtx
= GEN_INT (pos
);
7552 /* Make the required operation. See if we can use existing rtx. */
7553 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7554 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7556 new_rtx
= gen_lowpart (mode
, new_rtx
);
7561 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7562 with any other operations in X. Return X without that shift if so. */
7565 extract_left_shift (rtx x
, int count
)
7567 enum rtx_code code
= GET_CODE (x
);
7568 machine_mode mode
= GET_MODE (x
);
7574 /* This is the shift itself. If it is wide enough, we will return
7575 either the value being shifted if the shift count is equal to
7576 COUNT or a shift for the difference. */
7577 if (CONST_INT_P (XEXP (x
, 1))
7578 && INTVAL (XEXP (x
, 1)) >= count
)
7579 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7580 INTVAL (XEXP (x
, 1)) - count
);
7584 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7585 return simplify_gen_unary (code
, mode
, tem
, mode
);
7589 case PLUS
: case IOR
: case XOR
: case AND
:
7590 /* If we can safely shift this constant and we find the inner shift,
7591 make a new operation. */
7592 if (CONST_INT_P (XEXP (x
, 1))
7593 && (UINTVAL (XEXP (x
, 1))
7594 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7595 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7597 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7598 return simplify_gen_binary (code
, mode
, tem
,
7599 gen_int_mode (val
, mode
));
7610 /* Look at the expression rooted at X. Look for expressions
7611 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7612 Form these expressions.
7614 Return the new rtx, usually just X.
7616 Also, for machines like the VAX that don't have logical shift insns,
7617 try to convert logical to arithmetic shift operations in cases where
7618 they are equivalent. This undoes the canonicalizations to logical
7619 shifts done elsewhere.
7621 We try, as much as possible, to re-use rtl expressions to save memory.
7623 IN_CODE says what kind of expression we are processing. Normally, it is
7624 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7625 being kludges), it is MEM. When processing the arguments of a comparison
7626 or a COMPARE against zero, it is COMPARE. */
7629 make_compound_operation (rtx x
, enum rtx_code in_code
)
7631 enum rtx_code code
= GET_CODE (x
);
7632 machine_mode mode
= GET_MODE (x
);
7633 int mode_width
= GET_MODE_PRECISION (mode
);
7635 enum rtx_code next_code
;
7641 /* Select the code to be used in recursive calls. Once we are inside an
7642 address, we stay there. If we have a comparison, set to COMPARE,
7643 but once inside, go back to our default of SET. */
7645 next_code
= (code
== MEM
? MEM
7646 : ((code
== PLUS
|| code
== MINUS
)
7647 && SCALAR_INT_MODE_P (mode
)) ? MEM
7648 : ((code
== COMPARE
|| COMPARISON_P (x
))
7649 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7650 : in_code
== COMPARE
? SET
: in_code
);
7652 /* Process depending on the code of this operation. If NEW is set
7653 nonzero, it will be returned. */
7658 /* Convert shifts by constants into multiplications if inside
7660 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7661 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7662 && INTVAL (XEXP (x
, 1)) >= 0
7663 && SCALAR_INT_MODE_P (mode
))
7665 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7666 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7668 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7669 if (GET_CODE (new_rtx
) == NEG
)
7671 new_rtx
= XEXP (new_rtx
, 0);
7674 multval
= trunc_int_for_mode (multval
, mode
);
7675 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7682 lhs
= make_compound_operation (lhs
, next_code
);
7683 rhs
= make_compound_operation (rhs
, next_code
);
7684 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7685 && SCALAR_INT_MODE_P (mode
))
7687 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7689 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7691 else if (GET_CODE (lhs
) == MULT
7692 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7694 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7695 simplify_gen_unary (NEG
, mode
,
7698 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7702 SUBST (XEXP (x
, 0), lhs
);
7703 SUBST (XEXP (x
, 1), rhs
);
7706 x
= gen_lowpart (mode
, new_rtx
);
7712 lhs
= make_compound_operation (lhs
, next_code
);
7713 rhs
= make_compound_operation (rhs
, next_code
);
7714 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7715 && SCALAR_INT_MODE_P (mode
))
7717 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7719 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7721 else if (GET_CODE (rhs
) == MULT
7722 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7724 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7725 simplify_gen_unary (NEG
, mode
,
7728 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7732 SUBST (XEXP (x
, 0), lhs
);
7733 SUBST (XEXP (x
, 1), rhs
);
7736 return gen_lowpart (mode
, new_rtx
);
7739 /* If the second operand is not a constant, we can't do anything
7741 if (!CONST_INT_P (XEXP (x
, 1)))
7744 /* If the constant is a power of two minus one and the first operand
7745 is a logical right shift, make an extraction. */
7746 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7747 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7749 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7750 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7751 0, in_code
== COMPARE
);
7754 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7755 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7756 && subreg_lowpart_p (XEXP (x
, 0))
7757 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7758 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7760 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7762 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7763 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7764 0, in_code
== COMPARE
);
7766 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7767 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7768 || GET_CODE (XEXP (x
, 0)) == IOR
)
7769 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7770 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7771 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7773 /* Apply the distributive law, and then try to make extractions. */
7774 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7775 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7777 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7779 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7782 /* If we are have (and (rotate X C) M) and C is larger than the number
7783 of bits in M, this is an extraction. */
7785 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7786 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7787 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7788 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7790 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7791 new_rtx
= make_extraction (mode
, new_rtx
,
7792 (GET_MODE_PRECISION (mode
)
7793 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7794 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7797 /* On machines without logical shifts, if the operand of the AND is
7798 a logical shift and our mask turns off all the propagated sign
7799 bits, we can replace the logical shift with an arithmetic shift. */
7800 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7801 && !have_insn_for (LSHIFTRT
, mode
)
7802 && have_insn_for (ASHIFTRT
, mode
)
7803 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7804 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7805 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7806 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7808 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7810 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7811 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7813 gen_rtx_ASHIFTRT (mode
,
7814 make_compound_operation
7815 (XEXP (XEXP (x
, 0), 0), next_code
),
7816 XEXP (XEXP (x
, 0), 1)));
7819 /* If the constant is one less than a power of two, this might be
7820 representable by an extraction even if no shift is present.
7821 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7822 we are in a COMPARE. */
7823 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7824 new_rtx
= make_extraction (mode
,
7825 make_compound_operation (XEXP (x
, 0),
7827 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7829 /* If we are in a comparison and this is an AND with a power of two,
7830 convert this into the appropriate bit extract. */
7831 else if (in_code
== COMPARE
7832 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7833 new_rtx
= make_extraction (mode
,
7834 make_compound_operation (XEXP (x
, 0),
7836 i
, NULL_RTX
, 1, 1, 0, 1);
7841 /* If the sign bit is known to be zero, replace this with an
7842 arithmetic shift. */
7843 if (have_insn_for (ASHIFTRT
, mode
)
7844 && ! have_insn_for (LSHIFTRT
, mode
)
7845 && mode_width
<= HOST_BITS_PER_WIDE_INT
7846 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7848 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7849 make_compound_operation (XEXP (x
, 0),
7855 /* ... fall through ... */
7861 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7862 this is a SIGN_EXTRACT. */
7863 if (CONST_INT_P (rhs
)
7864 && GET_CODE (lhs
) == ASHIFT
7865 && CONST_INT_P (XEXP (lhs
, 1))
7866 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7867 && INTVAL (XEXP (lhs
, 1)) >= 0
7868 && INTVAL (rhs
) < mode_width
)
7870 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7871 new_rtx
= make_extraction (mode
, new_rtx
,
7872 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7873 NULL_RTX
, mode_width
- INTVAL (rhs
),
7874 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7878 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7879 If so, try to merge the shifts into a SIGN_EXTEND. We could
7880 also do this for some cases of SIGN_EXTRACT, but it doesn't
7881 seem worth the effort; the case checked for occurs on Alpha. */
7884 && ! (GET_CODE (lhs
) == SUBREG
7885 && (OBJECT_P (SUBREG_REG (lhs
))))
7886 && CONST_INT_P (rhs
)
7887 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7888 && INTVAL (rhs
) < mode_width
7889 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7890 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7891 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7892 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7897 /* Call ourselves recursively on the inner expression. If we are
7898 narrowing the object and it has a different RTL code from
7899 what it originally did, do this SUBREG as a force_to_mode. */
7901 rtx inner
= SUBREG_REG (x
), simplified
;
7902 enum rtx_code subreg_code
= in_code
;
7904 /* If in_code is COMPARE, it isn't always safe to pass it through
7905 to the recursive make_compound_operation call. */
7906 if (subreg_code
== COMPARE
7907 && (!subreg_lowpart_p (x
)
7908 || GET_CODE (inner
) == SUBREG
7909 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7910 is (const_int 0), rather than
7911 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7912 || (GET_CODE (inner
) == AND
7913 && CONST_INT_P (XEXP (inner
, 1))
7914 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7915 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
7916 >= GET_MODE_BITSIZE (mode
))))
7919 tem
= make_compound_operation (inner
, subreg_code
);
7922 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7926 if (GET_CODE (tem
) != GET_CODE (inner
)
7927 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7928 && subreg_lowpart_p (x
))
7931 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7933 /* If we have something other than a SUBREG, we might have
7934 done an expansion, so rerun ourselves. */
7935 if (GET_CODE (newer
) != SUBREG
)
7936 newer
= make_compound_operation (newer
, in_code
);
7938 /* force_to_mode can expand compounds. If it just re-expanded the
7939 compound, use gen_lowpart to convert to the desired mode. */
7940 if (rtx_equal_p (newer
, x
)
7941 /* Likewise if it re-expanded the compound only partially.
7942 This happens for SUBREG of ZERO_EXTRACT if they extract
7943 the same number of bits. */
7944 || (GET_CODE (newer
) == SUBREG
7945 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7946 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7947 && GET_CODE (inner
) == AND
7948 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7949 return gen_lowpart (GET_MODE (x
), tem
);
7965 x
= gen_lowpart (mode
, new_rtx
);
7966 code
= GET_CODE (x
);
7969 /* Now recursively process each operand of this operation. We need to
7970 handle ZERO_EXTEND specially so that we don't lose track of the
7972 if (GET_CODE (x
) == ZERO_EXTEND
)
7974 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7975 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7976 new_rtx
, GET_MODE (XEXP (x
, 0)));
7979 SUBST (XEXP (x
, 0), new_rtx
);
7983 fmt
= GET_RTX_FORMAT (code
);
7984 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7987 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7988 SUBST (XEXP (x
, i
), new_rtx
);
7990 else if (fmt
[i
] == 'E')
7991 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7993 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7994 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7998 /* If this is a commutative operation, the changes to the operands
7999 may have made it noncanonical. */
8000 if (COMMUTATIVE_ARITH_P (x
)
8001 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
8004 SUBST (XEXP (x
, 0), XEXP (x
, 1));
8005 SUBST (XEXP (x
, 1), tem
);
8011 /* Given M see if it is a value that would select a field of bits
8012 within an item, but not the entire word. Return -1 if not.
8013 Otherwise, return the starting position of the field, where 0 is the
8016 *PLEN is set to the length of the field. */
8019 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8021 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8022 int pos
= m
? ctz_hwi (m
) : -1;
8026 /* Now shift off the low-order zero bits and see if we have a
8027 power of two minus 1. */
8028 len
= exact_log2 ((m
>> pos
) + 1);
8037 /* If X refers to a register that equals REG in value, replace these
8038 references with REG. */
8040 canon_reg_for_combine (rtx x
, rtx reg
)
8047 enum rtx_code code
= GET_CODE (x
);
8048 switch (GET_RTX_CLASS (code
))
8051 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8052 if (op0
!= XEXP (x
, 0))
8053 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8058 case RTX_COMM_ARITH
:
8059 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8060 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8061 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8062 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8066 case RTX_COMM_COMPARE
:
8067 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8068 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8069 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8070 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8071 GET_MODE (op0
), op0
, op1
);
8075 case RTX_BITFIELD_OPS
:
8076 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8077 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8078 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8079 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8080 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8081 GET_MODE (op0
), op0
, op1
, op2
);
8086 if (rtx_equal_p (get_last_value (reg
), x
)
8087 || rtx_equal_p (reg
, get_last_value (x
)))
8096 fmt
= GET_RTX_FORMAT (code
);
8098 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8101 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8102 if (op
!= XEXP (x
, i
))
8112 else if (fmt
[i
] == 'E')
8115 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8117 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8118 if (op
!= XVECEXP (x
, i
, j
))
8125 XVECEXP (x
, i
, j
) = op
;
8136 /* Return X converted to MODE. If the value is already truncated to
8137 MODE we can just return a subreg even though in the general case we
8138 would need an explicit truncation. */
8141 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8143 if (!CONST_INT_P (x
)
8144 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8145 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8146 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8148 /* Bit-cast X into an integer mode. */
8149 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8150 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8151 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8155 return gen_lowpart (mode
, x
);
8158 /* See if X can be simplified knowing that we will only refer to it in
8159 MODE and will only refer to those bits that are nonzero in MASK.
8160 If other bits are being computed or if masking operations are done
8161 that select a superset of the bits in MASK, they can sometimes be
8164 Return a possibly simplified expression, but always convert X to
8165 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8167 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8168 are all off in X. This is used when X will be complemented, by either
8169 NOT, NEG, or XOR. */
8172 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8175 enum rtx_code code
= GET_CODE (x
);
8176 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8177 machine_mode op_mode
;
8178 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8181 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8182 code below will do the wrong thing since the mode of such an
8183 expression is VOIDmode.
8185 Also do nothing if X is a CLOBBER; this can happen if X was
8186 the return value from a call to gen_lowpart. */
8187 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8190 /* We want to perform the operation in its present mode unless we know
8191 that the operation is valid in MODE, in which case we do the operation
8193 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8194 && have_insn_for (code
, mode
))
8195 ? mode
: GET_MODE (x
));
8197 /* It is not valid to do a right-shift in a narrower mode
8198 than the one it came in with. */
8199 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8200 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8201 op_mode
= GET_MODE (x
);
8203 /* Truncate MASK to fit OP_MODE. */
8205 mask
&= GET_MODE_MASK (op_mode
);
8207 /* When we have an arithmetic operation, or a shift whose count we
8208 do not know, we need to assume that all bits up to the highest-order
8209 bit in MASK will be needed. This is how we form such a mask. */
8210 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8211 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8213 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8216 /* Determine what bits of X are guaranteed to be (non)zero. */
8217 nonzero
= nonzero_bits (x
, mode
);
8219 /* If none of the bits in X are needed, return a zero. */
8220 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8223 /* If X is a CONST_INT, return a new one. Do this here since the
8224 test below will fail. */
8225 if (CONST_INT_P (x
))
8227 if (SCALAR_INT_MODE_P (mode
))
8228 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8231 x
= GEN_INT (INTVAL (x
) & mask
);
8232 return gen_lowpart_common (mode
, x
);
8236 /* If X is narrower than MODE and we want all the bits in X's mode, just
8237 get X in the proper mode. */
8238 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8239 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8240 return gen_lowpart (mode
, x
);
8242 /* We can ignore the effect of a SUBREG if it narrows the mode or
8243 if the constant masks to zero all the bits the mode doesn't have. */
8244 if (GET_CODE (x
) == SUBREG
8245 && subreg_lowpart_p (x
)
8246 && ((GET_MODE_SIZE (GET_MODE (x
))
8247 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8249 & GET_MODE_MASK (GET_MODE (x
))
8250 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8251 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8253 /* The arithmetic simplifications here only work for scalar integer modes. */
8254 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8255 return gen_lowpart_or_truncate (mode
, x
);
8260 /* If X is a (clobber (const_int)), return it since we know we are
8261 generating something that won't match. */
8268 x
= expand_compound_operation (x
);
8269 if (GET_CODE (x
) != code
)
8270 return force_to_mode (x
, mode
, mask
, next_select
);
8274 /* Similarly for a truncate. */
8275 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8278 /* If this is an AND with a constant, convert it into an AND
8279 whose constant is the AND of that constant with MASK. If it
8280 remains an AND of MASK, delete it since it is redundant. */
8282 if (CONST_INT_P (XEXP (x
, 1)))
8284 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8285 mask
& INTVAL (XEXP (x
, 1)));
8287 /* If X is still an AND, see if it is an AND with a mask that
8288 is just some low-order bits. If so, and it is MASK, we don't
8291 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8292 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8296 /* If it remains an AND, try making another AND with the bits
8297 in the mode mask that aren't in MASK turned on. If the
8298 constant in the AND is wide enough, this might make a
8299 cheaper constant. */
8301 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8302 && GET_MODE_MASK (GET_MODE (x
)) != mask
8303 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8305 unsigned HOST_WIDE_INT cval
8306 = UINTVAL (XEXP (x
, 1))
8307 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8310 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8311 gen_int_mode (cval
, GET_MODE (x
)));
8312 if (set_src_cost (y
, optimize_this_for_speed_p
)
8313 < set_src_cost (x
, optimize_this_for_speed_p
))
8323 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8324 low-order bits (as in an alignment operation) and FOO is already
8325 aligned to that boundary, mask C1 to that boundary as well.
8326 This may eliminate that PLUS and, later, the AND. */
8329 unsigned int width
= GET_MODE_PRECISION (mode
);
8330 unsigned HOST_WIDE_INT smask
= mask
;
8332 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8333 number, sign extend it. */
8335 if (width
< HOST_BITS_PER_WIDE_INT
8336 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8337 smask
|= HOST_WIDE_INT_M1U
<< width
;
8339 if (CONST_INT_P (XEXP (x
, 1))
8340 && exact_log2 (- smask
) >= 0
8341 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8342 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8343 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8344 (INTVAL (XEXP (x
, 1)) & smask
)),
8345 mode
, smask
, next_select
);
8348 /* ... fall through ... */
8351 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8352 most significant bit in MASK since carries from those bits will
8353 affect the bits we are interested in. */
8358 /* If X is (minus C Y) where C's least set bit is larger than any bit
8359 in the mask, then we may replace with (neg Y). */
8360 if (CONST_INT_P (XEXP (x
, 0))
8361 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8363 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8365 return force_to_mode (x
, mode
, mask
, next_select
);
8368 /* Similarly, if C contains every bit in the fuller_mask, then we may
8369 replace with (not Y). */
8370 if (CONST_INT_P (XEXP (x
, 0))
8371 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8373 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8374 XEXP (x
, 1), GET_MODE (x
));
8375 return force_to_mode (x
, mode
, mask
, next_select
);
8383 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8384 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8385 operation which may be a bitfield extraction. Ensure that the
8386 constant we form is not wider than the mode of X. */
8388 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8389 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8390 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8391 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8392 && CONST_INT_P (XEXP (x
, 1))
8393 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8394 + floor_log2 (INTVAL (XEXP (x
, 1))))
8395 < GET_MODE_PRECISION (GET_MODE (x
)))
8396 && (UINTVAL (XEXP (x
, 1))
8397 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8399 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8400 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8402 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8403 XEXP (XEXP (x
, 0), 0), temp
);
8404 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8405 XEXP (XEXP (x
, 0), 1));
8406 return force_to_mode (x
, mode
, mask
, next_select
);
8410 /* For most binary operations, just propagate into the operation and
8411 change the mode if we have an operation of that mode. */
8413 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8414 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8416 /* If we ended up truncating both operands, truncate the result of the
8417 operation instead. */
8418 if (GET_CODE (op0
) == TRUNCATE
8419 && GET_CODE (op1
) == TRUNCATE
)
8421 op0
= XEXP (op0
, 0);
8422 op1
= XEXP (op1
, 0);
8425 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8426 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8428 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8429 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8433 /* For left shifts, do the same, but just for the first operand.
8434 However, we cannot do anything with shifts where we cannot
8435 guarantee that the counts are smaller than the size of the mode
8436 because such a count will have a different meaning in a
8439 if (! (CONST_INT_P (XEXP (x
, 1))
8440 && INTVAL (XEXP (x
, 1)) >= 0
8441 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8442 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8443 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8444 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8447 /* If the shift count is a constant and we can do arithmetic in
8448 the mode of the shift, refine which bits we need. Otherwise, use the
8449 conservative form of the mask. */
8450 if (CONST_INT_P (XEXP (x
, 1))
8451 && INTVAL (XEXP (x
, 1)) >= 0
8452 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8453 && HWI_COMPUTABLE_MODE_P (op_mode
))
8454 mask
>>= INTVAL (XEXP (x
, 1));
8458 op0
= gen_lowpart_or_truncate (op_mode
,
8459 force_to_mode (XEXP (x
, 0), op_mode
,
8460 mask
, next_select
));
8462 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8463 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8467 /* Here we can only do something if the shift count is a constant,
8468 this shift constant is valid for the host, and we can do arithmetic
8471 if (CONST_INT_P (XEXP (x
, 1))
8472 && INTVAL (XEXP (x
, 1)) >= 0
8473 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8474 && HWI_COMPUTABLE_MODE_P (op_mode
))
8476 rtx inner
= XEXP (x
, 0);
8477 unsigned HOST_WIDE_INT inner_mask
;
8479 /* Select the mask of the bits we need for the shift operand. */
8480 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8482 /* We can only change the mode of the shift if we can do arithmetic
8483 in the mode of the shift and INNER_MASK is no wider than the
8484 width of X's mode. */
8485 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8486 op_mode
= GET_MODE (x
);
8488 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8490 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8491 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8494 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8495 shift and AND produces only copies of the sign bit (C2 is one less
8496 than a power of two), we can do this with just a shift. */
8498 if (GET_CODE (x
) == LSHIFTRT
8499 && CONST_INT_P (XEXP (x
, 1))
8500 /* The shift puts one of the sign bit copies in the least significant
8502 && ((INTVAL (XEXP (x
, 1))
8503 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8504 >= GET_MODE_PRECISION (GET_MODE (x
)))
8505 && exact_log2 (mask
+ 1) >= 0
8506 /* Number of bits left after the shift must be more than the mask
8508 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8509 <= GET_MODE_PRECISION (GET_MODE (x
)))
8510 /* Must be more sign bit copies than the mask needs. */
8511 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8512 >= exact_log2 (mask
+ 1)))
8513 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8514 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8515 - exact_log2 (mask
+ 1)));
8520 /* If we are just looking for the sign bit, we don't need this shift at
8521 all, even if it has a variable count. */
8522 if (val_signbit_p (GET_MODE (x
), mask
))
8523 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8525 /* If this is a shift by a constant, get a mask that contains those bits
8526 that are not copies of the sign bit. We then have two cases: If
8527 MASK only includes those bits, this can be a logical shift, which may
8528 allow simplifications. If MASK is a single-bit field not within
8529 those bits, we are requesting a copy of the sign bit and hence can
8530 shift the sign bit to the appropriate location. */
8532 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8533 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8537 /* If the considered data is wider than HOST_WIDE_INT, we can't
8538 represent a mask for all its bits in a single scalar.
8539 But we only care about the lower bits, so calculate these. */
8541 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8543 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8545 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8546 is the number of bits a full-width mask would have set.
8547 We need only shift if these are fewer than nonzero can
8548 hold. If not, we must keep all bits set in nonzero. */
8550 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8551 < HOST_BITS_PER_WIDE_INT
)
8552 nonzero
>>= INTVAL (XEXP (x
, 1))
8553 + HOST_BITS_PER_WIDE_INT
8554 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8558 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8559 nonzero
>>= INTVAL (XEXP (x
, 1));
8562 if ((mask
& ~nonzero
) == 0)
8564 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8565 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8566 if (GET_CODE (x
) != ASHIFTRT
)
8567 return force_to_mode (x
, mode
, mask
, next_select
);
8570 else if ((i
= exact_log2 (mask
)) >= 0)
8572 x
= simplify_shift_const
8573 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8574 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8576 if (GET_CODE (x
) != ASHIFTRT
)
8577 return force_to_mode (x
, mode
, mask
, next_select
);
8581 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8582 even if the shift count isn't a constant. */
8584 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8585 XEXP (x
, 0), XEXP (x
, 1));
8589 /* If this is a zero- or sign-extension operation that just affects bits
8590 we don't care about, remove it. Be sure the call above returned
8591 something that is still a shift. */
8593 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8594 && CONST_INT_P (XEXP (x
, 1))
8595 && INTVAL (XEXP (x
, 1)) >= 0
8596 && (INTVAL (XEXP (x
, 1))
8597 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8598 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8599 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8600 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8607 /* If the shift count is constant and we can do computations
8608 in the mode of X, compute where the bits we care about are.
8609 Otherwise, we can't do anything. Don't change the mode of
8610 the shift or propagate MODE into the shift, though. */
8611 if (CONST_INT_P (XEXP (x
, 1))
8612 && INTVAL (XEXP (x
, 1)) >= 0)
8614 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8616 gen_int_mode (mask
, GET_MODE (x
)),
8618 if (temp
&& CONST_INT_P (temp
))
8619 x
= simplify_gen_binary (code
, GET_MODE (x
),
8620 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8621 INTVAL (temp
), next_select
),
8627 /* If we just want the low-order bit, the NEG isn't needed since it
8628 won't change the low-order bit. */
8630 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8632 /* We need any bits less significant than the most significant bit in
8633 MASK since carries from those bits will affect the bits we are
8639 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8640 same as the XOR case above. Ensure that the constant we form is not
8641 wider than the mode of X. */
8643 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8644 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8645 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8646 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8647 < GET_MODE_PRECISION (GET_MODE (x
)))
8648 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8650 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8652 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8653 XEXP (XEXP (x
, 0), 0), temp
);
8654 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8655 temp
, XEXP (XEXP (x
, 0), 1));
8657 return force_to_mode (x
, mode
, mask
, next_select
);
8660 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8661 use the full mask inside the NOT. */
8665 op0
= gen_lowpart_or_truncate (op_mode
,
8666 force_to_mode (XEXP (x
, 0), mode
, mask
,
8668 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8669 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8673 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8674 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8675 which is equal to STORE_FLAG_VALUE. */
8676 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8677 && XEXP (x
, 1) == const0_rtx
8678 && GET_MODE (XEXP (x
, 0)) == mode
8679 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8680 && (nonzero_bits (XEXP (x
, 0), mode
)
8681 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8682 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8687 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8688 written in a narrower mode. We play it safe and do not do so. */
8690 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8691 force_to_mode (XEXP (x
, 1), mode
,
8692 mask
, next_select
));
8693 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8694 force_to_mode (XEXP (x
, 2), mode
,
8695 mask
, next_select
));
8696 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8697 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8698 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8706 /* Ensure we return a value of the proper mode. */
8707 return gen_lowpart_or_truncate (mode
, x
);
8710 /* Return nonzero if X is an expression that has one of two values depending on
8711 whether some other value is zero or nonzero. In that case, we return the
8712 value that is being tested, *PTRUE is set to the value if the rtx being
8713 returned has a nonzero value, and *PFALSE is set to the other alternative.
8715 If we return zero, we set *PTRUE and *PFALSE to X. */
8718 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8720 machine_mode mode
= GET_MODE (x
);
8721 enum rtx_code code
= GET_CODE (x
);
8722 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8723 unsigned HOST_WIDE_INT nz
;
8725 /* If we are comparing a value against zero, we are done. */
8726 if ((code
== NE
|| code
== EQ
)
8727 && XEXP (x
, 1) == const0_rtx
)
8729 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8730 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8734 /* If this is a unary operation whose operand has one of two values, apply
8735 our opcode to compute those values. */
8736 else if (UNARY_P (x
)
8737 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8739 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8740 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8741 GET_MODE (XEXP (x
, 0)));
8745 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8746 make can't possibly match and would suppress other optimizations. */
8747 else if (code
== COMPARE
)
8750 /* If this is a binary operation, see if either side has only one of two
8751 values. If either one does or if both do and they are conditional on
8752 the same value, compute the new true and false values. */
8753 else if (BINARY_P (x
))
8755 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8756 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8758 if ((cond0
!= 0 || cond1
!= 0)
8759 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8761 /* If if_then_else_cond returned zero, then true/false are the
8762 same rtl. We must copy one of them to prevent invalid rtl
8765 true0
= copy_rtx (true0
);
8766 else if (cond1
== 0)
8767 true1
= copy_rtx (true1
);
8769 if (COMPARISON_P (x
))
8771 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8773 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8778 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8779 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8782 return cond0
? cond0
: cond1
;
8785 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8786 operands is zero when the other is nonzero, and vice-versa,
8787 and STORE_FLAG_VALUE is 1 or -1. */
8789 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8790 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8792 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8794 rtx op0
= XEXP (XEXP (x
, 0), 1);
8795 rtx op1
= XEXP (XEXP (x
, 1), 1);
8797 cond0
= XEXP (XEXP (x
, 0), 0);
8798 cond1
= XEXP (XEXP (x
, 1), 0);
8800 if (COMPARISON_P (cond0
)
8801 && COMPARISON_P (cond1
)
8802 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8803 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8804 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8805 || ((swap_condition (GET_CODE (cond0
))
8806 == reversed_comparison_code (cond1
, NULL
))
8807 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8808 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8809 && ! side_effects_p (x
))
8811 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8812 *pfalse
= simplify_gen_binary (MULT
, mode
,
8814 ? simplify_gen_unary (NEG
, mode
,
8822 /* Similarly for MULT, AND and UMIN, except that for these the result
8824 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8825 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8826 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8828 cond0
= XEXP (XEXP (x
, 0), 0);
8829 cond1
= XEXP (XEXP (x
, 1), 0);
8831 if (COMPARISON_P (cond0
)
8832 && COMPARISON_P (cond1
)
8833 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8834 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8835 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8836 || ((swap_condition (GET_CODE (cond0
))
8837 == reversed_comparison_code (cond1
, NULL
))
8838 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8839 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8840 && ! side_effects_p (x
))
8842 *ptrue
= *pfalse
= const0_rtx
;
8848 else if (code
== IF_THEN_ELSE
)
8850 /* If we have IF_THEN_ELSE already, extract the condition and
8851 canonicalize it if it is NE or EQ. */
8852 cond0
= XEXP (x
, 0);
8853 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8854 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8855 return XEXP (cond0
, 0);
8856 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8858 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8859 return XEXP (cond0
, 0);
8865 /* If X is a SUBREG, we can narrow both the true and false values
8866 if the inner expression, if there is a condition. */
8867 else if (code
== SUBREG
8868 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8871 true0
= simplify_gen_subreg (mode
, true0
,
8872 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8873 false0
= simplify_gen_subreg (mode
, false0
,
8874 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8875 if (true0
&& false0
)
8883 /* If X is a constant, this isn't special and will cause confusions
8884 if we treat it as such. Likewise if it is equivalent to a constant. */
8885 else if (CONSTANT_P (x
)
8886 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8889 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8890 will be least confusing to the rest of the compiler. */
8891 else if (mode
== BImode
)
8893 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8897 /* If X is known to be either 0 or -1, those are the true and
8898 false values when testing X. */
8899 else if (x
== constm1_rtx
|| x
== const0_rtx
8900 || (mode
!= VOIDmode
8901 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8903 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8907 /* Likewise for 0 or a single bit. */
8908 else if (HWI_COMPUTABLE_MODE_P (mode
)
8909 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8911 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8915 /* Otherwise fail; show no condition with true and false values the same. */
8916 *ptrue
= *pfalse
= x
;
8920 /* Return the value of expression X given the fact that condition COND
8921 is known to be true when applied to REG as its first operand and VAL
8922 as its second. X is known to not be shared and so can be modified in
8925 We only handle the simplest cases, and specifically those cases that
8926 arise with IF_THEN_ELSE expressions. */
8929 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8931 enum rtx_code code
= GET_CODE (x
);
8936 if (side_effects_p (x
))
8939 /* If either operand of the condition is a floating point value,
8940 then we have to avoid collapsing an EQ comparison. */
8942 && rtx_equal_p (x
, reg
)
8943 && ! FLOAT_MODE_P (GET_MODE (x
))
8944 && ! FLOAT_MODE_P (GET_MODE (val
)))
8947 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8950 /* If X is (abs REG) and we know something about REG's relationship
8951 with zero, we may be able to simplify this. */
8953 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8956 case GE
: case GT
: case EQ
:
8959 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8961 GET_MODE (XEXP (x
, 0)));
8966 /* The only other cases we handle are MIN, MAX, and comparisons if the
8967 operands are the same as REG and VAL. */
8969 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8971 if (rtx_equal_p (XEXP (x
, 0), val
))
8972 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8974 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8976 if (COMPARISON_P (x
))
8978 if (comparison_dominates_p (cond
, code
))
8979 return const_true_rtx
;
8981 code
= reversed_comparison_code (x
, NULL
);
8983 && comparison_dominates_p (cond
, code
))
8988 else if (code
== SMAX
|| code
== SMIN
8989 || code
== UMIN
|| code
== UMAX
)
8991 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8993 /* Do not reverse the condition when it is NE or EQ.
8994 This is because we cannot conclude anything about
8995 the value of 'SMAX (x, y)' when x is not equal to y,
8996 but we can when x equals y. */
8997 if ((code
== SMAX
|| code
== UMAX
)
8998 && ! (cond
== EQ
|| cond
== NE
))
8999 cond
= reverse_condition (cond
);
9004 return unsignedp
? x
: XEXP (x
, 1);
9006 return unsignedp
? x
: XEXP (x
, 0);
9008 return unsignedp
? XEXP (x
, 1) : x
;
9010 return unsignedp
? XEXP (x
, 0) : x
;
9017 else if (code
== SUBREG
)
9019 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9020 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9022 if (SUBREG_REG (x
) != r
)
9024 /* We must simplify subreg here, before we lose track of the
9025 original inner_mode. */
9026 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9027 inner_mode
, SUBREG_BYTE (x
));
9031 SUBST (SUBREG_REG (x
), r
);
9036 /* We don't have to handle SIGN_EXTEND here, because even in the
9037 case of replacing something with a modeless CONST_INT, a
9038 CONST_INT is already (supposed to be) a valid sign extension for
9039 its narrower mode, which implies it's already properly
9040 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9041 story is different. */
9042 else if (code
== ZERO_EXTEND
)
9044 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9045 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9047 if (XEXP (x
, 0) != r
)
9049 /* We must simplify the zero_extend here, before we lose
9050 track of the original inner_mode. */
9051 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9056 SUBST (XEXP (x
, 0), r
);
9062 fmt
= GET_RTX_FORMAT (code
);
9063 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9066 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9067 else if (fmt
[i
] == 'E')
9068 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9069 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9076 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9077 assignment as a field assignment. */
9080 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
9082 if (x
== y
|| rtx_equal_p (x
, y
))
9085 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9088 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9089 Note that all SUBREGs of MEM are paradoxical; otherwise they
9090 would have been rewritten. */
9091 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9092 && MEM_P (SUBREG_REG (y
))
9093 && rtx_equal_p (SUBREG_REG (y
),
9094 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9097 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9098 && MEM_P (SUBREG_REG (x
))
9099 && rtx_equal_p (SUBREG_REG (x
),
9100 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9103 /* We used to see if get_last_value of X and Y were the same but that's
9104 not correct. In one direction, we'll cause the assignment to have
9105 the wrong destination and in the case, we'll import a register into this
9106 insn that might have already have been dead. So fail if none of the
9107 above cases are true. */
9111 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9112 Return that assignment if so.
9114 We only handle the most common cases. */
9117 make_field_assignment (rtx x
)
9119 rtx dest
= SET_DEST (x
);
9120 rtx src
= SET_SRC (x
);
9125 unsigned HOST_WIDE_INT len
;
9129 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9130 a clear of a one-bit field. We will have changed it to
9131 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9134 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9135 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9136 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9137 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9139 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9142 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9146 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9147 && subreg_lowpart_p (XEXP (src
, 0))
9148 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9149 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9150 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9151 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9152 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9153 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9155 assign
= make_extraction (VOIDmode
, dest
, 0,
9156 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9159 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9163 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9165 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9166 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9167 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9169 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9172 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9176 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9177 SRC is an AND with all bits of that field set, then we can discard
9179 if (GET_CODE (dest
) == ZERO_EXTRACT
9180 && CONST_INT_P (XEXP (dest
, 1))
9181 && GET_CODE (src
) == AND
9182 && CONST_INT_P (XEXP (src
, 1)))
9184 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9185 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9186 unsigned HOST_WIDE_INT ze_mask
;
9188 if (width
>= HOST_BITS_PER_WIDE_INT
)
9191 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9193 /* Complete overlap. We can remove the source AND. */
9194 if ((and_mask
& ze_mask
) == ze_mask
)
9195 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9197 /* Partial overlap. We can reduce the source AND. */
9198 if ((and_mask
& ze_mask
) != and_mask
)
9200 mode
= GET_MODE (src
);
9201 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9202 gen_int_mode (and_mask
& ze_mask
, mode
));
9203 return gen_rtx_SET (VOIDmode
, dest
, src
);
9207 /* The other case we handle is assignments into a constant-position
9208 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9209 a mask that has all one bits except for a group of zero bits and
9210 OTHER is known to have zeros where C1 has ones, this is such an
9211 assignment. Compute the position and length from C1. Shift OTHER
9212 to the appropriate position, force it to the required mode, and
9213 make the extraction. Check for the AND in both operands. */
9215 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9218 rhs
= expand_compound_operation (XEXP (src
, 0));
9219 lhs
= expand_compound_operation (XEXP (src
, 1));
9221 if (GET_CODE (rhs
) == AND
9222 && CONST_INT_P (XEXP (rhs
, 1))
9223 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9224 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9225 else if (GET_CODE (lhs
) == AND
9226 && CONST_INT_P (XEXP (lhs
, 1))
9227 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9228 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9232 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9233 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9234 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9235 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9238 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9242 /* The mode to use for the source is the mode of the assignment, or of
9243 what is inside a possible STRICT_LOW_PART. */
9244 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9245 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9247 /* Shift OTHER right POS places and make it the source, restricting it
9248 to the proper length and mode. */
9250 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9254 src
= force_to_mode (src
, mode
,
9255 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9256 ? ~(unsigned HOST_WIDE_INT
) 0
9257 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9260 /* If SRC is masked by an AND that does not make a difference in
9261 the value being stored, strip it. */
9262 if (GET_CODE (assign
) == ZERO_EXTRACT
9263 && CONST_INT_P (XEXP (assign
, 1))
9264 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9265 && GET_CODE (src
) == AND
9266 && CONST_INT_P (XEXP (src
, 1))
9267 && UINTVAL (XEXP (src
, 1))
9268 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9269 src
= XEXP (src
, 0);
9271 return gen_rtx_SET (VOIDmode
, assign
, src
);
9274 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9278 apply_distributive_law (rtx x
)
9280 enum rtx_code code
= GET_CODE (x
);
9281 enum rtx_code inner_code
;
9282 rtx lhs
, rhs
, other
;
9285 /* Distributivity is not true for floating point as it can change the
9286 value. So we don't do it unless -funsafe-math-optimizations. */
9287 if (FLOAT_MODE_P (GET_MODE (x
))
9288 && ! flag_unsafe_math_optimizations
)
9291 /* The outer operation can only be one of the following: */
9292 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9293 && code
!= PLUS
&& code
!= MINUS
)
9299 /* If either operand is a primitive we can't do anything, so get out
9301 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9304 lhs
= expand_compound_operation (lhs
);
9305 rhs
= expand_compound_operation (rhs
);
9306 inner_code
= GET_CODE (lhs
);
9307 if (inner_code
!= GET_CODE (rhs
))
9310 /* See if the inner and outer operations distribute. */
9317 /* These all distribute except over PLUS. */
9318 if (code
== PLUS
|| code
== MINUS
)
9323 if (code
!= PLUS
&& code
!= MINUS
)
9328 /* This is also a multiply, so it distributes over everything. */
9331 /* This used to handle SUBREG, but this turned out to be counter-
9332 productive, since (subreg (op ...)) usually is not handled by
9333 insn patterns, and this "optimization" therefore transformed
9334 recognizable patterns into unrecognizable ones. Therefore the
9335 SUBREG case was removed from here.
9337 It is possible that distributing SUBREG over arithmetic operations
9338 leads to an intermediate result than can then be optimized further,
9339 e.g. by moving the outer SUBREG to the other side of a SET as done
9340 in simplify_set. This seems to have been the original intent of
9341 handling SUBREGs here.
9343 However, with current GCC this does not appear to actually happen,
9344 at least on major platforms. If some case is found where removing
9345 the SUBREG case here prevents follow-on optimizations, distributing
9346 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9352 /* Set LHS and RHS to the inner operands (A and B in the example
9353 above) and set OTHER to the common operand (C in the example).
9354 There is only one way to do this unless the inner operation is
9356 if (COMMUTATIVE_ARITH_P (lhs
)
9357 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9358 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9359 else if (COMMUTATIVE_ARITH_P (lhs
)
9360 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9361 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9362 else if (COMMUTATIVE_ARITH_P (lhs
)
9363 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9364 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9365 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9366 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9370 /* Form the new inner operation, seeing if it simplifies first. */
9371 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9373 /* There is one exception to the general way of distributing:
9374 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9375 if (code
== XOR
&& inner_code
== IOR
)
9378 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9381 /* We may be able to continuing distributing the result, so call
9382 ourselves recursively on the inner operation before forming the
9383 outer operation, which we return. */
9384 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9385 apply_distributive_law (tem
), other
);
9388 /* See if X is of the form (* (+ A B) C), and if so convert to
9389 (+ (* A C) (* B C)) and try to simplify.
9391 Most of the time, this results in no change. However, if some of
9392 the operands are the same or inverses of each other, simplifications
9395 For example, (and (ior A B) (not B)) can occur as the result of
9396 expanding a bit field assignment. When we apply the distributive
9397 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9398 which then simplifies to (and (A (not B))).
9400 Note that no checks happen on the validity of applying the inverse
9401 distributive law. This is pointless since we can do it in the
9402 few places where this routine is called.
9404 N is the index of the term that is decomposed (the arithmetic operation,
9405 i.e. (+ A B) in the first example above). !N is the index of the term that
9406 is distributed, i.e. of C in the first example above. */
9408 distribute_and_simplify_rtx (rtx x
, int n
)
9411 enum rtx_code outer_code
, inner_code
;
9412 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9414 /* Distributivity is not true for floating point as it can change the
9415 value. So we don't do it unless -funsafe-math-optimizations. */
9416 if (FLOAT_MODE_P (GET_MODE (x
))
9417 && ! flag_unsafe_math_optimizations
)
9420 decomposed
= XEXP (x
, n
);
9421 if (!ARITHMETIC_P (decomposed
))
9424 mode
= GET_MODE (x
);
9425 outer_code
= GET_CODE (x
);
9426 distributed
= XEXP (x
, !n
);
9428 inner_code
= GET_CODE (decomposed
);
9429 inner_op0
= XEXP (decomposed
, 0);
9430 inner_op1
= XEXP (decomposed
, 1);
9432 /* Special case (and (xor B C) (not A)), which is equivalent to
9433 (xor (ior A B) (ior A C)) */
9434 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9436 distributed
= XEXP (distributed
, 0);
9442 /* Distribute the second term. */
9443 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9444 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9448 /* Distribute the first term. */
9449 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9450 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9453 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9455 if (GET_CODE (tmp
) != outer_code
9456 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9457 < set_src_cost (x
, optimize_this_for_speed_p
)))
9463 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9464 in MODE. Return an equivalent form, if different from (and VAROP
9465 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9468 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9469 unsigned HOST_WIDE_INT constop
)
9471 unsigned HOST_WIDE_INT nonzero
;
9472 unsigned HOST_WIDE_INT orig_constop
;
9477 orig_constop
= constop
;
9478 if (GET_CODE (varop
) == CLOBBER
)
9481 /* Simplify VAROP knowing that we will be only looking at some of the
9484 Note by passing in CONSTOP, we guarantee that the bits not set in
9485 CONSTOP are not significant and will never be examined. We must
9486 ensure that is the case by explicitly masking out those bits
9487 before returning. */
9488 varop
= force_to_mode (varop
, mode
, constop
, 0);
9490 /* If VAROP is a CLOBBER, we will fail so return it. */
9491 if (GET_CODE (varop
) == CLOBBER
)
9494 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9495 to VAROP and return the new constant. */
9496 if (CONST_INT_P (varop
))
9497 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9499 /* See what bits may be nonzero in VAROP. Unlike the general case of
9500 a call to nonzero_bits, here we don't care about bits outside
9503 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9505 /* Turn off all bits in the constant that are known to already be zero.
9506 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9507 which is tested below. */
9511 /* If we don't have any bits left, return zero. */
9515 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9516 a power of two, we can replace this with an ASHIFT. */
9517 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9518 && (i
= exact_log2 (constop
)) >= 0)
9519 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9521 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9522 or XOR, then try to apply the distributive law. This may eliminate
9523 operations if either branch can be simplified because of the AND.
9524 It may also make some cases more complex, but those cases probably
9525 won't match a pattern either with or without this. */
9527 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9531 apply_distributive_law
9532 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9533 simplify_and_const_int (NULL_RTX
,
9537 simplify_and_const_int (NULL_RTX
,
9542 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9543 the AND and see if one of the operands simplifies to zero. If so, we
9544 may eliminate it. */
9546 if (GET_CODE (varop
) == PLUS
9547 && exact_log2 (constop
+ 1) >= 0)
9551 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9552 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9553 if (o0
== const0_rtx
)
9555 if (o1
== const0_rtx
)
9559 /* Make a SUBREG if necessary. If we can't make it, fail. */
9560 varop
= gen_lowpart (mode
, varop
);
9561 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9564 /* If we are only masking insignificant bits, return VAROP. */
9565 if (constop
== nonzero
)
9568 if (varop
== orig_varop
&& constop
== orig_constop
)
9571 /* Otherwise, return an AND. */
9572 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9576 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9579 Return an equivalent form, if different from X. Otherwise, return X. If
9580 X is zero, we are to always construct the equivalent form. */
9583 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9584 unsigned HOST_WIDE_INT constop
)
9586 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9591 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9592 gen_int_mode (constop
, mode
));
9593 if (GET_MODE (x
) != mode
)
9594 x
= gen_lowpart (mode
, x
);
9598 /* Given a REG, X, compute which bits in X can be nonzero.
9599 We don't care about bits outside of those defined in MODE.
9601 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9602 a shift, AND, or zero_extract, we can do better. */
9605 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9606 const_rtx known_x ATTRIBUTE_UNUSED
,
9607 machine_mode known_mode ATTRIBUTE_UNUSED
,
9608 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9609 unsigned HOST_WIDE_INT
*nonzero
)
9614 /* If X is a register whose nonzero bits value is current, use it.
9615 Otherwise, if X is a register whose value we can find, use that
9616 value. Otherwise, use the previously-computed global nonzero bits
9617 for this register. */
9619 rsp
= ®_stat
[REGNO (x
)];
9620 if (rsp
->last_set_value
!= 0
9621 && (rsp
->last_set_mode
== mode
9622 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9623 && GET_MODE_CLASS (mode
) == MODE_INT
))
9624 && ((rsp
->last_set_label
>= label_tick_ebb_start
9625 && rsp
->last_set_label
< label_tick
)
9626 || (rsp
->last_set_label
== label_tick
9627 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9628 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9629 && REG_N_SETS (REGNO (x
)) == 1
9631 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9634 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9636 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9637 /* We don't know anything about the upper bits. */
9638 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9644 tem
= get_last_value (x
);
9648 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9649 /* If X is narrower than MODE and TEM is a non-negative
9650 constant that would appear negative in the mode of X,
9651 sign-extend it for use in reg_nonzero_bits because some
9652 machines (maybe most) will actually do the sign-extension
9653 and this is the conservative approach.
9655 ??? For 2.5, try to tighten up the MD files in this regard
9656 instead of this kludge. */
9658 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9659 && CONST_INT_P (tem
)
9661 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9662 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9666 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9668 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9670 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9671 /* We don't know anything about the upper bits. */
9672 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9680 /* Return the number of bits at the high-order end of X that are known to
9681 be equal to the sign bit. X will be used in mode MODE; if MODE is
9682 VOIDmode, X will be used in its own mode. The returned value will always
9683 be between 1 and the number of bits in MODE. */
9686 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
9687 const_rtx known_x ATTRIBUTE_UNUSED
,
9688 machine_mode known_mode
9690 unsigned int known_ret ATTRIBUTE_UNUSED
,
9691 unsigned int *result
)
9696 rsp
= ®_stat
[REGNO (x
)];
9697 if (rsp
->last_set_value
!= 0
9698 && rsp
->last_set_mode
== mode
9699 && ((rsp
->last_set_label
>= label_tick_ebb_start
9700 && rsp
->last_set_label
< label_tick
)
9701 || (rsp
->last_set_label
== label_tick
9702 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9703 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9704 && REG_N_SETS (REGNO (x
)) == 1
9706 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9709 *result
= rsp
->last_set_sign_bit_copies
;
9713 tem
= get_last_value (x
);
9717 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9718 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9719 *result
= rsp
->sign_bit_copies
;
9724 /* Return the number of "extended" bits there are in X, when interpreted
9725 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9726 unsigned quantities, this is the number of high-order zero bits.
9727 For signed quantities, this is the number of copies of the sign bit
9728 minus 1. In both case, this function returns the number of "spare"
9729 bits. For example, if two quantities for which this function returns
9730 at least 1 are added, the addition is known not to overflow.
9732 This function will always return 0 unless called during combine, which
9733 implies that it must be called from a define_split. */
9736 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
9738 if (nonzero_sign_valid
== 0)
9742 ? (HWI_COMPUTABLE_MODE_P (mode
)
9743 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9744 - floor_log2 (nonzero_bits (x
, mode
)))
9746 : num_sign_bit_copies (x
, mode
) - 1);
9749 /* This function is called from `simplify_shift_const' to merge two
9750 outer operations. Specifically, we have already found that we need
9751 to perform operation *POP0 with constant *PCONST0 at the outermost
9752 position. We would now like to also perform OP1 with constant CONST1
9753 (with *POP0 being done last).
9755 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9756 the resulting operation. *PCOMP_P is set to 1 if we would need to
9757 complement the innermost operand, otherwise it is unchanged.
9759 MODE is the mode in which the operation will be done. No bits outside
9760 the width of this mode matter. It is assumed that the width of this mode
9761 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9763 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9764 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9765 result is simply *PCONST0.
9767 If the resulting operation cannot be expressed as one operation, we
9768 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9771 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
9773 enum rtx_code op0
= *pop0
;
9774 HOST_WIDE_INT const0
= *pconst0
;
9776 const0
&= GET_MODE_MASK (mode
);
9777 const1
&= GET_MODE_MASK (mode
);
9779 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9783 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9786 if (op1
== UNKNOWN
|| op0
== SET
)
9789 else if (op0
== UNKNOWN
)
9790 op0
= op1
, const0
= const1
;
9792 else if (op0
== op1
)
9816 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9817 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9820 /* If the two constants aren't the same, we can't do anything. The
9821 remaining six cases can all be done. */
9822 else if (const0
!= const1
)
9830 /* (a & b) | b == b */
9832 else /* op1 == XOR */
9833 /* (a ^ b) | b == a | b */
9839 /* (a & b) ^ b == (~a) & b */
9840 op0
= AND
, *pcomp_p
= 1;
9841 else /* op1 == IOR */
9842 /* (a | b) ^ b == a & ~b */
9843 op0
= AND
, const0
= ~const0
;
9848 /* (a | b) & b == b */
9850 else /* op1 == XOR */
9851 /* (a ^ b) & b) == (~a) & b */
9858 /* Check for NO-OP cases. */
9859 const0
&= GET_MODE_MASK (mode
);
9861 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9863 else if (const0
== 0 && op0
== AND
)
9865 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9871 /* ??? Slightly redundant with the above mask, but not entirely.
9872 Moving this above means we'd have to sign-extend the mode mask
9873 for the final test. */
9874 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9875 *pconst0
= trunc_int_for_mode (const0
, mode
);
9880 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9881 the shift in. The original shift operation CODE is performed on OP in
9882 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9883 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9884 result of the shift is subject to operation OUTER_CODE with operand
9888 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9889 machine_mode orig_mode
, machine_mode mode
,
9890 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9892 if (orig_mode
== mode
)
9894 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9896 /* In general we can't perform in wider mode for right shift and rotate. */
9900 /* We can still widen if the bits brought in from the left are identical
9901 to the sign bit of ORIG_MODE. */
9902 if (num_sign_bit_copies (op
, mode
)
9903 > (unsigned) (GET_MODE_PRECISION (mode
)
9904 - GET_MODE_PRECISION (orig_mode
)))
9909 /* Similarly here but with zero bits. */
9910 if (HWI_COMPUTABLE_MODE_P (mode
)
9911 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9914 /* We can also widen if the bits brought in will be masked off. This
9915 operation is performed in ORIG_MODE. */
9916 if (outer_code
== AND
)
9918 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9921 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9937 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9938 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9939 if we cannot simplify it. Otherwise, return a simplified value.
9941 The shift is normally computed in the widest mode we find in VAROP, as
9942 long as it isn't a different number of words than RESULT_MODE. Exceptions
9943 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9946 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
9947 rtx varop
, int orig_count
)
9949 enum rtx_code orig_code
= code
;
9950 rtx orig_varop
= varop
;
9952 machine_mode mode
= result_mode
;
9953 machine_mode shift_mode
, tmode
;
9954 unsigned int mode_words
9955 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9956 /* We form (outer_op (code varop count) (outer_const)). */
9957 enum rtx_code outer_op
= UNKNOWN
;
9958 HOST_WIDE_INT outer_const
= 0;
9959 int complement_p
= 0;
9962 /* Make sure and truncate the "natural" shift on the way in. We don't
9963 want to do this inside the loop as it makes it more difficult to
9965 if (SHIFT_COUNT_TRUNCATED
)
9966 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9968 /* If we were given an invalid count, don't do anything except exactly
9969 what was requested. */
9971 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9976 /* Unless one of the branches of the `if' in this loop does a `continue',
9977 we will `break' the loop after the `if'. */
9981 /* If we have an operand of (clobber (const_int 0)), fail. */
9982 if (GET_CODE (varop
) == CLOBBER
)
9985 /* Convert ROTATERT to ROTATE. */
9986 if (code
== ROTATERT
)
9988 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9990 if (VECTOR_MODE_P (result_mode
))
9991 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9993 count
= bitsize
- count
;
9996 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9997 mode
, outer_op
, outer_const
);
9999 /* Handle cases where the count is greater than the size of the mode
10000 minus 1. For ASHIFT, use the size minus one as the count (this can
10001 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10002 take the count modulo the size. For other shifts, the result is
10005 Since these shifts are being produced by the compiler by combining
10006 multiple operations, each of which are defined, we know what the
10007 result is supposed to be. */
10009 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
10011 if (code
== ASHIFTRT
)
10012 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10013 else if (code
== ROTATE
|| code
== ROTATERT
)
10014 count
%= GET_MODE_PRECISION (shift_mode
);
10017 /* We can't simply return zero because there may be an
10019 varop
= const0_rtx
;
10025 /* If we discovered we had to complement VAROP, leave. Making a NOT
10026 here would cause an infinite loop. */
10030 /* An arithmetic right shift of a quantity known to be -1 or 0
10032 if (code
== ASHIFTRT
10033 && (num_sign_bit_copies (varop
, shift_mode
)
10034 == GET_MODE_PRECISION (shift_mode
)))
10040 /* If we are doing an arithmetic right shift and discarding all but
10041 the sign bit copies, this is equivalent to doing a shift by the
10042 bitsize minus one. Convert it into that shift because it will often
10043 allow other simplifications. */
10045 if (code
== ASHIFTRT
10046 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
10047 >= GET_MODE_PRECISION (shift_mode
)))
10048 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10050 /* We simplify the tests below and elsewhere by converting
10051 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10052 `make_compound_operation' will convert it to an ASHIFTRT for
10053 those machines (such as VAX) that don't have an LSHIFTRT. */
10054 if (code
== ASHIFTRT
10055 && val_signbit_known_clear_p (shift_mode
,
10056 nonzero_bits (varop
, shift_mode
)))
10059 if (((code
== LSHIFTRT
10060 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10061 && !(nonzero_bits (varop
, shift_mode
) >> count
))
10063 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10064 && !((nonzero_bits (varop
, shift_mode
) << count
)
10065 & GET_MODE_MASK (shift_mode
))))
10066 && !side_effects_p (varop
))
10067 varop
= const0_rtx
;
10069 switch (GET_CODE (varop
))
10075 new_rtx
= expand_compound_operation (varop
);
10076 if (new_rtx
!= varop
)
10084 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10085 minus the width of a smaller mode, we can do this with a
10086 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10087 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10088 && ! mode_dependent_address_p (XEXP (varop
, 0),
10089 MEM_ADDR_SPACE (varop
))
10090 && ! MEM_VOLATILE_P (varop
)
10091 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10092 MODE_INT
, 1)) != BLKmode
)
10094 new_rtx
= adjust_address_nv (varop
, tmode
,
10095 BYTES_BIG_ENDIAN
? 0
10096 : count
/ BITS_PER_UNIT
);
10098 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10099 : ZERO_EXTEND
, mode
, new_rtx
);
10106 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10107 the same number of words as what we've seen so far. Then store
10108 the widest mode in MODE. */
10109 if (subreg_lowpart_p (varop
)
10110 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10111 > GET_MODE_SIZE (GET_MODE (varop
)))
10112 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10113 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10115 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10116 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10118 varop
= SUBREG_REG (varop
);
10119 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10120 mode
= GET_MODE (varop
);
10126 /* Some machines use MULT instead of ASHIFT because MULT
10127 is cheaper. But it is still better on those machines to
10128 merge two shifts into one. */
10129 if (CONST_INT_P (XEXP (varop
, 1))
10130 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10133 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10135 GEN_INT (exact_log2 (
10136 UINTVAL (XEXP (varop
, 1)))));
10142 /* Similar, for when divides are cheaper. */
10143 if (CONST_INT_P (XEXP (varop
, 1))
10144 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10147 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10149 GEN_INT (exact_log2 (
10150 UINTVAL (XEXP (varop
, 1)))));
10156 /* If we are extracting just the sign bit of an arithmetic
10157 right shift, that shift is not needed. However, the sign
10158 bit of a wider mode may be different from what would be
10159 interpreted as the sign bit in a narrower mode, so, if
10160 the result is narrower, don't discard the shift. */
10161 if (code
== LSHIFTRT
10162 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10163 && (GET_MODE_BITSIZE (result_mode
)
10164 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10166 varop
= XEXP (varop
, 0);
10170 /* ... fall through ... */
10175 /* Here we have two nested shifts. The result is usually the
10176 AND of a new shift with a mask. We compute the result below. */
10177 if (CONST_INT_P (XEXP (varop
, 1))
10178 && INTVAL (XEXP (varop
, 1)) >= 0
10179 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10180 && HWI_COMPUTABLE_MODE_P (result_mode
)
10181 && HWI_COMPUTABLE_MODE_P (mode
)
10182 && !VECTOR_MODE_P (result_mode
))
10184 enum rtx_code first_code
= GET_CODE (varop
);
10185 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10186 unsigned HOST_WIDE_INT mask
;
10189 /* We have one common special case. We can't do any merging if
10190 the inner code is an ASHIFTRT of a smaller mode. However, if
10191 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10192 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10193 we can convert it to
10194 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10195 This simplifies certain SIGN_EXTEND operations. */
10196 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10197 && count
== (GET_MODE_PRECISION (result_mode
)
10198 - GET_MODE_PRECISION (GET_MODE (varop
))))
10200 /* C3 has the low-order C1 bits zero. */
10202 mask
= GET_MODE_MASK (mode
)
10203 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10205 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10206 XEXP (varop
, 0), mask
);
10207 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10209 count
= first_count
;
10214 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10215 than C1 high-order bits equal to the sign bit, we can convert
10216 this to either an ASHIFT or an ASHIFTRT depending on the
10219 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10221 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10222 && GET_MODE (varop
) == shift_mode
10223 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10226 varop
= XEXP (varop
, 0);
10227 count
-= first_count
;
10237 /* There are some cases we can't do. If CODE is ASHIFTRT,
10238 we can only do this if FIRST_CODE is also ASHIFTRT.
10240 We can't do the case when CODE is ROTATE and FIRST_CODE is
10243 If the mode of this shift is not the mode of the outer shift,
10244 we can't do this if either shift is a right shift or ROTATE.
10246 Finally, we can't do any of these if the mode is too wide
10247 unless the codes are the same.
10249 Handle the case where the shift codes are the same
10252 if (code
== first_code
)
10254 if (GET_MODE (varop
) != result_mode
10255 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10256 || code
== ROTATE
))
10259 count
+= first_count
;
10260 varop
= XEXP (varop
, 0);
10264 if (code
== ASHIFTRT
10265 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10266 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10267 || (GET_MODE (varop
) != result_mode
10268 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10269 || first_code
== ROTATE
10270 || code
== ROTATE
)))
10273 /* To compute the mask to apply after the shift, shift the
10274 nonzero bits of the inner shift the same way the
10275 outer shift will. */
10277 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10281 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10284 /* Give up if we can't compute an outer operation to use. */
10286 || !CONST_INT_P (mask_rtx
)
10287 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10289 result_mode
, &complement_p
))
10292 /* If the shifts are in the same direction, we add the
10293 counts. Otherwise, we subtract them. */
10294 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10295 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10296 count
+= first_count
;
10298 count
-= first_count
;
10300 /* If COUNT is positive, the new shift is usually CODE,
10301 except for the two exceptions below, in which case it is
10302 FIRST_CODE. If the count is negative, FIRST_CODE should
10305 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10306 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10308 else if (count
< 0)
10309 code
= first_code
, count
= -count
;
10311 varop
= XEXP (varop
, 0);
10315 /* If we have (A << B << C) for any shift, we can convert this to
10316 (A << C << B). This wins if A is a constant. Only try this if
10317 B is not a constant. */
10319 else if (GET_CODE (varop
) == code
10320 && CONST_INT_P (XEXP (varop
, 0))
10321 && !CONST_INT_P (XEXP (varop
, 1)))
10323 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10326 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10333 if (VECTOR_MODE_P (mode
))
10336 /* Make this fit the case below. */
10337 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10343 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10344 with C the size of VAROP - 1 and the shift is logical if
10345 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10346 we have an (le X 0) operation. If we have an arithmetic shift
10347 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10348 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10350 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10351 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10352 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10353 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10354 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10355 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10358 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10361 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10362 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10367 /* If we have (shift (logical)), move the logical to the outside
10368 to allow it to possibly combine with another logical and the
10369 shift to combine with another shift. This also canonicalizes to
10370 what a ZERO_EXTRACT looks like. Also, some machines have
10371 (and (shift)) insns. */
10373 if (CONST_INT_P (XEXP (varop
, 1))
10374 /* We can't do this if we have (ashiftrt (xor)) and the
10375 constant has its sign bit set in shift_mode with shift_mode
10376 wider than result_mode. */
10377 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10378 && result_mode
!= shift_mode
10379 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10381 && (new_rtx
= simplify_const_binary_operation
10382 (code
, result_mode
,
10383 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10384 GEN_INT (count
))) != 0
10385 && CONST_INT_P (new_rtx
)
10386 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10387 INTVAL (new_rtx
), result_mode
, &complement_p
))
10389 varop
= XEXP (varop
, 0);
10393 /* If we can't do that, try to simplify the shift in each arm of the
10394 logical expression, make a new logical expression, and apply
10395 the inverse distributive law. This also can't be done for
10396 (ashiftrt (xor)) where we've widened the shift and the constant
10397 changes the sign bit. */
10398 if (CONST_INT_P (XEXP (varop
, 1))
10399 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10400 && result_mode
!= shift_mode
10401 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10404 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10405 XEXP (varop
, 0), count
);
10406 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10407 XEXP (varop
, 1), count
);
10409 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10411 varop
= apply_distributive_law (varop
);
10419 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10420 says that the sign bit can be tested, FOO has mode MODE, C is
10421 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10422 that may be nonzero. */
10423 if (code
== LSHIFTRT
10424 && XEXP (varop
, 1) == const0_rtx
10425 && GET_MODE (XEXP (varop
, 0)) == result_mode
10426 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10427 && HWI_COMPUTABLE_MODE_P (result_mode
)
10428 && STORE_FLAG_VALUE
== -1
10429 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10430 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10433 varop
= XEXP (varop
, 0);
10440 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10441 than the number of bits in the mode is equivalent to A. */
10442 if (code
== LSHIFTRT
10443 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10444 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10446 varop
= XEXP (varop
, 0);
10451 /* NEG commutes with ASHIFT since it is multiplication. Move the
10452 NEG outside to allow shifts to combine. */
10454 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10457 varop
= XEXP (varop
, 0);
10463 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10464 is one less than the number of bits in the mode is
10465 equivalent to (xor A 1). */
10466 if (code
== LSHIFTRT
10467 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10468 && XEXP (varop
, 1) == constm1_rtx
10469 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10470 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10474 varop
= XEXP (varop
, 0);
10478 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10479 that might be nonzero in BAR are those being shifted out and those
10480 bits are known zero in FOO, we can replace the PLUS with FOO.
10481 Similarly in the other operand order. This code occurs when
10482 we are computing the size of a variable-size array. */
10484 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10485 && count
< HOST_BITS_PER_WIDE_INT
10486 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10487 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10488 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10490 varop
= XEXP (varop
, 0);
10493 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10494 && count
< HOST_BITS_PER_WIDE_INT
10495 && HWI_COMPUTABLE_MODE_P (result_mode
)
10496 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10498 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10499 & nonzero_bits (XEXP (varop
, 1),
10502 varop
= XEXP (varop
, 1);
10506 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10508 && CONST_INT_P (XEXP (varop
, 1))
10509 && (new_rtx
= simplify_const_binary_operation
10510 (ASHIFT
, result_mode
,
10511 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10512 GEN_INT (count
))) != 0
10513 && CONST_INT_P (new_rtx
)
10514 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10515 INTVAL (new_rtx
), result_mode
, &complement_p
))
10517 varop
= XEXP (varop
, 0);
10521 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10522 signbit', and attempt to change the PLUS to an XOR and move it to
10523 the outer operation as is done above in the AND/IOR/XOR case
10524 leg for shift(logical). See details in logical handling above
10525 for reasoning in doing so. */
10526 if (code
== LSHIFTRT
10527 && CONST_INT_P (XEXP (varop
, 1))
10528 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10529 && (new_rtx
= simplify_const_binary_operation
10530 (code
, result_mode
,
10531 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10532 GEN_INT (count
))) != 0
10533 && CONST_INT_P (new_rtx
)
10534 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10535 INTVAL (new_rtx
), result_mode
, &complement_p
))
10537 varop
= XEXP (varop
, 0);
10544 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10545 with C the size of VAROP - 1 and the shift is logical if
10546 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10547 we have a (gt X 0) operation. If the shift is arithmetic with
10548 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10549 we have a (neg (gt X 0)) operation. */
10551 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10552 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10553 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10554 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10555 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10556 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10557 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10560 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10563 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10564 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10571 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10572 if the truncate does not affect the value. */
10573 if (code
== LSHIFTRT
10574 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10575 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10576 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10577 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10578 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10580 rtx varop_inner
= XEXP (varop
, 0);
10583 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10584 XEXP (varop_inner
, 0),
10586 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10587 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10600 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10601 outer_op
, outer_const
);
10603 /* We have now finished analyzing the shift. The result should be
10604 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10605 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10606 to the result of the shift. OUTER_CONST is the relevant constant,
10607 but we must turn off all bits turned off in the shift. */
10609 if (outer_op
== UNKNOWN
10610 && orig_code
== code
&& orig_count
== count
10611 && varop
== orig_varop
10612 && shift_mode
== GET_MODE (varop
))
10615 /* Make a SUBREG if necessary. If we can't make it, fail. */
10616 varop
= gen_lowpart (shift_mode
, varop
);
10617 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10620 /* If we have an outer operation and we just made a shift, it is
10621 possible that we could have simplified the shift were it not
10622 for the outer operation. So try to do the simplification
10625 if (outer_op
!= UNKNOWN
)
10626 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10631 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10633 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10634 turn off all the bits that the shift would have turned off. */
10635 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10636 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10637 GET_MODE_MASK (result_mode
) >> orig_count
);
10639 /* Do the remainder of the processing in RESULT_MODE. */
10640 x
= gen_lowpart_or_truncate (result_mode
, x
);
10642 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10645 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10647 if (outer_op
!= UNKNOWN
)
10649 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10650 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10651 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10653 if (outer_op
== AND
)
10654 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10655 else if (outer_op
== SET
)
10657 /* This means that we have determined that the result is
10658 equivalent to a constant. This should be rare. */
10659 if (!side_effects_p (x
))
10660 x
= GEN_INT (outer_const
);
10662 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10663 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10665 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10666 GEN_INT (outer_const
));
10672 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10673 The result of the shift is RESULT_MODE. If we cannot simplify it,
10674 return X or, if it is NULL, synthesize the expression with
10675 simplify_gen_binary. Otherwise, return a simplified value.
10677 The shift is normally computed in the widest mode we find in VAROP, as
10678 long as it isn't a different number of words than RESULT_MODE. Exceptions
10679 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10682 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
10683 rtx varop
, int count
)
10685 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10690 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10691 if (GET_MODE (x
) != result_mode
)
10692 x
= gen_lowpart (result_mode
, x
);
10697 /* Like recog, but we receive the address of a pointer to a new pattern.
10698 We try to match the rtx that the pointer points to.
10699 If that fails, we may try to modify or replace the pattern,
10700 storing the replacement into the same pointer object.
10702 Modifications include deletion or addition of CLOBBERs.
10704 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10705 the CLOBBERs are placed.
10707 The value is the final insn code from the pattern ultimately matched,
10711 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10713 rtx pat
= *pnewpat
;
10714 rtx pat_without_clobbers
;
10715 int insn_code_number
;
10716 int num_clobbers_to_add
= 0;
10718 rtx notes
= NULL_RTX
;
10719 rtx old_notes
, old_pat
;
10722 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10723 we use to indicate that something didn't match. If we find such a
10724 thing, force rejection. */
10725 if (GET_CODE (pat
) == PARALLEL
)
10726 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10727 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10728 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10731 old_pat
= PATTERN (insn
);
10732 old_notes
= REG_NOTES (insn
);
10733 PATTERN (insn
) = pat
;
10734 REG_NOTES (insn
) = NULL_RTX
;
10736 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10737 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10739 if (insn_code_number
< 0)
10740 fputs ("Failed to match this instruction:\n", dump_file
);
10742 fputs ("Successfully matched this instruction:\n", dump_file
);
10743 print_rtl_single (dump_file
, pat
);
10746 /* If it isn't, there is the possibility that we previously had an insn
10747 that clobbered some register as a side effect, but the combined
10748 insn doesn't need to do that. So try once more without the clobbers
10749 unless this represents an ASM insn. */
10751 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10752 && GET_CODE (pat
) == PARALLEL
)
10756 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10757 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10760 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10764 SUBST_INT (XVECLEN (pat
, 0), pos
);
10767 pat
= XVECEXP (pat
, 0, 0);
10769 PATTERN (insn
) = pat
;
10770 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10771 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10773 if (insn_code_number
< 0)
10774 fputs ("Failed to match this instruction:\n", dump_file
);
10776 fputs ("Successfully matched this instruction:\n", dump_file
);
10777 print_rtl_single (dump_file
, pat
);
10781 pat_without_clobbers
= pat
;
10783 PATTERN (insn
) = old_pat
;
10784 REG_NOTES (insn
) = old_notes
;
10786 /* Recognize all noop sets, these will be killed by followup pass. */
10787 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10788 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10790 /* If we had any clobbers to add, make a new pattern than contains
10791 them. Then check to make sure that all of them are dead. */
10792 if (num_clobbers_to_add
)
10794 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10795 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10796 ? (XVECLEN (pat
, 0)
10797 + num_clobbers_to_add
)
10798 : num_clobbers_to_add
+ 1));
10800 if (GET_CODE (pat
) == PARALLEL
)
10801 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10802 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10804 XVECEXP (newpat
, 0, 0) = pat
;
10806 add_clobbers (newpat
, insn_code_number
);
10808 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10809 i
< XVECLEN (newpat
, 0); i
++)
10811 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10812 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10814 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10816 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10817 notes
= alloc_reg_note (REG_UNUSED
,
10818 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10824 if (insn_code_number
>= 0
10825 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10827 old_pat
= PATTERN (insn
);
10828 old_notes
= REG_NOTES (insn
);
10829 old_icode
= INSN_CODE (insn
);
10830 PATTERN (insn
) = pat
;
10831 REG_NOTES (insn
) = notes
;
10833 /* Allow targets to reject combined insn. */
10834 if (!targetm
.legitimate_combined_insn (insn
))
10836 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10837 fputs ("Instruction not appropriate for target.",
10840 /* Callers expect recog_for_combine to strip
10841 clobbers from the pattern on failure. */
10842 pat
= pat_without_clobbers
;
10845 insn_code_number
= -1;
10848 PATTERN (insn
) = old_pat
;
10849 REG_NOTES (insn
) = old_notes
;
10850 INSN_CODE (insn
) = old_icode
;
10856 return insn_code_number
;
10859 /* Like gen_lowpart_general but for use by combine. In combine it
10860 is not possible to create any new pseudoregs. However, it is
10861 safe to create invalid memory addresses, because combine will
10862 try to recognize them and all they will do is make the combine
10865 If for some reason this cannot do its job, an rtx
10866 (clobber (const_int 0)) is returned.
10867 An insn containing that will not be recognized. */
10870 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
10872 machine_mode imode
= GET_MODE (x
);
10873 unsigned int osize
= GET_MODE_SIZE (omode
);
10874 unsigned int isize
= GET_MODE_SIZE (imode
);
10877 if (omode
== imode
)
10880 /* We can only support MODE being wider than a word if X is a
10881 constant integer or has a mode the same size. */
10882 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10883 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
10886 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10887 won't know what to do. So we will strip off the SUBREG here and
10888 process normally. */
10889 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10891 x
= SUBREG_REG (x
);
10893 /* For use in case we fall down into the address adjustments
10894 further below, we need to adjust the known mode and size of
10895 x; imode and isize, since we just adjusted x. */
10896 imode
= GET_MODE (x
);
10898 if (imode
== omode
)
10901 isize
= GET_MODE_SIZE (imode
);
10904 result
= gen_lowpart_common (omode
, x
);
10913 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10915 if (MEM_VOLATILE_P (x
)
10916 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10919 /* If we want to refer to something bigger than the original memref,
10920 generate a paradoxical subreg instead. That will force a reload
10921 of the original memref X. */
10923 return gen_rtx_SUBREG (omode
, x
, 0);
10925 if (WORDS_BIG_ENDIAN
)
10926 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10928 /* Adjust the address so that the address-after-the-data is
10930 if (BYTES_BIG_ENDIAN
)
10931 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10933 return adjust_address_nv (x
, omode
, offset
);
10936 /* If X is a comparison operator, rewrite it in a new mode. This
10937 probably won't match, but may allow further simplifications. */
10938 else if (COMPARISON_P (x
))
10939 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10941 /* If we couldn't simplify X any other way, just enclose it in a
10942 SUBREG. Normally, this SUBREG won't match, but some patterns may
10943 include an explicit SUBREG or we may simplify it further in combine. */
10949 offset
= subreg_lowpart_offset (omode
, imode
);
10950 if (imode
== VOIDmode
)
10952 imode
= int_mode_for_mode (omode
);
10953 x
= gen_lowpart_common (imode
, x
);
10957 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10963 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10966 /* Try to simplify a comparison between OP0 and a constant OP1,
10967 where CODE is the comparison code that will be tested, into a
10968 (CODE OP0 const0_rtx) form.
10970 The result is a possibly different comparison code to use.
10971 *POP1 may be updated. */
10973 static enum rtx_code
10974 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
10975 rtx op0
, rtx
*pop1
)
10977 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10978 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10980 /* Get the constant we are comparing against and turn off all bits
10981 not on in our mode. */
10982 if (mode
!= VOIDmode
)
10983 const_op
= trunc_int_for_mode (const_op
, mode
);
10985 /* If we are comparing against a constant power of two and the value
10986 being compared can only have that single bit nonzero (e.g., it was
10987 `and'ed with that bit), we can replace this with a comparison
10990 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10991 || code
== LT
|| code
== LTU
)
10992 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10993 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
10994 && (nonzero_bits (op0
, mode
)
10995 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
10997 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11001 /* Similarly, if we are comparing a value known to be either -1 or
11002 0 with -1, change it to the opposite comparison against zero. */
11004 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11005 || code
== GEU
|| code
== LTU
)
11006 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11008 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11012 /* Do some canonicalizations based on the comparison code. We prefer
11013 comparisons against zero and then prefer equality comparisons.
11014 If we can reduce the size of a constant, we will do that too. */
11018 /* < C is equivalent to <= (C - 1) */
11023 /* ... fall through to LE case below. */
11029 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11036 /* If we are doing a <= 0 comparison on a value known to have
11037 a zero sign bit, we can replace this with == 0. */
11038 else if (const_op
== 0
11039 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11040 && (nonzero_bits (op0
, mode
)
11041 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11047 /* >= C is equivalent to > (C - 1). */
11052 /* ... fall through to GT below. */
11058 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11065 /* If we are doing a > 0 comparison on a value known to have
11066 a zero sign bit, we can replace this with != 0. */
11067 else if (const_op
== 0
11068 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11069 && (nonzero_bits (op0
, mode
)
11070 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11076 /* < C is equivalent to <= (C - 1). */
11081 /* ... fall through ... */
11083 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11084 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11085 && (unsigned HOST_WIDE_INT
) const_op
11086 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11096 /* unsigned <= 0 is equivalent to == 0 */
11099 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11100 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11101 && (unsigned HOST_WIDE_INT
) const_op
11102 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11110 /* >= C is equivalent to > (C - 1). */
11115 /* ... fall through ... */
11118 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11119 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11120 && (unsigned HOST_WIDE_INT
) const_op
11121 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11131 /* unsigned > 0 is equivalent to != 0 */
11134 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11135 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11136 && (unsigned HOST_WIDE_INT
) const_op
11137 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11148 *pop1
= GEN_INT (const_op
);
11152 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11153 comparison code that will be tested.
11155 The result is a possibly different comparison code to use. *POP0 and
11156 *POP1 may be updated.
11158 It is possible that we might detect that a comparison is either always
11159 true or always false. However, we do not perform general constant
11160 folding in combine, so this knowledge isn't useful. Such tautologies
11161 should have been detected earlier. Hence we ignore all such cases. */
11163 static enum rtx_code
11164 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11170 machine_mode mode
, tmode
;
11172 /* Try a few ways of applying the same transformation to both operands. */
11175 #ifndef WORD_REGISTER_OPERATIONS
11176 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11177 so check specially. */
11178 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11179 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11180 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11181 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11182 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11183 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11184 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11185 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11186 && CONST_INT_P (XEXP (op0
, 1))
11187 && XEXP (op0
, 1) == XEXP (op1
, 1)
11188 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11189 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11190 && (INTVAL (XEXP (op0
, 1))
11191 == (GET_MODE_PRECISION (GET_MODE (op0
))
11192 - (GET_MODE_PRECISION
11193 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11195 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11196 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11200 /* If both operands are the same constant shift, see if we can ignore the
11201 shift. We can if the shift is a rotate or if the bits shifted out of
11202 this shift are known to be zero for both inputs and if the type of
11203 comparison is compatible with the shift. */
11204 if (GET_CODE (op0
) == GET_CODE (op1
)
11205 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11206 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11207 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11208 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11209 || (GET_CODE (op0
) == ASHIFTRT
11210 && (code
!= GTU
&& code
!= LTU
11211 && code
!= GEU
&& code
!= LEU
)))
11212 && CONST_INT_P (XEXP (op0
, 1))
11213 && INTVAL (XEXP (op0
, 1)) >= 0
11214 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11215 && XEXP (op0
, 1) == XEXP (op1
, 1))
11217 machine_mode mode
= GET_MODE (op0
);
11218 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11219 int shift_count
= INTVAL (XEXP (op0
, 1));
11221 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11222 mask
&= (mask
>> shift_count
) << shift_count
;
11223 else if (GET_CODE (op0
) == ASHIFT
)
11224 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11226 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11227 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11228 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11233 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11234 SUBREGs are of the same mode, and, in both cases, the AND would
11235 be redundant if the comparison was done in the narrower mode,
11236 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11237 and the operand's possibly nonzero bits are 0xffffff01; in that case
11238 if we only care about QImode, we don't need the AND). This case
11239 occurs if the output mode of an scc insn is not SImode and
11240 STORE_FLAG_VALUE == 1 (e.g., the 386).
11242 Similarly, check for a case where the AND's are ZERO_EXTEND
11243 operations from some narrower mode even though a SUBREG is not
11246 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11247 && CONST_INT_P (XEXP (op0
, 1))
11248 && CONST_INT_P (XEXP (op1
, 1)))
11250 rtx inner_op0
= XEXP (op0
, 0);
11251 rtx inner_op1
= XEXP (op1
, 0);
11252 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11253 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11256 if (paradoxical_subreg_p (inner_op0
)
11257 && GET_CODE (inner_op1
) == SUBREG
11258 && (GET_MODE (SUBREG_REG (inner_op0
))
11259 == GET_MODE (SUBREG_REG (inner_op1
)))
11260 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11261 <= HOST_BITS_PER_WIDE_INT
)
11262 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11263 GET_MODE (SUBREG_REG (inner_op0
)))))
11264 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11265 GET_MODE (SUBREG_REG (inner_op1
))))))
11267 op0
= SUBREG_REG (inner_op0
);
11268 op1
= SUBREG_REG (inner_op1
);
11270 /* The resulting comparison is always unsigned since we masked
11271 off the original sign bit. */
11272 code
= unsigned_condition (code
);
11278 for (tmode
= GET_CLASS_NARROWEST_MODE
11279 (GET_MODE_CLASS (GET_MODE (op0
)));
11280 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11281 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11283 op0
= gen_lowpart (tmode
, inner_op0
);
11284 op1
= gen_lowpart (tmode
, inner_op1
);
11285 code
= unsigned_condition (code
);
11294 /* If both operands are NOT, we can strip off the outer operation
11295 and adjust the comparison code for swapped operands; similarly for
11296 NEG, except that this must be an equality comparison. */
11297 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11298 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11299 && (code
== EQ
|| code
== NE
)))
11300 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11306 /* If the first operand is a constant, swap the operands and adjust the
11307 comparison code appropriately, but don't do this if the second operand
11308 is already a constant integer. */
11309 if (swap_commutative_operands_p (op0
, op1
))
11311 tem
= op0
, op0
= op1
, op1
= tem
;
11312 code
= swap_condition (code
);
11315 /* We now enter a loop during which we will try to simplify the comparison.
11316 For the most part, we only are concerned with comparisons with zero,
11317 but some things may really be comparisons with zero but not start
11318 out looking that way. */
11320 while (CONST_INT_P (op1
))
11322 machine_mode mode
= GET_MODE (op0
);
11323 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11324 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11325 int equality_comparison_p
;
11326 int sign_bit_comparison_p
;
11327 int unsigned_comparison_p
;
11328 HOST_WIDE_INT const_op
;
11330 /* We only want to handle integral modes. This catches VOIDmode,
11331 CCmode, and the floating-point modes. An exception is that we
11332 can handle VOIDmode if OP0 is a COMPARE or a comparison
11335 if (GET_MODE_CLASS (mode
) != MODE_INT
11336 && ! (mode
== VOIDmode
11337 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11340 /* Try to simplify the compare to constant, possibly changing the
11341 comparison op, and/or changing op1 to zero. */
11342 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11343 const_op
= INTVAL (op1
);
11345 /* Compute some predicates to simplify code below. */
11347 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11348 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11349 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11352 /* If this is a sign bit comparison and we can do arithmetic in
11353 MODE, say that we will only be needing the sign bit of OP0. */
11354 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11355 op0
= force_to_mode (op0
, mode
,
11356 (unsigned HOST_WIDE_INT
) 1
11357 << (GET_MODE_PRECISION (mode
) - 1),
11360 /* Now try cases based on the opcode of OP0. If none of the cases
11361 does a "continue", we exit this loop immediately after the
11364 switch (GET_CODE (op0
))
11367 /* If we are extracting a single bit from a variable position in
11368 a constant that has only a single bit set and are comparing it
11369 with zero, we can convert this into an equality comparison
11370 between the position and the location of the single bit. */
11371 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11372 have already reduced the shift count modulo the word size. */
11373 if (!SHIFT_COUNT_TRUNCATED
11374 && CONST_INT_P (XEXP (op0
, 0))
11375 && XEXP (op0
, 1) == const1_rtx
11376 && equality_comparison_p
&& const_op
== 0
11377 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11379 if (BITS_BIG_ENDIAN
)
11380 i
= BITS_PER_WORD
- 1 - i
;
11382 op0
= XEXP (op0
, 2);
11386 /* Result is nonzero iff shift count is equal to I. */
11387 code
= reverse_condition (code
);
11391 /* ... fall through ... */
11394 tem
= expand_compound_operation (op0
);
11403 /* If testing for equality, we can take the NOT of the constant. */
11404 if (equality_comparison_p
11405 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11407 op0
= XEXP (op0
, 0);
11412 /* If just looking at the sign bit, reverse the sense of the
11414 if (sign_bit_comparison_p
)
11416 op0
= XEXP (op0
, 0);
11417 code
= (code
== GE
? LT
: GE
);
11423 /* If testing for equality, we can take the NEG of the constant. */
11424 if (equality_comparison_p
11425 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11427 op0
= XEXP (op0
, 0);
11432 /* The remaining cases only apply to comparisons with zero. */
11436 /* When X is ABS or is known positive,
11437 (neg X) is < 0 if and only if X != 0. */
11439 if (sign_bit_comparison_p
11440 && (GET_CODE (XEXP (op0
, 0)) == ABS
11441 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11442 && (nonzero_bits (XEXP (op0
, 0), mode
)
11443 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11446 op0
= XEXP (op0
, 0);
11447 code
= (code
== LT
? NE
: EQ
);
11451 /* If we have NEG of something whose two high-order bits are the
11452 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11453 if (num_sign_bit_copies (op0
, mode
) >= 2)
11455 op0
= XEXP (op0
, 0);
11456 code
= swap_condition (code
);
11462 /* If we are testing equality and our count is a constant, we
11463 can perform the inverse operation on our RHS. */
11464 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11465 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11466 op1
, XEXP (op0
, 1))) != 0)
11468 op0
= XEXP (op0
, 0);
11473 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11474 a particular bit. Convert it to an AND of a constant of that
11475 bit. This will be converted into a ZERO_EXTRACT. */
11476 if (const_op
== 0 && sign_bit_comparison_p
11477 && CONST_INT_P (XEXP (op0
, 1))
11478 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11480 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11481 ((unsigned HOST_WIDE_INT
) 1
11483 - INTVAL (XEXP (op0
, 1)))));
11484 code
= (code
== LT
? NE
: EQ
);
11488 /* Fall through. */
11491 /* ABS is ignorable inside an equality comparison with zero. */
11492 if (const_op
== 0 && equality_comparison_p
)
11494 op0
= XEXP (op0
, 0);
11500 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11501 (compare FOO CONST) if CONST fits in FOO's mode and we
11502 are either testing inequality or have an unsigned
11503 comparison with ZERO_EXTEND or a signed comparison with
11504 SIGN_EXTEND. But don't do it if we don't have a compare
11505 insn of the given mode, since we'd have to revert it
11506 later on, and then we wouldn't know whether to sign- or
11508 mode
= GET_MODE (XEXP (op0
, 0));
11509 if (GET_MODE_CLASS (mode
) == MODE_INT
11510 && ! unsigned_comparison_p
11511 && HWI_COMPUTABLE_MODE_P (mode
)
11512 && trunc_int_for_mode (const_op
, mode
) == const_op
11513 && have_insn_for (COMPARE
, mode
))
11515 op0
= XEXP (op0
, 0);
11521 /* Check for the case where we are comparing A - C1 with C2, that is
11523 (subreg:MODE (plus (A) (-C1))) op (C2)
11525 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11526 comparison in the wider mode. One of the following two conditions
11527 must be true in order for this to be valid:
11529 1. The mode extension results in the same bit pattern being added
11530 on both sides and the comparison is equality or unsigned. As
11531 C2 has been truncated to fit in MODE, the pattern can only be
11534 2. The mode extension results in the sign bit being copied on
11537 The difficulty here is that we have predicates for A but not for
11538 (A - C1) so we need to check that C1 is within proper bounds so
11539 as to perturbate A as little as possible. */
11541 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11542 && subreg_lowpart_p (op0
)
11543 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11544 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11545 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11547 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11548 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11549 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11552 && (unsigned HOST_WIDE_INT
) c1
11553 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11554 && (equality_comparison_p
|| unsigned_comparison_p
)
11555 /* (A - C1) zero-extends if it is positive and sign-extends
11556 if it is negative, C2 both zero- and sign-extends. */
11557 && ((0 == (nonzero_bits (a
, inner_mode
)
11558 & ~GET_MODE_MASK (mode
))
11560 /* (A - C1) sign-extends if it is positive and 1-extends
11561 if it is negative, C2 both sign- and 1-extends. */
11562 || (num_sign_bit_copies (a
, inner_mode
)
11563 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11566 || ((unsigned HOST_WIDE_INT
) c1
11567 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11568 /* (A - C1) always sign-extends, like C2. */
11569 && num_sign_bit_copies (a
, inner_mode
)
11570 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11571 - (mode_width
- 1))))
11573 op0
= SUBREG_REG (op0
);
11578 /* If the inner mode is narrower and we are extracting the low part,
11579 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11580 if (subreg_lowpart_p (op0
)
11581 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11582 /* Fall through */ ;
11586 /* ... fall through ... */
11589 mode
= GET_MODE (XEXP (op0
, 0));
11590 if (GET_MODE_CLASS (mode
) == MODE_INT
11591 && (unsigned_comparison_p
|| equality_comparison_p
)
11592 && HWI_COMPUTABLE_MODE_P (mode
)
11593 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11595 && have_insn_for (COMPARE
, mode
))
11597 op0
= XEXP (op0
, 0);
11603 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11604 this for equality comparisons due to pathological cases involving
11606 if (equality_comparison_p
11607 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11608 op1
, XEXP (op0
, 1))))
11610 op0
= XEXP (op0
, 0);
11615 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11616 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11617 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11619 op0
= XEXP (XEXP (op0
, 0), 0);
11620 code
= (code
== LT
? EQ
: NE
);
11626 /* We used to optimize signed comparisons against zero, but that
11627 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11628 arrive here as equality comparisons, or (GEU, LTU) are
11629 optimized away. No need to special-case them. */
11631 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11632 (eq B (minus A C)), whichever simplifies. We can only do
11633 this for equality comparisons due to pathological cases involving
11635 if (equality_comparison_p
11636 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11637 XEXP (op0
, 1), op1
)))
11639 op0
= XEXP (op0
, 0);
11644 if (equality_comparison_p
11645 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11646 XEXP (op0
, 0), op1
)))
11648 op0
= XEXP (op0
, 1);
11653 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11654 of bits in X minus 1, is one iff X > 0. */
11655 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11656 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11657 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11658 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11660 op0
= XEXP (op0
, 1);
11661 code
= (code
== GE
? LE
: GT
);
11667 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11668 if C is zero or B is a constant. */
11669 if (equality_comparison_p
11670 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11671 XEXP (op0
, 1), op1
)))
11673 op0
= XEXP (op0
, 0);
11680 case UNEQ
: case LTGT
:
11681 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11682 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11683 case UNORDERED
: case ORDERED
:
11684 /* We can't do anything if OP0 is a condition code value, rather
11685 than an actual data value. */
11687 || CC0_P (XEXP (op0
, 0))
11688 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11691 /* Get the two operands being compared. */
11692 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11693 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11695 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11697 /* Check for the cases where we simply want the result of the
11698 earlier test or the opposite of that result. */
11699 if (code
== NE
|| code
== EQ
11700 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11701 && (code
== LT
|| code
== GE
)))
11703 enum rtx_code new_code
;
11704 if (code
== LT
|| code
== NE
)
11705 new_code
= GET_CODE (op0
);
11707 new_code
= reversed_comparison_code (op0
, NULL
);
11709 if (new_code
!= UNKNOWN
)
11720 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11722 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11723 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11724 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11726 op0
= XEXP (op0
, 1);
11727 code
= (code
== GE
? GT
: LE
);
11733 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11734 will be converted to a ZERO_EXTRACT later. */
11735 if (const_op
== 0 && equality_comparison_p
11736 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11737 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11739 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11740 XEXP (XEXP (op0
, 0), 1));
11741 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11745 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11746 zero and X is a comparison and C1 and C2 describe only bits set
11747 in STORE_FLAG_VALUE, we can compare with X. */
11748 if (const_op
== 0 && equality_comparison_p
11749 && mode_width
<= HOST_BITS_PER_WIDE_INT
11750 && CONST_INT_P (XEXP (op0
, 1))
11751 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11752 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11753 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11754 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11756 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11757 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11758 if ((~STORE_FLAG_VALUE
& mask
) == 0
11759 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11760 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11761 && COMPARISON_P (tem
))))
11763 op0
= XEXP (XEXP (op0
, 0), 0);
11768 /* If we are doing an equality comparison of an AND of a bit equal
11769 to the sign bit, replace this with a LT or GE comparison of
11770 the underlying value. */
11771 if (equality_comparison_p
11773 && CONST_INT_P (XEXP (op0
, 1))
11774 && mode_width
<= HOST_BITS_PER_WIDE_INT
11775 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11776 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11778 op0
= XEXP (op0
, 0);
11779 code
= (code
== EQ
? GE
: LT
);
11783 /* If this AND operation is really a ZERO_EXTEND from a narrower
11784 mode, the constant fits within that mode, and this is either an
11785 equality or unsigned comparison, try to do this comparison in
11790 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11791 -> (ne:DI (reg:SI 4) (const_int 0))
11793 unless TRULY_NOOP_TRUNCATION allows it or the register is
11794 known to hold a value of the required mode the
11795 transformation is invalid. */
11796 if ((equality_comparison_p
|| unsigned_comparison_p
)
11797 && CONST_INT_P (XEXP (op0
, 1))
11798 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11799 & GET_MODE_MASK (mode
))
11801 && const_op
>> i
== 0
11802 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11803 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11804 || (REG_P (XEXP (op0
, 0))
11805 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11807 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11811 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11812 fits in both M1 and M2 and the SUBREG is either paradoxical
11813 or represents the low part, permute the SUBREG and the AND
11815 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11817 unsigned HOST_WIDE_INT c1
;
11818 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11819 /* Require an integral mode, to avoid creating something like
11821 if (SCALAR_INT_MODE_P (tmode
)
11822 /* It is unsafe to commute the AND into the SUBREG if the
11823 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11824 not defined. As originally written the upper bits
11825 have a defined value due to the AND operation.
11826 However, if we commute the AND inside the SUBREG then
11827 they no longer have defined values and the meaning of
11828 the code has been changed. */
11830 #ifdef WORD_REGISTER_OPERATIONS
11831 || (mode_width
> GET_MODE_PRECISION (tmode
)
11832 && mode_width
<= BITS_PER_WORD
)
11834 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11835 && subreg_lowpart_p (XEXP (op0
, 0))))
11836 && CONST_INT_P (XEXP (op0
, 1))
11837 && mode_width
<= HOST_BITS_PER_WIDE_INT
11838 && HWI_COMPUTABLE_MODE_P (tmode
)
11839 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11840 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11842 && c1
!= GET_MODE_MASK (tmode
))
11844 op0
= simplify_gen_binary (AND
, tmode
,
11845 SUBREG_REG (XEXP (op0
, 0)),
11846 gen_int_mode (c1
, tmode
));
11847 op0
= gen_lowpart (mode
, op0
);
11852 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11853 if (const_op
== 0 && equality_comparison_p
11854 && XEXP (op0
, 1) == const1_rtx
11855 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11857 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11858 XEXP (XEXP (op0
, 0), 0), 1);
11859 code
= (code
== NE
? EQ
: NE
);
11863 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11864 (eq (and (lshiftrt X) 1) 0).
11865 Also handle the case where (not X) is expressed using xor. */
11866 if (const_op
== 0 && equality_comparison_p
11867 && XEXP (op0
, 1) == const1_rtx
11868 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11870 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11871 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11873 if (GET_CODE (shift_op
) == NOT
11874 || (GET_CODE (shift_op
) == XOR
11875 && CONST_INT_P (XEXP (shift_op
, 1))
11876 && CONST_INT_P (shift_count
)
11877 && HWI_COMPUTABLE_MODE_P (mode
)
11878 && (UINTVAL (XEXP (shift_op
, 1))
11879 == (unsigned HOST_WIDE_INT
) 1
11880 << INTVAL (shift_count
))))
11883 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11884 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11885 code
= (code
== NE
? EQ
: NE
);
11892 /* If we have (compare (ashift FOO N) (const_int C)) and
11893 the high order N bits of FOO (N+1 if an inequality comparison)
11894 are known to be zero, we can do this by comparing FOO with C
11895 shifted right N bits so long as the low-order N bits of C are
11897 if (CONST_INT_P (XEXP (op0
, 1))
11898 && INTVAL (XEXP (op0
, 1)) >= 0
11899 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11900 < HOST_BITS_PER_WIDE_INT
)
11901 && (((unsigned HOST_WIDE_INT
) const_op
11902 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11904 && mode_width
<= HOST_BITS_PER_WIDE_INT
11905 && (nonzero_bits (XEXP (op0
, 0), mode
)
11906 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11907 + ! equality_comparison_p
))) == 0)
11909 /* We must perform a logical shift, not an arithmetic one,
11910 as we want the top N bits of C to be zero. */
11911 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11913 temp
>>= INTVAL (XEXP (op0
, 1));
11914 op1
= gen_int_mode (temp
, mode
);
11915 op0
= XEXP (op0
, 0);
11919 /* If we are doing a sign bit comparison, it means we are testing
11920 a particular bit. Convert it to the appropriate AND. */
11921 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11922 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11924 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11925 ((unsigned HOST_WIDE_INT
) 1
11927 - INTVAL (XEXP (op0
, 1)))));
11928 code
= (code
== LT
? NE
: EQ
);
11932 /* If this an equality comparison with zero and we are shifting
11933 the low bit to the sign bit, we can convert this to an AND of the
11935 if (const_op
== 0 && equality_comparison_p
11936 && CONST_INT_P (XEXP (op0
, 1))
11937 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11939 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11945 /* If this is an equality comparison with zero, we can do this
11946 as a logical shift, which might be much simpler. */
11947 if (equality_comparison_p
&& const_op
== 0
11948 && CONST_INT_P (XEXP (op0
, 1)))
11950 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11952 INTVAL (XEXP (op0
, 1)));
11956 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11957 do the comparison in a narrower mode. */
11958 if (! unsigned_comparison_p
11959 && CONST_INT_P (XEXP (op0
, 1))
11960 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11961 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11962 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11963 MODE_INT
, 1)) != BLKmode
11964 && (((unsigned HOST_WIDE_INT
) const_op
11965 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11966 <= GET_MODE_MASK (tmode
)))
11968 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11972 /* Likewise if OP0 is a PLUS of a sign extension with a
11973 constant, which is usually represented with the PLUS
11974 between the shifts. */
11975 if (! unsigned_comparison_p
11976 && CONST_INT_P (XEXP (op0
, 1))
11977 && GET_CODE (XEXP (op0
, 0)) == PLUS
11978 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11979 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11980 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11981 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11982 MODE_INT
, 1)) != BLKmode
11983 && (((unsigned HOST_WIDE_INT
) const_op
11984 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11985 <= GET_MODE_MASK (tmode
)))
11987 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11988 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11989 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11990 add_const
, XEXP (op0
, 1));
11992 op0
= simplify_gen_binary (PLUS
, tmode
,
11993 gen_lowpart (tmode
, inner
),
11998 /* ... fall through ... */
12000 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12001 the low order N bits of FOO are known to be zero, we can do this
12002 by comparing FOO with C shifted left N bits so long as no
12003 overflow occurs. Even if the low order N bits of FOO aren't known
12004 to be zero, if the comparison is >= or < we can use the same
12005 optimization and for > or <= by setting all the low
12006 order N bits in the comparison constant. */
12007 if (CONST_INT_P (XEXP (op0
, 1))
12008 && INTVAL (XEXP (op0
, 1)) > 0
12009 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12010 && mode_width
<= HOST_BITS_PER_WIDE_INT
12011 && (((unsigned HOST_WIDE_INT
) const_op
12012 + (GET_CODE (op0
) != LSHIFTRT
12013 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12016 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12018 unsigned HOST_WIDE_INT low_bits
12019 = (nonzero_bits (XEXP (op0
, 0), mode
)
12020 & (((unsigned HOST_WIDE_INT
) 1
12021 << INTVAL (XEXP (op0
, 1))) - 1));
12022 if (low_bits
== 0 || !equality_comparison_p
)
12024 /* If the shift was logical, then we must make the condition
12026 if (GET_CODE (op0
) == LSHIFTRT
)
12027 code
= unsigned_condition (code
);
12029 const_op
<<= INTVAL (XEXP (op0
, 1));
12031 && (code
== GT
|| code
== GTU
12032 || code
== LE
|| code
== LEU
))
12034 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
12035 op1
= GEN_INT (const_op
);
12036 op0
= XEXP (op0
, 0);
12041 /* If we are using this shift to extract just the sign bit, we
12042 can replace this with an LT or GE comparison. */
12044 && (equality_comparison_p
|| sign_bit_comparison_p
)
12045 && CONST_INT_P (XEXP (op0
, 1))
12046 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12048 op0
= XEXP (op0
, 0);
12049 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12061 /* Now make any compound operations involved in this comparison. Then,
12062 check for an outmost SUBREG on OP0 that is not doing anything or is
12063 paradoxical. The latter transformation must only be performed when
12064 it is known that the "extra" bits will be the same in op0 and op1 or
12065 that they don't matter. There are three cases to consider:
12067 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12068 care bits and we can assume they have any convenient value. So
12069 making the transformation is safe.
12071 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12072 In this case the upper bits of op0 are undefined. We should not make
12073 the simplification in that case as we do not know the contents of
12076 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12077 UNKNOWN. In that case we know those bits are zeros or ones. We must
12078 also be sure that they are the same as the upper bits of op1.
12080 We can never remove a SUBREG for a non-equality comparison because
12081 the sign bit is in a different place in the underlying object. */
12083 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
12084 op1
= make_compound_operation (op1
, SET
);
12086 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12087 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12088 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12089 && (code
== NE
|| code
== EQ
))
12091 if (paradoxical_subreg_p (op0
))
12093 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12095 if (REG_P (SUBREG_REG (op0
)))
12097 op0
= SUBREG_REG (op0
);
12098 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12101 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12102 <= HOST_BITS_PER_WIDE_INT
)
12103 && (nonzero_bits (SUBREG_REG (op0
),
12104 GET_MODE (SUBREG_REG (op0
)))
12105 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12107 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12109 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12110 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12111 op0
= SUBREG_REG (op0
), op1
= tem
;
12115 /* We now do the opposite procedure: Some machines don't have compare
12116 insns in all modes. If OP0's mode is an integer mode smaller than a
12117 word and we can't do a compare in that mode, see if there is a larger
12118 mode for which we can do the compare. There are a number of cases in
12119 which we can use the wider mode. */
12121 mode
= GET_MODE (op0
);
12122 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12123 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12124 && ! have_insn_for (COMPARE
, mode
))
12125 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12126 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12127 tmode
= GET_MODE_WIDER_MODE (tmode
))
12128 if (have_insn_for (COMPARE
, tmode
))
12132 /* If this is a test for negative, we can make an explicit
12133 test of the sign bit. Test this first so we can use
12134 a paradoxical subreg to extend OP0. */
12136 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12137 && HWI_COMPUTABLE_MODE_P (mode
))
12139 unsigned HOST_WIDE_INT sign
12140 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
12141 op0
= simplify_gen_binary (AND
, tmode
,
12142 gen_lowpart (tmode
, op0
),
12143 gen_int_mode (sign
, tmode
));
12144 code
= (code
== LT
) ? NE
: EQ
;
12148 /* If the only nonzero bits in OP0 and OP1 are those in the
12149 narrower mode and this is an equality or unsigned comparison,
12150 we can use the wider mode. Similarly for sign-extended
12151 values, in which case it is true for all comparisons. */
12152 zero_extended
= ((code
== EQ
|| code
== NE
12153 || code
== GEU
|| code
== GTU
12154 || code
== LEU
|| code
== LTU
)
12155 && (nonzero_bits (op0
, tmode
)
12156 & ~GET_MODE_MASK (mode
)) == 0
12157 && ((CONST_INT_P (op1
)
12158 || (nonzero_bits (op1
, tmode
)
12159 & ~GET_MODE_MASK (mode
)) == 0)));
12162 || ((num_sign_bit_copies (op0
, tmode
)
12163 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12164 - GET_MODE_PRECISION (mode
)))
12165 && (num_sign_bit_copies (op1
, tmode
)
12166 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12167 - GET_MODE_PRECISION (mode
)))))
12169 /* If OP0 is an AND and we don't have an AND in MODE either,
12170 make a new AND in the proper mode. */
12171 if (GET_CODE (op0
) == AND
12172 && !have_insn_for (AND
, mode
))
12173 op0
= simplify_gen_binary (AND
, tmode
,
12174 gen_lowpart (tmode
,
12176 gen_lowpart (tmode
,
12182 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12183 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12187 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12188 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12195 /* We may have changed the comparison operands. Re-canonicalize. */
12196 if (swap_commutative_operands_p (op0
, op1
))
12198 tem
= op0
, op0
= op1
, op1
= tem
;
12199 code
= swap_condition (code
);
12202 /* If this machine only supports a subset of valid comparisons, see if we
12203 can convert an unsupported one into a supported one. */
12204 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12212 /* Utility function for record_value_for_reg. Count number of
12217 enum rtx_code code
= GET_CODE (x
);
12221 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12222 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12224 rtx x0
= XEXP (x
, 0);
12225 rtx x1
= XEXP (x
, 1);
12228 return 1 + 2 * count_rtxs (x0
);
12230 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12231 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12232 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12233 return 2 + 2 * count_rtxs (x0
)
12234 + count_rtxs (x
== XEXP (x1
, 0)
12235 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12237 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12238 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12239 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12240 return 2 + 2 * count_rtxs (x1
)
12241 + count_rtxs (x
== XEXP (x0
, 0)
12242 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12245 fmt
= GET_RTX_FORMAT (code
);
12246 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12248 ret
+= count_rtxs (XEXP (x
, i
));
12249 else if (fmt
[i
] == 'E')
12250 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12251 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12256 /* Utility function for following routine. Called when X is part of a value
12257 being stored into last_set_value. Sets last_set_table_tick
12258 for each register mentioned. Similar to mention_regs in cse.c */
12261 update_table_tick (rtx x
)
12263 enum rtx_code code
= GET_CODE (x
);
12264 const char *fmt
= GET_RTX_FORMAT (code
);
12269 unsigned int regno
= REGNO (x
);
12270 unsigned int endregno
= END_REGNO (x
);
12273 for (r
= regno
; r
< endregno
; r
++)
12275 reg_stat_type
*rsp
= ®_stat
[r
];
12276 rsp
->last_set_table_tick
= label_tick
;
12282 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12285 /* Check for identical subexpressions. If x contains
12286 identical subexpression we only have to traverse one of
12288 if (i
== 0 && ARITHMETIC_P (x
))
12290 /* Note that at this point x1 has already been
12292 rtx x0
= XEXP (x
, 0);
12293 rtx x1
= XEXP (x
, 1);
12295 /* If x0 and x1 are identical then there is no need to
12300 /* If x0 is identical to a subexpression of x1 then while
12301 processing x1, x0 has already been processed. Thus we
12302 are done with x. */
12303 if (ARITHMETIC_P (x1
)
12304 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12307 /* If x1 is identical to a subexpression of x0 then we
12308 still have to process the rest of x0. */
12309 if (ARITHMETIC_P (x0
)
12310 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12312 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12317 update_table_tick (XEXP (x
, i
));
12319 else if (fmt
[i
] == 'E')
12320 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12321 update_table_tick (XVECEXP (x
, i
, j
));
12324 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12325 are saying that the register is clobbered and we no longer know its
12326 value. If INSN is zero, don't update reg_stat[].last_set; this is
12327 only permitted with VALUE also zero and is used to invalidate the
12331 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12333 unsigned int regno
= REGNO (reg
);
12334 unsigned int endregno
= END_REGNO (reg
);
12336 reg_stat_type
*rsp
;
12338 /* If VALUE contains REG and we have a previous value for REG, substitute
12339 the previous value. */
12340 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12344 /* Set things up so get_last_value is allowed to see anything set up to
12346 subst_low_luid
= DF_INSN_LUID (insn
);
12347 tem
= get_last_value (reg
);
12349 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12350 it isn't going to be useful and will take a lot of time to process,
12351 so just use the CLOBBER. */
12355 if (ARITHMETIC_P (tem
)
12356 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12357 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12358 tem
= XEXP (tem
, 0);
12359 else if (count_occurrences (value
, reg
, 1) >= 2)
12361 /* If there are two or more occurrences of REG in VALUE,
12362 prevent the value from growing too much. */
12363 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12364 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12367 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12371 /* For each register modified, show we don't know its value, that
12372 we don't know about its bitwise content, that its value has been
12373 updated, and that we don't know the location of the death of the
12375 for (i
= regno
; i
< endregno
; i
++)
12377 rsp
= ®_stat
[i
];
12380 rsp
->last_set
= insn
;
12382 rsp
->last_set_value
= 0;
12383 rsp
->last_set_mode
= VOIDmode
;
12384 rsp
->last_set_nonzero_bits
= 0;
12385 rsp
->last_set_sign_bit_copies
= 0;
12386 rsp
->last_death
= 0;
12387 rsp
->truncated_to_mode
= VOIDmode
;
12390 /* Mark registers that are being referenced in this value. */
12392 update_table_tick (value
);
12394 /* Now update the status of each register being set.
12395 If someone is using this register in this block, set this register
12396 to invalid since we will get confused between the two lives in this
12397 basic block. This makes using this register always invalid. In cse, we
12398 scan the table to invalidate all entries using this register, but this
12399 is too much work for us. */
12401 for (i
= regno
; i
< endregno
; i
++)
12403 rsp
= ®_stat
[i
];
12404 rsp
->last_set_label
= label_tick
;
12406 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12407 rsp
->last_set_invalid
= 1;
12409 rsp
->last_set_invalid
= 0;
12412 /* The value being assigned might refer to X (like in "x++;"). In that
12413 case, we must replace it with (clobber (const_int 0)) to prevent
12415 rsp
= ®_stat
[regno
];
12416 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12418 value
= copy_rtx (value
);
12419 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12423 /* For the main register being modified, update the value, the mode, the
12424 nonzero bits, and the number of sign bit copies. */
12426 rsp
->last_set_value
= value
;
12430 machine_mode mode
= GET_MODE (reg
);
12431 subst_low_luid
= DF_INSN_LUID (insn
);
12432 rsp
->last_set_mode
= mode
;
12433 if (GET_MODE_CLASS (mode
) == MODE_INT
12434 && HWI_COMPUTABLE_MODE_P (mode
))
12435 mode
= nonzero_bits_mode
;
12436 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12437 rsp
->last_set_sign_bit_copies
12438 = num_sign_bit_copies (value
, GET_MODE (reg
));
12442 /* Called via note_stores from record_dead_and_set_regs to handle one
12443 SET or CLOBBER in an insn. DATA is the instruction in which the
12444 set is occurring. */
12447 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12449 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12451 if (GET_CODE (dest
) == SUBREG
)
12452 dest
= SUBREG_REG (dest
);
12454 if (!record_dead_insn
)
12457 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12463 /* If we are setting the whole register, we know its value. Otherwise
12464 show that we don't know the value. We can handle SUBREG in
12466 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12467 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12468 else if (GET_CODE (setter
) == SET
12469 && GET_CODE (SET_DEST (setter
)) == SUBREG
12470 && SUBREG_REG (SET_DEST (setter
)) == dest
12471 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12472 && subreg_lowpart_p (SET_DEST (setter
)))
12473 record_value_for_reg (dest
, record_dead_insn
,
12474 gen_lowpart (GET_MODE (dest
),
12475 SET_SRC (setter
)));
12477 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12479 else if (MEM_P (dest
)
12480 /* Ignore pushes, they clobber nothing. */
12481 && ! push_operand (dest
, GET_MODE (dest
)))
12482 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12485 /* Update the records of when each REG was most recently set or killed
12486 for the things done by INSN. This is the last thing done in processing
12487 INSN in the combiner loop.
12489 We update reg_stat[], in particular fields last_set, last_set_value,
12490 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12491 last_death, and also the similar information mem_last_set (which insn
12492 most recently modified memory) and last_call_luid (which insn was the
12493 most recent subroutine call). */
12496 record_dead_and_set_regs (rtx_insn
*insn
)
12501 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12503 if (REG_NOTE_KIND (link
) == REG_DEAD
12504 && REG_P (XEXP (link
, 0)))
12506 unsigned int regno
= REGNO (XEXP (link
, 0));
12507 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12509 for (i
= regno
; i
< endregno
; i
++)
12511 reg_stat_type
*rsp
;
12513 rsp
= ®_stat
[i
];
12514 rsp
->last_death
= insn
;
12517 else if (REG_NOTE_KIND (link
) == REG_INC
)
12518 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12523 hard_reg_set_iterator hrsi
;
12524 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12526 reg_stat_type
*rsp
;
12528 rsp
= ®_stat
[i
];
12529 rsp
->last_set_invalid
= 1;
12530 rsp
->last_set
= insn
;
12531 rsp
->last_set_value
= 0;
12532 rsp
->last_set_mode
= VOIDmode
;
12533 rsp
->last_set_nonzero_bits
= 0;
12534 rsp
->last_set_sign_bit_copies
= 0;
12535 rsp
->last_death
= 0;
12536 rsp
->truncated_to_mode
= VOIDmode
;
12539 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12541 /* We can't combine into a call pattern. Remember, though, that
12542 the return value register is set at this LUID. We could
12543 still replace a register with the return value from the
12544 wrong subroutine call! */
12545 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12548 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12551 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12552 register present in the SUBREG, so for each such SUBREG go back and
12553 adjust nonzero and sign bit information of the registers that are
12554 known to have some zero/sign bits set.
12556 This is needed because when combine blows the SUBREGs away, the
12557 information on zero/sign bits is lost and further combines can be
12558 missed because of that. */
12561 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12563 struct insn_link
*links
;
12565 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12566 machine_mode mode
= GET_MODE (subreg
);
12568 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12571 for (links
= LOG_LINKS (insn
); links
;)
12573 reg_stat_type
*rsp
;
12575 insn
= links
->insn
;
12576 set
= single_set (insn
);
12578 if (! set
|| !REG_P (SET_DEST (set
))
12579 || REGNO (SET_DEST (set
)) != regno
12580 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12582 links
= links
->next
;
12586 rsp
= ®_stat
[regno
];
12587 if (rsp
->last_set
== insn
)
12589 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12590 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12593 if (REG_P (SET_SRC (set
)))
12595 regno
= REGNO (SET_SRC (set
));
12596 links
= LOG_LINKS (insn
);
12603 /* Check if X, a register, is known to contain a value already
12604 truncated to MODE. In this case we can use a subreg to refer to
12605 the truncated value even though in the generic case we would need
12606 an explicit truncation. */
12609 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
12611 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12612 machine_mode truncated
= rsp
->truncated_to_mode
;
12615 || rsp
->truncation_label
< label_tick_ebb_start
)
12617 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12619 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12624 /* If X is a hard reg or a subreg record the mode that the register is
12625 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12626 to turn a truncate into a subreg using this information. Return true
12627 if traversing X is complete. */
12630 record_truncated_value (rtx x
)
12632 machine_mode truncated_mode
;
12633 reg_stat_type
*rsp
;
12635 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12637 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12638 truncated_mode
= GET_MODE (x
);
12640 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12643 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12646 x
= SUBREG_REG (x
);
12648 /* ??? For hard-regs we now record everything. We might be able to
12649 optimize this using last_set_mode. */
12650 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12651 truncated_mode
= GET_MODE (x
);
12655 rsp
= ®_stat
[REGNO (x
)];
12656 if (rsp
->truncated_to_mode
== 0
12657 || rsp
->truncation_label
< label_tick_ebb_start
12658 || (GET_MODE_SIZE (truncated_mode
)
12659 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12661 rsp
->truncated_to_mode
= truncated_mode
;
12662 rsp
->truncation_label
= label_tick
;
12668 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12669 the modes they are used in. This can help truning TRUNCATEs into
12673 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12675 subrtx_var_iterator::array_type array
;
12676 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
12677 if (record_truncated_value (*iter
))
12678 iter
.skip_subrtxes ();
12681 /* Scan X for promoted SUBREGs. For each one found,
12682 note what it implies to the registers used in it. */
12685 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
12687 if (GET_CODE (x
) == SUBREG
12688 && SUBREG_PROMOTED_VAR_P (x
)
12689 && REG_P (SUBREG_REG (x
)))
12690 record_promoted_value (insn
, x
);
12693 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12696 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12700 check_promoted_subreg (insn
, XEXP (x
, i
));
12704 if (XVEC (x
, i
) != 0)
12705 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12706 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12712 /* Verify that all the registers and memory references mentioned in *LOC are
12713 still valid. *LOC was part of a value set in INSN when label_tick was
12714 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12715 the invalid references with (clobber (const_int 0)) and return 1. This
12716 replacement is useful because we often can get useful information about
12717 the form of a value (e.g., if it was produced by a shift that always
12718 produces -1 or 0) even though we don't know exactly what registers it
12719 was produced from. */
12722 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
12725 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12726 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12731 unsigned int regno
= REGNO (x
);
12732 unsigned int endregno
= END_REGNO (x
);
12735 for (j
= regno
; j
< endregno
; j
++)
12737 reg_stat_type
*rsp
= ®_stat
[j
];
12738 if (rsp
->last_set_invalid
12739 /* If this is a pseudo-register that was only set once and not
12740 live at the beginning of the function, it is always valid. */
12741 || (! (regno
>= FIRST_PSEUDO_REGISTER
12742 && REG_N_SETS (regno
) == 1
12743 && (!REGNO_REG_SET_P
12744 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
12746 && rsp
->last_set_label
> tick
))
12749 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12756 /* If this is a memory reference, make sure that there were no stores after
12757 it that might have clobbered the value. We don't have alias info, so we
12758 assume any store invalidates it. Moreover, we only have local UIDs, so
12759 we also assume that there were stores in the intervening basic blocks. */
12760 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12761 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12764 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12768 for (i
= 0; i
< len
; i
++)
12772 /* Check for identical subexpressions. If x contains
12773 identical subexpression we only have to traverse one of
12775 if (i
== 1 && ARITHMETIC_P (x
))
12777 /* Note that at this point x0 has already been checked
12778 and found valid. */
12779 rtx x0
= XEXP (x
, 0);
12780 rtx x1
= XEXP (x
, 1);
12782 /* If x0 and x1 are identical then x is also valid. */
12786 /* If x1 is identical to a subexpression of x0 then
12787 while checking x0, x1 has already been checked. Thus
12788 it is valid and so as x. */
12789 if (ARITHMETIC_P (x0
)
12790 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12793 /* If x0 is identical to a subexpression of x1 then x is
12794 valid iff the rest of x1 is valid. */
12795 if (ARITHMETIC_P (x1
)
12796 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12798 get_last_value_validate (&XEXP (x1
,
12799 x0
== XEXP (x1
, 0) ? 1 : 0),
12800 insn
, tick
, replace
);
12803 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12807 else if (fmt
[i
] == 'E')
12808 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12809 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12810 insn
, tick
, replace
) == 0)
12814 /* If we haven't found a reason for it to be invalid, it is valid. */
12818 /* Get the last value assigned to X, if known. Some registers
12819 in the value may be replaced with (clobber (const_int 0)) if their value
12820 is known longer known reliably. */
12823 get_last_value (const_rtx x
)
12825 unsigned int regno
;
12827 reg_stat_type
*rsp
;
12829 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12830 then convert it to the desired mode. If this is a paradoxical SUBREG,
12831 we cannot predict what values the "extra" bits might have. */
12832 if (GET_CODE (x
) == SUBREG
12833 && subreg_lowpart_p (x
)
12834 && !paradoxical_subreg_p (x
)
12835 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12836 return gen_lowpart (GET_MODE (x
), value
);
12842 rsp
= ®_stat
[regno
];
12843 value
= rsp
->last_set_value
;
12845 /* If we don't have a value, or if it isn't for this basic block and
12846 it's either a hard register, set more than once, or it's a live
12847 at the beginning of the function, return 0.
12849 Because if it's not live at the beginning of the function then the reg
12850 is always set before being used (is never used without being set).
12851 And, if it's set only once, and it's always set before use, then all
12852 uses must have the same last value, even if it's not from this basic
12856 || (rsp
->last_set_label
< label_tick_ebb_start
12857 && (regno
< FIRST_PSEUDO_REGISTER
12858 || REG_N_SETS (regno
) != 1
12860 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
12863 /* If the value was set in a later insn than the ones we are processing,
12864 we can't use it even if the register was only set once. */
12865 if (rsp
->last_set_label
== label_tick
12866 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12869 /* If the value has all its registers valid, return it. */
12870 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12873 /* Otherwise, make a copy and replace any invalid register with
12874 (clobber (const_int 0)). If that fails for some reason, return 0. */
12876 value
= copy_rtx (value
);
12877 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12883 /* Return nonzero if expression X refers to a REG or to memory
12884 that is set in an instruction more recent than FROM_LUID. */
12887 use_crosses_set_p (const_rtx x
, int from_luid
)
12891 enum rtx_code code
= GET_CODE (x
);
12895 unsigned int regno
= REGNO (x
);
12896 unsigned endreg
= END_REGNO (x
);
12898 #ifdef PUSH_ROUNDING
12899 /* Don't allow uses of the stack pointer to be moved,
12900 because we don't know whether the move crosses a push insn. */
12901 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12904 for (; regno
< endreg
; regno
++)
12906 reg_stat_type
*rsp
= ®_stat
[regno
];
12908 && rsp
->last_set_label
== label_tick
12909 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12915 if (code
== MEM
&& mem_last_set
> from_luid
)
12918 fmt
= GET_RTX_FORMAT (code
);
12920 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12925 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12926 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12929 else if (fmt
[i
] == 'e'
12930 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12936 /* Define three variables used for communication between the following
12939 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12940 static int reg_dead_flag
;
12942 /* Function called via note_stores from reg_dead_at_p.
12944 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12945 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12948 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12950 unsigned int regno
, endregno
;
12955 regno
= REGNO (dest
);
12956 endregno
= END_REGNO (dest
);
12957 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12958 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12961 /* Return nonzero if REG is known to be dead at INSN.
12963 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12964 referencing REG, it is dead. If we hit a SET referencing REG, it is
12965 live. Otherwise, see if it is live or dead at the start of the basic
12966 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12967 must be assumed to be always live. */
12970 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
12975 /* Set variables for reg_dead_at_p_1. */
12976 reg_dead_regno
= REGNO (reg
);
12977 reg_dead_endregno
= END_REGNO (reg
);
12981 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12982 we allow the machine description to decide whether use-and-clobber
12983 patterns are OK. */
12984 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12986 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12987 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12991 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12992 beginning of basic block. */
12993 block
= BLOCK_FOR_INSN (insn
);
12998 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13001 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13003 return reg_dead_flag
== 1 ? 1 : 0;
13005 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13009 if (insn
== BB_HEAD (block
))
13012 insn
= PREV_INSN (insn
);
13015 /* Look at live-in sets for the basic block that we were in. */
13016 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13017 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13023 /* Note hard registers in X that are used. */
13026 mark_used_regs_combine (rtx x
)
13028 RTX_CODE code
= GET_CODE (x
);
13029 unsigned int regno
;
13040 case ADDR_DIFF_VEC
:
13043 /* CC0 must die in the insn after it is set, so we don't need to take
13044 special note of it here. */
13050 /* If we are clobbering a MEM, mark any hard registers inside the
13051 address as used. */
13052 if (MEM_P (XEXP (x
, 0)))
13053 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13058 /* A hard reg in a wide mode may really be multiple registers.
13059 If so, mark all of them just like the first. */
13060 if (regno
< FIRST_PSEUDO_REGISTER
)
13062 /* None of this applies to the stack, frame or arg pointers. */
13063 if (regno
== STACK_POINTER_REGNUM
13064 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13065 || regno
== HARD_FRAME_POINTER_REGNUM
13067 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13068 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13070 || regno
== FRAME_POINTER_REGNUM
)
13073 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13079 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13081 rtx testreg
= SET_DEST (x
);
13083 while (GET_CODE (testreg
) == SUBREG
13084 || GET_CODE (testreg
) == ZERO_EXTRACT
13085 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13086 testreg
= XEXP (testreg
, 0);
13088 if (MEM_P (testreg
))
13089 mark_used_regs_combine (XEXP (testreg
, 0));
13091 mark_used_regs_combine (SET_SRC (x
));
13099 /* Recursively scan the operands of this expression. */
13102 const char *fmt
= GET_RTX_FORMAT (code
);
13104 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13107 mark_used_regs_combine (XEXP (x
, i
));
13108 else if (fmt
[i
] == 'E')
13112 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13113 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13119 /* Remove register number REGNO from the dead registers list of INSN.
13121 Return the note used to record the death, if there was one. */
13124 remove_death (unsigned int regno
, rtx_insn
*insn
)
13126 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13129 remove_note (insn
, note
);
13134 /* For each register (hardware or pseudo) used within expression X, if its
13135 death is in an instruction with luid between FROM_LUID (inclusive) and
13136 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13137 list headed by PNOTES.
13139 That said, don't move registers killed by maybe_kill_insn.
13141 This is done when X is being merged by combination into TO_INSN. These
13142 notes will then be distributed as needed. */
13145 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13150 enum rtx_code code
= GET_CODE (x
);
13154 unsigned int regno
= REGNO (x
);
13155 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13157 /* Don't move the register if it gets killed in between from and to. */
13158 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13159 && ! reg_referenced_p (x
, maybe_kill_insn
))
13163 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13164 && DF_INSN_LUID (where_dead
) >= from_luid
13165 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13167 rtx note
= remove_death (regno
, where_dead
);
13169 /* It is possible for the call above to return 0. This can occur
13170 when last_death points to I2 or I1 that we combined with.
13171 In that case make a new note.
13173 We must also check for the case where X is a hard register
13174 and NOTE is a death note for a range of hard registers
13175 including X. In that case, we must put REG_DEAD notes for
13176 the remaining registers in place of NOTE. */
13178 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13179 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13180 > GET_MODE_SIZE (GET_MODE (x
))))
13182 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13183 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
13184 unsigned int ourend
= END_HARD_REGNO (x
);
13187 for (i
= deadregno
; i
< deadend
; i
++)
13188 if (i
< regno
|| i
>= ourend
)
13189 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13192 /* If we didn't find any note, or if we found a REG_DEAD note that
13193 covers only part of the given reg, and we have a multi-reg hard
13194 register, then to be safe we must check for REG_DEAD notes
13195 for each register other than the first. They could have
13196 their own REG_DEAD notes lying around. */
13197 else if ((note
== 0
13199 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13200 < GET_MODE_SIZE (GET_MODE (x
)))))
13201 && regno
< FIRST_PSEUDO_REGISTER
13202 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13204 unsigned int ourend
= END_HARD_REGNO (x
);
13205 unsigned int i
, offset
;
13209 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13213 for (i
= regno
+ offset
; i
< ourend
; i
++)
13214 move_deaths (regno_reg_rtx
[i
],
13215 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13218 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13220 XEXP (note
, 1) = *pnotes
;
13224 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13230 else if (GET_CODE (x
) == SET
)
13232 rtx dest
= SET_DEST (x
);
13234 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13236 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13237 that accesses one word of a multi-word item, some
13238 piece of everything register in the expression is used by
13239 this insn, so remove any old death. */
13240 /* ??? So why do we test for equality of the sizes? */
13242 if (GET_CODE (dest
) == ZERO_EXTRACT
13243 || GET_CODE (dest
) == STRICT_LOW_PART
13244 || (GET_CODE (dest
) == SUBREG
13245 && (((GET_MODE_SIZE (GET_MODE (dest
))
13246 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13247 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13248 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13250 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13254 /* If this is some other SUBREG, we know it replaces the entire
13255 value, so use that as the destination. */
13256 if (GET_CODE (dest
) == SUBREG
)
13257 dest
= SUBREG_REG (dest
);
13259 /* If this is a MEM, adjust deaths of anything used in the address.
13260 For a REG (the only other possibility), the entire value is
13261 being replaced so the old value is not used in this insn. */
13264 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13269 else if (GET_CODE (x
) == CLOBBER
)
13272 len
= GET_RTX_LENGTH (code
);
13273 fmt
= GET_RTX_FORMAT (code
);
13275 for (i
= 0; i
< len
; i
++)
13280 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13281 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13284 else if (fmt
[i
] == 'e')
13285 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13289 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13290 pattern of an insn. X must be a REG. */
13293 reg_bitfield_target_p (rtx x
, rtx body
)
13297 if (GET_CODE (body
) == SET
)
13299 rtx dest
= SET_DEST (body
);
13301 unsigned int regno
, tregno
, endregno
, endtregno
;
13303 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13304 target
= XEXP (dest
, 0);
13305 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13306 target
= SUBREG_REG (XEXP (dest
, 0));
13310 if (GET_CODE (target
) == SUBREG
)
13311 target
= SUBREG_REG (target
);
13313 if (!REG_P (target
))
13316 tregno
= REGNO (target
), regno
= REGNO (x
);
13317 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13318 return target
== x
;
13320 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13321 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13323 return endregno
> tregno
&& regno
< endtregno
;
13326 else if (GET_CODE (body
) == PARALLEL
)
13327 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13328 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13334 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13335 as appropriate. I3 and I2 are the insns resulting from the combination
13336 insns including FROM (I2 may be zero).
13338 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13339 not need REG_DEAD notes because they are being substituted for. This
13340 saves searching in the most common cases.
13342 Each note in the list is either ignored or placed on some insns, depending
13343 on the type of note. */
13346 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13347 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13349 rtx note
, next_note
;
13351 rtx_insn
*tem_insn
;
13353 for (note
= notes
; note
; note
= next_note
)
13355 rtx_insn
*place
= 0, *place2
= 0;
13357 next_note
= XEXP (note
, 1);
13358 switch (REG_NOTE_KIND (note
))
13362 /* Doesn't matter much where we put this, as long as it's somewhere.
13363 It is preferable to keep these notes on branches, which is most
13364 likely to be i3. */
13368 case REG_NON_LOCAL_GOTO
:
13373 gcc_assert (i2
&& JUMP_P (i2
));
13378 case REG_EH_REGION
:
13379 /* These notes must remain with the call or trapping instruction. */
13382 else if (i2
&& CALL_P (i2
))
13386 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13387 if (may_trap_p (i3
))
13389 else if (i2
&& may_trap_p (i2
))
13391 /* ??? Otherwise assume we've combined things such that we
13392 can now prove that the instructions can't trap. Drop the
13393 note in this case. */
13397 case REG_ARGS_SIZE
:
13398 /* ??? How to distribute between i3-i1. Assume i3 contains the
13399 entire adjustment. Assert i3 contains at least some adjust. */
13400 if (!noop_move_p (i3
))
13402 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13403 /* fixup_args_size_notes looks at REG_NORETURN note,
13404 so ensure the note is placed there first. */
13408 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13409 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13413 XEXP (n
, 1) = REG_NOTES (i3
);
13414 REG_NOTES (i3
) = n
;
13418 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13419 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13420 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13421 gcc_assert (old_size
!= args_size
13423 && !ACCUMULATE_OUTGOING_ARGS
13424 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13431 case REG_CALL_DECL
:
13432 /* These notes must remain with the call. It should not be
13433 possible for both I2 and I3 to be a call. */
13438 gcc_assert (i2
&& CALL_P (i2
));
13444 /* Any clobbers for i3 may still exist, and so we must process
13445 REG_UNUSED notes from that insn.
13447 Any clobbers from i2 or i1 can only exist if they were added by
13448 recog_for_combine. In that case, recog_for_combine created the
13449 necessary REG_UNUSED notes. Trying to keep any original
13450 REG_UNUSED notes from these insns can cause incorrect output
13451 if it is for the same register as the original i3 dest.
13452 In that case, we will notice that the register is set in i3,
13453 and then add a REG_UNUSED note for the destination of i3, which
13454 is wrong. However, it is possible to have REG_UNUSED notes from
13455 i2 or i1 for register which were both used and clobbered, so
13456 we keep notes from i2 or i1 if they will turn into REG_DEAD
13459 /* If this register is set or clobbered in I3, put the note there
13460 unless there is one already. */
13461 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13463 if (from_insn
!= i3
)
13466 if (! (REG_P (XEXP (note
, 0))
13467 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13468 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13471 /* Otherwise, if this register is used by I3, then this register
13472 now dies here, so we must put a REG_DEAD note here unless there
13474 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13475 && ! (REG_P (XEXP (note
, 0))
13476 ? find_regno_note (i3
, REG_DEAD
,
13477 REGNO (XEXP (note
, 0)))
13478 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13480 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13488 /* These notes say something about results of an insn. We can
13489 only support them if they used to be on I3 in which case they
13490 remain on I3. Otherwise they are ignored.
13492 If the note refers to an expression that is not a constant, we
13493 must also ignore the note since we cannot tell whether the
13494 equivalence is still true. It might be possible to do
13495 slightly better than this (we only have a problem if I2DEST
13496 or I1DEST is present in the expression), but it doesn't
13497 seem worth the trouble. */
13499 if (from_insn
== i3
13500 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13505 /* These notes say something about how a register is used. They must
13506 be present on any use of the register in I2 or I3. */
13507 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13510 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13519 case REG_LABEL_TARGET
:
13520 case REG_LABEL_OPERAND
:
13521 /* This can show up in several ways -- either directly in the
13522 pattern, or hidden off in the constant pool with (or without?)
13523 a REG_EQUAL note. */
13524 /* ??? Ignore the without-reg_equal-note problem for now. */
13525 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13526 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13527 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13528 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
13532 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13533 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13534 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13535 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
13543 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13544 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13546 if (place
&& JUMP_P (place
)
13547 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13548 && (JUMP_LABEL (place
) == NULL
13549 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13551 rtx label
= JUMP_LABEL (place
);
13554 JUMP_LABEL (place
) = XEXP (note
, 0);
13555 else if (LABEL_P (label
))
13556 LABEL_NUSES (label
)--;
13559 if (place2
&& JUMP_P (place2
)
13560 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13561 && (JUMP_LABEL (place2
) == NULL
13562 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13564 rtx label
= JUMP_LABEL (place2
);
13567 JUMP_LABEL (place2
) = XEXP (note
, 0);
13568 else if (LABEL_P (label
))
13569 LABEL_NUSES (label
)--;
13575 /* This note says something about the value of a register prior
13576 to the execution of an insn. It is too much trouble to see
13577 if the note is still correct in all situations. It is better
13578 to simply delete it. */
13582 /* If we replaced the right hand side of FROM_INSN with a
13583 REG_EQUAL note, the original use of the dying register
13584 will not have been combined into I3 and I2. In such cases,
13585 FROM_INSN is guaranteed to be the first of the combined
13586 instructions, so we simply need to search back before
13587 FROM_INSN for the previous use or set of this register,
13588 then alter the notes there appropriately.
13590 If the register is used as an input in I3, it dies there.
13591 Similarly for I2, if it is nonzero and adjacent to I3.
13593 If the register is not used as an input in either I3 or I2
13594 and it is not one of the registers we were supposed to eliminate,
13595 there are two possibilities. We might have a non-adjacent I2
13596 or we might have somehow eliminated an additional register
13597 from a computation. For example, we might have had A & B where
13598 we discover that B will always be zero. In this case we will
13599 eliminate the reference to A.
13601 In both cases, we must search to see if we can find a previous
13602 use of A and put the death note there. */
13605 && from_insn
== i2mod
13606 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13607 tem_insn
= from_insn
;
13611 && CALL_P (from_insn
)
13612 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13614 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13616 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13617 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13619 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13621 && reg_overlap_mentioned_p (XEXP (note
, 0),
13623 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13624 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13631 basic_block bb
= this_basic_block
;
13633 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13635 if (!NONDEBUG_INSN_P (tem_insn
))
13637 if (tem_insn
== BB_HEAD (bb
))
13642 /* If the register is being set at TEM_INSN, see if that is all
13643 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13644 into a REG_UNUSED note instead. Don't delete sets to
13645 global register vars. */
13646 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13647 || !global_regs
[REGNO (XEXP (note
, 0))])
13648 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
13650 rtx set
= single_set (tem_insn
);
13651 rtx inner_dest
= 0;
13653 rtx_insn
*cc0_setter
= NULL
;
13657 for (inner_dest
= SET_DEST (set
);
13658 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13659 || GET_CODE (inner_dest
) == SUBREG
13660 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13661 inner_dest
= XEXP (inner_dest
, 0))
13664 /* Verify that it was the set, and not a clobber that
13665 modified the register.
13667 CC0 targets must be careful to maintain setter/user
13668 pairs. If we cannot delete the setter due to side
13669 effects, mark the user with an UNUSED note instead
13672 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13673 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13675 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13676 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
13677 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13681 /* Move the notes and links of TEM_INSN elsewhere.
13682 This might delete other dead insns recursively.
13683 First set the pattern to something that won't use
13685 rtx old_notes
= REG_NOTES (tem_insn
);
13687 PATTERN (tem_insn
) = pc_rtx
;
13688 REG_NOTES (tem_insn
) = NULL
;
13690 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
13691 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13692 distribute_links (LOG_LINKS (tem_insn
));
13694 SET_INSN_DELETED (tem_insn
);
13695 if (tem_insn
== i2
)
13699 /* Delete the setter too. */
13702 PATTERN (cc0_setter
) = pc_rtx
;
13703 old_notes
= REG_NOTES (cc0_setter
);
13704 REG_NOTES (cc0_setter
) = NULL
;
13706 distribute_notes (old_notes
, cc0_setter
,
13708 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13709 distribute_links (LOG_LINKS (cc0_setter
));
13711 SET_INSN_DELETED (cc0_setter
);
13712 if (cc0_setter
== i2
)
13719 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13721 /* If there isn't already a REG_UNUSED note, put one
13722 here. Do not place a REG_DEAD note, even if
13723 the register is also used here; that would not
13724 match the algorithm used in lifetime analysis
13725 and can cause the consistency check in the
13726 scheduler to fail. */
13727 if (! find_regno_note (tem_insn
, REG_UNUSED
,
13728 REGNO (XEXP (note
, 0))))
13733 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
13734 || (CALL_P (tem_insn
)
13735 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
13739 /* If we are doing a 3->2 combination, and we have a
13740 register which formerly died in i3 and was not used
13741 by i2, which now no longer dies in i3 and is used in
13742 i2 but does not die in i2, and place is between i2
13743 and i3, then we may need to move a link from place to
13745 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13747 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13748 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13750 struct insn_link
*links
= LOG_LINKS (place
);
13751 LOG_LINKS (place
) = NULL
;
13752 distribute_links (links
);
13757 if (tem_insn
== BB_HEAD (bb
))
13763 /* If the register is set or already dead at PLACE, we needn't do
13764 anything with this note if it is still a REG_DEAD note.
13765 We check here if it is set at all, not if is it totally replaced,
13766 which is what `dead_or_set_p' checks, so also check for it being
13769 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13771 unsigned int regno
= REGNO (XEXP (note
, 0));
13772 reg_stat_type
*rsp
= ®_stat
[regno
];
13774 if (dead_or_set_p (place
, XEXP (note
, 0))
13775 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13777 /* Unless the register previously died in PLACE, clear
13778 last_death. [I no longer understand why this is
13780 if (rsp
->last_death
!= place
)
13781 rsp
->last_death
= 0;
13785 rsp
->last_death
= place
;
13787 /* If this is a death note for a hard reg that is occupying
13788 multiple registers, ensure that we are still using all
13789 parts of the object. If we find a piece of the object
13790 that is unused, we must arrange for an appropriate REG_DEAD
13791 note to be added for it. However, we can't just emit a USE
13792 and tag the note to it, since the register might actually
13793 be dead; so we recourse, and the recursive call then finds
13794 the previous insn that used this register. */
13796 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13797 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13799 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13800 bool all_used
= true;
13803 for (i
= regno
; i
< endregno
; i
++)
13804 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13805 && ! find_regno_fusage (place
, USE
, i
))
13806 || dead_or_set_regno_p (place
, i
))
13814 /* Put only REG_DEAD notes for pieces that are
13815 not already dead or set. */
13817 for (i
= regno
; i
< endregno
;
13818 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13820 rtx piece
= regno_reg_rtx
[i
];
13821 basic_block bb
= this_basic_block
;
13823 if (! dead_or_set_p (place
, piece
)
13824 && ! reg_bitfield_target_p (piece
,
13827 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13830 distribute_notes (new_note
, place
, place
,
13831 NULL
, NULL_RTX
, NULL_RTX
,
13834 else if (! refers_to_regno_p (i
, i
+ 1,
13835 PATTERN (place
), 0)
13836 && ! find_regno_fusage (place
, USE
, i
))
13837 for (tem_insn
= PREV_INSN (place
); ;
13838 tem_insn
= PREV_INSN (tem_insn
))
13840 if (!NONDEBUG_INSN_P (tem_insn
))
13842 if (tem_insn
== BB_HEAD (bb
))
13846 if (dead_or_set_p (tem_insn
, piece
)
13847 || reg_bitfield_target_p (piece
,
13848 PATTERN (tem_insn
)))
13850 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
13863 /* Any other notes should not be present at this point in the
13865 gcc_unreachable ();
13870 XEXP (note
, 1) = REG_NOTES (place
);
13871 REG_NOTES (place
) = note
;
13875 add_shallow_copy_of_reg_note (place2
, note
);
13879 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13880 I3, I2, and I1 to new locations. This is also called to add a link
13881 pointing at I3 when I3's destination is changed. */
13884 distribute_links (struct insn_link
*links
)
13886 struct insn_link
*link
, *next_link
;
13888 for (link
= links
; link
; link
= next_link
)
13890 rtx_insn
*place
= 0;
13894 next_link
= link
->next
;
13896 /* If the insn that this link points to is a NOTE, ignore it. */
13897 if (NOTE_P (link
->insn
))
13901 rtx pat
= PATTERN (link
->insn
);
13902 if (GET_CODE (pat
) == SET
)
13904 else if (GET_CODE (pat
) == PARALLEL
)
13907 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
13909 set
= XVECEXP (pat
, 0, i
);
13910 if (GET_CODE (set
) != SET
)
13913 reg
= SET_DEST (set
);
13914 while (GET_CODE (reg
) == ZERO_EXTRACT
13915 || GET_CODE (reg
) == STRICT_LOW_PART
13916 || GET_CODE (reg
) == SUBREG
)
13917 reg
= XEXP (reg
, 0);
13922 if (REGNO (reg
) == link
->regno
)
13925 if (i
== XVECLEN (pat
, 0))
13931 reg
= SET_DEST (set
);
13933 while (GET_CODE (reg
) == ZERO_EXTRACT
13934 || GET_CODE (reg
) == STRICT_LOW_PART
13935 || GET_CODE (reg
) == SUBREG
)
13936 reg
= XEXP (reg
, 0);
13938 /* A LOG_LINK is defined as being placed on the first insn that uses
13939 a register and points to the insn that sets the register. Start
13940 searching at the next insn after the target of the link and stop
13941 when we reach a set of the register or the end of the basic block.
13943 Note that this correctly handles the link that used to point from
13944 I3 to I2. Also note that not much searching is typically done here
13945 since most links don't point very far away. */
13947 for (insn
= NEXT_INSN (link
->insn
);
13948 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
13949 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13950 insn
= NEXT_INSN (insn
))
13951 if (DEBUG_INSN_P (insn
))
13953 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13955 if (reg_referenced_p (reg
, PATTERN (insn
)))
13959 else if (CALL_P (insn
)
13960 && find_reg_fusage (insn
, USE
, reg
))
13965 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13968 /* If we found a place to put the link, place it there unless there
13969 is already a link to the same insn as LINK at that point. */
13973 struct insn_link
*link2
;
13975 FOR_EACH_LOG_LINK (link2
, place
)
13976 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
13981 link
->next
= LOG_LINKS (place
);
13982 LOG_LINKS (place
) = link
;
13984 /* Set added_links_insn to the earliest insn we added a
13986 if (added_links_insn
== 0
13987 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13988 added_links_insn
= place
;
13994 /* Check for any register or memory mentioned in EQUIV that is not
13995 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13996 of EXPR where some registers may have been replaced by constants. */
13999 unmentioned_reg_p (rtx equiv
, rtx expr
)
14001 subrtx_iterator::array_type array
;
14002 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14004 const_rtx x
= *iter
;
14005 if ((REG_P (x
) || MEM_P (x
))
14006 && !reg_mentioned_p (x
, expr
))
14012 DEBUG_FUNCTION
void
14013 dump_combine_stats (FILE *file
)
14017 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14018 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14022 dump_combine_total_stats (FILE *file
)
14026 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14027 total_attempts
, total_merges
, total_extras
, total_successes
);
14030 /* Try combining insns through substitution. */
14031 static unsigned int
14032 rest_of_handle_combine (void)
14034 int rebuild_jump_labels_after_combine
;
14036 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14037 df_note_add_problem ();
14040 regstat_init_n_sets_and_refs ();
14042 rebuild_jump_labels_after_combine
14043 = combine_instructions (get_insns (), max_reg_num ());
14045 /* Combining insns may have turned an indirect jump into a
14046 direct jump. Rebuild the JUMP_LABEL fields of jumping
14048 if (rebuild_jump_labels_after_combine
)
14050 timevar_push (TV_JUMP
);
14051 rebuild_jump_labels (get_insns ());
14053 timevar_pop (TV_JUMP
);
14056 regstat_free_n_sets_and_refs ();
14062 const pass_data pass_data_combine
=
14064 RTL_PASS
, /* type */
14065 "combine", /* name */
14066 OPTGROUP_NONE
, /* optinfo_flags */
14067 TV_COMBINE
, /* tv_id */
14068 PROP_cfglayout
, /* properties_required */
14069 0, /* properties_provided */
14070 0, /* properties_destroyed */
14071 0, /* todo_flags_start */
14072 TODO_df_finish
, /* todo_flags_finish */
14075 class pass_combine
: public rtl_opt_pass
14078 pass_combine (gcc::context
*ctxt
)
14079 : rtl_opt_pass (pass_data_combine
, ctxt
)
14082 /* opt_pass methods: */
14083 virtual bool gate (function
*) { return (optimize
> 0); }
14084 virtual unsigned int execute (function
*)
14086 return rest_of_handle_combine ();
14089 }; // class pass_combine
14091 } // anon namespace
14094 make_pass_combine (gcc::context
*ctxt
)
14096 return new pass_combine (ctxt
);