1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 typedef struct reg_stat_struct
{
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
254 DEF_VEC_O(reg_stat_type
);
255 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
257 static VEC(reg_stat_type
,heap
) *reg_stat
;
259 /* Record the luid of the last insn that invalidated memory
260 (anything that writes memory, and subroutine calls, but not pushes). */
262 static int mem_last_set
;
264 /* Record the luid of the last CALL_INSN
265 so we can tell whether a potential combination crosses any calls. */
267 static int last_call_luid
;
269 /* When `subst' is called, this is the insn that is being modified
270 (by combining in a previous insn). The PATTERN of this insn
271 is still the old pattern partially modified and it should not be
272 looked at, but this may be used to examine the successors of the insn
273 to judge whether a simplification is valid. */
275 static rtx subst_insn
;
277 /* This is the lowest LUID that `subst' is currently dealing with.
278 get_last_value will not return a value if the register was set at or
279 after this LUID. If not for this mechanism, we could get confused if
280 I2 or I1 in try_combine were an insn that used the old value of a register
281 to obtain a new value. In that case, we might erroneously get the
282 new value of the register when we wanted the old one. */
284 static int subst_low_luid
;
286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
287 must consider all these registers to be always live. */
289 static HARD_REG_SET newpat_used_regs
;
291 /* This is an insn to which a LOG_LINKS entry has been added. If this
292 insn is the earlier than I2 or I3, combine should rescan starting at
295 static rtx added_links_insn
;
297 /* Basic block in which we are performing combines. */
298 static basic_block this_basic_block
;
299 static bool optimize_this_for_speed_p
;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known
;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost
;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx
*uid_log_links
;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick
;
323 /* Reset to label_tick for each extended basic block in scanning order. */
325 static int label_tick_ebb_start
;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode
;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid
;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
344 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
};
350 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
351 union { rtx
*r
; int *i
; } where
;
354 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
355 num_undo says how many are currently recorded.
357 other_insn is nonzero if we have modified some other insn in the process
358 of working on subst_insn. It must be verified too. */
367 static struct undobuf undobuf
;
369 /* Number of times the pseudo being substituted for
370 was found and replaced. */
372 static int n_occurrences
;
374 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
376 unsigned HOST_WIDE_INT
,
377 unsigned HOST_WIDE_INT
*);
378 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
380 unsigned int, unsigned int *);
381 static void do_SUBST (rtx
*, rtx
);
382 static void do_SUBST_INT (int *, int);
383 static void init_reg_last (void);
384 static void setup_incoming_promotions (rtx
);
385 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
386 static int cant_combine_insn_p (rtx
);
387 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
388 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
389 static int contains_muldiv (rtx
);
390 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *);
391 static void undo_all (void);
392 static void undo_commit (void);
393 static rtx
*find_split_point (rtx
*, rtx
, bool);
394 static rtx
subst (rtx
, rtx
, rtx
, int, int);
395 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
396 static rtx
simplify_if_then_else (rtx
);
397 static rtx
simplify_set (rtx
);
398 static rtx
simplify_logical (rtx
);
399 static rtx
expand_compound_operation (rtx
);
400 static const_rtx
expand_field_assignment (const_rtx
);
401 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
402 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
403 static rtx
extract_left_shift (rtx
, int);
404 static rtx
make_compound_operation (rtx
, enum rtx_code
);
405 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
406 unsigned HOST_WIDE_INT
*);
407 static rtx
canon_reg_for_combine (rtx
, rtx
);
408 static rtx
force_to_mode (rtx
, enum machine_mode
,
409 unsigned HOST_WIDE_INT
, int);
410 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
411 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
412 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
413 static rtx
make_field_assignment (rtx
);
414 static rtx
apply_distributive_law (rtx
);
415 static rtx
distribute_and_simplify_rtx (rtx
, int);
416 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
417 unsigned HOST_WIDE_INT
);
418 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
419 unsigned HOST_WIDE_INT
);
420 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
421 HOST_WIDE_INT
, enum machine_mode
, int *);
422 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
423 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
425 static int recog_for_combine (rtx
*, rtx
, rtx
*);
426 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
427 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
428 static void update_table_tick (rtx
);
429 static void record_value_for_reg (rtx
, rtx
, rtx
);
430 static void check_promoted_subreg (rtx
, rtx
);
431 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
432 static void record_dead_and_set_regs (rtx
);
433 static int get_last_value_validate (rtx
*, rtx
, int, int);
434 static rtx
get_last_value (const_rtx
);
435 static int use_crosses_set_p (const_rtx
, int);
436 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
437 static int reg_dead_at_p (rtx
, rtx
);
438 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
439 static int reg_bitfield_target_p (rtx
, rtx
);
440 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
441 static void distribute_links (rtx
);
442 static void mark_used_regs_combine (rtx
);
443 static void record_promoted_value (rtx
, rtx
);
444 static int unmentioned_reg_p_1 (rtx
*, void *);
445 static bool unmentioned_reg_p (rtx
, rtx
);
446 static int record_truncated_value (rtx
*, void *);
447 static void record_truncated_values (rtx
*, void *);
448 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
449 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
452 /* It is not safe to use ordinary gen_lowpart in combine.
453 See comments in gen_lowpart_for_combine. */
454 #undef RTL_HOOKS_GEN_LOWPART
455 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
457 /* Our implementation of gen_lowpart never emits a new pseudo. */
458 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
459 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
461 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
462 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
464 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
465 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
467 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
468 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
470 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
473 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
474 PATTERN can not be split. Otherwise, it returns an insn sequence.
475 This is a wrapper around split_insns which ensures that the
476 reg_stat vector is made larger if the splitter creates a new
480 combine_split_insns (rtx pattern
, rtx insn
)
485 ret
= split_insns (pattern
, insn
);
486 nregs
= max_reg_num ();
487 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
488 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
492 /* This is used by find_single_use to locate an rtx in LOC that
493 contains exactly one use of DEST, which is typically either a REG
494 or CC0. It returns a pointer to the innermost rtx expression
495 containing DEST. Appearances of DEST that are being used to
496 totally replace it are not counted. */
499 find_single_use_1 (rtx dest
, rtx
*loc
)
502 enum rtx_code code
= GET_CODE (x
);
520 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
521 of a REG that occupies all of the REG, the insn uses DEST if
522 it is mentioned in the destination or the source. Otherwise, we
523 need just check the source. */
524 if (GET_CODE (SET_DEST (x
)) != CC0
525 && GET_CODE (SET_DEST (x
)) != PC
526 && !REG_P (SET_DEST (x
))
527 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
528 && REG_P (SUBREG_REG (SET_DEST (x
)))
529 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
530 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
531 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
532 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
535 return find_single_use_1 (dest
, &SET_SRC (x
));
539 return find_single_use_1 (dest
, &XEXP (x
, 0));
545 /* If it wasn't one of the common cases above, check each expression and
546 vector of this code. Look for a unique usage of DEST. */
548 fmt
= GET_RTX_FORMAT (code
);
549 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
553 if (dest
== XEXP (x
, i
)
554 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
555 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
558 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
561 result
= this_result
;
562 else if (this_result
)
563 /* Duplicate usage. */
566 else if (fmt
[i
] == 'E')
570 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
572 if (XVECEXP (x
, i
, j
) == dest
574 && REG_P (XVECEXP (x
, i
, j
))
575 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
578 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
581 result
= this_result
;
582 else if (this_result
)
592 /* See if DEST, produced in INSN, is used only a single time in the
593 sequel. If so, return a pointer to the innermost rtx expression in which
596 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
598 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
599 care about REG_DEAD notes or LOG_LINKS.
601 Otherwise, we find the single use by finding an insn that has a
602 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
603 only referenced once in that insn, we know that it must be the first
604 and last insn referencing DEST. */
607 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
617 next
= NEXT_INSN (insn
);
619 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
622 result
= find_single_use_1 (dest
, &PATTERN (next
));
632 bb
= BLOCK_FOR_INSN (insn
);
633 for (next
= NEXT_INSN (insn
);
634 next
&& BLOCK_FOR_INSN (next
) == bb
;
635 next
= NEXT_INSN (next
))
636 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
638 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
639 if (XEXP (link
, 0) == insn
)
644 result
= find_single_use_1 (dest
, &PATTERN (next
));
654 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
655 insn. The substitution can be undone by undo_all. If INTO is already
656 set to NEWVAL, do not record this change. Because computing NEWVAL might
657 also call SUBST, we have to compute it before we put anything into
661 do_SUBST (rtx
*into
, rtx newval
)
666 if (oldval
== newval
)
669 /* We'd like to catch as many invalid transformations here as
670 possible. Unfortunately, there are way too many mode changes
671 that are perfectly valid, so we'd waste too much effort for
672 little gain doing the checks here. Focus on catching invalid
673 transformations involving integer constants. */
674 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
675 && CONST_INT_P (newval
))
677 /* Sanity check that we're replacing oldval with a CONST_INT
678 that is a valid sign-extension for the original mode. */
679 gcc_assert (INTVAL (newval
)
680 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
682 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
683 CONST_INT is not valid, because after the replacement, the
684 original mode would be gone. Unfortunately, we can't tell
685 when do_SUBST is called to replace the operand thereof, so we
686 perform this test on oldval instead, checking whether an
687 invalid replacement took place before we got here. */
688 gcc_assert (!(GET_CODE (oldval
) == SUBREG
689 && CONST_INT_P (SUBREG_REG (oldval
))));
690 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
691 && CONST_INT_P (XEXP (oldval
, 0))));
695 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
697 buf
= XNEW (struct undo
);
699 buf
->kind
= UNDO_RTX
;
701 buf
->old_contents
.r
= oldval
;
704 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
707 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
709 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
710 for the value of a HOST_WIDE_INT value (including CONST_INT) is
714 do_SUBST_INT (int *into
, int newval
)
719 if (oldval
== newval
)
723 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
725 buf
= XNEW (struct undo
);
727 buf
->kind
= UNDO_INT
;
729 buf
->old_contents
.i
= oldval
;
732 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
735 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
737 /* Similar to SUBST, but just substitute the mode. This is used when
738 changing the mode of a pseudo-register, so that any other
739 references to the entry in the regno_reg_rtx array will change as
743 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
746 enum machine_mode oldval
= GET_MODE (*into
);
748 if (oldval
== newval
)
752 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
754 buf
= XNEW (struct undo
);
756 buf
->kind
= UNDO_MODE
;
758 buf
->old_contents
.m
= oldval
;
759 adjust_reg_mode (*into
, newval
);
761 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
764 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
766 /* Subroutine of try_combine. Determine whether the combine replacement
767 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
768 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
769 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
770 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
771 function returns false, if the costs of all instructions can be
772 estimated, and the replacements are more expensive than the original
776 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
777 rtx newi2pat
, rtx newotherpat
)
779 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
780 int new_i2_cost
, new_i3_cost
;
781 int old_cost
, new_cost
;
783 /* Lookup the original insn_rtx_costs. */
784 i2_cost
= INSN_COST (i2
);
785 i3_cost
= INSN_COST (i3
);
789 i1_cost
= INSN_COST (i1
);
792 i0_cost
= INSN_COST (i0
);
793 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
794 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
798 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
799 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
805 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
806 i1_cost
= i0_cost
= 0;
809 /* Calculate the replacement insn_rtx_costs. */
810 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
813 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
814 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
815 ? new_i2_cost
+ new_i3_cost
: 0;
819 new_cost
= new_i3_cost
;
823 if (undobuf
.other_insn
)
825 int old_other_cost
, new_other_cost
;
827 old_other_cost
= INSN_COST (undobuf
.other_insn
);
828 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
829 if (old_other_cost
> 0 && new_other_cost
> 0)
831 old_cost
+= old_other_cost
;
832 new_cost
+= new_other_cost
;
838 /* Disallow this recombination if both new_cost and old_cost are
839 greater than zero, and new_cost is greater than old cost. */
841 && new_cost
> old_cost
)
848 "rejecting combination of insns %d, %d, %d and %d\n",
849 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
851 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
852 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
857 "rejecting combination of insns %d, %d and %d\n",
858 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
859 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
860 i1_cost
, i2_cost
, i3_cost
, old_cost
);
865 "rejecting combination of insns %d and %d\n",
866 INSN_UID (i2
), INSN_UID (i3
));
867 fprintf (dump_file
, "original costs %d + %d = %d\n",
868 i2_cost
, i3_cost
, old_cost
);
873 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
874 new_i2_cost
, new_i3_cost
, new_cost
);
877 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
883 /* Update the uid_insn_cost array with the replacement costs. */
884 INSN_COST (i2
) = new_i2_cost
;
885 INSN_COST (i3
) = new_i3_cost
;
893 /* Delete any insns that copy a register to itself. */
896 delete_noop_moves (void)
903 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
905 next
= NEXT_INSN (insn
);
906 if (INSN_P (insn
) && noop_move_p (insn
))
909 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
911 delete_insn_and_edges (insn
);
918 /* Fill in log links field for all insns. */
921 create_log_links (void)
925 df_ref
*def_vec
, *use_vec
;
927 next_use
= XCNEWVEC (rtx
, max_reg_num ());
929 /* Pass through each block from the end, recording the uses of each
930 register and establishing log links when def is encountered.
931 Note that we do not clear next_use array in order to save time,
932 so we have to test whether the use is in the same basic block as def.
934 There are a few cases below when we do not consider the definition or
935 usage -- these are taken from original flow.c did. Don't ask me why it is
936 done this way; I don't know and if it works, I don't want to know. */
940 FOR_BB_INSNS_REVERSE (bb
, insn
)
942 if (!NONDEBUG_INSN_P (insn
))
945 /* Log links are created only once. */
946 gcc_assert (!LOG_LINKS (insn
));
948 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
950 df_ref def
= *def_vec
;
951 int regno
= DF_REF_REGNO (def
);
954 if (!next_use
[regno
])
957 /* Do not consider if it is pre/post modification in MEM. */
958 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
961 /* Do not make the log link for frame pointer. */
962 if ((regno
== FRAME_POINTER_REGNUM
963 && (! reload_completed
|| frame_pointer_needed
))
964 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
965 || (regno
== HARD_FRAME_POINTER_REGNUM
966 && (! reload_completed
|| frame_pointer_needed
))
968 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
969 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
974 use_insn
= next_use
[regno
];
975 if (BLOCK_FOR_INSN (use_insn
) == bb
)
979 We don't build a LOG_LINK for hard registers contained
980 in ASM_OPERANDs. If these registers get replaced,
981 we might wind up changing the semantics of the insn,
982 even if reload can make what appear to be valid
983 assignments later. */
984 if (regno
>= FIRST_PSEUDO_REGISTER
985 || asm_noperands (PATTERN (use_insn
)) < 0)
987 /* Don't add duplicate links between instructions. */
989 for (links
= LOG_LINKS (use_insn
); links
;
990 links
= XEXP (links
, 1))
991 if (insn
== XEXP (links
, 0))
995 LOG_LINKS (use_insn
) =
996 alloc_INSN_LIST (insn
, LOG_LINKS (use_insn
));
999 next_use
[regno
] = NULL_RTX
;
1002 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1004 df_ref use
= *use_vec
;
1005 int regno
= DF_REF_REGNO (use
);
1007 /* Do not consider the usage of the stack pointer
1008 by function call. */
1009 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1012 next_use
[regno
] = insn
;
1020 /* Clear LOG_LINKS fields of insns. */
1023 clear_log_links (void)
1027 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1029 free_INSN_LIST_list (&LOG_LINKS (insn
));
1032 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1033 true if we found a LOG_LINK that proves that A feeds B. This only works
1034 if there are no instructions between A and B which could have a link
1035 depending on A, since in that case we would not record a link for B.
1036 We also check the implicit dependency created by a cc0 setter/user
1040 insn_a_feeds_b (rtx a
, rtx b
)
1043 for (links
= LOG_LINKS (b
); links
; links
= XEXP (links
, 1))
1044 if (XEXP (links
, 0) == a
)
1053 /* Main entry point for combiner. F is the first insn of the function.
1054 NREGS is the first unused pseudo-reg number.
1056 Return nonzero if the combiner has turned an indirect jump
1057 instruction into a direct jump. */
1059 combine_instructions (rtx f
, unsigned int nregs
)
1065 rtx links
, nextlinks
;
1067 basic_block last_bb
;
1069 int new_direct_jump_p
= 0;
1071 for (first
= f
; first
&& !INSN_P (first
); )
1072 first
= NEXT_INSN (first
);
1076 combine_attempts
= 0;
1079 combine_successes
= 0;
1081 rtl_hooks
= combine_rtl_hooks
;
1083 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1085 init_recog_no_volatile ();
1087 /* Allocate array for insn info. */
1088 max_uid_known
= get_max_uid ();
1089 uid_log_links
= XCNEWVEC (rtx
, max_uid_known
+ 1);
1090 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1092 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1094 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1095 problems when, for example, we have j <<= 1 in a loop. */
1097 nonzero_sign_valid
= 0;
1098 label_tick
= label_tick_ebb_start
= 1;
1100 /* Scan all SETs and see if we can deduce anything about what
1101 bits are known to be zero for some registers and how many copies
1102 of the sign bit are known to exist for those registers.
1104 Also set any known values so that we can use it while searching
1105 for what bits are known to be set. */
1107 setup_incoming_promotions (first
);
1108 /* Allow the entry block and the first block to fall into the same EBB.
1109 Conceptually the incoming promotions are assigned to the entry block. */
1110 last_bb
= ENTRY_BLOCK_PTR
;
1112 create_log_links ();
1113 FOR_EACH_BB (this_basic_block
)
1115 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1120 if (!single_pred_p (this_basic_block
)
1121 || single_pred (this_basic_block
) != last_bb
)
1122 label_tick_ebb_start
= label_tick
;
1123 last_bb
= this_basic_block
;
1125 FOR_BB_INSNS (this_basic_block
, insn
)
1126 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1128 subst_low_luid
= DF_INSN_LUID (insn
);
1131 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1133 record_dead_and_set_regs (insn
);
1136 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1137 if (REG_NOTE_KIND (links
) == REG_INC
)
1138 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1142 /* Record the current insn_rtx_cost of this instruction. */
1143 if (NONJUMP_INSN_P (insn
))
1144 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1145 optimize_this_for_speed_p
);
1147 fprintf(dump_file
, "insn_cost %d: %d\n",
1148 INSN_UID (insn
), INSN_COST (insn
));
1152 nonzero_sign_valid
= 1;
1154 /* Now scan all the insns in forward order. */
1155 label_tick
= label_tick_ebb_start
= 1;
1157 setup_incoming_promotions (first
);
1158 last_bb
= ENTRY_BLOCK_PTR
;
1160 FOR_EACH_BB (this_basic_block
)
1162 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1167 if (!single_pred_p (this_basic_block
)
1168 || single_pred (this_basic_block
) != last_bb
)
1169 label_tick_ebb_start
= label_tick
;
1170 last_bb
= this_basic_block
;
1172 rtl_profile_for_bb (this_basic_block
);
1173 for (insn
= BB_HEAD (this_basic_block
);
1174 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1175 insn
= next
? next
: NEXT_INSN (insn
))
1178 if (NONDEBUG_INSN_P (insn
))
1180 /* See if we know about function return values before this
1181 insn based upon SUBREG flags. */
1182 check_promoted_subreg (insn
, PATTERN (insn
));
1184 /* See if we can find hardregs and subreg of pseudos in
1185 narrower modes. This could help turning TRUNCATEs
1187 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1189 /* Try this insn with each insn it links back to. */
1191 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1192 if ((next
= try_combine (insn
, XEXP (links
, 0), NULL_RTX
,
1193 NULL_RTX
, &new_direct_jump_p
)) != 0)
1196 /* Try each sequence of three linked insns ending with this one. */
1198 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1200 rtx link
= XEXP (links
, 0);
1202 /* If the linked insn has been replaced by a note, then there
1203 is no point in pursuing this chain any further. */
1207 for (nextlinks
= LOG_LINKS (link
);
1209 nextlinks
= XEXP (nextlinks
, 1))
1210 if ((next
= try_combine (insn
, link
, XEXP (nextlinks
, 0),
1212 &new_direct_jump_p
)) != 0)
1217 /* Try to combine a jump insn that uses CC0
1218 with a preceding insn that sets CC0, and maybe with its
1219 logical predecessor as well.
1220 This is how we make decrement-and-branch insns.
1221 We need this special code because data flow connections
1222 via CC0 do not get entered in LOG_LINKS. */
1225 && (prev
= prev_nonnote_insn (insn
)) != 0
1226 && NONJUMP_INSN_P (prev
)
1227 && sets_cc0_p (PATTERN (prev
)))
1229 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1230 &new_direct_jump_p
)) != 0)
1233 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1234 nextlinks
= XEXP (nextlinks
, 1))
1235 if ((next
= try_combine (insn
, prev
, XEXP (nextlinks
, 0),
1237 &new_direct_jump_p
)) != 0)
1241 /* Do the same for an insn that explicitly references CC0. */
1242 if (NONJUMP_INSN_P (insn
)
1243 && (prev
= prev_nonnote_insn (insn
)) != 0
1244 && NONJUMP_INSN_P (prev
)
1245 && sets_cc0_p (PATTERN (prev
))
1246 && GET_CODE (PATTERN (insn
)) == SET
1247 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1249 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1250 &new_direct_jump_p
)) != 0)
1253 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1254 nextlinks
= XEXP (nextlinks
, 1))
1255 if ((next
= try_combine (insn
, prev
, XEXP (nextlinks
, 0),
1257 &new_direct_jump_p
)) != 0)
1261 /* Finally, see if any of the insns that this insn links to
1262 explicitly references CC0. If so, try this insn, that insn,
1263 and its predecessor if it sets CC0. */
1264 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1265 if (NONJUMP_INSN_P (XEXP (links
, 0))
1266 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
1267 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
1268 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
1269 && NONJUMP_INSN_P (prev
)
1270 && sets_cc0_p (PATTERN (prev
))
1271 && (next
= try_combine (insn
, XEXP (links
, 0),
1273 &new_direct_jump_p
)) != 0)
1277 /* Try combining an insn with two different insns whose results it
1279 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1280 for (nextlinks
= XEXP (links
, 1); nextlinks
;
1281 nextlinks
= XEXP (nextlinks
, 1))
1282 if ((next
= try_combine (insn
, XEXP (links
, 0),
1283 XEXP (nextlinks
, 0), NULL_RTX
,
1284 &new_direct_jump_p
)) != 0)
1287 /* Try four-instruction combinations. */
1288 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1291 rtx link
= XEXP (links
, 0);
1293 /* If the linked insn has been replaced by a note, then there
1294 is no point in pursuing this chain any further. */
1298 for (next1
= LOG_LINKS (link
); next1
; next1
= XEXP (next1
, 1))
1300 rtx link1
= XEXP (next1
, 0);
1303 /* I0 -> I1 -> I2 -> I3. */
1304 for (nextlinks
= LOG_LINKS (link1
); nextlinks
;
1305 nextlinks
= XEXP (nextlinks
, 1))
1306 if ((next
= try_combine (insn
, link
, link1
,
1307 XEXP (nextlinks
, 0),
1308 &new_direct_jump_p
)) != 0)
1310 /* I0, I1 -> I2, I2 -> I3. */
1311 for (nextlinks
= XEXP (next1
, 1); nextlinks
;
1312 nextlinks
= XEXP (nextlinks
, 1))
1313 if ((next
= try_combine (insn
, link
, link1
,
1314 XEXP (nextlinks
, 0),
1315 &new_direct_jump_p
)) != 0)
1319 for (next1
= XEXP (links
, 1); next1
; next1
= XEXP (next1
, 1))
1321 rtx link1
= XEXP (next1
, 0);
1324 /* I0 -> I2; I1, I2 -> I3. */
1325 for (nextlinks
= LOG_LINKS (link
); nextlinks
;
1326 nextlinks
= XEXP (nextlinks
, 1))
1327 if ((next
= try_combine (insn
, link
, link1
,
1328 XEXP (nextlinks
, 0),
1329 &new_direct_jump_p
)) != 0)
1331 /* I0 -> I1; I1, I2 -> I3. */
1332 for (nextlinks
= LOG_LINKS (link1
); nextlinks
;
1333 nextlinks
= XEXP (nextlinks
, 1))
1334 if ((next
= try_combine (insn
, link
, link1
,
1335 XEXP (nextlinks
, 0),
1336 &new_direct_jump_p
)) != 0)
1341 /* Try this insn with each REG_EQUAL note it links back to. */
1342 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1345 rtx temp
= XEXP (links
, 0);
1346 if ((set
= single_set (temp
)) != 0
1347 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1348 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1349 /* Avoid using a register that may already been marked
1350 dead by an earlier instruction. */
1351 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1352 && (GET_MODE (note
) == VOIDmode
1353 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1354 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1356 /* Temporarily replace the set's source with the
1357 contents of the REG_EQUAL note. The insn will
1358 be deleted or recognized by try_combine. */
1359 rtx orig
= SET_SRC (set
);
1360 SET_SRC (set
) = note
;
1362 i2mod_old_rhs
= copy_rtx (orig
);
1363 i2mod_new_rhs
= copy_rtx (note
);
1364 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1365 &new_direct_jump_p
);
1369 SET_SRC (set
) = orig
;
1374 record_dead_and_set_regs (insn
);
1382 default_rtl_profile ();
1385 new_direct_jump_p
|= purge_all_dead_edges ();
1386 delete_noop_moves ();
1389 free (uid_log_links
);
1390 free (uid_insn_cost
);
1391 VEC_free (reg_stat_type
, heap
, reg_stat
);
1394 struct undo
*undo
, *next
;
1395 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1403 total_attempts
+= combine_attempts
;
1404 total_merges
+= combine_merges
;
1405 total_extras
+= combine_extras
;
1406 total_successes
+= combine_successes
;
1408 nonzero_sign_valid
= 0;
1409 rtl_hooks
= general_rtl_hooks
;
1411 /* Make recognizer allow volatile MEMs again. */
1414 return new_direct_jump_p
;
1417 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1420 init_reg_last (void)
1425 FOR_EACH_VEC_ELT (reg_stat_type
, reg_stat
, i
, p
)
1426 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1429 /* Set up any promoted values for incoming argument registers. */
1432 setup_incoming_promotions (rtx first
)
1435 bool strictly_local
= false;
1437 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1438 arg
= DECL_CHAIN (arg
))
1440 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1442 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1444 /* Only continue if the incoming argument is in a register. */
1448 /* Determine, if possible, whether all call sites of the current
1449 function lie within the current compilation unit. (This does
1450 take into account the exporting of a function via taking its
1451 address, and so forth.) */
1452 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1454 /* The mode and signedness of the argument before any promotions happen
1455 (equal to the mode of the pseudo holding it at that stage). */
1456 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1457 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1459 /* The mode and signedness of the argument after any source language and
1460 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1461 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1462 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1464 /* The mode and signedness of the argument as it is actually passed,
1465 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1466 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1467 TREE_TYPE (cfun
->decl
), 0);
1469 /* The mode of the register in which the argument is being passed. */
1470 mode4
= GET_MODE (reg
);
1472 /* Eliminate sign extensions in the callee when:
1473 (a) A mode promotion has occurred; */
1476 /* (b) The mode of the register is the same as the mode of
1477 the argument as it is passed; */
1480 /* (c) There's no language level extension; */
1483 /* (c.1) All callers are from the current compilation unit. If that's
1484 the case we don't have to rely on an ABI, we only have to know
1485 what we're generating right now, and we know that we will do the
1486 mode1 to mode2 promotion with the given sign. */
1487 else if (!strictly_local
)
1489 /* (c.2) The combination of the two promotions is useful. This is
1490 true when the signs match, or if the first promotion is unsigned.
1491 In the later case, (sign_extend (zero_extend x)) is the same as
1492 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1498 /* Record that the value was promoted from mode1 to mode3,
1499 so that any sign extension at the head of the current
1500 function may be eliminated. */
1501 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1502 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1503 record_value_for_reg (reg
, first
, x
);
1507 /* Called via note_stores. If X is a pseudo that is narrower than
1508 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1510 If we are setting only a portion of X and we can't figure out what
1511 portion, assume all bits will be used since we don't know what will
1514 Similarly, set how many bits of X are known to be copies of the sign bit
1515 at all locations in the function. This is the smallest number implied
1519 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1521 rtx insn
= (rtx
) data
;
1525 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1526 /* If this register is undefined at the start of the file, we can't
1527 say what its contents were. */
1528 && ! REGNO_REG_SET_P
1529 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1530 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1532 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1534 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1536 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1537 rsp
->sign_bit_copies
= 1;
1541 /* If this register is being initialized using itself, and the
1542 register is uninitialized in this basic block, and there are
1543 no LOG_LINKS which set the register, then part of the
1544 register is uninitialized. In that case we can't assume
1545 anything about the number of nonzero bits.
1547 ??? We could do better if we checked this in
1548 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1549 could avoid making assumptions about the insn which initially
1550 sets the register, while still using the information in other
1551 insns. We would have to be careful to check every insn
1552 involved in the combination. */
1555 && reg_referenced_p (x
, PATTERN (insn
))
1556 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1561 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1563 if (dead_or_set_p (XEXP (link
, 0), x
))
1568 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1569 rsp
->sign_bit_copies
= 1;
1574 /* If this is a complex assignment, see if we can convert it into a
1575 simple assignment. */
1576 set
= expand_field_assignment (set
);
1578 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1579 set what we know about X. */
1581 if (SET_DEST (set
) == x
1582 || (GET_CODE (SET_DEST (set
)) == SUBREG
1583 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1584 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1585 && SUBREG_REG (SET_DEST (set
)) == x
))
1587 rtx src
= SET_SRC (set
);
1589 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1590 /* If X is narrower than a word and SRC is a non-negative
1591 constant that would appear negative in the mode of X,
1592 sign-extend it for use in reg_stat[].nonzero_bits because some
1593 machines (maybe most) will actually do the sign-extension
1594 and this is the conservative approach.
1596 ??? For 2.5, try to tighten up the MD files in this regard
1597 instead of this kludge. */
1599 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1600 && CONST_INT_P (src
)
1602 && 0 != (UINTVAL (src
)
1603 & ((unsigned HOST_WIDE_INT
) 1
1604 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1605 src
= GEN_INT (UINTVAL (src
)
1606 | ((unsigned HOST_WIDE_INT
) (-1)
1607 << GET_MODE_BITSIZE (GET_MODE (x
))));
1610 /* Don't call nonzero_bits if it cannot change anything. */
1611 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1612 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1613 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1614 if (rsp
->sign_bit_copies
== 0
1615 || rsp
->sign_bit_copies
> num
)
1616 rsp
->sign_bit_copies
= num
;
1620 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1621 rsp
->sign_bit_copies
= 1;
1626 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1627 optionally insns that were previously combined into I3 or that will be
1628 combined into the merger of INSN and I3. The order is PRED, PRED2,
1629 INSN, SUCC, SUCC2, I3.
1631 Return 0 if the combination is not allowed for any reason.
1633 If the combination is allowed, *PDEST will be set to the single
1634 destination of INSN and *PSRC to the single source, and this function
1638 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1639 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1640 rtx
*pdest
, rtx
*psrc
)
1649 bool all_adjacent
= true;
1655 if (next_active_insn (succ2
) != i3
)
1656 all_adjacent
= false;
1657 if (next_active_insn (succ
) != succ2
)
1658 all_adjacent
= false;
1660 else if (next_active_insn (succ
) != i3
)
1661 all_adjacent
= false;
1662 if (next_active_insn (insn
) != succ
)
1663 all_adjacent
= false;
1665 else if (next_active_insn (insn
) != i3
)
1666 all_adjacent
= false;
1668 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1669 or a PARALLEL consisting of such a SET and CLOBBERs.
1671 If INSN has CLOBBER parallel parts, ignore them for our processing.
1672 By definition, these happen during the execution of the insn. When it
1673 is merged with another insn, all bets are off. If they are, in fact,
1674 needed and aren't also supplied in I3, they may be added by
1675 recog_for_combine. Otherwise, it won't match.
1677 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1680 Get the source and destination of INSN. If more than one, can't
1683 if (GET_CODE (PATTERN (insn
)) == SET
)
1684 set
= PATTERN (insn
);
1685 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1686 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1688 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1690 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1692 switch (GET_CODE (elt
))
1694 /* This is important to combine floating point insns
1695 for the SH4 port. */
1697 /* Combining an isolated USE doesn't make sense.
1698 We depend here on combinable_i3pat to reject them. */
1699 /* The code below this loop only verifies that the inputs of
1700 the SET in INSN do not change. We call reg_set_between_p
1701 to verify that the REG in the USE does not change between
1703 If the USE in INSN was for a pseudo register, the matching
1704 insn pattern will likely match any register; combining this
1705 with any other USE would only be safe if we knew that the
1706 used registers have identical values, or if there was
1707 something to tell them apart, e.g. different modes. For
1708 now, we forgo such complicated tests and simply disallow
1709 combining of USES of pseudo registers with any other USE. */
1710 if (REG_P (XEXP (elt
, 0))
1711 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1713 rtx i3pat
= PATTERN (i3
);
1714 int i
= XVECLEN (i3pat
, 0) - 1;
1715 unsigned int regno
= REGNO (XEXP (elt
, 0));
1719 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1721 if (GET_CODE (i3elt
) == USE
1722 && REG_P (XEXP (i3elt
, 0))
1723 && (REGNO (XEXP (i3elt
, 0)) == regno
1724 ? reg_set_between_p (XEXP (elt
, 0),
1725 PREV_INSN (insn
), i3
)
1726 : regno
>= FIRST_PSEUDO_REGISTER
))
1733 /* We can ignore CLOBBERs. */
1738 /* Ignore SETs whose result isn't used but not those that
1739 have side-effects. */
1740 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1741 && insn_nothrow_p (insn
)
1742 && !side_effects_p (elt
))
1745 /* If we have already found a SET, this is a second one and
1746 so we cannot combine with this insn. */
1754 /* Anything else means we can't combine. */
1760 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1761 so don't do anything with it. */
1762 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1771 set
= expand_field_assignment (set
);
1772 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1774 /* Don't eliminate a store in the stack pointer. */
1775 if (dest
== stack_pointer_rtx
1776 /* Don't combine with an insn that sets a register to itself if it has
1777 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1778 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1779 /* Can't merge an ASM_OPERANDS. */
1780 || GET_CODE (src
) == ASM_OPERANDS
1781 /* Can't merge a function call. */
1782 || GET_CODE (src
) == CALL
1783 /* Don't eliminate a function call argument. */
1785 && (find_reg_fusage (i3
, USE
, dest
)
1787 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1788 && global_regs
[REGNO (dest
)])))
1789 /* Don't substitute into an incremented register. */
1790 || FIND_REG_INC_NOTE (i3
, dest
)
1791 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1792 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1793 /* Don't substitute into a non-local goto, this confuses CFG. */
1794 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1795 /* Make sure that DEST is not used after SUCC but before I3. */
1798 && (reg_used_between_p (dest
, succ2
, i3
)
1799 || reg_used_between_p (dest
, succ
, succ2
)))
1800 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1801 /* Make sure that the value that is to be substituted for the register
1802 does not use any registers whose values alter in between. However,
1803 If the insns are adjacent, a use can't cross a set even though we
1804 think it might (this can happen for a sequence of insns each setting
1805 the same destination; last_set of that register might point to
1806 a NOTE). If INSN has a REG_EQUIV note, the register is always
1807 equivalent to the memory so the substitution is valid even if there
1808 are intervening stores. Also, don't move a volatile asm or
1809 UNSPEC_VOLATILE across any other insns. */
1812 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1813 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1814 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1815 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1816 /* Don't combine across a CALL_INSN, because that would possibly
1817 change whether the life span of some REGs crosses calls or not,
1818 and it is a pain to update that information.
1819 Exception: if source is a constant, moving it later can't hurt.
1820 Accept that as a special case. */
1821 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1824 /* DEST must either be a REG or CC0. */
1827 /* If register alignment is being enforced for multi-word items in all
1828 cases except for parameters, it is possible to have a register copy
1829 insn referencing a hard register that is not allowed to contain the
1830 mode being copied and which would not be valid as an operand of most
1831 insns. Eliminate this problem by not combining with such an insn.
1833 Also, on some machines we don't want to extend the life of a hard
1837 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1838 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1839 /* Don't extend the life of a hard register unless it is
1840 user variable (if we have few registers) or it can't
1841 fit into the desired register (meaning something special
1843 Also avoid substituting a return register into I3, because
1844 reload can't handle a conflict with constraints of other
1846 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1847 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1850 else if (GET_CODE (dest
) != CC0
)
1854 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1855 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1856 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1858 /* Don't substitute for a register intended as a clobberable
1860 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1861 if (rtx_equal_p (reg
, dest
))
1864 /* If the clobber represents an earlyclobber operand, we must not
1865 substitute an expression containing the clobbered register.
1866 As we do not analyze the constraint strings here, we have to
1867 make the conservative assumption. However, if the register is
1868 a fixed hard reg, the clobber cannot represent any operand;
1869 we leave it up to the machine description to either accept or
1870 reject use-and-clobber patterns. */
1872 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1873 || !fixed_regs
[REGNO (reg
)])
1874 if (reg_overlap_mentioned_p (reg
, src
))
1878 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1879 or not), reject, unless nothing volatile comes between it and I3 */
1881 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1883 /* Make sure neither succ nor succ2 contains a volatile reference. */
1884 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1886 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1888 /* We'll check insns between INSN and I3 below. */
1891 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1892 to be an explicit register variable, and was chosen for a reason. */
1894 if (GET_CODE (src
) == ASM_OPERANDS
1895 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1898 /* If there are any volatile insns between INSN and I3, reject, because
1899 they might affect machine state. */
1901 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1902 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& volatile_insn_p (PATTERN (p
)))
1905 /* If INSN contains an autoincrement or autodecrement, make sure that
1906 register is not used between there and I3, and not already used in
1907 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1908 Also insist that I3 not be a jump; if it were one
1909 and the incremented register were spilled, we would lose. */
1912 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1913 if (REG_NOTE_KIND (link
) == REG_INC
1915 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1916 || (pred
!= NULL_RTX
1917 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1918 || (pred2
!= NULL_RTX
1919 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1920 || (succ
!= NULL_RTX
1921 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1922 || (succ2
!= NULL_RTX
1923 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1924 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1929 /* Don't combine an insn that follows a CC0-setting insn.
1930 An insn that uses CC0 must not be separated from the one that sets it.
1931 We do, however, allow I2 to follow a CC0-setting insn if that insn
1932 is passed as I1; in that case it will be deleted also.
1933 We also allow combining in this case if all the insns are adjacent
1934 because that would leave the two CC0 insns adjacent as well.
1935 It would be more logical to test whether CC0 occurs inside I1 or I2,
1936 but that would be much slower, and this ought to be equivalent. */
1938 p
= prev_nonnote_insn (insn
);
1939 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1944 /* If we get here, we have passed all the tests and the combination is
1953 /* LOC is the location within I3 that contains its pattern or the component
1954 of a PARALLEL of the pattern. We validate that it is valid for combining.
1956 One problem is if I3 modifies its output, as opposed to replacing it
1957 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1958 doing so would produce an insn that is not equivalent to the original insns.
1962 (set (reg:DI 101) (reg:DI 100))
1963 (set (subreg:SI (reg:DI 101) 0) <foo>)
1965 This is NOT equivalent to:
1967 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1968 (set (reg:DI 101) (reg:DI 100))])
1970 Not only does this modify 100 (in which case it might still be valid
1971 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1973 We can also run into a problem if I2 sets a register that I1
1974 uses and I1 gets directly substituted into I3 (not via I2). In that
1975 case, we would be getting the wrong value of I2DEST into I3, so we
1976 must reject the combination. This case occurs when I2 and I1 both
1977 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1978 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1979 of a SET must prevent combination from occurring. The same situation
1980 can occur for I0, in which case I0_NOT_IN_SRC is set.
1982 Before doing the above check, we first try to expand a field assignment
1983 into a set of logical operations.
1985 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1986 we place a register that is both set and used within I3. If more than one
1987 such register is detected, we fail.
1989 Return 1 if the combination is valid, zero otherwise. */
1992 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
1993 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
1997 if (GET_CODE (x
) == SET
)
2000 rtx dest
= SET_DEST (set
);
2001 rtx src
= SET_SRC (set
);
2002 rtx inner_dest
= dest
;
2005 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2006 || GET_CODE (inner_dest
) == SUBREG
2007 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2008 inner_dest
= XEXP (inner_dest
, 0);
2010 /* Check for the case where I3 modifies its output, as discussed
2011 above. We don't want to prevent pseudos from being combined
2012 into the address of a MEM, so only prevent the combination if
2013 i1 or i2 set the same MEM. */
2014 if ((inner_dest
!= dest
&&
2015 (!MEM_P (inner_dest
)
2016 || rtx_equal_p (i2dest
, inner_dest
)
2017 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2018 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2019 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2020 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2021 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2023 /* This is the same test done in can_combine_p except we can't test
2024 all_adjacent; we don't have to, since this instruction will stay
2025 in place, thus we are not considering increasing the lifetime of
2028 Also, if this insn sets a function argument, combining it with
2029 something that might need a spill could clobber a previous
2030 function argument; the all_adjacent test in can_combine_p also
2031 checks this; here, we do a more specific test for this case. */
2033 || (REG_P (inner_dest
)
2034 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2035 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2036 GET_MODE (inner_dest
))))
2037 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2038 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2041 /* If DEST is used in I3, it is being killed in this insn, so
2042 record that for later. We have to consider paradoxical
2043 subregs here, since they kill the whole register, but we
2044 ignore partial subregs, STRICT_LOW_PART, etc.
2045 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2046 STACK_POINTER_REGNUM, since these are always considered to be
2047 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2049 if (GET_CODE (subdest
) == SUBREG
2050 && (GET_MODE_SIZE (GET_MODE (subdest
))
2051 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2052 subdest
= SUBREG_REG (subdest
);
2055 && reg_referenced_p (subdest
, PATTERN (i3
))
2056 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2057 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2058 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2060 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2061 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2062 || ! fixed_regs
[REGNO (subdest
)])
2064 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2066 if (*pi3dest_killed
)
2069 *pi3dest_killed
= subdest
;
2073 else if (GET_CODE (x
) == PARALLEL
)
2077 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2078 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2079 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2086 /* Return 1 if X is an arithmetic expression that contains a multiplication
2087 and division. We don't count multiplications by powers of two here. */
2090 contains_muldiv (rtx x
)
2092 switch (GET_CODE (x
))
2094 case MOD
: case DIV
: case UMOD
: case UDIV
:
2098 return ! (CONST_INT_P (XEXP (x
, 1))
2099 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2102 return contains_muldiv (XEXP (x
, 0))
2103 || contains_muldiv (XEXP (x
, 1));
2106 return contains_muldiv (XEXP (x
, 0));
2112 /* Determine whether INSN can be used in a combination. Return nonzero if
2113 not. This is used in try_combine to detect early some cases where we
2114 can't perform combinations. */
2117 cant_combine_insn_p (rtx insn
)
2122 /* If this isn't really an insn, we can't do anything.
2123 This can occur when flow deletes an insn that it has merged into an
2124 auto-increment address. */
2125 if (! INSN_P (insn
))
2128 /* Never combine loads and stores involving hard regs that are likely
2129 to be spilled. The register allocator can usually handle such
2130 reg-reg moves by tying. If we allow the combiner to make
2131 substitutions of likely-spilled regs, reload might die.
2132 As an exception, we allow combinations involving fixed regs; these are
2133 not available to the register allocator so there's no risk involved. */
2135 set
= single_set (insn
);
2138 src
= SET_SRC (set
);
2139 dest
= SET_DEST (set
);
2140 if (GET_CODE (src
) == SUBREG
)
2141 src
= SUBREG_REG (src
);
2142 if (GET_CODE (dest
) == SUBREG
)
2143 dest
= SUBREG_REG (dest
);
2144 if (REG_P (src
) && REG_P (dest
)
2145 && ((HARD_REGISTER_P (src
)
2146 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2147 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2148 || (HARD_REGISTER_P (dest
)
2149 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2150 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2156 struct likely_spilled_retval_info
2158 unsigned regno
, nregs
;
2162 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2163 hard registers that are known to be written to / clobbered in full. */
2165 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2167 struct likely_spilled_retval_info
*const info
=
2168 (struct likely_spilled_retval_info
*) data
;
2169 unsigned regno
, nregs
;
2172 if (!REG_P (XEXP (set
, 0)))
2175 if (regno
>= info
->regno
+ info
->nregs
)
2177 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2178 if (regno
+ nregs
<= info
->regno
)
2180 new_mask
= (2U << (nregs
- 1)) - 1;
2181 if (regno
< info
->regno
)
2182 new_mask
>>= info
->regno
- regno
;
2184 new_mask
<<= regno
- info
->regno
;
2185 info
->mask
&= ~new_mask
;
2188 /* Return nonzero iff part of the return value is live during INSN, and
2189 it is likely spilled. This can happen when more than one insn is needed
2190 to copy the return value, e.g. when we consider to combine into the
2191 second copy insn for a complex value. */
2194 likely_spilled_retval_p (rtx insn
)
2196 rtx use
= BB_END (this_basic_block
);
2198 unsigned regno
, nregs
;
2199 /* We assume here that no machine mode needs more than
2200 32 hard registers when the value overlaps with a register
2201 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2203 struct likely_spilled_retval_info info
;
2205 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2207 reg
= XEXP (PATTERN (use
), 0);
2208 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2210 regno
= REGNO (reg
);
2211 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2214 mask
= (2U << (nregs
- 1)) - 1;
2216 /* Disregard parts of the return value that are set later. */
2220 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2222 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2225 /* Check if any of the (probably) live return value registers is
2230 if ((mask
& 1 << nregs
)
2231 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2237 /* Adjust INSN after we made a change to its destination.
2239 Changing the destination can invalidate notes that say something about
2240 the results of the insn and a LOG_LINK pointing to the insn. */
2243 adjust_for_new_dest (rtx insn
)
2245 /* For notes, be conservative and simply remove them. */
2246 remove_reg_equal_equiv_notes (insn
);
2248 /* The new insn will have a destination that was previously the destination
2249 of an insn just above it. Call distribute_links to make a LOG_LINK from
2250 the next use of that destination. */
2251 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
2253 df_insn_rescan (insn
);
2256 /* Return TRUE if combine can reuse reg X in mode MODE.
2257 ADDED_SETS is nonzero if the original set is still required. */
2259 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2267 /* Allow hard registers if the new mode is legal, and occupies no more
2268 registers than the old mode. */
2269 if (regno
< FIRST_PSEUDO_REGISTER
)
2270 return (HARD_REGNO_MODE_OK (regno
, mode
)
2271 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2272 >= hard_regno_nregs
[regno
][mode
]));
2274 /* Or a pseudo that is only used once. */
2275 return (REG_N_SETS (regno
) == 1 && !added_sets
2276 && !REG_USERVAR_P (x
));
2280 /* Check whether X, the destination of a set, refers to part of
2281 the register specified by REG. */
2284 reg_subword_p (rtx x
, rtx reg
)
2286 /* Check that reg is an integer mode register. */
2287 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2290 if (GET_CODE (x
) == STRICT_LOW_PART
2291 || GET_CODE (x
) == ZERO_EXTRACT
)
2294 return GET_CODE (x
) == SUBREG
2295 && SUBREG_REG (x
) == reg
2296 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2300 /* Replace auto-increment addressing modes with explicit operations to access
2301 the same addresses without modifying the corresponding registers. */
2304 cleanup_auto_inc_dec (rtx src
, enum machine_mode mem_mode
)
2307 const RTX_CODE code
= GET_CODE (x
);
2323 /* SCRATCH must be shared because they represent distinct values. */
2326 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
2331 if (shared_const_p (x
))
2336 mem_mode
= GET_MODE (x
);
2341 gcc_assert (mem_mode
!= VOIDmode
&& mem_mode
!= BLKmode
);
2342 return gen_rtx_PLUS (GET_MODE (x
),
2343 cleanup_auto_inc_dec (XEXP (x
, 0), mem_mode
),
2344 GEN_INT (code
== PRE_INC
2345 ? GET_MODE_SIZE (mem_mode
)
2346 : -GET_MODE_SIZE (mem_mode
)));
2352 return cleanup_auto_inc_dec (code
== PRE_MODIFY
2353 ? XEXP (x
, 1) : XEXP (x
, 0),
2360 /* Copy the various flags, fields, and other information. We assume
2361 that all fields need copying, and then clear the fields that should
2362 not be copied. That is the sensible default behavior, and forces
2363 us to explicitly document why we are *not* copying a flag. */
2364 x
= shallow_copy_rtx (x
);
2366 /* We do not copy the USED flag, which is used as a mark bit during
2367 walks over the RTL. */
2368 RTX_FLAG (x
, used
) = 0;
2370 /* We do not copy FRAME_RELATED for INSNs. */
2372 RTX_FLAG (x
, frame_related
) = 0;
2374 fmt
= GET_RTX_FORMAT (code
);
2375 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2377 XEXP (x
, i
) = cleanup_auto_inc_dec (XEXP (x
, i
), mem_mode
);
2378 else if (fmt
[i
] == 'E' || fmt
[i
] == 'V')
2381 XVEC (x
, i
) = rtvec_alloc (XVECLEN (x
, i
));
2382 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2384 = cleanup_auto_inc_dec (XVECEXP (src
, i
, j
), mem_mode
);
2391 /* Auxiliary data structure for propagate_for_debug_stmt. */
2393 struct rtx_subst_pair
2399 /* DATA points to an rtx_subst_pair. Return the value that should be
2403 propagate_for_debug_subst (rtx from
, const_rtx old_rtx
, void *data
)
2405 struct rtx_subst_pair
*pair
= (struct rtx_subst_pair
*)data
;
2407 if (!rtx_equal_p (from
, old_rtx
))
2409 if (!pair
->adjusted
)
2411 pair
->adjusted
= true;
2413 pair
->to
= cleanup_auto_inc_dec (pair
->to
, VOIDmode
);
2415 pair
->to
= copy_rtx (pair
->to
);
2417 pair
->to
= make_compound_operation (pair
->to
, SET
);
2420 return copy_rtx (pair
->to
);
2423 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2427 propagate_for_debug (rtx insn
, rtx last
, rtx dest
, rtx src
)
2431 struct rtx_subst_pair p
;
2435 next
= NEXT_INSN (insn
);
2436 while (next
!= last
)
2439 next
= NEXT_INSN (insn
);
2440 if (DEBUG_INSN_P (insn
))
2442 loc
= simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn
),
2443 dest
, propagate_for_debug_subst
, &p
);
2444 if (loc
== INSN_VAR_LOCATION_LOC (insn
))
2446 INSN_VAR_LOCATION_LOC (insn
) = loc
;
2447 df_insn_rescan (insn
);
2452 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2453 Note that the INSN should be deleted *after* removing dead edges, so
2454 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2455 but not for a (set (pc) (label_ref FOO)). */
2458 update_cfg_for_uncondjump (rtx insn
)
2460 basic_block bb
= BLOCK_FOR_INSN (insn
);
2461 bool at_end
= (BB_END (bb
) == insn
);
2464 purge_dead_edges (bb
);
2467 if (at_end
&& EDGE_COUNT (bb
->succs
) == 1)
2471 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2473 /* Remove barriers from the footer if there are any. */
2474 for (insn
= bb
->il
.rtl
->footer
; insn
; insn
= NEXT_INSN (insn
))
2475 if (BARRIER_P (insn
))
2477 if (PREV_INSN (insn
))
2478 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2480 bb
->il
.rtl
->footer
= NEXT_INSN (insn
);
2481 if (NEXT_INSN (insn
))
2482 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2484 else if (LABEL_P (insn
))
2489 /* Try to combine the insns I0, I1 and I2 into I3.
2490 Here I0, I1 and I2 appear earlier than I3.
2491 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2494 If we are combining more than two insns and the resulting insn is not
2495 recognized, try splitting it into two insns. If that happens, I2 and I3
2496 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2497 Otherwise, I0, I1 and I2 are pseudo-deleted.
2499 Return 0 if the combination does not work. Then nothing is changed.
2500 If we did the combination, return the insn at which combine should
2503 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2504 new direct jump instruction. */
2507 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
)
2509 /* New patterns for I3 and I2, respectively. */
2510 rtx newpat
, newi2pat
= 0;
2511 rtvec newpat_vec_with_clobbers
= 0;
2512 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2513 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2515 int added_sets_0
, added_sets_1
, added_sets_2
;
2516 /* Total number of SETs to put into I3. */
2518 /* Nonzero if I2's or I1's body now appears in I3. */
2519 int i2_is_used
= 0, i1_is_used
= 0;
2520 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2521 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2522 /* Contains I3 if the destination of I3 is used in its source, which means
2523 that the old life of I3 is being killed. If that usage is placed into
2524 I2 and not in I3, a REG_DEAD note must be made. */
2525 rtx i3dest_killed
= 0;
2526 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2527 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2528 /* Copy of SET_SRC of I1, if needed. */
2530 /* Set if I2DEST was reused as a scratch register. */
2531 bool i2scratch
= false;
2532 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2533 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2534 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2535 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2536 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2537 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2538 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2539 /* Notes that must be added to REG_NOTES in I3 and I2. */
2540 rtx new_i3_notes
, new_i2_notes
;
2541 /* Notes that we substituted I3 into I2 instead of the normal case. */
2542 int i3_subst_into_i2
= 0;
2543 /* Notes that I1, I2 or I3 is a MULT operation. */
2546 int changed_i3_dest
= 0;
2552 rtx new_other_notes
;
2555 /* Only try four-insn combinations when there's high likelihood of
2556 success. Look for simple insns, such as loads of constants or
2557 binary operations involving a constant. */
2564 if (!flag_expensive_optimizations
)
2567 for (i
= 0; i
< 4; i
++)
2569 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2570 rtx set
= single_set (insn
);
2574 src
= SET_SRC (set
);
2575 if (CONSTANT_P (src
))
2580 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2582 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2583 || GET_CODE (src
) == LSHIFTRT
)
2586 if (ngood
< 2 && nshift
< 2)
2590 /* Exit early if one of the insns involved can't be used for
2592 if (cant_combine_insn_p (i3
)
2593 || cant_combine_insn_p (i2
)
2594 || (i1
&& cant_combine_insn_p (i1
))
2595 || (i0
&& cant_combine_insn_p (i0
))
2596 || likely_spilled_retval_p (i3
))
2600 undobuf
.other_insn
= 0;
2602 /* Reset the hard register usage information. */
2603 CLEAR_HARD_REG_SET (newpat_used_regs
);
2605 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2608 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2609 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2611 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2612 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2614 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2615 INSN_UID (i2
), INSN_UID (i3
));
2618 /* If multiple insns feed into one of I2 or I3, they can be in any
2619 order. To simplify the code below, reorder them in sequence. */
2620 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2621 temp
= i2
, i2
= i0
, i0
= temp
;
2622 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2623 temp
= i1
, i1
= i0
, i0
= temp
;
2624 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2625 temp
= i1
, i1
= i2
, i2
= temp
;
2627 added_links_insn
= 0;
2629 /* First check for one important special case that the code below will
2630 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2631 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2632 we may be able to replace that destination with the destination of I3.
2633 This occurs in the common code where we compute both a quotient and
2634 remainder into a structure, in which case we want to do the computation
2635 directly into the structure to avoid register-register copies.
2637 Note that this case handles both multiple sets in I2 and also cases
2638 where I2 has a number of CLOBBERs inside the PARALLEL.
2640 We make very conservative checks below and only try to handle the
2641 most common cases of this. For example, we only handle the case
2642 where I2 and I3 are adjacent to avoid making difficult register
2645 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2646 && REG_P (SET_SRC (PATTERN (i3
)))
2647 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2648 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2649 && GET_CODE (PATTERN (i2
)) == PARALLEL
2650 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2651 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2652 below would need to check what is inside (and reg_overlap_mentioned_p
2653 doesn't support those codes anyway). Don't allow those destinations;
2654 the resulting insn isn't likely to be recognized anyway. */
2655 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2656 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2657 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2658 SET_DEST (PATTERN (i3
)))
2659 && next_active_insn (i2
) == i3
)
2661 rtx p2
= PATTERN (i2
);
2663 /* Make sure that the destination of I3,
2664 which we are going to substitute into one output of I2,
2665 is not used within another output of I2. We must avoid making this:
2666 (parallel [(set (mem (reg 69)) ...)
2667 (set (reg 69) ...)])
2668 which is not well-defined as to order of actions.
2669 (Besides, reload can't handle output reloads for this.)
2671 The problem can also happen if the dest of I3 is a memory ref,
2672 if another dest in I2 is an indirect memory ref. */
2673 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2674 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2675 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2676 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2677 SET_DEST (XVECEXP (p2
, 0, i
))))
2680 if (i
== XVECLEN (p2
, 0))
2681 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2682 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2683 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2688 subst_low_luid
= DF_INSN_LUID (i2
);
2690 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2691 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2692 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2693 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2695 /* Replace the dest in I2 with our dest and make the resulting
2696 insn the new pattern for I3. Then skip to where we validate
2697 the pattern. Everything was set up above. */
2698 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2700 i3_subst_into_i2
= 1;
2701 goto validate_replacement
;
2705 /* If I2 is setting a pseudo to a constant and I3 is setting some
2706 sub-part of it to another constant, merge them by making a new
2709 && (temp
= single_set (i2
)) != 0
2710 && (CONST_INT_P (SET_SRC (temp
))
2711 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2712 && GET_CODE (PATTERN (i3
)) == SET
2713 && (CONST_INT_P (SET_SRC (PATTERN (i3
)))
2714 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2715 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2717 rtx dest
= SET_DEST (PATTERN (i3
));
2721 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2723 if (CONST_INT_P (XEXP (dest
, 1))
2724 && CONST_INT_P (XEXP (dest
, 2)))
2726 width
= INTVAL (XEXP (dest
, 1));
2727 offset
= INTVAL (XEXP (dest
, 2));
2728 dest
= XEXP (dest
, 0);
2729 if (BITS_BIG_ENDIAN
)
2730 offset
= GET_MODE_BITSIZE (GET_MODE (dest
)) - width
- offset
;
2735 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2736 dest
= XEXP (dest
, 0);
2737 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
2743 /* If this is the low part, we're done. */
2744 if (subreg_lowpart_p (dest
))
2746 /* Handle the case where inner is twice the size of outer. */
2747 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2748 == 2 * GET_MODE_BITSIZE (GET_MODE (dest
)))
2749 offset
+= GET_MODE_BITSIZE (GET_MODE (dest
));
2750 /* Otherwise give up for now. */
2756 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2757 <= HOST_BITS_PER_DOUBLE_INT
))
2760 rtx inner
= SET_SRC (PATTERN (i3
));
2761 rtx outer
= SET_SRC (temp
);
2763 o
= rtx_to_double_int (outer
);
2764 i
= rtx_to_double_int (inner
);
2766 m
= double_int_mask (width
);
2767 i
= double_int_and (i
, m
);
2768 m
= double_int_lshift (m
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2769 i
= double_int_lshift (i
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2770 o
= double_int_ior (double_int_and_not (o
, m
), i
);
2774 subst_low_luid
= DF_INSN_LUID (i2
);
2775 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2776 i2dest
= SET_DEST (temp
);
2777 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2779 /* Replace the source in I2 with the new constant and make the
2780 resulting insn the new pattern for I3. Then skip to where we
2781 validate the pattern. Everything was set up above. */
2782 SUBST (SET_SRC (temp
),
2783 immed_double_int_const (o
, GET_MODE (SET_DEST (temp
))));
2785 newpat
= PATTERN (i2
);
2787 /* The dest of I3 has been replaced with the dest of I2. */
2788 changed_i3_dest
= 1;
2789 goto validate_replacement
;
2794 /* If we have no I1 and I2 looks like:
2795 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2797 make up a dummy I1 that is
2800 (set (reg:CC X) (compare:CC Y (const_int 0)))
2802 (We can ignore any trailing CLOBBERs.)
2804 This undoes a previous combination and allows us to match a branch-and-
2807 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2808 && XVECLEN (PATTERN (i2
), 0) >= 2
2809 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2810 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2812 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2813 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2814 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2815 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2816 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2817 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2819 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2820 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2825 /* We make I1 with the same INSN_UID as I2. This gives it
2826 the same DF_INSN_LUID for value tracking. Our fake I1 will
2827 never appear in the insn stream so giving it the same INSN_UID
2828 as I2 will not cause a problem. */
2830 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2831 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2832 INSN_LOCATOR (i2
), -1, NULL_RTX
);
2834 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2835 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2836 SET_DEST (PATTERN (i1
)));
2841 /* Verify that I2 and I1 are valid for combining. */
2842 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2843 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2845 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2852 /* Record whether I2DEST is used in I2SRC and similarly for the other
2853 cases. Knowing this will help in register status updating below. */
2854 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2855 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2856 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2857 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2858 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2859 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2860 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2861 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2862 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2864 /* For the earlier insns, determine which of the subsequent ones they
2866 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2867 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2868 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2869 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2870 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2872 /* Ensure that I3's pattern can be the destination of combines. */
2873 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2874 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2875 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2876 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2883 /* See if any of the insns is a MULT operation. Unless one is, we will
2884 reject a combination that is, since it must be slower. Be conservative
2886 if (GET_CODE (i2src
) == MULT
2887 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2888 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2889 || (GET_CODE (PATTERN (i3
)) == SET
2890 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2893 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2894 We used to do this EXCEPT in one case: I3 has a post-inc in an
2895 output operand. However, that exception can give rise to insns like
2897 which is a famous insn on the PDP-11 where the value of r3 used as the
2898 source was model-dependent. Avoid this sort of thing. */
2901 if (!(GET_CODE (PATTERN (i3
)) == SET
2902 && REG_P (SET_SRC (PATTERN (i3
)))
2903 && MEM_P (SET_DEST (PATTERN (i3
)))
2904 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2905 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2906 /* It's not the exception. */
2909 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2910 if (REG_NOTE_KIND (link
) == REG_INC
2911 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2913 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2920 /* See if the SETs in I1 or I2 need to be kept around in the merged
2921 instruction: whenever the value set there is still needed past I3.
2922 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2924 For the SET in I1, we have two cases: If I1 and I2 independently
2925 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2926 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2927 in I1 needs to be kept around unless I1DEST dies or is set in either
2928 I2 or I3. The same consideration applies to I0. */
2930 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2933 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2934 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2939 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2940 || (i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
2941 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)));
2945 /* We are about to copy insns for the case where they need to be kept
2946 around. Check that they can be copied in the merged instruction. */
2948 if (targetm
.cannot_copy_insn_p
2949 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2950 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2951 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2957 /* If the set in I2 needs to be kept around, we must make a copy of
2958 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2959 PATTERN (I2), we are only substituting for the original I1DEST, not into
2960 an already-substituted copy. This also prevents making self-referential
2961 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2966 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2967 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2969 i2pat
= copy_rtx (PATTERN (i2
));
2974 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2975 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2977 i1pat
= copy_rtx (PATTERN (i1
));
2982 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2983 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2985 i0pat
= copy_rtx (PATTERN (i0
));
2990 /* Substitute in the latest insn for the regs set by the earlier ones. */
2992 maxreg
= max_reg_num ();
2997 /* Many machines that don't use CC0 have insns that can both perform an
2998 arithmetic operation and set the condition code. These operations will
2999 be represented as a PARALLEL with the first element of the vector
3000 being a COMPARE of an arithmetic operation with the constant zero.
3001 The second element of the vector will set some pseudo to the result
3002 of the same arithmetic operation. If we simplify the COMPARE, we won't
3003 match such a pattern and so will generate an extra insn. Here we test
3004 for this case, where both the comparison and the operation result are
3005 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3006 I2SRC. Later we will make the PARALLEL that contains I2. */
3008 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3009 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3010 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
3011 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3013 #ifdef SELECT_CC_MODE
3015 enum machine_mode compare_mode
;
3018 newpat
= PATTERN (i3
);
3019 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
3023 #ifdef SELECT_CC_MODE
3024 /* See if a COMPARE with the operand we substituted in should be done
3025 with the mode that is currently being used. If not, do the same
3026 processing we do in `subst' for a SET; namely, if the destination
3027 is used only once, try to replace it with a register of the proper
3028 mode and also replace the COMPARE. */
3029 if (undobuf
.other_insn
== 0
3030 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
3031 &undobuf
.other_insn
))
3032 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
3034 != GET_MODE (SET_DEST (newpat
))))
3036 if (can_change_dest_mode (SET_DEST (newpat
), added_sets_2
,
3039 unsigned int regno
= REGNO (SET_DEST (newpat
));
3042 if (regno
< FIRST_PSEUDO_REGISTER
)
3043 new_dest
= gen_rtx_REG (compare_mode
, regno
);
3046 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3047 new_dest
= regno_reg_rtx
[regno
];
3050 SUBST (SET_DEST (newpat
), new_dest
);
3051 SUBST (XEXP (*cc_use
, 0), new_dest
);
3052 SUBST (SET_SRC (newpat
),
3053 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
3056 undobuf
.other_insn
= 0;
3063 /* It is possible that the source of I2 or I1 may be performing
3064 an unneeded operation, such as a ZERO_EXTEND of something
3065 that is known to have the high part zero. Handle that case
3066 by letting subst look at the innermost one of them.
3068 Another way to do this would be to have a function that tries
3069 to simplify a single insn instead of merging two or more
3070 insns. We don't do this because of the potential of infinite
3071 loops and because of the potential extra memory required.
3072 However, doing it the way we are is a bit of a kludge and
3073 doesn't catch all cases.
3075 But only do this if -fexpensive-optimizations since it slows
3076 things down and doesn't usually win.
3078 This is not done in the COMPARE case above because the
3079 unmodified I2PAT is used in the PARALLEL and so a pattern
3080 with a modified I2SRC would not match. */
3082 if (flag_expensive_optimizations
)
3084 /* Pass pc_rtx so no substitutions are done, just
3088 subst_low_luid
= DF_INSN_LUID (i1
);
3089 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
3093 subst_low_luid
= DF_INSN_LUID (i2
);
3094 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
3098 n_occurrences
= 0; /* `subst' counts here */
3099 subst_low_luid
= DF_INSN_LUID (i2
);
3101 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3102 copy of I2SRC each time we substitute it, in order to avoid creating
3103 self-referential RTL when we will be substituting I1SRC for I1DEST
3104 later. Likewise if I0 feeds into I2, either directly or indirectly
3105 through I1, and I0DEST is in I0SRC. */
3106 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
3107 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3108 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3109 && i0dest_in_i0src
));
3112 /* Record whether I2's body now appears within I3's body. */
3113 i2_is_used
= n_occurrences
;
3116 /* If we already got a failure, don't try to do more. Otherwise, try to
3117 substitute I1 if we have it. */
3119 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3121 /* Check that an autoincrement side-effect on I1 has not been lost.
3122 This happens if I1DEST is mentioned in I2 and dies there, and
3123 has disappeared from the new pattern. */
3124 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3126 && dead_or_set_p (i2
, i1dest
)
3127 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3128 /* Before we can do this substitution, we must redo the test done
3129 above (see detailed comments there) that ensures I1DEST isn't
3130 mentioned in any SETs in NEWPAT that are field assignments. */
3131 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3139 subst_low_luid
= DF_INSN_LUID (i1
);
3141 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3142 copy of I1SRC each time we substitute it, in order to avoid creating
3143 self-referential RTL when we will be substituting I0SRC for I0DEST
3145 newpat
= subst (newpat
, i1dest
, i1src
, 0,
3146 i0_feeds_i1_n
&& i0dest_in_i0src
);
3149 /* Record whether I1's body now appears within I3's body. */
3150 i1_is_used
= n_occurrences
;
3153 /* Likewise for I0 if we have it. */
3155 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3157 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3158 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3159 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3160 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3161 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3168 /* If the following substitution will modify I1SRC, make a copy of it
3169 for the case where it is substituted for I1DEST in I2PAT later. */
3170 if (i0_feeds_i1_n
&& added_sets_2
&& i1_feeds_i2_n
)
3171 i1src_copy
= copy_rtx (i1src
);
3174 subst_low_luid
= DF_INSN_LUID (i0
);
3175 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0);
3179 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3180 to count all the ways that I2SRC and I1SRC can be used. */
3181 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3182 && i2_is_used
+ added_sets_2
> 1)
3183 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3184 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3186 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3187 && (n_occurrences
+ added_sets_0
3188 + (added_sets_1
&& i0_feeds_i1_n
)
3189 + (added_sets_2
&& i0_feeds_i2_n
)
3191 /* Fail if we tried to make a new register. */
3192 || max_reg_num () != maxreg
3193 /* Fail if we couldn't do something and have a CLOBBER. */
3194 || GET_CODE (newpat
) == CLOBBER
3195 /* Fail if this new pattern is a MULT and we didn't have one before
3196 at the outer level. */
3197 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3204 /* If the actions of the earlier insns must be kept
3205 in addition to substituting them into the latest one,
3206 we must make a new PARALLEL for the latest insn
3207 to hold additional the SETs. */
3209 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3211 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3214 if (GET_CODE (newpat
) == PARALLEL
)
3216 rtvec old
= XVEC (newpat
, 0);
3217 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3218 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3219 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3220 sizeof (old
->elem
[0]) * old
->num_elem
);
3225 total_sets
= 1 + extra_sets
;
3226 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3227 XVECEXP (newpat
, 0, 0) = old
;
3231 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3237 t
= subst (t
, i0dest
, i0src
, 0, 0);
3239 XVECEXP (newpat
, 0, --total_sets
) = t
;
3245 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0,
3246 i0_feeds_i1_n
&& i0dest_in_i0src
);
3247 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3248 t
= subst (t
, i0dest
, i0src
, 0, 0);
3250 XVECEXP (newpat
, 0, --total_sets
) = t
;
3254 validate_replacement
:
3256 /* Note which hard regs this insn has as inputs. */
3257 mark_used_regs_combine (newpat
);
3259 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3260 consider splitting this pattern, we might need these clobbers. */
3261 if (i1
&& GET_CODE (newpat
) == PARALLEL
3262 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3264 int len
= XVECLEN (newpat
, 0);
3266 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3267 for (i
= 0; i
< len
; i
++)
3268 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3271 /* Is the result of combination a valid instruction? */
3272 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3274 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3275 the second SET's destination is a register that is unused and isn't
3276 marked as an instruction that might trap in an EH region. In that case,
3277 we just need the first SET. This can occur when simplifying a divmod
3278 insn. We *must* test for this case here because the code below that
3279 splits two independent SETs doesn't handle this case correctly when it
3280 updates the register status.
3282 It's pointless doing this if we originally had two sets, one from
3283 i3, and one from i2. Combining then splitting the parallel results
3284 in the original i2 again plus an invalid insn (which we delete).
3285 The net effect is only to move instructions around, which makes
3286 debug info less accurate.
3288 Also check the case where the first SET's destination is unused.
3289 That would not cause incorrect code, but does cause an unneeded
3292 if (insn_code_number
< 0
3293 && !(added_sets_2
&& i1
== 0)
3294 && GET_CODE (newpat
) == PARALLEL
3295 && XVECLEN (newpat
, 0) == 2
3296 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3297 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3298 && asm_noperands (newpat
) < 0)
3300 rtx set0
= XVECEXP (newpat
, 0, 0);
3301 rtx set1
= XVECEXP (newpat
, 0, 1);
3303 if (((REG_P (SET_DEST (set1
))
3304 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3305 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3306 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3307 && insn_nothrow_p (i3
)
3308 && !side_effects_p (SET_SRC (set1
)))
3311 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3314 else if (((REG_P (SET_DEST (set0
))
3315 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3316 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3317 && find_reg_note (i3
, REG_UNUSED
,
3318 SUBREG_REG (SET_DEST (set0
)))))
3319 && insn_nothrow_p (i3
)
3320 && !side_effects_p (SET_SRC (set0
)))
3323 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3325 if (insn_code_number
>= 0)
3326 changed_i3_dest
= 1;
3330 /* If we were combining three insns and the result is a simple SET
3331 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3332 insns. There are two ways to do this. It can be split using a
3333 machine-specific method (like when you have an addition of a large
3334 constant) or by combine in the function find_split_point. */
3336 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3337 && asm_noperands (newpat
) < 0)
3339 rtx parallel
, m_split
, *split
;
3341 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3342 use I2DEST as a scratch register will help. In the latter case,
3343 convert I2DEST to the mode of the source of NEWPAT if we can. */
3345 m_split
= combine_split_insns (newpat
, i3
);
3347 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3348 inputs of NEWPAT. */
3350 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3351 possible to try that as a scratch reg. This would require adding
3352 more code to make it work though. */
3354 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3356 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3358 /* First try to split using the original register as a
3359 scratch register. */
3360 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3361 gen_rtvec (2, newpat
,
3362 gen_rtx_CLOBBER (VOIDmode
,
3364 m_split
= combine_split_insns (parallel
, i3
);
3366 /* If that didn't work, try changing the mode of I2DEST if
3369 && new_mode
!= GET_MODE (i2dest
)
3370 && new_mode
!= VOIDmode
3371 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3373 enum machine_mode old_mode
= GET_MODE (i2dest
);
3376 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3377 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3380 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3381 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3384 parallel
= (gen_rtx_PARALLEL
3386 gen_rtvec (2, newpat
,
3387 gen_rtx_CLOBBER (VOIDmode
,
3389 m_split
= combine_split_insns (parallel
, i3
);
3392 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3396 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3397 buf
= undobuf
.undos
;
3398 undobuf
.undos
= buf
->next
;
3399 buf
->next
= undobuf
.frees
;
3400 undobuf
.frees
= buf
;
3404 i2scratch
= m_split
!= 0;
3407 /* If recog_for_combine has discarded clobbers, try to use them
3408 again for the split. */
3409 if (m_split
== 0 && newpat_vec_with_clobbers
)
3411 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3412 m_split
= combine_split_insns (parallel
, i3
);
3415 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3417 m_split
= PATTERN (m_split
);
3418 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3419 if (insn_code_number
>= 0)
3422 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3423 && (next_real_insn (i2
) == i3
3424 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3427 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3428 newi2pat
= PATTERN (m_split
);
3430 i3set
= single_set (NEXT_INSN (m_split
));
3431 i2set
= single_set (m_split
);
3433 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3435 /* If I2 or I3 has multiple SETs, we won't know how to track
3436 register status, so don't use these insns. If I2's destination
3437 is used between I2 and I3, we also can't use these insns. */
3439 if (i2_code_number
>= 0 && i2set
&& i3set
3440 && (next_real_insn (i2
) == i3
3441 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3442 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3444 if (insn_code_number
>= 0)
3447 /* It is possible that both insns now set the destination of I3.
3448 If so, we must show an extra use of it. */
3450 if (insn_code_number
>= 0)
3452 rtx new_i3_dest
= SET_DEST (i3set
);
3453 rtx new_i2_dest
= SET_DEST (i2set
);
3455 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3456 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3457 || GET_CODE (new_i3_dest
) == SUBREG
)
3458 new_i3_dest
= XEXP (new_i3_dest
, 0);
3460 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3461 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3462 || GET_CODE (new_i2_dest
) == SUBREG
)
3463 new_i2_dest
= XEXP (new_i2_dest
, 0);
3465 if (REG_P (new_i3_dest
)
3466 && REG_P (new_i2_dest
)
3467 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3468 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3472 /* If we can split it and use I2DEST, go ahead and see if that
3473 helps things be recognized. Verify that none of the registers
3474 are set between I2 and I3. */
3475 if (insn_code_number
< 0
3476 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3480 /* We need I2DEST in the proper mode. If it is a hard register
3481 or the only use of a pseudo, we can change its mode.
3482 Make sure we don't change a hard register to have a mode that
3483 isn't valid for it, or change the number of registers. */
3484 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3485 || GET_MODE (*split
) == VOIDmode
3486 || can_change_dest_mode (i2dest
, added_sets_2
,
3488 && (next_real_insn (i2
) == i3
3489 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3490 /* We can't overwrite I2DEST if its value is still used by
3492 && ! reg_referenced_p (i2dest
, newpat
))
3494 rtx newdest
= i2dest
;
3495 enum rtx_code split_code
= GET_CODE (*split
);
3496 enum machine_mode split_mode
= GET_MODE (*split
);
3497 bool subst_done
= false;
3498 newi2pat
= NULL_RTX
;
3502 /* *SPLIT may be part of I2SRC, so make sure we have the
3503 original expression around for later debug processing.
3504 We should not need I2SRC any more in other cases. */
3505 if (MAY_HAVE_DEBUG_INSNS
)
3506 i2src
= copy_rtx (i2src
);
3510 /* Get NEWDEST as a register in the proper mode. We have already
3511 validated that we can do this. */
3512 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3514 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3515 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3518 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3519 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3523 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3524 an ASHIFT. This can occur if it was inside a PLUS and hence
3525 appeared to be a memory address. This is a kludge. */
3526 if (split_code
== MULT
3527 && CONST_INT_P (XEXP (*split
, 1))
3528 && INTVAL (XEXP (*split
, 1)) > 0
3529 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3531 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3532 XEXP (*split
, 0), GEN_INT (i
)));
3533 /* Update split_code because we may not have a multiply
3535 split_code
= GET_CODE (*split
);
3538 #ifdef INSN_SCHEDULING
3539 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3540 be written as a ZERO_EXTEND. */
3541 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3543 #ifdef LOAD_EXTEND_OP
3544 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3545 what it really is. */
3546 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3548 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3549 SUBREG_REG (*split
)));
3552 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3553 SUBREG_REG (*split
)));
3557 /* Attempt to split binary operators using arithmetic identities. */
3558 if (BINARY_P (SET_SRC (newpat
))
3559 && split_mode
== GET_MODE (SET_SRC (newpat
))
3560 && ! side_effects_p (SET_SRC (newpat
)))
3562 rtx setsrc
= SET_SRC (newpat
);
3563 enum machine_mode mode
= GET_MODE (setsrc
);
3564 enum rtx_code code
= GET_CODE (setsrc
);
3565 rtx src_op0
= XEXP (setsrc
, 0);
3566 rtx src_op1
= XEXP (setsrc
, 1);
3568 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3569 if (rtx_equal_p (src_op0
, src_op1
))
3571 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3572 SUBST (XEXP (setsrc
, 0), newdest
);
3573 SUBST (XEXP (setsrc
, 1), newdest
);
3576 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3577 else if ((code
== PLUS
|| code
== MULT
)
3578 && GET_CODE (src_op0
) == code
3579 && GET_CODE (XEXP (src_op0
, 0)) == code
3580 && (INTEGRAL_MODE_P (mode
)
3581 || (FLOAT_MODE_P (mode
)
3582 && flag_unsafe_math_optimizations
)))
3584 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3585 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3586 rtx r
= XEXP (src_op0
, 1);
3589 /* Split both "((X op Y) op X) op Y" and
3590 "((X op Y) op Y) op X" as "T op T" where T is
3592 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3593 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3595 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3597 SUBST (XEXP (setsrc
, 0), newdest
);
3598 SUBST (XEXP (setsrc
, 1), newdest
);
3601 /* Split "((X op X) op Y) op Y)" as "T op T" where
3603 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3605 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3606 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3607 SUBST (XEXP (setsrc
, 0), newdest
);
3608 SUBST (XEXP (setsrc
, 1), newdest
);
3616 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3617 SUBST (*split
, newdest
);
3620 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3622 /* recog_for_combine might have added CLOBBERs to newi2pat.
3623 Make sure NEWPAT does not depend on the clobbered regs. */
3624 if (GET_CODE (newi2pat
) == PARALLEL
)
3625 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3626 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3628 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3629 if (reg_overlap_mentioned_p (reg
, newpat
))
3636 /* If the split point was a MULT and we didn't have one before,
3637 don't use one now. */
3638 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3639 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3643 /* Check for a case where we loaded from memory in a narrow mode and
3644 then sign extended it, but we need both registers. In that case,
3645 we have a PARALLEL with both loads from the same memory location.
3646 We can split this into a load from memory followed by a register-register
3647 copy. This saves at least one insn, more if register allocation can
3650 We cannot do this if the destination of the first assignment is a
3651 condition code register or cc0. We eliminate this case by making sure
3652 the SET_DEST and SET_SRC have the same mode.
3654 We cannot do this if the destination of the second assignment is
3655 a register that we have already assumed is zero-extended. Similarly
3656 for a SUBREG of such a register. */
3658 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3659 && GET_CODE (newpat
) == PARALLEL
3660 && XVECLEN (newpat
, 0) == 2
3661 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3662 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3663 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3664 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3665 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3666 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3667 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3668 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3670 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3671 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3672 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3674 && VEC_index (reg_stat_type
, reg_stat
,
3675 REGNO (temp
))->nonzero_bits
!= 0
3676 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3677 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3678 && (VEC_index (reg_stat_type
, reg_stat
,
3679 REGNO (temp
))->nonzero_bits
3680 != GET_MODE_MASK (word_mode
))))
3681 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3682 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3684 && VEC_index (reg_stat_type
, reg_stat
,
3685 REGNO (temp
))->nonzero_bits
!= 0
3686 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3687 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3688 && (VEC_index (reg_stat_type
, reg_stat
,
3689 REGNO (temp
))->nonzero_bits
3690 != GET_MODE_MASK (word_mode
)))))
3691 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3692 SET_SRC (XVECEXP (newpat
, 0, 1)))
3693 && ! find_reg_note (i3
, REG_UNUSED
,
3694 SET_DEST (XVECEXP (newpat
, 0, 0))))
3698 newi2pat
= XVECEXP (newpat
, 0, 0);
3699 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3700 newpat
= XVECEXP (newpat
, 0, 1);
3701 SUBST (SET_SRC (newpat
),
3702 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3703 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3705 if (i2_code_number
>= 0)
3706 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3708 if (insn_code_number
>= 0)
3712 /* Similarly, check for a case where we have a PARALLEL of two independent
3713 SETs but we started with three insns. In this case, we can do the sets
3714 as two separate insns. This case occurs when some SET allows two
3715 other insns to combine, but the destination of that SET is still live. */
3717 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3718 && GET_CODE (newpat
) == PARALLEL
3719 && XVECLEN (newpat
, 0) == 2
3720 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3721 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3722 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3723 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3724 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3725 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3726 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3727 XVECEXP (newpat
, 0, 0))
3728 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3729 XVECEXP (newpat
, 0, 1))
3730 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3731 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3733 /* Normally, it doesn't matter which of the two is done first,
3734 but the one that references cc0 can't be the second, and
3735 one which uses any regs/memory set in between i2 and i3 can't
3737 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3740 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3744 newi2pat
= XVECEXP (newpat
, 0, 1);
3745 newpat
= XVECEXP (newpat
, 0, 0);
3747 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 0)),
3750 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1))
3754 newi2pat
= XVECEXP (newpat
, 0, 0);
3755 newpat
= XVECEXP (newpat
, 0, 1);
3763 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3765 if (i2_code_number
>= 0)
3767 /* recog_for_combine might have added CLOBBERs to newi2pat.
3768 Make sure NEWPAT does not depend on the clobbered regs. */
3769 if (GET_CODE (newi2pat
) == PARALLEL
)
3771 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3772 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3774 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3775 if (reg_overlap_mentioned_p (reg
, newpat
))
3783 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3787 /* If it still isn't recognized, fail and change things back the way they
3789 if ((insn_code_number
< 0
3790 /* Is the result a reasonable ASM_OPERANDS? */
3791 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3797 /* If we had to change another insn, make sure it is valid also. */
3798 if (undobuf
.other_insn
)
3800 CLEAR_HARD_REG_SET (newpat_used_regs
);
3802 other_pat
= PATTERN (undobuf
.other_insn
);
3803 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3806 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3814 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3815 they are adjacent to each other or not. */
3817 rtx p
= prev_nonnote_insn (i3
);
3818 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3819 && sets_cc0_p (newi2pat
))
3827 /* Only allow this combination if insn_rtx_costs reports that the
3828 replacement instructions are cheaper than the originals. */
3829 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3835 if (MAY_HAVE_DEBUG_INSNS
)
3839 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3840 if (undo
->kind
== UNDO_MODE
)
3842 rtx reg
= *undo
->where
.r
;
3843 enum machine_mode new_mode
= GET_MODE (reg
);
3844 enum machine_mode old_mode
= undo
->old_contents
.m
;
3846 /* Temporarily revert mode back. */
3847 adjust_reg_mode (reg
, old_mode
);
3849 if (reg
== i2dest
&& i2scratch
)
3851 /* If we used i2dest as a scratch register with a
3852 different mode, substitute it for the original
3853 i2src while its original mode is temporarily
3854 restored, and then clear i2scratch so that we don't
3855 do it again later. */
3856 propagate_for_debug (i2
, i3
, reg
, i2src
);
3858 /* Put back the new mode. */
3859 adjust_reg_mode (reg
, new_mode
);
3863 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3874 last
= undobuf
.other_insn
;
3878 /* We're dealing with a reg that changed mode but not
3879 meaning, so we want to turn it into a subreg for
3880 the new mode. However, because of REG sharing and
3881 because its mode had already changed, we have to do
3882 it in two steps. First, replace any debug uses of
3883 reg, with its original mode temporarily restored,
3884 with this copy we have created; then, replace the
3885 copy with the SUBREG of the original shared reg,
3886 once again changed to the new mode. */
3887 propagate_for_debug (first
, last
, reg
, tempreg
);
3888 adjust_reg_mode (reg
, new_mode
);
3889 propagate_for_debug (first
, last
, tempreg
,
3890 lowpart_subreg (old_mode
, reg
, new_mode
));
3895 /* If we will be able to accept this, we have made a
3896 change to the destination of I3. This requires us to
3897 do a few adjustments. */
3899 if (changed_i3_dest
)
3901 PATTERN (i3
) = newpat
;
3902 adjust_for_new_dest (i3
);
3905 /* We now know that we can do this combination. Merge the insns and
3906 update the status of registers and LOG_LINKS. */
3908 if (undobuf
.other_insn
)
3912 PATTERN (undobuf
.other_insn
) = other_pat
;
3914 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3915 are still valid. Then add any non-duplicate notes added by
3916 recog_for_combine. */
3917 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3919 next
= XEXP (note
, 1);
3921 if (REG_NOTE_KIND (note
) == REG_UNUSED
3922 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3923 remove_note (undobuf
.other_insn
, note
);
3926 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3927 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3937 /* I3 now uses what used to be its destination and which is now
3938 I2's destination. This requires us to do a few adjustments. */
3939 PATTERN (i3
) = newpat
;
3940 adjust_for_new_dest (i3
);
3942 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3945 However, some later insn might be using I2's dest and have
3946 a LOG_LINK pointing at I3. We must remove this link.
3947 The simplest way to remove the link is to point it at I1,
3948 which we know will be a NOTE. */
3950 /* newi2pat is usually a SET here; however, recog_for_combine might
3951 have added some clobbers. */
3952 if (GET_CODE (newi2pat
) == PARALLEL
)
3953 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3955 ni2dest
= SET_DEST (newi2pat
);
3957 for (insn
= NEXT_INSN (i3
);
3958 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3959 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3960 insn
= NEXT_INSN (insn
))
3962 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3964 for (link
= LOG_LINKS (insn
); link
;
3965 link
= XEXP (link
, 1))
3966 if (XEXP (link
, 0) == i3
)
3967 XEXP (link
, 0) = i1
;
3975 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3976 rtx i3links
, i2links
, i1links
= 0, i0links
= 0;
3980 /* Compute which registers we expect to eliminate. newi2pat may be setting
3981 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3982 same as i3dest, in which case newi2pat may be setting i1dest. */
3983 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3984 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3987 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3988 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3991 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3992 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3996 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3998 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3999 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4001 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4003 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4005 /* Ensure that we do not have something that should not be shared but
4006 occurs multiple times in the new insns. Check this by first
4007 resetting all the `used' flags and then copying anything is shared. */
4009 reset_used_flags (i3notes
);
4010 reset_used_flags (i2notes
);
4011 reset_used_flags (i1notes
);
4012 reset_used_flags (i0notes
);
4013 reset_used_flags (newpat
);
4014 reset_used_flags (newi2pat
);
4015 if (undobuf
.other_insn
)
4016 reset_used_flags (PATTERN (undobuf
.other_insn
));
4018 i3notes
= copy_rtx_if_shared (i3notes
);
4019 i2notes
= copy_rtx_if_shared (i2notes
);
4020 i1notes
= copy_rtx_if_shared (i1notes
);
4021 i0notes
= copy_rtx_if_shared (i0notes
);
4022 newpat
= copy_rtx_if_shared (newpat
);
4023 newi2pat
= copy_rtx_if_shared (newi2pat
);
4024 if (undobuf
.other_insn
)
4025 reset_used_flags (PATTERN (undobuf
.other_insn
));
4027 INSN_CODE (i3
) = insn_code_number
;
4028 PATTERN (i3
) = newpat
;
4030 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4032 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4034 reset_used_flags (call_usage
);
4035 call_usage
= copy_rtx (call_usage
);
4039 /* I2SRC must still be meaningful at this point. Some splitting
4040 operations can invalidate I2SRC, but those operations do not
4043 replace_rtx (call_usage
, i2dest
, i2src
);
4047 replace_rtx (call_usage
, i1dest
, i1src
);
4049 replace_rtx (call_usage
, i0dest
, i0src
);
4051 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4054 if (undobuf
.other_insn
)
4055 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4057 /* We had one special case above where I2 had more than one set and
4058 we replaced a destination of one of those sets with the destination
4059 of I3. In that case, we have to update LOG_LINKS of insns later
4060 in this basic block. Note that this (expensive) case is rare.
4062 Also, in this case, we must pretend that all REG_NOTEs for I2
4063 actually came from I3, so that REG_UNUSED notes from I2 will be
4064 properly handled. */
4066 if (i3_subst_into_i2
)
4068 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4069 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4070 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4071 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4072 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4073 && ! find_reg_note (i2
, REG_UNUSED
,
4074 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4075 for (temp
= NEXT_INSN (i2
);
4076 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4077 || BB_HEAD (this_basic_block
) != temp
);
4078 temp
= NEXT_INSN (temp
))
4079 if (temp
!= i3
&& INSN_P (temp
))
4080 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
4081 if (XEXP (link
, 0) == i2
)
4082 XEXP (link
, 0) = i3
;
4087 while (XEXP (link
, 1))
4088 link
= XEXP (link
, 1);
4089 XEXP (link
, 1) = i2notes
;
4103 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4104 propagate_for_debug (i2
, i3
, i2dest
, i2src
);
4105 INSN_CODE (i2
) = i2_code_number
;
4106 PATTERN (i2
) = newi2pat
;
4110 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4111 propagate_for_debug (i2
, i3
, i2dest
, i2src
);
4112 SET_INSN_DELETED (i2
);
4119 if (MAY_HAVE_DEBUG_INSNS
)
4120 propagate_for_debug (i1
, i3
, i1dest
, i1src
);
4121 SET_INSN_DELETED (i1
);
4128 if (MAY_HAVE_DEBUG_INSNS
)
4129 propagate_for_debug (i0
, i3
, i0dest
, i0src
);
4130 SET_INSN_DELETED (i0
);
4133 /* Get death notes for everything that is now used in either I3 or
4134 I2 and used to die in a previous insn. If we built two new
4135 patterns, move from I1 to I2 then I2 to I3 so that we get the
4136 proper movement on registers that I2 modifies. */
4139 from_luid
= DF_INSN_LUID (i0
);
4141 from_luid
= DF_INSN_LUID (i1
);
4143 from_luid
= DF_INSN_LUID (i2
);
4145 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4146 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4148 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4150 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4151 elim_i2
, elim_i1
, elim_i0
);
4153 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4154 elim_i2
, elim_i1
, elim_i0
);
4156 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4157 elim_i2
, elim_i1
, elim_i0
);
4159 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4160 elim_i2
, elim_i1
, elim_i0
);
4162 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4163 elim_i2
, elim_i1
, elim_i0
);
4165 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4166 know these are REG_UNUSED and want them to go to the desired insn,
4167 so we always pass it as i3. */
4169 if (newi2pat
&& new_i2_notes
)
4170 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4174 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4177 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4178 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4179 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4180 in that case, it might delete I2. Similarly for I2 and I1.
4181 Show an additional death due to the REG_DEAD note we make here. If
4182 we discard it in distribute_notes, we will decrement it again. */
4186 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4187 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4189 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
, elim_i0
);
4191 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4193 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4194 elim_i2
, elim_i1
, elim_i0
);
4197 if (i2dest_in_i2src
)
4199 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4200 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4201 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4202 NULL_RTX
, NULL_RTX
);
4204 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4205 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4208 if (i1dest_in_i1src
)
4210 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4211 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4212 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4213 NULL_RTX
, NULL_RTX
);
4215 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4216 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4219 if (i0dest_in_i0src
)
4221 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4222 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4223 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4224 NULL_RTX
, NULL_RTX
);
4226 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4227 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4230 distribute_links (i3links
);
4231 distribute_links (i2links
);
4232 distribute_links (i1links
);
4233 distribute_links (i0links
);
4238 rtx i2_insn
= 0, i2_val
= 0, set
;
4240 /* The insn that used to set this register doesn't exist, and
4241 this life of the register may not exist either. See if one of
4242 I3's links points to an insn that sets I2DEST. If it does,
4243 that is now the last known value for I2DEST. If we don't update
4244 this and I2 set the register to a value that depended on its old
4245 contents, we will get confused. If this insn is used, thing
4246 will be set correctly in combine_instructions. */
4248 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4249 if ((set
= single_set (XEXP (link
, 0))) != 0
4250 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4251 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
4253 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4255 /* If the reg formerly set in I2 died only once and that was in I3,
4256 zero its use count so it won't make `reload' do any work. */
4258 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4259 && ! i2dest_in_i2src
)
4261 regno
= REGNO (i2dest
);
4262 INC_REG_N_SETS (regno
, -1);
4266 if (i1
&& REG_P (i1dest
))
4269 rtx i1_insn
= 0, i1_val
= 0, set
;
4271 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4272 if ((set
= single_set (XEXP (link
, 0))) != 0
4273 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4274 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
4276 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4278 regno
= REGNO (i1dest
);
4279 if (! added_sets_1
&& ! i1dest_in_i1src
)
4280 INC_REG_N_SETS (regno
, -1);
4283 if (i0
&& REG_P (i0dest
))
4286 rtx i0_insn
= 0, i0_val
= 0, set
;
4288 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4289 if ((set
= single_set (XEXP (link
, 0))) != 0
4290 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4291 i0_insn
= XEXP (link
, 0), i0_val
= SET_SRC (set
);
4293 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4295 regno
= REGNO (i0dest
);
4296 if (! added_sets_0
&& ! i0dest_in_i0src
)
4297 INC_REG_N_SETS (regno
, -1);
4300 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4301 been made to this insn. The order of
4302 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4303 can affect nonzero_bits of newpat */
4305 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4306 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4309 if (undobuf
.other_insn
!= NULL_RTX
)
4313 fprintf (dump_file
, "modifying other_insn ");
4314 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4316 df_insn_rescan (undobuf
.other_insn
);
4319 if (i0
&& !(NOTE_P(i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4323 fprintf (dump_file
, "modifying insn i1 ");
4324 dump_insn_slim (dump_file
, i0
);
4326 df_insn_rescan (i0
);
4329 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4333 fprintf (dump_file
, "modifying insn i1 ");
4334 dump_insn_slim (dump_file
, i1
);
4336 df_insn_rescan (i1
);
4339 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4343 fprintf (dump_file
, "modifying insn i2 ");
4344 dump_insn_slim (dump_file
, i2
);
4346 df_insn_rescan (i2
);
4349 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4353 fprintf (dump_file
, "modifying insn i3 ");
4354 dump_insn_slim (dump_file
, i3
);
4356 df_insn_rescan (i3
);
4359 /* Set new_direct_jump_p if a new return or simple jump instruction
4360 has been created. Adjust the CFG accordingly. */
4362 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4364 *new_direct_jump_p
= 1;
4365 mark_jump_label (PATTERN (i3
), i3
, 0);
4366 update_cfg_for_uncondjump (i3
);
4369 if (undobuf
.other_insn
!= NULL_RTX
4370 && (returnjump_p (undobuf
.other_insn
)
4371 || any_uncondjump_p (undobuf
.other_insn
)))
4373 *new_direct_jump_p
= 1;
4374 update_cfg_for_uncondjump (undobuf
.other_insn
);
4377 /* A noop might also need cleaning up of CFG, if it comes from the
4378 simplification of a jump. */
4379 if (GET_CODE (newpat
) == SET
4380 && SET_SRC (newpat
) == pc_rtx
4381 && SET_DEST (newpat
) == pc_rtx
)
4383 *new_direct_jump_p
= 1;
4384 update_cfg_for_uncondjump (i3
);
4387 if (undobuf
.other_insn
!= NULL_RTX
4388 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4389 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4390 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4392 *new_direct_jump_p
= 1;
4393 update_cfg_for_uncondjump (undobuf
.other_insn
);
4396 combine_successes
++;
4399 if (added_links_insn
4400 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4401 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4402 return added_links_insn
;
4404 return newi2pat
? i2
: i3
;
4407 /* Undo all the modifications recorded in undobuf. */
4412 struct undo
*undo
, *next
;
4414 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4420 *undo
->where
.r
= undo
->old_contents
.r
;
4423 *undo
->where
.i
= undo
->old_contents
.i
;
4426 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4432 undo
->next
= undobuf
.frees
;
4433 undobuf
.frees
= undo
;
4439 /* We've committed to accepting the changes we made. Move all
4440 of the undos to the free list. */
4445 struct undo
*undo
, *next
;
4447 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4450 undo
->next
= undobuf
.frees
;
4451 undobuf
.frees
= undo
;
4456 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4457 where we have an arithmetic expression and return that point. LOC will
4460 try_combine will call this function to see if an insn can be split into
4464 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4467 enum rtx_code code
= GET_CODE (x
);
4469 unsigned HOST_WIDE_INT len
= 0;
4470 HOST_WIDE_INT pos
= 0;
4472 rtx inner
= NULL_RTX
;
4474 /* First special-case some codes. */
4478 #ifdef INSN_SCHEDULING
4479 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4481 if (MEM_P (SUBREG_REG (x
)))
4484 return find_split_point (&SUBREG_REG (x
), insn
, false);
4488 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4489 using LO_SUM and HIGH. */
4490 if (GET_CODE (XEXP (x
, 0)) == CONST
4491 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4493 enum machine_mode address_mode
4494 = targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (x
));
4497 gen_rtx_LO_SUM (address_mode
,
4498 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4500 return &XEXP (XEXP (x
, 0), 0);
4504 /* If we have a PLUS whose second operand is a constant and the
4505 address is not valid, perhaps will can split it up using
4506 the machine-specific way to split large constants. We use
4507 the first pseudo-reg (one of the virtual regs) as a placeholder;
4508 it will not remain in the result. */
4509 if (GET_CODE (XEXP (x
, 0)) == PLUS
4510 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4511 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4512 MEM_ADDR_SPACE (x
)))
4514 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4515 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4519 /* This should have produced two insns, each of which sets our
4520 placeholder. If the source of the second is a valid address,
4521 we can make put both sources together and make a split point
4525 && NEXT_INSN (seq
) != NULL_RTX
4526 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4527 && NONJUMP_INSN_P (seq
)
4528 && GET_CODE (PATTERN (seq
)) == SET
4529 && SET_DEST (PATTERN (seq
)) == reg
4530 && ! reg_mentioned_p (reg
,
4531 SET_SRC (PATTERN (seq
)))
4532 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4533 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4534 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4535 && memory_address_addr_space_p
4536 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4537 MEM_ADDR_SPACE (x
)))
4539 rtx src1
= SET_SRC (PATTERN (seq
));
4540 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4542 /* Replace the placeholder in SRC2 with SRC1. If we can
4543 find where in SRC2 it was placed, that can become our
4544 split point and we can replace this address with SRC2.
4545 Just try two obvious places. */
4547 src2
= replace_rtx (src2
, reg
, src1
);
4549 if (XEXP (src2
, 0) == src1
)
4550 split
= &XEXP (src2
, 0);
4551 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4552 && XEXP (XEXP (src2
, 0), 0) == src1
)
4553 split
= &XEXP (XEXP (src2
, 0), 0);
4557 SUBST (XEXP (x
, 0), src2
);
4562 /* If that didn't work, perhaps the first operand is complex and
4563 needs to be computed separately, so make a split point there.
4564 This will occur on machines that just support REG + CONST
4565 and have a constant moved through some previous computation. */
4567 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4568 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4569 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4570 return &XEXP (XEXP (x
, 0), 0);
4573 /* If we have a PLUS whose first operand is complex, try computing it
4574 separately by making a split there. */
4575 if (GET_CODE (XEXP (x
, 0)) == PLUS
4576 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4578 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4579 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4580 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4581 return &XEXP (XEXP (x
, 0), 0);
4586 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4587 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4588 we need to put the operand into a register. So split at that
4591 if (SET_DEST (x
) == cc0_rtx
4592 && GET_CODE (SET_SRC (x
)) != COMPARE
4593 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4594 && !OBJECT_P (SET_SRC (x
))
4595 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4596 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4597 return &SET_SRC (x
);
4600 /* See if we can split SET_SRC as it stands. */
4601 split
= find_split_point (&SET_SRC (x
), insn
, true);
4602 if (split
&& split
!= &SET_SRC (x
))
4605 /* See if we can split SET_DEST as it stands. */
4606 split
= find_split_point (&SET_DEST (x
), insn
, false);
4607 if (split
&& split
!= &SET_DEST (x
))
4610 /* See if this is a bitfield assignment with everything constant. If
4611 so, this is an IOR of an AND, so split it into that. */
4612 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4613 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
4614 <= HOST_BITS_PER_WIDE_INT
)
4615 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4616 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4617 && CONST_INT_P (SET_SRC (x
))
4618 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4619 + INTVAL (XEXP (SET_DEST (x
), 2)))
4620 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
4621 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4623 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4624 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4625 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4626 rtx dest
= XEXP (SET_DEST (x
), 0);
4627 enum machine_mode mode
= GET_MODE (dest
);
4628 unsigned HOST_WIDE_INT mask
4629 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4632 if (BITS_BIG_ENDIAN
)
4633 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
4635 or_mask
= gen_int_mode (src
<< pos
, mode
);
4638 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4641 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4643 simplify_gen_binary (IOR
, mode
,
4644 simplify_gen_binary (AND
, mode
,
4649 SUBST (SET_DEST (x
), dest
);
4651 split
= find_split_point (&SET_SRC (x
), insn
, true);
4652 if (split
&& split
!= &SET_SRC (x
))
4656 /* Otherwise, see if this is an operation that we can split into two.
4657 If so, try to split that. */
4658 code
= GET_CODE (SET_SRC (x
));
4663 /* If we are AND'ing with a large constant that is only a single
4664 bit and the result is only being used in a context where we
4665 need to know if it is zero or nonzero, replace it with a bit
4666 extraction. This will avoid the large constant, which might
4667 have taken more than one insn to make. If the constant were
4668 not a valid argument to the AND but took only one insn to make,
4669 this is no worse, but if it took more than one insn, it will
4672 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4673 && REG_P (XEXP (SET_SRC (x
), 0))
4674 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4675 && REG_P (SET_DEST (x
))
4676 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4677 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4678 && XEXP (*split
, 0) == SET_DEST (x
)
4679 && XEXP (*split
, 1) == const0_rtx
)
4681 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4682 XEXP (SET_SRC (x
), 0),
4683 pos
, NULL_RTX
, 1, 1, 0, 0);
4684 if (extraction
!= 0)
4686 SUBST (SET_SRC (x
), extraction
);
4687 return find_split_point (loc
, insn
, false);
4693 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4694 is known to be on, this can be converted into a NEG of a shift. */
4695 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4696 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4697 && 1 <= (pos
= exact_log2
4698 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4699 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4701 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4705 gen_rtx_LSHIFTRT (mode
,
4706 XEXP (SET_SRC (x
), 0),
4709 split
= find_split_point (&SET_SRC (x
), insn
, true);
4710 if (split
&& split
!= &SET_SRC (x
))
4716 inner
= XEXP (SET_SRC (x
), 0);
4718 /* We can't optimize if either mode is a partial integer
4719 mode as we don't know how many bits are significant
4721 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4722 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4726 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
4732 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4733 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4735 inner
= XEXP (SET_SRC (x
), 0);
4736 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4737 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4739 if (BITS_BIG_ENDIAN
)
4740 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
4741 unsignedp
= (code
== ZERO_EXTRACT
);
4749 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
4751 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4753 /* For unsigned, we have a choice of a shift followed by an
4754 AND or two shifts. Use two shifts for field sizes where the
4755 constant might be too large. We assume here that we can
4756 always at least get 8-bit constants in an AND insn, which is
4757 true for every current RISC. */
4759 if (unsignedp
&& len
<= 8)
4764 (mode
, gen_lowpart (mode
, inner
),
4766 GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
)
4769 split
= find_split_point (&SET_SRC (x
), insn
, true);
4770 if (split
&& split
!= &SET_SRC (x
))
4777 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4778 gen_rtx_ASHIFT (mode
,
4779 gen_lowpart (mode
, inner
),
4780 GEN_INT (GET_MODE_BITSIZE (mode
)
4782 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
4784 split
= find_split_point (&SET_SRC (x
), insn
, true);
4785 if (split
&& split
!= &SET_SRC (x
))
4790 /* See if this is a simple operation with a constant as the second
4791 operand. It might be that this constant is out of range and hence
4792 could be used as a split point. */
4793 if (BINARY_P (SET_SRC (x
))
4794 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4795 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4796 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4797 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4798 return &XEXP (SET_SRC (x
), 1);
4800 /* Finally, see if this is a simple operation with its first operand
4801 not in a register. The operation might require this operand in a
4802 register, so return it as a split point. We can always do this
4803 because if the first operand were another operation, we would have
4804 already found it as a split point. */
4805 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4806 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4807 return &XEXP (SET_SRC (x
), 0);
4813 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4814 it is better to write this as (not (ior A B)) so we can split it.
4815 Similarly for IOR. */
4816 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4819 gen_rtx_NOT (GET_MODE (x
),
4820 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4822 XEXP (XEXP (x
, 0), 0),
4823 XEXP (XEXP (x
, 1), 0))));
4824 return find_split_point (loc
, insn
, set_src
);
4827 /* Many RISC machines have a large set of logical insns. If the
4828 second operand is a NOT, put it first so we will try to split the
4829 other operand first. */
4830 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4832 rtx tem
= XEXP (x
, 0);
4833 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4834 SUBST (XEXP (x
, 1), tem
);
4840 /* Canonicalization can produce (minus A (mult B C)), where C is a
4841 constant. It may be better to try splitting (plus (mult B -C) A)
4842 instead if this isn't a multiply by a power of two. */
4843 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4844 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4845 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4847 enum machine_mode mode
= GET_MODE (x
);
4848 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4849 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4850 SUBST (*loc
, gen_rtx_PLUS (mode
, gen_rtx_MULT (mode
,
4851 XEXP (XEXP (x
, 1), 0),
4852 GEN_INT (other_int
)),
4854 return find_split_point (loc
, insn
, set_src
);
4857 /* Split at a multiply-accumulate instruction. However if this is
4858 the SET_SRC, we likely do not have such an instruction and it's
4859 worthless to try this split. */
4860 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4867 /* Otherwise, select our actions depending on our rtx class. */
4868 switch (GET_RTX_CLASS (code
))
4870 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4872 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4875 /* ... fall through ... */
4877 case RTX_COMM_ARITH
:
4879 case RTX_COMM_COMPARE
:
4880 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4883 /* ... fall through ... */
4885 /* Some machines have (and (shift ...) ...) insns. If X is not
4886 an AND, but XEXP (X, 0) is, use it as our split point. */
4887 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4888 return &XEXP (x
, 0);
4890 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4896 /* Otherwise, we don't have a split point. */
4901 /* Throughout X, replace FROM with TO, and return the result.
4902 The result is TO if X is FROM;
4903 otherwise the result is X, but its contents may have been modified.
4904 If they were modified, a record was made in undobuf so that
4905 undo_all will (among other things) return X to its original state.
4907 If the number of changes necessary is too much to record to undo,
4908 the excess changes are not made, so the result is invalid.
4909 The changes already made can still be undone.
4910 undobuf.num_undo is incremented for such changes, so by testing that
4911 the caller can tell whether the result is valid.
4913 `n_occurrences' is incremented each time FROM is replaced.
4915 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4917 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4918 by copying if `n_occurrences' is nonzero. */
4921 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
4923 enum rtx_code code
= GET_CODE (x
);
4924 enum machine_mode op0_mode
= VOIDmode
;
4929 /* Two expressions are equal if they are identical copies of a shared
4930 RTX or if they are both registers with the same register number
4933 #define COMBINE_RTX_EQUAL_P(X,Y) \
4935 || (REG_P (X) && REG_P (Y) \
4936 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4938 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4941 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4944 /* If X and FROM are the same register but different modes, they
4945 will not have been seen as equal above. However, the log links code
4946 will make a LOG_LINKS entry for that case. If we do nothing, we
4947 will try to rerecognize our original insn and, when it succeeds,
4948 we will delete the feeding insn, which is incorrect.
4950 So force this insn not to match in this (rare) case. */
4951 if (! in_dest
&& code
== REG
&& REG_P (from
)
4952 && reg_overlap_mentioned_p (x
, from
))
4953 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4955 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4956 of which may contain things that can be combined. */
4957 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4960 /* It is possible to have a subexpression appear twice in the insn.
4961 Suppose that FROM is a register that appears within TO.
4962 Then, after that subexpression has been scanned once by `subst',
4963 the second time it is scanned, TO may be found. If we were
4964 to scan TO here, we would find FROM within it and create a
4965 self-referent rtl structure which is completely wrong. */
4966 if (COMBINE_RTX_EQUAL_P (x
, to
))
4969 /* Parallel asm_operands need special attention because all of the
4970 inputs are shared across the arms. Furthermore, unsharing the
4971 rtl results in recognition failures. Failure to handle this case
4972 specially can result in circular rtl.
4974 Solve this by doing a normal pass across the first entry of the
4975 parallel, and only processing the SET_DESTs of the subsequent
4978 if (code
== PARALLEL
4979 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4980 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4982 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
4984 /* If this substitution failed, this whole thing fails. */
4985 if (GET_CODE (new_rtx
) == CLOBBER
4986 && XEXP (new_rtx
, 0) == const0_rtx
)
4989 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4991 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4993 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4996 && GET_CODE (dest
) != CC0
4997 && GET_CODE (dest
) != PC
)
4999 new_rtx
= subst (dest
, from
, to
, 0, unique_copy
);
5001 /* If this substitution failed, this whole thing fails. */
5002 if (GET_CODE (new_rtx
) == CLOBBER
5003 && XEXP (new_rtx
, 0) == const0_rtx
)
5006 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5012 len
= GET_RTX_LENGTH (code
);
5013 fmt
= GET_RTX_FORMAT (code
);
5015 /* We don't need to process a SET_DEST that is a register, CC0,
5016 or PC, so set up to skip this common case. All other cases
5017 where we want to suppress replacing something inside a
5018 SET_SRC are handled via the IN_DEST operand. */
5020 && (REG_P (SET_DEST (x
))
5021 || GET_CODE (SET_DEST (x
)) == CC0
5022 || GET_CODE (SET_DEST (x
)) == PC
))
5025 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5028 op0_mode
= GET_MODE (XEXP (x
, 0));
5030 for (i
= 0; i
< len
; i
++)
5035 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5037 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5039 new_rtx
= (unique_copy
&& n_occurrences
5040 ? copy_rtx (to
) : to
);
5045 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0,
5048 /* If this substitution failed, this whole thing
5050 if (GET_CODE (new_rtx
) == CLOBBER
5051 && XEXP (new_rtx
, 0) == const0_rtx
)
5055 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5058 else if (fmt
[i
] == 'e')
5060 /* If this is a register being set, ignore it. */
5061 new_rtx
= XEXP (x
, i
);
5064 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5066 || code
== STRICT_LOW_PART
))
5069 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5071 /* In general, don't install a subreg involving two
5072 modes not tieable. It can worsen register
5073 allocation, and can even make invalid reload
5074 insns, since the reg inside may need to be copied
5075 from in the outside mode, and that may be invalid
5076 if it is an fp reg copied in integer mode.
5078 We allow two exceptions to this: It is valid if
5079 it is inside another SUBREG and the mode of that
5080 SUBREG and the mode of the inside of TO is
5081 tieable and it is valid if X is a SET that copies
5084 if (GET_CODE (to
) == SUBREG
5085 && ! MODES_TIEABLE_P (GET_MODE (to
),
5086 GET_MODE (SUBREG_REG (to
)))
5087 && ! (code
== SUBREG
5088 && MODES_TIEABLE_P (GET_MODE (x
),
5089 GET_MODE (SUBREG_REG (to
))))
5091 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5094 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5096 #ifdef CANNOT_CHANGE_MODE_CLASS
5099 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5100 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5103 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5106 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5110 /* If we are in a SET_DEST, suppress most cases unless we
5111 have gone inside a MEM, in which case we want to
5112 simplify the address. We assume here that things that
5113 are actually part of the destination have their inner
5114 parts in the first expression. This is true for SUBREG,
5115 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5116 things aside from REG and MEM that should appear in a
5118 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5120 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5121 || code
== ZERO_EXTRACT
))
5123 && i
== 0), unique_copy
);
5125 /* If we found that we will have to reject this combination,
5126 indicate that by returning the CLOBBER ourselves, rather than
5127 an expression containing it. This will speed things up as
5128 well as prevent accidents where two CLOBBERs are considered
5129 to be equal, thus producing an incorrect simplification. */
5131 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5134 if (GET_CODE (x
) == SUBREG
5135 && (CONST_INT_P (new_rtx
)
5136 || GET_CODE (new_rtx
) == CONST_DOUBLE
))
5138 enum machine_mode mode
= GET_MODE (x
);
5140 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5141 GET_MODE (SUBREG_REG (x
)),
5144 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5146 else if (CONST_INT_P (new_rtx
)
5147 && GET_CODE (x
) == ZERO_EXTEND
)
5149 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5150 new_rtx
, GET_MODE (XEXP (x
, 0)));
5154 SUBST (XEXP (x
, i
), new_rtx
);
5159 /* Check if we are loading something from the constant pool via float
5160 extension; in this case we would undo compress_float_constant
5161 optimization and degenerate constant load to an immediate value. */
5162 if (GET_CODE (x
) == FLOAT_EXTEND
5163 && MEM_P (XEXP (x
, 0))
5164 && MEM_READONLY_P (XEXP (x
, 0)))
5166 rtx tmp
= avoid_constant_pool_reference (x
);
5171 /* Try to simplify X. If the simplification changed the code, it is likely
5172 that further simplification will help, so loop, but limit the number
5173 of repetitions that will be performed. */
5175 for (i
= 0; i
< 4; i
++)
5177 /* If X is sufficiently simple, don't bother trying to do anything
5179 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5180 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
5182 if (GET_CODE (x
) == code
)
5185 code
= GET_CODE (x
);
5187 /* We no longer know the original mode of operand 0 since we
5188 have changed the form of X) */
5189 op0_mode
= VOIDmode
;
5195 /* Simplify X, a piece of RTL. We just operate on the expression at the
5196 outer level; call `subst' to simplify recursively. Return the new
5199 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5200 if we are inside a SET_DEST. */
5203 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
5205 enum rtx_code code
= GET_CODE (x
);
5206 enum machine_mode mode
= GET_MODE (x
);
5210 /* If this is a commutative operation, put a constant last and a complex
5211 expression first. We don't need to do this for comparisons here. */
5212 if (COMMUTATIVE_ARITH_P (x
)
5213 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5216 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5217 SUBST (XEXP (x
, 1), temp
);
5220 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5221 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5222 things. Check for cases where both arms are testing the same
5225 Don't do anything if all operands are very simple. */
5228 && ((!OBJECT_P (XEXP (x
, 0))
5229 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5230 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5231 || (!OBJECT_P (XEXP (x
, 1))
5232 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5233 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5235 && (!OBJECT_P (XEXP (x
, 0))
5236 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5237 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5239 rtx cond
, true_rtx
, false_rtx
;
5241 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5243 /* If everything is a comparison, what we have is highly unlikely
5244 to be simpler, so don't use it. */
5245 && ! (COMPARISON_P (x
)
5246 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5248 rtx cop1
= const0_rtx
;
5249 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5251 if (cond_code
== NE
&& COMPARISON_P (cond
))
5254 /* Simplify the alternative arms; this may collapse the true and
5255 false arms to store-flag values. Be careful to use copy_rtx
5256 here since true_rtx or false_rtx might share RTL with x as a
5257 result of the if_then_else_cond call above. */
5258 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
5259 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
5261 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5262 is unlikely to be simpler. */
5263 if (general_operand (true_rtx
, VOIDmode
)
5264 && general_operand (false_rtx
, VOIDmode
))
5266 enum rtx_code reversed
;
5268 /* Restarting if we generate a store-flag expression will cause
5269 us to loop. Just drop through in this case. */
5271 /* If the result values are STORE_FLAG_VALUE and zero, we can
5272 just make the comparison operation. */
5273 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5274 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5276 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5277 && ((reversed
= reversed_comparison_code_parts
5278 (cond_code
, cond
, cop1
, NULL
))
5280 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5283 /* Likewise, we can make the negate of a comparison operation
5284 if the result values are - STORE_FLAG_VALUE and zero. */
5285 else if (CONST_INT_P (true_rtx
)
5286 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5287 && false_rtx
== const0_rtx
)
5288 x
= simplify_gen_unary (NEG
, mode
,
5289 simplify_gen_relational (cond_code
,
5293 else if (CONST_INT_P (false_rtx
)
5294 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5295 && true_rtx
== const0_rtx
5296 && ((reversed
= reversed_comparison_code_parts
5297 (cond_code
, cond
, cop1
, NULL
))
5299 x
= simplify_gen_unary (NEG
, mode
,
5300 simplify_gen_relational (reversed
,
5305 return gen_rtx_IF_THEN_ELSE (mode
,
5306 simplify_gen_relational (cond_code
,
5311 true_rtx
, false_rtx
);
5313 code
= GET_CODE (x
);
5314 op0_mode
= VOIDmode
;
5319 /* Try to fold this expression in case we have constants that weren't
5322 switch (GET_RTX_CLASS (code
))
5325 if (op0_mode
== VOIDmode
)
5326 op0_mode
= GET_MODE (XEXP (x
, 0));
5327 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5330 case RTX_COMM_COMPARE
:
5332 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5333 if (cmp_mode
== VOIDmode
)
5335 cmp_mode
= GET_MODE (XEXP (x
, 1));
5336 if (cmp_mode
== VOIDmode
)
5337 cmp_mode
= op0_mode
;
5339 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5340 XEXP (x
, 0), XEXP (x
, 1));
5343 case RTX_COMM_ARITH
:
5345 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5347 case RTX_BITFIELD_OPS
:
5349 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5350 XEXP (x
, 1), XEXP (x
, 2));
5359 code
= GET_CODE (temp
);
5360 op0_mode
= VOIDmode
;
5361 mode
= GET_MODE (temp
);
5364 /* First see if we can apply the inverse distributive law. */
5365 if (code
== PLUS
|| code
== MINUS
5366 || code
== AND
|| code
== IOR
|| code
== XOR
)
5368 x
= apply_distributive_law (x
);
5369 code
= GET_CODE (x
);
5370 op0_mode
= VOIDmode
;
5373 /* If CODE is an associative operation not otherwise handled, see if we
5374 can associate some operands. This can win if they are constants or
5375 if they are logically related (i.e. (a & b) & a). */
5376 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5377 || code
== AND
|| code
== IOR
|| code
== XOR
5378 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5379 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5380 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5382 if (GET_CODE (XEXP (x
, 0)) == code
)
5384 rtx other
= XEXP (XEXP (x
, 0), 0);
5385 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5386 rtx inner_op1
= XEXP (x
, 1);
5389 /* Make sure we pass the constant operand if any as the second
5390 one if this is a commutative operation. */
5391 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5393 rtx tem
= inner_op0
;
5394 inner_op0
= inner_op1
;
5397 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5398 : code
== DIV
? MULT
5400 mode
, inner_op0
, inner_op1
);
5402 /* For commutative operations, try the other pair if that one
5404 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5406 other
= XEXP (XEXP (x
, 0), 1);
5407 inner
= simplify_binary_operation (code
, mode
,
5408 XEXP (XEXP (x
, 0), 0),
5413 return simplify_gen_binary (code
, mode
, other
, inner
);
5417 /* A little bit of algebraic simplification here. */
5421 /* Ensure that our address has any ASHIFTs converted to MULT in case
5422 address-recognizing predicates are called later. */
5423 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5424 SUBST (XEXP (x
, 0), temp
);
5428 if (op0_mode
== VOIDmode
)
5429 op0_mode
= GET_MODE (SUBREG_REG (x
));
5431 /* See if this can be moved to simplify_subreg. */
5432 if (CONSTANT_P (SUBREG_REG (x
))
5433 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5434 /* Don't call gen_lowpart if the inner mode
5435 is VOIDmode and we cannot simplify it, as SUBREG without
5436 inner mode is invalid. */
5437 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5438 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5439 return gen_lowpart (mode
, SUBREG_REG (x
));
5441 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5445 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5451 /* Don't change the mode of the MEM if that would change the meaning
5453 if (MEM_P (SUBREG_REG (x
))
5454 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5455 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
5456 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5458 /* Note that we cannot do any narrowing for non-constants since
5459 we might have been counting on using the fact that some bits were
5460 zero. We now do this in the SET. */
5465 temp
= expand_compound_operation (XEXP (x
, 0));
5467 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5468 replaced by (lshiftrt X C). This will convert
5469 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5471 if (GET_CODE (temp
) == ASHIFTRT
5472 && CONST_INT_P (XEXP (temp
, 1))
5473 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5474 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5475 INTVAL (XEXP (temp
, 1)));
5477 /* If X has only a single bit that might be nonzero, say, bit I, convert
5478 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5479 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5480 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5481 or a SUBREG of one since we'd be making the expression more
5482 complex if it was just a register. */
5485 && ! (GET_CODE (temp
) == SUBREG
5486 && REG_P (SUBREG_REG (temp
)))
5487 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5489 rtx temp1
= simplify_shift_const
5490 (NULL_RTX
, ASHIFTRT
, mode
,
5491 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5492 GET_MODE_BITSIZE (mode
) - 1 - i
),
5493 GET_MODE_BITSIZE (mode
) - 1 - i
);
5495 /* If all we did was surround TEMP with the two shifts, we
5496 haven't improved anything, so don't use it. Otherwise,
5497 we are better off with TEMP1. */
5498 if (GET_CODE (temp1
) != ASHIFTRT
5499 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5500 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5506 /* We can't handle truncation to a partial integer mode here
5507 because we don't know the real bitsize of the partial
5509 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5512 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5514 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5515 GET_MODE_MASK (mode
), 0));
5517 /* We can truncate a constant value and return it. */
5518 if (CONST_INT_P (XEXP (x
, 0)))
5519 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5521 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5522 whose value is a comparison can be replaced with a subreg if
5523 STORE_FLAG_VALUE permits. */
5524 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5525 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5526 && (temp
= get_last_value (XEXP (x
, 0)))
5527 && COMPARISON_P (temp
))
5528 return gen_lowpart (mode
, XEXP (x
, 0));
5532 /* (const (const X)) can become (const X). Do it this way rather than
5533 returning the inner CONST since CONST can be shared with a
5535 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5536 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5541 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5542 can add in an offset. find_split_point will split this address up
5543 again if it doesn't match. */
5544 if (GET_CODE (XEXP (x
, 0)) == HIGH
5545 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5551 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5552 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5553 bit-field and can be replaced by either a sign_extend or a
5554 sign_extract. The `and' may be a zero_extend and the two
5555 <c>, -<c> constants may be reversed. */
5556 if (GET_CODE (XEXP (x
, 0)) == XOR
5557 && CONST_INT_P (XEXP (x
, 1))
5558 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5559 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5560 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5561 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5562 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5563 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5564 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5565 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5566 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5567 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5568 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5569 == (unsigned int) i
+ 1))))
5570 return simplify_shift_const
5571 (NULL_RTX
, ASHIFTRT
, mode
,
5572 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5573 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5574 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
5575 GET_MODE_BITSIZE (mode
) - (i
+ 1));
5577 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5578 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5579 the bitsize of the mode - 1. This allows simplification of
5580 "a = (b & 8) == 0;" */
5581 if (XEXP (x
, 1) == constm1_rtx
5582 && !REG_P (XEXP (x
, 0))
5583 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5584 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5585 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5586 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5587 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5588 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5589 GET_MODE_BITSIZE (mode
) - 1),
5590 GET_MODE_BITSIZE (mode
) - 1);
5592 /* If we are adding two things that have no bits in common, convert
5593 the addition into an IOR. This will often be further simplified,
5594 for example in cases like ((a & 1) + (a & 2)), which can
5597 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5598 && (nonzero_bits (XEXP (x
, 0), mode
)
5599 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5601 /* Try to simplify the expression further. */
5602 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5603 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
5605 /* If we could, great. If not, do not go ahead with the IOR
5606 replacement, since PLUS appears in many special purpose
5607 address arithmetic instructions. */
5608 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
5614 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5615 (and <foo> (const_int pow2-1)) */
5616 if (GET_CODE (XEXP (x
, 1)) == AND
5617 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5618 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5619 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5620 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5621 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5625 /* If we have (mult (plus A B) C), apply the distributive law and then
5626 the inverse distributive law to see if things simplify. This
5627 occurs mostly in addresses, often when unrolling loops. */
5629 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5631 rtx result
= distribute_and_simplify_rtx (x
, 0);
5636 /* Try simplify a*(b/c) as (a*b)/c. */
5637 if (FLOAT_MODE_P (mode
) && flag_associative_math
5638 && GET_CODE (XEXP (x
, 0)) == DIV
)
5640 rtx tem
= simplify_binary_operation (MULT
, mode
,
5641 XEXP (XEXP (x
, 0), 0),
5644 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5649 /* If this is a divide by a power of two, treat it as a shift if
5650 its first operand is a shift. */
5651 if (CONST_INT_P (XEXP (x
, 1))
5652 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5653 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5654 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5655 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5656 || GET_CODE (XEXP (x
, 0)) == ROTATE
5657 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5658 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5662 case GT
: case GTU
: case GE
: case GEU
:
5663 case LT
: case LTU
: case LE
: case LEU
:
5664 case UNEQ
: case LTGT
:
5665 case UNGT
: case UNGE
:
5666 case UNLT
: case UNLE
:
5667 case UNORDERED
: case ORDERED
:
5668 /* If the first operand is a condition code, we can't do anything
5670 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5671 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5672 && ! CC0_P (XEXP (x
, 0))))
5674 rtx op0
= XEXP (x
, 0);
5675 rtx op1
= XEXP (x
, 1);
5676 enum rtx_code new_code
;
5678 if (GET_CODE (op0
) == COMPARE
)
5679 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5681 /* Simplify our comparison, if possible. */
5682 new_code
= simplify_comparison (code
, &op0
, &op1
);
5684 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5685 if only the low-order bit is possibly nonzero in X (such as when
5686 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5687 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5688 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5691 Remove any ZERO_EXTRACT we made when thinking this was a
5692 comparison. It may now be simpler to use, e.g., an AND. If a
5693 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5694 the call to make_compound_operation in the SET case. */
5696 if (STORE_FLAG_VALUE
== 1
5697 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5698 && op1
== const0_rtx
5699 && mode
== GET_MODE (op0
)
5700 && nonzero_bits (op0
, mode
) == 1)
5701 return gen_lowpart (mode
,
5702 expand_compound_operation (op0
));
5704 else if (STORE_FLAG_VALUE
== 1
5705 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5706 && op1
== const0_rtx
5707 && mode
== GET_MODE (op0
)
5708 && (num_sign_bit_copies (op0
, mode
)
5709 == GET_MODE_BITSIZE (mode
)))
5711 op0
= expand_compound_operation (op0
);
5712 return simplify_gen_unary (NEG
, mode
,
5713 gen_lowpart (mode
, op0
),
5717 else if (STORE_FLAG_VALUE
== 1
5718 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5719 && op1
== const0_rtx
5720 && mode
== GET_MODE (op0
)
5721 && nonzero_bits (op0
, mode
) == 1)
5723 op0
= expand_compound_operation (op0
);
5724 return simplify_gen_binary (XOR
, mode
,
5725 gen_lowpart (mode
, op0
),
5729 else if (STORE_FLAG_VALUE
== 1
5730 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5731 && op1
== const0_rtx
5732 && mode
== GET_MODE (op0
)
5733 && (num_sign_bit_copies (op0
, mode
)
5734 == GET_MODE_BITSIZE (mode
)))
5736 op0
= expand_compound_operation (op0
);
5737 return plus_constant (gen_lowpart (mode
, op0
), 1);
5740 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5742 if (STORE_FLAG_VALUE
== -1
5743 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5744 && op1
== const0_rtx
5745 && (num_sign_bit_copies (op0
, mode
)
5746 == GET_MODE_BITSIZE (mode
)))
5747 return gen_lowpart (mode
,
5748 expand_compound_operation (op0
));
5750 else if (STORE_FLAG_VALUE
== -1
5751 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5752 && op1
== const0_rtx
5753 && mode
== GET_MODE (op0
)
5754 && nonzero_bits (op0
, mode
) == 1)
5756 op0
= expand_compound_operation (op0
);
5757 return simplify_gen_unary (NEG
, mode
,
5758 gen_lowpart (mode
, op0
),
5762 else if (STORE_FLAG_VALUE
== -1
5763 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5764 && op1
== const0_rtx
5765 && mode
== GET_MODE (op0
)
5766 && (num_sign_bit_copies (op0
, mode
)
5767 == GET_MODE_BITSIZE (mode
)))
5769 op0
= expand_compound_operation (op0
);
5770 return simplify_gen_unary (NOT
, mode
,
5771 gen_lowpart (mode
, op0
),
5775 /* If X is 0/1, (eq X 0) is X-1. */
5776 else if (STORE_FLAG_VALUE
== -1
5777 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5778 && op1
== const0_rtx
5779 && mode
== GET_MODE (op0
)
5780 && nonzero_bits (op0
, mode
) == 1)
5782 op0
= expand_compound_operation (op0
);
5783 return plus_constant (gen_lowpart (mode
, op0
), -1);
5786 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5787 one bit that might be nonzero, we can convert (ne x 0) to
5788 (ashift x c) where C puts the bit in the sign bit. Remove any
5789 AND with STORE_FLAG_VALUE when we are done, since we are only
5790 going to test the sign bit. */
5791 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5792 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5793 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5794 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5795 && op1
== const0_rtx
5796 && mode
== GET_MODE (op0
)
5797 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5799 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5800 expand_compound_operation (op0
),
5801 GET_MODE_BITSIZE (mode
) - 1 - i
);
5802 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5808 /* If the code changed, return a whole new comparison. */
5809 if (new_code
!= code
)
5810 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5812 /* Otherwise, keep this operation, but maybe change its operands.
5813 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5814 SUBST (XEXP (x
, 0), op0
);
5815 SUBST (XEXP (x
, 1), op1
);
5820 return simplify_if_then_else (x
);
5826 /* If we are processing SET_DEST, we are done. */
5830 return expand_compound_operation (x
);
5833 return simplify_set (x
);
5837 return simplify_logical (x
);
5844 /* If this is a shift by a constant amount, simplify it. */
5845 if (CONST_INT_P (XEXP (x
, 1)))
5846 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5847 INTVAL (XEXP (x
, 1)));
5849 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5851 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5852 ((unsigned HOST_WIDE_INT
) 1
5853 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5865 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5868 simplify_if_then_else (rtx x
)
5870 enum machine_mode mode
= GET_MODE (x
);
5871 rtx cond
= XEXP (x
, 0);
5872 rtx true_rtx
= XEXP (x
, 1);
5873 rtx false_rtx
= XEXP (x
, 2);
5874 enum rtx_code true_code
= GET_CODE (cond
);
5875 int comparison_p
= COMPARISON_P (cond
);
5878 enum rtx_code false_code
;
5881 /* Simplify storing of the truth value. */
5882 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5883 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5884 XEXP (cond
, 0), XEXP (cond
, 1));
5886 /* Also when the truth value has to be reversed. */
5888 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5889 && (reversed
= reversed_comparison (cond
, mode
)))
5892 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5893 in it is being compared against certain values. Get the true and false
5894 comparisons and see if that says anything about the value of each arm. */
5897 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5899 && REG_P (XEXP (cond
, 0)))
5902 rtx from
= XEXP (cond
, 0);
5903 rtx true_val
= XEXP (cond
, 1);
5904 rtx false_val
= true_val
;
5907 /* If FALSE_CODE is EQ, swap the codes and arms. */
5909 if (false_code
== EQ
)
5911 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5912 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5915 /* If we are comparing against zero and the expression being tested has
5916 only a single bit that might be nonzero, that is its value when it is
5917 not equal to zero. Similarly if it is known to be -1 or 0. */
5919 if (true_code
== EQ
&& true_val
== const0_rtx
5920 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5923 false_val
= GEN_INT (trunc_int_for_mode (nzb
, GET_MODE (from
)));
5925 else if (true_code
== EQ
&& true_val
== const0_rtx
5926 && (num_sign_bit_copies (from
, GET_MODE (from
))
5927 == GET_MODE_BITSIZE (GET_MODE (from
))))
5930 false_val
= constm1_rtx
;
5933 /* Now simplify an arm if we know the value of the register in the
5934 branch and it is used in the arm. Be careful due to the potential
5935 of locally-shared RTL. */
5937 if (reg_mentioned_p (from
, true_rtx
))
5938 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5940 pc_rtx
, pc_rtx
, 0, 0);
5941 if (reg_mentioned_p (from
, false_rtx
))
5942 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5944 pc_rtx
, pc_rtx
, 0, 0);
5946 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5947 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5949 true_rtx
= XEXP (x
, 1);
5950 false_rtx
= XEXP (x
, 2);
5951 true_code
= GET_CODE (cond
);
5954 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5955 reversed, do so to avoid needing two sets of patterns for
5956 subtract-and-branch insns. Similarly if we have a constant in the true
5957 arm, the false arm is the same as the first operand of the comparison, or
5958 the false arm is more complicated than the true arm. */
5961 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5962 && (true_rtx
== pc_rtx
5963 || (CONSTANT_P (true_rtx
)
5964 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5965 || true_rtx
== const0_rtx
5966 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5967 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5968 && !OBJECT_P (false_rtx
))
5969 || reg_mentioned_p (true_rtx
, false_rtx
)
5970 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5972 true_code
= reversed_comparison_code (cond
, NULL
);
5973 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5974 SUBST (XEXP (x
, 1), false_rtx
);
5975 SUBST (XEXP (x
, 2), true_rtx
);
5977 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5980 /* It is possible that the conditional has been simplified out. */
5981 true_code
= GET_CODE (cond
);
5982 comparison_p
= COMPARISON_P (cond
);
5985 /* If the two arms are identical, we don't need the comparison. */
5987 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5990 /* Convert a == b ? b : a to "a". */
5991 if (true_code
== EQ
&& ! side_effects_p (cond
)
5992 && !HONOR_NANS (mode
)
5993 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5994 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5996 else if (true_code
== NE
&& ! side_effects_p (cond
)
5997 && !HONOR_NANS (mode
)
5998 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5999 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6002 /* Look for cases where we have (abs x) or (neg (abs X)). */
6004 if (GET_MODE_CLASS (mode
) == MODE_INT
6006 && XEXP (cond
, 1) == const0_rtx
6007 && GET_CODE (false_rtx
) == NEG
6008 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6009 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6010 && ! side_effects_p (true_rtx
))
6015 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6019 simplify_gen_unary (NEG
, mode
,
6020 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6026 /* Look for MIN or MAX. */
6028 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6030 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6031 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6032 && ! side_effects_p (cond
))
6037 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6040 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6043 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6046 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6051 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6052 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6053 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6054 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6055 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6056 neither 1 or -1, but it isn't worth checking for. */
6058 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6060 && GET_MODE_CLASS (mode
) == MODE_INT
6061 && ! side_effects_p (x
))
6063 rtx t
= make_compound_operation (true_rtx
, SET
);
6064 rtx f
= make_compound_operation (false_rtx
, SET
);
6065 rtx cond_op0
= XEXP (cond
, 0);
6066 rtx cond_op1
= XEXP (cond
, 1);
6067 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6068 enum machine_mode m
= mode
;
6069 rtx z
= 0, c1
= NULL_RTX
;
6071 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6072 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6073 || GET_CODE (t
) == ASHIFT
6074 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6075 && rtx_equal_p (XEXP (t
, 0), f
))
6076 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6078 /* If an identity-zero op is commutative, check whether there
6079 would be a match if we swapped the operands. */
6080 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6081 || GET_CODE (t
) == XOR
)
6082 && rtx_equal_p (XEXP (t
, 1), f
))
6083 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6084 else if (GET_CODE (t
) == SIGN_EXTEND
6085 && (GET_CODE (XEXP (t
, 0)) == PLUS
6086 || GET_CODE (XEXP (t
, 0)) == MINUS
6087 || GET_CODE (XEXP (t
, 0)) == IOR
6088 || GET_CODE (XEXP (t
, 0)) == XOR
6089 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6090 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6091 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6092 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6093 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6094 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6095 && (num_sign_bit_copies (f
, GET_MODE (f
))
6097 (GET_MODE_BITSIZE (mode
)
6098 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6100 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6101 extend_op
= SIGN_EXTEND
;
6102 m
= GET_MODE (XEXP (t
, 0));
6104 else if (GET_CODE (t
) == SIGN_EXTEND
6105 && (GET_CODE (XEXP (t
, 0)) == PLUS
6106 || GET_CODE (XEXP (t
, 0)) == IOR
6107 || GET_CODE (XEXP (t
, 0)) == XOR
)
6108 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6109 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6110 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6111 && (num_sign_bit_copies (f
, GET_MODE (f
))
6113 (GET_MODE_BITSIZE (mode
)
6114 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6116 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6117 extend_op
= SIGN_EXTEND
;
6118 m
= GET_MODE (XEXP (t
, 0));
6120 else if (GET_CODE (t
) == ZERO_EXTEND
6121 && (GET_CODE (XEXP (t
, 0)) == PLUS
6122 || GET_CODE (XEXP (t
, 0)) == MINUS
6123 || GET_CODE (XEXP (t
, 0)) == IOR
6124 || GET_CODE (XEXP (t
, 0)) == XOR
6125 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6126 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6127 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6128 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6129 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6130 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6131 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6132 && ((nonzero_bits (f
, GET_MODE (f
))
6133 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6136 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6137 extend_op
= ZERO_EXTEND
;
6138 m
= GET_MODE (XEXP (t
, 0));
6140 else if (GET_CODE (t
) == ZERO_EXTEND
6141 && (GET_CODE (XEXP (t
, 0)) == PLUS
6142 || GET_CODE (XEXP (t
, 0)) == IOR
6143 || GET_CODE (XEXP (t
, 0)) == XOR
)
6144 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6145 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6146 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6147 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6148 && ((nonzero_bits (f
, GET_MODE (f
))
6149 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6152 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6153 extend_op
= ZERO_EXTEND
;
6154 m
= GET_MODE (XEXP (t
, 0));
6159 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6160 cond_op0
, cond_op1
),
6161 pc_rtx
, pc_rtx
, 0, 0);
6162 temp
= simplify_gen_binary (MULT
, m
, temp
,
6163 simplify_gen_binary (MULT
, m
, c1
,
6165 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
6166 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6168 if (extend_op
!= UNKNOWN
)
6169 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6175 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6176 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6177 negation of a single bit, we can convert this operation to a shift. We
6178 can actually do this more generally, but it doesn't seem worth it. */
6180 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6181 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6182 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6183 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6184 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6185 == GET_MODE_BITSIZE (mode
))
6186 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6188 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6189 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6191 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6192 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6193 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6194 && GET_MODE (XEXP (cond
, 0)) == mode
6195 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6196 == nonzero_bits (XEXP (cond
, 0), mode
)
6197 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6198 return XEXP (cond
, 0);
6203 /* Simplify X, a SET expression. Return the new expression. */
6206 simplify_set (rtx x
)
6208 rtx src
= SET_SRC (x
);
6209 rtx dest
= SET_DEST (x
);
6210 enum machine_mode mode
6211 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6215 /* (set (pc) (return)) gets written as (return). */
6216 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
6219 /* Now that we know for sure which bits of SRC we are using, see if we can
6220 simplify the expression for the object knowing that we only need the
6223 if (GET_MODE_CLASS (mode
) == MODE_INT
6224 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
6226 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6227 SUBST (SET_SRC (x
), src
);
6230 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6231 the comparison result and try to simplify it unless we already have used
6232 undobuf.other_insn. */
6233 if ((GET_MODE_CLASS (mode
) == MODE_CC
6234 || GET_CODE (src
) == COMPARE
6236 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6237 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6238 && COMPARISON_P (*cc_use
)
6239 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6241 enum rtx_code old_code
= GET_CODE (*cc_use
);
6242 enum rtx_code new_code
;
6244 int other_changed
= 0;
6245 enum machine_mode compare_mode
= GET_MODE (dest
);
6247 if (GET_CODE (src
) == COMPARE
)
6248 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6250 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6252 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6255 new_code
= old_code
;
6256 else if (!CONSTANT_P (tmp
))
6258 new_code
= GET_CODE (tmp
);
6259 op0
= XEXP (tmp
, 0);
6260 op1
= XEXP (tmp
, 1);
6264 rtx pat
= PATTERN (other_insn
);
6265 undobuf
.other_insn
= other_insn
;
6266 SUBST (*cc_use
, tmp
);
6268 /* Attempt to simplify CC user. */
6269 if (GET_CODE (pat
) == SET
)
6271 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6272 if (new_rtx
!= NULL_RTX
)
6273 SUBST (SET_SRC (pat
), new_rtx
);
6276 /* Convert X into a no-op move. */
6277 SUBST (SET_DEST (x
), pc_rtx
);
6278 SUBST (SET_SRC (x
), pc_rtx
);
6282 /* Simplify our comparison, if possible. */
6283 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6285 #ifdef SELECT_CC_MODE
6286 /* If this machine has CC modes other than CCmode, check to see if we
6287 need to use a different CC mode here. */
6288 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6289 compare_mode
= GET_MODE (op0
);
6291 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6294 /* If the mode changed, we have to change SET_DEST, the mode in the
6295 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6296 a hard register, just build new versions with the proper mode. If it
6297 is a pseudo, we lose unless it is only time we set the pseudo, in
6298 which case we can safely change its mode. */
6299 if (compare_mode
!= GET_MODE (dest
))
6301 if (can_change_dest_mode (dest
, 0, compare_mode
))
6303 unsigned int regno
= REGNO (dest
);
6306 if (regno
< FIRST_PSEUDO_REGISTER
)
6307 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6310 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6311 new_dest
= regno_reg_rtx
[regno
];
6314 SUBST (SET_DEST (x
), new_dest
);
6315 SUBST (XEXP (*cc_use
, 0), new_dest
);
6322 #endif /* SELECT_CC_MODE */
6324 /* If the code changed, we have to build a new comparison in
6325 undobuf.other_insn. */
6326 if (new_code
!= old_code
)
6328 int other_changed_previously
= other_changed
;
6329 unsigned HOST_WIDE_INT mask
;
6330 rtx old_cc_use
= *cc_use
;
6332 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6336 /* If the only change we made was to change an EQ into an NE or
6337 vice versa, OP0 has only one bit that might be nonzero, and OP1
6338 is zero, check if changing the user of the condition code will
6339 produce a valid insn. If it won't, we can keep the original code
6340 in that insn by surrounding our operation with an XOR. */
6342 if (((old_code
== NE
&& new_code
== EQ
)
6343 || (old_code
== EQ
&& new_code
== NE
))
6344 && ! other_changed_previously
&& op1
== const0_rtx
6345 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
6346 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6348 rtx pat
= PATTERN (other_insn
), note
= 0;
6350 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6351 && ! check_asm_operands (pat
)))
6353 *cc_use
= old_cc_use
;
6356 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6357 op0
, GEN_INT (mask
));
6363 undobuf
.other_insn
= other_insn
;
6365 /* Otherwise, if we didn't previously have a COMPARE in the
6366 correct mode, we need one. */
6367 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6369 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6372 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6374 SUBST (SET_SRC (x
), op0
);
6377 /* Otherwise, update the COMPARE if needed. */
6378 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6380 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6386 /* Get SET_SRC in a form where we have placed back any
6387 compound expressions. Then do the checks below. */
6388 src
= make_compound_operation (src
, SET
);
6389 SUBST (SET_SRC (x
), src
);
6392 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6393 and X being a REG or (subreg (reg)), we may be able to convert this to
6394 (set (subreg:m2 x) (op)).
6396 We can always do this if M1 is narrower than M2 because that means that
6397 we only care about the low bits of the result.
6399 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6400 perform a narrower operation than requested since the high-order bits will
6401 be undefined. On machine where it is defined, this transformation is safe
6402 as long as M1 and M2 have the same number of words. */
6404 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6405 && !OBJECT_P (SUBREG_REG (src
))
6406 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6408 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6409 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6410 #ifndef WORD_REGISTER_OPERATIONS
6411 && (GET_MODE_SIZE (GET_MODE (src
))
6412 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6414 #ifdef CANNOT_CHANGE_MODE_CLASS
6415 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6416 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6417 GET_MODE (SUBREG_REG (src
)),
6421 || (GET_CODE (dest
) == SUBREG
6422 && REG_P (SUBREG_REG (dest
)))))
6424 SUBST (SET_DEST (x
),
6425 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6427 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6429 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6433 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6436 && GET_CODE (src
) == SUBREG
6437 && subreg_lowpart_p (src
)
6438 && (GET_MODE_BITSIZE (GET_MODE (src
))
6439 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
6441 rtx inner
= SUBREG_REG (src
);
6442 enum machine_mode inner_mode
= GET_MODE (inner
);
6444 /* Here we make sure that we don't have a sign bit on. */
6445 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
6446 && (nonzero_bits (inner
, inner_mode
)
6447 < ((unsigned HOST_WIDE_INT
) 1
6448 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
6450 SUBST (SET_SRC (x
), inner
);
6456 #ifdef LOAD_EXTEND_OP
6457 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6458 would require a paradoxical subreg. Replace the subreg with a
6459 zero_extend to avoid the reload that would otherwise be required. */
6461 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6462 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6463 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6464 && SUBREG_BYTE (src
) == 0
6465 && (GET_MODE_SIZE (GET_MODE (src
))
6466 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6467 && MEM_P (SUBREG_REG (src
)))
6470 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6471 GET_MODE (src
), SUBREG_REG (src
)));
6477 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6478 are comparing an item known to be 0 or -1 against 0, use a logical
6479 operation instead. Check for one of the arms being an IOR of the other
6480 arm with some value. We compute three terms to be IOR'ed together. In
6481 practice, at most two will be nonzero. Then we do the IOR's. */
6483 if (GET_CODE (dest
) != PC
6484 && GET_CODE (src
) == IF_THEN_ELSE
6485 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6486 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6487 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6488 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6489 #ifdef HAVE_conditional_move
6490 && ! can_conditionally_move_p (GET_MODE (src
))
6492 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6493 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6494 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6495 && ! side_effects_p (src
))
6497 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6498 ? XEXP (src
, 1) : XEXP (src
, 2));
6499 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6500 ? XEXP (src
, 2) : XEXP (src
, 1));
6501 rtx term1
= const0_rtx
, term2
, term3
;
6503 if (GET_CODE (true_rtx
) == IOR
6504 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6505 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6506 else if (GET_CODE (true_rtx
) == IOR
6507 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6508 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6509 else if (GET_CODE (false_rtx
) == IOR
6510 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6511 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6512 else if (GET_CODE (false_rtx
) == IOR
6513 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6514 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6516 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6517 XEXP (XEXP (src
, 0), 0), true_rtx
);
6518 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6519 simplify_gen_unary (NOT
, GET_MODE (src
),
6520 XEXP (XEXP (src
, 0), 0),
6525 simplify_gen_binary (IOR
, GET_MODE (src
),
6526 simplify_gen_binary (IOR
, GET_MODE (src
),
6533 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6534 whole thing fail. */
6535 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6537 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6540 /* Convert this into a field assignment operation, if possible. */
6541 return make_field_assignment (x
);
6544 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6548 simplify_logical (rtx x
)
6550 enum machine_mode mode
= GET_MODE (x
);
6551 rtx op0
= XEXP (x
, 0);
6552 rtx op1
= XEXP (x
, 1);
6554 switch (GET_CODE (x
))
6557 /* We can call simplify_and_const_int only if we don't lose
6558 any (sign) bits when converting INTVAL (op1) to
6559 "unsigned HOST_WIDE_INT". */
6560 if (CONST_INT_P (op1
)
6561 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6562 || INTVAL (op1
) > 0))
6564 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6565 if (GET_CODE (x
) != AND
)
6572 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6573 apply the distributive law and then the inverse distributive
6574 law to see if things simplify. */
6575 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6577 rtx result
= distribute_and_simplify_rtx (x
, 0);
6581 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6583 rtx result
= distribute_and_simplify_rtx (x
, 1);
6590 /* If we have (ior (and A B) C), apply the distributive law and then
6591 the inverse distributive law to see if things simplify. */
6593 if (GET_CODE (op0
) == AND
)
6595 rtx result
= distribute_and_simplify_rtx (x
, 0);
6600 if (GET_CODE (op1
) == AND
)
6602 rtx result
= distribute_and_simplify_rtx (x
, 1);
6615 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6616 operations" because they can be replaced with two more basic operations.
6617 ZERO_EXTEND is also considered "compound" because it can be replaced with
6618 an AND operation, which is simpler, though only one operation.
6620 The function expand_compound_operation is called with an rtx expression
6621 and will convert it to the appropriate shifts and AND operations,
6622 simplifying at each stage.
6624 The function make_compound_operation is called to convert an expression
6625 consisting of shifts and ANDs into the equivalent compound expression.
6626 It is the inverse of this function, loosely speaking. */
6629 expand_compound_operation (rtx x
)
6631 unsigned HOST_WIDE_INT pos
= 0, len
;
6633 unsigned int modewidth
;
6636 switch (GET_CODE (x
))
6641 /* We can't necessarily use a const_int for a multiword mode;
6642 it depends on implicitly extending the value.
6643 Since we don't know the right way to extend it,
6644 we can't tell whether the implicit way is right.
6646 Even for a mode that is no wider than a const_int,
6647 we can't win, because we need to sign extend one of its bits through
6648 the rest of it, and we don't know which bit. */
6649 if (CONST_INT_P (XEXP (x
, 0)))
6652 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6653 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6654 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6655 reloaded. If not for that, MEM's would very rarely be safe.
6657 Reject MODEs bigger than a word, because we might not be able
6658 to reference a two-register group starting with an arbitrary register
6659 (and currently gen_lowpart might crash for a SUBREG). */
6661 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6664 /* Reject MODEs that aren't scalar integers because turning vector
6665 or complex modes into shifts causes problems. */
6667 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6670 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
6671 /* If the inner object has VOIDmode (the only way this can happen
6672 is if it is an ASM_OPERANDS), we can't do anything since we don't
6673 know how much masking to do. */
6682 /* ... fall through ... */
6685 /* If the operand is a CLOBBER, just return it. */
6686 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6689 if (!CONST_INT_P (XEXP (x
, 1))
6690 || !CONST_INT_P (XEXP (x
, 2))
6691 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6694 /* Reject MODEs that aren't scalar integers because turning vector
6695 or complex modes into shifts causes problems. */
6697 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6700 len
= INTVAL (XEXP (x
, 1));
6701 pos
= INTVAL (XEXP (x
, 2));
6703 /* This should stay within the object being extracted, fail otherwise. */
6704 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
6707 if (BITS_BIG_ENDIAN
)
6708 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6715 /* Convert sign extension to zero extension, if we know that the high
6716 bit is not set, as this is easier to optimize. It will be converted
6717 back to cheaper alternative in make_extraction. */
6718 if (GET_CODE (x
) == SIGN_EXTEND
6719 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6720 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6721 & ~(((unsigned HOST_WIDE_INT
)
6722 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6726 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6727 rtx temp2
= expand_compound_operation (temp
);
6729 /* Make sure this is a profitable operation. */
6730 if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6731 > rtx_cost (temp2
, SET
, optimize_this_for_speed_p
))
6733 else if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6734 > rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
6740 /* We can optimize some special cases of ZERO_EXTEND. */
6741 if (GET_CODE (x
) == ZERO_EXTEND
)
6743 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6744 know that the last value didn't have any inappropriate bits
6746 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6747 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6748 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6749 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6750 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6751 return XEXP (XEXP (x
, 0), 0);
6753 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6754 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6755 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6756 && subreg_lowpart_p (XEXP (x
, 0))
6757 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6758 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6759 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6760 return SUBREG_REG (XEXP (x
, 0));
6762 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6763 is a comparison and STORE_FLAG_VALUE permits. This is like
6764 the first case, but it works even when GET_MODE (x) is larger
6765 than HOST_WIDE_INT. */
6766 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6767 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6768 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6769 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6770 <= HOST_BITS_PER_WIDE_INT
)
6771 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6772 return XEXP (XEXP (x
, 0), 0);
6774 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6775 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6776 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6777 && subreg_lowpart_p (XEXP (x
, 0))
6778 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6779 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6780 <= HOST_BITS_PER_WIDE_INT
)
6781 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6782 return SUBREG_REG (XEXP (x
, 0));
6786 /* If we reach here, we want to return a pair of shifts. The inner
6787 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6788 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6789 logical depending on the value of UNSIGNEDP.
6791 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6792 converted into an AND of a shift.
6794 We must check for the case where the left shift would have a negative
6795 count. This can happen in a case like (x >> 31) & 255 on machines
6796 that can't shift by a constant. On those machines, we would first
6797 combine the shift with the AND to produce a variable-position
6798 extraction. Then the constant of 31 would be substituted in
6799 to produce such a position. */
6801 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
6802 if (modewidth
>= pos
+ len
)
6804 enum machine_mode mode
= GET_MODE (x
);
6805 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6806 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6808 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6809 tem
, modewidth
- pos
- len
);
6810 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6811 mode
, tem
, modewidth
- len
);
6813 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6814 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6815 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6818 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6820 /* Any other cases we can't handle. */
6823 /* If we couldn't do this for some reason, return the original
6825 if (GET_CODE (tem
) == CLOBBER
)
6831 /* X is a SET which contains an assignment of one object into
6832 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6833 or certain SUBREGS). If possible, convert it into a series of
6836 We half-heartedly support variable positions, but do not at all
6837 support variable lengths. */
6840 expand_field_assignment (const_rtx x
)
6843 rtx pos
; /* Always counts from low bit. */
6845 rtx mask
, cleared
, masked
;
6846 enum machine_mode compute_mode
;
6848 /* Loop until we find something we can't simplify. */
6851 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6852 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6854 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6855 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6856 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6858 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6859 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6861 inner
= XEXP (SET_DEST (x
), 0);
6862 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6863 pos
= XEXP (SET_DEST (x
), 2);
6865 /* A constant position should stay within the width of INNER. */
6866 if (CONST_INT_P (pos
)
6867 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6870 if (BITS_BIG_ENDIAN
)
6872 if (CONST_INT_P (pos
))
6873 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6875 else if (GET_CODE (pos
) == MINUS
6876 && CONST_INT_P (XEXP (pos
, 1))
6877 && (INTVAL (XEXP (pos
, 1))
6878 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6879 /* If position is ADJUST - X, new position is X. */
6880 pos
= XEXP (pos
, 0);
6882 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6883 GEN_INT (GET_MODE_BITSIZE (
6890 /* A SUBREG between two modes that occupy the same numbers of words
6891 can be done by moving the SUBREG to the source. */
6892 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6893 /* We need SUBREGs to compute nonzero_bits properly. */
6894 && nonzero_sign_valid
6895 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6896 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6897 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6898 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6900 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6902 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6909 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6910 inner
= SUBREG_REG (inner
);
6912 compute_mode
= GET_MODE (inner
);
6914 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6915 if (! SCALAR_INT_MODE_P (compute_mode
))
6917 enum machine_mode imode
;
6919 /* Don't do anything for vector or complex integral types. */
6920 if (! FLOAT_MODE_P (compute_mode
))
6923 /* Try to find an integral mode to pun with. */
6924 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6925 if (imode
== BLKmode
)
6928 compute_mode
= imode
;
6929 inner
= gen_lowpart (imode
, inner
);
6932 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6933 if (len
>= HOST_BITS_PER_WIDE_INT
)
6936 /* Now compute the equivalent expression. Make a copy of INNER
6937 for the SET_DEST in case it is a MEM into which we will substitute;
6938 we don't want shared RTL in that case. */
6939 mask
= GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6940 cleared
= simplify_gen_binary (AND
, compute_mode
,
6941 simplify_gen_unary (NOT
, compute_mode
,
6942 simplify_gen_binary (ASHIFT
,
6947 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6948 simplify_gen_binary (
6950 gen_lowpart (compute_mode
, SET_SRC (x
)),
6954 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6955 simplify_gen_binary (IOR
, compute_mode
,
6962 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6963 it is an RTX that represents a variable starting position; otherwise,
6964 POS is the (constant) starting bit position (counted from the LSB).
6966 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6969 IN_DEST is nonzero if this is a reference in the destination of a
6970 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6971 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6974 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6975 ZERO_EXTRACT should be built even for bits starting at bit 0.
6977 MODE is the desired mode of the result (if IN_DEST == 0).
6979 The result is an RTX for the extraction or NULL_RTX if the target
6983 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6984 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6985 int in_dest
, int in_compare
)
6987 /* This mode describes the size of the storage area
6988 to fetch the overall value from. Within that, we
6989 ignore the POS lowest bits, etc. */
6990 enum machine_mode is_mode
= GET_MODE (inner
);
6991 enum machine_mode inner_mode
;
6992 enum machine_mode wanted_inner_mode
;
6993 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6994 enum machine_mode pos_mode
= word_mode
;
6995 enum machine_mode extraction_mode
= word_mode
;
6996 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6998 rtx orig_pos_rtx
= pos_rtx
;
6999 HOST_WIDE_INT orig_pos
;
7001 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7003 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7004 consider just the QI as the memory to extract from.
7005 The subreg adds or removes high bits; its mode is
7006 irrelevant to the meaning of this extraction,
7007 since POS and LEN count from the lsb. */
7008 if (MEM_P (SUBREG_REG (inner
)))
7009 is_mode
= GET_MODE (SUBREG_REG (inner
));
7010 inner
= SUBREG_REG (inner
);
7012 else if (GET_CODE (inner
) == ASHIFT
7013 && CONST_INT_P (XEXP (inner
, 1))
7014 && pos_rtx
== 0 && pos
== 0
7015 && len
> UINTVAL (XEXP (inner
, 1)))
7017 /* We're extracting the least significant bits of an rtx
7018 (ashift X (const_int C)), where LEN > C. Extract the
7019 least significant (LEN - C) bits of X, giving an rtx
7020 whose mode is MODE, then shift it left C times. */
7021 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7022 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7023 unsignedp
, in_dest
, in_compare
);
7025 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7028 inner_mode
= GET_MODE (inner
);
7030 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7031 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7033 /* See if this can be done without an extraction. We never can if the
7034 width of the field is not the same as that of some integer mode. For
7035 registers, we can only avoid the extraction if the position is at the
7036 low-order bit and this is either not in the destination or we have the
7037 appropriate STRICT_LOW_PART operation available.
7039 For MEM, we can avoid an extract if the field starts on an appropriate
7040 boundary and we can change the mode of the memory reference. */
7042 if (tmode
!= BLKmode
7043 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7045 && (inner_mode
== tmode
7047 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
7048 GET_MODE_BITSIZE (inner_mode
))
7049 || reg_truncated_to_mode (tmode
, inner
))
7052 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7053 || (MEM_P (inner
) && pos_rtx
== 0
7055 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7056 : BITS_PER_UNIT
)) == 0
7057 /* We can't do this if we are widening INNER_MODE (it
7058 may not be aligned, for one thing). */
7059 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
7060 && (inner_mode
== tmode
7061 || (! mode_dependent_address_p (XEXP (inner
, 0))
7062 && ! MEM_VOLATILE_P (inner
))))))
7064 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7065 field. If the original and current mode are the same, we need not
7066 adjust the offset. Otherwise, we do if bytes big endian.
7068 If INNER is not a MEM, get a piece consisting of just the field
7069 of interest (in this case POS % BITS_PER_WORD must be 0). */
7073 HOST_WIDE_INT offset
;
7075 /* POS counts from lsb, but make OFFSET count in memory order. */
7076 if (BYTES_BIG_ENDIAN
)
7077 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7079 offset
= pos
/ BITS_PER_UNIT
;
7081 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7083 else if (REG_P (inner
))
7085 if (tmode
!= inner_mode
)
7087 /* We can't call gen_lowpart in a DEST since we
7088 always want a SUBREG (see below) and it would sometimes
7089 return a new hard register. */
7092 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7094 if (WORDS_BIG_ENDIAN
7095 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7096 final_word
= ((GET_MODE_SIZE (inner_mode
)
7097 - GET_MODE_SIZE (tmode
))
7098 / UNITS_PER_WORD
) - final_word
;
7100 final_word
*= UNITS_PER_WORD
;
7101 if (BYTES_BIG_ENDIAN
&&
7102 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7103 final_word
+= (GET_MODE_SIZE (inner_mode
)
7104 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7106 /* Avoid creating invalid subregs, for example when
7107 simplifying (x>>32)&255. */
7108 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7111 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7114 new_rtx
= gen_lowpart (tmode
, inner
);
7120 new_rtx
= force_to_mode (inner
, tmode
,
7121 len
>= HOST_BITS_PER_WIDE_INT
7122 ? ~(unsigned HOST_WIDE_INT
) 0
7123 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7126 /* If this extraction is going into the destination of a SET,
7127 make a STRICT_LOW_PART unless we made a MEM. */
7130 return (MEM_P (new_rtx
) ? new_rtx
7131 : (GET_CODE (new_rtx
) != SUBREG
7132 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7133 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7138 if (CONST_INT_P (new_rtx
)
7139 || GET_CODE (new_rtx
) == CONST_DOUBLE
)
7140 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7141 mode
, new_rtx
, tmode
);
7143 /* If we know that no extraneous bits are set, and that the high
7144 bit is not set, convert the extraction to the cheaper of
7145 sign and zero extension, that are equivalent in these cases. */
7146 if (flag_expensive_optimizations
7147 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
7148 && ((nonzero_bits (new_rtx
, tmode
)
7149 & ~(((unsigned HOST_WIDE_INT
)
7150 GET_MODE_MASK (tmode
))
7154 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7155 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7157 /* Prefer ZERO_EXTENSION, since it gives more information to
7159 if (rtx_cost (temp
, SET
, optimize_this_for_speed_p
)
7160 <= rtx_cost (temp1
, SET
, optimize_this_for_speed_p
))
7165 /* Otherwise, sign- or zero-extend unless we already are in the
7168 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7172 /* Unless this is a COMPARE or we have a funny memory reference,
7173 don't do anything with zero-extending field extracts starting at
7174 the low-order bit since they are simple AND operations. */
7175 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7176 && ! in_compare
&& unsignedp
)
7179 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7180 if the position is not a constant and the length is not 1. In all
7181 other cases, we would only be going outside our object in cases when
7182 an original shift would have been undefined. */
7184 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
7185 || (pos_rtx
!= 0 && len
!= 1)))
7188 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7189 and the mode for the result. */
7190 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
7192 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
7193 pos_mode
= mode_for_extraction (EP_insv
, 2);
7194 extraction_mode
= mode_for_extraction (EP_insv
, 3);
7197 if (! in_dest
&& unsignedp
7198 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
7200 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
7201 pos_mode
= mode_for_extraction (EP_extzv
, 3);
7202 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
7205 if (! in_dest
&& ! unsignedp
7206 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
7208 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
7209 pos_mode
= mode_for_extraction (EP_extv
, 3);
7210 extraction_mode
= mode_for_extraction (EP_extv
, 0);
7213 /* Never narrow an object, since that might not be safe. */
7215 if (mode
!= VOIDmode
7216 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7217 extraction_mode
= mode
;
7219 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
7220 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7221 pos_mode
= GET_MODE (pos_rtx
);
7223 /* If this is not from memory, the desired mode is the preferred mode
7224 for an extraction pattern's first input operand, or word_mode if there
7227 wanted_inner_mode
= wanted_inner_reg_mode
;
7230 /* Be careful not to go beyond the extracted object and maintain the
7231 natural alignment of the memory. */
7232 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7233 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7234 > GET_MODE_BITSIZE (wanted_inner_mode
))
7236 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7237 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7240 /* If we have to change the mode of memory and cannot, the desired mode
7241 is EXTRACTION_MODE. */
7242 if (inner_mode
!= wanted_inner_mode
7243 && (mode_dependent_address_p (XEXP (inner
, 0))
7244 || MEM_VOLATILE_P (inner
)
7246 wanted_inner_mode
= extraction_mode
;
7251 if (BITS_BIG_ENDIAN
)
7253 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7254 BITS_BIG_ENDIAN style. If position is constant, compute new
7255 position. Otherwise, build subtraction.
7256 Note that POS is relative to the mode of the original argument.
7257 If it's a MEM we need to recompute POS relative to that.
7258 However, if we're extracting from (or inserting into) a register,
7259 we want to recompute POS relative to wanted_inner_mode. */
7260 int width
= (MEM_P (inner
)
7261 ? GET_MODE_BITSIZE (is_mode
)
7262 : GET_MODE_BITSIZE (wanted_inner_mode
));
7265 pos
= width
- len
- pos
;
7268 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
7269 /* POS may be less than 0 now, but we check for that below.
7270 Note that it can only be less than 0 if !MEM_P (inner). */
7273 /* If INNER has a wider mode, and this is a constant extraction, try to
7274 make it smaller and adjust the byte to point to the byte containing
7276 if (wanted_inner_mode
!= VOIDmode
7277 && inner_mode
!= wanted_inner_mode
7279 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7281 && ! mode_dependent_address_p (XEXP (inner
, 0))
7282 && ! MEM_VOLATILE_P (inner
))
7286 /* The computations below will be correct if the machine is big
7287 endian in both bits and bytes or little endian in bits and bytes.
7288 If it is mixed, we must adjust. */
7290 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7291 adjust OFFSET to compensate. */
7292 if (BYTES_BIG_ENDIAN
7293 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7294 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7296 /* We can now move to the desired byte. */
7297 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7298 * GET_MODE_SIZE (wanted_inner_mode
);
7299 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7301 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7302 && is_mode
!= wanted_inner_mode
)
7303 offset
= (GET_MODE_SIZE (is_mode
)
7304 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7306 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7309 /* If INNER is not memory, get it into the proper mode. If we are changing
7310 its mode, POS must be a constant and smaller than the size of the new
7312 else if (!MEM_P (inner
))
7314 /* On the LHS, don't create paradoxical subregs implicitely truncating
7315 the register unless TRULY_NOOP_TRUNCATION. */
7317 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner
)),
7318 GET_MODE_BITSIZE (wanted_inner_mode
)))
7321 if (GET_MODE (inner
) != wanted_inner_mode
7323 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7329 inner
= force_to_mode (inner
, wanted_inner_mode
,
7331 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7332 ? ~(unsigned HOST_WIDE_INT
) 0
7333 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7338 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7339 have to zero extend. Otherwise, we can just use a SUBREG. */
7341 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7343 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
7345 /* If we know that no extraneous bits are set, and that the high
7346 bit is not set, convert extraction to cheaper one - either
7347 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7349 if (flag_expensive_optimizations
7350 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
7351 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7352 & ~(((unsigned HOST_WIDE_INT
)
7353 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7357 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
7359 /* Prefer ZERO_EXTENSION, since it gives more information to
7361 if (rtx_cost (temp1
, SET
, optimize_this_for_speed_p
)
7362 < rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
7367 else if (pos_rtx
!= 0
7368 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7369 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
7371 /* Make POS_RTX unless we already have it and it is correct. If we don't
7372 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7374 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7375 pos_rtx
= orig_pos_rtx
;
7377 else if (pos_rtx
== 0)
7378 pos_rtx
= GEN_INT (pos
);
7380 /* Make the required operation. See if we can use existing rtx. */
7381 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7382 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7384 new_rtx
= gen_lowpart (mode
, new_rtx
);
7389 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7390 with any other operations in X. Return X without that shift if so. */
7393 extract_left_shift (rtx x
, int count
)
7395 enum rtx_code code
= GET_CODE (x
);
7396 enum machine_mode mode
= GET_MODE (x
);
7402 /* This is the shift itself. If it is wide enough, we will return
7403 either the value being shifted if the shift count is equal to
7404 COUNT or a shift for the difference. */
7405 if (CONST_INT_P (XEXP (x
, 1))
7406 && INTVAL (XEXP (x
, 1)) >= count
)
7407 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7408 INTVAL (XEXP (x
, 1)) - count
);
7412 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7413 return simplify_gen_unary (code
, mode
, tem
, mode
);
7417 case PLUS
: case IOR
: case XOR
: case AND
:
7418 /* If we can safely shift this constant and we find the inner shift,
7419 make a new operation. */
7420 if (CONST_INT_P (XEXP (x
, 1))
7421 && (UINTVAL (XEXP (x
, 1))
7422 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7423 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7424 return simplify_gen_binary (code
, mode
, tem
,
7425 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7436 /* Look at the expression rooted at X. Look for expressions
7437 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7438 Form these expressions.
7440 Return the new rtx, usually just X.
7442 Also, for machines like the VAX that don't have logical shift insns,
7443 try to convert logical to arithmetic shift operations in cases where
7444 they are equivalent. This undoes the canonicalizations to logical
7445 shifts done elsewhere.
7447 We try, as much as possible, to re-use rtl expressions to save memory.
7449 IN_CODE says what kind of expression we are processing. Normally, it is
7450 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7451 being kludges), it is MEM. When processing the arguments of a comparison
7452 or a COMPARE against zero, it is COMPARE. */
7455 make_compound_operation (rtx x
, enum rtx_code in_code
)
7457 enum rtx_code code
= GET_CODE (x
);
7458 enum machine_mode mode
= GET_MODE (x
);
7459 int mode_width
= GET_MODE_BITSIZE (mode
);
7461 enum rtx_code next_code
;
7467 /* Select the code to be used in recursive calls. Once we are inside an
7468 address, we stay there. If we have a comparison, set to COMPARE,
7469 but once inside, go back to our default of SET. */
7471 next_code
= (code
== MEM
? MEM
7472 : ((code
== PLUS
|| code
== MINUS
)
7473 && SCALAR_INT_MODE_P (mode
)) ? MEM
7474 : ((code
== COMPARE
|| COMPARISON_P (x
))
7475 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7476 : in_code
== COMPARE
? SET
: in_code
);
7478 /* Process depending on the code of this operation. If NEW is set
7479 nonzero, it will be returned. */
7484 /* Convert shifts by constants into multiplications if inside
7486 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7487 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7488 && INTVAL (XEXP (x
, 1)) >= 0
7489 && SCALAR_INT_MODE_P (mode
))
7491 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7492 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7494 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7495 if (GET_CODE (new_rtx
) == NEG
)
7497 new_rtx
= XEXP (new_rtx
, 0);
7500 multval
= trunc_int_for_mode (multval
, mode
);
7501 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, GEN_INT (multval
));
7508 lhs
= make_compound_operation (lhs
, next_code
);
7509 rhs
= make_compound_operation (rhs
, next_code
);
7510 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7511 && SCALAR_INT_MODE_P (mode
))
7513 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7515 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7517 else if (GET_CODE (lhs
) == MULT
7518 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7520 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7521 simplify_gen_unary (NEG
, mode
,
7524 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7528 SUBST (XEXP (x
, 0), lhs
);
7529 SUBST (XEXP (x
, 1), rhs
);
7532 x
= gen_lowpart (mode
, new_rtx
);
7538 lhs
= make_compound_operation (lhs
, next_code
);
7539 rhs
= make_compound_operation (rhs
, next_code
);
7540 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7541 && SCALAR_INT_MODE_P (mode
))
7543 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7545 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7547 else if (GET_CODE (rhs
) == MULT
7548 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7550 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7551 simplify_gen_unary (NEG
, mode
,
7554 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7558 SUBST (XEXP (x
, 0), lhs
);
7559 SUBST (XEXP (x
, 1), rhs
);
7562 return gen_lowpart (mode
, new_rtx
);
7565 /* If the second operand is not a constant, we can't do anything
7567 if (!CONST_INT_P (XEXP (x
, 1)))
7570 /* If the constant is a power of two minus one and the first operand
7571 is a logical right shift, make an extraction. */
7572 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7573 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7575 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7576 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7577 0, in_code
== COMPARE
);
7580 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7581 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7582 && subreg_lowpart_p (XEXP (x
, 0))
7583 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7584 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7586 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7588 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7589 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7590 0, in_code
== COMPARE
);
7592 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7593 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7594 || GET_CODE (XEXP (x
, 0)) == IOR
)
7595 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7596 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7597 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7599 /* Apply the distributive law, and then try to make extractions. */
7600 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7601 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7603 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7605 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7608 /* If we are have (and (rotate X C) M) and C is larger than the number
7609 of bits in M, this is an extraction. */
7611 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7612 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7613 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7614 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7616 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7617 new_rtx
= make_extraction (mode
, new_rtx
,
7618 (GET_MODE_BITSIZE (mode
)
7619 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7620 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7623 /* On machines without logical shifts, if the operand of the AND is
7624 a logical shift and our mask turns off all the propagated sign
7625 bits, we can replace the logical shift with an arithmetic shift. */
7626 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7627 && !have_insn_for (LSHIFTRT
, mode
)
7628 && have_insn_for (ASHIFTRT
, mode
)
7629 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7630 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7631 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7632 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7634 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7636 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7637 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7639 gen_rtx_ASHIFTRT (mode
,
7640 make_compound_operation
7641 (XEXP (XEXP (x
, 0), 0), next_code
),
7642 XEXP (XEXP (x
, 0), 1)));
7645 /* If the constant is one less than a power of two, this might be
7646 representable by an extraction even if no shift is present.
7647 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7648 we are in a COMPARE. */
7649 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7650 new_rtx
= make_extraction (mode
,
7651 make_compound_operation (XEXP (x
, 0),
7653 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7655 /* If we are in a comparison and this is an AND with a power of two,
7656 convert this into the appropriate bit extract. */
7657 else if (in_code
== COMPARE
7658 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7659 new_rtx
= make_extraction (mode
,
7660 make_compound_operation (XEXP (x
, 0),
7662 i
, NULL_RTX
, 1, 1, 0, 1);
7667 /* If the sign bit is known to be zero, replace this with an
7668 arithmetic shift. */
7669 if (have_insn_for (ASHIFTRT
, mode
)
7670 && ! have_insn_for (LSHIFTRT
, mode
)
7671 && mode_width
<= HOST_BITS_PER_WIDE_INT
7672 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7674 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7675 make_compound_operation (XEXP (x
, 0),
7681 /* ... fall through ... */
7687 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7688 this is a SIGN_EXTRACT. */
7689 if (CONST_INT_P (rhs
)
7690 && GET_CODE (lhs
) == ASHIFT
7691 && CONST_INT_P (XEXP (lhs
, 1))
7692 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7693 && INTVAL (rhs
) < mode_width
)
7695 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7696 new_rtx
= make_extraction (mode
, new_rtx
,
7697 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7698 NULL_RTX
, mode_width
- INTVAL (rhs
),
7699 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7703 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7704 If so, try to merge the shifts into a SIGN_EXTEND. We could
7705 also do this for some cases of SIGN_EXTRACT, but it doesn't
7706 seem worth the effort; the case checked for occurs on Alpha. */
7709 && ! (GET_CODE (lhs
) == SUBREG
7710 && (OBJECT_P (SUBREG_REG (lhs
))))
7711 && CONST_INT_P (rhs
)
7712 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7713 && INTVAL (rhs
) < mode_width
7714 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7715 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7716 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7717 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7722 /* Call ourselves recursively on the inner expression. If we are
7723 narrowing the object and it has a different RTL code from
7724 what it originally did, do this SUBREG as a force_to_mode. */
7726 rtx inner
= SUBREG_REG (x
), simplified
;
7728 tem
= make_compound_operation (inner
, in_code
);
7731 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7735 if (GET_CODE (tem
) != GET_CODE (inner
)
7736 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7737 && subreg_lowpart_p (x
))
7740 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7742 /* If we have something other than a SUBREG, we might have
7743 done an expansion, so rerun ourselves. */
7744 if (GET_CODE (newer
) != SUBREG
)
7745 newer
= make_compound_operation (newer
, in_code
);
7747 /* force_to_mode can expand compounds. If it just re-expanded the
7748 compound, use gen_lowpart to convert to the desired mode. */
7749 if (rtx_equal_p (newer
, x
)
7750 /* Likewise if it re-expanded the compound only partially.
7751 This happens for SUBREG of ZERO_EXTRACT if they extract
7752 the same number of bits. */
7753 || (GET_CODE (newer
) == SUBREG
7754 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7755 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7756 && GET_CODE (inner
) == AND
7757 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7758 return gen_lowpart (GET_MODE (x
), tem
);
7774 x
= gen_lowpart (mode
, new_rtx
);
7775 code
= GET_CODE (x
);
7778 /* Now recursively process each operand of this operation. */
7779 fmt
= GET_RTX_FORMAT (code
);
7780 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7783 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7784 SUBST (XEXP (x
, i
), new_rtx
);
7786 else if (fmt
[i
] == 'E')
7787 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7789 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7790 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7794 /* If this is a commutative operation, the changes to the operands
7795 may have made it noncanonical. */
7796 if (COMMUTATIVE_ARITH_P (x
)
7797 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7800 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7801 SUBST (XEXP (x
, 1), tem
);
7807 /* Given M see if it is a value that would select a field of bits
7808 within an item, but not the entire word. Return -1 if not.
7809 Otherwise, return the starting position of the field, where 0 is the
7812 *PLEN is set to the length of the field. */
7815 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7817 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7818 int pos
= m
? ctz_hwi (m
) : -1;
7822 /* Now shift off the low-order zero bits and see if we have a
7823 power of two minus 1. */
7824 len
= exact_log2 ((m
>> pos
) + 1);
7833 /* If X refers to a register that equals REG in value, replace these
7834 references with REG. */
7836 canon_reg_for_combine (rtx x
, rtx reg
)
7843 enum rtx_code code
= GET_CODE (x
);
7844 switch (GET_RTX_CLASS (code
))
7847 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7848 if (op0
!= XEXP (x
, 0))
7849 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7854 case RTX_COMM_ARITH
:
7855 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7856 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7857 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7858 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7862 case RTX_COMM_COMPARE
:
7863 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7864 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7865 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7866 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7867 GET_MODE (op0
), op0
, op1
);
7871 case RTX_BITFIELD_OPS
:
7872 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7873 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7874 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7875 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7876 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7877 GET_MODE (op0
), op0
, op1
, op2
);
7882 if (rtx_equal_p (get_last_value (reg
), x
)
7883 || rtx_equal_p (reg
, get_last_value (x
)))
7892 fmt
= GET_RTX_FORMAT (code
);
7894 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7897 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7898 if (op
!= XEXP (x
, i
))
7908 else if (fmt
[i
] == 'E')
7911 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7913 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7914 if (op
!= XVECEXP (x
, i
, j
))
7921 XVECEXP (x
, i
, j
) = op
;
7932 /* Return X converted to MODE. If the value is already truncated to
7933 MODE we can just return a subreg even though in the general case we
7934 would need an explicit truncation. */
7937 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7939 if (!CONST_INT_P (x
)
7940 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7941 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
7942 GET_MODE_BITSIZE (GET_MODE (x
)))
7943 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7945 /* Bit-cast X into an integer mode. */
7946 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7947 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7948 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7952 return gen_lowpart (mode
, x
);
7955 /* See if X can be simplified knowing that we will only refer to it in
7956 MODE and will only refer to those bits that are nonzero in MASK.
7957 If other bits are being computed or if masking operations are done
7958 that select a superset of the bits in MASK, they can sometimes be
7961 Return a possibly simplified expression, but always convert X to
7962 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7964 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7965 are all off in X. This is used when X will be complemented, by either
7966 NOT, NEG, or XOR. */
7969 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7972 enum rtx_code code
= GET_CODE (x
);
7973 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7974 enum machine_mode op_mode
;
7975 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7978 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7979 code below will do the wrong thing since the mode of such an
7980 expression is VOIDmode.
7982 Also do nothing if X is a CLOBBER; this can happen if X was
7983 the return value from a call to gen_lowpart. */
7984 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7987 /* We want to perform the operation is its present mode unless we know
7988 that the operation is valid in MODE, in which case we do the operation
7990 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
7991 && have_insn_for (code
, mode
))
7992 ? mode
: GET_MODE (x
));
7994 /* It is not valid to do a right-shift in a narrower mode
7995 than the one it came in with. */
7996 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
7997 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
7998 op_mode
= GET_MODE (x
);
8000 /* Truncate MASK to fit OP_MODE. */
8002 mask
&= GET_MODE_MASK (op_mode
);
8004 /* When we have an arithmetic operation, or a shift whose count we
8005 do not know, we need to assume that all bits up to the highest-order
8006 bit in MASK will be needed. This is how we form such a mask. */
8007 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8008 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8010 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8013 /* Determine what bits of X are guaranteed to be (non)zero. */
8014 nonzero
= nonzero_bits (x
, mode
);
8016 /* If none of the bits in X are needed, return a zero. */
8017 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8020 /* If X is a CONST_INT, return a new one. Do this here since the
8021 test below will fail. */
8022 if (CONST_INT_P (x
))
8024 if (SCALAR_INT_MODE_P (mode
))
8025 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8028 x
= GEN_INT (INTVAL (x
) & mask
);
8029 return gen_lowpart_common (mode
, x
);
8033 /* If X is narrower than MODE and we want all the bits in X's mode, just
8034 get X in the proper mode. */
8035 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8036 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8037 return gen_lowpart (mode
, x
);
8039 /* We can ignore the effect of a SUBREG if it narrows the mode or
8040 if the constant masks to zero all the bits the mode doesn't have. */
8041 if (GET_CODE (x
) == SUBREG
8042 && subreg_lowpart_p (x
)
8043 && ((GET_MODE_SIZE (GET_MODE (x
))
8044 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8046 & GET_MODE_MASK (GET_MODE (x
))
8047 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8048 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8050 /* The arithmetic simplifications here only work for scalar integer modes. */
8051 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8052 return gen_lowpart_or_truncate (mode
, x
);
8057 /* If X is a (clobber (const_int)), return it since we know we are
8058 generating something that won't match. */
8065 x
= expand_compound_operation (x
);
8066 if (GET_CODE (x
) != code
)
8067 return force_to_mode (x
, mode
, mask
, next_select
);
8071 /* Similarly for a truncate. */
8072 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8075 /* If this is an AND with a constant, convert it into an AND
8076 whose constant is the AND of that constant with MASK. If it
8077 remains an AND of MASK, delete it since it is redundant. */
8079 if (CONST_INT_P (XEXP (x
, 1)))
8081 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8082 mask
& INTVAL (XEXP (x
, 1)));
8084 /* If X is still an AND, see if it is an AND with a mask that
8085 is just some low-order bits. If so, and it is MASK, we don't
8088 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8089 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8093 /* If it remains an AND, try making another AND with the bits
8094 in the mode mask that aren't in MASK turned on. If the
8095 constant in the AND is wide enough, this might make a
8096 cheaper constant. */
8098 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8099 && GET_MODE_MASK (GET_MODE (x
)) != mask
8100 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
8102 unsigned HOST_WIDE_INT cval
8103 = UINTVAL (XEXP (x
, 1))
8104 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8105 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
8108 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8109 number, sign extend it. */
8110 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8111 && (cval
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8112 cval
|= (unsigned HOST_WIDE_INT
) -1 << width
;
8114 y
= simplify_gen_binary (AND
, GET_MODE (x
),
8115 XEXP (x
, 0), GEN_INT (cval
));
8116 if (rtx_cost (y
, SET
, optimize_this_for_speed_p
)
8117 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
8127 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8128 low-order bits (as in an alignment operation) and FOO is already
8129 aligned to that boundary, mask C1 to that boundary as well.
8130 This may eliminate that PLUS and, later, the AND. */
8133 unsigned int width
= GET_MODE_BITSIZE (mode
);
8134 unsigned HOST_WIDE_INT smask
= mask
;
8136 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8137 number, sign extend it. */
8139 if (width
< HOST_BITS_PER_WIDE_INT
8140 && (smask
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8141 smask
|= (unsigned HOST_WIDE_INT
) (-1) << width
;
8143 if (CONST_INT_P (XEXP (x
, 1))
8144 && exact_log2 (- smask
) >= 0
8145 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8146 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8147 return force_to_mode (plus_constant (XEXP (x
, 0),
8148 (INTVAL (XEXP (x
, 1)) & smask
)),
8149 mode
, smask
, next_select
);
8152 /* ... fall through ... */
8155 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8156 most significant bit in MASK since carries from those bits will
8157 affect the bits we are interested in. */
8162 /* If X is (minus C Y) where C's least set bit is larger than any bit
8163 in the mask, then we may replace with (neg Y). */
8164 if (CONST_INT_P (XEXP (x
, 0))
8165 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8166 & -INTVAL (XEXP (x
, 0))))
8169 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8171 return force_to_mode (x
, mode
, mask
, next_select
);
8174 /* Similarly, if C contains every bit in the fuller_mask, then we may
8175 replace with (not Y). */
8176 if (CONST_INT_P (XEXP (x
, 0))
8177 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8179 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8180 XEXP (x
, 1), GET_MODE (x
));
8181 return force_to_mode (x
, mode
, mask
, next_select
);
8189 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8190 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8191 operation which may be a bitfield extraction. Ensure that the
8192 constant we form is not wider than the mode of X. */
8194 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8195 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8196 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8197 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8198 && CONST_INT_P (XEXP (x
, 1))
8199 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8200 + floor_log2 (INTVAL (XEXP (x
, 1))))
8201 < GET_MODE_BITSIZE (GET_MODE (x
)))
8202 && (UINTVAL (XEXP (x
, 1))
8203 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8205 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
8206 << INTVAL (XEXP (XEXP (x
, 0), 1)));
8207 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8208 XEXP (XEXP (x
, 0), 0), temp
);
8209 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8210 XEXP (XEXP (x
, 0), 1));
8211 return force_to_mode (x
, mode
, mask
, next_select
);
8215 /* For most binary operations, just propagate into the operation and
8216 change the mode if we have an operation of that mode. */
8218 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8219 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8221 /* If we ended up truncating both operands, truncate the result of the
8222 operation instead. */
8223 if (GET_CODE (op0
) == TRUNCATE
8224 && GET_CODE (op1
) == TRUNCATE
)
8226 op0
= XEXP (op0
, 0);
8227 op1
= XEXP (op1
, 0);
8230 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8231 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8233 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8234 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8238 /* For left shifts, do the same, but just for the first operand.
8239 However, we cannot do anything with shifts where we cannot
8240 guarantee that the counts are smaller than the size of the mode
8241 because such a count will have a different meaning in a
8244 if (! (CONST_INT_P (XEXP (x
, 1))
8245 && INTVAL (XEXP (x
, 1)) >= 0
8246 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
8247 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8248 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8249 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
8252 /* If the shift count is a constant and we can do arithmetic in
8253 the mode of the shift, refine which bits we need. Otherwise, use the
8254 conservative form of the mask. */
8255 if (CONST_INT_P (XEXP (x
, 1))
8256 && INTVAL (XEXP (x
, 1)) >= 0
8257 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
8258 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
8259 mask
>>= INTVAL (XEXP (x
, 1));
8263 op0
= gen_lowpart_or_truncate (op_mode
,
8264 force_to_mode (XEXP (x
, 0), op_mode
,
8265 mask
, next_select
));
8267 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8268 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8272 /* Here we can only do something if the shift count is a constant,
8273 this shift constant is valid for the host, and we can do arithmetic
8276 if (CONST_INT_P (XEXP (x
, 1))
8277 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8278 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
8280 rtx inner
= XEXP (x
, 0);
8281 unsigned HOST_WIDE_INT inner_mask
;
8283 /* Select the mask of the bits we need for the shift operand. */
8284 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8286 /* We can only change the mode of the shift if we can do arithmetic
8287 in the mode of the shift and INNER_MASK is no wider than the
8288 width of X's mode. */
8289 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8290 op_mode
= GET_MODE (x
);
8292 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8294 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8295 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8298 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8299 shift and AND produces only copies of the sign bit (C2 is one less
8300 than a power of two), we can do this with just a shift. */
8302 if (GET_CODE (x
) == LSHIFTRT
8303 && CONST_INT_P (XEXP (x
, 1))
8304 /* The shift puts one of the sign bit copies in the least significant
8306 && ((INTVAL (XEXP (x
, 1))
8307 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8308 >= GET_MODE_BITSIZE (GET_MODE (x
)))
8309 && exact_log2 (mask
+ 1) >= 0
8310 /* Number of bits left after the shift must be more than the mask
8312 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8313 <= GET_MODE_BITSIZE (GET_MODE (x
)))
8314 /* Must be more sign bit copies than the mask needs. */
8315 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8316 >= exact_log2 (mask
+ 1)))
8317 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8318 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
8319 - exact_log2 (mask
+ 1)));
8324 /* If we are just looking for the sign bit, we don't need this shift at
8325 all, even if it has a variable count. */
8326 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8327 && (mask
== ((unsigned HOST_WIDE_INT
) 1
8328 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8329 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8331 /* If this is a shift by a constant, get a mask that contains those bits
8332 that are not copies of the sign bit. We then have two cases: If
8333 MASK only includes those bits, this can be a logical shift, which may
8334 allow simplifications. If MASK is a single-bit field not within
8335 those bits, we are requesting a copy of the sign bit and hence can
8336 shift the sign bit to the appropriate location. */
8338 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8339 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8343 /* If the considered data is wider than HOST_WIDE_INT, we can't
8344 represent a mask for all its bits in a single scalar.
8345 But we only care about the lower bits, so calculate these. */
8347 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8349 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8351 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8352 is the number of bits a full-width mask would have set.
8353 We need only shift if these are fewer than nonzero can
8354 hold. If not, we must keep all bits set in nonzero. */
8356 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8357 < HOST_BITS_PER_WIDE_INT
)
8358 nonzero
>>= INTVAL (XEXP (x
, 1))
8359 + HOST_BITS_PER_WIDE_INT
8360 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
8364 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8365 nonzero
>>= INTVAL (XEXP (x
, 1));
8368 if ((mask
& ~nonzero
) == 0)
8370 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8371 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8372 if (GET_CODE (x
) != ASHIFTRT
)
8373 return force_to_mode (x
, mode
, mask
, next_select
);
8376 else if ((i
= exact_log2 (mask
)) >= 0)
8378 x
= simplify_shift_const
8379 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8380 GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
8382 if (GET_CODE (x
) != ASHIFTRT
)
8383 return force_to_mode (x
, mode
, mask
, next_select
);
8387 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8388 even if the shift count isn't a constant. */
8390 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8391 XEXP (x
, 0), XEXP (x
, 1));
8395 /* If this is a zero- or sign-extension operation that just affects bits
8396 we don't care about, remove it. Be sure the call above returned
8397 something that is still a shift. */
8399 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8400 && CONST_INT_P (XEXP (x
, 1))
8401 && INTVAL (XEXP (x
, 1)) >= 0
8402 && (INTVAL (XEXP (x
, 1))
8403 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8404 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8405 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8406 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8413 /* If the shift count is constant and we can do computations
8414 in the mode of X, compute where the bits we care about are.
8415 Otherwise, we can't do anything. Don't change the mode of
8416 the shift or propagate MODE into the shift, though. */
8417 if (CONST_INT_P (XEXP (x
, 1))
8418 && INTVAL (XEXP (x
, 1)) >= 0)
8420 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8421 GET_MODE (x
), GEN_INT (mask
),
8423 if (temp
&& CONST_INT_P (temp
))
8425 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8426 INTVAL (temp
), next_select
));
8431 /* If we just want the low-order bit, the NEG isn't needed since it
8432 won't change the low-order bit. */
8434 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8436 /* We need any bits less significant than the most significant bit in
8437 MASK since carries from those bits will affect the bits we are
8443 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8444 same as the XOR case above. Ensure that the constant we form is not
8445 wider than the mode of X. */
8447 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8448 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8449 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8450 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8451 < GET_MODE_BITSIZE (GET_MODE (x
)))
8452 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8454 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8456 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8457 XEXP (XEXP (x
, 0), 0), temp
);
8458 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8459 temp
, XEXP (XEXP (x
, 0), 1));
8461 return force_to_mode (x
, mode
, mask
, next_select
);
8464 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8465 use the full mask inside the NOT. */
8469 op0
= gen_lowpart_or_truncate (op_mode
,
8470 force_to_mode (XEXP (x
, 0), mode
, mask
,
8472 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8473 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8477 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8478 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8479 which is equal to STORE_FLAG_VALUE. */
8480 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8481 && XEXP (x
, 1) == const0_rtx
8482 && GET_MODE (XEXP (x
, 0)) == mode
8483 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8484 && (nonzero_bits (XEXP (x
, 0), mode
)
8485 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8486 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8491 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8492 written in a narrower mode. We play it safe and do not do so. */
8495 gen_lowpart_or_truncate (GET_MODE (x
),
8496 force_to_mode (XEXP (x
, 1), mode
,
8497 mask
, next_select
)));
8499 gen_lowpart_or_truncate (GET_MODE (x
),
8500 force_to_mode (XEXP (x
, 2), mode
,
8501 mask
, next_select
)));
8508 /* Ensure we return a value of the proper mode. */
8509 return gen_lowpart_or_truncate (mode
, x
);
8512 /* Return nonzero if X is an expression that has one of two values depending on
8513 whether some other value is zero or nonzero. In that case, we return the
8514 value that is being tested, *PTRUE is set to the value if the rtx being
8515 returned has a nonzero value, and *PFALSE is set to the other alternative.
8517 If we return zero, we set *PTRUE and *PFALSE to X. */
8520 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8522 enum machine_mode mode
= GET_MODE (x
);
8523 enum rtx_code code
= GET_CODE (x
);
8524 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8525 unsigned HOST_WIDE_INT nz
;
8527 /* If we are comparing a value against zero, we are done. */
8528 if ((code
== NE
|| code
== EQ
)
8529 && XEXP (x
, 1) == const0_rtx
)
8531 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8532 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8536 /* If this is a unary operation whose operand has one of two values, apply
8537 our opcode to compute those values. */
8538 else if (UNARY_P (x
)
8539 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8541 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8542 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8543 GET_MODE (XEXP (x
, 0)));
8547 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8548 make can't possibly match and would suppress other optimizations. */
8549 else if (code
== COMPARE
)
8552 /* If this is a binary operation, see if either side has only one of two
8553 values. If either one does or if both do and they are conditional on
8554 the same value, compute the new true and false values. */
8555 else if (BINARY_P (x
))
8557 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8558 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8560 if ((cond0
!= 0 || cond1
!= 0)
8561 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8563 /* If if_then_else_cond returned zero, then true/false are the
8564 same rtl. We must copy one of them to prevent invalid rtl
8567 true0
= copy_rtx (true0
);
8568 else if (cond1
== 0)
8569 true1
= copy_rtx (true1
);
8571 if (COMPARISON_P (x
))
8573 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8575 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8580 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8581 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8584 return cond0
? cond0
: cond1
;
8587 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8588 operands is zero when the other is nonzero, and vice-versa,
8589 and STORE_FLAG_VALUE is 1 or -1. */
8591 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8592 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8594 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8596 rtx op0
= XEXP (XEXP (x
, 0), 1);
8597 rtx op1
= XEXP (XEXP (x
, 1), 1);
8599 cond0
= XEXP (XEXP (x
, 0), 0);
8600 cond1
= XEXP (XEXP (x
, 1), 0);
8602 if (COMPARISON_P (cond0
)
8603 && COMPARISON_P (cond1
)
8604 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8605 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8606 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8607 || ((swap_condition (GET_CODE (cond0
))
8608 == reversed_comparison_code (cond1
, NULL
))
8609 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8610 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8611 && ! side_effects_p (x
))
8613 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8614 *pfalse
= simplify_gen_binary (MULT
, mode
,
8616 ? simplify_gen_unary (NEG
, mode
,
8624 /* Similarly for MULT, AND and UMIN, except that for these the result
8626 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8627 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8628 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8630 cond0
= XEXP (XEXP (x
, 0), 0);
8631 cond1
= XEXP (XEXP (x
, 1), 0);
8633 if (COMPARISON_P (cond0
)
8634 && COMPARISON_P (cond1
)
8635 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8636 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8637 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8638 || ((swap_condition (GET_CODE (cond0
))
8639 == reversed_comparison_code (cond1
, NULL
))
8640 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8641 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8642 && ! side_effects_p (x
))
8644 *ptrue
= *pfalse
= const0_rtx
;
8650 else if (code
== IF_THEN_ELSE
)
8652 /* If we have IF_THEN_ELSE already, extract the condition and
8653 canonicalize it if it is NE or EQ. */
8654 cond0
= XEXP (x
, 0);
8655 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8656 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8657 return XEXP (cond0
, 0);
8658 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8660 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8661 return XEXP (cond0
, 0);
8667 /* If X is a SUBREG, we can narrow both the true and false values
8668 if the inner expression, if there is a condition. */
8669 else if (code
== SUBREG
8670 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8673 true0
= simplify_gen_subreg (mode
, true0
,
8674 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8675 false0
= simplify_gen_subreg (mode
, false0
,
8676 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8677 if (true0
&& false0
)
8685 /* If X is a constant, this isn't special and will cause confusions
8686 if we treat it as such. Likewise if it is equivalent to a constant. */
8687 else if (CONSTANT_P (x
)
8688 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8691 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8692 will be least confusing to the rest of the compiler. */
8693 else if (mode
== BImode
)
8695 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8699 /* If X is known to be either 0 or -1, those are the true and
8700 false values when testing X. */
8701 else if (x
== constm1_rtx
|| x
== const0_rtx
8702 || (mode
!= VOIDmode
8703 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
8705 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8709 /* Likewise for 0 or a single bit. */
8710 else if (SCALAR_INT_MODE_P (mode
)
8711 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8712 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8714 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8718 /* Otherwise fail; show no condition with true and false values the same. */
8719 *ptrue
= *pfalse
= x
;
8723 /* Return the value of expression X given the fact that condition COND
8724 is known to be true when applied to REG as its first operand and VAL
8725 as its second. X is known to not be shared and so can be modified in
8728 We only handle the simplest cases, and specifically those cases that
8729 arise with IF_THEN_ELSE expressions. */
8732 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8734 enum rtx_code code
= GET_CODE (x
);
8739 if (side_effects_p (x
))
8742 /* If either operand of the condition is a floating point value,
8743 then we have to avoid collapsing an EQ comparison. */
8745 && rtx_equal_p (x
, reg
)
8746 && ! FLOAT_MODE_P (GET_MODE (x
))
8747 && ! FLOAT_MODE_P (GET_MODE (val
)))
8750 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8753 /* If X is (abs REG) and we know something about REG's relationship
8754 with zero, we may be able to simplify this. */
8756 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8759 case GE
: case GT
: case EQ
:
8762 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8764 GET_MODE (XEXP (x
, 0)));
8769 /* The only other cases we handle are MIN, MAX, and comparisons if the
8770 operands are the same as REG and VAL. */
8772 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8774 if (rtx_equal_p (XEXP (x
, 0), val
))
8775 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8777 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8779 if (COMPARISON_P (x
))
8781 if (comparison_dominates_p (cond
, code
))
8782 return const_true_rtx
;
8784 code
= reversed_comparison_code (x
, NULL
);
8786 && comparison_dominates_p (cond
, code
))
8791 else if (code
== SMAX
|| code
== SMIN
8792 || code
== UMIN
|| code
== UMAX
)
8794 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8796 /* Do not reverse the condition when it is NE or EQ.
8797 This is because we cannot conclude anything about
8798 the value of 'SMAX (x, y)' when x is not equal to y,
8799 but we can when x equals y. */
8800 if ((code
== SMAX
|| code
== UMAX
)
8801 && ! (cond
== EQ
|| cond
== NE
))
8802 cond
= reverse_condition (cond
);
8807 return unsignedp
? x
: XEXP (x
, 1);
8809 return unsignedp
? x
: XEXP (x
, 0);
8811 return unsignedp
? XEXP (x
, 1) : x
;
8813 return unsignedp
? XEXP (x
, 0) : x
;
8820 else if (code
== SUBREG
)
8822 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8823 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8825 if (SUBREG_REG (x
) != r
)
8827 /* We must simplify subreg here, before we lose track of the
8828 original inner_mode. */
8829 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8830 inner_mode
, SUBREG_BYTE (x
));
8834 SUBST (SUBREG_REG (x
), r
);
8839 /* We don't have to handle SIGN_EXTEND here, because even in the
8840 case of replacing something with a modeless CONST_INT, a
8841 CONST_INT is already (supposed to be) a valid sign extension for
8842 its narrower mode, which implies it's already properly
8843 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8844 story is different. */
8845 else if (code
== ZERO_EXTEND
)
8847 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8848 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8850 if (XEXP (x
, 0) != r
)
8852 /* We must simplify the zero_extend here, before we lose
8853 track of the original inner_mode. */
8854 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8859 SUBST (XEXP (x
, 0), r
);
8865 fmt
= GET_RTX_FORMAT (code
);
8866 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8869 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8870 else if (fmt
[i
] == 'E')
8871 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8872 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8879 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8880 assignment as a field assignment. */
8883 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8885 if (x
== y
|| rtx_equal_p (x
, y
))
8888 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8891 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8892 Note that all SUBREGs of MEM are paradoxical; otherwise they
8893 would have been rewritten. */
8894 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8895 && MEM_P (SUBREG_REG (y
))
8896 && rtx_equal_p (SUBREG_REG (y
),
8897 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8900 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8901 && MEM_P (SUBREG_REG (x
))
8902 && rtx_equal_p (SUBREG_REG (x
),
8903 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8906 /* We used to see if get_last_value of X and Y were the same but that's
8907 not correct. In one direction, we'll cause the assignment to have
8908 the wrong destination and in the case, we'll import a register into this
8909 insn that might have already have been dead. So fail if none of the
8910 above cases are true. */
8914 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8915 Return that assignment if so.
8917 We only handle the most common cases. */
8920 make_field_assignment (rtx x
)
8922 rtx dest
= SET_DEST (x
);
8923 rtx src
= SET_SRC (x
);
8928 unsigned HOST_WIDE_INT len
;
8930 enum machine_mode mode
;
8932 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8933 a clear of a one-bit field. We will have changed it to
8934 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8937 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8938 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8939 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8940 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8942 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8945 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8949 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8950 && subreg_lowpart_p (XEXP (src
, 0))
8951 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8952 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8953 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8954 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8955 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8956 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8958 assign
= make_extraction (VOIDmode
, dest
, 0,
8959 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8962 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8966 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8968 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8969 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8970 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8972 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8975 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8979 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8980 SRC is an AND with all bits of that field set, then we can discard
8982 if (GET_CODE (dest
) == ZERO_EXTRACT
8983 && CONST_INT_P (XEXP (dest
, 1))
8984 && GET_CODE (src
) == AND
8985 && CONST_INT_P (XEXP (src
, 1)))
8987 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
8988 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
8989 unsigned HOST_WIDE_INT ze_mask
;
8991 if (width
>= HOST_BITS_PER_WIDE_INT
)
8994 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
8996 /* Complete overlap. We can remove the source AND. */
8997 if ((and_mask
& ze_mask
) == ze_mask
)
8998 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9000 /* Partial overlap. We can reduce the source AND. */
9001 if ((and_mask
& ze_mask
) != and_mask
)
9003 mode
= GET_MODE (src
);
9004 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9005 gen_int_mode (and_mask
& ze_mask
, mode
));
9006 return gen_rtx_SET (VOIDmode
, dest
, src
);
9010 /* The other case we handle is assignments into a constant-position
9011 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9012 a mask that has all one bits except for a group of zero bits and
9013 OTHER is known to have zeros where C1 has ones, this is such an
9014 assignment. Compute the position and length from C1. Shift OTHER
9015 to the appropriate position, force it to the required mode, and
9016 make the extraction. Check for the AND in both operands. */
9018 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9021 rhs
= expand_compound_operation (XEXP (src
, 0));
9022 lhs
= expand_compound_operation (XEXP (src
, 1));
9024 if (GET_CODE (rhs
) == AND
9025 && CONST_INT_P (XEXP (rhs
, 1))
9026 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9027 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9028 else if (GET_CODE (lhs
) == AND
9029 && CONST_INT_P (XEXP (lhs
, 1))
9030 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9031 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9035 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9036 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
9037 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9038 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9041 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9045 /* The mode to use for the source is the mode of the assignment, or of
9046 what is inside a possible STRICT_LOW_PART. */
9047 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9048 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9050 /* Shift OTHER right POS places and make it the source, restricting it
9051 to the proper length and mode. */
9053 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9057 src
= force_to_mode (src
, mode
,
9058 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
9059 ? ~(unsigned HOST_WIDE_INT
) 0
9060 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9063 /* If SRC is masked by an AND that does not make a difference in
9064 the value being stored, strip it. */
9065 if (GET_CODE (assign
) == ZERO_EXTRACT
9066 && CONST_INT_P (XEXP (assign
, 1))
9067 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9068 && GET_CODE (src
) == AND
9069 && CONST_INT_P (XEXP (src
, 1))
9070 && UINTVAL (XEXP (src
, 1))
9071 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9072 src
= XEXP (src
, 0);
9074 return gen_rtx_SET (VOIDmode
, assign
, src
);
9077 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9081 apply_distributive_law (rtx x
)
9083 enum rtx_code code
= GET_CODE (x
);
9084 enum rtx_code inner_code
;
9085 rtx lhs
, rhs
, other
;
9088 /* Distributivity is not true for floating point as it can change the
9089 value. So we don't do it unless -funsafe-math-optimizations. */
9090 if (FLOAT_MODE_P (GET_MODE (x
))
9091 && ! flag_unsafe_math_optimizations
)
9094 /* The outer operation can only be one of the following: */
9095 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9096 && code
!= PLUS
&& code
!= MINUS
)
9102 /* If either operand is a primitive we can't do anything, so get out
9104 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9107 lhs
= expand_compound_operation (lhs
);
9108 rhs
= expand_compound_operation (rhs
);
9109 inner_code
= GET_CODE (lhs
);
9110 if (inner_code
!= GET_CODE (rhs
))
9113 /* See if the inner and outer operations distribute. */
9120 /* These all distribute except over PLUS. */
9121 if (code
== PLUS
|| code
== MINUS
)
9126 if (code
!= PLUS
&& code
!= MINUS
)
9131 /* This is also a multiply, so it distributes over everything. */
9135 /* Non-paradoxical SUBREGs distributes over all operations,
9136 provided the inner modes and byte offsets are the same, this
9137 is an extraction of a low-order part, we don't convert an fp
9138 operation to int or vice versa, this is not a vector mode,
9139 and we would not be converting a single-word operation into a
9140 multi-word operation. The latter test is not required, but
9141 it prevents generating unneeded multi-word operations. Some
9142 of the previous tests are redundant given the latter test,
9143 but are retained because they are required for correctness.
9145 We produce the result slightly differently in this case. */
9147 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
9148 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
9149 || ! subreg_lowpart_p (lhs
)
9150 || (GET_MODE_CLASS (GET_MODE (lhs
))
9151 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
9152 || (GET_MODE_SIZE (GET_MODE (lhs
))
9153 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
9154 || VECTOR_MODE_P (GET_MODE (lhs
))
9155 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
9156 /* Result might need to be truncated. Don't change mode if
9157 explicit truncation is needed. */
9158 || !TRULY_NOOP_TRUNCATION
9159 (GET_MODE_BITSIZE (GET_MODE (x
)),
9160 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs
)))))
9163 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
9164 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
9165 return gen_lowpart (GET_MODE (x
), tem
);
9171 /* Set LHS and RHS to the inner operands (A and B in the example
9172 above) and set OTHER to the common operand (C in the example).
9173 There is only one way to do this unless the inner operation is
9175 if (COMMUTATIVE_ARITH_P (lhs
)
9176 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9177 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9178 else if (COMMUTATIVE_ARITH_P (lhs
)
9179 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9180 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9181 else if (COMMUTATIVE_ARITH_P (lhs
)
9182 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9183 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9184 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9185 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9189 /* Form the new inner operation, seeing if it simplifies first. */
9190 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9192 /* There is one exception to the general way of distributing:
9193 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9194 if (code
== XOR
&& inner_code
== IOR
)
9197 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9200 /* We may be able to continuing distributing the result, so call
9201 ourselves recursively on the inner operation before forming the
9202 outer operation, which we return. */
9203 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9204 apply_distributive_law (tem
), other
);
9207 /* See if X is of the form (* (+ A B) C), and if so convert to
9208 (+ (* A C) (* B C)) and try to simplify.
9210 Most of the time, this results in no change. However, if some of
9211 the operands are the same or inverses of each other, simplifications
9214 For example, (and (ior A B) (not B)) can occur as the result of
9215 expanding a bit field assignment. When we apply the distributive
9216 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9217 which then simplifies to (and (A (not B))).
9219 Note that no checks happen on the validity of applying the inverse
9220 distributive law. This is pointless since we can do it in the
9221 few places where this routine is called.
9223 N is the index of the term that is decomposed (the arithmetic operation,
9224 i.e. (+ A B) in the first example above). !N is the index of the term that
9225 is distributed, i.e. of C in the first example above. */
9227 distribute_and_simplify_rtx (rtx x
, int n
)
9229 enum machine_mode mode
;
9230 enum rtx_code outer_code
, inner_code
;
9231 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9233 /* Distributivity is not true for floating point as it can change the
9234 value. So we don't do it unless -funsafe-math-optimizations. */
9235 if (FLOAT_MODE_P (GET_MODE (x
))
9236 && ! flag_unsafe_math_optimizations
)
9239 decomposed
= XEXP (x
, n
);
9240 if (!ARITHMETIC_P (decomposed
))
9243 mode
= GET_MODE (x
);
9244 outer_code
= GET_CODE (x
);
9245 distributed
= XEXP (x
, !n
);
9247 inner_code
= GET_CODE (decomposed
);
9248 inner_op0
= XEXP (decomposed
, 0);
9249 inner_op1
= XEXP (decomposed
, 1);
9251 /* Special case (and (xor B C) (not A)), which is equivalent to
9252 (xor (ior A B) (ior A C)) */
9253 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9255 distributed
= XEXP (distributed
, 0);
9261 /* Distribute the second term. */
9262 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9263 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9267 /* Distribute the first term. */
9268 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9269 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9272 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9274 if (GET_CODE (tmp
) != outer_code
9275 && rtx_cost (tmp
, SET
, optimize_this_for_speed_p
)
9276 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
9282 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9283 in MODE. Return an equivalent form, if different from (and VAROP
9284 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9287 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9288 unsigned HOST_WIDE_INT constop
)
9290 unsigned HOST_WIDE_INT nonzero
;
9291 unsigned HOST_WIDE_INT orig_constop
;
9296 orig_constop
= constop
;
9297 if (GET_CODE (varop
) == CLOBBER
)
9300 /* Simplify VAROP knowing that we will be only looking at some of the
9303 Note by passing in CONSTOP, we guarantee that the bits not set in
9304 CONSTOP are not significant and will never be examined. We must
9305 ensure that is the case by explicitly masking out those bits
9306 before returning. */
9307 varop
= force_to_mode (varop
, mode
, constop
, 0);
9309 /* If VAROP is a CLOBBER, we will fail so return it. */
9310 if (GET_CODE (varop
) == CLOBBER
)
9313 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9314 to VAROP and return the new constant. */
9315 if (CONST_INT_P (varop
))
9316 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9318 /* See what bits may be nonzero in VAROP. Unlike the general case of
9319 a call to nonzero_bits, here we don't care about bits outside
9322 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9324 /* Turn off all bits in the constant that are known to already be zero.
9325 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9326 which is tested below. */
9330 /* If we don't have any bits left, return zero. */
9334 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9335 a power of two, we can replace this with an ASHIFT. */
9336 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9337 && (i
= exact_log2 (constop
)) >= 0)
9338 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9340 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9341 or XOR, then try to apply the distributive law. This may eliminate
9342 operations if either branch can be simplified because of the AND.
9343 It may also make some cases more complex, but those cases probably
9344 won't match a pattern either with or without this. */
9346 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9350 apply_distributive_law
9351 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9352 simplify_and_const_int (NULL_RTX
,
9356 simplify_and_const_int (NULL_RTX
,
9361 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9362 the AND and see if one of the operands simplifies to zero. If so, we
9363 may eliminate it. */
9365 if (GET_CODE (varop
) == PLUS
9366 && exact_log2 (constop
+ 1) >= 0)
9370 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9371 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9372 if (o0
== const0_rtx
)
9374 if (o1
== const0_rtx
)
9378 /* Make a SUBREG if necessary. If we can't make it, fail. */
9379 varop
= gen_lowpart (mode
, varop
);
9380 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9383 /* If we are only masking insignificant bits, return VAROP. */
9384 if (constop
== nonzero
)
9387 if (varop
== orig_varop
&& constop
== orig_constop
)
9390 /* Otherwise, return an AND. */
9391 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9395 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9398 Return an equivalent form, if different from X. Otherwise, return X. If
9399 X is zero, we are to always construct the equivalent form. */
9402 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9403 unsigned HOST_WIDE_INT constop
)
9405 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9410 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9411 gen_int_mode (constop
, mode
));
9412 if (GET_MODE (x
) != mode
)
9413 x
= gen_lowpart (mode
, x
);
9417 /* Given a REG, X, compute which bits in X can be nonzero.
9418 We don't care about bits outside of those defined in MODE.
9420 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9421 a shift, AND, or zero_extract, we can do better. */
9424 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9425 const_rtx known_x ATTRIBUTE_UNUSED
,
9426 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9427 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9428 unsigned HOST_WIDE_INT
*nonzero
)
9433 /* If X is a register whose nonzero bits value is current, use it.
9434 Otherwise, if X is a register whose value we can find, use that
9435 value. Otherwise, use the previously-computed global nonzero bits
9436 for this register. */
9438 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9439 if (rsp
->last_set_value
!= 0
9440 && (rsp
->last_set_mode
== mode
9441 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9442 && GET_MODE_CLASS (mode
) == MODE_INT
))
9443 && ((rsp
->last_set_label
>= label_tick_ebb_start
9444 && rsp
->last_set_label
< label_tick
)
9445 || (rsp
->last_set_label
== label_tick
9446 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9447 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9448 && REG_N_SETS (REGNO (x
)) == 1
9450 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9452 *nonzero
&= rsp
->last_set_nonzero_bits
;
9456 tem
= get_last_value (x
);
9460 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9461 /* If X is narrower than MODE and TEM is a non-negative
9462 constant that would appear negative in the mode of X,
9463 sign-extend it for use in reg_nonzero_bits because some
9464 machines (maybe most) will actually do the sign-extension
9465 and this is the conservative approach.
9467 ??? For 2.5, try to tighten up the MD files in this regard
9468 instead of this kludge. */
9470 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
9471 && CONST_INT_P (tem
)
9473 && 0 != (UINTVAL (tem
)
9474 & ((unsigned HOST_WIDE_INT
) 1
9475 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
9476 tem
= GEN_INT (UINTVAL (tem
)
9477 | ((unsigned HOST_WIDE_INT
) (-1)
9478 << GET_MODE_BITSIZE (GET_MODE (x
))));
9482 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9484 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9486 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
9487 /* We don't know anything about the upper bits. */
9488 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9495 /* Return the number of bits at the high-order end of X that are known to
9496 be equal to the sign bit. X will be used in mode MODE; if MODE is
9497 VOIDmode, X will be used in its own mode. The returned value will always
9498 be between 1 and the number of bits in MODE. */
9501 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9502 const_rtx known_x ATTRIBUTE_UNUSED
,
9503 enum machine_mode known_mode
9505 unsigned int known_ret ATTRIBUTE_UNUSED
,
9506 unsigned int *result
)
9511 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9512 if (rsp
->last_set_value
!= 0
9513 && rsp
->last_set_mode
== mode
9514 && ((rsp
->last_set_label
>= label_tick_ebb_start
9515 && rsp
->last_set_label
< label_tick
)
9516 || (rsp
->last_set_label
== label_tick
9517 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9518 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9519 && REG_N_SETS (REGNO (x
)) == 1
9521 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9523 *result
= rsp
->last_set_sign_bit_copies
;
9527 tem
= get_last_value (x
);
9531 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9532 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
9533 *result
= rsp
->sign_bit_copies
;
9538 /* Return the number of "extended" bits there are in X, when interpreted
9539 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9540 unsigned quantities, this is the number of high-order zero bits.
9541 For signed quantities, this is the number of copies of the sign bit
9542 minus 1. In both case, this function returns the number of "spare"
9543 bits. For example, if two quantities for which this function returns
9544 at least 1 are added, the addition is known not to overflow.
9546 This function will always return 0 unless called during combine, which
9547 implies that it must be called from a define_split. */
9550 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9552 if (nonzero_sign_valid
== 0)
9556 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9557 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
9558 - floor_log2 (nonzero_bits (x
, mode
)))
9560 : num_sign_bit_copies (x
, mode
) - 1);
9563 /* This function is called from `simplify_shift_const' to merge two
9564 outer operations. Specifically, we have already found that we need
9565 to perform operation *POP0 with constant *PCONST0 at the outermost
9566 position. We would now like to also perform OP1 with constant CONST1
9567 (with *POP0 being done last).
9569 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9570 the resulting operation. *PCOMP_P is set to 1 if we would need to
9571 complement the innermost operand, otherwise it is unchanged.
9573 MODE is the mode in which the operation will be done. No bits outside
9574 the width of this mode matter. It is assumed that the width of this mode
9575 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9577 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9578 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9579 result is simply *PCONST0.
9581 If the resulting operation cannot be expressed as one operation, we
9582 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9585 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9587 enum rtx_code op0
= *pop0
;
9588 HOST_WIDE_INT const0
= *pconst0
;
9590 const0
&= GET_MODE_MASK (mode
);
9591 const1
&= GET_MODE_MASK (mode
);
9593 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9597 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9600 if (op1
== UNKNOWN
|| op0
== SET
)
9603 else if (op0
== UNKNOWN
)
9604 op0
= op1
, const0
= const1
;
9606 else if (op0
== op1
)
9630 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9631 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9634 /* If the two constants aren't the same, we can't do anything. The
9635 remaining six cases can all be done. */
9636 else if (const0
!= const1
)
9644 /* (a & b) | b == b */
9646 else /* op1 == XOR */
9647 /* (a ^ b) | b == a | b */
9653 /* (a & b) ^ b == (~a) & b */
9654 op0
= AND
, *pcomp_p
= 1;
9655 else /* op1 == IOR */
9656 /* (a | b) ^ b == a & ~b */
9657 op0
= AND
, const0
= ~const0
;
9662 /* (a | b) & b == b */
9664 else /* op1 == XOR */
9665 /* (a ^ b) & b) == (~a) & b */
9672 /* Check for NO-OP cases. */
9673 const0
&= GET_MODE_MASK (mode
);
9675 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9677 else if (const0
== 0 && op0
== AND
)
9679 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9685 /* ??? Slightly redundant with the above mask, but not entirely.
9686 Moving this above means we'd have to sign-extend the mode mask
9687 for the final test. */
9688 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9689 *pconst0
= trunc_int_for_mode (const0
, mode
);
9694 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9695 the shift in. The original shift operation CODE is performed on OP in
9696 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9697 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9698 result of the shift is subject to operation OUTER_CODE with operand
9701 static enum machine_mode
9702 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9703 enum machine_mode orig_mode
, enum machine_mode mode
,
9704 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9706 if (orig_mode
== mode
)
9708 gcc_assert (GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (orig_mode
));
9710 /* In general we can't perform in wider mode for right shift and rotate. */
9714 /* We can still widen if the bits brought in from the left are identical
9715 to the sign bit of ORIG_MODE. */
9716 if (num_sign_bit_copies (op
, mode
)
9717 > (unsigned) (GET_MODE_BITSIZE (mode
)
9718 - GET_MODE_BITSIZE (orig_mode
)))
9723 /* Similarly here but with zero bits. */
9724 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9725 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9728 /* We can also widen if the bits brought in will be masked off. This
9729 operation is performed in ORIG_MODE. */
9730 if (outer_code
== AND
)
9732 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9735 && GET_MODE_BITSIZE (orig_mode
) - care_bits
>= count
)
9751 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9752 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9753 simplify it. Otherwise, return a simplified value.
9755 The shift is normally computed in the widest mode we find in VAROP, as
9756 long as it isn't a different number of words than RESULT_MODE. Exceptions
9757 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9760 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9761 rtx varop
, int orig_count
)
9763 enum rtx_code orig_code
= code
;
9764 rtx orig_varop
= varop
;
9766 enum machine_mode mode
= result_mode
;
9767 enum machine_mode shift_mode
, tmode
;
9768 unsigned int mode_words
9769 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9770 /* We form (outer_op (code varop count) (outer_const)). */
9771 enum rtx_code outer_op
= UNKNOWN
;
9772 HOST_WIDE_INT outer_const
= 0;
9773 int complement_p
= 0;
9776 /* Make sure and truncate the "natural" shift on the way in. We don't
9777 want to do this inside the loop as it makes it more difficult to
9779 if (SHIFT_COUNT_TRUNCATED
)
9780 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9782 /* If we were given an invalid count, don't do anything except exactly
9783 what was requested. */
9785 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9790 /* Unless one of the branches of the `if' in this loop does a `continue',
9791 we will `break' the loop after the `if'. */
9795 /* If we have an operand of (clobber (const_int 0)), fail. */
9796 if (GET_CODE (varop
) == CLOBBER
)
9799 /* Convert ROTATERT to ROTATE. */
9800 if (code
== ROTATERT
)
9802 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9804 if (VECTOR_MODE_P (result_mode
))
9805 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9807 count
= bitsize
- count
;
9810 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9811 mode
, outer_op
, outer_const
);
9813 /* Handle cases where the count is greater than the size of the mode
9814 minus 1. For ASHIFT, use the size minus one as the count (this can
9815 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9816 take the count modulo the size. For other shifts, the result is
9819 Since these shifts are being produced by the compiler by combining
9820 multiple operations, each of which are defined, we know what the
9821 result is supposed to be. */
9823 if (count
> (GET_MODE_BITSIZE (shift_mode
) - 1))
9825 if (code
== ASHIFTRT
)
9826 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9827 else if (code
== ROTATE
|| code
== ROTATERT
)
9828 count
%= GET_MODE_BITSIZE (shift_mode
);
9831 /* We can't simply return zero because there may be an
9839 /* If we discovered we had to complement VAROP, leave. Making a NOT
9840 here would cause an infinite loop. */
9844 /* An arithmetic right shift of a quantity known to be -1 or 0
9846 if (code
== ASHIFTRT
9847 && (num_sign_bit_copies (varop
, shift_mode
)
9848 == GET_MODE_BITSIZE (shift_mode
)))
9854 /* If we are doing an arithmetic right shift and discarding all but
9855 the sign bit copies, this is equivalent to doing a shift by the
9856 bitsize minus one. Convert it into that shift because it will often
9857 allow other simplifications. */
9859 if (code
== ASHIFTRT
9860 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9861 >= GET_MODE_BITSIZE (shift_mode
)))
9862 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9864 /* We simplify the tests below and elsewhere by converting
9865 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9866 `make_compound_operation' will convert it to an ASHIFTRT for
9867 those machines (such as VAX) that don't have an LSHIFTRT. */
9868 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9870 && ((nonzero_bits (varop
, shift_mode
)
9871 & ((unsigned HOST_WIDE_INT
) 1
9872 << (GET_MODE_BITSIZE (shift_mode
) - 1))) == 0))
9875 if (((code
== LSHIFTRT
9876 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9877 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9879 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9880 && !((nonzero_bits (varop
, shift_mode
) << count
)
9881 & GET_MODE_MASK (shift_mode
))))
9882 && !side_effects_p (varop
))
9885 switch (GET_CODE (varop
))
9891 new_rtx
= expand_compound_operation (varop
);
9892 if (new_rtx
!= varop
)
9900 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9901 minus the width of a smaller mode, we can do this with a
9902 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9903 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9904 && ! mode_dependent_address_p (XEXP (varop
, 0))
9905 && ! MEM_VOLATILE_P (varop
)
9906 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9907 MODE_INT
, 1)) != BLKmode
)
9909 new_rtx
= adjust_address_nv (varop
, tmode
,
9910 BYTES_BIG_ENDIAN
? 0
9911 : count
/ BITS_PER_UNIT
);
9913 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9914 : ZERO_EXTEND
, mode
, new_rtx
);
9921 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9922 the same number of words as what we've seen so far. Then store
9923 the widest mode in MODE. */
9924 if (subreg_lowpart_p (varop
)
9925 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9926 > GET_MODE_SIZE (GET_MODE (varop
)))
9927 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9928 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9930 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9931 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9933 varop
= SUBREG_REG (varop
);
9934 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9935 mode
= GET_MODE (varop
);
9941 /* Some machines use MULT instead of ASHIFT because MULT
9942 is cheaper. But it is still better on those machines to
9943 merge two shifts into one. */
9944 if (CONST_INT_P (XEXP (varop
, 1))
9945 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9948 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9950 GEN_INT (exact_log2 (
9951 UINTVAL (XEXP (varop
, 1)))));
9957 /* Similar, for when divides are cheaper. */
9958 if (CONST_INT_P (XEXP (varop
, 1))
9959 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9962 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9964 GEN_INT (exact_log2 (
9965 UINTVAL (XEXP (varop
, 1)))));
9971 /* If we are extracting just the sign bit of an arithmetic
9972 right shift, that shift is not needed. However, the sign
9973 bit of a wider mode may be different from what would be
9974 interpreted as the sign bit in a narrower mode, so, if
9975 the result is narrower, don't discard the shift. */
9976 if (code
== LSHIFTRT
9977 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9978 && (GET_MODE_BITSIZE (result_mode
)
9979 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9981 varop
= XEXP (varop
, 0);
9985 /* ... fall through ... */
9990 /* Here we have two nested shifts. The result is usually the
9991 AND of a new shift with a mask. We compute the result below. */
9992 if (CONST_INT_P (XEXP (varop
, 1))
9993 && INTVAL (XEXP (varop
, 1)) >= 0
9994 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9995 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9996 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9997 && !VECTOR_MODE_P (result_mode
))
9999 enum rtx_code first_code
= GET_CODE (varop
);
10000 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10001 unsigned HOST_WIDE_INT mask
;
10004 /* We have one common special case. We can't do any merging if
10005 the inner code is an ASHIFTRT of a smaller mode. However, if
10006 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10007 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10008 we can convert it to
10009 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
10010 This simplifies certain SIGN_EXTEND operations. */
10011 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10012 && count
== (GET_MODE_BITSIZE (result_mode
)
10013 - GET_MODE_BITSIZE (GET_MODE (varop
))))
10015 /* C3 has the low-order C1 bits zero. */
10017 mask
= GET_MODE_MASK (mode
)
10018 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10020 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10021 XEXP (varop
, 0), mask
);
10022 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10024 count
= first_count
;
10029 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10030 than C1 high-order bits equal to the sign bit, we can convert
10031 this to either an ASHIFT or an ASHIFTRT depending on the
10034 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10036 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10037 && GET_MODE (varop
) == shift_mode
10038 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10041 varop
= XEXP (varop
, 0);
10042 count
-= first_count
;
10052 /* There are some cases we can't do. If CODE is ASHIFTRT,
10053 we can only do this if FIRST_CODE is also ASHIFTRT.
10055 We can't do the case when CODE is ROTATE and FIRST_CODE is
10058 If the mode of this shift is not the mode of the outer shift,
10059 we can't do this if either shift is a right shift or ROTATE.
10061 Finally, we can't do any of these if the mode is too wide
10062 unless the codes are the same.
10064 Handle the case where the shift codes are the same
10067 if (code
== first_code
)
10069 if (GET_MODE (varop
) != result_mode
10070 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10071 || code
== ROTATE
))
10074 count
+= first_count
;
10075 varop
= XEXP (varop
, 0);
10079 if (code
== ASHIFTRT
10080 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10081 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
10082 || (GET_MODE (varop
) != result_mode
10083 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10084 || first_code
== ROTATE
10085 || code
== ROTATE
)))
10088 /* To compute the mask to apply after the shift, shift the
10089 nonzero bits of the inner shift the same way the
10090 outer shift will. */
10092 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
10095 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10098 /* Give up if we can't compute an outer operation to use. */
10100 || !CONST_INT_P (mask_rtx
)
10101 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10103 result_mode
, &complement_p
))
10106 /* If the shifts are in the same direction, we add the
10107 counts. Otherwise, we subtract them. */
10108 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10109 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10110 count
+= first_count
;
10112 count
-= first_count
;
10114 /* If COUNT is positive, the new shift is usually CODE,
10115 except for the two exceptions below, in which case it is
10116 FIRST_CODE. If the count is negative, FIRST_CODE should
10119 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10120 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10122 else if (count
< 0)
10123 code
= first_code
, count
= -count
;
10125 varop
= XEXP (varop
, 0);
10129 /* If we have (A << B << C) for any shift, we can convert this to
10130 (A << C << B). This wins if A is a constant. Only try this if
10131 B is not a constant. */
10133 else if (GET_CODE (varop
) == code
10134 && CONST_INT_P (XEXP (varop
, 0))
10135 && !CONST_INT_P (XEXP (varop
, 1)))
10137 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10140 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10147 if (VECTOR_MODE_P (mode
))
10150 /* Make this fit the case below. */
10151 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
10152 GEN_INT (GET_MODE_MASK (mode
)));
10158 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10159 with C the size of VAROP - 1 and the shift is logical if
10160 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10161 we have an (le X 0) operation. If we have an arithmetic shift
10162 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10163 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10165 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10166 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10167 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10168 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10169 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
10170 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10173 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10176 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10177 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10182 /* If we have (shift (logical)), move the logical to the outside
10183 to allow it to possibly combine with another logical and the
10184 shift to combine with another shift. This also canonicalizes to
10185 what a ZERO_EXTRACT looks like. Also, some machines have
10186 (and (shift)) insns. */
10188 if (CONST_INT_P (XEXP (varop
, 1))
10189 /* We can't do this if we have (ashiftrt (xor)) and the
10190 constant has its sign bit set in shift_mode. */
10191 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10192 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10194 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10196 GEN_INT (count
))) != 0
10197 && CONST_INT_P (new_rtx
)
10198 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10199 INTVAL (new_rtx
), result_mode
, &complement_p
))
10201 varop
= XEXP (varop
, 0);
10205 /* If we can't do that, try to simplify the shift in each arm of the
10206 logical expression, make a new logical expression, and apply
10207 the inverse distributive law. This also can't be done
10208 for some (ashiftrt (xor)). */
10209 if (CONST_INT_P (XEXP (varop
, 1))
10210 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10211 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10214 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10215 XEXP (varop
, 0), count
);
10216 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10217 XEXP (varop
, 1), count
);
10219 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10221 varop
= apply_distributive_law (varop
);
10229 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10230 says that the sign bit can be tested, FOO has mode MODE, C is
10231 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10232 that may be nonzero. */
10233 if (code
== LSHIFTRT
10234 && XEXP (varop
, 1) == const0_rtx
10235 && GET_MODE (XEXP (varop
, 0)) == result_mode
10236 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10237 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10238 && STORE_FLAG_VALUE
== -1
10239 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10240 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10243 varop
= XEXP (varop
, 0);
10250 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10251 than the number of bits in the mode is equivalent to A. */
10252 if (code
== LSHIFTRT
10253 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10254 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10256 varop
= XEXP (varop
, 0);
10261 /* NEG commutes with ASHIFT since it is multiplication. Move the
10262 NEG outside to allow shifts to combine. */
10264 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10267 varop
= XEXP (varop
, 0);
10273 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10274 is one less than the number of bits in the mode is
10275 equivalent to (xor A 1). */
10276 if (code
== LSHIFTRT
10277 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10278 && XEXP (varop
, 1) == constm1_rtx
10279 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10280 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10284 varop
= XEXP (varop
, 0);
10288 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10289 that might be nonzero in BAR are those being shifted out and those
10290 bits are known zero in FOO, we can replace the PLUS with FOO.
10291 Similarly in the other operand order. This code occurs when
10292 we are computing the size of a variable-size array. */
10294 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10295 && count
< HOST_BITS_PER_WIDE_INT
10296 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10297 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10298 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10300 varop
= XEXP (varop
, 0);
10303 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10304 && count
< HOST_BITS_PER_WIDE_INT
10305 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10306 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10308 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10309 & nonzero_bits (XEXP (varop
, 1),
10312 varop
= XEXP (varop
, 1);
10316 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10318 && CONST_INT_P (XEXP (varop
, 1))
10319 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10321 GEN_INT (count
))) != 0
10322 && CONST_INT_P (new_rtx
)
10323 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10324 INTVAL (new_rtx
), result_mode
, &complement_p
))
10326 varop
= XEXP (varop
, 0);
10330 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10331 signbit', and attempt to change the PLUS to an XOR and move it to
10332 the outer operation as is done above in the AND/IOR/XOR case
10333 leg for shift(logical). See details in logical handling above
10334 for reasoning in doing so. */
10335 if (code
== LSHIFTRT
10336 && CONST_INT_P (XEXP (varop
, 1))
10337 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10338 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10340 GEN_INT (count
))) != 0
10341 && CONST_INT_P (new_rtx
)
10342 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10343 INTVAL (new_rtx
), result_mode
, &complement_p
))
10345 varop
= XEXP (varop
, 0);
10352 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10353 with C the size of VAROP - 1 and the shift is logical if
10354 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10355 we have a (gt X 0) operation. If the shift is arithmetic with
10356 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10357 we have a (neg (gt X 0)) operation. */
10359 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10360 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10361 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
10362 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10363 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10364 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10365 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10368 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10371 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10372 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10379 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10380 if the truncate does not affect the value. */
10381 if (code
== LSHIFTRT
10382 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10383 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10384 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10385 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
10386 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
10388 rtx varop_inner
= XEXP (varop
, 0);
10391 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10392 XEXP (varop_inner
, 0),
10394 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10395 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10408 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10409 outer_op
, outer_const
);
10411 /* We have now finished analyzing the shift. The result should be
10412 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10413 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10414 to the result of the shift. OUTER_CONST is the relevant constant,
10415 but we must turn off all bits turned off in the shift. */
10417 if (outer_op
== UNKNOWN
10418 && orig_code
== code
&& orig_count
== count
10419 && varop
== orig_varop
10420 && shift_mode
== GET_MODE (varop
))
10423 /* Make a SUBREG if necessary. If we can't make it, fail. */
10424 varop
= gen_lowpart (shift_mode
, varop
);
10425 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10428 /* If we have an outer operation and we just made a shift, it is
10429 possible that we could have simplified the shift were it not
10430 for the outer operation. So try to do the simplification
10433 if (outer_op
!= UNKNOWN
)
10434 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10439 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10441 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10442 turn off all the bits that the shift would have turned off. */
10443 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10444 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10445 GET_MODE_MASK (result_mode
) >> orig_count
);
10447 /* Do the remainder of the processing in RESULT_MODE. */
10448 x
= gen_lowpart_or_truncate (result_mode
, x
);
10450 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10453 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10455 if (outer_op
!= UNKNOWN
)
10457 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10458 && GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10459 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10461 if (outer_op
== AND
)
10462 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10463 else if (outer_op
== SET
)
10465 /* This means that we have determined that the result is
10466 equivalent to a constant. This should be rare. */
10467 if (!side_effects_p (x
))
10468 x
= GEN_INT (outer_const
);
10470 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10471 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10473 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10474 GEN_INT (outer_const
));
10480 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10481 The result of the shift is RESULT_MODE. If we cannot simplify it,
10482 return X or, if it is NULL, synthesize the expression with
10483 simplify_gen_binary. Otherwise, return a simplified value.
10485 The shift is normally computed in the widest mode we find in VAROP, as
10486 long as it isn't a different number of words than RESULT_MODE. Exceptions
10487 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10490 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10491 rtx varop
, int count
)
10493 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10498 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10499 if (GET_MODE (x
) != result_mode
)
10500 x
= gen_lowpart (result_mode
, x
);
10505 /* Like recog, but we receive the address of a pointer to a new pattern.
10506 We try to match the rtx that the pointer points to.
10507 If that fails, we may try to modify or replace the pattern,
10508 storing the replacement into the same pointer object.
10510 Modifications include deletion or addition of CLOBBERs.
10512 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10513 the CLOBBERs are placed.
10515 The value is the final insn code from the pattern ultimately matched,
10519 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10521 rtx pat
= *pnewpat
;
10522 int insn_code_number
;
10523 int num_clobbers_to_add
= 0;
10526 rtx old_notes
, old_pat
;
10528 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10529 we use to indicate that something didn't match. If we find such a
10530 thing, force rejection. */
10531 if (GET_CODE (pat
) == PARALLEL
)
10532 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10533 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10534 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10537 old_pat
= PATTERN (insn
);
10538 old_notes
= REG_NOTES (insn
);
10539 PATTERN (insn
) = pat
;
10540 REG_NOTES (insn
) = 0;
10542 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10543 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10545 if (insn_code_number
< 0)
10546 fputs ("Failed to match this instruction:\n", dump_file
);
10548 fputs ("Successfully matched this instruction:\n", dump_file
);
10549 print_rtl_single (dump_file
, pat
);
10552 /* If it isn't, there is the possibility that we previously had an insn
10553 that clobbered some register as a side effect, but the combined
10554 insn doesn't need to do that. So try once more without the clobbers
10555 unless this represents an ASM insn. */
10557 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10558 && GET_CODE (pat
) == PARALLEL
)
10562 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10563 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10566 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10570 SUBST_INT (XVECLEN (pat
, 0), pos
);
10573 pat
= XVECEXP (pat
, 0, 0);
10575 PATTERN (insn
) = pat
;
10576 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10577 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10579 if (insn_code_number
< 0)
10580 fputs ("Failed to match this instruction:\n", dump_file
);
10582 fputs ("Successfully matched this instruction:\n", dump_file
);
10583 print_rtl_single (dump_file
, pat
);
10586 PATTERN (insn
) = old_pat
;
10587 REG_NOTES (insn
) = old_notes
;
10589 /* Recognize all noop sets, these will be killed by followup pass. */
10590 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10591 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10593 /* If we had any clobbers to add, make a new pattern than contains
10594 them. Then check to make sure that all of them are dead. */
10595 if (num_clobbers_to_add
)
10597 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10598 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10599 ? (XVECLEN (pat
, 0)
10600 + num_clobbers_to_add
)
10601 : num_clobbers_to_add
+ 1));
10603 if (GET_CODE (pat
) == PARALLEL
)
10604 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10605 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10607 XVECEXP (newpat
, 0, 0) = pat
;
10609 add_clobbers (newpat
, insn_code_number
);
10611 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10612 i
< XVECLEN (newpat
, 0); i
++)
10614 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10615 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10617 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10619 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10620 notes
= alloc_reg_note (REG_UNUSED
,
10621 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10630 return insn_code_number
;
10633 /* Like gen_lowpart_general but for use by combine. In combine it
10634 is not possible to create any new pseudoregs. However, it is
10635 safe to create invalid memory addresses, because combine will
10636 try to recognize them and all they will do is make the combine
10639 If for some reason this cannot do its job, an rtx
10640 (clobber (const_int 0)) is returned.
10641 An insn containing that will not be recognized. */
10644 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10646 enum machine_mode imode
= GET_MODE (x
);
10647 unsigned int osize
= GET_MODE_SIZE (omode
);
10648 unsigned int isize
= GET_MODE_SIZE (imode
);
10651 if (omode
== imode
)
10654 /* Return identity if this is a CONST or symbolic reference. */
10656 && (GET_CODE (x
) == CONST
10657 || GET_CODE (x
) == SYMBOL_REF
10658 || GET_CODE (x
) == LABEL_REF
))
10661 /* We can only support MODE being wider than a word if X is a
10662 constant integer or has a mode the same size. */
10663 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10664 && ! ((imode
== VOIDmode
10665 && (CONST_INT_P (x
)
10666 || GET_CODE (x
) == CONST_DOUBLE
))
10667 || isize
== osize
))
10670 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10671 won't know what to do. So we will strip off the SUBREG here and
10672 process normally. */
10673 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10675 x
= SUBREG_REG (x
);
10677 /* For use in case we fall down into the address adjustments
10678 further below, we need to adjust the known mode and size of
10679 x; imode and isize, since we just adjusted x. */
10680 imode
= GET_MODE (x
);
10682 if (imode
== omode
)
10685 isize
= GET_MODE_SIZE (imode
);
10688 result
= gen_lowpart_common (omode
, x
);
10697 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10699 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10702 /* If we want to refer to something bigger than the original memref,
10703 generate a paradoxical subreg instead. That will force a reload
10704 of the original memref X. */
10706 return gen_rtx_SUBREG (omode
, x
, 0);
10708 if (WORDS_BIG_ENDIAN
)
10709 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10711 /* Adjust the address so that the address-after-the-data is
10713 if (BYTES_BIG_ENDIAN
)
10714 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10716 return adjust_address_nv (x
, omode
, offset
);
10719 /* If X is a comparison operator, rewrite it in a new mode. This
10720 probably won't match, but may allow further simplifications. */
10721 else if (COMPARISON_P (x
))
10722 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10724 /* If we couldn't simplify X any other way, just enclose it in a
10725 SUBREG. Normally, this SUBREG won't match, but some patterns may
10726 include an explicit SUBREG or we may simplify it further in combine. */
10732 offset
= subreg_lowpart_offset (omode
, imode
);
10733 if (imode
== VOIDmode
)
10735 imode
= int_mode_for_mode (omode
);
10736 x
= gen_lowpart_common (imode
, x
);
10740 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10746 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10749 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10750 comparison code that will be tested.
10752 The result is a possibly different comparison code to use. *POP0 and
10753 *POP1 may be updated.
10755 It is possible that we might detect that a comparison is either always
10756 true or always false. However, we do not perform general constant
10757 folding in combine, so this knowledge isn't useful. Such tautologies
10758 should have been detected earlier. Hence we ignore all such cases. */
10760 static enum rtx_code
10761 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10767 enum machine_mode mode
, tmode
;
10769 /* Try a few ways of applying the same transformation to both operands. */
10772 #ifndef WORD_REGISTER_OPERATIONS
10773 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10774 so check specially. */
10775 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10776 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10777 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10778 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10779 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10780 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10781 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10782 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10783 && CONST_INT_P (XEXP (op0
, 1))
10784 && XEXP (op0
, 1) == XEXP (op1
, 1)
10785 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10786 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10787 && (INTVAL (XEXP (op0
, 1))
10788 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10789 - (GET_MODE_BITSIZE
10790 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10792 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10793 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10797 /* If both operands are the same constant shift, see if we can ignore the
10798 shift. We can if the shift is a rotate or if the bits shifted out of
10799 this shift are known to be zero for both inputs and if the type of
10800 comparison is compatible with the shift. */
10801 if (GET_CODE (op0
) == GET_CODE (op1
)
10802 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10803 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10804 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10805 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10806 || (GET_CODE (op0
) == ASHIFTRT
10807 && (code
!= GTU
&& code
!= LTU
10808 && code
!= GEU
&& code
!= LEU
)))
10809 && CONST_INT_P (XEXP (op0
, 1))
10810 && INTVAL (XEXP (op0
, 1)) >= 0
10811 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10812 && XEXP (op0
, 1) == XEXP (op1
, 1))
10814 enum machine_mode mode
= GET_MODE (op0
);
10815 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10816 int shift_count
= INTVAL (XEXP (op0
, 1));
10818 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10819 mask
&= (mask
>> shift_count
) << shift_count
;
10820 else if (GET_CODE (op0
) == ASHIFT
)
10821 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10823 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10824 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10825 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10830 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10831 SUBREGs are of the same mode, and, in both cases, the AND would
10832 be redundant if the comparison was done in the narrower mode,
10833 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10834 and the operand's possibly nonzero bits are 0xffffff01; in that case
10835 if we only care about QImode, we don't need the AND). This case
10836 occurs if the output mode of an scc insn is not SImode and
10837 STORE_FLAG_VALUE == 1 (e.g., the 386).
10839 Similarly, check for a case where the AND's are ZERO_EXTEND
10840 operations from some narrower mode even though a SUBREG is not
10843 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10844 && CONST_INT_P (XEXP (op0
, 1))
10845 && CONST_INT_P (XEXP (op1
, 1)))
10847 rtx inner_op0
= XEXP (op0
, 0);
10848 rtx inner_op1
= XEXP (op1
, 0);
10849 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10850 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10853 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10854 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10855 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10856 && (GET_MODE (SUBREG_REG (inner_op0
))
10857 == GET_MODE (SUBREG_REG (inner_op1
)))
10858 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10859 <= HOST_BITS_PER_WIDE_INT
)
10860 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10861 GET_MODE (SUBREG_REG (inner_op0
)))))
10862 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10863 GET_MODE (SUBREG_REG (inner_op1
))))))
10865 op0
= SUBREG_REG (inner_op0
);
10866 op1
= SUBREG_REG (inner_op1
);
10868 /* The resulting comparison is always unsigned since we masked
10869 off the original sign bit. */
10870 code
= unsigned_condition (code
);
10876 for (tmode
= GET_CLASS_NARROWEST_MODE
10877 (GET_MODE_CLASS (GET_MODE (op0
)));
10878 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10879 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10881 op0
= gen_lowpart (tmode
, inner_op0
);
10882 op1
= gen_lowpart (tmode
, inner_op1
);
10883 code
= unsigned_condition (code
);
10892 /* If both operands are NOT, we can strip off the outer operation
10893 and adjust the comparison code for swapped operands; similarly for
10894 NEG, except that this must be an equality comparison. */
10895 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10896 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10897 && (code
== EQ
|| code
== NE
)))
10898 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10904 /* If the first operand is a constant, swap the operands and adjust the
10905 comparison code appropriately, but don't do this if the second operand
10906 is already a constant integer. */
10907 if (swap_commutative_operands_p (op0
, op1
))
10909 tem
= op0
, op0
= op1
, op1
= tem
;
10910 code
= swap_condition (code
);
10913 /* We now enter a loop during which we will try to simplify the comparison.
10914 For the most part, we only are concerned with comparisons with zero,
10915 but some things may really be comparisons with zero but not start
10916 out looking that way. */
10918 while (CONST_INT_P (op1
))
10920 enum machine_mode mode
= GET_MODE (op0
);
10921 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10922 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10923 int equality_comparison_p
;
10924 int sign_bit_comparison_p
;
10925 int unsigned_comparison_p
;
10926 HOST_WIDE_INT const_op
;
10928 /* We only want to handle integral modes. This catches VOIDmode,
10929 CCmode, and the floating-point modes. An exception is that we
10930 can handle VOIDmode if OP0 is a COMPARE or a comparison
10933 if (GET_MODE_CLASS (mode
) != MODE_INT
10934 && ! (mode
== VOIDmode
10935 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10938 /* Get the constant we are comparing against and turn off all bits
10939 not on in our mode. */
10940 const_op
= INTVAL (op1
);
10941 if (mode
!= VOIDmode
)
10942 const_op
= trunc_int_for_mode (const_op
, mode
);
10943 op1
= GEN_INT (const_op
);
10945 /* If we are comparing against a constant power of two and the value
10946 being compared can only have that single bit nonzero (e.g., it was
10947 `and'ed with that bit), we can replace this with a comparison
10950 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10951 || code
== LT
|| code
== LTU
)
10952 && mode_width
<= HOST_BITS_PER_WIDE_INT
10953 && exact_log2 (const_op
) >= 0
10954 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10956 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10957 op1
= const0_rtx
, const_op
= 0;
10960 /* Similarly, if we are comparing a value known to be either -1 or
10961 0 with -1, change it to the opposite comparison against zero. */
10964 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10965 || code
== GEU
|| code
== LTU
)
10966 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10968 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10969 op1
= const0_rtx
, const_op
= 0;
10972 /* Do some canonicalizations based on the comparison code. We prefer
10973 comparisons against zero and then prefer equality comparisons.
10974 If we can reduce the size of a constant, we will do that too. */
10979 /* < C is equivalent to <= (C - 1) */
10983 op1
= GEN_INT (const_op
);
10985 /* ... fall through to LE case below. */
10991 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10995 op1
= GEN_INT (const_op
);
10999 /* If we are doing a <= 0 comparison on a value known to have
11000 a zero sign bit, we can replace this with == 0. */
11001 else if (const_op
== 0
11002 && mode_width
<= HOST_BITS_PER_WIDE_INT
11003 && (nonzero_bits (op0
, mode
)
11004 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11010 /* >= C is equivalent to > (C - 1). */
11014 op1
= GEN_INT (const_op
);
11016 /* ... fall through to GT below. */
11022 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11026 op1
= GEN_INT (const_op
);
11030 /* If we are doing a > 0 comparison on a value known to have
11031 a zero sign bit, we can replace this with != 0. */
11032 else if (const_op
== 0
11033 && mode_width
<= HOST_BITS_PER_WIDE_INT
11034 && (nonzero_bits (op0
, mode
)
11035 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11041 /* < C is equivalent to <= (C - 1). */
11045 op1
= GEN_INT (const_op
);
11047 /* ... fall through ... */
11050 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11051 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11052 && (unsigned HOST_WIDE_INT
) const_op
11053 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11055 const_op
= 0, op1
= const0_rtx
;
11063 /* unsigned <= 0 is equivalent to == 0 */
11067 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11068 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11069 && (unsigned HOST_WIDE_INT
) const_op
11070 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11072 const_op
= 0, op1
= const0_rtx
;
11078 /* >= C is equivalent to > (C - 1). */
11082 op1
= GEN_INT (const_op
);
11084 /* ... fall through ... */
11087 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11088 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11089 && (unsigned HOST_WIDE_INT
) const_op
11090 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11092 const_op
= 0, op1
= const0_rtx
;
11100 /* unsigned > 0 is equivalent to != 0 */
11104 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11105 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11106 && (unsigned HOST_WIDE_INT
) const_op
11107 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11109 const_op
= 0, op1
= const0_rtx
;
11118 /* Compute some predicates to simplify code below. */
11120 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11121 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11122 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11125 /* If this is a sign bit comparison and we can do arithmetic in
11126 MODE, say that we will only be needing the sign bit of OP0. */
11127 if (sign_bit_comparison_p
11128 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11129 op0
= force_to_mode (op0
, mode
,
11130 (unsigned HOST_WIDE_INT
) 1
11131 << (GET_MODE_BITSIZE (mode
) - 1),
11134 /* Now try cases based on the opcode of OP0. If none of the cases
11135 does a "continue", we exit this loop immediately after the
11138 switch (GET_CODE (op0
))
11141 /* If we are extracting a single bit from a variable position in
11142 a constant that has only a single bit set and are comparing it
11143 with zero, we can convert this into an equality comparison
11144 between the position and the location of the single bit. */
11145 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11146 have already reduced the shift count modulo the word size. */
11147 if (!SHIFT_COUNT_TRUNCATED
11148 && CONST_INT_P (XEXP (op0
, 0))
11149 && XEXP (op0
, 1) == const1_rtx
11150 && equality_comparison_p
&& const_op
== 0
11151 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11153 if (BITS_BIG_ENDIAN
)
11155 enum machine_mode new_mode
11156 = mode_for_extraction (EP_extzv
, 1);
11157 if (new_mode
== MAX_MACHINE_MODE
)
11158 i
= BITS_PER_WORD
- 1 - i
;
11162 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
11166 op0
= XEXP (op0
, 2);
11170 /* Result is nonzero iff shift count is equal to I. */
11171 code
= reverse_condition (code
);
11175 /* ... fall through ... */
11178 tem
= expand_compound_operation (op0
);
11187 /* If testing for equality, we can take the NOT of the constant. */
11188 if (equality_comparison_p
11189 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11191 op0
= XEXP (op0
, 0);
11196 /* If just looking at the sign bit, reverse the sense of the
11198 if (sign_bit_comparison_p
)
11200 op0
= XEXP (op0
, 0);
11201 code
= (code
== GE
? LT
: GE
);
11207 /* If testing for equality, we can take the NEG of the constant. */
11208 if (equality_comparison_p
11209 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11211 op0
= XEXP (op0
, 0);
11216 /* The remaining cases only apply to comparisons with zero. */
11220 /* When X is ABS or is known positive,
11221 (neg X) is < 0 if and only if X != 0. */
11223 if (sign_bit_comparison_p
11224 && (GET_CODE (XEXP (op0
, 0)) == ABS
11225 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11226 && (nonzero_bits (XEXP (op0
, 0), mode
)
11227 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11230 op0
= XEXP (op0
, 0);
11231 code
= (code
== LT
? NE
: EQ
);
11235 /* If we have NEG of something whose two high-order bits are the
11236 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11237 if (num_sign_bit_copies (op0
, mode
) >= 2)
11239 op0
= XEXP (op0
, 0);
11240 code
= swap_condition (code
);
11246 /* If we are testing equality and our count is a constant, we
11247 can perform the inverse operation on our RHS. */
11248 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11249 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11250 op1
, XEXP (op0
, 1))) != 0)
11252 op0
= XEXP (op0
, 0);
11257 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11258 a particular bit. Convert it to an AND of a constant of that
11259 bit. This will be converted into a ZERO_EXTRACT. */
11260 if (const_op
== 0 && sign_bit_comparison_p
11261 && CONST_INT_P (XEXP (op0
, 1))
11262 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11264 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11265 ((unsigned HOST_WIDE_INT
) 1
11267 - INTVAL (XEXP (op0
, 1)))));
11268 code
= (code
== LT
? NE
: EQ
);
11272 /* Fall through. */
11275 /* ABS is ignorable inside an equality comparison with zero. */
11276 if (const_op
== 0 && equality_comparison_p
)
11278 op0
= XEXP (op0
, 0);
11284 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11285 (compare FOO CONST) if CONST fits in FOO's mode and we
11286 are either testing inequality or have an unsigned
11287 comparison with ZERO_EXTEND or a signed comparison with
11288 SIGN_EXTEND. But don't do it if we don't have a compare
11289 insn of the given mode, since we'd have to revert it
11290 later on, and then we wouldn't know whether to sign- or
11292 mode
= GET_MODE (XEXP (op0
, 0));
11293 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11294 && ! unsigned_comparison_p
11295 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11296 && ((unsigned HOST_WIDE_INT
) const_op
11297 < (((unsigned HOST_WIDE_INT
) 1
11298 << (GET_MODE_BITSIZE (mode
) - 1))))
11299 && have_insn_for (COMPARE
, mode
))
11301 op0
= XEXP (op0
, 0);
11307 /* Check for the case where we are comparing A - C1 with C2, that is
11309 (subreg:MODE (plus (A) (-C1))) op (C2)
11311 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11312 comparison in the wider mode. One of the following two conditions
11313 must be true in order for this to be valid:
11315 1. The mode extension results in the same bit pattern being added
11316 on both sides and the comparison is equality or unsigned. As
11317 C2 has been truncated to fit in MODE, the pattern can only be
11320 2. The mode extension results in the sign bit being copied on
11323 The difficulty here is that we have predicates for A but not for
11324 (A - C1) so we need to check that C1 is within proper bounds so
11325 as to perturbate A as little as possible. */
11327 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11328 && subreg_lowpart_p (op0
)
11329 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
11330 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11331 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11333 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11334 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11335 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11338 && (unsigned HOST_WIDE_INT
) c1
11339 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11340 && (equality_comparison_p
|| unsigned_comparison_p
)
11341 /* (A - C1) zero-extends if it is positive and sign-extends
11342 if it is negative, C2 both zero- and sign-extends. */
11343 && ((0 == (nonzero_bits (a
, inner_mode
)
11344 & ~GET_MODE_MASK (mode
))
11346 /* (A - C1) sign-extends if it is positive and 1-extends
11347 if it is negative, C2 both sign- and 1-extends. */
11348 || (num_sign_bit_copies (a
, inner_mode
)
11349 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
11352 || ((unsigned HOST_WIDE_INT
) c1
11353 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11354 /* (A - C1) always sign-extends, like C2. */
11355 && num_sign_bit_copies (a
, inner_mode
)
11356 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
11357 - (mode_width
- 1))))
11359 op0
= SUBREG_REG (op0
);
11364 /* If the inner mode is narrower and we are extracting the low part,
11365 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11366 if (subreg_lowpart_p (op0
)
11367 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11368 /* Fall through */ ;
11372 /* ... fall through ... */
11375 mode
= GET_MODE (XEXP (op0
, 0));
11376 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11377 && (unsigned_comparison_p
|| equality_comparison_p
)
11378 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11379 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
11380 && have_insn_for (COMPARE
, mode
))
11382 op0
= XEXP (op0
, 0);
11388 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11389 this for equality comparisons due to pathological cases involving
11391 if (equality_comparison_p
11392 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11393 op1
, XEXP (op0
, 1))))
11395 op0
= XEXP (op0
, 0);
11400 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11401 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11402 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11404 op0
= XEXP (XEXP (op0
, 0), 0);
11405 code
= (code
== LT
? EQ
: NE
);
11411 /* We used to optimize signed comparisons against zero, but that
11412 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11413 arrive here as equality comparisons, or (GEU, LTU) are
11414 optimized away. No need to special-case them. */
11416 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11417 (eq B (minus A C)), whichever simplifies. We can only do
11418 this for equality comparisons due to pathological cases involving
11420 if (equality_comparison_p
11421 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11422 XEXP (op0
, 1), op1
)))
11424 op0
= XEXP (op0
, 0);
11429 if (equality_comparison_p
11430 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11431 XEXP (op0
, 0), op1
)))
11433 op0
= XEXP (op0
, 1);
11438 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11439 of bits in X minus 1, is one iff X > 0. */
11440 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11441 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11442 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11443 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11445 op0
= XEXP (op0
, 1);
11446 code
= (code
== GE
? LE
: GT
);
11452 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11453 if C is zero or B is a constant. */
11454 if (equality_comparison_p
11455 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11456 XEXP (op0
, 1), op1
)))
11458 op0
= XEXP (op0
, 0);
11465 case UNEQ
: case LTGT
:
11466 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11467 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11468 case UNORDERED
: case ORDERED
:
11469 /* We can't do anything if OP0 is a condition code value, rather
11470 than an actual data value. */
11472 || CC0_P (XEXP (op0
, 0))
11473 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11476 /* Get the two operands being compared. */
11477 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11478 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11480 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11482 /* Check for the cases where we simply want the result of the
11483 earlier test or the opposite of that result. */
11484 if (code
== NE
|| code
== EQ
11485 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
11486 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11487 && (STORE_FLAG_VALUE
11488 & (((unsigned HOST_WIDE_INT
) 1
11489 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
11490 && (code
== LT
|| code
== GE
)))
11492 enum rtx_code new_code
;
11493 if (code
== LT
|| code
== NE
)
11494 new_code
= GET_CODE (op0
);
11496 new_code
= reversed_comparison_code (op0
, NULL
);
11498 if (new_code
!= UNKNOWN
)
11509 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11511 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11512 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11513 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11515 op0
= XEXP (op0
, 1);
11516 code
= (code
== GE
? GT
: LE
);
11522 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11523 will be converted to a ZERO_EXTRACT later. */
11524 if (const_op
== 0 && equality_comparison_p
11525 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11526 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11528 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11529 XEXP (XEXP (op0
, 0), 1));
11530 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11534 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11535 zero and X is a comparison and C1 and C2 describe only bits set
11536 in STORE_FLAG_VALUE, we can compare with X. */
11537 if (const_op
== 0 && equality_comparison_p
11538 && mode_width
<= HOST_BITS_PER_WIDE_INT
11539 && CONST_INT_P (XEXP (op0
, 1))
11540 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11541 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11542 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11543 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11545 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11546 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11547 if ((~STORE_FLAG_VALUE
& mask
) == 0
11548 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11549 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11550 && COMPARISON_P (tem
))))
11552 op0
= XEXP (XEXP (op0
, 0), 0);
11557 /* If we are doing an equality comparison of an AND of a bit equal
11558 to the sign bit, replace this with a LT or GE comparison of
11559 the underlying value. */
11560 if (equality_comparison_p
11562 && CONST_INT_P (XEXP (op0
, 1))
11563 && mode_width
<= HOST_BITS_PER_WIDE_INT
11564 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11565 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11567 op0
= XEXP (op0
, 0);
11568 code
= (code
== EQ
? GE
: LT
);
11572 /* If this AND operation is really a ZERO_EXTEND from a narrower
11573 mode, the constant fits within that mode, and this is either an
11574 equality or unsigned comparison, try to do this comparison in
11579 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11580 -> (ne:DI (reg:SI 4) (const_int 0))
11582 unless TRULY_NOOP_TRUNCATION allows it or the register is
11583 known to hold a value of the required mode the
11584 transformation is invalid. */
11585 if ((equality_comparison_p
|| unsigned_comparison_p
)
11586 && CONST_INT_P (XEXP (op0
, 1))
11587 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11588 & GET_MODE_MASK (mode
))
11590 && const_op
>> i
== 0
11591 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11592 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
11593 GET_MODE_BITSIZE (GET_MODE (op0
)))
11594 || (REG_P (XEXP (op0
, 0))
11595 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11597 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11601 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11602 fits in both M1 and M2 and the SUBREG is either paradoxical
11603 or represents the low part, permute the SUBREG and the AND
11605 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11607 unsigned HOST_WIDE_INT c1
;
11608 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11609 /* Require an integral mode, to avoid creating something like
11611 if (SCALAR_INT_MODE_P (tmode
)
11612 /* It is unsafe to commute the AND into the SUBREG if the
11613 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11614 not defined. As originally written the upper bits
11615 have a defined value due to the AND operation.
11616 However, if we commute the AND inside the SUBREG then
11617 they no longer have defined values and the meaning of
11618 the code has been changed. */
11620 #ifdef WORD_REGISTER_OPERATIONS
11621 || (mode_width
> GET_MODE_BITSIZE (tmode
)
11622 && mode_width
<= BITS_PER_WORD
)
11624 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
11625 && subreg_lowpart_p (XEXP (op0
, 0))))
11626 && CONST_INT_P (XEXP (op0
, 1))
11627 && mode_width
<= HOST_BITS_PER_WIDE_INT
11628 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
11629 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11630 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11632 && c1
!= GET_MODE_MASK (tmode
))
11634 op0
= simplify_gen_binary (AND
, tmode
,
11635 SUBREG_REG (XEXP (op0
, 0)),
11636 gen_int_mode (c1
, tmode
));
11637 op0
= gen_lowpart (mode
, op0
);
11642 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11643 if (const_op
== 0 && equality_comparison_p
11644 && XEXP (op0
, 1) == const1_rtx
11645 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11647 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11648 XEXP (XEXP (op0
, 0), 0), 1);
11649 code
= (code
== NE
? EQ
: NE
);
11653 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11654 (eq (and (lshiftrt X) 1) 0).
11655 Also handle the case where (not X) is expressed using xor. */
11656 if (const_op
== 0 && equality_comparison_p
11657 && XEXP (op0
, 1) == const1_rtx
11658 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11660 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11661 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11663 if (GET_CODE (shift_op
) == NOT
11664 || (GET_CODE (shift_op
) == XOR
11665 && CONST_INT_P (XEXP (shift_op
, 1))
11666 && CONST_INT_P (shift_count
)
11667 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11668 && (UINTVAL (XEXP (shift_op
, 1))
11669 == (unsigned HOST_WIDE_INT
) 1
11670 << INTVAL (shift_count
))))
11673 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11674 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11675 code
= (code
== NE
? EQ
: NE
);
11682 /* If we have (compare (ashift FOO N) (const_int C)) and
11683 the high order N bits of FOO (N+1 if an inequality comparison)
11684 are known to be zero, we can do this by comparing FOO with C
11685 shifted right N bits so long as the low-order N bits of C are
11687 if (CONST_INT_P (XEXP (op0
, 1))
11688 && INTVAL (XEXP (op0
, 1)) >= 0
11689 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11690 < HOST_BITS_PER_WIDE_INT
)
11691 && (((unsigned HOST_WIDE_INT
) const_op
11692 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11694 && mode_width
<= HOST_BITS_PER_WIDE_INT
11695 && (nonzero_bits (XEXP (op0
, 0), mode
)
11696 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11697 + ! equality_comparison_p
))) == 0)
11699 /* We must perform a logical shift, not an arithmetic one,
11700 as we want the top N bits of C to be zero. */
11701 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11703 temp
>>= INTVAL (XEXP (op0
, 1));
11704 op1
= gen_int_mode (temp
, mode
);
11705 op0
= XEXP (op0
, 0);
11709 /* If we are doing a sign bit comparison, it means we are testing
11710 a particular bit. Convert it to the appropriate AND. */
11711 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11712 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11714 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11715 ((unsigned HOST_WIDE_INT
) 1
11717 - INTVAL (XEXP (op0
, 1)))));
11718 code
= (code
== LT
? NE
: EQ
);
11722 /* If this an equality comparison with zero and we are shifting
11723 the low bit to the sign bit, we can convert this to an AND of the
11725 if (const_op
== 0 && equality_comparison_p
11726 && CONST_INT_P (XEXP (op0
, 1))
11727 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11729 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11735 /* If this is an equality comparison with zero, we can do this
11736 as a logical shift, which might be much simpler. */
11737 if (equality_comparison_p
&& const_op
== 0
11738 && CONST_INT_P (XEXP (op0
, 1)))
11740 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11742 INTVAL (XEXP (op0
, 1)));
11746 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11747 do the comparison in a narrower mode. */
11748 if (! unsigned_comparison_p
11749 && CONST_INT_P (XEXP (op0
, 1))
11750 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11751 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11752 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11753 MODE_INT
, 1)) != BLKmode
11754 && (((unsigned HOST_WIDE_INT
) const_op
11755 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11756 <= GET_MODE_MASK (tmode
)))
11758 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11762 /* Likewise if OP0 is a PLUS of a sign extension with a
11763 constant, which is usually represented with the PLUS
11764 between the shifts. */
11765 if (! unsigned_comparison_p
11766 && CONST_INT_P (XEXP (op0
, 1))
11767 && GET_CODE (XEXP (op0
, 0)) == PLUS
11768 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11769 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11770 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11771 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11772 MODE_INT
, 1)) != BLKmode
11773 && (((unsigned HOST_WIDE_INT
) const_op
11774 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11775 <= GET_MODE_MASK (tmode
)))
11777 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11778 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11779 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11780 add_const
, XEXP (op0
, 1));
11782 op0
= simplify_gen_binary (PLUS
, tmode
,
11783 gen_lowpart (tmode
, inner
),
11788 /* ... fall through ... */
11790 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11791 the low order N bits of FOO are known to be zero, we can do this
11792 by comparing FOO with C shifted left N bits so long as no
11793 overflow occurs. Even if the low order N bits of FOO aren't known
11794 to be zero, if the comparison is >= or < we can use the same
11795 optimization and for > or <= by setting all the low
11796 order N bits in the comparison constant. */
11797 if (CONST_INT_P (XEXP (op0
, 1))
11798 && INTVAL (XEXP (op0
, 1)) > 0
11799 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11800 && mode_width
<= HOST_BITS_PER_WIDE_INT
11801 && (((unsigned HOST_WIDE_INT
) const_op
11802 + (GET_CODE (op0
) != LSHIFTRT
11803 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11806 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11808 unsigned HOST_WIDE_INT low_bits
11809 = (nonzero_bits (XEXP (op0
, 0), mode
)
11810 & (((unsigned HOST_WIDE_INT
) 1
11811 << INTVAL (XEXP (op0
, 1))) - 1));
11812 if (low_bits
== 0 || !equality_comparison_p
)
11814 /* If the shift was logical, then we must make the condition
11816 if (GET_CODE (op0
) == LSHIFTRT
)
11817 code
= unsigned_condition (code
);
11819 const_op
<<= INTVAL (XEXP (op0
, 1));
11821 && (code
== GT
|| code
== GTU
11822 || code
== LE
|| code
== LEU
))
11824 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11825 op1
= GEN_INT (const_op
);
11826 op0
= XEXP (op0
, 0);
11831 /* If we are using this shift to extract just the sign bit, we
11832 can replace this with an LT or GE comparison. */
11834 && (equality_comparison_p
|| sign_bit_comparison_p
)
11835 && CONST_INT_P (XEXP (op0
, 1))
11836 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11838 op0
= XEXP (op0
, 0);
11839 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11851 /* Now make any compound operations involved in this comparison. Then,
11852 check for an outmost SUBREG on OP0 that is not doing anything or is
11853 paradoxical. The latter transformation must only be performed when
11854 it is known that the "extra" bits will be the same in op0 and op1 or
11855 that they don't matter. There are three cases to consider:
11857 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11858 care bits and we can assume they have any convenient value. So
11859 making the transformation is safe.
11861 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11862 In this case the upper bits of op0 are undefined. We should not make
11863 the simplification in that case as we do not know the contents of
11866 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11867 UNKNOWN. In that case we know those bits are zeros or ones. We must
11868 also be sure that they are the same as the upper bits of op1.
11870 We can never remove a SUBREG for a non-equality comparison because
11871 the sign bit is in a different place in the underlying object. */
11873 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11874 op1
= make_compound_operation (op1
, SET
);
11876 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11877 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11878 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11879 && (code
== NE
|| code
== EQ
))
11881 if (GET_MODE_SIZE (GET_MODE (op0
))
11882 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11884 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11886 if (REG_P (SUBREG_REG (op0
)))
11888 op0
= SUBREG_REG (op0
);
11889 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11892 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11893 <= HOST_BITS_PER_WIDE_INT
)
11894 && (nonzero_bits (SUBREG_REG (op0
),
11895 GET_MODE (SUBREG_REG (op0
)))
11896 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11898 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11900 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11901 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11902 op0
= SUBREG_REG (op0
), op1
= tem
;
11906 /* We now do the opposite procedure: Some machines don't have compare
11907 insns in all modes. If OP0's mode is an integer mode smaller than a
11908 word and we can't do a compare in that mode, see if there is a larger
11909 mode for which we can do the compare. There are a number of cases in
11910 which we can use the wider mode. */
11912 mode
= GET_MODE (op0
);
11913 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11914 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11915 && ! have_insn_for (COMPARE
, mode
))
11916 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11918 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11919 tmode
= GET_MODE_WIDER_MODE (tmode
))
11920 if (have_insn_for (COMPARE
, tmode
))
11924 /* If this is a test for negative, we can make an explicit
11925 test of the sign bit. Test this first so we can use
11926 a paradoxical subreg to extend OP0. */
11928 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11929 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11931 op0
= simplify_gen_binary (AND
, tmode
,
11932 gen_lowpart (tmode
, op0
),
11933 GEN_INT ((unsigned HOST_WIDE_INT
) 1
11934 << (GET_MODE_BITSIZE (mode
)
11936 code
= (code
== LT
) ? NE
: EQ
;
11940 /* If the only nonzero bits in OP0 and OP1 are those in the
11941 narrower mode and this is an equality or unsigned comparison,
11942 we can use the wider mode. Similarly for sign-extended
11943 values, in which case it is true for all comparisons. */
11944 zero_extended
= ((code
== EQ
|| code
== NE
11945 || code
== GEU
|| code
== GTU
11946 || code
== LEU
|| code
== LTU
)
11947 && (nonzero_bits (op0
, tmode
)
11948 & ~GET_MODE_MASK (mode
)) == 0
11949 && ((CONST_INT_P (op1
)
11950 || (nonzero_bits (op1
, tmode
)
11951 & ~GET_MODE_MASK (mode
)) == 0)));
11954 || ((num_sign_bit_copies (op0
, tmode
)
11955 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11956 - GET_MODE_BITSIZE (mode
)))
11957 && (num_sign_bit_copies (op1
, tmode
)
11958 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11959 - GET_MODE_BITSIZE (mode
)))))
11961 /* If OP0 is an AND and we don't have an AND in MODE either,
11962 make a new AND in the proper mode. */
11963 if (GET_CODE (op0
) == AND
11964 && !have_insn_for (AND
, mode
))
11965 op0
= simplify_gen_binary (AND
, tmode
,
11966 gen_lowpart (tmode
,
11968 gen_lowpart (tmode
,
11974 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
11975 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
11979 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
11980 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
11987 #ifdef CANONICALIZE_COMPARISON
11988 /* If this machine only supports a subset of valid comparisons, see if we
11989 can convert an unsupported one into a supported one. */
11990 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11999 /* Utility function for record_value_for_reg. Count number of
12004 enum rtx_code code
= GET_CODE (x
);
12008 if (GET_RTX_CLASS (code
) == '2'
12009 || GET_RTX_CLASS (code
) == 'c')
12011 rtx x0
= XEXP (x
, 0);
12012 rtx x1
= XEXP (x
, 1);
12015 return 1 + 2 * count_rtxs (x0
);
12017 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
12018 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
12019 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12020 return 2 + 2 * count_rtxs (x0
)
12021 + count_rtxs (x
== XEXP (x1
, 0)
12022 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12024 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
12025 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
12026 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12027 return 2 + 2 * count_rtxs (x1
)
12028 + count_rtxs (x
== XEXP (x0
, 0)
12029 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12032 fmt
= GET_RTX_FORMAT (code
);
12033 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12035 ret
+= count_rtxs (XEXP (x
, i
));
12036 else if (fmt
[i
] == 'E')
12037 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12038 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12043 /* Utility function for following routine. Called when X is part of a value
12044 being stored into last_set_value. Sets last_set_table_tick
12045 for each register mentioned. Similar to mention_regs in cse.c */
12048 update_table_tick (rtx x
)
12050 enum rtx_code code
= GET_CODE (x
);
12051 const char *fmt
= GET_RTX_FORMAT (code
);
12056 unsigned int regno
= REGNO (x
);
12057 unsigned int endregno
= END_REGNO (x
);
12060 for (r
= regno
; r
< endregno
; r
++)
12062 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, r
);
12063 rsp
->last_set_table_tick
= label_tick
;
12069 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12072 /* Check for identical subexpressions. If x contains
12073 identical subexpression we only have to traverse one of
12075 if (i
== 0 && ARITHMETIC_P (x
))
12077 /* Note that at this point x1 has already been
12079 rtx x0
= XEXP (x
, 0);
12080 rtx x1
= XEXP (x
, 1);
12082 /* If x0 and x1 are identical then there is no need to
12087 /* If x0 is identical to a subexpression of x1 then while
12088 processing x1, x0 has already been processed. Thus we
12089 are done with x. */
12090 if (ARITHMETIC_P (x1
)
12091 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12094 /* If x1 is identical to a subexpression of x0 then we
12095 still have to process the rest of x0. */
12096 if (ARITHMETIC_P (x0
)
12097 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12099 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12104 update_table_tick (XEXP (x
, i
));
12106 else if (fmt
[i
] == 'E')
12107 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12108 update_table_tick (XVECEXP (x
, i
, j
));
12111 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12112 are saying that the register is clobbered and we no longer know its
12113 value. If INSN is zero, don't update reg_stat[].last_set; this is
12114 only permitted with VALUE also zero and is used to invalidate the
12118 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12120 unsigned int regno
= REGNO (reg
);
12121 unsigned int endregno
= END_REGNO (reg
);
12123 reg_stat_type
*rsp
;
12125 /* If VALUE contains REG and we have a previous value for REG, substitute
12126 the previous value. */
12127 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12131 /* Set things up so get_last_value is allowed to see anything set up to
12133 subst_low_luid
= DF_INSN_LUID (insn
);
12134 tem
= get_last_value (reg
);
12136 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12137 it isn't going to be useful and will take a lot of time to process,
12138 so just use the CLOBBER. */
12142 if (ARITHMETIC_P (tem
)
12143 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12144 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12145 tem
= XEXP (tem
, 0);
12146 else if (count_occurrences (value
, reg
, 1) >= 2)
12148 /* If there are two or more occurrences of REG in VALUE,
12149 prevent the value from growing too much. */
12150 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12151 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12154 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12158 /* For each register modified, show we don't know its value, that
12159 we don't know about its bitwise content, that its value has been
12160 updated, and that we don't know the location of the death of the
12162 for (i
= regno
; i
< endregno
; i
++)
12164 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12167 rsp
->last_set
= insn
;
12169 rsp
->last_set_value
= 0;
12170 rsp
->last_set_mode
= VOIDmode
;
12171 rsp
->last_set_nonzero_bits
= 0;
12172 rsp
->last_set_sign_bit_copies
= 0;
12173 rsp
->last_death
= 0;
12174 rsp
->truncated_to_mode
= VOIDmode
;
12177 /* Mark registers that are being referenced in this value. */
12179 update_table_tick (value
);
12181 /* Now update the status of each register being set.
12182 If someone is using this register in this block, set this register
12183 to invalid since we will get confused between the two lives in this
12184 basic block. This makes using this register always invalid. In cse, we
12185 scan the table to invalidate all entries using this register, but this
12186 is too much work for us. */
12188 for (i
= regno
; i
< endregno
; i
++)
12190 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12191 rsp
->last_set_label
= label_tick
;
12193 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12194 rsp
->last_set_invalid
= 1;
12196 rsp
->last_set_invalid
= 0;
12199 /* The value being assigned might refer to X (like in "x++;"). In that
12200 case, we must replace it with (clobber (const_int 0)) to prevent
12202 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12203 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12205 value
= copy_rtx (value
);
12206 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12210 /* For the main register being modified, update the value, the mode, the
12211 nonzero bits, and the number of sign bit copies. */
12213 rsp
->last_set_value
= value
;
12217 enum machine_mode mode
= GET_MODE (reg
);
12218 subst_low_luid
= DF_INSN_LUID (insn
);
12219 rsp
->last_set_mode
= mode
;
12220 if (GET_MODE_CLASS (mode
) == MODE_INT
12221 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
12222 mode
= nonzero_bits_mode
;
12223 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12224 rsp
->last_set_sign_bit_copies
12225 = num_sign_bit_copies (value
, GET_MODE (reg
));
12229 /* Called via note_stores from record_dead_and_set_regs to handle one
12230 SET or CLOBBER in an insn. DATA is the instruction in which the
12231 set is occurring. */
12234 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12236 rtx record_dead_insn
= (rtx
) data
;
12238 if (GET_CODE (dest
) == SUBREG
)
12239 dest
= SUBREG_REG (dest
);
12241 if (!record_dead_insn
)
12244 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12250 /* If we are setting the whole register, we know its value. Otherwise
12251 show that we don't know the value. We can handle SUBREG in
12253 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12254 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12255 else if (GET_CODE (setter
) == SET
12256 && GET_CODE (SET_DEST (setter
)) == SUBREG
12257 && SUBREG_REG (SET_DEST (setter
)) == dest
12258 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
12259 && subreg_lowpart_p (SET_DEST (setter
)))
12260 record_value_for_reg (dest
, record_dead_insn
,
12261 gen_lowpart (GET_MODE (dest
),
12262 SET_SRC (setter
)));
12264 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12266 else if (MEM_P (dest
)
12267 /* Ignore pushes, they clobber nothing. */
12268 && ! push_operand (dest
, GET_MODE (dest
)))
12269 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12272 /* Update the records of when each REG was most recently set or killed
12273 for the things done by INSN. This is the last thing done in processing
12274 INSN in the combiner loop.
12276 We update reg_stat[], in particular fields last_set, last_set_value,
12277 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12278 last_death, and also the similar information mem_last_set (which insn
12279 most recently modified memory) and last_call_luid (which insn was the
12280 most recent subroutine call). */
12283 record_dead_and_set_regs (rtx insn
)
12288 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12290 if (REG_NOTE_KIND (link
) == REG_DEAD
12291 && REG_P (XEXP (link
, 0)))
12293 unsigned int regno
= REGNO (XEXP (link
, 0));
12294 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12296 for (i
= regno
; i
< endregno
; i
++)
12298 reg_stat_type
*rsp
;
12300 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12301 rsp
->last_death
= insn
;
12304 else if (REG_NOTE_KIND (link
) == REG_INC
)
12305 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12310 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12311 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
12313 reg_stat_type
*rsp
;
12315 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12316 rsp
->last_set_invalid
= 1;
12317 rsp
->last_set
= insn
;
12318 rsp
->last_set_value
= 0;
12319 rsp
->last_set_mode
= VOIDmode
;
12320 rsp
->last_set_nonzero_bits
= 0;
12321 rsp
->last_set_sign_bit_copies
= 0;
12322 rsp
->last_death
= 0;
12323 rsp
->truncated_to_mode
= VOIDmode
;
12326 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12328 /* We can't combine into a call pattern. Remember, though, that
12329 the return value register is set at this LUID. We could
12330 still replace a register with the return value from the
12331 wrong subroutine call! */
12332 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12335 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12338 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12339 register present in the SUBREG, so for each such SUBREG go back and
12340 adjust nonzero and sign bit information of the registers that are
12341 known to have some zero/sign bits set.
12343 This is needed because when combine blows the SUBREGs away, the
12344 information on zero/sign bits is lost and further combines can be
12345 missed because of that. */
12348 record_promoted_value (rtx insn
, rtx subreg
)
12351 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12352 enum machine_mode mode
= GET_MODE (subreg
);
12354 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
12357 for (links
= LOG_LINKS (insn
); links
;)
12359 reg_stat_type
*rsp
;
12361 insn
= XEXP (links
, 0);
12362 set
= single_set (insn
);
12364 if (! set
|| !REG_P (SET_DEST (set
))
12365 || REGNO (SET_DEST (set
)) != regno
12366 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12368 links
= XEXP (links
, 1);
12372 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12373 if (rsp
->last_set
== insn
)
12375 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12376 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12379 if (REG_P (SET_SRC (set
)))
12381 regno
= REGNO (SET_SRC (set
));
12382 links
= LOG_LINKS (insn
);
12389 /* Check if X, a register, is known to contain a value already
12390 truncated to MODE. In this case we can use a subreg to refer to
12391 the truncated value even though in the generic case we would need
12392 an explicit truncation. */
12395 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12397 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12398 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12401 || rsp
->truncation_label
< label_tick_ebb_start
)
12403 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12405 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
12406 GET_MODE_BITSIZE (truncated
)))
12411 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12412 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12413 might be able to turn a truncate into a subreg using this information.
12414 Return -1 if traversing *P is complete or 0 otherwise. */
12417 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12420 enum machine_mode truncated_mode
;
12421 reg_stat_type
*rsp
;
12423 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12425 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12426 truncated_mode
= GET_MODE (x
);
12428 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12431 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode
),
12432 GET_MODE_BITSIZE (original_mode
)))
12435 x
= SUBREG_REG (x
);
12437 /* ??? For hard-regs we now record everything. We might be able to
12438 optimize this using last_set_mode. */
12439 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12440 truncated_mode
= GET_MODE (x
);
12444 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12445 if (rsp
->truncated_to_mode
== 0
12446 || rsp
->truncation_label
< label_tick_ebb_start
12447 || (GET_MODE_SIZE (truncated_mode
)
12448 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12450 rsp
->truncated_to_mode
= truncated_mode
;
12451 rsp
->truncation_label
= label_tick
;
12457 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12458 the modes they are used in. This can help truning TRUNCATEs into
12462 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12464 for_each_rtx (x
, record_truncated_value
, NULL
);
12467 /* Scan X for promoted SUBREGs. For each one found,
12468 note what it implies to the registers used in it. */
12471 check_promoted_subreg (rtx insn
, rtx x
)
12473 if (GET_CODE (x
) == SUBREG
12474 && SUBREG_PROMOTED_VAR_P (x
)
12475 && REG_P (SUBREG_REG (x
)))
12476 record_promoted_value (insn
, x
);
12479 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12482 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12486 check_promoted_subreg (insn
, XEXP (x
, i
));
12490 if (XVEC (x
, i
) != 0)
12491 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12492 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12498 /* Verify that all the registers and memory references mentioned in *LOC are
12499 still valid. *LOC was part of a value set in INSN when label_tick was
12500 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12501 the invalid references with (clobber (const_int 0)) and return 1. This
12502 replacement is useful because we often can get useful information about
12503 the form of a value (e.g., if it was produced by a shift that always
12504 produces -1 or 0) even though we don't know exactly what registers it
12505 was produced from. */
12508 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12511 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12512 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12517 unsigned int regno
= REGNO (x
);
12518 unsigned int endregno
= END_REGNO (x
);
12521 for (j
= regno
; j
< endregno
; j
++)
12523 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, j
);
12524 if (rsp
->last_set_invalid
12525 /* If this is a pseudo-register that was only set once and not
12526 live at the beginning of the function, it is always valid. */
12527 || (! (regno
>= FIRST_PSEUDO_REGISTER
12528 && REG_N_SETS (regno
) == 1
12529 && (!REGNO_REG_SET_P
12530 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12531 && rsp
->last_set_label
> tick
))
12534 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12541 /* If this is a memory reference, make sure that there were no stores after
12542 it that might have clobbered the value. We don't have alias info, so we
12543 assume any store invalidates it. Moreover, we only have local UIDs, so
12544 we also assume that there were stores in the intervening basic blocks. */
12545 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12546 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12549 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12553 for (i
= 0; i
< len
; i
++)
12557 /* Check for identical subexpressions. If x contains
12558 identical subexpression we only have to traverse one of
12560 if (i
== 1 && ARITHMETIC_P (x
))
12562 /* Note that at this point x0 has already been checked
12563 and found valid. */
12564 rtx x0
= XEXP (x
, 0);
12565 rtx x1
= XEXP (x
, 1);
12567 /* If x0 and x1 are identical then x is also valid. */
12571 /* If x1 is identical to a subexpression of x0 then
12572 while checking x0, x1 has already been checked. Thus
12573 it is valid and so as x. */
12574 if (ARITHMETIC_P (x0
)
12575 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12578 /* If x0 is identical to a subexpression of x1 then x is
12579 valid iff the rest of x1 is valid. */
12580 if (ARITHMETIC_P (x1
)
12581 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12583 get_last_value_validate (&XEXP (x1
,
12584 x0
== XEXP (x1
, 0) ? 1 : 0),
12585 insn
, tick
, replace
);
12588 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12592 else if (fmt
[i
] == 'E')
12593 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12594 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12595 insn
, tick
, replace
) == 0)
12599 /* If we haven't found a reason for it to be invalid, it is valid. */
12603 /* Get the last value assigned to X, if known. Some registers
12604 in the value may be replaced with (clobber (const_int 0)) if their value
12605 is known longer known reliably. */
12608 get_last_value (const_rtx x
)
12610 unsigned int regno
;
12612 reg_stat_type
*rsp
;
12614 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12615 then convert it to the desired mode. If this is a paradoxical SUBREG,
12616 we cannot predict what values the "extra" bits might have. */
12617 if (GET_CODE (x
) == SUBREG
12618 && subreg_lowpart_p (x
)
12619 && (GET_MODE_SIZE (GET_MODE (x
))
12620 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
12621 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12622 return gen_lowpart (GET_MODE (x
), value
);
12628 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12629 value
= rsp
->last_set_value
;
12631 /* If we don't have a value, or if it isn't for this basic block and
12632 it's either a hard register, set more than once, or it's a live
12633 at the beginning of the function, return 0.
12635 Because if it's not live at the beginning of the function then the reg
12636 is always set before being used (is never used without being set).
12637 And, if it's set only once, and it's always set before use, then all
12638 uses must have the same last value, even if it's not from this basic
12642 || (rsp
->last_set_label
< label_tick_ebb_start
12643 && (regno
< FIRST_PSEUDO_REGISTER
12644 || REG_N_SETS (regno
) != 1
12646 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12649 /* If the value was set in a later insn than the ones we are processing,
12650 we can't use it even if the register was only set once. */
12651 if (rsp
->last_set_label
== label_tick
12652 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12655 /* If the value has all its registers valid, return it. */
12656 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12659 /* Otherwise, make a copy and replace any invalid register with
12660 (clobber (const_int 0)). If that fails for some reason, return 0. */
12662 value
= copy_rtx (value
);
12663 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12669 /* Return nonzero if expression X refers to a REG or to memory
12670 that is set in an instruction more recent than FROM_LUID. */
12673 use_crosses_set_p (const_rtx x
, int from_luid
)
12677 enum rtx_code code
= GET_CODE (x
);
12681 unsigned int regno
= REGNO (x
);
12682 unsigned endreg
= END_REGNO (x
);
12684 #ifdef PUSH_ROUNDING
12685 /* Don't allow uses of the stack pointer to be moved,
12686 because we don't know whether the move crosses a push insn. */
12687 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12690 for (; regno
< endreg
; regno
++)
12692 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12694 && rsp
->last_set_label
== label_tick
12695 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12701 if (code
== MEM
&& mem_last_set
> from_luid
)
12704 fmt
= GET_RTX_FORMAT (code
);
12706 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12711 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12712 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12715 else if (fmt
[i
] == 'e'
12716 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12722 /* Define three variables used for communication between the following
12725 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12726 static int reg_dead_flag
;
12728 /* Function called via note_stores from reg_dead_at_p.
12730 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12731 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12734 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12736 unsigned int regno
, endregno
;
12741 regno
= REGNO (dest
);
12742 endregno
= END_REGNO (dest
);
12743 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12744 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12747 /* Return nonzero if REG is known to be dead at INSN.
12749 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12750 referencing REG, it is dead. If we hit a SET referencing REG, it is
12751 live. Otherwise, see if it is live or dead at the start of the basic
12752 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12753 must be assumed to be always live. */
12756 reg_dead_at_p (rtx reg
, rtx insn
)
12761 /* Set variables for reg_dead_at_p_1. */
12762 reg_dead_regno
= REGNO (reg
);
12763 reg_dead_endregno
= END_REGNO (reg
);
12767 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12768 we allow the machine description to decide whether use-and-clobber
12769 patterns are OK. */
12770 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12772 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12773 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12777 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12778 beginning of basic block. */
12779 block
= BLOCK_FOR_INSN (insn
);
12784 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12786 return reg_dead_flag
== 1 ? 1 : 0;
12788 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12792 if (insn
== BB_HEAD (block
))
12795 insn
= PREV_INSN (insn
);
12798 /* Look at live-in sets for the basic block that we were in. */
12799 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12800 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12806 /* Note hard registers in X that are used. */
12809 mark_used_regs_combine (rtx x
)
12811 RTX_CODE code
= GET_CODE (x
);
12812 unsigned int regno
;
12825 case ADDR_DIFF_VEC
:
12828 /* CC0 must die in the insn after it is set, so we don't need to take
12829 special note of it here. */
12835 /* If we are clobbering a MEM, mark any hard registers inside the
12836 address as used. */
12837 if (MEM_P (XEXP (x
, 0)))
12838 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12843 /* A hard reg in a wide mode may really be multiple registers.
12844 If so, mark all of them just like the first. */
12845 if (regno
< FIRST_PSEUDO_REGISTER
)
12847 /* None of this applies to the stack, frame or arg pointers. */
12848 if (regno
== STACK_POINTER_REGNUM
12849 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12850 || regno
== HARD_FRAME_POINTER_REGNUM
12852 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12853 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12855 || regno
== FRAME_POINTER_REGNUM
)
12858 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12864 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12866 rtx testreg
= SET_DEST (x
);
12868 while (GET_CODE (testreg
) == SUBREG
12869 || GET_CODE (testreg
) == ZERO_EXTRACT
12870 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12871 testreg
= XEXP (testreg
, 0);
12873 if (MEM_P (testreg
))
12874 mark_used_regs_combine (XEXP (testreg
, 0));
12876 mark_used_regs_combine (SET_SRC (x
));
12884 /* Recursively scan the operands of this expression. */
12887 const char *fmt
= GET_RTX_FORMAT (code
);
12889 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12892 mark_used_regs_combine (XEXP (x
, i
));
12893 else if (fmt
[i
] == 'E')
12897 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12898 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12904 /* Remove register number REGNO from the dead registers list of INSN.
12906 Return the note used to record the death, if there was one. */
12909 remove_death (unsigned int regno
, rtx insn
)
12911 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12914 remove_note (insn
, note
);
12919 /* For each register (hardware or pseudo) used within expression X, if its
12920 death is in an instruction with luid between FROM_LUID (inclusive) and
12921 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12922 list headed by PNOTES.
12924 That said, don't move registers killed by maybe_kill_insn.
12926 This is done when X is being merged by combination into TO_INSN. These
12927 notes will then be distributed as needed. */
12930 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12935 enum rtx_code code
= GET_CODE (x
);
12939 unsigned int regno
= REGNO (x
);
12940 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
)->last_death
;
12942 /* Don't move the register if it gets killed in between from and to. */
12943 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12944 && ! reg_referenced_p (x
, maybe_kill_insn
))
12948 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12949 && DF_INSN_LUID (where_dead
) >= from_luid
12950 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12952 rtx note
= remove_death (regno
, where_dead
);
12954 /* It is possible for the call above to return 0. This can occur
12955 when last_death points to I2 or I1 that we combined with.
12956 In that case make a new note.
12958 We must also check for the case where X is a hard register
12959 and NOTE is a death note for a range of hard registers
12960 including X. In that case, we must put REG_DEAD notes for
12961 the remaining registers in place of NOTE. */
12963 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12964 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12965 > GET_MODE_SIZE (GET_MODE (x
))))
12967 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12968 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12969 unsigned int ourend
= END_HARD_REGNO (x
);
12972 for (i
= deadregno
; i
< deadend
; i
++)
12973 if (i
< regno
|| i
>= ourend
)
12974 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
12977 /* If we didn't find any note, or if we found a REG_DEAD note that
12978 covers only part of the given reg, and we have a multi-reg hard
12979 register, then to be safe we must check for REG_DEAD notes
12980 for each register other than the first. They could have
12981 their own REG_DEAD notes lying around. */
12982 else if ((note
== 0
12984 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12985 < GET_MODE_SIZE (GET_MODE (x
)))))
12986 && regno
< FIRST_PSEUDO_REGISTER
12987 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12989 unsigned int ourend
= END_HARD_REGNO (x
);
12990 unsigned int i
, offset
;
12994 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12998 for (i
= regno
+ offset
; i
< ourend
; i
++)
12999 move_deaths (regno_reg_rtx
[i
],
13000 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13003 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13005 XEXP (note
, 1) = *pnotes
;
13009 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13015 else if (GET_CODE (x
) == SET
)
13017 rtx dest
= SET_DEST (x
);
13019 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13021 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13022 that accesses one word of a multi-word item, some
13023 piece of everything register in the expression is used by
13024 this insn, so remove any old death. */
13025 /* ??? So why do we test for equality of the sizes? */
13027 if (GET_CODE (dest
) == ZERO_EXTRACT
13028 || GET_CODE (dest
) == STRICT_LOW_PART
13029 || (GET_CODE (dest
) == SUBREG
13030 && (((GET_MODE_SIZE (GET_MODE (dest
))
13031 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13032 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13033 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13035 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13039 /* If this is some other SUBREG, we know it replaces the entire
13040 value, so use that as the destination. */
13041 if (GET_CODE (dest
) == SUBREG
)
13042 dest
= SUBREG_REG (dest
);
13044 /* If this is a MEM, adjust deaths of anything used in the address.
13045 For a REG (the only other possibility), the entire value is
13046 being replaced so the old value is not used in this insn. */
13049 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13054 else if (GET_CODE (x
) == CLOBBER
)
13057 len
= GET_RTX_LENGTH (code
);
13058 fmt
= GET_RTX_FORMAT (code
);
13060 for (i
= 0; i
< len
; i
++)
13065 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13066 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13069 else if (fmt
[i
] == 'e')
13070 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13074 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13075 pattern of an insn. X must be a REG. */
13078 reg_bitfield_target_p (rtx x
, rtx body
)
13082 if (GET_CODE (body
) == SET
)
13084 rtx dest
= SET_DEST (body
);
13086 unsigned int regno
, tregno
, endregno
, endtregno
;
13088 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13089 target
= XEXP (dest
, 0);
13090 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13091 target
= SUBREG_REG (XEXP (dest
, 0));
13095 if (GET_CODE (target
) == SUBREG
)
13096 target
= SUBREG_REG (target
);
13098 if (!REG_P (target
))
13101 tregno
= REGNO (target
), regno
= REGNO (x
);
13102 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13103 return target
== x
;
13105 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13106 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13108 return endregno
> tregno
&& regno
< endtregno
;
13111 else if (GET_CODE (body
) == PARALLEL
)
13112 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13113 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13119 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13120 as appropriate. I3 and I2 are the insns resulting from the combination
13121 insns including FROM (I2 may be zero).
13123 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13124 not need REG_DEAD notes because they are being substituted for. This
13125 saves searching in the most common cases.
13127 Each note in the list is either ignored or placed on some insns, depending
13128 on the type of note. */
13131 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13132 rtx elim_i1
, rtx elim_i0
)
13134 rtx note
, next_note
;
13137 for (note
= notes
; note
; note
= next_note
)
13139 rtx place
= 0, place2
= 0;
13141 next_note
= XEXP (note
, 1);
13142 switch (REG_NOTE_KIND (note
))
13146 /* Doesn't matter much where we put this, as long as it's somewhere.
13147 It is preferable to keep these notes on branches, which is most
13148 likely to be i3. */
13152 case REG_NON_LOCAL_GOTO
:
13157 gcc_assert (i2
&& JUMP_P (i2
));
13162 case REG_EH_REGION
:
13163 /* These notes must remain with the call or trapping instruction. */
13166 else if (i2
&& CALL_P (i2
))
13170 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13171 if (may_trap_p (i3
))
13173 else if (i2
&& may_trap_p (i2
))
13175 /* ??? Otherwise assume we've combined things such that we
13176 can now prove that the instructions can't trap. Drop the
13177 note in this case. */
13183 /* These notes must remain with the call. It should not be
13184 possible for both I2 and I3 to be a call. */
13189 gcc_assert (i2
&& CALL_P (i2
));
13195 /* Any clobbers for i3 may still exist, and so we must process
13196 REG_UNUSED notes from that insn.
13198 Any clobbers from i2 or i1 can only exist if they were added by
13199 recog_for_combine. In that case, recog_for_combine created the
13200 necessary REG_UNUSED notes. Trying to keep any original
13201 REG_UNUSED notes from these insns can cause incorrect output
13202 if it is for the same register as the original i3 dest.
13203 In that case, we will notice that the register is set in i3,
13204 and then add a REG_UNUSED note for the destination of i3, which
13205 is wrong. However, it is possible to have REG_UNUSED notes from
13206 i2 or i1 for register which were both used and clobbered, so
13207 we keep notes from i2 or i1 if they will turn into REG_DEAD
13210 /* If this register is set or clobbered in I3, put the note there
13211 unless there is one already. */
13212 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13214 if (from_insn
!= i3
)
13217 if (! (REG_P (XEXP (note
, 0))
13218 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13219 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13222 /* Otherwise, if this register is used by I3, then this register
13223 now dies here, so we must put a REG_DEAD note here unless there
13225 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13226 && ! (REG_P (XEXP (note
, 0))
13227 ? find_regno_note (i3
, REG_DEAD
,
13228 REGNO (XEXP (note
, 0)))
13229 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13231 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13239 /* These notes say something about results of an insn. We can
13240 only support them if they used to be on I3 in which case they
13241 remain on I3. Otherwise they are ignored.
13243 If the note refers to an expression that is not a constant, we
13244 must also ignore the note since we cannot tell whether the
13245 equivalence is still true. It might be possible to do
13246 slightly better than this (we only have a problem if I2DEST
13247 or I1DEST is present in the expression), but it doesn't
13248 seem worth the trouble. */
13250 if (from_insn
== i3
13251 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13256 /* These notes say something about how a register is used. They must
13257 be present on any use of the register in I2 or I3. */
13258 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13261 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13270 case REG_LABEL_TARGET
:
13271 case REG_LABEL_OPERAND
:
13272 /* This can show up in several ways -- either directly in the
13273 pattern, or hidden off in the constant pool with (or without?)
13274 a REG_EQUAL note. */
13275 /* ??? Ignore the without-reg_equal-note problem for now. */
13276 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13277 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13278 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13279 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13283 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13284 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13285 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13286 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13294 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13295 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13297 if (place
&& JUMP_P (place
)
13298 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13299 && (JUMP_LABEL (place
) == NULL
13300 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13302 rtx label
= JUMP_LABEL (place
);
13305 JUMP_LABEL (place
) = XEXP (note
, 0);
13306 else if (LABEL_P (label
))
13307 LABEL_NUSES (label
)--;
13310 if (place2
&& JUMP_P (place2
)
13311 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13312 && (JUMP_LABEL (place2
) == NULL
13313 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13315 rtx label
= JUMP_LABEL (place2
);
13318 JUMP_LABEL (place2
) = XEXP (note
, 0);
13319 else if (LABEL_P (label
))
13320 LABEL_NUSES (label
)--;
13326 /* This note says something about the value of a register prior
13327 to the execution of an insn. It is too much trouble to see
13328 if the note is still correct in all situations. It is better
13329 to simply delete it. */
13333 /* If we replaced the right hand side of FROM_INSN with a
13334 REG_EQUAL note, the original use of the dying register
13335 will not have been combined into I3 and I2. In such cases,
13336 FROM_INSN is guaranteed to be the first of the combined
13337 instructions, so we simply need to search back before
13338 FROM_INSN for the previous use or set of this register,
13339 then alter the notes there appropriately.
13341 If the register is used as an input in I3, it dies there.
13342 Similarly for I2, if it is nonzero and adjacent to I3.
13344 If the register is not used as an input in either I3 or I2
13345 and it is not one of the registers we were supposed to eliminate,
13346 there are two possibilities. We might have a non-adjacent I2
13347 or we might have somehow eliminated an additional register
13348 from a computation. For example, we might have had A & B where
13349 we discover that B will always be zero. In this case we will
13350 eliminate the reference to A.
13352 In both cases, we must search to see if we can find a previous
13353 use of A and put the death note there. */
13356 && from_insn
== i2mod
13357 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13362 && CALL_P (from_insn
)
13363 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13365 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13367 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13368 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13370 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13372 && reg_overlap_mentioned_p (XEXP (note
, 0),
13374 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13375 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13382 basic_block bb
= this_basic_block
;
13384 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13386 if (!NONDEBUG_INSN_P (tem
))
13388 if (tem
== BB_HEAD (bb
))
13393 /* If the register is being set at TEM, see if that is all
13394 TEM is doing. If so, delete TEM. Otherwise, make this
13395 into a REG_UNUSED note instead. Don't delete sets to
13396 global register vars. */
13397 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13398 || !global_regs
[REGNO (XEXP (note
, 0))])
13399 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13401 rtx set
= single_set (tem
);
13402 rtx inner_dest
= 0;
13404 rtx cc0_setter
= NULL_RTX
;
13408 for (inner_dest
= SET_DEST (set
);
13409 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13410 || GET_CODE (inner_dest
) == SUBREG
13411 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13412 inner_dest
= XEXP (inner_dest
, 0))
13415 /* Verify that it was the set, and not a clobber that
13416 modified the register.
13418 CC0 targets must be careful to maintain setter/user
13419 pairs. If we cannot delete the setter due to side
13420 effects, mark the user with an UNUSED note instead
13423 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13424 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13426 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13427 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13428 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13432 /* Move the notes and links of TEM elsewhere.
13433 This might delete other dead insns recursively.
13434 First set the pattern to something that won't use
13436 rtx old_notes
= REG_NOTES (tem
);
13438 PATTERN (tem
) = pc_rtx
;
13439 REG_NOTES (tem
) = NULL
;
13441 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13442 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13443 distribute_links (LOG_LINKS (tem
));
13445 SET_INSN_DELETED (tem
);
13450 /* Delete the setter too. */
13453 PATTERN (cc0_setter
) = pc_rtx
;
13454 old_notes
= REG_NOTES (cc0_setter
);
13455 REG_NOTES (cc0_setter
) = NULL
;
13457 distribute_notes (old_notes
, cc0_setter
,
13458 cc0_setter
, NULL_RTX
,
13459 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13460 distribute_links (LOG_LINKS (cc0_setter
));
13462 SET_INSN_DELETED (cc0_setter
);
13463 if (cc0_setter
== i2
)
13470 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13472 /* If there isn't already a REG_UNUSED note, put one
13473 here. Do not place a REG_DEAD note, even if
13474 the register is also used here; that would not
13475 match the algorithm used in lifetime analysis
13476 and can cause the consistency check in the
13477 scheduler to fail. */
13478 if (! find_regno_note (tem
, REG_UNUSED
,
13479 REGNO (XEXP (note
, 0))))
13484 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13486 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13490 /* If we are doing a 3->2 combination, and we have a
13491 register which formerly died in i3 and was not used
13492 by i2, which now no longer dies in i3 and is used in
13493 i2 but does not die in i2, and place is between i2
13494 and i3, then we may need to move a link from place to
13496 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13498 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13499 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13501 rtx links
= LOG_LINKS (place
);
13502 LOG_LINKS (place
) = 0;
13503 distribute_links (links
);
13508 if (tem
== BB_HEAD (bb
))
13514 /* If the register is set or already dead at PLACE, we needn't do
13515 anything with this note if it is still a REG_DEAD note.
13516 We check here if it is set at all, not if is it totally replaced,
13517 which is what `dead_or_set_p' checks, so also check for it being
13520 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13522 unsigned int regno
= REGNO (XEXP (note
, 0));
13523 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
13525 if (dead_or_set_p (place
, XEXP (note
, 0))
13526 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13528 /* Unless the register previously died in PLACE, clear
13529 last_death. [I no longer understand why this is
13531 if (rsp
->last_death
!= place
)
13532 rsp
->last_death
= 0;
13536 rsp
->last_death
= place
;
13538 /* If this is a death note for a hard reg that is occupying
13539 multiple registers, ensure that we are still using all
13540 parts of the object. If we find a piece of the object
13541 that is unused, we must arrange for an appropriate REG_DEAD
13542 note to be added for it. However, we can't just emit a USE
13543 and tag the note to it, since the register might actually
13544 be dead; so we recourse, and the recursive call then finds
13545 the previous insn that used this register. */
13547 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13548 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13550 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13554 for (i
= regno
; i
< endregno
; i
++)
13555 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13556 && ! find_regno_fusage (place
, USE
, i
))
13557 || dead_or_set_regno_p (place
, i
))
13562 /* Put only REG_DEAD notes for pieces that are
13563 not already dead or set. */
13565 for (i
= regno
; i
< endregno
;
13566 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13568 rtx piece
= regno_reg_rtx
[i
];
13569 basic_block bb
= this_basic_block
;
13571 if (! dead_or_set_p (place
, piece
)
13572 && ! reg_bitfield_target_p (piece
,
13575 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13578 distribute_notes (new_note
, place
, place
,
13579 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13582 else if (! refers_to_regno_p (i
, i
+ 1,
13583 PATTERN (place
), 0)
13584 && ! find_regno_fusage (place
, USE
, i
))
13585 for (tem
= PREV_INSN (place
); ;
13586 tem
= PREV_INSN (tem
))
13588 if (!NONDEBUG_INSN_P (tem
))
13590 if (tem
== BB_HEAD (bb
))
13594 if (dead_or_set_p (tem
, piece
)
13595 || reg_bitfield_target_p (piece
,
13598 add_reg_note (tem
, REG_UNUSED
, piece
);
13612 /* Any other notes should not be present at this point in the
13614 gcc_unreachable ();
13619 XEXP (note
, 1) = REG_NOTES (place
);
13620 REG_NOTES (place
) = note
;
13624 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13628 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13629 I3, I2, and I1 to new locations. This is also called to add a link
13630 pointing at I3 when I3's destination is changed. */
13633 distribute_links (rtx links
)
13635 rtx link
, next_link
;
13637 for (link
= links
; link
; link
= next_link
)
13643 next_link
= XEXP (link
, 1);
13645 /* If the insn that this link points to is a NOTE or isn't a single
13646 set, ignore it. In the latter case, it isn't clear what we
13647 can do other than ignore the link, since we can't tell which
13648 register it was for. Such links wouldn't be used by combine
13651 It is not possible for the destination of the target of the link to
13652 have been changed by combine. The only potential of this is if we
13653 replace I3, I2, and I1 by I3 and I2. But in that case the
13654 destination of I2 also remains unchanged. */
13656 if (NOTE_P (XEXP (link
, 0))
13657 || (set
= single_set (XEXP (link
, 0))) == 0)
13660 reg
= SET_DEST (set
);
13661 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13662 || GET_CODE (reg
) == STRICT_LOW_PART
)
13663 reg
= XEXP (reg
, 0);
13665 /* A LOG_LINK is defined as being placed on the first insn that uses
13666 a register and points to the insn that sets the register. Start
13667 searching at the next insn after the target of the link and stop
13668 when we reach a set of the register or the end of the basic block.
13670 Note that this correctly handles the link that used to point from
13671 I3 to I2. Also note that not much searching is typically done here
13672 since most links don't point very far away. */
13674 for (insn
= NEXT_INSN (XEXP (link
, 0));
13675 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13676 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13677 insn
= NEXT_INSN (insn
))
13678 if (DEBUG_INSN_P (insn
))
13680 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13682 if (reg_referenced_p (reg
, PATTERN (insn
)))
13686 else if (CALL_P (insn
)
13687 && find_reg_fusage (insn
, USE
, reg
))
13692 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13695 /* If we found a place to put the link, place it there unless there
13696 is already a link to the same insn as LINK at that point. */
13702 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13703 if (XEXP (link2
, 0) == XEXP (link
, 0))
13708 XEXP (link
, 1) = LOG_LINKS (place
);
13709 LOG_LINKS (place
) = link
;
13711 /* Set added_links_insn to the earliest insn we added a
13713 if (added_links_insn
== 0
13714 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13715 added_links_insn
= place
;
13721 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13722 Check whether the expression pointer to by LOC is a register or
13723 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13724 Otherwise return zero. */
13727 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13732 && (REG_P (x
) || MEM_P (x
))
13733 && ! reg_mentioned_p (x
, (rtx
) expr
))
13738 /* Check for any register or memory mentioned in EQUIV that is not
13739 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13740 of EXPR where some registers may have been replaced by constants. */
13743 unmentioned_reg_p (rtx equiv
, rtx expr
)
13745 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13749 dump_combine_stats (FILE *file
)
13753 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13754 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13758 dump_combine_total_stats (FILE *file
)
13762 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13763 total_attempts
, total_merges
, total_extras
, total_successes
);
13767 gate_handle_combine (void)
13769 return (optimize
> 0);
13772 /* Try combining insns through substitution. */
13773 static unsigned int
13774 rest_of_handle_combine (void)
13776 int rebuild_jump_labels_after_combine
;
13778 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13779 df_note_add_problem ();
13782 regstat_init_n_sets_and_refs ();
13784 rebuild_jump_labels_after_combine
13785 = combine_instructions (get_insns (), max_reg_num ());
13787 /* Combining insns may have turned an indirect jump into a
13788 direct jump. Rebuild the JUMP_LABEL fields of jumping
13790 if (rebuild_jump_labels_after_combine
)
13792 timevar_push (TV_JUMP
);
13793 rebuild_jump_labels (get_insns ());
13795 timevar_pop (TV_JUMP
);
13798 regstat_free_n_sets_and_refs ();
13802 struct rtl_opt_pass pass_combine
=
13806 "combine", /* name */
13807 gate_handle_combine
, /* gate */
13808 rest_of_handle_combine
, /* execute */
13811 0, /* static_pass_number */
13812 TV_COMBINE
, /* tv_id */
13813 PROP_cfglayout
, /* properties_required */
13814 0, /* properties_provided */
13815 0, /* properties_destroyed */
13816 0, /* todo_flags_start */
13818 TODO_df_finish
| TODO_verify_rtl_sharing
|
13819 TODO_ggc_collect
, /* todo_flags_finish */