1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts
;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges
;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras
;
121 /* Number of instructions combined in this function. */
123 static int combine_successes
;
125 /* Totals over entire compilation. */
127 static int total_attempts
, total_merges
, total_extras
, total_successes
;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs
;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs
;
146 typedef struct reg_stat_struct
{
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label
;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 DEF_VEC_O(reg_stat_type
);
256 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
258 static VEC(reg_stat_type
,heap
) *reg_stat
;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set
;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid
;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn
;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid
;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs
;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn
;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block
;
300 static bool optimize_this_for_speed_p
;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known
;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost
;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx
*uid_log_links
;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick
;
324 /* Reset to label_tick for each label. */
326 static int label_tick_ebb_start
;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode
;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid
;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
};
351 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
352 union { rtx
*r
; int *i
; } where
;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf
;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences
;
375 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
377 unsigned HOST_WIDE_INT
,
378 unsigned HOST_WIDE_INT
*);
379 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx
*, rtx
);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx
);
386 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
387 static int cant_combine_insn_p (rtx
);
388 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
389 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
390 static int contains_muldiv (rtx
);
391 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx
*find_split_point (rtx
*, rtx
);
395 static rtx
subst (rtx
, rtx
, rtx
, int, int);
396 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
397 static rtx
simplify_if_then_else (rtx
);
398 static rtx
simplify_set (rtx
);
399 static rtx
simplify_logical (rtx
);
400 static rtx
expand_compound_operation (rtx
);
401 static const_rtx
expand_field_assignment (const_rtx
);
402 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
403 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
404 static rtx
extract_left_shift (rtx
, int);
405 static rtx
make_compound_operation (rtx
, enum rtx_code
);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
407 unsigned HOST_WIDE_INT
*);
408 static rtx
canon_reg_for_combine (rtx
, rtx
);
409 static rtx
force_to_mode (rtx
, enum machine_mode
,
410 unsigned HOST_WIDE_INT
, int);
411 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
412 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
413 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
414 static rtx
make_field_assignment (rtx
);
415 static rtx
apply_distributive_law (rtx
);
416 static rtx
distribute_and_simplify_rtx (rtx
, int);
417 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
418 unsigned HOST_WIDE_INT
);
419 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
420 unsigned HOST_WIDE_INT
);
421 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
422 HOST_WIDE_INT
, enum machine_mode
, int *);
423 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
424 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
426 static int recog_for_combine (rtx
*, rtx
, rtx
*);
427 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
428 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
429 static void update_table_tick (rtx
);
430 static void record_value_for_reg (rtx
, rtx
, rtx
);
431 static void check_promoted_subreg (rtx
, rtx
);
432 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
433 static void record_dead_and_set_regs (rtx
);
434 static int get_last_value_validate (rtx
*, rtx
, int, int);
435 static rtx
get_last_value (const_rtx
);
436 static int use_crosses_set_p (const_rtx
, int);
437 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
438 static int reg_dead_at_p (rtx
, rtx
);
439 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
440 static int reg_bitfield_target_p (rtx
, rtx
);
441 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
442 static void distribute_links (rtx
);
443 static void mark_used_regs_combine (rtx
);
444 static void record_promoted_value (rtx
, rtx
);
445 static int unmentioned_reg_p_1 (rtx
*, void *);
446 static bool unmentioned_reg_p (rtx
, rtx
);
447 static int record_truncated_value (rtx
*, void *);
448 static void record_truncated_values (rtx
*, void *);
449 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
450 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern
, rtx insn
)
486 ret
= split_insns (pattern
, insn
);
487 nregs
= max_reg_num ();
488 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
489 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest
, rtx
*loc
)
503 enum rtx_code code
= GET_CODE (x
);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x
)) != CC0
526 && GET_CODE (SET_DEST (x
)) != PC
527 && !REG_P (SET_DEST (x
))
528 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x
)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
531 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
533 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
536 return find_single_use_1 (dest
, &SET_SRC (x
));
540 return find_single_use_1 (dest
, &XEXP (x
, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt
= GET_RTX_FORMAT (code
);
550 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
554 if (dest
== XEXP (x
, i
)
555 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
556 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
559 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
562 result
= this_result
;
563 else if (this_result
)
564 /* Duplicate usage. */
567 else if (fmt
[i
] == 'E')
571 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
573 if (XVECEXP (x
, i
, j
) == dest
575 && REG_P (XVECEXP (x
, i
, j
))
576 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
579 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
582 result
= this_result
;
583 else if (this_result
)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
618 next
= NEXT_INSN (insn
);
620 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
623 result
= find_single_use_1 (dest
, &PATTERN (next
));
633 bb
= BLOCK_FOR_INSN (insn
);
634 for (next
= NEXT_INSN (insn
);
635 next
&& BLOCK_FOR_INSN (next
) == bb
;
636 next
= NEXT_INSN (next
))
637 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
639 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
640 if (XEXP (link
, 0) == insn
)
645 result
= find_single_use_1 (dest
, &PATTERN (next
));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx
*into
, rtx newval
)
667 if (oldval
== newval
)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
676 && CONST_INT_P (newval
))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval
)
681 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval
) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval
))));
691 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval
, 0))));
696 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
698 buf
= XNEW (struct undo
);
700 buf
->kind
= UNDO_RTX
;
702 buf
->old_contents
.r
= oldval
;
705 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into
, int newval
)
720 if (oldval
== newval
)
724 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
726 buf
= XNEW (struct undo
);
728 buf
->kind
= UNDO_INT
;
730 buf
->old_contents
.i
= oldval
;
733 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
747 enum machine_mode oldval
= GET_MODE (*into
);
749 if (oldval
== newval
)
753 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
755 buf
= XNEW (struct undo
);
757 buf
->kind
= UNDO_MODE
;
759 buf
->old_contents
.m
= oldval
;
760 adjust_reg_mode (*into
, newval
);
762 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
,
780 int i1_cost
, i2_cost
, i3_cost
;
781 int new_i2_cost
, new_i3_cost
;
782 int old_cost
, new_cost
;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost
= INSN_COST (i2
);
786 i3_cost
= INSN_COST (i3
);
790 i1_cost
= INSN_COST (i1
);
791 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
792 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
796 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
804 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
805 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
806 ? new_i2_cost
+ new_i3_cost
: 0;
810 new_cost
= new_i3_cost
;
814 if (undobuf
.other_insn
)
816 int old_other_cost
, new_other_cost
;
818 old_other_cost
= INSN_COST (undobuf
.other_insn
);
819 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
820 if (old_other_cost
> 0 && new_other_cost
> 0)
822 old_cost
+= old_other_cost
;
823 new_cost
+= new_other_cost
;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost
> old_cost
)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
841 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
842 i1_cost
, i2_cost
, i3_cost
, old_cost
);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2
), INSN_UID (i3
));
849 fprintf (dump_file
, "original costs %d + %d = %d\n",
850 i2_cost
, i3_cost
, old_cost
);
855 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
856 new_i2_cost
, new_i3_cost
, new_cost
);
859 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2
) = new_i2_cost
;
867 INSN_COST (i3
) = new_i3_cost
;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
887 next
= NEXT_INSN (insn
);
888 if (INSN_P (insn
) && noop_move_p (insn
))
891 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
893 delete_insn_and_edges (insn
);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref
*def_vec
, *use_vec
;
909 next_use
= XCNEWVEC (rtx
, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb
, insn
)
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn
));
930 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
932 df_ref def
= *def_vec
;
933 int regno
= DF_REF_REGNO (def
);
936 if (!next_use
[regno
])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
943 /* Do not make the log link for frame pointer. */
944 if ((regno
== FRAME_POINTER_REGNUM
945 && (! reload_completed
|| frame_pointer_needed
))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno
== HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed
|| frame_pointer_needed
))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
956 use_insn
= next_use
[regno
];
957 if (BLOCK_FOR_INSN (use_insn
) == bb
)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno
>= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn
)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links
= LOG_LINKS (use_insn
); links
;
972 links
= XEXP (links
, 1))
973 if (insn
== XEXP (links
, 0))
977 LOG_LINKS (use_insn
) =
978 alloc_INSN_LIST (insn
, LOG_LINKS (use_insn
));
981 next_use
[regno
] = NULL_RTX
;
984 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
986 df_ref use
= *use_vec
;
987 int regno
= DF_REF_REGNO (use
);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
994 next_use
[regno
] = insn
;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1011 free_INSN_LIST_list (&LOG_LINKS (insn
));
1017 /* Main entry point for combiner. F is the first insn of the function.
1018 NREGS is the first unused pseudo-reg number.
1020 Return nonzero if the combiner has turned an indirect jump
1021 instruction into a direct jump. */
1023 combine_instructions (rtx f
, unsigned int nregs
)
1029 rtx links
, nextlinks
;
1032 int new_direct_jump_p
= 0;
1034 for (first
= f
; first
&& !INSN_P (first
); )
1035 first
= NEXT_INSN (first
);
1039 combine_attempts
= 0;
1042 combine_successes
= 0;
1044 rtl_hooks
= combine_rtl_hooks
;
1046 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1048 init_recog_no_volatile ();
1050 /* Allocate array for insn info. */
1051 max_uid_known
= get_max_uid ();
1052 uid_log_links
= XCNEWVEC (rtx
, max_uid_known
+ 1);
1053 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1055 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1057 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1058 problems when, for example, we have j <<= 1 in a loop. */
1060 nonzero_sign_valid
= 0;
1062 /* Scan all SETs and see if we can deduce anything about what
1063 bits are known to be zero for some registers and how many copies
1064 of the sign bit are known to exist for those registers.
1066 Also set any known values so that we can use it while searching
1067 for what bits are known to be set. */
1069 setup_incoming_promotions (first
);
1071 create_log_links ();
1072 label_tick_ebb_start
= ENTRY_BLOCK_PTR
->index
;
1073 FOR_EACH_BB (this_basic_block
)
1075 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1078 label_tick
= this_basic_block
->index
;
1079 if (!single_pred_p (this_basic_block
)
1080 || single_pred (this_basic_block
)->index
!= label_tick
- 1)
1081 label_tick_ebb_start
= label_tick
;
1082 FOR_BB_INSNS (this_basic_block
, insn
)
1083 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1085 subst_low_luid
= DF_INSN_LUID (insn
);
1088 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1090 record_dead_and_set_regs (insn
);
1093 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1094 if (REG_NOTE_KIND (links
) == REG_INC
)
1095 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1099 /* Record the current insn_rtx_cost of this instruction. */
1100 if (NONJUMP_INSN_P (insn
))
1101 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1102 optimize_this_for_speed_p
);
1104 fprintf(dump_file
, "insn_cost %d: %d\n",
1105 INSN_UID (insn
), INSN_COST (insn
));
1109 nonzero_sign_valid
= 1;
1111 /* Now scan all the insns in forward order. */
1113 label_tick_ebb_start
= ENTRY_BLOCK_PTR
->index
;
1115 setup_incoming_promotions (first
);
1117 FOR_EACH_BB (this_basic_block
)
1119 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1122 label_tick
= this_basic_block
->index
;
1123 if (!single_pred_p (this_basic_block
)
1124 || single_pred (this_basic_block
)->index
!= label_tick
- 1)
1125 label_tick_ebb_start
= label_tick
;
1126 rtl_profile_for_bb (this_basic_block
);
1127 for (insn
= BB_HEAD (this_basic_block
);
1128 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1129 insn
= next
? next
: NEXT_INSN (insn
))
1134 /* See if we know about function return values before this
1135 insn based upon SUBREG flags. */
1136 check_promoted_subreg (insn
, PATTERN (insn
));
1138 /* See if we can find hardregs and subreg of pseudos in
1139 narrower modes. This could help turning TRUNCATEs
1141 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1143 /* Try this insn with each insn it links back to. */
1145 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1146 if ((next
= try_combine (insn
, XEXP (links
, 0),
1147 NULL_RTX
, &new_direct_jump_p
)) != 0)
1150 /* Try each sequence of three linked insns ending with this one. */
1152 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1154 rtx link
= XEXP (links
, 0);
1156 /* If the linked insn has been replaced by a note, then there
1157 is no point in pursuing this chain any further. */
1161 for (nextlinks
= LOG_LINKS (link
);
1163 nextlinks
= XEXP (nextlinks
, 1))
1164 if ((next
= try_combine (insn
, link
,
1165 XEXP (nextlinks
, 0),
1166 &new_direct_jump_p
)) != 0)
1171 /* Try to combine a jump insn that uses CC0
1172 with a preceding insn that sets CC0, and maybe with its
1173 logical predecessor as well.
1174 This is how we make decrement-and-branch insns.
1175 We need this special code because data flow connections
1176 via CC0 do not get entered in LOG_LINKS. */
1179 && (prev
= prev_nonnote_insn (insn
)) != 0
1180 && NONJUMP_INSN_P (prev
)
1181 && sets_cc0_p (PATTERN (prev
)))
1183 if ((next
= try_combine (insn
, prev
,
1184 NULL_RTX
, &new_direct_jump_p
)) != 0)
1187 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1188 nextlinks
= XEXP (nextlinks
, 1))
1189 if ((next
= try_combine (insn
, prev
,
1190 XEXP (nextlinks
, 0),
1191 &new_direct_jump_p
)) != 0)
1195 /* Do the same for an insn that explicitly references CC0. */
1196 if (NONJUMP_INSN_P (insn
)
1197 && (prev
= prev_nonnote_insn (insn
)) != 0
1198 && NONJUMP_INSN_P (prev
)
1199 && sets_cc0_p (PATTERN (prev
))
1200 && GET_CODE (PATTERN (insn
)) == SET
1201 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1203 if ((next
= try_combine (insn
, prev
,
1204 NULL_RTX
, &new_direct_jump_p
)) != 0)
1207 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1208 nextlinks
= XEXP (nextlinks
, 1))
1209 if ((next
= try_combine (insn
, prev
,
1210 XEXP (nextlinks
, 0),
1211 &new_direct_jump_p
)) != 0)
1215 /* Finally, see if any of the insns that this insn links to
1216 explicitly references CC0. If so, try this insn, that insn,
1217 and its predecessor if it sets CC0. */
1218 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1219 if (NONJUMP_INSN_P (XEXP (links
, 0))
1220 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
1221 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
1222 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
1223 && NONJUMP_INSN_P (prev
)
1224 && sets_cc0_p (PATTERN (prev
))
1225 && (next
= try_combine (insn
, XEXP (links
, 0),
1226 prev
, &new_direct_jump_p
)) != 0)
1230 /* Try combining an insn with two different insns whose results it
1232 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1233 for (nextlinks
= XEXP (links
, 1); nextlinks
;
1234 nextlinks
= XEXP (nextlinks
, 1))
1235 if ((next
= try_combine (insn
, XEXP (links
, 0),
1236 XEXP (nextlinks
, 0),
1237 &new_direct_jump_p
)) != 0)
1240 /* Try this insn with each REG_EQUAL note it links back to. */
1241 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1244 rtx temp
= XEXP (links
, 0);
1245 if ((set
= single_set (temp
)) != 0
1246 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1247 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1248 /* Avoid using a register that may already been marked
1249 dead by an earlier instruction. */
1250 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1251 && (GET_MODE (note
) == VOIDmode
1252 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1253 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1255 /* Temporarily replace the set's source with the
1256 contents of the REG_EQUAL note. The insn will
1257 be deleted or recognized by try_combine. */
1258 rtx orig
= SET_SRC (set
);
1259 SET_SRC (set
) = note
;
1261 i2mod_old_rhs
= copy_rtx (orig
);
1262 i2mod_new_rhs
= copy_rtx (note
);
1263 next
= try_combine (insn
, i2mod
, NULL_RTX
,
1264 &new_direct_jump_p
);
1268 SET_SRC (set
) = orig
;
1273 record_dead_and_set_regs (insn
);
1281 default_rtl_profile ();
1284 new_direct_jump_p
|= purge_all_dead_edges ();
1285 delete_noop_moves ();
1288 free (uid_log_links
);
1289 free (uid_insn_cost
);
1290 VEC_free (reg_stat_type
, heap
, reg_stat
);
1293 struct undo
*undo
, *next
;
1294 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1302 total_attempts
+= combine_attempts
;
1303 total_merges
+= combine_merges
;
1304 total_extras
+= combine_extras
;
1305 total_successes
+= combine_successes
;
1307 nonzero_sign_valid
= 0;
1308 rtl_hooks
= general_rtl_hooks
;
1310 /* Make recognizer allow volatile MEMs again. */
1313 return new_direct_jump_p
;
1316 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1319 init_reg_last (void)
1324 for (i
= 0; VEC_iterate (reg_stat_type
, reg_stat
, i
, p
); ++i
)
1325 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1328 /* Set up any promoted values for incoming argument registers. */
1331 setup_incoming_promotions (rtx first
)
1334 bool strictly_local
= false;
1336 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1337 arg
= TREE_CHAIN (arg
))
1339 rtx reg
= DECL_INCOMING_RTL (arg
);
1341 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1343 /* Only continue if the incoming argument is in a register. */
1347 /* Determine, if possible, whether all call sites of the current
1348 function lie within the current compilation unit. (This does
1349 take into account the exporting of a function via taking its
1350 address, and so forth.) */
1351 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1353 /* The mode and signedness of the argument before any promotions happen
1354 (equal to the mode of the pseudo holding it at that stage). */
1355 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1356 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1358 /* The mode and signedness of the argument after any source language and
1359 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1360 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1361 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1363 /* The mode and signedness of the argument as it is actually passed,
1364 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1365 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1366 TREE_TYPE (cfun
->decl
), 0);
1368 /* The mode of the register in which the argument is being passed. */
1369 mode4
= GET_MODE (reg
);
1371 /* Eliminate sign extensions in the callee when possible. Only
1373 (a) a mode promotion has occurred;
1374 (b) the mode of the register is the same as the mode of
1375 the argument as it is passed; and
1376 (c) the signedness does not change across any of the promotions; and
1377 (d) when no language-level promotions (which we cannot guarantee
1378 will have been done by an external caller) are necessary,
1379 unless we know that this function is only ever called from
1380 the current compilation unit -- all of whose call sites will
1381 do the mode1 --> mode2 promotion. */
1385 && (mode1
== mode2
|| strictly_local
))
1387 /* Record that the value was promoted from mode1 to mode3,
1388 so that any sign extension at the head of the current
1389 function may be eliminated. */
1391 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1392 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1393 record_value_for_reg (reg
, first
, x
);
1398 /* Called via note_stores. If X is a pseudo that is narrower than
1399 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1401 If we are setting only a portion of X and we can't figure out what
1402 portion, assume all bits will be used since we don't know what will
1405 Similarly, set how many bits of X are known to be copies of the sign bit
1406 at all locations in the function. This is the smallest number implied
1410 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1412 rtx insn
= (rtx
) data
;
1416 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1417 /* If this register is undefined at the start of the file, we can't
1418 say what its contents were. */
1419 && ! REGNO_REG_SET_P
1420 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1421 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1423 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1425 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1427 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1428 rsp
->sign_bit_copies
= 1;
1432 /* If this register is being initialized using itself, and the
1433 register is uninitialized in this basic block, and there are
1434 no LOG_LINKS which set the register, then part of the
1435 register is uninitialized. In that case we can't assume
1436 anything about the number of nonzero bits.
1438 ??? We could do better if we checked this in
1439 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1440 could avoid making assumptions about the insn which initially
1441 sets the register, while still using the information in other
1442 insns. We would have to be careful to check every insn
1443 involved in the combination. */
1446 && reg_referenced_p (x
, PATTERN (insn
))
1447 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1452 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1454 if (dead_or_set_p (XEXP (link
, 0), x
))
1459 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1460 rsp
->sign_bit_copies
= 1;
1465 /* If this is a complex assignment, see if we can convert it into a
1466 simple assignment. */
1467 set
= expand_field_assignment (set
);
1469 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1470 set what we know about X. */
1472 if (SET_DEST (set
) == x
1473 || (GET_CODE (SET_DEST (set
)) == SUBREG
1474 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1475 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1476 && SUBREG_REG (SET_DEST (set
)) == x
))
1478 rtx src
= SET_SRC (set
);
1480 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1481 /* If X is narrower than a word and SRC is a non-negative
1482 constant that would appear negative in the mode of X,
1483 sign-extend it for use in reg_stat[].nonzero_bits because some
1484 machines (maybe most) will actually do the sign-extension
1485 and this is the conservative approach.
1487 ??? For 2.5, try to tighten up the MD files in this regard
1488 instead of this kludge. */
1490 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1491 && CONST_INT_P (src
)
1493 && 0 != (INTVAL (src
)
1494 & ((HOST_WIDE_INT
) 1
1495 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1496 src
= GEN_INT (INTVAL (src
)
1497 | ((HOST_WIDE_INT
) (-1)
1498 << GET_MODE_BITSIZE (GET_MODE (x
))));
1501 /* Don't call nonzero_bits if it cannot change anything. */
1502 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1503 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1504 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1505 if (rsp
->sign_bit_copies
== 0
1506 || rsp
->sign_bit_copies
> num
)
1507 rsp
->sign_bit_copies
= num
;
1511 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1512 rsp
->sign_bit_copies
= 1;
1517 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1518 insns that were previously combined into I3 or that will be combined
1519 into the merger of INSN and I3.
1521 Return 0 if the combination is not allowed for any reason.
1523 If the combination is allowed, *PDEST will be set to the single
1524 destination of INSN and *PSRC to the single source, and this function
1528 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1529 rtx
*pdest
, rtx
*psrc
)
1538 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1539 && next_active_insn (succ
) == i3
)
1540 : next_active_insn (insn
) == i3
);
1542 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1543 or a PARALLEL consisting of such a SET and CLOBBERs.
1545 If INSN has CLOBBER parallel parts, ignore them for our processing.
1546 By definition, these happen during the execution of the insn. When it
1547 is merged with another insn, all bets are off. If they are, in fact,
1548 needed and aren't also supplied in I3, they may be added by
1549 recog_for_combine. Otherwise, it won't match.
1551 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1554 Get the source and destination of INSN. If more than one, can't
1557 if (GET_CODE (PATTERN (insn
)) == SET
)
1558 set
= PATTERN (insn
);
1559 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1560 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1562 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1564 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1567 switch (GET_CODE (elt
))
1569 /* This is important to combine floating point insns
1570 for the SH4 port. */
1572 /* Combining an isolated USE doesn't make sense.
1573 We depend here on combinable_i3pat to reject them. */
1574 /* The code below this loop only verifies that the inputs of
1575 the SET in INSN do not change. We call reg_set_between_p
1576 to verify that the REG in the USE does not change between
1578 If the USE in INSN was for a pseudo register, the matching
1579 insn pattern will likely match any register; combining this
1580 with any other USE would only be safe if we knew that the
1581 used registers have identical values, or if there was
1582 something to tell them apart, e.g. different modes. For
1583 now, we forgo such complicated tests and simply disallow
1584 combining of USES of pseudo registers with any other USE. */
1585 if (REG_P (XEXP (elt
, 0))
1586 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1588 rtx i3pat
= PATTERN (i3
);
1589 int i
= XVECLEN (i3pat
, 0) - 1;
1590 unsigned int regno
= REGNO (XEXP (elt
, 0));
1594 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1596 if (GET_CODE (i3elt
) == USE
1597 && REG_P (XEXP (i3elt
, 0))
1598 && (REGNO (XEXP (i3elt
, 0)) == regno
1599 ? reg_set_between_p (XEXP (elt
, 0),
1600 PREV_INSN (insn
), i3
)
1601 : regno
>= FIRST_PSEUDO_REGISTER
))
1608 /* We can ignore CLOBBERs. */
1613 /* Ignore SETs whose result isn't used but not those that
1614 have side-effects. */
1615 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1616 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1617 || INTVAL (XEXP (note
, 0)) <= 0)
1618 && ! side_effects_p (elt
))
1621 /* If we have already found a SET, this is a second one and
1622 so we cannot combine with this insn. */
1630 /* Anything else means we can't combine. */
1636 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1637 so don't do anything with it. */
1638 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1647 set
= expand_field_assignment (set
);
1648 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1650 /* Don't eliminate a store in the stack pointer. */
1651 if (dest
== stack_pointer_rtx
1652 /* Don't combine with an insn that sets a register to itself if it has
1653 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1654 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1655 /* Can't merge an ASM_OPERANDS. */
1656 || GET_CODE (src
) == ASM_OPERANDS
1657 /* Can't merge a function call. */
1658 || GET_CODE (src
) == CALL
1659 /* Don't eliminate a function call argument. */
1661 && (find_reg_fusage (i3
, USE
, dest
)
1663 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1664 && global_regs
[REGNO (dest
)])))
1665 /* Don't substitute into an incremented register. */
1666 || FIND_REG_INC_NOTE (i3
, dest
)
1667 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1668 /* Don't substitute into a non-local goto, this confuses CFG. */
1669 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1670 /* Make sure that DEST is not used after SUCC but before I3. */
1671 || (succ
&& ! all_adjacent
1672 && reg_used_between_p (dest
, succ
, i3
))
1673 /* Make sure that the value that is to be substituted for the register
1674 does not use any registers whose values alter in between. However,
1675 If the insns are adjacent, a use can't cross a set even though we
1676 think it might (this can happen for a sequence of insns each setting
1677 the same destination; last_set of that register might point to
1678 a NOTE). If INSN has a REG_EQUIV note, the register is always
1679 equivalent to the memory so the substitution is valid even if there
1680 are intervening stores. Also, don't move a volatile asm or
1681 UNSPEC_VOLATILE across any other insns. */
1684 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1685 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1686 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1687 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1688 /* Don't combine across a CALL_INSN, because that would possibly
1689 change whether the life span of some REGs crosses calls or not,
1690 and it is a pain to update that information.
1691 Exception: if source is a constant, moving it later can't hurt.
1692 Accept that as a special case. */
1693 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1696 /* DEST must either be a REG or CC0. */
1699 /* If register alignment is being enforced for multi-word items in all
1700 cases except for parameters, it is possible to have a register copy
1701 insn referencing a hard register that is not allowed to contain the
1702 mode being copied and which would not be valid as an operand of most
1703 insns. Eliminate this problem by not combining with such an insn.
1705 Also, on some machines we don't want to extend the life of a hard
1709 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1710 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1711 /* Don't extend the life of a hard register unless it is
1712 user variable (if we have few registers) or it can't
1713 fit into the desired register (meaning something special
1715 Also avoid substituting a return register into I3, because
1716 reload can't handle a conflict with constraints of other
1718 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1719 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1722 else if (GET_CODE (dest
) != CC0
)
1726 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1727 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1728 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1730 /* Don't substitute for a register intended as a clobberable
1732 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1733 if (rtx_equal_p (reg
, dest
))
1736 /* If the clobber represents an earlyclobber operand, we must not
1737 substitute an expression containing the clobbered register.
1738 As we do not analyze the constraint strings here, we have to
1739 make the conservative assumption. However, if the register is
1740 a fixed hard reg, the clobber cannot represent any operand;
1741 we leave it up to the machine description to either accept or
1742 reject use-and-clobber patterns. */
1744 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1745 || !fixed_regs
[REGNO (reg
)])
1746 if (reg_overlap_mentioned_p (reg
, src
))
1750 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1751 or not), reject, unless nothing volatile comes between it and I3 */
1753 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1755 /* Make sure succ doesn't contain a volatile reference. */
1756 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1759 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1760 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1764 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1765 to be an explicit register variable, and was chosen for a reason. */
1767 if (GET_CODE (src
) == ASM_OPERANDS
1768 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1771 /* If there are any volatile insns between INSN and I3, reject, because
1772 they might affect machine state. */
1774 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1775 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1778 /* If INSN contains an autoincrement or autodecrement, make sure that
1779 register is not used between there and I3, and not already used in
1780 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1781 Also insist that I3 not be a jump; if it were one
1782 and the incremented register were spilled, we would lose. */
1785 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1786 if (REG_NOTE_KIND (link
) == REG_INC
1788 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1789 || (pred
!= NULL_RTX
1790 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1791 || (succ
!= NULL_RTX
1792 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1793 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1798 /* Don't combine an insn that follows a CC0-setting insn.
1799 An insn that uses CC0 must not be separated from the one that sets it.
1800 We do, however, allow I2 to follow a CC0-setting insn if that insn
1801 is passed as I1; in that case it will be deleted also.
1802 We also allow combining in this case if all the insns are adjacent
1803 because that would leave the two CC0 insns adjacent as well.
1804 It would be more logical to test whether CC0 occurs inside I1 or I2,
1805 but that would be much slower, and this ought to be equivalent. */
1807 p
= prev_nonnote_insn (insn
);
1808 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1813 /* If we get here, we have passed all the tests and the combination is
1822 /* LOC is the location within I3 that contains its pattern or the component
1823 of a PARALLEL of the pattern. We validate that it is valid for combining.
1825 One problem is if I3 modifies its output, as opposed to replacing it
1826 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1827 so would produce an insn that is not equivalent to the original insns.
1831 (set (reg:DI 101) (reg:DI 100))
1832 (set (subreg:SI (reg:DI 101) 0) <foo>)
1834 This is NOT equivalent to:
1836 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1837 (set (reg:DI 101) (reg:DI 100))])
1839 Not only does this modify 100 (in which case it might still be valid
1840 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1842 We can also run into a problem if I2 sets a register that I1
1843 uses and I1 gets directly substituted into I3 (not via I2). In that
1844 case, we would be getting the wrong value of I2DEST into I3, so we
1845 must reject the combination. This case occurs when I2 and I1 both
1846 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1847 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1848 of a SET must prevent combination from occurring.
1850 Before doing the above check, we first try to expand a field assignment
1851 into a set of logical operations.
1853 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1854 we place a register that is both set and used within I3. If more than one
1855 such register is detected, we fail.
1857 Return 1 if the combination is valid, zero otherwise. */
1860 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1861 int i1_not_in_src
, rtx
*pi3dest_killed
)
1865 if (GET_CODE (x
) == SET
)
1868 rtx dest
= SET_DEST (set
);
1869 rtx src
= SET_SRC (set
);
1870 rtx inner_dest
= dest
;
1873 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1874 || GET_CODE (inner_dest
) == SUBREG
1875 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1876 inner_dest
= XEXP (inner_dest
, 0);
1878 /* Check for the case where I3 modifies its output, as discussed
1879 above. We don't want to prevent pseudos from being combined
1880 into the address of a MEM, so only prevent the combination if
1881 i1 or i2 set the same MEM. */
1882 if ((inner_dest
!= dest
&&
1883 (!MEM_P (inner_dest
)
1884 || rtx_equal_p (i2dest
, inner_dest
)
1885 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1886 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1887 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1889 /* This is the same test done in can_combine_p except we can't test
1890 all_adjacent; we don't have to, since this instruction will stay
1891 in place, thus we are not considering increasing the lifetime of
1894 Also, if this insn sets a function argument, combining it with
1895 something that might need a spill could clobber a previous
1896 function argument; the all_adjacent test in can_combine_p also
1897 checks this; here, we do a more specific test for this case. */
1899 || (REG_P (inner_dest
)
1900 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1901 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1902 GET_MODE (inner_dest
))))
1903 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1906 /* If DEST is used in I3, it is being killed in this insn, so
1907 record that for later. We have to consider paradoxical
1908 subregs here, since they kill the whole register, but we
1909 ignore partial subregs, STRICT_LOW_PART, etc.
1910 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1911 STACK_POINTER_REGNUM, since these are always considered to be
1912 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1914 if (GET_CODE (subdest
) == SUBREG
1915 && (GET_MODE_SIZE (GET_MODE (subdest
))
1916 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
1917 subdest
= SUBREG_REG (subdest
);
1920 && reg_referenced_p (subdest
, PATTERN (i3
))
1921 && REGNO (subdest
) != FRAME_POINTER_REGNUM
1922 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1923 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
1925 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1926 && (REGNO (subdest
) != ARG_POINTER_REGNUM
1927 || ! fixed_regs
[REGNO (subdest
)])
1929 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
1931 if (*pi3dest_killed
)
1934 *pi3dest_killed
= subdest
;
1938 else if (GET_CODE (x
) == PARALLEL
)
1942 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1943 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1944 i1_not_in_src
, pi3dest_killed
))
1951 /* Return 1 if X is an arithmetic expression that contains a multiplication
1952 and division. We don't count multiplications by powers of two here. */
1955 contains_muldiv (rtx x
)
1957 switch (GET_CODE (x
))
1959 case MOD
: case DIV
: case UMOD
: case UDIV
:
1963 return ! (CONST_INT_P (XEXP (x
, 1))
1964 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1967 return contains_muldiv (XEXP (x
, 0))
1968 || contains_muldiv (XEXP (x
, 1));
1971 return contains_muldiv (XEXP (x
, 0));
1977 /* Determine whether INSN can be used in a combination. Return nonzero if
1978 not. This is used in try_combine to detect early some cases where we
1979 can't perform combinations. */
1982 cant_combine_insn_p (rtx insn
)
1987 /* If this isn't really an insn, we can't do anything.
1988 This can occur when flow deletes an insn that it has merged into an
1989 auto-increment address. */
1990 if (! INSN_P (insn
))
1993 /* Never combine loads and stores involving hard regs that are likely
1994 to be spilled. The register allocator can usually handle such
1995 reg-reg moves by tying. If we allow the combiner to make
1996 substitutions of likely-spilled regs, reload might die.
1997 As an exception, we allow combinations involving fixed regs; these are
1998 not available to the register allocator so there's no risk involved. */
2000 set
= single_set (insn
);
2003 src
= SET_SRC (set
);
2004 dest
= SET_DEST (set
);
2005 if (GET_CODE (src
) == SUBREG
)
2006 src
= SUBREG_REG (src
);
2007 if (GET_CODE (dest
) == SUBREG
)
2008 dest
= SUBREG_REG (dest
);
2009 if (REG_P (src
) && REG_P (dest
)
2010 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
2011 && ! fixed_regs
[REGNO (src
)]
2012 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
2013 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
2014 && ! fixed_regs
[REGNO (dest
)]
2015 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
2021 struct likely_spilled_retval_info
2023 unsigned regno
, nregs
;
2027 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2028 hard registers that are known to be written to / clobbered in full. */
2030 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2032 struct likely_spilled_retval_info
*const info
=
2033 (struct likely_spilled_retval_info
*) data
;
2034 unsigned regno
, nregs
;
2037 if (!REG_P (XEXP (set
, 0)))
2040 if (regno
>= info
->regno
+ info
->nregs
)
2042 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2043 if (regno
+ nregs
<= info
->regno
)
2045 new_mask
= (2U << (nregs
- 1)) - 1;
2046 if (regno
< info
->regno
)
2047 new_mask
>>= info
->regno
- regno
;
2049 new_mask
<<= regno
- info
->regno
;
2050 info
->mask
&= ~new_mask
;
2053 /* Return nonzero iff part of the return value is live during INSN, and
2054 it is likely spilled. This can happen when more than one insn is needed
2055 to copy the return value, e.g. when we consider to combine into the
2056 second copy insn for a complex value. */
2059 likely_spilled_retval_p (rtx insn
)
2061 rtx use
= BB_END (this_basic_block
);
2063 unsigned regno
, nregs
;
2064 /* We assume here that no machine mode needs more than
2065 32 hard registers when the value overlaps with a register
2066 for which FUNCTION_VALUE_REGNO_P is true. */
2068 struct likely_spilled_retval_info info
;
2070 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2072 reg
= XEXP (PATTERN (use
), 0);
2073 if (!REG_P (reg
) || !FUNCTION_VALUE_REGNO_P (REGNO (reg
)))
2075 regno
= REGNO (reg
);
2076 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2079 mask
= (2U << (nregs
- 1)) - 1;
2081 /* Disregard parts of the return value that are set later. */
2085 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2087 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2090 /* Check if any of the (probably) live return value registers is
2095 if ((mask
& 1 << nregs
)
2096 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno
+ nregs
)))
2102 /* Adjust INSN after we made a change to its destination.
2104 Changing the destination can invalidate notes that say something about
2105 the results of the insn and a LOG_LINK pointing to the insn. */
2108 adjust_for_new_dest (rtx insn
)
2110 /* For notes, be conservative and simply remove them. */
2111 remove_reg_equal_equiv_notes (insn
);
2113 /* The new insn will have a destination that was previously the destination
2114 of an insn just above it. Call distribute_links to make a LOG_LINK from
2115 the next use of that destination. */
2116 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
2118 df_insn_rescan (insn
);
2121 /* Return TRUE if combine can reuse reg X in mode MODE.
2122 ADDED_SETS is nonzero if the original set is still required. */
2124 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2132 /* Allow hard registers if the new mode is legal, and occupies no more
2133 registers than the old mode. */
2134 if (regno
< FIRST_PSEUDO_REGISTER
)
2135 return (HARD_REGNO_MODE_OK (regno
, mode
)
2136 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2137 >= hard_regno_nregs
[regno
][mode
]));
2139 /* Or a pseudo that is only used once. */
2140 return (REG_N_SETS (regno
) == 1 && !added_sets
2141 && !REG_USERVAR_P (x
));
2145 /* Check whether X, the destination of a set, refers to part of
2146 the register specified by REG. */
2149 reg_subword_p (rtx x
, rtx reg
)
2151 /* Check that reg is an integer mode register. */
2152 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2155 if (GET_CODE (x
) == STRICT_LOW_PART
2156 || GET_CODE (x
) == ZERO_EXTRACT
)
2159 return GET_CODE (x
) == SUBREG
2160 && SUBREG_REG (x
) == reg
2161 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2165 /* Delete the conditional jump INSN and adjust the CFG correspondingly.
2166 Note that the INSN should be deleted *after* removing dead edges, so
2167 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2168 but not for a (set (pc) (label_ref FOO)). */
2171 update_cfg_for_uncondjump (rtx insn
)
2173 basic_block bb
= BLOCK_FOR_INSN (insn
);
2175 if (BB_END (bb
) == insn
)
2176 purge_dead_edges (bb
);
2179 if (EDGE_COUNT (bb
->succs
) == 1)
2180 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2184 /* Try to combine the insns I1 and I2 into I3.
2185 Here I1 and I2 appear earlier than I3.
2186 I1 can be zero; then we combine just I2 into I3.
2188 If we are combining three insns and the resulting insn is not recognized,
2189 try splitting it into two insns. If that happens, I2 and I3 are retained
2190 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2193 Return 0 if the combination does not work. Then nothing is changed.
2194 If we did the combination, return the insn at which combine should
2197 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2198 new direct jump instruction. */
2201 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
2203 /* New patterns for I3 and I2, respectively. */
2204 rtx newpat
, newi2pat
= 0;
2205 rtvec newpat_vec_with_clobbers
= 0;
2206 int substed_i2
= 0, substed_i1
= 0;
2207 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2208 int added_sets_1
, added_sets_2
;
2209 /* Total number of SETs to put into I3. */
2211 /* Nonzero if I2's body now appears in I3. */
2213 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2214 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2215 /* Contains I3 if the destination of I3 is used in its source, which means
2216 that the old life of I3 is being killed. If that usage is placed into
2217 I2 and not in I3, a REG_DEAD note must be made. */
2218 rtx i3dest_killed
= 0;
2219 /* SET_DEST and SET_SRC of I2 and I1. */
2220 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
2221 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2222 rtx i1pat
= 0, i2pat
= 0;
2223 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2224 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2225 int i2dest_killed
= 0, i1dest_killed
= 0;
2226 int i1_feeds_i3
= 0;
2227 /* Notes that must be added to REG_NOTES in I3 and I2. */
2228 rtx new_i3_notes
, new_i2_notes
;
2229 /* Notes that we substituted I3 into I2 instead of the normal case. */
2230 int i3_subst_into_i2
= 0;
2231 /* Notes that I1, I2 or I3 is a MULT operation. */
2234 int changed_i3_dest
= 0;
2240 rtx new_other_notes
;
2243 /* Exit early if one of the insns involved can't be used for
2245 if (cant_combine_insn_p (i3
)
2246 || cant_combine_insn_p (i2
)
2247 || (i1
&& cant_combine_insn_p (i1
))
2248 || likely_spilled_retval_p (i3
))
2252 undobuf
.other_insn
= 0;
2254 /* Reset the hard register usage information. */
2255 CLEAR_HARD_REG_SET (newpat_used_regs
);
2257 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2260 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2261 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2263 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2264 INSN_UID (i2
), INSN_UID (i3
));
2267 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2268 code below, set I1 to be the earlier of the two insns. */
2269 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2270 temp
= i1
, i1
= i2
, i2
= temp
;
2272 added_links_insn
= 0;
2274 /* First check for one important special-case that the code below will
2275 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2276 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2277 we may be able to replace that destination with the destination of I3.
2278 This occurs in the common code where we compute both a quotient and
2279 remainder into a structure, in which case we want to do the computation
2280 directly into the structure to avoid register-register copies.
2282 Note that this case handles both multiple sets in I2 and also
2283 cases where I2 has a number of CLOBBER or PARALLELs.
2285 We make very conservative checks below and only try to handle the
2286 most common cases of this. For example, we only handle the case
2287 where I2 and I3 are adjacent to avoid making difficult register
2290 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2291 && REG_P (SET_SRC (PATTERN (i3
)))
2292 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2293 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2294 && GET_CODE (PATTERN (i2
)) == PARALLEL
2295 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2296 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2297 below would need to check what is inside (and reg_overlap_mentioned_p
2298 doesn't support those codes anyway). Don't allow those destinations;
2299 the resulting insn isn't likely to be recognized anyway. */
2300 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2301 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2302 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2303 SET_DEST (PATTERN (i3
)))
2304 && next_real_insn (i2
) == i3
)
2306 rtx p2
= PATTERN (i2
);
2308 /* Make sure that the destination of I3,
2309 which we are going to substitute into one output of I2,
2310 is not used within another output of I2. We must avoid making this:
2311 (parallel [(set (mem (reg 69)) ...)
2312 (set (reg 69) ...)])
2313 which is not well-defined as to order of actions.
2314 (Besides, reload can't handle output reloads for this.)
2316 The problem can also happen if the dest of I3 is a memory ref,
2317 if another dest in I2 is an indirect memory ref. */
2318 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2319 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2320 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2321 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2322 SET_DEST (XVECEXP (p2
, 0, i
))))
2325 if (i
== XVECLEN (p2
, 0))
2326 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2327 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2328 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2329 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2334 subst_low_luid
= DF_INSN_LUID (i2
);
2336 added_sets_2
= added_sets_1
= 0;
2337 i2dest
= SET_SRC (PATTERN (i3
));
2338 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2340 /* Replace the dest in I2 with our dest and make the resulting
2341 insn the new pattern for I3. Then skip to where we
2342 validate the pattern. Everything was set up above. */
2343 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
2344 SET_DEST (PATTERN (i3
)));
2347 i3_subst_into_i2
= 1;
2348 goto validate_replacement
;
2352 /* If I2 is setting a pseudo to a constant and I3 is setting some
2353 sub-part of it to another constant, merge them by making a new
2356 && (temp
= single_set (i2
)) != 0
2357 && (CONST_INT_P (SET_SRC (temp
))
2358 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2359 && GET_CODE (PATTERN (i3
)) == SET
2360 && (CONST_INT_P (SET_SRC (PATTERN (i3
)))
2361 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2362 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2364 rtx dest
= SET_DEST (PATTERN (i3
));
2368 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2370 if (CONST_INT_P (XEXP (dest
, 1))
2371 && CONST_INT_P (XEXP (dest
, 2)))
2373 width
= INTVAL (XEXP (dest
, 1));
2374 offset
= INTVAL (XEXP (dest
, 2));
2375 dest
= XEXP (dest
, 0);
2376 if (BITS_BIG_ENDIAN
)
2377 offset
= GET_MODE_BITSIZE (GET_MODE (dest
)) - width
- offset
;
2382 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2383 dest
= XEXP (dest
, 0);
2384 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
2390 /* If this is the low part, we're done. */
2391 if (subreg_lowpart_p (dest
))
2393 /* Handle the case where inner is twice the size of outer. */
2394 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2395 == 2 * GET_MODE_BITSIZE (GET_MODE (dest
)))
2396 offset
+= GET_MODE_BITSIZE (GET_MODE (dest
));
2397 /* Otherwise give up for now. */
2403 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2404 <= HOST_BITS_PER_WIDE_INT
* 2))
2406 HOST_WIDE_INT mhi
, ohi
, ihi
;
2407 HOST_WIDE_INT mlo
, olo
, ilo
;
2408 rtx inner
= SET_SRC (PATTERN (i3
));
2409 rtx outer
= SET_SRC (temp
);
2411 if (CONST_INT_P (outer
))
2413 olo
= INTVAL (outer
);
2414 ohi
= olo
< 0 ? -1 : 0;
2418 olo
= CONST_DOUBLE_LOW (outer
);
2419 ohi
= CONST_DOUBLE_HIGH (outer
);
2422 if (CONST_INT_P (inner
))
2424 ilo
= INTVAL (inner
);
2425 ihi
= ilo
< 0 ? -1 : 0;
2429 ilo
= CONST_DOUBLE_LOW (inner
);
2430 ihi
= CONST_DOUBLE_HIGH (inner
);
2433 if (width
< HOST_BITS_PER_WIDE_INT
)
2435 mlo
= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
2438 else if (width
< HOST_BITS_PER_WIDE_INT
* 2)
2440 mhi
= ((unsigned HOST_WIDE_INT
) 1
2441 << (width
- HOST_BITS_PER_WIDE_INT
)) - 1;
2453 if (offset
>= HOST_BITS_PER_WIDE_INT
)
2455 mhi
= mlo
<< (offset
- HOST_BITS_PER_WIDE_INT
);
2457 ihi
= ilo
<< (offset
- HOST_BITS_PER_WIDE_INT
);
2460 else if (offset
> 0)
2462 mhi
= (mhi
<< offset
) | ((unsigned HOST_WIDE_INT
) mlo
2463 >> (HOST_BITS_PER_WIDE_INT
- offset
));
2464 mlo
= mlo
<< offset
;
2465 ihi
= (ihi
<< offset
) | ((unsigned HOST_WIDE_INT
) ilo
2466 >> (HOST_BITS_PER_WIDE_INT
- offset
));
2467 ilo
= ilo
<< offset
;
2470 olo
= (olo
& ~mlo
) | ilo
;
2471 ohi
= (ohi
& ~mhi
) | ihi
;
2475 subst_low_luid
= DF_INSN_LUID (i2
);
2476 added_sets_2
= added_sets_1
= 0;
2477 i2dest
= SET_DEST (temp
);
2478 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2480 SUBST (SET_SRC (temp
),
2481 immed_double_const (olo
, ohi
, GET_MODE (SET_DEST (temp
))));
2483 newpat
= PATTERN (i2
);
2484 goto validate_replacement
;
2489 /* If we have no I1 and I2 looks like:
2490 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2492 make up a dummy I1 that is
2495 (set (reg:CC X) (compare:CC Y (const_int 0)))
2497 (We can ignore any trailing CLOBBERs.)
2499 This undoes a previous combination and allows us to match a branch-and-
2502 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2503 && XVECLEN (PATTERN (i2
), 0) >= 2
2504 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2505 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2507 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2508 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2509 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2510 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2511 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2512 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2514 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2515 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2520 /* We make I1 with the same INSN_UID as I2. This gives it
2521 the same DF_INSN_LUID for value tracking. Our fake I1 will
2522 never appear in the insn stream so giving it the same INSN_UID
2523 as I2 will not cause a problem. */
2525 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2526 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
2527 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
);
2529 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2530 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2531 SET_DEST (PATTERN (i1
)));
2536 /* Verify that I2 and I1 are valid for combining. */
2537 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
2538 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
2544 /* Record whether I2DEST is used in I2SRC and similarly for the other
2545 cases. Knowing this will help in register status updating below. */
2546 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2547 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2548 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2549 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2550 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2552 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2554 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
2556 /* Ensure that I3's pattern can be the destination of combines. */
2557 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
2558 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
2565 /* See if any of the insns is a MULT operation. Unless one is, we will
2566 reject a combination that is, since it must be slower. Be conservative
2568 if (GET_CODE (i2src
) == MULT
2569 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2570 || (GET_CODE (PATTERN (i3
)) == SET
2571 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2574 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2575 We used to do this EXCEPT in one case: I3 has a post-inc in an
2576 output operand. However, that exception can give rise to insns like
2578 which is a famous insn on the PDP-11 where the value of r3 used as the
2579 source was model-dependent. Avoid this sort of thing. */
2582 if (!(GET_CODE (PATTERN (i3
)) == SET
2583 && REG_P (SET_SRC (PATTERN (i3
)))
2584 && MEM_P (SET_DEST (PATTERN (i3
)))
2585 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2586 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2587 /* It's not the exception. */
2590 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2591 if (REG_NOTE_KIND (link
) == REG_INC
2592 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2594 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2601 /* See if the SETs in I1 or I2 need to be kept around in the merged
2602 instruction: whenever the value set there is still needed past I3.
2603 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2605 For the SET in I1, we have two cases: If I1 and I2 independently
2606 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2607 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2608 in I1 needs to be kept around unless I1DEST dies or is set in either
2609 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2610 I1DEST. If so, we know I1 feeds into I2. */
2612 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
2615 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
2616 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
2618 /* If the set in I2 needs to be kept around, we must make a copy of
2619 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2620 PATTERN (I2), we are only substituting for the original I1DEST, not into
2621 an already-substituted copy. This also prevents making self-referential
2622 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2627 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2628 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2630 i2pat
= copy_rtx (PATTERN (i2
));
2635 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2636 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2638 i1pat
= copy_rtx (PATTERN (i1
));
2643 /* Substitute in the latest insn for the regs set by the earlier ones. */
2645 maxreg
= max_reg_num ();
2650 /* Many machines that don't use CC0 have insns that can both perform an
2651 arithmetic operation and set the condition code. These operations will
2652 be represented as a PARALLEL with the first element of the vector
2653 being a COMPARE of an arithmetic operation with the constant zero.
2654 The second element of the vector will set some pseudo to the result
2655 of the same arithmetic operation. If we simplify the COMPARE, we won't
2656 match such a pattern and so will generate an extra insn. Here we test
2657 for this case, where both the comparison and the operation result are
2658 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2659 I2SRC. Later we will make the PARALLEL that contains I2. */
2661 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2662 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2663 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2664 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2666 #ifdef SELECT_CC_MODE
2668 enum machine_mode compare_mode
;
2671 newpat
= PATTERN (i3
);
2672 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2676 #ifdef SELECT_CC_MODE
2677 /* See if a COMPARE with the operand we substituted in should be done
2678 with the mode that is currently being used. If not, do the same
2679 processing we do in `subst' for a SET; namely, if the destination
2680 is used only once, try to replace it with a register of the proper
2681 mode and also replace the COMPARE. */
2682 if (undobuf
.other_insn
== 0
2683 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2684 &undobuf
.other_insn
))
2685 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2687 != GET_MODE (SET_DEST (newpat
))))
2689 if (can_change_dest_mode(SET_DEST (newpat
), added_sets_2
,
2692 unsigned int regno
= REGNO (SET_DEST (newpat
));
2695 if (regno
< FIRST_PSEUDO_REGISTER
)
2696 new_dest
= gen_rtx_REG (compare_mode
, regno
);
2699 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2700 new_dest
= regno_reg_rtx
[regno
];
2703 SUBST (SET_DEST (newpat
), new_dest
);
2704 SUBST (XEXP (*cc_use
, 0), new_dest
);
2705 SUBST (SET_SRC (newpat
),
2706 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2709 undobuf
.other_insn
= 0;
2716 /* It is possible that the source of I2 or I1 may be performing
2717 an unneeded operation, such as a ZERO_EXTEND of something
2718 that is known to have the high part zero. Handle that case
2719 by letting subst look at the innermost one of them.
2721 Another way to do this would be to have a function that tries
2722 to simplify a single insn instead of merging two or more
2723 insns. We don't do this because of the potential of infinite
2724 loops and because of the potential extra memory required.
2725 However, doing it the way we are is a bit of a kludge and
2726 doesn't catch all cases.
2728 But only do this if -fexpensive-optimizations since it slows
2729 things down and doesn't usually win.
2731 This is not done in the COMPARE case above because the
2732 unmodified I2PAT is used in the PARALLEL and so a pattern
2733 with a modified I2SRC would not match. */
2735 if (flag_expensive_optimizations
)
2737 /* Pass pc_rtx so no substitutions are done, just
2741 subst_low_luid
= DF_INSN_LUID (i1
);
2742 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
2746 subst_low_luid
= DF_INSN_LUID (i2
);
2747 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
2751 n_occurrences
= 0; /* `subst' counts here */
2753 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2754 need to make a unique copy of I2SRC each time we substitute it
2755 to avoid self-referential rtl. */
2757 subst_low_luid
= DF_INSN_LUID (i2
);
2758 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2759 ! i1_feeds_i3
&& i1dest_in_i1src
);
2762 /* Record whether i2's body now appears within i3's body. */
2763 i2_is_used
= n_occurrences
;
2766 /* If we already got a failure, don't try to do more. Otherwise,
2767 try to substitute in I1 if we have it. */
2769 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2771 /* Check that an autoincrement side-effect on I1 has not been lost.
2772 This happens if I1DEST is mentioned in I2 and dies there, and
2773 has disappeared from the new pattern. */
2774 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2776 && dead_or_set_p (i2
, i1dest
)
2777 && !reg_overlap_mentioned_p (i1dest
, newpat
))
2778 /* Before we can do this substitution, we must redo the test done
2779 above (see detailed comments there) that ensures that I1DEST
2780 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2781 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, 0, 0))
2788 subst_low_luid
= DF_INSN_LUID (i1
);
2789 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2793 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2794 to count all the ways that I2SRC and I1SRC can be used. */
2795 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2796 && i2_is_used
+ added_sets_2
> 1)
2797 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2798 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2800 /* Fail if we tried to make a new register. */
2801 || max_reg_num () != maxreg
2802 /* Fail if we couldn't do something and have a CLOBBER. */
2803 || GET_CODE (newpat
) == CLOBBER
2804 /* Fail if this new pattern is a MULT and we didn't have one before
2805 at the outer level. */
2806 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2813 /* If the actions of the earlier insns must be kept
2814 in addition to substituting them into the latest one,
2815 we must make a new PARALLEL for the latest insn
2816 to hold additional the SETs. */
2818 if (added_sets_1
|| added_sets_2
)
2822 if (GET_CODE (newpat
) == PARALLEL
)
2824 rtvec old
= XVEC (newpat
, 0);
2825 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2826 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2827 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2828 sizeof (old
->elem
[0]) * old
->num_elem
);
2833 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2834 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2835 XVECEXP (newpat
, 0, 0) = old
;
2839 XVECEXP (newpat
, 0, --total_sets
) = i1pat
;
2843 /* If there is no I1, use I2's body as is. We used to also not do
2844 the subst call below if I2 was substituted into I3,
2845 but that could lose a simplification. */
2847 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2849 /* See comment where i2pat is assigned. */
2850 XVECEXP (newpat
, 0, --total_sets
)
2851 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2855 /* We come here when we are replacing a destination in I2 with the
2856 destination of I3. */
2857 validate_replacement
:
2859 /* Note which hard regs this insn has as inputs. */
2860 mark_used_regs_combine (newpat
);
2862 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2863 consider splitting this pattern, we might need these clobbers. */
2864 if (i1
&& GET_CODE (newpat
) == PARALLEL
2865 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
2867 int len
= XVECLEN (newpat
, 0);
2869 newpat_vec_with_clobbers
= rtvec_alloc (len
);
2870 for (i
= 0; i
< len
; i
++)
2871 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
2874 /* Is the result of combination a valid instruction? */
2875 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2877 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2878 the second SET's destination is a register that is unused and isn't
2879 marked as an instruction that might trap in an EH region. In that case,
2880 we just need the first SET. This can occur when simplifying a divmod
2881 insn. We *must* test for this case here because the code below that
2882 splits two independent SETs doesn't handle this case correctly when it
2883 updates the register status.
2885 It's pointless doing this if we originally had two sets, one from
2886 i3, and one from i2. Combining then splitting the parallel results
2887 in the original i2 again plus an invalid insn (which we delete).
2888 The net effect is only to move instructions around, which makes
2889 debug info less accurate.
2891 Also check the case where the first SET's destination is unused.
2892 That would not cause incorrect code, but does cause an unneeded
2895 if (insn_code_number
< 0
2896 && !(added_sets_2
&& i1
== 0)
2897 && GET_CODE (newpat
) == PARALLEL
2898 && XVECLEN (newpat
, 0) == 2
2899 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2900 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2901 && asm_noperands (newpat
) < 0)
2903 rtx set0
= XVECEXP (newpat
, 0, 0);
2904 rtx set1
= XVECEXP (newpat
, 0, 1);
2907 if (((REG_P (SET_DEST (set1
))
2908 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2909 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2910 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2911 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2912 || INTVAL (XEXP (note
, 0)) <= 0)
2913 && ! side_effects_p (SET_SRC (set1
)))
2916 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2919 else if (((REG_P (SET_DEST (set0
))
2920 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2921 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2922 && find_reg_note (i3
, REG_UNUSED
,
2923 SUBREG_REG (SET_DEST (set0
)))))
2924 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2925 || INTVAL (XEXP (note
, 0)) <= 0)
2926 && ! side_effects_p (SET_SRC (set0
)))
2929 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2931 if (insn_code_number
>= 0)
2932 changed_i3_dest
= 1;
2936 /* If we were combining three insns and the result is a simple SET
2937 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2938 insns. There are two ways to do this. It can be split using a
2939 machine-specific method (like when you have an addition of a large
2940 constant) or by combine in the function find_split_point. */
2942 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2943 && asm_noperands (newpat
) < 0)
2945 rtx parallel
, m_split
, *split
;
2947 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2948 use I2DEST as a scratch register will help. In the latter case,
2949 convert I2DEST to the mode of the source of NEWPAT if we can. */
2951 m_split
= combine_split_insns (newpat
, i3
);
2953 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2954 inputs of NEWPAT. */
2956 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2957 possible to try that as a scratch reg. This would require adding
2958 more code to make it work though. */
2960 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
2962 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
2964 /* First try to split using the original register as a
2965 scratch register. */
2966 parallel
= gen_rtx_PARALLEL (VOIDmode
,
2967 gen_rtvec (2, newpat
,
2968 gen_rtx_CLOBBER (VOIDmode
,
2970 m_split
= combine_split_insns (parallel
, i3
);
2972 /* If that didn't work, try changing the mode of I2DEST if
2975 && new_mode
!= GET_MODE (i2dest
)
2976 && new_mode
!= VOIDmode
2977 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
2979 enum machine_mode old_mode
= GET_MODE (i2dest
);
2982 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
2983 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
2986 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
2987 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
2990 parallel
= (gen_rtx_PARALLEL
2992 gen_rtvec (2, newpat
,
2993 gen_rtx_CLOBBER (VOIDmode
,
2995 m_split
= combine_split_insns (parallel
, i3
);
2998 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3002 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3003 buf
= undobuf
.undos
;
3004 undobuf
.undos
= buf
->next
;
3005 buf
->next
= undobuf
.frees
;
3006 undobuf
.frees
= buf
;
3011 /* If recog_for_combine has discarded clobbers, try to use them
3012 again for the split. */
3013 if (m_split
== 0 && newpat_vec_with_clobbers
)
3015 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3016 m_split
= combine_split_insns (parallel
, i3
);
3019 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3021 m_split
= PATTERN (m_split
);
3022 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3023 if (insn_code_number
>= 0)
3026 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3027 && (next_real_insn (i2
) == i3
3028 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3031 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3032 newi2pat
= PATTERN (m_split
);
3034 i3set
= single_set (NEXT_INSN (m_split
));
3035 i2set
= single_set (m_split
);
3037 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3039 /* If I2 or I3 has multiple SETs, we won't know how to track
3040 register status, so don't use these insns. If I2's destination
3041 is used between I2 and I3, we also can't use these insns. */
3043 if (i2_code_number
>= 0 && i2set
&& i3set
3044 && (next_real_insn (i2
) == i3
3045 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3046 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3048 if (insn_code_number
>= 0)
3051 /* It is possible that both insns now set the destination of I3.
3052 If so, we must show an extra use of it. */
3054 if (insn_code_number
>= 0)
3056 rtx new_i3_dest
= SET_DEST (i3set
);
3057 rtx new_i2_dest
= SET_DEST (i2set
);
3059 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3060 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3061 || GET_CODE (new_i3_dest
) == SUBREG
)
3062 new_i3_dest
= XEXP (new_i3_dest
, 0);
3064 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3065 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3066 || GET_CODE (new_i2_dest
) == SUBREG
)
3067 new_i2_dest
= XEXP (new_i2_dest
, 0);
3069 if (REG_P (new_i3_dest
)
3070 && REG_P (new_i2_dest
)
3071 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3072 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3076 /* If we can split it and use I2DEST, go ahead and see if that
3077 helps things be recognized. Verify that none of the registers
3078 are set between I2 and I3. */
3079 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
3083 /* We need I2DEST in the proper mode. If it is a hard register
3084 or the only use of a pseudo, we can change its mode.
3085 Make sure we don't change a hard register to have a mode that
3086 isn't valid for it, or change the number of registers. */
3087 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3088 || GET_MODE (*split
) == VOIDmode
3089 || can_change_dest_mode (i2dest
, added_sets_2
,
3091 && (next_real_insn (i2
) == i3
3092 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3093 /* We can't overwrite I2DEST if its value is still used by
3095 && ! reg_referenced_p (i2dest
, newpat
))
3097 rtx newdest
= i2dest
;
3098 enum rtx_code split_code
= GET_CODE (*split
);
3099 enum machine_mode split_mode
= GET_MODE (*split
);
3100 bool subst_done
= false;
3101 newi2pat
= NULL_RTX
;
3103 /* Get NEWDEST as a register in the proper mode. We have already
3104 validated that we can do this. */
3105 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3107 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3108 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3111 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3112 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3116 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3117 an ASHIFT. This can occur if it was inside a PLUS and hence
3118 appeared to be a memory address. This is a kludge. */
3119 if (split_code
== MULT
3120 && CONST_INT_P (XEXP (*split
, 1))
3121 && INTVAL (XEXP (*split
, 1)) > 0
3122 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
3124 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3125 XEXP (*split
, 0), GEN_INT (i
)));
3126 /* Update split_code because we may not have a multiply
3128 split_code
= GET_CODE (*split
);
3131 #ifdef INSN_SCHEDULING
3132 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3133 be written as a ZERO_EXTEND. */
3134 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3136 #ifdef LOAD_EXTEND_OP
3137 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3138 what it really is. */
3139 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3141 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3142 SUBREG_REG (*split
)));
3145 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3146 SUBREG_REG (*split
)));
3150 /* Attempt to split binary operators using arithmetic identities. */
3151 if (BINARY_P (SET_SRC (newpat
))
3152 && split_mode
== GET_MODE (SET_SRC (newpat
))
3153 && ! side_effects_p (SET_SRC (newpat
)))
3155 rtx setsrc
= SET_SRC (newpat
);
3156 enum machine_mode mode
= GET_MODE (setsrc
);
3157 enum rtx_code code
= GET_CODE (setsrc
);
3158 rtx src_op0
= XEXP (setsrc
, 0);
3159 rtx src_op1
= XEXP (setsrc
, 1);
3161 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3162 if (rtx_equal_p (src_op0
, src_op1
))
3164 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3165 SUBST (XEXP (setsrc
, 0), newdest
);
3166 SUBST (XEXP (setsrc
, 1), newdest
);
3169 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3170 else if ((code
== PLUS
|| code
== MULT
)
3171 && GET_CODE (src_op0
) == code
3172 && GET_CODE (XEXP (src_op0
, 0)) == code
3173 && (INTEGRAL_MODE_P (mode
)
3174 || (FLOAT_MODE_P (mode
)
3175 && flag_unsafe_math_optimizations
)))
3177 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3178 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3179 rtx r
= XEXP (src_op0
, 1);
3182 /* Split both "((X op Y) op X) op Y" and
3183 "((X op Y) op Y) op X" as "T op T" where T is
3185 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3186 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3188 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3190 SUBST (XEXP (setsrc
, 0), newdest
);
3191 SUBST (XEXP (setsrc
, 1), newdest
);
3194 /* Split "((X op X) op Y) op Y)" as "T op T" where
3196 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3198 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3199 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3200 SUBST (XEXP (setsrc
, 0), newdest
);
3201 SUBST (XEXP (setsrc
, 1), newdest
);
3209 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3210 SUBST (*split
, newdest
);
3213 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3215 /* recog_for_combine might have added CLOBBERs to newi2pat.
3216 Make sure NEWPAT does not depend on the clobbered regs. */
3217 if (GET_CODE (newi2pat
) == PARALLEL
)
3218 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3219 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3221 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3222 if (reg_overlap_mentioned_p (reg
, newpat
))
3229 /* If the split point was a MULT and we didn't have one before,
3230 don't use one now. */
3231 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3232 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3236 /* Check for a case where we loaded from memory in a narrow mode and
3237 then sign extended it, but we need both registers. In that case,
3238 we have a PARALLEL with both loads from the same memory location.
3239 We can split this into a load from memory followed by a register-register
3240 copy. This saves at least one insn, more if register allocation can
3243 We cannot do this if the destination of the first assignment is a
3244 condition code register or cc0. We eliminate this case by making sure
3245 the SET_DEST and SET_SRC have the same mode.
3247 We cannot do this if the destination of the second assignment is
3248 a register that we have already assumed is zero-extended. Similarly
3249 for a SUBREG of such a register. */
3251 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3252 && GET_CODE (newpat
) == PARALLEL
3253 && XVECLEN (newpat
, 0) == 2
3254 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3255 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3256 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3257 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3258 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3259 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3260 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3261 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3263 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3264 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3265 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3267 && VEC_index (reg_stat_type
, reg_stat
,
3268 REGNO (temp
))->nonzero_bits
!= 0
3269 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3270 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3271 && (VEC_index (reg_stat_type
, reg_stat
,
3272 REGNO (temp
))->nonzero_bits
3273 != GET_MODE_MASK (word_mode
))))
3274 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3275 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3277 && VEC_index (reg_stat_type
, reg_stat
,
3278 REGNO (temp
))->nonzero_bits
!= 0
3279 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3280 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3281 && (VEC_index (reg_stat_type
, reg_stat
,
3282 REGNO (temp
))->nonzero_bits
3283 != GET_MODE_MASK (word_mode
)))))
3284 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3285 SET_SRC (XVECEXP (newpat
, 0, 1)))
3286 && ! find_reg_note (i3
, REG_UNUSED
,
3287 SET_DEST (XVECEXP (newpat
, 0, 0))))
3291 newi2pat
= XVECEXP (newpat
, 0, 0);
3292 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3293 newpat
= XVECEXP (newpat
, 0, 1);
3294 SUBST (SET_SRC (newpat
),
3295 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3296 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3298 if (i2_code_number
>= 0)
3299 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3301 if (insn_code_number
>= 0)
3305 /* Similarly, check for a case where we have a PARALLEL of two independent
3306 SETs but we started with three insns. In this case, we can do the sets
3307 as two separate insns. This case occurs when some SET allows two
3308 other insns to combine, but the destination of that SET is still live. */
3310 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3311 && GET_CODE (newpat
) == PARALLEL
3312 && XVECLEN (newpat
, 0) == 2
3313 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3314 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3315 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3316 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3317 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3318 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3319 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3321 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3322 XVECEXP (newpat
, 0, 0))
3323 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3324 XVECEXP (newpat
, 0, 1))
3325 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3326 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1))))
3328 /* We cannot split the parallel into two sets if both sets
3330 && ! (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3331 && reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1)))
3335 /* Normally, it doesn't matter which of the two is done first,
3336 but it does if one references cc0. In that case, it has to
3339 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
3341 newi2pat
= XVECEXP (newpat
, 0, 0);
3342 newpat
= XVECEXP (newpat
, 0, 1);
3347 newi2pat
= XVECEXP (newpat
, 0, 1);
3348 newpat
= XVECEXP (newpat
, 0, 0);
3351 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3353 if (i2_code_number
>= 0)
3354 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3357 /* If it still isn't recognized, fail and change things back the way they
3359 if ((insn_code_number
< 0
3360 /* Is the result a reasonable ASM_OPERANDS? */
3361 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3367 /* If we had to change another insn, make sure it is valid also. */
3368 if (undobuf
.other_insn
)
3370 CLEAR_HARD_REG_SET (newpat_used_regs
);
3372 other_pat
= PATTERN (undobuf
.other_insn
);
3373 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3376 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3384 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3385 they are adjacent to each other or not. */
3387 rtx p
= prev_nonnote_insn (i3
);
3388 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3389 && sets_cc0_p (newi2pat
))
3397 /* Only allow this combination if insn_rtx_costs reports that the
3398 replacement instructions are cheaper than the originals. */
3399 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3405 /* If we will be able to accept this, we have made a
3406 change to the destination of I3. This requires us to
3407 do a few adjustments. */
3409 if (changed_i3_dest
)
3411 PATTERN (i3
) = newpat
;
3412 adjust_for_new_dest (i3
);
3415 /* We now know that we can do this combination. Merge the insns and
3416 update the status of registers and LOG_LINKS. */
3418 if (undobuf
.other_insn
)
3422 PATTERN (undobuf
.other_insn
) = other_pat
;
3424 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3425 are still valid. Then add any non-duplicate notes added by
3426 recog_for_combine. */
3427 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3429 next
= XEXP (note
, 1);
3431 if (REG_NOTE_KIND (note
) == REG_UNUSED
3432 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3433 remove_note (undobuf
.other_insn
, note
);
3436 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3437 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3446 /* I3 now uses what used to be its destination and which is now
3447 I2's destination. This requires us to do a few adjustments. */
3448 PATTERN (i3
) = newpat
;
3449 adjust_for_new_dest (i3
);
3451 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3454 However, some later insn might be using I2's dest and have
3455 a LOG_LINK pointing at I3. We must remove this link.
3456 The simplest way to remove the link is to point it at I1,
3457 which we know will be a NOTE. */
3459 /* newi2pat is usually a SET here; however, recog_for_combine might
3460 have added some clobbers. */
3461 if (GET_CODE (newi2pat
) == PARALLEL
)
3462 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3464 ni2dest
= SET_DEST (newi2pat
);
3466 for (insn
= NEXT_INSN (i3
);
3467 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3468 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3469 insn
= NEXT_INSN (insn
))
3471 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3473 for (link
= LOG_LINKS (insn
); link
;
3474 link
= XEXP (link
, 1))
3475 if (XEXP (link
, 0) == i3
)
3476 XEXP (link
, 0) = i1
;
3484 rtx i3notes
, i2notes
, i1notes
= 0;
3485 rtx i3links
, i2links
, i1links
= 0;
3488 /* Compute which registers we expect to eliminate. newi2pat may be setting
3489 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3490 same as i3dest, in which case newi2pat may be setting i1dest. */
3491 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3492 || i2dest_in_i2src
|| i2dest_in_i1src
3495 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
3496 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3500 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3502 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3503 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3505 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3507 /* Ensure that we do not have something that should not be shared but
3508 occurs multiple times in the new insns. Check this by first
3509 resetting all the `used' flags and then copying anything is shared. */
3511 reset_used_flags (i3notes
);
3512 reset_used_flags (i2notes
);
3513 reset_used_flags (i1notes
);
3514 reset_used_flags (newpat
);
3515 reset_used_flags (newi2pat
);
3516 if (undobuf
.other_insn
)
3517 reset_used_flags (PATTERN (undobuf
.other_insn
));
3519 i3notes
= copy_rtx_if_shared (i3notes
);
3520 i2notes
= copy_rtx_if_shared (i2notes
);
3521 i1notes
= copy_rtx_if_shared (i1notes
);
3522 newpat
= copy_rtx_if_shared (newpat
);
3523 newi2pat
= copy_rtx_if_shared (newi2pat
);
3524 if (undobuf
.other_insn
)
3525 reset_used_flags (PATTERN (undobuf
.other_insn
));
3527 INSN_CODE (i3
) = insn_code_number
;
3528 PATTERN (i3
) = newpat
;
3530 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
3532 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
3534 reset_used_flags (call_usage
);
3535 call_usage
= copy_rtx (call_usage
);
3538 replace_rtx (call_usage
, i2dest
, i2src
);
3541 replace_rtx (call_usage
, i1dest
, i1src
);
3543 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
3546 if (undobuf
.other_insn
)
3547 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
3549 /* We had one special case above where I2 had more than one set and
3550 we replaced a destination of one of those sets with the destination
3551 of I3. In that case, we have to update LOG_LINKS of insns later
3552 in this basic block. Note that this (expensive) case is rare.
3554 Also, in this case, we must pretend that all REG_NOTEs for I2
3555 actually came from I3, so that REG_UNUSED notes from I2 will be
3556 properly handled. */
3558 if (i3_subst_into_i2
)
3560 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
3561 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
3562 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
3563 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
3564 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
3565 && ! find_reg_note (i2
, REG_UNUSED
,
3566 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
3567 for (temp
= NEXT_INSN (i2
);
3568 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3569 || BB_HEAD (this_basic_block
) != temp
);
3570 temp
= NEXT_INSN (temp
))
3571 if (temp
!= i3
&& INSN_P (temp
))
3572 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
3573 if (XEXP (link
, 0) == i2
)
3574 XEXP (link
, 0) = i3
;
3579 while (XEXP (link
, 1))
3580 link
= XEXP (link
, 1);
3581 XEXP (link
, 1) = i2notes
;
3595 INSN_CODE (i2
) = i2_code_number
;
3596 PATTERN (i2
) = newi2pat
;
3599 SET_INSN_DELETED (i2
);
3605 SET_INSN_DELETED (i1
);
3608 /* Get death notes for everything that is now used in either I3 or
3609 I2 and used to die in a previous insn. If we built two new
3610 patterns, move from I1 to I2 then I2 to I3 so that we get the
3611 proper movement on registers that I2 modifies. */
3615 move_deaths (newi2pat
, NULL_RTX
, DF_INSN_LUID (i1
), i2
, &midnotes
);
3616 move_deaths (newpat
, newi2pat
, DF_INSN_LUID (i1
), i3
, &midnotes
);
3619 move_deaths (newpat
, NULL_RTX
, i1
? DF_INSN_LUID (i1
) : DF_INSN_LUID (i2
),
3622 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3624 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
3627 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
3630 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
3633 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3636 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3637 know these are REG_UNUSED and want them to go to the desired insn,
3638 so we always pass it as i3. */
3640 if (newi2pat
&& new_i2_notes
)
3641 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3644 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3646 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3647 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3648 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3649 in that case, it might delete I2. Similarly for I2 and I1.
3650 Show an additional death due to the REG_DEAD note we make here. If
3651 we discard it in distribute_notes, we will decrement it again. */
3655 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
3656 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
3658 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
3660 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
3662 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3666 if (i2dest_in_i2src
)
3668 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3669 distribute_notes (alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
),
3670 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3672 distribute_notes (alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
),
3673 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3674 NULL_RTX
, NULL_RTX
);
3677 if (i1dest_in_i1src
)
3679 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3680 distribute_notes (alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
),
3681 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3683 distribute_notes (alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
),
3684 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3685 NULL_RTX
, NULL_RTX
);
3688 distribute_links (i3links
);
3689 distribute_links (i2links
);
3690 distribute_links (i1links
);
3695 rtx i2_insn
= 0, i2_val
= 0, set
;
3697 /* The insn that used to set this register doesn't exist, and
3698 this life of the register may not exist either. See if one of
3699 I3's links points to an insn that sets I2DEST. If it does,
3700 that is now the last known value for I2DEST. If we don't update
3701 this and I2 set the register to a value that depended on its old
3702 contents, we will get confused. If this insn is used, thing
3703 will be set correctly in combine_instructions. */
3705 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3706 if ((set
= single_set (XEXP (link
, 0))) != 0
3707 && rtx_equal_p (i2dest
, SET_DEST (set
)))
3708 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
3710 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
3712 /* If the reg formerly set in I2 died only once and that was in I3,
3713 zero its use count so it won't make `reload' do any work. */
3715 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
3716 && ! i2dest_in_i2src
)
3718 regno
= REGNO (i2dest
);
3719 INC_REG_N_SETS (regno
, -1);
3723 if (i1
&& REG_P (i1dest
))
3726 rtx i1_insn
= 0, i1_val
= 0, set
;
3728 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3729 if ((set
= single_set (XEXP (link
, 0))) != 0
3730 && rtx_equal_p (i1dest
, SET_DEST (set
)))
3731 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
3733 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
3735 regno
= REGNO (i1dest
);
3736 if (! added_sets_1
&& ! i1dest_in_i1src
)
3737 INC_REG_N_SETS (regno
, -1);
3740 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3741 been made to this insn. The order of
3742 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3743 can affect nonzero_bits of newpat */
3745 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
3746 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
3749 if (undobuf
.other_insn
!= NULL_RTX
)
3753 fprintf (dump_file
, "modifying other_insn ");
3754 dump_insn_slim (dump_file
, undobuf
.other_insn
);
3756 df_insn_rescan (undobuf
.other_insn
);
3759 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
3763 fprintf (dump_file
, "modifying insn i1 ");
3764 dump_insn_slim (dump_file
, i1
);
3766 df_insn_rescan (i1
);
3769 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
3773 fprintf (dump_file
, "modifying insn i2 ");
3774 dump_insn_slim (dump_file
, i2
);
3776 df_insn_rescan (i2
);
3779 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
3783 fprintf (dump_file
, "modifying insn i3 ");
3784 dump_insn_slim (dump_file
, i3
);
3786 df_insn_rescan (i3
);
3789 /* Set new_direct_jump_p if a new return or simple jump instruction
3790 has been created. Adjust the CFG accordingly. */
3792 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
3794 *new_direct_jump_p
= 1;
3795 mark_jump_label (PATTERN (i3
), i3
, 0);
3796 update_cfg_for_uncondjump (i3
);
3799 if (undobuf
.other_insn
!= NULL_RTX
3800 && (returnjump_p (undobuf
.other_insn
)
3801 || any_uncondjump_p (undobuf
.other_insn
)))
3803 *new_direct_jump_p
= 1;
3804 update_cfg_for_uncondjump (undobuf
.other_insn
);
3807 /* A noop might also need cleaning up of CFG, if it comes from the
3808 simplification of a jump. */
3809 if (GET_CODE (newpat
) == SET
3810 && SET_SRC (newpat
) == pc_rtx
3811 && SET_DEST (newpat
) == pc_rtx
)
3813 *new_direct_jump_p
= 1;
3814 update_cfg_for_uncondjump (i3
);
3817 combine_successes
++;
3820 if (added_links_insn
3821 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
3822 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
3823 return added_links_insn
;
3825 return newi2pat
? i2
: i3
;
3828 /* Undo all the modifications recorded in undobuf. */
3833 struct undo
*undo
, *next
;
3835 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3841 *undo
->where
.r
= undo
->old_contents
.r
;
3844 *undo
->where
.i
= undo
->old_contents
.i
;
3847 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
3853 undo
->next
= undobuf
.frees
;
3854 undobuf
.frees
= undo
;
3860 /* We've committed to accepting the changes we made. Move all
3861 of the undos to the free list. */
3866 struct undo
*undo
, *next
;
3868 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3871 undo
->next
= undobuf
.frees
;
3872 undobuf
.frees
= undo
;
3877 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3878 where we have an arithmetic expression and return that point. LOC will
3881 try_combine will call this function to see if an insn can be split into
3885 find_split_point (rtx
*loc
, rtx insn
)
3888 enum rtx_code code
= GET_CODE (x
);
3890 unsigned HOST_WIDE_INT len
= 0;
3891 HOST_WIDE_INT pos
= 0;
3893 rtx inner
= NULL_RTX
;
3895 /* First special-case some codes. */
3899 #ifdef INSN_SCHEDULING
3900 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3902 if (MEM_P (SUBREG_REG (x
)))
3905 return find_split_point (&SUBREG_REG (x
), insn
);
3909 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3910 using LO_SUM and HIGH. */
3911 if (GET_CODE (XEXP (x
, 0)) == CONST
3912 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3915 gen_rtx_LO_SUM (Pmode
,
3916 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3918 return &XEXP (XEXP (x
, 0), 0);
3922 /* If we have a PLUS whose second operand is a constant and the
3923 address is not valid, perhaps will can split it up using
3924 the machine-specific way to split large constants. We use
3925 the first pseudo-reg (one of the virtual regs) as a placeholder;
3926 it will not remain in the result. */
3927 if (GET_CODE (XEXP (x
, 0)) == PLUS
3928 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3929 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3931 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3932 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
3936 /* This should have produced two insns, each of which sets our
3937 placeholder. If the source of the second is a valid address,
3938 we can make put both sources together and make a split point
3942 && NEXT_INSN (seq
) != NULL_RTX
3943 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3944 && NONJUMP_INSN_P (seq
)
3945 && GET_CODE (PATTERN (seq
)) == SET
3946 && SET_DEST (PATTERN (seq
)) == reg
3947 && ! reg_mentioned_p (reg
,
3948 SET_SRC (PATTERN (seq
)))
3949 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3950 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3951 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3952 && memory_address_p (GET_MODE (x
),
3953 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3955 rtx src1
= SET_SRC (PATTERN (seq
));
3956 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3958 /* Replace the placeholder in SRC2 with SRC1. If we can
3959 find where in SRC2 it was placed, that can become our
3960 split point and we can replace this address with SRC2.
3961 Just try two obvious places. */
3963 src2
= replace_rtx (src2
, reg
, src1
);
3965 if (XEXP (src2
, 0) == src1
)
3966 split
= &XEXP (src2
, 0);
3967 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3968 && XEXP (XEXP (src2
, 0), 0) == src1
)
3969 split
= &XEXP (XEXP (src2
, 0), 0);
3973 SUBST (XEXP (x
, 0), src2
);
3978 /* If that didn't work, perhaps the first operand is complex and
3979 needs to be computed separately, so make a split point there.
3980 This will occur on machines that just support REG + CONST
3981 and have a constant moved through some previous computation. */
3983 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3984 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3985 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3986 return &XEXP (XEXP (x
, 0), 0);
3989 /* If we have a PLUS whose first operand is complex, try computing it
3990 separately by making a split there. */
3991 if (GET_CODE (XEXP (x
, 0)) == PLUS
3992 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0))
3993 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
3994 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3995 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3996 return &XEXP (XEXP (x
, 0), 0);
4001 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4002 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4003 we need to put the operand into a register. So split at that
4006 if (SET_DEST (x
) == cc0_rtx
4007 && GET_CODE (SET_SRC (x
)) != COMPARE
4008 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4009 && !OBJECT_P (SET_SRC (x
))
4010 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4011 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4012 return &SET_SRC (x
);
4015 /* See if we can split SET_SRC as it stands. */
4016 split
= find_split_point (&SET_SRC (x
), insn
);
4017 if (split
&& split
!= &SET_SRC (x
))
4020 /* See if we can split SET_DEST as it stands. */
4021 split
= find_split_point (&SET_DEST (x
), insn
);
4022 if (split
&& split
!= &SET_DEST (x
))
4025 /* See if this is a bitfield assignment with everything constant. If
4026 so, this is an IOR of an AND, so split it into that. */
4027 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4028 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
4029 <= HOST_BITS_PER_WIDE_INT
)
4030 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4031 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4032 && CONST_INT_P (SET_SRC (x
))
4033 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4034 + INTVAL (XEXP (SET_DEST (x
), 2)))
4035 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
4036 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4038 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4039 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4040 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4041 rtx dest
= XEXP (SET_DEST (x
), 0);
4042 enum machine_mode mode
= GET_MODE (dest
);
4043 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
4046 if (BITS_BIG_ENDIAN
)
4047 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
4049 or_mask
= gen_int_mode (src
<< pos
, mode
);
4052 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4055 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4057 simplify_gen_binary (IOR
, mode
,
4058 simplify_gen_binary (AND
, mode
,
4063 SUBST (SET_DEST (x
), dest
);
4065 split
= find_split_point (&SET_SRC (x
), insn
);
4066 if (split
&& split
!= &SET_SRC (x
))
4070 /* Otherwise, see if this is an operation that we can split into two.
4071 If so, try to split that. */
4072 code
= GET_CODE (SET_SRC (x
));
4077 /* If we are AND'ing with a large constant that is only a single
4078 bit and the result is only being used in a context where we
4079 need to know if it is zero or nonzero, replace it with a bit
4080 extraction. This will avoid the large constant, which might
4081 have taken more than one insn to make. If the constant were
4082 not a valid argument to the AND but took only one insn to make,
4083 this is no worse, but if it took more than one insn, it will
4086 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4087 && REG_P (XEXP (SET_SRC (x
), 0))
4088 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4089 && REG_P (SET_DEST (x
))
4090 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4091 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4092 && XEXP (*split
, 0) == SET_DEST (x
)
4093 && XEXP (*split
, 1) == const0_rtx
)
4095 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4096 XEXP (SET_SRC (x
), 0),
4097 pos
, NULL_RTX
, 1, 1, 0, 0);
4098 if (extraction
!= 0)
4100 SUBST (SET_SRC (x
), extraction
);
4101 return find_split_point (loc
, insn
);
4107 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4108 is known to be on, this can be converted into a NEG of a shift. */
4109 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4110 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4111 && 1 <= (pos
= exact_log2
4112 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4113 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4115 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4119 gen_rtx_LSHIFTRT (mode
,
4120 XEXP (SET_SRC (x
), 0),
4123 split
= find_split_point (&SET_SRC (x
), insn
);
4124 if (split
&& split
!= &SET_SRC (x
))
4130 inner
= XEXP (SET_SRC (x
), 0);
4132 /* We can't optimize if either mode is a partial integer
4133 mode as we don't know how many bits are significant
4135 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4136 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4140 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
4146 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4147 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4149 inner
= XEXP (SET_SRC (x
), 0);
4150 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4151 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4153 if (BITS_BIG_ENDIAN
)
4154 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
4155 unsignedp
= (code
== ZERO_EXTRACT
);
4163 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
4165 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4167 /* For unsigned, we have a choice of a shift followed by an
4168 AND or two shifts. Use two shifts for field sizes where the
4169 constant might be too large. We assume here that we can
4170 always at least get 8-bit constants in an AND insn, which is
4171 true for every current RISC. */
4173 if (unsignedp
&& len
<= 8)
4178 (mode
, gen_lowpart (mode
, inner
),
4180 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
4182 split
= find_split_point (&SET_SRC (x
), insn
);
4183 if (split
&& split
!= &SET_SRC (x
))
4190 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4191 gen_rtx_ASHIFT (mode
,
4192 gen_lowpart (mode
, inner
),
4193 GEN_INT (GET_MODE_BITSIZE (mode
)
4195 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
4197 split
= find_split_point (&SET_SRC (x
), insn
);
4198 if (split
&& split
!= &SET_SRC (x
))
4203 /* See if this is a simple operation with a constant as the second
4204 operand. It might be that this constant is out of range and hence
4205 could be used as a split point. */
4206 if (BINARY_P (SET_SRC (x
))
4207 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4208 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4209 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4210 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4211 return &XEXP (SET_SRC (x
), 1);
4213 /* Finally, see if this is a simple operation with its first operand
4214 not in a register. The operation might require this operand in a
4215 register, so return it as a split point. We can always do this
4216 because if the first operand were another operation, we would have
4217 already found it as a split point. */
4218 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4219 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4220 return &XEXP (SET_SRC (x
), 0);
4226 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4227 it is better to write this as (not (ior A B)) so we can split it.
4228 Similarly for IOR. */
4229 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4232 gen_rtx_NOT (GET_MODE (x
),
4233 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4235 XEXP (XEXP (x
, 0), 0),
4236 XEXP (XEXP (x
, 1), 0))));
4237 return find_split_point (loc
, insn
);
4240 /* Many RISC machines have a large set of logical insns. If the
4241 second operand is a NOT, put it first so we will try to split the
4242 other operand first. */
4243 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4245 rtx tem
= XEXP (x
, 0);
4246 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4247 SUBST (XEXP (x
, 1), tem
);
4255 /* Otherwise, select our actions depending on our rtx class. */
4256 switch (GET_RTX_CLASS (code
))
4258 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4260 split
= find_split_point (&XEXP (x
, 2), insn
);
4263 /* ... fall through ... */
4265 case RTX_COMM_ARITH
:
4267 case RTX_COMM_COMPARE
:
4268 split
= find_split_point (&XEXP (x
, 1), insn
);
4271 /* ... fall through ... */
4273 /* Some machines have (and (shift ...) ...) insns. If X is not
4274 an AND, but XEXP (X, 0) is, use it as our split point. */
4275 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4276 return &XEXP (x
, 0);
4278 split
= find_split_point (&XEXP (x
, 0), insn
);
4284 /* Otherwise, we don't have a split point. */
4289 /* Throughout X, replace FROM with TO, and return the result.
4290 The result is TO if X is FROM;
4291 otherwise the result is X, but its contents may have been modified.
4292 If they were modified, a record was made in undobuf so that
4293 undo_all will (among other things) return X to its original state.
4295 If the number of changes necessary is too much to record to undo,
4296 the excess changes are not made, so the result is invalid.
4297 The changes already made can still be undone.
4298 undobuf.num_undo is incremented for such changes, so by testing that
4299 the caller can tell whether the result is valid.
4301 `n_occurrences' is incremented each time FROM is replaced.
4303 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4305 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4306 by copying if `n_occurrences' is nonzero. */
4309 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
4311 enum rtx_code code
= GET_CODE (x
);
4312 enum machine_mode op0_mode
= VOIDmode
;
4317 /* Two expressions are equal if they are identical copies of a shared
4318 RTX or if they are both registers with the same register number
4321 #define COMBINE_RTX_EQUAL_P(X,Y) \
4323 || (REG_P (X) && REG_P (Y) \
4324 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4326 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4329 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4332 /* If X and FROM are the same register but different modes, they
4333 will not have been seen as equal above. However, the log links code
4334 will make a LOG_LINKS entry for that case. If we do nothing, we
4335 will try to rerecognize our original insn and, when it succeeds,
4336 we will delete the feeding insn, which is incorrect.
4338 So force this insn not to match in this (rare) case. */
4339 if (! in_dest
&& code
== REG
&& REG_P (from
)
4340 && reg_overlap_mentioned_p (x
, from
))
4341 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4343 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4344 of which may contain things that can be combined. */
4345 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4348 /* It is possible to have a subexpression appear twice in the insn.
4349 Suppose that FROM is a register that appears within TO.
4350 Then, after that subexpression has been scanned once by `subst',
4351 the second time it is scanned, TO may be found. If we were
4352 to scan TO here, we would find FROM within it and create a
4353 self-referent rtl structure which is completely wrong. */
4354 if (COMBINE_RTX_EQUAL_P (x
, to
))
4357 /* Parallel asm_operands need special attention because all of the
4358 inputs are shared across the arms. Furthermore, unsharing the
4359 rtl results in recognition failures. Failure to handle this case
4360 specially can result in circular rtl.
4362 Solve this by doing a normal pass across the first entry of the
4363 parallel, and only processing the SET_DESTs of the subsequent
4366 if (code
== PARALLEL
4367 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4368 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4370 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
4372 /* If this substitution failed, this whole thing fails. */
4373 if (GET_CODE (new_rtx
) == CLOBBER
4374 && XEXP (new_rtx
, 0) == const0_rtx
)
4377 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4379 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4381 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4384 && GET_CODE (dest
) != CC0
4385 && GET_CODE (dest
) != PC
)
4387 new_rtx
= subst (dest
, from
, to
, 0, unique_copy
);
4389 /* If this substitution failed, this whole thing fails. */
4390 if (GET_CODE (new_rtx
) == CLOBBER
4391 && XEXP (new_rtx
, 0) == const0_rtx
)
4394 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
4400 len
= GET_RTX_LENGTH (code
);
4401 fmt
= GET_RTX_FORMAT (code
);
4403 /* We don't need to process a SET_DEST that is a register, CC0,
4404 or PC, so set up to skip this common case. All other cases
4405 where we want to suppress replacing something inside a
4406 SET_SRC are handled via the IN_DEST operand. */
4408 && (REG_P (SET_DEST (x
))
4409 || GET_CODE (SET_DEST (x
)) == CC0
4410 || GET_CODE (SET_DEST (x
)) == PC
))
4413 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4416 op0_mode
= GET_MODE (XEXP (x
, 0));
4418 for (i
= 0; i
< len
; i
++)
4423 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4425 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
4427 new_rtx
= (unique_copy
&& n_occurrences
4428 ? copy_rtx (to
) : to
);
4433 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0,
4436 /* If this substitution failed, this whole thing
4438 if (GET_CODE (new_rtx
) == CLOBBER
4439 && XEXP (new_rtx
, 0) == const0_rtx
)
4443 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
4446 else if (fmt
[i
] == 'e')
4448 /* If this is a register being set, ignore it. */
4449 new_rtx
= XEXP (x
, i
);
4452 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
4454 || code
== STRICT_LOW_PART
))
4457 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
4459 /* In general, don't install a subreg involving two
4460 modes not tieable. It can worsen register
4461 allocation, and can even make invalid reload
4462 insns, since the reg inside may need to be copied
4463 from in the outside mode, and that may be invalid
4464 if it is an fp reg copied in integer mode.
4466 We allow two exceptions to this: It is valid if
4467 it is inside another SUBREG and the mode of that
4468 SUBREG and the mode of the inside of TO is
4469 tieable and it is valid if X is a SET that copies
4472 if (GET_CODE (to
) == SUBREG
4473 && ! MODES_TIEABLE_P (GET_MODE (to
),
4474 GET_MODE (SUBREG_REG (to
)))
4475 && ! (code
== SUBREG
4476 && MODES_TIEABLE_P (GET_MODE (x
),
4477 GET_MODE (SUBREG_REG (to
))))
4479 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
4482 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
4484 #ifdef CANNOT_CHANGE_MODE_CLASS
4487 && REGNO (to
) < FIRST_PSEUDO_REGISTER
4488 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
4491 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
4494 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
4498 /* If we are in a SET_DEST, suppress most cases unless we
4499 have gone inside a MEM, in which case we want to
4500 simplify the address. We assume here that things that
4501 are actually part of the destination have their inner
4502 parts in the first expression. This is true for SUBREG,
4503 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4504 things aside from REG and MEM that should appear in a
4506 new_rtx
= subst (XEXP (x
, i
), from
, to
,
4508 && (code
== SUBREG
|| code
== STRICT_LOW_PART
4509 || code
== ZERO_EXTRACT
))
4511 && i
== 0), unique_copy
);
4513 /* If we found that we will have to reject this combination,
4514 indicate that by returning the CLOBBER ourselves, rather than
4515 an expression containing it. This will speed things up as
4516 well as prevent accidents where two CLOBBERs are considered
4517 to be equal, thus producing an incorrect simplification. */
4519 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
4522 if (GET_CODE (x
) == SUBREG
4523 && (CONST_INT_P (new_rtx
)
4524 || GET_CODE (new_rtx
) == CONST_DOUBLE
))
4526 enum machine_mode mode
= GET_MODE (x
);
4528 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
4529 GET_MODE (SUBREG_REG (x
)),
4532 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
4534 else if (CONST_INT_P (new_rtx
)
4535 && GET_CODE (x
) == ZERO_EXTEND
)
4537 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
4538 new_rtx
, GET_MODE (XEXP (x
, 0)));
4542 SUBST (XEXP (x
, i
), new_rtx
);
4547 /* Check if we are loading something from the constant pool via float
4548 extension; in this case we would undo compress_float_constant
4549 optimization and degenerate constant load to an immediate value. */
4550 if (GET_CODE (x
) == FLOAT_EXTEND
4551 && MEM_P (XEXP (x
, 0))
4552 && MEM_READONLY_P (XEXP (x
, 0)))
4554 rtx tmp
= avoid_constant_pool_reference (x
);
4559 /* Try to simplify X. If the simplification changed the code, it is likely
4560 that further simplification will help, so loop, but limit the number
4561 of repetitions that will be performed. */
4563 for (i
= 0; i
< 4; i
++)
4565 /* If X is sufficiently simple, don't bother trying to do anything
4567 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
4568 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
4570 if (GET_CODE (x
) == code
)
4573 code
= GET_CODE (x
);
4575 /* We no longer know the original mode of operand 0 since we
4576 have changed the form of X) */
4577 op0_mode
= VOIDmode
;
4583 /* Simplify X, a piece of RTL. We just operate on the expression at the
4584 outer level; call `subst' to simplify recursively. Return the new
4587 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4588 if we are inside a SET_DEST. */
4591 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
4593 enum rtx_code code
= GET_CODE (x
);
4594 enum machine_mode mode
= GET_MODE (x
);
4598 /* If this is a commutative operation, put a constant last and a complex
4599 expression first. We don't need to do this for comparisons here. */
4600 if (COMMUTATIVE_ARITH_P (x
)
4601 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
4604 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4605 SUBST (XEXP (x
, 1), temp
);
4608 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4609 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4610 things. Check for cases where both arms are testing the same
4613 Don't do anything if all operands are very simple. */
4616 && ((!OBJECT_P (XEXP (x
, 0))
4617 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4618 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
4619 || (!OBJECT_P (XEXP (x
, 1))
4620 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
4621 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
4623 && (!OBJECT_P (XEXP (x
, 0))
4624 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4625 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
4627 rtx cond
, true_rtx
, false_rtx
;
4629 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
4631 /* If everything is a comparison, what we have is highly unlikely
4632 to be simpler, so don't use it. */
4633 && ! (COMPARISON_P (x
)
4634 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
4636 rtx cop1
= const0_rtx
;
4637 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
4639 if (cond_code
== NE
&& COMPARISON_P (cond
))
4642 /* Simplify the alternative arms; this may collapse the true and
4643 false arms to store-flag values. Be careful to use copy_rtx
4644 here since true_rtx or false_rtx might share RTL with x as a
4645 result of the if_then_else_cond call above. */
4646 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
4647 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
4649 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4650 is unlikely to be simpler. */
4651 if (general_operand (true_rtx
, VOIDmode
)
4652 && general_operand (false_rtx
, VOIDmode
))
4654 enum rtx_code reversed
;
4656 /* Restarting if we generate a store-flag expression will cause
4657 us to loop. Just drop through in this case. */
4659 /* If the result values are STORE_FLAG_VALUE and zero, we can
4660 just make the comparison operation. */
4661 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4662 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
4664 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4665 && ((reversed
= reversed_comparison_code_parts
4666 (cond_code
, cond
, cop1
, NULL
))
4668 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
4671 /* Likewise, we can make the negate of a comparison operation
4672 if the result values are - STORE_FLAG_VALUE and zero. */
4673 else if (CONST_INT_P (true_rtx
)
4674 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
4675 && false_rtx
== const0_rtx
)
4676 x
= simplify_gen_unary (NEG
, mode
,
4677 simplify_gen_relational (cond_code
,
4681 else if (CONST_INT_P (false_rtx
)
4682 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
4683 && true_rtx
== const0_rtx
4684 && ((reversed
= reversed_comparison_code_parts
4685 (cond_code
, cond
, cop1
, NULL
))
4687 x
= simplify_gen_unary (NEG
, mode
,
4688 simplify_gen_relational (reversed
,
4693 return gen_rtx_IF_THEN_ELSE (mode
,
4694 simplify_gen_relational (cond_code
,
4699 true_rtx
, false_rtx
);
4701 code
= GET_CODE (x
);
4702 op0_mode
= VOIDmode
;
4707 /* Try to fold this expression in case we have constants that weren't
4710 switch (GET_RTX_CLASS (code
))
4713 if (op0_mode
== VOIDmode
)
4714 op0_mode
= GET_MODE (XEXP (x
, 0));
4715 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
4718 case RTX_COMM_COMPARE
:
4720 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
4721 if (cmp_mode
== VOIDmode
)
4723 cmp_mode
= GET_MODE (XEXP (x
, 1));
4724 if (cmp_mode
== VOIDmode
)
4725 cmp_mode
= op0_mode
;
4727 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
4728 XEXP (x
, 0), XEXP (x
, 1));
4731 case RTX_COMM_ARITH
:
4733 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4735 case RTX_BITFIELD_OPS
:
4737 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
4738 XEXP (x
, 1), XEXP (x
, 2));
4747 code
= GET_CODE (temp
);
4748 op0_mode
= VOIDmode
;
4749 mode
= GET_MODE (temp
);
4752 /* First see if we can apply the inverse distributive law. */
4753 if (code
== PLUS
|| code
== MINUS
4754 || code
== AND
|| code
== IOR
|| code
== XOR
)
4756 x
= apply_distributive_law (x
);
4757 code
= GET_CODE (x
);
4758 op0_mode
= VOIDmode
;
4761 /* If CODE is an associative operation not otherwise handled, see if we
4762 can associate some operands. This can win if they are constants or
4763 if they are logically related (i.e. (a & b) & a). */
4764 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
4765 || code
== AND
|| code
== IOR
|| code
== XOR
4766 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
4767 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
4768 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
4770 if (GET_CODE (XEXP (x
, 0)) == code
)
4772 rtx other
= XEXP (XEXP (x
, 0), 0);
4773 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
4774 rtx inner_op1
= XEXP (x
, 1);
4777 /* Make sure we pass the constant operand if any as the second
4778 one if this is a commutative operation. */
4779 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
4781 rtx tem
= inner_op0
;
4782 inner_op0
= inner_op1
;
4785 inner
= simplify_binary_operation (code
== MINUS
? PLUS
4786 : code
== DIV
? MULT
4788 mode
, inner_op0
, inner_op1
);
4790 /* For commutative operations, try the other pair if that one
4792 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
4794 other
= XEXP (XEXP (x
, 0), 1);
4795 inner
= simplify_binary_operation (code
, mode
,
4796 XEXP (XEXP (x
, 0), 0),
4801 return simplify_gen_binary (code
, mode
, other
, inner
);
4805 /* A little bit of algebraic simplification here. */
4809 /* Ensure that our address has any ASHIFTs converted to MULT in case
4810 address-recognizing predicates are called later. */
4811 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
4812 SUBST (XEXP (x
, 0), temp
);
4816 if (op0_mode
== VOIDmode
)
4817 op0_mode
= GET_MODE (SUBREG_REG (x
));
4819 /* See if this can be moved to simplify_subreg. */
4820 if (CONSTANT_P (SUBREG_REG (x
))
4821 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
4822 /* Don't call gen_lowpart if the inner mode
4823 is VOIDmode and we cannot simplify it, as SUBREG without
4824 inner mode is invalid. */
4825 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
4826 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
4827 return gen_lowpart (mode
, SUBREG_REG (x
));
4829 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
4833 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
4839 /* Don't change the mode of the MEM if that would change the meaning
4841 if (MEM_P (SUBREG_REG (x
))
4842 && (MEM_VOLATILE_P (SUBREG_REG (x
))
4843 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
4844 return gen_rtx_CLOBBER (mode
, const0_rtx
);
4846 /* Note that we cannot do any narrowing for non-constants since
4847 we might have been counting on using the fact that some bits were
4848 zero. We now do this in the SET. */
4853 temp
= expand_compound_operation (XEXP (x
, 0));
4855 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4856 replaced by (lshiftrt X C). This will convert
4857 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4859 if (GET_CODE (temp
) == ASHIFTRT
4860 && CONST_INT_P (XEXP (temp
, 1))
4861 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4862 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4863 INTVAL (XEXP (temp
, 1)));
4865 /* If X has only a single bit that might be nonzero, say, bit I, convert
4866 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4867 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4868 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4869 or a SUBREG of one since we'd be making the expression more
4870 complex if it was just a register. */
4873 && ! (GET_CODE (temp
) == SUBREG
4874 && REG_P (SUBREG_REG (temp
)))
4875 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4877 rtx temp1
= simplify_shift_const
4878 (NULL_RTX
, ASHIFTRT
, mode
,
4879 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4880 GET_MODE_BITSIZE (mode
) - 1 - i
),
4881 GET_MODE_BITSIZE (mode
) - 1 - i
);
4883 /* If all we did was surround TEMP with the two shifts, we
4884 haven't improved anything, so don't use it. Otherwise,
4885 we are better off with TEMP1. */
4886 if (GET_CODE (temp1
) != ASHIFTRT
4887 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4888 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4894 /* We can't handle truncation to a partial integer mode here
4895 because we don't know the real bitsize of the partial
4897 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4900 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4902 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4903 GET_MODE_MASK (mode
), 0));
4905 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4906 whose value is a comparison can be replaced with a subreg if
4907 STORE_FLAG_VALUE permits. */
4908 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4909 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4910 && (temp
= get_last_value (XEXP (x
, 0)))
4911 && COMPARISON_P (temp
))
4912 return gen_lowpart (mode
, XEXP (x
, 0));
4916 /* (const (const X)) can become (const X). Do it this way rather than
4917 returning the inner CONST since CONST can be shared with a
4919 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4920 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4925 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4926 can add in an offset. find_split_point will split this address up
4927 again if it doesn't match. */
4928 if (GET_CODE (XEXP (x
, 0)) == HIGH
4929 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4935 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4936 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4937 bit-field and can be replaced by either a sign_extend or a
4938 sign_extract. The `and' may be a zero_extend and the two
4939 <c>, -<c> constants may be reversed. */
4940 if (GET_CODE (XEXP (x
, 0)) == XOR
4941 && CONST_INT_P (XEXP (x
, 1))
4942 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4943 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4944 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4945 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4946 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4947 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4948 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4949 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4950 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4951 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4952 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4953 == (unsigned int) i
+ 1))))
4954 return simplify_shift_const
4955 (NULL_RTX
, ASHIFTRT
, mode
,
4956 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4957 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4958 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4959 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4961 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4962 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4963 the bitsize of the mode - 1. This allows simplification of
4964 "a = (b & 8) == 0;" */
4965 if (XEXP (x
, 1) == constm1_rtx
4966 && !REG_P (XEXP (x
, 0))
4967 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4968 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4969 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4970 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4971 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4972 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4973 GET_MODE_BITSIZE (mode
) - 1),
4974 GET_MODE_BITSIZE (mode
) - 1);
4976 /* If we are adding two things that have no bits in common, convert
4977 the addition into an IOR. This will often be further simplified,
4978 for example in cases like ((a & 1) + (a & 2)), which can
4981 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4982 && (nonzero_bits (XEXP (x
, 0), mode
)
4983 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4985 /* Try to simplify the expression further. */
4986 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4987 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4989 /* If we could, great. If not, do not go ahead with the IOR
4990 replacement, since PLUS appears in many special purpose
4991 address arithmetic instructions. */
4992 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4998 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4999 (and <foo> (const_int pow2-1)) */
5000 if (GET_CODE (XEXP (x
, 1)) == AND
5001 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5002 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5003 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5004 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5005 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5009 /* If we have (mult (plus A B) C), apply the distributive law and then
5010 the inverse distributive law to see if things simplify. This
5011 occurs mostly in addresses, often when unrolling loops. */
5013 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5015 rtx result
= distribute_and_simplify_rtx (x
, 0);
5020 /* Try simplify a*(b/c) as (a*b)/c. */
5021 if (FLOAT_MODE_P (mode
) && flag_associative_math
5022 && GET_CODE (XEXP (x
, 0)) == DIV
)
5024 rtx tem
= simplify_binary_operation (MULT
, mode
,
5025 XEXP (XEXP (x
, 0), 0),
5028 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5033 /* If this is a divide by a power of two, treat it as a shift if
5034 its first operand is a shift. */
5035 if (CONST_INT_P (XEXP (x
, 1))
5036 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
5037 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5038 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5039 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5040 || GET_CODE (XEXP (x
, 0)) == ROTATE
5041 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5042 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5046 case GT
: case GTU
: case GE
: case GEU
:
5047 case LT
: case LTU
: case LE
: case LEU
:
5048 case UNEQ
: case LTGT
:
5049 case UNGT
: case UNGE
:
5050 case UNLT
: case UNLE
:
5051 case UNORDERED
: case ORDERED
:
5052 /* If the first operand is a condition code, we can't do anything
5054 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5055 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5056 && ! CC0_P (XEXP (x
, 0))))
5058 rtx op0
= XEXP (x
, 0);
5059 rtx op1
= XEXP (x
, 1);
5060 enum rtx_code new_code
;
5062 if (GET_CODE (op0
) == COMPARE
)
5063 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5065 /* Simplify our comparison, if possible. */
5066 new_code
= simplify_comparison (code
, &op0
, &op1
);
5068 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5069 if only the low-order bit is possibly nonzero in X (such as when
5070 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5071 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5072 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5075 Remove any ZERO_EXTRACT we made when thinking this was a
5076 comparison. It may now be simpler to use, e.g., an AND. If a
5077 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5078 the call to make_compound_operation in the SET case. */
5080 if (STORE_FLAG_VALUE
== 1
5081 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5082 && op1
== const0_rtx
5083 && mode
== GET_MODE (op0
)
5084 && nonzero_bits (op0
, mode
) == 1)
5085 return gen_lowpart (mode
,
5086 expand_compound_operation (op0
));
5088 else if (STORE_FLAG_VALUE
== 1
5089 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5090 && op1
== const0_rtx
5091 && mode
== GET_MODE (op0
)
5092 && (num_sign_bit_copies (op0
, mode
)
5093 == GET_MODE_BITSIZE (mode
)))
5095 op0
= expand_compound_operation (op0
);
5096 return simplify_gen_unary (NEG
, mode
,
5097 gen_lowpart (mode
, op0
),
5101 else if (STORE_FLAG_VALUE
== 1
5102 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5103 && op1
== const0_rtx
5104 && mode
== GET_MODE (op0
)
5105 && nonzero_bits (op0
, mode
) == 1)
5107 op0
= expand_compound_operation (op0
);
5108 return simplify_gen_binary (XOR
, mode
,
5109 gen_lowpart (mode
, op0
),
5113 else if (STORE_FLAG_VALUE
== 1
5114 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5115 && op1
== const0_rtx
5116 && mode
== GET_MODE (op0
)
5117 && (num_sign_bit_copies (op0
, mode
)
5118 == GET_MODE_BITSIZE (mode
)))
5120 op0
= expand_compound_operation (op0
);
5121 return plus_constant (gen_lowpart (mode
, op0
), 1);
5124 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5126 if (STORE_FLAG_VALUE
== -1
5127 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5128 && op1
== const0_rtx
5129 && (num_sign_bit_copies (op0
, mode
)
5130 == GET_MODE_BITSIZE (mode
)))
5131 return gen_lowpart (mode
,
5132 expand_compound_operation (op0
));
5134 else if (STORE_FLAG_VALUE
== -1
5135 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5136 && op1
== const0_rtx
5137 && mode
== GET_MODE (op0
)
5138 && nonzero_bits (op0
, mode
) == 1)
5140 op0
= expand_compound_operation (op0
);
5141 return simplify_gen_unary (NEG
, mode
,
5142 gen_lowpart (mode
, op0
),
5146 else if (STORE_FLAG_VALUE
== -1
5147 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5148 && op1
== const0_rtx
5149 && mode
== GET_MODE (op0
)
5150 && (num_sign_bit_copies (op0
, mode
)
5151 == GET_MODE_BITSIZE (mode
)))
5153 op0
= expand_compound_operation (op0
);
5154 return simplify_gen_unary (NOT
, mode
,
5155 gen_lowpart (mode
, op0
),
5159 /* If X is 0/1, (eq X 0) is X-1. */
5160 else if (STORE_FLAG_VALUE
== -1
5161 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5162 && op1
== const0_rtx
5163 && mode
== GET_MODE (op0
)
5164 && nonzero_bits (op0
, mode
) == 1)
5166 op0
= expand_compound_operation (op0
);
5167 return plus_constant (gen_lowpart (mode
, op0
), -1);
5170 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5171 one bit that might be nonzero, we can convert (ne x 0) to
5172 (ashift x c) where C puts the bit in the sign bit. Remove any
5173 AND with STORE_FLAG_VALUE when we are done, since we are only
5174 going to test the sign bit. */
5175 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5176 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5177 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5178 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5179 && op1
== const0_rtx
5180 && mode
== GET_MODE (op0
)
5181 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5183 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5184 expand_compound_operation (op0
),
5185 GET_MODE_BITSIZE (mode
) - 1 - i
);
5186 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5192 /* If the code changed, return a whole new comparison. */
5193 if (new_code
!= code
)
5194 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5196 /* Otherwise, keep this operation, but maybe change its operands.
5197 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5198 SUBST (XEXP (x
, 0), op0
);
5199 SUBST (XEXP (x
, 1), op1
);
5204 return simplify_if_then_else (x
);
5210 /* If we are processing SET_DEST, we are done. */
5214 return expand_compound_operation (x
);
5217 return simplify_set (x
);
5221 return simplify_logical (x
);
5228 /* If this is a shift by a constant amount, simplify it. */
5229 if (CONST_INT_P (XEXP (x
, 1)))
5230 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5231 INTVAL (XEXP (x
, 1)));
5233 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5235 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5237 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5249 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5252 simplify_if_then_else (rtx x
)
5254 enum machine_mode mode
= GET_MODE (x
);
5255 rtx cond
= XEXP (x
, 0);
5256 rtx true_rtx
= XEXP (x
, 1);
5257 rtx false_rtx
= XEXP (x
, 2);
5258 enum rtx_code true_code
= GET_CODE (cond
);
5259 int comparison_p
= COMPARISON_P (cond
);
5262 enum rtx_code false_code
;
5265 /* Simplify storing of the truth value. */
5266 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5267 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5268 XEXP (cond
, 0), XEXP (cond
, 1));
5270 /* Also when the truth value has to be reversed. */
5272 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5273 && (reversed
= reversed_comparison (cond
, mode
)))
5276 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5277 in it is being compared against certain values. Get the true and false
5278 comparisons and see if that says anything about the value of each arm. */
5281 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5283 && REG_P (XEXP (cond
, 0)))
5286 rtx from
= XEXP (cond
, 0);
5287 rtx true_val
= XEXP (cond
, 1);
5288 rtx false_val
= true_val
;
5291 /* If FALSE_CODE is EQ, swap the codes and arms. */
5293 if (false_code
== EQ
)
5295 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5296 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5299 /* If we are comparing against zero and the expression being tested has
5300 only a single bit that might be nonzero, that is its value when it is
5301 not equal to zero. Similarly if it is known to be -1 or 0. */
5303 if (true_code
== EQ
&& true_val
== const0_rtx
5304 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5307 false_val
= GEN_INT (trunc_int_for_mode (nzb
, GET_MODE (from
)));
5309 else if (true_code
== EQ
&& true_val
== const0_rtx
5310 && (num_sign_bit_copies (from
, GET_MODE (from
))
5311 == GET_MODE_BITSIZE (GET_MODE (from
))))
5314 false_val
= constm1_rtx
;
5317 /* Now simplify an arm if we know the value of the register in the
5318 branch and it is used in the arm. Be careful due to the potential
5319 of locally-shared RTL. */
5321 if (reg_mentioned_p (from
, true_rtx
))
5322 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5324 pc_rtx
, pc_rtx
, 0, 0);
5325 if (reg_mentioned_p (from
, false_rtx
))
5326 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5328 pc_rtx
, pc_rtx
, 0, 0);
5330 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5331 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5333 true_rtx
= XEXP (x
, 1);
5334 false_rtx
= XEXP (x
, 2);
5335 true_code
= GET_CODE (cond
);
5338 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5339 reversed, do so to avoid needing two sets of patterns for
5340 subtract-and-branch insns. Similarly if we have a constant in the true
5341 arm, the false arm is the same as the first operand of the comparison, or
5342 the false arm is more complicated than the true arm. */
5345 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5346 && (true_rtx
== pc_rtx
5347 || (CONSTANT_P (true_rtx
)
5348 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5349 || true_rtx
== const0_rtx
5350 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5351 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5352 && !OBJECT_P (false_rtx
))
5353 || reg_mentioned_p (true_rtx
, false_rtx
)
5354 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5356 true_code
= reversed_comparison_code (cond
, NULL
);
5357 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5358 SUBST (XEXP (x
, 1), false_rtx
);
5359 SUBST (XEXP (x
, 2), true_rtx
);
5361 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5364 /* It is possible that the conditional has been simplified out. */
5365 true_code
= GET_CODE (cond
);
5366 comparison_p
= COMPARISON_P (cond
);
5369 /* If the two arms are identical, we don't need the comparison. */
5371 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5374 /* Convert a == b ? b : a to "a". */
5375 if (true_code
== EQ
&& ! side_effects_p (cond
)
5376 && !HONOR_NANS (mode
)
5377 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5378 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5380 else if (true_code
== NE
&& ! side_effects_p (cond
)
5381 && !HONOR_NANS (mode
)
5382 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5383 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
5386 /* Look for cases where we have (abs x) or (neg (abs X)). */
5388 if (GET_MODE_CLASS (mode
) == MODE_INT
5390 && XEXP (cond
, 1) == const0_rtx
5391 && GET_CODE (false_rtx
) == NEG
5392 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
5393 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
5394 && ! side_effects_p (true_rtx
))
5399 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
5403 simplify_gen_unary (NEG
, mode
,
5404 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
5410 /* Look for MIN or MAX. */
5412 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
5414 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5415 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
5416 && ! side_effects_p (cond
))
5421 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
5424 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
5427 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
5430 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
5435 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5436 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5437 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5438 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5439 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5440 neither 1 or -1, but it isn't worth checking for. */
5442 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5444 && GET_MODE_CLASS (mode
) == MODE_INT
5445 && ! side_effects_p (x
))
5447 rtx t
= make_compound_operation (true_rtx
, SET
);
5448 rtx f
= make_compound_operation (false_rtx
, SET
);
5449 rtx cond_op0
= XEXP (cond
, 0);
5450 rtx cond_op1
= XEXP (cond
, 1);
5451 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
5452 enum machine_mode m
= mode
;
5453 rtx z
= 0, c1
= NULL_RTX
;
5455 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
5456 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
5457 || GET_CODE (t
) == ASHIFT
5458 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
5459 && rtx_equal_p (XEXP (t
, 0), f
))
5460 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
5462 /* If an identity-zero op is commutative, check whether there
5463 would be a match if we swapped the operands. */
5464 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
5465 || GET_CODE (t
) == XOR
)
5466 && rtx_equal_p (XEXP (t
, 1), f
))
5467 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
5468 else if (GET_CODE (t
) == SIGN_EXTEND
5469 && (GET_CODE (XEXP (t
, 0)) == PLUS
5470 || GET_CODE (XEXP (t
, 0)) == MINUS
5471 || GET_CODE (XEXP (t
, 0)) == IOR
5472 || GET_CODE (XEXP (t
, 0)) == XOR
5473 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5474 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5475 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5476 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5477 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5478 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5479 && (num_sign_bit_copies (f
, GET_MODE (f
))
5481 (GET_MODE_BITSIZE (mode
)
5482 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
5484 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5485 extend_op
= SIGN_EXTEND
;
5486 m
= GET_MODE (XEXP (t
, 0));
5488 else if (GET_CODE (t
) == SIGN_EXTEND
5489 && (GET_CODE (XEXP (t
, 0)) == PLUS
5490 || GET_CODE (XEXP (t
, 0)) == IOR
5491 || GET_CODE (XEXP (t
, 0)) == XOR
)
5492 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5493 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5494 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5495 && (num_sign_bit_copies (f
, GET_MODE (f
))
5497 (GET_MODE_BITSIZE (mode
)
5498 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5500 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5501 extend_op
= SIGN_EXTEND
;
5502 m
= GET_MODE (XEXP (t
, 0));
5504 else if (GET_CODE (t
) == ZERO_EXTEND
5505 && (GET_CODE (XEXP (t
, 0)) == PLUS
5506 || GET_CODE (XEXP (t
, 0)) == MINUS
5507 || GET_CODE (XEXP (t
, 0)) == IOR
5508 || GET_CODE (XEXP (t
, 0)) == XOR
5509 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5510 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5511 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5512 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5513 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5514 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5515 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5516 && ((nonzero_bits (f
, GET_MODE (f
))
5517 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5520 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5521 extend_op
= ZERO_EXTEND
;
5522 m
= GET_MODE (XEXP (t
, 0));
5524 else if (GET_CODE (t
) == ZERO_EXTEND
5525 && (GET_CODE (XEXP (t
, 0)) == PLUS
5526 || GET_CODE (XEXP (t
, 0)) == IOR
5527 || GET_CODE (XEXP (t
, 0)) == XOR
)
5528 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5529 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5530 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5531 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5532 && ((nonzero_bits (f
, GET_MODE (f
))
5533 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5536 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5537 extend_op
= ZERO_EXTEND
;
5538 m
= GET_MODE (XEXP (t
, 0));
5543 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
5544 cond_op0
, cond_op1
),
5545 pc_rtx
, pc_rtx
, 0, 0);
5546 temp
= simplify_gen_binary (MULT
, m
, temp
,
5547 simplify_gen_binary (MULT
, m
, c1
,
5549 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5550 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5552 if (extend_op
!= UNKNOWN
)
5553 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5559 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5560 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5561 negation of a single bit, we can convert this operation to a shift. We
5562 can actually do this more generally, but it doesn't seem worth it. */
5564 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5565 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
5566 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5567 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5568 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5569 == GET_MODE_BITSIZE (mode
))
5570 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5572 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5573 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5575 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5576 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5577 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
5578 && GET_MODE (XEXP (cond
, 0)) == mode
5579 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5580 == nonzero_bits (XEXP (cond
, 0), mode
)
5581 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5582 return XEXP (cond
, 0);
5587 /* Simplify X, a SET expression. Return the new expression. */
5590 simplify_set (rtx x
)
5592 rtx src
= SET_SRC (x
);
5593 rtx dest
= SET_DEST (x
);
5594 enum machine_mode mode
5595 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5599 /* (set (pc) (return)) gets written as (return). */
5600 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5603 /* Now that we know for sure which bits of SRC we are using, see if we can
5604 simplify the expression for the object knowing that we only need the
5607 if (GET_MODE_CLASS (mode
) == MODE_INT
5608 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5610 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, 0);
5611 SUBST (SET_SRC (x
), src
);
5614 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5615 the comparison result and try to simplify it unless we already have used
5616 undobuf.other_insn. */
5617 if ((GET_MODE_CLASS (mode
) == MODE_CC
5618 || GET_CODE (src
) == COMPARE
5620 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5621 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5622 && COMPARISON_P (*cc_use
)
5623 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5625 enum rtx_code old_code
= GET_CODE (*cc_use
);
5626 enum rtx_code new_code
;
5628 int other_changed
= 0;
5629 enum machine_mode compare_mode
= GET_MODE (dest
);
5631 if (GET_CODE (src
) == COMPARE
)
5632 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5634 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5636 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5639 new_code
= old_code
;
5640 else if (!CONSTANT_P (tmp
))
5642 new_code
= GET_CODE (tmp
);
5643 op0
= XEXP (tmp
, 0);
5644 op1
= XEXP (tmp
, 1);
5648 rtx pat
= PATTERN (other_insn
);
5649 undobuf
.other_insn
= other_insn
;
5650 SUBST (*cc_use
, tmp
);
5652 /* Attempt to simplify CC user. */
5653 if (GET_CODE (pat
) == SET
)
5655 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
5656 if (new_rtx
!= NULL_RTX
)
5657 SUBST (SET_SRC (pat
), new_rtx
);
5660 /* Convert X into a no-op move. */
5661 SUBST (SET_DEST (x
), pc_rtx
);
5662 SUBST (SET_SRC (x
), pc_rtx
);
5666 /* Simplify our comparison, if possible. */
5667 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5669 #ifdef SELECT_CC_MODE
5670 /* If this machine has CC modes other than CCmode, check to see if we
5671 need to use a different CC mode here. */
5672 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5673 compare_mode
= GET_MODE (op0
);
5675 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5678 /* If the mode changed, we have to change SET_DEST, the mode in the
5679 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5680 a hard register, just build new versions with the proper mode. If it
5681 is a pseudo, we lose unless it is only time we set the pseudo, in
5682 which case we can safely change its mode. */
5683 if (compare_mode
!= GET_MODE (dest
))
5685 if (can_change_dest_mode (dest
, 0, compare_mode
))
5687 unsigned int regno
= REGNO (dest
);
5690 if (regno
< FIRST_PSEUDO_REGISTER
)
5691 new_dest
= gen_rtx_REG (compare_mode
, regno
);
5694 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
5695 new_dest
= regno_reg_rtx
[regno
];
5698 SUBST (SET_DEST (x
), new_dest
);
5699 SUBST (XEXP (*cc_use
, 0), new_dest
);
5706 #endif /* SELECT_CC_MODE */
5708 /* If the code changed, we have to build a new comparison in
5709 undobuf.other_insn. */
5710 if (new_code
!= old_code
)
5712 int other_changed_previously
= other_changed
;
5713 unsigned HOST_WIDE_INT mask
;
5714 rtx old_cc_use
= *cc_use
;
5716 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5720 /* If the only change we made was to change an EQ into an NE or
5721 vice versa, OP0 has only one bit that might be nonzero, and OP1
5722 is zero, check if changing the user of the condition code will
5723 produce a valid insn. If it won't, we can keep the original code
5724 in that insn by surrounding our operation with an XOR. */
5726 if (((old_code
== NE
&& new_code
== EQ
)
5727 || (old_code
== EQ
&& new_code
== NE
))
5728 && ! other_changed_previously
&& op1
== const0_rtx
5729 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5730 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5732 rtx pat
= PATTERN (other_insn
), note
= 0;
5734 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5735 && ! check_asm_operands (pat
)))
5737 *cc_use
= old_cc_use
;
5740 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
5741 op0
, GEN_INT (mask
));
5747 undobuf
.other_insn
= other_insn
;
5749 /* Otherwise, if we didn't previously have a COMPARE in the
5750 correct mode, we need one. */
5751 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5753 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5756 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
5758 SUBST (SET_SRC (x
), op0
);
5761 /* Otherwise, update the COMPARE if needed. */
5762 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
5764 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5770 /* Get SET_SRC in a form where we have placed back any
5771 compound expressions. Then do the checks below. */
5772 src
= make_compound_operation (src
, SET
);
5773 SUBST (SET_SRC (x
), src
);
5776 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5777 and X being a REG or (subreg (reg)), we may be able to convert this to
5778 (set (subreg:m2 x) (op)).
5780 We can always do this if M1 is narrower than M2 because that means that
5781 we only care about the low bits of the result.
5783 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5784 perform a narrower operation than requested since the high-order bits will
5785 be undefined. On machine where it is defined, this transformation is safe
5786 as long as M1 and M2 have the same number of words. */
5788 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5789 && !OBJECT_P (SUBREG_REG (src
))
5790 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5792 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5793 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5794 #ifndef WORD_REGISTER_OPERATIONS
5795 && (GET_MODE_SIZE (GET_MODE (src
))
5796 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5798 #ifdef CANNOT_CHANGE_MODE_CLASS
5799 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5800 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5801 GET_MODE (SUBREG_REG (src
)),
5805 || (GET_CODE (dest
) == SUBREG
5806 && REG_P (SUBREG_REG (dest
)))))
5808 SUBST (SET_DEST (x
),
5809 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5811 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5813 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5817 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5820 && GET_CODE (src
) == SUBREG
5821 && subreg_lowpart_p (src
)
5822 && (GET_MODE_BITSIZE (GET_MODE (src
))
5823 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5825 rtx inner
= SUBREG_REG (src
);
5826 enum machine_mode inner_mode
= GET_MODE (inner
);
5828 /* Here we make sure that we don't have a sign bit on. */
5829 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5830 && (nonzero_bits (inner
, inner_mode
)
5831 < ((unsigned HOST_WIDE_INT
) 1
5832 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5834 SUBST (SET_SRC (x
), inner
);
5840 #ifdef LOAD_EXTEND_OP
5841 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5842 would require a paradoxical subreg. Replace the subreg with a
5843 zero_extend to avoid the reload that would otherwise be required. */
5845 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5846 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
5847 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5848 && SUBREG_BYTE (src
) == 0
5849 && (GET_MODE_SIZE (GET_MODE (src
))
5850 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5851 && MEM_P (SUBREG_REG (src
)))
5854 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5855 GET_MODE (src
), SUBREG_REG (src
)));
5861 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5862 are comparing an item known to be 0 or -1 against 0, use a logical
5863 operation instead. Check for one of the arms being an IOR of the other
5864 arm with some value. We compute three terms to be IOR'ed together. In
5865 practice, at most two will be nonzero. Then we do the IOR's. */
5867 if (GET_CODE (dest
) != PC
5868 && GET_CODE (src
) == IF_THEN_ELSE
5869 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5870 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5871 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5872 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5873 #ifdef HAVE_conditional_move
5874 && ! can_conditionally_move_p (GET_MODE (src
))
5876 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5877 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5878 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5879 && ! side_effects_p (src
))
5881 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5882 ? XEXP (src
, 1) : XEXP (src
, 2));
5883 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5884 ? XEXP (src
, 2) : XEXP (src
, 1));
5885 rtx term1
= const0_rtx
, term2
, term3
;
5887 if (GET_CODE (true_rtx
) == IOR
5888 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5889 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5890 else if (GET_CODE (true_rtx
) == IOR
5891 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5892 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5893 else if (GET_CODE (false_rtx
) == IOR
5894 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5895 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5896 else if (GET_CODE (false_rtx
) == IOR
5897 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5898 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5900 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
5901 XEXP (XEXP (src
, 0), 0), true_rtx
);
5902 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
5903 simplify_gen_unary (NOT
, GET_MODE (src
),
5904 XEXP (XEXP (src
, 0), 0),
5909 simplify_gen_binary (IOR
, GET_MODE (src
),
5910 simplify_gen_binary (IOR
, GET_MODE (src
),
5917 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5918 whole thing fail. */
5919 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5921 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5924 /* Convert this into a field assignment operation, if possible. */
5925 return make_field_assignment (x
);
5928 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5932 simplify_logical (rtx x
)
5934 enum machine_mode mode
= GET_MODE (x
);
5935 rtx op0
= XEXP (x
, 0);
5936 rtx op1
= XEXP (x
, 1);
5938 switch (GET_CODE (x
))
5941 /* We can call simplify_and_const_int only if we don't lose
5942 any (sign) bits when converting INTVAL (op1) to
5943 "unsigned HOST_WIDE_INT". */
5944 if (CONST_INT_P (op1
)
5945 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5946 || INTVAL (op1
) > 0))
5948 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5949 if (GET_CODE (x
) != AND
)
5956 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5957 apply the distributive law and then the inverse distributive
5958 law to see if things simplify. */
5959 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5961 rtx result
= distribute_and_simplify_rtx (x
, 0);
5965 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5967 rtx result
= distribute_and_simplify_rtx (x
, 1);
5974 /* If we have (ior (and A B) C), apply the distributive law and then
5975 the inverse distributive law to see if things simplify. */
5977 if (GET_CODE (op0
) == AND
)
5979 rtx result
= distribute_and_simplify_rtx (x
, 0);
5984 if (GET_CODE (op1
) == AND
)
5986 rtx result
= distribute_and_simplify_rtx (x
, 1);
5999 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6000 operations" because they can be replaced with two more basic operations.
6001 ZERO_EXTEND is also considered "compound" because it can be replaced with
6002 an AND operation, which is simpler, though only one operation.
6004 The function expand_compound_operation is called with an rtx expression
6005 and will convert it to the appropriate shifts and AND operations,
6006 simplifying at each stage.
6008 The function make_compound_operation is called to convert an expression
6009 consisting of shifts and ANDs into the equivalent compound expression.
6010 It is the inverse of this function, loosely speaking. */
6013 expand_compound_operation (rtx x
)
6015 unsigned HOST_WIDE_INT pos
= 0, len
;
6017 unsigned int modewidth
;
6020 switch (GET_CODE (x
))
6025 /* We can't necessarily use a const_int for a multiword mode;
6026 it depends on implicitly extending the value.
6027 Since we don't know the right way to extend it,
6028 we can't tell whether the implicit way is right.
6030 Even for a mode that is no wider than a const_int,
6031 we can't win, because we need to sign extend one of its bits through
6032 the rest of it, and we don't know which bit. */
6033 if (CONST_INT_P (XEXP (x
, 0)))
6036 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6037 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6038 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6039 reloaded. If not for that, MEM's would very rarely be safe.
6041 Reject MODEs bigger than a word, because we might not be able
6042 to reference a two-register group starting with an arbitrary register
6043 (and currently gen_lowpart might crash for a SUBREG). */
6045 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6048 /* Reject MODEs that aren't scalar integers because turning vector
6049 or complex modes into shifts causes problems. */
6051 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6054 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
6055 /* If the inner object has VOIDmode (the only way this can happen
6056 is if it is an ASM_OPERANDS), we can't do anything since we don't
6057 know how much masking to do. */
6066 /* ... fall through ... */
6069 /* If the operand is a CLOBBER, just return it. */
6070 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6073 if (!CONST_INT_P (XEXP (x
, 1))
6074 || !CONST_INT_P (XEXP (x
, 2))
6075 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6078 /* Reject MODEs that aren't scalar integers because turning vector
6079 or complex modes into shifts causes problems. */
6081 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6084 len
= INTVAL (XEXP (x
, 1));
6085 pos
= INTVAL (XEXP (x
, 2));
6087 /* This should stay within the object being extracted, fail otherwise. */
6088 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
6091 if (BITS_BIG_ENDIAN
)
6092 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6099 /* Convert sign extension to zero extension, if we know that the high
6100 bit is not set, as this is easier to optimize. It will be converted
6101 back to cheaper alternative in make_extraction. */
6102 if (GET_CODE (x
) == SIGN_EXTEND
6103 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6104 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6105 & ~(((unsigned HOST_WIDE_INT
)
6106 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6110 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6111 rtx temp2
= expand_compound_operation (temp
);
6113 /* Make sure this is a profitable operation. */
6114 if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6115 > rtx_cost (temp2
, SET
, optimize_this_for_speed_p
))
6117 else if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6118 > rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
6124 /* We can optimize some special cases of ZERO_EXTEND. */
6125 if (GET_CODE (x
) == ZERO_EXTEND
)
6127 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6128 know that the last value didn't have any inappropriate bits
6130 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6131 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6132 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6133 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6134 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6135 return XEXP (XEXP (x
, 0), 0);
6137 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6138 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6139 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6140 && subreg_lowpart_p (XEXP (x
, 0))
6141 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6142 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6143 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6144 return SUBREG_REG (XEXP (x
, 0));
6146 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6147 is a comparison and STORE_FLAG_VALUE permits. This is like
6148 the first case, but it works even when GET_MODE (x) is larger
6149 than HOST_WIDE_INT. */
6150 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6151 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6152 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6153 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6154 <= HOST_BITS_PER_WIDE_INT
)
6155 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6156 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6157 return XEXP (XEXP (x
, 0), 0);
6159 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6160 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6161 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6162 && subreg_lowpart_p (XEXP (x
, 0))
6163 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6164 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6165 <= HOST_BITS_PER_WIDE_INT
)
6166 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6167 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6168 return SUBREG_REG (XEXP (x
, 0));
6172 /* If we reach here, we want to return a pair of shifts. The inner
6173 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6174 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6175 logical depending on the value of UNSIGNEDP.
6177 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6178 converted into an AND of a shift.
6180 We must check for the case where the left shift would have a negative
6181 count. This can happen in a case like (x >> 31) & 255 on machines
6182 that can't shift by a constant. On those machines, we would first
6183 combine the shift with the AND to produce a variable-position
6184 extraction. Then the constant of 31 would be substituted in to produce
6185 a such a position. */
6187 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
6188 if (modewidth
+ len
>= pos
)
6190 enum machine_mode mode
= GET_MODE (x
);
6191 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6192 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6194 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6195 tem
, modewidth
- pos
- len
);
6196 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6197 mode
, tem
, modewidth
- len
);
6199 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6200 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6201 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6204 ((HOST_WIDE_INT
) 1 << len
) - 1);
6206 /* Any other cases we can't handle. */
6209 /* If we couldn't do this for some reason, return the original
6211 if (GET_CODE (tem
) == CLOBBER
)
6217 /* X is a SET which contains an assignment of one object into
6218 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6219 or certain SUBREGS). If possible, convert it into a series of
6222 We half-heartedly support variable positions, but do not at all
6223 support variable lengths. */
6226 expand_field_assignment (const_rtx x
)
6229 rtx pos
; /* Always counts from low bit. */
6231 rtx mask
, cleared
, masked
;
6232 enum machine_mode compute_mode
;
6234 /* Loop until we find something we can't simplify. */
6237 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6238 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6240 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6241 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6242 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6244 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6245 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6247 inner
= XEXP (SET_DEST (x
), 0);
6248 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6249 pos
= XEXP (SET_DEST (x
), 2);
6251 /* A constant position should stay within the width of INNER. */
6252 if (CONST_INT_P (pos
)
6253 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6256 if (BITS_BIG_ENDIAN
)
6258 if (CONST_INT_P (pos
))
6259 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6261 else if (GET_CODE (pos
) == MINUS
6262 && CONST_INT_P (XEXP (pos
, 1))
6263 && (INTVAL (XEXP (pos
, 1))
6264 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6265 /* If position is ADJUST - X, new position is X. */
6266 pos
= XEXP (pos
, 0);
6268 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6269 GEN_INT (GET_MODE_BITSIZE (
6276 /* A SUBREG between two modes that occupy the same numbers of words
6277 can be done by moving the SUBREG to the source. */
6278 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6279 /* We need SUBREGs to compute nonzero_bits properly. */
6280 && nonzero_sign_valid
6281 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6282 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6283 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6284 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6286 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6288 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6295 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6296 inner
= SUBREG_REG (inner
);
6298 compute_mode
= GET_MODE (inner
);
6300 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6301 if (! SCALAR_INT_MODE_P (compute_mode
))
6303 enum machine_mode imode
;
6305 /* Don't do anything for vector or complex integral types. */
6306 if (! FLOAT_MODE_P (compute_mode
))
6309 /* Try to find an integral mode to pun with. */
6310 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6311 if (imode
== BLKmode
)
6314 compute_mode
= imode
;
6315 inner
= gen_lowpart (imode
, inner
);
6318 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6319 if (len
>= HOST_BITS_PER_WIDE_INT
)
6322 /* Now compute the equivalent expression. Make a copy of INNER
6323 for the SET_DEST in case it is a MEM into which we will substitute;
6324 we don't want shared RTL in that case. */
6325 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6326 cleared
= simplify_gen_binary (AND
, compute_mode
,
6327 simplify_gen_unary (NOT
, compute_mode
,
6328 simplify_gen_binary (ASHIFT
,
6333 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6334 simplify_gen_binary (
6336 gen_lowpart (compute_mode
, SET_SRC (x
)),
6340 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6341 simplify_gen_binary (IOR
, compute_mode
,
6348 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6349 it is an RTX that represents a variable starting position; otherwise,
6350 POS is the (constant) starting bit position (counted from the LSB).
6352 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6355 IN_DEST is nonzero if this is a reference in the destination of a
6356 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6357 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6360 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6361 ZERO_EXTRACT should be built even for bits starting at bit 0.
6363 MODE is the desired mode of the result (if IN_DEST == 0).
6365 The result is an RTX for the extraction or NULL_RTX if the target
6369 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6370 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6371 int in_dest
, int in_compare
)
6373 /* This mode describes the size of the storage area
6374 to fetch the overall value from. Within that, we
6375 ignore the POS lowest bits, etc. */
6376 enum machine_mode is_mode
= GET_MODE (inner
);
6377 enum machine_mode inner_mode
;
6378 enum machine_mode wanted_inner_mode
;
6379 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6380 enum machine_mode pos_mode
= word_mode
;
6381 enum machine_mode extraction_mode
= word_mode
;
6382 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6384 rtx orig_pos_rtx
= pos_rtx
;
6385 HOST_WIDE_INT orig_pos
;
6387 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6389 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6390 consider just the QI as the memory to extract from.
6391 The subreg adds or removes high bits; its mode is
6392 irrelevant to the meaning of this extraction,
6393 since POS and LEN count from the lsb. */
6394 if (MEM_P (SUBREG_REG (inner
)))
6395 is_mode
= GET_MODE (SUBREG_REG (inner
));
6396 inner
= SUBREG_REG (inner
);
6398 else if (GET_CODE (inner
) == ASHIFT
6399 && CONST_INT_P (XEXP (inner
, 1))
6400 && pos_rtx
== 0 && pos
== 0
6401 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6403 /* We're extracting the least significant bits of an rtx
6404 (ashift X (const_int C)), where LEN > C. Extract the
6405 least significant (LEN - C) bits of X, giving an rtx
6406 whose mode is MODE, then shift it left C times. */
6407 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
6408 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6409 unsignedp
, in_dest
, in_compare
);
6411 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
6414 inner_mode
= GET_MODE (inner
);
6416 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
6417 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6419 /* See if this can be done without an extraction. We never can if the
6420 width of the field is not the same as that of some integer mode. For
6421 registers, we can only avoid the extraction if the position is at the
6422 low-order bit and this is either not in the destination or we have the
6423 appropriate STRICT_LOW_PART operation available.
6425 For MEM, we can avoid an extract if the field starts on an appropriate
6426 boundary and we can change the mode of the memory reference. */
6428 if (tmode
!= BLKmode
6429 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6431 && (inner_mode
== tmode
6433 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
6434 GET_MODE_BITSIZE (inner_mode
))
6435 || reg_truncated_to_mode (tmode
, inner
))
6438 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6439 || (MEM_P (inner
) && pos_rtx
== 0
6441 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6442 : BITS_PER_UNIT
)) == 0
6443 /* We can't do this if we are widening INNER_MODE (it
6444 may not be aligned, for one thing). */
6445 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6446 && (inner_mode
== tmode
6447 || (! mode_dependent_address_p (XEXP (inner
, 0))
6448 && ! MEM_VOLATILE_P (inner
))))))
6450 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6451 field. If the original and current mode are the same, we need not
6452 adjust the offset. Otherwise, we do if bytes big endian.
6454 If INNER is not a MEM, get a piece consisting of just the field
6455 of interest (in this case POS % BITS_PER_WORD must be 0). */
6459 HOST_WIDE_INT offset
;
6461 /* POS counts from lsb, but make OFFSET count in memory order. */
6462 if (BYTES_BIG_ENDIAN
)
6463 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6465 offset
= pos
/ BITS_PER_UNIT
;
6467 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
6469 else if (REG_P (inner
))
6471 if (tmode
!= inner_mode
)
6473 /* We can't call gen_lowpart in a DEST since we
6474 always want a SUBREG (see below) and it would sometimes
6475 return a new hard register. */
6478 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6480 if (WORDS_BIG_ENDIAN
6481 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6482 final_word
= ((GET_MODE_SIZE (inner_mode
)
6483 - GET_MODE_SIZE (tmode
))
6484 / UNITS_PER_WORD
) - final_word
;
6486 final_word
*= UNITS_PER_WORD
;
6487 if (BYTES_BIG_ENDIAN
&&
6488 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6489 final_word
+= (GET_MODE_SIZE (inner_mode
)
6490 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6492 /* Avoid creating invalid subregs, for example when
6493 simplifying (x>>32)&255. */
6494 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
6497 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
6500 new_rtx
= gen_lowpart (tmode
, inner
);
6506 new_rtx
= force_to_mode (inner
, tmode
,
6507 len
>= HOST_BITS_PER_WIDE_INT
6508 ? ~(unsigned HOST_WIDE_INT
) 0
6509 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6512 /* If this extraction is going into the destination of a SET,
6513 make a STRICT_LOW_PART unless we made a MEM. */
6516 return (MEM_P (new_rtx
) ? new_rtx
6517 : (GET_CODE (new_rtx
) != SUBREG
6518 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6519 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
6524 if (CONST_INT_P (new_rtx
))
6525 return gen_int_mode (INTVAL (new_rtx
), mode
);
6527 /* If we know that no extraneous bits are set, and that the high
6528 bit is not set, convert the extraction to the cheaper of
6529 sign and zero extension, that are equivalent in these cases. */
6530 if (flag_expensive_optimizations
6531 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6532 && ((nonzero_bits (new_rtx
, tmode
)
6533 & ~(((unsigned HOST_WIDE_INT
)
6534 GET_MODE_MASK (tmode
))
6538 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
6539 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
6541 /* Prefer ZERO_EXTENSION, since it gives more information to
6543 if (rtx_cost (temp
, SET
, optimize_this_for_speed_p
)
6544 <= rtx_cost (temp1
, SET
, optimize_this_for_speed_p
))
6549 /* Otherwise, sign- or zero-extend unless we already are in the
6552 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6556 /* Unless this is a COMPARE or we have a funny memory reference,
6557 don't do anything with zero-extending field extracts starting at
6558 the low-order bit since they are simple AND operations. */
6559 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6560 && ! in_compare
&& unsignedp
)
6563 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6564 if the position is not a constant and the length is not 1. In all
6565 other cases, we would only be going outside our object in cases when
6566 an original shift would have been undefined. */
6568 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6569 || (pos_rtx
!= 0 && len
!= 1)))
6572 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6573 and the mode for the result. */
6574 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6576 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6577 pos_mode
= mode_for_extraction (EP_insv
, 2);
6578 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6581 if (! in_dest
&& unsignedp
6582 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6584 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6585 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6586 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6589 if (! in_dest
&& ! unsignedp
6590 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6592 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6593 pos_mode
= mode_for_extraction (EP_extv
, 3);
6594 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6597 /* Never narrow an object, since that might not be safe. */
6599 if (mode
!= VOIDmode
6600 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6601 extraction_mode
= mode
;
6603 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6604 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6605 pos_mode
= GET_MODE (pos_rtx
);
6607 /* If this is not from memory, the desired mode is the preferred mode
6608 for an extraction pattern's first input operand, or word_mode if there
6611 wanted_inner_mode
= wanted_inner_reg_mode
;
6614 /* Be careful not to go beyond the extracted object and maintain the
6615 natural alignment of the memory. */
6616 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
6617 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
6618 > GET_MODE_BITSIZE (wanted_inner_mode
))
6620 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
6621 gcc_assert (wanted_inner_mode
!= VOIDmode
);
6624 /* If we have to change the mode of memory and cannot, the desired mode
6625 is EXTRACTION_MODE. */
6626 if (inner_mode
!= wanted_inner_mode
6627 && (mode_dependent_address_p (XEXP (inner
, 0))
6628 || MEM_VOLATILE_P (inner
)
6630 wanted_inner_mode
= extraction_mode
;
6635 if (BITS_BIG_ENDIAN
)
6637 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6638 BITS_BIG_ENDIAN style. If position is constant, compute new
6639 position. Otherwise, build subtraction.
6640 Note that POS is relative to the mode of the original argument.
6641 If it's a MEM we need to recompute POS relative to that.
6642 However, if we're extracting from (or inserting into) a register,
6643 we want to recompute POS relative to wanted_inner_mode. */
6644 int width
= (MEM_P (inner
)
6645 ? GET_MODE_BITSIZE (is_mode
)
6646 : GET_MODE_BITSIZE (wanted_inner_mode
));
6649 pos
= width
- len
- pos
;
6652 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6653 /* POS may be less than 0 now, but we check for that below.
6654 Note that it can only be less than 0 if !MEM_P (inner). */
6657 /* If INNER has a wider mode, and this is a constant extraction, try to
6658 make it smaller and adjust the byte to point to the byte containing
6660 if (wanted_inner_mode
!= VOIDmode
6661 && inner_mode
!= wanted_inner_mode
6663 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6665 && ! mode_dependent_address_p (XEXP (inner
, 0))
6666 && ! MEM_VOLATILE_P (inner
))
6670 /* The computations below will be correct if the machine is big
6671 endian in both bits and bytes or little endian in bits and bytes.
6672 If it is mixed, we must adjust. */
6674 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6675 adjust OFFSET to compensate. */
6676 if (BYTES_BIG_ENDIAN
6677 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6678 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6680 /* We can now move to the desired byte. */
6681 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
6682 * GET_MODE_SIZE (wanted_inner_mode
);
6683 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6685 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6686 && is_mode
!= wanted_inner_mode
)
6687 offset
= (GET_MODE_SIZE (is_mode
)
6688 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6690 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6693 /* If INNER is not memory, get it into the proper mode. If we are changing
6694 its mode, POS must be a constant and smaller than the size of the new
6696 else if (!MEM_P (inner
))
6698 /* On the LHS, don't create paradoxical subregs implicitely truncating
6699 the register unless TRULY_NOOP_TRUNCATION. */
6701 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner
)),
6702 GET_MODE_BITSIZE (wanted_inner_mode
)))
6705 if (GET_MODE (inner
) != wanted_inner_mode
6707 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6713 inner
= force_to_mode (inner
, wanted_inner_mode
,
6715 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6716 ? ~(unsigned HOST_WIDE_INT
) 0
6717 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6722 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6723 have to zero extend. Otherwise, we can just use a SUBREG. */
6725 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6727 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6729 /* If we know that no extraneous bits are set, and that the high
6730 bit is not set, convert extraction to cheaper one - either
6731 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6733 if (flag_expensive_optimizations
6734 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6735 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6736 & ~(((unsigned HOST_WIDE_INT
)
6737 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6741 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6743 /* Prefer ZERO_EXTENSION, since it gives more information to
6745 if (rtx_cost (temp1
, SET
, optimize_this_for_speed_p
)
6746 < rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
6751 else if (pos_rtx
!= 0
6752 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6753 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6755 /* Make POS_RTX unless we already have it and it is correct. If we don't
6756 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6758 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6759 pos_rtx
= orig_pos_rtx
;
6761 else if (pos_rtx
== 0)
6762 pos_rtx
= GEN_INT (pos
);
6764 /* Make the required operation. See if we can use existing rtx. */
6765 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6766 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6768 new_rtx
= gen_lowpart (mode
, new_rtx
);
6773 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6774 with any other operations in X. Return X without that shift if so. */
6777 extract_left_shift (rtx x
, int count
)
6779 enum rtx_code code
= GET_CODE (x
);
6780 enum machine_mode mode
= GET_MODE (x
);
6786 /* This is the shift itself. If it is wide enough, we will return
6787 either the value being shifted if the shift count is equal to
6788 COUNT or a shift for the difference. */
6789 if (CONST_INT_P (XEXP (x
, 1))
6790 && INTVAL (XEXP (x
, 1)) >= count
)
6791 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6792 INTVAL (XEXP (x
, 1)) - count
);
6796 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6797 return simplify_gen_unary (code
, mode
, tem
, mode
);
6801 case PLUS
: case IOR
: case XOR
: case AND
:
6802 /* If we can safely shift this constant and we find the inner shift,
6803 make a new operation. */
6804 if (CONST_INT_P (XEXP (x
, 1))
6805 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6806 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6807 return simplify_gen_binary (code
, mode
, tem
,
6808 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6819 /* Look at the expression rooted at X. Look for expressions
6820 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6821 Form these expressions.
6823 Return the new rtx, usually just X.
6825 Also, for machines like the VAX that don't have logical shift insns,
6826 try to convert logical to arithmetic shift operations in cases where
6827 they are equivalent. This undoes the canonicalizations to logical
6828 shifts done elsewhere.
6830 We try, as much as possible, to re-use rtl expressions to save memory.
6832 IN_CODE says what kind of expression we are processing. Normally, it is
6833 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6834 being kludges), it is MEM. When processing the arguments of a comparison
6835 or a COMPARE against zero, it is COMPARE. */
6838 make_compound_operation (rtx x
, enum rtx_code in_code
)
6840 enum rtx_code code
= GET_CODE (x
);
6841 enum machine_mode mode
= GET_MODE (x
);
6842 int mode_width
= GET_MODE_BITSIZE (mode
);
6844 enum rtx_code next_code
;
6850 /* Select the code to be used in recursive calls. Once we are inside an
6851 address, we stay there. If we have a comparison, set to COMPARE,
6852 but once inside, go back to our default of SET. */
6854 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6855 : ((code
== COMPARE
|| COMPARISON_P (x
))
6856 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6857 : in_code
== COMPARE
? SET
: in_code
);
6859 /* Process depending on the code of this operation. If NEW is set
6860 nonzero, it will be returned. */
6865 /* Convert shifts by constants into multiplications if inside
6867 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
6868 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6869 && INTVAL (XEXP (x
, 1)) >= 0)
6871 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
6872 new_rtx
= gen_rtx_MULT (mode
, new_rtx
,
6873 GEN_INT ((HOST_WIDE_INT
) 1
6874 << INTVAL (XEXP (x
, 1))));
6879 /* If the second operand is not a constant, we can't do anything
6881 if (!CONST_INT_P (XEXP (x
, 1)))
6884 /* If the constant is a power of two minus one and the first operand
6885 is a logical right shift, make an extraction. */
6886 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6887 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6889 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6890 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6891 0, in_code
== COMPARE
);
6894 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6895 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6896 && subreg_lowpart_p (XEXP (x
, 0))
6897 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6898 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6900 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6902 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
6903 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6904 0, in_code
== COMPARE
);
6906 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6907 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6908 || GET_CODE (XEXP (x
, 0)) == IOR
)
6909 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6910 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6911 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6913 /* Apply the distributive law, and then try to make extractions. */
6914 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6915 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6917 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6919 new_rtx
= make_compound_operation (new_rtx
, in_code
);
6922 /* If we are have (and (rotate X C) M) and C is larger than the number
6923 of bits in M, this is an extraction. */
6925 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6926 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
6927 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6928 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6930 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6931 new_rtx
= make_extraction (mode
, new_rtx
,
6932 (GET_MODE_BITSIZE (mode
)
6933 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6934 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6937 /* On machines without logical shifts, if the operand of the AND is
6938 a logical shift and our mask turns off all the propagated sign
6939 bits, we can replace the logical shift with an arithmetic shift. */
6940 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6941 && !have_insn_for (LSHIFTRT
, mode
)
6942 && have_insn_for (ASHIFTRT
, mode
)
6943 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
6944 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6945 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6946 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6948 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6950 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6951 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6953 gen_rtx_ASHIFTRT (mode
,
6954 make_compound_operation
6955 (XEXP (XEXP (x
, 0), 0), next_code
),
6956 XEXP (XEXP (x
, 0), 1)));
6959 /* If the constant is one less than a power of two, this might be
6960 representable by an extraction even if no shift is present.
6961 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6962 we are in a COMPARE. */
6963 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6964 new_rtx
= make_extraction (mode
,
6965 make_compound_operation (XEXP (x
, 0),
6967 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6969 /* If we are in a comparison and this is an AND with a power of two,
6970 convert this into the appropriate bit extract. */
6971 else if (in_code
== COMPARE
6972 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6973 new_rtx
= make_extraction (mode
,
6974 make_compound_operation (XEXP (x
, 0),
6976 i
, NULL_RTX
, 1, 1, 0, 1);
6981 /* If the sign bit is known to be zero, replace this with an
6982 arithmetic shift. */
6983 if (have_insn_for (ASHIFTRT
, mode
)
6984 && ! have_insn_for (LSHIFTRT
, mode
)
6985 && mode_width
<= HOST_BITS_PER_WIDE_INT
6986 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6988 new_rtx
= gen_rtx_ASHIFTRT (mode
,
6989 make_compound_operation (XEXP (x
, 0),
6995 /* ... fall through ... */
7001 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7002 this is a SIGN_EXTRACT. */
7003 if (CONST_INT_P (rhs
)
7004 && GET_CODE (lhs
) == ASHIFT
7005 && CONST_INT_P (XEXP (lhs
, 1))
7006 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7007 && INTVAL (rhs
) < mode_width
)
7009 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7010 new_rtx
= make_extraction (mode
, new_rtx
,
7011 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7012 NULL_RTX
, mode_width
- INTVAL (rhs
),
7013 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7017 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7018 If so, try to merge the shifts into a SIGN_EXTEND. We could
7019 also do this for some cases of SIGN_EXTRACT, but it doesn't
7020 seem worth the effort; the case checked for occurs on Alpha. */
7023 && ! (GET_CODE (lhs
) == SUBREG
7024 && (OBJECT_P (SUBREG_REG (lhs
))))
7025 && CONST_INT_P (rhs
)
7026 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7027 && INTVAL (rhs
) < mode_width
7028 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7029 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7030 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7031 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7036 /* Call ourselves recursively on the inner expression. If we are
7037 narrowing the object and it has a different RTL code from
7038 what it originally did, do this SUBREG as a force_to_mode. */
7040 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
7044 simplified
= simplify_subreg (GET_MODE (x
), tem
, GET_MODE (tem
),
7050 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
7051 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
7052 && subreg_lowpart_p (x
))
7054 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
7057 /* If we have something other than a SUBREG, we might have
7058 done an expansion, so rerun ourselves. */
7059 if (GET_CODE (newer
) != SUBREG
)
7060 newer
= make_compound_operation (newer
, in_code
);
7062 /* force_to_mode can expand compounds. If it just re-expanded the
7063 compound use gen_lowpart instead to convert to the desired
7065 if (rtx_equal_p (newer
, x
))
7066 return gen_lowpart (GET_MODE (x
), tem
);
7082 x
= gen_lowpart (mode
, new_rtx
);
7083 code
= GET_CODE (x
);
7086 /* Now recursively process each operand of this operation. */
7087 fmt
= GET_RTX_FORMAT (code
);
7088 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7091 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7092 SUBST (XEXP (x
, i
), new_rtx
);
7094 else if (fmt
[i
] == 'E')
7095 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7097 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7098 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7101 /* If this is a commutative operation, the changes to the operands
7102 may have made it noncanonical. */
7103 if (COMMUTATIVE_ARITH_P (x
)
7104 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7107 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7108 SUBST (XEXP (x
, 1), tem
);
7114 /* Given M see if it is a value that would select a field of bits
7115 within an item, but not the entire word. Return -1 if not.
7116 Otherwise, return the starting position of the field, where 0 is the
7119 *PLEN is set to the length of the field. */
7122 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7124 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7125 int pos
= exact_log2 (m
& -m
);
7129 /* Now shift off the low-order zero bits and see if we have a
7130 power of two minus 1. */
7131 len
= exact_log2 ((m
>> pos
) + 1);
7140 /* If X refers to a register that equals REG in value, replace these
7141 references with REG. */
7143 canon_reg_for_combine (rtx x
, rtx reg
)
7150 enum rtx_code code
= GET_CODE (x
);
7151 switch (GET_RTX_CLASS (code
))
7154 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7155 if (op0
!= XEXP (x
, 0))
7156 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7161 case RTX_COMM_ARITH
:
7162 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7163 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7164 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7165 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7169 case RTX_COMM_COMPARE
:
7170 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7171 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7172 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7173 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7174 GET_MODE (op0
), op0
, op1
);
7178 case RTX_BITFIELD_OPS
:
7179 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7180 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7181 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7182 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7183 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7184 GET_MODE (op0
), op0
, op1
, op2
);
7189 if (rtx_equal_p (get_last_value (reg
), x
)
7190 || rtx_equal_p (reg
, get_last_value (x
)))
7199 fmt
= GET_RTX_FORMAT (code
);
7201 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7204 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7205 if (op
!= XEXP (x
, i
))
7215 else if (fmt
[i
] == 'E')
7218 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7220 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7221 if (op
!= XVECEXP (x
, i
, j
))
7228 XVECEXP (x
, i
, j
) = op
;
7239 /* Return X converted to MODE. If the value is already truncated to
7240 MODE we can just return a subreg even though in the general case we
7241 would need an explicit truncation. */
7244 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7246 if (!CONST_INT_P (x
)
7247 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7248 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
7249 GET_MODE_BITSIZE (GET_MODE (x
)))
7250 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7252 /* Bit-cast X into an integer mode. */
7253 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7254 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7255 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7259 return gen_lowpart (mode
, x
);
7262 /* See if X can be simplified knowing that we will only refer to it in
7263 MODE and will only refer to those bits that are nonzero in MASK.
7264 If other bits are being computed or if masking operations are done
7265 that select a superset of the bits in MASK, they can sometimes be
7268 Return a possibly simplified expression, but always convert X to
7269 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7271 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7272 are all off in X. This is used when X will be complemented, by either
7273 NOT, NEG, or XOR. */
7276 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7279 enum rtx_code code
= GET_CODE (x
);
7280 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7281 enum machine_mode op_mode
;
7282 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7285 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7286 code below will do the wrong thing since the mode of such an
7287 expression is VOIDmode.
7289 Also do nothing if X is a CLOBBER; this can happen if X was
7290 the return value from a call to gen_lowpart. */
7291 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7294 /* We want to perform the operation is its present mode unless we know
7295 that the operation is valid in MODE, in which case we do the operation
7297 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
7298 && have_insn_for (code
, mode
))
7299 ? mode
: GET_MODE (x
));
7301 /* It is not valid to do a right-shift in a narrower mode
7302 than the one it came in with. */
7303 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
7304 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
7305 op_mode
= GET_MODE (x
);
7307 /* Truncate MASK to fit OP_MODE. */
7309 mask
&= GET_MODE_MASK (op_mode
);
7311 /* When we have an arithmetic operation, or a shift whose count we
7312 do not know, we need to assume that all bits up to the highest-order
7313 bit in MASK will be needed. This is how we form such a mask. */
7314 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
7315 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
7317 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
7320 /* Determine what bits of X are guaranteed to be (non)zero. */
7321 nonzero
= nonzero_bits (x
, mode
);
7323 /* If none of the bits in X are needed, return a zero. */
7324 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
7327 /* If X is a CONST_INT, return a new one. Do this here since the
7328 test below will fail. */
7329 if (CONST_INT_P (x
))
7331 if (SCALAR_INT_MODE_P (mode
))
7332 return gen_int_mode (INTVAL (x
) & mask
, mode
);
7335 x
= GEN_INT (INTVAL (x
) & mask
);
7336 return gen_lowpart_common (mode
, x
);
7340 /* If X is narrower than MODE and we want all the bits in X's mode, just
7341 get X in the proper mode. */
7342 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
7343 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
7344 return gen_lowpart (mode
, x
);
7346 /* We can ignore the effect of a SUBREG if it narrows the mode or
7347 if the constant masks to zero all the bits the mode doesn't have. */
7348 if (GET_CODE (x
) == SUBREG
7349 && subreg_lowpart_p (x
)
7350 && ((GET_MODE_SIZE (GET_MODE (x
))
7351 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7353 & GET_MODE_MASK (GET_MODE (x
))
7354 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
7355 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
7357 /* The arithmetic simplifications here only work for scalar integer modes. */
7358 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
7359 return gen_lowpart_or_truncate (mode
, x
);
7364 /* If X is a (clobber (const_int)), return it since we know we are
7365 generating something that won't match. */
7372 x
= expand_compound_operation (x
);
7373 if (GET_CODE (x
) != code
)
7374 return force_to_mode (x
, mode
, mask
, next_select
);
7378 /* Similarly for a truncate. */
7379 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7382 /* If this is an AND with a constant, convert it into an AND
7383 whose constant is the AND of that constant with MASK. If it
7384 remains an AND of MASK, delete it since it is redundant. */
7386 if (CONST_INT_P (XEXP (x
, 1)))
7388 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
7389 mask
& INTVAL (XEXP (x
, 1)));
7391 /* If X is still an AND, see if it is an AND with a mask that
7392 is just some low-order bits. If so, and it is MASK, we don't
7395 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
7396 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
7400 /* If it remains an AND, try making another AND with the bits
7401 in the mode mask that aren't in MASK turned on. If the
7402 constant in the AND is wide enough, this might make a
7403 cheaper constant. */
7405 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
7406 && GET_MODE_MASK (GET_MODE (x
)) != mask
7407 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
7409 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
7410 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
7411 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
7414 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7415 number, sign extend it. */
7416 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
7417 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7418 cval
|= (HOST_WIDE_INT
) -1 << width
;
7420 y
= simplify_gen_binary (AND
, GET_MODE (x
),
7421 XEXP (x
, 0), GEN_INT (cval
));
7422 if (rtx_cost (y
, SET
, optimize_this_for_speed_p
)
7423 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
7433 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7434 low-order bits (as in an alignment operation) and FOO is already
7435 aligned to that boundary, mask C1 to that boundary as well.
7436 This may eliminate that PLUS and, later, the AND. */
7439 unsigned int width
= GET_MODE_BITSIZE (mode
);
7440 unsigned HOST_WIDE_INT smask
= mask
;
7442 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7443 number, sign extend it. */
7445 if (width
< HOST_BITS_PER_WIDE_INT
7446 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7447 smask
|= (HOST_WIDE_INT
) -1 << width
;
7449 if (CONST_INT_P (XEXP (x
, 1))
7450 && exact_log2 (- smask
) >= 0
7451 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7452 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7453 return force_to_mode (plus_constant (XEXP (x
, 0),
7454 (INTVAL (XEXP (x
, 1)) & smask
)),
7455 mode
, smask
, next_select
);
7458 /* ... fall through ... */
7461 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7462 most significant bit in MASK since carries from those bits will
7463 affect the bits we are interested in. */
7468 /* If X is (minus C Y) where C's least set bit is larger than any bit
7469 in the mask, then we may replace with (neg Y). */
7470 if (CONST_INT_P (XEXP (x
, 0))
7471 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7472 & -INTVAL (XEXP (x
, 0))))
7475 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7477 return force_to_mode (x
, mode
, mask
, next_select
);
7480 /* Similarly, if C contains every bit in the fuller_mask, then we may
7481 replace with (not Y). */
7482 if (CONST_INT_P (XEXP (x
, 0))
7483 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7484 == INTVAL (XEXP (x
, 0))))
7486 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7487 XEXP (x
, 1), GET_MODE (x
));
7488 return force_to_mode (x
, mode
, mask
, next_select
);
7496 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7497 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7498 operation which may be a bitfield extraction. Ensure that the
7499 constant we form is not wider than the mode of X. */
7501 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7502 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7503 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7504 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7505 && CONST_INT_P (XEXP (x
, 1))
7506 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7507 + floor_log2 (INTVAL (XEXP (x
, 1))))
7508 < GET_MODE_BITSIZE (GET_MODE (x
)))
7509 && (INTVAL (XEXP (x
, 1))
7510 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7512 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7513 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7514 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
7515 XEXP (XEXP (x
, 0), 0), temp
);
7516 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7517 XEXP (XEXP (x
, 0), 1));
7518 return force_to_mode (x
, mode
, mask
, next_select
);
7522 /* For most binary operations, just propagate into the operation and
7523 change the mode if we have an operation of that mode. */
7525 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7526 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
7528 /* If we ended up truncating both operands, truncate the result of the
7529 operation instead. */
7530 if (GET_CODE (op0
) == TRUNCATE
7531 && GET_CODE (op1
) == TRUNCATE
)
7533 op0
= XEXP (op0
, 0);
7534 op1
= XEXP (op1
, 0);
7537 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
7538 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
7540 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7541 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
7545 /* For left shifts, do the same, but just for the first operand.
7546 However, we cannot do anything with shifts where we cannot
7547 guarantee that the counts are smaller than the size of the mode
7548 because such a count will have a different meaning in a
7551 if (! (CONST_INT_P (XEXP (x
, 1))
7552 && INTVAL (XEXP (x
, 1)) >= 0
7553 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7554 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7555 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7556 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7559 /* If the shift count is a constant and we can do arithmetic in
7560 the mode of the shift, refine which bits we need. Otherwise, use the
7561 conservative form of the mask. */
7562 if (CONST_INT_P (XEXP (x
, 1))
7563 && INTVAL (XEXP (x
, 1)) >= 0
7564 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7565 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7566 mask
>>= INTVAL (XEXP (x
, 1));
7570 op0
= gen_lowpart_or_truncate (op_mode
,
7571 force_to_mode (XEXP (x
, 0), op_mode
,
7572 mask
, next_select
));
7574 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7575 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7579 /* Here we can only do something if the shift count is a constant,
7580 this shift constant is valid for the host, and we can do arithmetic
7583 if (CONST_INT_P (XEXP (x
, 1))
7584 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7585 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7587 rtx inner
= XEXP (x
, 0);
7588 unsigned HOST_WIDE_INT inner_mask
;
7590 /* Select the mask of the bits we need for the shift operand. */
7591 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7593 /* We can only change the mode of the shift if we can do arithmetic
7594 in the mode of the shift and INNER_MASK is no wider than the
7595 width of X's mode. */
7596 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7597 op_mode
= GET_MODE (x
);
7599 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
7601 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7602 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7605 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7606 shift and AND produces only copies of the sign bit (C2 is one less
7607 than a power of two), we can do this with just a shift. */
7609 if (GET_CODE (x
) == LSHIFTRT
7610 && CONST_INT_P (XEXP (x
, 1))
7611 /* The shift puts one of the sign bit copies in the least significant
7613 && ((INTVAL (XEXP (x
, 1))
7614 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7615 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7616 && exact_log2 (mask
+ 1) >= 0
7617 /* Number of bits left after the shift must be more than the mask
7619 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7620 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7621 /* Must be more sign bit copies than the mask needs. */
7622 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7623 >= exact_log2 (mask
+ 1)))
7624 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7625 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7626 - exact_log2 (mask
+ 1)));
7631 /* If we are just looking for the sign bit, we don't need this shift at
7632 all, even if it has a variable count. */
7633 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7634 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7635 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7636 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7638 /* If this is a shift by a constant, get a mask that contains those bits
7639 that are not copies of the sign bit. We then have two cases: If
7640 MASK only includes those bits, this can be a logical shift, which may
7641 allow simplifications. If MASK is a single-bit field not within
7642 those bits, we are requesting a copy of the sign bit and hence can
7643 shift the sign bit to the appropriate location. */
7645 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
7646 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7650 /* If the considered data is wider than HOST_WIDE_INT, we can't
7651 represent a mask for all its bits in a single scalar.
7652 But we only care about the lower bits, so calculate these. */
7654 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7656 nonzero
= ~(HOST_WIDE_INT
) 0;
7658 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7659 is the number of bits a full-width mask would have set.
7660 We need only shift if these are fewer than nonzero can
7661 hold. If not, we must keep all bits set in nonzero. */
7663 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7664 < HOST_BITS_PER_WIDE_INT
)
7665 nonzero
>>= INTVAL (XEXP (x
, 1))
7666 + HOST_BITS_PER_WIDE_INT
7667 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7671 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7672 nonzero
>>= INTVAL (XEXP (x
, 1));
7675 if ((mask
& ~nonzero
) == 0)
7677 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
7678 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
7679 if (GET_CODE (x
) != ASHIFTRT
)
7680 return force_to_mode (x
, mode
, mask
, next_select
);
7683 else if ((i
= exact_log2 (mask
)) >= 0)
7685 x
= simplify_shift_const
7686 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7687 GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7689 if (GET_CODE (x
) != ASHIFTRT
)
7690 return force_to_mode (x
, mode
, mask
, next_select
);
7694 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7695 even if the shift count isn't a constant. */
7697 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7698 XEXP (x
, 0), XEXP (x
, 1));
7702 /* If this is a zero- or sign-extension operation that just affects bits
7703 we don't care about, remove it. Be sure the call above returned
7704 something that is still a shift. */
7706 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7707 && CONST_INT_P (XEXP (x
, 1))
7708 && INTVAL (XEXP (x
, 1)) >= 0
7709 && (INTVAL (XEXP (x
, 1))
7710 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7711 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7712 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7713 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7720 /* If the shift count is constant and we can do computations
7721 in the mode of X, compute where the bits we care about are.
7722 Otherwise, we can't do anything. Don't change the mode of
7723 the shift or propagate MODE into the shift, though. */
7724 if (CONST_INT_P (XEXP (x
, 1))
7725 && INTVAL (XEXP (x
, 1)) >= 0)
7727 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7728 GET_MODE (x
), GEN_INT (mask
),
7730 if (temp
&& CONST_INT_P (temp
))
7732 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7733 INTVAL (temp
), next_select
));
7738 /* If we just want the low-order bit, the NEG isn't needed since it
7739 won't change the low-order bit. */
7741 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
7743 /* We need any bits less significant than the most significant bit in
7744 MASK since carries from those bits will affect the bits we are
7750 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7751 same as the XOR case above. Ensure that the constant we form is not
7752 wider than the mode of X. */
7754 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7755 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7756 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7757 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7758 < GET_MODE_BITSIZE (GET_MODE (x
)))
7759 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7761 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7763 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
7764 XEXP (XEXP (x
, 0), 0), temp
);
7765 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7766 temp
, XEXP (XEXP (x
, 0), 1));
7768 return force_to_mode (x
, mode
, mask
, next_select
);
7771 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7772 use the full mask inside the NOT. */
7776 op0
= gen_lowpart_or_truncate (op_mode
,
7777 force_to_mode (XEXP (x
, 0), mode
, mask
,
7779 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7780 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7784 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7785 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7786 which is equal to STORE_FLAG_VALUE. */
7787 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7788 && GET_MODE (XEXP (x
, 0)) == mode
7789 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7790 && (nonzero_bits (XEXP (x
, 0), mode
)
7791 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7792 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7797 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7798 written in a narrower mode. We play it safe and do not do so. */
7801 gen_lowpart_or_truncate (GET_MODE (x
),
7802 force_to_mode (XEXP (x
, 1), mode
,
7803 mask
, next_select
)));
7805 gen_lowpart_or_truncate (GET_MODE (x
),
7806 force_to_mode (XEXP (x
, 2), mode
,
7807 mask
, next_select
)));
7814 /* Ensure we return a value of the proper mode. */
7815 return gen_lowpart_or_truncate (mode
, x
);
7818 /* Return nonzero if X is an expression that has one of two values depending on
7819 whether some other value is zero or nonzero. In that case, we return the
7820 value that is being tested, *PTRUE is set to the value if the rtx being
7821 returned has a nonzero value, and *PFALSE is set to the other alternative.
7823 If we return zero, we set *PTRUE and *PFALSE to X. */
7826 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7828 enum machine_mode mode
= GET_MODE (x
);
7829 enum rtx_code code
= GET_CODE (x
);
7830 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7831 unsigned HOST_WIDE_INT nz
;
7833 /* If we are comparing a value against zero, we are done. */
7834 if ((code
== NE
|| code
== EQ
)
7835 && XEXP (x
, 1) == const0_rtx
)
7837 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7838 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7842 /* If this is a unary operation whose operand has one of two values, apply
7843 our opcode to compute those values. */
7844 else if (UNARY_P (x
)
7845 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7847 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7848 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7849 GET_MODE (XEXP (x
, 0)));
7853 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7854 make can't possibly match and would suppress other optimizations. */
7855 else if (code
== COMPARE
)
7858 /* If this is a binary operation, see if either side has only one of two
7859 values. If either one does or if both do and they are conditional on
7860 the same value, compute the new true and false values. */
7861 else if (BINARY_P (x
))
7863 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7864 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7866 if ((cond0
!= 0 || cond1
!= 0)
7867 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7869 /* If if_then_else_cond returned zero, then true/false are the
7870 same rtl. We must copy one of them to prevent invalid rtl
7873 true0
= copy_rtx (true0
);
7874 else if (cond1
== 0)
7875 true1
= copy_rtx (true1
);
7877 if (COMPARISON_P (x
))
7879 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
7881 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
7886 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
7887 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
7890 return cond0
? cond0
: cond1
;
7893 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7894 operands is zero when the other is nonzero, and vice-versa,
7895 and STORE_FLAG_VALUE is 1 or -1. */
7897 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7898 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7900 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7902 rtx op0
= XEXP (XEXP (x
, 0), 1);
7903 rtx op1
= XEXP (XEXP (x
, 1), 1);
7905 cond0
= XEXP (XEXP (x
, 0), 0);
7906 cond1
= XEXP (XEXP (x
, 1), 0);
7908 if (COMPARISON_P (cond0
)
7909 && COMPARISON_P (cond1
)
7910 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7911 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7912 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7913 || ((swap_condition (GET_CODE (cond0
))
7914 == reversed_comparison_code (cond1
, NULL
))
7915 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7916 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7917 && ! side_effects_p (x
))
7919 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7920 *pfalse
= simplify_gen_binary (MULT
, mode
,
7922 ? simplify_gen_unary (NEG
, mode
,
7930 /* Similarly for MULT, AND and UMIN, except that for these the result
7932 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7933 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7934 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7936 cond0
= XEXP (XEXP (x
, 0), 0);
7937 cond1
= XEXP (XEXP (x
, 1), 0);
7939 if (COMPARISON_P (cond0
)
7940 && COMPARISON_P (cond1
)
7941 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7942 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7943 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7944 || ((swap_condition (GET_CODE (cond0
))
7945 == reversed_comparison_code (cond1
, NULL
))
7946 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7947 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7948 && ! side_effects_p (x
))
7950 *ptrue
= *pfalse
= const0_rtx
;
7956 else if (code
== IF_THEN_ELSE
)
7958 /* If we have IF_THEN_ELSE already, extract the condition and
7959 canonicalize it if it is NE or EQ. */
7960 cond0
= XEXP (x
, 0);
7961 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7962 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7963 return XEXP (cond0
, 0);
7964 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7966 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7967 return XEXP (cond0
, 0);
7973 /* If X is a SUBREG, we can narrow both the true and false values
7974 if the inner expression, if there is a condition. */
7975 else if (code
== SUBREG
7976 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7979 true0
= simplify_gen_subreg (mode
, true0
,
7980 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7981 false0
= simplify_gen_subreg (mode
, false0
,
7982 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7983 if (true0
&& false0
)
7991 /* If X is a constant, this isn't special and will cause confusions
7992 if we treat it as such. Likewise if it is equivalent to a constant. */
7993 else if (CONSTANT_P (x
)
7994 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7997 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7998 will be least confusing to the rest of the compiler. */
7999 else if (mode
== BImode
)
8001 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8005 /* If X is known to be either 0 or -1, those are the true and
8006 false values when testing X. */
8007 else if (x
== constm1_rtx
|| x
== const0_rtx
8008 || (mode
!= VOIDmode
8009 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
8011 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8015 /* Likewise for 0 or a single bit. */
8016 else if (SCALAR_INT_MODE_P (mode
)
8017 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8018 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8020 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8024 /* Otherwise fail; show no condition with true and false values the same. */
8025 *ptrue
= *pfalse
= x
;
8029 /* Return the value of expression X given the fact that condition COND
8030 is known to be true when applied to REG as its first operand and VAL
8031 as its second. X is known to not be shared and so can be modified in
8034 We only handle the simplest cases, and specifically those cases that
8035 arise with IF_THEN_ELSE expressions. */
8038 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8040 enum rtx_code code
= GET_CODE (x
);
8045 if (side_effects_p (x
))
8048 /* If either operand of the condition is a floating point value,
8049 then we have to avoid collapsing an EQ comparison. */
8051 && rtx_equal_p (x
, reg
)
8052 && ! FLOAT_MODE_P (GET_MODE (x
))
8053 && ! FLOAT_MODE_P (GET_MODE (val
)))
8056 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8059 /* If X is (abs REG) and we know something about REG's relationship
8060 with zero, we may be able to simplify this. */
8062 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8065 case GE
: case GT
: case EQ
:
8068 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8070 GET_MODE (XEXP (x
, 0)));
8075 /* The only other cases we handle are MIN, MAX, and comparisons if the
8076 operands are the same as REG and VAL. */
8078 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8080 if (rtx_equal_p (XEXP (x
, 0), val
))
8081 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8083 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8085 if (COMPARISON_P (x
))
8087 if (comparison_dominates_p (cond
, code
))
8088 return const_true_rtx
;
8090 code
= reversed_comparison_code (x
, NULL
);
8092 && comparison_dominates_p (cond
, code
))
8097 else if (code
== SMAX
|| code
== SMIN
8098 || code
== UMIN
|| code
== UMAX
)
8100 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8102 /* Do not reverse the condition when it is NE or EQ.
8103 This is because we cannot conclude anything about
8104 the value of 'SMAX (x, y)' when x is not equal to y,
8105 but we can when x equals y. */
8106 if ((code
== SMAX
|| code
== UMAX
)
8107 && ! (cond
== EQ
|| cond
== NE
))
8108 cond
= reverse_condition (cond
);
8113 return unsignedp
? x
: XEXP (x
, 1);
8115 return unsignedp
? x
: XEXP (x
, 0);
8117 return unsignedp
? XEXP (x
, 1) : x
;
8119 return unsignedp
? XEXP (x
, 0) : x
;
8126 else if (code
== SUBREG
)
8128 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8129 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8131 if (SUBREG_REG (x
) != r
)
8133 /* We must simplify subreg here, before we lose track of the
8134 original inner_mode. */
8135 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8136 inner_mode
, SUBREG_BYTE (x
));
8140 SUBST (SUBREG_REG (x
), r
);
8145 /* We don't have to handle SIGN_EXTEND here, because even in the
8146 case of replacing something with a modeless CONST_INT, a
8147 CONST_INT is already (supposed to be) a valid sign extension for
8148 its narrower mode, which implies it's already properly
8149 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8150 story is different. */
8151 else if (code
== ZERO_EXTEND
)
8153 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8154 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8156 if (XEXP (x
, 0) != r
)
8158 /* We must simplify the zero_extend here, before we lose
8159 track of the original inner_mode. */
8160 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8165 SUBST (XEXP (x
, 0), r
);
8171 fmt
= GET_RTX_FORMAT (code
);
8172 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8175 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8176 else if (fmt
[i
] == 'E')
8177 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8178 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8185 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8186 assignment as a field assignment. */
8189 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8191 if (x
== y
|| rtx_equal_p (x
, y
))
8194 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8197 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8198 Note that all SUBREGs of MEM are paradoxical; otherwise they
8199 would have been rewritten. */
8200 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8201 && MEM_P (SUBREG_REG (y
))
8202 && rtx_equal_p (SUBREG_REG (y
),
8203 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8206 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8207 && MEM_P (SUBREG_REG (x
))
8208 && rtx_equal_p (SUBREG_REG (x
),
8209 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8212 /* We used to see if get_last_value of X and Y were the same but that's
8213 not correct. In one direction, we'll cause the assignment to have
8214 the wrong destination and in the case, we'll import a register into this
8215 insn that might have already have been dead. So fail if none of the
8216 above cases are true. */
8220 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8221 Return that assignment if so.
8223 We only handle the most common cases. */
8226 make_field_assignment (rtx x
)
8228 rtx dest
= SET_DEST (x
);
8229 rtx src
= SET_SRC (x
);
8234 unsigned HOST_WIDE_INT len
;
8236 enum machine_mode mode
;
8238 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8239 a clear of a one-bit field. We will have changed it to
8240 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8243 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8244 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8245 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8246 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8248 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8251 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8255 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8256 && subreg_lowpart_p (XEXP (src
, 0))
8257 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8258 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8259 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8260 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8261 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8262 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8264 assign
= make_extraction (VOIDmode
, dest
, 0,
8265 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8268 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8272 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8274 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8275 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8276 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8278 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8281 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8285 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8286 SRC is an AND with all bits of that field set, then we can discard
8288 if (GET_CODE (dest
) == ZERO_EXTRACT
8289 && CONST_INT_P (XEXP (dest
, 1))
8290 && GET_CODE (src
) == AND
8291 && CONST_INT_P (XEXP (src
, 1)))
8293 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
8294 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
8295 unsigned HOST_WIDE_INT ze_mask
;
8297 if (width
>= HOST_BITS_PER_WIDE_INT
)
8300 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
8302 /* Complete overlap. We can remove the source AND. */
8303 if ((and_mask
& ze_mask
) == ze_mask
)
8304 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
8306 /* Partial overlap. We can reduce the source AND. */
8307 if ((and_mask
& ze_mask
) != and_mask
)
8309 mode
= GET_MODE (src
);
8310 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
8311 gen_int_mode (and_mask
& ze_mask
, mode
));
8312 return gen_rtx_SET (VOIDmode
, dest
, src
);
8316 /* The other case we handle is assignments into a constant-position
8317 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8318 a mask that has all one bits except for a group of zero bits and
8319 OTHER is known to have zeros where C1 has ones, this is such an
8320 assignment. Compute the position and length from C1. Shift OTHER
8321 to the appropriate position, force it to the required mode, and
8322 make the extraction. Check for the AND in both operands. */
8324 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
8327 rhs
= expand_compound_operation (XEXP (src
, 0));
8328 lhs
= expand_compound_operation (XEXP (src
, 1));
8330 if (GET_CODE (rhs
) == AND
8331 && CONST_INT_P (XEXP (rhs
, 1))
8332 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
8333 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
8334 else if (GET_CODE (lhs
) == AND
8335 && CONST_INT_P (XEXP (lhs
, 1))
8336 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
8337 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
8341 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
8342 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
8343 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
8344 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
8347 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
8351 /* The mode to use for the source is the mode of the assignment, or of
8352 what is inside a possible STRICT_LOW_PART. */
8353 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
8354 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
8356 /* Shift OTHER right POS places and make it the source, restricting it
8357 to the proper length and mode. */
8359 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
8363 src
= force_to_mode (src
, mode
,
8364 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
8365 ? ~(unsigned HOST_WIDE_INT
) 0
8366 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
8369 /* If SRC is masked by an AND that does not make a difference in
8370 the value being stored, strip it. */
8371 if (GET_CODE (assign
) == ZERO_EXTRACT
8372 && CONST_INT_P (XEXP (assign
, 1))
8373 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
8374 && GET_CODE (src
) == AND
8375 && CONST_INT_P (XEXP (src
, 1))
8376 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
8377 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
8378 src
= XEXP (src
, 0);
8380 return gen_rtx_SET (VOIDmode
, assign
, src
);
8383 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8387 apply_distributive_law (rtx x
)
8389 enum rtx_code code
= GET_CODE (x
);
8390 enum rtx_code inner_code
;
8391 rtx lhs
, rhs
, other
;
8394 /* Distributivity is not true for floating point as it can change the
8395 value. So we don't do it unless -funsafe-math-optimizations. */
8396 if (FLOAT_MODE_P (GET_MODE (x
))
8397 && ! flag_unsafe_math_optimizations
)
8400 /* The outer operation can only be one of the following: */
8401 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
8402 && code
!= PLUS
&& code
!= MINUS
)
8408 /* If either operand is a primitive we can't do anything, so get out
8410 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
8413 lhs
= expand_compound_operation (lhs
);
8414 rhs
= expand_compound_operation (rhs
);
8415 inner_code
= GET_CODE (lhs
);
8416 if (inner_code
!= GET_CODE (rhs
))
8419 /* See if the inner and outer operations distribute. */
8426 /* These all distribute except over PLUS. */
8427 if (code
== PLUS
|| code
== MINUS
)
8432 if (code
!= PLUS
&& code
!= MINUS
)
8437 /* This is also a multiply, so it distributes over everything. */
8441 /* Non-paradoxical SUBREGs distributes over all operations,
8442 provided the inner modes and byte offsets are the same, this
8443 is an extraction of a low-order part, we don't convert an fp
8444 operation to int or vice versa, this is not a vector mode,
8445 and we would not be converting a single-word operation into a
8446 multi-word operation. The latter test is not required, but
8447 it prevents generating unneeded multi-word operations. Some
8448 of the previous tests are redundant given the latter test,
8449 but are retained because they are required for correctness.
8451 We produce the result slightly differently in this case. */
8453 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
8454 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
8455 || ! subreg_lowpart_p (lhs
)
8456 || (GET_MODE_CLASS (GET_MODE (lhs
))
8457 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
8458 || (GET_MODE_SIZE (GET_MODE (lhs
))
8459 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
8460 || VECTOR_MODE_P (GET_MODE (lhs
))
8461 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
8462 /* Result might need to be truncated. Don't change mode if
8463 explicit truncation is needed. */
8464 || !TRULY_NOOP_TRUNCATION
8465 (GET_MODE_BITSIZE (GET_MODE (x
)),
8466 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs
)))))
8469 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
8470 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
8471 return gen_lowpart (GET_MODE (x
), tem
);
8477 /* Set LHS and RHS to the inner operands (A and B in the example
8478 above) and set OTHER to the common operand (C in the example).
8479 There is only one way to do this unless the inner operation is
8481 if (COMMUTATIVE_ARITH_P (lhs
)
8482 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8483 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8484 else if (COMMUTATIVE_ARITH_P (lhs
)
8485 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8486 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8487 else if (COMMUTATIVE_ARITH_P (lhs
)
8488 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8489 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8490 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8491 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8495 /* Form the new inner operation, seeing if it simplifies first. */
8496 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8498 /* There is one exception to the general way of distributing:
8499 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8500 if (code
== XOR
&& inner_code
== IOR
)
8503 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8506 /* We may be able to continuing distributing the result, so call
8507 ourselves recursively on the inner operation before forming the
8508 outer operation, which we return. */
8509 return simplify_gen_binary (inner_code
, GET_MODE (x
),
8510 apply_distributive_law (tem
), other
);
8513 /* See if X is of the form (* (+ A B) C), and if so convert to
8514 (+ (* A C) (* B C)) and try to simplify.
8516 Most of the time, this results in no change. However, if some of
8517 the operands are the same or inverses of each other, simplifications
8520 For example, (and (ior A B) (not B)) can occur as the result of
8521 expanding a bit field assignment. When we apply the distributive
8522 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8523 which then simplifies to (and (A (not B))).
8525 Note that no checks happen on the validity of applying the inverse
8526 distributive law. This is pointless since we can do it in the
8527 few places where this routine is called.
8529 N is the index of the term that is decomposed (the arithmetic operation,
8530 i.e. (+ A B) in the first example above). !N is the index of the term that
8531 is distributed, i.e. of C in the first example above. */
8533 distribute_and_simplify_rtx (rtx x
, int n
)
8535 enum machine_mode mode
;
8536 enum rtx_code outer_code
, inner_code
;
8537 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
8539 decomposed
= XEXP (x
, n
);
8540 if (!ARITHMETIC_P (decomposed
))
8543 mode
= GET_MODE (x
);
8544 outer_code
= GET_CODE (x
);
8545 distributed
= XEXP (x
, !n
);
8547 inner_code
= GET_CODE (decomposed
);
8548 inner_op0
= XEXP (decomposed
, 0);
8549 inner_op1
= XEXP (decomposed
, 1);
8551 /* Special case (and (xor B C) (not A)), which is equivalent to
8552 (xor (ior A B) (ior A C)) */
8553 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
8555 distributed
= XEXP (distributed
, 0);
8561 /* Distribute the second term. */
8562 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
8563 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
8567 /* Distribute the first term. */
8568 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
8569 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
8572 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
8574 if (GET_CODE (tmp
) != outer_code
8575 && rtx_cost (tmp
, SET
, optimize_this_for_speed_p
)
8576 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
8582 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8583 in MODE. Return an equivalent form, if different from (and VAROP
8584 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8587 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
8588 unsigned HOST_WIDE_INT constop
)
8590 unsigned HOST_WIDE_INT nonzero
;
8591 unsigned HOST_WIDE_INT orig_constop
;
8596 orig_constop
= constop
;
8597 if (GET_CODE (varop
) == CLOBBER
)
8600 /* Simplify VAROP knowing that we will be only looking at some of the
8603 Note by passing in CONSTOP, we guarantee that the bits not set in
8604 CONSTOP are not significant and will never be examined. We must
8605 ensure that is the case by explicitly masking out those bits
8606 before returning. */
8607 varop
= force_to_mode (varop
, mode
, constop
, 0);
8609 /* If VAROP is a CLOBBER, we will fail so return it. */
8610 if (GET_CODE (varop
) == CLOBBER
)
8613 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8614 to VAROP and return the new constant. */
8615 if (CONST_INT_P (varop
))
8616 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
8618 /* See what bits may be nonzero in VAROP. Unlike the general case of
8619 a call to nonzero_bits, here we don't care about bits outside
8622 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8624 /* Turn off all bits in the constant that are known to already be zero.
8625 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8626 which is tested below. */
8630 /* If we don't have any bits left, return zero. */
8634 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8635 a power of two, we can replace this with an ASHIFT. */
8636 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8637 && (i
= exact_log2 (constop
)) >= 0)
8638 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8640 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8641 or XOR, then try to apply the distributive law. This may eliminate
8642 operations if either branch can be simplified because of the AND.
8643 It may also make some cases more complex, but those cases probably
8644 won't match a pattern either with or without this. */
8646 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8650 apply_distributive_law
8651 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8652 simplify_and_const_int (NULL_RTX
,
8656 simplify_and_const_int (NULL_RTX
,
8661 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8662 the AND and see if one of the operands simplifies to zero. If so, we
8663 may eliminate it. */
8665 if (GET_CODE (varop
) == PLUS
8666 && exact_log2 (constop
+ 1) >= 0)
8670 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8671 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8672 if (o0
== const0_rtx
)
8674 if (o1
== const0_rtx
)
8678 /* Make a SUBREG if necessary. If we can't make it, fail. */
8679 varop
= gen_lowpart (mode
, varop
);
8680 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
8683 /* If we are only masking insignificant bits, return VAROP. */
8684 if (constop
== nonzero
)
8687 if (varop
== orig_varop
&& constop
== orig_constop
)
8690 /* Otherwise, return an AND. */
8691 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
8695 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8698 Return an equivalent form, if different from X. Otherwise, return X. If
8699 X is zero, we are to always construct the equivalent form. */
8702 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8703 unsigned HOST_WIDE_INT constop
)
8705 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
8710 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
8711 gen_int_mode (constop
, mode
));
8712 if (GET_MODE (x
) != mode
)
8713 x
= gen_lowpart (mode
, x
);
8717 /* Given a REG, X, compute which bits in X can be nonzero.
8718 We don't care about bits outside of those defined in MODE.
8720 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8721 a shift, AND, or zero_extract, we can do better. */
8724 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
8725 const_rtx known_x ATTRIBUTE_UNUSED
,
8726 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8727 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8728 unsigned HOST_WIDE_INT
*nonzero
)
8733 /* If X is a register whose nonzero bits value is current, use it.
8734 Otherwise, if X is a register whose value we can find, use that
8735 value. Otherwise, use the previously-computed global nonzero bits
8736 for this register. */
8738 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
8739 if (rsp
->last_set_value
!= 0
8740 && (rsp
->last_set_mode
== mode
8741 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
8742 && GET_MODE_CLASS (mode
) == MODE_INT
))
8743 && ((rsp
->last_set_label
>= label_tick_ebb_start
8744 && rsp
->last_set_label
< label_tick
)
8745 || (rsp
->last_set_label
== label_tick
8746 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
8747 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8748 && REG_N_SETS (REGNO (x
)) == 1
8750 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
8752 *nonzero
&= rsp
->last_set_nonzero_bits
;
8756 tem
= get_last_value (x
);
8760 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8761 /* If X is narrower than MODE and TEM is a non-negative
8762 constant that would appear negative in the mode of X,
8763 sign-extend it for use in reg_nonzero_bits because some
8764 machines (maybe most) will actually do the sign-extension
8765 and this is the conservative approach.
8767 ??? For 2.5, try to tighten up the MD files in this regard
8768 instead of this kludge. */
8770 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8771 && CONST_INT_P (tem
)
8773 && 0 != (INTVAL (tem
)
8774 & ((HOST_WIDE_INT
) 1
8775 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8776 tem
= GEN_INT (INTVAL (tem
)
8777 | ((HOST_WIDE_INT
) (-1)
8778 << GET_MODE_BITSIZE (GET_MODE (x
))));
8782 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
8784 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
8786 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8787 /* We don't know anything about the upper bits. */
8788 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8795 /* Return the number of bits at the high-order end of X that are known to
8796 be equal to the sign bit. X will be used in mode MODE; if MODE is
8797 VOIDmode, X will be used in its own mode. The returned value will always
8798 be between 1 and the number of bits in MODE. */
8801 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
8802 const_rtx known_x ATTRIBUTE_UNUSED
,
8803 enum machine_mode known_mode
8805 unsigned int known_ret ATTRIBUTE_UNUSED
,
8806 unsigned int *result
)
8811 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
8812 if (rsp
->last_set_value
!= 0
8813 && rsp
->last_set_mode
== mode
8814 && ((rsp
->last_set_label
>= label_tick_ebb_start
8815 && rsp
->last_set_label
< label_tick
)
8816 || (rsp
->last_set_label
== label_tick
8817 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
8818 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8819 && REG_N_SETS (REGNO (x
)) == 1
8821 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
8823 *result
= rsp
->last_set_sign_bit_copies
;
8827 tem
= get_last_value (x
);
8831 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
8832 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8833 *result
= rsp
->sign_bit_copies
;
8838 /* Return the number of "extended" bits there are in X, when interpreted
8839 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8840 unsigned quantities, this is the number of high-order zero bits.
8841 For signed quantities, this is the number of copies of the sign bit
8842 minus 1. In both case, this function returns the number of "spare"
8843 bits. For example, if two quantities for which this function returns
8844 at least 1 are added, the addition is known not to overflow.
8846 This function will always return 0 unless called during combine, which
8847 implies that it must be called from a define_split. */
8850 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
8852 if (nonzero_sign_valid
== 0)
8856 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8857 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8858 - floor_log2 (nonzero_bits (x
, mode
)))
8860 : num_sign_bit_copies (x
, mode
) - 1);
8863 /* This function is called from `simplify_shift_const' to merge two
8864 outer operations. Specifically, we have already found that we need
8865 to perform operation *POP0 with constant *PCONST0 at the outermost
8866 position. We would now like to also perform OP1 with constant CONST1
8867 (with *POP0 being done last).
8869 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8870 the resulting operation. *PCOMP_P is set to 1 if we would need to
8871 complement the innermost operand, otherwise it is unchanged.
8873 MODE is the mode in which the operation will be done. No bits outside
8874 the width of this mode matter. It is assumed that the width of this mode
8875 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8877 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8878 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8879 result is simply *PCONST0.
8881 If the resulting operation cannot be expressed as one operation, we
8882 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8885 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8887 enum rtx_code op0
= *pop0
;
8888 HOST_WIDE_INT const0
= *pconst0
;
8890 const0
&= GET_MODE_MASK (mode
);
8891 const1
&= GET_MODE_MASK (mode
);
8893 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8897 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8900 if (op1
== UNKNOWN
|| op0
== SET
)
8903 else if (op0
== UNKNOWN
)
8904 op0
= op1
, const0
= const1
;
8906 else if (op0
== op1
)
8930 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8931 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8934 /* If the two constants aren't the same, we can't do anything. The
8935 remaining six cases can all be done. */
8936 else if (const0
!= const1
)
8944 /* (a & b) | b == b */
8946 else /* op1 == XOR */
8947 /* (a ^ b) | b == a | b */
8953 /* (a & b) ^ b == (~a) & b */
8954 op0
= AND
, *pcomp_p
= 1;
8955 else /* op1 == IOR */
8956 /* (a | b) ^ b == a & ~b */
8957 op0
= AND
, const0
= ~const0
;
8962 /* (a | b) & b == b */
8964 else /* op1 == XOR */
8965 /* (a ^ b) & b) == (~a) & b */
8972 /* Check for NO-OP cases. */
8973 const0
&= GET_MODE_MASK (mode
);
8975 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8977 else if (const0
== 0 && op0
== AND
)
8979 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8985 /* ??? Slightly redundant with the above mask, but not entirely.
8986 Moving this above means we'd have to sign-extend the mode mask
8987 for the final test. */
8988 if (op0
!= UNKNOWN
&& op0
!= NEG
)
8989 *pconst0
= trunc_int_for_mode (const0
, mode
);
8994 /* A helper to simplify_shift_const_1 to determine the mode we can perform
8995 the shift in. The original shift operation CODE is performed on OP in
8996 ORIG_MODE. Return the wider mode MODE if we can perform the operation
8997 in that mode. Return ORIG_MODE otherwise. We can also assume that the
8998 result of the shift is subject to operation OUTER_CODE with operand
9001 static enum machine_mode
9002 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9003 enum machine_mode orig_mode
, enum machine_mode mode
,
9004 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9006 if (orig_mode
== mode
)
9008 gcc_assert (GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (orig_mode
));
9010 /* In general we can't perform in wider mode for right shift and rotate. */
9014 /* We can still widen if the bits brought in from the left are identical
9015 to the sign bit of ORIG_MODE. */
9016 if (num_sign_bit_copies (op
, mode
)
9017 > (unsigned) (GET_MODE_BITSIZE (mode
)
9018 - GET_MODE_BITSIZE (orig_mode
)))
9023 /* Similarly here but with zero bits. */
9024 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9025 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9028 /* We can also widen if the bits brought in will be masked off. This
9029 operation is performed in ORIG_MODE. */
9030 if (outer_code
== AND
)
9032 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9035 && GET_MODE_BITSIZE (orig_mode
) - care_bits
>= count
)
9051 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9052 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9053 simplify it. Otherwise, return a simplified value.
9055 The shift is normally computed in the widest mode we find in VAROP, as
9056 long as it isn't a different number of words than RESULT_MODE. Exceptions
9057 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9060 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9061 rtx varop
, int orig_count
)
9063 enum rtx_code orig_code
= code
;
9064 rtx orig_varop
= varop
;
9066 enum machine_mode mode
= result_mode
;
9067 enum machine_mode shift_mode
, tmode
;
9068 unsigned int mode_words
9069 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9070 /* We form (outer_op (code varop count) (outer_const)). */
9071 enum rtx_code outer_op
= UNKNOWN
;
9072 HOST_WIDE_INT outer_const
= 0;
9073 int complement_p
= 0;
9076 /* Make sure and truncate the "natural" shift on the way in. We don't
9077 want to do this inside the loop as it makes it more difficult to
9079 if (SHIFT_COUNT_TRUNCATED
)
9080 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9082 /* If we were given an invalid count, don't do anything except exactly
9083 what was requested. */
9085 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9090 /* Unless one of the branches of the `if' in this loop does a `continue',
9091 we will `break' the loop after the `if'. */
9095 /* If we have an operand of (clobber (const_int 0)), fail. */
9096 if (GET_CODE (varop
) == CLOBBER
)
9099 /* Convert ROTATERT to ROTATE. */
9100 if (code
== ROTATERT
)
9102 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9104 if (VECTOR_MODE_P (result_mode
))
9105 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9107 count
= bitsize
- count
;
9110 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9111 mode
, outer_op
, outer_const
);
9113 /* Handle cases where the count is greater than the size of the mode
9114 minus 1. For ASHIFT, use the size minus one as the count (this can
9115 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9116 take the count modulo the size. For other shifts, the result is
9119 Since these shifts are being produced by the compiler by combining
9120 multiple operations, each of which are defined, we know what the
9121 result is supposed to be. */
9123 if (count
> (GET_MODE_BITSIZE (shift_mode
) - 1))
9125 if (code
== ASHIFTRT
)
9126 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9127 else if (code
== ROTATE
|| code
== ROTATERT
)
9128 count
%= GET_MODE_BITSIZE (shift_mode
);
9131 /* We can't simply return zero because there may be an
9139 /* If we discovered we had to complement VAROP, leave. Making a NOT
9140 here would cause an infinite loop. */
9144 /* An arithmetic right shift of a quantity known to be -1 or 0
9146 if (code
== ASHIFTRT
9147 && (num_sign_bit_copies (varop
, shift_mode
)
9148 == GET_MODE_BITSIZE (shift_mode
)))
9154 /* If we are doing an arithmetic right shift and discarding all but
9155 the sign bit copies, this is equivalent to doing a shift by the
9156 bitsize minus one. Convert it into that shift because it will often
9157 allow other simplifications. */
9159 if (code
== ASHIFTRT
9160 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9161 >= GET_MODE_BITSIZE (shift_mode
)))
9162 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9164 /* We simplify the tests below and elsewhere by converting
9165 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9166 `make_compound_operation' will convert it to an ASHIFTRT for
9167 those machines (such as VAX) that don't have an LSHIFTRT. */
9168 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9170 && ((nonzero_bits (varop
, shift_mode
)
9171 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9175 if (((code
== LSHIFTRT
9176 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9177 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9179 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9180 && !((nonzero_bits (varop
, shift_mode
) << count
)
9181 & GET_MODE_MASK (shift_mode
))))
9182 && !side_effects_p (varop
))
9185 switch (GET_CODE (varop
))
9191 new_rtx
= expand_compound_operation (varop
);
9192 if (new_rtx
!= varop
)
9200 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9201 minus the width of a smaller mode, we can do this with a
9202 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9203 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9204 && ! mode_dependent_address_p (XEXP (varop
, 0))
9205 && ! MEM_VOLATILE_P (varop
)
9206 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9207 MODE_INT
, 1)) != BLKmode
)
9209 new_rtx
= adjust_address_nv (varop
, tmode
,
9210 BYTES_BIG_ENDIAN
? 0
9211 : count
/ BITS_PER_UNIT
);
9213 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9214 : ZERO_EXTEND
, mode
, new_rtx
);
9221 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9222 the same number of words as what we've seen so far. Then store
9223 the widest mode in MODE. */
9224 if (subreg_lowpart_p (varop
)
9225 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9226 > GET_MODE_SIZE (GET_MODE (varop
)))
9227 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9228 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9231 varop
= SUBREG_REG (varop
);
9232 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9233 mode
= GET_MODE (varop
);
9239 /* Some machines use MULT instead of ASHIFT because MULT
9240 is cheaper. But it is still better on those machines to
9241 merge two shifts into one. */
9242 if (CONST_INT_P (XEXP (varop
, 1))
9243 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9246 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9248 GEN_INT (exact_log2 (
9249 INTVAL (XEXP (varop
, 1)))));
9255 /* Similar, for when divides are cheaper. */
9256 if (CONST_INT_P (XEXP (varop
, 1))
9257 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9260 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9262 GEN_INT (exact_log2 (
9263 INTVAL (XEXP (varop
, 1)))));
9269 /* If we are extracting just the sign bit of an arithmetic
9270 right shift, that shift is not needed. However, the sign
9271 bit of a wider mode may be different from what would be
9272 interpreted as the sign bit in a narrower mode, so, if
9273 the result is narrower, don't discard the shift. */
9274 if (code
== LSHIFTRT
9275 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9276 && (GET_MODE_BITSIZE (result_mode
)
9277 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9279 varop
= XEXP (varop
, 0);
9283 /* ... fall through ... */
9288 /* Here we have two nested shifts. The result is usually the
9289 AND of a new shift with a mask. We compute the result below. */
9290 if (CONST_INT_P (XEXP (varop
, 1))
9291 && INTVAL (XEXP (varop
, 1)) >= 0
9292 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9293 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9294 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9295 && !VECTOR_MODE_P (result_mode
))
9297 enum rtx_code first_code
= GET_CODE (varop
);
9298 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9299 unsigned HOST_WIDE_INT mask
;
9302 /* We have one common special case. We can't do any merging if
9303 the inner code is an ASHIFTRT of a smaller mode. However, if
9304 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9305 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9306 we can convert it to
9307 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9308 This simplifies certain SIGN_EXTEND operations. */
9309 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9310 && count
== (GET_MODE_BITSIZE (result_mode
)
9311 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9313 /* C3 has the low-order C1 bits zero. */
9315 mask
= (GET_MODE_MASK (mode
)
9316 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9318 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9319 XEXP (varop
, 0), mask
);
9320 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9322 count
= first_count
;
9327 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9328 than C1 high-order bits equal to the sign bit, we can convert
9329 this to either an ASHIFT or an ASHIFTRT depending on the
9332 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9334 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9335 && GET_MODE (varop
) == shift_mode
9336 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9339 varop
= XEXP (varop
, 0);
9340 count
-= first_count
;
9350 /* There are some cases we can't do. If CODE is ASHIFTRT,
9351 we can only do this if FIRST_CODE is also ASHIFTRT.
9353 We can't do the case when CODE is ROTATE and FIRST_CODE is
9356 If the mode of this shift is not the mode of the outer shift,
9357 we can't do this if either shift is a right shift or ROTATE.
9359 Finally, we can't do any of these if the mode is too wide
9360 unless the codes are the same.
9362 Handle the case where the shift codes are the same
9365 if (code
== first_code
)
9367 if (GET_MODE (varop
) != result_mode
9368 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9372 count
+= first_count
;
9373 varop
= XEXP (varop
, 0);
9377 if (code
== ASHIFTRT
9378 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9379 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9380 || (GET_MODE (varop
) != result_mode
9381 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9382 || first_code
== ROTATE
9383 || code
== ROTATE
)))
9386 /* To compute the mask to apply after the shift, shift the
9387 nonzero bits of the inner shift the same way the
9388 outer shift will. */
9390 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9393 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
9396 /* Give up if we can't compute an outer operation to use. */
9398 || !CONST_INT_P (mask_rtx
)
9399 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9401 result_mode
, &complement_p
))
9404 /* If the shifts are in the same direction, we add the
9405 counts. Otherwise, we subtract them. */
9406 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9407 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9408 count
+= first_count
;
9410 count
-= first_count
;
9412 /* If COUNT is positive, the new shift is usually CODE,
9413 except for the two exceptions below, in which case it is
9414 FIRST_CODE. If the count is negative, FIRST_CODE should
9417 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9418 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9421 code
= first_code
, count
= -count
;
9423 varop
= XEXP (varop
, 0);
9427 /* If we have (A << B << C) for any shift, we can convert this to
9428 (A << C << B). This wins if A is a constant. Only try this if
9429 B is not a constant. */
9431 else if (GET_CODE (varop
) == code
9432 && CONST_INT_P (XEXP (varop
, 0))
9433 && !CONST_INT_P (XEXP (varop
, 1)))
9435 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
9438 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
9445 if (VECTOR_MODE_P (mode
))
9448 /* Make this fit the case below. */
9449 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9450 GEN_INT (GET_MODE_MASK (mode
)));
9456 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9457 with C the size of VAROP - 1 and the shift is logical if
9458 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9459 we have an (le X 0) operation. If we have an arithmetic shift
9460 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9461 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9463 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9464 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9465 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9466 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9467 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9468 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9471 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9474 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9475 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9480 /* If we have (shift (logical)), move the logical to the outside
9481 to allow it to possibly combine with another logical and the
9482 shift to combine with another shift. This also canonicalizes to
9483 what a ZERO_EXTRACT looks like. Also, some machines have
9484 (and (shift)) insns. */
9486 if (CONST_INT_P (XEXP (varop
, 1))
9487 /* We can't do this if we have (ashiftrt (xor)) and the
9488 constant has its sign bit set in shift_mode. */
9489 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9490 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9492 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
9494 GEN_INT (count
))) != 0
9495 && CONST_INT_P (new_rtx
)
9496 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9497 INTVAL (new_rtx
), result_mode
, &complement_p
))
9499 varop
= XEXP (varop
, 0);
9503 /* If we can't do that, try to simplify the shift in each arm of the
9504 logical expression, make a new logical expression, and apply
9505 the inverse distributive law. This also can't be done
9506 for some (ashiftrt (xor)). */
9507 if (CONST_INT_P (XEXP (varop
, 1))
9508 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9509 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9512 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9513 XEXP (varop
, 0), count
);
9514 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9515 XEXP (varop
, 1), count
);
9517 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
9519 varop
= apply_distributive_law (varop
);
9527 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9528 says that the sign bit can be tested, FOO has mode MODE, C is
9529 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9530 that may be nonzero. */
9531 if (code
== LSHIFTRT
9532 && XEXP (varop
, 1) == const0_rtx
9533 && GET_MODE (XEXP (varop
, 0)) == result_mode
9534 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9535 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9536 && STORE_FLAG_VALUE
== -1
9537 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9538 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9539 (HOST_WIDE_INT
) 1, result_mode
,
9542 varop
= XEXP (varop
, 0);
9549 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9550 than the number of bits in the mode is equivalent to A. */
9551 if (code
== LSHIFTRT
9552 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9553 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9555 varop
= XEXP (varop
, 0);
9560 /* NEG commutes with ASHIFT since it is multiplication. Move the
9561 NEG outside to allow shifts to combine. */
9563 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9564 (HOST_WIDE_INT
) 0, result_mode
,
9567 varop
= XEXP (varop
, 0);
9573 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9574 is one less than the number of bits in the mode is
9575 equivalent to (xor A 1). */
9576 if (code
== LSHIFTRT
9577 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9578 && XEXP (varop
, 1) == constm1_rtx
9579 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9580 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9581 (HOST_WIDE_INT
) 1, result_mode
,
9585 varop
= XEXP (varop
, 0);
9589 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9590 that might be nonzero in BAR are those being shifted out and those
9591 bits are known zero in FOO, we can replace the PLUS with FOO.
9592 Similarly in the other operand order. This code occurs when
9593 we are computing the size of a variable-size array. */
9595 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9596 && count
< HOST_BITS_PER_WIDE_INT
9597 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9598 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9599 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9601 varop
= XEXP (varop
, 0);
9604 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9605 && count
< HOST_BITS_PER_WIDE_INT
9606 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9607 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9609 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9610 & nonzero_bits (XEXP (varop
, 1),
9613 varop
= XEXP (varop
, 1);
9617 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9619 && CONST_INT_P (XEXP (varop
, 1))
9620 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
9622 GEN_INT (count
))) != 0
9623 && CONST_INT_P (new_rtx
)
9624 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9625 INTVAL (new_rtx
), result_mode
, &complement_p
))
9627 varop
= XEXP (varop
, 0);
9631 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9632 signbit', and attempt to change the PLUS to an XOR and move it to
9633 the outer operation as is done above in the AND/IOR/XOR case
9634 leg for shift(logical). See details in logical handling above
9635 for reasoning in doing so. */
9636 if (code
== LSHIFTRT
9637 && CONST_INT_P (XEXP (varop
, 1))
9638 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9639 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
9641 GEN_INT (count
))) != 0
9642 && CONST_INT_P (new_rtx
)
9643 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9644 INTVAL (new_rtx
), result_mode
, &complement_p
))
9646 varop
= XEXP (varop
, 0);
9653 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9654 with C the size of VAROP - 1 and the shift is logical if
9655 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9656 we have a (gt X 0) operation. If the shift is arithmetic with
9657 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9658 we have a (neg (gt X 0)) operation. */
9660 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9661 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9662 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9663 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9664 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
9665 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9666 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9669 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9672 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9673 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9680 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9681 if the truncate does not affect the value. */
9682 if (code
== LSHIFTRT
9683 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9684 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
9685 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9686 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9687 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9689 rtx varop_inner
= XEXP (varop
, 0);
9692 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9693 XEXP (varop_inner
, 0),
9695 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9696 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9709 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
9710 outer_op
, outer_const
);
9712 /* We have now finished analyzing the shift. The result should be
9713 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9714 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9715 to the result of the shift. OUTER_CONST is the relevant constant,
9716 but we must turn off all bits turned off in the shift. */
9718 if (outer_op
== UNKNOWN
9719 && orig_code
== code
&& orig_count
== count
9720 && varop
== orig_varop
9721 && shift_mode
== GET_MODE (varop
))
9724 /* Make a SUBREG if necessary. If we can't make it, fail. */
9725 varop
= gen_lowpart (shift_mode
, varop
);
9726 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9729 /* If we have an outer operation and we just made a shift, it is
9730 possible that we could have simplified the shift were it not
9731 for the outer operation. So try to do the simplification
9734 if (outer_op
!= UNKNOWN
)
9735 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
9740 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
9742 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9743 turn off all the bits that the shift would have turned off. */
9744 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9745 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9746 GET_MODE_MASK (result_mode
) >> orig_count
);
9748 /* Do the remainder of the processing in RESULT_MODE. */
9749 x
= gen_lowpart_or_truncate (result_mode
, x
);
9751 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9754 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9756 if (outer_op
!= UNKNOWN
)
9758 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
9759 && GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9760 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9762 if (outer_op
== AND
)
9763 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9764 else if (outer_op
== SET
)
9766 /* This means that we have determined that the result is
9767 equivalent to a constant. This should be rare. */
9768 if (!side_effects_p (x
))
9769 x
= GEN_INT (outer_const
);
9771 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9772 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9774 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
9775 GEN_INT (outer_const
));
9781 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9782 The result of the shift is RESULT_MODE. If we cannot simplify it,
9783 return X or, if it is NULL, synthesize the expression with
9784 simplify_gen_binary. Otherwise, return a simplified value.
9786 The shift is normally computed in the widest mode we find in VAROP, as
9787 long as it isn't a different number of words than RESULT_MODE. Exceptions
9788 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9791 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
9792 rtx varop
, int count
)
9794 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
9799 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
9800 if (GET_MODE (x
) != result_mode
)
9801 x
= gen_lowpart (result_mode
, x
);
9806 /* Like recog, but we receive the address of a pointer to a new pattern.
9807 We try to match the rtx that the pointer points to.
9808 If that fails, we may try to modify or replace the pattern,
9809 storing the replacement into the same pointer object.
9811 Modifications include deletion or addition of CLOBBERs.
9813 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9814 the CLOBBERs are placed.
9816 The value is the final insn code from the pattern ultimately matched,
9820 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9823 int insn_code_number
;
9824 int num_clobbers_to_add
= 0;
9827 rtx old_notes
, old_pat
;
9829 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9830 we use to indicate that something didn't match. If we find such a
9831 thing, force rejection. */
9832 if (GET_CODE (pat
) == PARALLEL
)
9833 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9834 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9835 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9838 old_pat
= PATTERN (insn
);
9839 old_notes
= REG_NOTES (insn
);
9840 PATTERN (insn
) = pat
;
9841 REG_NOTES (insn
) = 0;
9843 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9844 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
9846 if (insn_code_number
< 0)
9847 fputs ("Failed to match this instruction:\n", dump_file
);
9849 fputs ("Successfully matched this instruction:\n", dump_file
);
9850 print_rtl_single (dump_file
, pat
);
9853 /* If it isn't, there is the possibility that we previously had an insn
9854 that clobbered some register as a side effect, but the combined
9855 insn doesn't need to do that. So try once more without the clobbers
9856 unless this represents an ASM insn. */
9858 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9859 && GET_CODE (pat
) == PARALLEL
)
9863 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9864 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9867 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9871 SUBST_INT (XVECLEN (pat
, 0), pos
);
9874 pat
= XVECEXP (pat
, 0, 0);
9876 PATTERN (insn
) = pat
;
9877 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9878 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
9880 if (insn_code_number
< 0)
9881 fputs ("Failed to match this instruction:\n", dump_file
);
9883 fputs ("Successfully matched this instruction:\n", dump_file
);
9884 print_rtl_single (dump_file
, pat
);
9887 PATTERN (insn
) = old_pat
;
9888 REG_NOTES (insn
) = old_notes
;
9890 /* Recognize all noop sets, these will be killed by followup pass. */
9891 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9892 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9894 /* If we had any clobbers to add, make a new pattern than contains
9895 them. Then check to make sure that all of them are dead. */
9896 if (num_clobbers_to_add
)
9898 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9899 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9901 + num_clobbers_to_add
)
9902 : num_clobbers_to_add
+ 1));
9904 if (GET_CODE (pat
) == PARALLEL
)
9905 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9906 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9908 XVECEXP (newpat
, 0, 0) = pat
;
9910 add_clobbers (newpat
, insn_code_number
);
9912 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9913 i
< XVECLEN (newpat
, 0); i
++)
9915 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9916 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9918 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
9920 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
9921 notes
= alloc_reg_note (REG_UNUSED
,
9922 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9931 return insn_code_number
;
9934 /* Like gen_lowpart_general but for use by combine. In combine it
9935 is not possible to create any new pseudoregs. However, it is
9936 safe to create invalid memory addresses, because combine will
9937 try to recognize them and all they will do is make the combine
9940 If for some reason this cannot do its job, an rtx
9941 (clobber (const_int 0)) is returned.
9942 An insn containing that will not be recognized. */
9945 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9947 enum machine_mode imode
= GET_MODE (x
);
9948 unsigned int osize
= GET_MODE_SIZE (omode
);
9949 unsigned int isize
= GET_MODE_SIZE (imode
);
9955 /* Return identity if this is a CONST or symbolic reference. */
9957 && (GET_CODE (x
) == CONST
9958 || GET_CODE (x
) == SYMBOL_REF
9959 || GET_CODE (x
) == LABEL_REF
))
9962 /* We can only support MODE being wider than a word if X is a
9963 constant integer or has a mode the same size. */
9964 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9965 && ! ((imode
== VOIDmode
9967 || GET_CODE (x
) == CONST_DOUBLE
))
9971 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9972 won't know what to do. So we will strip off the SUBREG here and
9973 process normally. */
9974 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9978 /* For use in case we fall down into the address adjustments
9979 further below, we need to adjust the known mode and size of
9980 x; imode and isize, since we just adjusted x. */
9981 imode
= GET_MODE (x
);
9986 isize
= GET_MODE_SIZE (imode
);
9989 result
= gen_lowpart_common (omode
, x
);
9998 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10000 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10003 /* If we want to refer to something bigger than the original memref,
10004 generate a paradoxical subreg instead. That will force a reload
10005 of the original memref X. */
10007 return gen_rtx_SUBREG (omode
, x
, 0);
10009 if (WORDS_BIG_ENDIAN
)
10010 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10012 /* Adjust the address so that the address-after-the-data is
10014 if (BYTES_BIG_ENDIAN
)
10015 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10017 return adjust_address_nv (x
, omode
, offset
);
10020 /* If X is a comparison operator, rewrite it in a new mode. This
10021 probably won't match, but may allow further simplifications. */
10022 else if (COMPARISON_P (x
))
10023 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10025 /* If we couldn't simplify X any other way, just enclose it in a
10026 SUBREG. Normally, this SUBREG won't match, but some patterns may
10027 include an explicit SUBREG or we may simplify it further in combine. */
10033 offset
= subreg_lowpart_offset (omode
, imode
);
10034 if (imode
== VOIDmode
)
10036 imode
= int_mode_for_mode (omode
);
10037 x
= gen_lowpart_common (imode
, x
);
10041 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10047 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10050 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10051 comparison code that will be tested.
10053 The result is a possibly different comparison code to use. *POP0 and
10054 *POP1 may be updated.
10056 It is possible that we might detect that a comparison is either always
10057 true or always false. However, we do not perform general constant
10058 folding in combine, so this knowledge isn't useful. Such tautologies
10059 should have been detected earlier. Hence we ignore all such cases. */
10061 static enum rtx_code
10062 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10068 enum machine_mode mode
, tmode
;
10070 /* Try a few ways of applying the same transformation to both operands. */
10073 #ifndef WORD_REGISTER_OPERATIONS
10074 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10075 so check specially. */
10076 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10077 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10078 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10079 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10080 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10081 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10082 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10083 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10084 && CONST_INT_P (XEXP (op0
, 1))
10085 && XEXP (op0
, 1) == XEXP (op1
, 1)
10086 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10087 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10088 && (INTVAL (XEXP (op0
, 1))
10089 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10090 - (GET_MODE_BITSIZE
10091 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10093 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10094 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10098 /* If both operands are the same constant shift, see if we can ignore the
10099 shift. We can if the shift is a rotate or if the bits shifted out of
10100 this shift are known to be zero for both inputs and if the type of
10101 comparison is compatible with the shift. */
10102 if (GET_CODE (op0
) == GET_CODE (op1
)
10103 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10104 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10105 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10106 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10107 || (GET_CODE (op0
) == ASHIFTRT
10108 && (code
!= GTU
&& code
!= LTU
10109 && code
!= GEU
&& code
!= LEU
)))
10110 && CONST_INT_P (XEXP (op0
, 1))
10111 && INTVAL (XEXP (op0
, 1)) >= 0
10112 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10113 && XEXP (op0
, 1) == XEXP (op1
, 1))
10115 enum machine_mode mode
= GET_MODE (op0
);
10116 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10117 int shift_count
= INTVAL (XEXP (op0
, 1));
10119 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10120 mask
&= (mask
>> shift_count
) << shift_count
;
10121 else if (GET_CODE (op0
) == ASHIFT
)
10122 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10124 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10125 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10126 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10131 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10132 SUBREGs are of the same mode, and, in both cases, the AND would
10133 be redundant if the comparison was done in the narrower mode,
10134 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10135 and the operand's possibly nonzero bits are 0xffffff01; in that case
10136 if we only care about QImode, we don't need the AND). This case
10137 occurs if the output mode of an scc insn is not SImode and
10138 STORE_FLAG_VALUE == 1 (e.g., the 386).
10140 Similarly, check for a case where the AND's are ZERO_EXTEND
10141 operations from some narrower mode even though a SUBREG is not
10144 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10145 && CONST_INT_P (XEXP (op0
, 1))
10146 && CONST_INT_P (XEXP (op1
, 1)))
10148 rtx inner_op0
= XEXP (op0
, 0);
10149 rtx inner_op1
= XEXP (op1
, 0);
10150 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10151 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10154 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10155 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10156 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10157 && (GET_MODE (SUBREG_REG (inner_op0
))
10158 == GET_MODE (SUBREG_REG (inner_op1
)))
10159 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10160 <= HOST_BITS_PER_WIDE_INT
)
10161 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10162 GET_MODE (SUBREG_REG (inner_op0
)))))
10163 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10164 GET_MODE (SUBREG_REG (inner_op1
))))))
10166 op0
= SUBREG_REG (inner_op0
);
10167 op1
= SUBREG_REG (inner_op1
);
10169 /* The resulting comparison is always unsigned since we masked
10170 off the original sign bit. */
10171 code
= unsigned_condition (code
);
10177 for (tmode
= GET_CLASS_NARROWEST_MODE
10178 (GET_MODE_CLASS (GET_MODE (op0
)));
10179 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10180 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10182 op0
= gen_lowpart (tmode
, inner_op0
);
10183 op1
= gen_lowpart (tmode
, inner_op1
);
10184 code
= unsigned_condition (code
);
10193 /* If both operands are NOT, we can strip off the outer operation
10194 and adjust the comparison code for swapped operands; similarly for
10195 NEG, except that this must be an equality comparison. */
10196 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10197 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10198 && (code
== EQ
|| code
== NE
)))
10199 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10205 /* If the first operand is a constant, swap the operands and adjust the
10206 comparison code appropriately, but don't do this if the second operand
10207 is already a constant integer. */
10208 if (swap_commutative_operands_p (op0
, op1
))
10210 tem
= op0
, op0
= op1
, op1
= tem
;
10211 code
= swap_condition (code
);
10214 /* We now enter a loop during which we will try to simplify the comparison.
10215 For the most part, we only are concerned with comparisons with zero,
10216 but some things may really be comparisons with zero but not start
10217 out looking that way. */
10219 while (CONST_INT_P (op1
))
10221 enum machine_mode mode
= GET_MODE (op0
);
10222 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10223 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10224 int equality_comparison_p
;
10225 int sign_bit_comparison_p
;
10226 int unsigned_comparison_p
;
10227 HOST_WIDE_INT const_op
;
10229 /* We only want to handle integral modes. This catches VOIDmode,
10230 CCmode, and the floating-point modes. An exception is that we
10231 can handle VOIDmode if OP0 is a COMPARE or a comparison
10234 if (GET_MODE_CLASS (mode
) != MODE_INT
10235 && ! (mode
== VOIDmode
10236 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10239 /* Get the constant we are comparing against and turn off all bits
10240 not on in our mode. */
10241 const_op
= INTVAL (op1
);
10242 if (mode
!= VOIDmode
)
10243 const_op
= trunc_int_for_mode (const_op
, mode
);
10244 op1
= GEN_INT (const_op
);
10246 /* If we are comparing against a constant power of two and the value
10247 being compared can only have that single bit nonzero (e.g., it was
10248 `and'ed with that bit), we can replace this with a comparison
10251 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10252 || code
== LT
|| code
== LTU
)
10253 && mode_width
<= HOST_BITS_PER_WIDE_INT
10254 && exact_log2 (const_op
) >= 0
10255 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10257 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10258 op1
= const0_rtx
, const_op
= 0;
10261 /* Similarly, if we are comparing a value known to be either -1 or
10262 0 with -1, change it to the opposite comparison against zero. */
10265 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10266 || code
== GEU
|| code
== LTU
)
10267 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10269 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10270 op1
= const0_rtx
, const_op
= 0;
10273 /* Do some canonicalizations based on the comparison code. We prefer
10274 comparisons against zero and then prefer equality comparisons.
10275 If we can reduce the size of a constant, we will do that too. */
10280 /* < C is equivalent to <= (C - 1) */
10284 op1
= GEN_INT (const_op
);
10286 /* ... fall through to LE case below. */
10292 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10296 op1
= GEN_INT (const_op
);
10300 /* If we are doing a <= 0 comparison on a value known to have
10301 a zero sign bit, we can replace this with == 0. */
10302 else if (const_op
== 0
10303 && mode_width
<= HOST_BITS_PER_WIDE_INT
10304 && (nonzero_bits (op0
, mode
)
10305 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10310 /* >= C is equivalent to > (C - 1). */
10314 op1
= GEN_INT (const_op
);
10316 /* ... fall through to GT below. */
10322 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10326 op1
= GEN_INT (const_op
);
10330 /* If we are doing a > 0 comparison on a value known to have
10331 a zero sign bit, we can replace this with != 0. */
10332 else if (const_op
== 0
10333 && mode_width
<= HOST_BITS_PER_WIDE_INT
10334 && (nonzero_bits (op0
, mode
)
10335 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10340 /* < C is equivalent to <= (C - 1). */
10344 op1
= GEN_INT (const_op
);
10346 /* ... fall through ... */
10349 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10350 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10351 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10353 const_op
= 0, op1
= const0_rtx
;
10361 /* unsigned <= 0 is equivalent to == 0 */
10365 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10366 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10367 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10369 const_op
= 0, op1
= const0_rtx
;
10375 /* >= C is equivalent to > (C - 1). */
10379 op1
= GEN_INT (const_op
);
10381 /* ... fall through ... */
10384 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10385 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10386 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10388 const_op
= 0, op1
= const0_rtx
;
10396 /* unsigned > 0 is equivalent to != 0 */
10400 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10401 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10402 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10404 const_op
= 0, op1
= const0_rtx
;
10413 /* Compute some predicates to simplify code below. */
10415 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10416 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10417 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10420 /* If this is a sign bit comparison and we can do arithmetic in
10421 MODE, say that we will only be needing the sign bit of OP0. */
10422 if (sign_bit_comparison_p
10423 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10424 op0
= force_to_mode (op0
, mode
,
10426 << (GET_MODE_BITSIZE (mode
) - 1)),
10429 /* Now try cases based on the opcode of OP0. If none of the cases
10430 does a "continue", we exit this loop immediately after the
10433 switch (GET_CODE (op0
))
10436 /* If we are extracting a single bit from a variable position in
10437 a constant that has only a single bit set and are comparing it
10438 with zero, we can convert this into an equality comparison
10439 between the position and the location of the single bit. */
10440 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10441 have already reduced the shift count modulo the word size. */
10442 if (!SHIFT_COUNT_TRUNCATED
10443 && CONST_INT_P (XEXP (op0
, 0))
10444 && XEXP (op0
, 1) == const1_rtx
10445 && equality_comparison_p
&& const_op
== 0
10446 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10448 if (BITS_BIG_ENDIAN
)
10450 enum machine_mode new_mode
10451 = mode_for_extraction (EP_extzv
, 1);
10452 if (new_mode
== MAX_MACHINE_MODE
)
10453 i
= BITS_PER_WORD
- 1 - i
;
10457 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10461 op0
= XEXP (op0
, 2);
10465 /* Result is nonzero iff shift count is equal to I. */
10466 code
= reverse_condition (code
);
10470 /* ... fall through ... */
10473 tem
= expand_compound_operation (op0
);
10482 /* If testing for equality, we can take the NOT of the constant. */
10483 if (equality_comparison_p
10484 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10486 op0
= XEXP (op0
, 0);
10491 /* If just looking at the sign bit, reverse the sense of the
10493 if (sign_bit_comparison_p
)
10495 op0
= XEXP (op0
, 0);
10496 code
= (code
== GE
? LT
: GE
);
10502 /* If testing for equality, we can take the NEG of the constant. */
10503 if (equality_comparison_p
10504 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10506 op0
= XEXP (op0
, 0);
10511 /* The remaining cases only apply to comparisons with zero. */
10515 /* When X is ABS or is known positive,
10516 (neg X) is < 0 if and only if X != 0. */
10518 if (sign_bit_comparison_p
10519 && (GET_CODE (XEXP (op0
, 0)) == ABS
10520 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10521 && (nonzero_bits (XEXP (op0
, 0), mode
)
10522 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10524 op0
= XEXP (op0
, 0);
10525 code
= (code
== LT
? NE
: EQ
);
10529 /* If we have NEG of something whose two high-order bits are the
10530 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10531 if (num_sign_bit_copies (op0
, mode
) >= 2)
10533 op0
= XEXP (op0
, 0);
10534 code
= swap_condition (code
);
10540 /* If we are testing equality and our count is a constant, we
10541 can perform the inverse operation on our RHS. */
10542 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
10543 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10544 op1
, XEXP (op0
, 1))) != 0)
10546 op0
= XEXP (op0
, 0);
10551 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10552 a particular bit. Convert it to an AND of a constant of that
10553 bit. This will be converted into a ZERO_EXTRACT. */
10554 if (const_op
== 0 && sign_bit_comparison_p
10555 && CONST_INT_P (XEXP (op0
, 1))
10556 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10558 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10561 - INTVAL (XEXP (op0
, 1)))));
10562 code
= (code
== LT
? NE
: EQ
);
10566 /* Fall through. */
10569 /* ABS is ignorable inside an equality comparison with zero. */
10570 if (const_op
== 0 && equality_comparison_p
)
10572 op0
= XEXP (op0
, 0);
10578 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10579 (compare FOO CONST) if CONST fits in FOO's mode and we
10580 are either testing inequality or have an unsigned
10581 comparison with ZERO_EXTEND or a signed comparison with
10582 SIGN_EXTEND. But don't do it if we don't have a compare
10583 insn of the given mode, since we'd have to revert it
10584 later on, and then we wouldn't know whether to sign- or
10586 mode
= GET_MODE (XEXP (op0
, 0));
10587 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10588 && ! unsigned_comparison_p
10589 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10590 && ((unsigned HOST_WIDE_INT
) const_op
10591 < (((unsigned HOST_WIDE_INT
) 1
10592 << (GET_MODE_BITSIZE (mode
) - 1))))
10593 && have_insn_for (COMPARE
, mode
))
10595 op0
= XEXP (op0
, 0);
10601 /* Check for the case where we are comparing A - C1 with C2, that is
10603 (subreg:MODE (plus (A) (-C1))) op (C2)
10605 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10606 comparison in the wider mode. One of the following two conditions
10607 must be true in order for this to be valid:
10609 1. The mode extension results in the same bit pattern being added
10610 on both sides and the comparison is equality or unsigned. As
10611 C2 has been truncated to fit in MODE, the pattern can only be
10614 2. The mode extension results in the sign bit being copied on
10617 The difficulty here is that we have predicates for A but not for
10618 (A - C1) so we need to check that C1 is within proper bounds so
10619 as to perturbate A as little as possible. */
10621 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10622 && subreg_lowpart_p (op0
)
10623 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10624 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10625 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
10627 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10628 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10629 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10632 && (unsigned HOST_WIDE_INT
) c1
10633 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10634 && (equality_comparison_p
|| unsigned_comparison_p
)
10635 /* (A - C1) zero-extends if it is positive and sign-extends
10636 if it is negative, C2 both zero- and sign-extends. */
10637 && ((0 == (nonzero_bits (a
, inner_mode
)
10638 & ~GET_MODE_MASK (mode
))
10640 /* (A - C1) sign-extends if it is positive and 1-extends
10641 if it is negative, C2 both sign- and 1-extends. */
10642 || (num_sign_bit_copies (a
, inner_mode
)
10643 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10646 || ((unsigned HOST_WIDE_INT
) c1
10647 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10648 /* (A - C1) always sign-extends, like C2. */
10649 && num_sign_bit_copies (a
, inner_mode
)
10650 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10651 - (mode_width
- 1))))
10653 op0
= SUBREG_REG (op0
);
10658 /* If the inner mode is narrower and we are extracting the low part,
10659 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10660 if (subreg_lowpart_p (op0
)
10661 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10662 /* Fall through */ ;
10666 /* ... fall through ... */
10669 mode
= GET_MODE (XEXP (op0
, 0));
10670 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10671 && (unsigned_comparison_p
|| equality_comparison_p
)
10672 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10673 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
10674 && have_insn_for (COMPARE
, mode
))
10676 op0
= XEXP (op0
, 0);
10682 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10683 this for equality comparisons due to pathological cases involving
10685 if (equality_comparison_p
10686 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10687 op1
, XEXP (op0
, 1))))
10689 op0
= XEXP (op0
, 0);
10694 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10695 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10696 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10698 op0
= XEXP (XEXP (op0
, 0), 0);
10699 code
= (code
== LT
? EQ
: NE
);
10705 /* We used to optimize signed comparisons against zero, but that
10706 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10707 arrive here as equality comparisons, or (GEU, LTU) are
10708 optimized away. No need to special-case them. */
10710 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10711 (eq B (minus A C)), whichever simplifies. We can only do
10712 this for equality comparisons due to pathological cases involving
10714 if (equality_comparison_p
10715 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10716 XEXP (op0
, 1), op1
)))
10718 op0
= XEXP (op0
, 0);
10723 if (equality_comparison_p
10724 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10725 XEXP (op0
, 0), op1
)))
10727 op0
= XEXP (op0
, 1);
10732 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10733 of bits in X minus 1, is one iff X > 0. */
10734 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10735 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
10736 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10738 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10740 op0
= XEXP (op0
, 1);
10741 code
= (code
== GE
? LE
: GT
);
10747 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10748 if C is zero or B is a constant. */
10749 if (equality_comparison_p
10750 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10751 XEXP (op0
, 1), op1
)))
10753 op0
= XEXP (op0
, 0);
10760 case UNEQ
: case LTGT
:
10761 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10762 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10763 case UNORDERED
: case ORDERED
:
10764 /* We can't do anything if OP0 is a condition code value, rather
10765 than an actual data value. */
10767 || CC0_P (XEXP (op0
, 0))
10768 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10771 /* Get the two operands being compared. */
10772 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10773 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10775 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10777 /* Check for the cases where we simply want the result of the
10778 earlier test or the opposite of that result. */
10779 if (code
== NE
|| code
== EQ
10780 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10781 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10782 && (STORE_FLAG_VALUE
10783 & (((HOST_WIDE_INT
) 1
10784 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10785 && (code
== LT
|| code
== GE
)))
10787 enum rtx_code new_code
;
10788 if (code
== LT
|| code
== NE
)
10789 new_code
= GET_CODE (op0
);
10791 new_code
= reversed_comparison_code (op0
, NULL
);
10793 if (new_code
!= UNKNOWN
)
10804 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10806 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10807 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10808 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10810 op0
= XEXP (op0
, 1);
10811 code
= (code
== GE
? GT
: LE
);
10817 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10818 will be converted to a ZERO_EXTRACT later. */
10819 if (const_op
== 0 && equality_comparison_p
10820 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10821 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10823 op0
= simplify_and_const_int
10824 (NULL_RTX
, mode
, gen_rtx_LSHIFTRT (mode
,
10826 XEXP (XEXP (op0
, 0), 1)),
10827 (HOST_WIDE_INT
) 1);
10831 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10832 zero and X is a comparison and C1 and C2 describe only bits set
10833 in STORE_FLAG_VALUE, we can compare with X. */
10834 if (const_op
== 0 && equality_comparison_p
10835 && mode_width
<= HOST_BITS_PER_WIDE_INT
10836 && CONST_INT_P (XEXP (op0
, 1))
10837 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10838 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
10839 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10840 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10842 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10843 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10844 if ((~STORE_FLAG_VALUE
& mask
) == 0
10845 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10846 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10847 && COMPARISON_P (tem
))))
10849 op0
= XEXP (XEXP (op0
, 0), 0);
10854 /* If we are doing an equality comparison of an AND of a bit equal
10855 to the sign bit, replace this with a LT or GE comparison of
10856 the underlying value. */
10857 if (equality_comparison_p
10859 && CONST_INT_P (XEXP (op0
, 1))
10860 && mode_width
<= HOST_BITS_PER_WIDE_INT
10861 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10862 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10864 op0
= XEXP (op0
, 0);
10865 code
= (code
== EQ
? GE
: LT
);
10869 /* If this AND operation is really a ZERO_EXTEND from a narrower
10870 mode, the constant fits within that mode, and this is either an
10871 equality or unsigned comparison, try to do this comparison in
10876 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10877 -> (ne:DI (reg:SI 4) (const_int 0))
10879 unless TRULY_NOOP_TRUNCATION allows it or the register is
10880 known to hold a value of the required mode the
10881 transformation is invalid. */
10882 if ((equality_comparison_p
|| unsigned_comparison_p
)
10883 && CONST_INT_P (XEXP (op0
, 1))
10884 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10885 & GET_MODE_MASK (mode
))
10887 && const_op
>> i
== 0
10888 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
10889 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
10890 GET_MODE_BITSIZE (GET_MODE (op0
)))
10891 || (REG_P (XEXP (op0
, 0))
10892 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
10894 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10898 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10899 fits in both M1 and M2 and the SUBREG is either paradoxical
10900 or represents the low part, permute the SUBREG and the AND
10902 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10904 unsigned HOST_WIDE_INT c1
;
10905 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10906 /* Require an integral mode, to avoid creating something like
10908 if (SCALAR_INT_MODE_P (tmode
)
10909 /* It is unsafe to commute the AND into the SUBREG if the
10910 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10911 not defined. As originally written the upper bits
10912 have a defined value due to the AND operation.
10913 However, if we commute the AND inside the SUBREG then
10914 they no longer have defined values and the meaning of
10915 the code has been changed. */
10917 #ifdef WORD_REGISTER_OPERATIONS
10918 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10919 && mode_width
<= BITS_PER_WORD
)
10921 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10922 && subreg_lowpart_p (XEXP (op0
, 0))))
10923 && CONST_INT_P (XEXP (op0
, 1))
10924 && mode_width
<= HOST_BITS_PER_WIDE_INT
10925 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10926 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10927 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10929 && c1
!= GET_MODE_MASK (tmode
))
10931 op0
= simplify_gen_binary (AND
, tmode
,
10932 SUBREG_REG (XEXP (op0
, 0)),
10933 gen_int_mode (c1
, tmode
));
10934 op0
= gen_lowpart (mode
, op0
);
10939 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10940 if (const_op
== 0 && equality_comparison_p
10941 && XEXP (op0
, 1) == const1_rtx
10942 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10944 op0
= simplify_and_const_int
10945 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10946 code
= (code
== NE
? EQ
: NE
);
10950 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10951 (eq (and (lshiftrt X) 1) 0).
10952 Also handle the case where (not X) is expressed using xor. */
10953 if (const_op
== 0 && equality_comparison_p
10954 && XEXP (op0
, 1) == const1_rtx
10955 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10957 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10958 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10960 if (GET_CODE (shift_op
) == NOT
10961 || (GET_CODE (shift_op
) == XOR
10962 && CONST_INT_P (XEXP (shift_op
, 1))
10963 && CONST_INT_P (shift_count
)
10964 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10965 && (INTVAL (XEXP (shift_op
, 1))
10966 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10968 op0
= simplify_and_const_int
10970 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10971 (HOST_WIDE_INT
) 1);
10972 code
= (code
== NE
? EQ
: NE
);
10979 /* If we have (compare (ashift FOO N) (const_int C)) and
10980 the high order N bits of FOO (N+1 if an inequality comparison)
10981 are known to be zero, we can do this by comparing FOO with C
10982 shifted right N bits so long as the low-order N bits of C are
10984 if (CONST_INT_P (XEXP (op0
, 1))
10985 && INTVAL (XEXP (op0
, 1)) >= 0
10986 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10987 < HOST_BITS_PER_WIDE_INT
)
10989 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10990 && mode_width
<= HOST_BITS_PER_WIDE_INT
10991 && (nonzero_bits (XEXP (op0
, 0), mode
)
10992 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10993 + ! equality_comparison_p
))) == 0)
10995 /* We must perform a logical shift, not an arithmetic one,
10996 as we want the top N bits of C to be zero. */
10997 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10999 temp
>>= INTVAL (XEXP (op0
, 1));
11000 op1
= gen_int_mode (temp
, mode
);
11001 op0
= XEXP (op0
, 0);
11005 /* If we are doing a sign bit comparison, it means we are testing
11006 a particular bit. Convert it to the appropriate AND. */
11007 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11008 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11010 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11013 - INTVAL (XEXP (op0
, 1)))));
11014 code
= (code
== LT
? NE
: EQ
);
11018 /* If this an equality comparison with zero and we are shifting
11019 the low bit to the sign bit, we can convert this to an AND of the
11021 if (const_op
== 0 && equality_comparison_p
11022 && CONST_INT_P (XEXP (op0
, 1))
11023 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11026 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11027 (HOST_WIDE_INT
) 1);
11033 /* If this is an equality comparison with zero, we can do this
11034 as a logical shift, which might be much simpler. */
11035 if (equality_comparison_p
&& const_op
== 0
11036 && CONST_INT_P (XEXP (op0
, 1)))
11038 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11040 INTVAL (XEXP (op0
, 1)));
11044 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11045 do the comparison in a narrower mode. */
11046 if (! unsigned_comparison_p
11047 && CONST_INT_P (XEXP (op0
, 1))
11048 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11049 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11050 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11051 MODE_INT
, 1)) != BLKmode
11052 && (((unsigned HOST_WIDE_INT
) const_op
11053 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11054 <= GET_MODE_MASK (tmode
)))
11056 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11060 /* Likewise if OP0 is a PLUS of a sign extension with a
11061 constant, which is usually represented with the PLUS
11062 between the shifts. */
11063 if (! unsigned_comparison_p
11064 && CONST_INT_P (XEXP (op0
, 1))
11065 && GET_CODE (XEXP (op0
, 0)) == PLUS
11066 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11067 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11068 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11069 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11070 MODE_INT
, 1)) != BLKmode
11071 && (((unsigned HOST_WIDE_INT
) const_op
11072 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11073 <= GET_MODE_MASK (tmode
)))
11075 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11076 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11077 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11078 add_const
, XEXP (op0
, 1));
11080 op0
= simplify_gen_binary (PLUS
, tmode
,
11081 gen_lowpart (tmode
, inner
),
11086 /* ... fall through ... */
11088 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11089 the low order N bits of FOO are known to be zero, we can do this
11090 by comparing FOO with C shifted left N bits so long as no
11091 overflow occurs. */
11092 if (CONST_INT_P (XEXP (op0
, 1))
11093 && INTVAL (XEXP (op0
, 1)) >= 0
11094 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11095 && mode_width
<= HOST_BITS_PER_WIDE_INT
11096 && (nonzero_bits (XEXP (op0
, 0), mode
)
11097 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11098 && (((unsigned HOST_WIDE_INT
) const_op
11099 + (GET_CODE (op0
) != LSHIFTRT
11100 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11103 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11105 /* If the shift was logical, then we must make the condition
11107 if (GET_CODE (op0
) == LSHIFTRT
)
11108 code
= unsigned_condition (code
);
11110 const_op
<<= INTVAL (XEXP (op0
, 1));
11111 op1
= GEN_INT (const_op
);
11112 op0
= XEXP (op0
, 0);
11116 /* If we are using this shift to extract just the sign bit, we
11117 can replace this with an LT or GE comparison. */
11119 && (equality_comparison_p
|| sign_bit_comparison_p
)
11120 && CONST_INT_P (XEXP (op0
, 1))
11121 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11124 op0
= XEXP (op0
, 0);
11125 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11137 /* Now make any compound operations involved in this comparison. Then,
11138 check for an outmost SUBREG on OP0 that is not doing anything or is
11139 paradoxical. The latter transformation must only be performed when
11140 it is known that the "extra" bits will be the same in op0 and op1 or
11141 that they don't matter. There are three cases to consider:
11143 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11144 care bits and we can assume they have any convenient value. So
11145 making the transformation is safe.
11147 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11148 In this case the upper bits of op0 are undefined. We should not make
11149 the simplification in that case as we do not know the contents of
11152 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11153 UNKNOWN. In that case we know those bits are zeros or ones. We must
11154 also be sure that they are the same as the upper bits of op1.
11156 We can never remove a SUBREG for a non-equality comparison because
11157 the sign bit is in a different place in the underlying object. */
11159 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11160 op1
= make_compound_operation (op1
, SET
);
11162 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11163 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11164 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11165 && (code
== NE
|| code
== EQ
))
11167 if (GET_MODE_SIZE (GET_MODE (op0
))
11168 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11170 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11172 if (REG_P (SUBREG_REG (op0
)))
11174 op0
= SUBREG_REG (op0
);
11175 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11178 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11179 <= HOST_BITS_PER_WIDE_INT
)
11180 && (nonzero_bits (SUBREG_REG (op0
),
11181 GET_MODE (SUBREG_REG (op0
)))
11182 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11184 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11186 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11187 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11188 op0
= SUBREG_REG (op0
), op1
= tem
;
11192 /* We now do the opposite procedure: Some machines don't have compare
11193 insns in all modes. If OP0's mode is an integer mode smaller than a
11194 word and we can't do a compare in that mode, see if there is a larger
11195 mode for which we can do the compare. There are a number of cases in
11196 which we can use the wider mode. */
11198 mode
= GET_MODE (op0
);
11199 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11200 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11201 && ! have_insn_for (COMPARE
, mode
))
11202 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11204 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11205 tmode
= GET_MODE_WIDER_MODE (tmode
))
11206 if (have_insn_for (COMPARE
, tmode
))
11210 /* If the only nonzero bits in OP0 and OP1 are those in the
11211 narrower mode and this is an equality or unsigned comparison,
11212 we can use the wider mode. Similarly for sign-extended
11213 values, in which case it is true for all comparisons. */
11214 zero_extended
= ((code
== EQ
|| code
== NE
11215 || code
== GEU
|| code
== GTU
11216 || code
== LEU
|| code
== LTU
)
11217 && (nonzero_bits (op0
, tmode
)
11218 & ~GET_MODE_MASK (mode
)) == 0
11219 && ((CONST_INT_P (op1
)
11220 || (nonzero_bits (op1
, tmode
)
11221 & ~GET_MODE_MASK (mode
)) == 0)));
11224 || ((num_sign_bit_copies (op0
, tmode
)
11225 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11226 - GET_MODE_BITSIZE (mode
)))
11227 && (num_sign_bit_copies (op1
, tmode
)
11228 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11229 - GET_MODE_BITSIZE (mode
)))))
11231 /* If OP0 is an AND and we don't have an AND in MODE either,
11232 make a new AND in the proper mode. */
11233 if (GET_CODE (op0
) == AND
11234 && !have_insn_for (AND
, mode
))
11235 op0
= simplify_gen_binary (AND
, tmode
,
11236 gen_lowpart (tmode
,
11238 gen_lowpart (tmode
,
11241 op0
= gen_lowpart (tmode
, op0
);
11242 if (zero_extended
&& CONST_INT_P (op1
))
11243 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11244 op1
= gen_lowpart (tmode
, op1
);
11248 /* If this is a test for negative, we can make an explicit
11249 test of the sign bit. */
11251 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11252 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11254 op0
= simplify_gen_binary (AND
, tmode
,
11255 gen_lowpart (tmode
, op0
),
11256 GEN_INT ((HOST_WIDE_INT
) 1
11257 << (GET_MODE_BITSIZE (mode
)
11259 code
= (code
== LT
) ? NE
: EQ
;
11264 #ifdef CANONICALIZE_COMPARISON
11265 /* If this machine only supports a subset of valid comparisons, see if we
11266 can convert an unsupported one into a supported one. */
11267 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11276 /* Utility function for record_value_for_reg. Count number of
11281 enum rtx_code code
= GET_CODE (x
);
11285 if (GET_RTX_CLASS (code
) == '2'
11286 || GET_RTX_CLASS (code
) == 'c')
11288 rtx x0
= XEXP (x
, 0);
11289 rtx x1
= XEXP (x
, 1);
11292 return 1 + 2 * count_rtxs (x0
);
11294 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11295 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11296 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11297 return 2 + 2 * count_rtxs (x0
)
11298 + count_rtxs (x
== XEXP (x1
, 0)
11299 ? XEXP (x1
, 1) : XEXP (x1
, 0));
11301 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11302 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11303 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11304 return 2 + 2 * count_rtxs (x1
)
11305 + count_rtxs (x
== XEXP (x0
, 0)
11306 ? XEXP (x0
, 1) : XEXP (x0
, 0));
11309 fmt
= GET_RTX_FORMAT (code
);
11310 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11312 ret
+= count_rtxs (XEXP (x
, i
));
11313 else if (fmt
[i
] == 'E')
11314 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11315 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
11320 /* Utility function for following routine. Called when X is part of a value
11321 being stored into last_set_value. Sets last_set_table_tick
11322 for each register mentioned. Similar to mention_regs in cse.c */
11325 update_table_tick (rtx x
)
11327 enum rtx_code code
= GET_CODE (x
);
11328 const char *fmt
= GET_RTX_FORMAT (code
);
11333 unsigned int regno
= REGNO (x
);
11334 unsigned int endregno
= END_REGNO (x
);
11337 for (r
= regno
; r
< endregno
; r
++)
11339 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, r
);
11340 rsp
->last_set_table_tick
= label_tick
;
11346 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11349 /* Check for identical subexpressions. If x contains
11350 identical subexpression we only have to traverse one of
11352 if (i
== 0 && ARITHMETIC_P (x
))
11354 /* Note that at this point x1 has already been
11356 rtx x0
= XEXP (x
, 0);
11357 rtx x1
= XEXP (x
, 1);
11359 /* If x0 and x1 are identical then there is no need to
11364 /* If x0 is identical to a subexpression of x1 then while
11365 processing x1, x0 has already been processed. Thus we
11366 are done with x. */
11367 if (ARITHMETIC_P (x1
)
11368 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11371 /* If x1 is identical to a subexpression of x0 then we
11372 still have to process the rest of x0. */
11373 if (ARITHMETIC_P (x0
)
11374 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11376 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11381 update_table_tick (XEXP (x
, i
));
11383 else if (fmt
[i
] == 'E')
11384 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11385 update_table_tick (XVECEXP (x
, i
, j
));
11388 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11389 are saying that the register is clobbered and we no longer know its
11390 value. If INSN is zero, don't update reg_stat[].last_set; this is
11391 only permitted with VALUE also zero and is used to invalidate the
11395 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11397 unsigned int regno
= REGNO (reg
);
11398 unsigned int endregno
= END_REGNO (reg
);
11400 reg_stat_type
*rsp
;
11402 /* If VALUE contains REG and we have a previous value for REG, substitute
11403 the previous value. */
11404 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11408 /* Set things up so get_last_value is allowed to see anything set up to
11410 subst_low_luid
= DF_INSN_LUID (insn
);
11411 tem
= get_last_value (reg
);
11413 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11414 it isn't going to be useful and will take a lot of time to process,
11415 so just use the CLOBBER. */
11419 if (ARITHMETIC_P (tem
)
11420 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11421 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11422 tem
= XEXP (tem
, 0);
11423 else if (count_occurrences (value
, reg
, 1) >= 2)
11425 /* If there are two or more occurrences of REG in VALUE,
11426 prevent the value from growing too much. */
11427 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
11428 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
11431 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11435 /* For each register modified, show we don't know its value, that
11436 we don't know about its bitwise content, that its value has been
11437 updated, and that we don't know the location of the death of the
11439 for (i
= regno
; i
< endregno
; i
++)
11441 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11444 rsp
->last_set
= insn
;
11446 rsp
->last_set_value
= 0;
11447 rsp
->last_set_mode
= VOIDmode
;
11448 rsp
->last_set_nonzero_bits
= 0;
11449 rsp
->last_set_sign_bit_copies
= 0;
11450 rsp
->last_death
= 0;
11451 rsp
->truncated_to_mode
= VOIDmode
;
11454 /* Mark registers that are being referenced in this value. */
11456 update_table_tick (value
);
11458 /* Now update the status of each register being set.
11459 If someone is using this register in this block, set this register
11460 to invalid since we will get confused between the two lives in this
11461 basic block. This makes using this register always invalid. In cse, we
11462 scan the table to invalidate all entries using this register, but this
11463 is too much work for us. */
11465 for (i
= regno
; i
< endregno
; i
++)
11467 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11468 rsp
->last_set_label
= label_tick
;
11470 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
11471 rsp
->last_set_invalid
= 1;
11473 rsp
->last_set_invalid
= 0;
11476 /* The value being assigned might refer to X (like in "x++;"). In that
11477 case, we must replace it with (clobber (const_int 0)) to prevent
11479 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
11480 if (value
&& ! get_last_value_validate (&value
, insn
,
11481 rsp
->last_set_label
, 0))
11483 value
= copy_rtx (value
);
11484 if (! get_last_value_validate (&value
, insn
,
11485 rsp
->last_set_label
, 1))
11489 /* For the main register being modified, update the value, the mode, the
11490 nonzero bits, and the number of sign bit copies. */
11492 rsp
->last_set_value
= value
;
11496 enum machine_mode mode
= GET_MODE (reg
);
11497 subst_low_luid
= DF_INSN_LUID (insn
);
11498 rsp
->last_set_mode
= mode
;
11499 if (GET_MODE_CLASS (mode
) == MODE_INT
11500 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11501 mode
= nonzero_bits_mode
;
11502 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
11503 rsp
->last_set_sign_bit_copies
11504 = num_sign_bit_copies (value
, GET_MODE (reg
));
11508 /* Called via note_stores from record_dead_and_set_regs to handle one
11509 SET or CLOBBER in an insn. DATA is the instruction in which the
11510 set is occurring. */
11513 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
11515 rtx record_dead_insn
= (rtx
) data
;
11517 if (GET_CODE (dest
) == SUBREG
)
11518 dest
= SUBREG_REG (dest
);
11520 if (!record_dead_insn
)
11523 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
11529 /* If we are setting the whole register, we know its value. Otherwise
11530 show that we don't know the value. We can handle SUBREG in
11532 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11533 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11534 else if (GET_CODE (setter
) == SET
11535 && GET_CODE (SET_DEST (setter
)) == SUBREG
11536 && SUBREG_REG (SET_DEST (setter
)) == dest
11537 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11538 && subreg_lowpart_p (SET_DEST (setter
)))
11539 record_value_for_reg (dest
, record_dead_insn
,
11540 gen_lowpart (GET_MODE (dest
),
11541 SET_SRC (setter
)));
11543 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11545 else if (MEM_P (dest
)
11546 /* Ignore pushes, they clobber nothing. */
11547 && ! push_operand (dest
, GET_MODE (dest
)))
11548 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
11551 /* Update the records of when each REG was most recently set or killed
11552 for the things done by INSN. This is the last thing done in processing
11553 INSN in the combiner loop.
11555 We update reg_stat[], in particular fields last_set, last_set_value,
11556 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11557 last_death, and also the similar information mem_last_set (which insn
11558 most recently modified memory) and last_call_luid (which insn was the
11559 most recent subroutine call). */
11562 record_dead_and_set_regs (rtx insn
)
11567 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11569 if (REG_NOTE_KIND (link
) == REG_DEAD
11570 && REG_P (XEXP (link
, 0)))
11572 unsigned int regno
= REGNO (XEXP (link
, 0));
11573 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
11575 for (i
= regno
; i
< endregno
; i
++)
11577 reg_stat_type
*rsp
;
11579 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11580 rsp
->last_death
= insn
;
11583 else if (REG_NOTE_KIND (link
) == REG_INC
)
11584 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11589 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11590 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11592 reg_stat_type
*rsp
;
11594 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11595 rsp
->last_set_invalid
= 1;
11596 rsp
->last_set
= insn
;
11597 rsp
->last_set_value
= 0;
11598 rsp
->last_set_mode
= VOIDmode
;
11599 rsp
->last_set_nonzero_bits
= 0;
11600 rsp
->last_set_sign_bit_copies
= 0;
11601 rsp
->last_death
= 0;
11602 rsp
->truncated_to_mode
= VOIDmode
;
11605 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
11607 /* We can't combine into a call pattern. Remember, though, that
11608 the return value register is set at this LUID. We could
11609 still replace a register with the return value from the
11610 wrong subroutine call! */
11611 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
11614 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11617 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11618 register present in the SUBREG, so for each such SUBREG go back and
11619 adjust nonzero and sign bit information of the registers that are
11620 known to have some zero/sign bits set.
11622 This is needed because when combine blows the SUBREGs away, the
11623 information on zero/sign bits is lost and further combines can be
11624 missed because of that. */
11627 record_promoted_value (rtx insn
, rtx subreg
)
11630 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11631 enum machine_mode mode
= GET_MODE (subreg
);
11633 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11636 for (links
= LOG_LINKS (insn
); links
;)
11638 reg_stat_type
*rsp
;
11640 insn
= XEXP (links
, 0);
11641 set
= single_set (insn
);
11643 if (! set
|| !REG_P (SET_DEST (set
))
11644 || REGNO (SET_DEST (set
)) != regno
11645 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11647 links
= XEXP (links
, 1);
11651 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
11652 if (rsp
->last_set
== insn
)
11654 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11655 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11658 if (REG_P (SET_SRC (set
)))
11660 regno
= REGNO (SET_SRC (set
));
11661 links
= LOG_LINKS (insn
);
11668 /* Check if X, a register, is known to contain a value already
11669 truncated to MODE. In this case we can use a subreg to refer to
11670 the truncated value even though in the generic case we would need
11671 an explicit truncation. */
11674 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
11676 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
11677 enum machine_mode truncated
= rsp
->truncated_to_mode
;
11680 || rsp
->truncation_label
< label_tick_ebb_start
)
11682 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
11684 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
11685 GET_MODE_BITSIZE (truncated
)))
11690 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11691 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11692 might be able to turn a truncate into a subreg using this information.
11693 Return -1 if traversing *P is complete or 0 otherwise. */
11696 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
11699 enum machine_mode truncated_mode
;
11700 reg_stat_type
*rsp
;
11702 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
11704 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
11705 truncated_mode
= GET_MODE (x
);
11707 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
11710 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode
),
11711 GET_MODE_BITSIZE (original_mode
)))
11714 x
= SUBREG_REG (x
);
11716 /* ??? For hard-regs we now record everything. We might be able to
11717 optimize this using last_set_mode. */
11718 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
11719 truncated_mode
= GET_MODE (x
);
11723 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
11724 if (rsp
->truncated_to_mode
== 0
11725 || rsp
->truncation_label
< label_tick_ebb_start
11726 || (GET_MODE_SIZE (truncated_mode
)
11727 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
11729 rsp
->truncated_to_mode
= truncated_mode
;
11730 rsp
->truncation_label
= label_tick
;
11736 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11737 the modes they are used in. This can help truning TRUNCATEs into
11741 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
11743 for_each_rtx (x
, record_truncated_value
, NULL
);
11746 /* Scan X for promoted SUBREGs. For each one found,
11747 note what it implies to the registers used in it. */
11750 check_promoted_subreg (rtx insn
, rtx x
)
11752 if (GET_CODE (x
) == SUBREG
11753 && SUBREG_PROMOTED_VAR_P (x
)
11754 && REG_P (SUBREG_REG (x
)))
11755 record_promoted_value (insn
, x
);
11758 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11761 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11765 check_promoted_subreg (insn
, XEXP (x
, i
));
11769 if (XVEC (x
, i
) != 0)
11770 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11771 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11777 /* Utility routine for the following function. Verify that all the registers
11778 mentioned in *LOC are valid when *LOC was part of a value set when
11779 label_tick == TICK. Return 0 if some are not.
11781 If REPLACE is nonzero, replace the invalid reference with
11782 (clobber (const_int 0)) and return 1. This replacement is useful because
11783 we often can get useful information about the form of a value (e.g., if
11784 it was produced by a shift that always produces -1 or 0) even though
11785 we don't know exactly what registers it was produced from. */
11788 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11791 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11792 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11797 unsigned int regno
= REGNO (x
);
11798 unsigned int endregno
= END_REGNO (x
);
11801 for (j
= regno
; j
< endregno
; j
++)
11803 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, j
);
11804 if (rsp
->last_set_invalid
11805 /* If this is a pseudo-register that was only set once and not
11806 live at the beginning of the function, it is always valid. */
11807 || (! (regno
>= FIRST_PSEUDO_REGISTER
11808 && REG_N_SETS (regno
) == 1
11809 && (!REGNO_REG_SET_P
11810 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
11811 && rsp
->last_set_label
> tick
))
11814 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11821 /* If this is a memory reference, make sure that there were
11822 no stores after it that might have clobbered the value. We don't
11823 have alias info, so we assume any store invalidates it. */
11824 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11825 && DF_INSN_LUID (insn
) <= mem_last_set
)
11828 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11832 for (i
= 0; i
< len
; i
++)
11836 /* Check for identical subexpressions. If x contains
11837 identical subexpression we only have to traverse one of
11839 if (i
== 1 && ARITHMETIC_P (x
))
11841 /* Note that at this point x0 has already been checked
11842 and found valid. */
11843 rtx x0
= XEXP (x
, 0);
11844 rtx x1
= XEXP (x
, 1);
11846 /* If x0 and x1 are identical then x is also valid. */
11850 /* If x1 is identical to a subexpression of x0 then
11851 while checking x0, x1 has already been checked. Thus
11852 it is valid and so as x. */
11853 if (ARITHMETIC_P (x0
)
11854 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11857 /* If x0 is identical to a subexpression of x1 then x is
11858 valid iff the rest of x1 is valid. */
11859 if (ARITHMETIC_P (x1
)
11860 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11862 get_last_value_validate (&XEXP (x1
,
11863 x0
== XEXP (x1
, 0) ? 1 : 0),
11864 insn
, tick
, replace
);
11867 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11871 else if (fmt
[i
] == 'E')
11872 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11873 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
11874 insn
, tick
, replace
) == 0)
11878 /* If we haven't found a reason for it to be invalid, it is valid. */
11882 /* Get the last value assigned to X, if known. Some registers
11883 in the value may be replaced with (clobber (const_int 0)) if their value
11884 is known longer known reliably. */
11887 get_last_value (const_rtx x
)
11889 unsigned int regno
;
11891 reg_stat_type
*rsp
;
11893 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11894 then convert it to the desired mode. If this is a paradoxical SUBREG,
11895 we cannot predict what values the "extra" bits might have. */
11896 if (GET_CODE (x
) == SUBREG
11897 && subreg_lowpart_p (x
)
11898 && (GET_MODE_SIZE (GET_MODE (x
))
11899 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11900 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11901 return gen_lowpart (GET_MODE (x
), value
);
11907 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
11908 value
= rsp
->last_set_value
;
11910 /* If we don't have a value, or if it isn't for this basic block and
11911 it's either a hard register, set more than once, or it's a live
11912 at the beginning of the function, return 0.
11914 Because if it's not live at the beginning of the function then the reg
11915 is always set before being used (is never used without being set).
11916 And, if it's set only once, and it's always set before use, then all
11917 uses must have the same last value, even if it's not from this basic
11921 || (rsp
->last_set_label
< label_tick_ebb_start
11922 && (regno
< FIRST_PSEUDO_REGISTER
11923 || REG_N_SETS (regno
) != 1
11925 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
11928 /* If the value was set in a later insn than the ones we are processing,
11929 we can't use it even if the register was only set once. */
11930 if (rsp
->last_set_label
== label_tick
11931 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
11934 /* If the value has all its registers valid, return it. */
11935 if (get_last_value_validate (&value
, rsp
->last_set
,
11936 rsp
->last_set_label
, 0))
11939 /* Otherwise, make a copy and replace any invalid register with
11940 (clobber (const_int 0)). If that fails for some reason, return 0. */
11942 value
= copy_rtx (value
);
11943 if (get_last_value_validate (&value
, rsp
->last_set
,
11944 rsp
->last_set_label
, 1))
11950 /* Return nonzero if expression X refers to a REG or to memory
11951 that is set in an instruction more recent than FROM_LUID. */
11954 use_crosses_set_p (const_rtx x
, int from_luid
)
11958 enum rtx_code code
= GET_CODE (x
);
11962 unsigned int regno
= REGNO (x
);
11963 unsigned endreg
= END_REGNO (x
);
11965 #ifdef PUSH_ROUNDING
11966 /* Don't allow uses of the stack pointer to be moved,
11967 because we don't know whether the move crosses a push insn. */
11968 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11971 for (; regno
< endreg
; regno
++)
11973 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
11975 && rsp
->last_set_label
== label_tick
11976 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
11982 if (code
== MEM
&& mem_last_set
> from_luid
)
11985 fmt
= GET_RTX_FORMAT (code
);
11987 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11992 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11993 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
11996 else if (fmt
[i
] == 'e'
11997 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12003 /* Define three variables used for communication between the following
12006 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12007 static int reg_dead_flag
;
12009 /* Function called via note_stores from reg_dead_at_p.
12011 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12012 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12015 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12017 unsigned int regno
, endregno
;
12022 regno
= REGNO (dest
);
12023 endregno
= END_REGNO (dest
);
12024 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12025 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12028 /* Return nonzero if REG is known to be dead at INSN.
12030 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12031 referencing REG, it is dead. If we hit a SET referencing REG, it is
12032 live. Otherwise, see if it is live or dead at the start of the basic
12033 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12034 must be assumed to be always live. */
12037 reg_dead_at_p (rtx reg
, rtx insn
)
12042 /* Set variables for reg_dead_at_p_1. */
12043 reg_dead_regno
= REGNO (reg
);
12044 reg_dead_endregno
= END_REGNO (reg
);
12048 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12049 we allow the machine description to decide whether use-and-clobber
12050 patterns are OK. */
12051 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12053 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12054 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12058 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12059 beginning of basic block. */
12060 block
= BLOCK_FOR_INSN (insn
);
12065 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12067 return reg_dead_flag
== 1 ? 1 : 0;
12069 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12073 if (insn
== BB_HEAD (block
))
12076 insn
= PREV_INSN (insn
);
12079 /* Look at live-in sets for the basic block that we were in. */
12080 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12081 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12087 /* Note hard registers in X that are used. */
12090 mark_used_regs_combine (rtx x
)
12092 RTX_CODE code
= GET_CODE (x
);
12093 unsigned int regno
;
12106 case ADDR_DIFF_VEC
:
12109 /* CC0 must die in the insn after it is set, so we don't need to take
12110 special note of it here. */
12116 /* If we are clobbering a MEM, mark any hard registers inside the
12117 address as used. */
12118 if (MEM_P (XEXP (x
, 0)))
12119 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12124 /* A hard reg in a wide mode may really be multiple registers.
12125 If so, mark all of them just like the first. */
12126 if (regno
< FIRST_PSEUDO_REGISTER
)
12128 /* None of this applies to the stack, frame or arg pointers. */
12129 if (regno
== STACK_POINTER_REGNUM
12130 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12131 || regno
== HARD_FRAME_POINTER_REGNUM
12133 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12134 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12136 || regno
== FRAME_POINTER_REGNUM
)
12139 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12145 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12147 rtx testreg
= SET_DEST (x
);
12149 while (GET_CODE (testreg
) == SUBREG
12150 || GET_CODE (testreg
) == ZERO_EXTRACT
12151 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12152 testreg
= XEXP (testreg
, 0);
12154 if (MEM_P (testreg
))
12155 mark_used_regs_combine (XEXP (testreg
, 0));
12157 mark_used_regs_combine (SET_SRC (x
));
12165 /* Recursively scan the operands of this expression. */
12168 const char *fmt
= GET_RTX_FORMAT (code
);
12170 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12173 mark_used_regs_combine (XEXP (x
, i
));
12174 else if (fmt
[i
] == 'E')
12178 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12179 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12185 /* Remove register number REGNO from the dead registers list of INSN.
12187 Return the note used to record the death, if there was one. */
12190 remove_death (unsigned int regno
, rtx insn
)
12192 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12195 remove_note (insn
, note
);
12200 /* For each register (hardware or pseudo) used within expression X, if its
12201 death is in an instruction with luid between FROM_LUID (inclusive) and
12202 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12203 list headed by PNOTES.
12205 That said, don't move registers killed by maybe_kill_insn.
12207 This is done when X is being merged by combination into TO_INSN. These
12208 notes will then be distributed as needed. */
12211 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12216 enum rtx_code code
= GET_CODE (x
);
12220 unsigned int regno
= REGNO (x
);
12221 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
)->last_death
;
12223 /* Don't move the register if it gets killed in between from and to. */
12224 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12225 && ! reg_referenced_p (x
, maybe_kill_insn
))
12229 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12230 && DF_INSN_LUID (where_dead
) >= from_luid
12231 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12233 rtx note
= remove_death (regno
, where_dead
);
12235 /* It is possible for the call above to return 0. This can occur
12236 when last_death points to I2 or I1 that we combined with.
12237 In that case make a new note.
12239 We must also check for the case where X is a hard register
12240 and NOTE is a death note for a range of hard registers
12241 including X. In that case, we must put REG_DEAD notes for
12242 the remaining registers in place of NOTE. */
12244 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12245 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12246 > GET_MODE_SIZE (GET_MODE (x
))))
12248 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12249 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12250 unsigned int ourend
= END_HARD_REGNO (x
);
12253 for (i
= deadregno
; i
< deadend
; i
++)
12254 if (i
< regno
|| i
>= ourend
)
12255 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
12258 /* If we didn't find any note, or if we found a REG_DEAD note that
12259 covers only part of the given reg, and we have a multi-reg hard
12260 register, then to be safe we must check for REG_DEAD notes
12261 for each register other than the first. They could have
12262 their own REG_DEAD notes lying around. */
12263 else if ((note
== 0
12265 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12266 < GET_MODE_SIZE (GET_MODE (x
)))))
12267 && regno
< FIRST_PSEUDO_REGISTER
12268 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12270 unsigned int ourend
= END_HARD_REGNO (x
);
12271 unsigned int i
, offset
;
12275 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12279 for (i
= regno
+ offset
; i
< ourend
; i
++)
12280 move_deaths (regno_reg_rtx
[i
],
12281 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
12284 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12286 XEXP (note
, 1) = *pnotes
;
12290 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
12296 else if (GET_CODE (x
) == SET
)
12298 rtx dest
= SET_DEST (x
);
12300 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12302 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12303 that accesses one word of a multi-word item, some
12304 piece of everything register in the expression is used by
12305 this insn, so remove any old death. */
12306 /* ??? So why do we test for equality of the sizes? */
12308 if (GET_CODE (dest
) == ZERO_EXTRACT
12309 || GET_CODE (dest
) == STRICT_LOW_PART
12310 || (GET_CODE (dest
) == SUBREG
12311 && (((GET_MODE_SIZE (GET_MODE (dest
))
12312 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12313 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12314 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12316 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12320 /* If this is some other SUBREG, we know it replaces the entire
12321 value, so use that as the destination. */
12322 if (GET_CODE (dest
) == SUBREG
)
12323 dest
= SUBREG_REG (dest
);
12325 /* If this is a MEM, adjust deaths of anything used in the address.
12326 For a REG (the only other possibility), the entire value is
12327 being replaced so the old value is not used in this insn. */
12330 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
12335 else if (GET_CODE (x
) == CLOBBER
)
12338 len
= GET_RTX_LENGTH (code
);
12339 fmt
= GET_RTX_FORMAT (code
);
12341 for (i
= 0; i
< len
; i
++)
12346 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12347 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
12350 else if (fmt
[i
] == 'e')
12351 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12355 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12356 pattern of an insn. X must be a REG. */
12359 reg_bitfield_target_p (rtx x
, rtx body
)
12363 if (GET_CODE (body
) == SET
)
12365 rtx dest
= SET_DEST (body
);
12367 unsigned int regno
, tregno
, endregno
, endtregno
;
12369 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12370 target
= XEXP (dest
, 0);
12371 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12372 target
= SUBREG_REG (XEXP (dest
, 0));
12376 if (GET_CODE (target
) == SUBREG
)
12377 target
= SUBREG_REG (target
);
12379 if (!REG_P (target
))
12382 tregno
= REGNO (target
), regno
= REGNO (x
);
12383 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12384 return target
== x
;
12386 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
12387 endregno
= end_hard_regno (GET_MODE (x
), regno
);
12389 return endregno
> tregno
&& regno
< endtregno
;
12392 else if (GET_CODE (body
) == PARALLEL
)
12393 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12394 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12400 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12401 as appropriate. I3 and I2 are the insns resulting from the combination
12402 insns including FROM (I2 may be zero).
12404 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12405 not need REG_DEAD notes because they are being substituted for. This
12406 saves searching in the most common cases.
12408 Each note in the list is either ignored or placed on some insns, depending
12409 on the type of note. */
12412 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
12415 rtx note
, next_note
;
12418 for (note
= notes
; note
; note
= next_note
)
12420 rtx place
= 0, place2
= 0;
12422 next_note
= XEXP (note
, 1);
12423 switch (REG_NOTE_KIND (note
))
12427 /* Doesn't matter much where we put this, as long as it's somewhere.
12428 It is preferable to keep these notes on branches, which is most
12429 likely to be i3. */
12433 case REG_VALUE_PROFILE
:
12434 /* Just get rid of this note, as it is unused later anyway. */
12437 case REG_NON_LOCAL_GOTO
:
12442 gcc_assert (i2
&& JUMP_P (i2
));
12447 case REG_EH_REGION
:
12448 /* These notes must remain with the call or trapping instruction. */
12451 else if (i2
&& CALL_P (i2
))
12455 gcc_assert (flag_non_call_exceptions
);
12456 if (may_trap_p (i3
))
12458 else if (i2
&& may_trap_p (i2
))
12460 /* ??? Otherwise assume we've combined things such that we
12461 can now prove that the instructions can't trap. Drop the
12462 note in this case. */
12468 /* These notes must remain with the call. It should not be
12469 possible for both I2 and I3 to be a call. */
12474 gcc_assert (i2
&& CALL_P (i2
));
12480 /* Any clobbers for i3 may still exist, and so we must process
12481 REG_UNUSED notes from that insn.
12483 Any clobbers from i2 or i1 can only exist if they were added by
12484 recog_for_combine. In that case, recog_for_combine created the
12485 necessary REG_UNUSED notes. Trying to keep any original
12486 REG_UNUSED notes from these insns can cause incorrect output
12487 if it is for the same register as the original i3 dest.
12488 In that case, we will notice that the register is set in i3,
12489 and then add a REG_UNUSED note for the destination of i3, which
12490 is wrong. However, it is possible to have REG_UNUSED notes from
12491 i2 or i1 for register which were both used and clobbered, so
12492 we keep notes from i2 or i1 if they will turn into REG_DEAD
12495 /* If this register is set or clobbered in I3, put the note there
12496 unless there is one already. */
12497 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12499 if (from_insn
!= i3
)
12502 if (! (REG_P (XEXP (note
, 0))
12503 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12504 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12507 /* Otherwise, if this register is used by I3, then this register
12508 now dies here, so we must put a REG_DEAD note here unless there
12510 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12511 && ! (REG_P (XEXP (note
, 0))
12512 ? find_regno_note (i3
, REG_DEAD
,
12513 REGNO (XEXP (note
, 0)))
12514 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12516 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12524 /* These notes say something about results of an insn. We can
12525 only support them if they used to be on I3 in which case they
12526 remain on I3. Otherwise they are ignored.
12528 If the note refers to an expression that is not a constant, we
12529 must also ignore the note since we cannot tell whether the
12530 equivalence is still true. It might be possible to do
12531 slightly better than this (we only have a problem if I2DEST
12532 or I1DEST is present in the expression), but it doesn't
12533 seem worth the trouble. */
12535 if (from_insn
== i3
12536 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12541 /* These notes say something about how a register is used. They must
12542 be present on any use of the register in I2 or I3. */
12543 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12546 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12555 case REG_LABEL_TARGET
:
12556 case REG_LABEL_OPERAND
:
12557 /* This can show up in several ways -- either directly in the
12558 pattern, or hidden off in the constant pool with (or without?)
12559 a REG_EQUAL note. */
12560 /* ??? Ignore the without-reg_equal-note problem for now. */
12561 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12562 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12563 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12564 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12568 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12569 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12570 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12571 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12579 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12580 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12582 if (place
&& JUMP_P (place
)
12583 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
12584 && (JUMP_LABEL (place
) == NULL
12585 || JUMP_LABEL (place
) == XEXP (note
, 0)))
12587 rtx label
= JUMP_LABEL (place
);
12590 JUMP_LABEL (place
) = XEXP (note
, 0);
12591 else if (LABEL_P (label
))
12592 LABEL_NUSES (label
)--;
12595 if (place2
&& JUMP_P (place2
)
12596 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
12597 && (JUMP_LABEL (place2
) == NULL
12598 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
12600 rtx label
= JUMP_LABEL (place2
);
12603 JUMP_LABEL (place2
) = XEXP (note
, 0);
12604 else if (LABEL_P (label
))
12605 LABEL_NUSES (label
)--;
12611 /* This note says something about the value of a register prior
12612 to the execution of an insn. It is too much trouble to see
12613 if the note is still correct in all situations. It is better
12614 to simply delete it. */
12618 /* If we replaced the right hand side of FROM_INSN with a
12619 REG_EQUAL note, the original use of the dying register
12620 will not have been combined into I3 and I2. In such cases,
12621 FROM_INSN is guaranteed to be the first of the combined
12622 instructions, so we simply need to search back before
12623 FROM_INSN for the previous use or set of this register,
12624 then alter the notes there appropriately.
12626 If the register is used as an input in I3, it dies there.
12627 Similarly for I2, if it is nonzero and adjacent to I3.
12629 If the register is not used as an input in either I3 or I2
12630 and it is not one of the registers we were supposed to eliminate,
12631 there are two possibilities. We might have a non-adjacent I2
12632 or we might have somehow eliminated an additional register
12633 from a computation. For example, we might have had A & B where
12634 we discover that B will always be zero. In this case we will
12635 eliminate the reference to A.
12637 In both cases, we must search to see if we can find a previous
12638 use of A and put the death note there. */
12641 && from_insn
== i2mod
12642 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
12647 && CALL_P (from_insn
)
12648 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12650 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12652 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12653 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12655 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
12657 && reg_overlap_mentioned_p (XEXP (note
, 0),
12659 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12666 basic_block bb
= this_basic_block
;
12668 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
12670 if (! INSN_P (tem
))
12672 if (tem
== BB_HEAD (bb
))
12677 /* If the register is being set at TEM, see if that is all
12678 TEM is doing. If so, delete TEM. Otherwise, make this
12679 into a REG_UNUSED note instead. Don't delete sets to
12680 global register vars. */
12681 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12682 || !global_regs
[REGNO (XEXP (note
, 0))])
12683 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12685 rtx set
= single_set (tem
);
12686 rtx inner_dest
= 0;
12688 rtx cc0_setter
= NULL_RTX
;
12692 for (inner_dest
= SET_DEST (set
);
12693 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12694 || GET_CODE (inner_dest
) == SUBREG
12695 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12696 inner_dest
= XEXP (inner_dest
, 0))
12699 /* Verify that it was the set, and not a clobber that
12700 modified the register.
12702 CC0 targets must be careful to maintain setter/user
12703 pairs. If we cannot delete the setter due to side
12704 effects, mark the user with an UNUSED note instead
12707 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12708 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12710 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12711 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12712 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12716 /* Move the notes and links of TEM elsewhere.
12717 This might delete other dead insns recursively.
12718 First set the pattern to something that won't use
12720 rtx old_notes
= REG_NOTES (tem
);
12722 PATTERN (tem
) = pc_rtx
;
12723 REG_NOTES (tem
) = NULL
;
12725 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
12726 NULL_RTX
, NULL_RTX
);
12727 distribute_links (LOG_LINKS (tem
));
12729 SET_INSN_DELETED (tem
);
12734 /* Delete the setter too. */
12737 PATTERN (cc0_setter
) = pc_rtx
;
12738 old_notes
= REG_NOTES (cc0_setter
);
12739 REG_NOTES (cc0_setter
) = NULL
;
12741 distribute_notes (old_notes
, cc0_setter
,
12742 cc0_setter
, NULL_RTX
,
12743 NULL_RTX
, NULL_RTX
);
12744 distribute_links (LOG_LINKS (cc0_setter
));
12746 SET_INSN_DELETED (cc0_setter
);
12747 if (cc0_setter
== i2
)
12754 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12756 /* If there isn't already a REG_UNUSED note, put one
12757 here. Do not place a REG_DEAD note, even if
12758 the register is also used here; that would not
12759 match the algorithm used in lifetime analysis
12760 and can cause the consistency check in the
12761 scheduler to fail. */
12762 if (! find_regno_note (tem
, REG_UNUSED
,
12763 REGNO (XEXP (note
, 0))))
12768 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12770 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12774 /* If we are doing a 3->2 combination, and we have a
12775 register which formerly died in i3 and was not used
12776 by i2, which now no longer dies in i3 and is used in
12777 i2 but does not die in i2, and place is between i2
12778 and i3, then we may need to move a link from place to
12780 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
12782 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
12783 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12785 rtx links
= LOG_LINKS (place
);
12786 LOG_LINKS (place
) = 0;
12787 distribute_links (links
);
12792 if (tem
== BB_HEAD (bb
))
12798 /* If the register is set or already dead at PLACE, we needn't do
12799 anything with this note if it is still a REG_DEAD note.
12800 We check here if it is set at all, not if is it totally replaced,
12801 which is what `dead_or_set_p' checks, so also check for it being
12804 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12806 unsigned int regno
= REGNO (XEXP (note
, 0));
12807 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12809 if (dead_or_set_p (place
, XEXP (note
, 0))
12810 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12812 /* Unless the register previously died in PLACE, clear
12813 last_death. [I no longer understand why this is
12815 if (rsp
->last_death
!= place
)
12816 rsp
->last_death
= 0;
12820 rsp
->last_death
= place
;
12822 /* If this is a death note for a hard reg that is occupying
12823 multiple registers, ensure that we are still using all
12824 parts of the object. If we find a piece of the object
12825 that is unused, we must arrange for an appropriate REG_DEAD
12826 note to be added for it. However, we can't just emit a USE
12827 and tag the note to it, since the register might actually
12828 be dead; so we recourse, and the recursive call then finds
12829 the previous insn that used this register. */
12831 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12832 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12834 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
12838 for (i
= regno
; i
< endregno
; i
++)
12839 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12840 && ! find_regno_fusage (place
, USE
, i
))
12841 || dead_or_set_regno_p (place
, i
))
12846 /* Put only REG_DEAD notes for pieces that are
12847 not already dead or set. */
12849 for (i
= regno
; i
< endregno
;
12850 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12852 rtx piece
= regno_reg_rtx
[i
];
12853 basic_block bb
= this_basic_block
;
12855 if (! dead_or_set_p (place
, piece
)
12856 && ! reg_bitfield_target_p (piece
,
12859 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
12862 distribute_notes (new_note
, place
, place
,
12863 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12865 else if (! refers_to_regno_p (i
, i
+ 1,
12866 PATTERN (place
), 0)
12867 && ! find_regno_fusage (place
, USE
, i
))
12868 for (tem
= PREV_INSN (place
); ;
12869 tem
= PREV_INSN (tem
))
12871 if (! INSN_P (tem
))
12873 if (tem
== BB_HEAD (bb
))
12877 if (dead_or_set_p (tem
, piece
)
12878 || reg_bitfield_target_p (piece
,
12881 add_reg_note (tem
, REG_UNUSED
, piece
);
12895 /* Any other notes should not be present at this point in the
12897 gcc_unreachable ();
12902 XEXP (note
, 1) = REG_NOTES (place
);
12903 REG_NOTES (place
) = note
;
12907 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
12911 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12912 I3, I2, and I1 to new locations. This is also called to add a link
12913 pointing at I3 when I3's destination is changed. */
12916 distribute_links (rtx links
)
12918 rtx link
, next_link
;
12920 for (link
= links
; link
; link
= next_link
)
12926 next_link
= XEXP (link
, 1);
12928 /* If the insn that this link points to is a NOTE or isn't a single
12929 set, ignore it. In the latter case, it isn't clear what we
12930 can do other than ignore the link, since we can't tell which
12931 register it was for. Such links wouldn't be used by combine
12934 It is not possible for the destination of the target of the link to
12935 have been changed by combine. The only potential of this is if we
12936 replace I3, I2, and I1 by I3 and I2. But in that case the
12937 destination of I2 also remains unchanged. */
12939 if (NOTE_P (XEXP (link
, 0))
12940 || (set
= single_set (XEXP (link
, 0))) == 0)
12943 reg
= SET_DEST (set
);
12944 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12945 || GET_CODE (reg
) == STRICT_LOW_PART
)
12946 reg
= XEXP (reg
, 0);
12948 /* A LOG_LINK is defined as being placed on the first insn that uses
12949 a register and points to the insn that sets the register. Start
12950 searching at the next insn after the target of the link and stop
12951 when we reach a set of the register or the end of the basic block.
12953 Note that this correctly handles the link that used to point from
12954 I3 to I2. Also note that not much searching is typically done here
12955 since most links don't point very far away. */
12957 for (insn
= NEXT_INSN (XEXP (link
, 0));
12958 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12959 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12960 insn
= NEXT_INSN (insn
))
12961 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12963 if (reg_referenced_p (reg
, PATTERN (insn
)))
12967 else if (CALL_P (insn
)
12968 && find_reg_fusage (insn
, USE
, reg
))
12973 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12976 /* If we found a place to put the link, place it there unless there
12977 is already a link to the same insn as LINK at that point. */
12983 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12984 if (XEXP (link2
, 0) == XEXP (link
, 0))
12989 XEXP (link
, 1) = LOG_LINKS (place
);
12990 LOG_LINKS (place
) = link
;
12992 /* Set added_links_insn to the earliest insn we added a
12994 if (added_links_insn
== 0
12995 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
12996 added_links_insn
= place
;
13002 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13003 Check whether the expression pointer to by LOC is a register or
13004 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13005 Otherwise return zero. */
13008 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13013 && (REG_P (x
) || MEM_P (x
))
13014 && ! reg_mentioned_p (x
, (rtx
) expr
))
13019 /* Check for any register or memory mentioned in EQUIV that is not
13020 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13021 of EXPR where some registers may have been replaced by constants. */
13024 unmentioned_reg_p (rtx equiv
, rtx expr
)
13026 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13030 dump_combine_stats (FILE *file
)
13034 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13035 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13039 dump_combine_total_stats (FILE *file
)
13043 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13044 total_attempts
, total_merges
, total_extras
, total_successes
);
13048 gate_handle_combine (void)
13050 return (optimize
> 0);
13053 /* Try combining insns through substitution. */
13054 static unsigned int
13055 rest_of_handle_combine (void)
13057 int rebuild_jump_labels_after_combine
;
13059 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13060 df_note_add_problem ();
13063 regstat_init_n_sets_and_refs ();
13065 rebuild_jump_labels_after_combine
13066 = combine_instructions (get_insns (), max_reg_num ());
13068 /* Combining insns may have turned an indirect jump into a
13069 direct jump. Rebuild the JUMP_LABEL fields of jumping
13071 if (rebuild_jump_labels_after_combine
)
13073 timevar_push (TV_JUMP
);
13074 rebuild_jump_labels (get_insns ());
13076 timevar_pop (TV_JUMP
);
13079 regstat_free_n_sets_and_refs ();
13083 struct rtl_opt_pass pass_combine
=
13087 "combine", /* name */
13088 gate_handle_combine
, /* gate */
13089 rest_of_handle_combine
, /* execute */
13092 0, /* static_pass_number */
13093 TV_COMBINE
, /* tv_id */
13094 PROP_cfglayout
, /* properties_required */
13095 0, /* properties_provided */
13096 0, /* properties_destroyed */
13097 0, /* todo_flags_start */
13099 TODO_df_finish
| TODO_verify_rtl_sharing
|
13100 TODO_ggc_collect
, /* todo_flags_finish */