re PR debug/47994 (-fcompare-debug failure with -O2 -fpeel-loops -fno-rerun-cse-after...
[gcc.git] / gcc / combine.c
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
25
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
31
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
35
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
41
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
44
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
51
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
55
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
64
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
68
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
77
78 #include "config.h"
79 #include "system.h"
80 #include "coretypes.h"
81 #include "tm.h"
82 #include "rtl.h"
83 #include "tree.h"
84 #include "tm_p.h"
85 #include "flags.h"
86 #include "regs.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
90 #include "function.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "expr.h"
93 #include "insn-attr.h"
94 #include "recog.h"
95 #include "diagnostic-core.h"
96 #include "target.h"
97 #include "optabs.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
101 #include "output.h"
102 #include "params.h"
103 #include "timevar.h"
104 #include "tree-pass.h"
105 #include "df.h"
106 #include "cgraph.h"
107 #include "obstack.h"
108
109 /* Number of attempts to combine instructions in this function. */
110
111 static int combine_attempts;
112
113 /* Number of attempts that got as far as substitution in this function. */
114
115 static int combine_merges;
116
117 /* Number of instructions combined with added SETs in this function. */
118
119 static int combine_extras;
120
121 /* Number of instructions combined in this function. */
122
123 static int combine_successes;
124
125 /* Totals over entire compilation. */
126
127 static int total_attempts, total_merges, total_extras, total_successes;
128
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
135
136 static rtx i2mod;
137
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139
140 static rtx i2mod_old_rhs;
141
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143
144 static rtx i2mod_new_rhs;
145 \f
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
148 rtx last_death;
149
150 /* Record last point of modification of (hard or pseudo) register n. */
151 rtx last_set;
152
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
158
159 We use an approach similar to that used by cse, but change it in the
160 following ways:
161
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
165
166 Therefore, we maintain the following fields:
167
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
175 register's value
176
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
180 table.
181
182 (The next two parameters are out of date).
183
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
195
196 /* Record last value assigned to (hard or pseudo) register n. */
197
198 rtx last_set_value;
199
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
202
203 int last_set_table_tick;
204
205 /* Record the value of label_tick when the value for register n is placed in
206 last_set_value. */
207
208 int last_set_label;
209
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
214
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
222
223 char last_set_invalid;
224
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
229
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
233 zero.
234
235 If an entry is zero, it means that we don't know anything special. */
236
237 unsigned char sign_bit_copies;
238
239 unsigned HOST_WIDE_INT nonzero_bits;
240
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
244
245 int truncation_label;
246
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
250 value. */
251
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
253 } reg_stat_type;
254
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
257
258 static VEC(reg_stat_type,heap) *reg_stat;
259
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
262
263 static int mem_last_set;
264
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
267
268 static int last_call_luid;
269
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
275
276 static rtx subst_insn;
277
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
284
285 static int subst_low_luid;
286
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
289
290 static HARD_REG_SET newpat_used_regs;
291
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
294 that location. */
295
296 static rtx added_links_insn;
297
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
301
302 \f
303 /* Length of the currently allocated uid_insn_cost array. */
304
305 static int max_uid_known;
306
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
309
310 static int *uid_insn_cost;
311
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
314
315 struct insn_link {
316 rtx insn;
317 struct insn_link *next;
318 };
319
320 static struct insn_link **uid_log_links;
321
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
324
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
327
328 /* Links for LOG_LINKS are allocated from this obstack. */
329
330 static struct obstack insn_link_obstack;
331
332 /* Allocate a link. */
333
334 static inline struct insn_link *
335 alloc_insn_link (rtx insn, struct insn_link *next)
336 {
337 struct insn_link *l
338 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
339 sizeof (struct insn_link));
340 l->insn = insn;
341 l->next = next;
342 return l;
343 }
344
345 /* Incremented for each basic block. */
346
347 static int label_tick;
348
349 /* Reset to label_tick for each extended basic block in scanning order. */
350
351 static int label_tick_ebb_start;
352
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
355
356 static enum machine_mode nonzero_bits_mode;
357
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
362 in a loop. */
363
364 static int nonzero_sign_valid;
365
366 \f
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
369
370 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
371
372 struct undo
373 {
374 struct undo *next;
375 enum undo_kind kind;
376 union { rtx r; int i; enum machine_mode m; } old_contents;
377 union { rtx *r; int *i; } where;
378 };
379
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
382
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
385
386 struct undobuf
387 {
388 struct undo *undos;
389 struct undo *frees;
390 rtx other_insn;
391 };
392
393 static struct undobuf undobuf;
394
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
397
398 static int n_occurrences;
399
400 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
401 enum machine_mode,
402 unsigned HOST_WIDE_INT,
403 unsigned HOST_WIDE_INT *);
404 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
405 enum machine_mode,
406 unsigned int, unsigned int *);
407 static void do_SUBST (rtx *, rtx);
408 static void do_SUBST_INT (int *, int);
409 static void init_reg_last (void);
410 static void setup_incoming_promotions (rtx);
411 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
412 static int cant_combine_insn_p (rtx);
413 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
414 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
415 static int contains_muldiv (rtx);
416 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
417 static void undo_all (void);
418 static void undo_commit (void);
419 static rtx *find_split_point (rtx *, rtx, bool);
420 static rtx subst (rtx, rtx, rtx, int, int, int);
421 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
422 static rtx simplify_if_then_else (rtx);
423 static rtx simplify_set (rtx);
424 static rtx simplify_logical (rtx);
425 static rtx expand_compound_operation (rtx);
426 static const_rtx expand_field_assignment (const_rtx);
427 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
428 rtx, unsigned HOST_WIDE_INT, int, int, int);
429 static rtx extract_left_shift (rtx, int);
430 static rtx make_compound_operation (rtx, enum rtx_code);
431 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
432 unsigned HOST_WIDE_INT *);
433 static rtx canon_reg_for_combine (rtx, rtx);
434 static rtx force_to_mode (rtx, enum machine_mode,
435 unsigned HOST_WIDE_INT, int);
436 static rtx if_then_else_cond (rtx, rtx *, rtx *);
437 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
438 static int rtx_equal_for_field_assignment_p (rtx, rtx);
439 static rtx make_field_assignment (rtx);
440 static rtx apply_distributive_law (rtx);
441 static rtx distribute_and_simplify_rtx (rtx, int);
442 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
443 unsigned HOST_WIDE_INT);
444 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
445 unsigned HOST_WIDE_INT);
446 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
447 HOST_WIDE_INT, enum machine_mode, int *);
448 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
449 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
450 int);
451 static int recog_for_combine (rtx *, rtx, rtx *);
452 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
453 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
454 static void update_table_tick (rtx);
455 static void record_value_for_reg (rtx, rtx, rtx);
456 static void check_promoted_subreg (rtx, rtx);
457 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
458 static void record_dead_and_set_regs (rtx);
459 static int get_last_value_validate (rtx *, rtx, int, int);
460 static rtx get_last_value (const_rtx);
461 static int use_crosses_set_p (const_rtx, int);
462 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
463 static int reg_dead_at_p (rtx, rtx);
464 static void move_deaths (rtx, rtx, int, rtx, rtx *);
465 static int reg_bitfield_target_p (rtx, rtx);
466 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
467 static void distribute_links (struct insn_link *);
468 static void mark_used_regs_combine (rtx);
469 static void record_promoted_value (rtx, rtx);
470 static int unmentioned_reg_p_1 (rtx *, void *);
471 static bool unmentioned_reg_p (rtx, rtx);
472 static int record_truncated_value (rtx *, void *);
473 static void record_truncated_values (rtx *, void *);
474 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
475 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
476 \f
477
478 /* It is not safe to use ordinary gen_lowpart in combine.
479 See comments in gen_lowpart_for_combine. */
480 #undef RTL_HOOKS_GEN_LOWPART
481 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
482
483 /* Our implementation of gen_lowpart never emits a new pseudo. */
484 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
485 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
486
487 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
488 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
489
490 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
491 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
492
493 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
494 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
495
496 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
497
498 \f
499 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
500 PATTERN can not be split. Otherwise, it returns an insn sequence.
501 This is a wrapper around split_insns which ensures that the
502 reg_stat vector is made larger if the splitter creates a new
503 register. */
504
505 static rtx
506 combine_split_insns (rtx pattern, rtx insn)
507 {
508 rtx ret;
509 unsigned int nregs;
510
511 ret = split_insns (pattern, insn);
512 nregs = max_reg_num ();
513 if (nregs > VEC_length (reg_stat_type, reg_stat))
514 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
515 return ret;
516 }
517
518 /* This is used by find_single_use to locate an rtx in LOC that
519 contains exactly one use of DEST, which is typically either a REG
520 or CC0. It returns a pointer to the innermost rtx expression
521 containing DEST. Appearances of DEST that are being used to
522 totally replace it are not counted. */
523
524 static rtx *
525 find_single_use_1 (rtx dest, rtx *loc)
526 {
527 rtx x = *loc;
528 enum rtx_code code = GET_CODE (x);
529 rtx *result = NULL;
530 rtx *this_result;
531 int i;
532 const char *fmt;
533
534 switch (code)
535 {
536 case CONST_INT:
537 case CONST:
538 case LABEL_REF:
539 case SYMBOL_REF:
540 case CONST_DOUBLE:
541 case CONST_VECTOR:
542 case CLOBBER:
543 return 0;
544
545 case SET:
546 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
547 of a REG that occupies all of the REG, the insn uses DEST if
548 it is mentioned in the destination or the source. Otherwise, we
549 need just check the source. */
550 if (GET_CODE (SET_DEST (x)) != CC0
551 && GET_CODE (SET_DEST (x)) != PC
552 && !REG_P (SET_DEST (x))
553 && ! (GET_CODE (SET_DEST (x)) == SUBREG
554 && REG_P (SUBREG_REG (SET_DEST (x)))
555 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
556 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
557 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
558 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
559 break;
560
561 return find_single_use_1 (dest, &SET_SRC (x));
562
563 case MEM:
564 case SUBREG:
565 return find_single_use_1 (dest, &XEXP (x, 0));
566
567 default:
568 break;
569 }
570
571 /* If it wasn't one of the common cases above, check each expression and
572 vector of this code. Look for a unique usage of DEST. */
573
574 fmt = GET_RTX_FORMAT (code);
575 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
576 {
577 if (fmt[i] == 'e')
578 {
579 if (dest == XEXP (x, i)
580 || (REG_P (dest) && REG_P (XEXP (x, i))
581 && REGNO (dest) == REGNO (XEXP (x, i))))
582 this_result = loc;
583 else
584 this_result = find_single_use_1 (dest, &XEXP (x, i));
585
586 if (result == NULL)
587 result = this_result;
588 else if (this_result)
589 /* Duplicate usage. */
590 return NULL;
591 }
592 else if (fmt[i] == 'E')
593 {
594 int j;
595
596 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
597 {
598 if (XVECEXP (x, i, j) == dest
599 || (REG_P (dest)
600 && REG_P (XVECEXP (x, i, j))
601 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
602 this_result = loc;
603 else
604 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
605
606 if (result == NULL)
607 result = this_result;
608 else if (this_result)
609 return NULL;
610 }
611 }
612 }
613
614 return result;
615 }
616
617
618 /* See if DEST, produced in INSN, is used only a single time in the
619 sequel. If so, return a pointer to the innermost rtx expression in which
620 it is used.
621
622 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
623
624 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
625 care about REG_DEAD notes or LOG_LINKS.
626
627 Otherwise, we find the single use by finding an insn that has a
628 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
629 only referenced once in that insn, we know that it must be the first
630 and last insn referencing DEST. */
631
632 static rtx *
633 find_single_use (rtx dest, rtx insn, rtx *ploc)
634 {
635 basic_block bb;
636 rtx next;
637 rtx *result;
638 struct insn_link *link;
639
640 #ifdef HAVE_cc0
641 if (dest == cc0_rtx)
642 {
643 next = NEXT_INSN (insn);
644 if (next == 0
645 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
646 return 0;
647
648 result = find_single_use_1 (dest, &PATTERN (next));
649 if (result && ploc)
650 *ploc = next;
651 return result;
652 }
653 #endif
654
655 if (!REG_P (dest))
656 return 0;
657
658 bb = BLOCK_FOR_INSN (insn);
659 for (next = NEXT_INSN (insn);
660 next && BLOCK_FOR_INSN (next) == bb;
661 next = NEXT_INSN (next))
662 if (INSN_P (next) && dead_or_set_p (next, dest))
663 {
664 FOR_EACH_LOG_LINK (link, next)
665 if (link->insn == insn)
666 break;
667
668 if (link)
669 {
670 result = find_single_use_1 (dest, &PATTERN (next));
671 if (ploc)
672 *ploc = next;
673 return result;
674 }
675 }
676
677 return 0;
678 }
679 \f
680 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
681 insn. The substitution can be undone by undo_all. If INTO is already
682 set to NEWVAL, do not record this change. Because computing NEWVAL might
683 also call SUBST, we have to compute it before we put anything into
684 the undo table. */
685
686 static void
687 do_SUBST (rtx *into, rtx newval)
688 {
689 struct undo *buf;
690 rtx oldval = *into;
691
692 if (oldval == newval)
693 return;
694
695 /* We'd like to catch as many invalid transformations here as
696 possible. Unfortunately, there are way too many mode changes
697 that are perfectly valid, so we'd waste too much effort for
698 little gain doing the checks here. Focus on catching invalid
699 transformations involving integer constants. */
700 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
701 && CONST_INT_P (newval))
702 {
703 /* Sanity check that we're replacing oldval with a CONST_INT
704 that is a valid sign-extension for the original mode. */
705 gcc_assert (INTVAL (newval)
706 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
707
708 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
709 CONST_INT is not valid, because after the replacement, the
710 original mode would be gone. Unfortunately, we can't tell
711 when do_SUBST is called to replace the operand thereof, so we
712 perform this test on oldval instead, checking whether an
713 invalid replacement took place before we got here. */
714 gcc_assert (!(GET_CODE (oldval) == SUBREG
715 && CONST_INT_P (SUBREG_REG (oldval))));
716 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
717 && CONST_INT_P (XEXP (oldval, 0))));
718 }
719
720 if (undobuf.frees)
721 buf = undobuf.frees, undobuf.frees = buf->next;
722 else
723 buf = XNEW (struct undo);
724
725 buf->kind = UNDO_RTX;
726 buf->where.r = into;
727 buf->old_contents.r = oldval;
728 *into = newval;
729
730 buf->next = undobuf.undos, undobuf.undos = buf;
731 }
732
733 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
734
735 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
736 for the value of a HOST_WIDE_INT value (including CONST_INT) is
737 not safe. */
738
739 static void
740 do_SUBST_INT (int *into, int newval)
741 {
742 struct undo *buf;
743 int oldval = *into;
744
745 if (oldval == newval)
746 return;
747
748 if (undobuf.frees)
749 buf = undobuf.frees, undobuf.frees = buf->next;
750 else
751 buf = XNEW (struct undo);
752
753 buf->kind = UNDO_INT;
754 buf->where.i = into;
755 buf->old_contents.i = oldval;
756 *into = newval;
757
758 buf->next = undobuf.undos, undobuf.undos = buf;
759 }
760
761 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
762
763 /* Similar to SUBST, but just substitute the mode. This is used when
764 changing the mode of a pseudo-register, so that any other
765 references to the entry in the regno_reg_rtx array will change as
766 well. */
767
768 static void
769 do_SUBST_MODE (rtx *into, enum machine_mode newval)
770 {
771 struct undo *buf;
772 enum machine_mode oldval = GET_MODE (*into);
773
774 if (oldval == newval)
775 return;
776
777 if (undobuf.frees)
778 buf = undobuf.frees, undobuf.frees = buf->next;
779 else
780 buf = XNEW (struct undo);
781
782 buf->kind = UNDO_MODE;
783 buf->where.r = into;
784 buf->old_contents.m = oldval;
785 adjust_reg_mode (*into, newval);
786
787 buf->next = undobuf.undos, undobuf.undos = buf;
788 }
789
790 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
791 \f
792 /* Subroutine of try_combine. Determine whether the replacement patterns
793 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
794 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
795 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
796 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
797 of all the instructions can be estimated and the replacements are more
798 expensive than the original sequence. */
799
800 static bool
801 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
802 rtx newi2pat, rtx newotherpat)
803 {
804 int i0_cost, i1_cost, i2_cost, i3_cost;
805 int new_i2_cost, new_i3_cost;
806 int old_cost, new_cost;
807
808 /* Lookup the original insn_rtx_costs. */
809 i2_cost = INSN_COST (i2);
810 i3_cost = INSN_COST (i3);
811
812 if (i1)
813 {
814 i1_cost = INSN_COST (i1);
815 if (i0)
816 {
817 i0_cost = INSN_COST (i0);
818 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
819 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
820 }
821 else
822 {
823 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
824 ? i1_cost + i2_cost + i3_cost : 0);
825 i0_cost = 0;
826 }
827 }
828 else
829 {
830 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
831 i1_cost = i0_cost = 0;
832 }
833
834 /* Calculate the replacement insn_rtx_costs. */
835 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
836 if (newi2pat)
837 {
838 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
839 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
840 ? new_i2_cost + new_i3_cost : 0;
841 }
842 else
843 {
844 new_cost = new_i3_cost;
845 new_i2_cost = 0;
846 }
847
848 if (undobuf.other_insn)
849 {
850 int old_other_cost, new_other_cost;
851
852 old_other_cost = INSN_COST (undobuf.other_insn);
853 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
854 if (old_other_cost > 0 && new_other_cost > 0)
855 {
856 old_cost += old_other_cost;
857 new_cost += new_other_cost;
858 }
859 else
860 old_cost = 0;
861 }
862
863 /* Disallow this combination if both new_cost and old_cost are greater than
864 zero, and new_cost is greater than old cost. */
865 if (old_cost > 0 && new_cost > old_cost)
866 {
867 if (dump_file)
868 {
869 if (i0)
870 {
871 fprintf (dump_file,
872 "rejecting combination of insns %d, %d, %d and %d\n",
873 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
874 INSN_UID (i3));
875 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
876 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
877 }
878 else if (i1)
879 {
880 fprintf (dump_file,
881 "rejecting combination of insns %d, %d and %d\n",
882 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
883 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
884 i1_cost, i2_cost, i3_cost, old_cost);
885 }
886 else
887 {
888 fprintf (dump_file,
889 "rejecting combination of insns %d and %d\n",
890 INSN_UID (i2), INSN_UID (i3));
891 fprintf (dump_file, "original costs %d + %d = %d\n",
892 i2_cost, i3_cost, old_cost);
893 }
894
895 if (newi2pat)
896 {
897 fprintf (dump_file, "replacement costs %d + %d = %d\n",
898 new_i2_cost, new_i3_cost, new_cost);
899 }
900 else
901 fprintf (dump_file, "replacement cost %d\n", new_cost);
902 }
903
904 return false;
905 }
906
907 /* Update the uid_insn_cost array with the replacement costs. */
908 INSN_COST (i2) = new_i2_cost;
909 INSN_COST (i3) = new_i3_cost;
910 if (i1)
911 {
912 INSN_COST (i1) = 0;
913 if (i0)
914 INSN_COST (i0) = 0;
915 }
916
917 return true;
918 }
919
920
921 /* Delete any insns that copy a register to itself. */
922
923 static void
924 delete_noop_moves (void)
925 {
926 rtx insn, next;
927 basic_block bb;
928
929 FOR_EACH_BB (bb)
930 {
931 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
932 {
933 next = NEXT_INSN (insn);
934 if (INSN_P (insn) && noop_move_p (insn))
935 {
936 if (dump_file)
937 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
938
939 delete_insn_and_edges (insn);
940 }
941 }
942 }
943 }
944
945 \f
946 /* Fill in log links field for all insns. */
947
948 static void
949 create_log_links (void)
950 {
951 basic_block bb;
952 rtx *next_use, insn;
953 df_ref *def_vec, *use_vec;
954
955 next_use = XCNEWVEC (rtx, max_reg_num ());
956
957 /* Pass through each block from the end, recording the uses of each
958 register and establishing log links when def is encountered.
959 Note that we do not clear next_use array in order to save time,
960 so we have to test whether the use is in the same basic block as def.
961
962 There are a few cases below when we do not consider the definition or
963 usage -- these are taken from original flow.c did. Don't ask me why it is
964 done this way; I don't know and if it works, I don't want to know. */
965
966 FOR_EACH_BB (bb)
967 {
968 FOR_BB_INSNS_REVERSE (bb, insn)
969 {
970 if (!NONDEBUG_INSN_P (insn))
971 continue;
972
973 /* Log links are created only once. */
974 gcc_assert (!LOG_LINKS (insn));
975
976 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
977 {
978 df_ref def = *def_vec;
979 int regno = DF_REF_REGNO (def);
980 rtx use_insn;
981
982 if (!next_use[regno])
983 continue;
984
985 /* Do not consider if it is pre/post modification in MEM. */
986 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
987 continue;
988
989 /* Do not make the log link for frame pointer. */
990 if ((regno == FRAME_POINTER_REGNUM
991 && (! reload_completed || frame_pointer_needed))
992 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
993 || (regno == HARD_FRAME_POINTER_REGNUM
994 && (! reload_completed || frame_pointer_needed))
995 #endif
996 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
997 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
998 #endif
999 )
1000 continue;
1001
1002 use_insn = next_use[regno];
1003 if (BLOCK_FOR_INSN (use_insn) == bb)
1004 {
1005 /* flow.c claimed:
1006
1007 We don't build a LOG_LINK for hard registers contained
1008 in ASM_OPERANDs. If these registers get replaced,
1009 we might wind up changing the semantics of the insn,
1010 even if reload can make what appear to be valid
1011 assignments later. */
1012 if (regno >= FIRST_PSEUDO_REGISTER
1013 || asm_noperands (PATTERN (use_insn)) < 0)
1014 {
1015 /* Don't add duplicate links between instructions. */
1016 struct insn_link *links;
1017 FOR_EACH_LOG_LINK (links, use_insn)
1018 if (insn == links->insn)
1019 break;
1020
1021 if (!links)
1022 LOG_LINKS (use_insn)
1023 = alloc_insn_link (insn, LOG_LINKS (use_insn));
1024 }
1025 }
1026 next_use[regno] = NULL_RTX;
1027 }
1028
1029 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1030 {
1031 df_ref use = *use_vec;
1032 int regno = DF_REF_REGNO (use);
1033
1034 /* Do not consider the usage of the stack pointer
1035 by function call. */
1036 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1037 continue;
1038
1039 next_use[regno] = insn;
1040 }
1041 }
1042 }
1043
1044 free (next_use);
1045 }
1046
1047 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1048 true if we found a LOG_LINK that proves that A feeds B. This only works
1049 if there are no instructions between A and B which could have a link
1050 depending on A, since in that case we would not record a link for B.
1051 We also check the implicit dependency created by a cc0 setter/user
1052 pair. */
1053
1054 static bool
1055 insn_a_feeds_b (rtx a, rtx b)
1056 {
1057 struct insn_link *links;
1058 FOR_EACH_LOG_LINK (links, b)
1059 if (links->insn == a)
1060 return true;
1061 #ifdef HAVE_cc0
1062 if (sets_cc0_p (a))
1063 return true;
1064 #endif
1065 return false;
1066 }
1067 \f
1068 /* Main entry point for combiner. F is the first insn of the function.
1069 NREGS is the first unused pseudo-reg number.
1070
1071 Return nonzero if the combiner has turned an indirect jump
1072 instruction into a direct jump. */
1073 static int
1074 combine_instructions (rtx f, unsigned int nregs)
1075 {
1076 rtx insn, next;
1077 #ifdef HAVE_cc0
1078 rtx prev;
1079 #endif
1080 struct insn_link *links, *nextlinks;
1081 rtx first;
1082 basic_block last_bb;
1083
1084 int new_direct_jump_p = 0;
1085
1086 for (first = f; first && !INSN_P (first); )
1087 first = NEXT_INSN (first);
1088 if (!first)
1089 return 0;
1090
1091 combine_attempts = 0;
1092 combine_merges = 0;
1093 combine_extras = 0;
1094 combine_successes = 0;
1095
1096 rtl_hooks = combine_rtl_hooks;
1097
1098 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1099
1100 init_recog_no_volatile ();
1101
1102 /* Allocate array for insn info. */
1103 max_uid_known = get_max_uid ();
1104 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1105 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1106 gcc_obstack_init (&insn_link_obstack);
1107
1108 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1109
1110 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1111 problems when, for example, we have j <<= 1 in a loop. */
1112
1113 nonzero_sign_valid = 0;
1114 label_tick = label_tick_ebb_start = 1;
1115
1116 /* Scan all SETs and see if we can deduce anything about what
1117 bits are known to be zero for some registers and how many copies
1118 of the sign bit are known to exist for those registers.
1119
1120 Also set any known values so that we can use it while searching
1121 for what bits are known to be set. */
1122
1123 setup_incoming_promotions (first);
1124 /* Allow the entry block and the first block to fall into the same EBB.
1125 Conceptually the incoming promotions are assigned to the entry block. */
1126 last_bb = ENTRY_BLOCK_PTR;
1127
1128 create_log_links ();
1129 FOR_EACH_BB (this_basic_block)
1130 {
1131 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1132 last_call_luid = 0;
1133 mem_last_set = -1;
1134
1135 label_tick++;
1136 if (!single_pred_p (this_basic_block)
1137 || single_pred (this_basic_block) != last_bb)
1138 label_tick_ebb_start = label_tick;
1139 last_bb = this_basic_block;
1140
1141 FOR_BB_INSNS (this_basic_block, insn)
1142 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1143 {
1144 #ifdef AUTO_INC_DEC
1145 rtx links;
1146 #endif
1147
1148 subst_low_luid = DF_INSN_LUID (insn);
1149 subst_insn = insn;
1150
1151 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1152 insn);
1153 record_dead_and_set_regs (insn);
1154
1155 #ifdef AUTO_INC_DEC
1156 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1157 if (REG_NOTE_KIND (links) == REG_INC)
1158 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1159 insn);
1160 #endif
1161
1162 /* Record the current insn_rtx_cost of this instruction. */
1163 if (NONJUMP_INSN_P (insn))
1164 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1165 optimize_this_for_speed_p);
1166 if (dump_file)
1167 fprintf(dump_file, "insn_cost %d: %d\n",
1168 INSN_UID (insn), INSN_COST (insn));
1169 }
1170 }
1171
1172 nonzero_sign_valid = 1;
1173
1174 /* Now scan all the insns in forward order. */
1175 label_tick = label_tick_ebb_start = 1;
1176 init_reg_last ();
1177 setup_incoming_promotions (first);
1178 last_bb = ENTRY_BLOCK_PTR;
1179
1180 FOR_EACH_BB (this_basic_block)
1181 {
1182 rtx last_combined_insn = NULL_RTX;
1183 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1184 last_call_luid = 0;
1185 mem_last_set = -1;
1186
1187 label_tick++;
1188 if (!single_pred_p (this_basic_block)
1189 || single_pred (this_basic_block) != last_bb)
1190 label_tick_ebb_start = label_tick;
1191 last_bb = this_basic_block;
1192
1193 rtl_profile_for_bb (this_basic_block);
1194 for (insn = BB_HEAD (this_basic_block);
1195 insn != NEXT_INSN (BB_END (this_basic_block));
1196 insn = next ? next : NEXT_INSN (insn))
1197 {
1198 next = 0;
1199 if (NONDEBUG_INSN_P (insn))
1200 {
1201 while (last_combined_insn
1202 && INSN_DELETED_P (last_combined_insn))
1203 last_combined_insn = PREV_INSN (last_combined_insn);
1204 if (last_combined_insn == NULL_RTX
1205 || BARRIER_P (last_combined_insn)
1206 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1207 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1208 last_combined_insn = insn;
1209
1210 /* See if we know about function return values before this
1211 insn based upon SUBREG flags. */
1212 check_promoted_subreg (insn, PATTERN (insn));
1213
1214 /* See if we can find hardregs and subreg of pseudos in
1215 narrower modes. This could help turning TRUNCATEs
1216 into SUBREGs. */
1217 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1218
1219 /* Try this insn with each insn it links back to. */
1220
1221 FOR_EACH_LOG_LINK (links, insn)
1222 if ((next = try_combine (insn, links->insn, NULL_RTX,
1223 NULL_RTX, &new_direct_jump_p,
1224 last_combined_insn)) != 0)
1225 goto retry;
1226
1227 /* Try each sequence of three linked insns ending with this one. */
1228
1229 FOR_EACH_LOG_LINK (links, insn)
1230 {
1231 rtx link = links->insn;
1232
1233 /* If the linked insn has been replaced by a note, then there
1234 is no point in pursuing this chain any further. */
1235 if (NOTE_P (link))
1236 continue;
1237
1238 FOR_EACH_LOG_LINK (nextlinks, link)
1239 if ((next = try_combine (insn, link, nextlinks->insn,
1240 NULL_RTX, &new_direct_jump_p,
1241 last_combined_insn)) != 0)
1242 goto retry;
1243 }
1244
1245 #ifdef HAVE_cc0
1246 /* Try to combine a jump insn that uses CC0
1247 with a preceding insn that sets CC0, and maybe with its
1248 logical predecessor as well.
1249 This is how we make decrement-and-branch insns.
1250 We need this special code because data flow connections
1251 via CC0 do not get entered in LOG_LINKS. */
1252
1253 if (JUMP_P (insn)
1254 && (prev = prev_nonnote_insn (insn)) != 0
1255 && NONJUMP_INSN_P (prev)
1256 && sets_cc0_p (PATTERN (prev)))
1257 {
1258 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1259 &new_direct_jump_p,
1260 last_combined_insn)) != 0)
1261 goto retry;
1262
1263 FOR_EACH_LOG_LINK (nextlinks, prev)
1264 if ((next = try_combine (insn, prev, nextlinks->insn,
1265 NULL_RTX, &new_direct_jump_p,
1266 last_combined_insn)) != 0)
1267 goto retry;
1268 }
1269
1270 /* Do the same for an insn that explicitly references CC0. */
1271 if (NONJUMP_INSN_P (insn)
1272 && (prev = prev_nonnote_insn (insn)) != 0
1273 && NONJUMP_INSN_P (prev)
1274 && sets_cc0_p (PATTERN (prev))
1275 && GET_CODE (PATTERN (insn)) == SET
1276 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1277 {
1278 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1279 &new_direct_jump_p,
1280 last_combined_insn)) != 0)
1281 goto retry;
1282
1283 FOR_EACH_LOG_LINK (nextlinks, prev)
1284 if ((next = try_combine (insn, prev, nextlinks->insn,
1285 NULL_RTX, &new_direct_jump_p,
1286 last_combined_insn)) != 0)
1287 goto retry;
1288 }
1289
1290 /* Finally, see if any of the insns that this insn links to
1291 explicitly references CC0. If so, try this insn, that insn,
1292 and its predecessor if it sets CC0. */
1293 FOR_EACH_LOG_LINK (links, insn)
1294 if (NONJUMP_INSN_P (links->insn)
1295 && GET_CODE (PATTERN (links->insn)) == SET
1296 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1297 && (prev = prev_nonnote_insn (links->insn)) != 0
1298 && NONJUMP_INSN_P (prev)
1299 && sets_cc0_p (PATTERN (prev))
1300 && (next = try_combine (insn, links->insn,
1301 prev, NULL_RTX, &new_direct_jump_p,
1302 last_combined_insn)) != 0)
1303 goto retry;
1304 #endif
1305
1306 /* Try combining an insn with two different insns whose results it
1307 uses. */
1308 FOR_EACH_LOG_LINK (links, insn)
1309 for (nextlinks = links->next; nextlinks;
1310 nextlinks = nextlinks->next)
1311 if ((next = try_combine (insn, links->insn,
1312 nextlinks->insn, NULL_RTX,
1313 &new_direct_jump_p,
1314 last_combined_insn)) != 0)
1315 goto retry;
1316
1317 /* Try four-instruction combinations. */
1318 FOR_EACH_LOG_LINK (links, insn)
1319 {
1320 struct insn_link *next1;
1321 rtx link = links->insn;
1322
1323 /* If the linked insn has been replaced by a note, then there
1324 is no point in pursuing this chain any further. */
1325 if (NOTE_P (link))
1326 continue;
1327
1328 FOR_EACH_LOG_LINK (next1, link)
1329 {
1330 rtx link1 = next1->insn;
1331 if (NOTE_P (link1))
1332 continue;
1333 /* I0 -> I1 -> I2 -> I3. */
1334 FOR_EACH_LOG_LINK (nextlinks, link1)
1335 if ((next = try_combine (insn, link, link1,
1336 nextlinks->insn,
1337 &new_direct_jump_p,
1338 last_combined_insn)) != 0)
1339 goto retry;
1340 /* I0, I1 -> I2, I2 -> I3. */
1341 for (nextlinks = next1->next; nextlinks;
1342 nextlinks = nextlinks->next)
1343 if ((next = try_combine (insn, link, link1,
1344 nextlinks->insn,
1345 &new_direct_jump_p,
1346 last_combined_insn)) != 0)
1347 goto retry;
1348 }
1349
1350 for (next1 = links->next; next1; next1 = next1->next)
1351 {
1352 rtx link1 = next1->insn;
1353 if (NOTE_P (link1))
1354 continue;
1355 /* I0 -> I2; I1, I2 -> I3. */
1356 FOR_EACH_LOG_LINK (nextlinks, link)
1357 if ((next = try_combine (insn, link, link1,
1358 nextlinks->insn,
1359 &new_direct_jump_p,
1360 last_combined_insn)) != 0)
1361 goto retry;
1362 /* I0 -> I1; I1, I2 -> I3. */
1363 FOR_EACH_LOG_LINK (nextlinks, link1)
1364 if ((next = try_combine (insn, link, link1,
1365 nextlinks->insn,
1366 &new_direct_jump_p,
1367 last_combined_insn)) != 0)
1368 goto retry;
1369 }
1370 }
1371
1372 /* Try this insn with each REG_EQUAL note it links back to. */
1373 FOR_EACH_LOG_LINK (links, insn)
1374 {
1375 rtx set, note;
1376 rtx temp = links->insn;
1377 if ((set = single_set (temp)) != 0
1378 && (note = find_reg_equal_equiv_note (temp)) != 0
1379 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1380 /* Avoid using a register that may already been marked
1381 dead by an earlier instruction. */
1382 && ! unmentioned_reg_p (note, SET_SRC (set))
1383 && (GET_MODE (note) == VOIDmode
1384 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1385 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1386 {
1387 /* Temporarily replace the set's source with the
1388 contents of the REG_EQUAL note. The insn will
1389 be deleted or recognized by try_combine. */
1390 rtx orig = SET_SRC (set);
1391 SET_SRC (set) = note;
1392 i2mod = temp;
1393 i2mod_old_rhs = copy_rtx (orig);
1394 i2mod_new_rhs = copy_rtx (note);
1395 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1396 &new_direct_jump_p,
1397 last_combined_insn);
1398 i2mod = NULL_RTX;
1399 if (next)
1400 goto retry;
1401 SET_SRC (set) = orig;
1402 }
1403 }
1404
1405 if (!NOTE_P (insn))
1406 record_dead_and_set_regs (insn);
1407
1408 retry:
1409 ;
1410 }
1411 }
1412 }
1413
1414 default_rtl_profile ();
1415 clear_bb_flags ();
1416 new_direct_jump_p |= purge_all_dead_edges ();
1417 delete_noop_moves ();
1418
1419 /* Clean up. */
1420 obstack_free (&insn_link_obstack, NULL);
1421 free (uid_log_links);
1422 free (uid_insn_cost);
1423 VEC_free (reg_stat_type, heap, reg_stat);
1424
1425 {
1426 struct undo *undo, *next;
1427 for (undo = undobuf.frees; undo; undo = next)
1428 {
1429 next = undo->next;
1430 free (undo);
1431 }
1432 undobuf.frees = 0;
1433 }
1434
1435 total_attempts += combine_attempts;
1436 total_merges += combine_merges;
1437 total_extras += combine_extras;
1438 total_successes += combine_successes;
1439
1440 nonzero_sign_valid = 0;
1441 rtl_hooks = general_rtl_hooks;
1442
1443 /* Make recognizer allow volatile MEMs again. */
1444 init_recog ();
1445
1446 return new_direct_jump_p;
1447 }
1448
1449 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1450
1451 static void
1452 init_reg_last (void)
1453 {
1454 unsigned int i;
1455 reg_stat_type *p;
1456
1457 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1458 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1459 }
1460 \f
1461 /* Set up any promoted values for incoming argument registers. */
1462
1463 static void
1464 setup_incoming_promotions (rtx first)
1465 {
1466 tree arg;
1467 bool strictly_local = false;
1468
1469 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1470 arg = DECL_CHAIN (arg))
1471 {
1472 rtx x, reg = DECL_INCOMING_RTL (arg);
1473 int uns1, uns3;
1474 enum machine_mode mode1, mode2, mode3, mode4;
1475
1476 /* Only continue if the incoming argument is in a register. */
1477 if (!REG_P (reg))
1478 continue;
1479
1480 /* Determine, if possible, whether all call sites of the current
1481 function lie within the current compilation unit. (This does
1482 take into account the exporting of a function via taking its
1483 address, and so forth.) */
1484 strictly_local = cgraph_local_info (current_function_decl)->local;
1485
1486 /* The mode and signedness of the argument before any promotions happen
1487 (equal to the mode of the pseudo holding it at that stage). */
1488 mode1 = TYPE_MODE (TREE_TYPE (arg));
1489 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1490
1491 /* The mode and signedness of the argument after any source language and
1492 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1493 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1494 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1495
1496 /* The mode and signedness of the argument as it is actually passed,
1497 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1498 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1499 TREE_TYPE (cfun->decl), 0);
1500
1501 /* The mode of the register in which the argument is being passed. */
1502 mode4 = GET_MODE (reg);
1503
1504 /* Eliminate sign extensions in the callee when:
1505 (a) A mode promotion has occurred; */
1506 if (mode1 == mode3)
1507 continue;
1508 /* (b) The mode of the register is the same as the mode of
1509 the argument as it is passed; */
1510 if (mode3 != mode4)
1511 continue;
1512 /* (c) There's no language level extension; */
1513 if (mode1 == mode2)
1514 ;
1515 /* (c.1) All callers are from the current compilation unit. If that's
1516 the case we don't have to rely on an ABI, we only have to know
1517 what we're generating right now, and we know that we will do the
1518 mode1 to mode2 promotion with the given sign. */
1519 else if (!strictly_local)
1520 continue;
1521 /* (c.2) The combination of the two promotions is useful. This is
1522 true when the signs match, or if the first promotion is unsigned.
1523 In the later case, (sign_extend (zero_extend x)) is the same as
1524 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1525 else if (uns1)
1526 uns3 = true;
1527 else if (uns3)
1528 continue;
1529
1530 /* Record that the value was promoted from mode1 to mode3,
1531 so that any sign extension at the head of the current
1532 function may be eliminated. */
1533 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1534 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1535 record_value_for_reg (reg, first, x);
1536 }
1537 }
1538
1539 /* Called via note_stores. If X is a pseudo that is narrower than
1540 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1541
1542 If we are setting only a portion of X and we can't figure out what
1543 portion, assume all bits will be used since we don't know what will
1544 be happening.
1545
1546 Similarly, set how many bits of X are known to be copies of the sign bit
1547 at all locations in the function. This is the smallest number implied
1548 by any set of X. */
1549
1550 static void
1551 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1552 {
1553 rtx insn = (rtx) data;
1554 unsigned int num;
1555
1556 if (REG_P (x)
1557 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1558 /* If this register is undefined at the start of the file, we can't
1559 say what its contents were. */
1560 && ! REGNO_REG_SET_P
1561 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1562 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1563 {
1564 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1565
1566 if (set == 0 || GET_CODE (set) == CLOBBER)
1567 {
1568 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1569 rsp->sign_bit_copies = 1;
1570 return;
1571 }
1572
1573 /* If this register is being initialized using itself, and the
1574 register is uninitialized in this basic block, and there are
1575 no LOG_LINKS which set the register, then part of the
1576 register is uninitialized. In that case we can't assume
1577 anything about the number of nonzero bits.
1578
1579 ??? We could do better if we checked this in
1580 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1581 could avoid making assumptions about the insn which initially
1582 sets the register, while still using the information in other
1583 insns. We would have to be careful to check every insn
1584 involved in the combination. */
1585
1586 if (insn
1587 && reg_referenced_p (x, PATTERN (insn))
1588 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1589 REGNO (x)))
1590 {
1591 struct insn_link *link;
1592
1593 FOR_EACH_LOG_LINK (link, insn)
1594 if (dead_or_set_p (link->insn, x))
1595 break;
1596 if (!link)
1597 {
1598 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1599 rsp->sign_bit_copies = 1;
1600 return;
1601 }
1602 }
1603
1604 /* If this is a complex assignment, see if we can convert it into a
1605 simple assignment. */
1606 set = expand_field_assignment (set);
1607
1608 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1609 set what we know about X. */
1610
1611 if (SET_DEST (set) == x
1612 || (GET_CODE (SET_DEST (set)) == SUBREG
1613 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1614 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1615 && SUBREG_REG (SET_DEST (set)) == x))
1616 {
1617 rtx src = SET_SRC (set);
1618
1619 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1620 /* If X is narrower than a word and SRC is a non-negative
1621 constant that would appear negative in the mode of X,
1622 sign-extend it for use in reg_stat[].nonzero_bits because some
1623 machines (maybe most) will actually do the sign-extension
1624 and this is the conservative approach.
1625
1626 ??? For 2.5, try to tighten up the MD files in this regard
1627 instead of this kludge. */
1628
1629 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1630 && CONST_INT_P (src)
1631 && INTVAL (src) > 0
1632 && 0 != (UINTVAL (src)
1633 & ((unsigned HOST_WIDE_INT) 1
1634 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1635 src = GEN_INT (UINTVAL (src)
1636 | ((unsigned HOST_WIDE_INT) (-1)
1637 << GET_MODE_BITSIZE (GET_MODE (x))));
1638 #endif
1639
1640 /* Don't call nonzero_bits if it cannot change anything. */
1641 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1642 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1643 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1644 if (rsp->sign_bit_copies == 0
1645 || rsp->sign_bit_copies > num)
1646 rsp->sign_bit_copies = num;
1647 }
1648 else
1649 {
1650 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1651 rsp->sign_bit_copies = 1;
1652 }
1653 }
1654 }
1655 \f
1656 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1657 optionally insns that were previously combined into I3 or that will be
1658 combined into the merger of INSN and I3. The order is PRED, PRED2,
1659 INSN, SUCC, SUCC2, I3.
1660
1661 Return 0 if the combination is not allowed for any reason.
1662
1663 If the combination is allowed, *PDEST will be set to the single
1664 destination of INSN and *PSRC to the single source, and this function
1665 will return 1. */
1666
1667 static int
1668 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1669 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1670 rtx *pdest, rtx *psrc)
1671 {
1672 int i;
1673 const_rtx set = 0;
1674 rtx src, dest;
1675 rtx p;
1676 #ifdef AUTO_INC_DEC
1677 rtx link;
1678 #endif
1679 bool all_adjacent = true;
1680
1681 if (succ)
1682 {
1683 if (succ2)
1684 {
1685 if (next_active_insn (succ2) != i3)
1686 all_adjacent = false;
1687 if (next_active_insn (succ) != succ2)
1688 all_adjacent = false;
1689 }
1690 else if (next_active_insn (succ) != i3)
1691 all_adjacent = false;
1692 if (next_active_insn (insn) != succ)
1693 all_adjacent = false;
1694 }
1695 else if (next_active_insn (insn) != i3)
1696 all_adjacent = false;
1697
1698 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1699 or a PARALLEL consisting of such a SET and CLOBBERs.
1700
1701 If INSN has CLOBBER parallel parts, ignore them for our processing.
1702 By definition, these happen during the execution of the insn. When it
1703 is merged with another insn, all bets are off. If they are, in fact,
1704 needed and aren't also supplied in I3, they may be added by
1705 recog_for_combine. Otherwise, it won't match.
1706
1707 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1708 note.
1709
1710 Get the source and destination of INSN. If more than one, can't
1711 combine. */
1712
1713 if (GET_CODE (PATTERN (insn)) == SET)
1714 set = PATTERN (insn);
1715 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1716 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1717 {
1718 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1719 {
1720 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1721
1722 switch (GET_CODE (elt))
1723 {
1724 /* This is important to combine floating point insns
1725 for the SH4 port. */
1726 case USE:
1727 /* Combining an isolated USE doesn't make sense.
1728 We depend here on combinable_i3pat to reject them. */
1729 /* The code below this loop only verifies that the inputs of
1730 the SET in INSN do not change. We call reg_set_between_p
1731 to verify that the REG in the USE does not change between
1732 I3 and INSN.
1733 If the USE in INSN was for a pseudo register, the matching
1734 insn pattern will likely match any register; combining this
1735 with any other USE would only be safe if we knew that the
1736 used registers have identical values, or if there was
1737 something to tell them apart, e.g. different modes. For
1738 now, we forgo such complicated tests and simply disallow
1739 combining of USES of pseudo registers with any other USE. */
1740 if (REG_P (XEXP (elt, 0))
1741 && GET_CODE (PATTERN (i3)) == PARALLEL)
1742 {
1743 rtx i3pat = PATTERN (i3);
1744 int i = XVECLEN (i3pat, 0) - 1;
1745 unsigned int regno = REGNO (XEXP (elt, 0));
1746
1747 do
1748 {
1749 rtx i3elt = XVECEXP (i3pat, 0, i);
1750
1751 if (GET_CODE (i3elt) == USE
1752 && REG_P (XEXP (i3elt, 0))
1753 && (REGNO (XEXP (i3elt, 0)) == regno
1754 ? reg_set_between_p (XEXP (elt, 0),
1755 PREV_INSN (insn), i3)
1756 : regno >= FIRST_PSEUDO_REGISTER))
1757 return 0;
1758 }
1759 while (--i >= 0);
1760 }
1761 break;
1762
1763 /* We can ignore CLOBBERs. */
1764 case CLOBBER:
1765 break;
1766
1767 case SET:
1768 /* Ignore SETs whose result isn't used but not those that
1769 have side-effects. */
1770 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1771 && insn_nothrow_p (insn)
1772 && !side_effects_p (elt))
1773 break;
1774
1775 /* If we have already found a SET, this is a second one and
1776 so we cannot combine with this insn. */
1777 if (set)
1778 return 0;
1779
1780 set = elt;
1781 break;
1782
1783 default:
1784 /* Anything else means we can't combine. */
1785 return 0;
1786 }
1787 }
1788
1789 if (set == 0
1790 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1791 so don't do anything with it. */
1792 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1793 return 0;
1794 }
1795 else
1796 return 0;
1797
1798 if (set == 0)
1799 return 0;
1800
1801 set = expand_field_assignment (set);
1802 src = SET_SRC (set), dest = SET_DEST (set);
1803
1804 /* Don't eliminate a store in the stack pointer. */
1805 if (dest == stack_pointer_rtx
1806 /* Don't combine with an insn that sets a register to itself if it has
1807 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1808 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1809 /* Can't merge an ASM_OPERANDS. */
1810 || GET_CODE (src) == ASM_OPERANDS
1811 /* Can't merge a function call. */
1812 || GET_CODE (src) == CALL
1813 /* Don't eliminate a function call argument. */
1814 || (CALL_P (i3)
1815 && (find_reg_fusage (i3, USE, dest)
1816 || (REG_P (dest)
1817 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1818 && global_regs[REGNO (dest)])))
1819 /* Don't substitute into an incremented register. */
1820 || FIND_REG_INC_NOTE (i3, dest)
1821 || (succ && FIND_REG_INC_NOTE (succ, dest))
1822 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1823 /* Don't substitute into a non-local goto, this confuses CFG. */
1824 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1825 /* Make sure that DEST is not used after SUCC but before I3. */
1826 || (!all_adjacent
1827 && ((succ2
1828 && (reg_used_between_p (dest, succ2, i3)
1829 || reg_used_between_p (dest, succ, succ2)))
1830 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1831 /* Make sure that the value that is to be substituted for the register
1832 does not use any registers whose values alter in between. However,
1833 If the insns are adjacent, a use can't cross a set even though we
1834 think it might (this can happen for a sequence of insns each setting
1835 the same destination; last_set of that register might point to
1836 a NOTE). If INSN has a REG_EQUIV note, the register is always
1837 equivalent to the memory so the substitution is valid even if there
1838 are intervening stores. Also, don't move a volatile asm or
1839 UNSPEC_VOLATILE across any other insns. */
1840 || (! all_adjacent
1841 && (((!MEM_P (src)
1842 || ! find_reg_note (insn, REG_EQUIV, src))
1843 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1844 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1845 || GET_CODE (src) == UNSPEC_VOLATILE))
1846 /* Don't combine across a CALL_INSN, because that would possibly
1847 change whether the life span of some REGs crosses calls or not,
1848 and it is a pain to update that information.
1849 Exception: if source is a constant, moving it later can't hurt.
1850 Accept that as a special case. */
1851 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1852 return 0;
1853
1854 /* DEST must either be a REG or CC0. */
1855 if (REG_P (dest))
1856 {
1857 /* If register alignment is being enforced for multi-word items in all
1858 cases except for parameters, it is possible to have a register copy
1859 insn referencing a hard register that is not allowed to contain the
1860 mode being copied and which would not be valid as an operand of most
1861 insns. Eliminate this problem by not combining with such an insn.
1862
1863 Also, on some machines we don't want to extend the life of a hard
1864 register. */
1865
1866 if (REG_P (src)
1867 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1868 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1869 /* Don't extend the life of a hard register unless it is
1870 user variable (if we have few registers) or it can't
1871 fit into the desired register (meaning something special
1872 is going on).
1873 Also avoid substituting a return register into I3, because
1874 reload can't handle a conflict with constraints of other
1875 inputs. */
1876 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1877 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1878 return 0;
1879 }
1880 else if (GET_CODE (dest) != CC0)
1881 return 0;
1882
1883
1884 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1885 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1886 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1887 {
1888 /* Don't substitute for a register intended as a clobberable
1889 operand. */
1890 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1891 if (rtx_equal_p (reg, dest))
1892 return 0;
1893
1894 /* If the clobber represents an earlyclobber operand, we must not
1895 substitute an expression containing the clobbered register.
1896 As we do not analyze the constraint strings here, we have to
1897 make the conservative assumption. However, if the register is
1898 a fixed hard reg, the clobber cannot represent any operand;
1899 we leave it up to the machine description to either accept or
1900 reject use-and-clobber patterns. */
1901 if (!REG_P (reg)
1902 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1903 || !fixed_regs[REGNO (reg)])
1904 if (reg_overlap_mentioned_p (reg, src))
1905 return 0;
1906 }
1907
1908 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1909 or not), reject, unless nothing volatile comes between it and I3 */
1910
1911 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1912 {
1913 /* Make sure neither succ nor succ2 contains a volatile reference. */
1914 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1915 return 0;
1916 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1917 return 0;
1918 /* We'll check insns between INSN and I3 below. */
1919 }
1920
1921 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1922 to be an explicit register variable, and was chosen for a reason. */
1923
1924 if (GET_CODE (src) == ASM_OPERANDS
1925 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1926 return 0;
1927
1928 /* If there are any volatile insns between INSN and I3, reject, because
1929 they might affect machine state. */
1930
1931 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1932 if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
1933 return 0;
1934
1935 /* If INSN contains an autoincrement or autodecrement, make sure that
1936 register is not used between there and I3, and not already used in
1937 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1938 Also insist that I3 not be a jump; if it were one
1939 and the incremented register were spilled, we would lose. */
1940
1941 #ifdef AUTO_INC_DEC
1942 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1943 if (REG_NOTE_KIND (link) == REG_INC
1944 && (JUMP_P (i3)
1945 || reg_used_between_p (XEXP (link, 0), insn, i3)
1946 || (pred != NULL_RTX
1947 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1948 || (pred2 != NULL_RTX
1949 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1950 || (succ != NULL_RTX
1951 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1952 || (succ2 != NULL_RTX
1953 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1954 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1955 return 0;
1956 #endif
1957
1958 #ifdef HAVE_cc0
1959 /* Don't combine an insn that follows a CC0-setting insn.
1960 An insn that uses CC0 must not be separated from the one that sets it.
1961 We do, however, allow I2 to follow a CC0-setting insn if that insn
1962 is passed as I1; in that case it will be deleted also.
1963 We also allow combining in this case if all the insns are adjacent
1964 because that would leave the two CC0 insns adjacent as well.
1965 It would be more logical to test whether CC0 occurs inside I1 or I2,
1966 but that would be much slower, and this ought to be equivalent. */
1967
1968 p = prev_nonnote_insn (insn);
1969 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1970 && ! all_adjacent)
1971 return 0;
1972 #endif
1973
1974 /* If we get here, we have passed all the tests and the combination is
1975 to be allowed. */
1976
1977 *pdest = dest;
1978 *psrc = src;
1979
1980 return 1;
1981 }
1982 \f
1983 /* LOC is the location within I3 that contains its pattern or the component
1984 of a PARALLEL of the pattern. We validate that it is valid for combining.
1985
1986 One problem is if I3 modifies its output, as opposed to replacing it
1987 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1988 doing so would produce an insn that is not equivalent to the original insns.
1989
1990 Consider:
1991
1992 (set (reg:DI 101) (reg:DI 100))
1993 (set (subreg:SI (reg:DI 101) 0) <foo>)
1994
1995 This is NOT equivalent to:
1996
1997 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1998 (set (reg:DI 101) (reg:DI 100))])
1999
2000 Not only does this modify 100 (in which case it might still be valid
2001 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2002
2003 We can also run into a problem if I2 sets a register that I1
2004 uses and I1 gets directly substituted into I3 (not via I2). In that
2005 case, we would be getting the wrong value of I2DEST into I3, so we
2006 must reject the combination. This case occurs when I2 and I1 both
2007 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2008 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2009 of a SET must prevent combination from occurring. The same situation
2010 can occur for I0, in which case I0_NOT_IN_SRC is set.
2011
2012 Before doing the above check, we first try to expand a field assignment
2013 into a set of logical operations.
2014
2015 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2016 we place a register that is both set and used within I3. If more than one
2017 such register is detected, we fail.
2018
2019 Return 1 if the combination is valid, zero otherwise. */
2020
2021 static int
2022 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2023 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2024 {
2025 rtx x = *loc;
2026
2027 if (GET_CODE (x) == SET)
2028 {
2029 rtx set = x ;
2030 rtx dest = SET_DEST (set);
2031 rtx src = SET_SRC (set);
2032 rtx inner_dest = dest;
2033 rtx subdest;
2034
2035 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2036 || GET_CODE (inner_dest) == SUBREG
2037 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2038 inner_dest = XEXP (inner_dest, 0);
2039
2040 /* Check for the case where I3 modifies its output, as discussed
2041 above. We don't want to prevent pseudos from being combined
2042 into the address of a MEM, so only prevent the combination if
2043 i1 or i2 set the same MEM. */
2044 if ((inner_dest != dest &&
2045 (!MEM_P (inner_dest)
2046 || rtx_equal_p (i2dest, inner_dest)
2047 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2048 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2049 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2050 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2051 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2052
2053 /* This is the same test done in can_combine_p except we can't test
2054 all_adjacent; we don't have to, since this instruction will stay
2055 in place, thus we are not considering increasing the lifetime of
2056 INNER_DEST.
2057
2058 Also, if this insn sets a function argument, combining it with
2059 something that might need a spill could clobber a previous
2060 function argument; the all_adjacent test in can_combine_p also
2061 checks this; here, we do a more specific test for this case. */
2062
2063 || (REG_P (inner_dest)
2064 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2065 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2066 GET_MODE (inner_dest))))
2067 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2068 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2069 return 0;
2070
2071 /* If DEST is used in I3, it is being killed in this insn, so
2072 record that for later. We have to consider paradoxical
2073 subregs here, since they kill the whole register, but we
2074 ignore partial subregs, STRICT_LOW_PART, etc.
2075 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2076 STACK_POINTER_REGNUM, since these are always considered to be
2077 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2078 subdest = dest;
2079 if (GET_CODE (subdest) == SUBREG
2080 && (GET_MODE_SIZE (GET_MODE (subdest))
2081 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2082 subdest = SUBREG_REG (subdest);
2083 if (pi3dest_killed
2084 && REG_P (subdest)
2085 && reg_referenced_p (subdest, PATTERN (i3))
2086 && REGNO (subdest) != FRAME_POINTER_REGNUM
2087 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2088 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2089 #endif
2090 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2091 && (REGNO (subdest) != ARG_POINTER_REGNUM
2092 || ! fixed_regs [REGNO (subdest)])
2093 #endif
2094 && REGNO (subdest) != STACK_POINTER_REGNUM)
2095 {
2096 if (*pi3dest_killed)
2097 return 0;
2098
2099 *pi3dest_killed = subdest;
2100 }
2101 }
2102
2103 else if (GET_CODE (x) == PARALLEL)
2104 {
2105 int i;
2106
2107 for (i = 0; i < XVECLEN (x, 0); i++)
2108 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2109 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2110 return 0;
2111 }
2112
2113 return 1;
2114 }
2115 \f
2116 /* Return 1 if X is an arithmetic expression that contains a multiplication
2117 and division. We don't count multiplications by powers of two here. */
2118
2119 static int
2120 contains_muldiv (rtx x)
2121 {
2122 switch (GET_CODE (x))
2123 {
2124 case MOD: case DIV: case UMOD: case UDIV:
2125 return 1;
2126
2127 case MULT:
2128 return ! (CONST_INT_P (XEXP (x, 1))
2129 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2130 default:
2131 if (BINARY_P (x))
2132 return contains_muldiv (XEXP (x, 0))
2133 || contains_muldiv (XEXP (x, 1));
2134
2135 if (UNARY_P (x))
2136 return contains_muldiv (XEXP (x, 0));
2137
2138 return 0;
2139 }
2140 }
2141 \f
2142 /* Determine whether INSN can be used in a combination. Return nonzero if
2143 not. This is used in try_combine to detect early some cases where we
2144 can't perform combinations. */
2145
2146 static int
2147 cant_combine_insn_p (rtx insn)
2148 {
2149 rtx set;
2150 rtx src, dest;
2151
2152 /* If this isn't really an insn, we can't do anything.
2153 This can occur when flow deletes an insn that it has merged into an
2154 auto-increment address. */
2155 if (! INSN_P (insn))
2156 return 1;
2157
2158 /* Never combine loads and stores involving hard regs that are likely
2159 to be spilled. The register allocator can usually handle such
2160 reg-reg moves by tying. If we allow the combiner to make
2161 substitutions of likely-spilled regs, reload might die.
2162 As an exception, we allow combinations involving fixed regs; these are
2163 not available to the register allocator so there's no risk involved. */
2164
2165 set = single_set (insn);
2166 if (! set)
2167 return 0;
2168 src = SET_SRC (set);
2169 dest = SET_DEST (set);
2170 if (GET_CODE (src) == SUBREG)
2171 src = SUBREG_REG (src);
2172 if (GET_CODE (dest) == SUBREG)
2173 dest = SUBREG_REG (dest);
2174 if (REG_P (src) && REG_P (dest)
2175 && ((HARD_REGISTER_P (src)
2176 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2177 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2178 || (HARD_REGISTER_P (dest)
2179 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2180 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2181 return 1;
2182
2183 return 0;
2184 }
2185
2186 struct likely_spilled_retval_info
2187 {
2188 unsigned regno, nregs;
2189 unsigned mask;
2190 };
2191
2192 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2193 hard registers that are known to be written to / clobbered in full. */
2194 static void
2195 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2196 {
2197 struct likely_spilled_retval_info *const info =
2198 (struct likely_spilled_retval_info *) data;
2199 unsigned regno, nregs;
2200 unsigned new_mask;
2201
2202 if (!REG_P (XEXP (set, 0)))
2203 return;
2204 regno = REGNO (x);
2205 if (regno >= info->regno + info->nregs)
2206 return;
2207 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2208 if (regno + nregs <= info->regno)
2209 return;
2210 new_mask = (2U << (nregs - 1)) - 1;
2211 if (regno < info->regno)
2212 new_mask >>= info->regno - regno;
2213 else
2214 new_mask <<= regno - info->regno;
2215 info->mask &= ~new_mask;
2216 }
2217
2218 /* Return nonzero iff part of the return value is live during INSN, and
2219 it is likely spilled. This can happen when more than one insn is needed
2220 to copy the return value, e.g. when we consider to combine into the
2221 second copy insn for a complex value. */
2222
2223 static int
2224 likely_spilled_retval_p (rtx insn)
2225 {
2226 rtx use = BB_END (this_basic_block);
2227 rtx reg, p;
2228 unsigned regno, nregs;
2229 /* We assume here that no machine mode needs more than
2230 32 hard registers when the value overlaps with a register
2231 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2232 unsigned mask;
2233 struct likely_spilled_retval_info info;
2234
2235 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2236 return 0;
2237 reg = XEXP (PATTERN (use), 0);
2238 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2239 return 0;
2240 regno = REGNO (reg);
2241 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2242 if (nregs == 1)
2243 return 0;
2244 mask = (2U << (nregs - 1)) - 1;
2245
2246 /* Disregard parts of the return value that are set later. */
2247 info.regno = regno;
2248 info.nregs = nregs;
2249 info.mask = mask;
2250 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2251 if (INSN_P (p))
2252 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2253 mask = info.mask;
2254
2255 /* Check if any of the (probably) live return value registers is
2256 likely spilled. */
2257 nregs --;
2258 do
2259 {
2260 if ((mask & 1 << nregs)
2261 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2262 return 1;
2263 } while (nregs--);
2264 return 0;
2265 }
2266
2267 /* Adjust INSN after we made a change to its destination.
2268
2269 Changing the destination can invalidate notes that say something about
2270 the results of the insn and a LOG_LINK pointing to the insn. */
2271
2272 static void
2273 adjust_for_new_dest (rtx insn)
2274 {
2275 /* For notes, be conservative and simply remove them. */
2276 remove_reg_equal_equiv_notes (insn);
2277
2278 /* The new insn will have a destination that was previously the destination
2279 of an insn just above it. Call distribute_links to make a LOG_LINK from
2280 the next use of that destination. */
2281 distribute_links (alloc_insn_link (insn, NULL));
2282
2283 df_insn_rescan (insn);
2284 }
2285
2286 /* Return TRUE if combine can reuse reg X in mode MODE.
2287 ADDED_SETS is nonzero if the original set is still required. */
2288 static bool
2289 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2290 {
2291 unsigned int regno;
2292
2293 if (!REG_P(x))
2294 return false;
2295
2296 regno = REGNO (x);
2297 /* Allow hard registers if the new mode is legal, and occupies no more
2298 registers than the old mode. */
2299 if (regno < FIRST_PSEUDO_REGISTER)
2300 return (HARD_REGNO_MODE_OK (regno, mode)
2301 && (hard_regno_nregs[regno][GET_MODE (x)]
2302 >= hard_regno_nregs[regno][mode]));
2303
2304 /* Or a pseudo that is only used once. */
2305 return (REG_N_SETS (regno) == 1 && !added_sets
2306 && !REG_USERVAR_P (x));
2307 }
2308
2309
2310 /* Check whether X, the destination of a set, refers to part of
2311 the register specified by REG. */
2312
2313 static bool
2314 reg_subword_p (rtx x, rtx reg)
2315 {
2316 /* Check that reg is an integer mode register. */
2317 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2318 return false;
2319
2320 if (GET_CODE (x) == STRICT_LOW_PART
2321 || GET_CODE (x) == ZERO_EXTRACT)
2322 x = XEXP (x, 0);
2323
2324 return GET_CODE (x) == SUBREG
2325 && SUBREG_REG (x) == reg
2326 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2327 }
2328
2329 #ifdef AUTO_INC_DEC
2330 /* Replace auto-increment addressing modes with explicit operations to access
2331 the same addresses without modifying the corresponding registers. */
2332
2333 static rtx
2334 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2335 {
2336 rtx x = src;
2337 const RTX_CODE code = GET_CODE (x);
2338 int i;
2339 const char *fmt;
2340
2341 switch (code)
2342 {
2343 case REG:
2344 case CONST_INT:
2345 case CONST_DOUBLE:
2346 case CONST_FIXED:
2347 case CONST_VECTOR:
2348 case SYMBOL_REF:
2349 case CODE_LABEL:
2350 case PC:
2351 case CC0:
2352 case SCRATCH:
2353 /* SCRATCH must be shared because they represent distinct values. */
2354 return x;
2355 case CLOBBER:
2356 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2357 return x;
2358 break;
2359
2360 case CONST:
2361 if (shared_const_p (x))
2362 return x;
2363 break;
2364
2365 case MEM:
2366 mem_mode = GET_MODE (x);
2367 break;
2368
2369 case PRE_INC:
2370 case PRE_DEC:
2371 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2372 return gen_rtx_PLUS (GET_MODE (x),
2373 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2374 GEN_INT (code == PRE_INC
2375 ? GET_MODE_SIZE (mem_mode)
2376 : -GET_MODE_SIZE (mem_mode)));
2377
2378 case POST_INC:
2379 case POST_DEC:
2380 case PRE_MODIFY:
2381 case POST_MODIFY:
2382 return cleanup_auto_inc_dec (code == PRE_MODIFY
2383 ? XEXP (x, 1) : XEXP (x, 0),
2384 mem_mode);
2385
2386 default:
2387 break;
2388 }
2389
2390 /* Copy the various flags, fields, and other information. We assume
2391 that all fields need copying, and then clear the fields that should
2392 not be copied. That is the sensible default behavior, and forces
2393 us to explicitly document why we are *not* copying a flag. */
2394 x = shallow_copy_rtx (x);
2395
2396 /* We do not copy the USED flag, which is used as a mark bit during
2397 walks over the RTL. */
2398 RTX_FLAG (x, used) = 0;
2399
2400 /* We do not copy FRAME_RELATED for INSNs. */
2401 if (INSN_P (x))
2402 RTX_FLAG (x, frame_related) = 0;
2403
2404 fmt = GET_RTX_FORMAT (code);
2405 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2406 if (fmt[i] == 'e')
2407 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2408 else if (fmt[i] == 'E' || fmt[i] == 'V')
2409 {
2410 int j;
2411 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2412 for (j = 0; j < XVECLEN (x, i); j++)
2413 XVECEXP (x, i, j)
2414 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2415 }
2416
2417 return x;
2418 }
2419 #endif
2420
2421 /* Auxiliary data structure for propagate_for_debug_stmt. */
2422
2423 struct rtx_subst_pair
2424 {
2425 rtx to;
2426 bool adjusted;
2427 };
2428
2429 /* DATA points to an rtx_subst_pair. Return the value that should be
2430 substituted. */
2431
2432 static rtx
2433 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2434 {
2435 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2436
2437 if (!rtx_equal_p (from, old_rtx))
2438 return NULL_RTX;
2439 if (!pair->adjusted)
2440 {
2441 pair->adjusted = true;
2442 #ifdef AUTO_INC_DEC
2443 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2444 #else
2445 pair->to = copy_rtx (pair->to);
2446 #endif
2447 pair->to = make_compound_operation (pair->to, SET);
2448 return pair->to;
2449 }
2450 return copy_rtx (pair->to);
2451 }
2452
2453 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2454 and LAST, not including INSN, but including LAST. Also stop at the end
2455 of THIS_BASIC_BLOCK. */
2456
2457 static void
2458 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2459 {
2460 rtx next, loc, end = NEXT_INSN (BB_END (this_basic_block));
2461
2462 struct rtx_subst_pair p;
2463 p.to = src;
2464 p.adjusted = false;
2465
2466 next = NEXT_INSN (insn);
2467 last = NEXT_INSN (last);
2468 while (next != last && next != end)
2469 {
2470 insn = next;
2471 next = NEXT_INSN (insn);
2472 if (DEBUG_INSN_P (insn))
2473 {
2474 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2475 dest, propagate_for_debug_subst, &p);
2476 if (loc == INSN_VAR_LOCATION_LOC (insn))
2477 continue;
2478 INSN_VAR_LOCATION_LOC (insn) = loc;
2479 df_insn_rescan (insn);
2480 }
2481 }
2482 }
2483
2484 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2485 Note that the INSN should be deleted *after* removing dead edges, so
2486 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2487 but not for a (set (pc) (label_ref FOO)). */
2488
2489 static void
2490 update_cfg_for_uncondjump (rtx insn)
2491 {
2492 basic_block bb = BLOCK_FOR_INSN (insn);
2493 gcc_assert (BB_END (bb) == insn);
2494
2495 purge_dead_edges (bb);
2496
2497 delete_insn (insn);
2498 if (EDGE_COUNT (bb->succs) == 1)
2499 {
2500 rtx insn;
2501
2502 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2503
2504 /* Remove barriers from the footer if there are any. */
2505 for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2506 if (BARRIER_P (insn))
2507 {
2508 if (PREV_INSN (insn))
2509 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2510 else
2511 bb->il.rtl->footer = NEXT_INSN (insn);
2512 if (NEXT_INSN (insn))
2513 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2514 }
2515 else if (LABEL_P (insn))
2516 break;
2517 }
2518 }
2519
2520 /* Try to combine the insns I0, I1 and I2 into I3.
2521 Here I0, I1 and I2 appear earlier than I3.
2522 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2523 I3.
2524
2525 If we are combining more than two insns and the resulting insn is not
2526 recognized, try splitting it into two insns. If that happens, I2 and I3
2527 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2528 Otherwise, I0, I1 and I2 are pseudo-deleted.
2529
2530 Return 0 if the combination does not work. Then nothing is changed.
2531 If we did the combination, return the insn at which combine should
2532 resume scanning.
2533
2534 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2535 new direct jump instruction.
2536
2537 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2538 been I3 passed to an earlier try_combine within the same basic
2539 block. */
2540
2541 static rtx
2542 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2543 rtx last_combined_insn)
2544 {
2545 /* New patterns for I3 and I2, respectively. */
2546 rtx newpat, newi2pat = 0;
2547 rtvec newpat_vec_with_clobbers = 0;
2548 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2549 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2550 dead. */
2551 int added_sets_0, added_sets_1, added_sets_2;
2552 /* Total number of SETs to put into I3. */
2553 int total_sets;
2554 /* Nonzero if I2's or I1's body now appears in I3. */
2555 int i2_is_used = 0, i1_is_used = 0;
2556 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2557 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2558 /* Contains I3 if the destination of I3 is used in its source, which means
2559 that the old life of I3 is being killed. If that usage is placed into
2560 I2 and not in I3, a REG_DEAD note must be made. */
2561 rtx i3dest_killed = 0;
2562 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2563 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2564 /* Copy of SET_SRC of I1, if needed. */
2565 rtx i1src_copy = 0;
2566 /* Set if I2DEST was reused as a scratch register. */
2567 bool i2scratch = false;
2568 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2569 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2570 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2571 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2572 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2573 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2574 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2575 /* Notes that must be added to REG_NOTES in I3 and I2. */
2576 rtx new_i3_notes, new_i2_notes;
2577 /* Notes that we substituted I3 into I2 instead of the normal case. */
2578 int i3_subst_into_i2 = 0;
2579 /* Notes that I1, I2 or I3 is a MULT operation. */
2580 int have_mult = 0;
2581 int swap_i2i3 = 0;
2582 int changed_i3_dest = 0;
2583
2584 int maxreg;
2585 rtx temp;
2586 struct insn_link *link;
2587 rtx other_pat = 0;
2588 rtx new_other_notes;
2589 int i;
2590
2591 /* Only try four-insn combinations when there's high likelihood of
2592 success. Look for simple insns, such as loads of constants or
2593 binary operations involving a constant. */
2594 if (i0)
2595 {
2596 int i;
2597 int ngood = 0;
2598 int nshift = 0;
2599
2600 if (!flag_expensive_optimizations)
2601 return 0;
2602
2603 for (i = 0; i < 4; i++)
2604 {
2605 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2606 rtx set = single_set (insn);
2607 rtx src;
2608 if (!set)
2609 continue;
2610 src = SET_SRC (set);
2611 if (CONSTANT_P (src))
2612 {
2613 ngood += 2;
2614 break;
2615 }
2616 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2617 ngood++;
2618 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2619 || GET_CODE (src) == LSHIFTRT)
2620 nshift++;
2621 }
2622 if (ngood < 2 && nshift < 2)
2623 return 0;
2624 }
2625
2626 /* Exit early if one of the insns involved can't be used for
2627 combinations. */
2628 if (cant_combine_insn_p (i3)
2629 || cant_combine_insn_p (i2)
2630 || (i1 && cant_combine_insn_p (i1))
2631 || (i0 && cant_combine_insn_p (i0))
2632 || likely_spilled_retval_p (i3))
2633 return 0;
2634
2635 combine_attempts++;
2636 undobuf.other_insn = 0;
2637
2638 /* Reset the hard register usage information. */
2639 CLEAR_HARD_REG_SET (newpat_used_regs);
2640
2641 if (dump_file && (dump_flags & TDF_DETAILS))
2642 {
2643 if (i0)
2644 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2645 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2646 else if (i1)
2647 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2648 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2649 else
2650 fprintf (dump_file, "\nTrying %d -> %d:\n",
2651 INSN_UID (i2), INSN_UID (i3));
2652 }
2653
2654 /* If multiple insns feed into one of I2 or I3, they can be in any
2655 order. To simplify the code below, reorder them in sequence. */
2656 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2657 temp = i2, i2 = i0, i0 = temp;
2658 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2659 temp = i1, i1 = i0, i0 = temp;
2660 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2661 temp = i1, i1 = i2, i2 = temp;
2662
2663 added_links_insn = 0;
2664
2665 /* First check for one important special case that the code below will
2666 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2667 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2668 we may be able to replace that destination with the destination of I3.
2669 This occurs in the common code where we compute both a quotient and
2670 remainder into a structure, in which case we want to do the computation
2671 directly into the structure to avoid register-register copies.
2672
2673 Note that this case handles both multiple sets in I2 and also cases
2674 where I2 has a number of CLOBBERs inside the PARALLEL.
2675
2676 We make very conservative checks below and only try to handle the
2677 most common cases of this. For example, we only handle the case
2678 where I2 and I3 are adjacent to avoid making difficult register
2679 usage tests. */
2680
2681 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2682 && REG_P (SET_SRC (PATTERN (i3)))
2683 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2684 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2685 && GET_CODE (PATTERN (i2)) == PARALLEL
2686 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2687 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2688 below would need to check what is inside (and reg_overlap_mentioned_p
2689 doesn't support those codes anyway). Don't allow those destinations;
2690 the resulting insn isn't likely to be recognized anyway. */
2691 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2692 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2693 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2694 SET_DEST (PATTERN (i3)))
2695 && next_active_insn (i2) == i3)
2696 {
2697 rtx p2 = PATTERN (i2);
2698
2699 /* Make sure that the destination of I3,
2700 which we are going to substitute into one output of I2,
2701 is not used within another output of I2. We must avoid making this:
2702 (parallel [(set (mem (reg 69)) ...)
2703 (set (reg 69) ...)])
2704 which is not well-defined as to order of actions.
2705 (Besides, reload can't handle output reloads for this.)
2706
2707 The problem can also happen if the dest of I3 is a memory ref,
2708 if another dest in I2 is an indirect memory ref. */
2709 for (i = 0; i < XVECLEN (p2, 0); i++)
2710 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2711 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2712 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2713 SET_DEST (XVECEXP (p2, 0, i))))
2714 break;
2715
2716 if (i == XVECLEN (p2, 0))
2717 for (i = 0; i < XVECLEN (p2, 0); i++)
2718 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2719 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2720 {
2721 combine_merges++;
2722
2723 subst_insn = i3;
2724 subst_low_luid = DF_INSN_LUID (i2);
2725
2726 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2727 i2src = SET_SRC (XVECEXP (p2, 0, i));
2728 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2729 i2dest_killed = dead_or_set_p (i2, i2dest);
2730
2731 /* Replace the dest in I2 with our dest and make the resulting
2732 insn the new pattern for I3. Then skip to where we validate
2733 the pattern. Everything was set up above. */
2734 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2735 newpat = p2;
2736 i3_subst_into_i2 = 1;
2737 goto validate_replacement;
2738 }
2739 }
2740
2741 /* If I2 is setting a pseudo to a constant and I3 is setting some
2742 sub-part of it to another constant, merge them by making a new
2743 constant. */
2744 if (i1 == 0
2745 && (temp = single_set (i2)) != 0
2746 && (CONST_INT_P (SET_SRC (temp))
2747 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2748 && GET_CODE (PATTERN (i3)) == SET
2749 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2750 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2751 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2752 {
2753 rtx dest = SET_DEST (PATTERN (i3));
2754 int offset = -1;
2755 int width = 0;
2756
2757 if (GET_CODE (dest) == ZERO_EXTRACT)
2758 {
2759 if (CONST_INT_P (XEXP (dest, 1))
2760 && CONST_INT_P (XEXP (dest, 2)))
2761 {
2762 width = INTVAL (XEXP (dest, 1));
2763 offset = INTVAL (XEXP (dest, 2));
2764 dest = XEXP (dest, 0);
2765 if (BITS_BIG_ENDIAN)
2766 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2767 }
2768 }
2769 else
2770 {
2771 if (GET_CODE (dest) == STRICT_LOW_PART)
2772 dest = XEXP (dest, 0);
2773 width = GET_MODE_BITSIZE (GET_MODE (dest));
2774 offset = 0;
2775 }
2776
2777 if (offset >= 0)
2778 {
2779 /* If this is the low part, we're done. */
2780 if (subreg_lowpart_p (dest))
2781 ;
2782 /* Handle the case where inner is twice the size of outer. */
2783 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2784 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2785 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2786 /* Otherwise give up for now. */
2787 else
2788 offset = -1;
2789 }
2790
2791 if (offset >= 0
2792 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2793 <= HOST_BITS_PER_DOUBLE_INT))
2794 {
2795 double_int m, o, i;
2796 rtx inner = SET_SRC (PATTERN (i3));
2797 rtx outer = SET_SRC (temp);
2798
2799 o = rtx_to_double_int (outer);
2800 i = rtx_to_double_int (inner);
2801
2802 m = double_int_mask (width);
2803 i = double_int_and (i, m);
2804 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2805 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2806 o = double_int_ior (double_int_and_not (o, m), i);
2807
2808 combine_merges++;
2809 subst_insn = i3;
2810 subst_low_luid = DF_INSN_LUID (i2);
2811 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2812 i2dest = SET_DEST (temp);
2813 i2dest_killed = dead_or_set_p (i2, i2dest);
2814
2815 /* Replace the source in I2 with the new constant and make the
2816 resulting insn the new pattern for I3. Then skip to where we
2817 validate the pattern. Everything was set up above. */
2818 SUBST (SET_SRC (temp),
2819 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2820
2821 newpat = PATTERN (i2);
2822
2823 /* The dest of I3 has been replaced with the dest of I2. */
2824 changed_i3_dest = 1;
2825 goto validate_replacement;
2826 }
2827 }
2828
2829 #ifndef HAVE_cc0
2830 /* If we have no I1 and I2 looks like:
2831 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2832 (set Y OP)])
2833 make up a dummy I1 that is
2834 (set Y OP)
2835 and change I2 to be
2836 (set (reg:CC X) (compare:CC Y (const_int 0)))
2837
2838 (We can ignore any trailing CLOBBERs.)
2839
2840 This undoes a previous combination and allows us to match a branch-and-
2841 decrement insn. */
2842
2843 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2844 && XVECLEN (PATTERN (i2), 0) >= 2
2845 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2846 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2847 == MODE_CC)
2848 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2849 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2850 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2851 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2852 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2853 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2854 {
2855 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2856 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2857 break;
2858
2859 if (i == 1)
2860 {
2861 /* We make I1 with the same INSN_UID as I2. This gives it
2862 the same DF_INSN_LUID for value tracking. Our fake I1 will
2863 never appear in the insn stream so giving it the same INSN_UID
2864 as I2 will not cause a problem. */
2865
2866 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2867 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2868 INSN_LOCATOR (i2), -1, NULL_RTX);
2869
2870 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2871 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2872 SET_DEST (PATTERN (i1)));
2873 }
2874 }
2875 #endif
2876
2877 /* Verify that I2 and I1 are valid for combining. */
2878 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2879 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2880 &i1dest, &i1src))
2881 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2882 &i0dest, &i0src)))
2883 {
2884 undo_all ();
2885 return 0;
2886 }
2887
2888 /* Record whether I2DEST is used in I2SRC and similarly for the other
2889 cases. Knowing this will help in register status updating below. */
2890 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2891 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2892 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2893 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2894 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2895 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2896 i2dest_killed = dead_or_set_p (i2, i2dest);
2897 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2898 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2899
2900 /* For the earlier insns, determine which of the subsequent ones they
2901 feed. */
2902 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2903 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2904 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2905 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2906 && reg_overlap_mentioned_p (i0dest, i2src))));
2907
2908 /* Ensure that I3's pattern can be the destination of combines. */
2909 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2910 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2911 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2912 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2913 &i3dest_killed))
2914 {
2915 undo_all ();
2916 return 0;
2917 }
2918
2919 /* See if any of the insns is a MULT operation. Unless one is, we will
2920 reject a combination that is, since it must be slower. Be conservative
2921 here. */
2922 if (GET_CODE (i2src) == MULT
2923 || (i1 != 0 && GET_CODE (i1src) == MULT)
2924 || (i0 != 0 && GET_CODE (i0src) == MULT)
2925 || (GET_CODE (PATTERN (i3)) == SET
2926 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2927 have_mult = 1;
2928
2929 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2930 We used to do this EXCEPT in one case: I3 has a post-inc in an
2931 output operand. However, that exception can give rise to insns like
2932 mov r3,(r3)+
2933 which is a famous insn on the PDP-11 where the value of r3 used as the
2934 source was model-dependent. Avoid this sort of thing. */
2935
2936 #if 0
2937 if (!(GET_CODE (PATTERN (i3)) == SET
2938 && REG_P (SET_SRC (PATTERN (i3)))
2939 && MEM_P (SET_DEST (PATTERN (i3)))
2940 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2941 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2942 /* It's not the exception. */
2943 #endif
2944 #ifdef AUTO_INC_DEC
2945 {
2946 rtx link;
2947 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2948 if (REG_NOTE_KIND (link) == REG_INC
2949 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2950 || (i1 != 0
2951 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2952 {
2953 undo_all ();
2954 return 0;
2955 }
2956 }
2957 #endif
2958
2959 /* See if the SETs in I1 or I2 need to be kept around in the merged
2960 instruction: whenever the value set there is still needed past I3.
2961 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2962
2963 For the SET in I1, we have two cases: If I1 and I2 independently
2964 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2965 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2966 in I1 needs to be kept around unless I1DEST dies or is set in either
2967 I2 or I3. The same consideration applies to I0. */
2968
2969 added_sets_2 = !dead_or_set_p (i3, i2dest);
2970
2971 if (i1)
2972 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2973 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2974 else
2975 added_sets_1 = 0;
2976
2977 if (i0)
2978 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2979 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2980 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2981 else
2982 added_sets_0 = 0;
2983
2984 /* We are about to copy insns for the case where they need to be kept
2985 around. Check that they can be copied in the merged instruction. */
2986
2987 if (targetm.cannot_copy_insn_p
2988 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2989 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2990 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2991 {
2992 undo_all ();
2993 return 0;
2994 }
2995
2996 /* If the set in I2 needs to be kept around, we must make a copy of
2997 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2998 PATTERN (I2), we are only substituting for the original I1DEST, not into
2999 an already-substituted copy. This also prevents making self-referential
3000 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3001 I2DEST. */
3002
3003 if (added_sets_2)
3004 {
3005 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3006 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
3007 else
3008 i2pat = copy_rtx (PATTERN (i2));
3009 }
3010
3011 if (added_sets_1)
3012 {
3013 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3014 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
3015 else
3016 i1pat = copy_rtx (PATTERN (i1));
3017 }
3018
3019 if (added_sets_0)
3020 {
3021 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3022 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
3023 else
3024 i0pat = copy_rtx (PATTERN (i0));
3025 }
3026
3027 combine_merges++;
3028
3029 /* Substitute in the latest insn for the regs set by the earlier ones. */
3030
3031 maxreg = max_reg_num ();
3032
3033 subst_insn = i3;
3034
3035 #ifndef HAVE_cc0
3036 /* Many machines that don't use CC0 have insns that can both perform an
3037 arithmetic operation and set the condition code. These operations will
3038 be represented as a PARALLEL with the first element of the vector
3039 being a COMPARE of an arithmetic operation with the constant zero.
3040 The second element of the vector will set some pseudo to the result
3041 of the same arithmetic operation. If we simplify the COMPARE, we won't
3042 match such a pattern and so will generate an extra insn. Here we test
3043 for this case, where both the comparison and the operation result are
3044 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3045 I2SRC. Later we will make the PARALLEL that contains I2. */
3046
3047 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3048 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3049 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
3050 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3051 {
3052 #ifdef SELECT_CC_MODE
3053 rtx *cc_use;
3054 enum machine_mode compare_mode;
3055 #endif
3056
3057 newpat = PATTERN (i3);
3058 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
3059
3060 i2_is_used = 1;
3061
3062 #ifdef SELECT_CC_MODE
3063 /* See if a COMPARE with the operand we substituted in should be done
3064 with the mode that is currently being used. If not, do the same
3065 processing we do in `subst' for a SET; namely, if the destination
3066 is used only once, try to replace it with a register of the proper
3067 mode and also replace the COMPARE. */
3068 if (undobuf.other_insn == 0
3069 && (cc_use = find_single_use (SET_DEST (newpat), i3,
3070 &undobuf.other_insn))
3071 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
3072 i2src, const0_rtx))
3073 != GET_MODE (SET_DEST (newpat))))
3074 {
3075 if (can_change_dest_mode (SET_DEST (newpat), added_sets_2,
3076 compare_mode))
3077 {
3078 unsigned int regno = REGNO (SET_DEST (newpat));
3079 rtx new_dest;
3080
3081 if (regno < FIRST_PSEUDO_REGISTER)
3082 new_dest = gen_rtx_REG (compare_mode, regno);
3083 else
3084 {
3085 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3086 new_dest = regno_reg_rtx[regno];
3087 }
3088
3089 SUBST (SET_DEST (newpat), new_dest);
3090 SUBST (XEXP (*cc_use, 0), new_dest);
3091 SUBST (SET_SRC (newpat),
3092 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
3093 }
3094 else
3095 undobuf.other_insn = 0;
3096 }
3097 #endif
3098 }
3099 else
3100 #endif
3101 {
3102 /* It is possible that the source of I2 or I1 may be performing
3103 an unneeded operation, such as a ZERO_EXTEND of something
3104 that is known to have the high part zero. Handle that case
3105 by letting subst look at the inner insns.
3106
3107 Another way to do this would be to have a function that tries
3108 to simplify a single insn instead of merging two or more
3109 insns. We don't do this because of the potential of infinite
3110 loops and because of the potential extra memory required.
3111 However, doing it the way we are is a bit of a kludge and
3112 doesn't catch all cases.
3113
3114 But only do this if -fexpensive-optimizations since it slows
3115 things down and doesn't usually win.
3116
3117 This is not done in the COMPARE case above because the
3118 unmodified I2PAT is used in the PARALLEL and so a pattern
3119 with a modified I2SRC would not match. */
3120
3121 if (flag_expensive_optimizations)
3122 {
3123 /* Pass pc_rtx so no substitutions are done, just
3124 simplifications. */
3125 if (i1)
3126 {
3127 subst_low_luid = DF_INSN_LUID (i1);
3128 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3129 }
3130
3131 subst_low_luid = DF_INSN_LUID (i2);
3132 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3133 }
3134
3135 n_occurrences = 0; /* `subst' counts here */
3136 subst_low_luid = DF_INSN_LUID (i2);
3137
3138 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3139 copy of I2SRC each time we substitute it, in order to avoid creating
3140 self-referential RTL when we will be substituting I1SRC for I1DEST
3141 later. Likewise if I0 feeds into I2, either directly or indirectly
3142 through I1, and I0DEST is in I0SRC. */
3143 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3144 (i1_feeds_i2_n && i1dest_in_i1src)
3145 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3146 && i0dest_in_i0src));
3147 substed_i2 = 1;
3148
3149 /* Record whether I2's body now appears within I3's body. */
3150 i2_is_used = n_occurrences;
3151 }
3152
3153 /* If we already got a failure, don't try to do more. Otherwise, try to
3154 substitute I1 if we have it. */
3155
3156 if (i1 && GET_CODE (newpat) != CLOBBER)
3157 {
3158 /* Check that an autoincrement side-effect on I1 has not been lost.
3159 This happens if I1DEST is mentioned in I2 and dies there, and
3160 has disappeared from the new pattern. */
3161 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3162 && i1_feeds_i2_n
3163 && dead_or_set_p (i2, i1dest)
3164 && !reg_overlap_mentioned_p (i1dest, newpat))
3165 /* Before we can do this substitution, we must redo the test done
3166 above (see detailed comments there) that ensures I1DEST isn't
3167 mentioned in any SETs in NEWPAT that are field assignments. */
3168 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3169 0, 0, 0))
3170 {
3171 undo_all ();
3172 return 0;
3173 }
3174
3175 n_occurrences = 0;
3176 subst_low_luid = DF_INSN_LUID (i1);
3177
3178 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3179 copy of I1SRC each time we substitute it, in order to avoid creating
3180 self-referential RTL when we will be substituting I0SRC for I0DEST
3181 later. */
3182 newpat = subst (newpat, i1dest, i1src, 0, 0,
3183 i0_feeds_i1_n && i0dest_in_i0src);
3184 substed_i1 = 1;
3185
3186 /* Record whether I1's body now appears within I3's body. */
3187 i1_is_used = n_occurrences;
3188 }
3189
3190 /* Likewise for I0 if we have it. */
3191
3192 if (i0 && GET_CODE (newpat) != CLOBBER)
3193 {
3194 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3195 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3196 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3197 && !reg_overlap_mentioned_p (i0dest, newpat))
3198 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3199 0, 0, 0))
3200 {
3201 undo_all ();
3202 return 0;
3203 }
3204
3205 /* If the following substitution will modify I1SRC, make a copy of it
3206 for the case where it is substituted for I1DEST in I2PAT later. */
3207 if (i0_feeds_i1_n && added_sets_2 && i1_feeds_i2_n)
3208 i1src_copy = copy_rtx (i1src);
3209
3210 n_occurrences = 0;
3211 subst_low_luid = DF_INSN_LUID (i0);
3212 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3213 substed_i0 = 1;
3214 }
3215
3216 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3217 to count all the ways that I2SRC and I1SRC can be used. */
3218 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3219 && i2_is_used + added_sets_2 > 1)
3220 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3221 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3222 > 1))
3223 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3224 && (n_occurrences + added_sets_0
3225 + (added_sets_1 && i0_feeds_i1_n)
3226 + (added_sets_2 && i0_feeds_i2_n)
3227 > 1))
3228 /* Fail if we tried to make a new register. */
3229 || max_reg_num () != maxreg
3230 /* Fail if we couldn't do something and have a CLOBBER. */
3231 || GET_CODE (newpat) == CLOBBER
3232 /* Fail if this new pattern is a MULT and we didn't have one before
3233 at the outer level. */
3234 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3235 && ! have_mult))
3236 {
3237 undo_all ();
3238 return 0;
3239 }
3240
3241 /* If the actions of the earlier insns must be kept
3242 in addition to substituting them into the latest one,
3243 we must make a new PARALLEL for the latest insn
3244 to hold additional the SETs. */
3245
3246 if (added_sets_0 || added_sets_1 || added_sets_2)
3247 {
3248 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3249 combine_extras++;
3250
3251 if (GET_CODE (newpat) == PARALLEL)
3252 {
3253 rtvec old = XVEC (newpat, 0);
3254 total_sets = XVECLEN (newpat, 0) + extra_sets;
3255 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3256 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3257 sizeof (old->elem[0]) * old->num_elem);
3258 }
3259 else
3260 {
3261 rtx old = newpat;
3262 total_sets = 1 + extra_sets;
3263 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3264 XVECEXP (newpat, 0, 0) = old;
3265 }
3266
3267 if (added_sets_0)
3268 XVECEXP (newpat, 0, --total_sets) = i0pat;
3269
3270 if (added_sets_1)
3271 {
3272 rtx t = i1pat;
3273 if (i0_feeds_i1_n)
3274 t = subst (t, i0dest, i0src, 0, 0, 0);
3275
3276 XVECEXP (newpat, 0, --total_sets) = t;
3277 }
3278 if (added_sets_2)
3279 {
3280 rtx t = i2pat;
3281 if (i1_feeds_i2_n)
3282 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3283 i0_feeds_i1_n && i0dest_in_i0src);
3284 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3285 t = subst (t, i0dest, i0src, 0, 0, 0);
3286
3287 XVECEXP (newpat, 0, --total_sets) = t;
3288 }
3289 }
3290
3291 validate_replacement:
3292
3293 /* Note which hard regs this insn has as inputs. */
3294 mark_used_regs_combine (newpat);
3295
3296 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3297 consider splitting this pattern, we might need these clobbers. */
3298 if (i1 && GET_CODE (newpat) == PARALLEL
3299 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3300 {
3301 int len = XVECLEN (newpat, 0);
3302
3303 newpat_vec_with_clobbers = rtvec_alloc (len);
3304 for (i = 0; i < len; i++)
3305 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3306 }
3307
3308 /* Is the result of combination a valid instruction? */
3309 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3310
3311 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3312 the second SET's destination is a register that is unused and isn't
3313 marked as an instruction that might trap in an EH region. In that case,
3314 we just need the first SET. This can occur when simplifying a divmod
3315 insn. We *must* test for this case here because the code below that
3316 splits two independent SETs doesn't handle this case correctly when it
3317 updates the register status.
3318
3319 It's pointless doing this if we originally had two sets, one from
3320 i3, and one from i2. Combining then splitting the parallel results
3321 in the original i2 again plus an invalid insn (which we delete).
3322 The net effect is only to move instructions around, which makes
3323 debug info less accurate.
3324
3325 Also check the case where the first SET's destination is unused.
3326 That would not cause incorrect code, but does cause an unneeded
3327 insn to remain. */
3328
3329 if (insn_code_number < 0
3330 && !(added_sets_2 && i1 == 0)
3331 && GET_CODE (newpat) == PARALLEL
3332 && XVECLEN (newpat, 0) == 2
3333 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3334 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3335 && asm_noperands (newpat) < 0)
3336 {
3337 rtx set0 = XVECEXP (newpat, 0, 0);
3338 rtx set1 = XVECEXP (newpat, 0, 1);
3339
3340 if (((REG_P (SET_DEST (set1))
3341 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3342 || (GET_CODE (SET_DEST (set1)) == SUBREG
3343 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3344 && insn_nothrow_p (i3)
3345 && !side_effects_p (SET_SRC (set1)))
3346 {
3347 newpat = set0;
3348 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3349 }
3350
3351 else if (((REG_P (SET_DEST (set0))
3352 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3353 || (GET_CODE (SET_DEST (set0)) == SUBREG
3354 && find_reg_note (i3, REG_UNUSED,
3355 SUBREG_REG (SET_DEST (set0)))))
3356 && insn_nothrow_p (i3)
3357 && !side_effects_p (SET_SRC (set0)))
3358 {
3359 newpat = set1;
3360 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3361
3362 if (insn_code_number >= 0)
3363 changed_i3_dest = 1;
3364 }
3365 }
3366
3367 /* If we were combining three insns and the result is a simple SET
3368 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3369 insns. There are two ways to do this. It can be split using a
3370 machine-specific method (like when you have an addition of a large
3371 constant) or by combine in the function find_split_point. */
3372
3373 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3374 && asm_noperands (newpat) < 0)
3375 {
3376 rtx parallel, m_split, *split;
3377
3378 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3379 use I2DEST as a scratch register will help. In the latter case,
3380 convert I2DEST to the mode of the source of NEWPAT if we can. */
3381
3382 m_split = combine_split_insns (newpat, i3);
3383
3384 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3385 inputs of NEWPAT. */
3386
3387 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3388 possible to try that as a scratch reg. This would require adding
3389 more code to make it work though. */
3390
3391 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3392 {
3393 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3394
3395 /* First try to split using the original register as a
3396 scratch register. */
3397 parallel = gen_rtx_PARALLEL (VOIDmode,
3398 gen_rtvec (2, newpat,
3399 gen_rtx_CLOBBER (VOIDmode,
3400 i2dest)));
3401 m_split = combine_split_insns (parallel, i3);
3402
3403 /* If that didn't work, try changing the mode of I2DEST if
3404 we can. */
3405 if (m_split == 0
3406 && new_mode != GET_MODE (i2dest)
3407 && new_mode != VOIDmode
3408 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3409 {
3410 enum machine_mode old_mode = GET_MODE (i2dest);
3411 rtx ni2dest;
3412
3413 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3414 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3415 else
3416 {
3417 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3418 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3419 }
3420
3421 parallel = (gen_rtx_PARALLEL
3422 (VOIDmode,
3423 gen_rtvec (2, newpat,
3424 gen_rtx_CLOBBER (VOIDmode,
3425 ni2dest))));
3426 m_split = combine_split_insns (parallel, i3);
3427
3428 if (m_split == 0
3429 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3430 {
3431 struct undo *buf;
3432
3433 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3434 buf = undobuf.undos;
3435 undobuf.undos = buf->next;
3436 buf->next = undobuf.frees;
3437 undobuf.frees = buf;
3438 }
3439 }
3440
3441 i2scratch = m_split != 0;
3442 }
3443
3444 /* If recog_for_combine has discarded clobbers, try to use them
3445 again for the split. */
3446 if (m_split == 0 && newpat_vec_with_clobbers)
3447 {
3448 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3449 m_split = combine_split_insns (parallel, i3);
3450 }
3451
3452 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3453 {
3454 m_split = PATTERN (m_split);
3455 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3456 if (insn_code_number >= 0)
3457 newpat = m_split;
3458 }
3459 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3460 && (next_nonnote_nondebug_insn (i2) == i3
3461 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3462 {
3463 rtx i2set, i3set;
3464 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3465 newi2pat = PATTERN (m_split);
3466
3467 i3set = single_set (NEXT_INSN (m_split));
3468 i2set = single_set (m_split);
3469
3470 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3471
3472 /* If I2 or I3 has multiple SETs, we won't know how to track
3473 register status, so don't use these insns. If I2's destination
3474 is used between I2 and I3, we also can't use these insns. */
3475
3476 if (i2_code_number >= 0 && i2set && i3set
3477 && (next_nonnote_nondebug_insn (i2) == i3
3478 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3479 insn_code_number = recog_for_combine (&newi3pat, i3,
3480 &new_i3_notes);
3481 if (insn_code_number >= 0)
3482 newpat = newi3pat;
3483
3484 /* It is possible that both insns now set the destination of I3.
3485 If so, we must show an extra use of it. */
3486
3487 if (insn_code_number >= 0)
3488 {
3489 rtx new_i3_dest = SET_DEST (i3set);
3490 rtx new_i2_dest = SET_DEST (i2set);
3491
3492 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3493 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3494 || GET_CODE (new_i3_dest) == SUBREG)
3495 new_i3_dest = XEXP (new_i3_dest, 0);
3496
3497 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3498 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3499 || GET_CODE (new_i2_dest) == SUBREG)
3500 new_i2_dest = XEXP (new_i2_dest, 0);
3501
3502 if (REG_P (new_i3_dest)
3503 && REG_P (new_i2_dest)
3504 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3505 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3506 }
3507 }
3508
3509 /* If we can split it and use I2DEST, go ahead and see if that
3510 helps things be recognized. Verify that none of the registers
3511 are set between I2 and I3. */
3512 if (insn_code_number < 0
3513 && (split = find_split_point (&newpat, i3, false)) != 0
3514 #ifdef HAVE_cc0
3515 && REG_P (i2dest)
3516 #endif
3517 /* We need I2DEST in the proper mode. If it is a hard register
3518 or the only use of a pseudo, we can change its mode.
3519 Make sure we don't change a hard register to have a mode that
3520 isn't valid for it, or change the number of registers. */
3521 && (GET_MODE (*split) == GET_MODE (i2dest)
3522 || GET_MODE (*split) == VOIDmode
3523 || can_change_dest_mode (i2dest, added_sets_2,
3524 GET_MODE (*split)))
3525 && (next_nonnote_nondebug_insn (i2) == i3
3526 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3527 /* We can't overwrite I2DEST if its value is still used by
3528 NEWPAT. */
3529 && ! reg_referenced_p (i2dest, newpat))
3530 {
3531 rtx newdest = i2dest;
3532 enum rtx_code split_code = GET_CODE (*split);
3533 enum machine_mode split_mode = GET_MODE (*split);
3534 bool subst_done = false;
3535 newi2pat = NULL_RTX;
3536
3537 i2scratch = true;
3538
3539 /* *SPLIT may be part of I2SRC, so make sure we have the
3540 original expression around for later debug processing.
3541 We should not need I2SRC any more in other cases. */
3542 if (MAY_HAVE_DEBUG_INSNS)
3543 i2src = copy_rtx (i2src);
3544 else
3545 i2src = NULL;
3546
3547 /* Get NEWDEST as a register in the proper mode. We have already
3548 validated that we can do this. */
3549 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3550 {
3551 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3552 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3553 else
3554 {
3555 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3556 newdest = regno_reg_rtx[REGNO (i2dest)];
3557 }
3558 }
3559
3560 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3561 an ASHIFT. This can occur if it was inside a PLUS and hence
3562 appeared to be a memory address. This is a kludge. */
3563 if (split_code == MULT
3564 && CONST_INT_P (XEXP (*split, 1))
3565 && INTVAL (XEXP (*split, 1)) > 0
3566 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3567 {
3568 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3569 XEXP (*split, 0), GEN_INT (i)));
3570 /* Update split_code because we may not have a multiply
3571 anymore. */
3572 split_code = GET_CODE (*split);
3573 }
3574
3575 #ifdef INSN_SCHEDULING
3576 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3577 be written as a ZERO_EXTEND. */
3578 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3579 {
3580 #ifdef LOAD_EXTEND_OP
3581 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3582 what it really is. */
3583 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3584 == SIGN_EXTEND)
3585 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3586 SUBREG_REG (*split)));
3587 else
3588 #endif
3589 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3590 SUBREG_REG (*split)));
3591 }
3592 #endif
3593
3594 /* Attempt to split binary operators using arithmetic identities. */
3595 if (BINARY_P (SET_SRC (newpat))
3596 && split_mode == GET_MODE (SET_SRC (newpat))
3597 && ! side_effects_p (SET_SRC (newpat)))
3598 {
3599 rtx setsrc = SET_SRC (newpat);
3600 enum machine_mode mode = GET_MODE (setsrc);
3601 enum rtx_code code = GET_CODE (setsrc);
3602 rtx src_op0 = XEXP (setsrc, 0);
3603 rtx src_op1 = XEXP (setsrc, 1);
3604
3605 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3606 if (rtx_equal_p (src_op0, src_op1))
3607 {
3608 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3609 SUBST (XEXP (setsrc, 0), newdest);
3610 SUBST (XEXP (setsrc, 1), newdest);
3611 subst_done = true;
3612 }
3613 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3614 else if ((code == PLUS || code == MULT)
3615 && GET_CODE (src_op0) == code
3616 && GET_CODE (XEXP (src_op0, 0)) == code
3617 && (INTEGRAL_MODE_P (mode)
3618 || (FLOAT_MODE_P (mode)
3619 && flag_unsafe_math_optimizations)))
3620 {
3621 rtx p = XEXP (XEXP (src_op0, 0), 0);
3622 rtx q = XEXP (XEXP (src_op0, 0), 1);
3623 rtx r = XEXP (src_op0, 1);
3624 rtx s = src_op1;
3625
3626 /* Split both "((X op Y) op X) op Y" and
3627 "((X op Y) op Y) op X" as "T op T" where T is
3628 "X op Y". */
3629 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3630 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3631 {
3632 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3633 XEXP (src_op0, 0));
3634 SUBST (XEXP (setsrc, 0), newdest);
3635 SUBST (XEXP (setsrc, 1), newdest);
3636 subst_done = true;
3637 }
3638 /* Split "((X op X) op Y) op Y)" as "T op T" where
3639 T is "X op Y". */
3640 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3641 {
3642 rtx tmp = simplify_gen_binary (code, mode, p, r);
3643 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3644 SUBST (XEXP (setsrc, 0), newdest);
3645 SUBST (XEXP (setsrc, 1), newdest);
3646 subst_done = true;
3647 }
3648 }
3649 }
3650
3651 if (!subst_done)
3652 {
3653 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3654 SUBST (*split, newdest);
3655 }
3656
3657 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3658
3659 /* recog_for_combine might have added CLOBBERs to newi2pat.
3660 Make sure NEWPAT does not depend on the clobbered regs. */
3661 if (GET_CODE (newi2pat) == PARALLEL)
3662 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3663 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3664 {
3665 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3666 if (reg_overlap_mentioned_p (reg, newpat))
3667 {
3668 undo_all ();
3669 return 0;
3670 }
3671 }
3672
3673 /* If the split point was a MULT and we didn't have one before,
3674 don't use one now. */
3675 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3676 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3677 }
3678 }
3679
3680 /* Check for a case where we loaded from memory in a narrow mode and
3681 then sign extended it, but we need both registers. In that case,
3682 we have a PARALLEL with both loads from the same memory location.
3683 We can split this into a load from memory followed by a register-register
3684 copy. This saves at least one insn, more if register allocation can
3685 eliminate the copy.
3686
3687 We cannot do this if the destination of the first assignment is a
3688 condition code register or cc0. We eliminate this case by making sure
3689 the SET_DEST and SET_SRC have the same mode.
3690
3691 We cannot do this if the destination of the second assignment is
3692 a register that we have already assumed is zero-extended. Similarly
3693 for a SUBREG of such a register. */
3694
3695 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3696 && GET_CODE (newpat) == PARALLEL
3697 && XVECLEN (newpat, 0) == 2
3698 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3699 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3700 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3701 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3702 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3703 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3704 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3705 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3706 DF_INSN_LUID (i2))
3707 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3708 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3709 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3710 (REG_P (temp)
3711 && VEC_index (reg_stat_type, reg_stat,
3712 REGNO (temp))->nonzero_bits != 0
3713 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3714 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3715 && (VEC_index (reg_stat_type, reg_stat,
3716 REGNO (temp))->nonzero_bits
3717 != GET_MODE_MASK (word_mode))))
3718 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3719 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3720 (REG_P (temp)
3721 && VEC_index (reg_stat_type, reg_stat,
3722 REGNO (temp))->nonzero_bits != 0
3723 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3724 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3725 && (VEC_index (reg_stat_type, reg_stat,
3726 REGNO (temp))->nonzero_bits
3727 != GET_MODE_MASK (word_mode)))))
3728 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3729 SET_SRC (XVECEXP (newpat, 0, 1)))
3730 && ! find_reg_note (i3, REG_UNUSED,
3731 SET_DEST (XVECEXP (newpat, 0, 0))))
3732 {
3733 rtx ni2dest;
3734
3735 newi2pat = XVECEXP (newpat, 0, 0);
3736 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3737 newpat = XVECEXP (newpat, 0, 1);
3738 SUBST (SET_SRC (newpat),
3739 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3740 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3741
3742 if (i2_code_number >= 0)
3743 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3744
3745 if (insn_code_number >= 0)
3746 swap_i2i3 = 1;
3747 }
3748
3749 /* Similarly, check for a case where we have a PARALLEL of two independent
3750 SETs but we started with three insns. In this case, we can do the sets
3751 as two separate insns. This case occurs when some SET allows two
3752 other insns to combine, but the destination of that SET is still live. */
3753
3754 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3755 && GET_CODE (newpat) == PARALLEL
3756 && XVECLEN (newpat, 0) == 2
3757 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3758 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3759 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3760 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3761 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3762 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3763 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3764 XVECEXP (newpat, 0, 0))
3765 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3766 XVECEXP (newpat, 0, 1))
3767 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3768 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3769 {
3770 /* Normally, it doesn't matter which of the two is done first,
3771 but the one that references cc0 can't be the second, and
3772 one which uses any regs/memory set in between i2 and i3 can't
3773 be first. */
3774 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3775 DF_INSN_LUID (i2))
3776 #ifdef HAVE_cc0
3777 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3778 #endif
3779 )
3780 {
3781 newi2pat = XVECEXP (newpat, 0, 1);
3782 newpat = XVECEXP (newpat, 0, 0);
3783 }
3784 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3785 DF_INSN_LUID (i2))
3786 #ifdef HAVE_cc0
3787 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3788 #endif
3789 )
3790 {
3791 newi2pat = XVECEXP (newpat, 0, 0);
3792 newpat = XVECEXP (newpat, 0, 1);
3793 }
3794 else
3795 {
3796 undo_all ();
3797 return 0;
3798 }
3799
3800 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3801
3802 if (i2_code_number >= 0)
3803 {
3804 /* recog_for_combine might have added CLOBBERs to newi2pat.
3805 Make sure NEWPAT does not depend on the clobbered regs. */
3806 if (GET_CODE (newi2pat) == PARALLEL)
3807 {
3808 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3809 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3810 {
3811 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3812 if (reg_overlap_mentioned_p (reg, newpat))
3813 {
3814 undo_all ();
3815 return 0;
3816 }
3817 }
3818 }
3819
3820 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3821 }
3822 }
3823
3824 /* If it still isn't recognized, fail and change things back the way they
3825 were. */
3826 if ((insn_code_number < 0
3827 /* Is the result a reasonable ASM_OPERANDS? */
3828 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3829 {
3830 undo_all ();
3831 return 0;
3832 }
3833
3834 /* If we had to change another insn, make sure it is valid also. */
3835 if (undobuf.other_insn)
3836 {
3837 CLEAR_HARD_REG_SET (newpat_used_regs);
3838
3839 other_pat = PATTERN (undobuf.other_insn);
3840 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3841 &new_other_notes);
3842
3843 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3844 {
3845 undo_all ();
3846 return 0;
3847 }
3848 }
3849
3850 #ifdef HAVE_cc0
3851 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3852 they are adjacent to each other or not. */
3853 {
3854 rtx p = prev_nonnote_insn (i3);
3855 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3856 && sets_cc0_p (newi2pat))
3857 {
3858 undo_all ();
3859 return 0;
3860 }
3861 }
3862 #endif
3863
3864 /* Only allow this combination if insn_rtx_costs reports that the
3865 replacement instructions are cheaper than the originals. */
3866 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3867 {
3868 undo_all ();
3869 return 0;
3870 }
3871
3872 if (MAY_HAVE_DEBUG_INSNS)
3873 {
3874 struct undo *undo;
3875
3876 for (undo = undobuf.undos; undo; undo = undo->next)
3877 if (undo->kind == UNDO_MODE)
3878 {
3879 rtx reg = *undo->where.r;
3880 enum machine_mode new_mode = GET_MODE (reg);
3881 enum machine_mode old_mode = undo->old_contents.m;
3882
3883 /* Temporarily revert mode back. */
3884 adjust_reg_mode (reg, old_mode);
3885
3886 if (reg == i2dest && i2scratch)
3887 {
3888 /* If we used i2dest as a scratch register with a
3889 different mode, substitute it for the original
3890 i2src while its original mode is temporarily
3891 restored, and then clear i2scratch so that we don't
3892 do it again later. */
3893 propagate_for_debug (i2, last_combined_insn, reg, i2src);
3894 i2scratch = false;
3895 /* Put back the new mode. */
3896 adjust_reg_mode (reg, new_mode);
3897 }
3898 else
3899 {
3900 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3901 rtx first, last;
3902
3903 if (reg == i2dest)
3904 {
3905 first = i2;
3906 last = last_combined_insn;
3907 }
3908 else
3909 {
3910 first = i3;
3911 last = undobuf.other_insn;
3912 gcc_assert (last);
3913 if (DF_INSN_LUID (last)
3914 < DF_INSN_LUID (last_combined_insn))
3915 last = last_combined_insn;
3916 }
3917
3918 /* We're dealing with a reg that changed mode but not
3919 meaning, so we want to turn it into a subreg for
3920 the new mode. However, because of REG sharing and
3921 because its mode had already changed, we have to do
3922 it in two steps. First, replace any debug uses of
3923 reg, with its original mode temporarily restored,
3924 with this copy we have created; then, replace the
3925 copy with the SUBREG of the original shared reg,
3926 once again changed to the new mode. */
3927 propagate_for_debug (first, last, reg, tempreg);
3928 adjust_reg_mode (reg, new_mode);
3929 propagate_for_debug (first, last, tempreg,
3930 lowpart_subreg (old_mode, reg, new_mode));
3931 }
3932 }
3933 }
3934
3935 /* If we will be able to accept this, we have made a
3936 change to the destination of I3. This requires us to
3937 do a few adjustments. */
3938
3939 if (changed_i3_dest)
3940 {
3941 PATTERN (i3) = newpat;
3942 adjust_for_new_dest (i3);
3943 }
3944
3945 /* We now know that we can do this combination. Merge the insns and
3946 update the status of registers and LOG_LINKS. */
3947
3948 if (undobuf.other_insn)
3949 {
3950 rtx note, next;
3951
3952 PATTERN (undobuf.other_insn) = other_pat;
3953
3954 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3955 are still valid. Then add any non-duplicate notes added by
3956 recog_for_combine. */
3957 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3958 {
3959 next = XEXP (note, 1);
3960
3961 if (REG_NOTE_KIND (note) == REG_UNUSED
3962 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3963 remove_note (undobuf.other_insn, note);
3964 }
3965
3966 distribute_notes (new_other_notes, undobuf.other_insn,
3967 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3968 NULL_RTX);
3969 }
3970
3971 if (swap_i2i3)
3972 {
3973 rtx insn;
3974 struct insn_link *link;
3975 rtx ni2dest;
3976
3977 /* I3 now uses what used to be its destination and which is now
3978 I2's destination. This requires us to do a few adjustments. */
3979 PATTERN (i3) = newpat;
3980 adjust_for_new_dest (i3);
3981
3982 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3983 so we still will.
3984
3985 However, some later insn might be using I2's dest and have
3986 a LOG_LINK pointing at I3. We must remove this link.
3987 The simplest way to remove the link is to point it at I1,
3988 which we know will be a NOTE. */
3989
3990 /* newi2pat is usually a SET here; however, recog_for_combine might
3991 have added some clobbers. */
3992 if (GET_CODE (newi2pat) == PARALLEL)
3993 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3994 else
3995 ni2dest = SET_DEST (newi2pat);
3996
3997 for (insn = NEXT_INSN (i3);
3998 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3999 || insn != BB_HEAD (this_basic_block->next_bb));
4000 insn = NEXT_INSN (insn))
4001 {
4002 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4003 {
4004 FOR_EACH_LOG_LINK (link, insn)
4005 if (link->insn == i3)
4006 link->insn = i1;
4007
4008 break;
4009 }
4010 }
4011 }
4012
4013 {
4014 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4015 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4016 rtx midnotes = 0;
4017 int from_luid;
4018 /* Compute which registers we expect to eliminate. newi2pat may be setting
4019 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4020 same as i3dest, in which case newi2pat may be setting i1dest. */
4021 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4022 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4023 || !i2dest_killed
4024 ? 0 : i2dest);
4025 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4026 || (newi2pat && reg_set_p (i1dest, newi2pat))
4027 || !i1dest_killed
4028 ? 0 : i1dest);
4029 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4030 || (newi2pat && reg_set_p (i0dest, newi2pat))
4031 || !i0dest_killed
4032 ? 0 : i0dest);
4033
4034 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4035 clear them. */
4036 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4037 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4038 if (i1)
4039 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4040 if (i0)
4041 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4042
4043 /* Ensure that we do not have something that should not be shared but
4044 occurs multiple times in the new insns. Check this by first
4045 resetting all the `used' flags and then copying anything is shared. */
4046
4047 reset_used_flags (i3notes);
4048 reset_used_flags (i2notes);
4049 reset_used_flags (i1notes);
4050 reset_used_flags (i0notes);
4051 reset_used_flags (newpat);
4052 reset_used_flags (newi2pat);
4053 if (undobuf.other_insn)
4054 reset_used_flags (PATTERN (undobuf.other_insn));
4055
4056 i3notes = copy_rtx_if_shared (i3notes);
4057 i2notes = copy_rtx_if_shared (i2notes);
4058 i1notes = copy_rtx_if_shared (i1notes);
4059 i0notes = copy_rtx_if_shared (i0notes);
4060 newpat = copy_rtx_if_shared (newpat);
4061 newi2pat = copy_rtx_if_shared (newi2pat);
4062 if (undobuf.other_insn)
4063 reset_used_flags (PATTERN (undobuf.other_insn));
4064
4065 INSN_CODE (i3) = insn_code_number;
4066 PATTERN (i3) = newpat;
4067
4068 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4069 {
4070 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4071
4072 reset_used_flags (call_usage);
4073 call_usage = copy_rtx (call_usage);
4074
4075 if (substed_i2)
4076 {
4077 /* I2SRC must still be meaningful at this point. Some splitting
4078 operations can invalidate I2SRC, but those operations do not
4079 apply to calls. */
4080 gcc_assert (i2src);
4081 replace_rtx (call_usage, i2dest, i2src);
4082 }
4083
4084 if (substed_i1)
4085 replace_rtx (call_usage, i1dest, i1src);
4086 if (substed_i0)
4087 replace_rtx (call_usage, i0dest, i0src);
4088
4089 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4090 }
4091
4092 if (undobuf.other_insn)
4093 INSN_CODE (undobuf.other_insn) = other_code_number;
4094
4095 /* We had one special case above where I2 had more than one set and
4096 we replaced a destination of one of those sets with the destination
4097 of I3. In that case, we have to update LOG_LINKS of insns later
4098 in this basic block. Note that this (expensive) case is rare.
4099
4100 Also, in this case, we must pretend that all REG_NOTEs for I2
4101 actually came from I3, so that REG_UNUSED notes from I2 will be
4102 properly handled. */
4103
4104 if (i3_subst_into_i2)
4105 {
4106 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4107 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4108 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4109 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4110 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4111 && ! find_reg_note (i2, REG_UNUSED,
4112 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4113 for (temp = NEXT_INSN (i2);
4114 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4115 || BB_HEAD (this_basic_block) != temp);
4116 temp = NEXT_INSN (temp))
4117 if (temp != i3 && INSN_P (temp))
4118 FOR_EACH_LOG_LINK (link, temp)
4119 if (link->insn == i2)
4120 link->insn = i3;
4121
4122 if (i3notes)
4123 {
4124 rtx link = i3notes;
4125 while (XEXP (link, 1))
4126 link = XEXP (link, 1);
4127 XEXP (link, 1) = i2notes;
4128 }
4129 else
4130 i3notes = i2notes;
4131 i2notes = 0;
4132 }
4133
4134 LOG_LINKS (i3) = NULL;
4135 REG_NOTES (i3) = 0;
4136 LOG_LINKS (i2) = NULL;
4137 REG_NOTES (i2) = 0;
4138
4139 if (newi2pat)
4140 {
4141 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4142 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4143 INSN_CODE (i2) = i2_code_number;
4144 PATTERN (i2) = newi2pat;
4145 }
4146 else
4147 {
4148 if (MAY_HAVE_DEBUG_INSNS && i2src)
4149 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4150 SET_INSN_DELETED (i2);
4151 }
4152
4153 if (i1)
4154 {
4155 LOG_LINKS (i1) = NULL;
4156 REG_NOTES (i1) = 0;
4157 if (MAY_HAVE_DEBUG_INSNS)
4158 propagate_for_debug (i1, last_combined_insn, i1dest, i1src);
4159 SET_INSN_DELETED (i1);
4160 }
4161
4162 if (i0)
4163 {
4164 LOG_LINKS (i0) = NULL;
4165 REG_NOTES (i0) = 0;
4166 if (MAY_HAVE_DEBUG_INSNS)
4167 propagate_for_debug (i0, last_combined_insn, i0dest, i0src);
4168 SET_INSN_DELETED (i0);
4169 }
4170
4171 /* Get death notes for everything that is now used in either I3 or
4172 I2 and used to die in a previous insn. If we built two new
4173 patterns, move from I1 to I2 then I2 to I3 so that we get the
4174 proper movement on registers that I2 modifies. */
4175
4176 if (i0)
4177 from_luid = DF_INSN_LUID (i0);
4178 else if (i1)
4179 from_luid = DF_INSN_LUID (i1);
4180 else
4181 from_luid = DF_INSN_LUID (i2);
4182 if (newi2pat)
4183 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4184 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4185
4186 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4187 if (i3notes)
4188 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4189 elim_i2, elim_i1, elim_i0);
4190 if (i2notes)
4191 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4192 elim_i2, elim_i1, elim_i0);
4193 if (i1notes)
4194 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4195 elim_i2, elim_i1, elim_i0);
4196 if (i0notes)
4197 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4198 elim_i2, elim_i1, elim_i0);
4199 if (midnotes)
4200 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4201 elim_i2, elim_i1, elim_i0);
4202
4203 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4204 know these are REG_UNUSED and want them to go to the desired insn,
4205 so we always pass it as i3. */
4206
4207 if (newi2pat && new_i2_notes)
4208 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4209 NULL_RTX);
4210
4211 if (new_i3_notes)
4212 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4213 NULL_RTX);
4214
4215 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4216 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4217 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4218 in that case, it might delete I2. Similarly for I2 and I1.
4219 Show an additional death due to the REG_DEAD note we make here. If
4220 we discard it in distribute_notes, we will decrement it again. */
4221
4222 if (i3dest_killed)
4223 {
4224 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4225 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4226 NULL_RTX),
4227 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4228 else
4229 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4230 NULL_RTX),
4231 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4232 elim_i2, elim_i1, elim_i0);
4233 }
4234
4235 if (i2dest_in_i2src)
4236 {
4237 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4238 if (newi2pat && reg_set_p (i2dest, newi2pat))
4239 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4240 NULL_RTX, NULL_RTX);
4241 else
4242 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4243 NULL_RTX, NULL_RTX, NULL_RTX);
4244 }
4245
4246 if (i1dest_in_i1src)
4247 {
4248 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4249 if (newi2pat && reg_set_p (i1dest, newi2pat))
4250 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4251 NULL_RTX, NULL_RTX);
4252 else
4253 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4254 NULL_RTX, NULL_RTX, NULL_RTX);
4255 }
4256
4257 if (i0dest_in_i0src)
4258 {
4259 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4260 if (newi2pat && reg_set_p (i0dest, newi2pat))
4261 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4262 NULL_RTX, NULL_RTX);
4263 else
4264 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4265 NULL_RTX, NULL_RTX, NULL_RTX);
4266 }
4267
4268 distribute_links (i3links);
4269 distribute_links (i2links);
4270 distribute_links (i1links);
4271 distribute_links (i0links);
4272
4273 if (REG_P (i2dest))
4274 {
4275 struct insn_link *link;
4276 rtx i2_insn = 0, i2_val = 0, set;
4277
4278 /* The insn that used to set this register doesn't exist, and
4279 this life of the register may not exist either. See if one of
4280 I3's links points to an insn that sets I2DEST. If it does,
4281 that is now the last known value for I2DEST. If we don't update
4282 this and I2 set the register to a value that depended on its old
4283 contents, we will get confused. If this insn is used, thing
4284 will be set correctly in combine_instructions. */
4285 FOR_EACH_LOG_LINK (link, i3)
4286 if ((set = single_set (link->insn)) != 0
4287 && rtx_equal_p (i2dest, SET_DEST (set)))
4288 i2_insn = link->insn, i2_val = SET_SRC (set);
4289
4290 record_value_for_reg (i2dest, i2_insn, i2_val);
4291
4292 /* If the reg formerly set in I2 died only once and that was in I3,
4293 zero its use count so it won't make `reload' do any work. */
4294 if (! added_sets_2
4295 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4296 && ! i2dest_in_i2src)
4297 INC_REG_N_SETS (REGNO (i2dest), -1);
4298 }
4299
4300 if (i1 && REG_P (i1dest))
4301 {
4302 struct insn_link *link;
4303 rtx i1_insn = 0, i1_val = 0, set;
4304
4305 FOR_EACH_LOG_LINK (link, i3)
4306 if ((set = single_set (link->insn)) != 0
4307 && rtx_equal_p (i1dest, SET_DEST (set)))
4308 i1_insn = link->insn, i1_val = SET_SRC (set);
4309
4310 record_value_for_reg (i1dest, i1_insn, i1_val);
4311
4312 if (! added_sets_1 && ! i1dest_in_i1src)
4313 INC_REG_N_SETS (REGNO (i1dest), -1);
4314 }
4315
4316 if (i0 && REG_P (i0dest))
4317 {
4318 struct insn_link *link;
4319 rtx i0_insn = 0, i0_val = 0, set;
4320
4321 FOR_EACH_LOG_LINK (link, i3)
4322 if ((set = single_set (link->insn)) != 0
4323 && rtx_equal_p (i0dest, SET_DEST (set)))
4324 i0_insn = link->insn, i0_val = SET_SRC (set);
4325
4326 record_value_for_reg (i0dest, i0_insn, i0_val);
4327
4328 if (! added_sets_0 && ! i0dest_in_i0src)
4329 INC_REG_N_SETS (REGNO (i0dest), -1);
4330 }
4331
4332 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4333 been made to this insn. The order of
4334 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4335 can affect nonzero_bits of newpat */
4336 if (newi2pat)
4337 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4338 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4339 }
4340
4341 if (undobuf.other_insn != NULL_RTX)
4342 {
4343 if (dump_file)
4344 {
4345 fprintf (dump_file, "modifying other_insn ");
4346 dump_insn_slim (dump_file, undobuf.other_insn);
4347 }
4348 df_insn_rescan (undobuf.other_insn);
4349 }
4350
4351 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4352 {
4353 if (dump_file)
4354 {
4355 fprintf (dump_file, "modifying insn i1 ");
4356 dump_insn_slim (dump_file, i0);
4357 }
4358 df_insn_rescan (i0);
4359 }
4360
4361 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4362 {
4363 if (dump_file)
4364 {
4365 fprintf (dump_file, "modifying insn i1 ");
4366 dump_insn_slim (dump_file, i1);
4367 }
4368 df_insn_rescan (i1);
4369 }
4370
4371 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4372 {
4373 if (dump_file)
4374 {
4375 fprintf (dump_file, "modifying insn i2 ");
4376 dump_insn_slim (dump_file, i2);
4377 }
4378 df_insn_rescan (i2);
4379 }
4380
4381 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4382 {
4383 if (dump_file)
4384 {
4385 fprintf (dump_file, "modifying insn i3 ");
4386 dump_insn_slim (dump_file, i3);
4387 }
4388 df_insn_rescan (i3);
4389 }
4390
4391 /* Set new_direct_jump_p if a new return or simple jump instruction
4392 has been created. Adjust the CFG accordingly. */
4393
4394 if (returnjump_p (i3) || any_uncondjump_p (i3))
4395 {
4396 *new_direct_jump_p = 1;
4397 mark_jump_label (PATTERN (i3), i3, 0);
4398 update_cfg_for_uncondjump (i3);
4399 }
4400
4401 if (undobuf.other_insn != NULL_RTX
4402 && (returnjump_p (undobuf.other_insn)
4403 || any_uncondjump_p (undobuf.other_insn)))
4404 {
4405 *new_direct_jump_p = 1;
4406 update_cfg_for_uncondjump (undobuf.other_insn);
4407 }
4408
4409 /* A noop might also need cleaning up of CFG, if it comes from the
4410 simplification of a jump. */
4411 if (JUMP_P (i3)
4412 && GET_CODE (newpat) == SET
4413 && SET_SRC (newpat) == pc_rtx
4414 && SET_DEST (newpat) == pc_rtx)
4415 {
4416 *new_direct_jump_p = 1;
4417 update_cfg_for_uncondjump (i3);
4418 }
4419
4420 if (undobuf.other_insn != NULL_RTX
4421 && JUMP_P (undobuf.other_insn)
4422 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4423 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4424 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4425 {
4426 *new_direct_jump_p = 1;
4427 update_cfg_for_uncondjump (undobuf.other_insn);
4428 }
4429
4430 combine_successes++;
4431 undo_commit ();
4432
4433 if (added_links_insn
4434 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4435 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4436 return added_links_insn;
4437 else
4438 return newi2pat ? i2 : i3;
4439 }
4440 \f
4441 /* Undo all the modifications recorded in undobuf. */
4442
4443 static void
4444 undo_all (void)
4445 {
4446 struct undo *undo, *next;
4447
4448 for (undo = undobuf.undos; undo; undo = next)
4449 {
4450 next = undo->next;
4451 switch (undo->kind)
4452 {
4453 case UNDO_RTX:
4454 *undo->where.r = undo->old_contents.r;
4455 break;
4456 case UNDO_INT:
4457 *undo->where.i = undo->old_contents.i;
4458 break;
4459 case UNDO_MODE:
4460 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4461 break;
4462 default:
4463 gcc_unreachable ();
4464 }
4465
4466 undo->next = undobuf.frees;
4467 undobuf.frees = undo;
4468 }
4469
4470 undobuf.undos = 0;
4471 }
4472
4473 /* We've committed to accepting the changes we made. Move all
4474 of the undos to the free list. */
4475
4476 static void
4477 undo_commit (void)
4478 {
4479 struct undo *undo, *next;
4480
4481 for (undo = undobuf.undos; undo; undo = next)
4482 {
4483 next = undo->next;
4484 undo->next = undobuf.frees;
4485 undobuf.frees = undo;
4486 }
4487 undobuf.undos = 0;
4488 }
4489 \f
4490 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4491 where we have an arithmetic expression and return that point. LOC will
4492 be inside INSN.
4493
4494 try_combine will call this function to see if an insn can be split into
4495 two insns. */
4496
4497 static rtx *
4498 find_split_point (rtx *loc, rtx insn, bool set_src)
4499 {
4500 rtx x = *loc;
4501 enum rtx_code code = GET_CODE (x);
4502 rtx *split;
4503 unsigned HOST_WIDE_INT len = 0;
4504 HOST_WIDE_INT pos = 0;
4505 int unsignedp = 0;
4506 rtx inner = NULL_RTX;
4507
4508 /* First special-case some codes. */
4509 switch (code)
4510 {
4511 case SUBREG:
4512 #ifdef INSN_SCHEDULING
4513 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4514 point. */
4515 if (MEM_P (SUBREG_REG (x)))
4516 return loc;
4517 #endif
4518 return find_split_point (&SUBREG_REG (x), insn, false);
4519
4520 case MEM:
4521 #ifdef HAVE_lo_sum
4522 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4523 using LO_SUM and HIGH. */
4524 if (GET_CODE (XEXP (x, 0)) == CONST
4525 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4526 {
4527 enum machine_mode address_mode
4528 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4529
4530 SUBST (XEXP (x, 0),
4531 gen_rtx_LO_SUM (address_mode,
4532 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4533 XEXP (x, 0)));
4534 return &XEXP (XEXP (x, 0), 0);
4535 }
4536 #endif
4537
4538 /* If we have a PLUS whose second operand is a constant and the
4539 address is not valid, perhaps will can split it up using
4540 the machine-specific way to split large constants. We use
4541 the first pseudo-reg (one of the virtual regs) as a placeholder;
4542 it will not remain in the result. */
4543 if (GET_CODE (XEXP (x, 0)) == PLUS
4544 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4545 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4546 MEM_ADDR_SPACE (x)))
4547 {
4548 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4549 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4550 XEXP (x, 0)),
4551 subst_insn);
4552
4553 /* This should have produced two insns, each of which sets our
4554 placeholder. If the source of the second is a valid address,
4555 we can make put both sources together and make a split point
4556 in the middle. */
4557
4558 if (seq
4559 && NEXT_INSN (seq) != NULL_RTX
4560 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4561 && NONJUMP_INSN_P (seq)
4562 && GET_CODE (PATTERN (seq)) == SET
4563 && SET_DEST (PATTERN (seq)) == reg
4564 && ! reg_mentioned_p (reg,
4565 SET_SRC (PATTERN (seq)))
4566 && NONJUMP_INSN_P (NEXT_INSN (seq))
4567 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4568 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4569 && memory_address_addr_space_p
4570 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4571 MEM_ADDR_SPACE (x)))
4572 {
4573 rtx src1 = SET_SRC (PATTERN (seq));
4574 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4575
4576 /* Replace the placeholder in SRC2 with SRC1. If we can
4577 find where in SRC2 it was placed, that can become our
4578 split point and we can replace this address with SRC2.
4579 Just try two obvious places. */
4580
4581 src2 = replace_rtx (src2, reg, src1);
4582 split = 0;
4583 if (XEXP (src2, 0) == src1)
4584 split = &XEXP (src2, 0);
4585 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4586 && XEXP (XEXP (src2, 0), 0) == src1)
4587 split = &XEXP (XEXP (src2, 0), 0);
4588
4589 if (split)
4590 {
4591 SUBST (XEXP (x, 0), src2);
4592 return split;
4593 }
4594 }
4595
4596 /* If that didn't work, perhaps the first operand is complex and
4597 needs to be computed separately, so make a split point there.
4598 This will occur on machines that just support REG + CONST
4599 and have a constant moved through some previous computation. */
4600
4601 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4602 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4603 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4604 return &XEXP (XEXP (x, 0), 0);
4605 }
4606
4607 /* If we have a PLUS whose first operand is complex, try computing it
4608 separately by making a split there. */
4609 if (GET_CODE (XEXP (x, 0)) == PLUS
4610 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4611 MEM_ADDR_SPACE (x))
4612 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4613 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4614 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4615 return &XEXP (XEXP (x, 0), 0);
4616 break;
4617
4618 case SET:
4619 #ifdef HAVE_cc0
4620 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4621 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4622 we need to put the operand into a register. So split at that
4623 point. */
4624
4625 if (SET_DEST (x) == cc0_rtx
4626 && GET_CODE (SET_SRC (x)) != COMPARE
4627 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4628 && !OBJECT_P (SET_SRC (x))
4629 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4630 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4631 return &SET_SRC (x);
4632 #endif
4633
4634 /* See if we can split SET_SRC as it stands. */
4635 split = find_split_point (&SET_SRC (x), insn, true);
4636 if (split && split != &SET_SRC (x))
4637 return split;
4638
4639 /* See if we can split SET_DEST as it stands. */
4640 split = find_split_point (&SET_DEST (x), insn, false);
4641 if (split && split != &SET_DEST (x))
4642 return split;
4643
4644 /* See if this is a bitfield assignment with everything constant. If
4645 so, this is an IOR of an AND, so split it into that. */
4646 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4647 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4648 <= HOST_BITS_PER_WIDE_INT)
4649 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4650 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4651 && CONST_INT_P (SET_SRC (x))
4652 && ((INTVAL (XEXP (SET_DEST (x), 1))
4653 + INTVAL (XEXP (SET_DEST (x), 2)))
4654 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4655 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4656 {
4657 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4658 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4659 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4660 rtx dest = XEXP (SET_DEST (x), 0);
4661 enum machine_mode mode = GET_MODE (dest);
4662 unsigned HOST_WIDE_INT mask
4663 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4664 rtx or_mask;
4665
4666 if (BITS_BIG_ENDIAN)
4667 pos = GET_MODE_BITSIZE (mode) - len - pos;
4668
4669 or_mask = gen_int_mode (src << pos, mode);
4670 if (src == mask)
4671 SUBST (SET_SRC (x),
4672 simplify_gen_binary (IOR, mode, dest, or_mask));
4673 else
4674 {
4675 rtx negmask = gen_int_mode (~(mask << pos), mode);
4676 SUBST (SET_SRC (x),
4677 simplify_gen_binary (IOR, mode,
4678 simplify_gen_binary (AND, mode,
4679 dest, negmask),
4680 or_mask));
4681 }
4682
4683 SUBST (SET_DEST (x), dest);
4684
4685 split = find_split_point (&SET_SRC (x), insn, true);
4686 if (split && split != &SET_SRC (x))
4687 return split;
4688 }
4689
4690 /* Otherwise, see if this is an operation that we can split into two.
4691 If so, try to split that. */
4692 code = GET_CODE (SET_SRC (x));
4693
4694 switch (code)
4695 {
4696 case AND:
4697 /* If we are AND'ing with a large constant that is only a single
4698 bit and the result is only being used in a context where we
4699 need to know if it is zero or nonzero, replace it with a bit
4700 extraction. This will avoid the large constant, which might
4701 have taken more than one insn to make. If the constant were
4702 not a valid argument to the AND but took only one insn to make,
4703 this is no worse, but if it took more than one insn, it will
4704 be better. */
4705
4706 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4707 && REG_P (XEXP (SET_SRC (x), 0))
4708 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4709 && REG_P (SET_DEST (x))
4710 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4711 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4712 && XEXP (*split, 0) == SET_DEST (x)
4713 && XEXP (*split, 1) == const0_rtx)
4714 {
4715 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4716 XEXP (SET_SRC (x), 0),
4717 pos, NULL_RTX, 1, 1, 0, 0);
4718 if (extraction != 0)
4719 {
4720 SUBST (SET_SRC (x), extraction);
4721 return find_split_point (loc, insn, false);
4722 }
4723 }
4724 break;
4725
4726 case NE:
4727 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4728 is known to be on, this can be converted into a NEG of a shift. */
4729 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4730 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4731 && 1 <= (pos = exact_log2
4732 (nonzero_bits (XEXP (SET_SRC (x), 0),
4733 GET_MODE (XEXP (SET_SRC (x), 0))))))
4734 {
4735 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4736
4737 SUBST (SET_SRC (x),
4738 gen_rtx_NEG (mode,
4739 gen_rtx_LSHIFTRT (mode,
4740 XEXP (SET_SRC (x), 0),
4741 GEN_INT (pos))));
4742
4743 split = find_split_point (&SET_SRC (x), insn, true);
4744 if (split && split != &SET_SRC (x))
4745 return split;
4746 }
4747 break;
4748
4749 case SIGN_EXTEND:
4750 inner = XEXP (SET_SRC (x), 0);
4751
4752 /* We can't optimize if either mode is a partial integer
4753 mode as we don't know how many bits are significant
4754 in those modes. */
4755 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4756 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4757 break;
4758
4759 pos = 0;
4760 len = GET_MODE_BITSIZE (GET_MODE (inner));
4761 unsignedp = 0;
4762 break;
4763
4764 case SIGN_EXTRACT:
4765 case ZERO_EXTRACT:
4766 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4767 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4768 {
4769 inner = XEXP (SET_SRC (x), 0);
4770 len = INTVAL (XEXP (SET_SRC (x), 1));
4771 pos = INTVAL (XEXP (SET_SRC (x), 2));
4772
4773 if (BITS_BIG_ENDIAN)
4774 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4775 unsignedp = (code == ZERO_EXTRACT);
4776 }
4777 break;
4778
4779 default:
4780 break;
4781 }
4782
4783 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4784 {
4785 enum machine_mode mode = GET_MODE (SET_SRC (x));
4786
4787 /* For unsigned, we have a choice of a shift followed by an
4788 AND or two shifts. Use two shifts for field sizes where the
4789 constant might be too large. We assume here that we can
4790 always at least get 8-bit constants in an AND insn, which is
4791 true for every current RISC. */
4792
4793 if (unsignedp && len <= 8)
4794 {
4795 SUBST (SET_SRC (x),
4796 gen_rtx_AND (mode,
4797 gen_rtx_LSHIFTRT
4798 (mode, gen_lowpart (mode, inner),
4799 GEN_INT (pos)),
4800 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4801 - 1)));
4802
4803 split = find_split_point (&SET_SRC (x), insn, true);
4804 if (split && split != &SET_SRC (x))
4805 return split;
4806 }
4807 else
4808 {
4809 SUBST (SET_SRC (x),
4810 gen_rtx_fmt_ee
4811 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4812 gen_rtx_ASHIFT (mode,
4813 gen_lowpart (mode, inner),
4814 GEN_INT (GET_MODE_BITSIZE (mode)
4815 - len - pos)),
4816 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4817
4818 split = find_split_point (&SET_SRC (x), insn, true);
4819 if (split && split != &SET_SRC (x))
4820 return split;
4821 }
4822 }
4823
4824 /* See if this is a simple operation with a constant as the second
4825 operand. It might be that this constant is out of range and hence
4826 could be used as a split point. */
4827 if (BINARY_P (SET_SRC (x))
4828 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4829 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4830 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4831 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4832 return &XEXP (SET_SRC (x), 1);
4833
4834 /* Finally, see if this is a simple operation with its first operand
4835 not in a register. The operation might require this operand in a
4836 register, so return it as a split point. We can always do this
4837 because if the first operand were another operation, we would have
4838 already found it as a split point. */
4839 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4840 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4841 return &XEXP (SET_SRC (x), 0);
4842
4843 return 0;
4844
4845 case AND:
4846 case IOR:
4847 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4848 it is better to write this as (not (ior A B)) so we can split it.
4849 Similarly for IOR. */
4850 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4851 {
4852 SUBST (*loc,
4853 gen_rtx_NOT (GET_MODE (x),
4854 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4855 GET_MODE (x),
4856 XEXP (XEXP (x, 0), 0),
4857 XEXP (XEXP (x, 1), 0))));
4858 return find_split_point (loc, insn, set_src);
4859 }
4860
4861 /* Many RISC machines have a large set of logical insns. If the
4862 second operand is a NOT, put it first so we will try to split the
4863 other operand first. */
4864 if (GET_CODE (XEXP (x, 1)) == NOT)
4865 {
4866 rtx tem = XEXP (x, 0);
4867 SUBST (XEXP (x, 0), XEXP (x, 1));
4868 SUBST (XEXP (x, 1), tem);
4869 }
4870 break;
4871
4872 case PLUS:
4873 case MINUS:
4874 /* Canonicalization can produce (minus A (mult B C)), where C is a
4875 constant. It may be better to try splitting (plus (mult B -C) A)
4876 instead if this isn't a multiply by a power of two. */
4877 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4878 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4879 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4880 {
4881 enum machine_mode mode = GET_MODE (x);
4882 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4883 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4884 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4885 XEXP (XEXP (x, 1), 0),
4886 GEN_INT (other_int)),
4887 XEXP (x, 0)));
4888 return find_split_point (loc, insn, set_src);
4889 }
4890
4891 /* Split at a multiply-accumulate instruction. However if this is
4892 the SET_SRC, we likely do not have such an instruction and it's
4893 worthless to try this split. */
4894 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4895 return loc;
4896
4897 default:
4898 break;
4899 }
4900
4901 /* Otherwise, select our actions depending on our rtx class. */
4902 switch (GET_RTX_CLASS (code))
4903 {
4904 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4905 case RTX_TERNARY:
4906 split = find_split_point (&XEXP (x, 2), insn, false);
4907 if (split)
4908 return split;
4909 /* ... fall through ... */
4910 case RTX_BIN_ARITH:
4911 case RTX_COMM_ARITH:
4912 case RTX_COMPARE:
4913 case RTX_COMM_COMPARE:
4914 split = find_split_point (&XEXP (x, 1), insn, false);
4915 if (split)
4916 return split;
4917 /* ... fall through ... */
4918 case RTX_UNARY:
4919 /* Some machines have (and (shift ...) ...) insns. If X is not
4920 an AND, but XEXP (X, 0) is, use it as our split point. */
4921 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4922 return &XEXP (x, 0);
4923
4924 split = find_split_point (&XEXP (x, 0), insn, false);
4925 if (split)
4926 return split;
4927 return loc;
4928
4929 default:
4930 /* Otherwise, we don't have a split point. */
4931 return 0;
4932 }
4933 }
4934 \f
4935 /* Throughout X, replace FROM with TO, and return the result.
4936 The result is TO if X is FROM;
4937 otherwise the result is X, but its contents may have been modified.
4938 If they were modified, a record was made in undobuf so that
4939 undo_all will (among other things) return X to its original state.
4940
4941 If the number of changes necessary is too much to record to undo,
4942 the excess changes are not made, so the result is invalid.
4943 The changes already made can still be undone.
4944 undobuf.num_undo is incremented for such changes, so by testing that
4945 the caller can tell whether the result is valid.
4946
4947 `n_occurrences' is incremented each time FROM is replaced.
4948
4949 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4950
4951 IN_COND is nonzero if we are at the top level of a condition.
4952
4953 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4954 by copying if `n_occurrences' is nonzero. */
4955
4956 static rtx
4957 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4958 {
4959 enum rtx_code code = GET_CODE (x);
4960 enum machine_mode op0_mode = VOIDmode;
4961 const char *fmt;
4962 int len, i;
4963 rtx new_rtx;
4964
4965 /* Two expressions are equal if they are identical copies of a shared
4966 RTX or if they are both registers with the same register number
4967 and mode. */
4968
4969 #define COMBINE_RTX_EQUAL_P(X,Y) \
4970 ((X) == (Y) \
4971 || (REG_P (X) && REG_P (Y) \
4972 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4973
4974 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4975 {
4976 n_occurrences++;
4977 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4978 }
4979
4980 /* If X and FROM are the same register but different modes, they
4981 will not have been seen as equal above. However, the log links code
4982 will make a LOG_LINKS entry for that case. If we do nothing, we
4983 will try to rerecognize our original insn and, when it succeeds,
4984 we will delete the feeding insn, which is incorrect.
4985
4986 So force this insn not to match in this (rare) case. */
4987 if (! in_dest && code == REG && REG_P (from)
4988 && reg_overlap_mentioned_p (x, from))
4989 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4990
4991 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4992 of which may contain things that can be combined. */
4993 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4994 return x;
4995
4996 /* It is possible to have a subexpression appear twice in the insn.
4997 Suppose that FROM is a register that appears within TO.
4998 Then, after that subexpression has been scanned once by `subst',
4999 the second time it is scanned, TO may be found. If we were
5000 to scan TO here, we would find FROM within it and create a
5001 self-referent rtl structure which is completely wrong. */
5002 if (COMBINE_RTX_EQUAL_P (x, to))
5003 return to;
5004
5005 /* Parallel asm_operands need special attention because all of the
5006 inputs are shared across the arms. Furthermore, unsharing the
5007 rtl results in recognition failures. Failure to handle this case
5008 specially can result in circular rtl.
5009
5010 Solve this by doing a normal pass across the first entry of the
5011 parallel, and only processing the SET_DESTs of the subsequent
5012 entries. Ug. */
5013
5014 if (code == PARALLEL
5015 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5016 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5017 {
5018 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5019
5020 /* If this substitution failed, this whole thing fails. */
5021 if (GET_CODE (new_rtx) == CLOBBER
5022 && XEXP (new_rtx, 0) == const0_rtx)
5023 return new_rtx;
5024
5025 SUBST (XVECEXP (x, 0, 0), new_rtx);
5026
5027 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5028 {
5029 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5030
5031 if (!REG_P (dest)
5032 && GET_CODE (dest) != CC0
5033 && GET_CODE (dest) != PC)
5034 {
5035 new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5036
5037 /* If this substitution failed, this whole thing fails. */
5038 if (GET_CODE (new_rtx) == CLOBBER
5039 && XEXP (new_rtx, 0) == const0_rtx)
5040 return new_rtx;
5041
5042 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5043 }
5044 }
5045 }
5046 else
5047 {
5048 len = GET_RTX_LENGTH (code);
5049 fmt = GET_RTX_FORMAT (code);
5050
5051 /* We don't need to process a SET_DEST that is a register, CC0,
5052 or PC, so set up to skip this common case. All other cases
5053 where we want to suppress replacing something inside a
5054 SET_SRC are handled via the IN_DEST operand. */
5055 if (code == SET
5056 && (REG_P (SET_DEST (x))
5057 || GET_CODE (SET_DEST (x)) == CC0
5058 || GET_CODE (SET_DEST (x)) == PC))
5059 fmt = "ie";
5060
5061 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5062 constant. */
5063 if (fmt[0] == 'e')
5064 op0_mode = GET_MODE (XEXP (x, 0));
5065
5066 for (i = 0; i < len; i++)
5067 {
5068 if (fmt[i] == 'E')
5069 {
5070 int j;
5071 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5072 {
5073 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5074 {
5075 new_rtx = (unique_copy && n_occurrences
5076 ? copy_rtx (to) : to);
5077 n_occurrences++;
5078 }
5079 else
5080 {
5081 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5082 unique_copy);
5083
5084 /* If this substitution failed, this whole thing
5085 fails. */
5086 if (GET_CODE (new_rtx) == CLOBBER
5087 && XEXP (new_rtx, 0) == const0_rtx)
5088 return new_rtx;
5089 }
5090
5091 SUBST (XVECEXP (x, i, j), new_rtx);
5092 }
5093 }
5094 else if (fmt[i] == 'e')
5095 {
5096 /* If this is a register being set, ignore it. */
5097 new_rtx = XEXP (x, i);
5098 if (in_dest
5099 && i == 0
5100 && (((code == SUBREG || code == ZERO_EXTRACT)
5101 && REG_P (new_rtx))
5102 || code == STRICT_LOW_PART))
5103 ;
5104
5105 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5106 {
5107 /* In general, don't install a subreg involving two
5108 modes not tieable. It can worsen register
5109 allocation, and can even make invalid reload
5110 insns, since the reg inside may need to be copied
5111 from in the outside mode, and that may be invalid
5112 if it is an fp reg copied in integer mode.
5113
5114 We allow two exceptions to this: It is valid if
5115 it is inside another SUBREG and the mode of that
5116 SUBREG and the mode of the inside of TO is
5117 tieable and it is valid if X is a SET that copies
5118 FROM to CC0. */
5119
5120 if (GET_CODE (to) == SUBREG
5121 && ! MODES_TIEABLE_P (GET_MODE (to),
5122 GET_MODE (SUBREG_REG (to)))
5123 && ! (code == SUBREG
5124 && MODES_TIEABLE_P (GET_MODE (x),
5125 GET_MODE (SUBREG_REG (to))))
5126 #ifdef HAVE_cc0
5127 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5128 #endif
5129 )
5130 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5131
5132 #ifdef CANNOT_CHANGE_MODE_CLASS
5133 if (code == SUBREG
5134 && REG_P (to)
5135 && REGNO (to) < FIRST_PSEUDO_REGISTER
5136 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5137 GET_MODE (to),
5138 GET_MODE (x)))
5139 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5140 #endif
5141
5142 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5143 n_occurrences++;
5144 }
5145 else
5146 /* If we are in a SET_DEST, suppress most cases unless we
5147 have gone inside a MEM, in which case we want to
5148 simplify the address. We assume here that things that
5149 are actually part of the destination have their inner
5150 parts in the first expression. This is true for SUBREG,
5151 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5152 things aside from REG and MEM that should appear in a
5153 SET_DEST. */
5154 new_rtx = subst (XEXP (x, i), from, to,
5155 (((in_dest
5156 && (code == SUBREG || code == STRICT_LOW_PART
5157 || code == ZERO_EXTRACT))
5158 || code == SET)
5159 && i == 0),
5160 code == IF_THEN_ELSE && i == 0,
5161 unique_copy);
5162
5163 /* If we found that we will have to reject this combination,
5164 indicate that by returning the CLOBBER ourselves, rather than
5165 an expression containing it. This will speed things up as
5166 well as prevent accidents where two CLOBBERs are considered
5167 to be equal, thus producing an incorrect simplification. */
5168
5169 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5170 return new_rtx;
5171
5172 if (GET_CODE (x) == SUBREG
5173 && (CONST_INT_P (new_rtx)
5174 || GET_CODE (new_rtx) == CONST_DOUBLE))
5175 {
5176 enum machine_mode mode = GET_MODE (x);
5177
5178 x = simplify_subreg (GET_MODE (x), new_rtx,
5179 GET_MODE (SUBREG_REG (x)),
5180 SUBREG_BYTE (x));
5181 if (! x)
5182 x = gen_rtx_CLOBBER (mode, const0_rtx);
5183 }
5184 else if (CONST_INT_P (new_rtx)
5185 && GET_CODE (x) == ZERO_EXTEND)
5186 {
5187 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5188 new_rtx, GET_MODE (XEXP (x, 0)));
5189 gcc_assert (x);
5190 }
5191 else
5192 SUBST (XEXP (x, i), new_rtx);
5193 }
5194 }
5195 }
5196
5197 /* Check if we are loading something from the constant pool via float
5198 extension; in this case we would undo compress_float_constant
5199 optimization and degenerate constant load to an immediate value. */
5200 if (GET_CODE (x) == FLOAT_EXTEND
5201 && MEM_P (XEXP (x, 0))
5202 && MEM_READONLY_P (XEXP (x, 0)))
5203 {
5204 rtx tmp = avoid_constant_pool_reference (x);
5205 if (x != tmp)
5206 return x;
5207 }
5208
5209 /* Try to simplify X. If the simplification changed the code, it is likely
5210 that further simplification will help, so loop, but limit the number
5211 of repetitions that will be performed. */
5212
5213 for (i = 0; i < 4; i++)
5214 {
5215 /* If X is sufficiently simple, don't bother trying to do anything
5216 with it. */
5217 if (code != CONST_INT && code != REG && code != CLOBBER)
5218 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5219
5220 if (GET_CODE (x) == code)
5221 break;
5222
5223 code = GET_CODE (x);
5224
5225 /* We no longer know the original mode of operand 0 since we
5226 have changed the form of X) */
5227 op0_mode = VOIDmode;
5228 }
5229
5230 return x;
5231 }
5232 \f
5233 /* Simplify X, a piece of RTL. We just operate on the expression at the
5234 outer level; call `subst' to simplify recursively. Return the new
5235 expression.
5236
5237 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5238 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5239 of a condition. */
5240
5241 static rtx
5242 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5243 int in_cond)
5244 {
5245 enum rtx_code code = GET_CODE (x);
5246 enum machine_mode mode = GET_MODE (x);
5247 rtx temp;
5248 int i;
5249
5250 /* If this is a commutative operation, put a constant last and a complex
5251 expression first. We don't need to do this for comparisons here. */
5252 if (COMMUTATIVE_ARITH_P (x)
5253 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5254 {
5255 temp = XEXP (x, 0);
5256 SUBST (XEXP (x, 0), XEXP (x, 1));
5257 SUBST (XEXP (x, 1), temp);
5258 }
5259
5260 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5261 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5262 things. Check for cases where both arms are testing the same
5263 condition.
5264
5265 Don't do anything if all operands are very simple. */
5266
5267 if ((BINARY_P (x)
5268 && ((!OBJECT_P (XEXP (x, 0))
5269 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5270 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5271 || (!OBJECT_P (XEXP (x, 1))
5272 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5273 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5274 || (UNARY_P (x)
5275 && (!OBJECT_P (XEXP (x, 0))
5276 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5277 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5278 {
5279 rtx cond, true_rtx, false_rtx;
5280
5281 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5282 if (cond != 0
5283 /* If everything is a comparison, what we have is highly unlikely
5284 to be simpler, so don't use it. */
5285 && ! (COMPARISON_P (x)
5286 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5287 {
5288 rtx cop1 = const0_rtx;
5289 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5290
5291 if (cond_code == NE && COMPARISON_P (cond))
5292 return x;
5293
5294 /* Simplify the alternative arms; this may collapse the true and
5295 false arms to store-flag values. Be careful to use copy_rtx
5296 here since true_rtx or false_rtx might share RTL with x as a
5297 result of the if_then_else_cond call above. */
5298 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5299 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5300
5301 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5302 is unlikely to be simpler. */
5303 if (general_operand (true_rtx, VOIDmode)
5304 && general_operand (false_rtx, VOIDmode))
5305 {
5306 enum rtx_code reversed;
5307
5308 /* Restarting if we generate a store-flag expression will cause
5309 us to loop. Just drop through in this case. */
5310
5311 /* If the result values are STORE_FLAG_VALUE and zero, we can
5312 just make the comparison operation. */
5313 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5314 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5315 cond, cop1);
5316 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5317 && ((reversed = reversed_comparison_code_parts
5318 (cond_code, cond, cop1, NULL))
5319 != UNKNOWN))
5320 x = simplify_gen_relational (reversed, mode, VOIDmode,
5321 cond, cop1);
5322
5323 /* Likewise, we can make the negate of a comparison operation
5324 if the result values are - STORE_FLAG_VALUE and zero. */
5325 else if (CONST_INT_P (true_rtx)
5326 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5327 && false_rtx == const0_rtx)
5328 x = simplify_gen_unary (NEG, mode,
5329 simplify_gen_relational (cond_code,
5330 mode, VOIDmode,
5331 cond, cop1),
5332 mode);
5333 else if (CONST_INT_P (false_rtx)
5334 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5335 && true_rtx == const0_rtx
5336 && ((reversed = reversed_comparison_code_parts
5337 (cond_code, cond, cop1, NULL))
5338 != UNKNOWN))
5339 x = simplify_gen_unary (NEG, mode,
5340 simplify_gen_relational (reversed,
5341 mode, VOIDmode,
5342 cond, cop1),
5343 mode);
5344 else
5345 return gen_rtx_IF_THEN_ELSE (mode,
5346 simplify_gen_relational (cond_code,
5347 mode,
5348 VOIDmode,
5349 cond,
5350 cop1),
5351 true_rtx, false_rtx);
5352
5353 code = GET_CODE (x);
5354 op0_mode = VOIDmode;
5355 }
5356 }
5357 }
5358
5359 /* Try to fold this expression in case we have constants that weren't
5360 present before. */
5361 temp = 0;
5362 switch (GET_RTX_CLASS (code))
5363 {
5364 case RTX_UNARY:
5365 if (op0_mode == VOIDmode)
5366 op0_mode = GET_MODE (XEXP (x, 0));
5367 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5368 break;
5369 case RTX_COMPARE:
5370 case RTX_COMM_COMPARE:
5371 {
5372 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5373 if (cmp_mode == VOIDmode)
5374 {
5375 cmp_mode = GET_MODE (XEXP (x, 1));
5376 if (cmp_mode == VOIDmode)
5377 cmp_mode = op0_mode;
5378 }
5379 temp = simplify_relational_operation (code, mode, cmp_mode,
5380 XEXP (x, 0), XEXP (x, 1));
5381 }
5382 break;
5383 case RTX_COMM_ARITH:
5384 case RTX_BIN_ARITH:
5385 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5386 break;
5387 case RTX_BITFIELD_OPS:
5388 case RTX_TERNARY:
5389 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5390 XEXP (x, 1), XEXP (x, 2));
5391 break;
5392 default:
5393 break;
5394 }
5395
5396 if (temp)
5397 {
5398 x = temp;
5399 code = GET_CODE (temp);
5400 op0_mode = VOIDmode;
5401 mode = GET_MODE (temp);
5402 }
5403
5404 /* First see if we can apply the inverse distributive law. */
5405 if (code == PLUS || code == MINUS
5406 || code == AND || code == IOR || code == XOR)
5407 {
5408 x = apply_distributive_law (x);
5409 code = GET_CODE (x);
5410 op0_mode = VOIDmode;
5411 }
5412
5413 /* If CODE is an associative operation not otherwise handled, see if we
5414 can associate some operands. This can win if they are constants or
5415 if they are logically related (i.e. (a & b) & a). */
5416 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5417 || code == AND || code == IOR || code == XOR
5418 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5419 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5420 || (flag_associative_math && FLOAT_MODE_P (mode))))
5421 {
5422 if (GET_CODE (XEXP (x, 0)) == code)
5423 {
5424 rtx other = XEXP (XEXP (x, 0), 0);
5425 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5426 rtx inner_op1 = XEXP (x, 1);
5427 rtx inner;
5428
5429 /* Make sure we pass the constant operand if any as the second
5430 one if this is a commutative operation. */
5431 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5432 {
5433 rtx tem = inner_op0;
5434 inner_op0 = inner_op1;
5435 inner_op1 = tem;
5436 }
5437 inner = simplify_binary_operation (code == MINUS ? PLUS
5438 : code == DIV ? MULT
5439 : code,
5440 mode, inner_op0, inner_op1);
5441
5442 /* For commutative operations, try the other pair if that one
5443 didn't simplify. */
5444 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5445 {
5446 other = XEXP (XEXP (x, 0), 1);
5447 inner = simplify_binary_operation (code, mode,
5448 XEXP (XEXP (x, 0), 0),
5449 XEXP (x, 1));
5450 }
5451
5452 if (inner)
5453 return simplify_gen_binary (code, mode, other, inner);
5454 }
5455 }
5456
5457 /* A little bit of algebraic simplification here. */
5458 switch (code)
5459 {
5460 case MEM:
5461 /* Ensure that our address has any ASHIFTs converted to MULT in case
5462 address-recognizing predicates are called later. */
5463 temp = make_compound_operation (XEXP (x, 0), MEM);
5464 SUBST (XEXP (x, 0), temp);
5465 break;
5466
5467 case SUBREG:
5468 if (op0_mode == VOIDmode)
5469 op0_mode = GET_MODE (SUBREG_REG (x));
5470
5471 /* See if this can be moved to simplify_subreg. */
5472 if (CONSTANT_P (SUBREG_REG (x))
5473 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5474 /* Don't call gen_lowpart if the inner mode
5475 is VOIDmode and we cannot simplify it, as SUBREG without
5476 inner mode is invalid. */
5477 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5478 || gen_lowpart_common (mode, SUBREG_REG (x))))
5479 return gen_lowpart (mode, SUBREG_REG (x));
5480
5481 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5482 break;
5483 {
5484 rtx temp;
5485 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5486 SUBREG_BYTE (x));
5487 if (temp)
5488 return temp;
5489 }
5490
5491 /* Don't change the mode of the MEM if that would change the meaning
5492 of the address. */
5493 if (MEM_P (SUBREG_REG (x))
5494 && (MEM_VOLATILE_P (SUBREG_REG (x))
5495 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5496 return gen_rtx_CLOBBER (mode, const0_rtx);
5497
5498 /* Note that we cannot do any narrowing for non-constants since
5499 we might have been counting on using the fact that some bits were
5500 zero. We now do this in the SET. */
5501
5502 break;
5503
5504 case NEG:
5505 temp = expand_compound_operation (XEXP (x, 0));
5506
5507 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5508 replaced by (lshiftrt X C). This will convert
5509 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5510
5511 if (GET_CODE (temp) == ASHIFTRT
5512 && CONST_INT_P (XEXP (temp, 1))
5513 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5514 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5515 INTVAL (XEXP (temp, 1)));
5516
5517 /* If X has only a single bit that might be nonzero, say, bit I, convert
5518 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5519 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5520 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5521 or a SUBREG of one since we'd be making the expression more
5522 complex if it was just a register. */
5523
5524 if (!REG_P (temp)
5525 && ! (GET_CODE (temp) == SUBREG
5526 && REG_P (SUBREG_REG (temp)))
5527 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5528 {
5529 rtx temp1 = simplify_shift_const
5530 (NULL_RTX, ASHIFTRT, mode,
5531 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5532 GET_MODE_BITSIZE (mode) - 1 - i),
5533 GET_MODE_BITSIZE (mode) - 1 - i);
5534
5535 /* If all we did was surround TEMP with the two shifts, we
5536 haven't improved anything, so don't use it. Otherwise,
5537 we are better off with TEMP1. */
5538 if (GET_CODE (temp1) != ASHIFTRT
5539 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5540 || XEXP (XEXP (temp1, 0), 0) != temp)
5541 return temp1;
5542 }
5543 break;
5544
5545 case TRUNCATE:
5546 /* We can't handle truncation to a partial integer mode here
5547 because we don't know the real bitsize of the partial
5548 integer mode. */
5549 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5550 break;
5551
5552 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5553 SUBST (XEXP (x, 0),
5554 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5555 GET_MODE_MASK (mode), 0));
5556
5557 /* We can truncate a constant value and return it. */
5558 if (CONST_INT_P (XEXP (x, 0)))
5559 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5560
5561 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5562 whose value is a comparison can be replaced with a subreg if
5563 STORE_FLAG_VALUE permits. */
5564 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5565 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5566 && (temp = get_last_value (XEXP (x, 0)))
5567 && COMPARISON_P (temp))
5568 return gen_lowpart (mode, XEXP (x, 0));
5569 break;
5570
5571 case CONST:
5572 /* (const (const X)) can become (const X). Do it this way rather than
5573 returning the inner CONST since CONST can be shared with a
5574 REG_EQUAL note. */
5575 if (GET_CODE (XEXP (x, 0)) == CONST)
5576 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5577 break;
5578
5579 #ifdef HAVE_lo_sum
5580 case LO_SUM:
5581 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5582 can add in an offset. find_split_point will split this address up
5583 again if it doesn't match. */
5584 if (GET_CODE (XEXP (x, 0)) == HIGH
5585 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5586 return XEXP (x, 1);
5587 break;
5588 #endif
5589
5590 case PLUS:
5591 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5592 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5593 bit-field and can be replaced by either a sign_extend or a
5594 sign_extract. The `and' may be a zero_extend and the two
5595 <c>, -<c> constants may be reversed. */
5596 if (GET_CODE (XEXP (x, 0)) == XOR
5597 && CONST_INT_P (XEXP (x, 1))
5598 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5599 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5600 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5601 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5602 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5603 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5604 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5605 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5606 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5607 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5608 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5609 == (unsigned int) i + 1))))
5610 return simplify_shift_const
5611 (NULL_RTX, ASHIFTRT, mode,
5612 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5613 XEXP (XEXP (XEXP (x, 0), 0), 0),
5614 GET_MODE_BITSIZE (mode) - (i + 1)),
5615 GET_MODE_BITSIZE (mode) - (i + 1));
5616
5617 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5618 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5619 the bitsize of the mode - 1. This allows simplification of
5620 "a = (b & 8) == 0;" */
5621 if (XEXP (x, 1) == constm1_rtx
5622 && !REG_P (XEXP (x, 0))
5623 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5624 && REG_P (SUBREG_REG (XEXP (x, 0))))
5625 && nonzero_bits (XEXP (x, 0), mode) == 1)
5626 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5627 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5628 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5629 GET_MODE_BITSIZE (mode) - 1),
5630 GET_MODE_BITSIZE (mode) - 1);
5631
5632 /* If we are adding two things that have no bits in common, convert
5633 the addition into an IOR. This will often be further simplified,
5634 for example in cases like ((a & 1) + (a & 2)), which can
5635 become a & 3. */
5636
5637 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5638 && (nonzero_bits (XEXP (x, 0), mode)
5639 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5640 {
5641 /* Try to simplify the expression further. */
5642 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5643 temp = combine_simplify_rtx (tor, mode, in_dest, 0);
5644
5645 /* If we could, great. If not, do not go ahead with the IOR
5646 replacement, since PLUS appears in many special purpose
5647 address arithmetic instructions. */
5648 if (GET_CODE (temp) != CLOBBER && temp != tor)
5649 return temp;
5650 }
5651 break;
5652
5653 case MINUS:
5654 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5655 (and <foo> (const_int pow2-1)) */
5656 if (GET_CODE (XEXP (x, 1)) == AND
5657 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5658 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5659 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5660 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5661 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5662 break;
5663
5664 case MULT:
5665 /* If we have (mult (plus A B) C), apply the distributive law and then
5666 the inverse distributive law to see if things simplify. This
5667 occurs mostly in addresses, often when unrolling loops. */
5668
5669 if (GET_CODE (XEXP (x, 0)) == PLUS)
5670 {
5671 rtx result = distribute_and_simplify_rtx (x, 0);
5672 if (result)
5673 return result;
5674 }
5675
5676 /* Try simplify a*(b/c) as (a*b)/c. */
5677 if (FLOAT_MODE_P (mode) && flag_associative_math
5678 && GET_CODE (XEXP (x, 0)) == DIV)
5679 {
5680 rtx tem = simplify_binary_operation (MULT, mode,
5681 XEXP (XEXP (x, 0), 0),
5682 XEXP (x, 1));
5683 if (tem)
5684 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5685 }
5686 break;
5687
5688 case UDIV:
5689 /* If this is a divide by a power of two, treat it as a shift if
5690 its first operand is a shift. */
5691 if (CONST_INT_P (XEXP (x, 1))
5692 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5693 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5694 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5695 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5696 || GET_CODE (XEXP (x, 0)) == ROTATE
5697 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5698 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5699 break;
5700
5701 case EQ: case NE:
5702 case GT: case GTU: case GE: case GEU:
5703 case LT: case LTU: case LE: case LEU:
5704 case UNEQ: case LTGT:
5705 case UNGT: case UNGE:
5706 case UNLT: case UNLE:
5707 case UNORDERED: case ORDERED:
5708 /* If the first operand is a condition code, we can't do anything
5709 with it. */
5710 if (GET_CODE (XEXP (x, 0)) == COMPARE
5711 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5712 && ! CC0_P (XEXP (x, 0))))
5713 {
5714 rtx op0 = XEXP (x, 0);
5715 rtx op1 = XEXP (x, 1);
5716 enum rtx_code new_code;
5717
5718 if (GET_CODE (op0) == COMPARE)
5719 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5720
5721 /* Simplify our comparison, if possible. */
5722 new_code = simplify_comparison (code, &op0, &op1);
5723
5724 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5725 if only the low-order bit is possibly nonzero in X (such as when
5726 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5727 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5728 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5729 (plus X 1).
5730
5731 Remove any ZERO_EXTRACT we made when thinking this was a
5732 comparison. It may now be simpler to use, e.g., an AND. If a
5733 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5734 the call to make_compound_operation in the SET case.
5735
5736 Don't apply these optimizations if the caller would
5737 prefer a comparison rather than a value.
5738 E.g., for the condition in an IF_THEN_ELSE most targets need
5739 an explicit comparison. */
5740
5741 if (in_cond)
5742 ;
5743
5744 else if (STORE_FLAG_VALUE == 1
5745 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5746 && op1 == const0_rtx
5747 && mode == GET_MODE (op0)
5748 && nonzero_bits (op0, mode) == 1)
5749 return gen_lowpart (mode,
5750 expand_compound_operation (op0));
5751
5752 else if (STORE_FLAG_VALUE == 1
5753 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5754 && op1 == const0_rtx
5755 && mode == GET_MODE (op0)
5756 && (num_sign_bit_copies (op0, mode)
5757 == GET_MODE_BITSIZE (mode)))
5758 {
5759 op0 = expand_compound_operation (op0);
5760 return simplify_gen_unary (NEG, mode,
5761 gen_lowpart (mode, op0),
5762 mode);
5763 }
5764
5765 else if (STORE_FLAG_VALUE == 1
5766 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5767 && op1 == const0_rtx
5768 && mode == GET_MODE (op0)
5769 && nonzero_bits (op0, mode) == 1)
5770 {
5771 op0 = expand_compound_operation (op0);
5772 return simplify_gen_binary (XOR, mode,
5773 gen_lowpart (mode, op0),
5774 const1_rtx);
5775 }
5776
5777 else if (STORE_FLAG_VALUE == 1
5778 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5779 && op1 == const0_rtx
5780 && mode == GET_MODE (op0)
5781 && (num_sign_bit_copies (op0, mode)
5782 == GET_MODE_BITSIZE (mode)))
5783 {
5784 op0 = expand_compound_operation (op0);
5785 return plus_constant (gen_lowpart (mode, op0), 1);
5786 }
5787
5788 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5789 those above. */
5790 if (in_cond)
5791 ;
5792
5793 else if (STORE_FLAG_VALUE == -1
5794 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5795 && op1 == const0_rtx
5796 && (num_sign_bit_copies (op0, mode)
5797 == GET_MODE_BITSIZE (mode)))
5798 return gen_lowpart (mode,
5799 expand_compound_operation (op0));
5800
5801 else if (STORE_FLAG_VALUE == -1
5802 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5803 && op1 == const0_rtx
5804 && mode == GET_MODE (op0)
5805 && nonzero_bits (op0, mode) == 1)
5806 {
5807 op0 = expand_compound_operation (op0);
5808 return simplify_gen_unary (NEG, mode,
5809 gen_lowpart (mode, op0),
5810 mode);
5811 }
5812
5813 else if (STORE_FLAG_VALUE == -1
5814 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5815 && op1 == const0_rtx
5816 && mode == GET_MODE (op0)
5817 && (num_sign_bit_copies (op0, mode)
5818 == GET_MODE_BITSIZE (mode)))
5819 {
5820 op0 = expand_compound_operation (op0);
5821 return simplify_gen_unary (NOT, mode,
5822 gen_lowpart (mode, op0),
5823 mode);
5824 }
5825
5826 /* If X is 0/1, (eq X 0) is X-1. */
5827 else if (STORE_FLAG_VALUE == -1
5828 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5829 && op1 == const0_rtx
5830 && mode == GET_MODE (op0)
5831 && nonzero_bits (op0, mode) == 1)
5832 {
5833 op0 = expand_compound_operation (op0);
5834 return plus_constant (gen_lowpart (mode, op0), -1);
5835 }
5836
5837 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5838 one bit that might be nonzero, we can convert (ne x 0) to
5839 (ashift x c) where C puts the bit in the sign bit. Remove any
5840 AND with STORE_FLAG_VALUE when we are done, since we are only
5841 going to test the sign bit. */
5842 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5843 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5844 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5845 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5846 && op1 == const0_rtx
5847 && mode == GET_MODE (op0)
5848 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5849 {
5850 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5851 expand_compound_operation (op0),
5852 GET_MODE_BITSIZE (mode) - 1 - i);
5853 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5854 return XEXP (x, 0);
5855 else
5856 return x;
5857 }
5858
5859 /* If the code changed, return a whole new comparison. */
5860 if (new_code != code)
5861 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5862
5863 /* Otherwise, keep this operation, but maybe change its operands.
5864 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5865 SUBST (XEXP (x, 0), op0);
5866 SUBST (XEXP (x, 1), op1);
5867 }
5868 break;
5869
5870 case IF_THEN_ELSE:
5871 return simplify_if_then_else (x);
5872
5873 case ZERO_EXTRACT:
5874 case SIGN_EXTRACT:
5875 case ZERO_EXTEND:
5876 case SIGN_EXTEND:
5877 /* If we are processing SET_DEST, we are done. */
5878 if (in_dest)
5879 return x;
5880
5881 return expand_compound_operation (x);
5882
5883 case SET:
5884 return simplify_set (x);
5885
5886 case AND:
5887 case IOR:
5888 return simplify_logical (x);
5889
5890 case ASHIFT:
5891 case LSHIFTRT:
5892 case ASHIFTRT:
5893 case ROTATE:
5894 case ROTATERT:
5895 /* If this is a shift by a constant amount, simplify it. */
5896 if (CONST_INT_P (XEXP (x, 1)))
5897 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5898 INTVAL (XEXP (x, 1)));
5899
5900 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5901 SUBST (XEXP (x, 1),
5902 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5903 ((unsigned HOST_WIDE_INT) 1
5904 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5905 - 1,
5906 0));
5907 break;
5908
5909 default:
5910 break;
5911 }
5912
5913 return x;
5914 }
5915 \f
5916 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5917
5918 static rtx
5919 simplify_if_then_else (rtx x)
5920 {
5921 enum machine_mode mode = GET_MODE (x);
5922 rtx cond = XEXP (x, 0);
5923 rtx true_rtx = XEXP (x, 1);
5924 rtx false_rtx = XEXP (x, 2);
5925 enum rtx_code true_code = GET_CODE (cond);
5926 int comparison_p = COMPARISON_P (cond);
5927 rtx temp;
5928 int i;
5929 enum rtx_code false_code;
5930 rtx reversed;
5931
5932 /* Simplify storing of the truth value. */
5933 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5934 return simplify_gen_relational (true_code, mode, VOIDmode,
5935 XEXP (cond, 0), XEXP (cond, 1));
5936
5937 /* Also when the truth value has to be reversed. */
5938 if (comparison_p
5939 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5940 && (reversed = reversed_comparison (cond, mode)))
5941 return reversed;
5942
5943 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5944 in it is being compared against certain values. Get the true and false
5945 comparisons and see if that says anything about the value of each arm. */
5946
5947 if (comparison_p
5948 && ((false_code = reversed_comparison_code (cond, NULL))
5949 != UNKNOWN)
5950 && REG_P (XEXP (cond, 0)))
5951 {
5952 HOST_WIDE_INT nzb;
5953 rtx from = XEXP (cond, 0);
5954 rtx true_val = XEXP (cond, 1);
5955 rtx false_val = true_val;
5956 int swapped = 0;
5957
5958 /* If FALSE_CODE is EQ, swap the codes and arms. */
5959
5960 if (false_code == EQ)
5961 {
5962 swapped = 1, true_code = EQ, false_code = NE;
5963 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5964 }
5965
5966 /* If we are comparing against zero and the expression being tested has
5967 only a single bit that might be nonzero, that is its value when it is
5968 not equal to zero. Similarly if it is known to be -1 or 0. */
5969
5970 if (true_code == EQ && true_val == const0_rtx
5971 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5972 {
5973 false_code = EQ;
5974 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5975 }
5976 else if (true_code == EQ && true_val == const0_rtx
5977 && (num_sign_bit_copies (from, GET_MODE (from))
5978 == GET_MODE_BITSIZE (GET_MODE (from))))
5979 {
5980 false_code = EQ;
5981 false_val = constm1_rtx;
5982 }
5983
5984 /* Now simplify an arm if we know the value of the register in the
5985 branch and it is used in the arm. Be careful due to the potential
5986 of locally-shared RTL. */
5987
5988 if (reg_mentioned_p (from, true_rtx))
5989 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5990 from, true_val),
5991 pc_rtx, pc_rtx, 0, 0, 0);
5992 if (reg_mentioned_p (from, false_rtx))
5993 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5994 from, false_val),
5995 pc_rtx, pc_rtx, 0, 0, 0);
5996
5997 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5998 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5999
6000 true_rtx = XEXP (x, 1);
6001 false_rtx = XEXP (x, 2);
6002 true_code = GET_CODE (cond);
6003 }
6004
6005 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6006 reversed, do so to avoid needing two sets of patterns for
6007 subtract-and-branch insns. Similarly if we have a constant in the true
6008 arm, the false arm is the same as the first operand of the comparison, or
6009 the false arm is more complicated than the true arm. */
6010
6011 if (comparison_p
6012 && reversed_comparison_code (cond, NULL) != UNKNOWN
6013 && (true_rtx == pc_rtx
6014 || (CONSTANT_P (true_rtx)
6015 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6016 || true_rtx == const0_rtx
6017 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6018 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6019 && !OBJECT_P (false_rtx))
6020 || reg_mentioned_p (true_rtx, false_rtx)
6021 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6022 {
6023 true_code = reversed_comparison_code (cond, NULL);
6024 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6025 SUBST (XEXP (x, 1), false_rtx);
6026 SUBST (XEXP (x, 2), true_rtx);
6027
6028 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6029 cond = XEXP (x, 0);
6030
6031 /* It is possible that the conditional has been simplified out. */
6032 true_code = GET_CODE (cond);
6033 comparison_p = COMPARISON_P (cond);
6034 }
6035
6036 /* If the two arms are identical, we don't need the comparison. */
6037
6038 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6039 return true_rtx;
6040
6041 /* Convert a == b ? b : a to "a". */
6042 if (true_code == EQ && ! side_effects_p (cond)
6043 && !HONOR_NANS (mode)
6044 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6045 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6046 return false_rtx;
6047 else if (true_code == NE && ! side_effects_p (cond)
6048 && !HONOR_NANS (mode)
6049 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6050 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6051 return true_rtx;
6052
6053 /* Look for cases where we have (abs x) or (neg (abs X)). */
6054
6055 if (GET_MODE_CLASS (mode) == MODE_INT
6056 && comparison_p
6057 && XEXP (cond, 1) == const0_rtx
6058 && GET_CODE (false_rtx) == NEG
6059 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6060 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6061 && ! side_effects_p (true_rtx))
6062 switch (true_code)
6063 {
6064 case GT:
6065 case GE:
6066 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6067 case LT:
6068 case LE:
6069 return
6070 simplify_gen_unary (NEG, mode,
6071 simplify_gen_unary (ABS, mode, true_rtx, mode),
6072 mode);
6073 default:
6074 break;
6075 }
6076
6077 /* Look for MIN or MAX. */
6078
6079 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6080 && comparison_p
6081 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6082 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6083 && ! side_effects_p (cond))
6084 switch (true_code)
6085 {
6086 case GE:
6087 case GT:
6088 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6089 case LE:
6090 case LT:
6091 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6092 case GEU:
6093 case GTU:
6094 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6095 case LEU:
6096 case LTU:
6097 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6098 default:
6099 break;
6100 }
6101
6102 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6103 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6104 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6105 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6106 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6107 neither 1 or -1, but it isn't worth checking for. */
6108
6109 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6110 && comparison_p
6111 && GET_MODE_CLASS (mode) == MODE_INT
6112 && ! side_effects_p (x))
6113 {
6114 rtx t = make_compound_operation (true_rtx, SET);
6115 rtx f = make_compound_operation (false_rtx, SET);
6116 rtx cond_op0 = XEXP (cond, 0);
6117 rtx cond_op1 = XEXP (cond, 1);
6118 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6119 enum machine_mode m = mode;
6120 rtx z = 0, c1 = NULL_RTX;
6121
6122 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6123 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6124 || GET_CODE (t) == ASHIFT
6125 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6126 && rtx_equal_p (XEXP (t, 0), f))
6127 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6128
6129 /* If an identity-zero op is commutative, check whether there
6130 would be a match if we swapped the operands. */
6131 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6132 || GET_CODE (t) == XOR)
6133 && rtx_equal_p (XEXP (t, 1), f))
6134 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6135 else if (GET_CODE (t) == SIGN_EXTEND
6136 && (GET_CODE (XEXP (t, 0)) == PLUS
6137 || GET_CODE (XEXP (t, 0)) == MINUS
6138 || GET_CODE (XEXP (t, 0)) == IOR
6139 || GET_CODE (XEXP (t, 0)) == XOR
6140 || GET_CODE (XEXP (t, 0)) == ASHIFT
6141 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6142 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6143 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6144 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6145 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6146 && (num_sign_bit_copies (f, GET_MODE (f))
6147 > (unsigned int)
6148 (GET_MODE_BITSIZE (mode)
6149 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6150 {
6151 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6152 extend_op = SIGN_EXTEND;
6153 m = GET_MODE (XEXP (t, 0));
6154 }
6155 else if (GET_CODE (t) == SIGN_EXTEND
6156 && (GET_CODE (XEXP (t, 0)) == PLUS
6157 || GET_CODE (XEXP (t, 0)) == IOR
6158 || GET_CODE (XEXP (t, 0)) == XOR)
6159 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6160 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6161 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6162 && (num_sign_bit_copies (f, GET_MODE (f))
6163 > (unsigned int)
6164 (GET_MODE_BITSIZE (mode)
6165 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6166 {
6167 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6168 extend_op = SIGN_EXTEND;
6169 m = GET_MODE (XEXP (t, 0));
6170 }
6171 else if (GET_CODE (t) == ZERO_EXTEND
6172 && (GET_CODE (XEXP (t, 0)) == PLUS
6173 || GET_CODE (XEXP (t, 0)) == MINUS
6174 || GET_CODE (XEXP (t, 0)) == IOR
6175 || GET_CODE (XEXP (t, 0)) == XOR
6176 || GET_CODE (XEXP (t, 0)) == ASHIFT
6177 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6178 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6179 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6180 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6181 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6182 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6183 && ((nonzero_bits (f, GET_MODE (f))
6184 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6185 == 0))
6186 {
6187 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6188 extend_op = ZERO_EXTEND;
6189 m = GET_MODE (XEXP (t, 0));
6190 }
6191 else if (GET_CODE (t) == ZERO_EXTEND
6192 && (GET_CODE (XEXP (t, 0)) == PLUS
6193 || GET_CODE (XEXP (t, 0)) == IOR
6194 || GET_CODE (XEXP (t, 0)) == XOR)
6195 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6196 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6197 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6198 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6199 && ((nonzero_bits (f, GET_MODE (f))
6200 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6201 == 0))
6202 {
6203 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6204 extend_op = ZERO_EXTEND;
6205 m = GET_MODE (XEXP (t, 0));
6206 }
6207
6208 if (z)
6209 {
6210 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6211 cond_op0, cond_op1),
6212 pc_rtx, pc_rtx, 0, 0, 0);
6213 temp = simplify_gen_binary (MULT, m, temp,
6214 simplify_gen_binary (MULT, m, c1,
6215 const_true_rtx));
6216 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6217 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6218
6219 if (extend_op != UNKNOWN)
6220 temp = simplify_gen_unary (extend_op, mode, temp, m);
6221
6222 return temp;
6223 }
6224 }
6225
6226 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6227 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6228 negation of a single bit, we can convert this operation to a shift. We
6229 can actually do this more generally, but it doesn't seem worth it. */
6230
6231 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6232 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6233 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6234 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6235 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6236 == GET_MODE_BITSIZE (mode))
6237 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6238 return
6239 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6240 gen_lowpart (mode, XEXP (cond, 0)), i);
6241
6242 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6243 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6244 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6245 && GET_MODE (XEXP (cond, 0)) == mode
6246 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6247 == nonzero_bits (XEXP (cond, 0), mode)
6248 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6249 return XEXP (cond, 0);
6250
6251 return x;
6252 }
6253 \f
6254 /* Simplify X, a SET expression. Return the new expression. */
6255
6256 static rtx
6257 simplify_set (rtx x)
6258 {
6259 rtx src = SET_SRC (x);
6260 rtx dest = SET_DEST (x);
6261 enum machine_mode mode
6262 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6263 rtx other_insn;
6264 rtx *cc_use;
6265
6266 /* (set (pc) (return)) gets written as (return). */
6267 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
6268 return src;
6269
6270 /* Now that we know for sure which bits of SRC we are using, see if we can
6271 simplify the expression for the object knowing that we only need the
6272 low-order bits. */
6273
6274 if (GET_MODE_CLASS (mode) == MODE_INT
6275 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6276 {
6277 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6278 SUBST (SET_SRC (x), src);
6279 }
6280
6281 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6282 the comparison result and try to simplify it unless we already have used
6283 undobuf.other_insn. */
6284 if ((GET_MODE_CLASS (mode) == MODE_CC
6285 || GET_CODE (src) == COMPARE
6286 || CC0_P (dest))
6287 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6288 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6289 && COMPARISON_P (*cc_use)
6290 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6291 {
6292 enum rtx_code old_code = GET_CODE (*cc_use);
6293 enum rtx_code new_code;
6294 rtx op0, op1, tmp;
6295 int other_changed = 0;
6296 rtx inner_compare = NULL_RTX;
6297 enum machine_mode compare_mode = GET_MODE (dest);
6298
6299 if (GET_CODE (src) == COMPARE)
6300 {
6301 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6302 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6303 {
6304 inner_compare = op0;
6305 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6306 }
6307 }
6308 else
6309 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6310
6311 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6312 op0, op1);
6313 if (!tmp)
6314 new_code = old_code;
6315 else if (!CONSTANT_P (tmp))
6316 {
6317 new_code = GET_CODE (tmp);
6318 op0 = XEXP (tmp, 0);
6319 op1 = XEXP (tmp, 1);
6320 }
6321 else
6322 {
6323 rtx pat = PATTERN (other_insn);
6324 undobuf.other_insn = other_insn;
6325 SUBST (*cc_use, tmp);
6326
6327 /* Attempt to simplify CC user. */
6328 if (GET_CODE (pat) == SET)
6329 {
6330 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6331 if (new_rtx != NULL_RTX)
6332 SUBST (SET_SRC (pat), new_rtx);
6333 }
6334
6335 /* Convert X into a no-op move. */
6336 SUBST (SET_DEST (x), pc_rtx);
6337 SUBST (SET_SRC (x), pc_rtx);
6338 return x;
6339 }
6340
6341 /* Simplify our comparison, if possible. */
6342 new_code = simplify_comparison (new_code, &op0, &op1);
6343
6344 #ifdef SELECT_CC_MODE
6345 /* If this machine has CC modes other than CCmode, check to see if we
6346 need to use a different CC mode here. */
6347 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6348 compare_mode = GET_MODE (op0);
6349 else if (inner_compare
6350 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6351 && new_code == old_code
6352 && op0 == XEXP (inner_compare, 0)
6353 && op1 == XEXP (inner_compare, 1))
6354 compare_mode = GET_MODE (inner_compare);
6355 else
6356 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6357
6358 #ifndef HAVE_cc0
6359 /* If the mode changed, we have to change SET_DEST, the mode in the
6360 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6361 a hard register, just build new versions with the proper mode. If it
6362 is a pseudo, we lose unless it is only time we set the pseudo, in
6363 which case we can safely change its mode. */
6364 if (compare_mode != GET_MODE (dest))
6365 {
6366 if (can_change_dest_mode (dest, 0, compare_mode))
6367 {
6368 unsigned int regno = REGNO (dest);
6369 rtx new_dest;
6370
6371 if (regno < FIRST_PSEUDO_REGISTER)
6372 new_dest = gen_rtx_REG (compare_mode, regno);
6373 else
6374 {
6375 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6376 new_dest = regno_reg_rtx[regno];
6377 }
6378
6379 SUBST (SET_DEST (x), new_dest);
6380 SUBST (XEXP (*cc_use, 0), new_dest);
6381 other_changed = 1;
6382
6383 dest = new_dest;
6384 }
6385 }
6386 #endif /* cc0 */
6387 #endif /* SELECT_CC_MODE */
6388
6389 /* If the code changed, we have to build a new comparison in
6390 undobuf.other_insn. */
6391 if (new_code != old_code)
6392 {
6393 int other_changed_previously = other_changed;
6394 unsigned HOST_WIDE_INT mask;
6395 rtx old_cc_use = *cc_use;
6396
6397 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6398 dest, const0_rtx));
6399 other_changed = 1;
6400
6401 /* If the only change we made was to change an EQ into an NE or
6402 vice versa, OP0 has only one bit that might be nonzero, and OP1
6403 is zero, check if changing the user of the condition code will
6404 produce a valid insn. If it won't, we can keep the original code
6405 in that insn by surrounding our operation with an XOR. */
6406
6407 if (((old_code == NE && new_code == EQ)
6408 || (old_code == EQ && new_code == NE))
6409 && ! other_changed_previously && op1 == const0_rtx
6410 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6411 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6412 {
6413 rtx pat = PATTERN (other_insn), note = 0;
6414
6415 if ((recog_for_combine (&pat, other_insn, &note) < 0
6416 && ! check_asm_operands (pat)))
6417 {
6418 *cc_use = old_cc_use;
6419 other_changed = 0;
6420
6421 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6422 op0, GEN_INT (mask));
6423 }
6424 }
6425 }
6426
6427 if (other_changed)
6428 undobuf.other_insn = other_insn;
6429
6430 /* Otherwise, if we didn't previously have a COMPARE in the
6431 correct mode, we need one. */
6432 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6433 {
6434 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6435 src = SET_SRC (x);
6436 }
6437 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6438 {
6439 SUBST (SET_SRC (x), op0);
6440 src = SET_SRC (x);
6441 }
6442 /* Otherwise, update the COMPARE if needed. */
6443 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6444 {
6445 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6446 src = SET_SRC (x);
6447 }
6448 }
6449 else
6450 {
6451 /* Get SET_SRC in a form where we have placed back any
6452 compound expressions. Then do the checks below. */
6453 src = make_compound_operation (src, SET);
6454 SUBST (SET_SRC (x), src);
6455 }
6456
6457 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6458 and X being a REG or (subreg (reg)), we may be able to convert this to
6459 (set (subreg:m2 x) (op)).
6460
6461 We can always do this if M1 is narrower than M2 because that means that
6462 we only care about the low bits of the result.
6463
6464 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6465 perform a narrower operation than requested since the high-order bits will
6466 be undefined. On machine where it is defined, this transformation is safe
6467 as long as M1 and M2 have the same number of words. */
6468
6469 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6470 && !OBJECT_P (SUBREG_REG (src))
6471 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6472 / UNITS_PER_WORD)
6473 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6474 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6475 #ifndef WORD_REGISTER_OPERATIONS
6476 && (GET_MODE_SIZE (GET_MODE (src))
6477 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6478 #endif
6479 #ifdef CANNOT_CHANGE_MODE_CLASS
6480 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6481 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6482 GET_MODE (SUBREG_REG (src)),
6483 GET_MODE (src)))
6484 #endif
6485 && (REG_P (dest)
6486 || (GET_CODE (dest) == SUBREG
6487 && REG_P (SUBREG_REG (dest)))))
6488 {
6489 SUBST (SET_DEST (x),
6490 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6491 dest));
6492 SUBST (SET_SRC (x), SUBREG_REG (src));
6493
6494 src = SET_SRC (x), dest = SET_DEST (x);
6495 }
6496
6497 #ifdef HAVE_cc0
6498 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6499 in SRC. */
6500 if (dest == cc0_rtx
6501 && GET_CODE (src) == SUBREG
6502 && subreg_lowpart_p (src)
6503 && (GET_MODE_BITSIZE (GET_MODE (src))
6504 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6505 {
6506 rtx inner = SUBREG_REG (src);
6507 enum machine_mode inner_mode = GET_MODE (inner);
6508
6509 /* Here we make sure that we don't have a sign bit on. */
6510 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6511 && (nonzero_bits (inner, inner_mode)
6512 < ((unsigned HOST_WIDE_INT) 1
6513 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6514 {
6515 SUBST (SET_SRC (x), inner);
6516 src = SET_SRC (x);
6517 }
6518 }
6519 #endif
6520
6521 #ifdef LOAD_EXTEND_OP
6522 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6523 would require a paradoxical subreg. Replace the subreg with a
6524 zero_extend to avoid the reload that would otherwise be required. */
6525
6526 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6527 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6528 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6529 && SUBREG_BYTE (src) == 0
6530 && (GET_MODE_SIZE (GET_MODE (src))
6531 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6532 && MEM_P (SUBREG_REG (src)))
6533 {
6534 SUBST (SET_SRC (x),
6535 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6536 GET_MODE (src), SUBREG_REG (src)));
6537
6538 src = SET_SRC (x);
6539 }
6540 #endif
6541
6542 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6543 are comparing an item known to be 0 or -1 against 0, use a logical
6544 operation instead. Check for one of the arms being an IOR of the other
6545 arm with some value. We compute three terms to be IOR'ed together. In
6546 practice, at most two will be nonzero. Then we do the IOR's. */
6547
6548 if (GET_CODE (dest) != PC
6549 && GET_CODE (src) == IF_THEN_ELSE
6550 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6551 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6552 && XEXP (XEXP (src, 0), 1) == const0_rtx
6553 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6554 #ifdef HAVE_conditional_move
6555 && ! can_conditionally_move_p (GET_MODE (src))
6556 #endif
6557 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6558 GET_MODE (XEXP (XEXP (src, 0), 0)))
6559 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6560 && ! side_effects_p (src))
6561 {
6562 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6563 ? XEXP (src, 1) : XEXP (src, 2));
6564 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6565 ? XEXP (src, 2) : XEXP (src, 1));
6566 rtx term1 = const0_rtx, term2, term3;
6567
6568 if (GET_CODE (true_rtx) == IOR
6569 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6570 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6571 else if (GET_CODE (true_rtx) == IOR
6572 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6573 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6574 else if (GET_CODE (false_rtx) == IOR
6575 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6576 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6577 else if (GET_CODE (false_rtx) == IOR
6578 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6579 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6580
6581 term2 = simplify_gen_binary (AND, GET_MODE (src),
6582 XEXP (XEXP (src, 0), 0), true_rtx);
6583 term3 = simplify_gen_binary (AND, GET_MODE (src),
6584 simplify_gen_unary (NOT, GET_MODE (src),
6585 XEXP (XEXP (src, 0), 0),
6586 GET_MODE (src)),
6587 false_rtx);
6588
6589 SUBST (SET_SRC (x),
6590 simplify_gen_binary (IOR, GET_MODE (src),
6591 simplify_gen_binary (IOR, GET_MODE (src),
6592 term1, term2),
6593 term3));
6594
6595 src = SET_SRC (x);
6596 }
6597
6598 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6599 whole thing fail. */
6600 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6601 return src;
6602 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6603 return dest;
6604 else
6605 /* Convert this into a field assignment operation, if possible. */
6606 return make_field_assignment (x);
6607 }
6608 \f
6609 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6610 result. */
6611
6612 static rtx
6613 simplify_logical (rtx x)
6614 {
6615 enum machine_mode mode = GET_MODE (x);
6616 rtx op0 = XEXP (x, 0);
6617 rtx op1 = XEXP (x, 1);
6618
6619 switch (GET_CODE (x))
6620 {
6621 case AND:
6622 /* We can call simplify_and_const_int only if we don't lose
6623 any (sign) bits when converting INTVAL (op1) to
6624 "unsigned HOST_WIDE_INT". */
6625 if (CONST_INT_P (op1)
6626 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6627 || INTVAL (op1) > 0))
6628 {
6629 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6630 if (GET_CODE (x) != AND)
6631 return x;
6632
6633 op0 = XEXP (x, 0);
6634 op1 = XEXP (x, 1);
6635 }
6636
6637 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6638 apply the distributive law and then the inverse distributive
6639 law to see if things simplify. */
6640 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6641 {
6642 rtx result = distribute_and_simplify_rtx (x, 0);
6643 if (result)
6644 return result;
6645 }
6646 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6647 {
6648 rtx result = distribute_and_simplify_rtx (x, 1);
6649 if (result)
6650 return result;
6651 }
6652 break;
6653
6654 case IOR:
6655 /* If we have (ior (and A B) C), apply the distributive law and then
6656 the inverse distributive law to see if things simplify. */
6657
6658 if (GET_CODE (op0) == AND)
6659 {
6660 rtx result = distribute_and_simplify_rtx (x, 0);
6661 if (result)
6662 return result;
6663 }
6664
6665 if (GET_CODE (op1) == AND)
6666 {
6667 rtx result = distribute_and_simplify_rtx (x, 1);
6668 if (result)
6669 return result;
6670 }
6671 break;
6672
6673 default:
6674 gcc_unreachable ();
6675 }
6676
6677 return x;
6678 }
6679 \f
6680 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6681 operations" because they can be replaced with two more basic operations.
6682 ZERO_EXTEND is also considered "compound" because it can be replaced with
6683 an AND operation, which is simpler, though only one operation.
6684
6685 The function expand_compound_operation is called with an rtx expression
6686 and will convert it to the appropriate shifts and AND operations,
6687 simplifying at each stage.
6688
6689 The function make_compound_operation is called to convert an expression
6690 consisting of shifts and ANDs into the equivalent compound expression.
6691 It is the inverse of this function, loosely speaking. */
6692
6693 static rtx
6694 expand_compound_operation (rtx x)
6695 {
6696 unsigned HOST_WIDE_INT pos = 0, len;
6697 int unsignedp = 0;
6698 unsigned int modewidth;
6699 rtx tem;
6700
6701 switch (GET_CODE (x))
6702 {
6703 case ZERO_EXTEND:
6704 unsignedp = 1;
6705 case SIGN_EXTEND:
6706 /* We can't necessarily use a const_int for a multiword mode;
6707 it depends on implicitly extending the value.
6708 Since we don't know the right way to extend it,
6709 we can't tell whether the implicit way is right.
6710
6711 Even for a mode that is no wider than a const_int,
6712 we can't win, because we need to sign extend one of its bits through
6713 the rest of it, and we don't know which bit. */
6714 if (CONST_INT_P (XEXP (x, 0)))
6715 return x;
6716
6717 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6718 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6719 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6720 reloaded. If not for that, MEM's would very rarely be safe.
6721
6722 Reject MODEs bigger than a word, because we might not be able
6723 to reference a two-register group starting with an arbitrary register
6724 (and currently gen_lowpart might crash for a SUBREG). */
6725
6726 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6727 return x;
6728
6729 /* Reject MODEs that aren't scalar integers because turning vector
6730 or complex modes into shifts causes problems. */
6731
6732 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6733 return x;
6734
6735 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6736 /* If the inner object has VOIDmode (the only way this can happen
6737 is if it is an ASM_OPERANDS), we can't do anything since we don't
6738 know how much masking to do. */
6739 if (len == 0)
6740 return x;
6741
6742 break;
6743
6744 case ZERO_EXTRACT:
6745 unsignedp = 1;
6746
6747 /* ... fall through ... */
6748
6749 case SIGN_EXTRACT:
6750 /* If the operand is a CLOBBER, just return it. */
6751 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6752 return XEXP (x, 0);
6753
6754 if (!CONST_INT_P (XEXP (x, 1))
6755 || !CONST_INT_P (XEXP (x, 2))
6756 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6757 return x;
6758
6759 /* Reject MODEs that aren't scalar integers because turning vector
6760 or complex modes into shifts causes problems. */
6761
6762 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6763 return x;
6764
6765 len = INTVAL (XEXP (x, 1));
6766 pos = INTVAL (XEXP (x, 2));
6767
6768 /* This should stay within the object being extracted, fail otherwise. */
6769 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6770 return x;
6771
6772 if (BITS_BIG_ENDIAN)
6773 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6774
6775 break;
6776
6777 default:
6778 return x;
6779 }
6780 /* Convert sign extension to zero extension, if we know that the high
6781 bit is not set, as this is easier to optimize. It will be converted
6782 back to cheaper alternative in make_extraction. */
6783 if (GET_CODE (x) == SIGN_EXTEND
6784 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6785 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6786 & ~(((unsigned HOST_WIDE_INT)
6787 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6788 >> 1))
6789 == 0)))
6790 {
6791 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6792 rtx temp2 = expand_compound_operation (temp);
6793
6794 /* Make sure this is a profitable operation. */
6795 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6796 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6797 return temp2;
6798 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6799 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6800 return temp;
6801 else
6802 return x;
6803 }
6804
6805 /* We can optimize some special cases of ZERO_EXTEND. */
6806 if (GET_CODE (x) == ZERO_EXTEND)
6807 {
6808 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6809 know that the last value didn't have any inappropriate bits
6810 set. */
6811 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6812 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6813 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6814 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6815 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6816 return XEXP (XEXP (x, 0), 0);
6817
6818 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6819 if (GET_CODE (XEXP (x, 0)) == SUBREG
6820 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6821 && subreg_lowpart_p (XEXP (x, 0))
6822 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6823 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6824 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6825 return SUBREG_REG (XEXP (x, 0));
6826
6827 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6828 is a comparison and STORE_FLAG_VALUE permits. This is like
6829 the first case, but it works even when GET_MODE (x) is larger
6830 than HOST_WIDE_INT. */
6831 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6832 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6833 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6834 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6835 <= HOST_BITS_PER_WIDE_INT)
6836 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6837 return XEXP (XEXP (x, 0), 0);
6838
6839 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6840 if (GET_CODE (XEXP (x, 0)) == SUBREG
6841 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6842 && subreg_lowpart_p (XEXP (x, 0))
6843 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6844 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6845 <= HOST_BITS_PER_WIDE_INT)
6846 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6847 return SUBREG_REG (XEXP (x, 0));
6848
6849 }
6850
6851 /* If we reach here, we want to return a pair of shifts. The inner
6852 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6853 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6854 logical depending on the value of UNSIGNEDP.
6855
6856 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6857 converted into an AND of a shift.
6858
6859 We must check for the case where the left shift would have a negative
6860 count. This can happen in a case like (x >> 31) & 255 on machines
6861 that can't shift by a constant. On those machines, we would first
6862 combine the shift with the AND to produce a variable-position
6863 extraction. Then the constant of 31 would be substituted in
6864 to produce such a position. */
6865
6866 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6867 if (modewidth >= pos + len)
6868 {
6869 enum machine_mode mode = GET_MODE (x);
6870 tem = gen_lowpart (mode, XEXP (x, 0));
6871 if (!tem || GET_CODE (tem) == CLOBBER)
6872 return x;
6873 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6874 tem, modewidth - pos - len);
6875 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6876 mode, tem, modewidth - len);
6877 }
6878 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6879 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6880 simplify_shift_const (NULL_RTX, LSHIFTRT,
6881 GET_MODE (x),
6882 XEXP (x, 0), pos),
6883 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6884 else
6885 /* Any other cases we can't handle. */
6886 return x;
6887
6888 /* If we couldn't do this for some reason, return the original
6889 expression. */
6890 if (GET_CODE (tem) == CLOBBER)
6891 return x;
6892
6893 return tem;
6894 }
6895 \f
6896 /* X is a SET which contains an assignment of one object into
6897 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6898 or certain SUBREGS). If possible, convert it into a series of
6899 logical operations.
6900
6901 We half-heartedly support variable positions, but do not at all
6902 support variable lengths. */
6903
6904 static const_rtx
6905 expand_field_assignment (const_rtx x)
6906 {
6907 rtx inner;
6908 rtx pos; /* Always counts from low bit. */
6909 int len;
6910 rtx mask, cleared, masked;
6911 enum machine_mode compute_mode;
6912
6913 /* Loop until we find something we can't simplify. */
6914 while (1)
6915 {
6916 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6917 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6918 {
6919 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6920 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6921 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6922 }
6923 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6924 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6925 {
6926 inner = XEXP (SET_DEST (x), 0);
6927 len = INTVAL (XEXP (SET_DEST (x), 1));
6928 pos = XEXP (SET_DEST (x), 2);
6929
6930 /* A constant position should stay within the width of INNER. */
6931 if (CONST_INT_P (pos)
6932 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6933 break;
6934
6935 if (BITS_BIG_ENDIAN)
6936 {
6937 if (CONST_INT_P (pos))
6938 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6939 - INTVAL (pos));
6940 else if (GET_CODE (pos) == MINUS
6941 && CONST_INT_P (XEXP (pos, 1))
6942 && (INTVAL (XEXP (pos, 1))
6943 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6944 /* If position is ADJUST - X, new position is X. */
6945 pos = XEXP (pos, 0);
6946 else
6947 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6948 GEN_INT (GET_MODE_BITSIZE (
6949 GET_MODE (inner))
6950 - len),
6951 pos);
6952 }
6953 }
6954
6955 /* A SUBREG between two modes that occupy the same numbers of words
6956 can be done by moving the SUBREG to the source. */
6957 else if (GET_CODE (SET_DEST (x)) == SUBREG
6958 /* We need SUBREGs to compute nonzero_bits properly. */
6959 && nonzero_sign_valid
6960 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6961 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6962 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6963 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6964 {
6965 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6966 gen_lowpart
6967 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6968 SET_SRC (x)));
6969 continue;
6970 }
6971 else
6972 break;
6973
6974 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6975 inner = SUBREG_REG (inner);
6976
6977 compute_mode = GET_MODE (inner);
6978
6979 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6980 if (! SCALAR_INT_MODE_P (compute_mode))
6981 {
6982 enum machine_mode imode;
6983
6984 /* Don't do anything for vector or complex integral types. */
6985 if (! FLOAT_MODE_P (compute_mode))
6986 break;
6987
6988 /* Try to find an integral mode to pun with. */
6989 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6990 if (imode == BLKmode)
6991 break;
6992
6993 compute_mode = imode;
6994 inner = gen_lowpart (imode, inner);
6995 }
6996
6997 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6998 if (len >= HOST_BITS_PER_WIDE_INT)
6999 break;
7000
7001 /* Now compute the equivalent expression. Make a copy of INNER
7002 for the SET_DEST in case it is a MEM into which we will substitute;
7003 we don't want shared RTL in that case. */
7004 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
7005 cleared = simplify_gen_binary (AND, compute_mode,
7006 simplify_gen_unary (NOT, compute_mode,
7007 simplify_gen_binary (ASHIFT,
7008 compute_mode,
7009 mask, pos),
7010 compute_mode),
7011 inner);
7012 masked = simplify_gen_binary (ASHIFT, compute_mode,
7013 simplify_gen_binary (
7014 AND, compute_mode,
7015 gen_lowpart (compute_mode, SET_SRC (x)),
7016 mask),
7017 pos);
7018
7019 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7020 simplify_gen_binary (IOR, compute_mode,
7021 cleared, masked));
7022 }
7023
7024 return x;
7025 }
7026 \f
7027 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7028 it is an RTX that represents a variable starting position; otherwise,
7029 POS is the (constant) starting bit position (counted from the LSB).
7030
7031 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7032 signed reference.
7033
7034 IN_DEST is nonzero if this is a reference in the destination of a
7035 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7036 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7037 be used.
7038
7039 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7040 ZERO_EXTRACT should be built even for bits starting at bit 0.
7041
7042 MODE is the desired mode of the result (if IN_DEST == 0).
7043
7044 The result is an RTX for the extraction or NULL_RTX if the target
7045 can't handle it. */
7046
7047 static rtx
7048 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7049 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7050 int in_dest, int in_compare)
7051 {
7052 /* This mode describes the size of the storage area
7053 to fetch the overall value from. Within that, we
7054 ignore the POS lowest bits, etc. */
7055 enum machine_mode is_mode = GET_MODE (inner);
7056 enum machine_mode inner_mode;
7057 enum machine_mode wanted_inner_mode;
7058 enum machine_mode wanted_inner_reg_mode = word_mode;
7059 enum machine_mode pos_mode = word_mode;
7060 enum machine_mode extraction_mode = word_mode;
7061 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7062 rtx new_rtx = 0;
7063 rtx orig_pos_rtx = pos_rtx;
7064 HOST_WIDE_INT orig_pos;
7065
7066 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7067 {
7068 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7069 consider just the QI as the memory to extract from.
7070 The subreg adds or removes high bits; its mode is
7071 irrelevant to the meaning of this extraction,
7072 since POS and LEN count from the lsb. */
7073 if (MEM_P (SUBREG_REG (inner)))
7074 is_mode = GET_MODE (SUBREG_REG (inner));
7075 inner = SUBREG_REG (inner);
7076 }
7077 else if (GET_CODE (inner) == ASHIFT
7078 && CONST_INT_P (XEXP (inner, 1))
7079 && pos_rtx == 0 && pos == 0
7080 && len > UINTVAL (XEXP (inner, 1)))
7081 {
7082 /* We're extracting the least significant bits of an rtx
7083 (ashift X (const_int C)), where LEN > C. Extract the
7084 least significant (LEN - C) bits of X, giving an rtx
7085 whose mode is MODE, then shift it left C times. */
7086 new_rtx = make_extraction (mode, XEXP (inner, 0),
7087 0, 0, len - INTVAL (XEXP (inner, 1)),
7088 unsignedp, in_dest, in_compare);
7089 if (new_rtx != 0)
7090 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7091 }
7092
7093 inner_mode = GET_MODE (inner);
7094
7095 if (pos_rtx && CONST_INT_P (pos_rtx))
7096 pos = INTVAL (pos_rtx), pos_rtx = 0;
7097
7098 /* See if this can be done without an extraction. We never can if the
7099 width of the field is not the same as that of some integer mode. For
7100 registers, we can only avoid the extraction if the position is at the
7101 low-order bit and this is either not in the destination or we have the
7102 appropriate STRICT_LOW_PART operation available.
7103
7104 For MEM, we can avoid an extract if the field starts on an appropriate
7105 boundary and we can change the mode of the memory reference. */
7106
7107 if (tmode != BLKmode
7108 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7109 && !MEM_P (inner)
7110 && (inner_mode == tmode
7111 || !REG_P (inner)
7112 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
7113 GET_MODE_BITSIZE (inner_mode))
7114 || reg_truncated_to_mode (tmode, inner))
7115 && (! in_dest
7116 || (REG_P (inner)
7117 && have_insn_for (STRICT_LOW_PART, tmode))))
7118 || (MEM_P (inner) && pos_rtx == 0
7119 && (pos
7120 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7121 : BITS_PER_UNIT)) == 0
7122 /* We can't do this if we are widening INNER_MODE (it
7123 may not be aligned, for one thing). */
7124 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
7125 && (inner_mode == tmode
7126 || (! mode_dependent_address_p (XEXP (inner, 0))
7127 && ! MEM_VOLATILE_P (inner))))))
7128 {
7129 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7130 field. If the original and current mode are the same, we need not
7131 adjust the offset. Otherwise, we do if bytes big endian.
7132
7133 If INNER is not a MEM, get a piece consisting of just the field
7134 of interest (in this case POS % BITS_PER_WORD must be 0). */
7135
7136 if (MEM_P (inner))
7137 {
7138 HOST_WIDE_INT offset;
7139
7140 /* POS counts from lsb, but make OFFSET count in memory order. */
7141 if (BYTES_BIG_ENDIAN)
7142 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
7143 else
7144 offset = pos / BITS_PER_UNIT;
7145
7146 new_rtx = adjust_address_nv (inner, tmode, offset);
7147 }
7148 else if (REG_P (inner))
7149 {
7150 if (tmode != inner_mode)
7151 {
7152 /* We can't call gen_lowpart in a DEST since we
7153 always want a SUBREG (see below) and it would sometimes
7154 return a new hard register. */
7155 if (pos || in_dest)
7156 {
7157 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7158
7159 if (WORDS_BIG_ENDIAN
7160 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7161 final_word = ((GET_MODE_SIZE (inner_mode)
7162 - GET_MODE_SIZE (tmode))
7163 / UNITS_PER_WORD) - final_word;
7164
7165 final_word *= UNITS_PER_WORD;
7166 if (BYTES_BIG_ENDIAN &&
7167 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7168 final_word += (GET_MODE_SIZE (inner_mode)
7169 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7170
7171 /* Avoid creating invalid subregs, for example when
7172 simplifying (x>>32)&255. */
7173 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7174 return NULL_RTX;
7175
7176 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7177 }
7178 else
7179 new_rtx = gen_lowpart (tmode, inner);
7180 }
7181 else
7182 new_rtx = inner;
7183 }
7184 else
7185 new_rtx = force_to_mode (inner, tmode,
7186 len >= HOST_BITS_PER_WIDE_INT
7187 ? ~(unsigned HOST_WIDE_INT) 0
7188 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7189 0);
7190
7191 /* If this extraction is going into the destination of a SET,
7192 make a STRICT_LOW_PART unless we made a MEM. */
7193
7194 if (in_dest)
7195 return (MEM_P (new_rtx) ? new_rtx
7196 : (GET_CODE (new_rtx) != SUBREG
7197 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7198 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7199
7200 if (mode == tmode)
7201 return new_rtx;
7202
7203 if (CONST_INT_P (new_rtx)
7204 || GET_CODE (new_rtx) == CONST_DOUBLE)
7205 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7206 mode, new_rtx, tmode);
7207
7208 /* If we know that no extraneous bits are set, and that the high
7209 bit is not set, convert the extraction to the cheaper of
7210 sign and zero extension, that are equivalent in these cases. */
7211 if (flag_expensive_optimizations
7212 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
7213 && ((nonzero_bits (new_rtx, tmode)
7214 & ~(((unsigned HOST_WIDE_INT)
7215 GET_MODE_MASK (tmode))
7216 >> 1))
7217 == 0)))
7218 {
7219 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7220 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7221
7222 /* Prefer ZERO_EXTENSION, since it gives more information to
7223 backends. */
7224 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
7225 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
7226 return temp;
7227 return temp1;
7228 }
7229
7230 /* Otherwise, sign- or zero-extend unless we already are in the
7231 proper mode. */
7232
7233 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7234 mode, new_rtx));
7235 }
7236
7237 /* Unless this is a COMPARE or we have a funny memory reference,
7238 don't do anything with zero-extending field extracts starting at
7239 the low-order bit since they are simple AND operations. */
7240 if (pos_rtx == 0 && pos == 0 && ! in_dest
7241 && ! in_compare && unsignedp)
7242 return 0;
7243
7244 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7245 if the position is not a constant and the length is not 1. In all
7246 other cases, we would only be going outside our object in cases when
7247 an original shift would have been undefined. */
7248 if (MEM_P (inner)
7249 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
7250 || (pos_rtx != 0 && len != 1)))
7251 return 0;
7252
7253 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7254 and the mode for the result. */
7255 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7256 {
7257 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7258 pos_mode = mode_for_extraction (EP_insv, 2);
7259 extraction_mode = mode_for_extraction (EP_insv, 3);
7260 }
7261
7262 if (! in_dest && unsignedp
7263 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7264 {
7265 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7266 pos_mode = mode_for_extraction (EP_extzv, 3);
7267 extraction_mode = mode_for_extraction (EP_extzv, 0);
7268 }
7269
7270 if (! in_dest && ! unsignedp
7271 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7272 {
7273 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7274 pos_mode = mode_for_extraction (EP_extv, 3);
7275 extraction_mode = mode_for_extraction (EP_extv, 0);
7276 }
7277
7278 /* Never narrow an object, since that might not be safe. */
7279
7280 if (mode != VOIDmode
7281 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7282 extraction_mode = mode;
7283
7284 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7285 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7286 pos_mode = GET_MODE (pos_rtx);
7287
7288 /* If this is not from memory, the desired mode is the preferred mode
7289 for an extraction pattern's first input operand, or word_mode if there
7290 is none. */
7291 if (!MEM_P (inner))
7292 wanted_inner_mode = wanted_inner_reg_mode;
7293 else
7294 {
7295 /* Be careful not to go beyond the extracted object and maintain the
7296 natural alignment of the memory. */
7297 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7298 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7299 > GET_MODE_BITSIZE (wanted_inner_mode))
7300 {
7301 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7302 gcc_assert (wanted_inner_mode != VOIDmode);
7303 }
7304
7305 /* If we have to change the mode of memory and cannot, the desired mode
7306 is EXTRACTION_MODE. */
7307 if (inner_mode != wanted_inner_mode
7308 && (mode_dependent_address_p (XEXP (inner, 0))
7309 || MEM_VOLATILE_P (inner)
7310 || pos_rtx))
7311 wanted_inner_mode = extraction_mode;
7312 }
7313
7314 orig_pos = pos;
7315
7316 if (BITS_BIG_ENDIAN)
7317 {
7318 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7319 BITS_BIG_ENDIAN style. If position is constant, compute new
7320 position. Otherwise, build subtraction.
7321 Note that POS is relative to the mode of the original argument.
7322 If it's a MEM we need to recompute POS relative to that.
7323 However, if we're extracting from (or inserting into) a register,
7324 we want to recompute POS relative to wanted_inner_mode. */
7325 int width = (MEM_P (inner)
7326 ? GET_MODE_BITSIZE (is_mode)
7327 : GET_MODE_BITSIZE (wanted_inner_mode));
7328
7329 if (pos_rtx == 0)
7330 pos = width - len - pos;
7331 else
7332 pos_rtx
7333 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7334 /* POS may be less than 0 now, but we check for that below.
7335 Note that it can only be less than 0 if !MEM_P (inner). */
7336 }
7337
7338 /* If INNER has a wider mode, and this is a constant extraction, try to
7339 make it smaller and adjust the byte to point to the byte containing
7340 the value. */
7341 if (wanted_inner_mode != VOIDmode
7342 && inner_mode != wanted_inner_mode
7343 && ! pos_rtx
7344 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7345 && MEM_P (inner)
7346 && ! mode_dependent_address_p (XEXP (inner, 0))
7347 && ! MEM_VOLATILE_P (inner))
7348 {
7349 int offset = 0;
7350
7351 /* The computations below will be correct if the machine is big
7352 endian in both bits and bytes or little endian in bits and bytes.
7353 If it is mixed, we must adjust. */
7354
7355 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7356 adjust OFFSET to compensate. */
7357 if (BYTES_BIG_ENDIAN
7358 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7359 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7360
7361 /* We can now move to the desired byte. */
7362 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7363 * GET_MODE_SIZE (wanted_inner_mode);
7364 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7365
7366 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7367 && is_mode != wanted_inner_mode)
7368 offset = (GET_MODE_SIZE (is_mode)
7369 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7370
7371 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7372 }
7373
7374 /* If INNER is not memory, get it into the proper mode. If we are changing
7375 its mode, POS must be a constant and smaller than the size of the new
7376 mode. */
7377 else if (!MEM_P (inner))
7378 {
7379 /* On the LHS, don't create paradoxical subregs implicitely truncating
7380 the register unless TRULY_NOOP_TRUNCATION. */
7381 if (in_dest
7382 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7383 GET_MODE_BITSIZE (wanted_inner_mode)))
7384 return NULL_RTX;
7385
7386 if (GET_MODE (inner) != wanted_inner_mode
7387 && (pos_rtx != 0
7388 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7389 return NULL_RTX;
7390
7391 if (orig_pos < 0)
7392 return NULL_RTX;
7393
7394 inner = force_to_mode (inner, wanted_inner_mode,
7395 pos_rtx
7396 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7397 ? ~(unsigned HOST_WIDE_INT) 0
7398 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7399 << orig_pos),
7400 0);
7401 }
7402
7403 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7404 have to zero extend. Otherwise, we can just use a SUBREG. */
7405 if (pos_rtx != 0
7406 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7407 {
7408 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7409
7410 /* If we know that no extraneous bits are set, and that the high
7411 bit is not set, convert extraction to cheaper one - either
7412 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7413 cases. */
7414 if (flag_expensive_optimizations
7415 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7416 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7417 & ~(((unsigned HOST_WIDE_INT)
7418 GET_MODE_MASK (GET_MODE (pos_rtx)))
7419 >> 1))
7420 == 0)))
7421 {
7422 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7423
7424 /* Prefer ZERO_EXTENSION, since it gives more information to
7425 backends. */
7426 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7427 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7428 temp = temp1;
7429 }
7430 pos_rtx = temp;
7431 }
7432 else if (pos_rtx != 0
7433 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7434 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7435
7436 /* Make POS_RTX unless we already have it and it is correct. If we don't
7437 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7438 be a CONST_INT. */
7439 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7440 pos_rtx = orig_pos_rtx;
7441
7442 else if (pos_rtx == 0)
7443 pos_rtx = GEN_INT (pos);
7444
7445 /* Make the required operation. See if we can use existing rtx. */
7446 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7447 extraction_mode, inner, GEN_INT (len), pos_rtx);
7448 if (! in_dest)
7449 new_rtx = gen_lowpart (mode, new_rtx);
7450
7451 return new_rtx;
7452 }
7453 \f
7454 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7455 with any other operations in X. Return X without that shift if so. */
7456
7457 static rtx
7458 extract_left_shift (rtx x, int count)
7459 {
7460 enum rtx_code code = GET_CODE (x);
7461 enum machine_mode mode = GET_MODE (x);
7462 rtx tem;
7463
7464 switch (code)
7465 {
7466 case ASHIFT:
7467 /* This is the shift itself. If it is wide enough, we will return
7468 either the value being shifted if the shift count is equal to
7469 COUNT or a shift for the difference. */
7470 if (CONST_INT_P (XEXP (x, 1))
7471 && INTVAL (XEXP (x, 1)) >= count)
7472 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7473 INTVAL (XEXP (x, 1)) - count);
7474 break;
7475
7476 case NEG: case NOT:
7477 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7478 return simplify_gen_unary (code, mode, tem, mode);
7479
7480 break;
7481
7482 case PLUS: case IOR: case XOR: case AND:
7483 /* If we can safely shift this constant and we find the inner shift,
7484 make a new operation. */
7485 if (CONST_INT_P (XEXP (x, 1))
7486 && (UINTVAL (XEXP (x, 1))
7487 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7488 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7489 return simplify_gen_binary (code, mode, tem,
7490 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7491
7492 break;
7493
7494 default:
7495 break;
7496 }
7497
7498 return 0;
7499 }
7500 \f
7501 /* Look at the expression rooted at X. Look for expressions
7502 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7503 Form these expressions.
7504
7505 Return the new rtx, usually just X.
7506
7507 Also, for machines like the VAX that don't have logical shift insns,
7508 try to convert logical to arithmetic shift operations in cases where
7509 they are equivalent. This undoes the canonicalizations to logical
7510 shifts done elsewhere.
7511
7512 We try, as much as possible, to re-use rtl expressions to save memory.
7513
7514 IN_CODE says what kind of expression we are processing. Normally, it is
7515 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7516 being kludges), it is MEM. When processing the arguments of a comparison
7517 or a COMPARE against zero, it is COMPARE. */
7518
7519 static rtx
7520 make_compound_operation (rtx x, enum rtx_code in_code)
7521 {
7522 enum rtx_code code = GET_CODE (x);
7523 enum machine_mode mode = GET_MODE (x);
7524 int mode_width = GET_MODE_BITSIZE (mode);
7525 rtx rhs, lhs;
7526 enum rtx_code next_code;
7527 int i, j;
7528 rtx new_rtx = 0;
7529 rtx tem;
7530 const char *fmt;
7531
7532 /* Select the code to be used in recursive calls. Once we are inside an
7533 address, we stay there. If we have a comparison, set to COMPARE,
7534 but once inside, go back to our default of SET. */
7535
7536 next_code = (code == MEM ? MEM
7537 : ((code == PLUS || code == MINUS)
7538 && SCALAR_INT_MODE_P (mode)) ? MEM
7539 : ((code == COMPARE || COMPARISON_P (x))
7540 && XEXP (x, 1) == const0_rtx) ? COMPARE
7541 : in_code == COMPARE ? SET : in_code);
7542
7543 /* Process depending on the code of this operation. If NEW is set
7544 nonzero, it will be returned. */
7545
7546 switch (code)
7547 {
7548 case ASHIFT:
7549 /* Convert shifts by constants into multiplications if inside
7550 an address. */
7551 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7552 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7553 && INTVAL (XEXP (x, 1)) >= 0
7554 && SCALAR_INT_MODE_P (mode))
7555 {
7556 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7557 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7558
7559 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7560 if (GET_CODE (new_rtx) == NEG)
7561 {
7562 new_rtx = XEXP (new_rtx, 0);
7563 multval = -multval;
7564 }
7565 multval = trunc_int_for_mode (multval, mode);
7566 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7567 }
7568 break;
7569
7570 case PLUS:
7571 lhs = XEXP (x, 0);
7572 rhs = XEXP (x, 1);
7573 lhs = make_compound_operation (lhs, next_code);
7574 rhs = make_compound_operation (rhs, next_code);
7575 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7576 && SCALAR_INT_MODE_P (mode))
7577 {
7578 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7579 XEXP (lhs, 1));
7580 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7581 }
7582 else if (GET_CODE (lhs) == MULT
7583 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7584 {
7585 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7586 simplify_gen_unary (NEG, mode,
7587 XEXP (lhs, 1),
7588 mode));
7589 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7590 }
7591 else
7592 {
7593 SUBST (XEXP (x, 0), lhs);
7594 SUBST (XEXP (x, 1), rhs);
7595 goto maybe_swap;
7596 }
7597 x = gen_lowpart (mode, new_rtx);
7598 goto maybe_swap;
7599
7600 case MINUS:
7601 lhs = XEXP (x, 0);
7602 rhs = XEXP (x, 1);
7603 lhs = make_compound_operation (lhs, next_code);
7604 rhs = make_compound_operation (rhs, next_code);
7605 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7606 && SCALAR_INT_MODE_P (mode))
7607 {
7608 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7609 XEXP (rhs, 1));
7610 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7611 }
7612 else if (GET_CODE (rhs) == MULT
7613 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7614 {
7615 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7616 simplify_gen_unary (NEG, mode,
7617 XEXP (rhs, 1),
7618 mode));
7619 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7620 }
7621 else
7622 {
7623 SUBST (XEXP (x, 0), lhs);
7624 SUBST (XEXP (x, 1), rhs);
7625 return x;
7626 }
7627 return gen_lowpart (mode, new_rtx);
7628
7629 case AND:
7630 /* If the second operand is not a constant, we can't do anything
7631 with it. */
7632 if (!CONST_INT_P (XEXP (x, 1)))
7633 break;
7634
7635 /* If the constant is a power of two minus one and the first operand
7636 is a logical right shift, make an extraction. */
7637 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7638 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7639 {
7640 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7641 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7642 0, in_code == COMPARE);
7643 }
7644
7645 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7646 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7647 && subreg_lowpart_p (XEXP (x, 0))
7648 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7649 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7650 {
7651 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7652 next_code);
7653 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7654 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7655 0, in_code == COMPARE);
7656 }
7657 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7658 else if ((GET_CODE (XEXP (x, 0)) == XOR
7659 || GET_CODE (XEXP (x, 0)) == IOR)
7660 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7661 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7662 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7663 {
7664 /* Apply the distributive law, and then try to make extractions. */
7665 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7666 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7667 XEXP (x, 1)),
7668 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7669 XEXP (x, 1)));
7670 new_rtx = make_compound_operation (new_rtx, in_code);
7671 }
7672
7673 /* If we are have (and (rotate X C) M) and C is larger than the number
7674 of bits in M, this is an extraction. */
7675
7676 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7677 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7678 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7679 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7680 {
7681 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7682 new_rtx = make_extraction (mode, new_rtx,
7683 (GET_MODE_BITSIZE (mode)
7684 - INTVAL (XEXP (XEXP (x, 0), 1))),
7685 NULL_RTX, i, 1, 0, in_code == COMPARE);
7686 }
7687
7688 /* On machines without logical shifts, if the operand of the AND is
7689 a logical shift and our mask turns off all the propagated sign
7690 bits, we can replace the logical shift with an arithmetic shift. */
7691 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7692 && !have_insn_for (LSHIFTRT, mode)
7693 && have_insn_for (ASHIFTRT, mode)
7694 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7695 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7696 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7697 && mode_width <= HOST_BITS_PER_WIDE_INT)
7698 {
7699 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7700
7701 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7702 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7703 SUBST (XEXP (x, 0),
7704 gen_rtx_ASHIFTRT (mode,
7705 make_compound_operation
7706 (XEXP (XEXP (x, 0), 0), next_code),
7707 XEXP (XEXP (x, 0), 1)));
7708 }
7709
7710 /* If the constant is one less than a power of two, this might be
7711 representable by an extraction even if no shift is present.
7712 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7713 we are in a COMPARE. */
7714 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7715 new_rtx = make_extraction (mode,
7716 make_compound_operation (XEXP (x, 0),
7717 next_code),
7718 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7719
7720 /* If we are in a comparison and this is an AND with a power of two,
7721 convert this into the appropriate bit extract. */
7722 else if (in_code == COMPARE
7723 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7724 new_rtx = make_extraction (mode,
7725 make_compound_operation (XEXP (x, 0),
7726 next_code),
7727 i, NULL_RTX, 1, 1, 0, 1);
7728
7729 break;
7730
7731 case LSHIFTRT:
7732 /* If the sign bit is known to be zero, replace this with an
7733 arithmetic shift. */
7734 if (have_insn_for (ASHIFTRT, mode)
7735 && ! have_insn_for (LSHIFTRT, mode)
7736 && mode_width <= HOST_BITS_PER_WIDE_INT
7737 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7738 {
7739 new_rtx = gen_rtx_ASHIFTRT (mode,
7740 make_compound_operation (XEXP (x, 0),
7741 next_code),
7742 XEXP (x, 1));
7743 break;
7744 }
7745
7746 /* ... fall through ... */
7747
7748 case ASHIFTRT:
7749 lhs = XEXP (x, 0);
7750 rhs = XEXP (x, 1);
7751
7752 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7753 this is a SIGN_EXTRACT. */
7754 if (CONST_INT_P (rhs)
7755 && GET_CODE (lhs) == ASHIFT
7756 && CONST_INT_P (XEXP (lhs, 1))
7757 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7758 && INTVAL (rhs) < mode_width)
7759 {
7760 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7761 new_rtx = make_extraction (mode, new_rtx,
7762 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7763 NULL_RTX, mode_width - INTVAL (rhs),
7764 code == LSHIFTRT, 0, in_code == COMPARE);
7765 break;
7766 }
7767
7768 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7769 If so, try to merge the shifts into a SIGN_EXTEND. We could
7770 also do this for some cases of SIGN_EXTRACT, but it doesn't
7771 seem worth the effort; the case checked for occurs on Alpha. */
7772
7773 if (!OBJECT_P (lhs)
7774 && ! (GET_CODE (lhs) == SUBREG
7775 && (OBJECT_P (SUBREG_REG (lhs))))
7776 && CONST_INT_P (rhs)
7777 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7778 && INTVAL (rhs) < mode_width
7779 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7780 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7781 0, NULL_RTX, mode_width - INTVAL (rhs),
7782 code == LSHIFTRT, 0, in_code == COMPARE);
7783
7784 break;
7785
7786 case SUBREG:
7787 /* Call ourselves recursively on the inner expression. If we are
7788 narrowing the object and it has a different RTL code from
7789 what it originally did, do this SUBREG as a force_to_mode. */
7790 {
7791 rtx inner = SUBREG_REG (x), simplified;
7792
7793 tem = make_compound_operation (inner, in_code);
7794
7795 simplified
7796 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7797 if (simplified)
7798 tem = simplified;
7799
7800 if (GET_CODE (tem) != GET_CODE (inner)
7801 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7802 && subreg_lowpart_p (x))
7803 {
7804 rtx newer
7805 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7806
7807 /* If we have something other than a SUBREG, we might have
7808 done an expansion, so rerun ourselves. */
7809 if (GET_CODE (newer) != SUBREG)
7810 newer = make_compound_operation (newer, in_code);
7811
7812 /* force_to_mode can expand compounds. If it just re-expanded the
7813 compound, use gen_lowpart to convert to the desired mode. */
7814 if (rtx_equal_p (newer, x)
7815 /* Likewise if it re-expanded the compound only partially.
7816 This happens for SUBREG of ZERO_EXTRACT if they extract
7817 the same number of bits. */
7818 || (GET_CODE (newer) == SUBREG
7819 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7820 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7821 && GET_CODE (inner) == AND
7822 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7823 return gen_lowpart (GET_MODE (x), tem);
7824
7825 return newer;
7826 }
7827
7828 if (simplified)
7829 return tem;
7830 }
7831 break;
7832
7833 default:
7834 break;
7835 }
7836
7837 if (new_rtx)
7838 {
7839 x = gen_lowpart (mode, new_rtx);
7840 code = GET_CODE (x);
7841 }
7842
7843 /* Now recursively process each operand of this operation. */
7844 fmt = GET_RTX_FORMAT (code);
7845 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7846 if (fmt[i] == 'e')
7847 {
7848 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7849 SUBST (XEXP (x, i), new_rtx);
7850 }
7851 else if (fmt[i] == 'E')
7852 for (j = 0; j < XVECLEN (x, i); j++)
7853 {
7854 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7855 SUBST (XVECEXP (x, i, j), new_rtx);
7856 }
7857
7858 maybe_swap:
7859 /* If this is a commutative operation, the changes to the operands
7860 may have made it noncanonical. */
7861 if (COMMUTATIVE_ARITH_P (x)
7862 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7863 {
7864 tem = XEXP (x, 0);
7865 SUBST (XEXP (x, 0), XEXP (x, 1));
7866 SUBST (XEXP (x, 1), tem);
7867 }
7868
7869 return x;
7870 }
7871 \f
7872 /* Given M see if it is a value that would select a field of bits
7873 within an item, but not the entire word. Return -1 if not.
7874 Otherwise, return the starting position of the field, where 0 is the
7875 low-order bit.
7876
7877 *PLEN is set to the length of the field. */
7878
7879 static int
7880 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7881 {
7882 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7883 int pos = m ? ctz_hwi (m) : -1;
7884 int len = 0;
7885
7886 if (pos >= 0)
7887 /* Now shift off the low-order zero bits and see if we have a
7888 power of two minus 1. */
7889 len = exact_log2 ((m >> pos) + 1);
7890
7891 if (len <= 0)
7892 pos = -1;
7893
7894 *plen = len;
7895 return pos;
7896 }
7897 \f
7898 /* If X refers to a register that equals REG in value, replace these
7899 references with REG. */
7900 static rtx
7901 canon_reg_for_combine (rtx x, rtx reg)
7902 {
7903 rtx op0, op1, op2;
7904 const char *fmt;
7905 int i;
7906 bool copied;
7907
7908 enum rtx_code code = GET_CODE (x);
7909 switch (GET_RTX_CLASS (code))
7910 {
7911 case RTX_UNARY:
7912 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7913 if (op0 != XEXP (x, 0))
7914 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7915 GET_MODE (reg));
7916 break;
7917
7918 case RTX_BIN_ARITH:
7919 case RTX_COMM_ARITH:
7920 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7921 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7922 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7923 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7924 break;
7925
7926 case RTX_COMPARE:
7927 case RTX_COMM_COMPARE:
7928 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7929 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7930 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7931 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7932 GET_MODE (op0), op0, op1);
7933 break;
7934
7935 case RTX_TERNARY:
7936 case RTX_BITFIELD_OPS:
7937 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7938 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7939 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7940 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7941 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7942 GET_MODE (op0), op0, op1, op2);
7943
7944 case RTX_OBJ:
7945 if (REG_P (x))
7946 {
7947 if (rtx_equal_p (get_last_value (reg), x)
7948 || rtx_equal_p (reg, get_last_value (x)))
7949 return reg;
7950 else
7951 break;
7952 }
7953
7954 /* fall through */
7955
7956 default:
7957 fmt = GET_RTX_FORMAT (code);
7958 copied = false;
7959 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7960 if (fmt[i] == 'e')
7961 {
7962 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7963 if (op != XEXP (x, i))
7964 {
7965 if (!copied)
7966 {
7967 copied = true;
7968 x = copy_rtx (x);
7969 }
7970 XEXP (x, i) = op;
7971 }
7972 }
7973 else if (fmt[i] == 'E')
7974 {
7975 int j;
7976 for (j = 0; j < XVECLEN (x, i); j++)
7977 {
7978 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7979 if (op != XVECEXP (x, i, j))
7980 {
7981 if (!copied)
7982 {
7983 copied = true;
7984 x = copy_rtx (x);
7985 }
7986 XVECEXP (x, i, j) = op;
7987 }
7988 }
7989 }
7990
7991 break;
7992 }
7993
7994 return x;
7995 }
7996
7997 /* Return X converted to MODE. If the value is already truncated to
7998 MODE we can just return a subreg even though in the general case we
7999 would need an explicit truncation. */
8000
8001 static rtx
8002 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
8003 {
8004 if (!CONST_INT_P (x)
8005 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8006 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8007 GET_MODE_BITSIZE (GET_MODE (x)))
8008 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8009 {
8010 /* Bit-cast X into an integer mode. */
8011 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8012 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8013 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8014 x, GET_MODE (x));
8015 }
8016
8017 return gen_lowpart (mode, x);
8018 }
8019
8020 /* See if X can be simplified knowing that we will only refer to it in
8021 MODE and will only refer to those bits that are nonzero in MASK.
8022 If other bits are being computed or if masking operations are done
8023 that select a superset of the bits in MASK, they can sometimes be
8024 ignored.
8025
8026 Return a possibly simplified expression, but always convert X to
8027 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8028
8029 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8030 are all off in X. This is used when X will be complemented, by either
8031 NOT, NEG, or XOR. */
8032
8033 static rtx
8034 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8035 int just_select)
8036 {
8037 enum rtx_code code = GET_CODE (x);
8038 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8039 enum machine_mode op_mode;
8040 unsigned HOST_WIDE_INT fuller_mask, nonzero;
8041 rtx op0, op1, temp;
8042
8043 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8044 code below will do the wrong thing since the mode of such an
8045 expression is VOIDmode.
8046
8047 Also do nothing if X is a CLOBBER; this can happen if X was
8048 the return value from a call to gen_lowpart. */
8049 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8050 return x;
8051
8052 /* We want to perform the operation is its present mode unless we know
8053 that the operation is valid in MODE, in which case we do the operation
8054 in MODE. */
8055 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8056 && have_insn_for (code, mode))
8057 ? mode : GET_MODE (x));
8058
8059 /* It is not valid to do a right-shift in a narrower mode
8060 than the one it came in with. */
8061 if ((code == LSHIFTRT || code == ASHIFTRT)
8062 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
8063 op_mode = GET_MODE (x);
8064
8065 /* Truncate MASK to fit OP_MODE. */
8066 if (op_mode)
8067 mask &= GET_MODE_MASK (op_mode);
8068
8069 /* When we have an arithmetic operation, or a shift whose count we
8070 do not know, we need to assume that all bits up to the highest-order
8071 bit in MASK will be needed. This is how we form such a mask. */
8072 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8073 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8074 else
8075 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8076 - 1);
8077
8078 /* Determine what bits of X are guaranteed to be (non)zero. */
8079 nonzero = nonzero_bits (x, mode);
8080
8081 /* If none of the bits in X are needed, return a zero. */
8082 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8083 x = const0_rtx;
8084
8085 /* If X is a CONST_INT, return a new one. Do this here since the
8086 test below will fail. */
8087 if (CONST_INT_P (x))
8088 {
8089 if (SCALAR_INT_MODE_P (mode))
8090 return gen_int_mode (INTVAL (x) & mask, mode);
8091 else
8092 {
8093 x = GEN_INT (INTVAL (x) & mask);
8094 return gen_lowpart_common (mode, x);
8095 }
8096 }
8097
8098 /* If X is narrower than MODE and we want all the bits in X's mode, just
8099 get X in the proper mode. */
8100 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8101 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8102 return gen_lowpart (mode, x);
8103
8104 /* We can ignore the effect of a SUBREG if it narrows the mode or
8105 if the constant masks to zero all the bits the mode doesn't have. */
8106 if (GET_CODE (x) == SUBREG
8107 && subreg_lowpart_p (x)
8108 && ((GET_MODE_SIZE (GET_MODE (x))
8109 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8110 || (0 == (mask
8111 & GET_MODE_MASK (GET_MODE (x))
8112 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8113 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8114
8115 /* The arithmetic simplifications here only work for scalar integer modes. */
8116 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8117 return gen_lowpart_or_truncate (mode, x);
8118
8119 switch (code)
8120 {
8121 case CLOBBER:
8122 /* If X is a (clobber (const_int)), return it since we know we are
8123 generating something that won't match. */
8124 return x;
8125
8126 case SIGN_EXTEND:
8127 case ZERO_EXTEND:
8128 case ZERO_EXTRACT:
8129 case SIGN_EXTRACT:
8130 x = expand_compound_operation (x);
8131 if (GET_CODE (x) != code)
8132 return force_to_mode (x, mode, mask, next_select);
8133 break;
8134
8135 case TRUNCATE:
8136 /* Similarly for a truncate. */
8137 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8138
8139 case AND:
8140 /* If this is an AND with a constant, convert it into an AND
8141 whose constant is the AND of that constant with MASK. If it
8142 remains an AND of MASK, delete it since it is redundant. */
8143
8144 if (CONST_INT_P (XEXP (x, 1)))
8145 {
8146 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8147 mask & INTVAL (XEXP (x, 1)));
8148
8149 /* If X is still an AND, see if it is an AND with a mask that
8150 is just some low-order bits. If so, and it is MASK, we don't
8151 need it. */
8152
8153 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8154 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8155 == mask))
8156 x = XEXP (x, 0);
8157
8158 /* If it remains an AND, try making another AND with the bits
8159 in the mode mask that aren't in MASK turned on. If the
8160 constant in the AND is wide enough, this might make a
8161 cheaper constant. */
8162
8163 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8164 && GET_MODE_MASK (GET_MODE (x)) != mask
8165 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
8166 {
8167 unsigned HOST_WIDE_INT cval
8168 = UINTVAL (XEXP (x, 1))
8169 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8170 int width = GET_MODE_BITSIZE (GET_MODE (x));
8171 rtx y;
8172
8173 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8174 number, sign extend it. */
8175 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8176 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8177 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8178
8179 y = simplify_gen_binary (AND, GET_MODE (x),
8180 XEXP (x, 0), GEN_INT (cval));
8181 if (rtx_cost (y, SET, optimize_this_for_speed_p)
8182 < rtx_cost (x, SET, optimize_this_for_speed_p))
8183 x = y;
8184 }
8185
8186 break;
8187 }
8188
8189 goto binop;
8190
8191 case PLUS:
8192 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8193 low-order bits (as in an alignment operation) and FOO is already
8194 aligned to that boundary, mask C1 to that boundary as well.
8195 This may eliminate that PLUS and, later, the AND. */
8196
8197 {
8198 unsigned int width = GET_MODE_BITSIZE (mode);
8199 unsigned HOST_WIDE_INT smask = mask;
8200
8201 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8202 number, sign extend it. */
8203
8204 if (width < HOST_BITS_PER_WIDE_INT
8205 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8206 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8207
8208 if (CONST_INT_P (XEXP (x, 1))
8209 && exact_log2 (- smask) >= 0
8210 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8211 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8212 return force_to_mode (plus_constant (XEXP (x, 0),
8213 (INTVAL (XEXP (x, 1)) & smask)),
8214 mode, smask, next_select);
8215 }
8216
8217 /* ... fall through ... */
8218
8219 case MULT:
8220 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8221 most significant bit in MASK since carries from those bits will
8222 affect the bits we are interested in. */
8223 mask = fuller_mask;
8224 goto binop;
8225
8226 case MINUS:
8227 /* If X is (minus C Y) where C's least set bit is larger than any bit
8228 in the mask, then we may replace with (neg Y). */
8229 if (CONST_INT_P (XEXP (x, 0))
8230 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8231 & -INTVAL (XEXP (x, 0))))
8232 > mask))
8233 {
8234 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8235 GET_MODE (x));
8236 return force_to_mode (x, mode, mask, next_select);
8237 }
8238
8239 /* Similarly, if C contains every bit in the fuller_mask, then we may
8240 replace with (not Y). */
8241 if (CONST_INT_P (XEXP (x, 0))
8242 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8243 {
8244 x = simplify_gen_unary (NOT, GET_MODE (x),
8245 XEXP (x, 1), GET_MODE (x));
8246 return force_to_mode (x, mode, mask, next_select);
8247 }
8248
8249 mask = fuller_mask;
8250 goto binop;
8251
8252 case IOR:
8253 case XOR:
8254 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8255 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8256 operation which may be a bitfield extraction. Ensure that the
8257 constant we form is not wider than the mode of X. */
8258
8259 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8260 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8261 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8262 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8263 && CONST_INT_P (XEXP (x, 1))
8264 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8265 + floor_log2 (INTVAL (XEXP (x, 1))))
8266 < GET_MODE_BITSIZE (GET_MODE (x)))
8267 && (UINTVAL (XEXP (x, 1))
8268 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8269 {
8270 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8271 << INTVAL (XEXP (XEXP (x, 0), 1)));
8272 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8273 XEXP (XEXP (x, 0), 0), temp);
8274 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8275 XEXP (XEXP (x, 0), 1));
8276 return force_to_mode (x, mode, mask, next_select);
8277 }
8278
8279 binop:
8280 /* For most binary operations, just propagate into the operation and
8281 change the mode if we have an operation of that mode. */
8282
8283 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8284 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8285
8286 /* If we ended up truncating both operands, truncate the result of the
8287 operation instead. */
8288 if (GET_CODE (op0) == TRUNCATE
8289 && GET_CODE (op1) == TRUNCATE)
8290 {
8291 op0 = XEXP (op0, 0);
8292 op1 = XEXP (op1, 0);
8293 }
8294
8295 op0 = gen_lowpart_or_truncate (op_mode, op0);
8296 op1 = gen_lowpart_or_truncate (op_mode, op1);
8297
8298 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8299 x = simplify_gen_binary (code, op_mode, op0, op1);
8300 break;
8301
8302 case ASHIFT:
8303 /* For left shifts, do the same, but just for the first operand.
8304 However, we cannot do anything with shifts where we cannot
8305 guarantee that the counts are smaller than the size of the mode
8306 because such a count will have a different meaning in a
8307 wider mode. */
8308
8309 if (! (CONST_INT_P (XEXP (x, 1))
8310 && INTVAL (XEXP (x, 1)) >= 0
8311 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
8312 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8313 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8314 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
8315 break;
8316
8317 /* If the shift count is a constant and we can do arithmetic in
8318 the mode of the shift, refine which bits we need. Otherwise, use the
8319 conservative form of the mask. */
8320 if (CONST_INT_P (XEXP (x, 1))
8321 && INTVAL (XEXP (x, 1)) >= 0
8322 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
8323 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8324 mask >>= INTVAL (XEXP (x, 1));
8325 else
8326 mask = fuller_mask;
8327
8328 op0 = gen_lowpart_or_truncate (op_mode,
8329 force_to_mode (XEXP (x, 0), op_mode,
8330 mask, next_select));
8331
8332 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8333 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8334 break;
8335
8336 case LSHIFTRT:
8337 /* Here we can only do something if the shift count is a constant,
8338 this shift constant is valid for the host, and we can do arithmetic
8339 in OP_MODE. */
8340
8341 if (CONST_INT_P (XEXP (x, 1))
8342 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8343 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8344 {
8345 rtx inner = XEXP (x, 0);
8346 unsigned HOST_WIDE_INT inner_mask;
8347
8348 /* Select the mask of the bits we need for the shift operand. */
8349 inner_mask = mask << INTVAL (XEXP (x, 1));
8350
8351 /* We can only change the mode of the shift if we can do arithmetic
8352 in the mode of the shift and INNER_MASK is no wider than the
8353 width of X's mode. */
8354 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8355 op_mode = GET_MODE (x);
8356
8357 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8358
8359 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8360 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8361 }
8362
8363 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8364 shift and AND produces only copies of the sign bit (C2 is one less
8365 than a power of two), we can do this with just a shift. */
8366
8367 if (GET_CODE (x) == LSHIFTRT
8368 && CONST_INT_P (XEXP (x, 1))
8369 /* The shift puts one of the sign bit copies in the least significant
8370 bit. */
8371 && ((INTVAL (XEXP (x, 1))
8372 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8373 >= GET_MODE_BITSIZE (GET_MODE (x)))
8374 && exact_log2 (mask + 1) >= 0
8375 /* Number of bits left after the shift must be more than the mask
8376 needs. */
8377 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8378 <= GET_MODE_BITSIZE (GET_MODE (x)))
8379 /* Must be more sign bit copies than the mask needs. */
8380 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8381 >= exact_log2 (mask + 1)))
8382 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8383 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
8384 - exact_log2 (mask + 1)));
8385
8386 goto shiftrt;
8387
8388 case ASHIFTRT:
8389 /* If we are just looking for the sign bit, we don't need this shift at
8390 all, even if it has a variable count. */
8391 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8392 && (mask == ((unsigned HOST_WIDE_INT) 1
8393 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8394 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8395
8396 /* If this is a shift by a constant, get a mask that contains those bits
8397 that are not copies of the sign bit. We then have two cases: If
8398 MASK only includes those bits, this can be a logical shift, which may
8399 allow simplifications. If MASK is a single-bit field not within
8400 those bits, we are requesting a copy of the sign bit and hence can
8401 shift the sign bit to the appropriate location. */
8402
8403 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8404 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8405 {
8406 int i;
8407
8408 /* If the considered data is wider than HOST_WIDE_INT, we can't
8409 represent a mask for all its bits in a single scalar.
8410 But we only care about the lower bits, so calculate these. */
8411
8412 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8413 {
8414 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8415
8416 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8417 is the number of bits a full-width mask would have set.
8418 We need only shift if these are fewer than nonzero can
8419 hold. If not, we must keep all bits set in nonzero. */
8420
8421 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8422 < HOST_BITS_PER_WIDE_INT)
8423 nonzero >>= INTVAL (XEXP (x, 1))
8424 + HOST_BITS_PER_WIDE_INT
8425 - GET_MODE_BITSIZE (GET_MODE (x)) ;
8426 }
8427 else
8428 {
8429 nonzero = GET_MODE_MASK (GET_MODE (x));
8430 nonzero >>= INTVAL (XEXP (x, 1));
8431 }
8432
8433 if ((mask & ~nonzero) == 0)
8434 {
8435 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8436 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8437 if (GET_CODE (x) != ASHIFTRT)
8438 return force_to_mode (x, mode, mask, next_select);
8439 }
8440
8441 else if ((i = exact_log2 (mask)) >= 0)
8442 {
8443 x = simplify_shift_const
8444 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8445 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
8446
8447 if (GET_CODE (x) != ASHIFTRT)
8448 return force_to_mode (x, mode, mask, next_select);
8449 }
8450 }
8451
8452 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8453 even if the shift count isn't a constant. */
8454 if (mask == 1)
8455 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8456 XEXP (x, 0), XEXP (x, 1));
8457
8458 shiftrt:
8459
8460 /* If this is a zero- or sign-extension operation that just affects bits
8461 we don't care about, remove it. Be sure the call above returned
8462 something that is still a shift. */
8463
8464 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8465 && CONST_INT_P (XEXP (x, 1))
8466 && INTVAL (XEXP (x, 1)) >= 0
8467 && (INTVAL (XEXP (x, 1))
8468 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8469 && GET_CODE (XEXP (x, 0)) == ASHIFT
8470 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8471 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8472 next_select);
8473
8474 break;
8475
8476 case ROTATE:
8477 case ROTATERT:
8478 /* If the shift count is constant and we can do computations
8479 in the mode of X, compute where the bits we care about are.
8480 Otherwise, we can't do anything. Don't change the mode of
8481 the shift or propagate MODE into the shift, though. */
8482 if (CONST_INT_P (XEXP (x, 1))
8483 && INTVAL (XEXP (x, 1)) >= 0)
8484 {
8485 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8486 GET_MODE (x), GEN_INT (mask),
8487 XEXP (x, 1));
8488 if (temp && CONST_INT_P (temp))
8489 SUBST (XEXP (x, 0),
8490 force_to_mode (XEXP (x, 0), GET_MODE (x),
8491 INTVAL (temp), next_select));
8492 }
8493 break;
8494
8495 case NEG:
8496 /* If we just want the low-order bit, the NEG isn't needed since it
8497 won't change the low-order bit. */
8498 if (mask == 1)
8499 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8500
8501 /* We need any bits less significant than the most significant bit in
8502 MASK since carries from those bits will affect the bits we are
8503 interested in. */
8504 mask = fuller_mask;
8505 goto unop;
8506
8507 case NOT:
8508 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8509 same as the XOR case above. Ensure that the constant we form is not
8510 wider than the mode of X. */
8511
8512 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8513 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8514 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8515 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8516 < GET_MODE_BITSIZE (GET_MODE (x)))
8517 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8518 {
8519 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8520 GET_MODE (x));
8521 temp = simplify_gen_binary (XOR, GET_MODE (x),
8522 XEXP (XEXP (x, 0), 0), temp);
8523 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8524 temp, XEXP (XEXP (x, 0), 1));
8525
8526 return force_to_mode (x, mode, mask, next_select);
8527 }
8528
8529 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8530 use the full mask inside the NOT. */
8531 mask = fuller_mask;
8532
8533 unop:
8534 op0 = gen_lowpart_or_truncate (op_mode,
8535 force_to_mode (XEXP (x, 0), mode, mask,
8536 next_select));
8537 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8538 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8539 break;
8540
8541 case NE:
8542 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8543 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8544 which is equal to STORE_FLAG_VALUE. */
8545 if ((mask & ~STORE_FLAG_VALUE) == 0
8546 && XEXP (x, 1) == const0_rtx
8547 && GET_MODE (XEXP (x, 0)) == mode
8548 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8549 && (nonzero_bits (XEXP (x, 0), mode)
8550 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8551 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8552
8553 break;
8554
8555 case IF_THEN_ELSE:
8556 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8557 written in a narrower mode. We play it safe and do not do so. */
8558
8559 SUBST (XEXP (x, 1),
8560 gen_lowpart_or_truncate (GET_MODE (x),
8561 force_to_mode (XEXP (x, 1), mode,
8562 mask, next_select)));
8563 SUBST (XEXP (x, 2),
8564 gen_lowpart_or_truncate (GET_MODE (x),
8565 force_to_mode (XEXP (x, 2), mode,
8566 mask, next_select)));
8567 break;
8568
8569 default:
8570 break;
8571 }
8572
8573 /* Ensure we return a value of the proper mode. */
8574 return gen_lowpart_or_truncate (mode, x);
8575 }
8576 \f
8577 /* Return nonzero if X is an expression that has one of two values depending on
8578 whether some other value is zero or nonzero. In that case, we return the
8579 value that is being tested, *PTRUE is set to the value if the rtx being
8580 returned has a nonzero value, and *PFALSE is set to the other alternative.
8581
8582 If we return zero, we set *PTRUE and *PFALSE to X. */
8583
8584 static rtx
8585 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8586 {
8587 enum machine_mode mode = GET_MODE (x);
8588 enum rtx_code code = GET_CODE (x);
8589 rtx cond0, cond1, true0, true1, false0, false1;
8590 unsigned HOST_WIDE_INT nz;
8591
8592 /* If we are comparing a value against zero, we are done. */
8593 if ((code == NE || code == EQ)
8594 && XEXP (x, 1) == const0_rtx)
8595 {
8596 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8597 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8598 return XEXP (x, 0);
8599 }
8600
8601 /* If this is a unary operation whose operand has one of two values, apply
8602 our opcode to compute those values. */
8603 else if (UNARY_P (x)
8604 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8605 {
8606 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8607 *pfalse = simplify_gen_unary (code, mode, false0,
8608 GET_MODE (XEXP (x, 0)));
8609 return cond0;
8610 }
8611
8612 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8613 make can't possibly match and would suppress other optimizations. */
8614 else if (code == COMPARE)
8615 ;
8616
8617 /* If this is a binary operation, see if either side has only one of two
8618 values. If either one does or if both do and they are conditional on
8619 the same value, compute the new true and false values. */
8620 else if (BINARY_P (x))
8621 {
8622 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8623 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8624
8625 if ((cond0 != 0 || cond1 != 0)
8626 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8627 {
8628 /* If if_then_else_cond returned zero, then true/false are the
8629 same rtl. We must copy one of them to prevent invalid rtl
8630 sharing. */
8631 if (cond0 == 0)
8632 true0 = copy_rtx (true0);
8633 else if (cond1 == 0)
8634 true1 = copy_rtx (true1);
8635
8636 if (COMPARISON_P (x))
8637 {
8638 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8639 true0, true1);
8640 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8641 false0, false1);
8642 }
8643 else
8644 {
8645 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8646 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8647 }
8648
8649 return cond0 ? cond0 : cond1;
8650 }
8651
8652 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8653 operands is zero when the other is nonzero, and vice-versa,
8654 and STORE_FLAG_VALUE is 1 or -1. */
8655
8656 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8657 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8658 || code == UMAX)
8659 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8660 {
8661 rtx op0 = XEXP (XEXP (x, 0), 1);
8662 rtx op1 = XEXP (XEXP (x, 1), 1);
8663
8664 cond0 = XEXP (XEXP (x, 0), 0);
8665 cond1 = XEXP (XEXP (x, 1), 0);
8666
8667 if (COMPARISON_P (cond0)
8668 && COMPARISON_P (cond1)
8669 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8670 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8671 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8672 || ((swap_condition (GET_CODE (cond0))
8673 == reversed_comparison_code (cond1, NULL))
8674 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8675 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8676 && ! side_effects_p (x))
8677 {
8678 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8679 *pfalse = simplify_gen_binary (MULT, mode,
8680 (code == MINUS
8681 ? simplify_gen_unary (NEG, mode,
8682 op1, mode)
8683 : op1),
8684 const_true_rtx);
8685 return cond0;
8686 }
8687 }
8688
8689 /* Similarly for MULT, AND and UMIN, except that for these the result
8690 is always zero. */
8691 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8692 && (code == MULT || code == AND || code == UMIN)
8693 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8694 {
8695 cond0 = XEXP (XEXP (x, 0), 0);
8696 cond1 = XEXP (XEXP (x, 1), 0);
8697
8698 if (COMPARISON_P (cond0)
8699 && COMPARISON_P (cond1)
8700 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8701 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8702 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8703 || ((swap_condition (GET_CODE (cond0))
8704 == reversed_comparison_code (cond1, NULL))
8705 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8706 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8707 && ! side_effects_p (x))
8708 {
8709 *ptrue = *pfalse = const0_rtx;
8710 return cond0;
8711 }
8712 }
8713 }
8714
8715 else if (code == IF_THEN_ELSE)
8716 {
8717 /* If we have IF_THEN_ELSE already, extract the condition and
8718 canonicalize it if it is NE or EQ. */
8719 cond0 = XEXP (x, 0);
8720 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8721 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8722 return XEXP (cond0, 0);
8723 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8724 {
8725 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8726 return XEXP (cond0, 0);
8727 }
8728 else
8729 return cond0;
8730 }
8731
8732 /* If X is a SUBREG, we can narrow both the true and false values
8733 if the inner expression, if there is a condition. */
8734 else if (code == SUBREG
8735 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8736 &true0, &false0)))
8737 {
8738 true0 = simplify_gen_subreg (mode, true0,
8739 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8740 false0 = simplify_gen_subreg (mode, false0,
8741 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8742 if (true0 && false0)
8743 {
8744 *ptrue = true0;
8745 *pfalse = false0;
8746 return cond0;
8747 }
8748 }
8749
8750 /* If X is a constant, this isn't special and will cause confusions
8751 if we treat it as such. Likewise if it is equivalent to a constant. */
8752 else if (CONSTANT_P (x)
8753 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8754 ;
8755
8756 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8757 will be least confusing to the rest of the compiler. */
8758 else if (mode == BImode)
8759 {
8760 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8761 return x;
8762 }
8763
8764 /* If X is known to be either 0 or -1, those are the true and
8765 false values when testing X. */
8766 else if (x == constm1_rtx || x == const0_rtx
8767 || (mode != VOIDmode
8768 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8769 {
8770 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8771 return x;
8772 }
8773
8774 /* Likewise for 0 or a single bit. */
8775 else if (SCALAR_INT_MODE_P (mode)
8776 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8777 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8778 {
8779 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8780 return x;
8781 }
8782
8783 /* Otherwise fail; show no condition with true and false values the same. */
8784 *ptrue = *pfalse = x;
8785 return 0;
8786 }
8787 \f
8788 /* Return the value of expression X given the fact that condition COND
8789 is known to be true when applied to REG as its first operand and VAL
8790 as its second. X is known to not be shared and so can be modified in
8791 place.
8792
8793 We only handle the simplest cases, and specifically those cases that
8794 arise with IF_THEN_ELSE expressions. */
8795
8796 static rtx
8797 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8798 {
8799 enum rtx_code code = GET_CODE (x);
8800 rtx temp;
8801 const char *fmt;
8802 int i, j;
8803
8804 if (side_effects_p (x))
8805 return x;
8806
8807 /* If either operand of the condition is a floating point value,
8808 then we have to avoid collapsing an EQ comparison. */
8809 if (cond == EQ
8810 && rtx_equal_p (x, reg)
8811 && ! FLOAT_MODE_P (GET_MODE (x))
8812 && ! FLOAT_MODE_P (GET_MODE (val)))
8813 return val;
8814
8815 if (cond == UNEQ && rtx_equal_p (x, reg))
8816 return val;
8817
8818 /* If X is (abs REG) and we know something about REG's relationship
8819 with zero, we may be able to simplify this. */
8820
8821 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8822 switch (cond)
8823 {
8824 case GE: case GT: case EQ:
8825 return XEXP (x, 0);
8826 case LT: case LE:
8827 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8828 XEXP (x, 0),
8829 GET_MODE (XEXP (x, 0)));
8830 default:
8831 break;
8832 }
8833
8834 /* The only other cases we handle are MIN, MAX, and comparisons if the
8835 operands are the same as REG and VAL. */
8836
8837 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8838 {
8839 if (rtx_equal_p (XEXP (x, 0), val))
8840 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8841
8842 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8843 {
8844 if (COMPARISON_P (x))
8845 {
8846 if (comparison_dominates_p (cond, code))
8847 return const_true_rtx;
8848
8849 code = reversed_comparison_code (x, NULL);
8850 if (code != UNKNOWN
8851 && comparison_dominates_p (cond, code))
8852 return const0_rtx;
8853 else
8854 return x;
8855 }
8856 else if (code == SMAX || code == SMIN
8857 || code == UMIN || code == UMAX)
8858 {
8859 int unsignedp = (code == UMIN || code == UMAX);
8860
8861 /* Do not reverse the condition when it is NE or EQ.
8862 This is because we cannot conclude anything about
8863 the value of 'SMAX (x, y)' when x is not equal to y,
8864 but we can when x equals y. */
8865 if ((code == SMAX || code == UMAX)
8866 && ! (cond == EQ || cond == NE))
8867 cond = reverse_condition (cond);
8868
8869 switch (cond)
8870 {
8871 case GE: case GT:
8872 return unsignedp ? x : XEXP (x, 1);
8873 case LE: case LT:
8874 return unsignedp ? x : XEXP (x, 0);
8875 case GEU: case GTU:
8876 return unsignedp ? XEXP (x, 1) : x;
8877 case LEU: case LTU:
8878 return unsignedp ? XEXP (x, 0) : x;
8879 default:
8880 break;
8881 }
8882 }
8883 }
8884 }
8885 else if (code == SUBREG)
8886 {
8887 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8888 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8889
8890 if (SUBREG_REG (x) != r)
8891 {
8892 /* We must simplify subreg here, before we lose track of the
8893 original inner_mode. */
8894 new_rtx = simplify_subreg (GET_MODE (x), r,
8895 inner_mode, SUBREG_BYTE (x));
8896 if (new_rtx)
8897 return new_rtx;
8898 else
8899 SUBST (SUBREG_REG (x), r);
8900 }
8901
8902 return x;
8903 }
8904 /* We don't have to handle SIGN_EXTEND here, because even in the
8905 case of replacing something with a modeless CONST_INT, a
8906 CONST_INT is already (supposed to be) a valid sign extension for
8907 its narrower mode, which implies it's already properly
8908 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8909 story is different. */
8910 else if (code == ZERO_EXTEND)
8911 {
8912 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8913 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8914
8915 if (XEXP (x, 0) != r)
8916 {
8917 /* We must simplify the zero_extend here, before we lose
8918 track of the original inner_mode. */
8919 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8920 r, inner_mode);
8921 if (new_rtx)
8922 return new_rtx;
8923 else
8924 SUBST (XEXP (x, 0), r);
8925 }
8926
8927 return x;
8928 }
8929
8930 fmt = GET_RTX_FORMAT (code);
8931 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8932 {
8933 if (fmt[i] == 'e')
8934 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8935 else if (fmt[i] == 'E')
8936 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8937 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8938 cond, reg, val));
8939 }
8940
8941 return x;
8942 }
8943 \f
8944 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8945 assignment as a field assignment. */
8946
8947 static int
8948 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8949 {
8950 if (x == y || rtx_equal_p (x, y))
8951 return 1;
8952
8953 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8954 return 0;
8955
8956 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8957 Note that all SUBREGs of MEM are paradoxical; otherwise they
8958 would have been rewritten. */
8959 if (MEM_P (x) && GET_CODE (y) == SUBREG
8960 && MEM_P (SUBREG_REG (y))
8961 && rtx_equal_p (SUBREG_REG (y),
8962 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8963 return 1;
8964
8965 if (MEM_P (y) && GET_CODE (x) == SUBREG
8966 && MEM_P (SUBREG_REG (x))
8967 && rtx_equal_p (SUBREG_REG (x),
8968 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8969 return 1;
8970
8971 /* We used to see if get_last_value of X and Y were the same but that's
8972 not correct. In one direction, we'll cause the assignment to have
8973 the wrong destination and in the case, we'll import a register into this
8974 insn that might have already have been dead. So fail if none of the
8975 above cases are true. */
8976 return 0;
8977 }
8978 \f
8979 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8980 Return that assignment if so.
8981
8982 We only handle the most common cases. */
8983
8984 static rtx
8985 make_field_assignment (rtx x)
8986 {
8987 rtx dest = SET_DEST (x);
8988 rtx src = SET_SRC (x);
8989 rtx assign;
8990 rtx rhs, lhs;
8991 HOST_WIDE_INT c1;
8992 HOST_WIDE_INT pos;
8993 unsigned HOST_WIDE_INT len;
8994 rtx other;
8995 enum machine_mode mode;
8996
8997 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8998 a clear of a one-bit field. We will have changed it to
8999 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9000 for a SUBREG. */
9001
9002 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9003 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9004 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9005 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9006 {
9007 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9008 1, 1, 1, 0);
9009 if (assign != 0)
9010 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9011 return x;
9012 }
9013
9014 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9015 && subreg_lowpart_p (XEXP (src, 0))
9016 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9017 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9018 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9019 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9020 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9021 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9022 {
9023 assign = make_extraction (VOIDmode, dest, 0,
9024 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9025 1, 1, 1, 0);
9026 if (assign != 0)
9027 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9028 return x;
9029 }
9030
9031 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9032 one-bit field. */
9033 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9034 && XEXP (XEXP (src, 0), 0) == const1_rtx
9035 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9036 {
9037 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9038 1, 1, 1, 0);
9039 if (assign != 0)
9040 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9041 return x;
9042 }
9043
9044 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9045 SRC is an AND with all bits of that field set, then we can discard
9046 the AND. */
9047 if (GET_CODE (dest) == ZERO_EXTRACT
9048 && CONST_INT_P (XEXP (dest, 1))
9049 && GET_CODE (src) == AND
9050 && CONST_INT_P (XEXP (src, 1)))
9051 {
9052 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9053 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9054 unsigned HOST_WIDE_INT ze_mask;
9055
9056 if (width >= HOST_BITS_PER_WIDE_INT)
9057 ze_mask = -1;
9058 else
9059 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9060
9061 /* Complete overlap. We can remove the source AND. */
9062 if ((and_mask & ze_mask) == ze_mask)
9063 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9064
9065 /* Partial overlap. We can reduce the source AND. */
9066 if ((and_mask & ze_mask) != and_mask)
9067 {
9068 mode = GET_MODE (src);
9069 src = gen_rtx_AND (mode, XEXP (src, 0),
9070 gen_int_mode (and_mask & ze_mask, mode));
9071 return gen_rtx_SET (VOIDmode, dest, src);
9072 }
9073 }
9074
9075 /* The other case we handle is assignments into a constant-position
9076 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9077 a mask that has all one bits except for a group of zero bits and
9078 OTHER is known to have zeros where C1 has ones, this is such an
9079 assignment. Compute the position and length from C1. Shift OTHER
9080 to the appropriate position, force it to the required mode, and
9081 make the extraction. Check for the AND in both operands. */
9082
9083 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9084 return x;
9085
9086 rhs = expand_compound_operation (XEXP (src, 0));
9087 lhs = expand_compound_operation (XEXP (src, 1));
9088
9089 if (GET_CODE (rhs) == AND
9090 && CONST_INT_P (XEXP (rhs, 1))
9091 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9092 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9093 else if (GET_CODE (lhs) == AND
9094 && CONST_INT_P (XEXP (lhs, 1))
9095 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9096 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9097 else
9098 return x;
9099
9100 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9101 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
9102 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9103 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9104 return x;
9105
9106 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9107 if (assign == 0)
9108 return x;
9109
9110 /* The mode to use for the source is the mode of the assignment, or of
9111 what is inside a possible STRICT_LOW_PART. */
9112 mode = (GET_CODE (assign) == STRICT_LOW_PART
9113 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9114
9115 /* Shift OTHER right POS places and make it the source, restricting it
9116 to the proper length and mode. */
9117
9118 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9119 GET_MODE (src),
9120 other, pos),
9121 dest);
9122 src = force_to_mode (src, mode,
9123 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
9124 ? ~(unsigned HOST_WIDE_INT) 0
9125 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9126 0);
9127
9128 /* If SRC is masked by an AND that does not make a difference in
9129 the value being stored, strip it. */
9130 if (GET_CODE (assign) == ZERO_EXTRACT
9131 && CONST_INT_P (XEXP (assign, 1))
9132 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9133 && GET_CODE (src) == AND
9134 && CONST_INT_P (XEXP (src, 1))
9135 && UINTVAL (XEXP (src, 1))
9136 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9137 src = XEXP (src, 0);
9138
9139 return gen_rtx_SET (VOIDmode, assign, src);
9140 }
9141 \f
9142 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9143 if so. */
9144
9145 static rtx
9146 apply_distributive_law (rtx x)
9147 {
9148 enum rtx_code code = GET_CODE (x);
9149 enum rtx_code inner_code;
9150 rtx lhs, rhs, other;
9151 rtx tem;
9152
9153 /* Distributivity is not true for floating point as it can change the
9154 value. So we don't do it unless -funsafe-math-optimizations. */
9155 if (FLOAT_MODE_P (GET_MODE (x))
9156 && ! flag_unsafe_math_optimizations)
9157 return x;
9158
9159 /* The outer operation can only be one of the following: */
9160 if (code != IOR && code != AND && code != XOR
9161 && code != PLUS && code != MINUS)
9162 return x;
9163
9164 lhs = XEXP (x, 0);
9165 rhs = XEXP (x, 1);
9166
9167 /* If either operand is a primitive we can't do anything, so get out
9168 fast. */
9169 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9170 return x;
9171
9172 lhs = expand_compound_operation (lhs);
9173 rhs = expand_compound_operation (rhs);
9174 inner_code = GET_CODE (lhs);
9175 if (inner_code != GET_CODE (rhs))
9176 return x;
9177
9178 /* See if the inner and outer operations distribute. */
9179 switch (inner_code)
9180 {
9181 case LSHIFTRT:
9182 case ASHIFTRT:
9183 case AND:
9184 case IOR:
9185 /* These all distribute except over PLUS. */
9186 if (code == PLUS || code == MINUS)
9187 return x;
9188 break;
9189
9190 case MULT:
9191 if (code != PLUS && code != MINUS)
9192 return x;
9193 break;
9194
9195 case ASHIFT:
9196 /* This is also a multiply, so it distributes over everything. */
9197 break;
9198
9199 case SUBREG:
9200 /* Non-paradoxical SUBREGs distributes over all operations,
9201 provided the inner modes and byte offsets are the same, this
9202 is an extraction of a low-order part, we don't convert an fp
9203 operation to int or vice versa, this is not a vector mode,
9204 and we would not be converting a single-word operation into a
9205 multi-word operation. The latter test is not required, but
9206 it prevents generating unneeded multi-word operations. Some
9207 of the previous tests are redundant given the latter test,
9208 but are retained because they are required for correctness.
9209
9210 We produce the result slightly differently in this case. */
9211
9212 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9213 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9214 || ! subreg_lowpart_p (lhs)
9215 || (GET_MODE_CLASS (GET_MODE (lhs))
9216 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9217 || (GET_MODE_SIZE (GET_MODE (lhs))
9218 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
9219 || VECTOR_MODE_P (GET_MODE (lhs))
9220 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9221 /* Result might need to be truncated. Don't change mode if
9222 explicit truncation is needed. */
9223 || !TRULY_NOOP_TRUNCATION
9224 (GET_MODE_BITSIZE (GET_MODE (x)),
9225 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
9226 return x;
9227
9228 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9229 SUBREG_REG (lhs), SUBREG_REG (rhs));
9230 return gen_lowpart (GET_MODE (x), tem);
9231
9232 default:
9233 return x;
9234 }
9235
9236 /* Set LHS and RHS to the inner operands (A and B in the example
9237 above) and set OTHER to the common operand (C in the example).
9238 There is only one way to do this unless the inner operation is
9239 commutative. */
9240 if (COMMUTATIVE_ARITH_P (lhs)
9241 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9242 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9243 else if (COMMUTATIVE_ARITH_P (lhs)
9244 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9245 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9246 else if (COMMUTATIVE_ARITH_P (lhs)
9247 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9248 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9249 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9250 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9251 else
9252 return x;
9253
9254 /* Form the new inner operation, seeing if it simplifies first. */
9255 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9256
9257 /* There is one exception to the general way of distributing:
9258 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9259 if (code == XOR && inner_code == IOR)
9260 {
9261 inner_code = AND;
9262 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9263 }
9264
9265 /* We may be able to continuing distributing the result, so call
9266 ourselves recursively on the inner operation before forming the
9267 outer operation, which we return. */
9268 return simplify_gen_binary (inner_code, GET_MODE (x),
9269 apply_distributive_law (tem), other);
9270 }
9271
9272 /* See if X is of the form (* (+ A B) C), and if so convert to
9273 (+ (* A C) (* B C)) and try to simplify.
9274
9275 Most of the time, this results in no change. However, if some of
9276 the operands are the same or inverses of each other, simplifications
9277 will result.
9278
9279 For example, (and (ior A B) (not B)) can occur as the result of
9280 expanding a bit field assignment. When we apply the distributive
9281 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9282 which then simplifies to (and (A (not B))).
9283
9284 Note that no checks happen on the validity of applying the inverse
9285 distributive law. This is pointless since we can do it in the
9286 few places where this routine is called.
9287
9288 N is the index of the term that is decomposed (the arithmetic operation,
9289 i.e. (+ A B) in the first example above). !N is the index of the term that
9290 is distributed, i.e. of C in the first example above. */
9291 static rtx
9292 distribute_and_simplify_rtx (rtx x, int n)
9293 {
9294 enum machine_mode mode;
9295 enum rtx_code outer_code, inner_code;
9296 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9297
9298 /* Distributivity is not true for floating point as it can change the
9299 value. So we don't do it unless -funsafe-math-optimizations. */
9300 if (FLOAT_MODE_P (GET_MODE (x))
9301 && ! flag_unsafe_math_optimizations)
9302 return NULL_RTX;
9303
9304 decomposed = XEXP (x, n);
9305 if (!ARITHMETIC_P (decomposed))
9306 return NULL_RTX;
9307
9308 mode = GET_MODE (x);
9309 outer_code = GET_CODE (x);
9310 distributed = XEXP (x, !n);
9311
9312 inner_code = GET_CODE (decomposed);
9313 inner_op0 = XEXP (decomposed, 0);
9314 inner_op1 = XEXP (decomposed, 1);
9315
9316 /* Special case (and (xor B C) (not A)), which is equivalent to
9317 (xor (ior A B) (ior A C)) */
9318 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9319 {
9320 distributed = XEXP (distributed, 0);
9321 outer_code = IOR;
9322 }
9323
9324 if (n == 0)
9325 {
9326 /* Distribute the second term. */
9327 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9328 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9329 }
9330 else
9331 {
9332 /* Distribute the first term. */
9333 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9334 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9335 }
9336
9337 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9338 new_op0, new_op1));
9339 if (GET_CODE (tmp) != outer_code
9340 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
9341 < rtx_cost (x, SET, optimize_this_for_speed_p))
9342 return tmp;
9343
9344 return NULL_RTX;
9345 }
9346 \f
9347 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9348 in MODE. Return an equivalent form, if different from (and VAROP
9349 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9350
9351 static rtx
9352 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9353 unsigned HOST_WIDE_INT constop)
9354 {
9355 unsigned HOST_WIDE_INT nonzero;
9356 unsigned HOST_WIDE_INT orig_constop;
9357 rtx orig_varop;
9358 int i;
9359
9360 orig_varop = varop;
9361 orig_constop = constop;
9362 if (GET_CODE (varop) == CLOBBER)
9363 return NULL_RTX;
9364
9365 /* Simplify VAROP knowing that we will be only looking at some of the
9366 bits in it.
9367
9368 Note by passing in CONSTOP, we guarantee that the bits not set in
9369 CONSTOP are not significant and will never be examined. We must
9370 ensure that is the case by explicitly masking out those bits
9371 before returning. */
9372 varop = force_to_mode (varop, mode, constop, 0);
9373
9374 /* If VAROP is a CLOBBER, we will fail so return it. */
9375 if (GET_CODE (varop) == CLOBBER)
9376 return varop;
9377
9378 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9379 to VAROP and return the new constant. */
9380 if (CONST_INT_P (varop))
9381 return gen_int_mode (INTVAL (varop) & constop, mode);
9382
9383 /* See what bits may be nonzero in VAROP. Unlike the general case of
9384 a call to nonzero_bits, here we don't care about bits outside
9385 MODE. */
9386
9387 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9388
9389 /* Turn off all bits in the constant that are known to already be zero.
9390 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9391 which is tested below. */
9392
9393 constop &= nonzero;
9394
9395 /* If we don't have any bits left, return zero. */
9396 if (constop == 0)
9397 return const0_rtx;
9398
9399 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9400 a power of two, we can replace this with an ASHIFT. */
9401 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9402 && (i = exact_log2 (constop)) >= 0)
9403 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9404
9405 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9406 or XOR, then try to apply the distributive law. This may eliminate
9407 operations if either branch can be simplified because of the AND.
9408 It may also make some cases more complex, but those cases probably
9409 won't match a pattern either with or without this. */
9410
9411 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9412 return
9413 gen_lowpart
9414 (mode,
9415 apply_distributive_law
9416 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9417 simplify_and_const_int (NULL_RTX,
9418 GET_MODE (varop),
9419 XEXP (varop, 0),
9420 constop),
9421 simplify_and_const_int (NULL_RTX,
9422 GET_MODE (varop),
9423 XEXP (varop, 1),
9424 constop))));
9425
9426 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9427 the AND and see if one of the operands simplifies to zero. If so, we
9428 may eliminate it. */
9429
9430 if (GET_CODE (varop) == PLUS
9431 && exact_log2 (constop + 1) >= 0)
9432 {
9433 rtx o0, o1;
9434
9435 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9436 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9437 if (o0 == const0_rtx)
9438 return o1;
9439 if (o1 == const0_rtx)
9440 return o0;
9441 }
9442
9443 /* Make a SUBREG if necessary. If we can't make it, fail. */
9444 varop = gen_lowpart (mode, varop);
9445 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9446 return NULL_RTX;
9447
9448 /* If we are only masking insignificant bits, return VAROP. */
9449 if (constop == nonzero)
9450 return varop;
9451
9452 if (varop == orig_varop && constop == orig_constop)
9453 return NULL_RTX;
9454
9455 /* Otherwise, return an AND. */
9456 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9457 }
9458
9459
9460 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9461 in MODE.
9462
9463 Return an equivalent form, if different from X. Otherwise, return X. If
9464 X is zero, we are to always construct the equivalent form. */
9465
9466 static rtx
9467 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9468 unsigned HOST_WIDE_INT constop)
9469 {
9470 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9471 if (tem)
9472 return tem;
9473
9474 if (!x)
9475 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9476 gen_int_mode (constop, mode));
9477 if (GET_MODE (x) != mode)
9478 x = gen_lowpart (mode, x);
9479 return x;
9480 }
9481 \f
9482 /* Given a REG, X, compute which bits in X can be nonzero.
9483 We don't care about bits outside of those defined in MODE.
9484
9485 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9486 a shift, AND, or zero_extract, we can do better. */
9487
9488 static rtx
9489 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9490 const_rtx known_x ATTRIBUTE_UNUSED,
9491 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9492 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9493 unsigned HOST_WIDE_INT *nonzero)
9494 {
9495 rtx tem;
9496 reg_stat_type *rsp;
9497
9498 /* If X is a register whose nonzero bits value is current, use it.
9499 Otherwise, if X is a register whose value we can find, use that
9500 value. Otherwise, use the previously-computed global nonzero bits
9501 for this register. */
9502
9503 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9504 if (rsp->last_set_value != 0
9505 && (rsp->last_set_mode == mode
9506 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9507 && GET_MODE_CLASS (mode) == MODE_INT))
9508 && ((rsp->last_set_label >= label_tick_ebb_start
9509 && rsp->last_set_label < label_tick)
9510 || (rsp->last_set_label == label_tick
9511 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9512 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9513 && REG_N_SETS (REGNO (x)) == 1
9514 && !REGNO_REG_SET_P
9515 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9516 {
9517 *nonzero &= rsp->last_set_nonzero_bits;
9518 return NULL;
9519 }
9520
9521 tem = get_last_value (x);
9522
9523 if (tem)
9524 {
9525 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9526 /* If X is narrower than MODE and TEM is a non-negative
9527 constant that would appear negative in the mode of X,
9528 sign-extend it for use in reg_nonzero_bits because some
9529 machines (maybe most) will actually do the sign-extension
9530 and this is the conservative approach.
9531
9532 ??? For 2.5, try to tighten up the MD files in this regard
9533 instead of this kludge. */
9534
9535 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9536 && CONST_INT_P (tem)
9537 && INTVAL (tem) > 0
9538 && 0 != (UINTVAL (tem)
9539 & ((unsigned HOST_WIDE_INT) 1
9540 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9541 tem = GEN_INT (UINTVAL (tem)
9542 | ((unsigned HOST_WIDE_INT) (-1)
9543 << GET_MODE_BITSIZE (GET_MODE (x))));
9544 #endif
9545 return tem;
9546 }
9547 else if (nonzero_sign_valid && rsp->nonzero_bits)
9548 {
9549 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9550
9551 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9552 /* We don't know anything about the upper bits. */
9553 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9554 *nonzero &= mask;
9555 }
9556
9557 return NULL;
9558 }
9559
9560 /* Return the number of bits at the high-order end of X that are known to
9561 be equal to the sign bit. X will be used in mode MODE; if MODE is
9562 VOIDmode, X will be used in its own mode. The returned value will always
9563 be between 1 and the number of bits in MODE. */
9564
9565 static rtx
9566 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9567 const_rtx known_x ATTRIBUTE_UNUSED,
9568 enum machine_mode known_mode
9569 ATTRIBUTE_UNUSED,
9570 unsigned int known_ret ATTRIBUTE_UNUSED,
9571 unsigned int *result)
9572 {
9573 rtx tem;
9574 reg_stat_type *rsp;
9575
9576 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9577 if (rsp->last_set_value != 0
9578 && rsp->last_set_mode == mode
9579 && ((rsp->last_set_label >= label_tick_ebb_start
9580 && rsp->last_set_label < label_tick)
9581 || (rsp->last_set_label == label_tick
9582 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9583 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9584 && REG_N_SETS (REGNO (x)) == 1
9585 && !REGNO_REG_SET_P
9586 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9587 {
9588 *result = rsp->last_set_sign_bit_copies;
9589 return NULL;
9590 }
9591
9592 tem = get_last_value (x);
9593 if (tem != 0)
9594 return tem;
9595
9596 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9597 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9598 *result = rsp->sign_bit_copies;
9599
9600 return NULL;
9601 }
9602 \f
9603 /* Return the number of "extended" bits there are in X, when interpreted
9604 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9605 unsigned quantities, this is the number of high-order zero bits.
9606 For signed quantities, this is the number of copies of the sign bit
9607 minus 1. In both case, this function returns the number of "spare"
9608 bits. For example, if two quantities for which this function returns
9609 at least 1 are added, the addition is known not to overflow.
9610
9611 This function will always return 0 unless called during combine, which
9612 implies that it must be called from a define_split. */
9613
9614 unsigned int
9615 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9616 {
9617 if (nonzero_sign_valid == 0)
9618 return 0;
9619
9620 return (unsignedp
9621 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9622 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9623 - floor_log2 (nonzero_bits (x, mode)))
9624 : 0)
9625 : num_sign_bit_copies (x, mode) - 1);
9626 }
9627 \f
9628 /* This function is called from `simplify_shift_const' to merge two
9629 outer operations. Specifically, we have already found that we need
9630 to perform operation *POP0 with constant *PCONST0 at the outermost
9631 position. We would now like to also perform OP1 with constant CONST1
9632 (with *POP0 being done last).
9633
9634 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9635 the resulting operation. *PCOMP_P is set to 1 if we would need to
9636 complement the innermost operand, otherwise it is unchanged.
9637
9638 MODE is the mode in which the operation will be done. No bits outside
9639 the width of this mode matter. It is assumed that the width of this mode
9640 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9641
9642 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9643 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9644 result is simply *PCONST0.
9645
9646 If the resulting operation cannot be expressed as one operation, we
9647 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9648
9649 static int
9650 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9651 {
9652 enum rtx_code op0 = *pop0;
9653 HOST_WIDE_INT const0 = *pconst0;
9654
9655 const0 &= GET_MODE_MASK (mode);
9656 const1 &= GET_MODE_MASK (mode);
9657
9658 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9659 if (op0 == AND)
9660 const1 &= const0;
9661
9662 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9663 if OP0 is SET. */
9664
9665 if (op1 == UNKNOWN || op0 == SET)
9666 return 1;
9667
9668 else if (op0 == UNKNOWN)
9669 op0 = op1, const0 = const1;
9670
9671 else if (op0 == op1)
9672 {
9673 switch (op0)
9674 {
9675 case AND:
9676 const0 &= const1;
9677 break;
9678 case IOR:
9679 const0 |= const1;
9680 break;
9681 case XOR:
9682 const0 ^= const1;
9683 break;
9684 case PLUS:
9685 const0 += const1;
9686 break;
9687 case NEG:
9688 op0 = UNKNOWN;
9689 break;
9690 default:
9691 break;
9692 }
9693 }
9694
9695 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9696 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9697 return 0;
9698
9699 /* If the two constants aren't the same, we can't do anything. The
9700 remaining six cases can all be done. */
9701 else if (const0 != const1)
9702 return 0;
9703
9704 else
9705 switch (op0)
9706 {
9707 case IOR:
9708 if (op1 == AND)
9709 /* (a & b) | b == b */
9710 op0 = SET;
9711 else /* op1 == XOR */
9712 /* (a ^ b) | b == a | b */
9713 {;}
9714 break;
9715
9716 case XOR:
9717 if (op1 == AND)
9718 /* (a & b) ^ b == (~a) & b */
9719 op0 = AND, *pcomp_p = 1;
9720 else /* op1 == IOR */
9721 /* (a | b) ^ b == a & ~b */
9722 op0 = AND, const0 = ~const0;
9723 break;
9724
9725 case AND:
9726 if (op1 == IOR)
9727 /* (a | b) & b == b */
9728 op0 = SET;
9729 else /* op1 == XOR */
9730 /* (a ^ b) & b) == (~a) & b */
9731 *pcomp_p = 1;
9732 break;
9733 default:
9734 break;
9735 }
9736
9737 /* Check for NO-OP cases. */
9738 const0 &= GET_MODE_MASK (mode);
9739 if (const0 == 0
9740 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9741 op0 = UNKNOWN;
9742 else if (const0 == 0 && op0 == AND)
9743 op0 = SET;
9744 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9745 && op0 == AND)
9746 op0 = UNKNOWN;
9747
9748 *pop0 = op0;
9749
9750 /* ??? Slightly redundant with the above mask, but not entirely.
9751 Moving this above means we'd have to sign-extend the mode mask
9752 for the final test. */
9753 if (op0 != UNKNOWN && op0 != NEG)
9754 *pconst0 = trunc_int_for_mode (const0, mode);
9755
9756 return 1;
9757 }
9758 \f
9759 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9760 the shift in. The original shift operation CODE is performed on OP in
9761 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9762 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9763 result of the shift is subject to operation OUTER_CODE with operand
9764 OUTER_CONST. */
9765
9766 static enum machine_mode
9767 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9768 enum machine_mode orig_mode, enum machine_mode mode,
9769 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9770 {
9771 if (orig_mode == mode)
9772 return mode;
9773 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9774
9775 /* In general we can't perform in wider mode for right shift and rotate. */
9776 switch (code)
9777 {
9778 case ASHIFTRT:
9779 /* We can still widen if the bits brought in from the left are identical
9780 to the sign bit of ORIG_MODE. */
9781 if (num_sign_bit_copies (op, mode)
9782 > (unsigned) (GET_MODE_BITSIZE (mode)
9783 - GET_MODE_BITSIZE (orig_mode)))
9784 return mode;
9785 return orig_mode;
9786
9787 case LSHIFTRT:
9788 /* Similarly here but with zero bits. */
9789 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9790 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9791 return mode;
9792
9793 /* We can also widen if the bits brought in will be masked off. This
9794 operation is performed in ORIG_MODE. */
9795 if (outer_code == AND)
9796 {
9797 int care_bits = low_bitmask_len (orig_mode, outer_const);
9798
9799 if (care_bits >= 0
9800 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9801 return mode;
9802 }
9803 /* fall through */
9804
9805 case ROTATE:
9806 return orig_mode;
9807
9808 case ROTATERT:
9809 gcc_unreachable ();
9810
9811 default:
9812 return mode;
9813 }
9814 }
9815
9816 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9817 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9818 simplify it. Otherwise, return a simplified value.
9819
9820 The shift is normally computed in the widest mode we find in VAROP, as
9821 long as it isn't a different number of words than RESULT_MODE. Exceptions
9822 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9823
9824 static rtx
9825 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9826 rtx varop, int orig_count)
9827 {
9828 enum rtx_code orig_code = code;
9829 rtx orig_varop = varop;
9830 int count;
9831 enum machine_mode mode = result_mode;
9832 enum machine_mode shift_mode, tmode;
9833 unsigned int mode_words
9834 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9835 /* We form (outer_op (code varop count) (outer_const)). */
9836 enum rtx_code outer_op = UNKNOWN;
9837 HOST_WIDE_INT outer_const = 0;
9838 int complement_p = 0;
9839 rtx new_rtx, x;
9840
9841 /* Make sure and truncate the "natural" shift on the way in. We don't
9842 want to do this inside the loop as it makes it more difficult to
9843 combine shifts. */
9844 if (SHIFT_COUNT_TRUNCATED)
9845 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9846
9847 /* If we were given an invalid count, don't do anything except exactly
9848 what was requested. */
9849
9850 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9851 return NULL_RTX;
9852
9853 count = orig_count;
9854
9855 /* Unless one of the branches of the `if' in this loop does a `continue',
9856 we will `break' the loop after the `if'. */
9857
9858 while (count != 0)
9859 {
9860 /* If we have an operand of (clobber (const_int 0)), fail. */
9861 if (GET_CODE (varop) == CLOBBER)
9862 return NULL_RTX;
9863
9864 /* Convert ROTATERT to ROTATE. */
9865 if (code == ROTATERT)
9866 {
9867 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9868 code = ROTATE;
9869 if (VECTOR_MODE_P (result_mode))
9870 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9871 else
9872 count = bitsize - count;
9873 }
9874
9875 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9876 mode, outer_op, outer_const);
9877
9878 /* Handle cases where the count is greater than the size of the mode
9879 minus 1. For ASHIFT, use the size minus one as the count (this can
9880 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9881 take the count modulo the size. For other shifts, the result is
9882 zero.
9883
9884 Since these shifts are being produced by the compiler by combining
9885 multiple operations, each of which are defined, we know what the
9886 result is supposed to be. */
9887
9888 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9889 {
9890 if (code == ASHIFTRT)
9891 count = GET_MODE_BITSIZE (shift_mode) - 1;
9892 else if (code == ROTATE || code == ROTATERT)
9893 count %= GET_MODE_BITSIZE (shift_mode);
9894 else
9895 {
9896 /* We can't simply return zero because there may be an
9897 outer op. */
9898 varop = const0_rtx;
9899 count = 0;
9900 break;
9901 }
9902 }
9903
9904 /* If we discovered we had to complement VAROP, leave. Making a NOT
9905 here would cause an infinite loop. */
9906 if (complement_p)
9907 break;
9908
9909 /* An arithmetic right shift of a quantity known to be -1 or 0
9910 is a no-op. */
9911 if (code == ASHIFTRT
9912 && (num_sign_bit_copies (varop, shift_mode)
9913 == GET_MODE_BITSIZE (shift_mode)))
9914 {
9915 count = 0;
9916 break;
9917 }
9918
9919 /* If we are doing an arithmetic right shift and discarding all but
9920 the sign bit copies, this is equivalent to doing a shift by the
9921 bitsize minus one. Convert it into that shift because it will often
9922 allow other simplifications. */
9923
9924 if (code == ASHIFTRT
9925 && (count + num_sign_bit_copies (varop, shift_mode)
9926 >= GET_MODE_BITSIZE (shift_mode)))
9927 count = GET_MODE_BITSIZE (shift_mode) - 1;
9928
9929 /* We simplify the tests below and elsewhere by converting
9930 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9931 `make_compound_operation' will convert it to an ASHIFTRT for
9932 those machines (such as VAX) that don't have an LSHIFTRT. */
9933 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9934 && code == ASHIFTRT
9935 && ((nonzero_bits (varop, shift_mode)
9936 & ((unsigned HOST_WIDE_INT) 1
9937 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0))
9938 code = LSHIFTRT;
9939
9940 if (((code == LSHIFTRT
9941 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9942 && !(nonzero_bits (varop, shift_mode) >> count))
9943 || (code == ASHIFT
9944 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9945 && !((nonzero_bits (varop, shift_mode) << count)
9946 & GET_MODE_MASK (shift_mode))))
9947 && !side_effects_p (varop))
9948 varop = const0_rtx;
9949
9950 switch (GET_CODE (varop))
9951 {
9952 case SIGN_EXTEND:
9953 case ZERO_EXTEND:
9954 case SIGN_EXTRACT:
9955 case ZERO_EXTRACT:
9956 new_rtx = expand_compound_operation (varop);
9957 if (new_rtx != varop)
9958 {
9959 varop = new_rtx;
9960 continue;
9961 }
9962 break;
9963
9964 case MEM:
9965 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9966 minus the width of a smaller mode, we can do this with a
9967 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9968 if ((code == ASHIFTRT || code == LSHIFTRT)
9969 && ! mode_dependent_address_p (XEXP (varop, 0))
9970 && ! MEM_VOLATILE_P (varop)
9971 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9972 MODE_INT, 1)) != BLKmode)
9973 {
9974 new_rtx = adjust_address_nv (varop, tmode,
9975 BYTES_BIG_ENDIAN ? 0
9976 : count / BITS_PER_UNIT);
9977
9978 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9979 : ZERO_EXTEND, mode, new_rtx);
9980 count = 0;
9981 continue;
9982 }
9983 break;
9984
9985 case SUBREG:
9986 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9987 the same number of words as what we've seen so far. Then store
9988 the widest mode in MODE. */
9989 if (subreg_lowpart_p (varop)
9990 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9991 > GET_MODE_SIZE (GET_MODE (varop)))
9992 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9993 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9994 == mode_words
9995 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9996 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9997 {
9998 varop = SUBREG_REG (varop);
9999 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10000 mode = GET_MODE (varop);
10001 continue;
10002 }
10003 break;
10004
10005 case MULT:
10006 /* Some machines use MULT instead of ASHIFT because MULT
10007 is cheaper. But it is still better on those machines to
10008 merge two shifts into one. */
10009 if (CONST_INT_P (XEXP (varop, 1))
10010 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10011 {
10012 varop
10013 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10014 XEXP (varop, 0),
10015 GEN_INT (exact_log2 (
10016 UINTVAL (XEXP (varop, 1)))));
10017 continue;
10018 }
10019 break;
10020
10021 case UDIV:
10022 /* Similar, for when divides are cheaper. */
10023 if (CONST_INT_P (XEXP (varop, 1))
10024 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10025 {
10026 varop
10027 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10028 XEXP (varop, 0),
10029 GEN_INT (exact_log2 (
10030 UINTVAL (XEXP (varop, 1)))));
10031 continue;
10032 }
10033 break;
10034
10035 case ASHIFTRT:
10036 /* If we are extracting just the sign bit of an arithmetic
10037 right shift, that shift is not needed. However, the sign
10038 bit of a wider mode may be different from what would be
10039 interpreted as the sign bit in a narrower mode, so, if
10040 the result is narrower, don't discard the shift. */
10041 if (code == LSHIFTRT
10042 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10043 && (GET_MODE_BITSIZE (result_mode)
10044 >= GET_MODE_BITSIZE (GET_MODE (varop))))
10045 {
10046 varop = XEXP (varop, 0);
10047 continue;
10048 }
10049
10050 /* ... fall through ... */
10051
10052 case LSHIFTRT:
10053 case ASHIFT:
10054 case ROTATE:
10055 /* Here we have two nested shifts. The result is usually the
10056 AND of a new shift with a mask. We compute the result below. */
10057 if (CONST_INT_P (XEXP (varop, 1))
10058 && INTVAL (XEXP (varop, 1)) >= 0
10059 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
10060 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10061 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10062 && !VECTOR_MODE_P (result_mode))
10063 {
10064 enum rtx_code first_code = GET_CODE (varop);
10065 unsigned int first_count = INTVAL (XEXP (varop, 1));
10066 unsigned HOST_WIDE_INT mask;
10067 rtx mask_rtx;
10068
10069 /* We have one common special case. We can't do any merging if
10070 the inner code is an ASHIFTRT of a smaller mode. However, if
10071 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10072 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10073 we can convert it to
10074 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
10075 This simplifies certain SIGN_EXTEND operations. */
10076 if (code == ASHIFT && first_code == ASHIFTRT
10077 && count == (GET_MODE_BITSIZE (result_mode)
10078 - GET_MODE_BITSIZE (GET_MODE (varop))))
10079 {
10080 /* C3 has the low-order C1 bits zero. */
10081
10082 mask = GET_MODE_MASK (mode)
10083 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10084
10085 varop = simplify_and_const_int (NULL_RTX, result_mode,
10086 XEXP (varop, 0), mask);
10087 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10088 varop, count);
10089 count = first_count;
10090 code = ASHIFTRT;
10091 continue;
10092 }
10093
10094 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10095 than C1 high-order bits equal to the sign bit, we can convert
10096 this to either an ASHIFT or an ASHIFTRT depending on the
10097 two counts.
10098
10099 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10100
10101 if (code == ASHIFTRT && first_code == ASHIFT
10102 && GET_MODE (varop) == shift_mode
10103 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10104 > first_count))
10105 {
10106 varop = XEXP (varop, 0);
10107 count -= first_count;
10108 if (count < 0)
10109 {
10110 count = -count;
10111 code = ASHIFT;
10112 }
10113
10114 continue;
10115 }
10116
10117 /* There are some cases we can't do. If CODE is ASHIFTRT,
10118 we can only do this if FIRST_CODE is also ASHIFTRT.
10119
10120 We can't do the case when CODE is ROTATE and FIRST_CODE is
10121 ASHIFTRT.
10122
10123 If the mode of this shift is not the mode of the outer shift,
10124 we can't do this if either shift is a right shift or ROTATE.
10125
10126 Finally, we can't do any of these if the mode is too wide
10127 unless the codes are the same.
10128
10129 Handle the case where the shift codes are the same
10130 first. */
10131
10132 if (code == first_code)
10133 {
10134 if (GET_MODE (varop) != result_mode
10135 && (code == ASHIFTRT || code == LSHIFTRT
10136 || code == ROTATE))
10137 break;
10138
10139 count += first_count;
10140 varop = XEXP (varop, 0);
10141 continue;
10142 }
10143
10144 if (code == ASHIFTRT
10145 || (code == ROTATE && first_code == ASHIFTRT)
10146 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
10147 || (GET_MODE (varop) != result_mode
10148 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10149 || first_code == ROTATE
10150 || code == ROTATE)))
10151 break;
10152
10153 /* To compute the mask to apply after the shift, shift the
10154 nonzero bits of the inner shift the same way the
10155 outer shift will. */
10156
10157 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10158
10159 mask_rtx
10160 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10161 GEN_INT (count));
10162
10163 /* Give up if we can't compute an outer operation to use. */
10164 if (mask_rtx == 0
10165 || !CONST_INT_P (mask_rtx)
10166 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10167 INTVAL (mask_rtx),
10168 result_mode, &complement_p))
10169 break;
10170
10171 /* If the shifts are in the same direction, we add the
10172 counts. Otherwise, we subtract them. */
10173 if ((code == ASHIFTRT || code == LSHIFTRT)
10174 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10175 count += first_count;
10176 else
10177 count -= first_count;
10178
10179 /* If COUNT is positive, the new shift is usually CODE,
10180 except for the two exceptions below, in which case it is
10181 FIRST_CODE. If the count is negative, FIRST_CODE should
10182 always be used */
10183 if (count > 0
10184 && ((first_code == ROTATE && code == ASHIFT)
10185 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10186 code = first_code;
10187 else if (count < 0)
10188 code = first_code, count = -count;
10189
10190 varop = XEXP (varop, 0);
10191 continue;
10192 }
10193
10194 /* If we have (A << B << C) for any shift, we can convert this to
10195 (A << C << B). This wins if A is a constant. Only try this if
10196 B is not a constant. */
10197
10198 else if (GET_CODE (varop) == code
10199 && CONST_INT_P (XEXP (varop, 0))
10200 && !CONST_INT_P (XEXP (varop, 1)))
10201 {
10202 rtx new_rtx = simplify_const_binary_operation (code, mode,
10203 XEXP (varop, 0),
10204 GEN_INT (count));
10205 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10206 count = 0;
10207 continue;
10208 }
10209 break;
10210
10211 case NOT:
10212 if (VECTOR_MODE_P (mode))
10213 break;
10214
10215 /* Make this fit the case below. */
10216 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10217 GEN_INT (GET_MODE_MASK (mode)));
10218 continue;
10219
10220 case IOR:
10221 case AND:
10222 case XOR:
10223 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10224 with C the size of VAROP - 1 and the shift is logical if
10225 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10226 we have an (le X 0) operation. If we have an arithmetic shift
10227 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10228 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10229
10230 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10231 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10232 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10233 && (code == LSHIFTRT || code == ASHIFTRT)
10234 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10235 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10236 {
10237 count = 0;
10238 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10239 const0_rtx);
10240
10241 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10242 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10243
10244 continue;
10245 }
10246
10247 /* If we have (shift (logical)), move the logical to the outside
10248 to allow it to possibly combine with another logical and the
10249 shift to combine with another shift. This also canonicalizes to
10250 what a ZERO_EXTRACT looks like. Also, some machines have
10251 (and (shift)) insns. */
10252
10253 if (CONST_INT_P (XEXP (varop, 1))
10254 /* We can't do this if we have (ashiftrt (xor)) and the
10255 constant has its sign bit set in shift_mode. */
10256 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10257 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10258 shift_mode))
10259 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10260 XEXP (varop, 1),
10261 GEN_INT (count))) != 0
10262 && CONST_INT_P (new_rtx)
10263 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10264 INTVAL (new_rtx), result_mode, &complement_p))
10265 {
10266 varop = XEXP (varop, 0);
10267 continue;
10268 }
10269
10270 /* If we can't do that, try to simplify the shift in each arm of the
10271 logical expression, make a new logical expression, and apply
10272 the inverse distributive law. This also can't be done
10273 for some (ashiftrt (xor)). */
10274 if (CONST_INT_P (XEXP (varop, 1))
10275 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10276 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10277 shift_mode)))
10278 {
10279 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10280 XEXP (varop, 0), count);
10281 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10282 XEXP (varop, 1), count);
10283
10284 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10285 lhs, rhs);
10286 varop = apply_distributive_law (varop);
10287
10288 count = 0;
10289 continue;
10290 }
10291 break;
10292
10293 case EQ:
10294 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10295 says that the sign bit can be tested, FOO has mode MODE, C is
10296 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10297 that may be nonzero. */
10298 if (code == LSHIFTRT
10299 && XEXP (varop, 1) == const0_rtx
10300 && GET_MODE (XEXP (varop, 0)) == result_mode
10301 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10302 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10303 && STORE_FLAG_VALUE == -1
10304 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10305 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10306 &complement_p))
10307 {
10308 varop = XEXP (varop, 0);
10309 count = 0;
10310 continue;
10311 }
10312 break;
10313
10314 case NEG:
10315 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10316 than the number of bits in the mode is equivalent to A. */
10317 if (code == LSHIFTRT
10318 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10319 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10320 {
10321 varop = XEXP (varop, 0);
10322 count = 0;
10323 continue;
10324 }
10325
10326 /* NEG commutes with ASHIFT since it is multiplication. Move the
10327 NEG outside to allow shifts to combine. */
10328 if (code == ASHIFT
10329 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10330 &complement_p))
10331 {
10332 varop = XEXP (varop, 0);
10333 continue;
10334 }
10335 break;
10336
10337 case PLUS:
10338 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10339 is one less than the number of bits in the mode is
10340 equivalent to (xor A 1). */
10341 if (code == LSHIFTRT
10342 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10343 && XEXP (varop, 1) == constm1_rtx
10344 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10345 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10346 &complement_p))
10347 {
10348 count = 0;
10349 varop = XEXP (varop, 0);
10350 continue;
10351 }
10352
10353 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10354 that might be nonzero in BAR are those being shifted out and those
10355 bits are known zero in FOO, we can replace the PLUS with FOO.
10356 Similarly in the other operand order. This code occurs when
10357 we are computing the size of a variable-size array. */
10358
10359 if ((code == ASHIFTRT || code == LSHIFTRT)
10360 && count < HOST_BITS_PER_WIDE_INT
10361 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10362 && (nonzero_bits (XEXP (varop, 1), result_mode)
10363 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10364 {
10365 varop = XEXP (varop, 0);
10366 continue;
10367 }
10368 else if ((code == ASHIFTRT || code == LSHIFTRT)
10369 && count < HOST_BITS_PER_WIDE_INT
10370 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10371 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10372 >> count)
10373 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10374 & nonzero_bits (XEXP (varop, 1),
10375 result_mode)))
10376 {
10377 varop = XEXP (varop, 1);
10378 continue;
10379 }
10380
10381 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10382 if (code == ASHIFT
10383 && CONST_INT_P (XEXP (varop, 1))
10384 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10385 XEXP (varop, 1),
10386 GEN_INT (count))) != 0
10387 && CONST_INT_P (new_rtx)
10388 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10389 INTVAL (new_rtx), result_mode, &complement_p))
10390 {
10391 varop = XEXP (varop, 0);
10392 continue;
10393 }
10394
10395 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10396 signbit', and attempt to change the PLUS to an XOR and move it to
10397 the outer operation as is done above in the AND/IOR/XOR case
10398 leg for shift(logical). See details in logical handling above
10399 for reasoning in doing so. */
10400 if (code == LSHIFTRT
10401 && CONST_INT_P (XEXP (varop, 1))
10402 && mode_signbit_p (result_mode, XEXP (varop, 1))
10403 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10404 XEXP (varop, 1),
10405 GEN_INT (count))) != 0
10406 && CONST_INT_P (new_rtx)
10407 && merge_outer_ops (&outer_op, &outer_const, XOR,
10408 INTVAL (new_rtx), result_mode, &complement_p))
10409 {
10410 varop = XEXP (varop, 0);
10411 continue;
10412 }
10413
10414 break;
10415
10416 case MINUS:
10417 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10418 with C the size of VAROP - 1 and the shift is logical if
10419 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10420 we have a (gt X 0) operation. If the shift is arithmetic with
10421 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10422 we have a (neg (gt X 0)) operation. */
10423
10424 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10425 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10426 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10427 && (code == LSHIFTRT || code == ASHIFTRT)
10428 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10429 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10430 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10431 {
10432 count = 0;
10433 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10434 const0_rtx);
10435
10436 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10437 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10438
10439 continue;
10440 }
10441 break;
10442
10443 case TRUNCATE:
10444 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10445 if the truncate does not affect the value. */
10446 if (code == LSHIFTRT
10447 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10448 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10449 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10450 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
10451 - GET_MODE_BITSIZE (GET_MODE (varop)))))
10452 {
10453 rtx varop_inner = XEXP (varop, 0);
10454
10455 varop_inner
10456 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10457 XEXP (varop_inner, 0),
10458 GEN_INT
10459 (count + INTVAL (XEXP (varop_inner, 1))));
10460 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10461 count = 0;
10462 continue;
10463 }
10464 break;
10465
10466 default:
10467 break;
10468 }
10469
10470 break;
10471 }
10472
10473 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10474 outer_op, outer_const);
10475
10476 /* We have now finished analyzing the shift. The result should be
10477 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10478 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10479 to the result of the shift. OUTER_CONST is the relevant constant,
10480 but we must turn off all bits turned off in the shift. */
10481
10482 if (outer_op == UNKNOWN
10483 && orig_code == code && orig_count == count
10484 && varop == orig_varop
10485 && shift_mode == GET_MODE (varop))
10486 return NULL_RTX;
10487
10488 /* Make a SUBREG if necessary. If we can't make it, fail. */
10489 varop = gen_lowpart (shift_mode, varop);
10490 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10491 return NULL_RTX;
10492
10493 /* If we have an outer operation and we just made a shift, it is
10494 possible that we could have simplified the shift were it not
10495 for the outer operation. So try to do the simplification
10496 recursively. */
10497
10498 if (outer_op != UNKNOWN)
10499 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10500 else
10501 x = NULL_RTX;
10502
10503 if (x == NULL_RTX)
10504 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10505
10506 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10507 turn off all the bits that the shift would have turned off. */
10508 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10509 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10510 GET_MODE_MASK (result_mode) >> orig_count);
10511
10512 /* Do the remainder of the processing in RESULT_MODE. */
10513 x = gen_lowpart_or_truncate (result_mode, x);
10514
10515 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10516 operation. */
10517 if (complement_p)
10518 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10519
10520 if (outer_op != UNKNOWN)
10521 {
10522 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10523 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10524 outer_const = trunc_int_for_mode (outer_const, result_mode);
10525
10526 if (outer_op == AND)
10527 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10528 else if (outer_op == SET)
10529 {
10530 /* This means that we have determined that the result is
10531 equivalent to a constant. This should be rare. */
10532 if (!side_effects_p (x))
10533 x = GEN_INT (outer_const);
10534 }
10535 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10536 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10537 else
10538 x = simplify_gen_binary (outer_op, result_mode, x,
10539 GEN_INT (outer_const));
10540 }
10541
10542 return x;
10543 }
10544
10545 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10546 The result of the shift is RESULT_MODE. If we cannot simplify it,
10547 return X or, if it is NULL, synthesize the expression with
10548 simplify_gen_binary. Otherwise, return a simplified value.
10549
10550 The shift is normally computed in the widest mode we find in VAROP, as
10551 long as it isn't a different number of words than RESULT_MODE. Exceptions
10552 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10553
10554 static rtx
10555 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10556 rtx varop, int count)
10557 {
10558 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10559 if (tem)
10560 return tem;
10561
10562 if (!x)
10563 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10564 if (GET_MODE (x) != result_mode)
10565 x = gen_lowpart (result_mode, x);
10566 return x;
10567 }
10568
10569 \f
10570 /* Like recog, but we receive the address of a pointer to a new pattern.
10571 We try to match the rtx that the pointer points to.
10572 If that fails, we may try to modify or replace the pattern,
10573 storing the replacement into the same pointer object.
10574
10575 Modifications include deletion or addition of CLOBBERs.
10576
10577 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10578 the CLOBBERs are placed.
10579
10580 The value is the final insn code from the pattern ultimately matched,
10581 or -1. */
10582
10583 static int
10584 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10585 {
10586 rtx pat = *pnewpat;
10587 int insn_code_number;
10588 int num_clobbers_to_add = 0;
10589 int i;
10590 rtx notes = 0;
10591 rtx old_notes, old_pat;
10592
10593 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10594 we use to indicate that something didn't match. If we find such a
10595 thing, force rejection. */
10596 if (GET_CODE (pat) == PARALLEL)
10597 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10598 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10599 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10600 return -1;
10601
10602 old_pat = PATTERN (insn);
10603 old_notes = REG_NOTES (insn);
10604 PATTERN (insn) = pat;
10605 REG_NOTES (insn) = 0;
10606
10607 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10608 if (dump_file && (dump_flags & TDF_DETAILS))
10609 {
10610 if (insn_code_number < 0)
10611 fputs ("Failed to match this instruction:\n", dump_file);
10612 else
10613 fputs ("Successfully matched this instruction:\n", dump_file);
10614 print_rtl_single (dump_file, pat);
10615 }
10616
10617 /* If it isn't, there is the possibility that we previously had an insn
10618 that clobbered some register as a side effect, but the combined
10619 insn doesn't need to do that. So try once more without the clobbers
10620 unless this represents an ASM insn. */
10621
10622 if (insn_code_number < 0 && ! check_asm_operands (pat)
10623 && GET_CODE (pat) == PARALLEL)
10624 {
10625 int pos;
10626
10627 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10628 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10629 {
10630 if (i != pos)
10631 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10632 pos++;
10633 }
10634
10635 SUBST_INT (XVECLEN (pat, 0), pos);
10636
10637 if (pos == 1)
10638 pat = XVECEXP (pat, 0, 0);
10639
10640 PATTERN (insn) = pat;
10641 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10642 if (dump_file && (dump_flags & TDF_DETAILS))
10643 {
10644 if (insn_code_number < 0)
10645 fputs ("Failed to match this instruction:\n", dump_file);
10646 else
10647 fputs ("Successfully matched this instruction:\n", dump_file);
10648 print_rtl_single (dump_file, pat);
10649 }
10650 }
10651 PATTERN (insn) = old_pat;
10652 REG_NOTES (insn) = old_notes;
10653
10654 /* Recognize all noop sets, these will be killed by followup pass. */
10655 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10656 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10657
10658 /* If we had any clobbers to add, make a new pattern than contains
10659 them. Then check to make sure that all of them are dead. */
10660 if (num_clobbers_to_add)
10661 {
10662 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10663 rtvec_alloc (GET_CODE (pat) == PARALLEL
10664 ? (XVECLEN (pat, 0)
10665 + num_clobbers_to_add)
10666 : num_clobbers_to_add + 1));
10667
10668 if (GET_CODE (pat) == PARALLEL)
10669 for (i = 0; i < XVECLEN (pat, 0); i++)
10670 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10671 else
10672 XVECEXP (newpat, 0, 0) = pat;
10673
10674 add_clobbers (newpat, insn_code_number);
10675
10676 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10677 i < XVECLEN (newpat, 0); i++)
10678 {
10679 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10680 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10681 return -1;
10682 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10683 {
10684 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10685 notes = alloc_reg_note (REG_UNUSED,
10686 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10687 }
10688 }
10689 pat = newpat;
10690 }
10691
10692 *pnewpat = pat;
10693 *pnotes = notes;
10694
10695 return insn_code_number;
10696 }
10697 \f
10698 /* Like gen_lowpart_general but for use by combine. In combine it
10699 is not possible to create any new pseudoregs. However, it is
10700 safe to create invalid memory addresses, because combine will
10701 try to recognize them and all they will do is make the combine
10702 attempt fail.
10703
10704 If for some reason this cannot do its job, an rtx
10705 (clobber (const_int 0)) is returned.
10706 An insn containing that will not be recognized. */
10707
10708 static rtx
10709 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10710 {
10711 enum machine_mode imode = GET_MODE (x);
10712 unsigned int osize = GET_MODE_SIZE (omode);
10713 unsigned int isize = GET_MODE_SIZE (imode);
10714 rtx result;
10715
10716 if (omode == imode)
10717 return x;
10718
10719 /* Return identity if this is a CONST or symbolic reference. */
10720 if (omode == Pmode
10721 && (GET_CODE (x) == CONST
10722 || GET_CODE (x) == SYMBOL_REF
10723 || GET_CODE (x) == LABEL_REF))
10724 return x;
10725
10726 /* We can only support MODE being wider than a word if X is a
10727 constant integer or has a mode the same size. */
10728 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10729 && ! ((imode == VOIDmode
10730 && (CONST_INT_P (x)
10731 || GET_CODE (x) == CONST_DOUBLE))
10732 || isize == osize))
10733 goto fail;
10734
10735 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10736 won't know what to do. So we will strip off the SUBREG here and
10737 process normally. */
10738 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10739 {
10740 x = SUBREG_REG (x);
10741
10742 /* For use in case we fall down into the address adjustments
10743 further below, we need to adjust the known mode and size of
10744 x; imode and isize, since we just adjusted x. */
10745 imode = GET_MODE (x);
10746
10747 if (imode == omode)
10748 return x;
10749
10750 isize = GET_MODE_SIZE (imode);
10751 }
10752
10753 result = gen_lowpart_common (omode, x);
10754
10755 if (result)
10756 return result;
10757
10758 if (MEM_P (x))
10759 {
10760 int offset = 0;
10761
10762 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10763 address. */
10764 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10765 goto fail;
10766
10767 /* If we want to refer to something bigger than the original memref,
10768 generate a paradoxical subreg instead. That will force a reload
10769 of the original memref X. */
10770 if (isize < osize)
10771 return gen_rtx_SUBREG (omode, x, 0);
10772
10773 if (WORDS_BIG_ENDIAN)
10774 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10775
10776 /* Adjust the address so that the address-after-the-data is
10777 unchanged. */
10778 if (BYTES_BIG_ENDIAN)
10779 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10780
10781 return adjust_address_nv (x, omode, offset);
10782 }
10783
10784 /* If X is a comparison operator, rewrite it in a new mode. This
10785 probably won't match, but may allow further simplifications. */
10786 else if (COMPARISON_P (x))
10787 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10788
10789 /* If we couldn't simplify X any other way, just enclose it in a
10790 SUBREG. Normally, this SUBREG won't match, but some patterns may
10791 include an explicit SUBREG or we may simplify it further in combine. */
10792 else
10793 {
10794 int offset = 0;
10795 rtx res;
10796
10797 offset = subreg_lowpart_offset (omode, imode);
10798 if (imode == VOIDmode)
10799 {
10800 imode = int_mode_for_mode (omode);
10801 x = gen_lowpart_common (imode, x);
10802 if (x == NULL)
10803 goto fail;
10804 }
10805 res = simplify_gen_subreg (omode, x, imode, offset);
10806 if (res)
10807 return res;
10808 }
10809
10810 fail:
10811 return gen_rtx_CLOBBER (omode, const0_rtx);
10812 }
10813 \f
10814 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10815 comparison code that will be tested.
10816
10817 The result is a possibly different comparison code to use. *POP0 and
10818 *POP1 may be updated.
10819
10820 It is possible that we might detect that a comparison is either always
10821 true or always false. However, we do not perform general constant
10822 folding in combine, so this knowledge isn't useful. Such tautologies
10823 should have been detected earlier. Hence we ignore all such cases. */
10824
10825 static enum rtx_code
10826 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10827 {
10828 rtx op0 = *pop0;
10829 rtx op1 = *pop1;
10830 rtx tem, tem1;
10831 int i;
10832 enum machine_mode mode, tmode;
10833
10834 /* Try a few ways of applying the same transformation to both operands. */
10835 while (1)
10836 {
10837 #ifndef WORD_REGISTER_OPERATIONS
10838 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10839 so check specially. */
10840 if (code != GTU && code != GEU && code != LTU && code != LEU
10841 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10842 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10843 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10844 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10845 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10846 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10847 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10848 && CONST_INT_P (XEXP (op0, 1))
10849 && XEXP (op0, 1) == XEXP (op1, 1)
10850 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10851 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10852 && (INTVAL (XEXP (op0, 1))
10853 == (GET_MODE_BITSIZE (GET_MODE (op0))
10854 - (GET_MODE_BITSIZE
10855 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10856 {
10857 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10858 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10859 }
10860 #endif
10861
10862 /* If both operands are the same constant shift, see if we can ignore the
10863 shift. We can if the shift is a rotate or if the bits shifted out of
10864 this shift are known to be zero for both inputs and if the type of
10865 comparison is compatible with the shift. */
10866 if (GET_CODE (op0) == GET_CODE (op1)
10867 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10868 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10869 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10870 && (code != GT && code != LT && code != GE && code != LE))
10871 || (GET_CODE (op0) == ASHIFTRT
10872 && (code != GTU && code != LTU
10873 && code != GEU && code != LEU)))
10874 && CONST_INT_P (XEXP (op0, 1))
10875 && INTVAL (XEXP (op0, 1)) >= 0
10876 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10877 && XEXP (op0, 1) == XEXP (op1, 1))
10878 {
10879 enum machine_mode mode = GET_MODE (op0);
10880 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10881 int shift_count = INTVAL (XEXP (op0, 1));
10882
10883 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10884 mask &= (mask >> shift_count) << shift_count;
10885 else if (GET_CODE (op0) == ASHIFT)
10886 mask = (mask & (mask << shift_count)) >> shift_count;
10887
10888 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10889 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10890 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10891 else
10892 break;
10893 }
10894
10895 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10896 SUBREGs are of the same mode, and, in both cases, the AND would
10897 be redundant if the comparison was done in the narrower mode,
10898 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10899 and the operand's possibly nonzero bits are 0xffffff01; in that case
10900 if we only care about QImode, we don't need the AND). This case
10901 occurs if the output mode of an scc insn is not SImode and
10902 STORE_FLAG_VALUE == 1 (e.g., the 386).
10903
10904 Similarly, check for a case where the AND's are ZERO_EXTEND
10905 operations from some narrower mode even though a SUBREG is not
10906 present. */
10907
10908 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10909 && CONST_INT_P (XEXP (op0, 1))
10910 && CONST_INT_P (XEXP (op1, 1)))
10911 {
10912 rtx inner_op0 = XEXP (op0, 0);
10913 rtx inner_op1 = XEXP (op1, 0);
10914 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10915 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10916 int changed = 0;
10917
10918 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10919 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10920 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10921 && (GET_MODE (SUBREG_REG (inner_op0))
10922 == GET_MODE (SUBREG_REG (inner_op1)))
10923 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10924 <= HOST_BITS_PER_WIDE_INT)
10925 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10926 GET_MODE (SUBREG_REG (inner_op0)))))
10927 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10928 GET_MODE (SUBREG_REG (inner_op1))))))
10929 {
10930 op0 = SUBREG_REG (inner_op0);
10931 op1 = SUBREG_REG (inner_op1);
10932
10933 /* The resulting comparison is always unsigned since we masked
10934 off the original sign bit. */
10935 code = unsigned_condition (code);
10936
10937 changed = 1;
10938 }
10939
10940 else if (c0 == c1)
10941 for (tmode = GET_CLASS_NARROWEST_MODE
10942 (GET_MODE_CLASS (GET_MODE (op0)));
10943 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10944 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10945 {
10946 op0 = gen_lowpart (tmode, inner_op0);
10947 op1 = gen_lowpart (tmode, inner_op1);
10948 code = unsigned_condition (code);
10949 changed = 1;
10950 break;
10951 }
10952
10953 if (! changed)
10954 break;
10955 }
10956
10957 /* If both operands are NOT, we can strip off the outer operation
10958 and adjust the comparison code for swapped operands; similarly for
10959 NEG, except that this must be an equality comparison. */
10960 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10961 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10962 && (code == EQ || code == NE)))
10963 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10964
10965 else
10966 break;
10967 }
10968
10969 /* If the first operand is a constant, swap the operands and adjust the
10970 comparison code appropriately, but don't do this if the second operand
10971 is already a constant integer. */
10972 if (swap_commutative_operands_p (op0, op1))
10973 {
10974 tem = op0, op0 = op1, op1 = tem;
10975 code = swap_condition (code);
10976 }
10977
10978 /* We now enter a loop during which we will try to simplify the comparison.
10979 For the most part, we only are concerned with comparisons with zero,
10980 but some things may really be comparisons with zero but not start
10981 out looking that way. */
10982
10983 while (CONST_INT_P (op1))
10984 {
10985 enum machine_mode mode = GET_MODE (op0);
10986 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10987 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10988 int equality_comparison_p;
10989 int sign_bit_comparison_p;
10990 int unsigned_comparison_p;
10991 HOST_WIDE_INT const_op;
10992
10993 /* We only want to handle integral modes. This catches VOIDmode,
10994 CCmode, and the floating-point modes. An exception is that we
10995 can handle VOIDmode if OP0 is a COMPARE or a comparison
10996 operation. */
10997
10998 if (GET_MODE_CLASS (mode) != MODE_INT
10999 && ! (mode == VOIDmode
11000 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11001 break;
11002
11003 /* Get the constant we are comparing against and turn off all bits
11004 not on in our mode. */
11005 const_op = INTVAL (op1);
11006 if (mode != VOIDmode)
11007 const_op = trunc_int_for_mode (const_op, mode);
11008 op1 = GEN_INT (const_op);
11009
11010 /* If we are comparing against a constant power of two and the value
11011 being compared can only have that single bit nonzero (e.g., it was
11012 `and'ed with that bit), we can replace this with a comparison
11013 with zero. */
11014 if (const_op
11015 && (code == EQ || code == NE || code == GE || code == GEU
11016 || code == LT || code == LTU)
11017 && mode_width <= HOST_BITS_PER_WIDE_INT
11018 && exact_log2 (const_op) >= 0
11019 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
11020 {
11021 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11022 op1 = const0_rtx, const_op = 0;
11023 }
11024
11025 /* Similarly, if we are comparing a value known to be either -1 or
11026 0 with -1, change it to the opposite comparison against zero. */
11027
11028 if (const_op == -1
11029 && (code == EQ || code == NE || code == GT || code == LE
11030 || code == GEU || code == LTU)
11031 && num_sign_bit_copies (op0, mode) == mode_width)
11032 {
11033 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11034 op1 = const0_rtx, const_op = 0;
11035 }
11036
11037 /* Do some canonicalizations based on the comparison code. We prefer
11038 comparisons against zero and then prefer equality comparisons.
11039 If we can reduce the size of a constant, we will do that too. */
11040
11041 switch (code)
11042 {
11043 case LT:
11044 /* < C is equivalent to <= (C - 1) */
11045 if (const_op > 0)
11046 {
11047 const_op -= 1;
11048 op1 = GEN_INT (const_op);
11049 code = LE;
11050 /* ... fall through to LE case below. */
11051 }
11052 else
11053 break;
11054
11055 case LE:
11056 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11057 if (const_op < 0)
11058 {
11059 const_op += 1;
11060 op1 = GEN_INT (const_op);
11061 code = LT;
11062 }
11063
11064 /* If we are doing a <= 0 comparison on a value known to have
11065 a zero sign bit, we can replace this with == 0. */
11066 else if (const_op == 0
11067 && mode_width <= HOST_BITS_PER_WIDE_INT
11068 && (nonzero_bits (op0, mode)
11069 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11070 == 0)
11071 code = EQ;
11072 break;
11073
11074 case GE:
11075 /* >= C is equivalent to > (C - 1). */
11076 if (const_op > 0)
11077 {
11078 const_op -= 1;
11079 op1 = GEN_INT (const_op);
11080 code = GT;
11081 /* ... fall through to GT below. */
11082 }
11083 else
11084 break;
11085
11086 case GT:
11087 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11088 if (const_op < 0)
11089 {
11090 const_op += 1;
11091 op1 = GEN_INT (const_op);
11092 code = GE;
11093 }
11094
11095 /* If we are doing a > 0 comparison on a value known to have
11096 a zero sign bit, we can replace this with != 0. */
11097 else if (const_op == 0
11098 && mode_width <= HOST_BITS_PER_WIDE_INT
11099 && (nonzero_bits (op0, mode)
11100 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11101 == 0)
11102 code = NE;
11103 break;
11104
11105 case LTU:
11106 /* < C is equivalent to <= (C - 1). */
11107 if (const_op > 0)
11108 {
11109 const_op -= 1;
11110 op1 = GEN_INT (const_op);
11111 code = LEU;
11112 /* ... fall through ... */
11113 }
11114
11115 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11116 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11117 && (unsigned HOST_WIDE_INT) const_op
11118 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11119 {
11120 const_op = 0, op1 = const0_rtx;
11121 code = GE;
11122 break;
11123 }
11124 else
11125 break;
11126
11127 case LEU:
11128 /* unsigned <= 0 is equivalent to == 0 */
11129 if (const_op == 0)
11130 code = EQ;
11131
11132 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11133 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11134 && (unsigned HOST_WIDE_INT) const_op
11135 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11136 {
11137 const_op = 0, op1 = const0_rtx;
11138 code = GE;
11139 }
11140 break;
11141
11142 case GEU:
11143 /* >= C is equivalent to > (C - 1). */
11144 if (const_op > 1)
11145 {
11146 const_op -= 1;
11147 op1 = GEN_INT (const_op);
11148 code = GTU;
11149 /* ... fall through ... */
11150 }
11151
11152 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11153 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11154 && (unsigned HOST_WIDE_INT) const_op
11155 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11156 {
11157 const_op = 0, op1 = const0_rtx;
11158 code = LT;
11159 break;
11160 }
11161 else
11162 break;
11163
11164 case GTU:
11165 /* unsigned > 0 is equivalent to != 0 */
11166 if (const_op == 0)
11167 code = NE;
11168
11169 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11170 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11171 && (unsigned HOST_WIDE_INT) const_op
11172 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11173 {
11174 const_op = 0, op1 = const0_rtx;
11175 code = LT;
11176 }
11177 break;
11178
11179 default:
11180 break;
11181 }
11182
11183 /* Compute some predicates to simplify code below. */
11184
11185 equality_comparison_p = (code == EQ || code == NE);
11186 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11187 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11188 || code == GEU);
11189
11190 /* If this is a sign bit comparison and we can do arithmetic in
11191 MODE, say that we will only be needing the sign bit of OP0. */
11192 if (sign_bit_comparison_p
11193 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11194 op0 = force_to_mode (op0, mode,
11195 (unsigned HOST_WIDE_INT) 1
11196 << (GET_MODE_BITSIZE (mode) - 1),
11197 0);
11198
11199 /* Now try cases based on the opcode of OP0. If none of the cases
11200 does a "continue", we exit this loop immediately after the
11201 switch. */
11202
11203 switch (GET_CODE (op0))
11204 {
11205 case ZERO_EXTRACT:
11206 /* If we are extracting a single bit from a variable position in
11207 a constant that has only a single bit set and are comparing it
11208 with zero, we can convert this into an equality comparison
11209 between the position and the location of the single bit. */
11210 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11211 have already reduced the shift count modulo the word size. */
11212 if (!SHIFT_COUNT_TRUNCATED
11213 && CONST_INT_P (XEXP (op0, 0))
11214 && XEXP (op0, 1) == const1_rtx
11215 && equality_comparison_p && const_op == 0
11216 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11217 {
11218 if (BITS_BIG_ENDIAN)
11219 {
11220 enum machine_mode new_mode
11221 = mode_for_extraction (EP_extzv, 1);
11222 if (new_mode == MAX_MACHINE_MODE)
11223 i = BITS_PER_WORD - 1 - i;
11224 else
11225 {
11226 mode = new_mode;
11227 i = (GET_MODE_BITSIZE (mode) - 1 - i);
11228 }
11229 }
11230
11231 op0 = XEXP (op0, 2);
11232 op1 = GEN_INT (i);
11233 const_op = i;
11234
11235 /* Result is nonzero iff shift count is equal to I. */
11236 code = reverse_condition (code);
11237 continue;
11238 }
11239
11240 /* ... fall through ... */
11241
11242 case SIGN_EXTRACT:
11243 tem = expand_compound_operation (op0);
11244 if (tem != op0)
11245 {
11246 op0 = tem;
11247 continue;
11248 }
11249 break;
11250
11251 case NOT:
11252 /* If testing for equality, we can take the NOT of the constant. */
11253 if (equality_comparison_p
11254 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11255 {
11256 op0 = XEXP (op0, 0);
11257 op1 = tem;
11258 continue;
11259 }
11260
11261 /* If just looking at the sign bit, reverse the sense of the
11262 comparison. */
11263 if (sign_bit_comparison_p)
11264 {
11265 op0 = XEXP (op0, 0);
11266 code = (code == GE ? LT : GE);
11267 continue;
11268 }
11269 break;
11270
11271 case NEG:
11272 /* If testing for equality, we can take the NEG of the constant. */
11273 if (equality_comparison_p
11274 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11275 {
11276 op0 = XEXP (op0, 0);
11277 op1 = tem;
11278 continue;
11279 }
11280
11281 /* The remaining cases only apply to comparisons with zero. */
11282 if (const_op != 0)
11283 break;
11284
11285 /* When X is ABS or is known positive,
11286 (neg X) is < 0 if and only if X != 0. */
11287
11288 if (sign_bit_comparison_p
11289 && (GET_CODE (XEXP (op0, 0)) == ABS
11290 || (mode_width <= HOST_BITS_PER_WIDE_INT
11291 && (nonzero_bits (XEXP (op0, 0), mode)
11292 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11293 == 0)))
11294 {
11295 op0 = XEXP (op0, 0);
11296 code = (code == LT ? NE : EQ);
11297 continue;
11298 }
11299
11300 /* If we have NEG of something whose two high-order bits are the
11301 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11302 if (num_sign_bit_copies (op0, mode) >= 2)
11303 {
11304 op0 = XEXP (op0, 0);
11305 code = swap_condition (code);
11306 continue;
11307 }
11308 break;
11309
11310 case ROTATE:
11311 /* If we are testing equality and our count is a constant, we
11312 can perform the inverse operation on our RHS. */
11313 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11314 && (tem = simplify_binary_operation (ROTATERT, mode,
11315 op1, XEXP (op0, 1))) != 0)
11316 {
11317 op0 = XEXP (op0, 0);
11318 op1 = tem;
11319 continue;
11320 }
11321
11322 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11323 a particular bit. Convert it to an AND of a constant of that
11324 bit. This will be converted into a ZERO_EXTRACT. */
11325 if (const_op == 0 && sign_bit_comparison_p
11326 && CONST_INT_P (XEXP (op0, 1))
11327 && mode_width <= HOST_BITS_PER_WIDE_INT)
11328 {
11329 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11330 ((unsigned HOST_WIDE_INT) 1
11331 << (mode_width - 1
11332 - INTVAL (XEXP (op0, 1)))));
11333 code = (code == LT ? NE : EQ);
11334 continue;
11335 }
11336
11337 /* Fall through. */
11338
11339 case ABS:
11340 /* ABS is ignorable inside an equality comparison with zero. */
11341 if (const_op == 0 && equality_comparison_p)
11342 {
11343 op0 = XEXP (op0, 0);
11344 continue;
11345 }
11346 break;
11347
11348 case SIGN_EXTEND:
11349 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11350 (compare FOO CONST) if CONST fits in FOO's mode and we
11351 are either testing inequality or have an unsigned
11352 comparison with ZERO_EXTEND or a signed comparison with
11353 SIGN_EXTEND. But don't do it if we don't have a compare
11354 insn of the given mode, since we'd have to revert it
11355 later on, and then we wouldn't know whether to sign- or
11356 zero-extend. */
11357 mode = GET_MODE (XEXP (op0, 0));
11358 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11359 && ! unsigned_comparison_p
11360 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11361 && ((unsigned HOST_WIDE_INT) const_op
11362 < (((unsigned HOST_WIDE_INT) 1
11363 << (GET_MODE_BITSIZE (mode) - 1))))
11364 && have_insn_for (COMPARE, mode))
11365 {
11366 op0 = XEXP (op0, 0);
11367 continue;
11368 }
11369 break;
11370
11371 case SUBREG:
11372 /* Check for the case where we are comparing A - C1 with C2, that is
11373
11374 (subreg:MODE (plus (A) (-C1))) op (C2)
11375
11376 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11377 comparison in the wider mode. One of the following two conditions
11378 must be true in order for this to be valid:
11379
11380 1. The mode extension results in the same bit pattern being added
11381 on both sides and the comparison is equality or unsigned. As
11382 C2 has been truncated to fit in MODE, the pattern can only be
11383 all 0s or all 1s.
11384
11385 2. The mode extension results in the sign bit being copied on
11386 each side.
11387
11388 The difficulty here is that we have predicates for A but not for
11389 (A - C1) so we need to check that C1 is within proper bounds so
11390 as to perturbate A as little as possible. */
11391
11392 if (mode_width <= HOST_BITS_PER_WIDE_INT
11393 && subreg_lowpart_p (op0)
11394 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
11395 && GET_CODE (SUBREG_REG (op0)) == PLUS
11396 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11397 {
11398 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11399 rtx a = XEXP (SUBREG_REG (op0), 0);
11400 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11401
11402 if ((c1 > 0
11403 && (unsigned HOST_WIDE_INT) c1
11404 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11405 && (equality_comparison_p || unsigned_comparison_p)
11406 /* (A - C1) zero-extends if it is positive and sign-extends
11407 if it is negative, C2 both zero- and sign-extends. */
11408 && ((0 == (nonzero_bits (a, inner_mode)
11409 & ~GET_MODE_MASK (mode))
11410 && const_op >= 0)
11411 /* (A - C1) sign-extends if it is positive and 1-extends
11412 if it is negative, C2 both sign- and 1-extends. */
11413 || (num_sign_bit_copies (a, inner_mode)
11414 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11415 - mode_width)
11416 && const_op < 0)))
11417 || ((unsigned HOST_WIDE_INT) c1
11418 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11419 /* (A - C1) always sign-extends, like C2. */
11420 && num_sign_bit_copies (a, inner_mode)
11421 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11422 - (mode_width - 1))))
11423 {
11424 op0 = SUBREG_REG (op0);
11425 continue;
11426 }
11427 }
11428
11429 /* If the inner mode is narrower and we are extracting the low part,
11430 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11431 if (subreg_lowpart_p (op0)
11432 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
11433 /* Fall through */ ;
11434 else
11435 break;
11436
11437 /* ... fall through ... */
11438
11439 case ZERO_EXTEND:
11440 mode = GET_MODE (XEXP (op0, 0));
11441 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11442 && (unsigned_comparison_p || equality_comparison_p)
11443 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11444 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
11445 && have_insn_for (COMPARE, mode))
11446 {
11447 op0 = XEXP (op0, 0);
11448 continue;
11449 }
11450 break;
11451
11452 case PLUS:
11453 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11454 this for equality comparisons due to pathological cases involving
11455 overflows. */
11456 if (equality_comparison_p
11457 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11458 op1, XEXP (op0, 1))))
11459 {
11460 op0 = XEXP (op0, 0);
11461 op1 = tem;
11462 continue;
11463 }
11464
11465 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11466 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11467 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11468 {
11469 op0 = XEXP (XEXP (op0, 0), 0);
11470 code = (code == LT ? EQ : NE);
11471 continue;
11472 }
11473 break;
11474
11475 case MINUS:
11476 /* We used to optimize signed comparisons against zero, but that
11477 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11478 arrive here as equality comparisons, or (GEU, LTU) are
11479 optimized away. No need to special-case them. */
11480
11481 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11482 (eq B (minus A C)), whichever simplifies. We can only do
11483 this for equality comparisons due to pathological cases involving
11484 overflows. */
11485 if (equality_comparison_p
11486 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11487 XEXP (op0, 1), op1)))
11488 {
11489 op0 = XEXP (op0, 0);
11490 op1 = tem;
11491 continue;
11492 }
11493
11494 if (equality_comparison_p
11495 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11496 XEXP (op0, 0), op1)))
11497 {
11498 op0 = XEXP (op0, 1);
11499 op1 = tem;
11500 continue;
11501 }
11502
11503 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11504 of bits in X minus 1, is one iff X > 0. */
11505 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11506 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11507 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11508 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11509 {
11510 op0 = XEXP (op0, 1);
11511 code = (code == GE ? LE : GT);
11512 continue;
11513 }
11514 break;
11515
11516 case XOR:
11517 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11518 if C is zero or B is a constant. */
11519 if (equality_comparison_p
11520 && 0 != (tem = simplify_binary_operation (XOR, mode,
11521 XEXP (op0, 1), op1)))
11522 {
11523 op0 = XEXP (op0, 0);
11524 op1 = tem;
11525 continue;
11526 }
11527 break;
11528
11529 case EQ: case NE:
11530 case UNEQ: case LTGT:
11531 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11532 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11533 case UNORDERED: case ORDERED:
11534 /* We can't do anything if OP0 is a condition code value, rather
11535 than an actual data value. */
11536 if (const_op != 0
11537 || CC0_P (XEXP (op0, 0))
11538 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11539 break;
11540
11541 /* Get the two operands being compared. */
11542 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11543 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11544 else
11545 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11546
11547 /* Check for the cases where we simply want the result of the
11548 earlier test or the opposite of that result. */
11549 if (code == NE || code == EQ
11550 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11551 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11552 && (STORE_FLAG_VALUE
11553 & (((unsigned HOST_WIDE_INT) 1
11554 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11555 && (code == LT || code == GE)))
11556 {
11557 enum rtx_code new_code;
11558 if (code == LT || code == NE)
11559 new_code = GET_CODE (op0);
11560 else
11561 new_code = reversed_comparison_code (op0, NULL);
11562
11563 if (new_code != UNKNOWN)
11564 {
11565 code = new_code;
11566 op0 = tem;
11567 op1 = tem1;
11568 continue;
11569 }
11570 }
11571 break;
11572
11573 case IOR:
11574 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11575 iff X <= 0. */
11576 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11577 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11578 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11579 {
11580 op0 = XEXP (op0, 1);
11581 code = (code == GE ? GT : LE);
11582 continue;
11583 }
11584 break;
11585
11586 case AND:
11587 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11588 will be converted to a ZERO_EXTRACT later. */
11589 if (const_op == 0 && equality_comparison_p
11590 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11591 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11592 {
11593 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11594 XEXP (XEXP (op0, 0), 1));
11595 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11596 continue;
11597 }
11598
11599 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11600 zero and X is a comparison and C1 and C2 describe only bits set
11601 in STORE_FLAG_VALUE, we can compare with X. */
11602 if (const_op == 0 && equality_comparison_p
11603 && mode_width <= HOST_BITS_PER_WIDE_INT
11604 && CONST_INT_P (XEXP (op0, 1))
11605 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11606 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11607 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11608 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11609 {
11610 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11611 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11612 if ((~STORE_FLAG_VALUE & mask) == 0
11613 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11614 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11615 && COMPARISON_P (tem))))
11616 {
11617 op0 = XEXP (XEXP (op0, 0), 0);
11618 continue;
11619 }
11620 }
11621
11622 /* If we are doing an equality comparison of an AND of a bit equal
11623 to the sign bit, replace this with a LT or GE comparison of
11624 the underlying value. */
11625 if (equality_comparison_p
11626 && const_op == 0
11627 && CONST_INT_P (XEXP (op0, 1))
11628 && mode_width <= HOST_BITS_PER_WIDE_INT
11629 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11630 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11631 {
11632 op0 = XEXP (op0, 0);
11633 code = (code == EQ ? GE : LT);
11634 continue;
11635 }
11636
11637 /* If this AND operation is really a ZERO_EXTEND from a narrower
11638 mode, the constant fits within that mode, and this is either an
11639 equality or unsigned comparison, try to do this comparison in
11640 the narrower mode.
11641
11642 Note that in:
11643
11644 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11645 -> (ne:DI (reg:SI 4) (const_int 0))
11646
11647 unless TRULY_NOOP_TRUNCATION allows it or the register is
11648 known to hold a value of the required mode the
11649 transformation is invalid. */
11650 if ((equality_comparison_p || unsigned_comparison_p)
11651 && CONST_INT_P (XEXP (op0, 1))
11652 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11653 & GET_MODE_MASK (mode))
11654 + 1)) >= 0
11655 && const_op >> i == 0
11656 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11657 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11658 GET_MODE_BITSIZE (GET_MODE (op0)))
11659 || (REG_P (XEXP (op0, 0))
11660 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11661 {
11662 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11663 continue;
11664 }
11665
11666 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11667 fits in both M1 and M2 and the SUBREG is either paradoxical
11668 or represents the low part, permute the SUBREG and the AND
11669 and try again. */
11670 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11671 {
11672 unsigned HOST_WIDE_INT c1;
11673 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11674 /* Require an integral mode, to avoid creating something like
11675 (AND:SF ...). */
11676 if (SCALAR_INT_MODE_P (tmode)
11677 /* It is unsafe to commute the AND into the SUBREG if the
11678 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11679 not defined. As originally written the upper bits
11680 have a defined value due to the AND operation.
11681 However, if we commute the AND inside the SUBREG then
11682 they no longer have defined values and the meaning of
11683 the code has been changed. */
11684 && (0
11685 #ifdef WORD_REGISTER_OPERATIONS
11686 || (mode_width > GET_MODE_BITSIZE (tmode)
11687 && mode_width <= BITS_PER_WORD)
11688 #endif
11689 || (mode_width <= GET_MODE_BITSIZE (tmode)
11690 && subreg_lowpart_p (XEXP (op0, 0))))
11691 && CONST_INT_P (XEXP (op0, 1))
11692 && mode_width <= HOST_BITS_PER_WIDE_INT
11693 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11694 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11695 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11696 && c1 != mask
11697 && c1 != GET_MODE_MASK (tmode))
11698 {
11699 op0 = simplify_gen_binary (AND, tmode,
11700 SUBREG_REG (XEXP (op0, 0)),
11701 gen_int_mode (c1, tmode));
11702 op0 = gen_lowpart (mode, op0);
11703 continue;
11704 }
11705 }
11706
11707 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11708 if (const_op == 0 && equality_comparison_p
11709 && XEXP (op0, 1) == const1_rtx
11710 && GET_CODE (XEXP (op0, 0)) == NOT)
11711 {
11712 op0 = simplify_and_const_int (NULL_RTX, mode,
11713 XEXP (XEXP (op0, 0), 0), 1);
11714 code = (code == NE ? EQ : NE);
11715 continue;
11716 }
11717
11718 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11719 (eq (and (lshiftrt X) 1) 0).
11720 Also handle the case where (not X) is expressed using xor. */
11721 if (const_op == 0 && equality_comparison_p
11722 && XEXP (op0, 1) == const1_rtx
11723 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11724 {
11725 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11726 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11727
11728 if (GET_CODE (shift_op) == NOT
11729 || (GET_CODE (shift_op) == XOR
11730 && CONST_INT_P (XEXP (shift_op, 1))
11731 && CONST_INT_P (shift_count)
11732 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11733 && (UINTVAL (XEXP (shift_op, 1))
11734 == (unsigned HOST_WIDE_INT) 1
11735 << INTVAL (shift_count))))
11736 {
11737 op0
11738 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11739 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11740 code = (code == NE ? EQ : NE);
11741 continue;
11742 }
11743 }
11744 break;
11745
11746 case ASHIFT:
11747 /* If we have (compare (ashift FOO N) (const_int C)) and
11748 the high order N bits of FOO (N+1 if an inequality comparison)
11749 are known to be zero, we can do this by comparing FOO with C
11750 shifted right N bits so long as the low-order N bits of C are
11751 zero. */
11752 if (CONST_INT_P (XEXP (op0, 1))
11753 && INTVAL (XEXP (op0, 1)) >= 0
11754 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11755 < HOST_BITS_PER_WIDE_INT)
11756 && (((unsigned HOST_WIDE_INT) const_op
11757 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11758 - 1)) == 0)
11759 && mode_width <= HOST_BITS_PER_WIDE_INT
11760 && (nonzero_bits (XEXP (op0, 0), mode)
11761 & ~(mask >> (INTVAL (XEXP (op0, 1))
11762 + ! equality_comparison_p))) == 0)
11763 {
11764 /* We must perform a logical shift, not an arithmetic one,
11765 as we want the top N bits of C to be zero. */
11766 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11767
11768 temp >>= INTVAL (XEXP (op0, 1));
11769 op1 = gen_int_mode (temp, mode);
11770 op0 = XEXP (op0, 0);
11771 continue;
11772 }
11773
11774 /* If we are doing a sign bit comparison, it means we are testing
11775 a particular bit. Convert it to the appropriate AND. */
11776 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11777 && mode_width <= HOST_BITS_PER_WIDE_INT)
11778 {
11779 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11780 ((unsigned HOST_WIDE_INT) 1
11781 << (mode_width - 1
11782 - INTVAL (XEXP (op0, 1)))));
11783 code = (code == LT ? NE : EQ);
11784 continue;
11785 }
11786
11787 /* If this an equality comparison with zero and we are shifting
11788 the low bit to the sign bit, we can convert this to an AND of the
11789 low-order bit. */
11790 if (const_op == 0 && equality_comparison_p
11791 && CONST_INT_P (XEXP (op0, 1))
11792 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11793 {
11794 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11795 continue;
11796 }
11797 break;
11798
11799 case ASHIFTRT:
11800 /* If this is an equality comparison with zero, we can do this
11801 as a logical shift, which might be much simpler. */
11802 if (equality_comparison_p && const_op == 0
11803 && CONST_INT_P (XEXP (op0, 1)))
11804 {
11805 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11806 XEXP (op0, 0),
11807 INTVAL (XEXP (op0, 1)));
11808 continue;
11809 }
11810
11811 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11812 do the comparison in a narrower mode. */
11813 if (! unsigned_comparison_p
11814 && CONST_INT_P (XEXP (op0, 1))
11815 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11816 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11817 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11818 MODE_INT, 1)) != BLKmode
11819 && (((unsigned HOST_WIDE_INT) const_op
11820 + (GET_MODE_MASK (tmode) >> 1) + 1)
11821 <= GET_MODE_MASK (tmode)))
11822 {
11823 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11824 continue;
11825 }
11826
11827 /* Likewise if OP0 is a PLUS of a sign extension with a
11828 constant, which is usually represented with the PLUS
11829 between the shifts. */
11830 if (! unsigned_comparison_p
11831 && CONST_INT_P (XEXP (op0, 1))
11832 && GET_CODE (XEXP (op0, 0)) == PLUS
11833 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11834 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11835 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11836 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11837 MODE_INT, 1)) != BLKmode
11838 && (((unsigned HOST_WIDE_INT) const_op
11839 + (GET_MODE_MASK (tmode) >> 1) + 1)
11840 <= GET_MODE_MASK (tmode)))
11841 {
11842 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11843 rtx add_const = XEXP (XEXP (op0, 0), 1);
11844 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11845 add_const, XEXP (op0, 1));
11846
11847 op0 = simplify_gen_binary (PLUS, tmode,
11848 gen_lowpart (tmode, inner),
11849 new_const);
11850 continue;
11851 }
11852
11853 /* ... fall through ... */
11854 case LSHIFTRT:
11855 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11856 the low order N bits of FOO are known to be zero, we can do this
11857 by comparing FOO with C shifted left N bits so long as no
11858 overflow occurs. Even if the low order N bits of FOO aren't known
11859 to be zero, if the comparison is >= or < we can use the same
11860 optimization and for > or <= by setting all the low
11861 order N bits in the comparison constant. */
11862 if (CONST_INT_P (XEXP (op0, 1))
11863 && INTVAL (XEXP (op0, 1)) > 0
11864 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11865 && mode_width <= HOST_BITS_PER_WIDE_INT
11866 && (((unsigned HOST_WIDE_INT) const_op
11867 + (GET_CODE (op0) != LSHIFTRT
11868 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11869 + 1)
11870 : 0))
11871 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11872 {
11873 unsigned HOST_WIDE_INT low_bits
11874 = (nonzero_bits (XEXP (op0, 0), mode)
11875 & (((unsigned HOST_WIDE_INT) 1
11876 << INTVAL (XEXP (op0, 1))) - 1));
11877 if (low_bits == 0 || !equality_comparison_p)
11878 {
11879 /* If the shift was logical, then we must make the condition
11880 unsigned. */
11881 if (GET_CODE (op0) == LSHIFTRT)
11882 code = unsigned_condition (code);
11883
11884 const_op <<= INTVAL (XEXP (op0, 1));
11885 if (low_bits != 0
11886 && (code == GT || code == GTU
11887 || code == LE || code == LEU))
11888 const_op
11889 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11890 op1 = GEN_INT (const_op);
11891 op0 = XEXP (op0, 0);
11892 continue;
11893 }
11894 }
11895
11896 /* If we are using this shift to extract just the sign bit, we
11897 can replace this with an LT or GE comparison. */
11898 if (const_op == 0
11899 && (equality_comparison_p || sign_bit_comparison_p)
11900 && CONST_INT_P (XEXP (op0, 1))
11901 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11902 {
11903 op0 = XEXP (op0, 0);
11904 code = (code == NE || code == GT ? LT : GE);
11905 continue;
11906 }
11907 break;
11908
11909 default:
11910 break;
11911 }
11912
11913 break;
11914 }
11915
11916 /* Now make any compound operations involved in this comparison. Then,
11917 check for an outmost SUBREG on OP0 that is not doing anything or is
11918 paradoxical. The latter transformation must only be performed when
11919 it is known that the "extra" bits will be the same in op0 and op1 or
11920 that they don't matter. There are three cases to consider:
11921
11922 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11923 care bits and we can assume they have any convenient value. So
11924 making the transformation is safe.
11925
11926 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11927 In this case the upper bits of op0 are undefined. We should not make
11928 the simplification in that case as we do not know the contents of
11929 those bits.
11930
11931 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11932 UNKNOWN. In that case we know those bits are zeros or ones. We must
11933 also be sure that they are the same as the upper bits of op1.
11934
11935 We can never remove a SUBREG for a non-equality comparison because
11936 the sign bit is in a different place in the underlying object. */
11937
11938 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11939 op1 = make_compound_operation (op1, SET);
11940
11941 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11942 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11943 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11944 && (code == NE || code == EQ))
11945 {
11946 if (GET_MODE_SIZE (GET_MODE (op0))
11947 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11948 {
11949 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11950 implemented. */
11951 if (REG_P (SUBREG_REG (op0)))
11952 {
11953 op0 = SUBREG_REG (op0);
11954 op1 = gen_lowpart (GET_MODE (op0), op1);
11955 }
11956 }
11957 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11958 <= HOST_BITS_PER_WIDE_INT)
11959 && (nonzero_bits (SUBREG_REG (op0),
11960 GET_MODE (SUBREG_REG (op0)))
11961 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11962 {
11963 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11964
11965 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11966 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11967 op0 = SUBREG_REG (op0), op1 = tem;
11968 }
11969 }
11970
11971 /* We now do the opposite procedure: Some machines don't have compare
11972 insns in all modes. If OP0's mode is an integer mode smaller than a
11973 word and we can't do a compare in that mode, see if there is a larger
11974 mode for which we can do the compare. There are a number of cases in
11975 which we can use the wider mode. */
11976
11977 mode = GET_MODE (op0);
11978 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11979 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11980 && ! have_insn_for (COMPARE, mode))
11981 for (tmode = GET_MODE_WIDER_MODE (mode);
11982 (tmode != VOIDmode
11983 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11984 tmode = GET_MODE_WIDER_MODE (tmode))
11985 if (have_insn_for (COMPARE, tmode))
11986 {
11987 int zero_extended;
11988
11989 /* If this is a test for negative, we can make an explicit
11990 test of the sign bit. Test this first so we can use
11991 a paradoxical subreg to extend OP0. */
11992
11993 if (op1 == const0_rtx && (code == LT || code == GE)
11994 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11995 {
11996 op0 = simplify_gen_binary (AND, tmode,
11997 gen_lowpart (tmode, op0),
11998 GEN_INT ((unsigned HOST_WIDE_INT) 1
11999 << (GET_MODE_BITSIZE (mode)
12000 - 1)));
12001 code = (code == LT) ? NE : EQ;
12002 break;
12003 }
12004
12005 /* If the only nonzero bits in OP0 and OP1 are those in the
12006 narrower mode and this is an equality or unsigned comparison,
12007 we can use the wider mode. Similarly for sign-extended
12008 values, in which case it is true for all comparisons. */
12009 zero_extended = ((code == EQ || code == NE
12010 || code == GEU || code == GTU
12011 || code == LEU || code == LTU)
12012 && (nonzero_bits (op0, tmode)
12013 & ~GET_MODE_MASK (mode)) == 0
12014 && ((CONST_INT_P (op1)
12015 || (nonzero_bits (op1, tmode)
12016 & ~GET_MODE_MASK (mode)) == 0)));
12017
12018 if (zero_extended
12019 || ((num_sign_bit_copies (op0, tmode)
12020 > (unsigned int) (GET_MODE_BITSIZE (tmode)
12021 - GET_MODE_BITSIZE (mode)))
12022 && (num_sign_bit_copies (op1, tmode)
12023 > (unsigned int) (GET_MODE_BITSIZE (tmode)
12024 - GET_MODE_BITSIZE (mode)))))
12025 {
12026 /* If OP0 is an AND and we don't have an AND in MODE either,
12027 make a new AND in the proper mode. */
12028 if (GET_CODE (op0) == AND
12029 && !have_insn_for (AND, mode))
12030 op0 = simplify_gen_binary (AND, tmode,
12031 gen_lowpart (tmode,
12032 XEXP (op0, 0)),
12033 gen_lowpart (tmode,
12034 XEXP (op0, 1)));
12035 else
12036 {
12037 if (zero_extended)
12038 {
12039 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12040 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12041 }
12042 else
12043 {
12044 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12045 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12046 }
12047 break;
12048 }
12049 }
12050 }
12051
12052 #ifdef CANONICALIZE_COMPARISON
12053 /* If this machine only supports a subset of valid comparisons, see if we
12054 can convert an unsupported one into a supported one. */
12055 CANONICALIZE_COMPARISON (code, op0, op1);
12056 #endif
12057
12058 *pop0 = op0;
12059 *pop1 = op1;
12060
12061 return code;
12062 }
12063 \f
12064 /* Utility function for record_value_for_reg. Count number of
12065 rtxs in X. */
12066 static int
12067 count_rtxs (rtx x)
12068 {
12069 enum rtx_code code = GET_CODE (x);
12070 const char *fmt;
12071 int i, j, ret = 1;
12072
12073 if (GET_RTX_CLASS (code) == '2'
12074 || GET_RTX_CLASS (code) == 'c')
12075 {
12076 rtx x0 = XEXP (x, 0);
12077 rtx x1 = XEXP (x, 1);
12078
12079 if (x0 == x1)
12080 return 1 + 2 * count_rtxs (x0);
12081
12082 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12083 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12084 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12085 return 2 + 2 * count_rtxs (x0)
12086 + count_rtxs (x == XEXP (x1, 0)
12087 ? XEXP (x1, 1) : XEXP (x1, 0));
12088
12089 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12090 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12091 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12092 return 2 + 2 * count_rtxs (x1)
12093 + count_rtxs (x == XEXP (x0, 0)
12094 ? XEXP (x0, 1) : XEXP (x0, 0));
12095 }
12096
12097 fmt = GET_RTX_FORMAT (code);
12098 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12099 if (fmt[i] == 'e')
12100 ret += count_rtxs (XEXP (x, i));
12101 else if (fmt[i] == 'E')
12102 for (j = 0; j < XVECLEN (x, i); j++)
12103 ret += count_rtxs (XVECEXP (x, i, j));
12104
12105 return ret;
12106 }
12107 \f
12108 /* Utility function for following routine. Called when X is part of a value
12109 being stored into last_set_value. Sets last_set_table_tick
12110 for each register mentioned. Similar to mention_regs in cse.c */
12111
12112 static void
12113 update_table_tick (rtx x)
12114 {
12115 enum rtx_code code = GET_CODE (x);
12116 const char *fmt = GET_RTX_FORMAT (code);
12117 int i, j;
12118
12119 if (code == REG)
12120 {
12121 unsigned int regno = REGNO (x);
12122 unsigned int endregno = END_REGNO (x);
12123 unsigned int r;
12124
12125 for (r = regno; r < endregno; r++)
12126 {
12127 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12128 rsp->last_set_table_tick = label_tick;
12129 }
12130
12131 return;
12132 }
12133
12134 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12135 if (fmt[i] == 'e')
12136 {
12137 /* Check for identical subexpressions. If x contains
12138 identical subexpression we only have to traverse one of
12139 them. */
12140 if (i == 0 && ARITHMETIC_P (x))
12141 {
12142 /* Note that at this point x1 has already been
12143 processed. */
12144 rtx x0 = XEXP (x, 0);
12145 rtx x1 = XEXP (x, 1);
12146
12147 /* If x0 and x1 are identical then there is no need to
12148 process x0. */
12149 if (x0 == x1)
12150 break;
12151
12152 /* If x0 is identical to a subexpression of x1 then while
12153 processing x1, x0 has already been processed. Thus we
12154 are done with x. */
12155 if (ARITHMETIC_P (x1)
12156 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12157 break;
12158
12159 /* If x1 is identical to a subexpression of x0 then we
12160 still have to process the rest of x0. */
12161 if (ARITHMETIC_P (x0)
12162 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12163 {
12164 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12165 break;
12166 }
12167 }
12168
12169 update_table_tick (XEXP (x, i));
12170 }
12171 else if (fmt[i] == 'E')
12172 for (j = 0; j < XVECLEN (x, i); j++)
12173 update_table_tick (XVECEXP (x, i, j));
12174 }
12175
12176 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12177 are saying that the register is clobbered and we no longer know its
12178 value. If INSN is zero, don't update reg_stat[].last_set; this is
12179 only permitted with VALUE also zero and is used to invalidate the
12180 register. */
12181
12182 static void
12183 record_value_for_reg (rtx reg, rtx insn, rtx value)
12184 {
12185 unsigned int regno = REGNO (reg);
12186 unsigned int endregno = END_REGNO (reg);
12187 unsigned int i;
12188 reg_stat_type *rsp;
12189
12190 /* If VALUE contains REG and we have a previous value for REG, substitute
12191 the previous value. */
12192 if (value && insn && reg_overlap_mentioned_p (reg, value))
12193 {
12194 rtx tem;
12195
12196 /* Set things up so get_last_value is allowed to see anything set up to
12197 our insn. */
12198 subst_low_luid = DF_INSN_LUID (insn);
12199 tem = get_last_value (reg);
12200
12201 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12202 it isn't going to be useful and will take a lot of time to process,
12203 so just use the CLOBBER. */
12204
12205 if (tem)
12206 {
12207 if (ARITHMETIC_P (tem)
12208 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12209 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12210 tem = XEXP (tem, 0);
12211 else if (count_occurrences (value, reg, 1) >= 2)
12212 {
12213 /* If there are two or more occurrences of REG in VALUE,
12214 prevent the value from growing too much. */
12215 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12216 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12217 }
12218
12219 value = replace_rtx (copy_rtx (value), reg, tem);
12220 }
12221 }
12222
12223 /* For each register modified, show we don't know its value, that
12224 we don't know about its bitwise content, that its value has been
12225 updated, and that we don't know the location of the death of the
12226 register. */
12227 for (i = regno; i < endregno; i++)
12228 {
12229 rsp = VEC_index (reg_stat_type, reg_stat, i);
12230
12231 if (insn)
12232 rsp->last_set = insn;
12233
12234 rsp->last_set_value = 0;
12235 rsp->last_set_mode = VOIDmode;
12236 rsp->last_set_nonzero_bits = 0;
12237 rsp->last_set_sign_bit_copies = 0;
12238 rsp->last_death = 0;
12239 rsp->truncated_to_mode = VOIDmode;
12240 }
12241
12242 /* Mark registers that are being referenced in this value. */
12243 if (value)
12244 update_table_tick (value);
12245
12246 /* Now update the status of each register being set.
12247 If someone is using this register in this block, set this register
12248 to invalid since we will get confused between the two lives in this
12249 basic block. This makes using this register always invalid. In cse, we
12250 scan the table to invalidate all entries using this register, but this
12251 is too much work for us. */
12252
12253 for (i = regno; i < endregno; i++)
12254 {
12255 rsp = VEC_index (reg_stat_type, reg_stat, i);
12256 rsp->last_set_label = label_tick;
12257 if (!insn
12258 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12259 rsp->last_set_invalid = 1;
12260 else
12261 rsp->last_set_invalid = 0;
12262 }
12263
12264 /* The value being assigned might refer to X (like in "x++;"). In that
12265 case, we must replace it with (clobber (const_int 0)) to prevent
12266 infinite loops. */
12267 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12268 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12269 {
12270 value = copy_rtx (value);
12271 if (!get_last_value_validate (&value, insn, label_tick, 1))
12272 value = 0;
12273 }
12274
12275 /* For the main register being modified, update the value, the mode, the
12276 nonzero bits, and the number of sign bit copies. */
12277
12278 rsp->last_set_value = value;
12279
12280 if (value)
12281 {
12282 enum machine_mode mode = GET_MODE (reg);
12283 subst_low_luid = DF_INSN_LUID (insn);
12284 rsp->last_set_mode = mode;
12285 if (GET_MODE_CLASS (mode) == MODE_INT
12286 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12287 mode = nonzero_bits_mode;
12288 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12289 rsp->last_set_sign_bit_copies
12290 = num_sign_bit_copies (value, GET_MODE (reg));
12291 }
12292 }
12293
12294 /* Called via note_stores from record_dead_and_set_regs to handle one
12295 SET or CLOBBER in an insn. DATA is the instruction in which the
12296 set is occurring. */
12297
12298 static void
12299 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12300 {
12301 rtx record_dead_insn = (rtx) data;
12302
12303 if (GET_CODE (dest) == SUBREG)
12304 dest = SUBREG_REG (dest);
12305
12306 if (!record_dead_insn)
12307 {
12308 if (REG_P (dest))
12309 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12310 return;
12311 }
12312
12313 if (REG_P (dest))
12314 {
12315 /* If we are setting the whole register, we know its value. Otherwise
12316 show that we don't know the value. We can handle SUBREG in
12317 some cases. */
12318 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12319 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12320 else if (GET_CODE (setter) == SET
12321 && GET_CODE (SET_DEST (setter)) == SUBREG
12322 && SUBREG_REG (SET_DEST (setter)) == dest
12323 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
12324 && subreg_lowpart_p (SET_DEST (setter)))
12325 record_value_for_reg (dest, record_dead_insn,
12326 gen_lowpart (GET_MODE (dest),
12327 SET_SRC (setter)));
12328 else
12329 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12330 }
12331 else if (MEM_P (dest)
12332 /* Ignore pushes, they clobber nothing. */
12333 && ! push_operand (dest, GET_MODE (dest)))
12334 mem_last_set = DF_INSN_LUID (record_dead_insn);
12335 }
12336
12337 /* Update the records of when each REG was most recently set or killed
12338 for the things done by INSN. This is the last thing done in processing
12339 INSN in the combiner loop.
12340
12341 We update reg_stat[], in particular fields last_set, last_set_value,
12342 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12343 last_death, and also the similar information mem_last_set (which insn
12344 most recently modified memory) and last_call_luid (which insn was the
12345 most recent subroutine call). */
12346
12347 static void
12348 record_dead_and_set_regs (rtx insn)
12349 {
12350 rtx link;
12351 unsigned int i;
12352
12353 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12354 {
12355 if (REG_NOTE_KIND (link) == REG_DEAD
12356 && REG_P (XEXP (link, 0)))
12357 {
12358 unsigned int regno = REGNO (XEXP (link, 0));
12359 unsigned int endregno = END_REGNO (XEXP (link, 0));
12360
12361 for (i = regno; i < endregno; i++)
12362 {
12363 reg_stat_type *rsp;
12364
12365 rsp = VEC_index (reg_stat_type, reg_stat, i);
12366 rsp->last_death = insn;
12367 }
12368 }
12369 else if (REG_NOTE_KIND (link) == REG_INC)
12370 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12371 }
12372
12373 if (CALL_P (insn))
12374 {
12375 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12376 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12377 {
12378 reg_stat_type *rsp;
12379
12380 rsp = VEC_index (reg_stat_type, reg_stat, i);
12381 rsp->last_set_invalid = 1;
12382 rsp->last_set = insn;
12383 rsp->last_set_value = 0;
12384 rsp->last_set_mode = VOIDmode;
12385 rsp->last_set_nonzero_bits = 0;
12386 rsp->last_set_sign_bit_copies = 0;
12387 rsp->last_death = 0;
12388 rsp->truncated_to_mode = VOIDmode;
12389 }
12390
12391 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12392
12393 /* We can't combine into a call pattern. Remember, though, that
12394 the return value register is set at this LUID. We could
12395 still replace a register with the return value from the
12396 wrong subroutine call! */
12397 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12398 }
12399 else
12400 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12401 }
12402
12403 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12404 register present in the SUBREG, so for each such SUBREG go back and
12405 adjust nonzero and sign bit information of the registers that are
12406 known to have some zero/sign bits set.
12407
12408 This is needed because when combine blows the SUBREGs away, the
12409 information on zero/sign bits is lost and further combines can be
12410 missed because of that. */
12411
12412 static void
12413 record_promoted_value (rtx insn, rtx subreg)
12414 {
12415 struct insn_link *links;
12416 rtx set;
12417 unsigned int regno = REGNO (SUBREG_REG (subreg));
12418 enum machine_mode mode = GET_MODE (subreg);
12419
12420 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
12421 return;
12422
12423 for (links = LOG_LINKS (insn); links;)
12424 {
12425 reg_stat_type *rsp;
12426
12427 insn = links->insn;
12428 set = single_set (insn);
12429
12430 if (! set || !REG_P (SET_DEST (set))
12431 || REGNO (SET_DEST (set)) != regno
12432 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12433 {
12434 links = links->next;
12435 continue;
12436 }
12437
12438 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12439 if (rsp->last_set == insn)
12440 {
12441 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12442 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12443 }
12444
12445 if (REG_P (SET_SRC (set)))
12446 {
12447 regno = REGNO (SET_SRC (set));
12448 links = LOG_LINKS (insn);
12449 }
12450 else
12451 break;
12452 }
12453 }
12454
12455 /* Check if X, a register, is known to contain a value already
12456 truncated to MODE. In this case we can use a subreg to refer to
12457 the truncated value even though in the generic case we would need
12458 an explicit truncation. */
12459
12460 static bool
12461 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12462 {
12463 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12464 enum machine_mode truncated = rsp->truncated_to_mode;
12465
12466 if (truncated == 0
12467 || rsp->truncation_label < label_tick_ebb_start)
12468 return false;
12469 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12470 return true;
12471 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12472 GET_MODE_BITSIZE (truncated)))
12473 return true;
12474 return false;
12475 }
12476
12477 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12478 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12479 might be able to turn a truncate into a subreg using this information.
12480 Return -1 if traversing *P is complete or 0 otherwise. */
12481
12482 static int
12483 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12484 {
12485 rtx x = *p;
12486 enum machine_mode truncated_mode;
12487 reg_stat_type *rsp;
12488
12489 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12490 {
12491 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12492 truncated_mode = GET_MODE (x);
12493
12494 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12495 return -1;
12496
12497 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12498 GET_MODE_BITSIZE (original_mode)))
12499 return -1;
12500
12501 x = SUBREG_REG (x);
12502 }
12503 /* ??? For hard-regs we now record everything. We might be able to
12504 optimize this using last_set_mode. */
12505 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12506 truncated_mode = GET_MODE (x);
12507 else
12508 return 0;
12509
12510 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12511 if (rsp->truncated_to_mode == 0
12512 || rsp->truncation_label < label_tick_ebb_start
12513 || (GET_MODE_SIZE (truncated_mode)
12514 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12515 {
12516 rsp->truncated_to_mode = truncated_mode;
12517 rsp->truncation_label = label_tick;
12518 }
12519
12520 return -1;
12521 }
12522
12523 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12524 the modes they are used in. This can help truning TRUNCATEs into
12525 SUBREGs. */
12526
12527 static void
12528 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12529 {
12530 for_each_rtx (x, record_truncated_value, NULL);
12531 }
12532
12533 /* Scan X for promoted SUBREGs. For each one found,
12534 note what it implies to the registers used in it. */
12535
12536 static void
12537 check_promoted_subreg (rtx insn, rtx x)
12538 {
12539 if (GET_CODE (x) == SUBREG
12540 && SUBREG_PROMOTED_VAR_P (x)
12541 && REG_P (SUBREG_REG (x)))
12542 record_promoted_value (insn, x);
12543 else
12544 {
12545 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12546 int i, j;
12547
12548 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12549 switch (format[i])
12550 {
12551 case 'e':
12552 check_promoted_subreg (insn, XEXP (x, i));
12553 break;
12554 case 'V':
12555 case 'E':
12556 if (XVEC (x, i) != 0)
12557 for (j = 0; j < XVECLEN (x, i); j++)
12558 check_promoted_subreg (insn, XVECEXP (x, i, j));
12559 break;
12560 }
12561 }
12562 }
12563 \f
12564 /* Verify that all the registers and memory references mentioned in *LOC are
12565 still valid. *LOC was part of a value set in INSN when label_tick was
12566 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12567 the invalid references with (clobber (const_int 0)) and return 1. This
12568 replacement is useful because we often can get useful information about
12569 the form of a value (e.g., if it was produced by a shift that always
12570 produces -1 or 0) even though we don't know exactly what registers it
12571 was produced from. */
12572
12573 static int
12574 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12575 {
12576 rtx x = *loc;
12577 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12578 int len = GET_RTX_LENGTH (GET_CODE (x));
12579 int i, j;
12580
12581 if (REG_P (x))
12582 {
12583 unsigned int regno = REGNO (x);
12584 unsigned int endregno = END_REGNO (x);
12585 unsigned int j;
12586
12587 for (j = regno; j < endregno; j++)
12588 {
12589 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12590 if (rsp->last_set_invalid
12591 /* If this is a pseudo-register that was only set once and not
12592 live at the beginning of the function, it is always valid. */
12593 || (! (regno >= FIRST_PSEUDO_REGISTER
12594 && REG_N_SETS (regno) == 1
12595 && (!REGNO_REG_SET_P
12596 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12597 && rsp->last_set_label > tick))
12598 {
12599 if (replace)
12600 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12601 return replace;
12602 }
12603 }
12604
12605 return 1;
12606 }
12607 /* If this is a memory reference, make sure that there were no stores after
12608 it that might have clobbered the value. We don't have alias info, so we
12609 assume any store invalidates it. Moreover, we only have local UIDs, so
12610 we also assume that there were stores in the intervening basic blocks. */
12611 else if (MEM_P (x) && !MEM_READONLY_P (x)
12612 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12613 {
12614 if (replace)
12615 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12616 return replace;
12617 }
12618
12619 for (i = 0; i < len; i++)
12620 {
12621 if (fmt[i] == 'e')
12622 {
12623 /* Check for identical subexpressions. If x contains
12624 identical subexpression we only have to traverse one of
12625 them. */
12626 if (i == 1 && ARITHMETIC_P (x))
12627 {
12628 /* Note that at this point x0 has already been checked
12629 and found valid. */
12630 rtx x0 = XEXP (x, 0);
12631 rtx x1 = XEXP (x, 1);
12632
12633 /* If x0 and x1 are identical then x is also valid. */
12634 if (x0 == x1)
12635 return 1;
12636
12637 /* If x1 is identical to a subexpression of x0 then
12638 while checking x0, x1 has already been checked. Thus
12639 it is valid and so as x. */
12640 if (ARITHMETIC_P (x0)
12641 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12642 return 1;
12643
12644 /* If x0 is identical to a subexpression of x1 then x is
12645 valid iff the rest of x1 is valid. */
12646 if (ARITHMETIC_P (x1)
12647 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12648 return
12649 get_last_value_validate (&XEXP (x1,
12650 x0 == XEXP (x1, 0) ? 1 : 0),
12651 insn, tick, replace);
12652 }
12653
12654 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12655 replace) == 0)
12656 return 0;
12657 }
12658 else if (fmt[i] == 'E')
12659 for (j = 0; j < XVECLEN (x, i); j++)
12660 if (get_last_value_validate (&XVECEXP (x, i, j),
12661 insn, tick, replace) == 0)
12662 return 0;
12663 }
12664
12665 /* If we haven't found a reason for it to be invalid, it is valid. */
12666 return 1;
12667 }
12668
12669 /* Get the last value assigned to X, if known. Some registers
12670 in the value may be replaced with (clobber (const_int 0)) if their value
12671 is known longer known reliably. */
12672
12673 static rtx
12674 get_last_value (const_rtx x)
12675 {
12676 unsigned int regno;
12677 rtx value;
12678 reg_stat_type *rsp;
12679
12680 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12681 then convert it to the desired mode. If this is a paradoxical SUBREG,
12682 we cannot predict what values the "extra" bits might have. */
12683 if (GET_CODE (x) == SUBREG
12684 && subreg_lowpart_p (x)
12685 && (GET_MODE_SIZE (GET_MODE (x))
12686 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12687 && (value = get_last_value (SUBREG_REG (x))) != 0)
12688 return gen_lowpart (GET_MODE (x), value);
12689
12690 if (!REG_P (x))
12691 return 0;
12692
12693 regno = REGNO (x);
12694 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12695 value = rsp->last_set_value;
12696
12697 /* If we don't have a value, or if it isn't for this basic block and
12698 it's either a hard register, set more than once, or it's a live
12699 at the beginning of the function, return 0.
12700
12701 Because if it's not live at the beginning of the function then the reg
12702 is always set before being used (is never used without being set).
12703 And, if it's set only once, and it's always set before use, then all
12704 uses must have the same last value, even if it's not from this basic
12705 block. */
12706
12707 if (value == 0
12708 || (rsp->last_set_label < label_tick_ebb_start
12709 && (regno < FIRST_PSEUDO_REGISTER
12710 || REG_N_SETS (regno) != 1
12711 || REGNO_REG_SET_P
12712 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12713 return 0;
12714
12715 /* If the value was set in a later insn than the ones we are processing,
12716 we can't use it even if the register was only set once. */
12717 if (rsp->last_set_label == label_tick
12718 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12719 return 0;
12720
12721 /* If the value has all its registers valid, return it. */
12722 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12723 return value;
12724
12725 /* Otherwise, make a copy and replace any invalid register with
12726 (clobber (const_int 0)). If that fails for some reason, return 0. */
12727
12728 value = copy_rtx (value);
12729 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12730 return value;
12731
12732 return 0;
12733 }
12734 \f
12735 /* Return nonzero if expression X refers to a REG or to memory
12736 that is set in an instruction more recent than FROM_LUID. */
12737
12738 static int
12739 use_crosses_set_p (const_rtx x, int from_luid)
12740 {
12741 const char *fmt;
12742 int i;
12743 enum rtx_code code = GET_CODE (x);
12744
12745 if (code == REG)
12746 {
12747 unsigned int regno = REGNO (x);
12748 unsigned endreg = END_REGNO (x);
12749
12750 #ifdef PUSH_ROUNDING
12751 /* Don't allow uses of the stack pointer to be moved,
12752 because we don't know whether the move crosses a push insn. */
12753 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12754 return 1;
12755 #endif
12756 for (; regno < endreg; regno++)
12757 {
12758 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12759 if (rsp->last_set
12760 && rsp->last_set_label == label_tick
12761 && DF_INSN_LUID (rsp->last_set) > from_luid)
12762 return 1;
12763 }
12764 return 0;
12765 }
12766
12767 if (code == MEM && mem_last_set > from_luid)
12768 return 1;
12769
12770 fmt = GET_RTX_FORMAT (code);
12771
12772 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12773 {
12774 if (fmt[i] == 'E')
12775 {
12776 int j;
12777 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12778 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12779 return 1;
12780 }
12781 else if (fmt[i] == 'e'
12782 && use_crosses_set_p (XEXP (x, i), from_luid))
12783 return 1;
12784 }
12785 return 0;
12786 }
12787 \f
12788 /* Define three variables used for communication between the following
12789 routines. */
12790
12791 static unsigned int reg_dead_regno, reg_dead_endregno;
12792 static int reg_dead_flag;
12793
12794 /* Function called via note_stores from reg_dead_at_p.
12795
12796 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12797 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12798
12799 static void
12800 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12801 {
12802 unsigned int regno, endregno;
12803
12804 if (!REG_P (dest))
12805 return;
12806
12807 regno = REGNO (dest);
12808 endregno = END_REGNO (dest);
12809 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12810 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12811 }
12812
12813 /* Return nonzero if REG is known to be dead at INSN.
12814
12815 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12816 referencing REG, it is dead. If we hit a SET referencing REG, it is
12817 live. Otherwise, see if it is live or dead at the start of the basic
12818 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12819 must be assumed to be always live. */
12820
12821 static int
12822 reg_dead_at_p (rtx reg, rtx insn)
12823 {
12824 basic_block block;
12825 unsigned int i;
12826
12827 /* Set variables for reg_dead_at_p_1. */
12828 reg_dead_regno = REGNO (reg);
12829 reg_dead_endregno = END_REGNO (reg);
12830
12831 reg_dead_flag = 0;
12832
12833 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12834 we allow the machine description to decide whether use-and-clobber
12835 patterns are OK. */
12836 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12837 {
12838 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12839 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12840 return 0;
12841 }
12842
12843 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12844 beginning of basic block. */
12845 block = BLOCK_FOR_INSN (insn);
12846 for (;;)
12847 {
12848 if (INSN_P (insn))
12849 {
12850 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12851 if (reg_dead_flag)
12852 return reg_dead_flag == 1 ? 1 : 0;
12853
12854 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12855 return 1;
12856 }
12857
12858 if (insn == BB_HEAD (block))
12859 break;
12860
12861 insn = PREV_INSN (insn);
12862 }
12863
12864 /* Look at live-in sets for the basic block that we were in. */
12865 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12866 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12867 return 0;
12868
12869 return 1;
12870 }
12871 \f
12872 /* Note hard registers in X that are used. */
12873
12874 static void
12875 mark_used_regs_combine (rtx x)
12876 {
12877 RTX_CODE code = GET_CODE (x);
12878 unsigned int regno;
12879 int i;
12880
12881 switch (code)
12882 {
12883 case LABEL_REF:
12884 case SYMBOL_REF:
12885 case CONST_INT:
12886 case CONST:
12887 case CONST_DOUBLE:
12888 case CONST_VECTOR:
12889 case PC:
12890 case ADDR_VEC:
12891 case ADDR_DIFF_VEC:
12892 case ASM_INPUT:
12893 #ifdef HAVE_cc0
12894 /* CC0 must die in the insn after it is set, so we don't need to take
12895 special note of it here. */
12896 case CC0:
12897 #endif
12898 return;
12899
12900 case CLOBBER:
12901 /* If we are clobbering a MEM, mark any hard registers inside the
12902 address as used. */
12903 if (MEM_P (XEXP (x, 0)))
12904 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12905 return;
12906
12907 case REG:
12908 regno = REGNO (x);
12909 /* A hard reg in a wide mode may really be multiple registers.
12910 If so, mark all of them just like the first. */
12911 if (regno < FIRST_PSEUDO_REGISTER)
12912 {
12913 /* None of this applies to the stack, frame or arg pointers. */
12914 if (regno == STACK_POINTER_REGNUM
12915 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12916 || regno == HARD_FRAME_POINTER_REGNUM
12917 #endif
12918 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12919 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12920 #endif
12921 || regno == FRAME_POINTER_REGNUM)
12922 return;
12923
12924 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12925 }
12926 return;
12927
12928 case SET:
12929 {
12930 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12931 the address. */
12932 rtx testreg = SET_DEST (x);
12933
12934 while (GET_CODE (testreg) == SUBREG
12935 || GET_CODE (testreg) == ZERO_EXTRACT
12936 || GET_CODE (testreg) == STRICT_LOW_PART)
12937 testreg = XEXP (testreg, 0);
12938
12939 if (MEM_P (testreg))
12940 mark_used_regs_combine (XEXP (testreg, 0));
12941
12942 mark_used_regs_combine (SET_SRC (x));
12943 }
12944 return;
12945
12946 default:
12947 break;
12948 }
12949
12950 /* Recursively scan the operands of this expression. */
12951
12952 {
12953 const char *fmt = GET_RTX_FORMAT (code);
12954
12955 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12956 {
12957 if (fmt[i] == 'e')
12958 mark_used_regs_combine (XEXP (x, i));
12959 else if (fmt[i] == 'E')
12960 {
12961 int j;
12962
12963 for (j = 0; j < XVECLEN (x, i); j++)
12964 mark_used_regs_combine (XVECEXP (x, i, j));
12965 }
12966 }
12967 }
12968 }
12969 \f
12970 /* Remove register number REGNO from the dead registers list of INSN.
12971
12972 Return the note used to record the death, if there was one. */
12973
12974 rtx
12975 remove_death (unsigned int regno, rtx insn)
12976 {
12977 rtx note = find_regno_note (insn, REG_DEAD, regno);
12978
12979 if (note)
12980 remove_note (insn, note);
12981
12982 return note;
12983 }
12984
12985 /* For each register (hardware or pseudo) used within expression X, if its
12986 death is in an instruction with luid between FROM_LUID (inclusive) and
12987 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12988 list headed by PNOTES.
12989
12990 That said, don't move registers killed by maybe_kill_insn.
12991
12992 This is done when X is being merged by combination into TO_INSN. These
12993 notes will then be distributed as needed. */
12994
12995 static void
12996 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12997 rtx *pnotes)
12998 {
12999 const char *fmt;
13000 int len, i;
13001 enum rtx_code code = GET_CODE (x);
13002
13003 if (code == REG)
13004 {
13005 unsigned int regno = REGNO (x);
13006 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
13007
13008 /* Don't move the register if it gets killed in between from and to. */
13009 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13010 && ! reg_referenced_p (x, maybe_kill_insn))
13011 return;
13012
13013 if (where_dead
13014 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13015 && DF_INSN_LUID (where_dead) >= from_luid
13016 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13017 {
13018 rtx note = remove_death (regno, where_dead);
13019
13020 /* It is possible for the call above to return 0. This can occur
13021 when last_death points to I2 or I1 that we combined with.
13022 In that case make a new note.
13023
13024 We must also check for the case where X is a hard register
13025 and NOTE is a death note for a range of hard registers
13026 including X. In that case, we must put REG_DEAD notes for
13027 the remaining registers in place of NOTE. */
13028
13029 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13030 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13031 > GET_MODE_SIZE (GET_MODE (x))))
13032 {
13033 unsigned int deadregno = REGNO (XEXP (note, 0));
13034 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13035 unsigned int ourend = END_HARD_REGNO (x);
13036 unsigned int i;
13037
13038 for (i = deadregno; i < deadend; i++)
13039 if (i < regno || i >= ourend)
13040 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13041 }
13042
13043 /* If we didn't find any note, or if we found a REG_DEAD note that
13044 covers only part of the given reg, and we have a multi-reg hard
13045 register, then to be safe we must check for REG_DEAD notes
13046 for each register other than the first. They could have
13047 their own REG_DEAD notes lying around. */
13048 else if ((note == 0
13049 || (note != 0
13050 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13051 < GET_MODE_SIZE (GET_MODE (x)))))
13052 && regno < FIRST_PSEUDO_REGISTER
13053 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13054 {
13055 unsigned int ourend = END_HARD_REGNO (x);
13056 unsigned int i, offset;
13057 rtx oldnotes = 0;
13058
13059 if (note)
13060 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13061 else
13062 offset = 1;
13063
13064 for (i = regno + offset; i < ourend; i++)
13065 move_deaths (regno_reg_rtx[i],
13066 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13067 }
13068
13069 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13070 {
13071 XEXP (note, 1) = *pnotes;
13072 *pnotes = note;
13073 }
13074 else
13075 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13076 }
13077
13078 return;
13079 }
13080
13081 else if (GET_CODE (x) == SET)
13082 {
13083 rtx dest = SET_DEST (x);
13084
13085 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13086
13087 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13088 that accesses one word of a multi-word item, some
13089 piece of everything register in the expression is used by
13090 this insn, so remove any old death. */
13091 /* ??? So why do we test for equality of the sizes? */
13092
13093 if (GET_CODE (dest) == ZERO_EXTRACT
13094 || GET_CODE (dest) == STRICT_LOW_PART
13095 || (GET_CODE (dest) == SUBREG
13096 && (((GET_MODE_SIZE (GET_MODE (dest))
13097 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13098 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13099 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13100 {
13101 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13102 return;
13103 }
13104
13105 /* If this is some other SUBREG, we know it replaces the entire
13106 value, so use that as the destination. */
13107 if (GET_CODE (dest) == SUBREG)
13108 dest = SUBREG_REG (dest);
13109
13110 /* If this is a MEM, adjust deaths of anything used in the address.
13111 For a REG (the only other possibility), the entire value is
13112 being replaced so the old value is not used in this insn. */
13113
13114 if (MEM_P (dest))
13115 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13116 to_insn, pnotes);
13117 return;
13118 }
13119
13120 else if (GET_CODE (x) == CLOBBER)
13121 return;
13122
13123 len = GET_RTX_LENGTH (code);
13124 fmt = GET_RTX_FORMAT (code);
13125
13126 for (i = 0; i < len; i++)
13127 {
13128 if (fmt[i] == 'E')
13129 {
13130 int j;
13131 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13132 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13133 to_insn, pnotes);
13134 }
13135 else if (fmt[i] == 'e')
13136 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13137 }
13138 }
13139 \f
13140 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13141 pattern of an insn. X must be a REG. */
13142
13143 static int
13144 reg_bitfield_target_p (rtx x, rtx body)
13145 {
13146 int i;
13147
13148 if (GET_CODE (body) == SET)
13149 {
13150 rtx dest = SET_DEST (body);
13151 rtx target;
13152 unsigned int regno, tregno, endregno, endtregno;
13153
13154 if (GET_CODE (dest) == ZERO_EXTRACT)
13155 target = XEXP (dest, 0);
13156 else if (GET_CODE (dest) == STRICT_LOW_PART)
13157 target = SUBREG_REG (XEXP (dest, 0));
13158 else
13159 return 0;
13160
13161 if (GET_CODE (target) == SUBREG)
13162 target = SUBREG_REG (target);
13163
13164 if (!REG_P (target))
13165 return 0;
13166
13167 tregno = REGNO (target), regno = REGNO (x);
13168 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13169 return target == x;
13170
13171 endtregno = end_hard_regno (GET_MODE (target), tregno);
13172 endregno = end_hard_regno (GET_MODE (x), regno);
13173
13174 return endregno > tregno && regno < endtregno;
13175 }
13176
13177 else if (GET_CODE (body) == PARALLEL)
13178 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13179 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13180 return 1;
13181
13182 return 0;
13183 }
13184 \f
13185 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13186 as appropriate. I3 and I2 are the insns resulting from the combination
13187 insns including FROM (I2 may be zero).
13188
13189 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13190 not need REG_DEAD notes because they are being substituted for. This
13191 saves searching in the most common cases.
13192
13193 Each note in the list is either ignored or placed on some insns, depending
13194 on the type of note. */
13195
13196 static void
13197 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13198 rtx elim_i1, rtx elim_i0)
13199 {
13200 rtx note, next_note;
13201 rtx tem;
13202
13203 for (note = notes; note; note = next_note)
13204 {
13205 rtx place = 0, place2 = 0;
13206
13207 next_note = XEXP (note, 1);
13208 switch (REG_NOTE_KIND (note))
13209 {
13210 case REG_BR_PROB:
13211 case REG_BR_PRED:
13212 /* Doesn't matter much where we put this, as long as it's somewhere.
13213 It is preferable to keep these notes on branches, which is most
13214 likely to be i3. */
13215 place = i3;
13216 break;
13217
13218 case REG_NON_LOCAL_GOTO:
13219 if (JUMP_P (i3))
13220 place = i3;
13221 else
13222 {
13223 gcc_assert (i2 && JUMP_P (i2));
13224 place = i2;
13225 }
13226 break;
13227
13228 case REG_EH_REGION:
13229 /* These notes must remain with the call or trapping instruction. */
13230 if (CALL_P (i3))
13231 place = i3;
13232 else if (i2 && CALL_P (i2))
13233 place = i2;
13234 else
13235 {
13236 gcc_assert (cfun->can_throw_non_call_exceptions);
13237 if (may_trap_p (i3))
13238 place = i3;
13239 else if (i2 && may_trap_p (i2))
13240 place = i2;
13241 /* ??? Otherwise assume we've combined things such that we
13242 can now prove that the instructions can't trap. Drop the
13243 note in this case. */
13244 }
13245 break;
13246
13247 case REG_NORETURN:
13248 case REG_SETJMP:
13249 /* These notes must remain with the call. It should not be
13250 possible for both I2 and I3 to be a call. */
13251 if (CALL_P (i3))
13252 place = i3;
13253 else
13254 {
13255 gcc_assert (i2 && CALL_P (i2));
13256 place = i2;
13257 }
13258 break;
13259
13260 case REG_UNUSED:
13261 /* Any clobbers for i3 may still exist, and so we must process
13262 REG_UNUSED notes from that insn.
13263
13264 Any clobbers from i2 or i1 can only exist if they were added by
13265 recog_for_combine. In that case, recog_for_combine created the
13266 necessary REG_UNUSED notes. Trying to keep any original
13267 REG_UNUSED notes from these insns can cause incorrect output
13268 if it is for the same register as the original i3 dest.
13269 In that case, we will notice that the register is set in i3,
13270 and then add a REG_UNUSED note for the destination of i3, which
13271 is wrong. However, it is possible to have REG_UNUSED notes from
13272 i2 or i1 for register which were both used and clobbered, so
13273 we keep notes from i2 or i1 if they will turn into REG_DEAD
13274 notes. */
13275
13276 /* If this register is set or clobbered in I3, put the note there
13277 unless there is one already. */
13278 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13279 {
13280 if (from_insn != i3)
13281 break;
13282
13283 if (! (REG_P (XEXP (note, 0))
13284 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13285 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13286 place = i3;
13287 }
13288 /* Otherwise, if this register is used by I3, then this register
13289 now dies here, so we must put a REG_DEAD note here unless there
13290 is one already. */
13291 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13292 && ! (REG_P (XEXP (note, 0))
13293 ? find_regno_note (i3, REG_DEAD,
13294 REGNO (XEXP (note, 0)))
13295 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13296 {
13297 PUT_REG_NOTE_KIND (note, REG_DEAD);
13298 place = i3;
13299 }
13300 break;
13301
13302 case REG_EQUAL:
13303 case REG_EQUIV:
13304 case REG_NOALIAS:
13305 /* These notes say something about results of an insn. We can
13306 only support them if they used to be on I3 in which case they
13307 remain on I3. Otherwise they are ignored.
13308
13309 If the note refers to an expression that is not a constant, we
13310 must also ignore the note since we cannot tell whether the
13311 equivalence is still true. It might be possible to do
13312 slightly better than this (we only have a problem if I2DEST
13313 or I1DEST is present in the expression), but it doesn't
13314 seem worth the trouble. */
13315
13316 if (from_insn == i3
13317 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13318 place = i3;
13319 break;
13320
13321 case REG_INC:
13322 /* These notes say something about how a register is used. They must
13323 be present on any use of the register in I2 or I3. */
13324 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13325 place = i3;
13326
13327 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13328 {
13329 if (place)
13330 place2 = i2;
13331 else
13332 place = i2;
13333 }
13334 break;
13335
13336 case REG_LABEL_TARGET:
13337 case REG_LABEL_OPERAND:
13338 /* This can show up in several ways -- either directly in the
13339 pattern, or hidden off in the constant pool with (or without?)
13340 a REG_EQUAL note. */
13341 /* ??? Ignore the without-reg_equal-note problem for now. */
13342 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13343 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13344 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13345 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13346 place = i3;
13347
13348 if (i2
13349 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13350 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13351 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13352 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13353 {
13354 if (place)
13355 place2 = i2;
13356 else
13357 place = i2;
13358 }
13359
13360 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13361 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13362 there. */
13363 if (place && JUMP_P (place)
13364 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13365 && (JUMP_LABEL (place) == NULL
13366 || JUMP_LABEL (place) == XEXP (note, 0)))
13367 {
13368 rtx label = JUMP_LABEL (place);
13369
13370 if (!label)
13371 JUMP_LABEL (place) = XEXP (note, 0);
13372 else if (LABEL_P (label))
13373 LABEL_NUSES (label)--;
13374 }
13375
13376 if (place2 && JUMP_P (place2)
13377 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13378 && (JUMP_LABEL (place2) == NULL
13379 || JUMP_LABEL (place2) == XEXP (note, 0)))
13380 {
13381 rtx label = JUMP_LABEL (place2);
13382
13383 if (!label)
13384 JUMP_LABEL (place2) = XEXP (note, 0);
13385 else if (LABEL_P (label))
13386 LABEL_NUSES (label)--;
13387 place2 = 0;
13388 }
13389 break;
13390
13391 case REG_NONNEG:
13392 /* This note says something about the value of a register prior
13393 to the execution of an insn. It is too much trouble to see
13394 if the note is still correct in all situations. It is better
13395 to simply delete it. */
13396 break;
13397
13398 case REG_DEAD:
13399 /* If we replaced the right hand side of FROM_INSN with a
13400 REG_EQUAL note, the original use of the dying register
13401 will not have been combined into I3 and I2. In such cases,
13402 FROM_INSN is guaranteed to be the first of the combined
13403 instructions, so we simply need to search back before
13404 FROM_INSN for the previous use or set of this register,
13405 then alter the notes there appropriately.
13406
13407 If the register is used as an input in I3, it dies there.
13408 Similarly for I2, if it is nonzero and adjacent to I3.
13409
13410 If the register is not used as an input in either I3 or I2
13411 and it is not one of the registers we were supposed to eliminate,
13412 there are two possibilities. We might have a non-adjacent I2
13413 or we might have somehow eliminated an additional register
13414 from a computation. For example, we might have had A & B where
13415 we discover that B will always be zero. In this case we will
13416 eliminate the reference to A.
13417
13418 In both cases, we must search to see if we can find a previous
13419 use of A and put the death note there. */
13420
13421 if (from_insn
13422 && from_insn == i2mod
13423 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13424 tem = from_insn;
13425 else
13426 {
13427 if (from_insn
13428 && CALL_P (from_insn)
13429 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13430 place = from_insn;
13431 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13432 place = i3;
13433 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13434 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13435 place = i2;
13436 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13437 && !(i2mod
13438 && reg_overlap_mentioned_p (XEXP (note, 0),
13439 i2mod_old_rhs)))
13440 || rtx_equal_p (XEXP (note, 0), elim_i1)
13441 || rtx_equal_p (XEXP (note, 0), elim_i0))
13442 break;
13443 tem = i3;
13444 }
13445
13446 if (place == 0)
13447 {
13448 basic_block bb = this_basic_block;
13449
13450 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13451 {
13452 if (!NONDEBUG_INSN_P (tem))
13453 {
13454 if (tem == BB_HEAD (bb))
13455 break;
13456 continue;
13457 }
13458
13459 /* If the register is being set at TEM, see if that is all
13460 TEM is doing. If so, delete TEM. Otherwise, make this
13461 into a REG_UNUSED note instead. Don't delete sets to
13462 global register vars. */
13463 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13464 || !global_regs[REGNO (XEXP (note, 0))])
13465 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13466 {
13467 rtx set = single_set (tem);
13468 rtx inner_dest = 0;
13469 #ifdef HAVE_cc0
13470 rtx cc0_setter = NULL_RTX;
13471 #endif
13472
13473 if (set != 0)
13474 for (inner_dest = SET_DEST (set);
13475 (GET_CODE (inner_dest) == STRICT_LOW_PART
13476 || GET_CODE (inner_dest) == SUBREG
13477 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13478 inner_dest = XEXP (inner_dest, 0))
13479 ;
13480
13481 /* Verify that it was the set, and not a clobber that
13482 modified the register.
13483
13484 CC0 targets must be careful to maintain setter/user
13485 pairs. If we cannot delete the setter due to side
13486 effects, mark the user with an UNUSED note instead
13487 of deleting it. */
13488
13489 if (set != 0 && ! side_effects_p (SET_SRC (set))
13490 && rtx_equal_p (XEXP (note, 0), inner_dest)
13491 #ifdef HAVE_cc0
13492 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13493 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13494 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13495 #endif
13496 )
13497 {
13498 /* Move the notes and links of TEM elsewhere.
13499 This might delete other dead insns recursively.
13500 First set the pattern to something that won't use
13501 any register. */
13502 rtx old_notes = REG_NOTES (tem);
13503
13504 PATTERN (tem) = pc_rtx;
13505 REG_NOTES (tem) = NULL;
13506
13507 distribute_notes (old_notes, tem, tem, NULL_RTX,
13508 NULL_RTX, NULL_RTX, NULL_RTX);
13509 distribute_links (LOG_LINKS (tem));
13510
13511 SET_INSN_DELETED (tem);
13512 if (tem == i2)
13513 i2 = NULL_RTX;
13514
13515 #ifdef HAVE_cc0
13516 /* Delete the setter too. */
13517 if (cc0_setter)
13518 {
13519 PATTERN (cc0_setter) = pc_rtx;
13520 old_notes = REG_NOTES (cc0_setter);
13521 REG_NOTES (cc0_setter) = NULL;
13522
13523 distribute_notes (old_notes, cc0_setter,
13524 cc0_setter, NULL_RTX,
13525 NULL_RTX, NULL_RTX, NULL_RTX);
13526 distribute_links (LOG_LINKS (cc0_setter));
13527
13528 SET_INSN_DELETED (cc0_setter);
13529 if (cc0_setter == i2)
13530 i2 = NULL_RTX;
13531 }
13532 #endif
13533 }
13534 else
13535 {
13536 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13537
13538 /* If there isn't already a REG_UNUSED note, put one
13539 here. Do not place a REG_DEAD note, even if
13540 the register is also used here; that would not
13541 match the algorithm used in lifetime analysis
13542 and can cause the consistency check in the
13543 scheduler to fail. */
13544 if (! find_regno_note (tem, REG_UNUSED,
13545 REGNO (XEXP (note, 0))))
13546 place = tem;
13547 break;
13548 }
13549 }
13550 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13551 || (CALL_P (tem)
13552 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13553 {
13554 place = tem;
13555
13556 /* If we are doing a 3->2 combination, and we have a
13557 register which formerly died in i3 and was not used
13558 by i2, which now no longer dies in i3 and is used in
13559 i2 but does not die in i2, and place is between i2
13560 and i3, then we may need to move a link from place to
13561 i2. */
13562 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13563 && from_insn
13564 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13565 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13566 {
13567 struct insn_link *links = LOG_LINKS (place);
13568 LOG_LINKS (place) = NULL;
13569 distribute_links (links);
13570 }
13571 break;
13572 }
13573
13574 if (tem == BB_HEAD (bb))
13575 break;
13576 }
13577
13578 }
13579
13580 /* If the register is set or already dead at PLACE, we needn't do
13581 anything with this note if it is still a REG_DEAD note.
13582 We check here if it is set at all, not if is it totally replaced,
13583 which is what `dead_or_set_p' checks, so also check for it being
13584 set partially. */
13585
13586 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13587 {
13588 unsigned int regno = REGNO (XEXP (note, 0));
13589 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13590
13591 if (dead_or_set_p (place, XEXP (note, 0))
13592 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13593 {
13594 /* Unless the register previously died in PLACE, clear
13595 last_death. [I no longer understand why this is
13596 being done.] */
13597 if (rsp->last_death != place)
13598 rsp->last_death = 0;
13599 place = 0;
13600 }
13601 else
13602 rsp->last_death = place;
13603
13604 /* If this is a death note for a hard reg that is occupying
13605 multiple registers, ensure that we are still using all
13606 parts of the object. If we find a piece of the object
13607 that is unused, we must arrange for an appropriate REG_DEAD
13608 note to be added for it. However, we can't just emit a USE
13609 and tag the note to it, since the register might actually
13610 be dead; so we recourse, and the recursive call then finds
13611 the previous insn that used this register. */
13612
13613 if (place && regno < FIRST_PSEUDO_REGISTER
13614 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13615 {
13616 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13617 int all_used = 1;
13618 unsigned int i;
13619
13620 for (i = regno; i < endregno; i++)
13621 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13622 && ! find_regno_fusage (place, USE, i))
13623 || dead_or_set_regno_p (place, i))
13624 all_used = 0;
13625
13626 if (! all_used)
13627 {
13628 /* Put only REG_DEAD notes for pieces that are
13629 not already dead or set. */
13630
13631 for (i = regno; i < endregno;
13632 i += hard_regno_nregs[i][reg_raw_mode[i]])
13633 {
13634 rtx piece = regno_reg_rtx[i];
13635 basic_block bb = this_basic_block;
13636
13637 if (! dead_or_set_p (place, piece)
13638 && ! reg_bitfield_target_p (piece,
13639 PATTERN (place)))
13640 {
13641 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13642 NULL_RTX);
13643
13644 distribute_notes (new_note, place, place,
13645 NULL_RTX, NULL_RTX, NULL_RTX,
13646 NULL_RTX);
13647 }
13648 else if (! refers_to_regno_p (i, i + 1,
13649 PATTERN (place), 0)
13650 && ! find_regno_fusage (place, USE, i))
13651 for (tem = PREV_INSN (place); ;
13652 tem = PREV_INSN (tem))
13653 {
13654 if (!NONDEBUG_INSN_P (tem))
13655 {
13656 if (tem == BB_HEAD (bb))
13657 break;
13658 continue;
13659 }
13660 if (dead_or_set_p (tem, piece)
13661 || reg_bitfield_target_p (piece,
13662 PATTERN (tem)))
13663 {
13664 add_reg_note (tem, REG_UNUSED, piece);
13665 break;
13666 }
13667 }
13668
13669 }
13670
13671 place = 0;
13672 }
13673 }
13674 }
13675 break;
13676
13677 default:
13678 /* Any other notes should not be present at this point in the
13679 compilation. */
13680 gcc_unreachable ();
13681 }
13682
13683 if (place)
13684 {
13685 XEXP (note, 1) = REG_NOTES (place);
13686 REG_NOTES (place) = note;
13687 }
13688
13689 if (place2)
13690 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13691 }
13692 }
13693 \f
13694 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13695 I3, I2, and I1 to new locations. This is also called to add a link
13696 pointing at I3 when I3's destination is changed. */
13697
13698 static void
13699 distribute_links (struct insn_link *links)
13700 {
13701 struct insn_link *link, *next_link;
13702
13703 for (link = links; link; link = next_link)
13704 {
13705 rtx place = 0;
13706 rtx insn;
13707 rtx set, reg;
13708
13709 next_link = link->next;
13710
13711 /* If the insn that this link points to is a NOTE or isn't a single
13712 set, ignore it. In the latter case, it isn't clear what we
13713 can do other than ignore the link, since we can't tell which
13714 register it was for. Such links wouldn't be used by combine
13715 anyway.
13716
13717 It is not possible for the destination of the target of the link to
13718 have been changed by combine. The only potential of this is if we
13719 replace I3, I2, and I1 by I3 and I2. But in that case the
13720 destination of I2 also remains unchanged. */
13721
13722 if (NOTE_P (link->insn)
13723 || (set = single_set (link->insn)) == 0)
13724 continue;
13725
13726 reg = SET_DEST (set);
13727 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13728 || GET_CODE (reg) == STRICT_LOW_PART)
13729 reg = XEXP (reg, 0);
13730
13731 /* A LOG_LINK is defined as being placed on the first insn that uses
13732 a register and points to the insn that sets the register. Start
13733 searching at the next insn after the target of the link and stop
13734 when we reach a set of the register or the end of the basic block.
13735
13736 Note that this correctly handles the link that used to point from
13737 I3 to I2. Also note that not much searching is typically done here
13738 since most links don't point very far away. */
13739
13740 for (insn = NEXT_INSN (link->insn);
13741 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13742 || BB_HEAD (this_basic_block->next_bb) != insn));
13743 insn = NEXT_INSN (insn))
13744 if (DEBUG_INSN_P (insn))
13745 continue;
13746 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13747 {
13748 if (reg_referenced_p (reg, PATTERN (insn)))
13749 place = insn;
13750 break;
13751 }
13752 else if (CALL_P (insn)
13753 && find_reg_fusage (insn, USE, reg))
13754 {
13755 place = insn;
13756 break;
13757 }
13758 else if (INSN_P (insn) && reg_set_p (reg, insn))
13759 break;
13760
13761 /* If we found a place to put the link, place it there unless there
13762 is already a link to the same insn as LINK at that point. */
13763
13764 if (place)
13765 {
13766 struct insn_link *link2;
13767
13768 FOR_EACH_LOG_LINK (link2, place)
13769 if (link2->insn == link->insn)
13770 break;
13771
13772 if (link2 == NULL)
13773 {
13774 link->next = LOG_LINKS (place);
13775 LOG_LINKS (place) = link;
13776
13777 /* Set added_links_insn to the earliest insn we added a
13778 link to. */
13779 if (added_links_insn == 0
13780 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13781 added_links_insn = place;
13782 }
13783 }
13784 }
13785 }
13786 \f
13787 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13788 Check whether the expression pointer to by LOC is a register or
13789 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13790 Otherwise return zero. */
13791
13792 static int
13793 unmentioned_reg_p_1 (rtx *loc, void *expr)
13794 {
13795 rtx x = *loc;
13796
13797 if (x != NULL_RTX
13798 && (REG_P (x) || MEM_P (x))
13799 && ! reg_mentioned_p (x, (rtx) expr))
13800 return 1;
13801 return 0;
13802 }
13803
13804 /* Check for any register or memory mentioned in EQUIV that is not
13805 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13806 of EXPR where some registers may have been replaced by constants. */
13807
13808 static bool
13809 unmentioned_reg_p (rtx equiv, rtx expr)
13810 {
13811 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13812 }
13813 \f
13814 void
13815 dump_combine_stats (FILE *file)
13816 {
13817 fprintf
13818 (file,
13819 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13820 combine_attempts, combine_merges, combine_extras, combine_successes);
13821 }
13822
13823 void
13824 dump_combine_total_stats (FILE *file)
13825 {
13826 fprintf
13827 (file,
13828 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13829 total_attempts, total_merges, total_extras, total_successes);
13830 }
13831 \f
13832 static bool
13833 gate_handle_combine (void)
13834 {
13835 return (optimize > 0);
13836 }
13837
13838 /* Try combining insns through substitution. */
13839 static unsigned int
13840 rest_of_handle_combine (void)
13841 {
13842 int rebuild_jump_labels_after_combine;
13843
13844 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13845 df_note_add_problem ();
13846 df_analyze ();
13847
13848 regstat_init_n_sets_and_refs ();
13849
13850 rebuild_jump_labels_after_combine
13851 = combine_instructions (get_insns (), max_reg_num ());
13852
13853 /* Combining insns may have turned an indirect jump into a
13854 direct jump. Rebuild the JUMP_LABEL fields of jumping
13855 instructions. */
13856 if (rebuild_jump_labels_after_combine)
13857 {
13858 timevar_push (TV_JUMP);
13859 rebuild_jump_labels (get_insns ());
13860 cleanup_cfg (0);
13861 timevar_pop (TV_JUMP);
13862 }
13863
13864 regstat_free_n_sets_and_refs ();
13865 return 0;
13866 }
13867
13868 struct rtl_opt_pass pass_combine =
13869 {
13870 {
13871 RTL_PASS,
13872 "combine", /* name */
13873 gate_handle_combine, /* gate */
13874 rest_of_handle_combine, /* execute */
13875 NULL, /* sub */
13876 NULL, /* next */
13877 0, /* static_pass_number */
13878 TV_COMBINE, /* tv_id */
13879 PROP_cfglayout, /* properties_required */
13880 0, /* properties_provided */
13881 0, /* properties_destroyed */
13882 0, /* todo_flags_start */
13883 TODO_dump_func |
13884 TODO_df_finish | TODO_verify_rtl_sharing |
13885 TODO_ggc_collect, /* todo_flags_finish */
13886 }
13887 };