1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
104 #include "tree-pass.h"
105 #include "valtrack.h"
106 #include "rtl-iter.h"
107 #include "print-rtl.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts
;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges
;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras
;
121 /* Number of instructions combined in this function. */
123 static int combine_successes
;
125 /* Totals over entire compilation. */
127 static int total_attempts
, total_merges
, total_extras
, total_successes
;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
136 static rtx_insn
*i2mod
;
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs
;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs
;
146 struct reg_stat_type
{
147 /* Record last point of death of (hard or pseudo) register n. */
148 rtx_insn
*last_death
;
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label
;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
256 static vec
<reg_stat_type
> reg_stat
;
258 /* One plus the highest pseudo for which we track REG_N_SETS.
259 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
260 but during combine_split_insns new pseudos can be created. As we don't have
261 updated DF information in that case, it is hard to initialize the array
262 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
263 so instead of growing the arrays, just assume all newly created pseudos
264 during combine might be set multiple times. */
266 static unsigned int reg_n_sets_max
;
268 /* Record the luid of the last insn that invalidated memory
269 (anything that writes memory, and subroutine calls, but not pushes). */
271 static int mem_last_set
;
273 /* Record the luid of the last CALL_INSN
274 so we can tell whether a potential combination crosses any calls. */
276 static int last_call_luid
;
278 /* When `subst' is called, this is the insn that is being modified
279 (by combining in a previous insn). The PATTERN of this insn
280 is still the old pattern partially modified and it should not be
281 looked at, but this may be used to examine the successors of the insn
282 to judge whether a simplification is valid. */
284 static rtx_insn
*subst_insn
;
286 /* This is the lowest LUID that `subst' is currently dealing with.
287 get_last_value will not return a value if the register was set at or
288 after this LUID. If not for this mechanism, we could get confused if
289 I2 or I1 in try_combine were an insn that used the old value of a register
290 to obtain a new value. In that case, we might erroneously get the
291 new value of the register when we wanted the old one. */
293 static int subst_low_luid
;
295 /* This contains any hard registers that are used in newpat; reg_dead_at_p
296 must consider all these registers to be always live. */
298 static HARD_REG_SET newpat_used_regs
;
300 /* This is an insn to which a LOG_LINKS entry has been added. If this
301 insn is the earlier than I2 or I3, combine should rescan starting at
304 static rtx_insn
*added_links_insn
;
306 /* And similarly, for notes. */
308 static rtx_insn
*added_notes_insn
;
310 /* Basic block in which we are performing combines. */
311 static basic_block this_basic_block
;
312 static bool optimize_this_for_speed_p
;
315 /* Length of the currently allocated uid_insn_cost array. */
317 static int max_uid_known
;
319 /* The following array records the insn_cost for every insn
320 in the instruction stream. */
322 static int *uid_insn_cost
;
324 /* The following array records the LOG_LINKS for every insn in the
325 instruction stream as struct insn_link pointers. */
330 struct insn_link
*next
;
333 static struct insn_link
**uid_log_links
;
336 insn_uid_check (const_rtx insn
)
338 int uid
= INSN_UID (insn
);
339 gcc_checking_assert (uid
<= max_uid_known
);
343 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
344 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
346 #define FOR_EACH_LOG_LINK(L, INSN) \
347 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
349 /* Links for LOG_LINKS are allocated from this obstack. */
351 static struct obstack insn_link_obstack
;
353 /* Allocate a link. */
355 static inline struct insn_link
*
356 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
359 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
360 sizeof (struct insn_link
));
367 /* Incremented for each basic block. */
369 static int label_tick
;
371 /* Reset to label_tick for each extended basic block in scanning order. */
373 static int label_tick_ebb_start
;
375 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
376 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
378 static scalar_int_mode nonzero_bits_mode
;
380 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
381 be safely used. It is zero while computing them and after combine has
382 completed. This former test prevents propagating values based on
383 previously set values, which can be incorrect if a variable is modified
386 static int nonzero_sign_valid
;
389 /* Record one modification to rtl structure
390 to be undone by storing old_contents into *where. */
392 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
398 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
399 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
402 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
403 num_undo says how many are currently recorded.
405 other_insn is nonzero if we have modified some other insn in the process
406 of working on subst_insn. It must be verified too. */
412 rtx_insn
*other_insn
;
415 static struct undobuf undobuf
;
417 /* Number of times the pseudo being substituted for
418 was found and replaced. */
420 static int n_occurrences
;
422 static rtx
reg_nonzero_bits_for_combine (const_rtx
, scalar_int_mode
,
424 unsigned HOST_WIDE_INT
*);
425 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, scalar_int_mode
,
428 static void do_SUBST (rtx
*, rtx
);
429 static void do_SUBST_INT (int *, int);
430 static void init_reg_last (void);
431 static void setup_incoming_promotions (rtx_insn
*);
432 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
433 static int cant_combine_insn_p (rtx_insn
*);
434 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
435 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
436 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
437 static int contains_muldiv (rtx
);
438 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
440 static void undo_all (void);
441 static void undo_commit (void);
442 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
443 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
444 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
445 static rtx
simplify_if_then_else (rtx
);
446 static rtx
simplify_set (rtx
);
447 static rtx
simplify_logical (rtx
);
448 static rtx
expand_compound_operation (rtx
);
449 static const_rtx
expand_field_assignment (const_rtx
);
450 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
451 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
452 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
453 unsigned HOST_WIDE_INT
*);
454 static rtx
canon_reg_for_combine (rtx
, rtx
);
455 static rtx
force_int_to_mode (rtx
, scalar_int_mode
, scalar_int_mode
,
456 scalar_int_mode
, unsigned HOST_WIDE_INT
, int);
457 static rtx
force_to_mode (rtx
, machine_mode
,
458 unsigned HOST_WIDE_INT
, int);
459 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
460 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
461 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
462 static rtx
make_field_assignment (rtx
);
463 static rtx
apply_distributive_law (rtx
);
464 static rtx
distribute_and_simplify_rtx (rtx
, int);
465 static rtx
simplify_and_const_int_1 (scalar_int_mode
, rtx
,
466 unsigned HOST_WIDE_INT
);
467 static rtx
simplify_and_const_int (rtx
, scalar_int_mode
, rtx
,
468 unsigned HOST_WIDE_INT
);
469 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
470 HOST_WIDE_INT
, machine_mode
, int *);
471 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
472 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
474 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
475 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
476 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
478 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
479 static void update_table_tick (rtx
);
480 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
481 static void check_promoted_subreg (rtx_insn
*, rtx
);
482 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
483 static void record_dead_and_set_regs (rtx_insn
*);
484 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
485 static rtx
get_last_value (const_rtx
);
486 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
487 static int reg_dead_at_p (rtx
, rtx_insn
*);
488 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
489 static int reg_bitfield_target_p (rtx
, rtx
);
490 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
491 static void distribute_links (struct insn_link
*);
492 static void mark_used_regs_combine (rtx
);
493 static void record_promoted_value (rtx_insn
*, rtx
);
494 static bool unmentioned_reg_p (rtx
, rtx
);
495 static void record_truncated_values (rtx
*, void *);
496 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
497 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
500 /* It is not safe to use ordinary gen_lowpart in combine.
501 See comments in gen_lowpart_for_combine. */
502 #undef RTL_HOOKS_GEN_LOWPART
503 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
505 /* Our implementation of gen_lowpart never emits a new pseudo. */
506 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
507 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
509 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
510 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
512 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
513 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
515 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
516 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
518 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
521 /* Convenience wrapper for the canonicalize_comparison target hook.
522 Target hooks cannot use enum rtx_code. */
524 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
525 bool op0_preserve_value
)
527 int code_int
= (int)*code
;
528 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
529 *code
= (enum rtx_code
)code_int
;
532 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
533 PATTERN cannot be split. Otherwise, it returns an insn sequence.
534 This is a wrapper around split_insns which ensures that the
535 reg_stat vector is made larger if the splitter creates a new
539 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
544 ret
= split_insns (pattern
, insn
);
545 nregs
= max_reg_num ();
546 if (nregs
> reg_stat
.length ())
547 reg_stat
.safe_grow_cleared (nregs
);
551 /* This is used by find_single_use to locate an rtx in LOC that
552 contains exactly one use of DEST, which is typically either a REG
553 or CC0. It returns a pointer to the innermost rtx expression
554 containing DEST. Appearances of DEST that are being used to
555 totally replace it are not counted. */
558 find_single_use_1 (rtx dest
, rtx
*loc
)
561 enum rtx_code code
= GET_CODE (x
);
578 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
579 of a REG that occupies all of the REG, the insn uses DEST if
580 it is mentioned in the destination or the source. Otherwise, we
581 need just check the source. */
582 if (GET_CODE (SET_DEST (x
)) != CC0
583 && GET_CODE (SET_DEST (x
)) != PC
584 && !REG_P (SET_DEST (x
))
585 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
586 && REG_P (SUBREG_REG (SET_DEST (x
)))
587 && !read_modify_subreg_p (SET_DEST (x
))))
590 return find_single_use_1 (dest
, &SET_SRC (x
));
594 return find_single_use_1 (dest
, &XEXP (x
, 0));
600 /* If it wasn't one of the common cases above, check each expression and
601 vector of this code. Look for a unique usage of DEST. */
603 fmt
= GET_RTX_FORMAT (code
);
604 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
608 if (dest
== XEXP (x
, i
)
609 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
610 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
613 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
616 result
= this_result
;
617 else if (this_result
)
618 /* Duplicate usage. */
621 else if (fmt
[i
] == 'E')
625 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
627 if (XVECEXP (x
, i
, j
) == dest
629 && REG_P (XVECEXP (x
, i
, j
))
630 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
633 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
636 result
= this_result
;
637 else if (this_result
)
647 /* See if DEST, produced in INSN, is used only a single time in the
648 sequel. If so, return a pointer to the innermost rtx expression in which
651 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
653 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
654 care about REG_DEAD notes or LOG_LINKS.
656 Otherwise, we find the single use by finding an insn that has a
657 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
658 only referenced once in that insn, we know that it must be the first
659 and last insn referencing DEST. */
662 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
667 struct insn_link
*link
;
671 next
= NEXT_INSN (insn
);
673 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
676 result
= find_single_use_1 (dest
, &PATTERN (next
));
685 bb
= BLOCK_FOR_INSN (insn
);
686 for (next
= NEXT_INSN (insn
);
687 next
&& BLOCK_FOR_INSN (next
) == bb
;
688 next
= NEXT_INSN (next
))
689 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
691 FOR_EACH_LOG_LINK (link
, next
)
692 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
697 result
= find_single_use_1 (dest
, &PATTERN (next
));
707 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
708 insn. The substitution can be undone by undo_all. If INTO is already
709 set to NEWVAL, do not record this change. Because computing NEWVAL might
710 also call SUBST, we have to compute it before we put anything into
714 do_SUBST (rtx
*into
, rtx newval
)
719 if (oldval
== newval
)
722 /* We'd like to catch as many invalid transformations here as
723 possible. Unfortunately, there are way too many mode changes
724 that are perfectly valid, so we'd waste too much effort for
725 little gain doing the checks here. Focus on catching invalid
726 transformations involving integer constants. */
727 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
728 && CONST_INT_P (newval
))
730 /* Sanity check that we're replacing oldval with a CONST_INT
731 that is a valid sign-extension for the original mode. */
732 gcc_assert (INTVAL (newval
)
733 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
735 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
736 CONST_INT is not valid, because after the replacement, the
737 original mode would be gone. Unfortunately, we can't tell
738 when do_SUBST is called to replace the operand thereof, so we
739 perform this test on oldval instead, checking whether an
740 invalid replacement took place before we got here. */
741 gcc_assert (!(GET_CODE (oldval
) == SUBREG
742 && CONST_INT_P (SUBREG_REG (oldval
))));
743 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
744 && CONST_INT_P (XEXP (oldval
, 0))));
748 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
750 buf
= XNEW (struct undo
);
752 buf
->kind
= UNDO_RTX
;
754 buf
->old_contents
.r
= oldval
;
757 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
760 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
762 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
763 for the value of a HOST_WIDE_INT value (including CONST_INT) is
767 do_SUBST_INT (int *into
, int newval
)
772 if (oldval
== newval
)
776 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
778 buf
= XNEW (struct undo
);
780 buf
->kind
= UNDO_INT
;
782 buf
->old_contents
.i
= oldval
;
785 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
788 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
790 /* Similar to SUBST, but just substitute the mode. This is used when
791 changing the mode of a pseudo-register, so that any other
792 references to the entry in the regno_reg_rtx array will change as
796 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
799 machine_mode oldval
= GET_MODE (*into
);
801 if (oldval
== newval
)
805 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
807 buf
= XNEW (struct undo
);
809 buf
->kind
= UNDO_MODE
;
811 buf
->old_contents
.m
= oldval
;
812 adjust_reg_mode (*into
, newval
);
814 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
817 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
819 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
822 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
825 struct insn_link
* oldval
= *into
;
827 if (oldval
== newval
)
831 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
833 buf
= XNEW (struct undo
);
835 buf
->kind
= UNDO_LINKS
;
837 buf
->old_contents
.l
= oldval
;
840 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
843 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
845 /* Subroutine of try_combine. Determine whether the replacement patterns
846 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
847 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
848 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
849 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
850 of all the instructions can be estimated and the replacements are more
851 expensive than the original sequence. */
854 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
855 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
857 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
858 int new_i2_cost
, new_i3_cost
;
859 int old_cost
, new_cost
;
861 /* Lookup the original insn_costs. */
862 i2_cost
= INSN_COST (i2
);
863 i3_cost
= INSN_COST (i3
);
867 i1_cost
= INSN_COST (i1
);
870 i0_cost
= INSN_COST (i0
);
871 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
872 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
876 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
877 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
883 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
884 i1_cost
= i0_cost
= 0;
887 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
889 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
893 /* Calculate the replacement insn_costs. */
894 rtx tmp
= PATTERN (i3
);
895 PATTERN (i3
) = newpat
;
896 int tmpi
= INSN_CODE (i3
);
898 new_i3_cost
= insn_cost (i3
, optimize_this_for_speed_p
);
900 INSN_CODE (i3
) = tmpi
;
904 PATTERN (i2
) = newi2pat
;
905 tmpi
= INSN_CODE (i2
);
907 new_i2_cost
= insn_cost (i2
, optimize_this_for_speed_p
);
909 INSN_CODE (i2
) = tmpi
;
910 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
911 ? new_i2_cost
+ new_i3_cost
: 0;
915 new_cost
= new_i3_cost
;
919 if (undobuf
.other_insn
)
921 int old_other_cost
, new_other_cost
;
923 old_other_cost
= INSN_COST (undobuf
.other_insn
);
924 tmp
= PATTERN (undobuf
.other_insn
);
925 PATTERN (undobuf
.other_insn
) = newotherpat
;
926 tmpi
= INSN_CODE (undobuf
.other_insn
);
927 INSN_CODE (undobuf
.other_insn
) = -1;
928 new_other_cost
= insn_cost (undobuf
.other_insn
,
929 optimize_this_for_speed_p
);
930 PATTERN (undobuf
.other_insn
) = tmp
;
931 INSN_CODE (undobuf
.other_insn
) = tmpi
;
932 if (old_other_cost
> 0 && new_other_cost
> 0)
934 old_cost
+= old_other_cost
;
935 new_cost
+= new_other_cost
;
941 /* Disallow this combination if both new_cost and old_cost are greater than
942 zero, and new_cost is greater than old cost. */
943 int reject
= old_cost
> 0 && new_cost
> old_cost
;
947 fprintf (dump_file
, "%s combination of insns ",
948 reject
? "rejecting" : "allowing");
950 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
951 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
952 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
953 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
955 fprintf (dump_file
, "original costs ");
957 fprintf (dump_file
, "%d + ", i0_cost
);
958 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
959 fprintf (dump_file
, "%d + ", i1_cost
);
960 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
963 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
964 new_i2_cost
, new_i3_cost
, new_cost
);
966 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
972 /* Update the uid_insn_cost array with the replacement costs. */
973 INSN_COST (i2
) = new_i2_cost
;
974 INSN_COST (i3
) = new_i3_cost
;
986 /* Delete any insns that copy a register to itself.
987 Return true if the CFG was changed. */
990 delete_noop_moves (void)
992 rtx_insn
*insn
, *next
;
995 bool edges_deleted
= false;
997 FOR_EACH_BB_FN (bb
, cfun
)
999 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
1001 next
= NEXT_INSN (insn
);
1002 if (INSN_P (insn
) && noop_move_p (insn
))
1005 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
1007 edges_deleted
|= delete_insn_and_edges (insn
);
1012 return edges_deleted
;
1016 /* Return false if we do not want to (or cannot) combine DEF. */
1018 can_combine_def_p (df_ref def
)
1020 /* Do not consider if it is pre/post modification in MEM. */
1021 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1024 unsigned int regno
= DF_REF_REGNO (def
);
1026 /* Do not combine frame pointer adjustments. */
1027 if ((regno
== FRAME_POINTER_REGNUM
1028 && (!reload_completed
|| frame_pointer_needed
))
1029 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1030 && regno
== HARD_FRAME_POINTER_REGNUM
1031 && (!reload_completed
|| frame_pointer_needed
))
1032 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1033 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1039 /* Return false if we do not want to (or cannot) combine USE. */
1041 can_combine_use_p (df_ref use
)
1043 /* Do not consider the usage of the stack pointer by function call. */
1044 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1050 /* Fill in log links field for all insns. */
1053 create_log_links (void)
1056 rtx_insn
**next_use
;
1060 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1062 /* Pass through each block from the end, recording the uses of each
1063 register and establishing log links when def is encountered.
1064 Note that we do not clear next_use array in order to save time,
1065 so we have to test whether the use is in the same basic block as def.
1067 There are a few cases below when we do not consider the definition or
1068 usage -- these are taken from original flow.c did. Don't ask me why it is
1069 done this way; I don't know and if it works, I don't want to know. */
1071 FOR_EACH_BB_FN (bb
, cfun
)
1073 FOR_BB_INSNS_REVERSE (bb
, insn
)
1075 if (!NONDEBUG_INSN_P (insn
))
1078 /* Log links are created only once. */
1079 gcc_assert (!LOG_LINKS (insn
));
1081 FOR_EACH_INSN_DEF (def
, insn
)
1083 unsigned int regno
= DF_REF_REGNO (def
);
1086 if (!next_use
[regno
])
1089 if (!can_combine_def_p (def
))
1092 use_insn
= next_use
[regno
];
1093 next_use
[regno
] = NULL
;
1095 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1100 We don't build a LOG_LINK for hard registers contained
1101 in ASM_OPERANDs. If these registers get replaced,
1102 we might wind up changing the semantics of the insn,
1103 even if reload can make what appear to be valid
1104 assignments later. */
1105 if (regno
< FIRST_PSEUDO_REGISTER
1106 && asm_noperands (PATTERN (use_insn
)) >= 0)
1109 /* Don't add duplicate links between instructions. */
1110 struct insn_link
*links
;
1111 FOR_EACH_LOG_LINK (links
, use_insn
)
1112 if (insn
== links
->insn
&& regno
== links
->regno
)
1116 LOG_LINKS (use_insn
)
1117 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1120 FOR_EACH_INSN_USE (use
, insn
)
1121 if (can_combine_use_p (use
))
1122 next_use
[DF_REF_REGNO (use
)] = insn
;
1129 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1130 true if we found a LOG_LINK that proves that A feeds B. This only works
1131 if there are no instructions between A and B which could have a link
1132 depending on A, since in that case we would not record a link for B.
1133 We also check the implicit dependency created by a cc0 setter/user
1137 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1139 struct insn_link
*links
;
1140 FOR_EACH_LOG_LINK (links
, b
)
1141 if (links
->insn
== a
)
1143 if (HAVE_cc0
&& sets_cc0_p (a
))
1148 /* Main entry point for combiner. F is the first insn of the function.
1149 NREGS is the first unused pseudo-reg number.
1151 Return nonzero if the CFG was changed (e.g. if the combiner has
1152 turned an indirect jump instruction into a direct jump). */
1154 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1156 rtx_insn
*insn
, *next
;
1158 struct insn_link
*links
, *nextlinks
;
1160 basic_block last_bb
;
1162 int new_direct_jump_p
= 0;
1164 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1165 first
= NEXT_INSN (first
);
1169 combine_attempts
= 0;
1172 combine_successes
= 0;
1174 rtl_hooks
= combine_rtl_hooks
;
1176 reg_stat
.safe_grow_cleared (nregs
);
1178 init_recog_no_volatile ();
1180 /* Allocate array for insn info. */
1181 max_uid_known
= get_max_uid ();
1182 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1183 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1184 gcc_obstack_init (&insn_link_obstack
);
1186 nonzero_bits_mode
= int_mode_for_size (HOST_BITS_PER_WIDE_INT
, 0).require ();
1188 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1189 problems when, for example, we have j <<= 1 in a loop. */
1191 nonzero_sign_valid
= 0;
1192 label_tick
= label_tick_ebb_start
= 1;
1194 /* Scan all SETs and see if we can deduce anything about what
1195 bits are known to be zero for some registers and how many copies
1196 of the sign bit are known to exist for those registers.
1198 Also set any known values so that we can use it while searching
1199 for what bits are known to be set. */
1201 setup_incoming_promotions (first
);
1202 /* Allow the entry block and the first block to fall into the same EBB.
1203 Conceptually the incoming promotions are assigned to the entry block. */
1204 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1206 create_log_links ();
1207 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1209 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1214 if (!single_pred_p (this_basic_block
)
1215 || single_pred (this_basic_block
) != last_bb
)
1216 label_tick_ebb_start
= label_tick
;
1217 last_bb
= this_basic_block
;
1219 FOR_BB_INSNS (this_basic_block
, insn
)
1220 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1224 subst_low_luid
= DF_INSN_LUID (insn
);
1227 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1229 record_dead_and_set_regs (insn
);
1232 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1233 if (REG_NOTE_KIND (links
) == REG_INC
)
1234 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1237 /* Record the current insn_cost of this instruction. */
1238 if (NONJUMP_INSN_P (insn
))
1239 INSN_COST (insn
) = insn_cost (insn
, optimize_this_for_speed_p
);
1242 fprintf (dump_file
, "insn_cost %d for ", INSN_COST (insn
));
1243 dump_insn_slim (dump_file
, insn
);
1248 nonzero_sign_valid
= 1;
1250 /* Now scan all the insns in forward order. */
1251 label_tick
= label_tick_ebb_start
= 1;
1253 setup_incoming_promotions (first
);
1254 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1255 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1257 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1259 rtx_insn
*last_combined_insn
= NULL
;
1261 /* Ignore instruction combination in basic blocks that are going to
1262 be removed as unreachable anyway. See PR82386. */
1263 if (EDGE_COUNT (this_basic_block
->preds
) == 0)
1266 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1271 if (!single_pred_p (this_basic_block
)
1272 || single_pred (this_basic_block
) != last_bb
)
1273 label_tick_ebb_start
= label_tick
;
1274 last_bb
= this_basic_block
;
1276 rtl_profile_for_bb (this_basic_block
);
1277 for (insn
= BB_HEAD (this_basic_block
);
1278 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1279 insn
= next
? next
: NEXT_INSN (insn
))
1282 if (!NONDEBUG_INSN_P (insn
))
1285 while (last_combined_insn
1286 && (!NONDEBUG_INSN_P (last_combined_insn
)
1287 || last_combined_insn
->deleted ()))
1288 last_combined_insn
= PREV_INSN (last_combined_insn
);
1289 if (last_combined_insn
== NULL_RTX
1290 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1291 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1292 last_combined_insn
= insn
;
1294 /* See if we know about function return values before this
1295 insn based upon SUBREG flags. */
1296 check_promoted_subreg (insn
, PATTERN (insn
));
1298 /* See if we can find hardregs and subreg of pseudos in
1299 narrower modes. This could help turning TRUNCATEs
1301 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1303 /* Try this insn with each insn it links back to. */
1305 FOR_EACH_LOG_LINK (links
, insn
)
1306 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1307 NULL
, &new_direct_jump_p
,
1308 last_combined_insn
)) != 0)
1310 statistics_counter_event (cfun
, "two-insn combine", 1);
1314 /* Try each sequence of three linked insns ending with this one. */
1316 if (max_combine
>= 3)
1317 FOR_EACH_LOG_LINK (links
, insn
)
1319 rtx_insn
*link
= links
->insn
;
1321 /* If the linked insn has been replaced by a note, then there
1322 is no point in pursuing this chain any further. */
1326 FOR_EACH_LOG_LINK (nextlinks
, link
)
1327 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1328 NULL
, &new_direct_jump_p
,
1329 last_combined_insn
)) != 0)
1331 statistics_counter_event (cfun
, "three-insn combine", 1);
1336 /* Try to combine a jump insn that uses CC0
1337 with a preceding insn that sets CC0, and maybe with its
1338 logical predecessor as well.
1339 This is how we make decrement-and-branch insns.
1340 We need this special code because data flow connections
1341 via CC0 do not get entered in LOG_LINKS. */
1345 && (prev
= prev_nonnote_insn (insn
)) != 0
1346 && NONJUMP_INSN_P (prev
)
1347 && sets_cc0_p (PATTERN (prev
)))
1349 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1351 last_combined_insn
)) != 0)
1354 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1355 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1356 NULL
, &new_direct_jump_p
,
1357 last_combined_insn
)) != 0)
1361 /* Do the same for an insn that explicitly references CC0. */
1362 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1363 && (prev
= prev_nonnote_insn (insn
)) != 0
1364 && NONJUMP_INSN_P (prev
)
1365 && sets_cc0_p (PATTERN (prev
))
1366 && GET_CODE (PATTERN (insn
)) == SET
1367 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1369 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1371 last_combined_insn
)) != 0)
1374 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1375 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1376 NULL
, &new_direct_jump_p
,
1377 last_combined_insn
)) != 0)
1381 /* Finally, see if any of the insns that this insn links to
1382 explicitly references CC0. If so, try this insn, that insn,
1383 and its predecessor if it sets CC0. */
1386 FOR_EACH_LOG_LINK (links
, insn
)
1387 if (NONJUMP_INSN_P (links
->insn
)
1388 && GET_CODE (PATTERN (links
->insn
)) == SET
1389 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1390 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1391 && NONJUMP_INSN_P (prev
)
1392 && sets_cc0_p (PATTERN (prev
))
1393 && (next
= try_combine (insn
, links
->insn
,
1394 prev
, NULL
, &new_direct_jump_p
,
1395 last_combined_insn
)) != 0)
1399 /* Try combining an insn with two different insns whose results it
1401 if (max_combine
>= 3)
1402 FOR_EACH_LOG_LINK (links
, insn
)
1403 for (nextlinks
= links
->next
; nextlinks
;
1404 nextlinks
= nextlinks
->next
)
1405 if ((next
= try_combine (insn
, links
->insn
,
1406 nextlinks
->insn
, NULL
,
1408 last_combined_insn
)) != 0)
1411 statistics_counter_event (cfun
, "three-insn combine", 1);
1415 /* Try four-instruction combinations. */
1416 if (max_combine
>= 4)
1417 FOR_EACH_LOG_LINK (links
, insn
)
1419 struct insn_link
*next1
;
1420 rtx_insn
*link
= links
->insn
;
1422 /* If the linked insn has been replaced by a note, then there
1423 is no point in pursuing this chain any further. */
1427 FOR_EACH_LOG_LINK (next1
, link
)
1429 rtx_insn
*link1
= next1
->insn
;
1432 /* I0 -> I1 -> I2 -> I3. */
1433 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1434 if ((next
= try_combine (insn
, link
, link1
,
1437 last_combined_insn
)) != 0)
1439 statistics_counter_event (cfun
, "four-insn combine", 1);
1442 /* I0, I1 -> I2, I2 -> I3. */
1443 for (nextlinks
= next1
->next
; nextlinks
;
1444 nextlinks
= nextlinks
->next
)
1445 if ((next
= try_combine (insn
, link
, link1
,
1448 last_combined_insn
)) != 0)
1450 statistics_counter_event (cfun
, "four-insn combine", 1);
1455 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1457 rtx_insn
*link1
= next1
->insn
;
1460 /* I0 -> I2; I1, I2 -> I3. */
1461 FOR_EACH_LOG_LINK (nextlinks
, link
)
1462 if ((next
= try_combine (insn
, link
, link1
,
1465 last_combined_insn
)) != 0)
1467 statistics_counter_event (cfun
, "four-insn combine", 1);
1470 /* I0 -> I1; I1, I2 -> I3. */
1471 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1472 if ((next
= try_combine (insn
, link
, link1
,
1475 last_combined_insn
)) != 0)
1477 statistics_counter_event (cfun
, "four-insn combine", 1);
1483 /* Try this insn with each REG_EQUAL note it links back to. */
1484 FOR_EACH_LOG_LINK (links
, insn
)
1487 rtx_insn
*temp
= links
->insn
;
1488 if ((set
= single_set (temp
)) != 0
1489 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1490 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1491 /* Avoid using a register that may already been marked
1492 dead by an earlier instruction. */
1493 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1494 && (GET_MODE (note
) == VOIDmode
1495 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1496 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1497 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1498 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1499 == GET_MODE (note
))))))
1501 /* Temporarily replace the set's source with the
1502 contents of the REG_EQUAL note. The insn will
1503 be deleted or recognized by try_combine. */
1504 rtx orig_src
= SET_SRC (set
);
1505 rtx orig_dest
= SET_DEST (set
);
1506 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1507 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1508 SET_SRC (set
) = note
;
1510 i2mod_old_rhs
= copy_rtx (orig_src
);
1511 i2mod_new_rhs
= copy_rtx (note
);
1512 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1514 last_combined_insn
);
1518 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1521 SET_SRC (set
) = orig_src
;
1522 SET_DEST (set
) = orig_dest
;
1527 record_dead_and_set_regs (insn
);
1534 default_rtl_profile ();
1536 new_direct_jump_p
|= purge_all_dead_edges ();
1537 new_direct_jump_p
|= delete_noop_moves ();
1540 obstack_free (&insn_link_obstack
, NULL
);
1541 free (uid_log_links
);
1542 free (uid_insn_cost
);
1543 reg_stat
.release ();
1546 struct undo
*undo
, *next
;
1547 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1555 total_attempts
+= combine_attempts
;
1556 total_merges
+= combine_merges
;
1557 total_extras
+= combine_extras
;
1558 total_successes
+= combine_successes
;
1560 nonzero_sign_valid
= 0;
1561 rtl_hooks
= general_rtl_hooks
;
1563 /* Make recognizer allow volatile MEMs again. */
1566 return new_direct_jump_p
;
1569 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1572 init_reg_last (void)
1577 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1578 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1581 /* Set up any promoted values for incoming argument registers. */
1584 setup_incoming_promotions (rtx_insn
*first
)
1587 bool strictly_local
= false;
1589 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1590 arg
= DECL_CHAIN (arg
))
1592 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1594 machine_mode mode1
, mode2
, mode3
, mode4
;
1596 /* Only continue if the incoming argument is in a register. */
1600 /* Determine, if possible, whether all call sites of the current
1601 function lie within the current compilation unit. (This does
1602 take into account the exporting of a function via taking its
1603 address, and so forth.) */
1604 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1606 /* The mode and signedness of the argument before any promotions happen
1607 (equal to the mode of the pseudo holding it at that stage). */
1608 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1609 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1611 /* The mode and signedness of the argument after any source language and
1612 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1613 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1614 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1616 /* The mode and signedness of the argument as it is actually passed,
1617 see assign_parm_setup_reg in function.c. */
1618 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1619 TREE_TYPE (cfun
->decl
), 0);
1621 /* The mode of the register in which the argument is being passed. */
1622 mode4
= GET_MODE (reg
);
1624 /* Eliminate sign extensions in the callee when:
1625 (a) A mode promotion has occurred; */
1628 /* (b) The mode of the register is the same as the mode of
1629 the argument as it is passed; */
1632 /* (c) There's no language level extension; */
1635 /* (c.1) All callers are from the current compilation unit. If that's
1636 the case we don't have to rely on an ABI, we only have to know
1637 what we're generating right now, and we know that we will do the
1638 mode1 to mode2 promotion with the given sign. */
1639 else if (!strictly_local
)
1641 /* (c.2) The combination of the two promotions is useful. This is
1642 true when the signs match, or if the first promotion is unsigned.
1643 In the later case, (sign_extend (zero_extend x)) is the same as
1644 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1650 /* Record that the value was promoted from mode1 to mode3,
1651 so that any sign extension at the head of the current
1652 function may be eliminated. */
1653 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1654 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1655 record_value_for_reg (reg
, first
, x
);
1659 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1660 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1661 because some machines (maybe most) will actually do the sign-extension and
1662 this is the conservative approach.
1664 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1668 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1670 scalar_int_mode int_mode
;
1671 if (CONST_INT_P (src
)
1672 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1673 && GET_MODE_PRECISION (int_mode
) < prec
1675 && val_signbit_known_set_p (int_mode
, INTVAL (src
)))
1676 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (int_mode
));
1681 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1685 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1688 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1689 unsigned HOST_WIDE_INT bits
= 0;
1690 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1691 unsigned int num
= 0;
1694 reg_equal
= XEXP (reg_equal_note
, 0);
1696 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1698 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1700 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1703 /* Don't call nonzero_bits if it cannot change anything. */
1704 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1706 machine_mode mode
= GET_MODE (x
);
1707 if (GET_MODE_CLASS (mode
) == MODE_INT
1708 && HWI_COMPUTABLE_MODE_P (mode
))
1709 mode
= nonzero_bits_mode
;
1710 bits
= nonzero_bits (src
, mode
);
1711 if (reg_equal
&& bits
)
1712 bits
&= nonzero_bits (reg_equal
, mode
);
1713 rsp
->nonzero_bits
|= bits
;
1716 /* Don't call num_sign_bit_copies if it cannot change anything. */
1717 if (rsp
->sign_bit_copies
!= 1)
1719 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1720 if (reg_equal
&& maybe_ne (num
, GET_MODE_PRECISION (GET_MODE (x
))))
1722 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1723 if (num
== 0 || numeq
> num
)
1726 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1727 rsp
->sign_bit_copies
= num
;
1731 /* Called via note_stores. If X is a pseudo that is narrower than
1732 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1734 If we are setting only a portion of X and we can't figure out what
1735 portion, assume all bits will be used since we don't know what will
1738 Similarly, set how many bits of X are known to be copies of the sign bit
1739 at all locations in the function. This is the smallest number implied
1743 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1745 rtx_insn
*insn
= (rtx_insn
*) data
;
1746 scalar_int_mode mode
;
1749 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1750 /* If this register is undefined at the start of the file, we can't
1751 say what its contents were. */
1752 && ! REGNO_REG_SET_P
1753 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1754 && is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
1755 && HWI_COMPUTABLE_MODE_P (mode
))
1757 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1759 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1761 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1762 rsp
->sign_bit_copies
= 1;
1766 /* Should not happen as we only using pseduo registers. */
1767 gcc_assert (GET_CODE (set
) != CLOBBER_HIGH
);
1769 /* If this register is being initialized using itself, and the
1770 register is uninitialized in this basic block, and there are
1771 no LOG_LINKS which set the register, then part of the
1772 register is uninitialized. In that case we can't assume
1773 anything about the number of nonzero bits.
1775 ??? We could do better if we checked this in
1776 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1777 could avoid making assumptions about the insn which initially
1778 sets the register, while still using the information in other
1779 insns. We would have to be careful to check every insn
1780 involved in the combination. */
1783 && reg_referenced_p (x
, PATTERN (insn
))
1784 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1787 struct insn_link
*link
;
1789 FOR_EACH_LOG_LINK (link
, insn
)
1790 if (dead_or_set_p (link
->insn
, x
))
1794 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1795 rsp
->sign_bit_copies
= 1;
1800 /* If this is a complex assignment, see if we can convert it into a
1801 simple assignment. */
1802 set
= expand_field_assignment (set
);
1804 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1805 set what we know about X. */
1807 if (SET_DEST (set
) == x
1808 || (paradoxical_subreg_p (SET_DEST (set
))
1809 && SUBREG_REG (SET_DEST (set
)) == x
))
1810 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1813 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1814 rsp
->sign_bit_copies
= 1;
1819 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1820 optionally insns that were previously combined into I3 or that will be
1821 combined into the merger of INSN and I3. The order is PRED, PRED2,
1822 INSN, SUCC, SUCC2, I3.
1824 Return 0 if the combination is not allowed for any reason.
1826 If the combination is allowed, *PDEST will be set to the single
1827 destination of INSN and *PSRC to the single source, and this function
1831 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1832 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1833 rtx
*pdest
, rtx
*psrc
)
1840 bool all_adjacent
= true;
1841 int (*is_volatile_p
) (const_rtx
);
1847 if (next_active_insn (succ2
) != i3
)
1848 all_adjacent
= false;
1849 if (next_active_insn (succ
) != succ2
)
1850 all_adjacent
= false;
1852 else if (next_active_insn (succ
) != i3
)
1853 all_adjacent
= false;
1854 if (next_active_insn (insn
) != succ
)
1855 all_adjacent
= false;
1857 else if (next_active_insn (insn
) != i3
)
1858 all_adjacent
= false;
1860 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1861 or a PARALLEL consisting of such a SET and CLOBBERs.
1863 If INSN has CLOBBER parallel parts, ignore them for our processing.
1864 By definition, these happen during the execution of the insn. When it
1865 is merged with another insn, all bets are off. If they are, in fact,
1866 needed and aren't also supplied in I3, they may be added by
1867 recog_for_combine. Otherwise, it won't match.
1869 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1872 Get the source and destination of INSN. If more than one, can't
1875 if (GET_CODE (PATTERN (insn
)) == SET
)
1876 set
= PATTERN (insn
);
1877 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1878 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1880 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1882 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1884 switch (GET_CODE (elt
))
1886 /* This is important to combine floating point insns
1887 for the SH4 port. */
1889 /* Combining an isolated USE doesn't make sense.
1890 We depend here on combinable_i3pat to reject them. */
1891 /* The code below this loop only verifies that the inputs of
1892 the SET in INSN do not change. We call reg_set_between_p
1893 to verify that the REG in the USE does not change between
1895 If the USE in INSN was for a pseudo register, the matching
1896 insn pattern will likely match any register; combining this
1897 with any other USE would only be safe if we knew that the
1898 used registers have identical values, or if there was
1899 something to tell them apart, e.g. different modes. For
1900 now, we forgo such complicated tests and simply disallow
1901 combining of USES of pseudo registers with any other USE. */
1902 if (REG_P (XEXP (elt
, 0))
1903 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1905 rtx i3pat
= PATTERN (i3
);
1906 int i
= XVECLEN (i3pat
, 0) - 1;
1907 unsigned int regno
= REGNO (XEXP (elt
, 0));
1911 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1913 if (GET_CODE (i3elt
) == USE
1914 && REG_P (XEXP (i3elt
, 0))
1915 && (REGNO (XEXP (i3elt
, 0)) == regno
1916 ? reg_set_between_p (XEXP (elt
, 0),
1917 PREV_INSN (insn
), i3
)
1918 : regno
>= FIRST_PSEUDO_REGISTER
))
1925 /* We can ignore CLOBBERs. */
1931 /* Ignore SETs whose result isn't used but not those that
1932 have side-effects. */
1933 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1934 && insn_nothrow_p (insn
)
1935 && !side_effects_p (elt
))
1938 /* If we have already found a SET, this is a second one and
1939 so we cannot combine with this insn. */
1947 /* Anything else means we can't combine. */
1953 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1954 so don't do anything with it. */
1955 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1964 /* The simplification in expand_field_assignment may call back to
1965 get_last_value, so set safe guard here. */
1966 subst_low_luid
= DF_INSN_LUID (insn
);
1968 set
= expand_field_assignment (set
);
1969 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1971 /* Do not eliminate user-specified register if it is in an
1972 asm input because we may break the register asm usage defined
1973 in GCC manual if allow to do so.
1974 Be aware that this may cover more cases than we expect but this
1975 should be harmless. */
1976 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1977 && extract_asm_operands (PATTERN (i3
)))
1980 /* Don't eliminate a store in the stack pointer. */
1981 if (dest
== stack_pointer_rtx
1982 /* Don't combine with an insn that sets a register to itself if it has
1983 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1984 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1985 /* Can't merge an ASM_OPERANDS. */
1986 || GET_CODE (src
) == ASM_OPERANDS
1987 /* Can't merge a function call. */
1988 || GET_CODE (src
) == CALL
1989 /* Don't eliminate a function call argument. */
1991 && (find_reg_fusage (i3
, USE
, dest
)
1993 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1994 && global_regs
[REGNO (dest
)])))
1995 /* Don't substitute into an incremented register. */
1996 || FIND_REG_INC_NOTE (i3
, dest
)
1997 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1998 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1999 /* Don't substitute into a non-local goto, this confuses CFG. */
2000 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
2001 /* Make sure that DEST is not used after INSN but before SUCC, or
2002 after SUCC and before SUCC2, or after SUCC2 but before I3. */
2005 && (reg_used_between_p (dest
, succ2
, i3
)
2006 || reg_used_between_p (dest
, succ
, succ2
)))
2007 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))
2008 || (!succ2
&& !succ
&& reg_used_between_p (dest
, insn
, i3
))
2010 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
2011 that case SUCC is not in the insn stream, so use SUCC2
2012 instead for this test. */
2013 && reg_used_between_p (dest
, insn
,
2015 && INSN_UID (succ
) == INSN_UID (succ2
)
2017 /* Make sure that the value that is to be substituted for the register
2018 does not use any registers whose values alter in between. However,
2019 If the insns are adjacent, a use can't cross a set even though we
2020 think it might (this can happen for a sequence of insns each setting
2021 the same destination; last_set of that register might point to
2022 a NOTE). If INSN has a REG_EQUIV note, the register is always
2023 equivalent to the memory so the substitution is valid even if there
2024 are intervening stores. Also, don't move a volatile asm or
2025 UNSPEC_VOLATILE across any other insns. */
2028 || ! find_reg_note (insn
, REG_EQUIV
, src
))
2029 && modified_between_p (src
, insn
, i3
))
2030 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
2031 || GET_CODE (src
) == UNSPEC_VOLATILE
))
2032 /* Don't combine across a CALL_INSN, because that would possibly
2033 change whether the life span of some REGs crosses calls or not,
2034 and it is a pain to update that information.
2035 Exception: if source is a constant, moving it later can't hurt.
2036 Accept that as a special case. */
2037 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
2040 /* DEST must either be a REG or CC0. */
2043 /* If register alignment is being enforced for multi-word items in all
2044 cases except for parameters, it is possible to have a register copy
2045 insn referencing a hard register that is not allowed to contain the
2046 mode being copied and which would not be valid as an operand of most
2047 insns. Eliminate this problem by not combining with such an insn.
2049 Also, on some machines we don't want to extend the life of a hard
2053 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2054 && !targetm
.hard_regno_mode_ok (REGNO (dest
), GET_MODE (dest
)))
2055 /* Don't extend the life of a hard register unless it is
2056 user variable (if we have few registers) or it can't
2057 fit into the desired register (meaning something special
2059 Also avoid substituting a return register into I3, because
2060 reload can't handle a conflict with constraints of other
2062 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2063 && !targetm
.hard_regno_mode_ok (REGNO (src
),
2067 else if (GET_CODE (dest
) != CC0
)
2071 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2072 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2073 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2075 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2077 /* If the clobber represents an earlyclobber operand, we must not
2078 substitute an expression containing the clobbered register.
2079 As we do not analyze the constraint strings here, we have to
2080 make the conservative assumption. However, if the register is
2081 a fixed hard reg, the clobber cannot represent any operand;
2082 we leave it up to the machine description to either accept or
2083 reject use-and-clobber patterns. */
2085 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2086 || !fixed_regs
[REGNO (reg
)])
2087 if (reg_overlap_mentioned_p (reg
, src
))
2091 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2092 or not), reject, unless nothing volatile comes between it and I3 */
2094 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2096 /* Make sure neither succ nor succ2 contains a volatile reference. */
2097 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2099 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2101 /* We'll check insns between INSN and I3 below. */
2104 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2105 to be an explicit register variable, and was chosen for a reason. */
2107 if (GET_CODE (src
) == ASM_OPERANDS
2108 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2111 /* If INSN contains volatile references (specifically volatile MEMs),
2112 we cannot combine across any other volatile references.
2113 Even if INSN doesn't contain volatile references, any intervening
2114 volatile insn might affect machine state. */
2116 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2120 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2121 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2124 /* If INSN contains an autoincrement or autodecrement, make sure that
2125 register is not used between there and I3, and not already used in
2126 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2127 Also insist that I3 not be a jump; if it were one
2128 and the incremented register were spilled, we would lose. */
2131 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2132 if (REG_NOTE_KIND (link
) == REG_INC
2134 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2135 || (pred
!= NULL_RTX
2136 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2137 || (pred2
!= NULL_RTX
2138 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2139 || (succ
!= NULL_RTX
2140 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2141 || (succ2
!= NULL_RTX
2142 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2143 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2146 /* Don't combine an insn that follows a CC0-setting insn.
2147 An insn that uses CC0 must not be separated from the one that sets it.
2148 We do, however, allow I2 to follow a CC0-setting insn if that insn
2149 is passed as I1; in that case it will be deleted also.
2150 We also allow combining in this case if all the insns are adjacent
2151 because that would leave the two CC0 insns adjacent as well.
2152 It would be more logical to test whether CC0 occurs inside I1 or I2,
2153 but that would be much slower, and this ought to be equivalent. */
2157 p
= prev_nonnote_insn (insn
);
2158 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2163 /* If we get here, we have passed all the tests and the combination is
2172 /* LOC is the location within I3 that contains its pattern or the component
2173 of a PARALLEL of the pattern. We validate that it is valid for combining.
2175 One problem is if I3 modifies its output, as opposed to replacing it
2176 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2177 doing so would produce an insn that is not equivalent to the original insns.
2181 (set (reg:DI 101) (reg:DI 100))
2182 (set (subreg:SI (reg:DI 101) 0) <foo>)
2184 This is NOT equivalent to:
2186 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2187 (set (reg:DI 101) (reg:DI 100))])
2189 Not only does this modify 100 (in which case it might still be valid
2190 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2192 We can also run into a problem if I2 sets a register that I1
2193 uses and I1 gets directly substituted into I3 (not via I2). In that
2194 case, we would be getting the wrong value of I2DEST into I3, so we
2195 must reject the combination. This case occurs when I2 and I1 both
2196 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2197 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2198 of a SET must prevent combination from occurring. The same situation
2199 can occur for I0, in which case I0_NOT_IN_SRC is set.
2201 Before doing the above check, we first try to expand a field assignment
2202 into a set of logical operations.
2204 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2205 we place a register that is both set and used within I3. If more than one
2206 such register is detected, we fail.
2208 Return 1 if the combination is valid, zero otherwise. */
2211 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2212 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2216 if (GET_CODE (x
) == SET
)
2219 rtx dest
= SET_DEST (set
);
2220 rtx src
= SET_SRC (set
);
2221 rtx inner_dest
= dest
;
2224 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2225 || GET_CODE (inner_dest
) == SUBREG
2226 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2227 inner_dest
= XEXP (inner_dest
, 0);
2229 /* Check for the case where I3 modifies its output, as discussed
2230 above. We don't want to prevent pseudos from being combined
2231 into the address of a MEM, so only prevent the combination if
2232 i1 or i2 set the same MEM. */
2233 if ((inner_dest
!= dest
&&
2234 (!MEM_P (inner_dest
)
2235 || rtx_equal_p (i2dest
, inner_dest
)
2236 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2237 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2238 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2239 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2240 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2242 /* This is the same test done in can_combine_p except we can't test
2243 all_adjacent; we don't have to, since this instruction will stay
2244 in place, thus we are not considering increasing the lifetime of
2247 Also, if this insn sets a function argument, combining it with
2248 something that might need a spill could clobber a previous
2249 function argument; the all_adjacent test in can_combine_p also
2250 checks this; here, we do a more specific test for this case. */
2252 || (REG_P (inner_dest
)
2253 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2254 && !targetm
.hard_regno_mode_ok (REGNO (inner_dest
),
2255 GET_MODE (inner_dest
)))
2256 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2257 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2260 /* If DEST is used in I3, it is being killed in this insn, so
2261 record that for later. We have to consider paradoxical
2262 subregs here, since they kill the whole register, but we
2263 ignore partial subregs, STRICT_LOW_PART, etc.
2264 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2265 STACK_POINTER_REGNUM, since these are always considered to be
2266 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2268 if (GET_CODE (subdest
) == SUBREG
&& !partial_subreg_p (subdest
))
2269 subdest
= SUBREG_REG (subdest
);
2272 && reg_referenced_p (subdest
, PATTERN (i3
))
2273 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2274 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2275 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2276 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2277 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2278 || ! fixed_regs
[REGNO (subdest
)]))
2279 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2281 if (*pi3dest_killed
)
2284 *pi3dest_killed
= subdest
;
2288 else if (GET_CODE (x
) == PARALLEL
)
2292 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2293 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2294 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2301 /* Return 1 if X is an arithmetic expression that contains a multiplication
2302 and division. We don't count multiplications by powers of two here. */
2305 contains_muldiv (rtx x
)
2307 switch (GET_CODE (x
))
2309 case MOD
: case DIV
: case UMOD
: case UDIV
:
2313 return ! (CONST_INT_P (XEXP (x
, 1))
2314 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2317 return contains_muldiv (XEXP (x
, 0))
2318 || contains_muldiv (XEXP (x
, 1));
2321 return contains_muldiv (XEXP (x
, 0));
2327 /* Determine whether INSN can be used in a combination. Return nonzero if
2328 not. This is used in try_combine to detect early some cases where we
2329 can't perform combinations. */
2332 cant_combine_insn_p (rtx_insn
*insn
)
2337 /* If this isn't really an insn, we can't do anything.
2338 This can occur when flow deletes an insn that it has merged into an
2339 auto-increment address. */
2340 if (!NONDEBUG_INSN_P (insn
))
2343 /* Never combine loads and stores involving hard regs that are likely
2344 to be spilled. The register allocator can usually handle such
2345 reg-reg moves by tying. If we allow the combiner to make
2346 substitutions of likely-spilled regs, reload might die.
2347 As an exception, we allow combinations involving fixed regs; these are
2348 not available to the register allocator so there's no risk involved. */
2350 set
= single_set (insn
);
2353 src
= SET_SRC (set
);
2354 dest
= SET_DEST (set
);
2355 if (GET_CODE (src
) == SUBREG
)
2356 src
= SUBREG_REG (src
);
2357 if (GET_CODE (dest
) == SUBREG
)
2358 dest
= SUBREG_REG (dest
);
2359 if (REG_P (src
) && REG_P (dest
)
2360 && ((HARD_REGISTER_P (src
)
2361 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2362 #ifdef LEAF_REGISTERS
2363 && ! LEAF_REGISTERS
[REGNO (src
)])
2367 || (HARD_REGISTER_P (dest
)
2368 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2369 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2375 struct likely_spilled_retval_info
2377 unsigned regno
, nregs
;
2381 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2382 hard registers that are known to be written to / clobbered in full. */
2384 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2386 struct likely_spilled_retval_info
*const info
=
2387 (struct likely_spilled_retval_info
*) data
;
2388 unsigned regno
, nregs
;
2391 if (!REG_P (XEXP (set
, 0)))
2394 if (regno
>= info
->regno
+ info
->nregs
)
2396 nregs
= REG_NREGS (x
);
2397 if (regno
+ nregs
<= info
->regno
)
2399 new_mask
= (2U << (nregs
- 1)) - 1;
2400 if (regno
< info
->regno
)
2401 new_mask
>>= info
->regno
- regno
;
2403 new_mask
<<= regno
- info
->regno
;
2404 info
->mask
&= ~new_mask
;
2407 /* Return nonzero iff part of the return value is live during INSN, and
2408 it is likely spilled. This can happen when more than one insn is needed
2409 to copy the return value, e.g. when we consider to combine into the
2410 second copy insn for a complex value. */
2413 likely_spilled_retval_p (rtx_insn
*insn
)
2415 rtx_insn
*use
= BB_END (this_basic_block
);
2418 unsigned regno
, nregs
;
2419 /* We assume here that no machine mode needs more than
2420 32 hard registers when the value overlaps with a register
2421 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2423 struct likely_spilled_retval_info info
;
2425 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2427 reg
= XEXP (PATTERN (use
), 0);
2428 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2430 regno
= REGNO (reg
);
2431 nregs
= REG_NREGS (reg
);
2434 mask
= (2U << (nregs
- 1)) - 1;
2436 /* Disregard parts of the return value that are set later. */
2440 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2442 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2445 /* Check if any of the (probably) live return value registers is
2450 if ((mask
& 1 << nregs
)
2451 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2457 /* Adjust INSN after we made a change to its destination.
2459 Changing the destination can invalidate notes that say something about
2460 the results of the insn and a LOG_LINK pointing to the insn. */
2463 adjust_for_new_dest (rtx_insn
*insn
)
2465 /* For notes, be conservative and simply remove them. */
2466 remove_reg_equal_equiv_notes (insn
);
2468 /* The new insn will have a destination that was previously the destination
2469 of an insn just above it. Call distribute_links to make a LOG_LINK from
2470 the next use of that destination. */
2472 rtx set
= single_set (insn
);
2475 rtx reg
= SET_DEST (set
);
2477 while (GET_CODE (reg
) == ZERO_EXTRACT
2478 || GET_CODE (reg
) == STRICT_LOW_PART
2479 || GET_CODE (reg
) == SUBREG
)
2480 reg
= XEXP (reg
, 0);
2481 gcc_assert (REG_P (reg
));
2483 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2485 df_insn_rescan (insn
);
2488 /* Return TRUE if combine can reuse reg X in mode MODE.
2489 ADDED_SETS is nonzero if the original set is still required. */
2491 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2498 /* Don't change between modes with different underlying register sizes,
2499 since this could lead to invalid subregs. */
2500 if (maybe_ne (REGMODE_NATURAL_SIZE (mode
),
2501 REGMODE_NATURAL_SIZE (GET_MODE (x
))))
2505 /* Allow hard registers if the new mode is legal, and occupies no more
2506 registers than the old mode. */
2507 if (regno
< FIRST_PSEUDO_REGISTER
)
2508 return (targetm
.hard_regno_mode_ok (regno
, mode
)
2509 && REG_NREGS (x
) >= hard_regno_nregs (regno
, mode
));
2511 /* Or a pseudo that is only used once. */
2512 return (regno
< reg_n_sets_max
2513 && REG_N_SETS (regno
) == 1
2515 && !REG_USERVAR_P (x
));
2519 /* Check whether X, the destination of a set, refers to part of
2520 the register specified by REG. */
2523 reg_subword_p (rtx x
, rtx reg
)
2525 /* Check that reg is an integer mode register. */
2526 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2529 if (GET_CODE (x
) == STRICT_LOW_PART
2530 || GET_CODE (x
) == ZERO_EXTRACT
)
2533 return GET_CODE (x
) == SUBREG
2534 && SUBREG_REG (x
) == reg
2535 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2538 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2539 Note that the INSN should be deleted *after* removing dead edges, so
2540 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2541 but not for a (set (pc) (label_ref FOO)). */
2544 update_cfg_for_uncondjump (rtx_insn
*insn
)
2546 basic_block bb
= BLOCK_FOR_INSN (insn
);
2547 gcc_assert (BB_END (bb
) == insn
);
2549 purge_dead_edges (bb
);
2552 if (EDGE_COUNT (bb
->succs
) == 1)
2556 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2558 /* Remove barriers from the footer if there are any. */
2559 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2560 if (BARRIER_P (insn
))
2562 if (PREV_INSN (insn
))
2563 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2565 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2566 if (NEXT_INSN (insn
))
2567 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2569 else if (LABEL_P (insn
))
2574 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2575 by an arbitrary number of CLOBBERs. */
2577 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2579 if (GET_CODE (pat
) != PARALLEL
)
2582 int len
= XVECLEN (pat
, 0);
2587 for (i
= 0; i
< n
; i
++)
2588 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2589 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2591 for ( ; i
< len
; i
++)
2592 switch (GET_CODE (XVECEXP (pat
, 0, i
)))
2595 if (XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2606 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2607 CLOBBERs), can be split into individual SETs in that order, without
2608 changing semantics. */
2610 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2612 if (!insn_nothrow_p (insn
))
2615 rtx pat
= PATTERN (insn
);
2618 for (i
= 0; i
< n
; i
++)
2620 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2623 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2625 for (j
= i
+ 1; j
< n
; j
++)
2626 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2633 /* Return whether X is just a single set, with the source
2634 a general_operand. */
2636 is_just_move (rtx x
)
2641 return (GET_CODE (x
) == SET
&& general_operand (SET_SRC (x
), VOIDmode
));
2644 /* Try to combine the insns I0, I1 and I2 into I3.
2645 Here I0, I1 and I2 appear earlier than I3.
2646 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2649 If we are combining more than two insns and the resulting insn is not
2650 recognized, try splitting it into two insns. If that happens, I2 and I3
2651 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2652 Otherwise, I0, I1 and I2 are pseudo-deleted.
2654 Return 0 if the combination does not work. Then nothing is changed.
2655 If we did the combination, return the insn at which combine should
2658 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2659 new direct jump instruction.
2661 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2662 been I3 passed to an earlier try_combine within the same basic
2666 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2667 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2669 /* New patterns for I3 and I2, respectively. */
2670 rtx newpat
, newi2pat
= 0;
2671 rtvec newpat_vec_with_clobbers
= 0;
2672 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2673 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2675 int added_sets_0
, added_sets_1
, added_sets_2
;
2676 /* Total number of SETs to put into I3. */
2678 /* Nonzero if I2's or I1's body now appears in I3. */
2679 int i2_is_used
= 0, i1_is_used
= 0;
2680 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2681 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2682 /* Contains I3 if the destination of I3 is used in its source, which means
2683 that the old life of I3 is being killed. If that usage is placed into
2684 I2 and not in I3, a REG_DEAD note must be made. */
2685 rtx i3dest_killed
= 0;
2686 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2687 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2688 /* Copy of SET_SRC of I1 and I0, if needed. */
2689 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2690 /* Set if I2DEST was reused as a scratch register. */
2691 bool i2scratch
= false;
2692 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2693 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2694 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2695 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2696 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2697 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2698 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2699 /* Notes that must be added to REG_NOTES in I3 and I2. */
2700 rtx new_i3_notes
, new_i2_notes
;
2701 /* Notes that we substituted I3 into I2 instead of the normal case. */
2702 int i3_subst_into_i2
= 0;
2703 /* Notes that I1, I2 or I3 is a MULT operation. */
2707 int changed_i3_dest
= 0;
2708 bool i2_was_move
= false, i3_was_move
= false;
2711 rtx_insn
*temp_insn
;
2713 struct insn_link
*link
;
2715 rtx new_other_notes
;
2717 scalar_int_mode dest_mode
, temp_mode
;
2719 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2721 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2724 /* Only try four-insn combinations when there's high likelihood of
2725 success. Look for simple insns, such as loads of constants or
2726 binary operations involving a constant. */
2734 if (!flag_expensive_optimizations
)
2737 for (i
= 0; i
< 4; i
++)
2739 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2740 rtx set
= single_set (insn
);
2744 src
= SET_SRC (set
);
2745 if (CONSTANT_P (src
))
2750 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2752 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2753 || GET_CODE (src
) == LSHIFTRT
)
2757 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2758 are likely manipulating its value. Ideally we'll be able to combine
2759 all four insns into a bitfield insertion of some kind.
2761 Note the source in I0 might be inside a sign/zero extension and the
2762 memory modes in I0 and I3 might be different. So extract the address
2763 from the destination of I3 and search for it in the source of I0.
2765 In the event that there's a match but the source/dest do not actually
2766 refer to the same memory, the worst that happens is we try some
2767 combinations that we wouldn't have otherwise. */
2768 if ((set0
= single_set (i0
))
2769 /* Ensure the source of SET0 is a MEM, possibly buried inside
2771 && (GET_CODE (SET_SRC (set0
)) == MEM
2772 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2773 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2774 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2775 && (set3
= single_set (i3
))
2776 /* Ensure the destination of SET3 is a MEM. */
2777 && GET_CODE (SET_DEST (set3
)) == MEM
2778 /* Would it be better to extract the base address for the MEM
2779 in SET3 and look for that? I don't have cases where it matters
2780 but I could envision such cases. */
2781 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2784 if (ngood
< 2 && nshift
< 2)
2788 /* Exit early if one of the insns involved can't be used for
2791 || (i1
&& CALL_P (i1
))
2792 || (i0
&& CALL_P (i0
))
2793 || cant_combine_insn_p (i3
)
2794 || cant_combine_insn_p (i2
)
2795 || (i1
&& cant_combine_insn_p (i1
))
2796 || (i0
&& cant_combine_insn_p (i0
))
2797 || likely_spilled_retval_p (i3
))
2801 undobuf
.other_insn
= 0;
2803 /* Reset the hard register usage information. */
2804 CLEAR_HARD_REG_SET (newpat_used_regs
);
2806 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2809 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2810 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2812 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2813 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2815 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2816 INSN_UID (i2
), INSN_UID (i3
));
2819 dump_insn_slim (dump_file
, i0
);
2821 dump_insn_slim (dump_file
, i1
);
2822 dump_insn_slim (dump_file
, i2
);
2823 dump_insn_slim (dump_file
, i3
);
2826 /* If multiple insns feed into one of I2 or I3, they can be in any
2827 order. To simplify the code below, reorder them in sequence. */
2828 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2830 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2832 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2835 added_links_insn
= 0;
2836 added_notes_insn
= 0;
2838 /* First check for one important special case that the code below will
2839 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2840 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2841 we may be able to replace that destination with the destination of I3.
2842 This occurs in the common code where we compute both a quotient and
2843 remainder into a structure, in which case we want to do the computation
2844 directly into the structure to avoid register-register copies.
2846 Note that this case handles both multiple sets in I2 and also cases
2847 where I2 has a number of CLOBBERs inside the PARALLEL.
2849 We make very conservative checks below and only try to handle the
2850 most common cases of this. For example, we only handle the case
2851 where I2 and I3 are adjacent to avoid making difficult register
2854 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2855 && REG_P (SET_SRC (PATTERN (i3
)))
2856 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2857 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2858 && GET_CODE (PATTERN (i2
)) == PARALLEL
2859 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2860 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2861 below would need to check what is inside (and reg_overlap_mentioned_p
2862 doesn't support those codes anyway). Don't allow those destinations;
2863 the resulting insn isn't likely to be recognized anyway. */
2864 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2865 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2866 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2867 SET_DEST (PATTERN (i3
)))
2868 && next_active_insn (i2
) == i3
)
2870 rtx p2
= PATTERN (i2
);
2872 /* Make sure that the destination of I3,
2873 which we are going to substitute into one output of I2,
2874 is not used within another output of I2. We must avoid making this:
2875 (parallel [(set (mem (reg 69)) ...)
2876 (set (reg 69) ...)])
2877 which is not well-defined as to order of actions.
2878 (Besides, reload can't handle output reloads for this.)
2880 The problem can also happen if the dest of I3 is a memory ref,
2881 if another dest in I2 is an indirect memory ref.
2883 Neither can this PARALLEL be an asm. We do not allow combining
2884 that usually (see can_combine_p), so do not here either. */
2886 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2888 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2889 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
2890 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER_HIGH
)
2891 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2892 SET_DEST (XVECEXP (p2
, 0, i
))))
2894 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2895 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2900 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2901 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2902 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2907 subst_low_luid
= DF_INSN_LUID (i2
);
2909 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2910 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2911 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2912 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2914 /* Replace the dest in I2 with our dest and make the resulting
2915 insn the new pattern for I3. Then skip to where we validate
2916 the pattern. Everything was set up above. */
2917 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2919 i3_subst_into_i2
= 1;
2920 goto validate_replacement
;
2924 /* If I2 is setting a pseudo to a constant and I3 is setting some
2925 sub-part of it to another constant, merge them by making a new
2928 && (temp_expr
= single_set (i2
)) != 0
2929 && is_a
<scalar_int_mode
> (GET_MODE (SET_DEST (temp_expr
)), &temp_mode
)
2930 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2931 && GET_CODE (PATTERN (i3
)) == SET
2932 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2933 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2935 rtx dest
= SET_DEST (PATTERN (i3
));
2936 rtx temp_dest
= SET_DEST (temp_expr
);
2940 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2942 if (CONST_INT_P (XEXP (dest
, 1))
2943 && CONST_INT_P (XEXP (dest
, 2))
2944 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (dest
, 0)),
2947 width
= INTVAL (XEXP (dest
, 1));
2948 offset
= INTVAL (XEXP (dest
, 2));
2949 dest
= XEXP (dest
, 0);
2950 if (BITS_BIG_ENDIAN
)
2951 offset
= GET_MODE_PRECISION (dest_mode
) - width
- offset
;
2956 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2957 dest
= XEXP (dest
, 0);
2958 if (is_a
<scalar_int_mode
> (GET_MODE (dest
), &dest_mode
))
2960 width
= GET_MODE_PRECISION (dest_mode
);
2967 /* If this is the low part, we're done. */
2968 if (subreg_lowpart_p (dest
))
2970 /* Handle the case where inner is twice the size of outer. */
2971 else if (GET_MODE_PRECISION (temp_mode
)
2972 == 2 * GET_MODE_PRECISION (dest_mode
))
2973 offset
+= GET_MODE_PRECISION (dest_mode
);
2974 /* Otherwise give up for now. */
2981 rtx inner
= SET_SRC (PATTERN (i3
));
2982 rtx outer
= SET_SRC (temp_expr
);
2984 wide_int o
= wi::insert (rtx_mode_t (outer
, temp_mode
),
2985 rtx_mode_t (inner
, dest_mode
),
2990 subst_low_luid
= DF_INSN_LUID (i2
);
2991 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2993 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2995 /* Replace the source in I2 with the new constant and make the
2996 resulting insn the new pattern for I3. Then skip to where we
2997 validate the pattern. Everything was set up above. */
2998 SUBST (SET_SRC (temp_expr
),
2999 immed_wide_int_const (o
, temp_mode
));
3001 newpat
= PATTERN (i2
);
3003 /* The dest of I3 has been replaced with the dest of I2. */
3004 changed_i3_dest
= 1;
3005 goto validate_replacement
;
3009 /* If we have no I1 and I2 looks like:
3010 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
3012 make up a dummy I1 that is
3015 (set (reg:CC X) (compare:CC Y (const_int 0)))
3017 (We can ignore any trailing CLOBBERs.)
3019 This undoes a previous combination and allows us to match a branch-and-
3022 if (!HAVE_cc0
&& i1
== 0
3023 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
3024 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
3026 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
3027 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
3028 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
3029 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
3030 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3031 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
3033 /* We make I1 with the same INSN_UID as I2. This gives it
3034 the same DF_INSN_LUID for value tracking. Our fake I1 will
3035 never appear in the insn stream so giving it the same INSN_UID
3036 as I2 will not cause a problem. */
3038 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3039 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
3041 INSN_UID (i1
) = INSN_UID (i2
);
3043 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
3044 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
3045 SET_DEST (PATTERN (i1
)));
3046 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
3047 SUBST_LINK (LOG_LINKS (i2
),
3048 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
3051 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3052 make those two SETs separate I1 and I2 insns, and make an I0 that is
3054 if (!HAVE_cc0
&& i0
== 0
3055 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
3056 && can_split_parallel_of_n_reg_sets (i2
, 2)
3057 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3058 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
)
3059 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3060 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
3062 /* If there is no I1, there is no I0 either. */
3065 /* We make I1 with the same INSN_UID as I2. This gives it
3066 the same DF_INSN_LUID for value tracking. Our fake I1 will
3067 never appear in the insn stream so giving it the same INSN_UID
3068 as I2 will not cause a problem. */
3070 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3071 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
3073 INSN_UID (i1
) = INSN_UID (i2
);
3075 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
3078 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3079 if (!can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
))
3082 fprintf (dump_file
, "Can't combine i2 into i3\n");
3086 if (i1
&& !can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
, &i1dest
, &i1src
))
3089 fprintf (dump_file
, "Can't combine i1 into i3\n");
3093 if (i0
&& !can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
, &i0dest
, &i0src
))
3096 fprintf (dump_file
, "Can't combine i0 into i3\n");
3101 /* Record whether i2 and i3 are trivial moves. */
3102 i2_was_move
= is_just_move (i2
);
3103 i3_was_move
= is_just_move (i3
);
3105 /* Record whether I2DEST is used in I2SRC and similarly for the other
3106 cases. Knowing this will help in register status updating below. */
3107 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3108 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3109 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3110 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3111 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3112 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3113 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3114 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3115 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3117 /* For the earlier insns, determine which of the subsequent ones they
3119 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3120 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3121 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3122 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3123 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3125 /* Ensure that I3's pattern can be the destination of combines. */
3126 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3127 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3128 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3129 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3136 /* See if any of the insns is a MULT operation. Unless one is, we will
3137 reject a combination that is, since it must be slower. Be conservative
3139 if (GET_CODE (i2src
) == MULT
3140 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3141 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3142 || (GET_CODE (PATTERN (i3
)) == SET
3143 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3146 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3147 We used to do this EXCEPT in one case: I3 has a post-inc in an
3148 output operand. However, that exception can give rise to insns like
3150 which is a famous insn on the PDP-11 where the value of r3 used as the
3151 source was model-dependent. Avoid this sort of thing. */
3154 if (!(GET_CODE (PATTERN (i3
)) == SET
3155 && REG_P (SET_SRC (PATTERN (i3
)))
3156 && MEM_P (SET_DEST (PATTERN (i3
)))
3157 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3158 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3159 /* It's not the exception. */
3164 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3165 if (REG_NOTE_KIND (link
) == REG_INC
3166 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3168 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3175 /* See if the SETs in I1 or I2 need to be kept around in the merged
3176 instruction: whenever the value set there is still needed past I3.
3177 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3179 For the SET in I1, we have two cases: if I1 and I2 independently feed
3180 into I3, the set in I1 needs to be kept around unless I1DEST dies
3181 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3182 in I1 needs to be kept around unless I1DEST dies or is set in either
3183 I2 or I3. The same considerations apply to I0. */
3185 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3188 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3189 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3194 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3195 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3196 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3197 && dead_or_set_p (i2
, i0dest
)));
3201 /* We are about to copy insns for the case where they need to be kept
3202 around. Check that they can be copied in the merged instruction. */
3204 if (targetm
.cannot_copy_insn_p
3205 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3206 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3207 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3213 /* If the set in I2 needs to be kept around, we must make a copy of
3214 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3215 PATTERN (I2), we are only substituting for the original I1DEST, not into
3216 an already-substituted copy. This also prevents making self-referential
3217 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3222 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3223 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3225 i2pat
= copy_rtx (PATTERN (i2
));
3230 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3231 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3233 i1pat
= copy_rtx (PATTERN (i1
));
3238 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3239 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3241 i0pat
= copy_rtx (PATTERN (i0
));
3246 /* Substitute in the latest insn for the regs set by the earlier ones. */
3248 maxreg
= max_reg_num ();
3252 /* Many machines that don't use CC0 have insns that can both perform an
3253 arithmetic operation and set the condition code. These operations will
3254 be represented as a PARALLEL with the first element of the vector
3255 being a COMPARE of an arithmetic operation with the constant zero.
3256 The second element of the vector will set some pseudo to the result
3257 of the same arithmetic operation. If we simplify the COMPARE, we won't
3258 match such a pattern and so will generate an extra insn. Here we test
3259 for this case, where both the comparison and the operation result are
3260 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3261 I2SRC. Later we will make the PARALLEL that contains I2. */
3263 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3264 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3265 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3266 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3269 rtx
*cc_use_loc
= NULL
;
3270 rtx_insn
*cc_use_insn
= NULL
;
3271 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3272 machine_mode compare_mode
, orig_compare_mode
;
3273 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3274 scalar_int_mode mode
;
3276 newpat
= PATTERN (i3
);
3277 newpat_dest
= SET_DEST (newpat
);
3278 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3280 if (undobuf
.other_insn
== 0
3281 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3284 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3285 if (is_a
<scalar_int_mode
> (GET_MODE (i2dest
), &mode
))
3286 compare_code
= simplify_compare_const (compare_code
, mode
,
3288 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3291 /* Do the rest only if op1 is const0_rtx, which may be the
3292 result of simplification. */
3293 if (op1
== const0_rtx
)
3295 /* If a single use of the CC is found, prepare to modify it
3296 when SELECT_CC_MODE returns a new CC-class mode, or when
3297 the above simplify_compare_const() returned a new comparison
3298 operator. undobuf.other_insn is assigned the CC use insn
3299 when modifying it. */
3302 #ifdef SELECT_CC_MODE
3303 machine_mode new_mode
3304 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3305 if (new_mode
!= orig_compare_mode
3306 && can_change_dest_mode (SET_DEST (newpat
),
3307 added_sets_2
, new_mode
))
3309 unsigned int regno
= REGNO (newpat_dest
);
3310 compare_mode
= new_mode
;
3311 if (regno
< FIRST_PSEUDO_REGISTER
)
3312 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3315 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3316 newpat_dest
= regno_reg_rtx
[regno
];
3320 /* Cases for modifying the CC-using comparison. */
3321 if (compare_code
!= orig_compare_code
3322 /* ??? Do we need to verify the zero rtx? */
3323 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3325 /* Replace cc_use_loc with entire new RTX. */
3327 gen_rtx_fmt_ee (compare_code
, GET_MODE (*cc_use_loc
),
3328 newpat_dest
, const0_rtx
));
3329 undobuf
.other_insn
= cc_use_insn
;
3331 else if (compare_mode
!= orig_compare_mode
)
3333 /* Just replace the CC reg with a new mode. */
3334 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3335 undobuf
.other_insn
= cc_use_insn
;
3339 /* Now we modify the current newpat:
3340 First, SET_DEST(newpat) is updated if the CC mode has been
3341 altered. For targets without SELECT_CC_MODE, this should be
3343 if (compare_mode
!= orig_compare_mode
)
3344 SUBST (SET_DEST (newpat
), newpat_dest
);
3345 /* This is always done to propagate i2src into newpat. */
3346 SUBST (SET_SRC (newpat
),
3347 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3348 /* Create new version of i2pat if needed; the below PARALLEL
3349 creation needs this to work correctly. */
3350 if (! rtx_equal_p (i2src
, op0
))
3351 i2pat
= gen_rtx_SET (i2dest
, op0
);
3356 if (i2_is_used
== 0)
3358 /* It is possible that the source of I2 or I1 may be performing
3359 an unneeded operation, such as a ZERO_EXTEND of something
3360 that is known to have the high part zero. Handle that case
3361 by letting subst look at the inner insns.
3363 Another way to do this would be to have a function that tries
3364 to simplify a single insn instead of merging two or more
3365 insns. We don't do this because of the potential of infinite
3366 loops and because of the potential extra memory required.
3367 However, doing it the way we are is a bit of a kludge and
3368 doesn't catch all cases.
3370 But only do this if -fexpensive-optimizations since it slows
3371 things down and doesn't usually win.
3373 This is not done in the COMPARE case above because the
3374 unmodified I2PAT is used in the PARALLEL and so a pattern
3375 with a modified I2SRC would not match. */
3377 if (flag_expensive_optimizations
)
3379 /* Pass pc_rtx so no substitutions are done, just
3383 subst_low_luid
= DF_INSN_LUID (i1
);
3384 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3387 subst_low_luid
= DF_INSN_LUID (i2
);
3388 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3391 n_occurrences
= 0; /* `subst' counts here */
3392 subst_low_luid
= DF_INSN_LUID (i2
);
3394 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3395 copy of I2SRC each time we substitute it, in order to avoid creating
3396 self-referential RTL when we will be substituting I1SRC for I1DEST
3397 later. Likewise if I0 feeds into I2, either directly or indirectly
3398 through I1, and I0DEST is in I0SRC. */
3399 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3400 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3401 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3402 && i0dest_in_i0src
));
3405 /* Record whether I2's body now appears within I3's body. */
3406 i2_is_used
= n_occurrences
;
3409 /* If we already got a failure, don't try to do more. Otherwise, try to
3410 substitute I1 if we have it. */
3412 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3414 /* Check that an autoincrement side-effect on I1 has not been lost.
3415 This happens if I1DEST is mentioned in I2 and dies there, and
3416 has disappeared from the new pattern. */
3417 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3419 && dead_or_set_p (i2
, i1dest
)
3420 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3421 /* Before we can do this substitution, we must redo the test done
3422 above (see detailed comments there) that ensures I1DEST isn't
3423 mentioned in any SETs in NEWPAT that are field assignments. */
3424 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3432 subst_low_luid
= DF_INSN_LUID (i1
);
3434 /* If the following substitution will modify I1SRC, make a copy of it
3435 for the case where it is substituted for I1DEST in I2PAT later. */
3436 if (added_sets_2
&& i1_feeds_i2_n
)
3437 i1src_copy
= copy_rtx (i1src
);
3439 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3440 copy of I1SRC each time we substitute it, in order to avoid creating
3441 self-referential RTL when we will be substituting I0SRC for I0DEST
3443 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3444 i0_feeds_i1_n
&& i0dest_in_i0src
);
3447 /* Record whether I1's body now appears within I3's body. */
3448 i1_is_used
= n_occurrences
;
3451 /* Likewise for I0 if we have it. */
3453 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3455 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3456 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3457 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3458 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3459 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3466 /* If the following substitution will modify I0SRC, make a copy of it
3467 for the case where it is substituted for I0DEST in I1PAT later. */
3468 if (added_sets_1
&& i0_feeds_i1_n
)
3469 i0src_copy
= copy_rtx (i0src
);
3470 /* And a copy for I0DEST in I2PAT substitution. */
3471 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3472 || (i0_feeds_i2_n
)))
3473 i0src_copy2
= copy_rtx (i0src
);
3476 subst_low_luid
= DF_INSN_LUID (i0
);
3477 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3481 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3482 to count all the ways that I2SRC and I1SRC can be used. */
3483 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3484 && i2_is_used
+ added_sets_2
> 1)
3485 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3486 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3488 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3489 && (n_occurrences
+ added_sets_0
3490 + (added_sets_1
&& i0_feeds_i1_n
)
3491 + (added_sets_2
&& i0_feeds_i2_n
)
3493 /* Fail if we tried to make a new register. */
3494 || max_reg_num () != maxreg
3495 /* Fail if we couldn't do something and have a CLOBBER. */
3496 || GET_CODE (newpat
) == CLOBBER
3497 /* Fail if this new pattern is a MULT and we didn't have one before
3498 at the outer level. */
3499 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3506 /* If the actions of the earlier insns must be kept
3507 in addition to substituting them into the latest one,
3508 we must make a new PARALLEL for the latest insn
3509 to hold additional the SETs. */
3511 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3513 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3516 if (GET_CODE (newpat
) == PARALLEL
)
3518 rtvec old
= XVEC (newpat
, 0);
3519 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3520 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3521 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3522 sizeof (old
->elem
[0]) * old
->num_elem
);
3527 total_sets
= 1 + extra_sets
;
3528 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3529 XVECEXP (newpat
, 0, 0) = old
;
3533 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3539 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3541 XVECEXP (newpat
, 0, --total_sets
) = t
;
3547 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3548 i0_feeds_i1_n
&& i0dest_in_i0src
);
3549 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3550 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3552 XVECEXP (newpat
, 0, --total_sets
) = t
;
3556 validate_replacement
:
3558 /* Note which hard regs this insn has as inputs. */
3559 mark_used_regs_combine (newpat
);
3561 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3562 consider splitting this pattern, we might need these clobbers. */
3563 if (i1
&& GET_CODE (newpat
) == PARALLEL
3564 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3566 int len
= XVECLEN (newpat
, 0);
3568 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3569 for (i
= 0; i
< len
; i
++)
3570 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3573 /* We have recognized nothing yet. */
3574 insn_code_number
= -1;
3576 /* See if this is a PARALLEL of two SETs where one SET's destination is
3577 a register that is unused and this isn't marked as an instruction that
3578 might trap in an EH region. In that case, we just need the other SET.
3579 We prefer this over the PARALLEL.
3581 This can occur when simplifying a divmod insn. We *must* test for this
3582 case here because the code below that splits two independent SETs doesn't
3583 handle this case correctly when it updates the register status.
3585 It's pointless doing this if we originally had two sets, one from
3586 i3, and one from i2. Combining then splitting the parallel results
3587 in the original i2 again plus an invalid insn (which we delete).
3588 The net effect is only to move instructions around, which makes
3589 debug info less accurate.
3591 If the remaining SET came from I2 its destination should not be used
3592 between I2 and I3. See PR82024. */
3594 if (!(added_sets_2
&& i1
== 0)
3595 && is_parallel_of_n_reg_sets (newpat
, 2)
3596 && asm_noperands (newpat
) < 0)
3598 rtx set0
= XVECEXP (newpat
, 0, 0);
3599 rtx set1
= XVECEXP (newpat
, 0, 1);
3600 rtx oldpat
= newpat
;
3602 if (((REG_P (SET_DEST (set1
))
3603 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3604 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3605 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3606 && insn_nothrow_p (i3
)
3607 && !side_effects_p (SET_SRC (set1
)))
3610 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3613 else if (((REG_P (SET_DEST (set0
))
3614 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3615 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3616 && find_reg_note (i3
, REG_UNUSED
,
3617 SUBREG_REG (SET_DEST (set0
)))))
3618 && insn_nothrow_p (i3
)
3619 && !side_effects_p (SET_SRC (set0
)))
3621 rtx dest
= SET_DEST (set1
);
3622 if (GET_CODE (dest
) == SUBREG
)
3623 dest
= SUBREG_REG (dest
);
3624 if (!reg_used_between_p (dest
, i2
, i3
))
3627 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3629 if (insn_code_number
>= 0)
3630 changed_i3_dest
= 1;
3634 if (insn_code_number
< 0)
3638 /* Is the result of combination a valid instruction? */
3639 if (insn_code_number
< 0)
3640 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3642 /* If we were combining three insns and the result is a simple SET
3643 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3644 insns. There are two ways to do this. It can be split using a
3645 machine-specific method (like when you have an addition of a large
3646 constant) or by combine in the function find_split_point. */
3648 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3649 && asm_noperands (newpat
) < 0)
3651 rtx parallel
, *split
;
3652 rtx_insn
*m_split_insn
;
3654 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3655 use I2DEST as a scratch register will help. In the latter case,
3656 convert I2DEST to the mode of the source of NEWPAT if we can. */
3658 m_split_insn
= combine_split_insns (newpat
, i3
);
3660 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3661 inputs of NEWPAT. */
3663 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3664 possible to try that as a scratch reg. This would require adding
3665 more code to make it work though. */
3667 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3669 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3671 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3672 (temporarily, until we are committed to this instruction
3673 combination) does not work: for example, any call to nonzero_bits
3674 on the register (from a splitter in the MD file, for example)
3675 will get the old information, which is invalid.
3677 Since nowadays we can create registers during combine just fine,
3678 we should just create a new one here, not reuse i2dest. */
3680 /* First try to split using the original register as a
3681 scratch register. */
3682 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3683 gen_rtvec (2, newpat
,
3684 gen_rtx_CLOBBER (VOIDmode
,
3686 m_split_insn
= combine_split_insns (parallel
, i3
);
3688 /* If that didn't work, try changing the mode of I2DEST if
3690 if (m_split_insn
== 0
3691 && new_mode
!= GET_MODE (i2dest
)
3692 && new_mode
!= VOIDmode
3693 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3695 machine_mode old_mode
= GET_MODE (i2dest
);
3698 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3699 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3702 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3703 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3706 parallel
= (gen_rtx_PARALLEL
3708 gen_rtvec (2, newpat
,
3709 gen_rtx_CLOBBER (VOIDmode
,
3711 m_split_insn
= combine_split_insns (parallel
, i3
);
3713 if (m_split_insn
== 0
3714 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3718 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3719 buf
= undobuf
.undos
;
3720 undobuf
.undos
= buf
->next
;
3721 buf
->next
= undobuf
.frees
;
3722 undobuf
.frees
= buf
;
3726 i2scratch
= m_split_insn
!= 0;
3729 /* If recog_for_combine has discarded clobbers, try to use them
3730 again for the split. */
3731 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3733 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3734 m_split_insn
= combine_split_insns (parallel
, i3
);
3737 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3739 rtx m_split_pat
= PATTERN (m_split_insn
);
3740 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3741 if (insn_code_number
>= 0)
3742 newpat
= m_split_pat
;
3744 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3745 && (next_nonnote_nondebug_insn (i2
) == i3
3746 || !modified_between_p (PATTERN (m_split_insn
), i2
, i3
)))
3749 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3750 newi2pat
= PATTERN (m_split_insn
);
3752 i3set
= single_set (NEXT_INSN (m_split_insn
));
3753 i2set
= single_set (m_split_insn
);
3755 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3757 /* If I2 or I3 has multiple SETs, we won't know how to track
3758 register status, so don't use these insns. If I2's destination
3759 is used between I2 and I3, we also can't use these insns. */
3761 if (i2_code_number
>= 0 && i2set
&& i3set
3762 && (next_nonnote_nondebug_insn (i2
) == i3
3763 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3764 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3766 if (insn_code_number
>= 0)
3769 /* It is possible that both insns now set the destination of I3.
3770 If so, we must show an extra use of it. */
3772 if (insn_code_number
>= 0)
3774 rtx new_i3_dest
= SET_DEST (i3set
);
3775 rtx new_i2_dest
= SET_DEST (i2set
);
3777 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3778 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3779 || GET_CODE (new_i3_dest
) == SUBREG
)
3780 new_i3_dest
= XEXP (new_i3_dest
, 0);
3782 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3783 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3784 || GET_CODE (new_i2_dest
) == SUBREG
)
3785 new_i2_dest
= XEXP (new_i2_dest
, 0);
3787 if (REG_P (new_i3_dest
)
3788 && REG_P (new_i2_dest
)
3789 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3790 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3791 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3795 /* If we can split it and use I2DEST, go ahead and see if that
3796 helps things be recognized. Verify that none of the registers
3797 are set between I2 and I3. */
3798 if (insn_code_number
< 0
3799 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3800 && (!HAVE_cc0
|| REG_P (i2dest
))
3801 /* We need I2DEST in the proper mode. If it is a hard register
3802 or the only use of a pseudo, we can change its mode.
3803 Make sure we don't change a hard register to have a mode that
3804 isn't valid for it, or change the number of registers. */
3805 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3806 || GET_MODE (*split
) == VOIDmode
3807 || can_change_dest_mode (i2dest
, added_sets_2
,
3809 && (next_nonnote_nondebug_insn (i2
) == i3
3810 || !modified_between_p (*split
, i2
, i3
))
3811 /* We can't overwrite I2DEST if its value is still used by
3813 && ! reg_referenced_p (i2dest
, newpat
))
3815 rtx newdest
= i2dest
;
3816 enum rtx_code split_code
= GET_CODE (*split
);
3817 machine_mode split_mode
= GET_MODE (*split
);
3818 bool subst_done
= false;
3819 newi2pat
= NULL_RTX
;
3823 /* *SPLIT may be part of I2SRC, so make sure we have the
3824 original expression around for later debug processing.
3825 We should not need I2SRC any more in other cases. */
3826 if (MAY_HAVE_DEBUG_BIND_INSNS
)
3827 i2src
= copy_rtx (i2src
);
3831 /* Get NEWDEST as a register in the proper mode. We have already
3832 validated that we can do this. */
3833 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3835 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3836 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3839 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3840 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3844 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3845 an ASHIFT. This can occur if it was inside a PLUS and hence
3846 appeared to be a memory address. This is a kludge. */
3847 if (split_code
== MULT
3848 && CONST_INT_P (XEXP (*split
, 1))
3849 && INTVAL (XEXP (*split
, 1)) > 0
3850 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3852 rtx i_rtx
= gen_int_shift_amount (split_mode
, i
);
3853 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3854 XEXP (*split
, 0), i_rtx
));
3855 /* Update split_code because we may not have a multiply
3857 split_code
= GET_CODE (*split
);
3860 /* Similarly for (plus (mult FOO (const_int pow2))). */
3861 if (split_code
== PLUS
3862 && GET_CODE (XEXP (*split
, 0)) == MULT
3863 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3864 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3865 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3867 rtx nsplit
= XEXP (*split
, 0);
3868 rtx i_rtx
= gen_int_shift_amount (GET_MODE (nsplit
), i
);
3869 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3872 /* Update split_code because we may not have a multiply
3874 split_code
= GET_CODE (*split
);
3877 #ifdef INSN_SCHEDULING
3878 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3879 be written as a ZERO_EXTEND. */
3880 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3882 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3883 what it really is. */
3884 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3886 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3887 SUBREG_REG (*split
)));
3889 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3890 SUBREG_REG (*split
)));
3894 /* Attempt to split binary operators using arithmetic identities. */
3895 if (BINARY_P (SET_SRC (newpat
))
3896 && split_mode
== GET_MODE (SET_SRC (newpat
))
3897 && ! side_effects_p (SET_SRC (newpat
)))
3899 rtx setsrc
= SET_SRC (newpat
);
3900 machine_mode mode
= GET_MODE (setsrc
);
3901 enum rtx_code code
= GET_CODE (setsrc
);
3902 rtx src_op0
= XEXP (setsrc
, 0);
3903 rtx src_op1
= XEXP (setsrc
, 1);
3905 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3906 if (rtx_equal_p (src_op0
, src_op1
))
3908 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3909 SUBST (XEXP (setsrc
, 0), newdest
);
3910 SUBST (XEXP (setsrc
, 1), newdest
);
3913 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3914 else if ((code
== PLUS
|| code
== MULT
)
3915 && GET_CODE (src_op0
) == code
3916 && GET_CODE (XEXP (src_op0
, 0)) == code
3917 && (INTEGRAL_MODE_P (mode
)
3918 || (FLOAT_MODE_P (mode
)
3919 && flag_unsafe_math_optimizations
)))
3921 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3922 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3923 rtx r
= XEXP (src_op0
, 1);
3926 /* Split both "((X op Y) op X) op Y" and
3927 "((X op Y) op Y) op X" as "T op T" where T is
3929 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3930 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3932 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3933 SUBST (XEXP (setsrc
, 0), newdest
);
3934 SUBST (XEXP (setsrc
, 1), newdest
);
3937 /* Split "((X op X) op Y) op Y)" as "T op T" where
3939 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3941 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3942 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3943 SUBST (XEXP (setsrc
, 0), newdest
);
3944 SUBST (XEXP (setsrc
, 1), newdest
);
3952 newi2pat
= gen_rtx_SET (newdest
, *split
);
3953 SUBST (*split
, newdest
);
3956 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3958 /* recog_for_combine might have added CLOBBERs to newi2pat.
3959 Make sure NEWPAT does not depend on the clobbered regs. */
3960 if (GET_CODE (newi2pat
) == PARALLEL
)
3961 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3962 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3964 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3965 if (reg_overlap_mentioned_p (reg
, newpat
))
3972 /* If the split point was a MULT and we didn't have one before,
3973 don't use one now. */
3974 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3975 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3979 /* Check for a case where we loaded from memory in a narrow mode and
3980 then sign extended it, but we need both registers. In that case,
3981 we have a PARALLEL with both loads from the same memory location.
3982 We can split this into a load from memory followed by a register-register
3983 copy. This saves at least one insn, more if register allocation can
3986 We cannot do this if the destination of the first assignment is a
3987 condition code register or cc0. We eliminate this case by making sure
3988 the SET_DEST and SET_SRC have the same mode.
3990 We cannot do this if the destination of the second assignment is
3991 a register that we have already assumed is zero-extended. Similarly
3992 for a SUBREG of such a register. */
3994 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3995 && GET_CODE (newpat
) == PARALLEL
3996 && XVECLEN (newpat
, 0) == 2
3997 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3998 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3999 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
4000 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
4001 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
4002 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
4003 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
4004 && !modified_between_p (SET_SRC (XVECEXP (newpat
, 0, 1)), i2
, i3
)
4005 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
4006 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
4007 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
4009 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
4010 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
4012 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
4014 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
4015 != GET_MODE_MASK (word_mode
))))
4016 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
4017 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
4019 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
4020 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
4022 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
4024 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
4025 != GET_MODE_MASK (word_mode
)))))
4026 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
4027 SET_SRC (XVECEXP (newpat
, 0, 1)))
4028 && ! find_reg_note (i3
, REG_UNUSED
,
4029 SET_DEST (XVECEXP (newpat
, 0, 0))))
4033 newi2pat
= XVECEXP (newpat
, 0, 0);
4034 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
4035 newpat
= XVECEXP (newpat
, 0, 1);
4036 SUBST (SET_SRC (newpat
),
4037 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
4038 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4040 if (i2_code_number
>= 0)
4041 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4043 if (insn_code_number
>= 0)
4047 /* Similarly, check for a case where we have a PARALLEL of two independent
4048 SETs but we started with three insns. In this case, we can do the sets
4049 as two separate insns. This case occurs when some SET allows two
4050 other insns to combine, but the destination of that SET is still live.
4052 Also do this if we started with two insns and (at least) one of the
4053 resulting sets is a noop; this noop will be deleted later.
4055 Also do this if we started with two insns neither of which was a simple
4058 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
4059 && GET_CODE (newpat
) == PARALLEL
4060 && XVECLEN (newpat
, 0) == 2
4061 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
4062 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
4064 || set_noop_p (XVECEXP (newpat
, 0, 0))
4065 || set_noop_p (XVECEXP (newpat
, 0, 1))
4066 || (!i2_was_move
&& !i3_was_move
))
4067 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
4068 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
4069 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
4070 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
4071 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
4072 XVECEXP (newpat
, 0, 0))
4073 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
4074 XVECEXP (newpat
, 0, 1))
4075 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
4076 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
4078 rtx set0
= XVECEXP (newpat
, 0, 0);
4079 rtx set1
= XVECEXP (newpat
, 0, 1);
4081 /* Normally, it doesn't matter which of the two is done first,
4082 but the one that references cc0 can't be the second, and
4083 one which uses any regs/memory set in between i2 and i3 can't
4084 be first. The PARALLEL might also have been pre-existing in i3,
4085 so we need to make sure that we won't wrongly hoist a SET to i2
4086 that would conflict with a death note present in there, or would
4087 have its dest modified between i2 and i3. */
4088 if (!modified_between_p (SET_SRC (set1
), i2
, i3
)
4089 && !(REG_P (SET_DEST (set1
))
4090 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
4091 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
4092 && find_reg_note (i2
, REG_DEAD
,
4093 SUBREG_REG (SET_DEST (set1
))))
4094 && !modified_between_p (SET_DEST (set1
), i2
, i3
)
4095 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
4096 /* If I3 is a jump, ensure that set0 is a jump so that
4097 we do not create invalid RTL. */
4098 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
4104 else if (!modified_between_p (SET_SRC (set0
), i2
, i3
)
4105 && !(REG_P (SET_DEST (set0
))
4106 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
4107 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
4108 && find_reg_note (i2
, REG_DEAD
,
4109 SUBREG_REG (SET_DEST (set0
))))
4110 && !modified_between_p (SET_DEST (set0
), i2
, i3
)
4111 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
4112 /* If I3 is a jump, ensure that set1 is a jump so that
4113 we do not create invalid RTL. */
4114 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4126 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4128 if (i2_code_number
>= 0)
4130 /* recog_for_combine might have added CLOBBERs to newi2pat.
4131 Make sure NEWPAT does not depend on the clobbered regs. */
4132 if (GET_CODE (newi2pat
) == PARALLEL
)
4134 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4135 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4137 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4138 if (reg_overlap_mentioned_p (reg
, newpat
))
4146 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4148 if (insn_code_number
>= 0)
4153 /* If it still isn't recognized, fail and change things back the way they
4155 if ((insn_code_number
< 0
4156 /* Is the result a reasonable ASM_OPERANDS? */
4157 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4163 /* If we had to change another insn, make sure it is valid also. */
4164 if (undobuf
.other_insn
)
4166 CLEAR_HARD_REG_SET (newpat_used_regs
);
4168 other_pat
= PATTERN (undobuf
.other_insn
);
4169 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4172 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4179 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4180 they are adjacent to each other or not. */
4183 rtx_insn
*p
= prev_nonnote_insn (i3
);
4184 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4185 && sets_cc0_p (newi2pat
))
4192 /* Only allow this combination if insn_cost reports that the
4193 replacement instructions are cheaper than the originals. */
4194 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4200 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4204 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4205 if (undo
->kind
== UNDO_MODE
)
4207 rtx reg
= *undo
->where
.r
;
4208 machine_mode new_mode
= GET_MODE (reg
);
4209 machine_mode old_mode
= undo
->old_contents
.m
;
4211 /* Temporarily revert mode back. */
4212 adjust_reg_mode (reg
, old_mode
);
4214 if (reg
== i2dest
&& i2scratch
)
4216 /* If we used i2dest as a scratch register with a
4217 different mode, substitute it for the original
4218 i2src while its original mode is temporarily
4219 restored, and then clear i2scratch so that we don't
4220 do it again later. */
4221 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4224 /* Put back the new mode. */
4225 adjust_reg_mode (reg
, new_mode
);
4229 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4230 rtx_insn
*first
, *last
;
4235 last
= last_combined_insn
;
4240 last
= undobuf
.other_insn
;
4242 if (DF_INSN_LUID (last
)
4243 < DF_INSN_LUID (last_combined_insn
))
4244 last
= last_combined_insn
;
4247 /* We're dealing with a reg that changed mode but not
4248 meaning, so we want to turn it into a subreg for
4249 the new mode. However, because of REG sharing and
4250 because its mode had already changed, we have to do
4251 it in two steps. First, replace any debug uses of
4252 reg, with its original mode temporarily restored,
4253 with this copy we have created; then, replace the
4254 copy with the SUBREG of the original shared reg,
4255 once again changed to the new mode. */
4256 propagate_for_debug (first
, last
, reg
, tempreg
,
4258 adjust_reg_mode (reg
, new_mode
);
4259 propagate_for_debug (first
, last
, tempreg
,
4260 lowpart_subreg (old_mode
, reg
, new_mode
),
4266 /* If we will be able to accept this, we have made a
4267 change to the destination of I3. This requires us to
4268 do a few adjustments. */
4270 if (changed_i3_dest
)
4272 PATTERN (i3
) = newpat
;
4273 adjust_for_new_dest (i3
);
4276 /* We now know that we can do this combination. Merge the insns and
4277 update the status of registers and LOG_LINKS. */
4279 if (undobuf
.other_insn
)
4283 PATTERN (undobuf
.other_insn
) = other_pat
;
4285 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4286 ensure that they are still valid. Then add any non-duplicate
4287 notes added by recog_for_combine. */
4288 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4290 next
= XEXP (note
, 1);
4292 if ((REG_NOTE_KIND (note
) == REG_DEAD
4293 && !reg_referenced_p (XEXP (note
, 0),
4294 PATTERN (undobuf
.other_insn
)))
4295 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4296 && !reg_set_p (XEXP (note
, 0),
4297 PATTERN (undobuf
.other_insn
)))
4298 /* Simply drop equal note since it may be no longer valid
4299 for other_insn. It may be possible to record that CC
4300 register is changed and only discard those notes, but
4301 in practice it's unnecessary complication and doesn't
4302 give any meaningful improvement.
4305 || REG_NOTE_KIND (note
) == REG_EQUAL
4306 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4307 remove_note (undobuf
.other_insn
, note
);
4310 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4311 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4317 /* I3 now uses what used to be its destination and which is now
4318 I2's destination. This requires us to do a few adjustments. */
4319 PATTERN (i3
) = newpat
;
4320 adjust_for_new_dest (i3
);
4323 if (swap_i2i3
|| split_i2i3
)
4325 /* We might need a LOG_LINK from I3 to I2. But then we used to
4326 have one, so we still will.
4328 However, some later insn might be using I2's dest and have
4329 a LOG_LINK pointing at I3. We should change it to point at
4332 /* newi2pat is usually a SET here; however, recog_for_combine might
4333 have added some clobbers. */
4335 if (GET_CODE (x
) == PARALLEL
)
4336 x
= XVECEXP (newi2pat
, 0, 0);
4338 /* It can only be a SET of a REG or of a SUBREG of a REG. */
4339 unsigned int regno
= reg_or_subregno (SET_DEST (x
));
4342 for (rtx_insn
*insn
= NEXT_INSN (i3
);
4345 && NONDEBUG_INSN_P (insn
)
4346 && BLOCK_FOR_INSN (insn
) == this_basic_block
;
4347 insn
= NEXT_INSN (insn
))
4349 struct insn_link
*link
;
4350 FOR_EACH_LOG_LINK (link
, insn
)
4351 if (link
->insn
== i3
&& link
->regno
== regno
)
4361 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4362 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4365 /* Compute which registers we expect to eliminate. newi2pat may be setting
4366 either i3dest or i2dest, so we must check it. */
4367 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4368 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4371 /* For i1, we need to compute both local elimination and global
4372 elimination information with respect to newi2pat because i1dest
4373 may be the same as i3dest, in which case newi2pat may be setting
4374 i1dest. Global information is used when distributing REG_DEAD
4375 note for i2 and i3, in which case it does matter if newi2pat sets
4378 Local information is used when distributing REG_DEAD note for i1,
4379 in which case it doesn't matter if newi2pat sets i1dest or not.
4380 See PR62151, if we have four insns combination:
4382 i1: r1 <- i1src (using r0)
4384 i2: r0 <- i2src (using r1)
4385 i3: r3 <- i3src (using r0)
4387 From i1's point of view, r0 is eliminated, no matter if it is set
4388 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4389 should be discarded.
4391 Note local information only affects cases in forms like "I1->I2->I3",
4392 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4393 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4395 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4398 rtx elim_i1
= (local_elim_i1
== 0
4399 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4401 /* Same case as i1. */
4402 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4404 rtx elim_i0
= (local_elim_i0
== 0
4405 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4408 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4410 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4411 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4413 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4415 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4417 /* Ensure that we do not have something that should not be shared but
4418 occurs multiple times in the new insns. Check this by first
4419 resetting all the `used' flags and then copying anything is shared. */
4421 reset_used_flags (i3notes
);
4422 reset_used_flags (i2notes
);
4423 reset_used_flags (i1notes
);
4424 reset_used_flags (i0notes
);
4425 reset_used_flags (newpat
);
4426 reset_used_flags (newi2pat
);
4427 if (undobuf
.other_insn
)
4428 reset_used_flags (PATTERN (undobuf
.other_insn
));
4430 i3notes
= copy_rtx_if_shared (i3notes
);
4431 i2notes
= copy_rtx_if_shared (i2notes
);
4432 i1notes
= copy_rtx_if_shared (i1notes
);
4433 i0notes
= copy_rtx_if_shared (i0notes
);
4434 newpat
= copy_rtx_if_shared (newpat
);
4435 newi2pat
= copy_rtx_if_shared (newi2pat
);
4436 if (undobuf
.other_insn
)
4437 reset_used_flags (PATTERN (undobuf
.other_insn
));
4439 INSN_CODE (i3
) = insn_code_number
;
4440 PATTERN (i3
) = newpat
;
4442 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4444 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4445 link
= XEXP (link
, 1))
4449 /* I2SRC must still be meaningful at this point. Some
4450 splitting operations can invalidate I2SRC, but those
4451 operations do not apply to calls. */
4453 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4457 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4460 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4465 if (undobuf
.other_insn
)
4466 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4468 /* We had one special case above where I2 had more than one set and
4469 we replaced a destination of one of those sets with the destination
4470 of I3. In that case, we have to update LOG_LINKS of insns later
4471 in this basic block. Note that this (expensive) case is rare.
4473 Also, in this case, we must pretend that all REG_NOTEs for I2
4474 actually came from I3, so that REG_UNUSED notes from I2 will be
4475 properly handled. */
4477 if (i3_subst_into_i2
)
4479 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4480 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4481 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4482 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4483 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4484 && ! find_reg_note (i2
, REG_UNUSED
,
4485 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4486 for (temp_insn
= NEXT_INSN (i2
);
4488 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4489 || BB_HEAD (this_basic_block
) != temp_insn
);
4490 temp_insn
= NEXT_INSN (temp_insn
))
4491 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4492 FOR_EACH_LOG_LINK (link
, temp_insn
)
4493 if (link
->insn
== i2
)
4499 while (XEXP (link
, 1))
4500 link
= XEXP (link
, 1);
4501 XEXP (link
, 1) = i2notes
;
4508 LOG_LINKS (i3
) = NULL
;
4510 LOG_LINKS (i2
) = NULL
;
4515 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2scratch
)
4516 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4518 INSN_CODE (i2
) = i2_code_number
;
4519 PATTERN (i2
) = newi2pat
;
4523 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2src
)
4524 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4526 SET_INSN_DELETED (i2
);
4531 LOG_LINKS (i1
) = NULL
;
4533 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4534 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4536 SET_INSN_DELETED (i1
);
4541 LOG_LINKS (i0
) = NULL
;
4543 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4544 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4546 SET_INSN_DELETED (i0
);
4549 /* Get death notes for everything that is now used in either I3 or
4550 I2 and used to die in a previous insn. If we built two new
4551 patterns, move from I1 to I2 then I2 to I3 so that we get the
4552 proper movement on registers that I2 modifies. */
4555 from_luid
= DF_INSN_LUID (i0
);
4557 from_luid
= DF_INSN_LUID (i1
);
4559 from_luid
= DF_INSN_LUID (i2
);
4561 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4562 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4564 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4566 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4567 elim_i2
, elim_i1
, elim_i0
);
4569 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4570 elim_i2
, elim_i1
, elim_i0
);
4572 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4573 elim_i2
, local_elim_i1
, local_elim_i0
);
4575 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4576 elim_i2
, elim_i1
, local_elim_i0
);
4578 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4579 elim_i2
, elim_i1
, elim_i0
);
4581 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4582 know these are REG_UNUSED and want them to go to the desired insn,
4583 so we always pass it as i3. */
4585 if (newi2pat
&& new_i2_notes
)
4586 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4590 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4593 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4594 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4595 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4596 in that case, it might delete I2. Similarly for I2 and I1.
4597 Show an additional death due to the REG_DEAD note we make here. If
4598 we discard it in distribute_notes, we will decrement it again. */
4602 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4603 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4604 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4607 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4608 elim_i2
, elim_i1
, elim_i0
);
4611 if (i2dest_in_i2src
)
4613 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4614 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4615 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4616 NULL_RTX
, NULL_RTX
);
4618 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4619 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4622 if (i1dest_in_i1src
)
4624 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4625 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4626 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4627 NULL_RTX
, NULL_RTX
);
4629 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4630 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4633 if (i0dest_in_i0src
)
4635 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4636 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4637 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4638 NULL_RTX
, NULL_RTX
);
4640 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4641 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4644 distribute_links (i3links
);
4645 distribute_links (i2links
);
4646 distribute_links (i1links
);
4647 distribute_links (i0links
);
4651 struct insn_link
*link
;
4652 rtx_insn
*i2_insn
= 0;
4653 rtx i2_val
= 0, set
;
4655 /* The insn that used to set this register doesn't exist, and
4656 this life of the register may not exist either. See if one of
4657 I3's links points to an insn that sets I2DEST. If it does,
4658 that is now the last known value for I2DEST. If we don't update
4659 this and I2 set the register to a value that depended on its old
4660 contents, we will get confused. If this insn is used, thing
4661 will be set correctly in combine_instructions. */
4662 FOR_EACH_LOG_LINK (link
, i3
)
4663 if ((set
= single_set (link
->insn
)) != 0
4664 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4665 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4667 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4669 /* If the reg formerly set in I2 died only once and that was in I3,
4670 zero its use count so it won't make `reload' do any work. */
4672 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4673 && ! i2dest_in_i2src
4674 && REGNO (i2dest
) < reg_n_sets_max
)
4675 INC_REG_N_SETS (REGNO (i2dest
), -1);
4678 if (i1
&& REG_P (i1dest
))
4680 struct insn_link
*link
;
4681 rtx_insn
*i1_insn
= 0;
4682 rtx i1_val
= 0, set
;
4684 FOR_EACH_LOG_LINK (link
, i3
)
4685 if ((set
= single_set (link
->insn
)) != 0
4686 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4687 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4689 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4692 && ! i1dest_in_i1src
4693 && REGNO (i1dest
) < reg_n_sets_max
)
4694 INC_REG_N_SETS (REGNO (i1dest
), -1);
4697 if (i0
&& REG_P (i0dest
))
4699 struct insn_link
*link
;
4700 rtx_insn
*i0_insn
= 0;
4701 rtx i0_val
= 0, set
;
4703 FOR_EACH_LOG_LINK (link
, i3
)
4704 if ((set
= single_set (link
->insn
)) != 0
4705 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4706 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4708 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4711 && ! i0dest_in_i0src
4712 && REGNO (i0dest
) < reg_n_sets_max
)
4713 INC_REG_N_SETS (REGNO (i0dest
), -1);
4716 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4717 been made to this insn. The order is important, because newi2pat
4718 can affect nonzero_bits of newpat. */
4720 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4721 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4724 if (undobuf
.other_insn
!= NULL_RTX
)
4728 fprintf (dump_file
, "modifying other_insn ");
4729 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4731 df_insn_rescan (undobuf
.other_insn
);
4734 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4738 fprintf (dump_file
, "modifying insn i0 ");
4739 dump_insn_slim (dump_file
, i0
);
4741 df_insn_rescan (i0
);
4744 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4748 fprintf (dump_file
, "modifying insn i1 ");
4749 dump_insn_slim (dump_file
, i1
);
4751 df_insn_rescan (i1
);
4754 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4758 fprintf (dump_file
, "modifying insn i2 ");
4759 dump_insn_slim (dump_file
, i2
);
4761 df_insn_rescan (i2
);
4764 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4768 fprintf (dump_file
, "modifying insn i3 ");
4769 dump_insn_slim (dump_file
, i3
);
4771 df_insn_rescan (i3
);
4774 /* Set new_direct_jump_p if a new return or simple jump instruction
4775 has been created. Adjust the CFG accordingly. */
4776 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4778 *new_direct_jump_p
= 1;
4779 mark_jump_label (PATTERN (i3
), i3
, 0);
4780 update_cfg_for_uncondjump (i3
);
4783 if (undobuf
.other_insn
!= NULL_RTX
4784 && (returnjump_p (undobuf
.other_insn
)
4785 || any_uncondjump_p (undobuf
.other_insn
)))
4787 *new_direct_jump_p
= 1;
4788 update_cfg_for_uncondjump (undobuf
.other_insn
);
4791 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4792 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4794 basic_block bb
= BLOCK_FOR_INSN (i3
);
4796 remove_edge (split_block (bb
, i3
));
4797 emit_barrier_after_bb (bb
);
4798 *new_direct_jump_p
= 1;
4801 if (undobuf
.other_insn
4802 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4803 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4805 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4807 remove_edge (split_block (bb
, undobuf
.other_insn
));
4808 emit_barrier_after_bb (bb
);
4809 *new_direct_jump_p
= 1;
4812 /* A noop might also need cleaning up of CFG, if it comes from the
4813 simplification of a jump. */
4815 && GET_CODE (newpat
) == SET
4816 && SET_SRC (newpat
) == pc_rtx
4817 && SET_DEST (newpat
) == pc_rtx
)
4819 *new_direct_jump_p
= 1;
4820 update_cfg_for_uncondjump (i3
);
4823 if (undobuf
.other_insn
!= NULL_RTX
4824 && JUMP_P (undobuf
.other_insn
)
4825 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4826 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4827 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4829 *new_direct_jump_p
= 1;
4830 update_cfg_for_uncondjump (undobuf
.other_insn
);
4833 combine_successes
++;
4836 rtx_insn
*ret
= newi2pat
? i2
: i3
;
4837 if (added_links_insn
&& DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (ret
))
4838 ret
= added_links_insn
;
4839 if (added_notes_insn
&& DF_INSN_LUID (added_notes_insn
) < DF_INSN_LUID (ret
))
4840 ret
= added_notes_insn
;
4845 /* Get a marker for undoing to the current state. */
4848 get_undo_marker (void)
4850 return undobuf
.undos
;
4853 /* Undo the modifications up to the marker. */
4856 undo_to_marker (void *marker
)
4858 struct undo
*undo
, *next
;
4860 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4868 *undo
->where
.r
= undo
->old_contents
.r
;
4871 *undo
->where
.i
= undo
->old_contents
.i
;
4874 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4877 *undo
->where
.l
= undo
->old_contents
.l
;
4883 undo
->next
= undobuf
.frees
;
4884 undobuf
.frees
= undo
;
4887 undobuf
.undos
= (struct undo
*) marker
;
4890 /* Undo all the modifications recorded in undobuf. */
4898 /* We've committed to accepting the changes we made. Move all
4899 of the undos to the free list. */
4904 struct undo
*undo
, *next
;
4906 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4909 undo
->next
= undobuf
.frees
;
4910 undobuf
.frees
= undo
;
4915 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4916 where we have an arithmetic expression and return that point. LOC will
4919 try_combine will call this function to see if an insn can be split into
4923 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4926 enum rtx_code code
= GET_CODE (x
);
4928 unsigned HOST_WIDE_INT len
= 0;
4929 HOST_WIDE_INT pos
= 0;
4931 rtx inner
= NULL_RTX
;
4932 scalar_int_mode mode
, inner_mode
;
4934 /* First special-case some codes. */
4938 #ifdef INSN_SCHEDULING
4939 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4941 if (MEM_P (SUBREG_REG (x
)))
4944 return find_split_point (&SUBREG_REG (x
), insn
, false);
4947 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4948 using LO_SUM and HIGH. */
4949 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4950 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4952 machine_mode address_mode
= get_address_mode (x
);
4955 gen_rtx_LO_SUM (address_mode
,
4956 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4958 return &XEXP (XEXP (x
, 0), 0);
4961 /* If we have a PLUS whose second operand is a constant and the
4962 address is not valid, perhaps we can split it up using
4963 the machine-specific way to split large constants. We use
4964 the first pseudo-reg (one of the virtual regs) as a placeholder;
4965 it will not remain in the result. */
4966 if (GET_CODE (XEXP (x
, 0)) == PLUS
4967 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4968 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4969 MEM_ADDR_SPACE (x
)))
4971 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4972 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4975 /* This should have produced two insns, each of which sets our
4976 placeholder. If the source of the second is a valid address,
4977 we can put both sources together and make a split point
4981 && NEXT_INSN (seq
) != NULL_RTX
4982 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4983 && NONJUMP_INSN_P (seq
)
4984 && GET_CODE (PATTERN (seq
)) == SET
4985 && SET_DEST (PATTERN (seq
)) == reg
4986 && ! reg_mentioned_p (reg
,
4987 SET_SRC (PATTERN (seq
)))
4988 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4989 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4990 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4991 && memory_address_addr_space_p
4992 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4993 MEM_ADDR_SPACE (x
)))
4995 rtx src1
= SET_SRC (PATTERN (seq
));
4996 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4998 /* Replace the placeholder in SRC2 with SRC1. If we can
4999 find where in SRC2 it was placed, that can become our
5000 split point and we can replace this address with SRC2.
5001 Just try two obvious places. */
5003 src2
= replace_rtx (src2
, reg
, src1
);
5005 if (XEXP (src2
, 0) == src1
)
5006 split
= &XEXP (src2
, 0);
5007 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
5008 && XEXP (XEXP (src2
, 0), 0) == src1
)
5009 split
= &XEXP (XEXP (src2
, 0), 0);
5013 SUBST (XEXP (x
, 0), src2
);
5018 /* If that didn't work and we have a nested plus, like:
5019 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
5020 is valid address, try to split (REG1 * CONST1). */
5021 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
5022 && !OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 0))
5023 && OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5024 && ! (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SUBREG
5025 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x
, 0),
5028 rtx tem
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
5029 XEXP (XEXP (XEXP (x
, 0), 0), 0) = reg
;
5030 if (memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
5031 MEM_ADDR_SPACE (x
)))
5033 XEXP (XEXP (XEXP (x
, 0), 0), 0) = tem
;
5034 return &XEXP (XEXP (XEXP (x
, 0), 0), 0);
5036 XEXP (XEXP (XEXP (x
, 0), 0), 0) = tem
;
5038 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
5039 && OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 0))
5040 && !OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5041 && ! (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SUBREG
5042 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x
, 0),
5045 rtx tem
= XEXP (XEXP (XEXP (x
, 0), 0), 1);
5046 XEXP (XEXP (XEXP (x
, 0), 0), 1) = reg
;
5047 if (memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
5048 MEM_ADDR_SPACE (x
)))
5050 XEXP (XEXP (XEXP (x
, 0), 0), 1) = tem
;
5051 return &XEXP (XEXP (XEXP (x
, 0), 0), 1);
5053 XEXP (XEXP (XEXP (x
, 0), 0), 1) = tem
;
5056 /* If that didn't work, perhaps the first operand is complex and
5057 needs to be computed separately, so make a split point there.
5058 This will occur on machines that just support REG + CONST
5059 and have a constant moved through some previous computation. */
5060 if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
5061 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
5062 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
5063 return &XEXP (XEXP (x
, 0), 0);
5066 /* If we have a PLUS whose first operand is complex, try computing it
5067 separately by making a split there. */
5068 if (GET_CODE (XEXP (x
, 0)) == PLUS
5069 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
5071 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
5072 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
5073 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
5074 return &XEXP (XEXP (x
, 0), 0);
5078 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
5079 ZERO_EXTRACT, the most likely reason why this doesn't match is that
5080 we need to put the operand into a register. So split at that
5083 if (SET_DEST (x
) == cc0_rtx
5084 && GET_CODE (SET_SRC (x
)) != COMPARE
5085 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
5086 && !OBJECT_P (SET_SRC (x
))
5087 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
5088 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
5089 return &SET_SRC (x
);
5091 /* See if we can split SET_SRC as it stands. */
5092 split
= find_split_point (&SET_SRC (x
), insn
, true);
5093 if (split
&& split
!= &SET_SRC (x
))
5096 /* See if we can split SET_DEST as it stands. */
5097 split
= find_split_point (&SET_DEST (x
), insn
, false);
5098 if (split
&& split
!= &SET_DEST (x
))
5101 /* See if this is a bitfield assignment with everything constant. If
5102 so, this is an IOR of an AND, so split it into that. */
5103 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5104 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_DEST (x
), 0)),
5106 && HWI_COMPUTABLE_MODE_P (inner_mode
)
5107 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
5108 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
5109 && CONST_INT_P (SET_SRC (x
))
5110 && ((INTVAL (XEXP (SET_DEST (x
), 1))
5111 + INTVAL (XEXP (SET_DEST (x
), 2)))
5112 <= GET_MODE_PRECISION (inner_mode
))
5113 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
5115 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
5116 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
5117 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
5118 rtx dest
= XEXP (SET_DEST (x
), 0);
5119 unsigned HOST_WIDE_INT mask
5120 = (HOST_WIDE_INT_1U
<< len
) - 1;
5123 if (BITS_BIG_ENDIAN
)
5124 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5126 or_mask
= gen_int_mode (src
<< pos
, inner_mode
);
5129 simplify_gen_binary (IOR
, inner_mode
, dest
, or_mask
));
5132 rtx negmask
= gen_int_mode (~(mask
<< pos
), inner_mode
);
5134 simplify_gen_binary (IOR
, inner_mode
,
5135 simplify_gen_binary (AND
, inner_mode
,
5140 SUBST (SET_DEST (x
), dest
);
5142 split
= find_split_point (&SET_SRC (x
), insn
, true);
5143 if (split
&& split
!= &SET_SRC (x
))
5147 /* Otherwise, see if this is an operation that we can split into two.
5148 If so, try to split that. */
5149 code
= GET_CODE (SET_SRC (x
));
5154 /* If we are AND'ing with a large constant that is only a single
5155 bit and the result is only being used in a context where we
5156 need to know if it is zero or nonzero, replace it with a bit
5157 extraction. This will avoid the large constant, which might
5158 have taken more than one insn to make. If the constant were
5159 not a valid argument to the AND but took only one insn to make,
5160 this is no worse, but if it took more than one insn, it will
5163 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5164 && REG_P (XEXP (SET_SRC (x
), 0))
5165 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
5166 && REG_P (SET_DEST (x
))
5167 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
5168 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
5169 && XEXP (*split
, 0) == SET_DEST (x
)
5170 && XEXP (*split
, 1) == const0_rtx
)
5172 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
5173 XEXP (SET_SRC (x
), 0),
5174 pos
, NULL_RTX
, 1, 1, 0, 0);
5175 if (extraction
!= 0)
5177 SUBST (SET_SRC (x
), extraction
);
5178 return find_split_point (loc
, insn
, false);
5184 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5185 is known to be on, this can be converted into a NEG of a shift. */
5186 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5187 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5188 && ((pos
= exact_log2 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5189 GET_MODE (XEXP (SET_SRC (x
),
5192 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5193 rtx pos_rtx
= gen_int_shift_amount (mode
, pos
);
5196 gen_rtx_LSHIFTRT (mode
,
5197 XEXP (SET_SRC (x
), 0),
5200 split
= find_split_point (&SET_SRC (x
), insn
, true);
5201 if (split
&& split
!= &SET_SRC (x
))
5207 inner
= XEXP (SET_SRC (x
), 0);
5209 /* We can't optimize if either mode is a partial integer
5210 mode as we don't know how many bits are significant
5212 if (!is_int_mode (GET_MODE (inner
), &inner_mode
)
5213 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5217 len
= GET_MODE_PRECISION (inner_mode
);
5223 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_SRC (x
), 0)),
5225 && CONST_INT_P (XEXP (SET_SRC (x
), 1))
5226 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5228 inner
= XEXP (SET_SRC (x
), 0);
5229 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5230 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5232 if (BITS_BIG_ENDIAN
)
5233 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5234 unsignedp
= (code
== ZERO_EXTRACT
);
5243 && known_subrange_p (pos
, len
,
5244 0, GET_MODE_PRECISION (GET_MODE (inner
)))
5245 && is_a
<scalar_int_mode
> (GET_MODE (SET_SRC (x
)), &mode
))
5247 /* For unsigned, we have a choice of a shift followed by an
5248 AND or two shifts. Use two shifts for field sizes where the
5249 constant might be too large. We assume here that we can
5250 always at least get 8-bit constants in an AND insn, which is
5251 true for every current RISC. */
5253 if (unsignedp
&& len
<= 8)
5255 unsigned HOST_WIDE_INT mask
5256 = (HOST_WIDE_INT_1U
<< len
) - 1;
5257 rtx pos_rtx
= gen_int_shift_amount (mode
, pos
);
5261 (mode
, gen_lowpart (mode
, inner
), pos_rtx
),
5262 gen_int_mode (mask
, mode
)));
5264 split
= find_split_point (&SET_SRC (x
), insn
, true);
5265 if (split
&& split
!= &SET_SRC (x
))
5270 int left_bits
= GET_MODE_PRECISION (mode
) - len
- pos
;
5271 int right_bits
= GET_MODE_PRECISION (mode
) - len
;
5274 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5275 gen_rtx_ASHIFT (mode
,
5276 gen_lowpart (mode
, inner
),
5277 gen_int_shift_amount (mode
, left_bits
)),
5278 gen_int_shift_amount (mode
, right_bits
)));
5280 split
= find_split_point (&SET_SRC (x
), insn
, true);
5281 if (split
&& split
!= &SET_SRC (x
))
5286 /* See if this is a simple operation with a constant as the second
5287 operand. It might be that this constant is out of range and hence
5288 could be used as a split point. */
5289 if (BINARY_P (SET_SRC (x
))
5290 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5291 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5292 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5293 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5294 return &XEXP (SET_SRC (x
), 1);
5296 /* Finally, see if this is a simple operation with its first operand
5297 not in a register. The operation might require this operand in a
5298 register, so return it as a split point. We can always do this
5299 because if the first operand were another operation, we would have
5300 already found it as a split point. */
5301 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5302 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5303 return &XEXP (SET_SRC (x
), 0);
5309 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5310 it is better to write this as (not (ior A B)) so we can split it.
5311 Similarly for IOR. */
5312 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5315 gen_rtx_NOT (GET_MODE (x
),
5316 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5318 XEXP (XEXP (x
, 0), 0),
5319 XEXP (XEXP (x
, 1), 0))));
5320 return find_split_point (loc
, insn
, set_src
);
5323 /* Many RISC machines have a large set of logical insns. If the
5324 second operand is a NOT, put it first so we will try to split the
5325 other operand first. */
5326 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5328 rtx tem
= XEXP (x
, 0);
5329 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5330 SUBST (XEXP (x
, 1), tem
);
5336 /* Canonicalization can produce (minus A (mult B C)), where C is a
5337 constant. It may be better to try splitting (plus (mult B -C) A)
5338 instead if this isn't a multiply by a power of two. */
5339 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5340 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5341 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5343 machine_mode mode
= GET_MODE (x
);
5344 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5345 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5346 SUBST (*loc
, gen_rtx_PLUS (mode
,
5348 XEXP (XEXP (x
, 1), 0),
5349 gen_int_mode (other_int
,
5352 return find_split_point (loc
, insn
, set_src
);
5355 /* Split at a multiply-accumulate instruction. However if this is
5356 the SET_SRC, we likely do not have such an instruction and it's
5357 worthless to try this split. */
5359 && (GET_CODE (XEXP (x
, 0)) == MULT
5360 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5361 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5368 /* Otherwise, select our actions depending on our rtx class. */
5369 switch (GET_RTX_CLASS (code
))
5371 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5373 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5378 case RTX_COMM_ARITH
:
5380 case RTX_COMM_COMPARE
:
5381 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5386 /* Some machines have (and (shift ...) ...) insns. If X is not
5387 an AND, but XEXP (X, 0) is, use it as our split point. */
5388 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5389 return &XEXP (x
, 0);
5391 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5397 /* Otherwise, we don't have a split point. */
5402 /* Throughout X, replace FROM with TO, and return the result.
5403 The result is TO if X is FROM;
5404 otherwise the result is X, but its contents may have been modified.
5405 If they were modified, a record was made in undobuf so that
5406 undo_all will (among other things) return X to its original state.
5408 If the number of changes necessary is too much to record to undo,
5409 the excess changes are not made, so the result is invalid.
5410 The changes already made can still be undone.
5411 undobuf.num_undo is incremented for such changes, so by testing that
5412 the caller can tell whether the result is valid.
5414 `n_occurrences' is incremented each time FROM is replaced.
5416 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5418 IN_COND is nonzero if we are at the top level of a condition.
5420 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5421 by copying if `n_occurrences' is nonzero. */
5424 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5426 enum rtx_code code
= GET_CODE (x
);
5427 machine_mode op0_mode
= VOIDmode
;
5432 /* Two expressions are equal if they are identical copies of a shared
5433 RTX or if they are both registers with the same register number
5436 #define COMBINE_RTX_EQUAL_P(X,Y) \
5438 || (REG_P (X) && REG_P (Y) \
5439 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5441 /* Do not substitute into clobbers of regs -- this will never result in
5443 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5446 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5449 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5452 /* If X and FROM are the same register but different modes, they
5453 will not have been seen as equal above. However, the log links code
5454 will make a LOG_LINKS entry for that case. If we do nothing, we
5455 will try to rerecognize our original insn and, when it succeeds,
5456 we will delete the feeding insn, which is incorrect.
5458 So force this insn not to match in this (rare) case. */
5459 if (! in_dest
&& code
== REG
&& REG_P (from
)
5460 && reg_overlap_mentioned_p (x
, from
))
5461 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5463 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5464 of which may contain things that can be combined. */
5465 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5468 /* It is possible to have a subexpression appear twice in the insn.
5469 Suppose that FROM is a register that appears within TO.
5470 Then, after that subexpression has been scanned once by `subst',
5471 the second time it is scanned, TO may be found. If we were
5472 to scan TO here, we would find FROM within it and create a
5473 self-referent rtl structure which is completely wrong. */
5474 if (COMBINE_RTX_EQUAL_P (x
, to
))
5477 /* Parallel asm_operands need special attention because all of the
5478 inputs are shared across the arms. Furthermore, unsharing the
5479 rtl results in recognition failures. Failure to handle this case
5480 specially can result in circular rtl.
5482 Solve this by doing a normal pass across the first entry of the
5483 parallel, and only processing the SET_DESTs of the subsequent
5486 if (code
== PARALLEL
5487 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5488 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5490 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5492 /* If this substitution failed, this whole thing fails. */
5493 if (GET_CODE (new_rtx
) == CLOBBER
5494 && XEXP (new_rtx
, 0) == const0_rtx
)
5497 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5499 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5501 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5504 && GET_CODE (dest
) != CC0
5505 && GET_CODE (dest
) != PC
)
5507 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5509 /* If this substitution failed, this whole thing fails. */
5510 if (GET_CODE (new_rtx
) == CLOBBER
5511 && XEXP (new_rtx
, 0) == const0_rtx
)
5514 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5520 len
= GET_RTX_LENGTH (code
);
5521 fmt
= GET_RTX_FORMAT (code
);
5523 /* We don't need to process a SET_DEST that is a register, CC0,
5524 or PC, so set up to skip this common case. All other cases
5525 where we want to suppress replacing something inside a
5526 SET_SRC are handled via the IN_DEST operand. */
5528 && (REG_P (SET_DEST (x
))
5529 || GET_CODE (SET_DEST (x
)) == CC0
5530 || GET_CODE (SET_DEST (x
)) == PC
))
5533 /* Trying to simplify the operands of a widening MULT is not likely
5534 to create RTL matching a machine insn. */
5536 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5537 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5538 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5539 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5540 && REG_P (XEXP (XEXP (x
, 0), 0))
5541 && REG_P (XEXP (XEXP (x
, 1), 0))
5546 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5549 op0_mode
= GET_MODE (XEXP (x
, 0));
5551 for (i
= 0; i
< len
; i
++)
5556 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5558 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5560 new_rtx
= (unique_copy
&& n_occurrences
5561 ? copy_rtx (to
) : to
);
5566 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5569 /* If this substitution failed, this whole thing
5571 if (GET_CODE (new_rtx
) == CLOBBER
5572 && XEXP (new_rtx
, 0) == const0_rtx
)
5576 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5579 else if (fmt
[i
] == 'e')
5581 /* If this is a register being set, ignore it. */
5582 new_rtx
= XEXP (x
, i
);
5585 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5587 || code
== STRICT_LOW_PART
))
5590 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5592 /* In general, don't install a subreg involving two
5593 modes not tieable. It can worsen register
5594 allocation, and can even make invalid reload
5595 insns, since the reg inside may need to be copied
5596 from in the outside mode, and that may be invalid
5597 if it is an fp reg copied in integer mode.
5599 We allow two exceptions to this: It is valid if
5600 it is inside another SUBREG and the mode of that
5601 SUBREG and the mode of the inside of TO is
5602 tieable and it is valid if X is a SET that copies
5605 if (GET_CODE (to
) == SUBREG
5606 && !targetm
.modes_tieable_p (GET_MODE (to
),
5607 GET_MODE (SUBREG_REG (to
)))
5608 && ! (code
== SUBREG
5609 && (targetm
.modes_tieable_p
5610 (GET_MODE (x
), GET_MODE (SUBREG_REG (to
)))))
5614 && XEXP (x
, 0) == cc0_rtx
))))
5615 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5619 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5620 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5623 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5625 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5629 /* If we are in a SET_DEST, suppress most cases unless we
5630 have gone inside a MEM, in which case we want to
5631 simplify the address. We assume here that things that
5632 are actually part of the destination have their inner
5633 parts in the first expression. This is true for SUBREG,
5634 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5635 things aside from REG and MEM that should appear in a
5637 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5639 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5640 || code
== ZERO_EXTRACT
))
5643 code
== IF_THEN_ELSE
&& i
== 0,
5646 /* If we found that we will have to reject this combination,
5647 indicate that by returning the CLOBBER ourselves, rather than
5648 an expression containing it. This will speed things up as
5649 well as prevent accidents where two CLOBBERs are considered
5650 to be equal, thus producing an incorrect simplification. */
5652 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5655 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5657 machine_mode mode
= GET_MODE (x
);
5659 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5660 GET_MODE (SUBREG_REG (x
)),
5663 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5665 else if (CONST_SCALAR_INT_P (new_rtx
)
5666 && (GET_CODE (x
) == ZERO_EXTEND
5667 || GET_CODE (x
) == FLOAT
5668 || GET_CODE (x
) == UNSIGNED_FLOAT
))
5670 x
= simplify_unary_operation (GET_CODE (x
), GET_MODE (x
),
5672 GET_MODE (XEXP (x
, 0)));
5674 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5677 SUBST (XEXP (x
, i
), new_rtx
);
5682 /* Check if we are loading something from the constant pool via float
5683 extension; in this case we would undo compress_float_constant
5684 optimization and degenerate constant load to an immediate value. */
5685 if (GET_CODE (x
) == FLOAT_EXTEND
5686 && MEM_P (XEXP (x
, 0))
5687 && MEM_READONLY_P (XEXP (x
, 0)))
5689 rtx tmp
= avoid_constant_pool_reference (x
);
5694 /* Try to simplify X. If the simplification changed the code, it is likely
5695 that further simplification will help, so loop, but limit the number
5696 of repetitions that will be performed. */
5698 for (i
= 0; i
< 4; i
++)
5700 /* If X is sufficiently simple, don't bother trying to do anything
5702 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5703 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5705 if (GET_CODE (x
) == code
)
5708 code
= GET_CODE (x
);
5710 /* We no longer know the original mode of operand 0 since we
5711 have changed the form of X) */
5712 op0_mode
= VOIDmode
;
5718 /* If X is a commutative operation whose operands are not in the canonical
5719 order, use substitutions to swap them. */
5722 maybe_swap_commutative_operands (rtx x
)
5724 if (COMMUTATIVE_ARITH_P (x
)
5725 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5727 rtx temp
= XEXP (x
, 0);
5728 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5729 SUBST (XEXP (x
, 1), temp
);
5733 /* Simplify X, a piece of RTL. We just operate on the expression at the
5734 outer level; call `subst' to simplify recursively. Return the new
5737 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5738 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5742 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5745 enum rtx_code code
= GET_CODE (x
);
5746 machine_mode mode
= GET_MODE (x
);
5747 scalar_int_mode int_mode
;
5751 /* If this is a commutative operation, put a constant last and a complex
5752 expression first. We don't need to do this for comparisons here. */
5753 maybe_swap_commutative_operands (x
);
5755 /* Try to fold this expression in case we have constants that weren't
5758 switch (GET_RTX_CLASS (code
))
5761 if (op0_mode
== VOIDmode
)
5762 op0_mode
= GET_MODE (XEXP (x
, 0));
5763 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5766 case RTX_COMM_COMPARE
:
5768 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5769 if (cmp_mode
== VOIDmode
)
5771 cmp_mode
= GET_MODE (XEXP (x
, 1));
5772 if (cmp_mode
== VOIDmode
)
5773 cmp_mode
= op0_mode
;
5775 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5776 XEXP (x
, 0), XEXP (x
, 1));
5779 case RTX_COMM_ARITH
:
5781 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5783 case RTX_BITFIELD_OPS
:
5785 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5786 XEXP (x
, 1), XEXP (x
, 2));
5795 code
= GET_CODE (temp
);
5796 op0_mode
= VOIDmode
;
5797 mode
= GET_MODE (temp
);
5800 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5801 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5802 things. Check for cases where both arms are testing the same
5805 Don't do anything if all operands are very simple. */
5808 && ((!OBJECT_P (XEXP (x
, 0))
5809 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5810 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5811 || (!OBJECT_P (XEXP (x
, 1))
5812 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5813 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5815 && (!OBJECT_P (XEXP (x
, 0))
5816 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5817 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5819 rtx cond
, true_rtx
, false_rtx
;
5821 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5823 /* If everything is a comparison, what we have is highly unlikely
5824 to be simpler, so don't use it. */
5825 && ! (COMPARISON_P (x
)
5826 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
)))
5827 /* Similarly, if we end up with one of the expressions the same
5828 as the original, it is certainly not simpler. */
5829 && ! rtx_equal_p (x
, true_rtx
)
5830 && ! rtx_equal_p (x
, false_rtx
))
5832 rtx cop1
= const0_rtx
;
5833 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5835 if (cond_code
== NE
&& COMPARISON_P (cond
))
5838 /* Simplify the alternative arms; this may collapse the true and
5839 false arms to store-flag values. Be careful to use copy_rtx
5840 here since true_rtx or false_rtx might share RTL with x as a
5841 result of the if_then_else_cond call above. */
5842 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5843 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5845 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5846 is unlikely to be simpler. */
5847 if (general_operand (true_rtx
, VOIDmode
)
5848 && general_operand (false_rtx
, VOIDmode
))
5850 enum rtx_code reversed
;
5852 /* Restarting if we generate a store-flag expression will cause
5853 us to loop. Just drop through in this case. */
5855 /* If the result values are STORE_FLAG_VALUE and zero, we can
5856 just make the comparison operation. */
5857 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5858 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5860 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5861 && ((reversed
= reversed_comparison_code_parts
5862 (cond_code
, cond
, cop1
, NULL
))
5864 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5867 /* Likewise, we can make the negate of a comparison operation
5868 if the result values are - STORE_FLAG_VALUE and zero. */
5869 else if (CONST_INT_P (true_rtx
)
5870 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5871 && false_rtx
== const0_rtx
)
5872 x
= simplify_gen_unary (NEG
, mode
,
5873 simplify_gen_relational (cond_code
,
5877 else if (CONST_INT_P (false_rtx
)
5878 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5879 && true_rtx
== const0_rtx
5880 && ((reversed
= reversed_comparison_code_parts
5881 (cond_code
, cond
, cop1
, NULL
))
5883 x
= simplify_gen_unary (NEG
, mode
,
5884 simplify_gen_relational (reversed
,
5889 return gen_rtx_IF_THEN_ELSE (mode
,
5890 simplify_gen_relational (cond_code
,
5895 true_rtx
, false_rtx
);
5897 code
= GET_CODE (x
);
5898 op0_mode
= VOIDmode
;
5903 /* First see if we can apply the inverse distributive law. */
5904 if (code
== PLUS
|| code
== MINUS
5905 || code
== AND
|| code
== IOR
|| code
== XOR
)
5907 x
= apply_distributive_law (x
);
5908 code
= GET_CODE (x
);
5909 op0_mode
= VOIDmode
;
5912 /* If CODE is an associative operation not otherwise handled, see if we
5913 can associate some operands. This can win if they are constants or
5914 if they are logically related (i.e. (a & b) & a). */
5915 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5916 || code
== AND
|| code
== IOR
|| code
== XOR
5917 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5918 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5919 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5921 if (GET_CODE (XEXP (x
, 0)) == code
)
5923 rtx other
= XEXP (XEXP (x
, 0), 0);
5924 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5925 rtx inner_op1
= XEXP (x
, 1);
5928 /* Make sure we pass the constant operand if any as the second
5929 one if this is a commutative operation. */
5930 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5931 std::swap (inner_op0
, inner_op1
);
5932 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5933 : code
== DIV
? MULT
5935 mode
, inner_op0
, inner_op1
);
5937 /* For commutative operations, try the other pair if that one
5939 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5941 other
= XEXP (XEXP (x
, 0), 1);
5942 inner
= simplify_binary_operation (code
, mode
,
5943 XEXP (XEXP (x
, 0), 0),
5948 return simplify_gen_binary (code
, mode
, other
, inner
);
5952 /* A little bit of algebraic simplification here. */
5956 /* Ensure that our address has any ASHIFTs converted to MULT in case
5957 address-recognizing predicates are called later. */
5958 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5959 SUBST (XEXP (x
, 0), temp
);
5963 if (op0_mode
== VOIDmode
)
5964 op0_mode
= GET_MODE (SUBREG_REG (x
));
5966 /* See if this can be moved to simplify_subreg. */
5967 if (CONSTANT_P (SUBREG_REG (x
))
5968 && known_eq (subreg_lowpart_offset (mode
, op0_mode
), SUBREG_BYTE (x
))
5969 /* Don't call gen_lowpart if the inner mode
5970 is VOIDmode and we cannot simplify it, as SUBREG without
5971 inner mode is invalid. */
5972 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5973 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5974 return gen_lowpart (mode
, SUBREG_REG (x
));
5976 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5980 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5985 /* If op is known to have all lower bits zero, the result is zero. */
5986 scalar_int_mode int_mode
, int_op0_mode
;
5988 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5989 && is_a
<scalar_int_mode
> (op0_mode
, &int_op0_mode
)
5990 && (GET_MODE_PRECISION (int_mode
)
5991 < GET_MODE_PRECISION (int_op0_mode
))
5992 && known_eq (subreg_lowpart_offset (int_mode
, int_op0_mode
),
5994 && HWI_COMPUTABLE_MODE_P (int_op0_mode
)
5995 && ((nonzero_bits (SUBREG_REG (x
), int_op0_mode
)
5996 & GET_MODE_MASK (int_mode
)) == 0)
5997 && !side_effects_p (SUBREG_REG (x
)))
5998 return CONST0_RTX (int_mode
);
6001 /* Don't change the mode of the MEM if that would change the meaning
6003 if (MEM_P (SUBREG_REG (x
))
6004 && (MEM_VOLATILE_P (SUBREG_REG (x
))
6005 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
6006 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
6007 return gen_rtx_CLOBBER (mode
, const0_rtx
);
6009 /* Note that we cannot do any narrowing for non-constants since
6010 we might have been counting on using the fact that some bits were
6011 zero. We now do this in the SET. */
6016 temp
= expand_compound_operation (XEXP (x
, 0));
6018 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
6019 replaced by (lshiftrt X C). This will convert
6020 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
6022 if (GET_CODE (temp
) == ASHIFTRT
6023 && CONST_INT_P (XEXP (temp
, 1))
6024 && INTVAL (XEXP (temp
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
6025 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
6026 INTVAL (XEXP (temp
, 1)));
6028 /* If X has only a single bit that might be nonzero, say, bit I, convert
6029 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6030 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
6031 (sign_extract X 1 Y). But only do this if TEMP isn't a register
6032 or a SUBREG of one since we'd be making the expression more
6033 complex if it was just a register. */
6036 && ! (GET_CODE (temp
) == SUBREG
6037 && REG_P (SUBREG_REG (temp
)))
6038 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6039 && (i
= exact_log2 (nonzero_bits (temp
, int_mode
))) >= 0)
6041 rtx temp1
= simplify_shift_const
6042 (NULL_RTX
, ASHIFTRT
, int_mode
,
6043 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
, temp
,
6044 GET_MODE_PRECISION (int_mode
) - 1 - i
),
6045 GET_MODE_PRECISION (int_mode
) - 1 - i
);
6047 /* If all we did was surround TEMP with the two shifts, we
6048 haven't improved anything, so don't use it. Otherwise,
6049 we are better off with TEMP1. */
6050 if (GET_CODE (temp1
) != ASHIFTRT
6051 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
6052 || XEXP (XEXP (temp1
, 0), 0) != temp
)
6058 /* We can't handle truncation to a partial integer mode here
6059 because we don't know the real bitsize of the partial
6061 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
6064 if (HWI_COMPUTABLE_MODE_P (mode
))
6066 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
6067 GET_MODE_MASK (mode
), 0));
6069 /* We can truncate a constant value and return it. */
6072 if (poly_int_rtx_p (XEXP (x
, 0), &c
))
6073 return gen_int_mode (c
, mode
);
6076 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
6077 whose value is a comparison can be replaced with a subreg if
6078 STORE_FLAG_VALUE permits. */
6079 if (HWI_COMPUTABLE_MODE_P (mode
)
6080 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
6081 && (temp
= get_last_value (XEXP (x
, 0)))
6082 && COMPARISON_P (temp
))
6083 return gen_lowpart (mode
, XEXP (x
, 0));
6087 /* (const (const X)) can become (const X). Do it this way rather than
6088 returning the inner CONST since CONST can be shared with a
6090 if (GET_CODE (XEXP (x
, 0)) == CONST
)
6091 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
6095 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6096 can add in an offset. find_split_point will split this address up
6097 again if it doesn't match. */
6098 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
6099 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
6104 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6105 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6106 bit-field and can be replaced by either a sign_extend or a
6107 sign_extract. The `and' may be a zero_extend and the two
6108 <c>, -<c> constants may be reversed. */
6109 if (GET_CODE (XEXP (x
, 0)) == XOR
6110 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6111 && CONST_INT_P (XEXP (x
, 1))
6112 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
6113 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
6114 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
6115 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
6116 && HWI_COMPUTABLE_MODE_P (int_mode
)
6117 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
6118 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6119 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6120 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
6121 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
6122 && known_eq ((GET_MODE_PRECISION
6123 (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))),
6124 (unsigned int) i
+ 1))))
6125 return simplify_shift_const
6126 (NULL_RTX
, ASHIFTRT
, int_mode
,
6127 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6128 XEXP (XEXP (XEXP (x
, 0), 0), 0),
6129 GET_MODE_PRECISION (int_mode
) - (i
+ 1)),
6130 GET_MODE_PRECISION (int_mode
) - (i
+ 1));
6132 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6133 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6134 the bitsize of the mode - 1. This allows simplification of
6135 "a = (b & 8) == 0;" */
6136 if (XEXP (x
, 1) == constm1_rtx
6137 && !REG_P (XEXP (x
, 0))
6138 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
6139 && REG_P (SUBREG_REG (XEXP (x
, 0))))
6140 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6141 && nonzero_bits (XEXP (x
, 0), int_mode
) == 1)
6142 return simplify_shift_const
6143 (NULL_RTX
, ASHIFTRT
, int_mode
,
6144 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6145 gen_rtx_XOR (int_mode
, XEXP (x
, 0),
6147 GET_MODE_PRECISION (int_mode
) - 1),
6148 GET_MODE_PRECISION (int_mode
) - 1);
6150 /* If we are adding two things that have no bits in common, convert
6151 the addition into an IOR. This will often be further simplified,
6152 for example in cases like ((a & 1) + (a & 2)), which can
6155 if (HWI_COMPUTABLE_MODE_P (mode
)
6156 && (nonzero_bits (XEXP (x
, 0), mode
)
6157 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
6159 /* Try to simplify the expression further. */
6160 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
6161 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
6163 /* If we could, great. If not, do not go ahead with the IOR
6164 replacement, since PLUS appears in many special purpose
6165 address arithmetic instructions. */
6166 if (GET_CODE (temp
) != CLOBBER
6167 && (GET_CODE (temp
) != IOR
6168 || ((XEXP (temp
, 0) != XEXP (x
, 0)
6169 || XEXP (temp
, 1) != XEXP (x
, 1))
6170 && (XEXP (temp
, 0) != XEXP (x
, 1)
6171 || XEXP (temp
, 1) != XEXP (x
, 0)))))
6175 /* Canonicalize x + x into x << 1. */
6176 if (GET_MODE_CLASS (mode
) == MODE_INT
6177 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
6178 && !side_effects_p (XEXP (x
, 0)))
6179 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
6184 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6185 (and <foo> (const_int pow2-1)) */
6186 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6187 && GET_CODE (XEXP (x
, 1)) == AND
6188 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
6189 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
6190 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6191 return simplify_and_const_int (NULL_RTX
, int_mode
, XEXP (x
, 0),
6192 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
6196 /* If we have (mult (plus A B) C), apply the distributive law and then
6197 the inverse distributive law to see if things simplify. This
6198 occurs mostly in addresses, often when unrolling loops. */
6200 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
6202 rtx result
= distribute_and_simplify_rtx (x
, 0);
6207 /* Try simplify a*(b/c) as (a*b)/c. */
6208 if (FLOAT_MODE_P (mode
) && flag_associative_math
6209 && GET_CODE (XEXP (x
, 0)) == DIV
)
6211 rtx tem
= simplify_binary_operation (MULT
, mode
,
6212 XEXP (XEXP (x
, 0), 0),
6215 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6220 /* If this is a divide by a power of two, treat it as a shift if
6221 its first operand is a shift. */
6222 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6223 && CONST_INT_P (XEXP (x
, 1))
6224 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6225 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6226 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6227 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6228 || GET_CODE (XEXP (x
, 0)) == ROTATE
6229 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6230 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, int_mode
,
6235 case GT
: case GTU
: case GE
: case GEU
:
6236 case LT
: case LTU
: case LE
: case LEU
:
6237 case UNEQ
: case LTGT
:
6238 case UNGT
: case UNGE
:
6239 case UNLT
: case UNLE
:
6240 case UNORDERED
: case ORDERED
:
6241 /* If the first operand is a condition code, we can't do anything
6243 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6244 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6245 && ! CC0_P (XEXP (x
, 0))))
6247 rtx op0
= XEXP (x
, 0);
6248 rtx op1
= XEXP (x
, 1);
6249 enum rtx_code new_code
;
6251 if (GET_CODE (op0
) == COMPARE
)
6252 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6254 /* Simplify our comparison, if possible. */
6255 new_code
= simplify_comparison (code
, &op0
, &op1
);
6257 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6258 if only the low-order bit is possibly nonzero in X (such as when
6259 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6260 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6261 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6264 Remove any ZERO_EXTRACT we made when thinking this was a
6265 comparison. It may now be simpler to use, e.g., an AND. If a
6266 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6267 the call to make_compound_operation in the SET case.
6269 Don't apply these optimizations if the caller would
6270 prefer a comparison rather than a value.
6271 E.g., for the condition in an IF_THEN_ELSE most targets need
6272 an explicit comparison. */
6277 else if (STORE_FLAG_VALUE
== 1
6279 && is_int_mode (mode
, &int_mode
)
6280 && op1
== const0_rtx
6281 && int_mode
== GET_MODE (op0
)
6282 && nonzero_bits (op0
, int_mode
) == 1)
6283 return gen_lowpart (int_mode
,
6284 expand_compound_operation (op0
));
6286 else if (STORE_FLAG_VALUE
== 1
6288 && is_int_mode (mode
, &int_mode
)
6289 && op1
== const0_rtx
6290 && int_mode
== GET_MODE (op0
)
6291 && (num_sign_bit_copies (op0
, int_mode
)
6292 == GET_MODE_PRECISION (int_mode
)))
6294 op0
= expand_compound_operation (op0
);
6295 return simplify_gen_unary (NEG
, int_mode
,
6296 gen_lowpart (int_mode
, op0
),
6300 else if (STORE_FLAG_VALUE
== 1
6302 && is_int_mode (mode
, &int_mode
)
6303 && op1
== const0_rtx
6304 && int_mode
== GET_MODE (op0
)
6305 && nonzero_bits (op0
, int_mode
) == 1)
6307 op0
= expand_compound_operation (op0
);
6308 return simplify_gen_binary (XOR
, int_mode
,
6309 gen_lowpart (int_mode
, op0
),
6313 else if (STORE_FLAG_VALUE
== 1
6315 && is_int_mode (mode
, &int_mode
)
6316 && op1
== const0_rtx
6317 && int_mode
== GET_MODE (op0
)
6318 && (num_sign_bit_copies (op0
, int_mode
)
6319 == GET_MODE_PRECISION (int_mode
)))
6321 op0
= expand_compound_operation (op0
);
6322 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), 1);
6325 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6330 else if (STORE_FLAG_VALUE
== -1
6332 && is_int_mode (mode
, &int_mode
)
6333 && op1
== const0_rtx
6334 && int_mode
== GET_MODE (op0
)
6335 && (num_sign_bit_copies (op0
, int_mode
)
6336 == GET_MODE_PRECISION (int_mode
)))
6337 return gen_lowpart (int_mode
, expand_compound_operation (op0
));
6339 else if (STORE_FLAG_VALUE
== -1
6341 && is_int_mode (mode
, &int_mode
)
6342 && op1
== const0_rtx
6343 && int_mode
== GET_MODE (op0
)
6344 && nonzero_bits (op0
, int_mode
) == 1)
6346 op0
= expand_compound_operation (op0
);
6347 return simplify_gen_unary (NEG
, int_mode
,
6348 gen_lowpart (int_mode
, op0
),
6352 else if (STORE_FLAG_VALUE
== -1
6354 && is_int_mode (mode
, &int_mode
)
6355 && op1
== const0_rtx
6356 && int_mode
== GET_MODE (op0
)
6357 && (num_sign_bit_copies (op0
, int_mode
)
6358 == GET_MODE_PRECISION (int_mode
)))
6360 op0
= expand_compound_operation (op0
);
6361 return simplify_gen_unary (NOT
, int_mode
,
6362 gen_lowpart (int_mode
, op0
),
6366 /* If X is 0/1, (eq X 0) is X-1. */
6367 else if (STORE_FLAG_VALUE
== -1
6369 && is_int_mode (mode
, &int_mode
)
6370 && op1
== const0_rtx
6371 && int_mode
== GET_MODE (op0
)
6372 && nonzero_bits (op0
, int_mode
) == 1)
6374 op0
= expand_compound_operation (op0
);
6375 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), -1);
6378 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6379 one bit that might be nonzero, we can convert (ne x 0) to
6380 (ashift x c) where C puts the bit in the sign bit. Remove any
6381 AND with STORE_FLAG_VALUE when we are done, since we are only
6382 going to test the sign bit. */
6384 && is_int_mode (mode
, &int_mode
)
6385 && HWI_COMPUTABLE_MODE_P (int_mode
)
6386 && val_signbit_p (int_mode
, STORE_FLAG_VALUE
)
6387 && op1
== const0_rtx
6388 && int_mode
== GET_MODE (op0
)
6389 && (i
= exact_log2 (nonzero_bits (op0
, int_mode
))) >= 0)
6391 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6392 expand_compound_operation (op0
),
6393 GET_MODE_PRECISION (int_mode
) - 1 - i
);
6394 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6400 /* If the code changed, return a whole new comparison.
6401 We also need to avoid using SUBST in cases where
6402 simplify_comparison has widened a comparison with a CONST_INT,
6403 since in that case the wider CONST_INT may fail the sanity
6404 checks in do_SUBST. */
6405 if (new_code
!= code
6406 || (CONST_INT_P (op1
)
6407 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6408 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6409 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6411 /* Otherwise, keep this operation, but maybe change its operands.
6412 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6413 SUBST (XEXP (x
, 0), op0
);
6414 SUBST (XEXP (x
, 1), op1
);
6419 return simplify_if_then_else (x
);
6425 /* If we are processing SET_DEST, we are done. */
6429 return expand_compound_operation (x
);
6432 return simplify_set (x
);
6436 return simplify_logical (x
);
6443 /* If this is a shift by a constant amount, simplify it. */
6444 if (CONST_INT_P (XEXP (x
, 1)))
6445 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6446 INTVAL (XEXP (x
, 1)));
6448 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6450 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6452 << exact_log2 (GET_MODE_UNIT_BITSIZE
6465 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6468 simplify_if_then_else (rtx x
)
6470 machine_mode mode
= GET_MODE (x
);
6471 rtx cond
= XEXP (x
, 0);
6472 rtx true_rtx
= XEXP (x
, 1);
6473 rtx false_rtx
= XEXP (x
, 2);
6474 enum rtx_code true_code
= GET_CODE (cond
);
6475 int comparison_p
= COMPARISON_P (cond
);
6478 enum rtx_code false_code
;
6480 scalar_int_mode int_mode
, inner_mode
;
6482 /* Simplify storing of the truth value. */
6483 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6484 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6485 XEXP (cond
, 0), XEXP (cond
, 1));
6487 /* Also when the truth value has to be reversed. */
6489 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6490 && (reversed
= reversed_comparison (cond
, mode
)))
6493 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6494 in it is being compared against certain values. Get the true and false
6495 comparisons and see if that says anything about the value of each arm. */
6498 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6500 && REG_P (XEXP (cond
, 0)))
6503 rtx from
= XEXP (cond
, 0);
6504 rtx true_val
= XEXP (cond
, 1);
6505 rtx false_val
= true_val
;
6508 /* If FALSE_CODE is EQ, swap the codes and arms. */
6510 if (false_code
== EQ
)
6512 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6513 std::swap (true_rtx
, false_rtx
);
6516 scalar_int_mode from_mode
;
6517 if (is_a
<scalar_int_mode
> (GET_MODE (from
), &from_mode
))
6519 /* If we are comparing against zero and the expression being
6520 tested has only a single bit that might be nonzero, that is
6521 its value when it is not equal to zero. Similarly if it is
6522 known to be -1 or 0. */
6524 && true_val
== const0_rtx
6525 && pow2p_hwi (nzb
= nonzero_bits (from
, from_mode
)))
6528 false_val
= gen_int_mode (nzb
, from_mode
);
6530 else if (true_code
== EQ
6531 && true_val
== const0_rtx
6532 && (num_sign_bit_copies (from
, from_mode
)
6533 == GET_MODE_PRECISION (from_mode
)))
6536 false_val
= constm1_rtx
;
6540 /* Now simplify an arm if we know the value of the register in the
6541 branch and it is used in the arm. Be careful due to the potential
6542 of locally-shared RTL. */
6544 if (reg_mentioned_p (from
, true_rtx
))
6545 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6547 pc_rtx
, pc_rtx
, 0, 0, 0);
6548 if (reg_mentioned_p (from
, false_rtx
))
6549 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6551 pc_rtx
, pc_rtx
, 0, 0, 0);
6553 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6554 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6556 true_rtx
= XEXP (x
, 1);
6557 false_rtx
= XEXP (x
, 2);
6558 true_code
= GET_CODE (cond
);
6561 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6562 reversed, do so to avoid needing two sets of patterns for
6563 subtract-and-branch insns. Similarly if we have a constant in the true
6564 arm, the false arm is the same as the first operand of the comparison, or
6565 the false arm is more complicated than the true arm. */
6568 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6569 && (true_rtx
== pc_rtx
6570 || (CONSTANT_P (true_rtx
)
6571 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6572 || true_rtx
== const0_rtx
6573 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6574 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6575 && !OBJECT_P (false_rtx
))
6576 || reg_mentioned_p (true_rtx
, false_rtx
)
6577 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6579 true_code
= reversed_comparison_code (cond
, NULL
);
6580 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6581 SUBST (XEXP (x
, 1), false_rtx
);
6582 SUBST (XEXP (x
, 2), true_rtx
);
6584 std::swap (true_rtx
, false_rtx
);
6587 /* It is possible that the conditional has been simplified out. */
6588 true_code
= GET_CODE (cond
);
6589 comparison_p
= COMPARISON_P (cond
);
6592 /* If the two arms are identical, we don't need the comparison. */
6594 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6597 /* Convert a == b ? b : a to "a". */
6598 if (true_code
== EQ
&& ! side_effects_p (cond
)
6599 && !HONOR_NANS (mode
)
6600 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6601 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6603 else if (true_code
== NE
&& ! side_effects_p (cond
)
6604 && !HONOR_NANS (mode
)
6605 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6606 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6609 /* Look for cases where we have (abs x) or (neg (abs X)). */
6611 if (GET_MODE_CLASS (mode
) == MODE_INT
6613 && XEXP (cond
, 1) == const0_rtx
6614 && GET_CODE (false_rtx
) == NEG
6615 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6616 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6617 && ! side_effects_p (true_rtx
))
6622 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6626 simplify_gen_unary (NEG
, mode
,
6627 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6633 /* Look for MIN or MAX. */
6635 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6637 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6638 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6639 && ! side_effects_p (cond
))
6644 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6647 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6650 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6653 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6658 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6659 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6660 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6661 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6662 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6663 neither 1 or -1, but it isn't worth checking for. */
6665 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6667 && is_int_mode (mode
, &int_mode
)
6668 && ! side_effects_p (x
))
6670 rtx t
= make_compound_operation (true_rtx
, SET
);
6671 rtx f
= make_compound_operation (false_rtx
, SET
);
6672 rtx cond_op0
= XEXP (cond
, 0);
6673 rtx cond_op1
= XEXP (cond
, 1);
6674 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6675 scalar_int_mode m
= int_mode
;
6676 rtx z
= 0, c1
= NULL_RTX
;
6678 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6679 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6680 || GET_CODE (t
) == ASHIFT
6681 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6682 && rtx_equal_p (XEXP (t
, 0), f
))
6683 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6685 /* If an identity-zero op is commutative, check whether there
6686 would be a match if we swapped the operands. */
6687 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6688 || GET_CODE (t
) == XOR
)
6689 && rtx_equal_p (XEXP (t
, 1), f
))
6690 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6691 else if (GET_CODE (t
) == SIGN_EXTEND
6692 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6693 && (GET_CODE (XEXP (t
, 0)) == PLUS
6694 || GET_CODE (XEXP (t
, 0)) == MINUS
6695 || GET_CODE (XEXP (t
, 0)) == IOR
6696 || GET_CODE (XEXP (t
, 0)) == XOR
6697 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6698 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6699 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6700 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6701 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6702 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6703 && (num_sign_bit_copies (f
, GET_MODE (f
))
6705 (GET_MODE_PRECISION (int_mode
)
6706 - GET_MODE_PRECISION (inner_mode
))))
6708 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6709 extend_op
= SIGN_EXTEND
;
6712 else if (GET_CODE (t
) == SIGN_EXTEND
6713 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6714 && (GET_CODE (XEXP (t
, 0)) == PLUS
6715 || GET_CODE (XEXP (t
, 0)) == IOR
6716 || GET_CODE (XEXP (t
, 0)) == XOR
)
6717 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6718 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6719 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6720 && (num_sign_bit_copies (f
, GET_MODE (f
))
6722 (GET_MODE_PRECISION (int_mode
)
6723 - GET_MODE_PRECISION (inner_mode
))))
6725 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6726 extend_op
= SIGN_EXTEND
;
6729 else if (GET_CODE (t
) == ZERO_EXTEND
6730 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6731 && (GET_CODE (XEXP (t
, 0)) == PLUS
6732 || GET_CODE (XEXP (t
, 0)) == MINUS
6733 || GET_CODE (XEXP (t
, 0)) == IOR
6734 || GET_CODE (XEXP (t
, 0)) == XOR
6735 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6736 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6737 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6738 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6739 && HWI_COMPUTABLE_MODE_P (int_mode
)
6740 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6741 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6742 && ((nonzero_bits (f
, GET_MODE (f
))
6743 & ~GET_MODE_MASK (inner_mode
))
6746 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6747 extend_op
= ZERO_EXTEND
;
6750 else if (GET_CODE (t
) == ZERO_EXTEND
6751 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6752 && (GET_CODE (XEXP (t
, 0)) == PLUS
6753 || GET_CODE (XEXP (t
, 0)) == IOR
6754 || GET_CODE (XEXP (t
, 0)) == XOR
)
6755 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6756 && HWI_COMPUTABLE_MODE_P (int_mode
)
6757 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6758 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6759 && ((nonzero_bits (f
, GET_MODE (f
))
6760 & ~GET_MODE_MASK (inner_mode
))
6763 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6764 extend_op
= ZERO_EXTEND
;
6770 machine_mode cm
= m
;
6771 if ((op
== ASHIFT
|| op
== LSHIFTRT
|| op
== ASHIFTRT
)
6772 && GET_MODE (c1
) != VOIDmode
)
6774 temp
= subst (simplify_gen_relational (true_code
, cm
, VOIDmode
,
6775 cond_op0
, cond_op1
),
6776 pc_rtx
, pc_rtx
, 0, 0, 0);
6777 temp
= simplify_gen_binary (MULT
, cm
, temp
,
6778 simplify_gen_binary (MULT
, cm
, c1
,
6780 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6781 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6783 if (extend_op
!= UNKNOWN
)
6784 temp
= simplify_gen_unary (extend_op
, int_mode
, temp
, m
);
6790 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6791 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6792 negation of a single bit, we can convert this operation to a shift. We
6793 can actually do this more generally, but it doesn't seem worth it. */
6796 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6797 && XEXP (cond
, 1) == const0_rtx
6798 && false_rtx
== const0_rtx
6799 && CONST_INT_P (true_rtx
)
6800 && ((nonzero_bits (XEXP (cond
, 0), int_mode
) == 1
6801 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6802 || ((num_sign_bit_copies (XEXP (cond
, 0), int_mode
)
6803 == GET_MODE_PRECISION (int_mode
))
6804 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6806 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6807 gen_lowpart (int_mode
, XEXP (cond
, 0)), i
);
6809 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6810 non-zero bit in A is C1. */
6811 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6812 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6813 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6814 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (cond
, 0)), &inner_mode
)
6815 && (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))
6816 == nonzero_bits (XEXP (cond
, 0), inner_mode
)
6817 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))) >= 0)
6819 rtx val
= XEXP (cond
, 0);
6820 if (inner_mode
== int_mode
)
6822 else if (GET_MODE_PRECISION (inner_mode
) < GET_MODE_PRECISION (int_mode
))
6823 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, val
, inner_mode
);
6829 /* Simplify X, a SET expression. Return the new expression. */
6832 simplify_set (rtx x
)
6834 rtx src
= SET_SRC (x
);
6835 rtx dest
= SET_DEST (x
);
6837 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6838 rtx_insn
*other_insn
;
6840 scalar_int_mode int_mode
;
6842 /* (set (pc) (return)) gets written as (return). */
6843 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6846 /* Now that we know for sure which bits of SRC we are using, see if we can
6847 simplify the expression for the object knowing that we only need the
6850 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6852 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6853 SUBST (SET_SRC (x
), src
);
6856 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6857 the comparison result and try to simplify it unless we already have used
6858 undobuf.other_insn. */
6859 if ((GET_MODE_CLASS (mode
) == MODE_CC
6860 || GET_CODE (src
) == COMPARE
6862 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6863 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6864 && COMPARISON_P (*cc_use
)
6865 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6867 enum rtx_code old_code
= GET_CODE (*cc_use
);
6868 enum rtx_code new_code
;
6870 int other_changed
= 0;
6871 rtx inner_compare
= NULL_RTX
;
6872 machine_mode compare_mode
= GET_MODE (dest
);
6874 if (GET_CODE (src
) == COMPARE
)
6876 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6877 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6879 inner_compare
= op0
;
6880 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6884 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6886 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6889 new_code
= old_code
;
6890 else if (!CONSTANT_P (tmp
))
6892 new_code
= GET_CODE (tmp
);
6893 op0
= XEXP (tmp
, 0);
6894 op1
= XEXP (tmp
, 1);
6898 rtx pat
= PATTERN (other_insn
);
6899 undobuf
.other_insn
= other_insn
;
6900 SUBST (*cc_use
, tmp
);
6902 /* Attempt to simplify CC user. */
6903 if (GET_CODE (pat
) == SET
)
6905 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6906 if (new_rtx
!= NULL_RTX
)
6907 SUBST (SET_SRC (pat
), new_rtx
);
6910 /* Convert X into a no-op move. */
6911 SUBST (SET_DEST (x
), pc_rtx
);
6912 SUBST (SET_SRC (x
), pc_rtx
);
6916 /* Simplify our comparison, if possible. */
6917 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6919 #ifdef SELECT_CC_MODE
6920 /* If this machine has CC modes other than CCmode, check to see if we
6921 need to use a different CC mode here. */
6922 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6923 compare_mode
= GET_MODE (op0
);
6924 else if (inner_compare
6925 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6926 && new_code
== old_code
6927 && op0
== XEXP (inner_compare
, 0)
6928 && op1
== XEXP (inner_compare
, 1))
6929 compare_mode
= GET_MODE (inner_compare
);
6931 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6933 /* If the mode changed, we have to change SET_DEST, the mode in the
6934 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6935 a hard register, just build new versions with the proper mode. If it
6936 is a pseudo, we lose unless it is only time we set the pseudo, in
6937 which case we can safely change its mode. */
6938 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6940 if (can_change_dest_mode (dest
, 0, compare_mode
))
6942 unsigned int regno
= REGNO (dest
);
6945 if (regno
< FIRST_PSEUDO_REGISTER
)
6946 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6949 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6950 new_dest
= regno_reg_rtx
[regno
];
6953 SUBST (SET_DEST (x
), new_dest
);
6954 SUBST (XEXP (*cc_use
, 0), new_dest
);
6960 #endif /* SELECT_CC_MODE */
6962 /* If the code changed, we have to build a new comparison in
6963 undobuf.other_insn. */
6964 if (new_code
!= old_code
)
6966 int other_changed_previously
= other_changed
;
6967 unsigned HOST_WIDE_INT mask
;
6968 rtx old_cc_use
= *cc_use
;
6970 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6974 /* If the only change we made was to change an EQ into an NE or
6975 vice versa, OP0 has only one bit that might be nonzero, and OP1
6976 is zero, check if changing the user of the condition code will
6977 produce a valid insn. If it won't, we can keep the original code
6978 in that insn by surrounding our operation with an XOR. */
6980 if (((old_code
== NE
&& new_code
== EQ
)
6981 || (old_code
== EQ
&& new_code
== NE
))
6982 && ! other_changed_previously
&& op1
== const0_rtx
6983 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6984 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6986 rtx pat
= PATTERN (other_insn
), note
= 0;
6988 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6989 && ! check_asm_operands (pat
)))
6991 *cc_use
= old_cc_use
;
6994 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
7002 undobuf
.other_insn
= other_insn
;
7004 /* Don't generate a compare of a CC with 0, just use that CC. */
7005 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
7007 SUBST (SET_SRC (x
), op0
);
7010 /* Otherwise, if we didn't previously have the same COMPARE we
7011 want, create it from scratch. */
7012 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
7013 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
7015 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
7021 /* Get SET_SRC in a form where we have placed back any
7022 compound expressions. Then do the checks below. */
7023 src
= make_compound_operation (src
, SET
);
7024 SUBST (SET_SRC (x
), src
);
7027 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7028 and X being a REG or (subreg (reg)), we may be able to convert this to
7029 (set (subreg:m2 x) (op)).
7031 We can always do this if M1 is narrower than M2 because that means that
7032 we only care about the low bits of the result.
7034 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7035 perform a narrower operation than requested since the high-order bits will
7036 be undefined. On machine where it is defined, this transformation is safe
7037 as long as M1 and M2 have the same number of words. */
7039 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
7040 && !OBJECT_P (SUBREG_REG (src
))
7041 && (known_equal_after_align_up
7042 (GET_MODE_SIZE (GET_MODE (src
)),
7043 GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))),
7045 && (WORD_REGISTER_OPERATIONS
|| !paradoxical_subreg_p (src
))
7046 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
7047 && !REG_CAN_CHANGE_MODE_P (REGNO (dest
),
7048 GET_MODE (SUBREG_REG (src
)),
7051 || (GET_CODE (dest
) == SUBREG
7052 && REG_P (SUBREG_REG (dest
)))))
7054 SUBST (SET_DEST (x
),
7055 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
7057 SUBST (SET_SRC (x
), SUBREG_REG (src
));
7059 src
= SET_SRC (x
), dest
= SET_DEST (x
);
7062 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
7065 && partial_subreg_p (src
)
7066 && subreg_lowpart_p (src
))
7068 rtx inner
= SUBREG_REG (src
);
7069 machine_mode inner_mode
= GET_MODE (inner
);
7071 /* Here we make sure that we don't have a sign bit on. */
7072 if (val_signbit_known_clear_p (GET_MODE (src
),
7073 nonzero_bits (inner
, inner_mode
)))
7075 SUBST (SET_SRC (x
), inner
);
7080 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7081 would require a paradoxical subreg. Replace the subreg with a
7082 zero_extend to avoid the reload that would otherwise be required.
7083 Don't do this unless we have a scalar integer mode, otherwise the
7084 transformation is incorrect. */
7086 enum rtx_code extend_op
;
7087 if (paradoxical_subreg_p (src
)
7088 && MEM_P (SUBREG_REG (src
))
7089 && SCALAR_INT_MODE_P (GET_MODE (src
))
7090 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
7093 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
7098 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7099 are comparing an item known to be 0 or -1 against 0, use a logical
7100 operation instead. Check for one of the arms being an IOR of the other
7101 arm with some value. We compute three terms to be IOR'ed together. In
7102 practice, at most two will be nonzero. Then we do the IOR's. */
7104 if (GET_CODE (dest
) != PC
7105 && GET_CODE (src
) == IF_THEN_ELSE
7106 && is_int_mode (GET_MODE (src
), &int_mode
)
7107 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
7108 && XEXP (XEXP (src
, 0), 1) == const0_rtx
7109 && int_mode
== GET_MODE (XEXP (XEXP (src
, 0), 0))
7110 && (!HAVE_conditional_move
7111 || ! can_conditionally_move_p (int_mode
))
7112 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0), int_mode
)
7113 == GET_MODE_PRECISION (int_mode
))
7114 && ! side_effects_p (src
))
7116 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7117 ? XEXP (src
, 1) : XEXP (src
, 2));
7118 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7119 ? XEXP (src
, 2) : XEXP (src
, 1));
7120 rtx term1
= const0_rtx
, term2
, term3
;
7122 if (GET_CODE (true_rtx
) == IOR
7123 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
7124 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
7125 else if (GET_CODE (true_rtx
) == IOR
7126 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
7127 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
7128 else if (GET_CODE (false_rtx
) == IOR
7129 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
7130 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
7131 else if (GET_CODE (false_rtx
) == IOR
7132 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
7133 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
7135 term2
= simplify_gen_binary (AND
, int_mode
,
7136 XEXP (XEXP (src
, 0), 0), true_rtx
);
7137 term3
= simplify_gen_binary (AND
, int_mode
,
7138 simplify_gen_unary (NOT
, int_mode
,
7139 XEXP (XEXP (src
, 0), 0),
7144 simplify_gen_binary (IOR
, int_mode
,
7145 simplify_gen_binary (IOR
, int_mode
,
7152 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7153 whole thing fail. */
7154 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
7156 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
7159 /* Convert this into a field assignment operation, if possible. */
7160 return make_field_assignment (x
);
7163 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7167 simplify_logical (rtx x
)
7169 rtx op0
= XEXP (x
, 0);
7170 rtx op1
= XEXP (x
, 1);
7171 scalar_int_mode mode
;
7173 switch (GET_CODE (x
))
7176 /* We can call simplify_and_const_int only if we don't lose
7177 any (sign) bits when converting INTVAL (op1) to
7178 "unsigned HOST_WIDE_INT". */
7179 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
7180 && CONST_INT_P (op1
)
7181 && (HWI_COMPUTABLE_MODE_P (mode
)
7182 || INTVAL (op1
) > 0))
7184 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
7185 if (GET_CODE (x
) != AND
)
7192 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7193 apply the distributive law and then the inverse distributive
7194 law to see if things simplify. */
7195 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
7197 rtx result
= distribute_and_simplify_rtx (x
, 0);
7201 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
7203 rtx result
= distribute_and_simplify_rtx (x
, 1);
7210 /* If we have (ior (and A B) C), apply the distributive law and then
7211 the inverse distributive law to see if things simplify. */
7213 if (GET_CODE (op0
) == AND
)
7215 rtx result
= distribute_and_simplify_rtx (x
, 0);
7220 if (GET_CODE (op1
) == AND
)
7222 rtx result
= distribute_and_simplify_rtx (x
, 1);
7235 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7236 operations" because they can be replaced with two more basic operations.
7237 ZERO_EXTEND is also considered "compound" because it can be replaced with
7238 an AND operation, which is simpler, though only one operation.
7240 The function expand_compound_operation is called with an rtx expression
7241 and will convert it to the appropriate shifts and AND operations,
7242 simplifying at each stage.
7244 The function make_compound_operation is called to convert an expression
7245 consisting of shifts and ANDs into the equivalent compound expression.
7246 It is the inverse of this function, loosely speaking. */
7249 expand_compound_operation (rtx x
)
7251 unsigned HOST_WIDE_INT pos
= 0, len
;
7253 unsigned int modewidth
;
7255 scalar_int_mode inner_mode
;
7257 switch (GET_CODE (x
))
7263 /* We can't necessarily use a const_int for a multiword mode;
7264 it depends on implicitly extending the value.
7265 Since we don't know the right way to extend it,
7266 we can't tell whether the implicit way is right.
7268 Even for a mode that is no wider than a const_int,
7269 we can't win, because we need to sign extend one of its bits through
7270 the rest of it, and we don't know which bit. */
7271 if (CONST_INT_P (XEXP (x
, 0)))
7274 /* Reject modes that aren't scalar integers because turning vector
7275 or complex modes into shifts causes problems. */
7276 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7279 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7280 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7281 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7282 reloaded. If not for that, MEM's would very rarely be safe.
7284 Reject modes bigger than a word, because we might not be able
7285 to reference a two-register group starting with an arbitrary register
7286 (and currently gen_lowpart might crash for a SUBREG). */
7288 if (GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7291 len
= GET_MODE_PRECISION (inner_mode
);
7292 /* If the inner object has VOIDmode (the only way this can happen
7293 is if it is an ASM_OPERANDS), we can't do anything since we don't
7294 know how much masking to do. */
7306 /* If the operand is a CLOBBER, just return it. */
7307 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7310 if (!CONST_INT_P (XEXP (x
, 1))
7311 || !CONST_INT_P (XEXP (x
, 2)))
7314 /* Reject modes that aren't scalar integers because turning vector
7315 or complex modes into shifts causes problems. */
7316 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7319 len
= INTVAL (XEXP (x
, 1));
7320 pos
= INTVAL (XEXP (x
, 2));
7322 /* This should stay within the object being extracted, fail otherwise. */
7323 if (len
+ pos
> GET_MODE_PRECISION (inner_mode
))
7326 if (BITS_BIG_ENDIAN
)
7327 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
7335 /* We've rejected non-scalar operations by now. */
7336 scalar_int_mode mode
= as_a
<scalar_int_mode
> (GET_MODE (x
));
7338 /* Convert sign extension to zero extension, if we know that the high
7339 bit is not set, as this is easier to optimize. It will be converted
7340 back to cheaper alternative in make_extraction. */
7341 if (GET_CODE (x
) == SIGN_EXTEND
7342 && HWI_COMPUTABLE_MODE_P (mode
)
7343 && ((nonzero_bits (XEXP (x
, 0), inner_mode
)
7344 & ~(((unsigned HOST_WIDE_INT
) GET_MODE_MASK (inner_mode
)) >> 1))
7347 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7348 rtx temp2
= expand_compound_operation (temp
);
7350 /* Make sure this is a profitable operation. */
7351 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7352 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7354 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7355 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7361 /* We can optimize some special cases of ZERO_EXTEND. */
7362 if (GET_CODE (x
) == ZERO_EXTEND
)
7364 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7365 know that the last value didn't have any inappropriate bits
7367 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7368 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7369 && HWI_COMPUTABLE_MODE_P (mode
)
7370 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
)
7371 & ~GET_MODE_MASK (inner_mode
)) == 0)
7372 return XEXP (XEXP (x
, 0), 0);
7374 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7375 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7376 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7377 && subreg_lowpart_p (XEXP (x
, 0))
7378 && HWI_COMPUTABLE_MODE_P (mode
)
7379 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), mode
)
7380 & ~GET_MODE_MASK (inner_mode
)) == 0)
7381 return SUBREG_REG (XEXP (x
, 0));
7383 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7384 is a comparison and STORE_FLAG_VALUE permits. This is like
7385 the first case, but it works even when MODE is larger
7386 than HOST_WIDE_INT. */
7387 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7388 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7389 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7390 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7391 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7392 return XEXP (XEXP (x
, 0), 0);
7394 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7395 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7396 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7397 && subreg_lowpart_p (XEXP (x
, 0))
7398 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7399 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7400 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7401 return SUBREG_REG (XEXP (x
, 0));
7405 /* If we reach here, we want to return a pair of shifts. The inner
7406 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7407 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7408 logical depending on the value of UNSIGNEDP.
7410 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7411 converted into an AND of a shift.
7413 We must check for the case where the left shift would have a negative
7414 count. This can happen in a case like (x >> 31) & 255 on machines
7415 that can't shift by a constant. On those machines, we would first
7416 combine the shift with the AND to produce a variable-position
7417 extraction. Then the constant of 31 would be substituted in
7418 to produce such a position. */
7420 modewidth
= GET_MODE_PRECISION (mode
);
7421 if (modewidth
>= pos
+ len
)
7423 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7424 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7426 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7427 tem
, modewidth
- pos
- len
);
7428 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7429 mode
, tem
, modewidth
- len
);
7431 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7432 tem
= simplify_and_const_int (NULL_RTX
, mode
,
7433 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7436 (HOST_WIDE_INT_1U
<< len
) - 1);
7438 /* Any other cases we can't handle. */
7441 /* If we couldn't do this for some reason, return the original
7443 if (GET_CODE (tem
) == CLOBBER
)
7449 /* X is a SET which contains an assignment of one object into
7450 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7451 or certain SUBREGS). If possible, convert it into a series of
7454 We half-heartedly support variable positions, but do not at all
7455 support variable lengths. */
7458 expand_field_assignment (const_rtx x
)
7461 rtx pos
; /* Always counts from low bit. */
7463 rtx mask
, cleared
, masked
;
7464 scalar_int_mode compute_mode
;
7466 /* Loop until we find something we can't simplify. */
7469 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7470 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7472 rtx x0
= XEXP (SET_DEST (x
), 0);
7473 if (!GET_MODE_PRECISION (GET_MODE (x0
)).is_constant (&len
))
7475 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7476 pos
= gen_int_mode (subreg_lsb (XEXP (SET_DEST (x
), 0)),
7479 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7480 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7482 inner
= XEXP (SET_DEST (x
), 0);
7483 if (!GET_MODE_PRECISION (GET_MODE (inner
)).is_constant (&inner_len
))
7486 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7487 pos
= XEXP (SET_DEST (x
), 2);
7489 /* A constant position should stay within the width of INNER. */
7490 if (CONST_INT_P (pos
) && INTVAL (pos
) + len
> inner_len
)
7493 if (BITS_BIG_ENDIAN
)
7495 if (CONST_INT_P (pos
))
7496 pos
= GEN_INT (inner_len
- len
- INTVAL (pos
));
7497 else if (GET_CODE (pos
) == MINUS
7498 && CONST_INT_P (XEXP (pos
, 1))
7499 && INTVAL (XEXP (pos
, 1)) == inner_len
- len
)
7500 /* If position is ADJUST - X, new position is X. */
7501 pos
= XEXP (pos
, 0);
7503 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7504 gen_int_mode (inner_len
- len
,
7510 /* If the destination is a subreg that overwrites the whole of the inner
7511 register, we can move the subreg to the source. */
7512 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7513 /* We need SUBREGs to compute nonzero_bits properly. */
7514 && nonzero_sign_valid
7515 && !read_modify_subreg_p (SET_DEST (x
)))
7517 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7519 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7526 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7527 inner
= SUBREG_REG (inner
);
7529 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7530 if (!is_a
<scalar_int_mode
> (GET_MODE (inner
), &compute_mode
))
7532 /* Don't do anything for vector or complex integral types. */
7533 if (! FLOAT_MODE_P (GET_MODE (inner
)))
7536 /* Try to find an integral mode to pun with. */
7537 if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner
)), 0)
7538 .exists (&compute_mode
))
7541 inner
= gen_lowpart (compute_mode
, inner
);
7544 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7545 if (len
>= HOST_BITS_PER_WIDE_INT
)
7548 /* Don't try to compute in too wide unsupported modes. */
7549 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7552 /* Now compute the equivalent expression. Make a copy of INNER
7553 for the SET_DEST in case it is a MEM into which we will substitute;
7554 we don't want shared RTL in that case. */
7555 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7557 cleared
= simplify_gen_binary (AND
, compute_mode
,
7558 simplify_gen_unary (NOT
, compute_mode
,
7559 simplify_gen_binary (ASHIFT
,
7564 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7565 simplify_gen_binary (
7567 gen_lowpart (compute_mode
, SET_SRC (x
)),
7571 x
= gen_rtx_SET (copy_rtx (inner
),
7572 simplify_gen_binary (IOR
, compute_mode
,
7579 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7580 it is an RTX that represents the (variable) starting position; otherwise,
7581 POS is the (constant) starting bit position. Both are counted from the LSB.
7583 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7585 IN_DEST is nonzero if this is a reference in the destination of a SET.
7586 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7587 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7590 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7591 ZERO_EXTRACT should be built even for bits starting at bit 0.
7593 MODE is the desired mode of the result (if IN_DEST == 0).
7595 The result is an RTX for the extraction or NULL_RTX if the target
7599 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7600 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7601 int in_dest
, int in_compare
)
7603 /* This mode describes the size of the storage area
7604 to fetch the overall value from. Within that, we
7605 ignore the POS lowest bits, etc. */
7606 machine_mode is_mode
= GET_MODE (inner
);
7607 machine_mode inner_mode
;
7608 scalar_int_mode wanted_inner_mode
;
7609 scalar_int_mode wanted_inner_reg_mode
= word_mode
;
7610 scalar_int_mode pos_mode
= word_mode
;
7611 machine_mode extraction_mode
= word_mode
;
7613 rtx orig_pos_rtx
= pos_rtx
;
7614 HOST_WIDE_INT orig_pos
;
7616 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7617 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7619 if (GET_CODE (inner
) == SUBREG
7620 && subreg_lowpart_p (inner
)
7621 && (paradoxical_subreg_p (inner
)
7622 /* If trying or potentionally trying to extract
7623 bits outside of is_mode, don't look through
7624 non-paradoxical SUBREGs. See PR82192. */
7625 || (pos_rtx
== NULL_RTX
7626 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
)))))
7628 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7629 consider just the QI as the memory to extract from.
7630 The subreg adds or removes high bits; its mode is
7631 irrelevant to the meaning of this extraction,
7632 since POS and LEN count from the lsb. */
7633 if (MEM_P (SUBREG_REG (inner
)))
7634 is_mode
= GET_MODE (SUBREG_REG (inner
));
7635 inner
= SUBREG_REG (inner
);
7637 else if (GET_CODE (inner
) == ASHIFT
7638 && CONST_INT_P (XEXP (inner
, 1))
7639 && pos_rtx
== 0 && pos
== 0
7640 && len
> UINTVAL (XEXP (inner
, 1)))
7642 /* We're extracting the least significant bits of an rtx
7643 (ashift X (const_int C)), where LEN > C. Extract the
7644 least significant (LEN - C) bits of X, giving an rtx
7645 whose mode is MODE, then shift it left C times. */
7646 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7647 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7648 unsignedp
, in_dest
, in_compare
);
7650 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7652 else if (GET_CODE (inner
) == TRUNCATE
7653 /* If trying or potentionally trying to extract
7654 bits outside of is_mode, don't look through
7655 TRUNCATE. See PR82192. */
7656 && pos_rtx
== NULL_RTX
7657 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
)))
7658 inner
= XEXP (inner
, 0);
7660 inner_mode
= GET_MODE (inner
);
7662 /* See if this can be done without an extraction. We never can if the
7663 width of the field is not the same as that of some integer mode. For
7664 registers, we can only avoid the extraction if the position is at the
7665 low-order bit and this is either not in the destination or we have the
7666 appropriate STRICT_LOW_PART operation available.
7668 For MEM, we can avoid an extract if the field starts on an appropriate
7669 boundary and we can change the mode of the memory reference. */
7671 scalar_int_mode tmode
;
7672 if (int_mode_for_size (len
, 1).exists (&tmode
)
7673 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7675 && (pos
== 0 || REG_P (inner
))
7676 && (inner_mode
== tmode
7678 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7679 || reg_truncated_to_mode (tmode
, inner
))
7682 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7683 || (MEM_P (inner
) && pos_rtx
== 0
7685 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7686 : BITS_PER_UNIT
)) == 0
7687 /* We can't do this if we are widening INNER_MODE (it
7688 may not be aligned, for one thing). */
7689 && !paradoxical_subreg_p (tmode
, inner_mode
)
7690 && (inner_mode
== tmode
7691 || (! mode_dependent_address_p (XEXP (inner
, 0),
7692 MEM_ADDR_SPACE (inner
))
7693 && ! MEM_VOLATILE_P (inner
))))))
7695 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7696 field. If the original and current mode are the same, we need not
7697 adjust the offset. Otherwise, we do if bytes big endian.
7699 If INNER is not a MEM, get a piece consisting of just the field
7700 of interest (in this case POS % BITS_PER_WORD must be 0). */
7706 /* POS counts from lsb, but make OFFSET count in memory order. */
7707 if (BYTES_BIG_ENDIAN
)
7708 offset
= bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode
)
7711 offset
= pos
/ BITS_PER_UNIT
;
7713 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7715 else if (REG_P (inner
))
7717 if (tmode
!= inner_mode
)
7719 /* We can't call gen_lowpart in a DEST since we
7720 always want a SUBREG (see below) and it would sometimes
7721 return a new hard register. */
7725 = subreg_offset_from_lsb (tmode
, inner_mode
, pos
);
7727 /* Avoid creating invalid subregs, for example when
7728 simplifying (x>>32)&255. */
7729 if (!validate_subreg (tmode
, inner_mode
, inner
, offset
))
7732 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, offset
);
7735 new_rtx
= gen_lowpart (tmode
, inner
);
7741 new_rtx
= force_to_mode (inner
, tmode
,
7742 len
>= HOST_BITS_PER_WIDE_INT
7744 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7746 /* If this extraction is going into the destination of a SET,
7747 make a STRICT_LOW_PART unless we made a MEM. */
7750 return (MEM_P (new_rtx
) ? new_rtx
7751 : (GET_CODE (new_rtx
) != SUBREG
7752 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7753 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7758 if (CONST_SCALAR_INT_P (new_rtx
))
7759 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7760 mode
, new_rtx
, tmode
);
7762 /* If we know that no extraneous bits are set, and that the high
7763 bit is not set, convert the extraction to the cheaper of
7764 sign and zero extension, that are equivalent in these cases. */
7765 if (flag_expensive_optimizations
7766 && (HWI_COMPUTABLE_MODE_P (tmode
)
7767 && ((nonzero_bits (new_rtx
, tmode
)
7768 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7771 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7772 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7774 /* Prefer ZERO_EXTENSION, since it gives more information to
7776 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7777 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7782 /* Otherwise, sign- or zero-extend unless we already are in the
7785 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7789 /* Unless this is a COMPARE or we have a funny memory reference,
7790 don't do anything with zero-extending field extracts starting at
7791 the low-order bit since they are simple AND operations. */
7792 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7793 && ! in_compare
&& unsignedp
)
7796 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7797 if the position is not a constant and the length is not 1. In all
7798 other cases, we would only be going outside our object in cases when
7799 an original shift would have been undefined. */
7801 && ((pos_rtx
== 0 && maybe_gt (pos
+ len
, GET_MODE_PRECISION (is_mode
)))
7802 || (pos_rtx
!= 0 && len
!= 1)))
7805 enum extraction_pattern pattern
= (in_dest
? EP_insv
7806 : unsignedp
? EP_extzv
: EP_extv
);
7808 /* If INNER is not from memory, we want it to have the mode of a register
7809 extraction pattern's structure operand, or word_mode if there is no
7810 such pattern. The same applies to extraction_mode and pos_mode
7811 and their respective operands.
7813 For memory, assume that the desired extraction_mode and pos_mode
7814 are the same as for a register operation, since at present we don't
7815 have named patterns for aligned memory structures. */
7816 struct extraction_insn insn
;
7817 unsigned int inner_size
;
7818 if (GET_MODE_BITSIZE (inner_mode
).is_constant (&inner_size
)
7819 && get_best_reg_extraction_insn (&insn
, pattern
, inner_size
, mode
))
7821 wanted_inner_reg_mode
= insn
.struct_mode
.require ();
7822 pos_mode
= insn
.pos_mode
;
7823 extraction_mode
= insn
.field_mode
;
7826 /* Never narrow an object, since that might not be safe. */
7828 if (mode
!= VOIDmode
7829 && partial_subreg_p (extraction_mode
, mode
))
7830 extraction_mode
= mode
;
7833 wanted_inner_mode
= wanted_inner_reg_mode
;
7836 /* Be careful not to go beyond the extracted object and maintain the
7837 natural alignment of the memory. */
7838 wanted_inner_mode
= smallest_int_mode_for_size (len
);
7839 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7840 > GET_MODE_BITSIZE (wanted_inner_mode
))
7841 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
).require ();
7846 if (BITS_BIG_ENDIAN
)
7848 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7849 BITS_BIG_ENDIAN style. If position is constant, compute new
7850 position. Otherwise, build subtraction.
7851 Note that POS is relative to the mode of the original argument.
7852 If it's a MEM we need to recompute POS relative to that.
7853 However, if we're extracting from (or inserting into) a register,
7854 we want to recompute POS relative to wanted_inner_mode. */
7857 width
= GET_MODE_BITSIZE (wanted_inner_mode
);
7858 else if (!GET_MODE_BITSIZE (is_mode
).is_constant (&width
))
7862 pos
= width
- len
- pos
;
7865 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7866 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7868 /* POS may be less than 0 now, but we check for that below.
7869 Note that it can only be less than 0 if !MEM_P (inner). */
7872 /* If INNER has a wider mode, and this is a constant extraction, try to
7873 make it smaller and adjust the byte to point to the byte containing
7875 if (wanted_inner_mode
!= VOIDmode
7876 && inner_mode
!= wanted_inner_mode
7878 && partial_subreg_p (wanted_inner_mode
, is_mode
)
7880 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7881 && ! MEM_VOLATILE_P (inner
))
7883 poly_int64 offset
= 0;
7885 /* The computations below will be correct if the machine is big
7886 endian in both bits and bytes or little endian in bits and bytes.
7887 If it is mixed, we must adjust. */
7889 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7890 adjust OFFSET to compensate. */
7891 if (BYTES_BIG_ENDIAN
7892 && paradoxical_subreg_p (is_mode
, inner_mode
))
7893 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7895 /* We can now move to the desired byte. */
7896 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7897 * GET_MODE_SIZE (wanted_inner_mode
);
7898 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7900 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7901 && is_mode
!= wanted_inner_mode
)
7902 offset
= (GET_MODE_SIZE (is_mode
)
7903 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7905 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7908 /* If INNER is not memory, get it into the proper mode. If we are changing
7909 its mode, POS must be a constant and smaller than the size of the new
7911 else if (!MEM_P (inner
))
7913 /* On the LHS, don't create paradoxical subregs implicitely truncating
7914 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7916 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7920 if (GET_MODE (inner
) != wanted_inner_mode
7922 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7928 inner
= force_to_mode (inner
, wanted_inner_mode
,
7930 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7932 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7937 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7938 have to zero extend. Otherwise, we can just use a SUBREG.
7940 We dealt with constant rtxes earlier, so pos_rtx cannot
7941 have VOIDmode at this point. */
7943 && (GET_MODE_SIZE (pos_mode
)
7944 > GET_MODE_SIZE (as_a
<scalar_int_mode
> (GET_MODE (pos_rtx
)))))
7946 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7947 GET_MODE (pos_rtx
));
7949 /* If we know that no extraneous bits are set, and that the high
7950 bit is not set, convert extraction to cheaper one - either
7951 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7953 if (flag_expensive_optimizations
7954 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7955 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7956 & ~(((unsigned HOST_WIDE_INT
)
7957 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7961 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7962 GET_MODE (pos_rtx
));
7964 /* Prefer ZERO_EXTENSION, since it gives more information to
7966 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7967 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7973 /* Make POS_RTX unless we already have it and it is correct. If we don't
7974 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7976 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7977 pos_rtx
= orig_pos_rtx
;
7979 else if (pos_rtx
== 0)
7980 pos_rtx
= GEN_INT (pos
);
7982 /* Make the required operation. See if we can use existing rtx. */
7983 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7984 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7986 new_rtx
= gen_lowpart (mode
, new_rtx
);
7991 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7992 can be commuted with any other operations in X. Return X without
7993 that shift if so. */
7996 extract_left_shift (scalar_int_mode mode
, rtx x
, int count
)
7998 enum rtx_code code
= GET_CODE (x
);
8004 /* This is the shift itself. If it is wide enough, we will return
8005 either the value being shifted if the shift count is equal to
8006 COUNT or a shift for the difference. */
8007 if (CONST_INT_P (XEXP (x
, 1))
8008 && INTVAL (XEXP (x
, 1)) >= count
)
8009 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
8010 INTVAL (XEXP (x
, 1)) - count
);
8014 if ((tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
8015 return simplify_gen_unary (code
, mode
, tem
, mode
);
8019 case PLUS
: case IOR
: case XOR
: case AND
:
8020 /* If we can safely shift this constant and we find the inner shift,
8021 make a new operation. */
8022 if (CONST_INT_P (XEXP (x
, 1))
8023 && (UINTVAL (XEXP (x
, 1))
8024 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
8025 && (tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
8027 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
8028 return simplify_gen_binary (code
, mode
, tem
,
8029 gen_int_mode (val
, mode
));
8040 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8041 level of the expression and MODE is its mode. IN_CODE is as for
8042 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8043 that should be used when recursing on operands of *X_PTR.
8045 There are two possible actions:
8047 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8048 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8050 - Return a new rtx, which the caller returns directly. */
8053 make_compound_operation_int (scalar_int_mode mode
, rtx
*x_ptr
,
8054 enum rtx_code in_code
,
8055 enum rtx_code
*next_code_ptr
)
8058 enum rtx_code next_code
= *next_code_ptr
;
8059 enum rtx_code code
= GET_CODE (x
);
8060 int mode_width
= GET_MODE_PRECISION (mode
);
8065 scalar_int_mode inner_mode
;
8066 bool equality_comparison
= false;
8070 equality_comparison
= true;
8074 /* Process depending on the code of this operation. If NEW is set
8075 nonzero, it will be returned. */
8080 /* Convert shifts by constants into multiplications if inside
8082 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
8083 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8084 && INTVAL (XEXP (x
, 1)) >= 0)
8086 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
8087 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
8089 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8090 if (GET_CODE (new_rtx
) == NEG
)
8092 new_rtx
= XEXP (new_rtx
, 0);
8095 multval
= trunc_int_for_mode (multval
, mode
);
8096 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
8103 lhs
= make_compound_operation (lhs
, next_code
);
8104 rhs
= make_compound_operation (rhs
, next_code
);
8105 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
8107 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
8109 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8111 else if (GET_CODE (lhs
) == MULT
8112 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
8114 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
8115 simplify_gen_unary (NEG
, mode
,
8118 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8122 SUBST (XEXP (x
, 0), lhs
);
8123 SUBST (XEXP (x
, 1), rhs
);
8125 maybe_swap_commutative_operands (x
);
8131 lhs
= make_compound_operation (lhs
, next_code
);
8132 rhs
= make_compound_operation (rhs
, next_code
);
8133 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
8135 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
8137 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8139 else if (GET_CODE (rhs
) == MULT
8140 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
8142 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
8143 simplify_gen_unary (NEG
, mode
,
8146 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8150 SUBST (XEXP (x
, 0), lhs
);
8151 SUBST (XEXP (x
, 1), rhs
);
8156 /* If the second operand is not a constant, we can't do anything
8158 if (!CONST_INT_P (XEXP (x
, 1)))
8161 /* If the constant is a power of two minus one and the first operand
8162 is a logical right shift, make an extraction. */
8163 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8164 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8166 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8167 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1),
8168 i
, 1, 0, in_code
== COMPARE
);
8171 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8172 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
8173 && subreg_lowpart_p (XEXP (x
, 0))
8174 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (XEXP (x
, 0))),
8176 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
8177 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8179 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
8180 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
8181 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
8183 i
, 1, 0, in_code
== COMPARE
);
8185 /* If we narrowed the mode when dropping the subreg, then we lose. */
8186 if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
))
8189 /* If that didn't give anything, see if the AND simplifies on
8191 if (!new_rtx
&& i
>= 0)
8193 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8194 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
8195 0, in_code
== COMPARE
);
8198 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8199 else if ((GET_CODE (XEXP (x
, 0)) == XOR
8200 || GET_CODE (XEXP (x
, 0)) == IOR
)
8201 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
8202 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
8203 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8205 /* Apply the distributive law, and then try to make extractions. */
8206 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
8207 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
8209 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
8211 new_rtx
= make_compound_operation (new_rtx
, in_code
);
8214 /* If we are have (and (rotate X C) M) and C is larger than the number
8215 of bits in M, this is an extraction. */
8217 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
8218 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8219 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
8220 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
8222 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8223 new_rtx
= make_extraction (mode
, new_rtx
,
8224 (GET_MODE_PRECISION (mode
)
8225 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8226 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8229 /* On machines without logical shifts, if the operand of the AND is
8230 a logical shift and our mask turns off all the propagated sign
8231 bits, we can replace the logical shift with an arithmetic shift. */
8232 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8233 && !have_insn_for (LSHIFTRT
, mode
)
8234 && have_insn_for (ASHIFTRT
, mode
)
8235 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8236 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8237 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8238 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8240 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8242 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8243 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8245 gen_rtx_ASHIFTRT (mode
,
8246 make_compound_operation (XEXP (XEXP (x
,
8250 XEXP (XEXP (x
, 0), 1)));
8253 /* If the constant is one less than a power of two, this might be
8254 representable by an extraction even if no shift is present.
8255 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8256 we are in a COMPARE. */
8257 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8258 new_rtx
= make_extraction (mode
,
8259 make_compound_operation (XEXP (x
, 0),
8261 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8263 /* If we are in a comparison and this is an AND with a power of two,
8264 convert this into the appropriate bit extract. */
8265 else if (in_code
== COMPARE
8266 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8267 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8268 new_rtx
= make_extraction (mode
,
8269 make_compound_operation (XEXP (x
, 0),
8271 i
, NULL_RTX
, 1, 1, 0, 1);
8273 /* If the one operand is a paradoxical subreg of a register or memory and
8274 the constant (limited to the smaller mode) has only zero bits where
8275 the sub expression has known zero bits, this can be expressed as
8277 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8281 sub
= XEXP (XEXP (x
, 0), 0);
8282 machine_mode sub_mode
= GET_MODE (sub
);
8284 if ((REG_P (sub
) || MEM_P (sub
))
8285 && GET_MODE_PRECISION (sub_mode
).is_constant (&sub_width
)
8286 && sub_width
< mode_width
)
8288 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8289 unsigned HOST_WIDE_INT mask
;
8291 /* original AND constant with all the known zero bits set */
8292 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8293 if ((mask
& mode_mask
) == mode_mask
)
8295 new_rtx
= make_compound_operation (sub
, next_code
);
8296 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0, sub_width
,
8297 1, 0, in_code
== COMPARE
);
8305 /* If the sign bit is known to be zero, replace this with an
8306 arithmetic shift. */
8307 if (have_insn_for (ASHIFTRT
, mode
)
8308 && ! have_insn_for (LSHIFTRT
, mode
)
8309 && mode_width
<= HOST_BITS_PER_WIDE_INT
8310 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8312 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8313 make_compound_operation (XEXP (x
, 0),
8325 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8326 this is a SIGN_EXTRACT. */
8327 if (CONST_INT_P (rhs
)
8328 && GET_CODE (lhs
) == ASHIFT
8329 && CONST_INT_P (XEXP (lhs
, 1))
8330 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8331 && INTVAL (XEXP (lhs
, 1)) >= 0
8332 && INTVAL (rhs
) < mode_width
)
8334 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8335 new_rtx
= make_extraction (mode
, new_rtx
,
8336 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8337 NULL_RTX
, mode_width
- INTVAL (rhs
),
8338 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8342 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8343 If so, try to merge the shifts into a SIGN_EXTEND. We could
8344 also do this for some cases of SIGN_EXTRACT, but it doesn't
8345 seem worth the effort; the case checked for occurs on Alpha. */
8348 && ! (GET_CODE (lhs
) == SUBREG
8349 && (OBJECT_P (SUBREG_REG (lhs
))))
8350 && CONST_INT_P (rhs
)
8351 && INTVAL (rhs
) >= 0
8352 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8353 && INTVAL (rhs
) < mode_width
8354 && (new_rtx
= extract_left_shift (mode
, lhs
, INTVAL (rhs
))) != 0)
8355 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
,
8357 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8358 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8363 /* Call ourselves recursively on the inner expression. If we are
8364 narrowing the object and it has a different RTL code from
8365 what it originally did, do this SUBREG as a force_to_mode. */
8367 rtx inner
= SUBREG_REG (x
), simplified
;
8368 enum rtx_code subreg_code
= in_code
;
8370 /* If the SUBREG is masking of a logical right shift,
8371 make an extraction. */
8372 if (GET_CODE (inner
) == LSHIFTRT
8373 && is_a
<scalar_int_mode
> (GET_MODE (inner
), &inner_mode
)
8374 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (inner_mode
)
8375 && CONST_INT_P (XEXP (inner
, 1))
8376 && UINTVAL (XEXP (inner
, 1)) < GET_MODE_PRECISION (inner_mode
)
8377 && subreg_lowpart_p (x
))
8379 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8380 int width
= GET_MODE_PRECISION (inner_mode
)
8381 - INTVAL (XEXP (inner
, 1));
8382 if (width
> mode_width
)
8384 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8385 width
, 1, 0, in_code
== COMPARE
);
8389 /* If in_code is COMPARE, it isn't always safe to pass it through
8390 to the recursive make_compound_operation call. */
8391 if (subreg_code
== COMPARE
8392 && (!subreg_lowpart_p (x
)
8393 || GET_CODE (inner
) == SUBREG
8394 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8395 is (const_int 0), rather than
8396 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8397 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8398 for non-equality comparisons against 0 is not equivalent
8399 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8400 || (GET_CODE (inner
) == AND
8401 && CONST_INT_P (XEXP (inner
, 1))
8402 && partial_subreg_p (x
)
8403 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8404 >= GET_MODE_BITSIZE (mode
) - 1)))
8407 tem
= make_compound_operation (inner
, subreg_code
);
8410 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8414 if (GET_CODE (tem
) != GET_CODE (inner
)
8415 && partial_subreg_p (x
)
8416 && subreg_lowpart_p (x
))
8419 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8421 /* If we have something other than a SUBREG, we might have
8422 done an expansion, so rerun ourselves. */
8423 if (GET_CODE (newer
) != SUBREG
)
8424 newer
= make_compound_operation (newer
, in_code
);
8426 /* force_to_mode can expand compounds. If it just re-expanded
8427 the compound, use gen_lowpart to convert to the desired
8429 if (rtx_equal_p (newer
, x
)
8430 /* Likewise if it re-expanded the compound only partially.
8431 This happens for SUBREG of ZERO_EXTRACT if they extract
8432 the same number of bits. */
8433 || (GET_CODE (newer
) == SUBREG
8434 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8435 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8436 && GET_CODE (inner
) == AND
8437 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8438 return gen_lowpart (GET_MODE (x
), tem
);
8453 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8454 *next_code_ptr
= next_code
;
8458 /* Look at the expression rooted at X. Look for expressions
8459 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8460 Form these expressions.
8462 Return the new rtx, usually just X.
8464 Also, for machines like the VAX that don't have logical shift insns,
8465 try to convert logical to arithmetic shift operations in cases where
8466 they are equivalent. This undoes the canonicalizations to logical
8467 shifts done elsewhere.
8469 We try, as much as possible, to re-use rtl expressions to save memory.
8471 IN_CODE says what kind of expression we are processing. Normally, it is
8472 SET. In a memory address it is MEM. When processing the arguments of
8473 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8474 precisely it is an equality comparison against zero. */
8477 make_compound_operation (rtx x
, enum rtx_code in_code
)
8479 enum rtx_code code
= GET_CODE (x
);
8482 enum rtx_code next_code
;
8485 /* Select the code to be used in recursive calls. Once we are inside an
8486 address, we stay there. If we have a comparison, set to COMPARE,
8487 but once inside, go back to our default of SET. */
8489 next_code
= (code
== MEM
? MEM
8490 : ((code
== COMPARE
|| COMPARISON_P (x
))
8491 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8492 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8494 scalar_int_mode mode
;
8495 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
8497 rtx new_rtx
= make_compound_operation_int (mode
, &x
, in_code
,
8501 code
= GET_CODE (x
);
8504 /* Now recursively process each operand of this operation. We need to
8505 handle ZERO_EXTEND specially so that we don't lose track of the
8507 if (code
== ZERO_EXTEND
)
8509 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8510 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8511 new_rtx
, GET_MODE (XEXP (x
, 0)));
8514 SUBST (XEXP (x
, 0), new_rtx
);
8518 fmt
= GET_RTX_FORMAT (code
);
8519 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8522 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8523 SUBST (XEXP (x
, i
), new_rtx
);
8525 else if (fmt
[i
] == 'E')
8526 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8528 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8529 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8532 maybe_swap_commutative_operands (x
);
8536 /* Given M see if it is a value that would select a field of bits
8537 within an item, but not the entire word. Return -1 if not.
8538 Otherwise, return the starting position of the field, where 0 is the
8541 *PLEN is set to the length of the field. */
8544 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8546 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8547 int pos
= m
? ctz_hwi (m
) : -1;
8551 /* Now shift off the low-order zero bits and see if we have a
8552 power of two minus 1. */
8553 len
= exact_log2 ((m
>> pos
) + 1);
8562 /* If X refers to a register that equals REG in value, replace these
8563 references with REG. */
8565 canon_reg_for_combine (rtx x
, rtx reg
)
8572 enum rtx_code code
= GET_CODE (x
);
8573 switch (GET_RTX_CLASS (code
))
8576 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8577 if (op0
!= XEXP (x
, 0))
8578 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8583 case RTX_COMM_ARITH
:
8584 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8585 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8586 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8587 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8591 case RTX_COMM_COMPARE
:
8592 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8593 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8594 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8595 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8596 GET_MODE (op0
), op0
, op1
);
8600 case RTX_BITFIELD_OPS
:
8601 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8602 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8603 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8604 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8605 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8606 GET_MODE (op0
), op0
, op1
, op2
);
8612 if (rtx_equal_p (get_last_value (reg
), x
)
8613 || rtx_equal_p (reg
, get_last_value (x
)))
8622 fmt
= GET_RTX_FORMAT (code
);
8624 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8627 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8628 if (op
!= XEXP (x
, i
))
8638 else if (fmt
[i
] == 'E')
8641 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8643 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8644 if (op
!= XVECEXP (x
, i
, j
))
8651 XVECEXP (x
, i
, j
) = op
;
8662 /* Return X converted to MODE. If the value is already truncated to
8663 MODE we can just return a subreg even though in the general case we
8664 would need an explicit truncation. */
8667 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8669 if (!CONST_INT_P (x
)
8670 && partial_subreg_p (mode
, GET_MODE (x
))
8671 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8672 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8674 /* Bit-cast X into an integer mode. */
8675 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8676 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)).require (), x
);
8677 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
).require (),
8681 return gen_lowpart (mode
, x
);
8684 /* See if X can be simplified knowing that we will only refer to it in
8685 MODE and will only refer to those bits that are nonzero in MASK.
8686 If other bits are being computed or if masking operations are done
8687 that select a superset of the bits in MASK, they can sometimes be
8690 Return a possibly simplified expression, but always convert X to
8691 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8693 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8694 are all off in X. This is used when X will be complemented, by either
8695 NOT, NEG, or XOR. */
8698 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8701 enum rtx_code code
= GET_CODE (x
);
8702 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8703 machine_mode op_mode
;
8704 unsigned HOST_WIDE_INT nonzero
;
8706 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8707 code below will do the wrong thing since the mode of such an
8708 expression is VOIDmode.
8710 Also do nothing if X is a CLOBBER; this can happen if X was
8711 the return value from a call to gen_lowpart. */
8712 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8715 /* We want to perform the operation in its present mode unless we know
8716 that the operation is valid in MODE, in which case we do the operation
8718 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8719 && have_insn_for (code
, mode
))
8720 ? mode
: GET_MODE (x
));
8722 /* It is not valid to do a right-shift in a narrower mode
8723 than the one it came in with. */
8724 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8725 && partial_subreg_p (mode
, GET_MODE (x
)))
8726 op_mode
= GET_MODE (x
);
8728 /* Truncate MASK to fit OP_MODE. */
8730 mask
&= GET_MODE_MASK (op_mode
);
8732 /* Determine what bits of X are guaranteed to be (non)zero. */
8733 nonzero
= nonzero_bits (x
, mode
);
8735 /* If none of the bits in X are needed, return a zero. */
8736 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8739 /* If X is a CONST_INT, return a new one. Do this here since the
8740 test below will fail. */
8741 if (CONST_INT_P (x
))
8743 if (SCALAR_INT_MODE_P (mode
))
8744 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8747 x
= GEN_INT (INTVAL (x
) & mask
);
8748 return gen_lowpart_common (mode
, x
);
8752 /* If X is narrower than MODE and we want all the bits in X's mode, just
8753 get X in the proper mode. */
8754 if (paradoxical_subreg_p (mode
, GET_MODE (x
))
8755 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8756 return gen_lowpart (mode
, x
);
8758 /* We can ignore the effect of a SUBREG if it narrows the mode or
8759 if the constant masks to zero all the bits the mode doesn't have. */
8760 if (GET_CODE (x
) == SUBREG
8761 && subreg_lowpart_p (x
)
8762 && (partial_subreg_p (x
)
8764 & GET_MODE_MASK (GET_MODE (x
))
8765 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))) == 0))
8766 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8768 scalar_int_mode int_mode
, xmode
;
8769 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
8770 && is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
8771 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8773 return force_int_to_mode (x
, int_mode
, xmode
,
8774 as_a
<scalar_int_mode
> (op_mode
),
8777 return gen_lowpart_or_truncate (mode
, x
);
8780 /* Subroutine of force_to_mode that handles cases in which both X and
8781 the result are scalar integers. MODE is the mode of the result,
8782 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8783 is preferred for simplified versions of X. The other arguments
8784 are as for force_to_mode. */
8787 force_int_to_mode (rtx x
, scalar_int_mode mode
, scalar_int_mode xmode
,
8788 scalar_int_mode op_mode
, unsigned HOST_WIDE_INT mask
,
8791 enum rtx_code code
= GET_CODE (x
);
8792 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8793 unsigned HOST_WIDE_INT fuller_mask
;
8795 poly_int64 const_op0
;
8797 /* When we have an arithmetic operation, or a shift whose count we
8798 do not know, we need to assume that all bits up to the highest-order
8799 bit in MASK will be needed. This is how we form such a mask. */
8800 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8801 fuller_mask
= HOST_WIDE_INT_M1U
;
8803 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8809 /* If X is a (clobber (const_int)), return it since we know we are
8810 generating something that won't match. */
8817 x
= expand_compound_operation (x
);
8818 if (GET_CODE (x
) != code
)
8819 return force_to_mode (x
, mode
, mask
, next_select
);
8823 /* Similarly for a truncate. */
8824 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8827 /* If this is an AND with a constant, convert it into an AND
8828 whose constant is the AND of that constant with MASK. If it
8829 remains an AND of MASK, delete it since it is redundant. */
8831 if (CONST_INT_P (XEXP (x
, 1)))
8833 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8834 mask
& INTVAL (XEXP (x
, 1)));
8837 /* If X is still an AND, see if it is an AND with a mask that
8838 is just some low-order bits. If so, and it is MASK, we don't
8841 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8842 && (INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (xmode
)) == mask
)
8845 /* If it remains an AND, try making another AND with the bits
8846 in the mode mask that aren't in MASK turned on. If the
8847 constant in the AND is wide enough, this might make a
8848 cheaper constant. */
8850 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8851 && GET_MODE_MASK (xmode
) != mask
8852 && HWI_COMPUTABLE_MODE_P (xmode
))
8854 unsigned HOST_WIDE_INT cval
8855 = UINTVAL (XEXP (x
, 1)) | (GET_MODE_MASK (xmode
) & ~mask
);
8858 y
= simplify_gen_binary (AND
, xmode
, XEXP (x
, 0),
8859 gen_int_mode (cval
, xmode
));
8860 if (set_src_cost (y
, xmode
, optimize_this_for_speed_p
)
8861 < set_src_cost (x
, xmode
, optimize_this_for_speed_p
))
8871 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8872 low-order bits (as in an alignment operation) and FOO is already
8873 aligned to that boundary, mask C1 to that boundary as well.
8874 This may eliminate that PLUS and, later, the AND. */
8877 unsigned int width
= GET_MODE_PRECISION (mode
);
8878 unsigned HOST_WIDE_INT smask
= mask
;
8880 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8881 number, sign extend it. */
8883 if (width
< HOST_BITS_PER_WIDE_INT
8884 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8885 smask
|= HOST_WIDE_INT_M1U
<< width
;
8887 if (CONST_INT_P (XEXP (x
, 1))
8888 && pow2p_hwi (- smask
)
8889 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8890 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8891 return force_to_mode (plus_constant (xmode
, XEXP (x
, 0),
8892 (INTVAL (XEXP (x
, 1)) & smask
)),
8893 mode
, smask
, next_select
);
8899 /* Substituting into the operands of a widening MULT is not likely to
8900 create RTL matching a machine insn. */
8902 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8903 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8904 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8905 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8906 && REG_P (XEXP (XEXP (x
, 0), 0))
8907 && REG_P (XEXP (XEXP (x
, 1), 0)))
8908 return gen_lowpart_or_truncate (mode
, x
);
8910 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8911 most significant bit in MASK since carries from those bits will
8912 affect the bits we are interested in. */
8917 /* If X is (minus C Y) where C's least set bit is larger than any bit
8918 in the mask, then we may replace with (neg Y). */
8919 if (poly_int_rtx_p (XEXP (x
, 0), &const_op0
)
8920 && (unsigned HOST_WIDE_INT
) known_alignment (const_op0
) > mask
)
8922 x
= simplify_gen_unary (NEG
, xmode
, XEXP (x
, 1), xmode
);
8923 return force_to_mode (x
, mode
, mask
, next_select
);
8926 /* Similarly, if C contains every bit in the fuller_mask, then we may
8927 replace with (not Y). */
8928 if (CONST_INT_P (XEXP (x
, 0))
8929 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8931 x
= simplify_gen_unary (NOT
, xmode
, XEXP (x
, 1), xmode
);
8932 return force_to_mode (x
, mode
, mask
, next_select
);
8940 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8941 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8942 operation which may be a bitfield extraction. Ensure that the
8943 constant we form is not wider than the mode of X. */
8945 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8946 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8947 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8948 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8949 && CONST_INT_P (XEXP (x
, 1))
8950 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8951 + floor_log2 (INTVAL (XEXP (x
, 1))))
8952 < GET_MODE_PRECISION (xmode
))
8953 && (UINTVAL (XEXP (x
, 1))
8954 & ~nonzero_bits (XEXP (x
, 0), xmode
)) == 0)
8956 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8957 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8959 temp
= simplify_gen_binary (GET_CODE (x
), xmode
,
8960 XEXP (XEXP (x
, 0), 0), temp
);
8961 x
= simplify_gen_binary (LSHIFTRT
, xmode
, temp
,
8962 XEXP (XEXP (x
, 0), 1));
8963 return force_to_mode (x
, mode
, mask
, next_select
);
8967 /* For most binary operations, just propagate into the operation and
8968 change the mode if we have an operation of that mode. */
8970 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8971 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8973 /* If we ended up truncating both operands, truncate the result of the
8974 operation instead. */
8975 if (GET_CODE (op0
) == TRUNCATE
8976 && GET_CODE (op1
) == TRUNCATE
)
8978 op0
= XEXP (op0
, 0);
8979 op1
= XEXP (op1
, 0);
8982 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8983 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8985 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8987 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8993 /* For left shifts, do the same, but just for the first operand.
8994 However, we cannot do anything with shifts where we cannot
8995 guarantee that the counts are smaller than the size of the mode
8996 because such a count will have a different meaning in a
8999 if (! (CONST_INT_P (XEXP (x
, 1))
9000 && INTVAL (XEXP (x
, 1)) >= 0
9001 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
9002 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
9003 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
9004 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
9007 /* If the shift count is a constant and we can do arithmetic in
9008 the mode of the shift, refine which bits we need. Otherwise, use the
9009 conservative form of the mask. */
9010 if (CONST_INT_P (XEXP (x
, 1))
9011 && INTVAL (XEXP (x
, 1)) >= 0
9012 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
9013 && HWI_COMPUTABLE_MODE_P (op_mode
))
9014 mask
>>= INTVAL (XEXP (x
, 1));
9018 op0
= gen_lowpart_or_truncate (op_mode
,
9019 force_to_mode (XEXP (x
, 0), mode
,
9020 mask
, next_select
));
9022 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
9024 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
9030 /* Here we can only do something if the shift count is a constant,
9031 this shift constant is valid for the host, and we can do arithmetic
9034 if (CONST_INT_P (XEXP (x
, 1))
9035 && INTVAL (XEXP (x
, 1)) >= 0
9036 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
9037 && HWI_COMPUTABLE_MODE_P (op_mode
))
9039 rtx inner
= XEXP (x
, 0);
9040 unsigned HOST_WIDE_INT inner_mask
;
9042 /* Select the mask of the bits we need for the shift operand. */
9043 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
9045 /* We can only change the mode of the shift if we can do arithmetic
9046 in the mode of the shift and INNER_MASK is no wider than the
9047 width of X's mode. */
9048 if ((inner_mask
& ~GET_MODE_MASK (xmode
)) != 0)
9051 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
9053 if (xmode
!= op_mode
|| inner
!= XEXP (x
, 0))
9055 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
9060 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9061 shift and AND produces only copies of the sign bit (C2 is one less
9062 than a power of two), we can do this with just a shift. */
9064 if (GET_CODE (x
) == LSHIFTRT
9065 && CONST_INT_P (XEXP (x
, 1))
9066 /* The shift puts one of the sign bit copies in the least significant
9068 && ((INTVAL (XEXP (x
, 1))
9069 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
9070 >= GET_MODE_PRECISION (xmode
))
9071 && pow2p_hwi (mask
+ 1)
9072 /* Number of bits left after the shift must be more than the mask
9074 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
9075 <= GET_MODE_PRECISION (xmode
))
9076 /* Must be more sign bit copies than the mask needs. */
9077 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
9078 >= exact_log2 (mask
+ 1)))
9080 int nbits
= GET_MODE_PRECISION (xmode
) - exact_log2 (mask
+ 1);
9081 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0),
9082 gen_int_shift_amount (xmode
, nbits
));
9087 /* If we are just looking for the sign bit, we don't need this shift at
9088 all, even if it has a variable count. */
9089 if (val_signbit_p (xmode
, mask
))
9090 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9092 /* If this is a shift by a constant, get a mask that contains those bits
9093 that are not copies of the sign bit. We then have two cases: If
9094 MASK only includes those bits, this can be a logical shift, which may
9095 allow simplifications. If MASK is a single-bit field not within
9096 those bits, we are requesting a copy of the sign bit and hence can
9097 shift the sign bit to the appropriate location. */
9099 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
9100 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
9102 unsigned HOST_WIDE_INT nonzero
;
9105 /* If the considered data is wider than HOST_WIDE_INT, we can't
9106 represent a mask for all its bits in a single scalar.
9107 But we only care about the lower bits, so calculate these. */
9109 if (GET_MODE_PRECISION (xmode
) > HOST_BITS_PER_WIDE_INT
)
9111 nonzero
= HOST_WIDE_INT_M1U
;
9113 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9114 is the number of bits a full-width mask would have set.
9115 We need only shift if these are fewer than nonzero can
9116 hold. If not, we must keep all bits set in nonzero. */
9118 if (GET_MODE_PRECISION (xmode
) - INTVAL (XEXP (x
, 1))
9119 < HOST_BITS_PER_WIDE_INT
)
9120 nonzero
>>= INTVAL (XEXP (x
, 1))
9121 + HOST_BITS_PER_WIDE_INT
9122 - GET_MODE_PRECISION (xmode
);
9126 nonzero
= GET_MODE_MASK (xmode
);
9127 nonzero
>>= INTVAL (XEXP (x
, 1));
9130 if ((mask
& ~nonzero
) == 0)
9132 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, xmode
,
9133 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
9134 if (GET_CODE (x
) != ASHIFTRT
)
9135 return force_to_mode (x
, mode
, mask
, next_select
);
9138 else if ((i
= exact_log2 (mask
)) >= 0)
9140 x
= simplify_shift_const
9141 (NULL_RTX
, LSHIFTRT
, xmode
, XEXP (x
, 0),
9142 GET_MODE_PRECISION (xmode
) - 1 - i
);
9144 if (GET_CODE (x
) != ASHIFTRT
)
9145 return force_to_mode (x
, mode
, mask
, next_select
);
9149 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9150 even if the shift count isn't a constant. */
9152 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0), XEXP (x
, 1));
9156 /* If this is a zero- or sign-extension operation that just affects bits
9157 we don't care about, remove it. Be sure the call above returned
9158 something that is still a shift. */
9160 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
9161 && CONST_INT_P (XEXP (x
, 1))
9162 && INTVAL (XEXP (x
, 1)) >= 0
9163 && (INTVAL (XEXP (x
, 1))
9164 <= GET_MODE_PRECISION (xmode
) - (floor_log2 (mask
) + 1))
9165 && GET_CODE (XEXP (x
, 0)) == ASHIFT
9166 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
9167 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
9174 /* If the shift count is constant and we can do computations
9175 in the mode of X, compute where the bits we care about are.
9176 Otherwise, we can't do anything. Don't change the mode of
9177 the shift or propagate MODE into the shift, though. */
9178 if (CONST_INT_P (XEXP (x
, 1))
9179 && INTVAL (XEXP (x
, 1)) >= 0)
9181 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
9182 xmode
, gen_int_mode (mask
, xmode
),
9184 if (temp
&& CONST_INT_P (temp
))
9185 x
= simplify_gen_binary (code
, xmode
,
9186 force_to_mode (XEXP (x
, 0), xmode
,
9187 INTVAL (temp
), next_select
),
9193 /* If we just want the low-order bit, the NEG isn't needed since it
9194 won't change the low-order bit. */
9196 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
9198 /* We need any bits less significant than the most significant bit in
9199 MASK since carries from those bits will affect the bits we are
9205 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9206 same as the XOR case above. Ensure that the constant we form is not
9207 wider than the mode of X. */
9209 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
9210 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
9211 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
9212 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
9213 < GET_MODE_PRECISION (xmode
))
9214 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
9216 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)), xmode
);
9217 temp
= simplify_gen_binary (XOR
, xmode
, XEXP (XEXP (x
, 0), 0), temp
);
9218 x
= simplify_gen_binary (LSHIFTRT
, xmode
,
9219 temp
, XEXP (XEXP (x
, 0), 1));
9221 return force_to_mode (x
, mode
, mask
, next_select
);
9224 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9225 use the full mask inside the NOT. */
9229 op0
= gen_lowpart_or_truncate (op_mode
,
9230 force_to_mode (XEXP (x
, 0), mode
, mask
,
9232 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
9234 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
9240 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9241 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9242 which is equal to STORE_FLAG_VALUE. */
9243 if ((mask
& ~STORE_FLAG_VALUE
) == 0
9244 && XEXP (x
, 1) == const0_rtx
9245 && GET_MODE (XEXP (x
, 0)) == mode
9246 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
9247 && (nonzero_bits (XEXP (x
, 0), mode
)
9248 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
9249 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9254 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9255 written in a narrower mode. We play it safe and do not do so. */
9257 op0
= gen_lowpart_or_truncate (xmode
,
9258 force_to_mode (XEXP (x
, 1), mode
,
9259 mask
, next_select
));
9260 op1
= gen_lowpart_or_truncate (xmode
,
9261 force_to_mode (XEXP (x
, 2), mode
,
9262 mask
, next_select
));
9263 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9264 x
= simplify_gen_ternary (IF_THEN_ELSE
, xmode
,
9265 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9273 /* Ensure we return a value of the proper mode. */
9274 return gen_lowpart_or_truncate (mode
, x
);
9277 /* Return nonzero if X is an expression that has one of two values depending on
9278 whether some other value is zero or nonzero. In that case, we return the
9279 value that is being tested, *PTRUE is set to the value if the rtx being
9280 returned has a nonzero value, and *PFALSE is set to the other alternative.
9282 If we return zero, we set *PTRUE and *PFALSE to X. */
9285 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9287 machine_mode mode
= GET_MODE (x
);
9288 enum rtx_code code
= GET_CODE (x
);
9289 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9290 unsigned HOST_WIDE_INT nz
;
9291 scalar_int_mode int_mode
;
9293 /* If we are comparing a value against zero, we are done. */
9294 if ((code
== NE
|| code
== EQ
)
9295 && XEXP (x
, 1) == const0_rtx
)
9297 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9298 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9302 /* If this is a unary operation whose operand has one of two values, apply
9303 our opcode to compute those values. */
9304 else if (UNARY_P (x
)
9305 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9307 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9308 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9309 GET_MODE (XEXP (x
, 0)));
9313 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9314 make can't possibly match and would suppress other optimizations. */
9315 else if (code
== COMPARE
)
9318 /* If this is a binary operation, see if either side has only one of two
9319 values. If either one does or if both do and they are conditional on
9320 the same value, compute the new true and false values. */
9321 else if (BINARY_P (x
))
9323 rtx op0
= XEXP (x
, 0);
9324 rtx op1
= XEXP (x
, 1);
9325 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9326 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9328 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9329 && (REG_P (op0
) || REG_P (op1
)))
9331 /* Try to enable a simplification by undoing work done by
9332 if_then_else_cond if it converted a REG into something more
9337 true0
= false0
= op0
;
9342 true1
= false1
= op1
;
9346 if ((cond0
!= 0 || cond1
!= 0)
9347 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9349 /* If if_then_else_cond returned zero, then true/false are the
9350 same rtl. We must copy one of them to prevent invalid rtl
9353 true0
= copy_rtx (true0
);
9354 else if (cond1
== 0)
9355 true1
= copy_rtx (true1
);
9357 if (COMPARISON_P (x
))
9359 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9361 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9366 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9367 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9370 return cond0
? cond0
: cond1
;
9373 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9374 operands is zero when the other is nonzero, and vice-versa,
9375 and STORE_FLAG_VALUE is 1 or -1. */
9377 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9378 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9380 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9382 rtx op0
= XEXP (XEXP (x
, 0), 1);
9383 rtx op1
= XEXP (XEXP (x
, 1), 1);
9385 cond0
= XEXP (XEXP (x
, 0), 0);
9386 cond1
= XEXP (XEXP (x
, 1), 0);
9388 if (COMPARISON_P (cond0
)
9389 && COMPARISON_P (cond1
)
9390 && SCALAR_INT_MODE_P (mode
)
9391 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9392 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9393 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9394 || ((swap_condition (GET_CODE (cond0
))
9395 == reversed_comparison_code (cond1
, NULL
))
9396 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9397 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9398 && ! side_effects_p (x
))
9400 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9401 *pfalse
= simplify_gen_binary (MULT
, mode
,
9403 ? simplify_gen_unary (NEG
, mode
,
9411 /* Similarly for MULT, AND and UMIN, except that for these the result
9413 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9414 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9415 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9417 cond0
= XEXP (XEXP (x
, 0), 0);
9418 cond1
= XEXP (XEXP (x
, 1), 0);
9420 if (COMPARISON_P (cond0
)
9421 && COMPARISON_P (cond1
)
9422 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9423 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9424 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9425 || ((swap_condition (GET_CODE (cond0
))
9426 == reversed_comparison_code (cond1
, NULL
))
9427 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9428 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9429 && ! side_effects_p (x
))
9431 *ptrue
= *pfalse
= const0_rtx
;
9437 else if (code
== IF_THEN_ELSE
)
9439 /* If we have IF_THEN_ELSE already, extract the condition and
9440 canonicalize it if it is NE or EQ. */
9441 cond0
= XEXP (x
, 0);
9442 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9443 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9444 return XEXP (cond0
, 0);
9445 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9447 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9448 return XEXP (cond0
, 0);
9454 /* If X is a SUBREG, we can narrow both the true and false values
9455 if the inner expression, if there is a condition. */
9456 else if (code
== SUBREG
9457 && (cond0
= if_then_else_cond (SUBREG_REG (x
), &true0
,
9460 true0
= simplify_gen_subreg (mode
, true0
,
9461 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9462 false0
= simplify_gen_subreg (mode
, false0
,
9463 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9464 if (true0
&& false0
)
9472 /* If X is a constant, this isn't special and will cause confusions
9473 if we treat it as such. Likewise if it is equivalent to a constant. */
9474 else if (CONSTANT_P (x
)
9475 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9478 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9479 will be least confusing to the rest of the compiler. */
9480 else if (mode
== BImode
)
9482 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9486 /* If X is known to be either 0 or -1, those are the true and
9487 false values when testing X. */
9488 else if (x
== constm1_rtx
|| x
== const0_rtx
9489 || (is_a
<scalar_int_mode
> (mode
, &int_mode
)
9490 && (num_sign_bit_copies (x
, int_mode
)
9491 == GET_MODE_PRECISION (int_mode
))))
9493 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9497 /* Likewise for 0 or a single bit. */
9498 else if (HWI_COMPUTABLE_MODE_P (mode
)
9499 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9501 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9505 /* Otherwise fail; show no condition with true and false values the same. */
9506 *ptrue
= *pfalse
= x
;
9510 /* Return the value of expression X given the fact that condition COND
9511 is known to be true when applied to REG as its first operand and VAL
9512 as its second. X is known to not be shared and so can be modified in
9515 We only handle the simplest cases, and specifically those cases that
9516 arise with IF_THEN_ELSE expressions. */
9519 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9521 enum rtx_code code
= GET_CODE (x
);
9525 if (side_effects_p (x
))
9528 /* If either operand of the condition is a floating point value,
9529 then we have to avoid collapsing an EQ comparison. */
9531 && rtx_equal_p (x
, reg
)
9532 && ! FLOAT_MODE_P (GET_MODE (x
))
9533 && ! FLOAT_MODE_P (GET_MODE (val
)))
9536 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9539 /* If X is (abs REG) and we know something about REG's relationship
9540 with zero, we may be able to simplify this. */
9542 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9545 case GE
: case GT
: case EQ
:
9548 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9550 GET_MODE (XEXP (x
, 0)));
9555 /* The only other cases we handle are MIN, MAX, and comparisons if the
9556 operands are the same as REG and VAL. */
9558 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9560 if (rtx_equal_p (XEXP (x
, 0), val
))
9562 std::swap (val
, reg
);
9563 cond
= swap_condition (cond
);
9566 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9568 if (COMPARISON_P (x
))
9570 if (comparison_dominates_p (cond
, code
))
9571 return VECTOR_MODE_P (GET_MODE (x
)) ? x
: const_true_rtx
;
9573 code
= reversed_comparison_code (x
, NULL
);
9575 && comparison_dominates_p (cond
, code
))
9576 return CONST0_RTX (GET_MODE (x
));
9580 else if (code
== SMAX
|| code
== SMIN
9581 || code
== UMIN
|| code
== UMAX
)
9583 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9585 /* Do not reverse the condition when it is NE or EQ.
9586 This is because we cannot conclude anything about
9587 the value of 'SMAX (x, y)' when x is not equal to y,
9588 but we can when x equals y. */
9589 if ((code
== SMAX
|| code
== UMAX
)
9590 && ! (cond
== EQ
|| cond
== NE
))
9591 cond
= reverse_condition (cond
);
9596 return unsignedp
? x
: XEXP (x
, 1);
9598 return unsignedp
? x
: XEXP (x
, 0);
9600 return unsignedp
? XEXP (x
, 1) : x
;
9602 return unsignedp
? XEXP (x
, 0) : x
;
9609 else if (code
== SUBREG
)
9611 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9612 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9614 if (SUBREG_REG (x
) != r
)
9616 /* We must simplify subreg here, before we lose track of the
9617 original inner_mode. */
9618 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9619 inner_mode
, SUBREG_BYTE (x
));
9623 SUBST (SUBREG_REG (x
), r
);
9628 /* We don't have to handle SIGN_EXTEND here, because even in the
9629 case of replacing something with a modeless CONST_INT, a
9630 CONST_INT is already (supposed to be) a valid sign extension for
9631 its narrower mode, which implies it's already properly
9632 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9633 story is different. */
9634 else if (code
== ZERO_EXTEND
)
9636 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9637 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9639 if (XEXP (x
, 0) != r
)
9641 /* We must simplify the zero_extend here, before we lose
9642 track of the original inner_mode. */
9643 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9648 SUBST (XEXP (x
, 0), r
);
9654 fmt
= GET_RTX_FORMAT (code
);
9655 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9658 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9659 else if (fmt
[i
] == 'E')
9660 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9661 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9668 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9669 assignment as a field assignment. */
9672 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9674 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9676 if (paradoxical_subreg_p (GET_MODE (x
), GET_MODE (y
)))
9678 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9680 x
= adjust_address_nv (x
, GET_MODE (y
),
9681 byte_lowpart_offset (GET_MODE (y
),
9685 if (x
== y
|| rtx_equal_p (x
, y
))
9688 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9691 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9692 Note that all SUBREGs of MEM are paradoxical; otherwise they
9693 would have been rewritten. */
9694 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9695 && MEM_P (SUBREG_REG (y
))
9696 && rtx_equal_p (SUBREG_REG (y
),
9697 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9700 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9701 && MEM_P (SUBREG_REG (x
))
9702 && rtx_equal_p (SUBREG_REG (x
),
9703 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9706 /* We used to see if get_last_value of X and Y were the same but that's
9707 not correct. In one direction, we'll cause the assignment to have
9708 the wrong destination and in the case, we'll import a register into this
9709 insn that might have already have been dead. So fail if none of the
9710 above cases are true. */
9714 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9715 Return that assignment if so.
9717 We only handle the most common cases. */
9720 make_field_assignment (rtx x
)
9722 rtx dest
= SET_DEST (x
);
9723 rtx src
= SET_SRC (x
);
9728 unsigned HOST_WIDE_INT len
;
9731 /* All the rules in this function are specific to scalar integers. */
9732 scalar_int_mode mode
;
9733 if (!is_a
<scalar_int_mode
> (GET_MODE (dest
), &mode
))
9736 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9737 a clear of a one-bit field. We will have changed it to
9738 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9741 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9742 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9743 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9744 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9746 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9749 return gen_rtx_SET (assign
, const0_rtx
);
9753 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9754 && subreg_lowpart_p (XEXP (src
, 0))
9755 && partial_subreg_p (XEXP (src
, 0))
9756 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9757 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9758 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9759 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9761 assign
= make_extraction (VOIDmode
, dest
, 0,
9762 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9765 return gen_rtx_SET (assign
, const0_rtx
);
9769 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9771 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9772 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9773 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9775 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9778 return gen_rtx_SET (assign
, const1_rtx
);
9782 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9783 SRC is an AND with all bits of that field set, then we can discard
9785 if (GET_CODE (dest
) == ZERO_EXTRACT
9786 && CONST_INT_P (XEXP (dest
, 1))
9787 && GET_CODE (src
) == AND
9788 && CONST_INT_P (XEXP (src
, 1)))
9790 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9791 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9792 unsigned HOST_WIDE_INT ze_mask
;
9794 if (width
>= HOST_BITS_PER_WIDE_INT
)
9797 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9799 /* Complete overlap. We can remove the source AND. */
9800 if ((and_mask
& ze_mask
) == ze_mask
)
9801 return gen_rtx_SET (dest
, XEXP (src
, 0));
9803 /* Partial overlap. We can reduce the source AND. */
9804 if ((and_mask
& ze_mask
) != and_mask
)
9806 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9807 gen_int_mode (and_mask
& ze_mask
, mode
));
9808 return gen_rtx_SET (dest
, src
);
9812 /* The other case we handle is assignments into a constant-position
9813 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9814 a mask that has all one bits except for a group of zero bits and
9815 OTHER is known to have zeros where C1 has ones, this is such an
9816 assignment. Compute the position and length from C1. Shift OTHER
9817 to the appropriate position, force it to the required mode, and
9818 make the extraction. Check for the AND in both operands. */
9820 /* One or more SUBREGs might obscure the constant-position field
9821 assignment. The first one we are likely to encounter is an outer
9822 narrowing SUBREG, which we can just strip for the purposes of
9823 identifying the constant-field assignment. */
9824 scalar_int_mode src_mode
= mode
;
9825 if (GET_CODE (src
) == SUBREG
9826 && subreg_lowpart_p (src
)
9827 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (src
)), &src_mode
))
9828 src
= SUBREG_REG (src
);
9830 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9833 rhs
= expand_compound_operation (XEXP (src
, 0));
9834 lhs
= expand_compound_operation (XEXP (src
, 1));
9836 if (GET_CODE (rhs
) == AND
9837 && CONST_INT_P (XEXP (rhs
, 1))
9838 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9839 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9840 /* The second SUBREG that might get in the way is a paradoxical
9841 SUBREG around the first operand of the AND. We want to
9842 pretend the operand is as wide as the destination here. We
9843 do this by adjusting the MEM to wider mode for the sole
9844 purpose of the call to rtx_equal_for_field_assignment_p. Also
9845 note this trick only works for MEMs. */
9846 else if (GET_CODE (rhs
) == AND
9847 && paradoxical_subreg_p (XEXP (rhs
, 0))
9848 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9849 && CONST_INT_P (XEXP (rhs
, 1))
9850 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9852 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9853 else if (GET_CODE (lhs
) == AND
9854 && CONST_INT_P (XEXP (lhs
, 1))
9855 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9856 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9857 /* The second SUBREG that might get in the way is a paradoxical
9858 SUBREG around the first operand of the AND. We want to
9859 pretend the operand is as wide as the destination here. We
9860 do this by adjusting the MEM to wider mode for the sole
9861 purpose of the call to rtx_equal_for_field_assignment_p. Also
9862 note this trick only works for MEMs. */
9863 else if (GET_CODE (lhs
) == AND
9864 && paradoxical_subreg_p (XEXP (lhs
, 0))
9865 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9866 && CONST_INT_P (XEXP (lhs
, 1))
9867 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9869 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9873 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (mode
), &len
);
9875 || pos
+ len
> GET_MODE_PRECISION (mode
)
9876 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
9877 || (c1
& nonzero_bits (other
, mode
)) != 0)
9880 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9884 /* The mode to use for the source is the mode of the assignment, or of
9885 what is inside a possible STRICT_LOW_PART. */
9886 machine_mode new_mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9887 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9889 /* Shift OTHER right POS places and make it the source, restricting it
9890 to the proper length and mode. */
9892 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9893 src_mode
, other
, pos
),
9895 src
= force_to_mode (src
, new_mode
,
9896 len
>= HOST_BITS_PER_WIDE_INT
9898 : (HOST_WIDE_INT_1U
<< len
) - 1,
9901 /* If SRC is masked by an AND that does not make a difference in
9902 the value being stored, strip it. */
9903 if (GET_CODE (assign
) == ZERO_EXTRACT
9904 && CONST_INT_P (XEXP (assign
, 1))
9905 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9906 && GET_CODE (src
) == AND
9907 && CONST_INT_P (XEXP (src
, 1))
9908 && UINTVAL (XEXP (src
, 1))
9909 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9910 src
= XEXP (src
, 0);
9912 return gen_rtx_SET (assign
, src
);
9915 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9919 apply_distributive_law (rtx x
)
9921 enum rtx_code code
= GET_CODE (x
);
9922 enum rtx_code inner_code
;
9923 rtx lhs
, rhs
, other
;
9926 /* Distributivity is not true for floating point as it can change the
9927 value. So we don't do it unless -funsafe-math-optimizations. */
9928 if (FLOAT_MODE_P (GET_MODE (x
))
9929 && ! flag_unsafe_math_optimizations
)
9932 /* The outer operation can only be one of the following: */
9933 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9934 && code
!= PLUS
&& code
!= MINUS
)
9940 /* If either operand is a primitive we can't do anything, so get out
9942 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9945 lhs
= expand_compound_operation (lhs
);
9946 rhs
= expand_compound_operation (rhs
);
9947 inner_code
= GET_CODE (lhs
);
9948 if (inner_code
!= GET_CODE (rhs
))
9951 /* See if the inner and outer operations distribute. */
9958 /* These all distribute except over PLUS. */
9959 if (code
== PLUS
|| code
== MINUS
)
9964 if (code
!= PLUS
&& code
!= MINUS
)
9969 /* This is also a multiply, so it distributes over everything. */
9972 /* This used to handle SUBREG, but this turned out to be counter-
9973 productive, since (subreg (op ...)) usually is not handled by
9974 insn patterns, and this "optimization" therefore transformed
9975 recognizable patterns into unrecognizable ones. Therefore the
9976 SUBREG case was removed from here.
9978 It is possible that distributing SUBREG over arithmetic operations
9979 leads to an intermediate result than can then be optimized further,
9980 e.g. by moving the outer SUBREG to the other side of a SET as done
9981 in simplify_set. This seems to have been the original intent of
9982 handling SUBREGs here.
9984 However, with current GCC this does not appear to actually happen,
9985 at least on major platforms. If some case is found where removing
9986 the SUBREG case here prevents follow-on optimizations, distributing
9987 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9993 /* Set LHS and RHS to the inner operands (A and B in the example
9994 above) and set OTHER to the common operand (C in the example).
9995 There is only one way to do this unless the inner operation is
9997 if (COMMUTATIVE_ARITH_P (lhs
)
9998 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9999 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
10000 else if (COMMUTATIVE_ARITH_P (lhs
)
10001 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
10002 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
10003 else if (COMMUTATIVE_ARITH_P (lhs
)
10004 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
10005 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
10006 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
10007 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
10011 /* Form the new inner operation, seeing if it simplifies first. */
10012 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
10014 /* There is one exception to the general way of distributing:
10015 (a | c) ^ (b | c) -> (a ^ b) & ~c */
10016 if (code
== XOR
&& inner_code
== IOR
)
10019 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
10022 /* We may be able to continuing distributing the result, so call
10023 ourselves recursively on the inner operation before forming the
10024 outer operation, which we return. */
10025 return simplify_gen_binary (inner_code
, GET_MODE (x
),
10026 apply_distributive_law (tem
), other
);
10029 /* See if X is of the form (* (+ A B) C), and if so convert to
10030 (+ (* A C) (* B C)) and try to simplify.
10032 Most of the time, this results in no change. However, if some of
10033 the operands are the same or inverses of each other, simplifications
10036 For example, (and (ior A B) (not B)) can occur as the result of
10037 expanding a bit field assignment. When we apply the distributive
10038 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10039 which then simplifies to (and (A (not B))).
10041 Note that no checks happen on the validity of applying the inverse
10042 distributive law. This is pointless since we can do it in the
10043 few places where this routine is called.
10045 N is the index of the term that is decomposed (the arithmetic operation,
10046 i.e. (+ A B) in the first example above). !N is the index of the term that
10047 is distributed, i.e. of C in the first example above. */
10049 distribute_and_simplify_rtx (rtx x
, int n
)
10052 enum rtx_code outer_code
, inner_code
;
10053 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
10055 /* Distributivity is not true for floating point as it can change the
10056 value. So we don't do it unless -funsafe-math-optimizations. */
10057 if (FLOAT_MODE_P (GET_MODE (x
))
10058 && ! flag_unsafe_math_optimizations
)
10061 decomposed
= XEXP (x
, n
);
10062 if (!ARITHMETIC_P (decomposed
))
10065 mode
= GET_MODE (x
);
10066 outer_code
= GET_CODE (x
);
10067 distributed
= XEXP (x
, !n
);
10069 inner_code
= GET_CODE (decomposed
);
10070 inner_op0
= XEXP (decomposed
, 0);
10071 inner_op1
= XEXP (decomposed
, 1);
10073 /* Special case (and (xor B C) (not A)), which is equivalent to
10074 (xor (ior A B) (ior A C)) */
10075 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
10077 distributed
= XEXP (distributed
, 0);
10083 /* Distribute the second term. */
10084 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
10085 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
10089 /* Distribute the first term. */
10090 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
10091 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
10094 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
10095 new_op0
, new_op1
));
10096 if (GET_CODE (tmp
) != outer_code
10097 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
10098 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
10104 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10105 in MODE. Return an equivalent form, if different from (and VAROP
10106 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10109 simplify_and_const_int_1 (scalar_int_mode mode
, rtx varop
,
10110 unsigned HOST_WIDE_INT constop
)
10112 unsigned HOST_WIDE_INT nonzero
;
10113 unsigned HOST_WIDE_INT orig_constop
;
10117 orig_varop
= varop
;
10118 orig_constop
= constop
;
10119 if (GET_CODE (varop
) == CLOBBER
)
10122 /* Simplify VAROP knowing that we will be only looking at some of the
10125 Note by passing in CONSTOP, we guarantee that the bits not set in
10126 CONSTOP are not significant and will never be examined. We must
10127 ensure that is the case by explicitly masking out those bits
10128 before returning. */
10129 varop
= force_to_mode (varop
, mode
, constop
, 0);
10131 /* If VAROP is a CLOBBER, we will fail so return it. */
10132 if (GET_CODE (varop
) == CLOBBER
)
10135 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10136 to VAROP and return the new constant. */
10137 if (CONST_INT_P (varop
))
10138 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
10140 /* See what bits may be nonzero in VAROP. Unlike the general case of
10141 a call to nonzero_bits, here we don't care about bits outside
10144 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
10146 /* Turn off all bits in the constant that are known to already be zero.
10147 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10148 which is tested below. */
10150 constop
&= nonzero
;
10152 /* If we don't have any bits left, return zero. */
10156 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10157 a power of two, we can replace this with an ASHIFT. */
10158 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
10159 && (i
= exact_log2 (constop
)) >= 0)
10160 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
10162 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10163 or XOR, then try to apply the distributive law. This may eliminate
10164 operations if either branch can be simplified because of the AND.
10165 It may also make some cases more complex, but those cases probably
10166 won't match a pattern either with or without this. */
10168 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
10170 scalar_int_mode varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10174 apply_distributive_law
10175 (simplify_gen_binary (GET_CODE (varop
), varop_mode
,
10176 simplify_and_const_int (NULL_RTX
, varop_mode
,
10179 simplify_and_const_int (NULL_RTX
, varop_mode
,
10184 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10185 the AND and see if one of the operands simplifies to zero. If so, we
10186 may eliminate it. */
10188 if (GET_CODE (varop
) == PLUS
10189 && pow2p_hwi (constop
+ 1))
10193 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
10194 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
10195 if (o0
== const0_rtx
)
10197 if (o1
== const0_rtx
)
10201 /* Make a SUBREG if necessary. If we can't make it, fail. */
10202 varop
= gen_lowpart (mode
, varop
);
10203 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10206 /* If we are only masking insignificant bits, return VAROP. */
10207 if (constop
== nonzero
)
10210 if (varop
== orig_varop
&& constop
== orig_constop
)
10213 /* Otherwise, return an AND. */
10214 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
10218 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10221 Return an equivalent form, if different from X. Otherwise, return X. If
10222 X is zero, we are to always construct the equivalent form. */
10225 simplify_and_const_int (rtx x
, scalar_int_mode mode
, rtx varop
,
10226 unsigned HOST_WIDE_INT constop
)
10228 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
10233 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
10234 gen_int_mode (constop
, mode
));
10235 if (GET_MODE (x
) != mode
)
10236 x
= gen_lowpart (mode
, x
);
10240 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10241 We don't care about bits outside of those defined in MODE.
10242 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10244 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10245 a shift, AND, or zero_extract, we can do better. */
10248 reg_nonzero_bits_for_combine (const_rtx x
, scalar_int_mode xmode
,
10249 scalar_int_mode mode
,
10250 unsigned HOST_WIDE_INT
*nonzero
)
10253 reg_stat_type
*rsp
;
10255 /* If X is a register whose nonzero bits value is current, use it.
10256 Otherwise, if X is a register whose value we can find, use that
10257 value. Otherwise, use the previously-computed global nonzero bits
10258 for this register. */
10260 rsp
= ®_stat
[REGNO (x
)];
10261 if (rsp
->last_set_value
!= 0
10262 && (rsp
->last_set_mode
== mode
10263 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10264 && GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
10265 && GET_MODE_CLASS (mode
) == MODE_INT
))
10266 && ((rsp
->last_set_label
>= label_tick_ebb_start
10267 && rsp
->last_set_label
< label_tick
)
10268 || (rsp
->last_set_label
== label_tick
10269 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10270 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10271 && REGNO (x
) < reg_n_sets_max
10272 && REG_N_SETS (REGNO (x
)) == 1
10273 && !REGNO_REG_SET_P
10274 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10277 /* Note that, even if the precision of last_set_mode is lower than that
10278 of mode, record_value_for_reg invoked nonzero_bits on the register
10279 with nonzero_bits_mode (because last_set_mode is necessarily integral
10280 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10281 are all valid, hence in mode too since nonzero_bits_mode is defined
10282 to the largest HWI_COMPUTABLE_MODE_P mode. */
10283 *nonzero
&= rsp
->last_set_nonzero_bits
;
10287 tem
= get_last_value (x
);
10290 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10291 tem
= sign_extend_short_imm (tem
, xmode
, GET_MODE_PRECISION (mode
));
10296 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10298 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10300 if (GET_MODE_PRECISION (xmode
) < GET_MODE_PRECISION (mode
))
10301 /* We don't know anything about the upper bits. */
10302 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (xmode
);
10310 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10311 end of X that are known to be equal to the sign bit. X will be used
10312 in mode MODE; the returned value will always be between 1 and the
10313 number of bits in MODE. */
10316 reg_num_sign_bit_copies_for_combine (const_rtx x
, scalar_int_mode xmode
,
10317 scalar_int_mode mode
,
10318 unsigned int *result
)
10321 reg_stat_type
*rsp
;
10323 rsp
= ®_stat
[REGNO (x
)];
10324 if (rsp
->last_set_value
!= 0
10325 && rsp
->last_set_mode
== mode
10326 && ((rsp
->last_set_label
>= label_tick_ebb_start
10327 && rsp
->last_set_label
< label_tick
)
10328 || (rsp
->last_set_label
== label_tick
10329 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10330 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10331 && REGNO (x
) < reg_n_sets_max
10332 && REG_N_SETS (REGNO (x
)) == 1
10333 && !REGNO_REG_SET_P
10334 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10337 *result
= rsp
->last_set_sign_bit_copies
;
10341 tem
= get_last_value (x
);
10345 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10346 && GET_MODE_PRECISION (xmode
) == GET_MODE_PRECISION (mode
))
10347 *result
= rsp
->sign_bit_copies
;
10352 /* Return the number of "extended" bits there are in X, when interpreted
10353 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10354 unsigned quantities, this is the number of high-order zero bits.
10355 For signed quantities, this is the number of copies of the sign bit
10356 minus 1. In both case, this function returns the number of "spare"
10357 bits. For example, if two quantities for which this function returns
10358 at least 1 are added, the addition is known not to overflow.
10360 This function will always return 0 unless called during combine, which
10361 implies that it must be called from a define_split. */
10364 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10366 if (nonzero_sign_valid
== 0)
10369 scalar_int_mode int_mode
;
10371 ? (is_a
<scalar_int_mode
> (mode
, &int_mode
)
10372 && HWI_COMPUTABLE_MODE_P (int_mode
)
10373 ? (unsigned int) (GET_MODE_PRECISION (int_mode
) - 1
10374 - floor_log2 (nonzero_bits (x
, int_mode
)))
10376 : num_sign_bit_copies (x
, mode
) - 1);
10379 /* This function is called from `simplify_shift_const' to merge two
10380 outer operations. Specifically, we have already found that we need
10381 to perform operation *POP0 with constant *PCONST0 at the outermost
10382 position. We would now like to also perform OP1 with constant CONST1
10383 (with *POP0 being done last).
10385 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10386 the resulting operation. *PCOMP_P is set to 1 if we would need to
10387 complement the innermost operand, otherwise it is unchanged.
10389 MODE is the mode in which the operation will be done. No bits outside
10390 the width of this mode matter. It is assumed that the width of this mode
10391 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10393 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10394 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10395 result is simply *PCONST0.
10397 If the resulting operation cannot be expressed as one operation, we
10398 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10401 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10403 enum rtx_code op0
= *pop0
;
10404 HOST_WIDE_INT const0
= *pconst0
;
10406 const0
&= GET_MODE_MASK (mode
);
10407 const1
&= GET_MODE_MASK (mode
);
10409 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10413 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10416 if (op1
== UNKNOWN
|| op0
== SET
)
10419 else if (op0
== UNKNOWN
)
10420 op0
= op1
, const0
= const1
;
10422 else if (op0
== op1
)
10446 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10447 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10450 /* If the two constants aren't the same, we can't do anything. The
10451 remaining six cases can all be done. */
10452 else if (const0
!= const1
)
10460 /* (a & b) | b == b */
10462 else /* op1 == XOR */
10463 /* (a ^ b) | b == a | b */
10469 /* (a & b) ^ b == (~a) & b */
10470 op0
= AND
, *pcomp_p
= 1;
10471 else /* op1 == IOR */
10472 /* (a | b) ^ b == a & ~b */
10473 op0
= AND
, const0
= ~const0
;
10478 /* (a | b) & b == b */
10480 else /* op1 == XOR */
10481 /* (a ^ b) & b) == (~a) & b */
10488 /* Check for NO-OP cases. */
10489 const0
&= GET_MODE_MASK (mode
);
10491 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10493 else if (const0
== 0 && op0
== AND
)
10495 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10501 /* ??? Slightly redundant with the above mask, but not entirely.
10502 Moving this above means we'd have to sign-extend the mode mask
10503 for the final test. */
10504 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10505 *pconst0
= trunc_int_for_mode (const0
, mode
);
10510 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10511 the shift in. The original shift operation CODE is performed on OP in
10512 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10513 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10514 result of the shift is subject to operation OUTER_CODE with operand
10517 static scalar_int_mode
10518 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10519 scalar_int_mode orig_mode
, scalar_int_mode mode
,
10520 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10522 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10524 /* In general we can't perform in wider mode for right shift and rotate. */
10528 /* We can still widen if the bits brought in from the left are identical
10529 to the sign bit of ORIG_MODE. */
10530 if (num_sign_bit_copies (op
, mode
)
10531 > (unsigned) (GET_MODE_PRECISION (mode
)
10532 - GET_MODE_PRECISION (orig_mode
)))
10537 /* Similarly here but with zero bits. */
10538 if (HWI_COMPUTABLE_MODE_P (mode
)
10539 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10542 /* We can also widen if the bits brought in will be masked off. This
10543 operation is performed in ORIG_MODE. */
10544 if (outer_code
== AND
)
10546 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10549 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10558 gcc_unreachable ();
10565 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10566 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10567 if we cannot simplify it. Otherwise, return a simplified value.
10569 The shift is normally computed in the widest mode we find in VAROP, as
10570 long as it isn't a different number of words than RESULT_MODE. Exceptions
10571 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10574 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10575 rtx varop
, int orig_count
)
10577 enum rtx_code orig_code
= code
;
10578 rtx orig_varop
= varop
;
10580 machine_mode mode
= result_mode
;
10581 machine_mode shift_mode
;
10582 scalar_int_mode tmode
, inner_mode
, int_mode
, int_varop_mode
, int_result_mode
;
10583 /* We form (outer_op (code varop count) (outer_const)). */
10584 enum rtx_code outer_op
= UNKNOWN
;
10585 HOST_WIDE_INT outer_const
= 0;
10586 int complement_p
= 0;
10589 /* Make sure and truncate the "natural" shift on the way in. We don't
10590 want to do this inside the loop as it makes it more difficult to
10592 if (SHIFT_COUNT_TRUNCATED
)
10593 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10595 /* If we were given an invalid count, don't do anything except exactly
10596 what was requested. */
10598 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10601 count
= orig_count
;
10603 /* Unless one of the branches of the `if' in this loop does a `continue',
10604 we will `break' the loop after the `if'. */
10608 /* If we have an operand of (clobber (const_int 0)), fail. */
10609 if (GET_CODE (varop
) == CLOBBER
)
10612 /* Convert ROTATERT to ROTATE. */
10613 if (code
== ROTATERT
)
10615 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10617 count
= bitsize
- count
;
10620 shift_mode
= result_mode
;
10621 if (shift_mode
!= mode
)
10623 /* We only change the modes of scalar shifts. */
10624 int_mode
= as_a
<scalar_int_mode
> (mode
);
10625 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10626 shift_mode
= try_widen_shift_mode (code
, varop
, count
,
10627 int_result_mode
, int_mode
,
10628 outer_op
, outer_const
);
10631 scalar_int_mode shift_unit_mode
10632 = as_a
<scalar_int_mode
> (GET_MODE_INNER (shift_mode
));
10634 /* Handle cases where the count is greater than the size of the mode
10635 minus 1. For ASHIFT, use the size minus one as the count (this can
10636 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10637 take the count modulo the size. For other shifts, the result is
10640 Since these shifts are being produced by the compiler by combining
10641 multiple operations, each of which are defined, we know what the
10642 result is supposed to be. */
10644 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10646 if (code
== ASHIFTRT
)
10647 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10648 else if (code
== ROTATE
|| code
== ROTATERT
)
10649 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10652 /* We can't simply return zero because there may be an
10654 varop
= const0_rtx
;
10660 /* If we discovered we had to complement VAROP, leave. Making a NOT
10661 here would cause an infinite loop. */
10665 if (shift_mode
== shift_unit_mode
)
10667 /* An arithmetic right shift of a quantity known to be -1 or 0
10669 if (code
== ASHIFTRT
10670 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10671 == GET_MODE_PRECISION (shift_unit_mode
)))
10677 /* If we are doing an arithmetic right shift and discarding all but
10678 the sign bit copies, this is equivalent to doing a shift by the
10679 bitsize minus one. Convert it into that shift because it will
10680 often allow other simplifications. */
10682 if (code
== ASHIFTRT
10683 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10684 >= GET_MODE_PRECISION (shift_unit_mode
)))
10685 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10687 /* We simplify the tests below and elsewhere by converting
10688 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10689 `make_compound_operation' will convert it to an ASHIFTRT for
10690 those machines (such as VAX) that don't have an LSHIFTRT. */
10691 if (code
== ASHIFTRT
10692 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10693 && val_signbit_known_clear_p (shift_unit_mode
,
10694 nonzero_bits (varop
,
10698 if (((code
== LSHIFTRT
10699 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10700 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10702 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10703 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10704 & GET_MODE_MASK (shift_unit_mode
))))
10705 && !side_effects_p (varop
))
10706 varop
= const0_rtx
;
10709 switch (GET_CODE (varop
))
10715 new_rtx
= expand_compound_operation (varop
);
10716 if (new_rtx
!= varop
)
10724 /* The following rules apply only to scalars. */
10725 if (shift_mode
!= shift_unit_mode
)
10727 int_mode
= as_a
<scalar_int_mode
> (mode
);
10729 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10730 minus the width of a smaller mode, we can do this with a
10731 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10732 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10733 && ! mode_dependent_address_p (XEXP (varop
, 0),
10734 MEM_ADDR_SPACE (varop
))
10735 && ! MEM_VOLATILE_P (varop
)
10736 && (int_mode_for_size (GET_MODE_BITSIZE (int_mode
) - count
, 1)
10739 new_rtx
= adjust_address_nv (varop
, tmode
,
10740 BYTES_BIG_ENDIAN
? 0
10741 : count
/ BITS_PER_UNIT
);
10743 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10744 : ZERO_EXTEND
, int_mode
, new_rtx
);
10751 /* The following rules apply only to scalars. */
10752 if (shift_mode
!= shift_unit_mode
)
10754 int_mode
= as_a
<scalar_int_mode
> (mode
);
10755 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10757 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10758 the same number of words as what we've seen so far. Then store
10759 the widest mode in MODE. */
10760 if (subreg_lowpart_p (varop
)
10761 && is_int_mode (GET_MODE (SUBREG_REG (varop
)), &inner_mode
)
10762 && GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_varop_mode
)
10763 && (CEIL (GET_MODE_SIZE (inner_mode
), UNITS_PER_WORD
)
10764 == CEIL (GET_MODE_SIZE (int_mode
), UNITS_PER_WORD
))
10765 && GET_MODE_CLASS (int_varop_mode
) == MODE_INT
)
10767 varop
= SUBREG_REG (varop
);
10768 if (GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_mode
))
10775 /* Some machines use MULT instead of ASHIFT because MULT
10776 is cheaper. But it is still better on those machines to
10777 merge two shifts into one. */
10778 if (CONST_INT_P (XEXP (varop
, 1))
10779 && (log2
= exact_log2 (UINTVAL (XEXP (varop
, 1)))) >= 0)
10781 rtx log2_rtx
= gen_int_shift_amount (GET_MODE (varop
), log2
);
10782 varop
= simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10783 XEXP (varop
, 0), log2_rtx
);
10789 /* Similar, for when divides are cheaper. */
10790 if (CONST_INT_P (XEXP (varop
, 1))
10791 && (log2
= exact_log2 (UINTVAL (XEXP (varop
, 1)))) >= 0)
10793 rtx log2_rtx
= gen_int_shift_amount (GET_MODE (varop
), log2
);
10794 varop
= simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10795 XEXP (varop
, 0), log2_rtx
);
10801 /* If we are extracting just the sign bit of an arithmetic
10802 right shift, that shift is not needed. However, the sign
10803 bit of a wider mode may be different from what would be
10804 interpreted as the sign bit in a narrower mode, so, if
10805 the result is narrower, don't discard the shift. */
10806 if (code
== LSHIFTRT
10807 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10808 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10809 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10811 varop
= XEXP (varop
, 0);
10820 /* The following rules apply only to scalars. */
10821 if (shift_mode
!= shift_unit_mode
)
10823 int_mode
= as_a
<scalar_int_mode
> (mode
);
10824 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10825 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10827 /* Here we have two nested shifts. The result is usually the
10828 AND of a new shift with a mask. We compute the result below. */
10829 if (CONST_INT_P (XEXP (varop
, 1))
10830 && INTVAL (XEXP (varop
, 1)) >= 0
10831 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (int_varop_mode
)
10832 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
10833 && HWI_COMPUTABLE_MODE_P (int_mode
))
10835 enum rtx_code first_code
= GET_CODE (varop
);
10836 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10837 unsigned HOST_WIDE_INT mask
;
10840 /* We have one common special case. We can't do any merging if
10841 the inner code is an ASHIFTRT of a smaller mode. However, if
10842 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10843 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10844 we can convert it to
10845 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10846 This simplifies certain SIGN_EXTEND operations. */
10847 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10848 && count
== (GET_MODE_PRECISION (int_result_mode
)
10849 - GET_MODE_PRECISION (int_varop_mode
)))
10851 /* C3 has the low-order C1 bits zero. */
10853 mask
= GET_MODE_MASK (int_mode
)
10854 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10856 varop
= simplify_and_const_int (NULL_RTX
, int_result_mode
,
10857 XEXP (varop
, 0), mask
);
10858 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
,
10859 int_result_mode
, varop
, count
);
10860 count
= first_count
;
10865 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10866 than C1 high-order bits equal to the sign bit, we can convert
10867 this to either an ASHIFT or an ASHIFTRT depending on the
10870 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10872 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10873 && int_varop_mode
== shift_unit_mode
10874 && (num_sign_bit_copies (XEXP (varop
, 0), shift_unit_mode
)
10877 varop
= XEXP (varop
, 0);
10878 count
-= first_count
;
10888 /* There are some cases we can't do. If CODE is ASHIFTRT,
10889 we can only do this if FIRST_CODE is also ASHIFTRT.
10891 We can't do the case when CODE is ROTATE and FIRST_CODE is
10894 If the mode of this shift is not the mode of the outer shift,
10895 we can't do this if either shift is a right shift or ROTATE.
10897 Finally, we can't do any of these if the mode is too wide
10898 unless the codes are the same.
10900 Handle the case where the shift codes are the same
10903 if (code
== first_code
)
10905 if (int_varop_mode
!= int_result_mode
10906 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10907 || code
== ROTATE
))
10910 count
+= first_count
;
10911 varop
= XEXP (varop
, 0);
10915 if (code
== ASHIFTRT
10916 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10917 || GET_MODE_PRECISION (int_mode
) > HOST_BITS_PER_WIDE_INT
10918 || (int_varop_mode
!= int_result_mode
10919 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10920 || first_code
== ROTATE
10921 || code
== ROTATE
)))
10924 /* To compute the mask to apply after the shift, shift the
10925 nonzero bits of the inner shift the same way the
10926 outer shift will. */
10928 mask_rtx
= gen_int_mode (nonzero_bits (varop
, int_varop_mode
),
10930 rtx count_rtx
= gen_int_shift_amount (int_result_mode
, count
);
10932 = simplify_const_binary_operation (code
, int_result_mode
,
10933 mask_rtx
, count_rtx
);
10935 /* Give up if we can't compute an outer operation to use. */
10937 || !CONST_INT_P (mask_rtx
)
10938 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10940 int_result_mode
, &complement_p
))
10943 /* If the shifts are in the same direction, we add the
10944 counts. Otherwise, we subtract them. */
10945 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10946 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10947 count
+= first_count
;
10949 count
-= first_count
;
10951 /* If COUNT is positive, the new shift is usually CODE,
10952 except for the two exceptions below, in which case it is
10953 FIRST_CODE. If the count is negative, FIRST_CODE should
10956 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10957 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10959 else if (count
< 0)
10960 code
= first_code
, count
= -count
;
10962 varop
= XEXP (varop
, 0);
10966 /* If we have (A << B << C) for any shift, we can convert this to
10967 (A << C << B). This wins if A is a constant. Only try this if
10968 B is not a constant. */
10970 else if (GET_CODE (varop
) == code
10971 && CONST_INT_P (XEXP (varop
, 0))
10972 && !CONST_INT_P (XEXP (varop
, 1)))
10974 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10975 sure the result will be masked. See PR70222. */
10976 if (code
== LSHIFTRT
10977 && int_mode
!= int_result_mode
10978 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10979 GET_MODE_MASK (int_result_mode
)
10980 >> orig_count
, int_result_mode
,
10983 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10984 up outer sign extension (often left and right shift) is
10985 hardly more efficient than the original. See PR70429. */
10986 if (code
== ASHIFTRT
&& int_mode
!= int_result_mode
)
10989 rtx count_rtx
= gen_int_shift_amount (int_result_mode
, count
);
10990 rtx new_rtx
= simplify_const_binary_operation (code
, int_mode
,
10993 varop
= gen_rtx_fmt_ee (code
, int_mode
, new_rtx
, XEXP (varop
, 1));
11000 /* The following rules apply only to scalars. */
11001 if (shift_mode
!= shift_unit_mode
)
11004 /* Make this fit the case below. */
11005 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
11011 /* The following rules apply only to scalars. */
11012 if (shift_mode
!= shift_unit_mode
)
11014 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
11015 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11017 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11018 with C the size of VAROP - 1 and the shift is logical if
11019 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11020 we have an (le X 0) operation. If we have an arithmetic shift
11021 and STORE_FLAG_VALUE is 1 or we have a logical shift with
11022 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11024 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
11025 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
11026 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11027 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11028 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
11029 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11032 varop
= gen_rtx_LE (int_varop_mode
, XEXP (varop
, 1),
11035 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11036 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
11041 /* If we have (shift (logical)), move the logical to the outside
11042 to allow it to possibly combine with another logical and the
11043 shift to combine with another shift. This also canonicalizes to
11044 what a ZERO_EXTRACT looks like. Also, some machines have
11045 (and (shift)) insns. */
11047 if (CONST_INT_P (XEXP (varop
, 1))
11048 /* We can't do this if we have (ashiftrt (xor)) and the
11049 constant has its sign bit set in shift_unit_mode with
11050 shift_unit_mode wider than result_mode. */
11051 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
11052 && int_result_mode
!= shift_unit_mode
11053 && trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
11054 shift_unit_mode
) < 0)
11055 && (new_rtx
= simplify_const_binary_operation
11056 (code
, int_result_mode
,
11057 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11058 gen_int_shift_amount (int_result_mode
, count
))) != 0
11059 && CONST_INT_P (new_rtx
)
11060 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
11061 INTVAL (new_rtx
), int_result_mode
,
11064 varop
= XEXP (varop
, 0);
11068 /* If we can't do that, try to simplify the shift in each arm of the
11069 logical expression, make a new logical expression, and apply
11070 the inverse distributive law. This also can't be done for
11071 (ashiftrt (xor)) where we've widened the shift and the constant
11072 changes the sign bit. */
11073 if (CONST_INT_P (XEXP (varop
, 1))
11074 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
11075 && int_result_mode
!= shift_unit_mode
11076 && trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
11077 shift_unit_mode
) < 0))
11079 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
11080 XEXP (varop
, 0), count
);
11081 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
11082 XEXP (varop
, 1), count
);
11084 varop
= simplify_gen_binary (GET_CODE (varop
), shift_unit_mode
,
11086 varop
= apply_distributive_law (varop
);
11094 /* The following rules apply only to scalars. */
11095 if (shift_mode
!= shift_unit_mode
)
11097 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11099 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11100 says that the sign bit can be tested, FOO has mode MODE, C is
11101 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11102 that may be nonzero. */
11103 if (code
== LSHIFTRT
11104 && XEXP (varop
, 1) == const0_rtx
11105 && GET_MODE (XEXP (varop
, 0)) == int_result_mode
11106 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11107 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11108 && STORE_FLAG_VALUE
== -1
11109 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11110 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11111 int_result_mode
, &complement_p
))
11113 varop
= XEXP (varop
, 0);
11120 /* The following rules apply only to scalars. */
11121 if (shift_mode
!= shift_unit_mode
)
11123 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11125 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11126 than the number of bits in the mode is equivalent to A. */
11127 if (code
== LSHIFTRT
11128 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11129 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1)
11131 varop
= XEXP (varop
, 0);
11136 /* NEG commutes with ASHIFT since it is multiplication. Move the
11137 NEG outside to allow shifts to combine. */
11139 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0,
11140 int_result_mode
, &complement_p
))
11142 varop
= XEXP (varop
, 0);
11148 /* The following rules apply only to scalars. */
11149 if (shift_mode
!= shift_unit_mode
)
11151 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11153 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11154 is one less than the number of bits in the mode is
11155 equivalent to (xor A 1). */
11156 if (code
== LSHIFTRT
11157 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11158 && XEXP (varop
, 1) == constm1_rtx
11159 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11160 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11161 int_result_mode
, &complement_p
))
11164 varop
= XEXP (varop
, 0);
11168 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11169 that might be nonzero in BAR are those being shifted out and those
11170 bits are known zero in FOO, we can replace the PLUS with FOO.
11171 Similarly in the other operand order. This code occurs when
11172 we are computing the size of a variable-size array. */
11174 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11175 && count
< HOST_BITS_PER_WIDE_INT
11176 && nonzero_bits (XEXP (varop
, 1), int_result_mode
) >> count
== 0
11177 && (nonzero_bits (XEXP (varop
, 1), int_result_mode
)
11178 & nonzero_bits (XEXP (varop
, 0), int_result_mode
)) == 0)
11180 varop
= XEXP (varop
, 0);
11183 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11184 && count
< HOST_BITS_PER_WIDE_INT
11185 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11186 && (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11188 && (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11189 & nonzero_bits (XEXP (varop
, 1), int_result_mode
)) == 0)
11191 varop
= XEXP (varop
, 1);
11195 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11197 && CONST_INT_P (XEXP (varop
, 1))
11198 && (new_rtx
= simplify_const_binary_operation
11199 (ASHIFT
, int_result_mode
,
11200 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11201 gen_int_shift_amount (int_result_mode
, count
))) != 0
11202 && CONST_INT_P (new_rtx
)
11203 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
11204 INTVAL (new_rtx
), int_result_mode
,
11207 varop
= XEXP (varop
, 0);
11211 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11212 signbit', and attempt to change the PLUS to an XOR and move it to
11213 the outer operation as is done above in the AND/IOR/XOR case
11214 leg for shift(logical). See details in logical handling above
11215 for reasoning in doing so. */
11216 if (code
== LSHIFTRT
11217 && CONST_INT_P (XEXP (varop
, 1))
11218 && mode_signbit_p (int_result_mode
, XEXP (varop
, 1))
11219 && (new_rtx
= simplify_const_binary_operation
11220 (code
, int_result_mode
,
11221 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11222 gen_int_shift_amount (int_result_mode
, count
))) != 0
11223 && CONST_INT_P (new_rtx
)
11224 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
11225 INTVAL (new_rtx
), int_result_mode
,
11228 varop
= XEXP (varop
, 0);
11235 /* The following rules apply only to scalars. */
11236 if (shift_mode
!= shift_unit_mode
)
11238 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
11240 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11241 with C the size of VAROP - 1 and the shift is logical if
11242 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11243 we have a (gt X 0) operation. If the shift is arithmetic with
11244 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11245 we have a (neg (gt X 0)) operation. */
11247 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11248 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
11249 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
11250 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11251 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11252 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
11253 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11256 varop
= gen_rtx_GT (int_varop_mode
, XEXP (varop
, 1),
11259 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11260 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
11267 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11268 if the truncate does not affect the value. */
11269 if (code
== LSHIFTRT
11270 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
11271 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11272 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
11273 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
11274 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
11276 rtx varop_inner
= XEXP (varop
, 0);
11277 int new_count
= count
+ INTVAL (XEXP (varop_inner
, 1));
11278 rtx new_count_rtx
= gen_int_shift_amount (GET_MODE (varop_inner
),
11280 varop_inner
= gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
11281 XEXP (varop_inner
, 0),
11283 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11296 shift_mode
= result_mode
;
11297 if (shift_mode
!= mode
)
11299 /* We only change the modes of scalar shifts. */
11300 int_mode
= as_a
<scalar_int_mode
> (mode
);
11301 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11302 shift_mode
= try_widen_shift_mode (code
, varop
, count
, int_result_mode
,
11303 int_mode
, outer_op
, outer_const
);
11306 /* We have now finished analyzing the shift. The result should be
11307 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11308 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11309 to the result of the shift. OUTER_CONST is the relevant constant,
11310 but we must turn off all bits turned off in the shift. */
11312 if (outer_op
== UNKNOWN
11313 && orig_code
== code
&& orig_count
== count
11314 && varop
== orig_varop
11315 && shift_mode
== GET_MODE (varop
))
11318 /* Make a SUBREG if necessary. If we can't make it, fail. */
11319 varop
= gen_lowpart (shift_mode
, varop
);
11320 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11323 /* If we have an outer operation and we just made a shift, it is
11324 possible that we could have simplified the shift were it not
11325 for the outer operation. So try to do the simplification
11328 if (outer_op
!= UNKNOWN
)
11329 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11334 x
= simplify_gen_binary (code
, shift_mode
, varop
,
11335 gen_int_shift_amount (shift_mode
, count
));
11337 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11338 turn off all the bits that the shift would have turned off. */
11339 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11340 /* We only change the modes of scalar shifts. */
11341 x
= simplify_and_const_int (NULL_RTX
, as_a
<scalar_int_mode
> (shift_mode
),
11342 x
, GET_MODE_MASK (result_mode
) >> orig_count
);
11344 /* Do the remainder of the processing in RESULT_MODE. */
11345 x
= gen_lowpart_or_truncate (result_mode
, x
);
11347 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11350 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11352 if (outer_op
!= UNKNOWN
)
11354 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11356 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11357 && GET_MODE_PRECISION (int_result_mode
) < HOST_BITS_PER_WIDE_INT
)
11358 outer_const
= trunc_int_for_mode (outer_const
, int_result_mode
);
11360 if (outer_op
== AND
)
11361 x
= simplify_and_const_int (NULL_RTX
, int_result_mode
, x
, outer_const
);
11362 else if (outer_op
== SET
)
11364 /* This means that we have determined that the result is
11365 equivalent to a constant. This should be rare. */
11366 if (!side_effects_p (x
))
11367 x
= GEN_INT (outer_const
);
11369 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11370 x
= simplify_gen_unary (outer_op
, int_result_mode
, x
, int_result_mode
);
11372 x
= simplify_gen_binary (outer_op
, int_result_mode
, x
,
11373 GEN_INT (outer_const
));
11379 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11380 The result of the shift is RESULT_MODE. If we cannot simplify it,
11381 return X or, if it is NULL, synthesize the expression with
11382 simplify_gen_binary. Otherwise, return a simplified value.
11384 The shift is normally computed in the widest mode we find in VAROP, as
11385 long as it isn't a different number of words than RESULT_MODE. Exceptions
11386 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11389 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11390 rtx varop
, int count
)
11392 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11397 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
,
11398 gen_int_shift_amount (GET_MODE (varop
), count
));
11399 if (GET_MODE (x
) != result_mode
)
11400 x
= gen_lowpart (result_mode
, x
);
11405 /* A subroutine of recog_for_combine. See there for arguments and
11409 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11411 rtx pat
= *pnewpat
;
11412 rtx pat_without_clobbers
;
11413 int insn_code_number
;
11414 int num_clobbers_to_add
= 0;
11416 rtx notes
= NULL_RTX
;
11417 rtx old_notes
, old_pat
;
11420 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11421 we use to indicate that something didn't match. If we find such a
11422 thing, force rejection. */
11423 if (GET_CODE (pat
) == PARALLEL
)
11424 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11425 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11426 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11429 old_pat
= PATTERN (insn
);
11430 old_notes
= REG_NOTES (insn
);
11431 PATTERN (insn
) = pat
;
11432 REG_NOTES (insn
) = NULL_RTX
;
11434 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11435 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11437 if (insn_code_number
< 0)
11438 fputs ("Failed to match this instruction:\n", dump_file
);
11440 fputs ("Successfully matched this instruction:\n", dump_file
);
11441 print_rtl_single (dump_file
, pat
);
11444 /* If it isn't, there is the possibility that we previously had an insn
11445 that clobbered some register as a side effect, but the combined
11446 insn doesn't need to do that. So try once more without the clobbers
11447 unless this represents an ASM insn. */
11449 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11450 && GET_CODE (pat
) == PARALLEL
)
11454 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11455 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11458 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11462 SUBST_INT (XVECLEN (pat
, 0), pos
);
11465 pat
= XVECEXP (pat
, 0, 0);
11467 PATTERN (insn
) = pat
;
11468 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11469 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11471 if (insn_code_number
< 0)
11472 fputs ("Failed to match this instruction:\n", dump_file
);
11474 fputs ("Successfully matched this instruction:\n", dump_file
);
11475 print_rtl_single (dump_file
, pat
);
11479 pat_without_clobbers
= pat
;
11481 PATTERN (insn
) = old_pat
;
11482 REG_NOTES (insn
) = old_notes
;
11484 /* Recognize all noop sets, these will be killed by followup pass. */
11485 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11486 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11488 /* If we had any clobbers to add, make a new pattern than contains
11489 them. Then check to make sure that all of them are dead. */
11490 if (num_clobbers_to_add
)
11492 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11493 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11494 ? (XVECLEN (pat
, 0)
11495 + num_clobbers_to_add
)
11496 : num_clobbers_to_add
+ 1));
11498 if (GET_CODE (pat
) == PARALLEL
)
11499 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11500 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11502 XVECEXP (newpat
, 0, 0) = pat
;
11504 add_clobbers (newpat
, insn_code_number
);
11506 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11507 i
< XVECLEN (newpat
, 0); i
++)
11509 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11510 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11512 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11514 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11515 notes
= alloc_reg_note (REG_UNUSED
,
11516 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11522 if (insn_code_number
>= 0
11523 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11525 old_pat
= PATTERN (insn
);
11526 old_notes
= REG_NOTES (insn
);
11527 old_icode
= INSN_CODE (insn
);
11528 PATTERN (insn
) = pat
;
11529 REG_NOTES (insn
) = notes
;
11530 INSN_CODE (insn
) = insn_code_number
;
11532 /* Allow targets to reject combined insn. */
11533 if (!targetm
.legitimate_combined_insn (insn
))
11535 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11536 fputs ("Instruction not appropriate for target.",
11539 /* Callers expect recog_for_combine to strip
11540 clobbers from the pattern on failure. */
11541 pat
= pat_without_clobbers
;
11544 insn_code_number
= -1;
11547 PATTERN (insn
) = old_pat
;
11548 REG_NOTES (insn
) = old_notes
;
11549 INSN_CODE (insn
) = old_icode
;
11555 return insn_code_number
;
11558 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11559 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11560 Return whether anything was so changed. */
11563 change_zero_ext (rtx pat
)
11565 bool changed
= false;
11566 rtx
*src
= &SET_SRC (pat
);
11568 subrtx_ptr_iterator::array_type array
;
11569 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11572 scalar_int_mode mode
, inner_mode
;
11573 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
11577 if (GET_CODE (x
) == ZERO_EXTRACT
11578 && CONST_INT_P (XEXP (x
, 1))
11579 && CONST_INT_P (XEXP (x
, 2))
11580 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
)
11581 && GET_MODE_PRECISION (inner_mode
) <= GET_MODE_PRECISION (mode
))
11583 size
= INTVAL (XEXP (x
, 1));
11585 int start
= INTVAL (XEXP (x
, 2));
11586 if (BITS_BIG_ENDIAN
)
11587 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11590 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0),
11591 gen_int_shift_amount (inner_mode
, start
));
11595 if (mode
!= inner_mode
)
11597 if (REG_P (x
) && HARD_REGISTER_P (x
)
11598 && !can_change_dest_mode (x
, 0, mode
))
11601 x
= gen_lowpart_SUBREG (mode
, x
);
11604 else if (GET_CODE (x
) == ZERO_EXTEND
11605 && GET_CODE (XEXP (x
, 0)) == SUBREG
11606 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11607 && !paradoxical_subreg_p (XEXP (x
, 0))
11608 && subreg_lowpart_p (XEXP (x
, 0)))
11610 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11611 size
= GET_MODE_PRECISION (inner_mode
);
11612 x
= SUBREG_REG (XEXP (x
, 0));
11613 if (GET_MODE (x
) != mode
)
11615 if (REG_P (x
) && HARD_REGISTER_P (x
)
11616 && !can_change_dest_mode (x
, 0, mode
))
11619 x
= gen_lowpart_SUBREG (mode
, x
);
11622 else if (GET_CODE (x
) == ZERO_EXTEND
11623 && REG_P (XEXP (x
, 0))
11624 && HARD_REGISTER_P (XEXP (x
, 0))
11625 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11627 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11628 size
= GET_MODE_PRECISION (inner_mode
);
11629 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11634 if (!(GET_CODE (x
) == LSHIFTRT
11635 && CONST_INT_P (XEXP (x
, 1))
11636 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11638 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11639 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11647 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11648 maybe_swap_commutative_operands (**iter
);
11650 rtx
*dst
= &SET_DEST (pat
);
11651 scalar_int_mode mode
;
11652 if (GET_CODE (*dst
) == ZERO_EXTRACT
11653 && REG_P (XEXP (*dst
, 0))
11654 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (*dst
, 0)), &mode
)
11655 && CONST_INT_P (XEXP (*dst
, 1))
11656 && CONST_INT_P (XEXP (*dst
, 2)))
11658 rtx reg
= XEXP (*dst
, 0);
11659 int width
= INTVAL (XEXP (*dst
, 1));
11660 int offset
= INTVAL (XEXP (*dst
, 2));
11661 int reg_width
= GET_MODE_PRECISION (mode
);
11662 if (BITS_BIG_ENDIAN
)
11663 offset
= reg_width
- width
- offset
;
11666 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11667 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11668 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11670 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11673 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11674 w
= gen_rtx_IOR (mode
, x
, z
);
11675 SUBST (SET_DEST (pat
), reg
);
11676 SUBST (SET_SRC (pat
), w
);
11684 /* Like recog, but we receive the address of a pointer to a new pattern.
11685 We try to match the rtx that the pointer points to.
11686 If that fails, we may try to modify or replace the pattern,
11687 storing the replacement into the same pointer object.
11689 Modifications include deletion or addition of CLOBBERs. If the
11690 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11691 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11692 (and undo if that fails).
11694 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11695 the CLOBBERs are placed.
11697 The value is the final insn code from the pattern ultimately matched,
11701 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11703 rtx pat
= *pnewpat
;
11704 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11705 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11706 return insn_code_number
;
11708 void *marker
= get_undo_marker ();
11709 bool changed
= false;
11711 if (GET_CODE (pat
) == SET
)
11712 changed
= change_zero_ext (pat
);
11713 else if (GET_CODE (pat
) == PARALLEL
)
11716 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11718 rtx set
= XVECEXP (pat
, 0, i
);
11719 if (GET_CODE (set
) == SET
)
11720 changed
|= change_zero_ext (set
);
11726 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11728 if (insn_code_number
< 0)
11729 undo_to_marker (marker
);
11732 return insn_code_number
;
11735 /* Like gen_lowpart_general but for use by combine. In combine it
11736 is not possible to create any new pseudoregs. However, it is
11737 safe to create invalid memory addresses, because combine will
11738 try to recognize them and all they will do is make the combine
11741 If for some reason this cannot do its job, an rtx
11742 (clobber (const_int 0)) is returned.
11743 An insn containing that will not be recognized. */
11746 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11748 machine_mode imode
= GET_MODE (x
);
11751 if (omode
== imode
)
11754 /* We can only support MODE being wider than a word if X is a
11755 constant integer or has a mode the same size. */
11756 if (maybe_gt (GET_MODE_SIZE (omode
), UNITS_PER_WORD
)
11757 && ! (CONST_SCALAR_INT_P (x
)
11758 || known_eq (GET_MODE_SIZE (imode
), GET_MODE_SIZE (omode
))))
11761 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11762 won't know what to do. So we will strip off the SUBREG here and
11763 process normally. */
11764 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11766 x
= SUBREG_REG (x
);
11768 /* For use in case we fall down into the address adjustments
11769 further below, we need to adjust the known mode and size of
11770 x; imode and isize, since we just adjusted x. */
11771 imode
= GET_MODE (x
);
11773 if (imode
== omode
)
11777 result
= gen_lowpart_common (omode
, x
);
11784 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11786 if (MEM_VOLATILE_P (x
)
11787 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11790 /* If we want to refer to something bigger than the original memref,
11791 generate a paradoxical subreg instead. That will force a reload
11792 of the original memref X. */
11793 if (paradoxical_subreg_p (omode
, imode
))
11794 return gen_rtx_SUBREG (omode
, x
, 0);
11796 poly_int64 offset
= byte_lowpart_offset (omode
, imode
);
11797 return adjust_address_nv (x
, omode
, offset
);
11800 /* If X is a comparison operator, rewrite it in a new mode. This
11801 probably won't match, but may allow further simplifications. */
11802 else if (COMPARISON_P (x
))
11803 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11805 /* If we couldn't simplify X any other way, just enclose it in a
11806 SUBREG. Normally, this SUBREG won't match, but some patterns may
11807 include an explicit SUBREG or we may simplify it further in combine. */
11812 if (imode
== VOIDmode
)
11814 imode
= int_mode_for_mode (omode
).require ();
11815 x
= gen_lowpart_common (imode
, x
);
11819 res
= lowpart_subreg (omode
, x
, imode
);
11825 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11828 /* Try to simplify a comparison between OP0 and a constant OP1,
11829 where CODE is the comparison code that will be tested, into a
11830 (CODE OP0 const0_rtx) form.
11832 The result is a possibly different comparison code to use.
11833 *POP1 may be updated. */
11835 static enum rtx_code
11836 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11837 rtx op0
, rtx
*pop1
)
11839 scalar_int_mode int_mode
;
11840 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11842 /* Get the constant we are comparing against and turn off all bits
11843 not on in our mode. */
11844 if (mode
!= VOIDmode
)
11845 const_op
= trunc_int_for_mode (const_op
, mode
);
11847 /* If we are comparing against a constant power of two and the value
11848 being compared can only have that single bit nonzero (e.g., it was
11849 `and'ed with that bit), we can replace this with a comparison
11852 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11853 || code
== LT
|| code
== LTU
)
11854 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11855 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11856 && pow2p_hwi (const_op
& GET_MODE_MASK (int_mode
))
11857 && (nonzero_bits (op0
, int_mode
)
11858 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (int_mode
))))
11860 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11864 /* Similarly, if we are comparing a value known to be either -1 or
11865 0 with -1, change it to the opposite comparison against zero. */
11867 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11868 || code
== GEU
|| code
== LTU
)
11869 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11870 && num_sign_bit_copies (op0
, int_mode
) == GET_MODE_PRECISION (int_mode
))
11872 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11876 /* Do some canonicalizations based on the comparison code. We prefer
11877 comparisons against zero and then prefer equality comparisons.
11878 If we can reduce the size of a constant, we will do that too. */
11882 /* < C is equivalent to <= (C - 1) */
11887 /* ... fall through to LE case below. */
11888 gcc_fallthrough ();
11894 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11901 /* If we are doing a <= 0 comparison on a value known to have
11902 a zero sign bit, we can replace this with == 0. */
11903 else if (const_op
== 0
11904 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11905 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11906 && (nonzero_bits (op0
, int_mode
)
11907 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11913 /* >= C is equivalent to > (C - 1). */
11918 /* ... fall through to GT below. */
11919 gcc_fallthrough ();
11925 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11932 /* If we are doing a > 0 comparison on a value known to have
11933 a zero sign bit, we can replace this with != 0. */
11934 else if (const_op
== 0
11935 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11936 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11937 && (nonzero_bits (op0
, int_mode
)
11938 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11944 /* < C is equivalent to <= (C - 1). */
11949 /* ... fall through ... */
11950 gcc_fallthrough ();
11952 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11953 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11954 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11955 && ((unsigned HOST_WIDE_INT
) const_op
11956 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11966 /* unsigned <= 0 is equivalent to == 0 */
11969 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11970 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11971 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11972 && ((unsigned HOST_WIDE_INT
) const_op
11973 == ((HOST_WIDE_INT_1U
11974 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1)))
11982 /* >= C is equivalent to > (C - 1). */
11987 /* ... fall through ... */
11988 gcc_fallthrough ();
11991 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11992 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11993 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11994 && ((unsigned HOST_WIDE_INT
) const_op
11995 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
12005 /* unsigned > 0 is equivalent to != 0 */
12008 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
12009 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
12010 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
12011 && ((unsigned HOST_WIDE_INT
) const_op
12012 == (HOST_WIDE_INT_1U
12013 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1))
12024 *pop1
= GEN_INT (const_op
);
12028 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12029 comparison code that will be tested.
12031 The result is a possibly different comparison code to use. *POP0 and
12032 *POP1 may be updated.
12034 It is possible that we might detect that a comparison is either always
12035 true or always false. However, we do not perform general constant
12036 folding in combine, so this knowledge isn't useful. Such tautologies
12037 should have been detected earlier. Hence we ignore all such cases. */
12039 static enum rtx_code
12040 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
12046 scalar_int_mode mode
, inner_mode
, tmode
;
12047 opt_scalar_int_mode tmode_iter
;
12049 /* Try a few ways of applying the same transformation to both operands. */
12052 /* The test below this one won't handle SIGN_EXTENDs on these machines,
12053 so check specially. */
12054 if (!WORD_REGISTER_OPERATIONS
12055 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
12056 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
12057 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12058 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
12059 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
12060 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
12061 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &mode
)
12062 && (is_a
<scalar_int_mode
>
12063 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))), &inner_mode
))
12064 && inner_mode
== GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0)))
12065 && CONST_INT_P (XEXP (op0
, 1))
12066 && XEXP (op0
, 1) == XEXP (op1
, 1)
12067 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12068 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
12069 && (INTVAL (XEXP (op0
, 1))
12070 == (GET_MODE_PRECISION (mode
)
12071 - GET_MODE_PRECISION (inner_mode
))))
12073 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
12074 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
12077 /* If both operands are the same constant shift, see if we can ignore the
12078 shift. We can if the shift is a rotate or if the bits shifted out of
12079 this shift are known to be zero for both inputs and if the type of
12080 comparison is compatible with the shift. */
12081 if (GET_CODE (op0
) == GET_CODE (op1
)
12082 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
12083 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
12084 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
12085 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
12086 || (GET_CODE (op0
) == ASHIFTRT
12087 && (code
!= GTU
&& code
!= LTU
12088 && code
!= GEU
&& code
!= LEU
)))
12089 && CONST_INT_P (XEXP (op0
, 1))
12090 && INTVAL (XEXP (op0
, 1)) >= 0
12091 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12092 && XEXP (op0
, 1) == XEXP (op1
, 1))
12094 machine_mode mode
= GET_MODE (op0
);
12095 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12096 int shift_count
= INTVAL (XEXP (op0
, 1));
12098 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
12099 mask
&= (mask
>> shift_count
) << shift_count
;
12100 else if (GET_CODE (op0
) == ASHIFT
)
12101 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
12103 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
12104 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
12105 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
12110 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12111 SUBREGs are of the same mode, and, in both cases, the AND would
12112 be redundant if the comparison was done in the narrower mode,
12113 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12114 and the operand's possibly nonzero bits are 0xffffff01; in that case
12115 if we only care about QImode, we don't need the AND). This case
12116 occurs if the output mode of an scc insn is not SImode and
12117 STORE_FLAG_VALUE == 1 (e.g., the 386).
12119 Similarly, check for a case where the AND's are ZERO_EXTEND
12120 operations from some narrower mode even though a SUBREG is not
12123 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
12124 && CONST_INT_P (XEXP (op0
, 1))
12125 && CONST_INT_P (XEXP (op1
, 1)))
12127 rtx inner_op0
= XEXP (op0
, 0);
12128 rtx inner_op1
= XEXP (op1
, 0);
12129 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
12130 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
12133 if (paradoxical_subreg_p (inner_op0
)
12134 && GET_CODE (inner_op1
) == SUBREG
12135 && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0
)))
12136 && (GET_MODE (SUBREG_REG (inner_op0
))
12137 == GET_MODE (SUBREG_REG (inner_op1
)))
12138 && ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
12139 GET_MODE (SUBREG_REG (inner_op0
)))) == 0
12140 && ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
12141 GET_MODE (SUBREG_REG (inner_op1
)))) == 0)
12143 op0
= SUBREG_REG (inner_op0
);
12144 op1
= SUBREG_REG (inner_op1
);
12146 /* The resulting comparison is always unsigned since we masked
12147 off the original sign bit. */
12148 code
= unsigned_condition (code
);
12154 FOR_EACH_MODE_UNTIL (tmode
,
12155 as_a
<scalar_int_mode
> (GET_MODE (op0
)))
12156 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
12158 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
12159 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
12160 code
= unsigned_condition (code
);
12169 /* If both operands are NOT, we can strip off the outer operation
12170 and adjust the comparison code for swapped operands; similarly for
12171 NEG, except that this must be an equality comparison. */
12172 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
12173 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
12174 && (code
== EQ
|| code
== NE
)))
12175 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
12181 /* If the first operand is a constant, swap the operands and adjust the
12182 comparison code appropriately, but don't do this if the second operand
12183 is already a constant integer. */
12184 if (swap_commutative_operands_p (op0
, op1
))
12186 std::swap (op0
, op1
);
12187 code
= swap_condition (code
);
12190 /* We now enter a loop during which we will try to simplify the comparison.
12191 For the most part, we only are concerned with comparisons with zero,
12192 but some things may really be comparisons with zero but not start
12193 out looking that way. */
12195 while (CONST_INT_P (op1
))
12197 machine_mode raw_mode
= GET_MODE (op0
);
12198 scalar_int_mode int_mode
;
12199 int equality_comparison_p
;
12200 int sign_bit_comparison_p
;
12201 int unsigned_comparison_p
;
12202 HOST_WIDE_INT const_op
;
12204 /* We only want to handle integral modes. This catches VOIDmode,
12205 CCmode, and the floating-point modes. An exception is that we
12206 can handle VOIDmode if OP0 is a COMPARE or a comparison
12209 if (GET_MODE_CLASS (raw_mode
) != MODE_INT
12210 && ! (raw_mode
== VOIDmode
12211 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
12214 /* Try to simplify the compare to constant, possibly changing the
12215 comparison op, and/or changing op1 to zero. */
12216 code
= simplify_compare_const (code
, raw_mode
, op0
, &op1
);
12217 const_op
= INTVAL (op1
);
12219 /* Compute some predicates to simplify code below. */
12221 equality_comparison_p
= (code
== EQ
|| code
== NE
);
12222 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
12223 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
12226 /* If this is a sign bit comparison and we can do arithmetic in
12227 MODE, say that we will only be needing the sign bit of OP0. */
12228 if (sign_bit_comparison_p
12229 && is_a
<scalar_int_mode
> (raw_mode
, &int_mode
)
12230 && HWI_COMPUTABLE_MODE_P (int_mode
))
12231 op0
= force_to_mode (op0
, int_mode
,
12233 << (GET_MODE_PRECISION (int_mode
) - 1),
12236 if (COMPARISON_P (op0
))
12238 /* We can't do anything if OP0 is a condition code value, rather
12239 than an actual data value. */
12241 || CC0_P (XEXP (op0
, 0))
12242 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12245 /* Get the two operands being compared. */
12246 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12247 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12249 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12251 /* Check for the cases where we simply want the result of the
12252 earlier test or the opposite of that result. */
12253 if (code
== NE
|| code
== EQ
12254 || (val_signbit_known_set_p (raw_mode
, STORE_FLAG_VALUE
)
12255 && (code
== LT
|| code
== GE
)))
12257 enum rtx_code new_code
;
12258 if (code
== LT
|| code
== NE
)
12259 new_code
= GET_CODE (op0
);
12261 new_code
= reversed_comparison_code (op0
, NULL
);
12263 if (new_code
!= UNKNOWN
)
12274 if (raw_mode
== VOIDmode
)
12276 scalar_int_mode mode
= as_a
<scalar_int_mode
> (raw_mode
);
12278 /* Now try cases based on the opcode of OP0. If none of the cases
12279 does a "continue", we exit this loop immediately after the
12282 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
12283 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12284 switch (GET_CODE (op0
))
12287 /* If we are extracting a single bit from a variable position in
12288 a constant that has only a single bit set and are comparing it
12289 with zero, we can convert this into an equality comparison
12290 between the position and the location of the single bit. */
12291 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12292 have already reduced the shift count modulo the word size. */
12293 if (!SHIFT_COUNT_TRUNCATED
12294 && CONST_INT_P (XEXP (op0
, 0))
12295 && XEXP (op0
, 1) == const1_rtx
12296 && equality_comparison_p
&& const_op
== 0
12297 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
12299 if (BITS_BIG_ENDIAN
)
12300 i
= BITS_PER_WORD
- 1 - i
;
12302 op0
= XEXP (op0
, 2);
12306 /* Result is nonzero iff shift count is equal to I. */
12307 code
= reverse_condition (code
);
12314 tem
= expand_compound_operation (op0
);
12323 /* If testing for equality, we can take the NOT of the constant. */
12324 if (equality_comparison_p
12325 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
12327 op0
= XEXP (op0
, 0);
12332 /* If just looking at the sign bit, reverse the sense of the
12334 if (sign_bit_comparison_p
)
12336 op0
= XEXP (op0
, 0);
12337 code
= (code
== GE
? LT
: GE
);
12343 /* If testing for equality, we can take the NEG of the constant. */
12344 if (equality_comparison_p
12345 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
12347 op0
= XEXP (op0
, 0);
12352 /* The remaining cases only apply to comparisons with zero. */
12356 /* When X is ABS or is known positive,
12357 (neg X) is < 0 if and only if X != 0. */
12359 if (sign_bit_comparison_p
12360 && (GET_CODE (XEXP (op0
, 0)) == ABS
12361 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12362 && (nonzero_bits (XEXP (op0
, 0), mode
)
12363 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12366 op0
= XEXP (op0
, 0);
12367 code
= (code
== LT
? NE
: EQ
);
12371 /* If we have NEG of something whose two high-order bits are the
12372 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12373 if (num_sign_bit_copies (op0
, mode
) >= 2)
12375 op0
= XEXP (op0
, 0);
12376 code
= swap_condition (code
);
12382 /* If we are testing equality and our count is a constant, we
12383 can perform the inverse operation on our RHS. */
12384 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12385 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12386 op1
, XEXP (op0
, 1))) != 0)
12388 op0
= XEXP (op0
, 0);
12393 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12394 a particular bit. Convert it to an AND of a constant of that
12395 bit. This will be converted into a ZERO_EXTRACT. */
12396 if (const_op
== 0 && sign_bit_comparison_p
12397 && CONST_INT_P (XEXP (op0
, 1))
12398 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12400 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12403 - INTVAL (XEXP (op0
, 1)))));
12404 code
= (code
== LT
? NE
: EQ
);
12408 /* Fall through. */
12411 /* ABS is ignorable inside an equality comparison with zero. */
12412 if (const_op
== 0 && equality_comparison_p
)
12414 op0
= XEXP (op0
, 0);
12420 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12421 (compare FOO CONST) if CONST fits in FOO's mode and we
12422 are either testing inequality or have an unsigned
12423 comparison with ZERO_EXTEND or a signed comparison with
12424 SIGN_EXTEND. But don't do it if we don't have a compare
12425 insn of the given mode, since we'd have to revert it
12426 later on, and then we wouldn't know whether to sign- or
12428 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12429 && ! unsigned_comparison_p
12430 && HWI_COMPUTABLE_MODE_P (mode
)
12431 && trunc_int_for_mode (const_op
, mode
) == const_op
12432 && have_insn_for (COMPARE
, mode
))
12434 op0
= XEXP (op0
, 0);
12440 /* Check for the case where we are comparing A - C1 with C2, that is
12442 (subreg:MODE (plus (A) (-C1))) op (C2)
12444 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12445 comparison in the wider mode. One of the following two conditions
12446 must be true in order for this to be valid:
12448 1. The mode extension results in the same bit pattern being added
12449 on both sides and the comparison is equality or unsigned. As
12450 C2 has been truncated to fit in MODE, the pattern can only be
12453 2. The mode extension results in the sign bit being copied on
12456 The difficulty here is that we have predicates for A but not for
12457 (A - C1) so we need to check that C1 is within proper bounds so
12458 as to perturbate A as little as possible. */
12460 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12461 && subreg_lowpart_p (op0
)
12462 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op0
)),
12464 && GET_MODE_PRECISION (inner_mode
) > mode_width
12465 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12466 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12468 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12469 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12472 && (unsigned HOST_WIDE_INT
) c1
12473 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12474 && (equality_comparison_p
|| unsigned_comparison_p
)
12475 /* (A - C1) zero-extends if it is positive and sign-extends
12476 if it is negative, C2 both zero- and sign-extends. */
12477 && (((nonzero_bits (a
, inner_mode
)
12478 & ~GET_MODE_MASK (mode
)) == 0
12480 /* (A - C1) sign-extends if it is positive and 1-extends
12481 if it is negative, C2 both sign- and 1-extends. */
12482 || (num_sign_bit_copies (a
, inner_mode
)
12483 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12486 || ((unsigned HOST_WIDE_INT
) c1
12487 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12488 /* (A - C1) always sign-extends, like C2. */
12489 && num_sign_bit_copies (a
, inner_mode
)
12490 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12491 - (mode_width
- 1))))
12493 op0
= SUBREG_REG (op0
);
12498 /* If the inner mode is narrower and we are extracting the low part,
12499 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12500 if (paradoxical_subreg_p (op0
))
12502 else if (subreg_lowpart_p (op0
)
12503 && GET_MODE_CLASS (mode
) == MODE_INT
12504 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12505 && (code
== NE
|| code
== EQ
)
12506 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12507 && !paradoxical_subreg_p (op0
)
12508 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12509 & ~GET_MODE_MASK (mode
)) == 0)
12511 /* Remove outer subregs that don't do anything. */
12512 tem
= gen_lowpart (inner_mode
, op1
);
12514 if ((nonzero_bits (tem
, inner_mode
)
12515 & ~GET_MODE_MASK (mode
)) == 0)
12517 op0
= SUBREG_REG (op0
);
12529 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12530 && (unsigned_comparison_p
|| equality_comparison_p
)
12531 && HWI_COMPUTABLE_MODE_P (mode
)
12532 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12534 && have_insn_for (COMPARE
, mode
))
12536 op0
= XEXP (op0
, 0);
12542 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12543 this for equality comparisons due to pathological cases involving
12545 if (equality_comparison_p
12546 && (tem
= simplify_binary_operation (MINUS
, mode
,
12547 op1
, XEXP (op0
, 1))) != 0)
12549 op0
= XEXP (op0
, 0);
12554 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12555 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12556 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12558 op0
= XEXP (XEXP (op0
, 0), 0);
12559 code
= (code
== LT
? EQ
: NE
);
12565 /* We used to optimize signed comparisons against zero, but that
12566 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12567 arrive here as equality comparisons, or (GEU, LTU) are
12568 optimized away. No need to special-case them. */
12570 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12571 (eq B (minus A C)), whichever simplifies. We can only do
12572 this for equality comparisons due to pathological cases involving
12574 if (equality_comparison_p
12575 && (tem
= simplify_binary_operation (PLUS
, mode
,
12576 XEXP (op0
, 1), op1
)) != 0)
12578 op0
= XEXP (op0
, 0);
12583 if (equality_comparison_p
12584 && (tem
= simplify_binary_operation (MINUS
, mode
,
12585 XEXP (op0
, 0), op1
)) != 0)
12587 op0
= XEXP (op0
, 1);
12592 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12593 of bits in X minus 1, is one iff X > 0. */
12594 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12595 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12596 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12597 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12599 op0
= XEXP (op0
, 1);
12600 code
= (code
== GE
? LE
: GT
);
12606 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12607 if C is zero or B is a constant. */
12608 if (equality_comparison_p
12609 && (tem
= simplify_binary_operation (XOR
, mode
,
12610 XEXP (op0
, 1), op1
)) != 0)
12612 op0
= XEXP (op0
, 0);
12620 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12622 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12623 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12624 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12626 op0
= XEXP (op0
, 1);
12627 code
= (code
== GE
? GT
: LE
);
12633 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12634 will be converted to a ZERO_EXTRACT later. */
12635 if (const_op
== 0 && equality_comparison_p
12636 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12637 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12639 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12640 XEXP (XEXP (op0
, 0), 1));
12641 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12645 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12646 zero and X is a comparison and C1 and C2 describe only bits set
12647 in STORE_FLAG_VALUE, we can compare with X. */
12648 if (const_op
== 0 && equality_comparison_p
12649 && mode_width
<= HOST_BITS_PER_WIDE_INT
12650 && CONST_INT_P (XEXP (op0
, 1))
12651 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12652 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12653 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12654 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12656 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12657 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12658 if ((~STORE_FLAG_VALUE
& mask
) == 0
12659 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12660 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12661 && COMPARISON_P (tem
))))
12663 op0
= XEXP (XEXP (op0
, 0), 0);
12668 /* If we are doing an equality comparison of an AND of a bit equal
12669 to the sign bit, replace this with a LT or GE comparison of
12670 the underlying value. */
12671 if (equality_comparison_p
12673 && CONST_INT_P (XEXP (op0
, 1))
12674 && mode_width
<= HOST_BITS_PER_WIDE_INT
12675 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12676 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12678 op0
= XEXP (op0
, 0);
12679 code
= (code
== EQ
? GE
: LT
);
12683 /* If this AND operation is really a ZERO_EXTEND from a narrower
12684 mode, the constant fits within that mode, and this is either an
12685 equality or unsigned comparison, try to do this comparison in
12690 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12691 -> (ne:DI (reg:SI 4) (const_int 0))
12693 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12694 known to hold a value of the required mode the
12695 transformation is invalid. */
12696 if ((equality_comparison_p
|| unsigned_comparison_p
)
12697 && CONST_INT_P (XEXP (op0
, 1))
12698 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12699 & GET_MODE_MASK (mode
))
12701 && const_op
>> i
== 0
12702 && int_mode_for_size (i
, 1).exists (&tmode
))
12704 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12708 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12709 fits in both M1 and M2 and the SUBREG is either paradoxical
12710 or represents the low part, permute the SUBREG and the AND
12712 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12713 && CONST_INT_P (XEXP (op0
, 1)))
12715 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12716 /* Require an integral mode, to avoid creating something like
12718 if ((is_a
<scalar_int_mode
>
12719 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))), &tmode
))
12720 /* It is unsafe to commute the AND into the SUBREG if the
12721 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12722 not defined. As originally written the upper bits
12723 have a defined value due to the AND operation.
12724 However, if we commute the AND inside the SUBREG then
12725 they no longer have defined values and the meaning of
12726 the code has been changed.
12727 Also C1 should not change value in the smaller mode,
12728 see PR67028 (a positive C1 can become negative in the
12729 smaller mode, so that the AND does no longer mask the
12731 && ((WORD_REGISTER_OPERATIONS
12732 && mode_width
> GET_MODE_PRECISION (tmode
)
12733 && mode_width
<= BITS_PER_WORD
12734 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12735 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12736 && subreg_lowpart_p (XEXP (op0
, 0))))
12737 && mode_width
<= HOST_BITS_PER_WIDE_INT
12738 && HWI_COMPUTABLE_MODE_P (tmode
)
12739 && (c1
& ~mask
) == 0
12740 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12742 && c1
!= GET_MODE_MASK (tmode
))
12744 op0
= simplify_gen_binary (AND
, tmode
,
12745 SUBREG_REG (XEXP (op0
, 0)),
12746 gen_int_mode (c1
, tmode
));
12747 op0
= gen_lowpart (mode
, op0
);
12752 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12753 if (const_op
== 0 && equality_comparison_p
12754 && XEXP (op0
, 1) == const1_rtx
12755 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12757 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12758 XEXP (XEXP (op0
, 0), 0), 1);
12759 code
= (code
== NE
? EQ
: NE
);
12763 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12764 (eq (and (lshiftrt X) 1) 0).
12765 Also handle the case where (not X) is expressed using xor. */
12766 if (const_op
== 0 && equality_comparison_p
12767 && XEXP (op0
, 1) == const1_rtx
12768 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12770 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12771 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12773 if (GET_CODE (shift_op
) == NOT
12774 || (GET_CODE (shift_op
) == XOR
12775 && CONST_INT_P (XEXP (shift_op
, 1))
12776 && CONST_INT_P (shift_count
)
12777 && HWI_COMPUTABLE_MODE_P (mode
)
12778 && (UINTVAL (XEXP (shift_op
, 1))
12779 == HOST_WIDE_INT_1U
12780 << INTVAL (shift_count
))))
12783 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12784 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12785 code
= (code
== NE
? EQ
: NE
);
12792 /* If we have (compare (ashift FOO N) (const_int C)) and
12793 the high order N bits of FOO (N+1 if an inequality comparison)
12794 are known to be zero, we can do this by comparing FOO with C
12795 shifted right N bits so long as the low-order N bits of C are
12797 if (CONST_INT_P (XEXP (op0
, 1))
12798 && INTVAL (XEXP (op0
, 1)) >= 0
12799 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12800 < HOST_BITS_PER_WIDE_INT
)
12801 && (((unsigned HOST_WIDE_INT
) const_op
12802 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12804 && mode_width
<= HOST_BITS_PER_WIDE_INT
12805 && (nonzero_bits (XEXP (op0
, 0), mode
)
12806 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12807 + ! equality_comparison_p
))) == 0)
12809 /* We must perform a logical shift, not an arithmetic one,
12810 as we want the top N bits of C to be zero. */
12811 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12813 temp
>>= INTVAL (XEXP (op0
, 1));
12814 op1
= gen_int_mode (temp
, mode
);
12815 op0
= XEXP (op0
, 0);
12819 /* If we are doing a sign bit comparison, it means we are testing
12820 a particular bit. Convert it to the appropriate AND. */
12821 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12822 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12824 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12827 - INTVAL (XEXP (op0
, 1)))));
12828 code
= (code
== LT
? NE
: EQ
);
12832 /* If this an equality comparison with zero and we are shifting
12833 the low bit to the sign bit, we can convert this to an AND of the
12835 if (const_op
== 0 && equality_comparison_p
12836 && CONST_INT_P (XEXP (op0
, 1))
12837 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12839 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12845 /* If this is an equality comparison with zero, we can do this
12846 as a logical shift, which might be much simpler. */
12847 if (equality_comparison_p
&& const_op
== 0
12848 && CONST_INT_P (XEXP (op0
, 1)))
12850 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12852 INTVAL (XEXP (op0
, 1)));
12856 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12857 do the comparison in a narrower mode. */
12858 if (! unsigned_comparison_p
12859 && CONST_INT_P (XEXP (op0
, 1))
12860 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12861 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12862 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12864 && (((unsigned HOST_WIDE_INT
) const_op
12865 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12866 <= GET_MODE_MASK (tmode
)))
12868 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12872 /* Likewise if OP0 is a PLUS of a sign extension with a
12873 constant, which is usually represented with the PLUS
12874 between the shifts. */
12875 if (! unsigned_comparison_p
12876 && CONST_INT_P (XEXP (op0
, 1))
12877 && GET_CODE (XEXP (op0
, 0)) == PLUS
12878 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12879 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12880 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12881 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12883 && (((unsigned HOST_WIDE_INT
) const_op
12884 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12885 <= GET_MODE_MASK (tmode
)))
12887 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12888 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12889 rtx new_const
= simplify_gen_binary (ASHIFTRT
, mode
,
12890 add_const
, XEXP (op0
, 1));
12892 op0
= simplify_gen_binary (PLUS
, tmode
,
12893 gen_lowpart (tmode
, inner
),
12900 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12901 the low order N bits of FOO are known to be zero, we can do this
12902 by comparing FOO with C shifted left N bits so long as no
12903 overflow occurs. Even if the low order N bits of FOO aren't known
12904 to be zero, if the comparison is >= or < we can use the same
12905 optimization and for > or <= by setting all the low
12906 order N bits in the comparison constant. */
12907 if (CONST_INT_P (XEXP (op0
, 1))
12908 && INTVAL (XEXP (op0
, 1)) > 0
12909 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12910 && mode_width
<= HOST_BITS_PER_WIDE_INT
12911 && (((unsigned HOST_WIDE_INT
) const_op
12912 + (GET_CODE (op0
) != LSHIFTRT
12913 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12916 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12918 unsigned HOST_WIDE_INT low_bits
12919 = (nonzero_bits (XEXP (op0
, 0), mode
)
12920 & ((HOST_WIDE_INT_1U
12921 << INTVAL (XEXP (op0
, 1))) - 1));
12922 if (low_bits
== 0 || !equality_comparison_p
)
12924 /* If the shift was logical, then we must make the condition
12926 if (GET_CODE (op0
) == LSHIFTRT
)
12927 code
= unsigned_condition (code
);
12929 const_op
= (unsigned HOST_WIDE_INT
) const_op
12930 << INTVAL (XEXP (op0
, 1));
12932 && (code
== GT
|| code
== GTU
12933 || code
== LE
|| code
== LEU
))
12935 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12936 op1
= GEN_INT (const_op
);
12937 op0
= XEXP (op0
, 0);
12942 /* If we are using this shift to extract just the sign bit, we
12943 can replace this with an LT or GE comparison. */
12945 && (equality_comparison_p
|| sign_bit_comparison_p
)
12946 && CONST_INT_P (XEXP (op0
, 1))
12947 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12949 op0
= XEXP (op0
, 0);
12950 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12962 /* Now make any compound operations involved in this comparison. Then,
12963 check for an outmost SUBREG on OP0 that is not doing anything or is
12964 paradoxical. The latter transformation must only be performed when
12965 it is known that the "extra" bits will be the same in op0 and op1 or
12966 that they don't matter. There are three cases to consider:
12968 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12969 care bits and we can assume they have any convenient value. So
12970 making the transformation is safe.
12972 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12973 In this case the upper bits of op0 are undefined. We should not make
12974 the simplification in that case as we do not know the contents of
12977 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12978 In that case we know those bits are zeros or ones. We must also be
12979 sure that they are the same as the upper bits of op1.
12981 We can never remove a SUBREG for a non-equality comparison because
12982 the sign bit is in a different place in the underlying object. */
12984 rtx_code op0_mco_code
= SET
;
12985 if (op1
== const0_rtx
)
12986 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12988 op0
= make_compound_operation (op0
, op0_mco_code
);
12989 op1
= make_compound_operation (op1
, SET
);
12991 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12992 && is_int_mode (GET_MODE (op0
), &mode
)
12993 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12994 && (code
== NE
|| code
== EQ
))
12996 if (paradoxical_subreg_p (op0
))
12998 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13000 if (REG_P (SUBREG_REG (op0
)))
13002 op0
= SUBREG_REG (op0
);
13003 op1
= gen_lowpart (inner_mode
, op1
);
13006 else if (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
13007 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
13008 & ~GET_MODE_MASK (mode
)) == 0)
13010 tem
= gen_lowpart (inner_mode
, op1
);
13012 if ((nonzero_bits (tem
, inner_mode
) & ~GET_MODE_MASK (mode
)) == 0)
13013 op0
= SUBREG_REG (op0
), op1
= tem
;
13017 /* We now do the opposite procedure: Some machines don't have compare
13018 insns in all modes. If OP0's mode is an integer mode smaller than a
13019 word and we can't do a compare in that mode, see if there is a larger
13020 mode for which we can do the compare. There are a number of cases in
13021 which we can use the wider mode. */
13023 if (is_int_mode (GET_MODE (op0
), &mode
)
13024 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
13025 && ! have_insn_for (COMPARE
, mode
))
13026 FOR_EACH_WIDER_MODE (tmode_iter
, mode
)
13028 tmode
= tmode_iter
.require ();
13029 if (!HWI_COMPUTABLE_MODE_P (tmode
))
13031 if (have_insn_for (COMPARE
, tmode
))
13035 /* If this is a test for negative, we can make an explicit
13036 test of the sign bit. Test this first so we can use
13037 a paradoxical subreg to extend OP0. */
13039 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
13040 && HWI_COMPUTABLE_MODE_P (mode
))
13042 unsigned HOST_WIDE_INT sign
13043 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
13044 op0
= simplify_gen_binary (AND
, tmode
,
13045 gen_lowpart (tmode
, op0
),
13046 gen_int_mode (sign
, tmode
));
13047 code
= (code
== LT
) ? NE
: EQ
;
13051 /* If the only nonzero bits in OP0 and OP1 are those in the
13052 narrower mode and this is an equality or unsigned comparison,
13053 we can use the wider mode. Similarly for sign-extended
13054 values, in which case it is true for all comparisons. */
13055 zero_extended
= ((code
== EQ
|| code
== NE
13056 || code
== GEU
|| code
== GTU
13057 || code
== LEU
|| code
== LTU
)
13058 && (nonzero_bits (op0
, tmode
)
13059 & ~GET_MODE_MASK (mode
)) == 0
13060 && ((CONST_INT_P (op1
)
13061 || (nonzero_bits (op1
, tmode
)
13062 & ~GET_MODE_MASK (mode
)) == 0)));
13065 || ((num_sign_bit_copies (op0
, tmode
)
13066 > (unsigned int) (GET_MODE_PRECISION (tmode
)
13067 - GET_MODE_PRECISION (mode
)))
13068 && (num_sign_bit_copies (op1
, tmode
)
13069 > (unsigned int) (GET_MODE_PRECISION (tmode
)
13070 - GET_MODE_PRECISION (mode
)))))
13072 /* If OP0 is an AND and we don't have an AND in MODE either,
13073 make a new AND in the proper mode. */
13074 if (GET_CODE (op0
) == AND
13075 && !have_insn_for (AND
, mode
))
13076 op0
= simplify_gen_binary (AND
, tmode
,
13077 gen_lowpart (tmode
,
13079 gen_lowpart (tmode
,
13085 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
13087 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
13092 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
13094 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
13103 /* We may have changed the comparison operands. Re-canonicalize. */
13104 if (swap_commutative_operands_p (op0
, op1
))
13106 std::swap (op0
, op1
);
13107 code
= swap_condition (code
);
13110 /* If this machine only supports a subset of valid comparisons, see if we
13111 can convert an unsupported one into a supported one. */
13112 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
13120 /* Utility function for record_value_for_reg. Count number of
13125 enum rtx_code code
= GET_CODE (x
);
13129 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
13130 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
13132 rtx x0
= XEXP (x
, 0);
13133 rtx x1
= XEXP (x
, 1);
13136 return 1 + 2 * count_rtxs (x0
);
13138 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
13139 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
13140 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13141 return 2 + 2 * count_rtxs (x0
)
13142 + count_rtxs (x
== XEXP (x1
, 0)
13143 ? XEXP (x1
, 1) : XEXP (x1
, 0));
13145 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
13146 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
13147 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13148 return 2 + 2 * count_rtxs (x1
)
13149 + count_rtxs (x
== XEXP (x0
, 0)
13150 ? XEXP (x0
, 1) : XEXP (x0
, 0));
13153 fmt
= GET_RTX_FORMAT (code
);
13154 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13156 ret
+= count_rtxs (XEXP (x
, i
));
13157 else if (fmt
[i
] == 'E')
13158 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13159 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
13164 /* Utility function for following routine. Called when X is part of a value
13165 being stored into last_set_value. Sets last_set_table_tick
13166 for each register mentioned. Similar to mention_regs in cse.c */
13169 update_table_tick (rtx x
)
13171 enum rtx_code code
= GET_CODE (x
);
13172 const char *fmt
= GET_RTX_FORMAT (code
);
13177 unsigned int regno
= REGNO (x
);
13178 unsigned int endregno
= END_REGNO (x
);
13181 for (r
= regno
; r
< endregno
; r
++)
13183 reg_stat_type
*rsp
= ®_stat
[r
];
13184 rsp
->last_set_table_tick
= label_tick
;
13190 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13193 /* Check for identical subexpressions. If x contains
13194 identical subexpression we only have to traverse one of
13196 if (i
== 0 && ARITHMETIC_P (x
))
13198 /* Note that at this point x1 has already been
13200 rtx x0
= XEXP (x
, 0);
13201 rtx x1
= XEXP (x
, 1);
13203 /* If x0 and x1 are identical then there is no need to
13208 /* If x0 is identical to a subexpression of x1 then while
13209 processing x1, x0 has already been processed. Thus we
13210 are done with x. */
13211 if (ARITHMETIC_P (x1
)
13212 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13215 /* If x1 is identical to a subexpression of x0 then we
13216 still have to process the rest of x0. */
13217 if (ARITHMETIC_P (x0
)
13218 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13220 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
13225 update_table_tick (XEXP (x
, i
));
13227 else if (fmt
[i
] == 'E')
13228 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13229 update_table_tick (XVECEXP (x
, i
, j
));
13232 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13233 are saying that the register is clobbered and we no longer know its
13234 value. If INSN is zero, don't update reg_stat[].last_set; this is
13235 only permitted with VALUE also zero and is used to invalidate the
13239 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
13241 unsigned int regno
= REGNO (reg
);
13242 unsigned int endregno
= END_REGNO (reg
);
13244 reg_stat_type
*rsp
;
13246 /* If VALUE contains REG and we have a previous value for REG, substitute
13247 the previous value. */
13248 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
13252 /* Set things up so get_last_value is allowed to see anything set up to
13254 subst_low_luid
= DF_INSN_LUID (insn
);
13255 tem
= get_last_value (reg
);
13257 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13258 it isn't going to be useful and will take a lot of time to process,
13259 so just use the CLOBBER. */
13263 if (ARITHMETIC_P (tem
)
13264 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
13265 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
13266 tem
= XEXP (tem
, 0);
13267 else if (count_occurrences (value
, reg
, 1) >= 2)
13269 /* If there are two or more occurrences of REG in VALUE,
13270 prevent the value from growing too much. */
13271 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
13272 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
13275 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
13279 /* For each register modified, show we don't know its value, that
13280 we don't know about its bitwise content, that its value has been
13281 updated, and that we don't know the location of the death of the
13283 for (i
= regno
; i
< endregno
; i
++)
13285 rsp
= ®_stat
[i
];
13288 rsp
->last_set
= insn
;
13290 rsp
->last_set_value
= 0;
13291 rsp
->last_set_mode
= VOIDmode
;
13292 rsp
->last_set_nonzero_bits
= 0;
13293 rsp
->last_set_sign_bit_copies
= 0;
13294 rsp
->last_death
= 0;
13295 rsp
->truncated_to_mode
= VOIDmode
;
13298 /* Mark registers that are being referenced in this value. */
13300 update_table_tick (value
);
13302 /* Now update the status of each register being set.
13303 If someone is using this register in this block, set this register
13304 to invalid since we will get confused between the two lives in this
13305 basic block. This makes using this register always invalid. In cse, we
13306 scan the table to invalidate all entries using this register, but this
13307 is too much work for us. */
13309 for (i
= regno
; i
< endregno
; i
++)
13311 rsp
= ®_stat
[i
];
13312 rsp
->last_set_label
= label_tick
;
13314 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13315 rsp
->last_set_invalid
= 1;
13317 rsp
->last_set_invalid
= 0;
13320 /* The value being assigned might refer to X (like in "x++;"). In that
13321 case, we must replace it with (clobber (const_int 0)) to prevent
13323 rsp
= ®_stat
[regno
];
13324 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
13326 value
= copy_rtx (value
);
13327 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
13331 /* For the main register being modified, update the value, the mode, the
13332 nonzero bits, and the number of sign bit copies. */
13334 rsp
->last_set_value
= value
;
13338 machine_mode mode
= GET_MODE (reg
);
13339 subst_low_luid
= DF_INSN_LUID (insn
);
13340 rsp
->last_set_mode
= mode
;
13341 if (GET_MODE_CLASS (mode
) == MODE_INT
13342 && HWI_COMPUTABLE_MODE_P (mode
))
13343 mode
= nonzero_bits_mode
;
13344 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13345 rsp
->last_set_sign_bit_copies
13346 = num_sign_bit_copies (value
, GET_MODE (reg
));
13350 /* Called via note_stores from record_dead_and_set_regs to handle one
13351 SET or CLOBBER in an insn. DATA is the instruction in which the
13352 set is occurring. */
13355 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13357 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13359 if (GET_CODE (dest
) == SUBREG
)
13360 dest
= SUBREG_REG (dest
);
13362 if (!record_dead_insn
)
13365 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13371 /* If we are setting the whole register, we know its value. Otherwise
13372 show that we don't know the value. We can handle a SUBREG if it's
13373 the low part, but we must be careful with paradoxical SUBREGs on
13374 RISC architectures because we cannot strip e.g. an extension around
13375 a load and record the naked load since the RTL middle-end considers
13376 that the upper bits are defined according to LOAD_EXTEND_OP. */
13377 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13378 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13379 else if (GET_CODE (setter
) == SET
13380 && GET_CODE (SET_DEST (setter
)) == SUBREG
13381 && SUBREG_REG (SET_DEST (setter
)) == dest
13382 && known_le (GET_MODE_PRECISION (GET_MODE (dest
)),
13384 && subreg_lowpart_p (SET_DEST (setter
)))
13385 record_value_for_reg (dest
, record_dead_insn
,
13386 WORD_REGISTER_OPERATIONS
13387 && word_register_operation_p (SET_SRC (setter
))
13388 && paradoxical_subreg_p (SET_DEST (setter
))
13390 : gen_lowpart (GET_MODE (dest
),
13391 SET_SRC (setter
)));
13392 else if (GET_CODE (setter
) == CLOBBER_HIGH
)
13394 reg_stat_type
*rsp
= ®_stat
[REGNO (dest
)];
13395 if (rsp
->last_set_value
13396 && reg_is_clobbered_by_clobber_high
13397 (REGNO (dest
), GET_MODE (rsp
->last_set_value
),
13399 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13402 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13404 else if (MEM_P (dest
)
13405 /* Ignore pushes, they clobber nothing. */
13406 && ! push_operand (dest
, GET_MODE (dest
)))
13407 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13410 /* Update the records of when each REG was most recently set or killed
13411 for the things done by INSN. This is the last thing done in processing
13412 INSN in the combiner loop.
13414 We update reg_stat[], in particular fields last_set, last_set_value,
13415 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13416 last_death, and also the similar information mem_last_set (which insn
13417 most recently modified memory) and last_call_luid (which insn was the
13418 most recent subroutine call). */
13421 record_dead_and_set_regs (rtx_insn
*insn
)
13426 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13428 if (REG_NOTE_KIND (link
) == REG_DEAD
13429 && REG_P (XEXP (link
, 0)))
13431 unsigned int regno
= REGNO (XEXP (link
, 0));
13432 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13434 for (i
= regno
; i
< endregno
; i
++)
13436 reg_stat_type
*rsp
;
13438 rsp
= ®_stat
[i
];
13439 rsp
->last_death
= insn
;
13442 else if (REG_NOTE_KIND (link
) == REG_INC
)
13443 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13448 hard_reg_set_iterator hrsi
;
13449 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
13451 reg_stat_type
*rsp
;
13453 rsp
= ®_stat
[i
];
13454 rsp
->last_set_invalid
= 1;
13455 rsp
->last_set
= insn
;
13456 rsp
->last_set_value
= 0;
13457 rsp
->last_set_mode
= VOIDmode
;
13458 rsp
->last_set_nonzero_bits
= 0;
13459 rsp
->last_set_sign_bit_copies
= 0;
13460 rsp
->last_death
= 0;
13461 rsp
->truncated_to_mode
= VOIDmode
;
13464 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13466 /* We can't combine into a call pattern. Remember, though, that
13467 the return value register is set at this LUID. We could
13468 still replace a register with the return value from the
13469 wrong subroutine call! */
13470 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
13473 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
13476 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13477 register present in the SUBREG, so for each such SUBREG go back and
13478 adjust nonzero and sign bit information of the registers that are
13479 known to have some zero/sign bits set.
13481 This is needed because when combine blows the SUBREGs away, the
13482 information on zero/sign bits is lost and further combines can be
13483 missed because of that. */
13486 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13488 struct insn_link
*links
;
13490 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13491 machine_mode mode
= GET_MODE (subreg
);
13493 if (!HWI_COMPUTABLE_MODE_P (mode
))
13496 for (links
= LOG_LINKS (insn
); links
;)
13498 reg_stat_type
*rsp
;
13500 insn
= links
->insn
;
13501 set
= single_set (insn
);
13503 if (! set
|| !REG_P (SET_DEST (set
))
13504 || REGNO (SET_DEST (set
)) != regno
13505 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13507 links
= links
->next
;
13511 rsp
= ®_stat
[regno
];
13512 if (rsp
->last_set
== insn
)
13514 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13515 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13518 if (REG_P (SET_SRC (set
)))
13520 regno
= REGNO (SET_SRC (set
));
13521 links
= LOG_LINKS (insn
);
13528 /* Check if X, a register, is known to contain a value already
13529 truncated to MODE. In this case we can use a subreg to refer to
13530 the truncated value even though in the generic case we would need
13531 an explicit truncation. */
13534 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13536 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13537 machine_mode truncated
= rsp
->truncated_to_mode
;
13540 || rsp
->truncation_label
< label_tick_ebb_start
)
13542 if (!partial_subreg_p (mode
, truncated
))
13544 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13549 /* If X is a hard reg or a subreg record the mode that the register is
13550 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13551 able to turn a truncate into a subreg using this information. Return true
13552 if traversing X is complete. */
13555 record_truncated_value (rtx x
)
13557 machine_mode truncated_mode
;
13558 reg_stat_type
*rsp
;
13560 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13562 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13563 truncated_mode
= GET_MODE (x
);
13565 if (!partial_subreg_p (truncated_mode
, original_mode
))
13568 truncated_mode
= GET_MODE (x
);
13569 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13572 x
= SUBREG_REG (x
);
13574 /* ??? For hard-regs we now record everything. We might be able to
13575 optimize this using last_set_mode. */
13576 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13577 truncated_mode
= GET_MODE (x
);
13581 rsp
= ®_stat
[REGNO (x
)];
13582 if (rsp
->truncated_to_mode
== 0
13583 || rsp
->truncation_label
< label_tick_ebb_start
13584 || partial_subreg_p (truncated_mode
, rsp
->truncated_to_mode
))
13586 rsp
->truncated_to_mode
= truncated_mode
;
13587 rsp
->truncation_label
= label_tick
;
13593 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13594 the modes they are used in. This can help truning TRUNCATEs into
13598 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13600 subrtx_var_iterator::array_type array
;
13601 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13602 if (record_truncated_value (*iter
))
13603 iter
.skip_subrtxes ();
13606 /* Scan X for promoted SUBREGs. For each one found,
13607 note what it implies to the registers used in it. */
13610 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13612 if (GET_CODE (x
) == SUBREG
13613 && SUBREG_PROMOTED_VAR_P (x
)
13614 && REG_P (SUBREG_REG (x
)))
13615 record_promoted_value (insn
, x
);
13618 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13621 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13625 check_promoted_subreg (insn
, XEXP (x
, i
));
13629 if (XVEC (x
, i
) != 0)
13630 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13631 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13637 /* Verify that all the registers and memory references mentioned in *LOC are
13638 still valid. *LOC was part of a value set in INSN when label_tick was
13639 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13640 the invalid references with (clobber (const_int 0)) and return 1. This
13641 replacement is useful because we often can get useful information about
13642 the form of a value (e.g., if it was produced by a shift that always
13643 produces -1 or 0) even though we don't know exactly what registers it
13644 was produced from. */
13647 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13650 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13651 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13656 unsigned int regno
= REGNO (x
);
13657 unsigned int endregno
= END_REGNO (x
);
13660 for (j
= regno
; j
< endregno
; j
++)
13662 reg_stat_type
*rsp
= ®_stat
[j
];
13663 if (rsp
->last_set_invalid
13664 /* If this is a pseudo-register that was only set once and not
13665 live at the beginning of the function, it is always valid. */
13666 || (! (regno
>= FIRST_PSEUDO_REGISTER
13667 && regno
< reg_n_sets_max
13668 && REG_N_SETS (regno
) == 1
13669 && (!REGNO_REG_SET_P
13670 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13672 && rsp
->last_set_label
> tick
))
13675 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13682 /* If this is a memory reference, make sure that there were no stores after
13683 it that might have clobbered the value. We don't have alias info, so we
13684 assume any store invalidates it. Moreover, we only have local UIDs, so
13685 we also assume that there were stores in the intervening basic blocks. */
13686 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13687 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13690 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13694 for (i
= 0; i
< len
; i
++)
13698 /* Check for identical subexpressions. If x contains
13699 identical subexpression we only have to traverse one of
13701 if (i
== 1 && ARITHMETIC_P (x
))
13703 /* Note that at this point x0 has already been checked
13704 and found valid. */
13705 rtx x0
= XEXP (x
, 0);
13706 rtx x1
= XEXP (x
, 1);
13708 /* If x0 and x1 are identical then x is also valid. */
13712 /* If x1 is identical to a subexpression of x0 then
13713 while checking x0, x1 has already been checked. Thus
13714 it is valid and so as x. */
13715 if (ARITHMETIC_P (x0
)
13716 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13719 /* If x0 is identical to a subexpression of x1 then x is
13720 valid iff the rest of x1 is valid. */
13721 if (ARITHMETIC_P (x1
)
13722 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13724 get_last_value_validate (&XEXP (x1
,
13725 x0
== XEXP (x1
, 0) ? 1 : 0),
13726 insn
, tick
, replace
);
13729 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13733 else if (fmt
[i
] == 'E')
13734 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13735 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13736 insn
, tick
, replace
) == 0)
13740 /* If we haven't found a reason for it to be invalid, it is valid. */
13744 /* Get the last value assigned to X, if known. Some registers
13745 in the value may be replaced with (clobber (const_int 0)) if their value
13746 is known longer known reliably. */
13749 get_last_value (const_rtx x
)
13751 unsigned int regno
;
13753 reg_stat_type
*rsp
;
13755 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13756 then convert it to the desired mode. If this is a paradoxical SUBREG,
13757 we cannot predict what values the "extra" bits might have. */
13758 if (GET_CODE (x
) == SUBREG
13759 && subreg_lowpart_p (x
)
13760 && !paradoxical_subreg_p (x
)
13761 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13762 return gen_lowpart (GET_MODE (x
), value
);
13768 rsp
= ®_stat
[regno
];
13769 value
= rsp
->last_set_value
;
13771 /* If we don't have a value, or if it isn't for this basic block and
13772 it's either a hard register, set more than once, or it's a live
13773 at the beginning of the function, return 0.
13775 Because if it's not live at the beginning of the function then the reg
13776 is always set before being used (is never used without being set).
13777 And, if it's set only once, and it's always set before use, then all
13778 uses must have the same last value, even if it's not from this basic
13782 || (rsp
->last_set_label
< label_tick_ebb_start
13783 && (regno
< FIRST_PSEUDO_REGISTER
13784 || regno
>= reg_n_sets_max
13785 || REG_N_SETS (regno
) != 1
13787 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13790 /* If the value was set in a later insn than the ones we are processing,
13791 we can't use it even if the register was only set once. */
13792 if (rsp
->last_set_label
== label_tick
13793 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13796 /* If fewer bits were set than what we are asked for now, we cannot use
13798 if (maybe_lt (GET_MODE_PRECISION (rsp
->last_set_mode
),
13799 GET_MODE_PRECISION (GET_MODE (x
))))
13802 /* If the value has all its registers valid, return it. */
13803 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13806 /* Otherwise, make a copy and replace any invalid register with
13807 (clobber (const_int 0)). If that fails for some reason, return 0. */
13809 value
= copy_rtx (value
);
13810 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13816 /* Define three variables used for communication between the following
13819 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13820 static int reg_dead_flag
;
13823 /* Function called via note_stores from reg_dead_at_p.
13825 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13826 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13829 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13831 unsigned int regno
, endregno
;
13836 if (GET_CODE (x
) == CLOBBER_HIGH
13837 && !reg_is_clobbered_by_clobber_high (reg_dead_reg
, XEXP (x
, 0)))
13840 regno
= REGNO (dest
);
13841 endregno
= END_REGNO (dest
);
13842 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13843 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13846 /* Return nonzero if REG is known to be dead at INSN.
13848 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13849 referencing REG, it is dead. If we hit a SET referencing REG, it is
13850 live. Otherwise, see if it is live or dead at the start of the basic
13851 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13852 must be assumed to be always live. */
13855 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13860 /* Set variables for reg_dead_at_p_1. */
13861 reg_dead_regno
= REGNO (reg
);
13862 reg_dead_endregno
= END_REGNO (reg
);
13863 reg_dead_reg
= reg
;
13867 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13868 we allow the machine description to decide whether use-and-clobber
13869 patterns are OK. */
13870 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13872 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13873 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13877 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13878 beginning of basic block. */
13879 block
= BLOCK_FOR_INSN (insn
);
13884 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13887 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13889 return reg_dead_flag
== 1 ? 1 : 0;
13891 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13895 if (insn
== BB_HEAD (block
))
13898 insn
= PREV_INSN (insn
);
13901 /* Look at live-in sets for the basic block that we were in. */
13902 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13903 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13909 /* Note hard registers in X that are used. */
13912 mark_used_regs_combine (rtx x
)
13914 RTX_CODE code
= GET_CODE (x
);
13915 unsigned int regno
;
13926 case ADDR_DIFF_VEC
:
13928 /* CC0 must die in the insn after it is set, so we don't need to take
13929 special note of it here. */
13934 /* If we are clobbering a MEM, mark any hard registers inside the
13935 address as used. */
13936 if (MEM_P (XEXP (x
, 0)))
13937 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13942 /* A hard reg in a wide mode may really be multiple registers.
13943 If so, mark all of them just like the first. */
13944 if (regno
< FIRST_PSEUDO_REGISTER
)
13946 /* None of this applies to the stack, frame or arg pointers. */
13947 if (regno
== STACK_POINTER_REGNUM
13948 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13949 && regno
== HARD_FRAME_POINTER_REGNUM
)
13950 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13951 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13952 || regno
== FRAME_POINTER_REGNUM
)
13955 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13961 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13963 rtx testreg
= SET_DEST (x
);
13965 while (GET_CODE (testreg
) == SUBREG
13966 || GET_CODE (testreg
) == ZERO_EXTRACT
13967 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13968 testreg
= XEXP (testreg
, 0);
13970 if (MEM_P (testreg
))
13971 mark_used_regs_combine (XEXP (testreg
, 0));
13973 mark_used_regs_combine (SET_SRC (x
));
13981 /* Recursively scan the operands of this expression. */
13984 const char *fmt
= GET_RTX_FORMAT (code
);
13986 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13989 mark_used_regs_combine (XEXP (x
, i
));
13990 else if (fmt
[i
] == 'E')
13994 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13995 mark_used_regs_combine (XVECEXP (x
, i
, j
));
14001 /* Remove register number REGNO from the dead registers list of INSN.
14003 Return the note used to record the death, if there was one. */
14006 remove_death (unsigned int regno
, rtx_insn
*insn
)
14008 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
14011 remove_note (insn
, note
);
14016 /* For each register (hardware or pseudo) used within expression X, if its
14017 death is in an instruction with luid between FROM_LUID (inclusive) and
14018 TO_INSN (exclusive), put a REG_DEAD note for that register in the
14019 list headed by PNOTES.
14021 That said, don't move registers killed by maybe_kill_insn.
14023 This is done when X is being merged by combination into TO_INSN. These
14024 notes will then be distributed as needed. */
14027 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
14032 enum rtx_code code
= GET_CODE (x
);
14036 unsigned int regno
= REGNO (x
);
14037 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
14039 /* If we do not know where the register died, it may still die between
14040 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14041 if (!where_dead
|| DF_INSN_LUID (where_dead
) >= DF_INSN_LUID (to_insn
))
14043 rtx_insn
*insn
= prev_real_nondebug_insn (to_insn
);
14045 && BLOCK_FOR_INSN (insn
) == BLOCK_FOR_INSN (to_insn
)
14046 && DF_INSN_LUID (insn
) >= from_luid
)
14048 if (dead_or_set_regno_p (insn
, regno
))
14050 if (find_regno_note (insn
, REG_DEAD
, regno
))
14055 insn
= prev_real_nondebug_insn (insn
);
14059 /* Don't move the register if it gets killed in between from and to. */
14060 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
14061 && ! reg_referenced_p (x
, maybe_kill_insn
))
14065 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
14066 && DF_INSN_LUID (where_dead
) >= from_luid
14067 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
14069 rtx note
= remove_death (regno
, where_dead
);
14071 /* It is possible for the call above to return 0. This can occur
14072 when last_death points to I2 or I1 that we combined with.
14073 In that case make a new note.
14075 We must also check for the case where X is a hard register
14076 and NOTE is a death note for a range of hard registers
14077 including X. In that case, we must put REG_DEAD notes for
14078 the remaining registers in place of NOTE. */
14080 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
14081 && partial_subreg_p (GET_MODE (x
), GET_MODE (XEXP (note
, 0))))
14083 unsigned int deadregno
= REGNO (XEXP (note
, 0));
14084 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
14085 unsigned int ourend
= END_REGNO (x
);
14088 for (i
= deadregno
; i
< deadend
; i
++)
14089 if (i
< regno
|| i
>= ourend
)
14090 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
14093 /* If we didn't find any note, or if we found a REG_DEAD note that
14094 covers only part of the given reg, and we have a multi-reg hard
14095 register, then to be safe we must check for REG_DEAD notes
14096 for each register other than the first. They could have
14097 their own REG_DEAD notes lying around. */
14098 else if ((note
== 0
14100 && partial_subreg_p (GET_MODE (XEXP (note
, 0)),
14102 && regno
< FIRST_PSEUDO_REGISTER
14103 && REG_NREGS (x
) > 1)
14105 unsigned int ourend
= END_REGNO (x
);
14106 unsigned int i
, offset
;
14110 offset
= hard_regno_nregs (regno
, GET_MODE (XEXP (note
, 0)));
14114 for (i
= regno
+ offset
; i
< ourend
; i
++)
14115 move_deaths (regno_reg_rtx
[i
],
14116 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
14119 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
14121 XEXP (note
, 1) = *pnotes
;
14125 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
14131 else if (GET_CODE (x
) == SET
)
14133 rtx dest
= SET_DEST (x
);
14135 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14137 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14138 that accesses one word of a multi-word item, some
14139 piece of everything register in the expression is used by
14140 this insn, so remove any old death. */
14141 /* ??? So why do we test for equality of the sizes? */
14143 if (GET_CODE (dest
) == ZERO_EXTRACT
14144 || GET_CODE (dest
) == STRICT_LOW_PART
14145 || (GET_CODE (dest
) == SUBREG
14146 && !read_modify_subreg_p (dest
)))
14148 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14152 /* If this is some other SUBREG, we know it replaces the entire
14153 value, so use that as the destination. */
14154 if (GET_CODE (dest
) == SUBREG
)
14155 dest
= SUBREG_REG (dest
);
14157 /* If this is a MEM, adjust deaths of anything used in the address.
14158 For a REG (the only other possibility), the entire value is
14159 being replaced so the old value is not used in this insn. */
14162 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
14167 else if (GET_CODE (x
) == CLOBBER
)
14170 len
= GET_RTX_LENGTH (code
);
14171 fmt
= GET_RTX_FORMAT (code
);
14173 for (i
= 0; i
< len
; i
++)
14178 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
14179 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
14182 else if (fmt
[i
] == 'e')
14183 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14187 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14188 pattern of an insn. X must be a REG. */
14191 reg_bitfield_target_p (rtx x
, rtx body
)
14195 if (GET_CODE (body
) == SET
)
14197 rtx dest
= SET_DEST (body
);
14199 unsigned int regno
, tregno
, endregno
, endtregno
;
14201 if (GET_CODE (dest
) == ZERO_EXTRACT
)
14202 target
= XEXP (dest
, 0);
14203 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
14204 target
= SUBREG_REG (XEXP (dest
, 0));
14208 if (GET_CODE (target
) == SUBREG
)
14209 target
= SUBREG_REG (target
);
14211 if (!REG_P (target
))
14214 tregno
= REGNO (target
), regno
= REGNO (x
);
14215 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
14216 return target
== x
;
14218 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
14219 endregno
= end_hard_regno (GET_MODE (x
), regno
);
14221 return endregno
> tregno
&& regno
< endtregno
;
14224 else if (GET_CODE (body
) == PARALLEL
)
14225 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
14226 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
14232 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14233 as appropriate. I3 and I2 are the insns resulting from the combination
14234 insns including FROM (I2 may be zero).
14236 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14237 not need REG_DEAD notes because they are being substituted for. This
14238 saves searching in the most common cases.
14240 Each note in the list is either ignored or placed on some insns, depending
14241 on the type of note. */
14244 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
14245 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
14247 rtx note
, next_note
;
14249 rtx_insn
*tem_insn
;
14251 for (note
= notes
; note
; note
= next_note
)
14253 rtx_insn
*place
= 0, *place2
= 0;
14255 next_note
= XEXP (note
, 1);
14256 switch (REG_NOTE_KIND (note
))
14260 /* Doesn't matter much where we put this, as long as it's somewhere.
14261 It is preferable to keep these notes on branches, which is most
14262 likely to be i3. */
14266 case REG_NON_LOCAL_GOTO
:
14271 gcc_assert (i2
&& JUMP_P (i2
));
14276 case REG_EH_REGION
:
14277 /* These notes must remain with the call or trapping instruction. */
14280 else if (i2
&& CALL_P (i2
))
14284 gcc_assert (cfun
->can_throw_non_call_exceptions
);
14285 if (may_trap_p (i3
))
14287 else if (i2
&& may_trap_p (i2
))
14289 /* ??? Otherwise assume we've combined things such that we
14290 can now prove that the instructions can't trap. Drop the
14291 note in this case. */
14295 case REG_ARGS_SIZE
:
14296 /* ??? How to distribute between i3-i1. Assume i3 contains the
14297 entire adjustment. Assert i3 contains at least some adjust. */
14298 if (!noop_move_p (i3
))
14300 poly_int64 old_size
, args_size
= get_args_size (note
);
14301 /* fixup_args_size_notes looks at REG_NORETURN note,
14302 so ensure the note is placed there first. */
14306 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14307 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14311 XEXP (n
, 1) = REG_NOTES (i3
);
14312 REG_NOTES (i3
) = n
;
14316 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14317 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14318 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14319 gcc_assert (maybe_ne (old_size
, args_size
)
14321 && !ACCUMULATE_OUTGOING_ARGS
14322 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14329 case REG_CALL_DECL
:
14330 case REG_CALL_NOCF_CHECK
:
14331 /* These notes must remain with the call. It should not be
14332 possible for both I2 and I3 to be a call. */
14337 gcc_assert (i2
&& CALL_P (i2
));
14343 /* Any clobbers for i3 may still exist, and so we must process
14344 REG_UNUSED notes from that insn.
14346 Any clobbers from i2 or i1 can only exist if they were added by
14347 recog_for_combine. In that case, recog_for_combine created the
14348 necessary REG_UNUSED notes. Trying to keep any original
14349 REG_UNUSED notes from these insns can cause incorrect output
14350 if it is for the same register as the original i3 dest.
14351 In that case, we will notice that the register is set in i3,
14352 and then add a REG_UNUSED note for the destination of i3, which
14353 is wrong. However, it is possible to have REG_UNUSED notes from
14354 i2 or i1 for register which were both used and clobbered, so
14355 we keep notes from i2 or i1 if they will turn into REG_DEAD
14358 /* If this register is set or clobbered in I3, put the note there
14359 unless there is one already. */
14360 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14362 if (from_insn
!= i3
)
14365 if (! (REG_P (XEXP (note
, 0))
14366 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14367 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14370 /* Otherwise, if this register is used by I3, then this register
14371 now dies here, so we must put a REG_DEAD note here unless there
14373 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14374 && ! (REG_P (XEXP (note
, 0))
14375 ? find_regno_note (i3
, REG_DEAD
,
14376 REGNO (XEXP (note
, 0)))
14377 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14379 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14383 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14384 but we can't tell which at this point. We must reset any
14385 expectations we had about the value that was previously
14386 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14387 and, if appropriate, restore its previous value, but we
14388 don't have enough information for that at this point. */
14391 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14393 /* Otherwise, if this register is now referenced in i2
14394 then the register used to be modified in one of the
14395 original insns. If it was i3 (say, in an unused
14396 parallel), it's now completely gone, so the note can
14397 be discarded. But if it was modified in i2, i1 or i0
14398 and we still reference it in i2, then we're
14399 referencing the previous value, and since the
14400 register was modified and REG_UNUSED, we know that
14401 the previous value is now dead. So, if we only
14402 reference the register in i2, we change the note to
14403 REG_DEAD, to reflect the previous value. However, if
14404 we're also setting or clobbering the register as
14405 scratch, we know (because the register was not
14406 referenced in i3) that it's unused, just as it was
14407 unused before, and we place the note in i2. */
14408 if (from_insn
!= i3
&& i2
&& INSN_P (i2
)
14409 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14411 if (!reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14412 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14413 if (! (REG_P (XEXP (note
, 0))
14414 ? find_regno_note (i2
, REG_NOTE_KIND (note
),
14415 REGNO (XEXP (note
, 0)))
14416 : find_reg_note (i2
, REG_NOTE_KIND (note
),
14427 /* These notes say something about results of an insn. We can
14428 only support them if they used to be on I3 in which case they
14429 remain on I3. Otherwise they are ignored.
14431 If the note refers to an expression that is not a constant, we
14432 must also ignore the note since we cannot tell whether the
14433 equivalence is still true. It might be possible to do
14434 slightly better than this (we only have a problem if I2DEST
14435 or I1DEST is present in the expression), but it doesn't
14436 seem worth the trouble. */
14438 if (from_insn
== i3
14439 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14444 /* These notes say something about how a register is used. They must
14445 be present on any use of the register in I2 or I3. */
14446 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14449 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14458 case REG_LABEL_TARGET
:
14459 case REG_LABEL_OPERAND
:
14460 /* This can show up in several ways -- either directly in the
14461 pattern, or hidden off in the constant pool with (or without?)
14462 a REG_EQUAL note. */
14463 /* ??? Ignore the without-reg_equal-note problem for now. */
14464 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14465 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14466 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14467 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14471 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14472 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14473 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14474 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14482 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14483 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14485 if (place
&& JUMP_P (place
)
14486 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14487 && (JUMP_LABEL (place
) == NULL
14488 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14490 rtx label
= JUMP_LABEL (place
);
14493 JUMP_LABEL (place
) = XEXP (note
, 0);
14494 else if (LABEL_P (label
))
14495 LABEL_NUSES (label
)--;
14498 if (place2
&& JUMP_P (place2
)
14499 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14500 && (JUMP_LABEL (place2
) == NULL
14501 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14503 rtx label
= JUMP_LABEL (place2
);
14506 JUMP_LABEL (place2
) = XEXP (note
, 0);
14507 else if (LABEL_P (label
))
14508 LABEL_NUSES (label
)--;
14514 /* This note says something about the value of a register prior
14515 to the execution of an insn. It is too much trouble to see
14516 if the note is still correct in all situations. It is better
14517 to simply delete it. */
14521 /* If we replaced the right hand side of FROM_INSN with a
14522 REG_EQUAL note, the original use of the dying register
14523 will not have been combined into I3 and I2. In such cases,
14524 FROM_INSN is guaranteed to be the first of the combined
14525 instructions, so we simply need to search back before
14526 FROM_INSN for the previous use or set of this register,
14527 then alter the notes there appropriately.
14529 If the register is used as an input in I3, it dies there.
14530 Similarly for I2, if it is nonzero and adjacent to I3.
14532 If the register is not used as an input in either I3 or I2
14533 and it is not one of the registers we were supposed to eliminate,
14534 there are two possibilities. We might have a non-adjacent I2
14535 or we might have somehow eliminated an additional register
14536 from a computation. For example, we might have had A & B where
14537 we discover that B will always be zero. In this case we will
14538 eliminate the reference to A.
14540 In both cases, we must search to see if we can find a previous
14541 use of A and put the death note there. */
14544 && from_insn
== i2mod
14545 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14546 tem_insn
= from_insn
;
14550 && CALL_P (from_insn
)
14551 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14553 else if (i2
&& reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14555 /* If the new I2 sets the same register that is marked
14556 dead in the note, we do not in general know where to
14557 put the note. One important case we _can_ handle is
14558 when the note comes from I3. */
14559 if (from_insn
== i3
)
14564 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14566 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14567 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14569 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14571 && reg_overlap_mentioned_p (XEXP (note
, 0),
14573 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14574 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14581 basic_block bb
= this_basic_block
;
14583 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14585 if (!NONDEBUG_INSN_P (tem_insn
))
14587 if (tem_insn
== BB_HEAD (bb
))
14592 /* If the register is being set at TEM_INSN, see if that is all
14593 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14594 into a REG_UNUSED note instead. Don't delete sets to
14595 global register vars. */
14596 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14597 || !global_regs
[REGNO (XEXP (note
, 0))])
14598 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14600 rtx set
= single_set (tem_insn
);
14601 rtx inner_dest
= 0;
14602 rtx_insn
*cc0_setter
= NULL
;
14605 for (inner_dest
= SET_DEST (set
);
14606 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14607 || GET_CODE (inner_dest
) == SUBREG
14608 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14609 inner_dest
= XEXP (inner_dest
, 0))
14612 /* Verify that it was the set, and not a clobber that
14613 modified the register.
14615 CC0 targets must be careful to maintain setter/user
14616 pairs. If we cannot delete the setter due to side
14617 effects, mark the user with an UNUSED note instead
14620 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14621 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14623 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14624 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14625 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14627 /* Move the notes and links of TEM_INSN elsewhere.
14628 This might delete other dead insns recursively.
14629 First set the pattern to something that won't use
14631 rtx old_notes
= REG_NOTES (tem_insn
);
14633 PATTERN (tem_insn
) = pc_rtx
;
14634 REG_NOTES (tem_insn
) = NULL
;
14636 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14637 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14638 distribute_links (LOG_LINKS (tem_insn
));
14640 unsigned int regno
= REGNO (XEXP (note
, 0));
14641 reg_stat_type
*rsp
= ®_stat
[regno
];
14642 if (rsp
->last_set
== tem_insn
)
14643 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14645 SET_INSN_DELETED (tem_insn
);
14646 if (tem_insn
== i2
)
14649 /* Delete the setter too. */
14652 PATTERN (cc0_setter
) = pc_rtx
;
14653 old_notes
= REG_NOTES (cc0_setter
);
14654 REG_NOTES (cc0_setter
) = NULL
;
14656 distribute_notes (old_notes
, cc0_setter
,
14658 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14659 distribute_links (LOG_LINKS (cc0_setter
));
14661 SET_INSN_DELETED (cc0_setter
);
14662 if (cc0_setter
== i2
)
14668 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14670 /* If there isn't already a REG_UNUSED note, put one
14671 here. Do not place a REG_DEAD note, even if
14672 the register is also used here; that would not
14673 match the algorithm used in lifetime analysis
14674 and can cause the consistency check in the
14675 scheduler to fail. */
14676 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14677 REGNO (XEXP (note
, 0))))
14682 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14683 || (CALL_P (tem_insn
)
14684 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14688 /* If we are doing a 3->2 combination, and we have a
14689 register which formerly died in i3 and was not used
14690 by i2, which now no longer dies in i3 and is used in
14691 i2 but does not die in i2, and place is between i2
14692 and i3, then we may need to move a link from place to
14694 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14696 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14697 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14699 struct insn_link
*links
= LOG_LINKS (place
);
14700 LOG_LINKS (place
) = NULL
;
14701 distribute_links (links
);
14706 if (tem_insn
== BB_HEAD (bb
))
14712 /* If the register is set or already dead at PLACE, we needn't do
14713 anything with this note if it is still a REG_DEAD note.
14714 We check here if it is set at all, not if is it totally replaced,
14715 which is what `dead_or_set_p' checks, so also check for it being
14718 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14720 unsigned int regno
= REGNO (XEXP (note
, 0));
14721 reg_stat_type
*rsp
= ®_stat
[regno
];
14723 if (dead_or_set_p (place
, XEXP (note
, 0))
14724 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14726 /* Unless the register previously died in PLACE, clear
14727 last_death. [I no longer understand why this is
14729 if (rsp
->last_death
!= place
)
14730 rsp
->last_death
= 0;
14734 rsp
->last_death
= place
;
14736 /* If this is a death note for a hard reg that is occupying
14737 multiple registers, ensure that we are still using all
14738 parts of the object. If we find a piece of the object
14739 that is unused, we must arrange for an appropriate REG_DEAD
14740 note to be added for it. However, we can't just emit a USE
14741 and tag the note to it, since the register might actually
14742 be dead; so we recourse, and the recursive call then finds
14743 the previous insn that used this register. */
14745 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14747 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14748 bool all_used
= true;
14751 for (i
= regno
; i
< endregno
; i
++)
14752 if ((! refers_to_regno_p (i
, PATTERN (place
))
14753 && ! find_regno_fusage (place
, USE
, i
))
14754 || dead_or_set_regno_p (place
, i
))
14762 /* Put only REG_DEAD notes for pieces that are
14763 not already dead or set. */
14765 for (i
= regno
; i
< endregno
;
14766 i
+= hard_regno_nregs (i
, reg_raw_mode
[i
]))
14768 rtx piece
= regno_reg_rtx
[i
];
14769 basic_block bb
= this_basic_block
;
14771 if (! dead_or_set_p (place
, piece
)
14772 && ! reg_bitfield_target_p (piece
,
14775 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14778 distribute_notes (new_note
, place
, place
,
14779 NULL
, NULL_RTX
, NULL_RTX
,
14782 else if (! refers_to_regno_p (i
, PATTERN (place
))
14783 && ! find_regno_fusage (place
, USE
, i
))
14784 for (tem_insn
= PREV_INSN (place
); ;
14785 tem_insn
= PREV_INSN (tem_insn
))
14787 if (!NONDEBUG_INSN_P (tem_insn
))
14789 if (tem_insn
== BB_HEAD (bb
))
14793 if (dead_or_set_p (tem_insn
, piece
)
14794 || reg_bitfield_target_p (piece
,
14795 PATTERN (tem_insn
)))
14797 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14810 /* Any other notes should not be present at this point in the
14812 gcc_unreachable ();
14817 XEXP (note
, 1) = REG_NOTES (place
);
14818 REG_NOTES (place
) = note
;
14820 /* Set added_notes_insn to the earliest insn we added a note to. */
14821 if (added_notes_insn
== 0
14822 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place
))
14823 added_notes_insn
= place
;
14828 add_shallow_copy_of_reg_note (place2
, note
);
14830 /* Set added_notes_insn to the earliest insn we added a note to. */
14831 if (added_notes_insn
== 0
14832 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place2
))
14833 added_notes_insn
= place2
;
14838 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14839 I3, I2, and I1 to new locations. This is also called to add a link
14840 pointing at I3 when I3's destination is changed. */
14843 distribute_links (struct insn_link
*links
)
14845 struct insn_link
*link
, *next_link
;
14847 for (link
= links
; link
; link
= next_link
)
14849 rtx_insn
*place
= 0;
14853 next_link
= link
->next
;
14855 /* If the insn that this link points to is a NOTE, ignore it. */
14856 if (NOTE_P (link
->insn
))
14860 rtx pat
= PATTERN (link
->insn
);
14861 if (GET_CODE (pat
) == SET
)
14863 else if (GET_CODE (pat
) == PARALLEL
)
14866 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14868 set
= XVECEXP (pat
, 0, i
);
14869 if (GET_CODE (set
) != SET
)
14872 reg
= SET_DEST (set
);
14873 while (GET_CODE (reg
) == ZERO_EXTRACT
14874 || GET_CODE (reg
) == STRICT_LOW_PART
14875 || GET_CODE (reg
) == SUBREG
)
14876 reg
= XEXP (reg
, 0);
14881 if (REGNO (reg
) == link
->regno
)
14884 if (i
== XVECLEN (pat
, 0))
14890 reg
= SET_DEST (set
);
14892 while (GET_CODE (reg
) == ZERO_EXTRACT
14893 || GET_CODE (reg
) == STRICT_LOW_PART
14894 || GET_CODE (reg
) == SUBREG
)
14895 reg
= XEXP (reg
, 0);
14900 /* A LOG_LINK is defined as being placed on the first insn that uses
14901 a register and points to the insn that sets the register. Start
14902 searching at the next insn after the target of the link and stop
14903 when we reach a set of the register or the end of the basic block.
14905 Note that this correctly handles the link that used to point from
14906 I3 to I2. Also note that not much searching is typically done here
14907 since most links don't point very far away. */
14909 for (insn
= NEXT_INSN (link
->insn
);
14910 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14911 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14912 insn
= NEXT_INSN (insn
))
14913 if (DEBUG_INSN_P (insn
))
14915 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14917 if (reg_referenced_p (reg
, PATTERN (insn
)))
14921 else if (CALL_P (insn
)
14922 && find_reg_fusage (insn
, USE
, reg
))
14927 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14930 /* If we found a place to put the link, place it there unless there
14931 is already a link to the same insn as LINK at that point. */
14935 struct insn_link
*link2
;
14937 FOR_EACH_LOG_LINK (link2
, place
)
14938 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14943 link
->next
= LOG_LINKS (place
);
14944 LOG_LINKS (place
) = link
;
14946 /* Set added_links_insn to the earliest insn we added a
14948 if (added_links_insn
== 0
14949 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14950 added_links_insn
= place
;
14956 /* Check for any register or memory mentioned in EQUIV that is not
14957 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14958 of EXPR where some registers may have been replaced by constants. */
14961 unmentioned_reg_p (rtx equiv
, rtx expr
)
14963 subrtx_iterator::array_type array
;
14964 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14966 const_rtx x
= *iter
;
14967 if ((REG_P (x
) || MEM_P (x
))
14968 && !reg_mentioned_p (x
, expr
))
14974 DEBUG_FUNCTION
void
14975 dump_combine_stats (FILE *file
)
14979 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14980 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14984 dump_combine_total_stats (FILE *file
)
14988 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14989 total_attempts
, total_merges
, total_extras
, total_successes
);
14992 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
14993 the reg-to-reg copy can usefully combine with later instructions, but we
14994 do not want to combine the hard reg into later instructions, for that
14995 restricts register allocation. */
14997 make_more_copies (void)
15001 FOR_EACH_BB_FN (bb
, cfun
)
15005 FOR_BB_INSNS (bb
, insn
)
15007 if (!NONDEBUG_INSN_P (insn
))
15010 rtx set
= single_set (insn
);
15014 rtx dest
= SET_DEST (set
);
15015 if (!(REG_P (dest
) && !HARD_REGISTER_P (dest
)))
15018 rtx src
= SET_SRC (set
);
15019 if (!(REG_P (src
) && HARD_REGISTER_P (src
)))
15021 if (TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
)))
15024 rtx new_reg
= gen_reg_rtx (GET_MODE (dest
));
15025 rtx_insn
*new_insn
= gen_move_insn (new_reg
, src
);
15026 SET_SRC (set
) = new_reg
;
15027 emit_insn_before (new_insn
, insn
);
15028 df_insn_rescan (insn
);
15033 /* Try combining insns through substitution. */
15034 static unsigned int
15035 rest_of_handle_combine (void)
15037 make_more_copies ();
15039 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
15040 df_note_add_problem ();
15043 regstat_init_n_sets_and_refs ();
15044 reg_n_sets_max
= max_reg_num ();
15046 int rebuild_jump_labels_after_combine
15047 = combine_instructions (get_insns (), max_reg_num ());
15049 /* Combining insns may have turned an indirect jump into a
15050 direct jump. Rebuild the JUMP_LABEL fields of jumping
15052 if (rebuild_jump_labels_after_combine
)
15054 if (dom_info_available_p (CDI_DOMINATORS
))
15055 free_dominance_info (CDI_DOMINATORS
);
15056 timevar_push (TV_JUMP
);
15057 rebuild_jump_labels (get_insns ());
15059 timevar_pop (TV_JUMP
);
15062 regstat_free_n_sets_and_refs ();
15068 const pass_data pass_data_combine
=
15070 RTL_PASS
, /* type */
15071 "combine", /* name */
15072 OPTGROUP_NONE
, /* optinfo_flags */
15073 TV_COMBINE
, /* tv_id */
15074 PROP_cfglayout
, /* properties_required */
15075 0, /* properties_provided */
15076 0, /* properties_destroyed */
15077 0, /* todo_flags_start */
15078 TODO_df_finish
, /* todo_flags_finish */
15081 class pass_combine
: public rtl_opt_pass
15084 pass_combine (gcc::context
*ctxt
)
15085 : rtl_opt_pass (pass_data_combine
, ctxt
)
15088 /* opt_pass methods: */
15089 virtual bool gate (function
*) { return (optimize
> 0); }
15090 virtual unsigned int execute (function
*)
15092 return rest_of_handle_combine ();
15095 }; // class pass_combine
15097 } // anon namespace
15100 make_pass_combine (gcc::context
*ctxt
)
15102 return new pass_combine (ctxt
);