1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts
;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges
;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras
;
121 /* Number of instructions combined in this function. */
123 static int combine_successes
;
125 /* Totals over entire compilation. */
127 static int total_attempts
, total_merges
, total_extras
, total_successes
;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs
;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs
;
146 typedef struct reg_stat_struct
{
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label
;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 DEF_VEC_O(reg_stat_type
);
256 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
258 static VEC(reg_stat_type
,heap
) *reg_stat
;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set
;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid
;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn
;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid
;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs
;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn
;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block
;
300 static bool optimize_this_for_speed_p
;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known
;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost
;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx
*uid_log_links
;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick
;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start
;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode
;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid
;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
};
351 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
352 union { rtx
*r
; int *i
; } where
;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf
;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences
;
375 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
377 unsigned HOST_WIDE_INT
,
378 unsigned HOST_WIDE_INT
*);
379 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx
*, rtx
);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx
);
386 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
387 static int cant_combine_insn_p (rtx
);
388 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
389 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
390 static int contains_muldiv (rtx
);
391 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx
*find_split_point (rtx
*, rtx
);
395 static rtx
subst (rtx
, rtx
, rtx
, int, int);
396 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
397 static rtx
simplify_if_then_else (rtx
);
398 static rtx
simplify_set (rtx
);
399 static rtx
simplify_logical (rtx
);
400 static rtx
expand_compound_operation (rtx
);
401 static const_rtx
expand_field_assignment (const_rtx
);
402 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
403 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
404 static rtx
extract_left_shift (rtx
, int);
405 static rtx
make_compound_operation (rtx
, enum rtx_code
);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
407 unsigned HOST_WIDE_INT
*);
408 static rtx
canon_reg_for_combine (rtx
, rtx
);
409 static rtx
force_to_mode (rtx
, enum machine_mode
,
410 unsigned HOST_WIDE_INT
, int);
411 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
412 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
413 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
414 static rtx
make_field_assignment (rtx
);
415 static rtx
apply_distributive_law (rtx
);
416 static rtx
distribute_and_simplify_rtx (rtx
, int);
417 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
418 unsigned HOST_WIDE_INT
);
419 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
420 unsigned HOST_WIDE_INT
);
421 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
422 HOST_WIDE_INT
, enum machine_mode
, int *);
423 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
424 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
426 static int recog_for_combine (rtx
*, rtx
, rtx
*);
427 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
428 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
429 static void update_table_tick (rtx
);
430 static void record_value_for_reg (rtx
, rtx
, rtx
);
431 static void check_promoted_subreg (rtx
, rtx
);
432 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
433 static void record_dead_and_set_regs (rtx
);
434 static int get_last_value_validate (rtx
*, rtx
, int, int);
435 static rtx
get_last_value (const_rtx
);
436 static int use_crosses_set_p (const_rtx
, int);
437 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
438 static int reg_dead_at_p (rtx
, rtx
);
439 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
440 static int reg_bitfield_target_p (rtx
, rtx
);
441 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
442 static void distribute_links (rtx
);
443 static void mark_used_regs_combine (rtx
);
444 static void record_promoted_value (rtx
, rtx
);
445 static int unmentioned_reg_p_1 (rtx
*, void *);
446 static bool unmentioned_reg_p (rtx
, rtx
);
447 static int record_truncated_value (rtx
*, void *);
448 static void record_truncated_values (rtx
*, void *);
449 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
450 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern
, rtx insn
)
486 ret
= split_insns (pattern
, insn
);
487 nregs
= max_reg_num ();
488 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
489 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest
, rtx
*loc
)
503 enum rtx_code code
= GET_CODE (x
);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x
)) != CC0
526 && GET_CODE (SET_DEST (x
)) != PC
527 && !REG_P (SET_DEST (x
))
528 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x
)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
531 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
533 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
536 return find_single_use_1 (dest
, &SET_SRC (x
));
540 return find_single_use_1 (dest
, &XEXP (x
, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt
= GET_RTX_FORMAT (code
);
550 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
554 if (dest
== XEXP (x
, i
)
555 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
556 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
559 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
562 result
= this_result
;
563 else if (this_result
)
564 /* Duplicate usage. */
567 else if (fmt
[i
] == 'E')
571 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
573 if (XVECEXP (x
, i
, j
) == dest
575 && REG_P (XVECEXP (x
, i
, j
))
576 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
579 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
582 result
= this_result
;
583 else if (this_result
)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
618 next
= NEXT_INSN (insn
);
620 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
623 result
= find_single_use_1 (dest
, &PATTERN (next
));
633 bb
= BLOCK_FOR_INSN (insn
);
634 for (next
= NEXT_INSN (insn
);
635 next
&& BLOCK_FOR_INSN (next
) == bb
;
636 next
= NEXT_INSN (next
))
637 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
639 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
640 if (XEXP (link
, 0) == insn
)
645 result
= find_single_use_1 (dest
, &PATTERN (next
));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx
*into
, rtx newval
)
667 if (oldval
== newval
)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
676 && CONST_INT_P (newval
))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval
)
681 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval
) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval
))));
691 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval
, 0))));
696 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
698 buf
= XNEW (struct undo
);
700 buf
->kind
= UNDO_RTX
;
702 buf
->old_contents
.r
= oldval
;
705 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into
, int newval
)
720 if (oldval
== newval
)
724 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
726 buf
= XNEW (struct undo
);
728 buf
->kind
= UNDO_INT
;
730 buf
->old_contents
.i
= oldval
;
733 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
747 enum machine_mode oldval
= GET_MODE (*into
);
749 if (oldval
== newval
)
753 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
755 buf
= XNEW (struct undo
);
757 buf
->kind
= UNDO_MODE
;
759 buf
->old_contents
.m
= oldval
;
760 adjust_reg_mode (*into
, newval
);
762 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
,
780 int i1_cost
, i2_cost
, i3_cost
;
781 int new_i2_cost
, new_i3_cost
;
782 int old_cost
, new_cost
;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost
= INSN_COST (i2
);
786 i3_cost
= INSN_COST (i3
);
790 i1_cost
= INSN_COST (i1
);
791 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
792 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
796 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
804 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
805 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
806 ? new_i2_cost
+ new_i3_cost
: 0;
810 new_cost
= new_i3_cost
;
814 if (undobuf
.other_insn
)
816 int old_other_cost
, new_other_cost
;
818 old_other_cost
= INSN_COST (undobuf
.other_insn
);
819 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
820 if (old_other_cost
> 0 && new_other_cost
> 0)
822 old_cost
+= old_other_cost
;
823 new_cost
+= new_other_cost
;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost
> old_cost
)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
841 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
842 i1_cost
, i2_cost
, i3_cost
, old_cost
);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2
), INSN_UID (i3
));
849 fprintf (dump_file
, "original costs %d + %d = %d\n",
850 i2_cost
, i3_cost
, old_cost
);
855 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
856 new_i2_cost
, new_i3_cost
, new_cost
);
859 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2
) = new_i2_cost
;
867 INSN_COST (i3
) = new_i3_cost
;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
887 next
= NEXT_INSN (insn
);
888 if (INSN_P (insn
) && noop_move_p (insn
))
891 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
893 delete_insn_and_edges (insn
);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref
*def_vec
, *use_vec
;
909 next_use
= XCNEWVEC (rtx
, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb
, insn
)
924 if (!NONDEBUG_INSN_P (insn
))
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn
));
930 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
932 df_ref def
= *def_vec
;
933 int regno
= DF_REF_REGNO (def
);
936 if (!next_use
[regno
])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
943 /* Do not make the log link for frame pointer. */
944 if ((regno
== FRAME_POINTER_REGNUM
945 && (! reload_completed
|| frame_pointer_needed
))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno
== HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed
|| frame_pointer_needed
))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
956 use_insn
= next_use
[regno
];
957 if (BLOCK_FOR_INSN (use_insn
) == bb
)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno
>= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn
)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links
= LOG_LINKS (use_insn
); links
;
972 links
= XEXP (links
, 1))
973 if (insn
== XEXP (links
, 0))
977 LOG_LINKS (use_insn
) =
978 alloc_INSN_LIST (insn
, LOG_LINKS (use_insn
));
981 next_use
[regno
] = NULL_RTX
;
984 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
986 df_ref use
= *use_vec
;
987 int regno
= DF_REF_REGNO (use
);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
994 next_use
[regno
] = insn
;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1011 free_INSN_LIST_list (&LOG_LINKS (insn
));
1014 /* Main entry point for combiner. F is the first insn of the function.
1015 NREGS is the first unused pseudo-reg number.
1017 Return nonzero if the combiner has turned an indirect jump
1018 instruction into a direct jump. */
1020 combine_instructions (rtx f
, unsigned int nregs
)
1026 rtx links
, nextlinks
;
1028 basic_block last_bb
;
1030 int new_direct_jump_p
= 0;
1032 for (first
= f
; first
&& !INSN_P (first
); )
1033 first
= NEXT_INSN (first
);
1037 combine_attempts
= 0;
1040 combine_successes
= 0;
1042 rtl_hooks
= combine_rtl_hooks
;
1044 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1046 init_recog_no_volatile ();
1048 /* Allocate array for insn info. */
1049 max_uid_known
= get_max_uid ();
1050 uid_log_links
= XCNEWVEC (rtx
, max_uid_known
+ 1);
1051 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1053 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1055 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1056 problems when, for example, we have j <<= 1 in a loop. */
1058 nonzero_sign_valid
= 0;
1059 label_tick
= label_tick_ebb_start
= 1;
1061 /* Scan all SETs and see if we can deduce anything about what
1062 bits are known to be zero for some registers and how many copies
1063 of the sign bit are known to exist for those registers.
1065 Also set any known values so that we can use it while searching
1066 for what bits are known to be set. */
1068 setup_incoming_promotions (first
);
1069 /* Allow the entry block and the first block to fall into the same EBB.
1070 Conceptually the incoming promotions are assigned to the entry block. */
1071 last_bb
= ENTRY_BLOCK_PTR
;
1073 create_log_links ();
1074 FOR_EACH_BB (this_basic_block
)
1076 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1081 if (!single_pred_p (this_basic_block
)
1082 || single_pred (this_basic_block
) != last_bb
)
1083 label_tick_ebb_start
= label_tick
;
1084 last_bb
= this_basic_block
;
1086 FOR_BB_INSNS (this_basic_block
, insn
)
1087 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1089 subst_low_luid
= DF_INSN_LUID (insn
);
1092 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1094 record_dead_and_set_regs (insn
);
1097 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1098 if (REG_NOTE_KIND (links
) == REG_INC
)
1099 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1103 /* Record the current insn_rtx_cost of this instruction. */
1104 if (NONJUMP_INSN_P (insn
))
1105 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1106 optimize_this_for_speed_p
);
1108 fprintf(dump_file
, "insn_cost %d: %d\n",
1109 INSN_UID (insn
), INSN_COST (insn
));
1113 nonzero_sign_valid
= 1;
1115 /* Now scan all the insns in forward order. */
1116 label_tick
= label_tick_ebb_start
= 1;
1118 setup_incoming_promotions (first
);
1119 last_bb
= ENTRY_BLOCK_PTR
;
1121 FOR_EACH_BB (this_basic_block
)
1123 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1128 if (!single_pred_p (this_basic_block
)
1129 || single_pred (this_basic_block
) != last_bb
)
1130 label_tick_ebb_start
= label_tick
;
1131 last_bb
= this_basic_block
;
1133 rtl_profile_for_bb (this_basic_block
);
1134 for (insn
= BB_HEAD (this_basic_block
);
1135 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1136 insn
= next
? next
: NEXT_INSN (insn
))
1139 if (NONDEBUG_INSN_P (insn
))
1141 /* See if we know about function return values before this
1142 insn based upon SUBREG flags. */
1143 check_promoted_subreg (insn
, PATTERN (insn
));
1145 /* See if we can find hardregs and subreg of pseudos in
1146 narrower modes. This could help turning TRUNCATEs
1148 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1150 /* Try this insn with each insn it links back to. */
1152 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1153 if ((next
= try_combine (insn
, XEXP (links
, 0),
1154 NULL_RTX
, &new_direct_jump_p
)) != 0)
1157 /* Try each sequence of three linked insns ending with this one. */
1159 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1161 rtx link
= XEXP (links
, 0);
1163 /* If the linked insn has been replaced by a note, then there
1164 is no point in pursuing this chain any further. */
1168 for (nextlinks
= LOG_LINKS (link
);
1170 nextlinks
= XEXP (nextlinks
, 1))
1171 if ((next
= try_combine (insn
, link
,
1172 XEXP (nextlinks
, 0),
1173 &new_direct_jump_p
)) != 0)
1178 /* Try to combine a jump insn that uses CC0
1179 with a preceding insn that sets CC0, and maybe with its
1180 logical predecessor as well.
1181 This is how we make decrement-and-branch insns.
1182 We need this special code because data flow connections
1183 via CC0 do not get entered in LOG_LINKS. */
1186 && (prev
= prev_nonnote_insn (insn
)) != 0
1187 && NONJUMP_INSN_P (prev
)
1188 && sets_cc0_p (PATTERN (prev
)))
1190 if ((next
= try_combine (insn
, prev
,
1191 NULL_RTX
, &new_direct_jump_p
)) != 0)
1194 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1195 nextlinks
= XEXP (nextlinks
, 1))
1196 if ((next
= try_combine (insn
, prev
,
1197 XEXP (nextlinks
, 0),
1198 &new_direct_jump_p
)) != 0)
1202 /* Do the same for an insn that explicitly references CC0. */
1203 if (NONJUMP_INSN_P (insn
)
1204 && (prev
= prev_nonnote_insn (insn
)) != 0
1205 && NONJUMP_INSN_P (prev
)
1206 && sets_cc0_p (PATTERN (prev
))
1207 && GET_CODE (PATTERN (insn
)) == SET
1208 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1210 if ((next
= try_combine (insn
, prev
,
1211 NULL_RTX
, &new_direct_jump_p
)) != 0)
1214 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1215 nextlinks
= XEXP (nextlinks
, 1))
1216 if ((next
= try_combine (insn
, prev
,
1217 XEXP (nextlinks
, 0),
1218 &new_direct_jump_p
)) != 0)
1222 /* Finally, see if any of the insns that this insn links to
1223 explicitly references CC0. If so, try this insn, that insn,
1224 and its predecessor if it sets CC0. */
1225 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1226 if (NONJUMP_INSN_P (XEXP (links
, 0))
1227 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
1228 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
1229 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
1230 && NONJUMP_INSN_P (prev
)
1231 && sets_cc0_p (PATTERN (prev
))
1232 && (next
= try_combine (insn
, XEXP (links
, 0),
1233 prev
, &new_direct_jump_p
)) != 0)
1237 /* Try combining an insn with two different insns whose results it
1239 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1240 for (nextlinks
= XEXP (links
, 1); nextlinks
;
1241 nextlinks
= XEXP (nextlinks
, 1))
1242 if ((next
= try_combine (insn
, XEXP (links
, 0),
1243 XEXP (nextlinks
, 0),
1244 &new_direct_jump_p
)) != 0)
1247 /* Try this insn with each REG_EQUAL note it links back to. */
1248 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1251 rtx temp
= XEXP (links
, 0);
1252 if ((set
= single_set (temp
)) != 0
1253 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1254 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1255 /* Avoid using a register that may already been marked
1256 dead by an earlier instruction. */
1257 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1258 && (GET_MODE (note
) == VOIDmode
1259 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1260 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1262 /* Temporarily replace the set's source with the
1263 contents of the REG_EQUAL note. The insn will
1264 be deleted or recognized by try_combine. */
1265 rtx orig
= SET_SRC (set
);
1266 SET_SRC (set
) = note
;
1268 i2mod_old_rhs
= copy_rtx (orig
);
1269 i2mod_new_rhs
= copy_rtx (note
);
1270 next
= try_combine (insn
, i2mod
, NULL_RTX
,
1271 &new_direct_jump_p
);
1275 SET_SRC (set
) = orig
;
1280 record_dead_and_set_regs (insn
);
1288 default_rtl_profile ();
1291 new_direct_jump_p
|= purge_all_dead_edges ();
1292 delete_noop_moves ();
1295 free (uid_log_links
);
1296 free (uid_insn_cost
);
1297 VEC_free (reg_stat_type
, heap
, reg_stat
);
1300 struct undo
*undo
, *next
;
1301 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1309 total_attempts
+= combine_attempts
;
1310 total_merges
+= combine_merges
;
1311 total_extras
+= combine_extras
;
1312 total_successes
+= combine_successes
;
1314 nonzero_sign_valid
= 0;
1315 rtl_hooks
= general_rtl_hooks
;
1317 /* Make recognizer allow volatile MEMs again. */
1320 return new_direct_jump_p
;
1323 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1326 init_reg_last (void)
1331 for (i
= 0; VEC_iterate (reg_stat_type
, reg_stat
, i
, p
); ++i
)
1332 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1335 /* Set up any promoted values for incoming argument registers. */
1338 setup_incoming_promotions (rtx first
)
1341 bool strictly_local
= false;
1343 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1344 arg
= TREE_CHAIN (arg
))
1346 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1348 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1350 /* Only continue if the incoming argument is in a register. */
1354 /* Determine, if possible, whether all call sites of the current
1355 function lie within the current compilation unit. (This does
1356 take into account the exporting of a function via taking its
1357 address, and so forth.) */
1358 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1360 /* The mode and signedness of the argument before any promotions happen
1361 (equal to the mode of the pseudo holding it at that stage). */
1362 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1363 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1365 /* The mode and signedness of the argument after any source language and
1366 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1367 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1368 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1370 /* The mode and signedness of the argument as it is actually passed,
1371 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1372 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1373 TREE_TYPE (cfun
->decl
), 0);
1375 /* The mode of the register in which the argument is being passed. */
1376 mode4
= GET_MODE (reg
);
1378 /* Eliminate sign extensions in the callee when:
1379 (a) A mode promotion has occurred; */
1382 /* (b) The mode of the register is the same as the mode of
1383 the argument as it is passed; */
1386 /* (c) There's no language level extension; */
1389 /* (c.1) All callers are from the current compilation unit. If that's
1390 the case we don't have to rely on an ABI, we only have to know
1391 what we're generating right now, and we know that we will do the
1392 mode1 to mode2 promotion with the given sign. */
1393 else if (!strictly_local
)
1395 /* (c.2) The combination of the two promotions is useful. This is
1396 true when the signs match, or if the first promotion is unsigned.
1397 In the later case, (sign_extend (zero_extend x)) is the same as
1398 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1404 /* Record that the value was promoted from mode1 to mode3,
1405 so that any sign extension at the head of the current
1406 function may be eliminated. */
1407 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1408 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1409 record_value_for_reg (reg
, first
, x
);
1413 /* Called via note_stores. If X is a pseudo that is narrower than
1414 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1416 If we are setting only a portion of X and we can't figure out what
1417 portion, assume all bits will be used since we don't know what will
1420 Similarly, set how many bits of X are known to be copies of the sign bit
1421 at all locations in the function. This is the smallest number implied
1425 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1427 rtx insn
= (rtx
) data
;
1431 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1432 /* If this register is undefined at the start of the file, we can't
1433 say what its contents were. */
1434 && ! REGNO_REG_SET_P
1435 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1436 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1438 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1440 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1442 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1443 rsp
->sign_bit_copies
= 1;
1447 /* If this register is being initialized using itself, and the
1448 register is uninitialized in this basic block, and there are
1449 no LOG_LINKS which set the register, then part of the
1450 register is uninitialized. In that case we can't assume
1451 anything about the number of nonzero bits.
1453 ??? We could do better if we checked this in
1454 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1455 could avoid making assumptions about the insn which initially
1456 sets the register, while still using the information in other
1457 insns. We would have to be careful to check every insn
1458 involved in the combination. */
1461 && reg_referenced_p (x
, PATTERN (insn
))
1462 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1467 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1469 if (dead_or_set_p (XEXP (link
, 0), x
))
1474 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1475 rsp
->sign_bit_copies
= 1;
1480 /* If this is a complex assignment, see if we can convert it into a
1481 simple assignment. */
1482 set
= expand_field_assignment (set
);
1484 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1485 set what we know about X. */
1487 if (SET_DEST (set
) == x
1488 || (GET_CODE (SET_DEST (set
)) == SUBREG
1489 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1490 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1491 && SUBREG_REG (SET_DEST (set
)) == x
))
1493 rtx src
= SET_SRC (set
);
1495 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1496 /* If X is narrower than a word and SRC is a non-negative
1497 constant that would appear negative in the mode of X,
1498 sign-extend it for use in reg_stat[].nonzero_bits because some
1499 machines (maybe most) will actually do the sign-extension
1500 and this is the conservative approach.
1502 ??? For 2.5, try to tighten up the MD files in this regard
1503 instead of this kludge. */
1505 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1506 && CONST_INT_P (src
)
1508 && 0 != (INTVAL (src
)
1509 & ((HOST_WIDE_INT
) 1
1510 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1511 src
= GEN_INT (INTVAL (src
)
1512 | ((HOST_WIDE_INT
) (-1)
1513 << GET_MODE_BITSIZE (GET_MODE (x
))));
1516 /* Don't call nonzero_bits if it cannot change anything. */
1517 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1518 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1519 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1520 if (rsp
->sign_bit_copies
== 0
1521 || rsp
->sign_bit_copies
> num
)
1522 rsp
->sign_bit_copies
= num
;
1526 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1527 rsp
->sign_bit_copies
= 1;
1532 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1533 insns that were previously combined into I3 or that will be combined
1534 into the merger of INSN and I3.
1536 Return 0 if the combination is not allowed for any reason.
1538 If the combination is allowed, *PDEST will be set to the single
1539 destination of INSN and *PSRC to the single source, and this function
1543 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1544 rtx
*pdest
, rtx
*psrc
)
1553 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1554 && next_active_insn (succ
) == i3
)
1555 : next_active_insn (insn
) == i3
);
1557 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1558 or a PARALLEL consisting of such a SET and CLOBBERs.
1560 If INSN has CLOBBER parallel parts, ignore them for our processing.
1561 By definition, these happen during the execution of the insn. When it
1562 is merged with another insn, all bets are off. If they are, in fact,
1563 needed and aren't also supplied in I3, they may be added by
1564 recog_for_combine. Otherwise, it won't match.
1566 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1569 Get the source and destination of INSN. If more than one, can't
1572 if (GET_CODE (PATTERN (insn
)) == SET
)
1573 set
= PATTERN (insn
);
1574 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1575 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1577 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1579 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1581 switch (GET_CODE (elt
))
1583 /* This is important to combine floating point insns
1584 for the SH4 port. */
1586 /* Combining an isolated USE doesn't make sense.
1587 We depend here on combinable_i3pat to reject them. */
1588 /* The code below this loop only verifies that the inputs of
1589 the SET in INSN do not change. We call reg_set_between_p
1590 to verify that the REG in the USE does not change between
1592 If the USE in INSN was for a pseudo register, the matching
1593 insn pattern will likely match any register; combining this
1594 with any other USE would only be safe if we knew that the
1595 used registers have identical values, or if there was
1596 something to tell them apart, e.g. different modes. For
1597 now, we forgo such complicated tests and simply disallow
1598 combining of USES of pseudo registers with any other USE. */
1599 if (REG_P (XEXP (elt
, 0))
1600 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1602 rtx i3pat
= PATTERN (i3
);
1603 int i
= XVECLEN (i3pat
, 0) - 1;
1604 unsigned int regno
= REGNO (XEXP (elt
, 0));
1608 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1610 if (GET_CODE (i3elt
) == USE
1611 && REG_P (XEXP (i3elt
, 0))
1612 && (REGNO (XEXP (i3elt
, 0)) == regno
1613 ? reg_set_between_p (XEXP (elt
, 0),
1614 PREV_INSN (insn
), i3
)
1615 : regno
>= FIRST_PSEUDO_REGISTER
))
1622 /* We can ignore CLOBBERs. */
1627 /* Ignore SETs whose result isn't used but not those that
1628 have side-effects. */
1629 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1630 && insn_nothrow_p (insn
)
1631 && !side_effects_p (elt
))
1634 /* If we have already found a SET, this is a second one and
1635 so we cannot combine with this insn. */
1643 /* Anything else means we can't combine. */
1649 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1650 so don't do anything with it. */
1651 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1660 set
= expand_field_assignment (set
);
1661 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1663 /* Don't eliminate a store in the stack pointer. */
1664 if (dest
== stack_pointer_rtx
1665 /* Don't combine with an insn that sets a register to itself if it has
1666 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1667 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1668 /* Can't merge an ASM_OPERANDS. */
1669 || GET_CODE (src
) == ASM_OPERANDS
1670 /* Can't merge a function call. */
1671 || GET_CODE (src
) == CALL
1672 /* Don't eliminate a function call argument. */
1674 && (find_reg_fusage (i3
, USE
, dest
)
1676 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1677 && global_regs
[REGNO (dest
)])))
1678 /* Don't substitute into an incremented register. */
1679 || FIND_REG_INC_NOTE (i3
, dest
)
1680 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1681 /* Don't substitute into a non-local goto, this confuses CFG. */
1682 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1683 /* Make sure that DEST is not used after SUCC but before I3. */
1684 || (succ
&& ! all_adjacent
1685 && reg_used_between_p (dest
, succ
, i3
))
1686 /* Make sure that the value that is to be substituted for the register
1687 does not use any registers whose values alter in between. However,
1688 If the insns are adjacent, a use can't cross a set even though we
1689 think it might (this can happen for a sequence of insns each setting
1690 the same destination; last_set of that register might point to
1691 a NOTE). If INSN has a REG_EQUIV note, the register is always
1692 equivalent to the memory so the substitution is valid even if there
1693 are intervening stores. Also, don't move a volatile asm or
1694 UNSPEC_VOLATILE across any other insns. */
1697 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1698 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1699 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1700 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1701 /* Don't combine across a CALL_INSN, because that would possibly
1702 change whether the life span of some REGs crosses calls or not,
1703 and it is a pain to update that information.
1704 Exception: if source is a constant, moving it later can't hurt.
1705 Accept that as a special case. */
1706 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1709 /* DEST must either be a REG or CC0. */
1712 /* If register alignment is being enforced for multi-word items in all
1713 cases except for parameters, it is possible to have a register copy
1714 insn referencing a hard register that is not allowed to contain the
1715 mode being copied and which would not be valid as an operand of most
1716 insns. Eliminate this problem by not combining with such an insn.
1718 Also, on some machines we don't want to extend the life of a hard
1722 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1723 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1724 /* Don't extend the life of a hard register unless it is
1725 user variable (if we have few registers) or it can't
1726 fit into the desired register (meaning something special
1728 Also avoid substituting a return register into I3, because
1729 reload can't handle a conflict with constraints of other
1731 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1732 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1735 else if (GET_CODE (dest
) != CC0
)
1739 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1740 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1741 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1743 /* Don't substitute for a register intended as a clobberable
1745 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1746 if (rtx_equal_p (reg
, dest
))
1749 /* If the clobber represents an earlyclobber operand, we must not
1750 substitute an expression containing the clobbered register.
1751 As we do not analyze the constraint strings here, we have to
1752 make the conservative assumption. However, if the register is
1753 a fixed hard reg, the clobber cannot represent any operand;
1754 we leave it up to the machine description to either accept or
1755 reject use-and-clobber patterns. */
1757 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1758 || !fixed_regs
[REGNO (reg
)])
1759 if (reg_overlap_mentioned_p (reg
, src
))
1763 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1764 or not), reject, unless nothing volatile comes between it and I3 */
1766 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1768 /* Make sure succ doesn't contain a volatile reference. */
1769 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1772 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1773 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1777 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1778 to be an explicit register variable, and was chosen for a reason. */
1780 if (GET_CODE (src
) == ASM_OPERANDS
1781 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1784 /* If there are any volatile insns between INSN and I3, reject, because
1785 they might affect machine state. */
1787 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1788 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1791 /* If INSN contains an autoincrement or autodecrement, make sure that
1792 register is not used between there and I3, and not already used in
1793 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1794 Also insist that I3 not be a jump; if it were one
1795 and the incremented register were spilled, we would lose. */
1798 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1799 if (REG_NOTE_KIND (link
) == REG_INC
1801 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1802 || (pred
!= NULL_RTX
1803 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1804 || (succ
!= NULL_RTX
1805 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1806 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1811 /* Don't combine an insn that follows a CC0-setting insn.
1812 An insn that uses CC0 must not be separated from the one that sets it.
1813 We do, however, allow I2 to follow a CC0-setting insn if that insn
1814 is passed as I1; in that case it will be deleted also.
1815 We also allow combining in this case if all the insns are adjacent
1816 because that would leave the two CC0 insns adjacent as well.
1817 It would be more logical to test whether CC0 occurs inside I1 or I2,
1818 but that would be much slower, and this ought to be equivalent. */
1820 p
= prev_nonnote_insn (insn
);
1821 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1826 /* If we get here, we have passed all the tests and the combination is
1835 /* LOC is the location within I3 that contains its pattern or the component
1836 of a PARALLEL of the pattern. We validate that it is valid for combining.
1838 One problem is if I3 modifies its output, as opposed to replacing it
1839 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1840 so would produce an insn that is not equivalent to the original insns.
1844 (set (reg:DI 101) (reg:DI 100))
1845 (set (subreg:SI (reg:DI 101) 0) <foo>)
1847 This is NOT equivalent to:
1849 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1850 (set (reg:DI 101) (reg:DI 100))])
1852 Not only does this modify 100 (in which case it might still be valid
1853 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1855 We can also run into a problem if I2 sets a register that I1
1856 uses and I1 gets directly substituted into I3 (not via I2). In that
1857 case, we would be getting the wrong value of I2DEST into I3, so we
1858 must reject the combination. This case occurs when I2 and I1 both
1859 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1860 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1861 of a SET must prevent combination from occurring.
1863 Before doing the above check, we first try to expand a field assignment
1864 into a set of logical operations.
1866 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1867 we place a register that is both set and used within I3. If more than one
1868 such register is detected, we fail.
1870 Return 1 if the combination is valid, zero otherwise. */
1873 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1874 int i1_not_in_src
, rtx
*pi3dest_killed
)
1878 if (GET_CODE (x
) == SET
)
1881 rtx dest
= SET_DEST (set
);
1882 rtx src
= SET_SRC (set
);
1883 rtx inner_dest
= dest
;
1886 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1887 || GET_CODE (inner_dest
) == SUBREG
1888 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1889 inner_dest
= XEXP (inner_dest
, 0);
1891 /* Check for the case where I3 modifies its output, as discussed
1892 above. We don't want to prevent pseudos from being combined
1893 into the address of a MEM, so only prevent the combination if
1894 i1 or i2 set the same MEM. */
1895 if ((inner_dest
!= dest
&&
1896 (!MEM_P (inner_dest
)
1897 || rtx_equal_p (i2dest
, inner_dest
)
1898 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1899 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1900 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1902 /* This is the same test done in can_combine_p except we can't test
1903 all_adjacent; we don't have to, since this instruction will stay
1904 in place, thus we are not considering increasing the lifetime of
1907 Also, if this insn sets a function argument, combining it with
1908 something that might need a spill could clobber a previous
1909 function argument; the all_adjacent test in can_combine_p also
1910 checks this; here, we do a more specific test for this case. */
1912 || (REG_P (inner_dest
)
1913 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1914 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1915 GET_MODE (inner_dest
))))
1916 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1919 /* If DEST is used in I3, it is being killed in this insn, so
1920 record that for later. We have to consider paradoxical
1921 subregs here, since they kill the whole register, but we
1922 ignore partial subregs, STRICT_LOW_PART, etc.
1923 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1924 STACK_POINTER_REGNUM, since these are always considered to be
1925 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1927 if (GET_CODE (subdest
) == SUBREG
1928 && (GET_MODE_SIZE (GET_MODE (subdest
))
1929 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
1930 subdest
= SUBREG_REG (subdest
);
1933 && reg_referenced_p (subdest
, PATTERN (i3
))
1934 && REGNO (subdest
) != FRAME_POINTER_REGNUM
1935 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1936 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
1938 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1939 && (REGNO (subdest
) != ARG_POINTER_REGNUM
1940 || ! fixed_regs
[REGNO (subdest
)])
1942 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
1944 if (*pi3dest_killed
)
1947 *pi3dest_killed
= subdest
;
1951 else if (GET_CODE (x
) == PARALLEL
)
1955 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1956 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1957 i1_not_in_src
, pi3dest_killed
))
1964 /* Return 1 if X is an arithmetic expression that contains a multiplication
1965 and division. We don't count multiplications by powers of two here. */
1968 contains_muldiv (rtx x
)
1970 switch (GET_CODE (x
))
1972 case MOD
: case DIV
: case UMOD
: case UDIV
:
1976 return ! (CONST_INT_P (XEXP (x
, 1))
1977 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1980 return contains_muldiv (XEXP (x
, 0))
1981 || contains_muldiv (XEXP (x
, 1));
1984 return contains_muldiv (XEXP (x
, 0));
1990 /* Determine whether INSN can be used in a combination. Return nonzero if
1991 not. This is used in try_combine to detect early some cases where we
1992 can't perform combinations. */
1995 cant_combine_insn_p (rtx insn
)
2000 /* If this isn't really an insn, we can't do anything.
2001 This can occur when flow deletes an insn that it has merged into an
2002 auto-increment address. */
2003 if (! INSN_P (insn
))
2006 /* Never combine loads and stores involving hard regs that are likely
2007 to be spilled. The register allocator can usually handle such
2008 reg-reg moves by tying. If we allow the combiner to make
2009 substitutions of likely-spilled regs, reload might die.
2010 As an exception, we allow combinations involving fixed regs; these are
2011 not available to the register allocator so there's no risk involved. */
2013 set
= single_set (insn
);
2016 src
= SET_SRC (set
);
2017 dest
= SET_DEST (set
);
2018 if (GET_CODE (src
) == SUBREG
)
2019 src
= SUBREG_REG (src
);
2020 if (GET_CODE (dest
) == SUBREG
)
2021 dest
= SUBREG_REG (dest
);
2022 if (REG_P (src
) && REG_P (dest
)
2023 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
2024 && ! fixed_regs
[REGNO (src
)]
2025 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
2026 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
2027 && ! fixed_regs
[REGNO (dest
)]
2028 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
2034 struct likely_spilled_retval_info
2036 unsigned regno
, nregs
;
2040 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2041 hard registers that are known to be written to / clobbered in full. */
2043 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2045 struct likely_spilled_retval_info
*const info
=
2046 (struct likely_spilled_retval_info
*) data
;
2047 unsigned regno
, nregs
;
2050 if (!REG_P (XEXP (set
, 0)))
2053 if (regno
>= info
->regno
+ info
->nregs
)
2055 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2056 if (regno
+ nregs
<= info
->regno
)
2058 new_mask
= (2U << (nregs
- 1)) - 1;
2059 if (regno
< info
->regno
)
2060 new_mask
>>= info
->regno
- regno
;
2062 new_mask
<<= regno
- info
->regno
;
2063 info
->mask
&= ~new_mask
;
2066 /* Return nonzero iff part of the return value is live during INSN, and
2067 it is likely spilled. This can happen when more than one insn is needed
2068 to copy the return value, e.g. when we consider to combine into the
2069 second copy insn for a complex value. */
2072 likely_spilled_retval_p (rtx insn
)
2074 rtx use
= BB_END (this_basic_block
);
2076 unsigned regno
, nregs
;
2077 /* We assume here that no machine mode needs more than
2078 32 hard registers when the value overlaps with a register
2079 for which FUNCTION_VALUE_REGNO_P is true. */
2081 struct likely_spilled_retval_info info
;
2083 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2085 reg
= XEXP (PATTERN (use
), 0);
2086 if (!REG_P (reg
) || !FUNCTION_VALUE_REGNO_P (REGNO (reg
)))
2088 regno
= REGNO (reg
);
2089 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2092 mask
= (2U << (nregs
- 1)) - 1;
2094 /* Disregard parts of the return value that are set later. */
2098 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2100 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2103 /* Check if any of the (probably) live return value registers is
2108 if ((mask
& 1 << nregs
)
2109 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno
+ nregs
)))
2115 /* Adjust INSN after we made a change to its destination.
2117 Changing the destination can invalidate notes that say something about
2118 the results of the insn and a LOG_LINK pointing to the insn. */
2121 adjust_for_new_dest (rtx insn
)
2123 /* For notes, be conservative and simply remove them. */
2124 remove_reg_equal_equiv_notes (insn
);
2126 /* The new insn will have a destination that was previously the destination
2127 of an insn just above it. Call distribute_links to make a LOG_LINK from
2128 the next use of that destination. */
2129 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
2131 df_insn_rescan (insn
);
2134 /* Return TRUE if combine can reuse reg X in mode MODE.
2135 ADDED_SETS is nonzero if the original set is still required. */
2137 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2145 /* Allow hard registers if the new mode is legal, and occupies no more
2146 registers than the old mode. */
2147 if (regno
< FIRST_PSEUDO_REGISTER
)
2148 return (HARD_REGNO_MODE_OK (regno
, mode
)
2149 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2150 >= hard_regno_nregs
[regno
][mode
]));
2152 /* Or a pseudo that is only used once. */
2153 return (REG_N_SETS (regno
) == 1 && !added_sets
2154 && !REG_USERVAR_P (x
));
2158 /* Check whether X, the destination of a set, refers to part of
2159 the register specified by REG. */
2162 reg_subword_p (rtx x
, rtx reg
)
2164 /* Check that reg is an integer mode register. */
2165 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2168 if (GET_CODE (x
) == STRICT_LOW_PART
2169 || GET_CODE (x
) == ZERO_EXTRACT
)
2172 return GET_CODE (x
) == SUBREG
2173 && SUBREG_REG (x
) == reg
2174 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2178 /* Replace auto-increment addressing modes with explicit operations to
2179 access the same addresses without modifying the corresponding
2180 registers. If AFTER holds, SRC is meant to be reused after the
2181 side effect, otherwise it is to be reused before that. */
2184 cleanup_auto_inc_dec (rtx src
, bool after
, enum machine_mode mem_mode
)
2187 const RTX_CODE code
= GET_CODE (x
);
2203 /* SCRATCH must be shared because they represent distinct values. */
2206 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
2211 if (shared_const_p (x
))
2216 mem_mode
= GET_MODE (x
);
2223 gcc_assert (mem_mode
!= VOIDmode
&& mem_mode
!= BLKmode
);
2224 if (after
== (code
== PRE_INC
|| code
== PRE_DEC
))
2225 x
= cleanup_auto_inc_dec (XEXP (x
, 0), after
, mem_mode
);
2227 x
= gen_rtx_PLUS (GET_MODE (x
),
2228 cleanup_auto_inc_dec (XEXP (x
, 0), after
, mem_mode
),
2229 GEN_INT ((code
== PRE_INC
|| code
== POST_INC
)
2230 ? GET_MODE_SIZE (mem_mode
)
2231 : -GET_MODE_SIZE (mem_mode
)));
2236 if (after
== (code
== PRE_MODIFY
))
2240 return cleanup_auto_inc_dec (x
, after
, mem_mode
);
2246 /* Copy the various flags, fields, and other information. We assume
2247 that all fields need copying, and then clear the fields that should
2248 not be copied. That is the sensible default behavior, and forces
2249 us to explicitly document why we are *not* copying a flag. */
2250 x
= shallow_copy_rtx (x
);
2252 /* We do not copy the USED flag, which is used as a mark bit during
2253 walks over the RTL. */
2254 RTX_FLAG (x
, used
) = 0;
2256 /* We do not copy FRAME_RELATED for INSNs. */
2258 RTX_FLAG (x
, frame_related
) = 0;
2260 fmt
= GET_RTX_FORMAT (code
);
2261 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2263 XEXP (x
, i
) = cleanup_auto_inc_dec (XEXP (x
, i
), after
, mem_mode
);
2264 else if (fmt
[i
] == 'E' || fmt
[i
] == 'V')
2267 XVEC (x
, i
) = rtvec_alloc (XVECLEN (x
, i
));
2268 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2270 = cleanup_auto_inc_dec (XVECEXP (src
, i
, j
), after
, mem_mode
);
2276 /* Auxiliary data structure for propagate_for_debug_stmt. */
2278 struct rtx_subst_pair
2285 /* DATA points to an rtx_subst_pair. Return the value that should be
2289 propagate_for_debug_subst (rtx from
, const_rtx old_rtx
, void *data
)
2291 struct rtx_subst_pair
*pair
= (struct rtx_subst_pair
*)data
;
2293 if (!rtx_equal_p (from
, old_rtx
))
2295 if (!pair
->adjusted
)
2297 pair
->adjusted
= true;
2298 pair
->to
= cleanup_auto_inc_dec (pair
->to
, pair
->after
, VOIDmode
);
2301 return copy_rtx (pair
->to
);
2305 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2306 and LAST. If MOVE holds, debug insns must also be moved past
2310 propagate_for_debug (rtx insn
, rtx last
, rtx dest
, rtx src
, bool move
)
2312 rtx next
, move_pos
= move
? last
: NULL_RTX
, loc
;
2315 struct rtx_subst_pair p
;
2321 next
= NEXT_INSN (insn
);
2322 while (next
!= last
)
2325 next
= NEXT_INSN (insn
);
2326 if (DEBUG_INSN_P (insn
))
2329 loc
= simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn
),
2330 dest
, propagate_for_debug_subst
, &p
);
2332 loc
= simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
), dest
, src
);
2334 if (loc
== INSN_VAR_LOCATION_LOC (insn
))
2336 INSN_VAR_LOCATION_LOC (insn
) = loc
;
2340 PREV_INSN (insn
) = NEXT_INSN (insn
) = NULL_RTX
;
2341 move_pos
= emit_debug_insn_after (insn
, move_pos
);
2344 df_insn_rescan (insn
);
2349 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2350 Note that the INSN should be deleted *after* removing dead edges, so
2351 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2352 but not for a (set (pc) (label_ref FOO)). */
2355 update_cfg_for_uncondjump (rtx insn
)
2357 basic_block bb
= BLOCK_FOR_INSN (insn
);
2358 bool at_end
= (BB_END (bb
) == insn
);
2361 purge_dead_edges (bb
);
2364 if (at_end
&& EDGE_COUNT (bb
->succs
) == 1)
2365 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2369 /* Try to combine the insns I1 and I2 into I3.
2370 Here I1 and I2 appear earlier than I3.
2371 I1 can be zero; then we combine just I2 into I3.
2373 If we are combining three insns and the resulting insn is not recognized,
2374 try splitting it into two insns. If that happens, I2 and I3 are retained
2375 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2378 Return 0 if the combination does not work. Then nothing is changed.
2379 If we did the combination, return the insn at which combine should
2382 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2383 new direct jump instruction. */
2386 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
2388 /* New patterns for I3 and I2, respectively. */
2389 rtx newpat
, newi2pat
= 0;
2390 rtvec newpat_vec_with_clobbers
= 0;
2391 int substed_i2
= 0, substed_i1
= 0;
2392 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2393 int added_sets_1
, added_sets_2
;
2394 /* Total number of SETs to put into I3. */
2396 /* Nonzero if I2's body now appears in I3. */
2398 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2399 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2400 /* Contains I3 if the destination of I3 is used in its source, which means
2401 that the old life of I3 is being killed. If that usage is placed into
2402 I2 and not in I3, a REG_DEAD note must be made. */
2403 rtx i3dest_killed
= 0;
2404 /* SET_DEST and SET_SRC of I2 and I1. */
2405 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0;
2406 /* Set if I2DEST was reused as a scratch register. */
2407 bool i2scratch
= false;
2408 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2409 rtx i1pat
= 0, i2pat
= 0;
2410 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2411 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2412 int i2dest_killed
= 0, i1dest_killed
= 0;
2413 int i1_feeds_i3
= 0;
2414 /* Notes that must be added to REG_NOTES in I3 and I2. */
2415 rtx new_i3_notes
, new_i2_notes
;
2416 /* Notes that we substituted I3 into I2 instead of the normal case. */
2417 int i3_subst_into_i2
= 0;
2418 /* Notes that I1, I2 or I3 is a MULT operation. */
2421 int changed_i3_dest
= 0;
2427 rtx new_other_notes
;
2430 /* Exit early if one of the insns involved can't be used for
2432 if (cant_combine_insn_p (i3
)
2433 || cant_combine_insn_p (i2
)
2434 || (i1
&& cant_combine_insn_p (i1
))
2435 || likely_spilled_retval_p (i3
))
2439 undobuf
.other_insn
= 0;
2441 /* Reset the hard register usage information. */
2442 CLEAR_HARD_REG_SET (newpat_used_regs
);
2444 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2447 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2448 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2450 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2451 INSN_UID (i2
), INSN_UID (i3
));
2454 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2455 code below, set I1 to be the earlier of the two insns. */
2456 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2457 temp
= i1
, i1
= i2
, i2
= temp
;
2459 added_links_insn
= 0;
2461 /* First check for one important special-case that the code below will
2462 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2463 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2464 we may be able to replace that destination with the destination of I3.
2465 This occurs in the common code where we compute both a quotient and
2466 remainder into a structure, in which case we want to do the computation
2467 directly into the structure to avoid register-register copies.
2469 Note that this case handles both multiple sets in I2 and also
2470 cases where I2 has a number of CLOBBER or PARALLELs.
2472 We make very conservative checks below and only try to handle the
2473 most common cases of this. For example, we only handle the case
2474 where I2 and I3 are adjacent to avoid making difficult register
2477 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2478 && REG_P (SET_SRC (PATTERN (i3
)))
2479 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2480 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2481 && GET_CODE (PATTERN (i2
)) == PARALLEL
2482 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2483 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2484 below would need to check what is inside (and reg_overlap_mentioned_p
2485 doesn't support those codes anyway). Don't allow those destinations;
2486 the resulting insn isn't likely to be recognized anyway. */
2487 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2488 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2489 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2490 SET_DEST (PATTERN (i3
)))
2491 && next_active_insn (i2
) == i3
)
2493 rtx p2
= PATTERN (i2
);
2495 /* Make sure that the destination of I3,
2496 which we are going to substitute into one output of I2,
2497 is not used within another output of I2. We must avoid making this:
2498 (parallel [(set (mem (reg 69)) ...)
2499 (set (reg 69) ...)])
2500 which is not well-defined as to order of actions.
2501 (Besides, reload can't handle output reloads for this.)
2503 The problem can also happen if the dest of I3 is a memory ref,
2504 if another dest in I2 is an indirect memory ref. */
2505 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2506 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2507 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2508 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2509 SET_DEST (XVECEXP (p2
, 0, i
))))
2512 if (i
== XVECLEN (p2
, 0))
2513 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2514 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2515 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2516 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2521 subst_low_luid
= DF_INSN_LUID (i2
);
2523 added_sets_2
= added_sets_1
= 0;
2524 i2src
= SET_DEST (PATTERN (i3
));
2525 i2dest
= SET_SRC (PATTERN (i3
));
2526 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2528 /* Replace the dest in I2 with our dest and make the resulting
2529 insn the new pattern for I3. Then skip to where we
2530 validate the pattern. Everything was set up above. */
2531 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
2532 SET_DEST (PATTERN (i3
)));
2535 i3_subst_into_i2
= 1;
2536 goto validate_replacement
;
2540 /* If I2 is setting a pseudo to a constant and I3 is setting some
2541 sub-part of it to another constant, merge them by making a new
2544 && (temp
= single_set (i2
)) != 0
2545 && (CONST_INT_P (SET_SRC (temp
))
2546 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2547 && GET_CODE (PATTERN (i3
)) == SET
2548 && (CONST_INT_P (SET_SRC (PATTERN (i3
)))
2549 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2550 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2552 rtx dest
= SET_DEST (PATTERN (i3
));
2556 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2558 if (CONST_INT_P (XEXP (dest
, 1))
2559 && CONST_INT_P (XEXP (dest
, 2)))
2561 width
= INTVAL (XEXP (dest
, 1));
2562 offset
= INTVAL (XEXP (dest
, 2));
2563 dest
= XEXP (dest
, 0);
2564 if (BITS_BIG_ENDIAN
)
2565 offset
= GET_MODE_BITSIZE (GET_MODE (dest
)) - width
- offset
;
2570 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2571 dest
= XEXP (dest
, 0);
2572 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
2578 /* If this is the low part, we're done. */
2579 if (subreg_lowpart_p (dest
))
2581 /* Handle the case where inner is twice the size of outer. */
2582 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2583 == 2 * GET_MODE_BITSIZE (GET_MODE (dest
)))
2584 offset
+= GET_MODE_BITSIZE (GET_MODE (dest
));
2585 /* Otherwise give up for now. */
2591 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2592 <= HOST_BITS_PER_WIDE_INT
* 2))
2594 HOST_WIDE_INT mhi
, ohi
, ihi
;
2595 HOST_WIDE_INT mlo
, olo
, ilo
;
2596 rtx inner
= SET_SRC (PATTERN (i3
));
2597 rtx outer
= SET_SRC (temp
);
2599 if (CONST_INT_P (outer
))
2601 olo
= INTVAL (outer
);
2602 ohi
= olo
< 0 ? -1 : 0;
2606 olo
= CONST_DOUBLE_LOW (outer
);
2607 ohi
= CONST_DOUBLE_HIGH (outer
);
2610 if (CONST_INT_P (inner
))
2612 ilo
= INTVAL (inner
);
2613 ihi
= ilo
< 0 ? -1 : 0;
2617 ilo
= CONST_DOUBLE_LOW (inner
);
2618 ihi
= CONST_DOUBLE_HIGH (inner
);
2621 if (width
< HOST_BITS_PER_WIDE_INT
)
2623 mlo
= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
2626 else if (width
< HOST_BITS_PER_WIDE_INT
* 2)
2628 mhi
= ((unsigned HOST_WIDE_INT
) 1
2629 << (width
- HOST_BITS_PER_WIDE_INT
)) - 1;
2641 if (offset
>= HOST_BITS_PER_WIDE_INT
)
2643 mhi
= mlo
<< (offset
- HOST_BITS_PER_WIDE_INT
);
2645 ihi
= ilo
<< (offset
- HOST_BITS_PER_WIDE_INT
);
2648 else if (offset
> 0)
2650 mhi
= (mhi
<< offset
) | ((unsigned HOST_WIDE_INT
) mlo
2651 >> (HOST_BITS_PER_WIDE_INT
- offset
));
2652 mlo
= mlo
<< offset
;
2653 ihi
= (ihi
<< offset
) | ((unsigned HOST_WIDE_INT
) ilo
2654 >> (HOST_BITS_PER_WIDE_INT
- offset
));
2655 ilo
= ilo
<< offset
;
2658 olo
= (olo
& ~mlo
) | ilo
;
2659 ohi
= (ohi
& ~mhi
) | ihi
;
2663 subst_low_luid
= DF_INSN_LUID (i2
);
2664 added_sets_2
= added_sets_1
= 0;
2665 i2dest
= SET_DEST (temp
);
2666 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2668 /* Replace the source in I2 with the new constant and make the
2669 resulting insn the new pattern for I3. Then skip to where we
2670 validate the pattern. Everything was set up above. */
2671 SUBST (SET_SRC (temp
),
2672 immed_double_const (olo
, ohi
, GET_MODE (SET_DEST (temp
))));
2674 newpat
= PATTERN (i2
);
2676 /* The dest of I3 has been replaced with the dest of I2. */
2677 changed_i3_dest
= 1;
2678 goto validate_replacement
;
2683 /* If we have no I1 and I2 looks like:
2684 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2686 make up a dummy I1 that is
2689 (set (reg:CC X) (compare:CC Y (const_int 0)))
2691 (We can ignore any trailing CLOBBERs.)
2693 This undoes a previous combination and allows us to match a branch-and-
2696 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2697 && XVECLEN (PATTERN (i2
), 0) >= 2
2698 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2699 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2701 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2702 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2703 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2704 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2705 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2706 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2708 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2709 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2714 /* We make I1 with the same INSN_UID as I2. This gives it
2715 the same DF_INSN_LUID for value tracking. Our fake I1 will
2716 never appear in the insn stream so giving it the same INSN_UID
2717 as I2 will not cause a problem. */
2719 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2720 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
2721 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
);
2723 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2724 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2725 SET_DEST (PATTERN (i1
)));
2730 /* Verify that I2 and I1 are valid for combining. */
2731 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
2732 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
2738 /* Record whether I2DEST is used in I2SRC and similarly for the other
2739 cases. Knowing this will help in register status updating below. */
2740 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2741 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2742 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2743 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2744 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2746 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2748 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
2750 /* Ensure that I3's pattern can be the destination of combines. */
2751 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
2752 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
2759 /* See if any of the insns is a MULT operation. Unless one is, we will
2760 reject a combination that is, since it must be slower. Be conservative
2762 if (GET_CODE (i2src
) == MULT
2763 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2764 || (GET_CODE (PATTERN (i3
)) == SET
2765 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2768 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2769 We used to do this EXCEPT in one case: I3 has a post-inc in an
2770 output operand. However, that exception can give rise to insns like
2772 which is a famous insn on the PDP-11 where the value of r3 used as the
2773 source was model-dependent. Avoid this sort of thing. */
2776 if (!(GET_CODE (PATTERN (i3
)) == SET
2777 && REG_P (SET_SRC (PATTERN (i3
)))
2778 && MEM_P (SET_DEST (PATTERN (i3
)))
2779 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2780 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2781 /* It's not the exception. */
2784 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2785 if (REG_NOTE_KIND (link
) == REG_INC
2786 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2788 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2795 /* See if the SETs in I1 or I2 need to be kept around in the merged
2796 instruction: whenever the value set there is still needed past I3.
2797 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2799 For the SET in I1, we have two cases: If I1 and I2 independently
2800 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2801 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2802 in I1 needs to be kept around unless I1DEST dies or is set in either
2803 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2804 I1DEST. If so, we know I1 feeds into I2. */
2806 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
2809 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
2810 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
2812 /* If the set in I2 needs to be kept around, we must make a copy of
2813 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2814 PATTERN (I2), we are only substituting for the original I1DEST, not into
2815 an already-substituted copy. This also prevents making self-referential
2816 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2821 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2822 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2824 i2pat
= copy_rtx (PATTERN (i2
));
2829 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2830 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2832 i1pat
= copy_rtx (PATTERN (i1
));
2837 /* Substitute in the latest insn for the regs set by the earlier ones. */
2839 maxreg
= max_reg_num ();
2844 /* Many machines that don't use CC0 have insns that can both perform an
2845 arithmetic operation and set the condition code. These operations will
2846 be represented as a PARALLEL with the first element of the vector
2847 being a COMPARE of an arithmetic operation with the constant zero.
2848 The second element of the vector will set some pseudo to the result
2849 of the same arithmetic operation. If we simplify the COMPARE, we won't
2850 match such a pattern and so will generate an extra insn. Here we test
2851 for this case, where both the comparison and the operation result are
2852 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2853 I2SRC. Later we will make the PARALLEL that contains I2. */
2855 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2856 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2857 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2858 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2860 #ifdef SELECT_CC_MODE
2862 enum machine_mode compare_mode
;
2865 newpat
= PATTERN (i3
);
2866 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2870 #ifdef SELECT_CC_MODE
2871 /* See if a COMPARE with the operand we substituted in should be done
2872 with the mode that is currently being used. If not, do the same
2873 processing we do in `subst' for a SET; namely, if the destination
2874 is used only once, try to replace it with a register of the proper
2875 mode and also replace the COMPARE. */
2876 if (undobuf
.other_insn
== 0
2877 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2878 &undobuf
.other_insn
))
2879 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2881 != GET_MODE (SET_DEST (newpat
))))
2883 if (can_change_dest_mode(SET_DEST (newpat
), added_sets_2
,
2886 unsigned int regno
= REGNO (SET_DEST (newpat
));
2889 if (regno
< FIRST_PSEUDO_REGISTER
)
2890 new_dest
= gen_rtx_REG (compare_mode
, regno
);
2893 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2894 new_dest
= regno_reg_rtx
[regno
];
2897 SUBST (SET_DEST (newpat
), new_dest
);
2898 SUBST (XEXP (*cc_use
, 0), new_dest
);
2899 SUBST (SET_SRC (newpat
),
2900 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2903 undobuf
.other_insn
= 0;
2910 /* It is possible that the source of I2 or I1 may be performing
2911 an unneeded operation, such as a ZERO_EXTEND of something
2912 that is known to have the high part zero. Handle that case
2913 by letting subst look at the innermost one of them.
2915 Another way to do this would be to have a function that tries
2916 to simplify a single insn instead of merging two or more
2917 insns. We don't do this because of the potential of infinite
2918 loops and because of the potential extra memory required.
2919 However, doing it the way we are is a bit of a kludge and
2920 doesn't catch all cases.
2922 But only do this if -fexpensive-optimizations since it slows
2923 things down and doesn't usually win.
2925 This is not done in the COMPARE case above because the
2926 unmodified I2PAT is used in the PARALLEL and so a pattern
2927 with a modified I2SRC would not match. */
2929 if (flag_expensive_optimizations
)
2931 /* Pass pc_rtx so no substitutions are done, just
2935 subst_low_luid
= DF_INSN_LUID (i1
);
2936 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
2940 subst_low_luid
= DF_INSN_LUID (i2
);
2941 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
2945 n_occurrences
= 0; /* `subst' counts here */
2947 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2948 need to make a unique copy of I2SRC each time we substitute it
2949 to avoid self-referential rtl. */
2951 subst_low_luid
= DF_INSN_LUID (i2
);
2952 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2953 ! i1_feeds_i3
&& i1dest_in_i1src
);
2956 /* Record whether i2's body now appears within i3's body. */
2957 i2_is_used
= n_occurrences
;
2960 /* If we already got a failure, don't try to do more. Otherwise,
2961 try to substitute in I1 if we have it. */
2963 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2965 /* Check that an autoincrement side-effect on I1 has not been lost.
2966 This happens if I1DEST is mentioned in I2 and dies there, and
2967 has disappeared from the new pattern. */
2968 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2970 && dead_or_set_p (i2
, i1dest
)
2971 && !reg_overlap_mentioned_p (i1dest
, newpat
))
2972 /* Before we can do this substitution, we must redo the test done
2973 above (see detailed comments there) that ensures that I1DEST
2974 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2975 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, 0, 0))
2982 subst_low_luid
= DF_INSN_LUID (i1
);
2983 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2987 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2988 to count all the ways that I2SRC and I1SRC can be used. */
2989 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2990 && i2_is_used
+ added_sets_2
> 1)
2991 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2992 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2994 /* Fail if we tried to make a new register. */
2995 || max_reg_num () != maxreg
2996 /* Fail if we couldn't do something and have a CLOBBER. */
2997 || GET_CODE (newpat
) == CLOBBER
2998 /* Fail if this new pattern is a MULT and we didn't have one before
2999 at the outer level. */
3000 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3007 /* If the actions of the earlier insns must be kept
3008 in addition to substituting them into the latest one,
3009 we must make a new PARALLEL for the latest insn
3010 to hold additional the SETs. */
3012 if (added_sets_1
|| added_sets_2
)
3016 if (GET_CODE (newpat
) == PARALLEL
)
3018 rtvec old
= XVEC (newpat
, 0);
3019 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
3020 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3021 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3022 sizeof (old
->elem
[0]) * old
->num_elem
);
3027 total_sets
= 1 + added_sets_1
+ added_sets_2
;
3028 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3029 XVECEXP (newpat
, 0, 0) = old
;
3033 XVECEXP (newpat
, 0, --total_sets
) = i1pat
;
3037 /* If there is no I1, use I2's body as is. We used to also not do
3038 the subst call below if I2 was substituted into I3,
3039 but that could lose a simplification. */
3041 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
3043 /* See comment where i2pat is assigned. */
3044 XVECEXP (newpat
, 0, --total_sets
)
3045 = subst (i2pat
, i1dest
, i1src
, 0, 0);
3049 validate_replacement
:
3051 /* Note which hard regs this insn has as inputs. */
3052 mark_used_regs_combine (newpat
);
3054 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3055 consider splitting this pattern, we might need these clobbers. */
3056 if (i1
&& GET_CODE (newpat
) == PARALLEL
3057 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3059 int len
= XVECLEN (newpat
, 0);
3061 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3062 for (i
= 0; i
< len
; i
++)
3063 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3066 /* Is the result of combination a valid instruction? */
3067 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3069 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3070 the second SET's destination is a register that is unused and isn't
3071 marked as an instruction that might trap in an EH region. In that case,
3072 we just need the first SET. This can occur when simplifying a divmod
3073 insn. We *must* test for this case here because the code below that
3074 splits two independent SETs doesn't handle this case correctly when it
3075 updates the register status.
3077 It's pointless doing this if we originally had two sets, one from
3078 i3, and one from i2. Combining then splitting the parallel results
3079 in the original i2 again plus an invalid insn (which we delete).
3080 The net effect is only to move instructions around, which makes
3081 debug info less accurate.
3083 Also check the case where the first SET's destination is unused.
3084 That would not cause incorrect code, but does cause an unneeded
3087 if (insn_code_number
< 0
3088 && !(added_sets_2
&& i1
== 0)
3089 && GET_CODE (newpat
) == PARALLEL
3090 && XVECLEN (newpat
, 0) == 2
3091 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3092 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3093 && asm_noperands (newpat
) < 0)
3095 rtx set0
= XVECEXP (newpat
, 0, 0);
3096 rtx set1
= XVECEXP (newpat
, 0, 1);
3098 if (((REG_P (SET_DEST (set1
))
3099 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3100 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3101 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3102 && insn_nothrow_p (i3
)
3103 && !side_effects_p (SET_SRC (set1
)))
3106 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3109 else if (((REG_P (SET_DEST (set0
))
3110 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3111 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3112 && find_reg_note (i3
, REG_UNUSED
,
3113 SUBREG_REG (SET_DEST (set0
)))))
3114 && insn_nothrow_p (i3
)
3115 && !side_effects_p (SET_SRC (set0
)))
3118 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3120 if (insn_code_number
>= 0)
3121 changed_i3_dest
= 1;
3125 /* If we were combining three insns and the result is a simple SET
3126 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3127 insns. There are two ways to do this. It can be split using a
3128 machine-specific method (like when you have an addition of a large
3129 constant) or by combine in the function find_split_point. */
3131 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3132 && asm_noperands (newpat
) < 0)
3134 rtx parallel
, m_split
, *split
;
3136 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3137 use I2DEST as a scratch register will help. In the latter case,
3138 convert I2DEST to the mode of the source of NEWPAT if we can. */
3140 m_split
= combine_split_insns (newpat
, i3
);
3142 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3143 inputs of NEWPAT. */
3145 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3146 possible to try that as a scratch reg. This would require adding
3147 more code to make it work though. */
3149 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3151 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3153 /* First try to split using the original register as a
3154 scratch register. */
3155 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3156 gen_rtvec (2, newpat
,
3157 gen_rtx_CLOBBER (VOIDmode
,
3159 m_split
= combine_split_insns (parallel
, i3
);
3161 /* If that didn't work, try changing the mode of I2DEST if
3164 && new_mode
!= GET_MODE (i2dest
)
3165 && new_mode
!= VOIDmode
3166 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3168 enum machine_mode old_mode
= GET_MODE (i2dest
);
3171 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3172 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3175 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3176 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3179 parallel
= (gen_rtx_PARALLEL
3181 gen_rtvec (2, newpat
,
3182 gen_rtx_CLOBBER (VOIDmode
,
3184 m_split
= combine_split_insns (parallel
, i3
);
3187 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3191 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3192 buf
= undobuf
.undos
;
3193 undobuf
.undos
= buf
->next
;
3194 buf
->next
= undobuf
.frees
;
3195 undobuf
.frees
= buf
;
3199 i2scratch
= m_split
!= 0;
3202 /* If recog_for_combine has discarded clobbers, try to use them
3203 again for the split. */
3204 if (m_split
== 0 && newpat_vec_with_clobbers
)
3206 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3207 m_split
= combine_split_insns (parallel
, i3
);
3210 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3212 m_split
= PATTERN (m_split
);
3213 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3214 if (insn_code_number
>= 0)
3217 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3218 && (next_real_insn (i2
) == i3
3219 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3222 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3223 newi2pat
= PATTERN (m_split
);
3225 i3set
= single_set (NEXT_INSN (m_split
));
3226 i2set
= single_set (m_split
);
3228 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3230 /* If I2 or I3 has multiple SETs, we won't know how to track
3231 register status, so don't use these insns. If I2's destination
3232 is used between I2 and I3, we also can't use these insns. */
3234 if (i2_code_number
>= 0 && i2set
&& i3set
3235 && (next_real_insn (i2
) == i3
3236 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3237 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3239 if (insn_code_number
>= 0)
3242 /* It is possible that both insns now set the destination of I3.
3243 If so, we must show an extra use of it. */
3245 if (insn_code_number
>= 0)
3247 rtx new_i3_dest
= SET_DEST (i3set
);
3248 rtx new_i2_dest
= SET_DEST (i2set
);
3250 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3251 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3252 || GET_CODE (new_i3_dest
) == SUBREG
)
3253 new_i3_dest
= XEXP (new_i3_dest
, 0);
3255 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3256 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3257 || GET_CODE (new_i2_dest
) == SUBREG
)
3258 new_i2_dest
= XEXP (new_i2_dest
, 0);
3260 if (REG_P (new_i3_dest
)
3261 && REG_P (new_i2_dest
)
3262 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3263 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3267 /* If we can split it and use I2DEST, go ahead and see if that
3268 helps things be recognized. Verify that none of the registers
3269 are set between I2 and I3. */
3270 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
3274 /* We need I2DEST in the proper mode. If it is a hard register
3275 or the only use of a pseudo, we can change its mode.
3276 Make sure we don't change a hard register to have a mode that
3277 isn't valid for it, or change the number of registers. */
3278 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3279 || GET_MODE (*split
) == VOIDmode
3280 || can_change_dest_mode (i2dest
, added_sets_2
,
3282 && (next_real_insn (i2
) == i3
3283 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3284 /* We can't overwrite I2DEST if its value is still used by
3286 && ! reg_referenced_p (i2dest
, newpat
))
3288 rtx newdest
= i2dest
;
3289 enum rtx_code split_code
= GET_CODE (*split
);
3290 enum machine_mode split_mode
= GET_MODE (*split
);
3291 bool subst_done
= false;
3292 newi2pat
= NULL_RTX
;
3296 /* Get NEWDEST as a register in the proper mode. We have already
3297 validated that we can do this. */
3298 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3300 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3301 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3304 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3305 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3309 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3310 an ASHIFT. This can occur if it was inside a PLUS and hence
3311 appeared to be a memory address. This is a kludge. */
3312 if (split_code
== MULT
3313 && CONST_INT_P (XEXP (*split
, 1))
3314 && INTVAL (XEXP (*split
, 1)) > 0
3315 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
3317 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3318 XEXP (*split
, 0), GEN_INT (i
)));
3319 /* Update split_code because we may not have a multiply
3321 split_code
= GET_CODE (*split
);
3324 #ifdef INSN_SCHEDULING
3325 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3326 be written as a ZERO_EXTEND. */
3327 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3329 #ifdef LOAD_EXTEND_OP
3330 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3331 what it really is. */
3332 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3334 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3335 SUBREG_REG (*split
)));
3338 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3339 SUBREG_REG (*split
)));
3343 /* Attempt to split binary operators using arithmetic identities. */
3344 if (BINARY_P (SET_SRC (newpat
))
3345 && split_mode
== GET_MODE (SET_SRC (newpat
))
3346 && ! side_effects_p (SET_SRC (newpat
)))
3348 rtx setsrc
= SET_SRC (newpat
);
3349 enum machine_mode mode
= GET_MODE (setsrc
);
3350 enum rtx_code code
= GET_CODE (setsrc
);
3351 rtx src_op0
= XEXP (setsrc
, 0);
3352 rtx src_op1
= XEXP (setsrc
, 1);
3354 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3355 if (rtx_equal_p (src_op0
, src_op1
))
3357 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3358 SUBST (XEXP (setsrc
, 0), newdest
);
3359 SUBST (XEXP (setsrc
, 1), newdest
);
3362 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3363 else if ((code
== PLUS
|| code
== MULT
)
3364 && GET_CODE (src_op0
) == code
3365 && GET_CODE (XEXP (src_op0
, 0)) == code
3366 && (INTEGRAL_MODE_P (mode
)
3367 || (FLOAT_MODE_P (mode
)
3368 && flag_unsafe_math_optimizations
)))
3370 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3371 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3372 rtx r
= XEXP (src_op0
, 1);
3375 /* Split both "((X op Y) op X) op Y" and
3376 "((X op Y) op Y) op X" as "T op T" where T is
3378 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3379 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3381 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3383 SUBST (XEXP (setsrc
, 0), newdest
);
3384 SUBST (XEXP (setsrc
, 1), newdest
);
3387 /* Split "((X op X) op Y) op Y)" as "T op T" where
3389 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3391 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3392 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3393 SUBST (XEXP (setsrc
, 0), newdest
);
3394 SUBST (XEXP (setsrc
, 1), newdest
);
3402 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3403 SUBST (*split
, newdest
);
3406 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3408 /* recog_for_combine might have added CLOBBERs to newi2pat.
3409 Make sure NEWPAT does not depend on the clobbered regs. */
3410 if (GET_CODE (newi2pat
) == PARALLEL
)
3411 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3412 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3414 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3415 if (reg_overlap_mentioned_p (reg
, newpat
))
3422 /* If the split point was a MULT and we didn't have one before,
3423 don't use one now. */
3424 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3425 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3429 /* Check for a case where we loaded from memory in a narrow mode and
3430 then sign extended it, but we need both registers. In that case,
3431 we have a PARALLEL with both loads from the same memory location.
3432 We can split this into a load from memory followed by a register-register
3433 copy. This saves at least one insn, more if register allocation can
3436 We cannot do this if the destination of the first assignment is a
3437 condition code register or cc0. We eliminate this case by making sure
3438 the SET_DEST and SET_SRC have the same mode.
3440 We cannot do this if the destination of the second assignment is
3441 a register that we have already assumed is zero-extended. Similarly
3442 for a SUBREG of such a register. */
3444 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3445 && GET_CODE (newpat
) == PARALLEL
3446 && XVECLEN (newpat
, 0) == 2
3447 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3448 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3449 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3450 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3451 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3452 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3453 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3454 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3456 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3457 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3458 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3460 && VEC_index (reg_stat_type
, reg_stat
,
3461 REGNO (temp
))->nonzero_bits
!= 0
3462 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3463 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3464 && (VEC_index (reg_stat_type
, reg_stat
,
3465 REGNO (temp
))->nonzero_bits
3466 != GET_MODE_MASK (word_mode
))))
3467 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3468 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3470 && VEC_index (reg_stat_type
, reg_stat
,
3471 REGNO (temp
))->nonzero_bits
!= 0
3472 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3473 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3474 && (VEC_index (reg_stat_type
, reg_stat
,
3475 REGNO (temp
))->nonzero_bits
3476 != GET_MODE_MASK (word_mode
)))))
3477 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3478 SET_SRC (XVECEXP (newpat
, 0, 1)))
3479 && ! find_reg_note (i3
, REG_UNUSED
,
3480 SET_DEST (XVECEXP (newpat
, 0, 0))))
3484 newi2pat
= XVECEXP (newpat
, 0, 0);
3485 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3486 newpat
= XVECEXP (newpat
, 0, 1);
3487 SUBST (SET_SRC (newpat
),
3488 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3489 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3491 if (i2_code_number
>= 0)
3492 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3494 if (insn_code_number
>= 0)
3498 /* Similarly, check for a case where we have a PARALLEL of two independent
3499 SETs but we started with three insns. In this case, we can do the sets
3500 as two separate insns. This case occurs when some SET allows two
3501 other insns to combine, but the destination of that SET is still live. */
3503 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3504 && GET_CODE (newpat
) == PARALLEL
3505 && XVECLEN (newpat
, 0) == 2
3506 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3507 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3508 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3509 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3510 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3511 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3512 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3514 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3515 XVECEXP (newpat
, 0, 0))
3516 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3517 XVECEXP (newpat
, 0, 1))
3518 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3519 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1))))
3521 /* We cannot split the parallel into two sets if both sets
3523 && ! (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3524 && reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1)))
3528 /* Normally, it doesn't matter which of the two is done first,
3529 but it does if one references cc0. In that case, it has to
3532 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
3534 newi2pat
= XVECEXP (newpat
, 0, 0);
3535 newpat
= XVECEXP (newpat
, 0, 1);
3540 newi2pat
= XVECEXP (newpat
, 0, 1);
3541 newpat
= XVECEXP (newpat
, 0, 0);
3544 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3546 if (i2_code_number
>= 0)
3547 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3550 /* If it still isn't recognized, fail and change things back the way they
3552 if ((insn_code_number
< 0
3553 /* Is the result a reasonable ASM_OPERANDS? */
3554 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3560 /* If we had to change another insn, make sure it is valid also. */
3561 if (undobuf
.other_insn
)
3563 CLEAR_HARD_REG_SET (newpat_used_regs
);
3565 other_pat
= PATTERN (undobuf
.other_insn
);
3566 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3569 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3577 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3578 they are adjacent to each other or not. */
3580 rtx p
= prev_nonnote_insn (i3
);
3581 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3582 && sets_cc0_p (newi2pat
))
3590 /* Only allow this combination if insn_rtx_costs reports that the
3591 replacement instructions are cheaper than the originals. */
3592 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3598 if (MAY_HAVE_DEBUG_INSNS
)
3602 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3603 if (undo
->kind
== UNDO_MODE
)
3605 rtx reg
= *undo
->where
.r
;
3606 enum machine_mode new_mode
= GET_MODE (reg
);
3607 enum machine_mode old_mode
= undo
->old_contents
.m
;
3609 /* Temporarily revert mode back. */
3610 adjust_reg_mode (reg
, old_mode
);
3612 if (reg
== i2dest
&& i2scratch
)
3614 /* If we used i2dest as a scratch register with a
3615 different mode, substitute it for the original
3616 i2src while its original mode is temporarily
3617 restored, and then clear i2scratch so that we don't
3618 do it again later. */
3619 propagate_for_debug (i2
, i3
, reg
, i2src
, false);
3621 /* Put back the new mode. */
3622 adjust_reg_mode (reg
, new_mode
);
3626 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3637 last
= undobuf
.other_insn
;
3641 /* We're dealing with a reg that changed mode but not
3642 meaning, so we want to turn it into a subreg for
3643 the new mode. However, because of REG sharing and
3644 because its mode had already changed, we have to do
3645 it in two steps. First, replace any debug uses of
3646 reg, with its original mode temporarily restored,
3647 with this copy we have created; then, replace the
3648 copy with the SUBREG of the original shared reg,
3649 once again changed to the new mode. */
3650 propagate_for_debug (first
, last
, reg
, tempreg
, false);
3651 adjust_reg_mode (reg
, new_mode
);
3652 propagate_for_debug (first
, last
, tempreg
,
3653 lowpart_subreg (old_mode
, reg
, new_mode
),
3659 /* If we will be able to accept this, we have made a
3660 change to the destination of I3. This requires us to
3661 do a few adjustments. */
3663 if (changed_i3_dest
)
3665 PATTERN (i3
) = newpat
;
3666 adjust_for_new_dest (i3
);
3669 /* We now know that we can do this combination. Merge the insns and
3670 update the status of registers and LOG_LINKS. */
3672 if (undobuf
.other_insn
)
3676 PATTERN (undobuf
.other_insn
) = other_pat
;
3678 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3679 are still valid. Then add any non-duplicate notes added by
3680 recog_for_combine. */
3681 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3683 next
= XEXP (note
, 1);
3685 if (REG_NOTE_KIND (note
) == REG_UNUSED
3686 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3687 remove_note (undobuf
.other_insn
, note
);
3690 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3691 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3700 /* I3 now uses what used to be its destination and which is now
3701 I2's destination. This requires us to do a few adjustments. */
3702 PATTERN (i3
) = newpat
;
3703 adjust_for_new_dest (i3
);
3705 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3708 However, some later insn might be using I2's dest and have
3709 a LOG_LINK pointing at I3. We must remove this link.
3710 The simplest way to remove the link is to point it at I1,
3711 which we know will be a NOTE. */
3713 /* newi2pat is usually a SET here; however, recog_for_combine might
3714 have added some clobbers. */
3715 if (GET_CODE (newi2pat
) == PARALLEL
)
3716 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3718 ni2dest
= SET_DEST (newi2pat
);
3720 for (insn
= NEXT_INSN (i3
);
3721 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3722 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3723 insn
= NEXT_INSN (insn
))
3725 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3727 for (link
= LOG_LINKS (insn
); link
;
3728 link
= XEXP (link
, 1))
3729 if (XEXP (link
, 0) == i3
)
3730 XEXP (link
, 0) = i1
;
3738 rtx i3notes
, i2notes
, i1notes
= 0;
3739 rtx i3links
, i2links
, i1links
= 0;
3742 /* Compute which registers we expect to eliminate. newi2pat may be setting
3743 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3744 same as i3dest, in which case newi2pat may be setting i1dest. */
3745 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3746 || i2dest_in_i2src
|| i2dest_in_i1src
3749 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
3750 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3754 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3756 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3757 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3759 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3761 /* Ensure that we do not have something that should not be shared but
3762 occurs multiple times in the new insns. Check this by first
3763 resetting all the `used' flags and then copying anything is shared. */
3765 reset_used_flags (i3notes
);
3766 reset_used_flags (i2notes
);
3767 reset_used_flags (i1notes
);
3768 reset_used_flags (newpat
);
3769 reset_used_flags (newi2pat
);
3770 if (undobuf
.other_insn
)
3771 reset_used_flags (PATTERN (undobuf
.other_insn
));
3773 i3notes
= copy_rtx_if_shared (i3notes
);
3774 i2notes
= copy_rtx_if_shared (i2notes
);
3775 i1notes
= copy_rtx_if_shared (i1notes
);
3776 newpat
= copy_rtx_if_shared (newpat
);
3777 newi2pat
= copy_rtx_if_shared (newi2pat
);
3778 if (undobuf
.other_insn
)
3779 reset_used_flags (PATTERN (undobuf
.other_insn
));
3781 INSN_CODE (i3
) = insn_code_number
;
3782 PATTERN (i3
) = newpat
;
3784 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
3786 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
3788 reset_used_flags (call_usage
);
3789 call_usage
= copy_rtx (call_usage
);
3792 replace_rtx (call_usage
, i2dest
, i2src
);
3795 replace_rtx (call_usage
, i1dest
, i1src
);
3797 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
3800 if (undobuf
.other_insn
)
3801 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
3803 /* We had one special case above where I2 had more than one set and
3804 we replaced a destination of one of those sets with the destination
3805 of I3. In that case, we have to update LOG_LINKS of insns later
3806 in this basic block. Note that this (expensive) case is rare.
3808 Also, in this case, we must pretend that all REG_NOTEs for I2
3809 actually came from I3, so that REG_UNUSED notes from I2 will be
3810 properly handled. */
3812 if (i3_subst_into_i2
)
3814 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
3815 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
3816 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
3817 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
3818 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
3819 && ! find_reg_note (i2
, REG_UNUSED
,
3820 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
3821 for (temp
= NEXT_INSN (i2
);
3822 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3823 || BB_HEAD (this_basic_block
) != temp
);
3824 temp
= NEXT_INSN (temp
))
3825 if (temp
!= i3
&& INSN_P (temp
))
3826 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
3827 if (XEXP (link
, 0) == i2
)
3828 XEXP (link
, 0) = i3
;
3833 while (XEXP (link
, 1))
3834 link
= XEXP (link
, 1);
3835 XEXP (link
, 1) = i2notes
;
3849 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
3850 propagate_for_debug (i2
, i3
, i2dest
, i2src
, false);
3851 INSN_CODE (i2
) = i2_code_number
;
3852 PATTERN (i2
) = newi2pat
;
3856 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
3857 propagate_for_debug (i2
, i3
, i2dest
, i2src
, i3_subst_into_i2
);
3858 SET_INSN_DELETED (i2
);
3865 if (MAY_HAVE_DEBUG_INSNS
)
3866 propagate_for_debug (i1
, i3
, i1dest
, i1src
, false);
3867 SET_INSN_DELETED (i1
);
3870 /* Get death notes for everything that is now used in either I3 or
3871 I2 and used to die in a previous insn. If we built two new
3872 patterns, move from I1 to I2 then I2 to I3 so that we get the
3873 proper movement on registers that I2 modifies. */
3877 move_deaths (newi2pat
, NULL_RTX
, DF_INSN_LUID (i1
), i2
, &midnotes
);
3878 move_deaths (newpat
, newi2pat
, DF_INSN_LUID (i1
), i3
, &midnotes
);
3881 move_deaths (newpat
, NULL_RTX
, i1
? DF_INSN_LUID (i1
) : DF_INSN_LUID (i2
),
3884 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3886 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
3889 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
3892 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
3895 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3898 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3899 know these are REG_UNUSED and want them to go to the desired insn,
3900 so we always pass it as i3. */
3902 if (newi2pat
&& new_i2_notes
)
3903 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3906 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3908 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3909 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3910 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3911 in that case, it might delete I2. Similarly for I2 and I1.
3912 Show an additional death due to the REG_DEAD note we make here. If
3913 we discard it in distribute_notes, we will decrement it again. */
3917 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
3918 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
3920 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
3922 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
3924 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3928 if (i2dest_in_i2src
)
3930 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3931 distribute_notes (alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
),
3932 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3934 distribute_notes (alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
),
3935 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3936 NULL_RTX
, NULL_RTX
);
3939 if (i1dest_in_i1src
)
3941 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3942 distribute_notes (alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
),
3943 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3945 distribute_notes (alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
),
3946 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3947 NULL_RTX
, NULL_RTX
);
3950 distribute_links (i3links
);
3951 distribute_links (i2links
);
3952 distribute_links (i1links
);
3957 rtx i2_insn
= 0, i2_val
= 0, set
;
3959 /* The insn that used to set this register doesn't exist, and
3960 this life of the register may not exist either. See if one of
3961 I3's links points to an insn that sets I2DEST. If it does,
3962 that is now the last known value for I2DEST. If we don't update
3963 this and I2 set the register to a value that depended on its old
3964 contents, we will get confused. If this insn is used, thing
3965 will be set correctly in combine_instructions. */
3967 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3968 if ((set
= single_set (XEXP (link
, 0))) != 0
3969 && rtx_equal_p (i2dest
, SET_DEST (set
)))
3970 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
3972 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
3974 /* If the reg formerly set in I2 died only once and that was in I3,
3975 zero its use count so it won't make `reload' do any work. */
3977 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
3978 && ! i2dest_in_i2src
)
3980 regno
= REGNO (i2dest
);
3981 INC_REG_N_SETS (regno
, -1);
3985 if (i1
&& REG_P (i1dest
))
3988 rtx i1_insn
= 0, i1_val
= 0, set
;
3990 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3991 if ((set
= single_set (XEXP (link
, 0))) != 0
3992 && rtx_equal_p (i1dest
, SET_DEST (set
)))
3993 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
3995 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
3997 regno
= REGNO (i1dest
);
3998 if (! added_sets_1
&& ! i1dest_in_i1src
)
3999 INC_REG_N_SETS (regno
, -1);
4002 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4003 been made to this insn. The order of
4004 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4005 can affect nonzero_bits of newpat */
4007 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4008 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4011 if (undobuf
.other_insn
!= NULL_RTX
)
4015 fprintf (dump_file
, "modifying other_insn ");
4016 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4018 df_insn_rescan (undobuf
.other_insn
);
4021 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4025 fprintf (dump_file
, "modifying insn i1 ");
4026 dump_insn_slim (dump_file
, i1
);
4028 df_insn_rescan (i1
);
4031 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4035 fprintf (dump_file
, "modifying insn i2 ");
4036 dump_insn_slim (dump_file
, i2
);
4038 df_insn_rescan (i2
);
4041 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4045 fprintf (dump_file
, "modifying insn i3 ");
4046 dump_insn_slim (dump_file
, i3
);
4048 df_insn_rescan (i3
);
4051 /* Set new_direct_jump_p if a new return or simple jump instruction
4052 has been created. Adjust the CFG accordingly. */
4054 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4056 *new_direct_jump_p
= 1;
4057 mark_jump_label (PATTERN (i3
), i3
, 0);
4058 update_cfg_for_uncondjump (i3
);
4061 if (undobuf
.other_insn
!= NULL_RTX
4062 && (returnjump_p (undobuf
.other_insn
)
4063 || any_uncondjump_p (undobuf
.other_insn
)))
4065 *new_direct_jump_p
= 1;
4066 update_cfg_for_uncondjump (undobuf
.other_insn
);
4069 /* A noop might also need cleaning up of CFG, if it comes from the
4070 simplification of a jump. */
4071 if (GET_CODE (newpat
) == SET
4072 && SET_SRC (newpat
) == pc_rtx
4073 && SET_DEST (newpat
) == pc_rtx
)
4075 *new_direct_jump_p
= 1;
4076 update_cfg_for_uncondjump (i3
);
4079 combine_successes
++;
4082 if (added_links_insn
4083 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4084 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4085 return added_links_insn
;
4087 return newi2pat
? i2
: i3
;
4090 /* Undo all the modifications recorded in undobuf. */
4095 struct undo
*undo
, *next
;
4097 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4103 *undo
->where
.r
= undo
->old_contents
.r
;
4106 *undo
->where
.i
= undo
->old_contents
.i
;
4109 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4115 undo
->next
= undobuf
.frees
;
4116 undobuf
.frees
= undo
;
4122 /* We've committed to accepting the changes we made. Move all
4123 of the undos to the free list. */
4128 struct undo
*undo
, *next
;
4130 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4133 undo
->next
= undobuf
.frees
;
4134 undobuf
.frees
= undo
;
4139 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4140 where we have an arithmetic expression and return that point. LOC will
4143 try_combine will call this function to see if an insn can be split into
4147 find_split_point (rtx
*loc
, rtx insn
)
4150 enum rtx_code code
= GET_CODE (x
);
4152 unsigned HOST_WIDE_INT len
= 0;
4153 HOST_WIDE_INT pos
= 0;
4155 rtx inner
= NULL_RTX
;
4157 /* First special-case some codes. */
4161 #ifdef INSN_SCHEDULING
4162 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4164 if (MEM_P (SUBREG_REG (x
)))
4167 return find_split_point (&SUBREG_REG (x
), insn
);
4171 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4172 using LO_SUM and HIGH. */
4173 if (GET_CODE (XEXP (x
, 0)) == CONST
4174 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4176 enum machine_mode address_mode
4177 = targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (x
));
4180 gen_rtx_LO_SUM (address_mode
,
4181 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4183 return &XEXP (XEXP (x
, 0), 0);
4187 /* If we have a PLUS whose second operand is a constant and the
4188 address is not valid, perhaps will can split it up using
4189 the machine-specific way to split large constants. We use
4190 the first pseudo-reg (one of the virtual regs) as a placeholder;
4191 it will not remain in the result. */
4192 if (GET_CODE (XEXP (x
, 0)) == PLUS
4193 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4194 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4195 MEM_ADDR_SPACE (x
)))
4197 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4198 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4202 /* This should have produced two insns, each of which sets our
4203 placeholder. If the source of the second is a valid address,
4204 we can make put both sources together and make a split point
4208 && NEXT_INSN (seq
) != NULL_RTX
4209 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4210 && NONJUMP_INSN_P (seq
)
4211 && GET_CODE (PATTERN (seq
)) == SET
4212 && SET_DEST (PATTERN (seq
)) == reg
4213 && ! reg_mentioned_p (reg
,
4214 SET_SRC (PATTERN (seq
)))
4215 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4216 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4217 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4218 && memory_address_addr_space_p
4219 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4220 MEM_ADDR_SPACE (x
)))
4222 rtx src1
= SET_SRC (PATTERN (seq
));
4223 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4225 /* Replace the placeholder in SRC2 with SRC1. If we can
4226 find where in SRC2 it was placed, that can become our
4227 split point and we can replace this address with SRC2.
4228 Just try two obvious places. */
4230 src2
= replace_rtx (src2
, reg
, src1
);
4232 if (XEXP (src2
, 0) == src1
)
4233 split
= &XEXP (src2
, 0);
4234 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4235 && XEXP (XEXP (src2
, 0), 0) == src1
)
4236 split
= &XEXP (XEXP (src2
, 0), 0);
4240 SUBST (XEXP (x
, 0), src2
);
4245 /* If that didn't work, perhaps the first operand is complex and
4246 needs to be computed separately, so make a split point there.
4247 This will occur on machines that just support REG + CONST
4248 and have a constant moved through some previous computation. */
4250 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4251 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4252 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4253 return &XEXP (XEXP (x
, 0), 0);
4256 /* If we have a PLUS whose first operand is complex, try computing it
4257 separately by making a split there. */
4258 if (GET_CODE (XEXP (x
, 0)) == PLUS
4259 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4261 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4262 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4263 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4264 return &XEXP (XEXP (x
, 0), 0);
4269 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4270 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4271 we need to put the operand into a register. So split at that
4274 if (SET_DEST (x
) == cc0_rtx
4275 && GET_CODE (SET_SRC (x
)) != COMPARE
4276 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4277 && !OBJECT_P (SET_SRC (x
))
4278 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4279 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4280 return &SET_SRC (x
);
4283 /* See if we can split SET_SRC as it stands. */
4284 split
= find_split_point (&SET_SRC (x
), insn
);
4285 if (split
&& split
!= &SET_SRC (x
))
4288 /* See if we can split SET_DEST as it stands. */
4289 split
= find_split_point (&SET_DEST (x
), insn
);
4290 if (split
&& split
!= &SET_DEST (x
))
4293 /* See if this is a bitfield assignment with everything constant. If
4294 so, this is an IOR of an AND, so split it into that. */
4295 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4296 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
4297 <= HOST_BITS_PER_WIDE_INT
)
4298 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4299 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4300 && CONST_INT_P (SET_SRC (x
))
4301 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4302 + INTVAL (XEXP (SET_DEST (x
), 2)))
4303 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
4304 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4306 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4307 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4308 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4309 rtx dest
= XEXP (SET_DEST (x
), 0);
4310 enum machine_mode mode
= GET_MODE (dest
);
4311 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
4314 if (BITS_BIG_ENDIAN
)
4315 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
4317 or_mask
= gen_int_mode (src
<< pos
, mode
);
4320 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4323 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4325 simplify_gen_binary (IOR
, mode
,
4326 simplify_gen_binary (AND
, mode
,
4331 SUBST (SET_DEST (x
), dest
);
4333 split
= find_split_point (&SET_SRC (x
), insn
);
4334 if (split
&& split
!= &SET_SRC (x
))
4338 /* Otherwise, see if this is an operation that we can split into two.
4339 If so, try to split that. */
4340 code
= GET_CODE (SET_SRC (x
));
4345 /* If we are AND'ing with a large constant that is only a single
4346 bit and the result is only being used in a context where we
4347 need to know if it is zero or nonzero, replace it with a bit
4348 extraction. This will avoid the large constant, which might
4349 have taken more than one insn to make. If the constant were
4350 not a valid argument to the AND but took only one insn to make,
4351 this is no worse, but if it took more than one insn, it will
4354 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4355 && REG_P (XEXP (SET_SRC (x
), 0))
4356 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4357 && REG_P (SET_DEST (x
))
4358 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4359 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4360 && XEXP (*split
, 0) == SET_DEST (x
)
4361 && XEXP (*split
, 1) == const0_rtx
)
4363 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4364 XEXP (SET_SRC (x
), 0),
4365 pos
, NULL_RTX
, 1, 1, 0, 0);
4366 if (extraction
!= 0)
4368 SUBST (SET_SRC (x
), extraction
);
4369 return find_split_point (loc
, insn
);
4375 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4376 is known to be on, this can be converted into a NEG of a shift. */
4377 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4378 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4379 && 1 <= (pos
= exact_log2
4380 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4381 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4383 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4387 gen_rtx_LSHIFTRT (mode
,
4388 XEXP (SET_SRC (x
), 0),
4391 split
= find_split_point (&SET_SRC (x
), insn
);
4392 if (split
&& split
!= &SET_SRC (x
))
4398 inner
= XEXP (SET_SRC (x
), 0);
4400 /* We can't optimize if either mode is a partial integer
4401 mode as we don't know how many bits are significant
4403 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4404 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4408 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
4414 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4415 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4417 inner
= XEXP (SET_SRC (x
), 0);
4418 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4419 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4421 if (BITS_BIG_ENDIAN
)
4422 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
4423 unsignedp
= (code
== ZERO_EXTRACT
);
4431 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
4433 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4435 /* For unsigned, we have a choice of a shift followed by an
4436 AND or two shifts. Use two shifts for field sizes where the
4437 constant might be too large. We assume here that we can
4438 always at least get 8-bit constants in an AND insn, which is
4439 true for every current RISC. */
4441 if (unsignedp
&& len
<= 8)
4446 (mode
, gen_lowpart (mode
, inner
),
4448 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
4450 split
= find_split_point (&SET_SRC (x
), insn
);
4451 if (split
&& split
!= &SET_SRC (x
))
4458 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4459 gen_rtx_ASHIFT (mode
,
4460 gen_lowpart (mode
, inner
),
4461 GEN_INT (GET_MODE_BITSIZE (mode
)
4463 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
4465 split
= find_split_point (&SET_SRC (x
), insn
);
4466 if (split
&& split
!= &SET_SRC (x
))
4471 /* See if this is a simple operation with a constant as the second
4472 operand. It might be that this constant is out of range and hence
4473 could be used as a split point. */
4474 if (BINARY_P (SET_SRC (x
))
4475 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4476 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4477 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4478 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4479 return &XEXP (SET_SRC (x
), 1);
4481 /* Finally, see if this is a simple operation with its first operand
4482 not in a register. The operation might require this operand in a
4483 register, so return it as a split point. We can always do this
4484 because if the first operand were another operation, we would have
4485 already found it as a split point. */
4486 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4487 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4488 return &XEXP (SET_SRC (x
), 0);
4494 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4495 it is better to write this as (not (ior A B)) so we can split it.
4496 Similarly for IOR. */
4497 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4500 gen_rtx_NOT (GET_MODE (x
),
4501 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4503 XEXP (XEXP (x
, 0), 0),
4504 XEXP (XEXP (x
, 1), 0))));
4505 return find_split_point (loc
, insn
);
4508 /* Many RISC machines have a large set of logical insns. If the
4509 second operand is a NOT, put it first so we will try to split the
4510 other operand first. */
4511 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4513 rtx tem
= XEXP (x
, 0);
4514 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4515 SUBST (XEXP (x
, 1), tem
);
4523 /* Otherwise, select our actions depending on our rtx class. */
4524 switch (GET_RTX_CLASS (code
))
4526 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4528 split
= find_split_point (&XEXP (x
, 2), insn
);
4531 /* ... fall through ... */
4533 case RTX_COMM_ARITH
:
4535 case RTX_COMM_COMPARE
:
4536 split
= find_split_point (&XEXP (x
, 1), insn
);
4539 /* ... fall through ... */
4541 /* Some machines have (and (shift ...) ...) insns. If X is not
4542 an AND, but XEXP (X, 0) is, use it as our split point. */
4543 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4544 return &XEXP (x
, 0);
4546 split
= find_split_point (&XEXP (x
, 0), insn
);
4552 /* Otherwise, we don't have a split point. */
4557 /* Throughout X, replace FROM with TO, and return the result.
4558 The result is TO if X is FROM;
4559 otherwise the result is X, but its contents may have been modified.
4560 If they were modified, a record was made in undobuf so that
4561 undo_all will (among other things) return X to its original state.
4563 If the number of changes necessary is too much to record to undo,
4564 the excess changes are not made, so the result is invalid.
4565 The changes already made can still be undone.
4566 undobuf.num_undo is incremented for such changes, so by testing that
4567 the caller can tell whether the result is valid.
4569 `n_occurrences' is incremented each time FROM is replaced.
4571 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4573 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4574 by copying if `n_occurrences' is nonzero. */
4577 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
4579 enum rtx_code code
= GET_CODE (x
);
4580 enum machine_mode op0_mode
= VOIDmode
;
4585 /* Two expressions are equal if they are identical copies of a shared
4586 RTX or if they are both registers with the same register number
4589 #define COMBINE_RTX_EQUAL_P(X,Y) \
4591 || (REG_P (X) && REG_P (Y) \
4592 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4594 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4597 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4600 /* If X and FROM are the same register but different modes, they
4601 will not have been seen as equal above. However, the log links code
4602 will make a LOG_LINKS entry for that case. If we do nothing, we
4603 will try to rerecognize our original insn and, when it succeeds,
4604 we will delete the feeding insn, which is incorrect.
4606 So force this insn not to match in this (rare) case. */
4607 if (! in_dest
&& code
== REG
&& REG_P (from
)
4608 && reg_overlap_mentioned_p (x
, from
))
4609 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4611 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4612 of which may contain things that can be combined. */
4613 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4616 /* It is possible to have a subexpression appear twice in the insn.
4617 Suppose that FROM is a register that appears within TO.
4618 Then, after that subexpression has been scanned once by `subst',
4619 the second time it is scanned, TO may be found. If we were
4620 to scan TO here, we would find FROM within it and create a
4621 self-referent rtl structure which is completely wrong. */
4622 if (COMBINE_RTX_EQUAL_P (x
, to
))
4625 /* Parallel asm_operands need special attention because all of the
4626 inputs are shared across the arms. Furthermore, unsharing the
4627 rtl results in recognition failures. Failure to handle this case
4628 specially can result in circular rtl.
4630 Solve this by doing a normal pass across the first entry of the
4631 parallel, and only processing the SET_DESTs of the subsequent
4634 if (code
== PARALLEL
4635 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4636 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4638 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
4640 /* If this substitution failed, this whole thing fails. */
4641 if (GET_CODE (new_rtx
) == CLOBBER
4642 && XEXP (new_rtx
, 0) == const0_rtx
)
4645 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4647 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4649 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4652 && GET_CODE (dest
) != CC0
4653 && GET_CODE (dest
) != PC
)
4655 new_rtx
= subst (dest
, from
, to
, 0, unique_copy
);
4657 /* If this substitution failed, this whole thing fails. */
4658 if (GET_CODE (new_rtx
) == CLOBBER
4659 && XEXP (new_rtx
, 0) == const0_rtx
)
4662 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
4668 len
= GET_RTX_LENGTH (code
);
4669 fmt
= GET_RTX_FORMAT (code
);
4671 /* We don't need to process a SET_DEST that is a register, CC0,
4672 or PC, so set up to skip this common case. All other cases
4673 where we want to suppress replacing something inside a
4674 SET_SRC are handled via the IN_DEST operand. */
4676 && (REG_P (SET_DEST (x
))
4677 || GET_CODE (SET_DEST (x
)) == CC0
4678 || GET_CODE (SET_DEST (x
)) == PC
))
4681 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4684 op0_mode
= GET_MODE (XEXP (x
, 0));
4686 for (i
= 0; i
< len
; i
++)
4691 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4693 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
4695 new_rtx
= (unique_copy
&& n_occurrences
4696 ? copy_rtx (to
) : to
);
4701 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0,
4704 /* If this substitution failed, this whole thing
4706 if (GET_CODE (new_rtx
) == CLOBBER
4707 && XEXP (new_rtx
, 0) == const0_rtx
)
4711 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
4714 else if (fmt
[i
] == 'e')
4716 /* If this is a register being set, ignore it. */
4717 new_rtx
= XEXP (x
, i
);
4720 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
4722 || code
== STRICT_LOW_PART
))
4725 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
4727 /* In general, don't install a subreg involving two
4728 modes not tieable. It can worsen register
4729 allocation, and can even make invalid reload
4730 insns, since the reg inside may need to be copied
4731 from in the outside mode, and that may be invalid
4732 if it is an fp reg copied in integer mode.
4734 We allow two exceptions to this: It is valid if
4735 it is inside another SUBREG and the mode of that
4736 SUBREG and the mode of the inside of TO is
4737 tieable and it is valid if X is a SET that copies
4740 if (GET_CODE (to
) == SUBREG
4741 && ! MODES_TIEABLE_P (GET_MODE (to
),
4742 GET_MODE (SUBREG_REG (to
)))
4743 && ! (code
== SUBREG
4744 && MODES_TIEABLE_P (GET_MODE (x
),
4745 GET_MODE (SUBREG_REG (to
))))
4747 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
4750 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
4752 #ifdef CANNOT_CHANGE_MODE_CLASS
4755 && REGNO (to
) < FIRST_PSEUDO_REGISTER
4756 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
4759 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
4762 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
4766 /* If we are in a SET_DEST, suppress most cases unless we
4767 have gone inside a MEM, in which case we want to
4768 simplify the address. We assume here that things that
4769 are actually part of the destination have their inner
4770 parts in the first expression. This is true for SUBREG,
4771 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4772 things aside from REG and MEM that should appear in a
4774 new_rtx
= subst (XEXP (x
, i
), from
, to
,
4776 && (code
== SUBREG
|| code
== STRICT_LOW_PART
4777 || code
== ZERO_EXTRACT
))
4779 && i
== 0), unique_copy
);
4781 /* If we found that we will have to reject this combination,
4782 indicate that by returning the CLOBBER ourselves, rather than
4783 an expression containing it. This will speed things up as
4784 well as prevent accidents where two CLOBBERs are considered
4785 to be equal, thus producing an incorrect simplification. */
4787 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
4790 if (GET_CODE (x
) == SUBREG
4791 && (CONST_INT_P (new_rtx
)
4792 || GET_CODE (new_rtx
) == CONST_DOUBLE
))
4794 enum machine_mode mode
= GET_MODE (x
);
4796 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
4797 GET_MODE (SUBREG_REG (x
)),
4800 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
4802 else if (CONST_INT_P (new_rtx
)
4803 && GET_CODE (x
) == ZERO_EXTEND
)
4805 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
4806 new_rtx
, GET_MODE (XEXP (x
, 0)));
4810 SUBST (XEXP (x
, i
), new_rtx
);
4815 /* Check if we are loading something from the constant pool via float
4816 extension; in this case we would undo compress_float_constant
4817 optimization and degenerate constant load to an immediate value. */
4818 if (GET_CODE (x
) == FLOAT_EXTEND
4819 && MEM_P (XEXP (x
, 0))
4820 && MEM_READONLY_P (XEXP (x
, 0)))
4822 rtx tmp
= avoid_constant_pool_reference (x
);
4827 /* Try to simplify X. If the simplification changed the code, it is likely
4828 that further simplification will help, so loop, but limit the number
4829 of repetitions that will be performed. */
4831 for (i
= 0; i
< 4; i
++)
4833 /* If X is sufficiently simple, don't bother trying to do anything
4835 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
4836 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
4838 if (GET_CODE (x
) == code
)
4841 code
= GET_CODE (x
);
4843 /* We no longer know the original mode of operand 0 since we
4844 have changed the form of X) */
4845 op0_mode
= VOIDmode
;
4851 /* Simplify X, a piece of RTL. We just operate on the expression at the
4852 outer level; call `subst' to simplify recursively. Return the new
4855 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4856 if we are inside a SET_DEST. */
4859 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
4861 enum rtx_code code
= GET_CODE (x
);
4862 enum machine_mode mode
= GET_MODE (x
);
4866 /* If this is a commutative operation, put a constant last and a complex
4867 expression first. We don't need to do this for comparisons here. */
4868 if (COMMUTATIVE_ARITH_P (x
)
4869 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
4872 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4873 SUBST (XEXP (x
, 1), temp
);
4876 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4877 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4878 things. Check for cases where both arms are testing the same
4881 Don't do anything if all operands are very simple. */
4884 && ((!OBJECT_P (XEXP (x
, 0))
4885 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4886 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
4887 || (!OBJECT_P (XEXP (x
, 1))
4888 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
4889 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
4891 && (!OBJECT_P (XEXP (x
, 0))
4892 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4893 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
4895 rtx cond
, true_rtx
, false_rtx
;
4897 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
4899 /* If everything is a comparison, what we have is highly unlikely
4900 to be simpler, so don't use it. */
4901 && ! (COMPARISON_P (x
)
4902 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
4904 rtx cop1
= const0_rtx
;
4905 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
4907 if (cond_code
== NE
&& COMPARISON_P (cond
))
4910 /* Simplify the alternative arms; this may collapse the true and
4911 false arms to store-flag values. Be careful to use copy_rtx
4912 here since true_rtx or false_rtx might share RTL with x as a
4913 result of the if_then_else_cond call above. */
4914 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
4915 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
4917 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4918 is unlikely to be simpler. */
4919 if (general_operand (true_rtx
, VOIDmode
)
4920 && general_operand (false_rtx
, VOIDmode
))
4922 enum rtx_code reversed
;
4924 /* Restarting if we generate a store-flag expression will cause
4925 us to loop. Just drop through in this case. */
4927 /* If the result values are STORE_FLAG_VALUE and zero, we can
4928 just make the comparison operation. */
4929 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4930 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
4932 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4933 && ((reversed
= reversed_comparison_code_parts
4934 (cond_code
, cond
, cop1
, NULL
))
4936 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
4939 /* Likewise, we can make the negate of a comparison operation
4940 if the result values are - STORE_FLAG_VALUE and zero. */
4941 else if (CONST_INT_P (true_rtx
)
4942 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
4943 && false_rtx
== const0_rtx
)
4944 x
= simplify_gen_unary (NEG
, mode
,
4945 simplify_gen_relational (cond_code
,
4949 else if (CONST_INT_P (false_rtx
)
4950 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
4951 && true_rtx
== const0_rtx
4952 && ((reversed
= reversed_comparison_code_parts
4953 (cond_code
, cond
, cop1
, NULL
))
4955 x
= simplify_gen_unary (NEG
, mode
,
4956 simplify_gen_relational (reversed
,
4961 return gen_rtx_IF_THEN_ELSE (mode
,
4962 simplify_gen_relational (cond_code
,
4967 true_rtx
, false_rtx
);
4969 code
= GET_CODE (x
);
4970 op0_mode
= VOIDmode
;
4975 /* Try to fold this expression in case we have constants that weren't
4978 switch (GET_RTX_CLASS (code
))
4981 if (op0_mode
== VOIDmode
)
4982 op0_mode
= GET_MODE (XEXP (x
, 0));
4983 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
4986 case RTX_COMM_COMPARE
:
4988 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
4989 if (cmp_mode
== VOIDmode
)
4991 cmp_mode
= GET_MODE (XEXP (x
, 1));
4992 if (cmp_mode
== VOIDmode
)
4993 cmp_mode
= op0_mode
;
4995 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
4996 XEXP (x
, 0), XEXP (x
, 1));
4999 case RTX_COMM_ARITH
:
5001 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5003 case RTX_BITFIELD_OPS
:
5005 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5006 XEXP (x
, 1), XEXP (x
, 2));
5015 code
= GET_CODE (temp
);
5016 op0_mode
= VOIDmode
;
5017 mode
= GET_MODE (temp
);
5020 /* First see if we can apply the inverse distributive law. */
5021 if (code
== PLUS
|| code
== MINUS
5022 || code
== AND
|| code
== IOR
|| code
== XOR
)
5024 x
= apply_distributive_law (x
);
5025 code
= GET_CODE (x
);
5026 op0_mode
= VOIDmode
;
5029 /* If CODE is an associative operation not otherwise handled, see if we
5030 can associate some operands. This can win if they are constants or
5031 if they are logically related (i.e. (a & b) & a). */
5032 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5033 || code
== AND
|| code
== IOR
|| code
== XOR
5034 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5035 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5036 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5038 if (GET_CODE (XEXP (x
, 0)) == code
)
5040 rtx other
= XEXP (XEXP (x
, 0), 0);
5041 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5042 rtx inner_op1
= XEXP (x
, 1);
5045 /* Make sure we pass the constant operand if any as the second
5046 one if this is a commutative operation. */
5047 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5049 rtx tem
= inner_op0
;
5050 inner_op0
= inner_op1
;
5053 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5054 : code
== DIV
? MULT
5056 mode
, inner_op0
, inner_op1
);
5058 /* For commutative operations, try the other pair if that one
5060 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5062 other
= XEXP (XEXP (x
, 0), 1);
5063 inner
= simplify_binary_operation (code
, mode
,
5064 XEXP (XEXP (x
, 0), 0),
5069 return simplify_gen_binary (code
, mode
, other
, inner
);
5073 /* A little bit of algebraic simplification here. */
5077 /* Ensure that our address has any ASHIFTs converted to MULT in case
5078 address-recognizing predicates are called later. */
5079 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5080 SUBST (XEXP (x
, 0), temp
);
5084 if (op0_mode
== VOIDmode
)
5085 op0_mode
= GET_MODE (SUBREG_REG (x
));
5087 /* See if this can be moved to simplify_subreg. */
5088 if (CONSTANT_P (SUBREG_REG (x
))
5089 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5090 /* Don't call gen_lowpart if the inner mode
5091 is VOIDmode and we cannot simplify it, as SUBREG without
5092 inner mode is invalid. */
5093 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5094 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5095 return gen_lowpart (mode
, SUBREG_REG (x
));
5097 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5101 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5107 /* Don't change the mode of the MEM if that would change the meaning
5109 if (MEM_P (SUBREG_REG (x
))
5110 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5111 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
5112 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5114 /* Note that we cannot do any narrowing for non-constants since
5115 we might have been counting on using the fact that some bits were
5116 zero. We now do this in the SET. */
5121 temp
= expand_compound_operation (XEXP (x
, 0));
5123 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5124 replaced by (lshiftrt X C). This will convert
5125 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5127 if (GET_CODE (temp
) == ASHIFTRT
5128 && CONST_INT_P (XEXP (temp
, 1))
5129 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5130 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5131 INTVAL (XEXP (temp
, 1)));
5133 /* If X has only a single bit that might be nonzero, say, bit I, convert
5134 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5135 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5136 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5137 or a SUBREG of one since we'd be making the expression more
5138 complex if it was just a register. */
5141 && ! (GET_CODE (temp
) == SUBREG
5142 && REG_P (SUBREG_REG (temp
)))
5143 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5145 rtx temp1
= simplify_shift_const
5146 (NULL_RTX
, ASHIFTRT
, mode
,
5147 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5148 GET_MODE_BITSIZE (mode
) - 1 - i
),
5149 GET_MODE_BITSIZE (mode
) - 1 - i
);
5151 /* If all we did was surround TEMP with the two shifts, we
5152 haven't improved anything, so don't use it. Otherwise,
5153 we are better off with TEMP1. */
5154 if (GET_CODE (temp1
) != ASHIFTRT
5155 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5156 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5162 /* We can't handle truncation to a partial integer mode here
5163 because we don't know the real bitsize of the partial
5165 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5168 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5170 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5171 GET_MODE_MASK (mode
), 0));
5173 /* We can truncate a constant value and return it. */
5174 if (CONST_INT_P (XEXP (x
, 0)))
5175 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5177 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5178 whose value is a comparison can be replaced with a subreg if
5179 STORE_FLAG_VALUE permits. */
5180 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5181 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5182 && (temp
= get_last_value (XEXP (x
, 0)))
5183 && COMPARISON_P (temp
))
5184 return gen_lowpart (mode
, XEXP (x
, 0));
5188 /* (const (const X)) can become (const X). Do it this way rather than
5189 returning the inner CONST since CONST can be shared with a
5191 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5192 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5197 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5198 can add in an offset. find_split_point will split this address up
5199 again if it doesn't match. */
5200 if (GET_CODE (XEXP (x
, 0)) == HIGH
5201 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5207 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5208 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5209 bit-field and can be replaced by either a sign_extend or a
5210 sign_extract. The `and' may be a zero_extend and the two
5211 <c>, -<c> constants may be reversed. */
5212 if (GET_CODE (XEXP (x
, 0)) == XOR
5213 && CONST_INT_P (XEXP (x
, 1))
5214 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5215 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5216 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5217 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
5218 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5219 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5220 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5221 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5222 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5223 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5224 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5225 == (unsigned int) i
+ 1))))
5226 return simplify_shift_const
5227 (NULL_RTX
, ASHIFTRT
, mode
,
5228 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5229 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5230 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
5231 GET_MODE_BITSIZE (mode
) - (i
+ 1));
5233 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5234 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5235 the bitsize of the mode - 1. This allows simplification of
5236 "a = (b & 8) == 0;" */
5237 if (XEXP (x
, 1) == constm1_rtx
5238 && !REG_P (XEXP (x
, 0))
5239 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5240 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5241 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5242 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5243 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5244 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5245 GET_MODE_BITSIZE (mode
) - 1),
5246 GET_MODE_BITSIZE (mode
) - 1);
5248 /* If we are adding two things that have no bits in common, convert
5249 the addition into an IOR. This will often be further simplified,
5250 for example in cases like ((a & 1) + (a & 2)), which can
5253 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5254 && (nonzero_bits (XEXP (x
, 0), mode
)
5255 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5257 /* Try to simplify the expression further. */
5258 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5259 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
5261 /* If we could, great. If not, do not go ahead with the IOR
5262 replacement, since PLUS appears in many special purpose
5263 address arithmetic instructions. */
5264 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
5270 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5271 (and <foo> (const_int pow2-1)) */
5272 if (GET_CODE (XEXP (x
, 1)) == AND
5273 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5274 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5275 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5276 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5277 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5281 /* If we have (mult (plus A B) C), apply the distributive law and then
5282 the inverse distributive law to see if things simplify. This
5283 occurs mostly in addresses, often when unrolling loops. */
5285 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5287 rtx result
= distribute_and_simplify_rtx (x
, 0);
5292 /* Try simplify a*(b/c) as (a*b)/c. */
5293 if (FLOAT_MODE_P (mode
) && flag_associative_math
5294 && GET_CODE (XEXP (x
, 0)) == DIV
)
5296 rtx tem
= simplify_binary_operation (MULT
, mode
,
5297 XEXP (XEXP (x
, 0), 0),
5300 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5305 /* If this is a divide by a power of two, treat it as a shift if
5306 its first operand is a shift. */
5307 if (CONST_INT_P (XEXP (x
, 1))
5308 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
5309 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5310 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5311 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5312 || GET_CODE (XEXP (x
, 0)) == ROTATE
5313 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5314 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5318 case GT
: case GTU
: case GE
: case GEU
:
5319 case LT
: case LTU
: case LE
: case LEU
:
5320 case UNEQ
: case LTGT
:
5321 case UNGT
: case UNGE
:
5322 case UNLT
: case UNLE
:
5323 case UNORDERED
: case ORDERED
:
5324 /* If the first operand is a condition code, we can't do anything
5326 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5327 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5328 && ! CC0_P (XEXP (x
, 0))))
5330 rtx op0
= XEXP (x
, 0);
5331 rtx op1
= XEXP (x
, 1);
5332 enum rtx_code new_code
;
5334 if (GET_CODE (op0
) == COMPARE
)
5335 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5337 /* Simplify our comparison, if possible. */
5338 new_code
= simplify_comparison (code
, &op0
, &op1
);
5340 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5341 if only the low-order bit is possibly nonzero in X (such as when
5342 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5343 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5344 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5347 Remove any ZERO_EXTRACT we made when thinking this was a
5348 comparison. It may now be simpler to use, e.g., an AND. If a
5349 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5350 the call to make_compound_operation in the SET case. */
5352 if (STORE_FLAG_VALUE
== 1
5353 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5354 && op1
== const0_rtx
5355 && mode
== GET_MODE (op0
)
5356 && nonzero_bits (op0
, mode
) == 1)
5357 return gen_lowpart (mode
,
5358 expand_compound_operation (op0
));
5360 else if (STORE_FLAG_VALUE
== 1
5361 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5362 && op1
== const0_rtx
5363 && mode
== GET_MODE (op0
)
5364 && (num_sign_bit_copies (op0
, mode
)
5365 == GET_MODE_BITSIZE (mode
)))
5367 op0
= expand_compound_operation (op0
);
5368 return simplify_gen_unary (NEG
, mode
,
5369 gen_lowpart (mode
, op0
),
5373 else if (STORE_FLAG_VALUE
== 1
5374 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5375 && op1
== const0_rtx
5376 && mode
== GET_MODE (op0
)
5377 && nonzero_bits (op0
, mode
) == 1)
5379 op0
= expand_compound_operation (op0
);
5380 return simplify_gen_binary (XOR
, mode
,
5381 gen_lowpart (mode
, op0
),
5385 else if (STORE_FLAG_VALUE
== 1
5386 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5387 && op1
== const0_rtx
5388 && mode
== GET_MODE (op0
)
5389 && (num_sign_bit_copies (op0
, mode
)
5390 == GET_MODE_BITSIZE (mode
)))
5392 op0
= expand_compound_operation (op0
);
5393 return plus_constant (gen_lowpart (mode
, op0
), 1);
5396 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5398 if (STORE_FLAG_VALUE
== -1
5399 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5400 && op1
== const0_rtx
5401 && (num_sign_bit_copies (op0
, mode
)
5402 == GET_MODE_BITSIZE (mode
)))
5403 return gen_lowpart (mode
,
5404 expand_compound_operation (op0
));
5406 else if (STORE_FLAG_VALUE
== -1
5407 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5408 && op1
== const0_rtx
5409 && mode
== GET_MODE (op0
)
5410 && nonzero_bits (op0
, mode
) == 1)
5412 op0
= expand_compound_operation (op0
);
5413 return simplify_gen_unary (NEG
, mode
,
5414 gen_lowpart (mode
, op0
),
5418 else if (STORE_FLAG_VALUE
== -1
5419 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5420 && op1
== const0_rtx
5421 && mode
== GET_MODE (op0
)
5422 && (num_sign_bit_copies (op0
, mode
)
5423 == GET_MODE_BITSIZE (mode
)))
5425 op0
= expand_compound_operation (op0
);
5426 return simplify_gen_unary (NOT
, mode
,
5427 gen_lowpart (mode
, op0
),
5431 /* If X is 0/1, (eq X 0) is X-1. */
5432 else if (STORE_FLAG_VALUE
== -1
5433 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5434 && op1
== const0_rtx
5435 && mode
== GET_MODE (op0
)
5436 && nonzero_bits (op0
, mode
) == 1)
5438 op0
= expand_compound_operation (op0
);
5439 return plus_constant (gen_lowpart (mode
, op0
), -1);
5442 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5443 one bit that might be nonzero, we can convert (ne x 0) to
5444 (ashift x c) where C puts the bit in the sign bit. Remove any
5445 AND with STORE_FLAG_VALUE when we are done, since we are only
5446 going to test the sign bit. */
5447 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5448 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5449 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5450 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5451 && op1
== const0_rtx
5452 && mode
== GET_MODE (op0
)
5453 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5455 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5456 expand_compound_operation (op0
),
5457 GET_MODE_BITSIZE (mode
) - 1 - i
);
5458 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5464 /* If the code changed, return a whole new comparison. */
5465 if (new_code
!= code
)
5466 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5468 /* Otherwise, keep this operation, but maybe change its operands.
5469 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5470 SUBST (XEXP (x
, 0), op0
);
5471 SUBST (XEXP (x
, 1), op1
);
5476 return simplify_if_then_else (x
);
5482 /* If we are processing SET_DEST, we are done. */
5486 return expand_compound_operation (x
);
5489 return simplify_set (x
);
5493 return simplify_logical (x
);
5500 /* If this is a shift by a constant amount, simplify it. */
5501 if (CONST_INT_P (XEXP (x
, 1)))
5502 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5503 INTVAL (XEXP (x
, 1)));
5505 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5507 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5509 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5521 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5524 simplify_if_then_else (rtx x
)
5526 enum machine_mode mode
= GET_MODE (x
);
5527 rtx cond
= XEXP (x
, 0);
5528 rtx true_rtx
= XEXP (x
, 1);
5529 rtx false_rtx
= XEXP (x
, 2);
5530 enum rtx_code true_code
= GET_CODE (cond
);
5531 int comparison_p
= COMPARISON_P (cond
);
5534 enum rtx_code false_code
;
5537 /* Simplify storing of the truth value. */
5538 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5539 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5540 XEXP (cond
, 0), XEXP (cond
, 1));
5542 /* Also when the truth value has to be reversed. */
5544 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5545 && (reversed
= reversed_comparison (cond
, mode
)))
5548 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5549 in it is being compared against certain values. Get the true and false
5550 comparisons and see if that says anything about the value of each arm. */
5553 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5555 && REG_P (XEXP (cond
, 0)))
5558 rtx from
= XEXP (cond
, 0);
5559 rtx true_val
= XEXP (cond
, 1);
5560 rtx false_val
= true_val
;
5563 /* If FALSE_CODE is EQ, swap the codes and arms. */
5565 if (false_code
== EQ
)
5567 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5568 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5571 /* If we are comparing against zero and the expression being tested has
5572 only a single bit that might be nonzero, that is its value when it is
5573 not equal to zero. Similarly if it is known to be -1 or 0. */
5575 if (true_code
== EQ
&& true_val
== const0_rtx
5576 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5579 false_val
= GEN_INT (trunc_int_for_mode (nzb
, GET_MODE (from
)));
5581 else if (true_code
== EQ
&& true_val
== const0_rtx
5582 && (num_sign_bit_copies (from
, GET_MODE (from
))
5583 == GET_MODE_BITSIZE (GET_MODE (from
))))
5586 false_val
= constm1_rtx
;
5589 /* Now simplify an arm if we know the value of the register in the
5590 branch and it is used in the arm. Be careful due to the potential
5591 of locally-shared RTL. */
5593 if (reg_mentioned_p (from
, true_rtx
))
5594 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5596 pc_rtx
, pc_rtx
, 0, 0);
5597 if (reg_mentioned_p (from
, false_rtx
))
5598 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5600 pc_rtx
, pc_rtx
, 0, 0);
5602 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5603 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5605 true_rtx
= XEXP (x
, 1);
5606 false_rtx
= XEXP (x
, 2);
5607 true_code
= GET_CODE (cond
);
5610 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5611 reversed, do so to avoid needing two sets of patterns for
5612 subtract-and-branch insns. Similarly if we have a constant in the true
5613 arm, the false arm is the same as the first operand of the comparison, or
5614 the false arm is more complicated than the true arm. */
5617 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5618 && (true_rtx
== pc_rtx
5619 || (CONSTANT_P (true_rtx
)
5620 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5621 || true_rtx
== const0_rtx
5622 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5623 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5624 && !OBJECT_P (false_rtx
))
5625 || reg_mentioned_p (true_rtx
, false_rtx
)
5626 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5628 true_code
= reversed_comparison_code (cond
, NULL
);
5629 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5630 SUBST (XEXP (x
, 1), false_rtx
);
5631 SUBST (XEXP (x
, 2), true_rtx
);
5633 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5636 /* It is possible that the conditional has been simplified out. */
5637 true_code
= GET_CODE (cond
);
5638 comparison_p
= COMPARISON_P (cond
);
5641 /* If the two arms are identical, we don't need the comparison. */
5643 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5646 /* Convert a == b ? b : a to "a". */
5647 if (true_code
== EQ
&& ! side_effects_p (cond
)
5648 && !HONOR_NANS (mode
)
5649 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5650 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5652 else if (true_code
== NE
&& ! side_effects_p (cond
)
5653 && !HONOR_NANS (mode
)
5654 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5655 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
5658 /* Look for cases where we have (abs x) or (neg (abs X)). */
5660 if (GET_MODE_CLASS (mode
) == MODE_INT
5662 && XEXP (cond
, 1) == const0_rtx
5663 && GET_CODE (false_rtx
) == NEG
5664 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
5665 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
5666 && ! side_effects_p (true_rtx
))
5671 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
5675 simplify_gen_unary (NEG
, mode
,
5676 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
5682 /* Look for MIN or MAX. */
5684 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
5686 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5687 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
5688 && ! side_effects_p (cond
))
5693 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
5696 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
5699 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
5702 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
5707 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5708 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5709 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5710 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5711 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5712 neither 1 or -1, but it isn't worth checking for. */
5714 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5716 && GET_MODE_CLASS (mode
) == MODE_INT
5717 && ! side_effects_p (x
))
5719 rtx t
= make_compound_operation (true_rtx
, SET
);
5720 rtx f
= make_compound_operation (false_rtx
, SET
);
5721 rtx cond_op0
= XEXP (cond
, 0);
5722 rtx cond_op1
= XEXP (cond
, 1);
5723 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
5724 enum machine_mode m
= mode
;
5725 rtx z
= 0, c1
= NULL_RTX
;
5727 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
5728 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
5729 || GET_CODE (t
) == ASHIFT
5730 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
5731 && rtx_equal_p (XEXP (t
, 0), f
))
5732 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
5734 /* If an identity-zero op is commutative, check whether there
5735 would be a match if we swapped the operands. */
5736 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
5737 || GET_CODE (t
) == XOR
)
5738 && rtx_equal_p (XEXP (t
, 1), f
))
5739 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
5740 else if (GET_CODE (t
) == SIGN_EXTEND
5741 && (GET_CODE (XEXP (t
, 0)) == PLUS
5742 || GET_CODE (XEXP (t
, 0)) == MINUS
5743 || GET_CODE (XEXP (t
, 0)) == IOR
5744 || GET_CODE (XEXP (t
, 0)) == XOR
5745 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5746 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5747 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5748 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5749 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5750 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5751 && (num_sign_bit_copies (f
, GET_MODE (f
))
5753 (GET_MODE_BITSIZE (mode
)
5754 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
5756 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5757 extend_op
= SIGN_EXTEND
;
5758 m
= GET_MODE (XEXP (t
, 0));
5760 else if (GET_CODE (t
) == SIGN_EXTEND
5761 && (GET_CODE (XEXP (t
, 0)) == PLUS
5762 || GET_CODE (XEXP (t
, 0)) == IOR
5763 || GET_CODE (XEXP (t
, 0)) == XOR
)
5764 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5765 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5766 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5767 && (num_sign_bit_copies (f
, GET_MODE (f
))
5769 (GET_MODE_BITSIZE (mode
)
5770 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5772 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5773 extend_op
= SIGN_EXTEND
;
5774 m
= GET_MODE (XEXP (t
, 0));
5776 else if (GET_CODE (t
) == ZERO_EXTEND
5777 && (GET_CODE (XEXP (t
, 0)) == PLUS
5778 || GET_CODE (XEXP (t
, 0)) == MINUS
5779 || GET_CODE (XEXP (t
, 0)) == IOR
5780 || GET_CODE (XEXP (t
, 0)) == XOR
5781 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5782 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5783 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5784 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5785 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5786 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5787 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5788 && ((nonzero_bits (f
, GET_MODE (f
))
5789 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5792 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5793 extend_op
= ZERO_EXTEND
;
5794 m
= GET_MODE (XEXP (t
, 0));
5796 else if (GET_CODE (t
) == ZERO_EXTEND
5797 && (GET_CODE (XEXP (t
, 0)) == PLUS
5798 || GET_CODE (XEXP (t
, 0)) == IOR
5799 || GET_CODE (XEXP (t
, 0)) == XOR
)
5800 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5801 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5802 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5803 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5804 && ((nonzero_bits (f
, GET_MODE (f
))
5805 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5808 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5809 extend_op
= ZERO_EXTEND
;
5810 m
= GET_MODE (XEXP (t
, 0));
5815 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
5816 cond_op0
, cond_op1
),
5817 pc_rtx
, pc_rtx
, 0, 0);
5818 temp
= simplify_gen_binary (MULT
, m
, temp
,
5819 simplify_gen_binary (MULT
, m
, c1
,
5821 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5822 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5824 if (extend_op
!= UNKNOWN
)
5825 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5831 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5832 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5833 negation of a single bit, we can convert this operation to a shift. We
5834 can actually do this more generally, but it doesn't seem worth it. */
5836 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5837 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
5838 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5839 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5840 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5841 == GET_MODE_BITSIZE (mode
))
5842 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5844 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5845 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5847 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5848 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5849 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
5850 && GET_MODE (XEXP (cond
, 0)) == mode
5851 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5852 == nonzero_bits (XEXP (cond
, 0), mode
)
5853 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5854 return XEXP (cond
, 0);
5859 /* Simplify X, a SET expression. Return the new expression. */
5862 simplify_set (rtx x
)
5864 rtx src
= SET_SRC (x
);
5865 rtx dest
= SET_DEST (x
);
5866 enum machine_mode mode
5867 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5871 /* (set (pc) (return)) gets written as (return). */
5872 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5875 /* Now that we know for sure which bits of SRC we are using, see if we can
5876 simplify the expression for the object knowing that we only need the
5879 if (GET_MODE_CLASS (mode
) == MODE_INT
5880 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5882 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, 0);
5883 SUBST (SET_SRC (x
), src
);
5886 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5887 the comparison result and try to simplify it unless we already have used
5888 undobuf.other_insn. */
5889 if ((GET_MODE_CLASS (mode
) == MODE_CC
5890 || GET_CODE (src
) == COMPARE
5892 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5893 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5894 && COMPARISON_P (*cc_use
)
5895 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5897 enum rtx_code old_code
= GET_CODE (*cc_use
);
5898 enum rtx_code new_code
;
5900 int other_changed
= 0;
5901 enum machine_mode compare_mode
= GET_MODE (dest
);
5903 if (GET_CODE (src
) == COMPARE
)
5904 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5906 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5908 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5911 new_code
= old_code
;
5912 else if (!CONSTANT_P (tmp
))
5914 new_code
= GET_CODE (tmp
);
5915 op0
= XEXP (tmp
, 0);
5916 op1
= XEXP (tmp
, 1);
5920 rtx pat
= PATTERN (other_insn
);
5921 undobuf
.other_insn
= other_insn
;
5922 SUBST (*cc_use
, tmp
);
5924 /* Attempt to simplify CC user. */
5925 if (GET_CODE (pat
) == SET
)
5927 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
5928 if (new_rtx
!= NULL_RTX
)
5929 SUBST (SET_SRC (pat
), new_rtx
);
5932 /* Convert X into a no-op move. */
5933 SUBST (SET_DEST (x
), pc_rtx
);
5934 SUBST (SET_SRC (x
), pc_rtx
);
5938 /* Simplify our comparison, if possible. */
5939 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5941 #ifdef SELECT_CC_MODE
5942 /* If this machine has CC modes other than CCmode, check to see if we
5943 need to use a different CC mode here. */
5944 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5945 compare_mode
= GET_MODE (op0
);
5947 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5950 /* If the mode changed, we have to change SET_DEST, the mode in the
5951 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5952 a hard register, just build new versions with the proper mode. If it
5953 is a pseudo, we lose unless it is only time we set the pseudo, in
5954 which case we can safely change its mode. */
5955 if (compare_mode
!= GET_MODE (dest
))
5957 if (can_change_dest_mode (dest
, 0, compare_mode
))
5959 unsigned int regno
= REGNO (dest
);
5962 if (regno
< FIRST_PSEUDO_REGISTER
)
5963 new_dest
= gen_rtx_REG (compare_mode
, regno
);
5966 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
5967 new_dest
= regno_reg_rtx
[regno
];
5970 SUBST (SET_DEST (x
), new_dest
);
5971 SUBST (XEXP (*cc_use
, 0), new_dest
);
5978 #endif /* SELECT_CC_MODE */
5980 /* If the code changed, we have to build a new comparison in
5981 undobuf.other_insn. */
5982 if (new_code
!= old_code
)
5984 int other_changed_previously
= other_changed
;
5985 unsigned HOST_WIDE_INT mask
;
5986 rtx old_cc_use
= *cc_use
;
5988 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5992 /* If the only change we made was to change an EQ into an NE or
5993 vice versa, OP0 has only one bit that might be nonzero, and OP1
5994 is zero, check if changing the user of the condition code will
5995 produce a valid insn. If it won't, we can keep the original code
5996 in that insn by surrounding our operation with an XOR. */
5998 if (((old_code
== NE
&& new_code
== EQ
)
5999 || (old_code
== EQ
&& new_code
== NE
))
6000 && ! other_changed_previously
&& op1
== const0_rtx
6001 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
6002 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6004 rtx pat
= PATTERN (other_insn
), note
= 0;
6006 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6007 && ! check_asm_operands (pat
)))
6009 *cc_use
= old_cc_use
;
6012 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6013 op0
, GEN_INT (mask
));
6019 undobuf
.other_insn
= other_insn
;
6021 /* Otherwise, if we didn't previously have a COMPARE in the
6022 correct mode, we need one. */
6023 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6025 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6028 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6030 SUBST (SET_SRC (x
), op0
);
6033 /* Otherwise, update the COMPARE if needed. */
6034 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6036 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6042 /* Get SET_SRC in a form where we have placed back any
6043 compound expressions. Then do the checks below. */
6044 src
= make_compound_operation (src
, SET
);
6045 SUBST (SET_SRC (x
), src
);
6048 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6049 and X being a REG or (subreg (reg)), we may be able to convert this to
6050 (set (subreg:m2 x) (op)).
6052 We can always do this if M1 is narrower than M2 because that means that
6053 we only care about the low bits of the result.
6055 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6056 perform a narrower operation than requested since the high-order bits will
6057 be undefined. On machine where it is defined, this transformation is safe
6058 as long as M1 and M2 have the same number of words. */
6060 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6061 && !OBJECT_P (SUBREG_REG (src
))
6062 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6064 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6065 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6066 #ifndef WORD_REGISTER_OPERATIONS
6067 && (GET_MODE_SIZE (GET_MODE (src
))
6068 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6070 #ifdef CANNOT_CHANGE_MODE_CLASS
6071 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6072 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6073 GET_MODE (SUBREG_REG (src
)),
6077 || (GET_CODE (dest
) == SUBREG
6078 && REG_P (SUBREG_REG (dest
)))))
6080 SUBST (SET_DEST (x
),
6081 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6083 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6085 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6089 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6092 && GET_CODE (src
) == SUBREG
6093 && subreg_lowpart_p (src
)
6094 && (GET_MODE_BITSIZE (GET_MODE (src
))
6095 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
6097 rtx inner
= SUBREG_REG (src
);
6098 enum machine_mode inner_mode
= GET_MODE (inner
);
6100 /* Here we make sure that we don't have a sign bit on. */
6101 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
6102 && (nonzero_bits (inner
, inner_mode
)
6103 < ((unsigned HOST_WIDE_INT
) 1
6104 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
6106 SUBST (SET_SRC (x
), inner
);
6112 #ifdef LOAD_EXTEND_OP
6113 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6114 would require a paradoxical subreg. Replace the subreg with a
6115 zero_extend to avoid the reload that would otherwise be required. */
6117 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6118 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6119 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6120 && SUBREG_BYTE (src
) == 0
6121 && (GET_MODE_SIZE (GET_MODE (src
))
6122 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6123 && MEM_P (SUBREG_REG (src
)))
6126 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6127 GET_MODE (src
), SUBREG_REG (src
)));
6133 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6134 are comparing an item known to be 0 or -1 against 0, use a logical
6135 operation instead. Check for one of the arms being an IOR of the other
6136 arm with some value. We compute three terms to be IOR'ed together. In
6137 practice, at most two will be nonzero. Then we do the IOR's. */
6139 if (GET_CODE (dest
) != PC
6140 && GET_CODE (src
) == IF_THEN_ELSE
6141 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6142 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6143 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6144 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6145 #ifdef HAVE_conditional_move
6146 && ! can_conditionally_move_p (GET_MODE (src
))
6148 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6149 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6150 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6151 && ! side_effects_p (src
))
6153 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6154 ? XEXP (src
, 1) : XEXP (src
, 2));
6155 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6156 ? XEXP (src
, 2) : XEXP (src
, 1));
6157 rtx term1
= const0_rtx
, term2
, term3
;
6159 if (GET_CODE (true_rtx
) == IOR
6160 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6161 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6162 else if (GET_CODE (true_rtx
) == IOR
6163 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6164 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6165 else if (GET_CODE (false_rtx
) == IOR
6166 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6167 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6168 else if (GET_CODE (false_rtx
) == IOR
6169 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6170 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6172 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6173 XEXP (XEXP (src
, 0), 0), true_rtx
);
6174 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6175 simplify_gen_unary (NOT
, GET_MODE (src
),
6176 XEXP (XEXP (src
, 0), 0),
6181 simplify_gen_binary (IOR
, GET_MODE (src
),
6182 simplify_gen_binary (IOR
, GET_MODE (src
),
6189 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6190 whole thing fail. */
6191 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6193 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6196 /* Convert this into a field assignment operation, if possible. */
6197 return make_field_assignment (x
);
6200 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6204 simplify_logical (rtx x
)
6206 enum machine_mode mode
= GET_MODE (x
);
6207 rtx op0
= XEXP (x
, 0);
6208 rtx op1
= XEXP (x
, 1);
6210 switch (GET_CODE (x
))
6213 /* We can call simplify_and_const_int only if we don't lose
6214 any (sign) bits when converting INTVAL (op1) to
6215 "unsigned HOST_WIDE_INT". */
6216 if (CONST_INT_P (op1
)
6217 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6218 || INTVAL (op1
) > 0))
6220 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6221 if (GET_CODE (x
) != AND
)
6228 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6229 apply the distributive law and then the inverse distributive
6230 law to see if things simplify. */
6231 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6233 rtx result
= distribute_and_simplify_rtx (x
, 0);
6237 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6239 rtx result
= distribute_and_simplify_rtx (x
, 1);
6246 /* If we have (ior (and A B) C), apply the distributive law and then
6247 the inverse distributive law to see if things simplify. */
6249 if (GET_CODE (op0
) == AND
)
6251 rtx result
= distribute_and_simplify_rtx (x
, 0);
6256 if (GET_CODE (op1
) == AND
)
6258 rtx result
= distribute_and_simplify_rtx (x
, 1);
6271 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6272 operations" because they can be replaced with two more basic operations.
6273 ZERO_EXTEND is also considered "compound" because it can be replaced with
6274 an AND operation, which is simpler, though only one operation.
6276 The function expand_compound_operation is called with an rtx expression
6277 and will convert it to the appropriate shifts and AND operations,
6278 simplifying at each stage.
6280 The function make_compound_operation is called to convert an expression
6281 consisting of shifts and ANDs into the equivalent compound expression.
6282 It is the inverse of this function, loosely speaking. */
6285 expand_compound_operation (rtx x
)
6287 unsigned HOST_WIDE_INT pos
= 0, len
;
6289 unsigned int modewidth
;
6292 switch (GET_CODE (x
))
6297 /* We can't necessarily use a const_int for a multiword mode;
6298 it depends on implicitly extending the value.
6299 Since we don't know the right way to extend it,
6300 we can't tell whether the implicit way is right.
6302 Even for a mode that is no wider than a const_int,
6303 we can't win, because we need to sign extend one of its bits through
6304 the rest of it, and we don't know which bit. */
6305 if (CONST_INT_P (XEXP (x
, 0)))
6308 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6309 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6310 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6311 reloaded. If not for that, MEM's would very rarely be safe.
6313 Reject MODEs bigger than a word, because we might not be able
6314 to reference a two-register group starting with an arbitrary register
6315 (and currently gen_lowpart might crash for a SUBREG). */
6317 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6320 /* Reject MODEs that aren't scalar integers because turning vector
6321 or complex modes into shifts causes problems. */
6323 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6326 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
6327 /* If the inner object has VOIDmode (the only way this can happen
6328 is if it is an ASM_OPERANDS), we can't do anything since we don't
6329 know how much masking to do. */
6338 /* ... fall through ... */
6341 /* If the operand is a CLOBBER, just return it. */
6342 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6345 if (!CONST_INT_P (XEXP (x
, 1))
6346 || !CONST_INT_P (XEXP (x
, 2))
6347 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6350 /* Reject MODEs that aren't scalar integers because turning vector
6351 or complex modes into shifts causes problems. */
6353 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6356 len
= INTVAL (XEXP (x
, 1));
6357 pos
= INTVAL (XEXP (x
, 2));
6359 /* This should stay within the object being extracted, fail otherwise. */
6360 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
6363 if (BITS_BIG_ENDIAN
)
6364 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6371 /* Convert sign extension to zero extension, if we know that the high
6372 bit is not set, as this is easier to optimize. It will be converted
6373 back to cheaper alternative in make_extraction. */
6374 if (GET_CODE (x
) == SIGN_EXTEND
6375 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6376 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6377 & ~(((unsigned HOST_WIDE_INT
)
6378 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6382 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6383 rtx temp2
= expand_compound_operation (temp
);
6385 /* Make sure this is a profitable operation. */
6386 if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6387 > rtx_cost (temp2
, SET
, optimize_this_for_speed_p
))
6389 else if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6390 > rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
6396 /* We can optimize some special cases of ZERO_EXTEND. */
6397 if (GET_CODE (x
) == ZERO_EXTEND
)
6399 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6400 know that the last value didn't have any inappropriate bits
6402 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6403 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6404 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6405 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6406 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6407 return XEXP (XEXP (x
, 0), 0);
6409 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6410 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6411 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6412 && subreg_lowpart_p (XEXP (x
, 0))
6413 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6414 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6415 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6416 return SUBREG_REG (XEXP (x
, 0));
6418 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6419 is a comparison and STORE_FLAG_VALUE permits. This is like
6420 the first case, but it works even when GET_MODE (x) is larger
6421 than HOST_WIDE_INT. */
6422 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6423 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6424 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6425 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6426 <= HOST_BITS_PER_WIDE_INT
)
6427 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6428 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6429 return XEXP (XEXP (x
, 0), 0);
6431 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6432 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6433 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6434 && subreg_lowpart_p (XEXP (x
, 0))
6435 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6436 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6437 <= HOST_BITS_PER_WIDE_INT
)
6438 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6439 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6440 return SUBREG_REG (XEXP (x
, 0));
6444 /* If we reach here, we want to return a pair of shifts. The inner
6445 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6446 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6447 logical depending on the value of UNSIGNEDP.
6449 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6450 converted into an AND of a shift.
6452 We must check for the case where the left shift would have a negative
6453 count. This can happen in a case like (x >> 31) & 255 on machines
6454 that can't shift by a constant. On those machines, we would first
6455 combine the shift with the AND to produce a variable-position
6456 extraction. Then the constant of 31 would be substituted in to produce
6457 a such a position. */
6459 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
6460 if (modewidth
+ len
>= pos
)
6462 enum machine_mode mode
= GET_MODE (x
);
6463 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6464 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6466 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6467 tem
, modewidth
- pos
- len
);
6468 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6469 mode
, tem
, modewidth
- len
);
6471 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6472 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6473 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6476 ((HOST_WIDE_INT
) 1 << len
) - 1);
6478 /* Any other cases we can't handle. */
6481 /* If we couldn't do this for some reason, return the original
6483 if (GET_CODE (tem
) == CLOBBER
)
6489 /* X is a SET which contains an assignment of one object into
6490 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6491 or certain SUBREGS). If possible, convert it into a series of
6494 We half-heartedly support variable positions, but do not at all
6495 support variable lengths. */
6498 expand_field_assignment (const_rtx x
)
6501 rtx pos
; /* Always counts from low bit. */
6503 rtx mask
, cleared
, masked
;
6504 enum machine_mode compute_mode
;
6506 /* Loop until we find something we can't simplify. */
6509 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6510 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6512 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6513 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6514 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6516 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6517 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6519 inner
= XEXP (SET_DEST (x
), 0);
6520 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6521 pos
= XEXP (SET_DEST (x
), 2);
6523 /* A constant position should stay within the width of INNER. */
6524 if (CONST_INT_P (pos
)
6525 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6528 if (BITS_BIG_ENDIAN
)
6530 if (CONST_INT_P (pos
))
6531 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6533 else if (GET_CODE (pos
) == MINUS
6534 && CONST_INT_P (XEXP (pos
, 1))
6535 && (INTVAL (XEXP (pos
, 1))
6536 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6537 /* If position is ADJUST - X, new position is X. */
6538 pos
= XEXP (pos
, 0);
6540 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6541 GEN_INT (GET_MODE_BITSIZE (
6548 /* A SUBREG between two modes that occupy the same numbers of words
6549 can be done by moving the SUBREG to the source. */
6550 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6551 /* We need SUBREGs to compute nonzero_bits properly. */
6552 && nonzero_sign_valid
6553 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6554 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6555 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6556 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6558 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6560 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6567 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6568 inner
= SUBREG_REG (inner
);
6570 compute_mode
= GET_MODE (inner
);
6572 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6573 if (! SCALAR_INT_MODE_P (compute_mode
))
6575 enum machine_mode imode
;
6577 /* Don't do anything for vector or complex integral types. */
6578 if (! FLOAT_MODE_P (compute_mode
))
6581 /* Try to find an integral mode to pun with. */
6582 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6583 if (imode
== BLKmode
)
6586 compute_mode
= imode
;
6587 inner
= gen_lowpart (imode
, inner
);
6590 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6591 if (len
>= HOST_BITS_PER_WIDE_INT
)
6594 /* Now compute the equivalent expression. Make a copy of INNER
6595 for the SET_DEST in case it is a MEM into which we will substitute;
6596 we don't want shared RTL in that case. */
6597 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6598 cleared
= simplify_gen_binary (AND
, compute_mode
,
6599 simplify_gen_unary (NOT
, compute_mode
,
6600 simplify_gen_binary (ASHIFT
,
6605 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6606 simplify_gen_binary (
6608 gen_lowpart (compute_mode
, SET_SRC (x
)),
6612 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6613 simplify_gen_binary (IOR
, compute_mode
,
6620 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6621 it is an RTX that represents a variable starting position; otherwise,
6622 POS is the (constant) starting bit position (counted from the LSB).
6624 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6627 IN_DEST is nonzero if this is a reference in the destination of a
6628 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6629 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6632 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6633 ZERO_EXTRACT should be built even for bits starting at bit 0.
6635 MODE is the desired mode of the result (if IN_DEST == 0).
6637 The result is an RTX for the extraction or NULL_RTX if the target
6641 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6642 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6643 int in_dest
, int in_compare
)
6645 /* This mode describes the size of the storage area
6646 to fetch the overall value from. Within that, we
6647 ignore the POS lowest bits, etc. */
6648 enum machine_mode is_mode
= GET_MODE (inner
);
6649 enum machine_mode inner_mode
;
6650 enum machine_mode wanted_inner_mode
;
6651 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6652 enum machine_mode pos_mode
= word_mode
;
6653 enum machine_mode extraction_mode
= word_mode
;
6654 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6656 rtx orig_pos_rtx
= pos_rtx
;
6657 HOST_WIDE_INT orig_pos
;
6659 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6661 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6662 consider just the QI as the memory to extract from.
6663 The subreg adds or removes high bits; its mode is
6664 irrelevant to the meaning of this extraction,
6665 since POS and LEN count from the lsb. */
6666 if (MEM_P (SUBREG_REG (inner
)))
6667 is_mode
= GET_MODE (SUBREG_REG (inner
));
6668 inner
= SUBREG_REG (inner
);
6670 else if (GET_CODE (inner
) == ASHIFT
6671 && CONST_INT_P (XEXP (inner
, 1))
6672 && pos_rtx
== 0 && pos
== 0
6673 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6675 /* We're extracting the least significant bits of an rtx
6676 (ashift X (const_int C)), where LEN > C. Extract the
6677 least significant (LEN - C) bits of X, giving an rtx
6678 whose mode is MODE, then shift it left C times. */
6679 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
6680 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6681 unsignedp
, in_dest
, in_compare
);
6683 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
6686 inner_mode
= GET_MODE (inner
);
6688 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
6689 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6691 /* See if this can be done without an extraction. We never can if the
6692 width of the field is not the same as that of some integer mode. For
6693 registers, we can only avoid the extraction if the position is at the
6694 low-order bit and this is either not in the destination or we have the
6695 appropriate STRICT_LOW_PART operation available.
6697 For MEM, we can avoid an extract if the field starts on an appropriate
6698 boundary and we can change the mode of the memory reference. */
6700 if (tmode
!= BLKmode
6701 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6703 && (inner_mode
== tmode
6705 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
6706 GET_MODE_BITSIZE (inner_mode
))
6707 || reg_truncated_to_mode (tmode
, inner
))
6710 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6711 || (MEM_P (inner
) && pos_rtx
== 0
6713 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6714 : BITS_PER_UNIT
)) == 0
6715 /* We can't do this if we are widening INNER_MODE (it
6716 may not be aligned, for one thing). */
6717 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6718 && (inner_mode
== tmode
6719 || (! mode_dependent_address_p (XEXP (inner
, 0))
6720 && ! MEM_VOLATILE_P (inner
))))))
6722 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6723 field. If the original and current mode are the same, we need not
6724 adjust the offset. Otherwise, we do if bytes big endian.
6726 If INNER is not a MEM, get a piece consisting of just the field
6727 of interest (in this case POS % BITS_PER_WORD must be 0). */
6731 HOST_WIDE_INT offset
;
6733 /* POS counts from lsb, but make OFFSET count in memory order. */
6734 if (BYTES_BIG_ENDIAN
)
6735 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6737 offset
= pos
/ BITS_PER_UNIT
;
6739 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
6741 else if (REG_P (inner
))
6743 if (tmode
!= inner_mode
)
6745 /* We can't call gen_lowpart in a DEST since we
6746 always want a SUBREG (see below) and it would sometimes
6747 return a new hard register. */
6750 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6752 if (WORDS_BIG_ENDIAN
6753 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6754 final_word
= ((GET_MODE_SIZE (inner_mode
)
6755 - GET_MODE_SIZE (tmode
))
6756 / UNITS_PER_WORD
) - final_word
;
6758 final_word
*= UNITS_PER_WORD
;
6759 if (BYTES_BIG_ENDIAN
&&
6760 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6761 final_word
+= (GET_MODE_SIZE (inner_mode
)
6762 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6764 /* Avoid creating invalid subregs, for example when
6765 simplifying (x>>32)&255. */
6766 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
6769 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
6772 new_rtx
= gen_lowpart (tmode
, inner
);
6778 new_rtx
= force_to_mode (inner
, tmode
,
6779 len
>= HOST_BITS_PER_WIDE_INT
6780 ? ~(unsigned HOST_WIDE_INT
) 0
6781 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6784 /* If this extraction is going into the destination of a SET,
6785 make a STRICT_LOW_PART unless we made a MEM. */
6788 return (MEM_P (new_rtx
) ? new_rtx
6789 : (GET_CODE (new_rtx
) != SUBREG
6790 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6791 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
6796 if (CONST_INT_P (new_rtx
))
6797 return gen_int_mode (INTVAL (new_rtx
), mode
);
6799 /* If we know that no extraneous bits are set, and that the high
6800 bit is not set, convert the extraction to the cheaper of
6801 sign and zero extension, that are equivalent in these cases. */
6802 if (flag_expensive_optimizations
6803 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6804 && ((nonzero_bits (new_rtx
, tmode
)
6805 & ~(((unsigned HOST_WIDE_INT
)
6806 GET_MODE_MASK (tmode
))
6810 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
6811 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
6813 /* Prefer ZERO_EXTENSION, since it gives more information to
6815 if (rtx_cost (temp
, SET
, optimize_this_for_speed_p
)
6816 <= rtx_cost (temp1
, SET
, optimize_this_for_speed_p
))
6821 /* Otherwise, sign- or zero-extend unless we already are in the
6824 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6828 /* Unless this is a COMPARE or we have a funny memory reference,
6829 don't do anything with zero-extending field extracts starting at
6830 the low-order bit since they are simple AND operations. */
6831 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6832 && ! in_compare
&& unsignedp
)
6835 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6836 if the position is not a constant and the length is not 1. In all
6837 other cases, we would only be going outside our object in cases when
6838 an original shift would have been undefined. */
6840 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6841 || (pos_rtx
!= 0 && len
!= 1)))
6844 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6845 and the mode for the result. */
6846 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6848 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6849 pos_mode
= mode_for_extraction (EP_insv
, 2);
6850 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6853 if (! in_dest
&& unsignedp
6854 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6856 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6857 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6858 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6861 if (! in_dest
&& ! unsignedp
6862 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6864 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6865 pos_mode
= mode_for_extraction (EP_extv
, 3);
6866 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6869 /* Never narrow an object, since that might not be safe. */
6871 if (mode
!= VOIDmode
6872 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6873 extraction_mode
= mode
;
6875 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6876 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6877 pos_mode
= GET_MODE (pos_rtx
);
6879 /* If this is not from memory, the desired mode is the preferred mode
6880 for an extraction pattern's first input operand, or word_mode if there
6883 wanted_inner_mode
= wanted_inner_reg_mode
;
6886 /* Be careful not to go beyond the extracted object and maintain the
6887 natural alignment of the memory. */
6888 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
6889 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
6890 > GET_MODE_BITSIZE (wanted_inner_mode
))
6892 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
6893 gcc_assert (wanted_inner_mode
!= VOIDmode
);
6896 /* If we have to change the mode of memory and cannot, the desired mode
6897 is EXTRACTION_MODE. */
6898 if (inner_mode
!= wanted_inner_mode
6899 && (mode_dependent_address_p (XEXP (inner
, 0))
6900 || MEM_VOLATILE_P (inner
)
6902 wanted_inner_mode
= extraction_mode
;
6907 if (BITS_BIG_ENDIAN
)
6909 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6910 BITS_BIG_ENDIAN style. If position is constant, compute new
6911 position. Otherwise, build subtraction.
6912 Note that POS is relative to the mode of the original argument.
6913 If it's a MEM we need to recompute POS relative to that.
6914 However, if we're extracting from (or inserting into) a register,
6915 we want to recompute POS relative to wanted_inner_mode. */
6916 int width
= (MEM_P (inner
)
6917 ? GET_MODE_BITSIZE (is_mode
)
6918 : GET_MODE_BITSIZE (wanted_inner_mode
));
6921 pos
= width
- len
- pos
;
6924 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6925 /* POS may be less than 0 now, but we check for that below.
6926 Note that it can only be less than 0 if !MEM_P (inner). */
6929 /* If INNER has a wider mode, and this is a constant extraction, try to
6930 make it smaller and adjust the byte to point to the byte containing
6932 if (wanted_inner_mode
!= VOIDmode
6933 && inner_mode
!= wanted_inner_mode
6935 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6937 && ! mode_dependent_address_p (XEXP (inner
, 0))
6938 && ! MEM_VOLATILE_P (inner
))
6942 /* The computations below will be correct if the machine is big
6943 endian in both bits and bytes or little endian in bits and bytes.
6944 If it is mixed, we must adjust. */
6946 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6947 adjust OFFSET to compensate. */
6948 if (BYTES_BIG_ENDIAN
6949 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6950 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6952 /* We can now move to the desired byte. */
6953 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
6954 * GET_MODE_SIZE (wanted_inner_mode
);
6955 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6957 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6958 && is_mode
!= wanted_inner_mode
)
6959 offset
= (GET_MODE_SIZE (is_mode
)
6960 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6962 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6965 /* If INNER is not memory, get it into the proper mode. If we are changing
6966 its mode, POS must be a constant and smaller than the size of the new
6968 else if (!MEM_P (inner
))
6970 /* On the LHS, don't create paradoxical subregs implicitely truncating
6971 the register unless TRULY_NOOP_TRUNCATION. */
6973 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner
)),
6974 GET_MODE_BITSIZE (wanted_inner_mode
)))
6977 if (GET_MODE (inner
) != wanted_inner_mode
6979 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6985 inner
= force_to_mode (inner
, wanted_inner_mode
,
6987 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6988 ? ~(unsigned HOST_WIDE_INT
) 0
6989 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6994 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6995 have to zero extend. Otherwise, we can just use a SUBREG. */
6997 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6999 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
7001 /* If we know that no extraneous bits are set, and that the high
7002 bit is not set, convert extraction to cheaper one - either
7003 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7005 if (flag_expensive_optimizations
7006 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
7007 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7008 & ~(((unsigned HOST_WIDE_INT
)
7009 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7013 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
7015 /* Prefer ZERO_EXTENSION, since it gives more information to
7017 if (rtx_cost (temp1
, SET
, optimize_this_for_speed_p
)
7018 < rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
7023 else if (pos_rtx
!= 0
7024 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7025 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
7027 /* Make POS_RTX unless we already have it and it is correct. If we don't
7028 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7030 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7031 pos_rtx
= orig_pos_rtx
;
7033 else if (pos_rtx
== 0)
7034 pos_rtx
= GEN_INT (pos
);
7036 /* Make the required operation. See if we can use existing rtx. */
7037 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7038 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7040 new_rtx
= gen_lowpart (mode
, new_rtx
);
7045 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7046 with any other operations in X. Return X without that shift if so. */
7049 extract_left_shift (rtx x
, int count
)
7051 enum rtx_code code
= GET_CODE (x
);
7052 enum machine_mode mode
= GET_MODE (x
);
7058 /* This is the shift itself. If it is wide enough, we will return
7059 either the value being shifted if the shift count is equal to
7060 COUNT or a shift for the difference. */
7061 if (CONST_INT_P (XEXP (x
, 1))
7062 && INTVAL (XEXP (x
, 1)) >= count
)
7063 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7064 INTVAL (XEXP (x
, 1)) - count
);
7068 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7069 return simplify_gen_unary (code
, mode
, tem
, mode
);
7073 case PLUS
: case IOR
: case XOR
: case AND
:
7074 /* If we can safely shift this constant and we find the inner shift,
7075 make a new operation. */
7076 if (CONST_INT_P (XEXP (x
, 1))
7077 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7078 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7079 return simplify_gen_binary (code
, mode
, tem
,
7080 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7091 /* Look at the expression rooted at X. Look for expressions
7092 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7093 Form these expressions.
7095 Return the new rtx, usually just X.
7097 Also, for machines like the VAX that don't have logical shift insns,
7098 try to convert logical to arithmetic shift operations in cases where
7099 they are equivalent. This undoes the canonicalizations to logical
7100 shifts done elsewhere.
7102 We try, as much as possible, to re-use rtl expressions to save memory.
7104 IN_CODE says what kind of expression we are processing. Normally, it is
7105 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7106 being kludges), it is MEM. When processing the arguments of a comparison
7107 or a COMPARE against zero, it is COMPARE. */
7110 make_compound_operation (rtx x
, enum rtx_code in_code
)
7112 enum rtx_code code
= GET_CODE (x
);
7113 enum machine_mode mode
= GET_MODE (x
);
7114 int mode_width
= GET_MODE_BITSIZE (mode
);
7116 enum rtx_code next_code
;
7122 /* Select the code to be used in recursive calls. Once we are inside an
7123 address, we stay there. If we have a comparison, set to COMPARE,
7124 but once inside, go back to our default of SET. */
7126 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
7127 : ((code
== COMPARE
|| COMPARISON_P (x
))
7128 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7129 : in_code
== COMPARE
? SET
: in_code
);
7131 /* Process depending on the code of this operation. If NEW is set
7132 nonzero, it will be returned. */
7137 /* Convert shifts by constants into multiplications if inside
7139 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7140 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7141 && INTVAL (XEXP (x
, 1)) >= 0)
7143 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7144 new_rtx
= gen_rtx_MULT (mode
, new_rtx
,
7145 GEN_INT ((HOST_WIDE_INT
) 1
7146 << INTVAL (XEXP (x
, 1))));
7151 /* If the second operand is not a constant, we can't do anything
7153 if (!CONST_INT_P (XEXP (x
, 1)))
7156 /* If the constant is a power of two minus one and the first operand
7157 is a logical right shift, make an extraction. */
7158 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7159 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7161 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7162 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7163 0, in_code
== COMPARE
);
7166 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7167 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7168 && subreg_lowpart_p (XEXP (x
, 0))
7169 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7170 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7172 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7174 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7175 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7176 0, in_code
== COMPARE
);
7178 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7179 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7180 || GET_CODE (XEXP (x
, 0)) == IOR
)
7181 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7182 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7183 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7185 /* Apply the distributive law, and then try to make extractions. */
7186 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7187 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7189 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7191 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7194 /* If we are have (and (rotate X C) M) and C is larger than the number
7195 of bits in M, this is an extraction. */
7197 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7198 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7199 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
7200 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7202 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7203 new_rtx
= make_extraction (mode
, new_rtx
,
7204 (GET_MODE_BITSIZE (mode
)
7205 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7206 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7209 /* On machines without logical shifts, if the operand of the AND is
7210 a logical shift and our mask turns off all the propagated sign
7211 bits, we can replace the logical shift with an arithmetic shift. */
7212 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7213 && !have_insn_for (LSHIFTRT
, mode
)
7214 && have_insn_for (ASHIFTRT
, mode
)
7215 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7216 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7217 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7218 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7220 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7222 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7223 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7225 gen_rtx_ASHIFTRT (mode
,
7226 make_compound_operation
7227 (XEXP (XEXP (x
, 0), 0), next_code
),
7228 XEXP (XEXP (x
, 0), 1)));
7231 /* If the constant is one less than a power of two, this might be
7232 representable by an extraction even if no shift is present.
7233 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7234 we are in a COMPARE. */
7235 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7236 new_rtx
= make_extraction (mode
,
7237 make_compound_operation (XEXP (x
, 0),
7239 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7241 /* If we are in a comparison and this is an AND with a power of two,
7242 convert this into the appropriate bit extract. */
7243 else if (in_code
== COMPARE
7244 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
7245 new_rtx
= make_extraction (mode
,
7246 make_compound_operation (XEXP (x
, 0),
7248 i
, NULL_RTX
, 1, 1, 0, 1);
7253 /* If the sign bit is known to be zero, replace this with an
7254 arithmetic shift. */
7255 if (have_insn_for (ASHIFTRT
, mode
)
7256 && ! have_insn_for (LSHIFTRT
, mode
)
7257 && mode_width
<= HOST_BITS_PER_WIDE_INT
7258 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7260 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7261 make_compound_operation (XEXP (x
, 0),
7267 /* ... fall through ... */
7273 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7274 this is a SIGN_EXTRACT. */
7275 if (CONST_INT_P (rhs
)
7276 && GET_CODE (lhs
) == ASHIFT
7277 && CONST_INT_P (XEXP (lhs
, 1))
7278 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7279 && INTVAL (rhs
) < mode_width
)
7281 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7282 new_rtx
= make_extraction (mode
, new_rtx
,
7283 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7284 NULL_RTX
, mode_width
- INTVAL (rhs
),
7285 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7289 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7290 If so, try to merge the shifts into a SIGN_EXTEND. We could
7291 also do this for some cases of SIGN_EXTRACT, but it doesn't
7292 seem worth the effort; the case checked for occurs on Alpha. */
7295 && ! (GET_CODE (lhs
) == SUBREG
7296 && (OBJECT_P (SUBREG_REG (lhs
))))
7297 && CONST_INT_P (rhs
)
7298 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7299 && INTVAL (rhs
) < mode_width
7300 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7301 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7302 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7303 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7308 /* Call ourselves recursively on the inner expression. If we are
7309 narrowing the object and it has a different RTL code from
7310 what it originally did, do this SUBREG as a force_to_mode. */
7312 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
7315 rtx simplified
= simplify_subreg (mode
, tem
, GET_MODE (SUBREG_REG (x
)),
7321 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
7322 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
7323 && subreg_lowpart_p (x
))
7325 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
7328 /* If we have something other than a SUBREG, we might have
7329 done an expansion, so rerun ourselves. */
7330 if (GET_CODE (newer
) != SUBREG
)
7331 newer
= make_compound_operation (newer
, in_code
);
7333 /* force_to_mode can expand compounds. If it just re-expanded the
7334 compound use gen_lowpart instead to convert to the desired
7336 if (rtx_equal_p (newer
, x
))
7337 return gen_lowpart (GET_MODE (x
), tem
);
7353 x
= gen_lowpart (mode
, new_rtx
);
7354 code
= GET_CODE (x
);
7357 /* Now recursively process each operand of this operation. */
7358 fmt
= GET_RTX_FORMAT (code
);
7359 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7362 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7363 SUBST (XEXP (x
, i
), new_rtx
);
7365 else if (fmt
[i
] == 'E')
7366 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7368 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7369 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7372 /* If this is a commutative operation, the changes to the operands
7373 may have made it noncanonical. */
7374 if (COMMUTATIVE_ARITH_P (x
)
7375 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7378 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7379 SUBST (XEXP (x
, 1), tem
);
7385 /* Given M see if it is a value that would select a field of bits
7386 within an item, but not the entire word. Return -1 if not.
7387 Otherwise, return the starting position of the field, where 0 is the
7390 *PLEN is set to the length of the field. */
7393 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7395 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7396 int pos
= exact_log2 (m
& -m
);
7400 /* Now shift off the low-order zero bits and see if we have a
7401 power of two minus 1. */
7402 len
= exact_log2 ((m
>> pos
) + 1);
7411 /* If X refers to a register that equals REG in value, replace these
7412 references with REG. */
7414 canon_reg_for_combine (rtx x
, rtx reg
)
7421 enum rtx_code code
= GET_CODE (x
);
7422 switch (GET_RTX_CLASS (code
))
7425 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7426 if (op0
!= XEXP (x
, 0))
7427 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7432 case RTX_COMM_ARITH
:
7433 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7434 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7435 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7436 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7440 case RTX_COMM_COMPARE
:
7441 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7442 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7443 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7444 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7445 GET_MODE (op0
), op0
, op1
);
7449 case RTX_BITFIELD_OPS
:
7450 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7451 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7452 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7453 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7454 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7455 GET_MODE (op0
), op0
, op1
, op2
);
7460 if (rtx_equal_p (get_last_value (reg
), x
)
7461 || rtx_equal_p (reg
, get_last_value (x
)))
7470 fmt
= GET_RTX_FORMAT (code
);
7472 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7475 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7476 if (op
!= XEXP (x
, i
))
7486 else if (fmt
[i
] == 'E')
7489 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7491 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7492 if (op
!= XVECEXP (x
, i
, j
))
7499 XVECEXP (x
, i
, j
) = op
;
7510 /* Return X converted to MODE. If the value is already truncated to
7511 MODE we can just return a subreg even though in the general case we
7512 would need an explicit truncation. */
7515 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7517 if (!CONST_INT_P (x
)
7518 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7519 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
7520 GET_MODE_BITSIZE (GET_MODE (x
)))
7521 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7523 /* Bit-cast X into an integer mode. */
7524 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7525 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7526 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7530 return gen_lowpart (mode
, x
);
7533 /* See if X can be simplified knowing that we will only refer to it in
7534 MODE and will only refer to those bits that are nonzero in MASK.
7535 If other bits are being computed or if masking operations are done
7536 that select a superset of the bits in MASK, they can sometimes be
7539 Return a possibly simplified expression, but always convert X to
7540 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7542 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7543 are all off in X. This is used when X will be complemented, by either
7544 NOT, NEG, or XOR. */
7547 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7550 enum rtx_code code
= GET_CODE (x
);
7551 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7552 enum machine_mode op_mode
;
7553 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7556 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7557 code below will do the wrong thing since the mode of such an
7558 expression is VOIDmode.
7560 Also do nothing if X is a CLOBBER; this can happen if X was
7561 the return value from a call to gen_lowpart. */
7562 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7565 /* We want to perform the operation is its present mode unless we know
7566 that the operation is valid in MODE, in which case we do the operation
7568 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
7569 && have_insn_for (code
, mode
))
7570 ? mode
: GET_MODE (x
));
7572 /* It is not valid to do a right-shift in a narrower mode
7573 than the one it came in with. */
7574 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
7575 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
7576 op_mode
= GET_MODE (x
);
7578 /* Truncate MASK to fit OP_MODE. */
7580 mask
&= GET_MODE_MASK (op_mode
);
7582 /* When we have an arithmetic operation, or a shift whose count we
7583 do not know, we need to assume that all bits up to the highest-order
7584 bit in MASK will be needed. This is how we form such a mask. */
7585 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
7586 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
7588 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
7591 /* Determine what bits of X are guaranteed to be (non)zero. */
7592 nonzero
= nonzero_bits (x
, mode
);
7594 /* If none of the bits in X are needed, return a zero. */
7595 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
7598 /* If X is a CONST_INT, return a new one. Do this here since the
7599 test below will fail. */
7600 if (CONST_INT_P (x
))
7602 if (SCALAR_INT_MODE_P (mode
))
7603 return gen_int_mode (INTVAL (x
) & mask
, mode
);
7606 x
= GEN_INT (INTVAL (x
) & mask
);
7607 return gen_lowpart_common (mode
, x
);
7611 /* If X is narrower than MODE and we want all the bits in X's mode, just
7612 get X in the proper mode. */
7613 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
7614 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
7615 return gen_lowpart (mode
, x
);
7617 /* We can ignore the effect of a SUBREG if it narrows the mode or
7618 if the constant masks to zero all the bits the mode doesn't have. */
7619 if (GET_CODE (x
) == SUBREG
7620 && subreg_lowpart_p (x
)
7621 && ((GET_MODE_SIZE (GET_MODE (x
))
7622 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7624 & GET_MODE_MASK (GET_MODE (x
))
7625 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
7626 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
7628 /* The arithmetic simplifications here only work for scalar integer modes. */
7629 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
7630 return gen_lowpart_or_truncate (mode
, x
);
7635 /* If X is a (clobber (const_int)), return it since we know we are
7636 generating something that won't match. */
7643 x
= expand_compound_operation (x
);
7644 if (GET_CODE (x
) != code
)
7645 return force_to_mode (x
, mode
, mask
, next_select
);
7649 /* Similarly for a truncate. */
7650 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7653 /* If this is an AND with a constant, convert it into an AND
7654 whose constant is the AND of that constant with MASK. If it
7655 remains an AND of MASK, delete it since it is redundant. */
7657 if (CONST_INT_P (XEXP (x
, 1)))
7659 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
7660 mask
& INTVAL (XEXP (x
, 1)));
7662 /* If X is still an AND, see if it is an AND with a mask that
7663 is just some low-order bits. If so, and it is MASK, we don't
7666 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
7667 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
7671 /* If it remains an AND, try making another AND with the bits
7672 in the mode mask that aren't in MASK turned on. If the
7673 constant in the AND is wide enough, this might make a
7674 cheaper constant. */
7676 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
7677 && GET_MODE_MASK (GET_MODE (x
)) != mask
7678 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
7680 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
7681 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
7682 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
7685 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7686 number, sign extend it. */
7687 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
7688 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7689 cval
|= (HOST_WIDE_INT
) -1 << width
;
7691 y
= simplify_gen_binary (AND
, GET_MODE (x
),
7692 XEXP (x
, 0), GEN_INT (cval
));
7693 if (rtx_cost (y
, SET
, optimize_this_for_speed_p
)
7694 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
7704 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7705 low-order bits (as in an alignment operation) and FOO is already
7706 aligned to that boundary, mask C1 to that boundary as well.
7707 This may eliminate that PLUS and, later, the AND. */
7710 unsigned int width
= GET_MODE_BITSIZE (mode
);
7711 unsigned HOST_WIDE_INT smask
= mask
;
7713 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7714 number, sign extend it. */
7716 if (width
< HOST_BITS_PER_WIDE_INT
7717 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7718 smask
|= (HOST_WIDE_INT
) -1 << width
;
7720 if (CONST_INT_P (XEXP (x
, 1))
7721 && exact_log2 (- smask
) >= 0
7722 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7723 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7724 return force_to_mode (plus_constant (XEXP (x
, 0),
7725 (INTVAL (XEXP (x
, 1)) & smask
)),
7726 mode
, smask
, next_select
);
7729 /* ... fall through ... */
7732 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7733 most significant bit in MASK since carries from those bits will
7734 affect the bits we are interested in. */
7739 /* If X is (minus C Y) where C's least set bit is larger than any bit
7740 in the mask, then we may replace with (neg Y). */
7741 if (CONST_INT_P (XEXP (x
, 0))
7742 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7743 & -INTVAL (XEXP (x
, 0))))
7746 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7748 return force_to_mode (x
, mode
, mask
, next_select
);
7751 /* Similarly, if C contains every bit in the fuller_mask, then we may
7752 replace with (not Y). */
7753 if (CONST_INT_P (XEXP (x
, 0))
7754 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7755 == INTVAL (XEXP (x
, 0))))
7757 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7758 XEXP (x
, 1), GET_MODE (x
));
7759 return force_to_mode (x
, mode
, mask
, next_select
);
7767 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7768 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7769 operation which may be a bitfield extraction. Ensure that the
7770 constant we form is not wider than the mode of X. */
7772 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7773 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7774 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7775 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7776 && CONST_INT_P (XEXP (x
, 1))
7777 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7778 + floor_log2 (INTVAL (XEXP (x
, 1))))
7779 < GET_MODE_BITSIZE (GET_MODE (x
)))
7780 && (INTVAL (XEXP (x
, 1))
7781 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7783 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7784 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7785 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
7786 XEXP (XEXP (x
, 0), 0), temp
);
7787 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7788 XEXP (XEXP (x
, 0), 1));
7789 return force_to_mode (x
, mode
, mask
, next_select
);
7793 /* For most binary operations, just propagate into the operation and
7794 change the mode if we have an operation of that mode. */
7796 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7797 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
7799 /* If we ended up truncating both operands, truncate the result of the
7800 operation instead. */
7801 if (GET_CODE (op0
) == TRUNCATE
7802 && GET_CODE (op1
) == TRUNCATE
)
7804 op0
= XEXP (op0
, 0);
7805 op1
= XEXP (op1
, 0);
7808 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
7809 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
7811 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7812 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
7816 /* For left shifts, do the same, but just for the first operand.
7817 However, we cannot do anything with shifts where we cannot
7818 guarantee that the counts are smaller than the size of the mode
7819 because such a count will have a different meaning in a
7822 if (! (CONST_INT_P (XEXP (x
, 1))
7823 && INTVAL (XEXP (x
, 1)) >= 0
7824 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7825 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7826 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7827 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7830 /* If the shift count is a constant and we can do arithmetic in
7831 the mode of the shift, refine which bits we need. Otherwise, use the
7832 conservative form of the mask. */
7833 if (CONST_INT_P (XEXP (x
, 1))
7834 && INTVAL (XEXP (x
, 1)) >= 0
7835 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7836 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7837 mask
>>= INTVAL (XEXP (x
, 1));
7841 op0
= gen_lowpart_or_truncate (op_mode
,
7842 force_to_mode (XEXP (x
, 0), op_mode
,
7843 mask
, next_select
));
7845 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7846 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7850 /* Here we can only do something if the shift count is a constant,
7851 this shift constant is valid for the host, and we can do arithmetic
7854 if (CONST_INT_P (XEXP (x
, 1))
7855 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7856 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7858 rtx inner
= XEXP (x
, 0);
7859 unsigned HOST_WIDE_INT inner_mask
;
7861 /* Select the mask of the bits we need for the shift operand. */
7862 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7864 /* We can only change the mode of the shift if we can do arithmetic
7865 in the mode of the shift and INNER_MASK is no wider than the
7866 width of X's mode. */
7867 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7868 op_mode
= GET_MODE (x
);
7870 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
7872 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7873 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7876 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7877 shift and AND produces only copies of the sign bit (C2 is one less
7878 than a power of two), we can do this with just a shift. */
7880 if (GET_CODE (x
) == LSHIFTRT
7881 && CONST_INT_P (XEXP (x
, 1))
7882 /* The shift puts one of the sign bit copies in the least significant
7884 && ((INTVAL (XEXP (x
, 1))
7885 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7886 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7887 && exact_log2 (mask
+ 1) >= 0
7888 /* Number of bits left after the shift must be more than the mask
7890 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7891 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7892 /* Must be more sign bit copies than the mask needs. */
7893 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7894 >= exact_log2 (mask
+ 1)))
7895 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7896 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7897 - exact_log2 (mask
+ 1)));
7902 /* If we are just looking for the sign bit, we don't need this shift at
7903 all, even if it has a variable count. */
7904 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7905 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7906 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7907 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7909 /* If this is a shift by a constant, get a mask that contains those bits
7910 that are not copies of the sign bit. We then have two cases: If
7911 MASK only includes those bits, this can be a logical shift, which may
7912 allow simplifications. If MASK is a single-bit field not within
7913 those bits, we are requesting a copy of the sign bit and hence can
7914 shift the sign bit to the appropriate location. */
7916 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
7917 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7921 /* If the considered data is wider than HOST_WIDE_INT, we can't
7922 represent a mask for all its bits in a single scalar.
7923 But we only care about the lower bits, so calculate these. */
7925 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7927 nonzero
= ~(HOST_WIDE_INT
) 0;
7929 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7930 is the number of bits a full-width mask would have set.
7931 We need only shift if these are fewer than nonzero can
7932 hold. If not, we must keep all bits set in nonzero. */
7934 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7935 < HOST_BITS_PER_WIDE_INT
)
7936 nonzero
>>= INTVAL (XEXP (x
, 1))
7937 + HOST_BITS_PER_WIDE_INT
7938 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7942 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7943 nonzero
>>= INTVAL (XEXP (x
, 1));
7946 if ((mask
& ~nonzero
) == 0)
7948 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
7949 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
7950 if (GET_CODE (x
) != ASHIFTRT
)
7951 return force_to_mode (x
, mode
, mask
, next_select
);
7954 else if ((i
= exact_log2 (mask
)) >= 0)
7956 x
= simplify_shift_const
7957 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7958 GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7960 if (GET_CODE (x
) != ASHIFTRT
)
7961 return force_to_mode (x
, mode
, mask
, next_select
);
7965 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7966 even if the shift count isn't a constant. */
7968 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7969 XEXP (x
, 0), XEXP (x
, 1));
7973 /* If this is a zero- or sign-extension operation that just affects bits
7974 we don't care about, remove it. Be sure the call above returned
7975 something that is still a shift. */
7977 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7978 && CONST_INT_P (XEXP (x
, 1))
7979 && INTVAL (XEXP (x
, 1)) >= 0
7980 && (INTVAL (XEXP (x
, 1))
7981 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7982 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7983 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7984 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7991 /* If the shift count is constant and we can do computations
7992 in the mode of X, compute where the bits we care about are.
7993 Otherwise, we can't do anything. Don't change the mode of
7994 the shift or propagate MODE into the shift, though. */
7995 if (CONST_INT_P (XEXP (x
, 1))
7996 && INTVAL (XEXP (x
, 1)) >= 0)
7998 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7999 GET_MODE (x
), GEN_INT (mask
),
8001 if (temp
&& CONST_INT_P (temp
))
8003 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8004 INTVAL (temp
), next_select
));
8009 /* If we just want the low-order bit, the NEG isn't needed since it
8010 won't change the low-order bit. */
8012 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8014 /* We need any bits less significant than the most significant bit in
8015 MASK since carries from those bits will affect the bits we are
8021 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8022 same as the XOR case above. Ensure that the constant we form is not
8023 wider than the mode of X. */
8025 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8026 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8027 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8028 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8029 < GET_MODE_BITSIZE (GET_MODE (x
)))
8030 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8032 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8034 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8035 XEXP (XEXP (x
, 0), 0), temp
);
8036 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8037 temp
, XEXP (XEXP (x
, 0), 1));
8039 return force_to_mode (x
, mode
, mask
, next_select
);
8042 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8043 use the full mask inside the NOT. */
8047 op0
= gen_lowpart_or_truncate (op_mode
,
8048 force_to_mode (XEXP (x
, 0), mode
, mask
,
8050 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8051 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8055 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8056 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8057 which is equal to STORE_FLAG_VALUE. */
8058 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
8059 && GET_MODE (XEXP (x
, 0)) == mode
8060 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8061 && (nonzero_bits (XEXP (x
, 0), mode
)
8062 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8063 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8068 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8069 written in a narrower mode. We play it safe and do not do so. */
8072 gen_lowpart_or_truncate (GET_MODE (x
),
8073 force_to_mode (XEXP (x
, 1), mode
,
8074 mask
, next_select
)));
8076 gen_lowpart_or_truncate (GET_MODE (x
),
8077 force_to_mode (XEXP (x
, 2), mode
,
8078 mask
, next_select
)));
8085 /* Ensure we return a value of the proper mode. */
8086 return gen_lowpart_or_truncate (mode
, x
);
8089 /* Return nonzero if X is an expression that has one of two values depending on
8090 whether some other value is zero or nonzero. In that case, we return the
8091 value that is being tested, *PTRUE is set to the value if the rtx being
8092 returned has a nonzero value, and *PFALSE is set to the other alternative.
8094 If we return zero, we set *PTRUE and *PFALSE to X. */
8097 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8099 enum machine_mode mode
= GET_MODE (x
);
8100 enum rtx_code code
= GET_CODE (x
);
8101 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8102 unsigned HOST_WIDE_INT nz
;
8104 /* If we are comparing a value against zero, we are done. */
8105 if ((code
== NE
|| code
== EQ
)
8106 && XEXP (x
, 1) == const0_rtx
)
8108 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8109 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8113 /* If this is a unary operation whose operand has one of two values, apply
8114 our opcode to compute those values. */
8115 else if (UNARY_P (x
)
8116 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8118 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8119 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8120 GET_MODE (XEXP (x
, 0)));
8124 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8125 make can't possibly match and would suppress other optimizations. */
8126 else if (code
== COMPARE
)
8129 /* If this is a binary operation, see if either side has only one of two
8130 values. If either one does or if both do and they are conditional on
8131 the same value, compute the new true and false values. */
8132 else if (BINARY_P (x
))
8134 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8135 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8137 if ((cond0
!= 0 || cond1
!= 0)
8138 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8140 /* If if_then_else_cond returned zero, then true/false are the
8141 same rtl. We must copy one of them to prevent invalid rtl
8144 true0
= copy_rtx (true0
);
8145 else if (cond1
== 0)
8146 true1
= copy_rtx (true1
);
8148 if (COMPARISON_P (x
))
8150 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8152 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8157 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8158 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8161 return cond0
? cond0
: cond1
;
8164 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8165 operands is zero when the other is nonzero, and vice-versa,
8166 and STORE_FLAG_VALUE is 1 or -1. */
8168 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8169 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8171 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8173 rtx op0
= XEXP (XEXP (x
, 0), 1);
8174 rtx op1
= XEXP (XEXP (x
, 1), 1);
8176 cond0
= XEXP (XEXP (x
, 0), 0);
8177 cond1
= XEXP (XEXP (x
, 1), 0);
8179 if (COMPARISON_P (cond0
)
8180 && COMPARISON_P (cond1
)
8181 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8182 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8183 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8184 || ((swap_condition (GET_CODE (cond0
))
8185 == reversed_comparison_code (cond1
, NULL
))
8186 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8187 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8188 && ! side_effects_p (x
))
8190 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8191 *pfalse
= simplify_gen_binary (MULT
, mode
,
8193 ? simplify_gen_unary (NEG
, mode
,
8201 /* Similarly for MULT, AND and UMIN, except that for these the result
8203 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8204 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8205 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8207 cond0
= XEXP (XEXP (x
, 0), 0);
8208 cond1
= XEXP (XEXP (x
, 1), 0);
8210 if (COMPARISON_P (cond0
)
8211 && COMPARISON_P (cond1
)
8212 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8213 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8214 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8215 || ((swap_condition (GET_CODE (cond0
))
8216 == reversed_comparison_code (cond1
, NULL
))
8217 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8218 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8219 && ! side_effects_p (x
))
8221 *ptrue
= *pfalse
= const0_rtx
;
8227 else if (code
== IF_THEN_ELSE
)
8229 /* If we have IF_THEN_ELSE already, extract the condition and
8230 canonicalize it if it is NE or EQ. */
8231 cond0
= XEXP (x
, 0);
8232 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8233 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8234 return XEXP (cond0
, 0);
8235 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8237 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8238 return XEXP (cond0
, 0);
8244 /* If X is a SUBREG, we can narrow both the true and false values
8245 if the inner expression, if there is a condition. */
8246 else if (code
== SUBREG
8247 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8250 true0
= simplify_gen_subreg (mode
, true0
,
8251 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8252 false0
= simplify_gen_subreg (mode
, false0
,
8253 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8254 if (true0
&& false0
)
8262 /* If X is a constant, this isn't special and will cause confusions
8263 if we treat it as such. Likewise if it is equivalent to a constant. */
8264 else if (CONSTANT_P (x
)
8265 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8268 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8269 will be least confusing to the rest of the compiler. */
8270 else if (mode
== BImode
)
8272 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8276 /* If X is known to be either 0 or -1, those are the true and
8277 false values when testing X. */
8278 else if (x
== constm1_rtx
|| x
== const0_rtx
8279 || (mode
!= VOIDmode
8280 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
8282 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8286 /* Likewise for 0 or a single bit. */
8287 else if (SCALAR_INT_MODE_P (mode
)
8288 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8289 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8291 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8295 /* Otherwise fail; show no condition with true and false values the same. */
8296 *ptrue
= *pfalse
= x
;
8300 /* Return the value of expression X given the fact that condition COND
8301 is known to be true when applied to REG as its first operand and VAL
8302 as its second. X is known to not be shared and so can be modified in
8305 We only handle the simplest cases, and specifically those cases that
8306 arise with IF_THEN_ELSE expressions. */
8309 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8311 enum rtx_code code
= GET_CODE (x
);
8316 if (side_effects_p (x
))
8319 /* If either operand of the condition is a floating point value,
8320 then we have to avoid collapsing an EQ comparison. */
8322 && rtx_equal_p (x
, reg
)
8323 && ! FLOAT_MODE_P (GET_MODE (x
))
8324 && ! FLOAT_MODE_P (GET_MODE (val
)))
8327 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8330 /* If X is (abs REG) and we know something about REG's relationship
8331 with zero, we may be able to simplify this. */
8333 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8336 case GE
: case GT
: case EQ
:
8339 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8341 GET_MODE (XEXP (x
, 0)));
8346 /* The only other cases we handle are MIN, MAX, and comparisons if the
8347 operands are the same as REG and VAL. */
8349 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8351 if (rtx_equal_p (XEXP (x
, 0), val
))
8352 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8354 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8356 if (COMPARISON_P (x
))
8358 if (comparison_dominates_p (cond
, code
))
8359 return const_true_rtx
;
8361 code
= reversed_comparison_code (x
, NULL
);
8363 && comparison_dominates_p (cond
, code
))
8368 else if (code
== SMAX
|| code
== SMIN
8369 || code
== UMIN
|| code
== UMAX
)
8371 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8373 /* Do not reverse the condition when it is NE or EQ.
8374 This is because we cannot conclude anything about
8375 the value of 'SMAX (x, y)' when x is not equal to y,
8376 but we can when x equals y. */
8377 if ((code
== SMAX
|| code
== UMAX
)
8378 && ! (cond
== EQ
|| cond
== NE
))
8379 cond
= reverse_condition (cond
);
8384 return unsignedp
? x
: XEXP (x
, 1);
8386 return unsignedp
? x
: XEXP (x
, 0);
8388 return unsignedp
? XEXP (x
, 1) : x
;
8390 return unsignedp
? XEXP (x
, 0) : x
;
8397 else if (code
== SUBREG
)
8399 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8400 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8402 if (SUBREG_REG (x
) != r
)
8404 /* We must simplify subreg here, before we lose track of the
8405 original inner_mode. */
8406 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8407 inner_mode
, SUBREG_BYTE (x
));
8411 SUBST (SUBREG_REG (x
), r
);
8416 /* We don't have to handle SIGN_EXTEND here, because even in the
8417 case of replacing something with a modeless CONST_INT, a
8418 CONST_INT is already (supposed to be) a valid sign extension for
8419 its narrower mode, which implies it's already properly
8420 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8421 story is different. */
8422 else if (code
== ZERO_EXTEND
)
8424 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8425 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8427 if (XEXP (x
, 0) != r
)
8429 /* We must simplify the zero_extend here, before we lose
8430 track of the original inner_mode. */
8431 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8436 SUBST (XEXP (x
, 0), r
);
8442 fmt
= GET_RTX_FORMAT (code
);
8443 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8446 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8447 else if (fmt
[i
] == 'E')
8448 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8449 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8456 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8457 assignment as a field assignment. */
8460 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8462 if (x
== y
|| rtx_equal_p (x
, y
))
8465 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8468 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8469 Note that all SUBREGs of MEM are paradoxical; otherwise they
8470 would have been rewritten. */
8471 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8472 && MEM_P (SUBREG_REG (y
))
8473 && rtx_equal_p (SUBREG_REG (y
),
8474 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8477 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8478 && MEM_P (SUBREG_REG (x
))
8479 && rtx_equal_p (SUBREG_REG (x
),
8480 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8483 /* We used to see if get_last_value of X and Y were the same but that's
8484 not correct. In one direction, we'll cause the assignment to have
8485 the wrong destination and in the case, we'll import a register into this
8486 insn that might have already have been dead. So fail if none of the
8487 above cases are true. */
8491 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8492 Return that assignment if so.
8494 We only handle the most common cases. */
8497 make_field_assignment (rtx x
)
8499 rtx dest
= SET_DEST (x
);
8500 rtx src
= SET_SRC (x
);
8505 unsigned HOST_WIDE_INT len
;
8507 enum machine_mode mode
;
8509 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8510 a clear of a one-bit field. We will have changed it to
8511 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8514 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8515 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8516 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8517 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8519 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8522 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8526 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8527 && subreg_lowpart_p (XEXP (src
, 0))
8528 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8529 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8530 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8531 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8532 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8533 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8535 assign
= make_extraction (VOIDmode
, dest
, 0,
8536 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8539 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8543 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8545 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8546 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8547 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8549 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8552 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8556 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8557 SRC is an AND with all bits of that field set, then we can discard
8559 if (GET_CODE (dest
) == ZERO_EXTRACT
8560 && CONST_INT_P (XEXP (dest
, 1))
8561 && GET_CODE (src
) == AND
8562 && CONST_INT_P (XEXP (src
, 1)))
8564 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
8565 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
8566 unsigned HOST_WIDE_INT ze_mask
;
8568 if (width
>= HOST_BITS_PER_WIDE_INT
)
8571 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
8573 /* Complete overlap. We can remove the source AND. */
8574 if ((and_mask
& ze_mask
) == ze_mask
)
8575 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
8577 /* Partial overlap. We can reduce the source AND. */
8578 if ((and_mask
& ze_mask
) != and_mask
)
8580 mode
= GET_MODE (src
);
8581 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
8582 gen_int_mode (and_mask
& ze_mask
, mode
));
8583 return gen_rtx_SET (VOIDmode
, dest
, src
);
8587 /* The other case we handle is assignments into a constant-position
8588 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8589 a mask that has all one bits except for a group of zero bits and
8590 OTHER is known to have zeros where C1 has ones, this is such an
8591 assignment. Compute the position and length from C1. Shift OTHER
8592 to the appropriate position, force it to the required mode, and
8593 make the extraction. Check for the AND in both operands. */
8595 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
8598 rhs
= expand_compound_operation (XEXP (src
, 0));
8599 lhs
= expand_compound_operation (XEXP (src
, 1));
8601 if (GET_CODE (rhs
) == AND
8602 && CONST_INT_P (XEXP (rhs
, 1))
8603 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
8604 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
8605 else if (GET_CODE (lhs
) == AND
8606 && CONST_INT_P (XEXP (lhs
, 1))
8607 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
8608 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
8612 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
8613 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
8614 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
8615 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
8618 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
8622 /* The mode to use for the source is the mode of the assignment, or of
8623 what is inside a possible STRICT_LOW_PART. */
8624 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
8625 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
8627 /* Shift OTHER right POS places and make it the source, restricting it
8628 to the proper length and mode. */
8630 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
8634 src
= force_to_mode (src
, mode
,
8635 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
8636 ? ~(unsigned HOST_WIDE_INT
) 0
8637 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
8640 /* If SRC is masked by an AND that does not make a difference in
8641 the value being stored, strip it. */
8642 if (GET_CODE (assign
) == ZERO_EXTRACT
8643 && CONST_INT_P (XEXP (assign
, 1))
8644 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
8645 && GET_CODE (src
) == AND
8646 && CONST_INT_P (XEXP (src
, 1))
8647 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
8648 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
8649 src
= XEXP (src
, 0);
8651 return gen_rtx_SET (VOIDmode
, assign
, src
);
8654 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8658 apply_distributive_law (rtx x
)
8660 enum rtx_code code
= GET_CODE (x
);
8661 enum rtx_code inner_code
;
8662 rtx lhs
, rhs
, other
;
8665 /* Distributivity is not true for floating point as it can change the
8666 value. So we don't do it unless -funsafe-math-optimizations. */
8667 if (FLOAT_MODE_P (GET_MODE (x
))
8668 && ! flag_unsafe_math_optimizations
)
8671 /* The outer operation can only be one of the following: */
8672 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
8673 && code
!= PLUS
&& code
!= MINUS
)
8679 /* If either operand is a primitive we can't do anything, so get out
8681 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
8684 lhs
= expand_compound_operation (lhs
);
8685 rhs
= expand_compound_operation (rhs
);
8686 inner_code
= GET_CODE (lhs
);
8687 if (inner_code
!= GET_CODE (rhs
))
8690 /* See if the inner and outer operations distribute. */
8697 /* These all distribute except over PLUS. */
8698 if (code
== PLUS
|| code
== MINUS
)
8703 if (code
!= PLUS
&& code
!= MINUS
)
8708 /* This is also a multiply, so it distributes over everything. */
8712 /* Non-paradoxical SUBREGs distributes over all operations,
8713 provided the inner modes and byte offsets are the same, this
8714 is an extraction of a low-order part, we don't convert an fp
8715 operation to int or vice versa, this is not a vector mode,
8716 and we would not be converting a single-word operation into a
8717 multi-word operation. The latter test is not required, but
8718 it prevents generating unneeded multi-word operations. Some
8719 of the previous tests are redundant given the latter test,
8720 but are retained because they are required for correctness.
8722 We produce the result slightly differently in this case. */
8724 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
8725 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
8726 || ! subreg_lowpart_p (lhs
)
8727 || (GET_MODE_CLASS (GET_MODE (lhs
))
8728 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
8729 || (GET_MODE_SIZE (GET_MODE (lhs
))
8730 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
8731 || VECTOR_MODE_P (GET_MODE (lhs
))
8732 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
8733 /* Result might need to be truncated. Don't change mode if
8734 explicit truncation is needed. */
8735 || !TRULY_NOOP_TRUNCATION
8736 (GET_MODE_BITSIZE (GET_MODE (x
)),
8737 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs
)))))
8740 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
8741 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
8742 return gen_lowpart (GET_MODE (x
), tem
);
8748 /* Set LHS and RHS to the inner operands (A and B in the example
8749 above) and set OTHER to the common operand (C in the example).
8750 There is only one way to do this unless the inner operation is
8752 if (COMMUTATIVE_ARITH_P (lhs
)
8753 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8754 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8755 else if (COMMUTATIVE_ARITH_P (lhs
)
8756 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8757 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8758 else if (COMMUTATIVE_ARITH_P (lhs
)
8759 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8760 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8761 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8762 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8766 /* Form the new inner operation, seeing if it simplifies first. */
8767 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8769 /* There is one exception to the general way of distributing:
8770 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8771 if (code
== XOR
&& inner_code
== IOR
)
8774 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8777 /* We may be able to continuing distributing the result, so call
8778 ourselves recursively on the inner operation before forming the
8779 outer operation, which we return. */
8780 return simplify_gen_binary (inner_code
, GET_MODE (x
),
8781 apply_distributive_law (tem
), other
);
8784 /* See if X is of the form (* (+ A B) C), and if so convert to
8785 (+ (* A C) (* B C)) and try to simplify.
8787 Most of the time, this results in no change. However, if some of
8788 the operands are the same or inverses of each other, simplifications
8791 For example, (and (ior A B) (not B)) can occur as the result of
8792 expanding a bit field assignment. When we apply the distributive
8793 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8794 which then simplifies to (and (A (not B))).
8796 Note that no checks happen on the validity of applying the inverse
8797 distributive law. This is pointless since we can do it in the
8798 few places where this routine is called.
8800 N is the index of the term that is decomposed (the arithmetic operation,
8801 i.e. (+ A B) in the first example above). !N is the index of the term that
8802 is distributed, i.e. of C in the first example above. */
8804 distribute_and_simplify_rtx (rtx x
, int n
)
8806 enum machine_mode mode
;
8807 enum rtx_code outer_code
, inner_code
;
8808 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
8810 /* Distributivity is not true for floating point as it can change the
8811 value. So we don't do it unless -funsafe-math-optimizations. */
8812 if (FLOAT_MODE_P (GET_MODE (x
))
8813 && ! flag_unsafe_math_optimizations
)
8816 decomposed
= XEXP (x
, n
);
8817 if (!ARITHMETIC_P (decomposed
))
8820 mode
= GET_MODE (x
);
8821 outer_code
= GET_CODE (x
);
8822 distributed
= XEXP (x
, !n
);
8824 inner_code
= GET_CODE (decomposed
);
8825 inner_op0
= XEXP (decomposed
, 0);
8826 inner_op1
= XEXP (decomposed
, 1);
8828 /* Special case (and (xor B C) (not A)), which is equivalent to
8829 (xor (ior A B) (ior A C)) */
8830 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
8832 distributed
= XEXP (distributed
, 0);
8838 /* Distribute the second term. */
8839 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
8840 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
8844 /* Distribute the first term. */
8845 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
8846 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
8849 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
8851 if (GET_CODE (tmp
) != outer_code
8852 && rtx_cost (tmp
, SET
, optimize_this_for_speed_p
)
8853 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
8859 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8860 in MODE. Return an equivalent form, if different from (and VAROP
8861 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8864 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
8865 unsigned HOST_WIDE_INT constop
)
8867 unsigned HOST_WIDE_INT nonzero
;
8868 unsigned HOST_WIDE_INT orig_constop
;
8873 orig_constop
= constop
;
8874 if (GET_CODE (varop
) == CLOBBER
)
8877 /* Simplify VAROP knowing that we will be only looking at some of the
8880 Note by passing in CONSTOP, we guarantee that the bits not set in
8881 CONSTOP are not significant and will never be examined. We must
8882 ensure that is the case by explicitly masking out those bits
8883 before returning. */
8884 varop
= force_to_mode (varop
, mode
, constop
, 0);
8886 /* If VAROP is a CLOBBER, we will fail so return it. */
8887 if (GET_CODE (varop
) == CLOBBER
)
8890 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8891 to VAROP and return the new constant. */
8892 if (CONST_INT_P (varop
))
8893 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
8895 /* See what bits may be nonzero in VAROP. Unlike the general case of
8896 a call to nonzero_bits, here we don't care about bits outside
8899 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8901 /* Turn off all bits in the constant that are known to already be zero.
8902 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8903 which is tested below. */
8907 /* If we don't have any bits left, return zero. */
8911 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8912 a power of two, we can replace this with an ASHIFT. */
8913 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8914 && (i
= exact_log2 (constop
)) >= 0)
8915 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8917 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8918 or XOR, then try to apply the distributive law. This may eliminate
8919 operations if either branch can be simplified because of the AND.
8920 It may also make some cases more complex, but those cases probably
8921 won't match a pattern either with or without this. */
8923 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8927 apply_distributive_law
8928 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8929 simplify_and_const_int (NULL_RTX
,
8933 simplify_and_const_int (NULL_RTX
,
8938 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8939 the AND and see if one of the operands simplifies to zero. If so, we
8940 may eliminate it. */
8942 if (GET_CODE (varop
) == PLUS
8943 && exact_log2 (constop
+ 1) >= 0)
8947 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8948 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8949 if (o0
== const0_rtx
)
8951 if (o1
== const0_rtx
)
8955 /* Make a SUBREG if necessary. If we can't make it, fail. */
8956 varop
= gen_lowpart (mode
, varop
);
8957 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
8960 /* If we are only masking insignificant bits, return VAROP. */
8961 if (constop
== nonzero
)
8964 if (varop
== orig_varop
&& constop
== orig_constop
)
8967 /* Otherwise, return an AND. */
8968 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
8972 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8975 Return an equivalent form, if different from X. Otherwise, return X. If
8976 X is zero, we are to always construct the equivalent form. */
8979 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8980 unsigned HOST_WIDE_INT constop
)
8982 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
8987 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
8988 gen_int_mode (constop
, mode
));
8989 if (GET_MODE (x
) != mode
)
8990 x
= gen_lowpart (mode
, x
);
8994 /* Given a REG, X, compute which bits in X can be nonzero.
8995 We don't care about bits outside of those defined in MODE.
8997 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8998 a shift, AND, or zero_extract, we can do better. */
9001 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9002 const_rtx known_x ATTRIBUTE_UNUSED
,
9003 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9004 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9005 unsigned HOST_WIDE_INT
*nonzero
)
9010 /* If X is a register whose nonzero bits value is current, use it.
9011 Otherwise, if X is a register whose value we can find, use that
9012 value. Otherwise, use the previously-computed global nonzero bits
9013 for this register. */
9015 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9016 if (rsp
->last_set_value
!= 0
9017 && (rsp
->last_set_mode
== mode
9018 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9019 && GET_MODE_CLASS (mode
) == MODE_INT
))
9020 && ((rsp
->last_set_label
>= label_tick_ebb_start
9021 && rsp
->last_set_label
< label_tick
)
9022 || (rsp
->last_set_label
== label_tick
9023 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9024 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9025 && REG_N_SETS (REGNO (x
)) == 1
9027 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9029 *nonzero
&= rsp
->last_set_nonzero_bits
;
9033 tem
= get_last_value (x
);
9037 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9038 /* If X is narrower than MODE and TEM is a non-negative
9039 constant that would appear negative in the mode of X,
9040 sign-extend it for use in reg_nonzero_bits because some
9041 machines (maybe most) will actually do the sign-extension
9042 and this is the conservative approach.
9044 ??? For 2.5, try to tighten up the MD files in this regard
9045 instead of this kludge. */
9047 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
9048 && CONST_INT_P (tem
)
9050 && 0 != (INTVAL (tem
)
9051 & ((HOST_WIDE_INT
) 1
9052 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
9053 tem
= GEN_INT (INTVAL (tem
)
9054 | ((HOST_WIDE_INT
) (-1)
9055 << GET_MODE_BITSIZE (GET_MODE (x
))));
9059 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9061 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9063 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
9064 /* We don't know anything about the upper bits. */
9065 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9072 /* Return the number of bits at the high-order end of X that are known to
9073 be equal to the sign bit. X will be used in mode MODE; if MODE is
9074 VOIDmode, X will be used in its own mode. The returned value will always
9075 be between 1 and the number of bits in MODE. */
9078 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9079 const_rtx known_x ATTRIBUTE_UNUSED
,
9080 enum machine_mode known_mode
9082 unsigned int known_ret ATTRIBUTE_UNUSED
,
9083 unsigned int *result
)
9088 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9089 if (rsp
->last_set_value
!= 0
9090 && rsp
->last_set_mode
== mode
9091 && ((rsp
->last_set_label
>= label_tick_ebb_start
9092 && rsp
->last_set_label
< label_tick
)
9093 || (rsp
->last_set_label
== label_tick
9094 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9095 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9096 && REG_N_SETS (REGNO (x
)) == 1
9098 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9100 *result
= rsp
->last_set_sign_bit_copies
;
9104 tem
= get_last_value (x
);
9108 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9109 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
9110 *result
= rsp
->sign_bit_copies
;
9115 /* Return the number of "extended" bits there are in X, when interpreted
9116 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9117 unsigned quantities, this is the number of high-order zero bits.
9118 For signed quantities, this is the number of copies of the sign bit
9119 minus 1. In both case, this function returns the number of "spare"
9120 bits. For example, if two quantities for which this function returns
9121 at least 1 are added, the addition is known not to overflow.
9123 This function will always return 0 unless called during combine, which
9124 implies that it must be called from a define_split. */
9127 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9129 if (nonzero_sign_valid
== 0)
9133 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9134 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
9135 - floor_log2 (nonzero_bits (x
, mode
)))
9137 : num_sign_bit_copies (x
, mode
) - 1);
9140 /* This function is called from `simplify_shift_const' to merge two
9141 outer operations. Specifically, we have already found that we need
9142 to perform operation *POP0 with constant *PCONST0 at the outermost
9143 position. We would now like to also perform OP1 with constant CONST1
9144 (with *POP0 being done last).
9146 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9147 the resulting operation. *PCOMP_P is set to 1 if we would need to
9148 complement the innermost operand, otherwise it is unchanged.
9150 MODE is the mode in which the operation will be done. No bits outside
9151 the width of this mode matter. It is assumed that the width of this mode
9152 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9154 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9155 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9156 result is simply *PCONST0.
9158 If the resulting operation cannot be expressed as one operation, we
9159 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9162 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9164 enum rtx_code op0
= *pop0
;
9165 HOST_WIDE_INT const0
= *pconst0
;
9167 const0
&= GET_MODE_MASK (mode
);
9168 const1
&= GET_MODE_MASK (mode
);
9170 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9174 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9177 if (op1
== UNKNOWN
|| op0
== SET
)
9180 else if (op0
== UNKNOWN
)
9181 op0
= op1
, const0
= const1
;
9183 else if (op0
== op1
)
9207 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9208 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9211 /* If the two constants aren't the same, we can't do anything. The
9212 remaining six cases can all be done. */
9213 else if (const0
!= const1
)
9221 /* (a & b) | b == b */
9223 else /* op1 == XOR */
9224 /* (a ^ b) | b == a | b */
9230 /* (a & b) ^ b == (~a) & b */
9231 op0
= AND
, *pcomp_p
= 1;
9232 else /* op1 == IOR */
9233 /* (a | b) ^ b == a & ~b */
9234 op0
= AND
, const0
= ~const0
;
9239 /* (a | b) & b == b */
9241 else /* op1 == XOR */
9242 /* (a ^ b) & b) == (~a) & b */
9249 /* Check for NO-OP cases. */
9250 const0
&= GET_MODE_MASK (mode
);
9252 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9254 else if (const0
== 0 && op0
== AND
)
9256 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9262 /* ??? Slightly redundant with the above mask, but not entirely.
9263 Moving this above means we'd have to sign-extend the mode mask
9264 for the final test. */
9265 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9266 *pconst0
= trunc_int_for_mode (const0
, mode
);
9271 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9272 the shift in. The original shift operation CODE is performed on OP in
9273 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9274 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9275 result of the shift is subject to operation OUTER_CODE with operand
9278 static enum machine_mode
9279 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9280 enum machine_mode orig_mode
, enum machine_mode mode
,
9281 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9283 if (orig_mode
== mode
)
9285 gcc_assert (GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (orig_mode
));
9287 /* In general we can't perform in wider mode for right shift and rotate. */
9291 /* We can still widen if the bits brought in from the left are identical
9292 to the sign bit of ORIG_MODE. */
9293 if (num_sign_bit_copies (op
, mode
)
9294 > (unsigned) (GET_MODE_BITSIZE (mode
)
9295 - GET_MODE_BITSIZE (orig_mode
)))
9300 /* Similarly here but with zero bits. */
9301 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9302 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9305 /* We can also widen if the bits brought in will be masked off. This
9306 operation is performed in ORIG_MODE. */
9307 if (outer_code
== AND
)
9309 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9312 && GET_MODE_BITSIZE (orig_mode
) - care_bits
>= count
)
9328 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9329 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9330 simplify it. Otherwise, return a simplified value.
9332 The shift is normally computed in the widest mode we find in VAROP, as
9333 long as it isn't a different number of words than RESULT_MODE. Exceptions
9334 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9337 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9338 rtx varop
, int orig_count
)
9340 enum rtx_code orig_code
= code
;
9341 rtx orig_varop
= varop
;
9343 enum machine_mode mode
= result_mode
;
9344 enum machine_mode shift_mode
, tmode
;
9345 unsigned int mode_words
9346 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9347 /* We form (outer_op (code varop count) (outer_const)). */
9348 enum rtx_code outer_op
= UNKNOWN
;
9349 HOST_WIDE_INT outer_const
= 0;
9350 int complement_p
= 0;
9353 /* Make sure and truncate the "natural" shift on the way in. We don't
9354 want to do this inside the loop as it makes it more difficult to
9356 if (SHIFT_COUNT_TRUNCATED
)
9357 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9359 /* If we were given an invalid count, don't do anything except exactly
9360 what was requested. */
9362 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9367 /* Unless one of the branches of the `if' in this loop does a `continue',
9368 we will `break' the loop after the `if'. */
9372 /* If we have an operand of (clobber (const_int 0)), fail. */
9373 if (GET_CODE (varop
) == CLOBBER
)
9376 /* Convert ROTATERT to ROTATE. */
9377 if (code
== ROTATERT
)
9379 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9381 if (VECTOR_MODE_P (result_mode
))
9382 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9384 count
= bitsize
- count
;
9387 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9388 mode
, outer_op
, outer_const
);
9390 /* Handle cases where the count is greater than the size of the mode
9391 minus 1. For ASHIFT, use the size minus one as the count (this can
9392 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9393 take the count modulo the size. For other shifts, the result is
9396 Since these shifts are being produced by the compiler by combining
9397 multiple operations, each of which are defined, we know what the
9398 result is supposed to be. */
9400 if (count
> (GET_MODE_BITSIZE (shift_mode
) - 1))
9402 if (code
== ASHIFTRT
)
9403 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9404 else if (code
== ROTATE
|| code
== ROTATERT
)
9405 count
%= GET_MODE_BITSIZE (shift_mode
);
9408 /* We can't simply return zero because there may be an
9416 /* If we discovered we had to complement VAROP, leave. Making a NOT
9417 here would cause an infinite loop. */
9421 /* An arithmetic right shift of a quantity known to be -1 or 0
9423 if (code
== ASHIFTRT
9424 && (num_sign_bit_copies (varop
, shift_mode
)
9425 == GET_MODE_BITSIZE (shift_mode
)))
9431 /* If we are doing an arithmetic right shift and discarding all but
9432 the sign bit copies, this is equivalent to doing a shift by the
9433 bitsize minus one. Convert it into that shift because it will often
9434 allow other simplifications. */
9436 if (code
== ASHIFTRT
9437 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9438 >= GET_MODE_BITSIZE (shift_mode
)))
9439 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9441 /* We simplify the tests below and elsewhere by converting
9442 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9443 `make_compound_operation' will convert it to an ASHIFTRT for
9444 those machines (such as VAX) that don't have an LSHIFTRT. */
9445 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9447 && ((nonzero_bits (varop
, shift_mode
)
9448 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9452 if (((code
== LSHIFTRT
9453 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9454 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9456 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9457 && !((nonzero_bits (varop
, shift_mode
) << count
)
9458 & GET_MODE_MASK (shift_mode
))))
9459 && !side_effects_p (varop
))
9462 switch (GET_CODE (varop
))
9468 new_rtx
= expand_compound_operation (varop
);
9469 if (new_rtx
!= varop
)
9477 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9478 minus the width of a smaller mode, we can do this with a
9479 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9480 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9481 && ! mode_dependent_address_p (XEXP (varop
, 0))
9482 && ! MEM_VOLATILE_P (varop
)
9483 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9484 MODE_INT
, 1)) != BLKmode
)
9486 new_rtx
= adjust_address_nv (varop
, tmode
,
9487 BYTES_BIG_ENDIAN
? 0
9488 : count
/ BITS_PER_UNIT
);
9490 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9491 : ZERO_EXTEND
, mode
, new_rtx
);
9498 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9499 the same number of words as what we've seen so far. Then store
9500 the widest mode in MODE. */
9501 if (subreg_lowpart_p (varop
)
9502 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9503 > GET_MODE_SIZE (GET_MODE (varop
)))
9504 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9505 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9508 varop
= SUBREG_REG (varop
);
9509 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9510 mode
= GET_MODE (varop
);
9516 /* Some machines use MULT instead of ASHIFT because MULT
9517 is cheaper. But it is still better on those machines to
9518 merge two shifts into one. */
9519 if (CONST_INT_P (XEXP (varop
, 1))
9520 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9523 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9525 GEN_INT (exact_log2 (
9526 INTVAL (XEXP (varop
, 1)))));
9532 /* Similar, for when divides are cheaper. */
9533 if (CONST_INT_P (XEXP (varop
, 1))
9534 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9537 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9539 GEN_INT (exact_log2 (
9540 INTVAL (XEXP (varop
, 1)))));
9546 /* If we are extracting just the sign bit of an arithmetic
9547 right shift, that shift is not needed. However, the sign
9548 bit of a wider mode may be different from what would be
9549 interpreted as the sign bit in a narrower mode, so, if
9550 the result is narrower, don't discard the shift. */
9551 if (code
== LSHIFTRT
9552 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9553 && (GET_MODE_BITSIZE (result_mode
)
9554 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9556 varop
= XEXP (varop
, 0);
9560 /* ... fall through ... */
9565 /* Here we have two nested shifts. The result is usually the
9566 AND of a new shift with a mask. We compute the result below. */
9567 if (CONST_INT_P (XEXP (varop
, 1))
9568 && INTVAL (XEXP (varop
, 1)) >= 0
9569 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9570 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9571 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9572 && !VECTOR_MODE_P (result_mode
))
9574 enum rtx_code first_code
= GET_CODE (varop
);
9575 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9576 unsigned HOST_WIDE_INT mask
;
9579 /* We have one common special case. We can't do any merging if
9580 the inner code is an ASHIFTRT of a smaller mode. However, if
9581 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9582 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9583 we can convert it to
9584 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9585 This simplifies certain SIGN_EXTEND operations. */
9586 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9587 && count
== (GET_MODE_BITSIZE (result_mode
)
9588 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9590 /* C3 has the low-order C1 bits zero. */
9592 mask
= (GET_MODE_MASK (mode
)
9593 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9595 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9596 XEXP (varop
, 0), mask
);
9597 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9599 count
= first_count
;
9604 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9605 than C1 high-order bits equal to the sign bit, we can convert
9606 this to either an ASHIFT or an ASHIFTRT depending on the
9609 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9611 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9612 && GET_MODE (varop
) == shift_mode
9613 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9616 varop
= XEXP (varop
, 0);
9617 count
-= first_count
;
9627 /* There are some cases we can't do. If CODE is ASHIFTRT,
9628 we can only do this if FIRST_CODE is also ASHIFTRT.
9630 We can't do the case when CODE is ROTATE and FIRST_CODE is
9633 If the mode of this shift is not the mode of the outer shift,
9634 we can't do this if either shift is a right shift or ROTATE.
9636 Finally, we can't do any of these if the mode is too wide
9637 unless the codes are the same.
9639 Handle the case where the shift codes are the same
9642 if (code
== first_code
)
9644 if (GET_MODE (varop
) != result_mode
9645 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9649 count
+= first_count
;
9650 varop
= XEXP (varop
, 0);
9654 if (code
== ASHIFTRT
9655 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9656 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9657 || (GET_MODE (varop
) != result_mode
9658 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9659 || first_code
== ROTATE
9660 || code
== ROTATE
)))
9663 /* To compute the mask to apply after the shift, shift the
9664 nonzero bits of the inner shift the same way the
9665 outer shift will. */
9667 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9670 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
9673 /* Give up if we can't compute an outer operation to use. */
9675 || !CONST_INT_P (mask_rtx
)
9676 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9678 result_mode
, &complement_p
))
9681 /* If the shifts are in the same direction, we add the
9682 counts. Otherwise, we subtract them. */
9683 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9684 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9685 count
+= first_count
;
9687 count
-= first_count
;
9689 /* If COUNT is positive, the new shift is usually CODE,
9690 except for the two exceptions below, in which case it is
9691 FIRST_CODE. If the count is negative, FIRST_CODE should
9694 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9695 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9698 code
= first_code
, count
= -count
;
9700 varop
= XEXP (varop
, 0);
9704 /* If we have (A << B << C) for any shift, we can convert this to
9705 (A << C << B). This wins if A is a constant. Only try this if
9706 B is not a constant. */
9708 else if (GET_CODE (varop
) == code
9709 && CONST_INT_P (XEXP (varop
, 0))
9710 && !CONST_INT_P (XEXP (varop
, 1)))
9712 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
9715 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
9722 if (VECTOR_MODE_P (mode
))
9725 /* Make this fit the case below. */
9726 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9727 GEN_INT (GET_MODE_MASK (mode
)));
9733 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9734 with C the size of VAROP - 1 and the shift is logical if
9735 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9736 we have an (le X 0) operation. If we have an arithmetic shift
9737 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9738 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9740 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9741 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9742 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9743 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9744 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9745 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9748 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9751 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9752 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9757 /* If we have (shift (logical)), move the logical to the outside
9758 to allow it to possibly combine with another logical and the
9759 shift to combine with another shift. This also canonicalizes to
9760 what a ZERO_EXTRACT looks like. Also, some machines have
9761 (and (shift)) insns. */
9763 if (CONST_INT_P (XEXP (varop
, 1))
9764 /* We can't do this if we have (ashiftrt (xor)) and the
9765 constant has its sign bit set in shift_mode. */
9766 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9767 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9769 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
9771 GEN_INT (count
))) != 0
9772 && CONST_INT_P (new_rtx
)
9773 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9774 INTVAL (new_rtx
), result_mode
, &complement_p
))
9776 varop
= XEXP (varop
, 0);
9780 /* If we can't do that, try to simplify the shift in each arm of the
9781 logical expression, make a new logical expression, and apply
9782 the inverse distributive law. This also can't be done
9783 for some (ashiftrt (xor)). */
9784 if (CONST_INT_P (XEXP (varop
, 1))
9785 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9786 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9789 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9790 XEXP (varop
, 0), count
);
9791 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9792 XEXP (varop
, 1), count
);
9794 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
9796 varop
= apply_distributive_law (varop
);
9804 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9805 says that the sign bit can be tested, FOO has mode MODE, C is
9806 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9807 that may be nonzero. */
9808 if (code
== LSHIFTRT
9809 && XEXP (varop
, 1) == const0_rtx
9810 && GET_MODE (XEXP (varop
, 0)) == result_mode
9811 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9812 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9813 && STORE_FLAG_VALUE
== -1
9814 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9815 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9816 (HOST_WIDE_INT
) 1, result_mode
,
9819 varop
= XEXP (varop
, 0);
9826 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9827 than the number of bits in the mode is equivalent to A. */
9828 if (code
== LSHIFTRT
9829 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9830 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9832 varop
= XEXP (varop
, 0);
9837 /* NEG commutes with ASHIFT since it is multiplication. Move the
9838 NEG outside to allow shifts to combine. */
9840 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9841 (HOST_WIDE_INT
) 0, result_mode
,
9844 varop
= XEXP (varop
, 0);
9850 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9851 is one less than the number of bits in the mode is
9852 equivalent to (xor A 1). */
9853 if (code
== LSHIFTRT
9854 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9855 && XEXP (varop
, 1) == constm1_rtx
9856 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9857 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9858 (HOST_WIDE_INT
) 1, result_mode
,
9862 varop
= XEXP (varop
, 0);
9866 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9867 that might be nonzero in BAR are those being shifted out and those
9868 bits are known zero in FOO, we can replace the PLUS with FOO.
9869 Similarly in the other operand order. This code occurs when
9870 we are computing the size of a variable-size array. */
9872 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9873 && count
< HOST_BITS_PER_WIDE_INT
9874 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9875 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9876 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9878 varop
= XEXP (varop
, 0);
9881 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9882 && count
< HOST_BITS_PER_WIDE_INT
9883 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9884 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9886 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9887 & nonzero_bits (XEXP (varop
, 1),
9890 varop
= XEXP (varop
, 1);
9894 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9896 && CONST_INT_P (XEXP (varop
, 1))
9897 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
9899 GEN_INT (count
))) != 0
9900 && CONST_INT_P (new_rtx
)
9901 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9902 INTVAL (new_rtx
), result_mode
, &complement_p
))
9904 varop
= XEXP (varop
, 0);
9908 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9909 signbit', and attempt to change the PLUS to an XOR and move it to
9910 the outer operation as is done above in the AND/IOR/XOR case
9911 leg for shift(logical). See details in logical handling above
9912 for reasoning in doing so. */
9913 if (code
== LSHIFTRT
9914 && CONST_INT_P (XEXP (varop
, 1))
9915 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9916 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
9918 GEN_INT (count
))) != 0
9919 && CONST_INT_P (new_rtx
)
9920 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9921 INTVAL (new_rtx
), result_mode
, &complement_p
))
9923 varop
= XEXP (varop
, 0);
9930 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9931 with C the size of VAROP - 1 and the shift is logical if
9932 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9933 we have a (gt X 0) operation. If the shift is arithmetic with
9934 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9935 we have a (neg (gt X 0)) operation. */
9937 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9938 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9939 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9940 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9941 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
9942 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9943 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9946 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9949 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9950 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9957 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9958 if the truncate does not affect the value. */
9959 if (code
== LSHIFTRT
9960 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9961 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
9962 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9963 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9964 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9966 rtx varop_inner
= XEXP (varop
, 0);
9969 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9970 XEXP (varop_inner
, 0),
9972 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9973 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9986 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
9987 outer_op
, outer_const
);
9989 /* We have now finished analyzing the shift. The result should be
9990 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9991 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9992 to the result of the shift. OUTER_CONST is the relevant constant,
9993 but we must turn off all bits turned off in the shift. */
9995 if (outer_op
== UNKNOWN
9996 && orig_code
== code
&& orig_count
== count
9997 && varop
== orig_varop
9998 && shift_mode
== GET_MODE (varop
))
10001 /* Make a SUBREG if necessary. If we can't make it, fail. */
10002 varop
= gen_lowpart (shift_mode
, varop
);
10003 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10006 /* If we have an outer operation and we just made a shift, it is
10007 possible that we could have simplified the shift were it not
10008 for the outer operation. So try to do the simplification
10011 if (outer_op
!= UNKNOWN
)
10012 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10017 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10019 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10020 turn off all the bits that the shift would have turned off. */
10021 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10022 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10023 GET_MODE_MASK (result_mode
) >> orig_count
);
10025 /* Do the remainder of the processing in RESULT_MODE. */
10026 x
= gen_lowpart_or_truncate (result_mode
, x
);
10028 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10031 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10033 if (outer_op
!= UNKNOWN
)
10035 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10036 && GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10037 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10039 if (outer_op
== AND
)
10040 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10041 else if (outer_op
== SET
)
10043 /* This means that we have determined that the result is
10044 equivalent to a constant. This should be rare. */
10045 if (!side_effects_p (x
))
10046 x
= GEN_INT (outer_const
);
10048 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10049 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10051 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10052 GEN_INT (outer_const
));
10058 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10059 The result of the shift is RESULT_MODE. If we cannot simplify it,
10060 return X or, if it is NULL, synthesize the expression with
10061 simplify_gen_binary. Otherwise, return a simplified value.
10063 The shift is normally computed in the widest mode we find in VAROP, as
10064 long as it isn't a different number of words than RESULT_MODE. Exceptions
10065 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10068 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10069 rtx varop
, int count
)
10071 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10076 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10077 if (GET_MODE (x
) != result_mode
)
10078 x
= gen_lowpart (result_mode
, x
);
10083 /* Like recog, but we receive the address of a pointer to a new pattern.
10084 We try to match the rtx that the pointer points to.
10085 If that fails, we may try to modify or replace the pattern,
10086 storing the replacement into the same pointer object.
10088 Modifications include deletion or addition of CLOBBERs.
10090 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10091 the CLOBBERs are placed.
10093 The value is the final insn code from the pattern ultimately matched,
10097 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10099 rtx pat
= *pnewpat
;
10100 int insn_code_number
;
10101 int num_clobbers_to_add
= 0;
10104 rtx old_notes
, old_pat
;
10106 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10107 we use to indicate that something didn't match. If we find such a
10108 thing, force rejection. */
10109 if (GET_CODE (pat
) == PARALLEL
)
10110 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10111 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10112 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10115 old_pat
= PATTERN (insn
);
10116 old_notes
= REG_NOTES (insn
);
10117 PATTERN (insn
) = pat
;
10118 REG_NOTES (insn
) = 0;
10120 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10121 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10123 if (insn_code_number
< 0)
10124 fputs ("Failed to match this instruction:\n", dump_file
);
10126 fputs ("Successfully matched this instruction:\n", dump_file
);
10127 print_rtl_single (dump_file
, pat
);
10130 /* If it isn't, there is the possibility that we previously had an insn
10131 that clobbered some register as a side effect, but the combined
10132 insn doesn't need to do that. So try once more without the clobbers
10133 unless this represents an ASM insn. */
10135 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10136 && GET_CODE (pat
) == PARALLEL
)
10140 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10141 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10144 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10148 SUBST_INT (XVECLEN (pat
, 0), pos
);
10151 pat
= XVECEXP (pat
, 0, 0);
10153 PATTERN (insn
) = pat
;
10154 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10155 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10157 if (insn_code_number
< 0)
10158 fputs ("Failed to match this instruction:\n", dump_file
);
10160 fputs ("Successfully matched this instruction:\n", dump_file
);
10161 print_rtl_single (dump_file
, pat
);
10164 PATTERN (insn
) = old_pat
;
10165 REG_NOTES (insn
) = old_notes
;
10167 /* Recognize all noop sets, these will be killed by followup pass. */
10168 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10169 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10171 /* If we had any clobbers to add, make a new pattern than contains
10172 them. Then check to make sure that all of them are dead. */
10173 if (num_clobbers_to_add
)
10175 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10176 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10177 ? (XVECLEN (pat
, 0)
10178 + num_clobbers_to_add
)
10179 : num_clobbers_to_add
+ 1));
10181 if (GET_CODE (pat
) == PARALLEL
)
10182 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10183 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10185 XVECEXP (newpat
, 0, 0) = pat
;
10187 add_clobbers (newpat
, insn_code_number
);
10189 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10190 i
< XVECLEN (newpat
, 0); i
++)
10192 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10193 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10195 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10197 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10198 notes
= alloc_reg_note (REG_UNUSED
,
10199 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10208 return insn_code_number
;
10211 /* Like gen_lowpart_general but for use by combine. In combine it
10212 is not possible to create any new pseudoregs. However, it is
10213 safe to create invalid memory addresses, because combine will
10214 try to recognize them and all they will do is make the combine
10217 If for some reason this cannot do its job, an rtx
10218 (clobber (const_int 0)) is returned.
10219 An insn containing that will not be recognized. */
10222 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10224 enum machine_mode imode
= GET_MODE (x
);
10225 unsigned int osize
= GET_MODE_SIZE (omode
);
10226 unsigned int isize
= GET_MODE_SIZE (imode
);
10229 if (omode
== imode
)
10232 /* Return identity if this is a CONST or symbolic reference. */
10234 && (GET_CODE (x
) == CONST
10235 || GET_CODE (x
) == SYMBOL_REF
10236 || GET_CODE (x
) == LABEL_REF
))
10239 /* We can only support MODE being wider than a word if X is a
10240 constant integer or has a mode the same size. */
10241 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10242 && ! ((imode
== VOIDmode
10243 && (CONST_INT_P (x
)
10244 || GET_CODE (x
) == CONST_DOUBLE
))
10245 || isize
== osize
))
10248 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10249 won't know what to do. So we will strip off the SUBREG here and
10250 process normally. */
10251 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10253 x
= SUBREG_REG (x
);
10255 /* For use in case we fall down into the address adjustments
10256 further below, we need to adjust the known mode and size of
10257 x; imode and isize, since we just adjusted x. */
10258 imode
= GET_MODE (x
);
10260 if (imode
== omode
)
10263 isize
= GET_MODE_SIZE (imode
);
10266 result
= gen_lowpart_common (omode
, x
);
10275 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10277 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10280 /* If we want to refer to something bigger than the original memref,
10281 generate a paradoxical subreg instead. That will force a reload
10282 of the original memref X. */
10284 return gen_rtx_SUBREG (omode
, x
, 0);
10286 if (WORDS_BIG_ENDIAN
)
10287 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10289 /* Adjust the address so that the address-after-the-data is
10291 if (BYTES_BIG_ENDIAN
)
10292 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10294 return adjust_address_nv (x
, omode
, offset
);
10297 /* If X is a comparison operator, rewrite it in a new mode. This
10298 probably won't match, but may allow further simplifications. */
10299 else if (COMPARISON_P (x
))
10300 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10302 /* If we couldn't simplify X any other way, just enclose it in a
10303 SUBREG. Normally, this SUBREG won't match, but some patterns may
10304 include an explicit SUBREG or we may simplify it further in combine. */
10310 offset
= subreg_lowpart_offset (omode
, imode
);
10311 if (imode
== VOIDmode
)
10313 imode
= int_mode_for_mode (omode
);
10314 x
= gen_lowpart_common (imode
, x
);
10318 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10324 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10327 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10328 comparison code that will be tested.
10330 The result is a possibly different comparison code to use. *POP0 and
10331 *POP1 may be updated.
10333 It is possible that we might detect that a comparison is either always
10334 true or always false. However, we do not perform general constant
10335 folding in combine, so this knowledge isn't useful. Such tautologies
10336 should have been detected earlier. Hence we ignore all such cases. */
10338 static enum rtx_code
10339 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10345 enum machine_mode mode
, tmode
;
10347 /* Try a few ways of applying the same transformation to both operands. */
10350 #ifndef WORD_REGISTER_OPERATIONS
10351 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10352 so check specially. */
10353 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10354 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10355 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10356 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10357 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10358 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10359 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10360 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10361 && CONST_INT_P (XEXP (op0
, 1))
10362 && XEXP (op0
, 1) == XEXP (op1
, 1)
10363 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10364 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10365 && (INTVAL (XEXP (op0
, 1))
10366 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10367 - (GET_MODE_BITSIZE
10368 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10370 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10371 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10375 /* If both operands are the same constant shift, see if we can ignore the
10376 shift. We can if the shift is a rotate or if the bits shifted out of
10377 this shift are known to be zero for both inputs and if the type of
10378 comparison is compatible with the shift. */
10379 if (GET_CODE (op0
) == GET_CODE (op1
)
10380 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10381 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10382 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10383 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10384 || (GET_CODE (op0
) == ASHIFTRT
10385 && (code
!= GTU
&& code
!= LTU
10386 && code
!= GEU
&& code
!= LEU
)))
10387 && CONST_INT_P (XEXP (op0
, 1))
10388 && INTVAL (XEXP (op0
, 1)) >= 0
10389 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10390 && XEXP (op0
, 1) == XEXP (op1
, 1))
10392 enum machine_mode mode
= GET_MODE (op0
);
10393 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10394 int shift_count
= INTVAL (XEXP (op0
, 1));
10396 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10397 mask
&= (mask
>> shift_count
) << shift_count
;
10398 else if (GET_CODE (op0
) == ASHIFT
)
10399 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10401 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10402 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10403 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10408 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10409 SUBREGs are of the same mode, and, in both cases, the AND would
10410 be redundant if the comparison was done in the narrower mode,
10411 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10412 and the operand's possibly nonzero bits are 0xffffff01; in that case
10413 if we only care about QImode, we don't need the AND). This case
10414 occurs if the output mode of an scc insn is not SImode and
10415 STORE_FLAG_VALUE == 1 (e.g., the 386).
10417 Similarly, check for a case where the AND's are ZERO_EXTEND
10418 operations from some narrower mode even though a SUBREG is not
10421 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10422 && CONST_INT_P (XEXP (op0
, 1))
10423 && CONST_INT_P (XEXP (op1
, 1)))
10425 rtx inner_op0
= XEXP (op0
, 0);
10426 rtx inner_op1
= XEXP (op1
, 0);
10427 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10428 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10431 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10432 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10433 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10434 && (GET_MODE (SUBREG_REG (inner_op0
))
10435 == GET_MODE (SUBREG_REG (inner_op1
)))
10436 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10437 <= HOST_BITS_PER_WIDE_INT
)
10438 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10439 GET_MODE (SUBREG_REG (inner_op0
)))))
10440 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10441 GET_MODE (SUBREG_REG (inner_op1
))))))
10443 op0
= SUBREG_REG (inner_op0
);
10444 op1
= SUBREG_REG (inner_op1
);
10446 /* The resulting comparison is always unsigned since we masked
10447 off the original sign bit. */
10448 code
= unsigned_condition (code
);
10454 for (tmode
= GET_CLASS_NARROWEST_MODE
10455 (GET_MODE_CLASS (GET_MODE (op0
)));
10456 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10457 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10459 op0
= gen_lowpart (tmode
, inner_op0
);
10460 op1
= gen_lowpart (tmode
, inner_op1
);
10461 code
= unsigned_condition (code
);
10470 /* If both operands are NOT, we can strip off the outer operation
10471 and adjust the comparison code for swapped operands; similarly for
10472 NEG, except that this must be an equality comparison. */
10473 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10474 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10475 && (code
== EQ
|| code
== NE
)))
10476 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10482 /* If the first operand is a constant, swap the operands and adjust the
10483 comparison code appropriately, but don't do this if the second operand
10484 is already a constant integer. */
10485 if (swap_commutative_operands_p (op0
, op1
))
10487 tem
= op0
, op0
= op1
, op1
= tem
;
10488 code
= swap_condition (code
);
10491 /* We now enter a loop during which we will try to simplify the comparison.
10492 For the most part, we only are concerned with comparisons with zero,
10493 but some things may really be comparisons with zero but not start
10494 out looking that way. */
10496 while (CONST_INT_P (op1
))
10498 enum machine_mode mode
= GET_MODE (op0
);
10499 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10500 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10501 int equality_comparison_p
;
10502 int sign_bit_comparison_p
;
10503 int unsigned_comparison_p
;
10504 HOST_WIDE_INT const_op
;
10506 /* We only want to handle integral modes. This catches VOIDmode,
10507 CCmode, and the floating-point modes. An exception is that we
10508 can handle VOIDmode if OP0 is a COMPARE or a comparison
10511 if (GET_MODE_CLASS (mode
) != MODE_INT
10512 && ! (mode
== VOIDmode
10513 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10516 /* Get the constant we are comparing against and turn off all bits
10517 not on in our mode. */
10518 const_op
= INTVAL (op1
);
10519 if (mode
!= VOIDmode
)
10520 const_op
= trunc_int_for_mode (const_op
, mode
);
10521 op1
= GEN_INT (const_op
);
10523 /* If we are comparing against a constant power of two and the value
10524 being compared can only have that single bit nonzero (e.g., it was
10525 `and'ed with that bit), we can replace this with a comparison
10528 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10529 || code
== LT
|| code
== LTU
)
10530 && mode_width
<= HOST_BITS_PER_WIDE_INT
10531 && exact_log2 (const_op
) >= 0
10532 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10534 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10535 op1
= const0_rtx
, const_op
= 0;
10538 /* Similarly, if we are comparing a value known to be either -1 or
10539 0 with -1, change it to the opposite comparison against zero. */
10542 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10543 || code
== GEU
|| code
== LTU
)
10544 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10546 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10547 op1
= const0_rtx
, const_op
= 0;
10550 /* Do some canonicalizations based on the comparison code. We prefer
10551 comparisons against zero and then prefer equality comparisons.
10552 If we can reduce the size of a constant, we will do that too. */
10557 /* < C is equivalent to <= (C - 1) */
10561 op1
= GEN_INT (const_op
);
10563 /* ... fall through to LE case below. */
10569 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10573 op1
= GEN_INT (const_op
);
10577 /* If we are doing a <= 0 comparison on a value known to have
10578 a zero sign bit, we can replace this with == 0. */
10579 else if (const_op
== 0
10580 && mode_width
<= HOST_BITS_PER_WIDE_INT
10581 && (nonzero_bits (op0
, mode
)
10582 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10587 /* >= C is equivalent to > (C - 1). */
10591 op1
= GEN_INT (const_op
);
10593 /* ... fall through to GT below. */
10599 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10603 op1
= GEN_INT (const_op
);
10607 /* If we are doing a > 0 comparison on a value known to have
10608 a zero sign bit, we can replace this with != 0. */
10609 else if (const_op
== 0
10610 && mode_width
<= HOST_BITS_PER_WIDE_INT
10611 && (nonzero_bits (op0
, mode
)
10612 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10617 /* < C is equivalent to <= (C - 1). */
10621 op1
= GEN_INT (const_op
);
10623 /* ... fall through ... */
10626 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10627 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10628 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10630 const_op
= 0, op1
= const0_rtx
;
10638 /* unsigned <= 0 is equivalent to == 0 */
10642 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10643 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10644 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10646 const_op
= 0, op1
= const0_rtx
;
10652 /* >= C is equivalent to > (C - 1). */
10656 op1
= GEN_INT (const_op
);
10658 /* ... fall through ... */
10661 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10662 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10663 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10665 const_op
= 0, op1
= const0_rtx
;
10673 /* unsigned > 0 is equivalent to != 0 */
10677 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10678 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10679 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10681 const_op
= 0, op1
= const0_rtx
;
10690 /* Compute some predicates to simplify code below. */
10692 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10693 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10694 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10697 /* If this is a sign bit comparison and we can do arithmetic in
10698 MODE, say that we will only be needing the sign bit of OP0. */
10699 if (sign_bit_comparison_p
10700 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10701 op0
= force_to_mode (op0
, mode
,
10703 << (GET_MODE_BITSIZE (mode
) - 1)),
10706 /* Now try cases based on the opcode of OP0. If none of the cases
10707 does a "continue", we exit this loop immediately after the
10710 switch (GET_CODE (op0
))
10713 /* If we are extracting a single bit from a variable position in
10714 a constant that has only a single bit set and are comparing it
10715 with zero, we can convert this into an equality comparison
10716 between the position and the location of the single bit. */
10717 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10718 have already reduced the shift count modulo the word size. */
10719 if (!SHIFT_COUNT_TRUNCATED
10720 && CONST_INT_P (XEXP (op0
, 0))
10721 && XEXP (op0
, 1) == const1_rtx
10722 && equality_comparison_p
&& const_op
== 0
10723 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10725 if (BITS_BIG_ENDIAN
)
10727 enum machine_mode new_mode
10728 = mode_for_extraction (EP_extzv
, 1);
10729 if (new_mode
== MAX_MACHINE_MODE
)
10730 i
= BITS_PER_WORD
- 1 - i
;
10734 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10738 op0
= XEXP (op0
, 2);
10742 /* Result is nonzero iff shift count is equal to I. */
10743 code
= reverse_condition (code
);
10747 /* ... fall through ... */
10750 tem
= expand_compound_operation (op0
);
10759 /* If testing for equality, we can take the NOT of the constant. */
10760 if (equality_comparison_p
10761 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10763 op0
= XEXP (op0
, 0);
10768 /* If just looking at the sign bit, reverse the sense of the
10770 if (sign_bit_comparison_p
)
10772 op0
= XEXP (op0
, 0);
10773 code
= (code
== GE
? LT
: GE
);
10779 /* If testing for equality, we can take the NEG of the constant. */
10780 if (equality_comparison_p
10781 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10783 op0
= XEXP (op0
, 0);
10788 /* The remaining cases only apply to comparisons with zero. */
10792 /* When X is ABS or is known positive,
10793 (neg X) is < 0 if and only if X != 0. */
10795 if (sign_bit_comparison_p
10796 && (GET_CODE (XEXP (op0
, 0)) == ABS
10797 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10798 && (nonzero_bits (XEXP (op0
, 0), mode
)
10799 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10801 op0
= XEXP (op0
, 0);
10802 code
= (code
== LT
? NE
: EQ
);
10806 /* If we have NEG of something whose two high-order bits are the
10807 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10808 if (num_sign_bit_copies (op0
, mode
) >= 2)
10810 op0
= XEXP (op0
, 0);
10811 code
= swap_condition (code
);
10817 /* If we are testing equality and our count is a constant, we
10818 can perform the inverse operation on our RHS. */
10819 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
10820 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10821 op1
, XEXP (op0
, 1))) != 0)
10823 op0
= XEXP (op0
, 0);
10828 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10829 a particular bit. Convert it to an AND of a constant of that
10830 bit. This will be converted into a ZERO_EXTRACT. */
10831 if (const_op
== 0 && sign_bit_comparison_p
10832 && CONST_INT_P (XEXP (op0
, 1))
10833 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10835 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10838 - INTVAL (XEXP (op0
, 1)))));
10839 code
= (code
== LT
? NE
: EQ
);
10843 /* Fall through. */
10846 /* ABS is ignorable inside an equality comparison with zero. */
10847 if (const_op
== 0 && equality_comparison_p
)
10849 op0
= XEXP (op0
, 0);
10855 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10856 (compare FOO CONST) if CONST fits in FOO's mode and we
10857 are either testing inequality or have an unsigned
10858 comparison with ZERO_EXTEND or a signed comparison with
10859 SIGN_EXTEND. But don't do it if we don't have a compare
10860 insn of the given mode, since we'd have to revert it
10861 later on, and then we wouldn't know whether to sign- or
10863 mode
= GET_MODE (XEXP (op0
, 0));
10864 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10865 && ! unsigned_comparison_p
10866 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10867 && ((unsigned HOST_WIDE_INT
) const_op
10868 < (((unsigned HOST_WIDE_INT
) 1
10869 << (GET_MODE_BITSIZE (mode
) - 1))))
10870 && have_insn_for (COMPARE
, mode
))
10872 op0
= XEXP (op0
, 0);
10878 /* Check for the case where we are comparing A - C1 with C2, that is
10880 (subreg:MODE (plus (A) (-C1))) op (C2)
10882 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10883 comparison in the wider mode. One of the following two conditions
10884 must be true in order for this to be valid:
10886 1. The mode extension results in the same bit pattern being added
10887 on both sides and the comparison is equality or unsigned. As
10888 C2 has been truncated to fit in MODE, the pattern can only be
10891 2. The mode extension results in the sign bit being copied on
10894 The difficulty here is that we have predicates for A but not for
10895 (A - C1) so we need to check that C1 is within proper bounds so
10896 as to perturbate A as little as possible. */
10898 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10899 && subreg_lowpart_p (op0
)
10900 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10901 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10902 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
10904 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10905 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10906 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10909 && (unsigned HOST_WIDE_INT
) c1
10910 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10911 && (equality_comparison_p
|| unsigned_comparison_p
)
10912 /* (A - C1) zero-extends if it is positive and sign-extends
10913 if it is negative, C2 both zero- and sign-extends. */
10914 && ((0 == (nonzero_bits (a
, inner_mode
)
10915 & ~GET_MODE_MASK (mode
))
10917 /* (A - C1) sign-extends if it is positive and 1-extends
10918 if it is negative, C2 both sign- and 1-extends. */
10919 || (num_sign_bit_copies (a
, inner_mode
)
10920 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10923 || ((unsigned HOST_WIDE_INT
) c1
10924 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10925 /* (A - C1) always sign-extends, like C2. */
10926 && num_sign_bit_copies (a
, inner_mode
)
10927 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10928 - (mode_width
- 1))))
10930 op0
= SUBREG_REG (op0
);
10935 /* If the inner mode is narrower and we are extracting the low part,
10936 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10937 if (subreg_lowpart_p (op0
)
10938 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10939 /* Fall through */ ;
10943 /* ... fall through ... */
10946 mode
= GET_MODE (XEXP (op0
, 0));
10947 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10948 && (unsigned_comparison_p
|| equality_comparison_p
)
10949 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10950 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
10951 && have_insn_for (COMPARE
, mode
))
10953 op0
= XEXP (op0
, 0);
10959 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10960 this for equality comparisons due to pathological cases involving
10962 if (equality_comparison_p
10963 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10964 op1
, XEXP (op0
, 1))))
10966 op0
= XEXP (op0
, 0);
10971 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10972 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10973 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10975 op0
= XEXP (XEXP (op0
, 0), 0);
10976 code
= (code
== LT
? EQ
: NE
);
10982 /* We used to optimize signed comparisons against zero, but that
10983 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10984 arrive here as equality comparisons, or (GEU, LTU) are
10985 optimized away. No need to special-case them. */
10987 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10988 (eq B (minus A C)), whichever simplifies. We can only do
10989 this for equality comparisons due to pathological cases involving
10991 if (equality_comparison_p
10992 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10993 XEXP (op0
, 1), op1
)))
10995 op0
= XEXP (op0
, 0);
11000 if (equality_comparison_p
11001 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11002 XEXP (op0
, 0), op1
)))
11004 op0
= XEXP (op0
, 1);
11009 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11010 of bits in X minus 1, is one iff X > 0. */
11011 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11012 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11013 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
11015 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11017 op0
= XEXP (op0
, 1);
11018 code
= (code
== GE
? LE
: GT
);
11024 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11025 if C is zero or B is a constant. */
11026 if (equality_comparison_p
11027 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11028 XEXP (op0
, 1), op1
)))
11030 op0
= XEXP (op0
, 0);
11037 case UNEQ
: case LTGT
:
11038 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11039 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11040 case UNORDERED
: case ORDERED
:
11041 /* We can't do anything if OP0 is a condition code value, rather
11042 than an actual data value. */
11044 || CC0_P (XEXP (op0
, 0))
11045 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11048 /* Get the two operands being compared. */
11049 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11050 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11052 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11054 /* Check for the cases where we simply want the result of the
11055 earlier test or the opposite of that result. */
11056 if (code
== NE
|| code
== EQ
11057 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
11058 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11059 && (STORE_FLAG_VALUE
11060 & (((HOST_WIDE_INT
) 1
11061 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
11062 && (code
== LT
|| code
== GE
)))
11064 enum rtx_code new_code
;
11065 if (code
== LT
|| code
== NE
)
11066 new_code
= GET_CODE (op0
);
11068 new_code
= reversed_comparison_code (op0
, NULL
);
11070 if (new_code
!= UNKNOWN
)
11081 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11083 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11084 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11085 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11087 op0
= XEXP (op0
, 1);
11088 code
= (code
== GE
? GT
: LE
);
11094 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11095 will be converted to a ZERO_EXTRACT later. */
11096 if (const_op
== 0 && equality_comparison_p
11097 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11098 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11100 op0
= simplify_and_const_int
11101 (NULL_RTX
, mode
, gen_rtx_LSHIFTRT (mode
,
11103 XEXP (XEXP (op0
, 0), 1)),
11104 (HOST_WIDE_INT
) 1);
11108 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11109 zero and X is a comparison and C1 and C2 describe only bits set
11110 in STORE_FLAG_VALUE, we can compare with X. */
11111 if (const_op
== 0 && equality_comparison_p
11112 && mode_width
<= HOST_BITS_PER_WIDE_INT
11113 && CONST_INT_P (XEXP (op0
, 1))
11114 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11115 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11116 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11117 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11119 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11120 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11121 if ((~STORE_FLAG_VALUE
& mask
) == 0
11122 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11123 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11124 && COMPARISON_P (tem
))))
11126 op0
= XEXP (XEXP (op0
, 0), 0);
11131 /* If we are doing an equality comparison of an AND of a bit equal
11132 to the sign bit, replace this with a LT or GE comparison of
11133 the underlying value. */
11134 if (equality_comparison_p
11136 && CONST_INT_P (XEXP (op0
, 1))
11137 && mode_width
<= HOST_BITS_PER_WIDE_INT
11138 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11139 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11141 op0
= XEXP (op0
, 0);
11142 code
= (code
== EQ
? GE
: LT
);
11146 /* If this AND operation is really a ZERO_EXTEND from a narrower
11147 mode, the constant fits within that mode, and this is either an
11148 equality or unsigned comparison, try to do this comparison in
11153 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11154 -> (ne:DI (reg:SI 4) (const_int 0))
11156 unless TRULY_NOOP_TRUNCATION allows it or the register is
11157 known to hold a value of the required mode the
11158 transformation is invalid. */
11159 if ((equality_comparison_p
|| unsigned_comparison_p
)
11160 && CONST_INT_P (XEXP (op0
, 1))
11161 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
11162 & GET_MODE_MASK (mode
))
11164 && const_op
>> i
== 0
11165 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11166 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
11167 GET_MODE_BITSIZE (GET_MODE (op0
)))
11168 || (REG_P (XEXP (op0
, 0))
11169 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11171 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11175 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11176 fits in both M1 and M2 and the SUBREG is either paradoxical
11177 or represents the low part, permute the SUBREG and the AND
11179 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11181 unsigned HOST_WIDE_INT c1
;
11182 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11183 /* Require an integral mode, to avoid creating something like
11185 if (SCALAR_INT_MODE_P (tmode
)
11186 /* It is unsafe to commute the AND into the SUBREG if the
11187 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11188 not defined. As originally written the upper bits
11189 have a defined value due to the AND operation.
11190 However, if we commute the AND inside the SUBREG then
11191 they no longer have defined values and the meaning of
11192 the code has been changed. */
11194 #ifdef WORD_REGISTER_OPERATIONS
11195 || (mode_width
> GET_MODE_BITSIZE (tmode
)
11196 && mode_width
<= BITS_PER_WORD
)
11198 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
11199 && subreg_lowpart_p (XEXP (op0
, 0))))
11200 && CONST_INT_P (XEXP (op0
, 1))
11201 && mode_width
<= HOST_BITS_PER_WIDE_INT
11202 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
11203 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11204 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11206 && c1
!= GET_MODE_MASK (tmode
))
11208 op0
= simplify_gen_binary (AND
, tmode
,
11209 SUBREG_REG (XEXP (op0
, 0)),
11210 gen_int_mode (c1
, tmode
));
11211 op0
= gen_lowpart (mode
, op0
);
11216 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11217 if (const_op
== 0 && equality_comparison_p
11218 && XEXP (op0
, 1) == const1_rtx
11219 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11221 op0
= simplify_and_const_int
11222 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
11223 code
= (code
== NE
? EQ
: NE
);
11227 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11228 (eq (and (lshiftrt X) 1) 0).
11229 Also handle the case where (not X) is expressed using xor. */
11230 if (const_op
== 0 && equality_comparison_p
11231 && XEXP (op0
, 1) == const1_rtx
11232 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11234 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11235 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11237 if (GET_CODE (shift_op
) == NOT
11238 || (GET_CODE (shift_op
) == XOR
11239 && CONST_INT_P (XEXP (shift_op
, 1))
11240 && CONST_INT_P (shift_count
)
11241 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11242 && (INTVAL (XEXP (shift_op
, 1))
11243 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11245 op0
= simplify_and_const_int
11247 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11248 (HOST_WIDE_INT
) 1);
11249 code
= (code
== NE
? EQ
: NE
);
11256 /* If we have (compare (ashift FOO N) (const_int C)) and
11257 the high order N bits of FOO (N+1 if an inequality comparison)
11258 are known to be zero, we can do this by comparing FOO with C
11259 shifted right N bits so long as the low-order N bits of C are
11261 if (CONST_INT_P (XEXP (op0
, 1))
11262 && INTVAL (XEXP (op0
, 1)) >= 0
11263 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11264 < HOST_BITS_PER_WIDE_INT
)
11266 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11267 && mode_width
<= HOST_BITS_PER_WIDE_INT
11268 && (nonzero_bits (XEXP (op0
, 0), mode
)
11269 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11270 + ! equality_comparison_p
))) == 0)
11272 /* We must perform a logical shift, not an arithmetic one,
11273 as we want the top N bits of C to be zero. */
11274 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11276 temp
>>= INTVAL (XEXP (op0
, 1));
11277 op1
= gen_int_mode (temp
, mode
);
11278 op0
= XEXP (op0
, 0);
11282 /* If we are doing a sign bit comparison, it means we are testing
11283 a particular bit. Convert it to the appropriate AND. */
11284 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11285 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11287 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11290 - INTVAL (XEXP (op0
, 1)))));
11291 code
= (code
== LT
? NE
: EQ
);
11295 /* If this an equality comparison with zero and we are shifting
11296 the low bit to the sign bit, we can convert this to an AND of the
11298 if (const_op
== 0 && equality_comparison_p
11299 && CONST_INT_P (XEXP (op0
, 1))
11300 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11303 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11304 (HOST_WIDE_INT
) 1);
11310 /* If this is an equality comparison with zero, we can do this
11311 as a logical shift, which might be much simpler. */
11312 if (equality_comparison_p
&& const_op
== 0
11313 && CONST_INT_P (XEXP (op0
, 1)))
11315 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11317 INTVAL (XEXP (op0
, 1)));
11321 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11322 do the comparison in a narrower mode. */
11323 if (! unsigned_comparison_p
11324 && CONST_INT_P (XEXP (op0
, 1))
11325 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11326 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11327 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11328 MODE_INT
, 1)) != BLKmode
11329 && (((unsigned HOST_WIDE_INT
) const_op
11330 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11331 <= GET_MODE_MASK (tmode
)))
11333 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11337 /* Likewise if OP0 is a PLUS of a sign extension with a
11338 constant, which is usually represented with the PLUS
11339 between the shifts. */
11340 if (! unsigned_comparison_p
11341 && CONST_INT_P (XEXP (op0
, 1))
11342 && GET_CODE (XEXP (op0
, 0)) == PLUS
11343 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11344 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11345 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11346 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11347 MODE_INT
, 1)) != BLKmode
11348 && (((unsigned HOST_WIDE_INT
) const_op
11349 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11350 <= GET_MODE_MASK (tmode
)))
11352 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11353 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11354 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11355 add_const
, XEXP (op0
, 1));
11357 op0
= simplify_gen_binary (PLUS
, tmode
,
11358 gen_lowpart (tmode
, inner
),
11363 /* ... fall through ... */
11365 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11366 the low order N bits of FOO are known to be zero, we can do this
11367 by comparing FOO with C shifted left N bits so long as no
11368 overflow occurs. */
11369 if (CONST_INT_P (XEXP (op0
, 1))
11370 && INTVAL (XEXP (op0
, 1)) >= 0
11371 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11372 && mode_width
<= HOST_BITS_PER_WIDE_INT
11373 && (nonzero_bits (XEXP (op0
, 0), mode
)
11374 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11375 && (((unsigned HOST_WIDE_INT
) const_op
11376 + (GET_CODE (op0
) != LSHIFTRT
11377 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11380 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11382 /* If the shift was logical, then we must make the condition
11384 if (GET_CODE (op0
) == LSHIFTRT
)
11385 code
= unsigned_condition (code
);
11387 const_op
<<= INTVAL (XEXP (op0
, 1));
11388 op1
= GEN_INT (const_op
);
11389 op0
= XEXP (op0
, 0);
11393 /* If we are using this shift to extract just the sign bit, we
11394 can replace this with an LT or GE comparison. */
11396 && (equality_comparison_p
|| sign_bit_comparison_p
)
11397 && CONST_INT_P (XEXP (op0
, 1))
11398 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11401 op0
= XEXP (op0
, 0);
11402 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11414 /* Now make any compound operations involved in this comparison. Then,
11415 check for an outmost SUBREG on OP0 that is not doing anything or is
11416 paradoxical. The latter transformation must only be performed when
11417 it is known that the "extra" bits will be the same in op0 and op1 or
11418 that they don't matter. There are three cases to consider:
11420 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11421 care bits and we can assume they have any convenient value. So
11422 making the transformation is safe.
11424 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11425 In this case the upper bits of op0 are undefined. We should not make
11426 the simplification in that case as we do not know the contents of
11429 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11430 UNKNOWN. In that case we know those bits are zeros or ones. We must
11431 also be sure that they are the same as the upper bits of op1.
11433 We can never remove a SUBREG for a non-equality comparison because
11434 the sign bit is in a different place in the underlying object. */
11436 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11437 op1
= make_compound_operation (op1
, SET
);
11439 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11440 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11441 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11442 && (code
== NE
|| code
== EQ
))
11444 if (GET_MODE_SIZE (GET_MODE (op0
))
11445 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11447 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11449 if (REG_P (SUBREG_REG (op0
)))
11451 op0
= SUBREG_REG (op0
);
11452 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11455 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11456 <= HOST_BITS_PER_WIDE_INT
)
11457 && (nonzero_bits (SUBREG_REG (op0
),
11458 GET_MODE (SUBREG_REG (op0
)))
11459 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11461 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11463 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11464 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11465 op0
= SUBREG_REG (op0
), op1
= tem
;
11469 /* We now do the opposite procedure: Some machines don't have compare
11470 insns in all modes. If OP0's mode is an integer mode smaller than a
11471 word and we can't do a compare in that mode, see if there is a larger
11472 mode for which we can do the compare. There are a number of cases in
11473 which we can use the wider mode. */
11475 mode
= GET_MODE (op0
);
11476 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11477 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11478 && ! have_insn_for (COMPARE
, mode
))
11479 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11481 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11482 tmode
= GET_MODE_WIDER_MODE (tmode
))
11483 if (have_insn_for (COMPARE
, tmode
))
11487 /* If this is a test for negative, we can make an explicit
11488 test of the sign bit. Test this first so we can use
11489 a paradoxical subreg to extend OP0. */
11491 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11492 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11494 op0
= simplify_gen_binary (AND
, tmode
,
11495 gen_lowpart (tmode
, op0
),
11496 GEN_INT ((HOST_WIDE_INT
) 1
11497 << (GET_MODE_BITSIZE (mode
)
11499 code
= (code
== LT
) ? NE
: EQ
;
11503 /* If the only nonzero bits in OP0 and OP1 are those in the
11504 narrower mode and this is an equality or unsigned comparison,
11505 we can use the wider mode. Similarly for sign-extended
11506 values, in which case it is true for all comparisons. */
11507 zero_extended
= ((code
== EQ
|| code
== NE
11508 || code
== GEU
|| code
== GTU
11509 || code
== LEU
|| code
== LTU
)
11510 && (nonzero_bits (op0
, tmode
)
11511 & ~GET_MODE_MASK (mode
)) == 0
11512 && ((CONST_INT_P (op1
)
11513 || (nonzero_bits (op1
, tmode
)
11514 & ~GET_MODE_MASK (mode
)) == 0)));
11517 || ((num_sign_bit_copies (op0
, tmode
)
11518 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11519 - GET_MODE_BITSIZE (mode
)))
11520 && (num_sign_bit_copies (op1
, tmode
)
11521 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11522 - GET_MODE_BITSIZE (mode
)))))
11524 /* If OP0 is an AND and we don't have an AND in MODE either,
11525 make a new AND in the proper mode. */
11526 if (GET_CODE (op0
) == AND
11527 && !have_insn_for (AND
, mode
))
11528 op0
= simplify_gen_binary (AND
, tmode
,
11529 gen_lowpart (tmode
,
11531 gen_lowpart (tmode
,
11537 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
11538 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
11542 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
11543 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
11550 #ifdef CANONICALIZE_COMPARISON
11551 /* If this machine only supports a subset of valid comparisons, see if we
11552 can convert an unsupported one into a supported one. */
11553 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11562 /* Utility function for record_value_for_reg. Count number of
11567 enum rtx_code code
= GET_CODE (x
);
11571 if (GET_RTX_CLASS (code
) == '2'
11572 || GET_RTX_CLASS (code
) == 'c')
11574 rtx x0
= XEXP (x
, 0);
11575 rtx x1
= XEXP (x
, 1);
11578 return 1 + 2 * count_rtxs (x0
);
11580 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11581 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11582 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11583 return 2 + 2 * count_rtxs (x0
)
11584 + count_rtxs (x
== XEXP (x1
, 0)
11585 ? XEXP (x1
, 1) : XEXP (x1
, 0));
11587 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11588 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11589 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11590 return 2 + 2 * count_rtxs (x1
)
11591 + count_rtxs (x
== XEXP (x0
, 0)
11592 ? XEXP (x0
, 1) : XEXP (x0
, 0));
11595 fmt
= GET_RTX_FORMAT (code
);
11596 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11598 ret
+= count_rtxs (XEXP (x
, i
));
11599 else if (fmt
[i
] == 'E')
11600 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11601 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
11606 /* Utility function for following routine. Called when X is part of a value
11607 being stored into last_set_value. Sets last_set_table_tick
11608 for each register mentioned. Similar to mention_regs in cse.c */
11611 update_table_tick (rtx x
)
11613 enum rtx_code code
= GET_CODE (x
);
11614 const char *fmt
= GET_RTX_FORMAT (code
);
11619 unsigned int regno
= REGNO (x
);
11620 unsigned int endregno
= END_REGNO (x
);
11623 for (r
= regno
; r
< endregno
; r
++)
11625 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, r
);
11626 rsp
->last_set_table_tick
= label_tick
;
11632 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11635 /* Check for identical subexpressions. If x contains
11636 identical subexpression we only have to traverse one of
11638 if (i
== 0 && ARITHMETIC_P (x
))
11640 /* Note that at this point x1 has already been
11642 rtx x0
= XEXP (x
, 0);
11643 rtx x1
= XEXP (x
, 1);
11645 /* If x0 and x1 are identical then there is no need to
11650 /* If x0 is identical to a subexpression of x1 then while
11651 processing x1, x0 has already been processed. Thus we
11652 are done with x. */
11653 if (ARITHMETIC_P (x1
)
11654 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11657 /* If x1 is identical to a subexpression of x0 then we
11658 still have to process the rest of x0. */
11659 if (ARITHMETIC_P (x0
)
11660 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11662 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11667 update_table_tick (XEXP (x
, i
));
11669 else if (fmt
[i
] == 'E')
11670 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11671 update_table_tick (XVECEXP (x
, i
, j
));
11674 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11675 are saying that the register is clobbered and we no longer know its
11676 value. If INSN is zero, don't update reg_stat[].last_set; this is
11677 only permitted with VALUE also zero and is used to invalidate the
11681 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11683 unsigned int regno
= REGNO (reg
);
11684 unsigned int endregno
= END_REGNO (reg
);
11686 reg_stat_type
*rsp
;
11688 /* If VALUE contains REG and we have a previous value for REG, substitute
11689 the previous value. */
11690 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11694 /* Set things up so get_last_value is allowed to see anything set up to
11696 subst_low_luid
= DF_INSN_LUID (insn
);
11697 tem
= get_last_value (reg
);
11699 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11700 it isn't going to be useful and will take a lot of time to process,
11701 so just use the CLOBBER. */
11705 if (ARITHMETIC_P (tem
)
11706 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11707 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11708 tem
= XEXP (tem
, 0);
11709 else if (count_occurrences (value
, reg
, 1) >= 2)
11711 /* If there are two or more occurrences of REG in VALUE,
11712 prevent the value from growing too much. */
11713 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
11714 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
11717 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11721 /* For each register modified, show we don't know its value, that
11722 we don't know about its bitwise content, that its value has been
11723 updated, and that we don't know the location of the death of the
11725 for (i
= regno
; i
< endregno
; i
++)
11727 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11730 rsp
->last_set
= insn
;
11732 rsp
->last_set_value
= 0;
11733 rsp
->last_set_mode
= VOIDmode
;
11734 rsp
->last_set_nonzero_bits
= 0;
11735 rsp
->last_set_sign_bit_copies
= 0;
11736 rsp
->last_death
= 0;
11737 rsp
->truncated_to_mode
= VOIDmode
;
11740 /* Mark registers that are being referenced in this value. */
11742 update_table_tick (value
);
11744 /* Now update the status of each register being set.
11745 If someone is using this register in this block, set this register
11746 to invalid since we will get confused between the two lives in this
11747 basic block. This makes using this register always invalid. In cse, we
11748 scan the table to invalidate all entries using this register, but this
11749 is too much work for us. */
11751 for (i
= regno
; i
< endregno
; i
++)
11753 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11754 rsp
->last_set_label
= label_tick
;
11756 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
11757 rsp
->last_set_invalid
= 1;
11759 rsp
->last_set_invalid
= 0;
11762 /* The value being assigned might refer to X (like in "x++;"). In that
11763 case, we must replace it with (clobber (const_int 0)) to prevent
11765 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
11766 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
11768 value
= copy_rtx (value
);
11769 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
11773 /* For the main register being modified, update the value, the mode, the
11774 nonzero bits, and the number of sign bit copies. */
11776 rsp
->last_set_value
= value
;
11780 enum machine_mode mode
= GET_MODE (reg
);
11781 subst_low_luid
= DF_INSN_LUID (insn
);
11782 rsp
->last_set_mode
= mode
;
11783 if (GET_MODE_CLASS (mode
) == MODE_INT
11784 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11785 mode
= nonzero_bits_mode
;
11786 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
11787 rsp
->last_set_sign_bit_copies
11788 = num_sign_bit_copies (value
, GET_MODE (reg
));
11792 /* Called via note_stores from record_dead_and_set_regs to handle one
11793 SET or CLOBBER in an insn. DATA is the instruction in which the
11794 set is occurring. */
11797 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
11799 rtx record_dead_insn
= (rtx
) data
;
11801 if (GET_CODE (dest
) == SUBREG
)
11802 dest
= SUBREG_REG (dest
);
11804 if (!record_dead_insn
)
11807 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
11813 /* If we are setting the whole register, we know its value. Otherwise
11814 show that we don't know the value. We can handle SUBREG in
11816 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11817 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11818 else if (GET_CODE (setter
) == SET
11819 && GET_CODE (SET_DEST (setter
)) == SUBREG
11820 && SUBREG_REG (SET_DEST (setter
)) == dest
11821 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11822 && subreg_lowpart_p (SET_DEST (setter
)))
11823 record_value_for_reg (dest
, record_dead_insn
,
11824 gen_lowpart (GET_MODE (dest
),
11825 SET_SRC (setter
)));
11827 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11829 else if (MEM_P (dest
)
11830 /* Ignore pushes, they clobber nothing. */
11831 && ! push_operand (dest
, GET_MODE (dest
)))
11832 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
11835 /* Update the records of when each REG was most recently set or killed
11836 for the things done by INSN. This is the last thing done in processing
11837 INSN in the combiner loop.
11839 We update reg_stat[], in particular fields last_set, last_set_value,
11840 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11841 last_death, and also the similar information mem_last_set (which insn
11842 most recently modified memory) and last_call_luid (which insn was the
11843 most recent subroutine call). */
11846 record_dead_and_set_regs (rtx insn
)
11851 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11853 if (REG_NOTE_KIND (link
) == REG_DEAD
11854 && REG_P (XEXP (link
, 0)))
11856 unsigned int regno
= REGNO (XEXP (link
, 0));
11857 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
11859 for (i
= regno
; i
< endregno
; i
++)
11861 reg_stat_type
*rsp
;
11863 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11864 rsp
->last_death
= insn
;
11867 else if (REG_NOTE_KIND (link
) == REG_INC
)
11868 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11873 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11874 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11876 reg_stat_type
*rsp
;
11878 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
11879 rsp
->last_set_invalid
= 1;
11880 rsp
->last_set
= insn
;
11881 rsp
->last_set_value
= 0;
11882 rsp
->last_set_mode
= VOIDmode
;
11883 rsp
->last_set_nonzero_bits
= 0;
11884 rsp
->last_set_sign_bit_copies
= 0;
11885 rsp
->last_death
= 0;
11886 rsp
->truncated_to_mode
= VOIDmode
;
11889 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
11891 /* We can't combine into a call pattern. Remember, though, that
11892 the return value register is set at this LUID. We could
11893 still replace a register with the return value from the
11894 wrong subroutine call! */
11895 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
11898 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11901 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11902 register present in the SUBREG, so for each such SUBREG go back and
11903 adjust nonzero and sign bit information of the registers that are
11904 known to have some zero/sign bits set.
11906 This is needed because when combine blows the SUBREGs away, the
11907 information on zero/sign bits is lost and further combines can be
11908 missed because of that. */
11911 record_promoted_value (rtx insn
, rtx subreg
)
11914 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11915 enum machine_mode mode
= GET_MODE (subreg
);
11917 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11920 for (links
= LOG_LINKS (insn
); links
;)
11922 reg_stat_type
*rsp
;
11924 insn
= XEXP (links
, 0);
11925 set
= single_set (insn
);
11927 if (! set
|| !REG_P (SET_DEST (set
))
11928 || REGNO (SET_DEST (set
)) != regno
11929 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11931 links
= XEXP (links
, 1);
11935 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
11936 if (rsp
->last_set
== insn
)
11938 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11939 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11942 if (REG_P (SET_SRC (set
)))
11944 regno
= REGNO (SET_SRC (set
));
11945 links
= LOG_LINKS (insn
);
11952 /* Check if X, a register, is known to contain a value already
11953 truncated to MODE. In this case we can use a subreg to refer to
11954 the truncated value even though in the generic case we would need
11955 an explicit truncation. */
11958 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
11960 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
11961 enum machine_mode truncated
= rsp
->truncated_to_mode
;
11964 || rsp
->truncation_label
< label_tick_ebb_start
)
11966 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
11968 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
11969 GET_MODE_BITSIZE (truncated
)))
11974 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11975 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11976 might be able to turn a truncate into a subreg using this information.
11977 Return -1 if traversing *P is complete or 0 otherwise. */
11980 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
11983 enum machine_mode truncated_mode
;
11984 reg_stat_type
*rsp
;
11986 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
11988 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
11989 truncated_mode
= GET_MODE (x
);
11991 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
11994 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode
),
11995 GET_MODE_BITSIZE (original_mode
)))
11998 x
= SUBREG_REG (x
);
12000 /* ??? For hard-regs we now record everything. We might be able to
12001 optimize this using last_set_mode. */
12002 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12003 truncated_mode
= GET_MODE (x
);
12007 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12008 if (rsp
->truncated_to_mode
== 0
12009 || rsp
->truncation_label
< label_tick_ebb_start
12010 || (GET_MODE_SIZE (truncated_mode
)
12011 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12013 rsp
->truncated_to_mode
= truncated_mode
;
12014 rsp
->truncation_label
= label_tick
;
12020 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12021 the modes they are used in. This can help truning TRUNCATEs into
12025 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12027 for_each_rtx (x
, record_truncated_value
, NULL
);
12030 /* Scan X for promoted SUBREGs. For each one found,
12031 note what it implies to the registers used in it. */
12034 check_promoted_subreg (rtx insn
, rtx x
)
12036 if (GET_CODE (x
) == SUBREG
12037 && SUBREG_PROMOTED_VAR_P (x
)
12038 && REG_P (SUBREG_REG (x
)))
12039 record_promoted_value (insn
, x
);
12042 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12045 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12049 check_promoted_subreg (insn
, XEXP (x
, i
));
12053 if (XVEC (x
, i
) != 0)
12054 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12055 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12061 /* Verify that all the registers and memory references mentioned in *LOC are
12062 still valid. *LOC was part of a value set in INSN when label_tick was
12063 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12064 the invalid references with (clobber (const_int 0)) and return 1. This
12065 replacement is useful because we often can get useful information about
12066 the form of a value (e.g., if it was produced by a shift that always
12067 produces -1 or 0) even though we don't know exactly what registers it
12068 was produced from. */
12071 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12074 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12075 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12080 unsigned int regno
= REGNO (x
);
12081 unsigned int endregno
= END_REGNO (x
);
12084 for (j
= regno
; j
< endregno
; j
++)
12086 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, j
);
12087 if (rsp
->last_set_invalid
12088 /* If this is a pseudo-register that was only set once and not
12089 live at the beginning of the function, it is always valid. */
12090 || (! (regno
>= FIRST_PSEUDO_REGISTER
12091 && REG_N_SETS (regno
) == 1
12092 && (!REGNO_REG_SET_P
12093 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12094 && rsp
->last_set_label
> tick
))
12097 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12104 /* If this is a memory reference, make sure that there were no stores after
12105 it that might have clobbered the value. We don't have alias info, so we
12106 assume any store invalidates it. Moreover, we only have local UIDs, so
12107 we also assume that there were stores in the intervening basic blocks. */
12108 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12109 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12112 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12116 for (i
= 0; i
< len
; i
++)
12120 /* Check for identical subexpressions. If x contains
12121 identical subexpression we only have to traverse one of
12123 if (i
== 1 && ARITHMETIC_P (x
))
12125 /* Note that at this point x0 has already been checked
12126 and found valid. */
12127 rtx x0
= XEXP (x
, 0);
12128 rtx x1
= XEXP (x
, 1);
12130 /* If x0 and x1 are identical then x is also valid. */
12134 /* If x1 is identical to a subexpression of x0 then
12135 while checking x0, x1 has already been checked. Thus
12136 it is valid and so as x. */
12137 if (ARITHMETIC_P (x0
)
12138 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12141 /* If x0 is identical to a subexpression of x1 then x is
12142 valid iff the rest of x1 is valid. */
12143 if (ARITHMETIC_P (x1
)
12144 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12146 get_last_value_validate (&XEXP (x1
,
12147 x0
== XEXP (x1
, 0) ? 1 : 0),
12148 insn
, tick
, replace
);
12151 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12155 else if (fmt
[i
] == 'E')
12156 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12157 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12158 insn
, tick
, replace
) == 0)
12162 /* If we haven't found a reason for it to be invalid, it is valid. */
12166 /* Get the last value assigned to X, if known. Some registers
12167 in the value may be replaced with (clobber (const_int 0)) if their value
12168 is known longer known reliably. */
12171 get_last_value (const_rtx x
)
12173 unsigned int regno
;
12175 reg_stat_type
*rsp
;
12177 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12178 then convert it to the desired mode. If this is a paradoxical SUBREG,
12179 we cannot predict what values the "extra" bits might have. */
12180 if (GET_CODE (x
) == SUBREG
12181 && subreg_lowpart_p (x
)
12182 && (GET_MODE_SIZE (GET_MODE (x
))
12183 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
12184 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12185 return gen_lowpart (GET_MODE (x
), value
);
12191 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12192 value
= rsp
->last_set_value
;
12194 /* If we don't have a value, or if it isn't for this basic block and
12195 it's either a hard register, set more than once, or it's a live
12196 at the beginning of the function, return 0.
12198 Because if it's not live at the beginning of the function then the reg
12199 is always set before being used (is never used without being set).
12200 And, if it's set only once, and it's always set before use, then all
12201 uses must have the same last value, even if it's not from this basic
12205 || (rsp
->last_set_label
< label_tick_ebb_start
12206 && (regno
< FIRST_PSEUDO_REGISTER
12207 || REG_N_SETS (regno
) != 1
12209 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12212 /* If the value was set in a later insn than the ones we are processing,
12213 we can't use it even if the register was only set once. */
12214 if (rsp
->last_set_label
== label_tick
12215 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12218 /* If the value has all its registers valid, return it. */
12219 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12222 /* Otherwise, make a copy and replace any invalid register with
12223 (clobber (const_int 0)). If that fails for some reason, return 0. */
12225 value
= copy_rtx (value
);
12226 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12232 /* Return nonzero if expression X refers to a REG or to memory
12233 that is set in an instruction more recent than FROM_LUID. */
12236 use_crosses_set_p (const_rtx x
, int from_luid
)
12240 enum rtx_code code
= GET_CODE (x
);
12244 unsigned int regno
= REGNO (x
);
12245 unsigned endreg
= END_REGNO (x
);
12247 #ifdef PUSH_ROUNDING
12248 /* Don't allow uses of the stack pointer to be moved,
12249 because we don't know whether the move crosses a push insn. */
12250 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12253 for (; regno
< endreg
; regno
++)
12255 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12257 && rsp
->last_set_label
== label_tick
12258 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12264 if (code
== MEM
&& mem_last_set
> from_luid
)
12267 fmt
= GET_RTX_FORMAT (code
);
12269 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12274 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12275 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12278 else if (fmt
[i
] == 'e'
12279 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12285 /* Define three variables used for communication between the following
12288 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12289 static int reg_dead_flag
;
12291 /* Function called via note_stores from reg_dead_at_p.
12293 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12294 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12297 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12299 unsigned int regno
, endregno
;
12304 regno
= REGNO (dest
);
12305 endregno
= END_REGNO (dest
);
12306 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12307 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12310 /* Return nonzero if REG is known to be dead at INSN.
12312 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12313 referencing REG, it is dead. If we hit a SET referencing REG, it is
12314 live. Otherwise, see if it is live or dead at the start of the basic
12315 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12316 must be assumed to be always live. */
12319 reg_dead_at_p (rtx reg
, rtx insn
)
12324 /* Set variables for reg_dead_at_p_1. */
12325 reg_dead_regno
= REGNO (reg
);
12326 reg_dead_endregno
= END_REGNO (reg
);
12330 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12331 we allow the machine description to decide whether use-and-clobber
12332 patterns are OK. */
12333 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12335 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12336 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12340 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12341 beginning of basic block. */
12342 block
= BLOCK_FOR_INSN (insn
);
12347 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12349 return reg_dead_flag
== 1 ? 1 : 0;
12351 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12355 if (insn
== BB_HEAD (block
))
12358 insn
= PREV_INSN (insn
);
12361 /* Look at live-in sets for the basic block that we were in. */
12362 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12363 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12369 /* Note hard registers in X that are used. */
12372 mark_used_regs_combine (rtx x
)
12374 RTX_CODE code
= GET_CODE (x
);
12375 unsigned int regno
;
12388 case ADDR_DIFF_VEC
:
12391 /* CC0 must die in the insn after it is set, so we don't need to take
12392 special note of it here. */
12398 /* If we are clobbering a MEM, mark any hard registers inside the
12399 address as used. */
12400 if (MEM_P (XEXP (x
, 0)))
12401 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12406 /* A hard reg in a wide mode may really be multiple registers.
12407 If so, mark all of them just like the first. */
12408 if (regno
< FIRST_PSEUDO_REGISTER
)
12410 /* None of this applies to the stack, frame or arg pointers. */
12411 if (regno
== STACK_POINTER_REGNUM
12412 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12413 || regno
== HARD_FRAME_POINTER_REGNUM
12415 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12416 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12418 || regno
== FRAME_POINTER_REGNUM
)
12421 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12427 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12429 rtx testreg
= SET_DEST (x
);
12431 while (GET_CODE (testreg
) == SUBREG
12432 || GET_CODE (testreg
) == ZERO_EXTRACT
12433 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12434 testreg
= XEXP (testreg
, 0);
12436 if (MEM_P (testreg
))
12437 mark_used_regs_combine (XEXP (testreg
, 0));
12439 mark_used_regs_combine (SET_SRC (x
));
12447 /* Recursively scan the operands of this expression. */
12450 const char *fmt
= GET_RTX_FORMAT (code
);
12452 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12455 mark_used_regs_combine (XEXP (x
, i
));
12456 else if (fmt
[i
] == 'E')
12460 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12461 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12467 /* Remove register number REGNO from the dead registers list of INSN.
12469 Return the note used to record the death, if there was one. */
12472 remove_death (unsigned int regno
, rtx insn
)
12474 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12477 remove_note (insn
, note
);
12482 /* For each register (hardware or pseudo) used within expression X, if its
12483 death is in an instruction with luid between FROM_LUID (inclusive) and
12484 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12485 list headed by PNOTES.
12487 That said, don't move registers killed by maybe_kill_insn.
12489 This is done when X is being merged by combination into TO_INSN. These
12490 notes will then be distributed as needed. */
12493 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12498 enum rtx_code code
= GET_CODE (x
);
12502 unsigned int regno
= REGNO (x
);
12503 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
)->last_death
;
12505 /* Don't move the register if it gets killed in between from and to. */
12506 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12507 && ! reg_referenced_p (x
, maybe_kill_insn
))
12511 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12512 && DF_INSN_LUID (where_dead
) >= from_luid
12513 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12515 rtx note
= remove_death (regno
, where_dead
);
12517 /* It is possible for the call above to return 0. This can occur
12518 when last_death points to I2 or I1 that we combined with.
12519 In that case make a new note.
12521 We must also check for the case where X is a hard register
12522 and NOTE is a death note for a range of hard registers
12523 including X. In that case, we must put REG_DEAD notes for
12524 the remaining registers in place of NOTE. */
12526 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12527 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12528 > GET_MODE_SIZE (GET_MODE (x
))))
12530 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12531 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12532 unsigned int ourend
= END_HARD_REGNO (x
);
12535 for (i
= deadregno
; i
< deadend
; i
++)
12536 if (i
< regno
|| i
>= ourend
)
12537 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
12540 /* If we didn't find any note, or if we found a REG_DEAD note that
12541 covers only part of the given reg, and we have a multi-reg hard
12542 register, then to be safe we must check for REG_DEAD notes
12543 for each register other than the first. They could have
12544 their own REG_DEAD notes lying around. */
12545 else if ((note
== 0
12547 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12548 < GET_MODE_SIZE (GET_MODE (x
)))))
12549 && regno
< FIRST_PSEUDO_REGISTER
12550 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12552 unsigned int ourend
= END_HARD_REGNO (x
);
12553 unsigned int i
, offset
;
12557 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12561 for (i
= regno
+ offset
; i
< ourend
; i
++)
12562 move_deaths (regno_reg_rtx
[i
],
12563 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
12566 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12568 XEXP (note
, 1) = *pnotes
;
12572 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
12578 else if (GET_CODE (x
) == SET
)
12580 rtx dest
= SET_DEST (x
);
12582 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12584 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12585 that accesses one word of a multi-word item, some
12586 piece of everything register in the expression is used by
12587 this insn, so remove any old death. */
12588 /* ??? So why do we test for equality of the sizes? */
12590 if (GET_CODE (dest
) == ZERO_EXTRACT
12591 || GET_CODE (dest
) == STRICT_LOW_PART
12592 || (GET_CODE (dest
) == SUBREG
12593 && (((GET_MODE_SIZE (GET_MODE (dest
))
12594 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12595 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12596 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12598 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12602 /* If this is some other SUBREG, we know it replaces the entire
12603 value, so use that as the destination. */
12604 if (GET_CODE (dest
) == SUBREG
)
12605 dest
= SUBREG_REG (dest
);
12607 /* If this is a MEM, adjust deaths of anything used in the address.
12608 For a REG (the only other possibility), the entire value is
12609 being replaced so the old value is not used in this insn. */
12612 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
12617 else if (GET_CODE (x
) == CLOBBER
)
12620 len
= GET_RTX_LENGTH (code
);
12621 fmt
= GET_RTX_FORMAT (code
);
12623 for (i
= 0; i
< len
; i
++)
12628 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12629 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
12632 else if (fmt
[i
] == 'e')
12633 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12637 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12638 pattern of an insn. X must be a REG. */
12641 reg_bitfield_target_p (rtx x
, rtx body
)
12645 if (GET_CODE (body
) == SET
)
12647 rtx dest
= SET_DEST (body
);
12649 unsigned int regno
, tregno
, endregno
, endtregno
;
12651 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12652 target
= XEXP (dest
, 0);
12653 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12654 target
= SUBREG_REG (XEXP (dest
, 0));
12658 if (GET_CODE (target
) == SUBREG
)
12659 target
= SUBREG_REG (target
);
12661 if (!REG_P (target
))
12664 tregno
= REGNO (target
), regno
= REGNO (x
);
12665 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12666 return target
== x
;
12668 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
12669 endregno
= end_hard_regno (GET_MODE (x
), regno
);
12671 return endregno
> tregno
&& regno
< endtregno
;
12674 else if (GET_CODE (body
) == PARALLEL
)
12675 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12676 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12682 /* Return the next insn after INSN that is neither a NOTE nor a
12683 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12686 next_nonnote_nondebug_insn (rtx insn
)
12690 insn
= NEXT_INSN (insn
);
12695 if (DEBUG_INSN_P (insn
))
12705 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12706 as appropriate. I3 and I2 are the insns resulting from the combination
12707 insns including FROM (I2 may be zero).
12709 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12710 not need REG_DEAD notes because they are being substituted for. This
12711 saves searching in the most common cases.
12713 Each note in the list is either ignored or placed on some insns, depending
12714 on the type of note. */
12717 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
12720 rtx note
, next_note
;
12723 for (note
= notes
; note
; note
= next_note
)
12725 rtx place
= 0, place2
= 0;
12727 next_note
= XEXP (note
, 1);
12728 switch (REG_NOTE_KIND (note
))
12732 /* Doesn't matter much where we put this, as long as it's somewhere.
12733 It is preferable to keep these notes on branches, which is most
12734 likely to be i3. */
12738 case REG_VALUE_PROFILE
:
12739 /* Just get rid of this note, as it is unused later anyway. */
12742 case REG_NON_LOCAL_GOTO
:
12747 gcc_assert (i2
&& JUMP_P (i2
));
12752 case REG_EH_REGION
:
12753 /* These notes must remain with the call or trapping instruction. */
12756 else if (i2
&& CALL_P (i2
))
12760 gcc_assert (flag_non_call_exceptions
);
12761 if (may_trap_p (i3
))
12763 else if (i2
&& may_trap_p (i2
))
12765 /* ??? Otherwise assume we've combined things such that we
12766 can now prove that the instructions can't trap. Drop the
12767 note in this case. */
12773 /* These notes must remain with the call. It should not be
12774 possible for both I2 and I3 to be a call. */
12779 gcc_assert (i2
&& CALL_P (i2
));
12785 /* Any clobbers for i3 may still exist, and so we must process
12786 REG_UNUSED notes from that insn.
12788 Any clobbers from i2 or i1 can only exist if they were added by
12789 recog_for_combine. In that case, recog_for_combine created the
12790 necessary REG_UNUSED notes. Trying to keep any original
12791 REG_UNUSED notes from these insns can cause incorrect output
12792 if it is for the same register as the original i3 dest.
12793 In that case, we will notice that the register is set in i3,
12794 and then add a REG_UNUSED note for the destination of i3, which
12795 is wrong. However, it is possible to have REG_UNUSED notes from
12796 i2 or i1 for register which were both used and clobbered, so
12797 we keep notes from i2 or i1 if they will turn into REG_DEAD
12800 /* If this register is set or clobbered in I3, put the note there
12801 unless there is one already. */
12802 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12804 if (from_insn
!= i3
)
12807 if (! (REG_P (XEXP (note
, 0))
12808 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12809 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12812 /* Otherwise, if this register is used by I3, then this register
12813 now dies here, so we must put a REG_DEAD note here unless there
12815 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12816 && ! (REG_P (XEXP (note
, 0))
12817 ? find_regno_note (i3
, REG_DEAD
,
12818 REGNO (XEXP (note
, 0)))
12819 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12821 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12829 /* These notes say something about results of an insn. We can
12830 only support them if they used to be on I3 in which case they
12831 remain on I3. Otherwise they are ignored.
12833 If the note refers to an expression that is not a constant, we
12834 must also ignore the note since we cannot tell whether the
12835 equivalence is still true. It might be possible to do
12836 slightly better than this (we only have a problem if I2DEST
12837 or I1DEST is present in the expression), but it doesn't
12838 seem worth the trouble. */
12840 if (from_insn
== i3
12841 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12846 /* These notes say something about how a register is used. They must
12847 be present on any use of the register in I2 or I3. */
12848 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12851 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12860 case REG_LABEL_TARGET
:
12861 case REG_LABEL_OPERAND
:
12862 /* This can show up in several ways -- either directly in the
12863 pattern, or hidden off in the constant pool with (or without?)
12864 a REG_EQUAL note. */
12865 /* ??? Ignore the without-reg_equal-note problem for now. */
12866 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12867 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12868 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12869 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12873 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12874 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12875 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12876 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12884 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12885 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12887 if (place
&& JUMP_P (place
)
12888 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
12889 && (JUMP_LABEL (place
) == NULL
12890 || JUMP_LABEL (place
) == XEXP (note
, 0)))
12892 rtx label
= JUMP_LABEL (place
);
12895 JUMP_LABEL (place
) = XEXP (note
, 0);
12896 else if (LABEL_P (label
))
12897 LABEL_NUSES (label
)--;
12900 if (place2
&& JUMP_P (place2
)
12901 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
12902 && (JUMP_LABEL (place2
) == NULL
12903 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
12905 rtx label
= JUMP_LABEL (place2
);
12908 JUMP_LABEL (place2
) = XEXP (note
, 0);
12909 else if (LABEL_P (label
))
12910 LABEL_NUSES (label
)--;
12916 /* This note says something about the value of a register prior
12917 to the execution of an insn. It is too much trouble to see
12918 if the note is still correct in all situations. It is better
12919 to simply delete it. */
12923 /* If we replaced the right hand side of FROM_INSN with a
12924 REG_EQUAL note, the original use of the dying register
12925 will not have been combined into I3 and I2. In such cases,
12926 FROM_INSN is guaranteed to be the first of the combined
12927 instructions, so we simply need to search back before
12928 FROM_INSN for the previous use or set of this register,
12929 then alter the notes there appropriately.
12931 If the register is used as an input in I3, it dies there.
12932 Similarly for I2, if it is nonzero and adjacent to I3.
12934 If the register is not used as an input in either I3 or I2
12935 and it is not one of the registers we were supposed to eliminate,
12936 there are two possibilities. We might have a non-adjacent I2
12937 or we might have somehow eliminated an additional register
12938 from a computation. For example, we might have had A & B where
12939 we discover that B will always be zero. In this case we will
12940 eliminate the reference to A.
12942 In both cases, we must search to see if we can find a previous
12943 use of A and put the death note there. */
12946 && from_insn
== i2mod
12947 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
12952 && CALL_P (from_insn
)
12953 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12955 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12957 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
12958 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12960 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
12962 && reg_overlap_mentioned_p (XEXP (note
, 0),
12964 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12971 basic_block bb
= this_basic_block
;
12973 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
12975 if (!NONDEBUG_INSN_P (tem
))
12977 if (tem
== BB_HEAD (bb
))
12982 /* If the register is being set at TEM, see if that is all
12983 TEM is doing. If so, delete TEM. Otherwise, make this
12984 into a REG_UNUSED note instead. Don't delete sets to
12985 global register vars. */
12986 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12987 || !global_regs
[REGNO (XEXP (note
, 0))])
12988 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12990 rtx set
= single_set (tem
);
12991 rtx inner_dest
= 0;
12993 rtx cc0_setter
= NULL_RTX
;
12997 for (inner_dest
= SET_DEST (set
);
12998 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12999 || GET_CODE (inner_dest
) == SUBREG
13000 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13001 inner_dest
= XEXP (inner_dest
, 0))
13004 /* Verify that it was the set, and not a clobber that
13005 modified the register.
13007 CC0 targets must be careful to maintain setter/user
13008 pairs. If we cannot delete the setter due to side
13009 effects, mark the user with an UNUSED note instead
13012 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13013 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13015 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13016 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13017 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13021 /* Move the notes and links of TEM elsewhere.
13022 This might delete other dead insns recursively.
13023 First set the pattern to something that won't use
13025 rtx old_notes
= REG_NOTES (tem
);
13027 PATTERN (tem
) = pc_rtx
;
13028 REG_NOTES (tem
) = NULL
;
13030 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13031 NULL_RTX
, NULL_RTX
);
13032 distribute_links (LOG_LINKS (tem
));
13034 SET_INSN_DELETED (tem
);
13039 /* Delete the setter too. */
13042 PATTERN (cc0_setter
) = pc_rtx
;
13043 old_notes
= REG_NOTES (cc0_setter
);
13044 REG_NOTES (cc0_setter
) = NULL
;
13046 distribute_notes (old_notes
, cc0_setter
,
13047 cc0_setter
, NULL_RTX
,
13048 NULL_RTX
, NULL_RTX
);
13049 distribute_links (LOG_LINKS (cc0_setter
));
13051 SET_INSN_DELETED (cc0_setter
);
13052 if (cc0_setter
== i2
)
13059 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13061 /* If there isn't already a REG_UNUSED note, put one
13062 here. Do not place a REG_DEAD note, even if
13063 the register is also used here; that would not
13064 match the algorithm used in lifetime analysis
13065 and can cause the consistency check in the
13066 scheduler to fail. */
13067 if (! find_regno_note (tem
, REG_UNUSED
,
13068 REGNO (XEXP (note
, 0))))
13073 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13075 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13079 /* If we are doing a 3->2 combination, and we have a
13080 register which formerly died in i3 and was not used
13081 by i2, which now no longer dies in i3 and is used in
13082 i2 but does not die in i2, and place is between i2
13083 and i3, then we may need to move a link from place to
13085 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13087 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13088 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13090 rtx links
= LOG_LINKS (place
);
13091 LOG_LINKS (place
) = 0;
13092 distribute_links (links
);
13097 if (tem
== BB_HEAD (bb
))
13103 /* If the register is set or already dead at PLACE, we needn't do
13104 anything with this note if it is still a REG_DEAD note.
13105 We check here if it is set at all, not if is it totally replaced,
13106 which is what `dead_or_set_p' checks, so also check for it being
13109 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13111 unsigned int regno
= REGNO (XEXP (note
, 0));
13112 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
13114 if (dead_or_set_p (place
, XEXP (note
, 0))
13115 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13117 /* Unless the register previously died in PLACE, clear
13118 last_death. [I no longer understand why this is
13120 if (rsp
->last_death
!= place
)
13121 rsp
->last_death
= 0;
13125 rsp
->last_death
= place
;
13127 /* If this is a death note for a hard reg that is occupying
13128 multiple registers, ensure that we are still using all
13129 parts of the object. If we find a piece of the object
13130 that is unused, we must arrange for an appropriate REG_DEAD
13131 note to be added for it. However, we can't just emit a USE
13132 and tag the note to it, since the register might actually
13133 be dead; so we recourse, and the recursive call then finds
13134 the previous insn that used this register. */
13136 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13137 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13139 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13143 for (i
= regno
; i
< endregno
; i
++)
13144 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13145 && ! find_regno_fusage (place
, USE
, i
))
13146 || dead_or_set_regno_p (place
, i
))
13151 /* Put only REG_DEAD notes for pieces that are
13152 not already dead or set. */
13154 for (i
= regno
; i
< endregno
;
13155 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13157 rtx piece
= regno_reg_rtx
[i
];
13158 basic_block bb
= this_basic_block
;
13160 if (! dead_or_set_p (place
, piece
)
13161 && ! reg_bitfield_target_p (piece
,
13164 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13167 distribute_notes (new_note
, place
, place
,
13168 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13170 else if (! refers_to_regno_p (i
, i
+ 1,
13171 PATTERN (place
), 0)
13172 && ! find_regno_fusage (place
, USE
, i
))
13173 for (tem
= PREV_INSN (place
); ;
13174 tem
= PREV_INSN (tem
))
13176 if (!NONDEBUG_INSN_P (tem
))
13178 if (tem
== BB_HEAD (bb
))
13182 if (dead_or_set_p (tem
, piece
)
13183 || reg_bitfield_target_p (piece
,
13186 add_reg_note (tem
, REG_UNUSED
, piece
);
13200 /* Any other notes should not be present at this point in the
13202 gcc_unreachable ();
13207 XEXP (note
, 1) = REG_NOTES (place
);
13208 REG_NOTES (place
) = note
;
13212 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13216 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13217 I3, I2, and I1 to new locations. This is also called to add a link
13218 pointing at I3 when I3's destination is changed. */
13221 distribute_links (rtx links
)
13223 rtx link
, next_link
;
13225 for (link
= links
; link
; link
= next_link
)
13231 next_link
= XEXP (link
, 1);
13233 /* If the insn that this link points to is a NOTE or isn't a single
13234 set, ignore it. In the latter case, it isn't clear what we
13235 can do other than ignore the link, since we can't tell which
13236 register it was for. Such links wouldn't be used by combine
13239 It is not possible for the destination of the target of the link to
13240 have been changed by combine. The only potential of this is if we
13241 replace I3, I2, and I1 by I3 and I2. But in that case the
13242 destination of I2 also remains unchanged. */
13244 if (NOTE_P (XEXP (link
, 0))
13245 || (set
= single_set (XEXP (link
, 0))) == 0)
13248 reg
= SET_DEST (set
);
13249 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13250 || GET_CODE (reg
) == STRICT_LOW_PART
)
13251 reg
= XEXP (reg
, 0);
13253 /* A LOG_LINK is defined as being placed on the first insn that uses
13254 a register and points to the insn that sets the register. Start
13255 searching at the next insn after the target of the link and stop
13256 when we reach a set of the register or the end of the basic block.
13258 Note that this correctly handles the link that used to point from
13259 I3 to I2. Also note that not much searching is typically done here
13260 since most links don't point very far away. */
13262 for (insn
= NEXT_INSN (XEXP (link
, 0));
13263 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13264 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13265 insn
= NEXT_INSN (insn
))
13266 if (DEBUG_INSN_P (insn
))
13268 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13270 if (reg_referenced_p (reg
, PATTERN (insn
)))
13274 else if (CALL_P (insn
)
13275 && find_reg_fusage (insn
, USE
, reg
))
13280 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13283 /* If we found a place to put the link, place it there unless there
13284 is already a link to the same insn as LINK at that point. */
13290 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13291 if (XEXP (link2
, 0) == XEXP (link
, 0))
13296 XEXP (link
, 1) = LOG_LINKS (place
);
13297 LOG_LINKS (place
) = link
;
13299 /* Set added_links_insn to the earliest insn we added a
13301 if (added_links_insn
== 0
13302 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13303 added_links_insn
= place
;
13309 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13310 Check whether the expression pointer to by LOC is a register or
13311 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13312 Otherwise return zero. */
13315 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13320 && (REG_P (x
) || MEM_P (x
))
13321 && ! reg_mentioned_p (x
, (rtx
) expr
))
13326 /* Check for any register or memory mentioned in EQUIV that is not
13327 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13328 of EXPR where some registers may have been replaced by constants. */
13331 unmentioned_reg_p (rtx equiv
, rtx expr
)
13333 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13337 dump_combine_stats (FILE *file
)
13341 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13342 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13346 dump_combine_total_stats (FILE *file
)
13350 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13351 total_attempts
, total_merges
, total_extras
, total_successes
);
13355 gate_handle_combine (void)
13357 return (optimize
> 0);
13360 /* Try combining insns through substitution. */
13361 static unsigned int
13362 rest_of_handle_combine (void)
13364 int rebuild_jump_labels_after_combine
;
13366 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13367 df_note_add_problem ();
13370 regstat_init_n_sets_and_refs ();
13372 rebuild_jump_labels_after_combine
13373 = combine_instructions (get_insns (), max_reg_num ());
13375 /* Combining insns may have turned an indirect jump into a
13376 direct jump. Rebuild the JUMP_LABEL fields of jumping
13378 if (rebuild_jump_labels_after_combine
)
13380 timevar_push (TV_JUMP
);
13381 rebuild_jump_labels (get_insns ());
13383 timevar_pop (TV_JUMP
);
13386 regstat_free_n_sets_and_refs ();
13390 struct rtl_opt_pass pass_combine
=
13394 "combine", /* name */
13395 gate_handle_combine
, /* gate */
13396 rest_of_handle_combine
, /* execute */
13399 0, /* static_pass_number */
13400 TV_COMBINE
, /* tv_id */
13401 PROP_cfglayout
, /* properties_required */
13402 0, /* properties_provided */
13403 0, /* properties_destroyed */
13404 0, /* todo_flags_start */
13406 TODO_df_finish
| TODO_verify_rtl_sharing
|
13407 TODO_ggc_collect
, /* todo_flags_finish */