1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx_insn
*i2mod
;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 struct reg_stat_type
{
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx_insn
*last_death
;
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
265 static unsigned int reg_n_sets_max
;
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
270 static int mem_last_set
;
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
275 static int last_call_luid
;
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
283 static rtx_insn
*subst_insn
;
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
292 static int subst_low_luid
;
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
297 static HARD_REG_SET newpat_used_regs
;
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
303 static rtx_insn
*added_links_insn
;
305 /* Basic block in which we are performing combines. */
306 static basic_block this_basic_block
;
307 static bool optimize_this_for_speed_p
;
310 /* Length of the currently allocated uid_insn_cost array. */
312 static int max_uid_known
;
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
317 static int *uid_insn_cost
;
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
325 struct insn_link
*next
;
328 static struct insn_link
**uid_log_links
;
331 insn_uid_check (const_rtx insn
)
333 int uid
= INSN_UID (insn
);
334 gcc_checking_assert (uid
<= max_uid_known
);
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
346 static struct obstack insn_link_obstack
;
348 /* Allocate a link. */
350 static inline struct insn_link
*
351 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
354 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
355 sizeof (struct insn_link
));
362 /* Incremented for each basic block. */
364 static int label_tick
;
366 /* Reset to label_tick for each extended basic block in scanning order. */
368 static int label_tick_ebb_start
;
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
373 static machine_mode nonzero_bits_mode
;
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
381 static int nonzero_sign_valid
;
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
387 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
393 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
394 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
407 rtx_insn
*other_insn
;
410 static struct undobuf undobuf
;
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
415 static int n_occurrences
;
417 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
419 unsigned HOST_WIDE_INT
,
420 unsigned HOST_WIDE_INT
*);
421 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
423 unsigned int, unsigned int *);
424 static void do_SUBST (rtx
*, rtx
);
425 static void do_SUBST_INT (int *, int);
426 static void init_reg_last (void);
427 static void setup_incoming_promotions (rtx_insn
*);
428 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
429 static int cant_combine_insn_p (rtx_insn
*);
430 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
431 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
432 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
433 static int contains_muldiv (rtx
);
434 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
436 static void undo_all (void);
437 static void undo_commit (void);
438 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
439 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
440 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
441 static rtx
simplify_if_then_else (rtx
);
442 static rtx
simplify_set (rtx
);
443 static rtx
simplify_logical (rtx
);
444 static rtx
expand_compound_operation (rtx
);
445 static const_rtx
expand_field_assignment (const_rtx
);
446 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
447 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
448 static rtx
extract_left_shift (rtx
, int);
449 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
450 unsigned HOST_WIDE_INT
*);
451 static rtx
canon_reg_for_combine (rtx
, rtx
);
452 static rtx
force_to_mode (rtx
, machine_mode
,
453 unsigned HOST_WIDE_INT
, int);
454 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
455 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
456 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
457 static rtx
make_field_assignment (rtx
);
458 static rtx
apply_distributive_law (rtx
);
459 static rtx
distribute_and_simplify_rtx (rtx
, int);
460 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
461 unsigned HOST_WIDE_INT
);
462 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
463 unsigned HOST_WIDE_INT
);
464 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
465 HOST_WIDE_INT
, machine_mode
, int *);
466 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
467 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
469 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
470 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
471 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
473 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
474 static void update_table_tick (rtx
);
475 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
476 static void check_promoted_subreg (rtx_insn
*, rtx
);
477 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
478 static void record_dead_and_set_regs (rtx_insn
*);
479 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
480 static rtx
get_last_value (const_rtx
);
481 static int use_crosses_set_p (const_rtx
, int);
482 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
483 static int reg_dead_at_p (rtx
, rtx_insn
*);
484 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
485 static int reg_bitfield_target_p (rtx
, rtx
);
486 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
487 static void distribute_links (struct insn_link
*);
488 static void mark_used_regs_combine (rtx
);
489 static void record_promoted_value (rtx_insn
*, rtx
);
490 static bool unmentioned_reg_p (rtx
, rtx
);
491 static void record_truncated_values (rtx
*, void *);
492 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
493 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
514 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
520 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
521 bool op0_preserve_value
)
523 int code_int
= (int)*code
;
524 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
525 *code
= (enum rtx_code
)code_int
;
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
535 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
540 ret
= split_insns (pattern
, insn
);
541 nregs
= max_reg_num ();
542 if (nregs
> reg_stat
.length ())
543 reg_stat
.safe_grow_cleared (nregs
);
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
554 find_single_use_1 (rtx dest
, rtx
*loc
)
557 enum rtx_code code
= GET_CODE (x
);
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
577 if (GET_CODE (SET_DEST (x
)) != CC0
578 && GET_CODE (SET_DEST (x
)) != PC
579 && !REG_P (SET_DEST (x
))
580 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
581 && REG_P (SUBREG_REG (SET_DEST (x
)))
582 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
583 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
584 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
585 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
588 return find_single_use_1 (dest
, &SET_SRC (x
));
592 return find_single_use_1 (dest
, &XEXP (x
, 0));
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
601 fmt
= GET_RTX_FORMAT (code
);
602 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
606 if (dest
== XEXP (x
, i
)
607 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
608 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
611 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
614 result
= this_result
;
615 else if (this_result
)
616 /* Duplicate usage. */
619 else if (fmt
[i
] == 'E')
623 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
625 if (XVECEXP (x
, i
, j
) == dest
627 && REG_P (XVECEXP (x
, i
, j
))
628 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
631 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
634 result
= this_result
;
635 else if (this_result
)
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
660 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
665 struct insn_link
*link
;
669 next
= NEXT_INSN (insn
);
671 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
674 result
= find_single_use_1 (dest
, &PATTERN (next
));
683 bb
= BLOCK_FOR_INSN (insn
);
684 for (next
= NEXT_INSN (insn
);
685 next
&& BLOCK_FOR_INSN (next
) == bb
;
686 next
= NEXT_INSN (next
))
687 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
689 FOR_EACH_LOG_LINK (link
, next
)
690 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
695 result
= find_single_use_1 (dest
, &PATTERN (next
));
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
712 do_SUBST (rtx
*into
, rtx newval
)
717 if (oldval
== newval
)
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
725 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
726 && CONST_INT_P (newval
))
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
730 gcc_assert (INTVAL (newval
)
731 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
739 gcc_assert (!(GET_CODE (oldval
) == SUBREG
740 && CONST_INT_P (SUBREG_REG (oldval
))));
741 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
742 && CONST_INT_P (XEXP (oldval
, 0))));
746 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
748 buf
= XNEW (struct undo
);
750 buf
->kind
= UNDO_RTX
;
752 buf
->old_contents
.r
= oldval
;
755 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
765 do_SUBST_INT (int *into
, int newval
)
770 if (oldval
== newval
)
774 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
776 buf
= XNEW (struct undo
);
778 buf
->kind
= UNDO_INT
;
780 buf
->old_contents
.i
= oldval
;
783 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
794 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
797 machine_mode oldval
= GET_MODE (*into
);
799 if (oldval
== newval
)
803 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
805 buf
= XNEW (struct undo
);
807 buf
->kind
= UNDO_MODE
;
809 buf
->old_contents
.m
= oldval
;
810 adjust_reg_mode (*into
, newval
);
812 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
823 struct insn_link
* oldval
= *into
;
825 if (oldval
== newval
)
829 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
831 buf
= XNEW (struct undo
);
833 buf
->kind
= UNDO_LINKS
;
835 buf
->old_contents
.l
= oldval
;
838 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
852 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
853 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
855 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
856 int new_i2_cost
, new_i3_cost
;
857 int old_cost
, new_cost
;
859 /* Lookup the original insn_rtx_costs. */
860 i2_cost
= INSN_COST (i2
);
861 i3_cost
= INSN_COST (i3
);
865 i1_cost
= INSN_COST (i1
);
868 i0_cost
= INSN_COST (i0
);
869 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
870 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
874 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
875 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
881 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
882 i1_cost
= i0_cost
= 0;
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
891 /* Calculate the replacement insn_rtx_costs. */
892 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
895 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
896 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
897 ? new_i2_cost
+ new_i3_cost
: 0;
901 new_cost
= new_i3_cost
;
905 if (undobuf
.other_insn
)
907 int old_other_cost
, new_other_cost
;
909 old_other_cost
= INSN_COST (undobuf
.other_insn
);
910 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
911 if (old_other_cost
> 0 && new_other_cost
> 0)
913 old_cost
+= old_other_cost
;
914 new_cost
+= new_other_cost
;
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
922 int reject
= old_cost
> 0 && new_cost
> old_cost
;
926 fprintf (dump_file
, "%s combination of insns ",
927 reject
? "rejecting" : "allowing");
929 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
930 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
931 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
932 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
934 fprintf (dump_file
, "original costs ");
936 fprintf (dump_file
, "%d + ", i0_cost
);
937 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
938 fprintf (dump_file
, "%d + ", i1_cost
);
939 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
942 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
943 new_i2_cost
, new_i3_cost
, new_cost
);
945 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
951 /* Update the uid_insn_cost array with the replacement costs. */
952 INSN_COST (i2
) = new_i2_cost
;
953 INSN_COST (i3
) = new_i3_cost
;
965 /* Delete any insns that copy a register to itself. */
968 delete_noop_moves (void)
970 rtx_insn
*insn
, *next
;
973 FOR_EACH_BB_FN (bb
, cfun
)
975 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
977 next
= NEXT_INSN (insn
);
978 if (INSN_P (insn
) && noop_move_p (insn
))
981 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
983 delete_insn_and_edges (insn
);
990 /* Return false if we do not want to (or cannot) combine DEF. */
992 can_combine_def_p (df_ref def
)
994 /* Do not consider if it is pre/post modification in MEM. */
995 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
998 unsigned int regno
= DF_REF_REGNO (def
);
1000 /* Do not combine frame pointer adjustments. */
1001 if ((regno
== FRAME_POINTER_REGNUM
1002 && (!reload_completed
|| frame_pointer_needed
))
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 && regno
== HARD_FRAME_POINTER_REGNUM
1005 && (!reload_completed
|| frame_pointer_needed
))
1006 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1007 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1013 /* Return false if we do not want to (or cannot) combine USE. */
1015 can_combine_use_p (df_ref use
)
1017 /* Do not consider the usage of the stack pointer by function call. */
1018 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1024 /* Fill in log links field for all insns. */
1027 create_log_links (void)
1030 rtx_insn
**next_use
;
1034 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1045 FOR_EACH_BB_FN (bb
, cfun
)
1047 FOR_BB_INSNS_REVERSE (bb
, insn
)
1049 if (!NONDEBUG_INSN_P (insn
))
1052 /* Log links are created only once. */
1053 gcc_assert (!LOG_LINKS (insn
));
1055 FOR_EACH_INSN_DEF (def
, insn
)
1057 unsigned int regno
= DF_REF_REGNO (def
);
1060 if (!next_use
[regno
])
1063 if (!can_combine_def_p (def
))
1066 use_insn
= next_use
[regno
];
1067 next_use
[regno
] = NULL
;
1069 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1079 if (regno
< FIRST_PSEUDO_REGISTER
1080 && asm_noperands (PATTERN (use_insn
)) >= 0)
1083 /* Don't add duplicate links between instructions. */
1084 struct insn_link
*links
;
1085 FOR_EACH_LOG_LINK (links
, use_insn
)
1086 if (insn
== links
->insn
&& regno
== links
->regno
)
1090 LOG_LINKS (use_insn
)
1091 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1094 FOR_EACH_INSN_USE (use
, insn
)
1095 if (can_combine_use_p (use
))
1096 next_use
[DF_REF_REGNO (use
)] = insn
;
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1111 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1113 struct insn_link
*links
;
1114 FOR_EACH_LOG_LINK (links
, b
)
1115 if (links
->insn
== a
)
1117 if (HAVE_cc0
&& sets_cc0_p (a
))
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1128 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1130 rtx_insn
*insn
, *next
;
1132 struct insn_link
*links
, *nextlinks
;
1134 basic_block last_bb
;
1136 int new_direct_jump_p
= 0;
1138 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1139 first
= NEXT_INSN (first
);
1143 combine_attempts
= 0;
1146 combine_successes
= 0;
1148 rtl_hooks
= combine_rtl_hooks
;
1150 reg_stat
.safe_grow_cleared (nregs
);
1152 init_recog_no_volatile ();
1154 /* Allocate array for insn info. */
1155 max_uid_known
= get_max_uid ();
1156 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1157 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1158 gcc_obstack_init (&insn_link_obstack
);
1160 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1165 nonzero_sign_valid
= 0;
1166 label_tick
= label_tick_ebb_start
= 1;
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1175 setup_incoming_promotions (first
);
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1178 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1180 create_log_links ();
1181 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1183 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1188 if (!single_pred_p (this_basic_block
)
1189 || single_pred (this_basic_block
) != last_bb
)
1190 label_tick_ebb_start
= label_tick
;
1191 last_bb
= this_basic_block
;
1193 FOR_BB_INSNS (this_basic_block
, insn
)
1194 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1198 subst_low_luid
= DF_INSN_LUID (insn
);
1201 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1203 record_dead_and_set_regs (insn
);
1206 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1207 if (REG_NOTE_KIND (links
) == REG_INC
)
1208 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1211 /* Record the current insn_rtx_cost of this instruction. */
1212 if (NONJUMP_INSN_P (insn
))
1213 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1214 optimize_this_for_speed_p
);
1216 fprintf (dump_file
, "insn_cost %d: %d\n",
1217 INSN_UID (insn
), INSN_COST (insn
));
1221 nonzero_sign_valid
= 1;
1223 /* Now scan all the insns in forward order. */
1224 label_tick
= label_tick_ebb_start
= 1;
1226 setup_incoming_promotions (first
);
1227 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1228 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1230 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1232 rtx_insn
*last_combined_insn
= NULL
;
1233 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1238 if (!single_pred_p (this_basic_block
)
1239 || single_pred (this_basic_block
) != last_bb
)
1240 label_tick_ebb_start
= label_tick
;
1241 last_bb
= this_basic_block
;
1243 rtl_profile_for_bb (this_basic_block
);
1244 for (insn
= BB_HEAD (this_basic_block
);
1245 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1246 insn
= next
? next
: NEXT_INSN (insn
))
1249 if (!NONDEBUG_INSN_P (insn
))
1252 while (last_combined_insn
1253 && last_combined_insn
->deleted ())
1254 last_combined_insn
= PREV_INSN (last_combined_insn
);
1255 if (last_combined_insn
== NULL_RTX
1256 || BARRIER_P (last_combined_insn
)
1257 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1258 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1259 last_combined_insn
= insn
;
1261 /* See if we know about function return values before this
1262 insn based upon SUBREG flags. */
1263 check_promoted_subreg (insn
, PATTERN (insn
));
1265 /* See if we can find hardregs and subreg of pseudos in
1266 narrower modes. This could help turning TRUNCATEs
1268 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1270 /* Try this insn with each insn it links back to. */
1272 FOR_EACH_LOG_LINK (links
, insn
)
1273 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1274 NULL
, &new_direct_jump_p
,
1275 last_combined_insn
)) != 0)
1277 statistics_counter_event (cfun
, "two-insn combine", 1);
1281 /* Try each sequence of three linked insns ending with this one. */
1283 if (max_combine
>= 3)
1284 FOR_EACH_LOG_LINK (links
, insn
)
1286 rtx_insn
*link
= links
->insn
;
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1293 FOR_EACH_LOG_LINK (nextlinks
, link
)
1294 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1295 NULL
, &new_direct_jump_p
,
1296 last_combined_insn
)) != 0)
1298 statistics_counter_event (cfun
, "three-insn combine", 1);
1303 /* Try to combine a jump insn that uses CC0
1304 with a preceding insn that sets CC0, and maybe with its
1305 logical predecessor as well.
1306 This is how we make decrement-and-branch insns.
1307 We need this special code because data flow connections
1308 via CC0 do not get entered in LOG_LINKS. */
1312 && (prev
= prev_nonnote_insn (insn
)) != 0
1313 && NONJUMP_INSN_P (prev
)
1314 && sets_cc0_p (PATTERN (prev
)))
1316 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1318 last_combined_insn
)) != 0)
1321 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1322 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1323 NULL
, &new_direct_jump_p
,
1324 last_combined_insn
)) != 0)
1328 /* Do the same for an insn that explicitly references CC0. */
1329 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1330 && (prev
= prev_nonnote_insn (insn
)) != 0
1331 && NONJUMP_INSN_P (prev
)
1332 && sets_cc0_p (PATTERN (prev
))
1333 && GET_CODE (PATTERN (insn
)) == SET
1334 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1336 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1338 last_combined_insn
)) != 0)
1341 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1342 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1343 NULL
, &new_direct_jump_p
,
1344 last_combined_insn
)) != 0)
1348 /* Finally, see if any of the insns that this insn links to
1349 explicitly references CC0. If so, try this insn, that insn,
1350 and its predecessor if it sets CC0. */
1353 FOR_EACH_LOG_LINK (links
, insn
)
1354 if (NONJUMP_INSN_P (links
->insn
)
1355 && GET_CODE (PATTERN (links
->insn
)) == SET
1356 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1357 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1358 && NONJUMP_INSN_P (prev
)
1359 && sets_cc0_p (PATTERN (prev
))
1360 && (next
= try_combine (insn
, links
->insn
,
1361 prev
, NULL
, &new_direct_jump_p
,
1362 last_combined_insn
)) != 0)
1366 /* Try combining an insn with two different insns whose results it
1368 if (max_combine
>= 3)
1369 FOR_EACH_LOG_LINK (links
, insn
)
1370 for (nextlinks
= links
->next
; nextlinks
;
1371 nextlinks
= nextlinks
->next
)
1372 if ((next
= try_combine (insn
, links
->insn
,
1373 nextlinks
->insn
, NULL
,
1375 last_combined_insn
)) != 0)
1378 statistics_counter_event (cfun
, "three-insn combine", 1);
1382 /* Try four-instruction combinations. */
1383 if (max_combine
>= 4)
1384 FOR_EACH_LOG_LINK (links
, insn
)
1386 struct insn_link
*next1
;
1387 rtx_insn
*link
= links
->insn
;
1389 /* If the linked insn has been replaced by a note, then there
1390 is no point in pursuing this chain any further. */
1394 FOR_EACH_LOG_LINK (next1
, link
)
1396 rtx_insn
*link1
= next1
->insn
;
1399 /* I0 -> I1 -> I2 -> I3. */
1400 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1401 if ((next
= try_combine (insn
, link
, link1
,
1404 last_combined_insn
)) != 0)
1406 statistics_counter_event (cfun
, "four-insn combine", 1);
1409 /* I0, I1 -> I2, I2 -> I3. */
1410 for (nextlinks
= next1
->next
; nextlinks
;
1411 nextlinks
= nextlinks
->next
)
1412 if ((next
= try_combine (insn
, link
, link1
,
1415 last_combined_insn
)) != 0)
1417 statistics_counter_event (cfun
, "four-insn combine", 1);
1422 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1424 rtx_insn
*link1
= next1
->insn
;
1427 /* I0 -> I2; I1, I2 -> I3. */
1428 FOR_EACH_LOG_LINK (nextlinks
, link
)
1429 if ((next
= try_combine (insn
, link
, link1
,
1432 last_combined_insn
)) != 0)
1434 statistics_counter_event (cfun
, "four-insn combine", 1);
1437 /* I0 -> I1; I1, I2 -> I3. */
1438 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1439 if ((next
= try_combine (insn
, link
, link1
,
1442 last_combined_insn
)) != 0)
1444 statistics_counter_event (cfun
, "four-insn combine", 1);
1450 /* Try this insn with each REG_EQUAL note it links back to. */
1451 FOR_EACH_LOG_LINK (links
, insn
)
1454 rtx_insn
*temp
= links
->insn
;
1455 if ((set
= single_set (temp
)) != 0
1456 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1457 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1458 /* Avoid using a register that may already been marked
1459 dead by an earlier instruction. */
1460 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1461 && (GET_MODE (note
) == VOIDmode
1462 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1463 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1464 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1465 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1466 == GET_MODE (note
))))))
1468 /* Temporarily replace the set's source with the
1469 contents of the REG_EQUAL note. The insn will
1470 be deleted or recognized by try_combine. */
1471 rtx orig_src
= SET_SRC (set
);
1472 rtx orig_dest
= SET_DEST (set
);
1473 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1474 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1475 SET_SRC (set
) = note
;
1477 i2mod_old_rhs
= copy_rtx (orig_src
);
1478 i2mod_new_rhs
= copy_rtx (note
);
1479 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1481 last_combined_insn
);
1485 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1488 SET_SRC (set
) = orig_src
;
1489 SET_DEST (set
) = orig_dest
;
1494 record_dead_and_set_regs (insn
);
1501 default_rtl_profile ();
1503 new_direct_jump_p
|= purge_all_dead_edges ();
1504 delete_noop_moves ();
1507 obstack_free (&insn_link_obstack
, NULL
);
1508 free (uid_log_links
);
1509 free (uid_insn_cost
);
1510 reg_stat
.release ();
1513 struct undo
*undo
, *next
;
1514 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1522 total_attempts
+= combine_attempts
;
1523 total_merges
+= combine_merges
;
1524 total_extras
+= combine_extras
;
1525 total_successes
+= combine_successes
;
1527 nonzero_sign_valid
= 0;
1528 rtl_hooks
= general_rtl_hooks
;
1530 /* Make recognizer allow volatile MEMs again. */
1533 return new_direct_jump_p
;
1536 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1539 init_reg_last (void)
1544 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1545 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1548 /* Set up any promoted values for incoming argument registers. */
1551 setup_incoming_promotions (rtx_insn
*first
)
1554 bool strictly_local
= false;
1556 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1557 arg
= DECL_CHAIN (arg
))
1559 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1561 machine_mode mode1
, mode2
, mode3
, mode4
;
1563 /* Only continue if the incoming argument is in a register. */
1567 /* Determine, if possible, whether all call sites of the current
1568 function lie within the current compilation unit. (This does
1569 take into account the exporting of a function via taking its
1570 address, and so forth.) */
1571 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1573 /* The mode and signedness of the argument before any promotions happen
1574 (equal to the mode of the pseudo holding it at that stage). */
1575 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1576 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1578 /* The mode and signedness of the argument after any source language and
1579 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1580 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1581 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1583 /* The mode and signedness of the argument as it is actually passed,
1584 see assign_parm_setup_reg in function.c. */
1585 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1586 TREE_TYPE (cfun
->decl
), 0);
1588 /* The mode of the register in which the argument is being passed. */
1589 mode4
= GET_MODE (reg
);
1591 /* Eliminate sign extensions in the callee when:
1592 (a) A mode promotion has occurred; */
1595 /* (b) The mode of the register is the same as the mode of
1596 the argument as it is passed; */
1599 /* (c) There's no language level extension; */
1602 /* (c.1) All callers are from the current compilation unit. If that's
1603 the case we don't have to rely on an ABI, we only have to know
1604 what we're generating right now, and we know that we will do the
1605 mode1 to mode2 promotion with the given sign. */
1606 else if (!strictly_local
)
1608 /* (c.2) The combination of the two promotions is useful. This is
1609 true when the signs match, or if the first promotion is unsigned.
1610 In the later case, (sign_extend (zero_extend x)) is the same as
1611 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1617 /* Record that the value was promoted from mode1 to mode3,
1618 so that any sign extension at the head of the current
1619 function may be eliminated. */
1620 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1621 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1622 record_value_for_reg (reg
, first
, x
);
1626 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1627 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1628 because some machines (maybe most) will actually do the sign-extension and
1629 this is the conservative approach.
1631 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1635 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1637 if (GET_MODE_PRECISION (mode
) < prec
1638 && CONST_INT_P (src
)
1640 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1641 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1646 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1650 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1653 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1654 unsigned HOST_WIDE_INT bits
= 0;
1655 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1656 unsigned int num
= 0;
1659 reg_equal
= XEXP (reg_equal_note
, 0);
1661 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1663 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1665 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1668 /* Don't call nonzero_bits if it cannot change anything. */
1669 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1671 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1672 if (reg_equal
&& bits
)
1673 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1674 rsp
->nonzero_bits
|= bits
;
1677 /* Don't call num_sign_bit_copies if it cannot change anything. */
1678 if (rsp
->sign_bit_copies
!= 1)
1680 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1681 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1683 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1684 if (num
== 0 || numeq
> num
)
1687 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1688 rsp
->sign_bit_copies
= num
;
1692 /* Called via note_stores. If X is a pseudo that is narrower than
1693 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1695 If we are setting only a portion of X and we can't figure out what
1696 portion, assume all bits will be used since we don't know what will
1699 Similarly, set how many bits of X are known to be copies of the sign bit
1700 at all locations in the function. This is the smallest number implied
1704 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1706 rtx_insn
*insn
= (rtx_insn
*) data
;
1709 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1710 /* If this register is undefined at the start of the file, we can't
1711 say what its contents were. */
1712 && ! REGNO_REG_SET_P
1713 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1714 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1716 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1718 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1720 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1721 rsp
->sign_bit_copies
= 1;
1725 /* If this register is being initialized using itself, and the
1726 register is uninitialized in this basic block, and there are
1727 no LOG_LINKS which set the register, then part of the
1728 register is uninitialized. In that case we can't assume
1729 anything about the number of nonzero bits.
1731 ??? We could do better if we checked this in
1732 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1733 could avoid making assumptions about the insn which initially
1734 sets the register, while still using the information in other
1735 insns. We would have to be careful to check every insn
1736 involved in the combination. */
1739 && reg_referenced_p (x
, PATTERN (insn
))
1740 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1743 struct insn_link
*link
;
1745 FOR_EACH_LOG_LINK (link
, insn
)
1746 if (dead_or_set_p (link
->insn
, x
))
1750 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1751 rsp
->sign_bit_copies
= 1;
1756 /* If this is a complex assignment, see if we can convert it into a
1757 simple assignment. */
1758 set
= expand_field_assignment (set
);
1760 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1761 set what we know about X. */
1763 if (SET_DEST (set
) == x
1764 || (paradoxical_subreg_p (SET_DEST (set
))
1765 && SUBREG_REG (SET_DEST (set
)) == x
))
1766 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1769 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1770 rsp
->sign_bit_copies
= 1;
1775 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1776 optionally insns that were previously combined into I3 or that will be
1777 combined into the merger of INSN and I3. The order is PRED, PRED2,
1778 INSN, SUCC, SUCC2, I3.
1780 Return 0 if the combination is not allowed for any reason.
1782 If the combination is allowed, *PDEST will be set to the single
1783 destination of INSN and *PSRC to the single source, and this function
1787 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1788 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1789 rtx
*pdest
, rtx
*psrc
)
1796 bool all_adjacent
= true;
1797 int (*is_volatile_p
) (const_rtx
);
1803 if (next_active_insn (succ2
) != i3
)
1804 all_adjacent
= false;
1805 if (next_active_insn (succ
) != succ2
)
1806 all_adjacent
= false;
1808 else if (next_active_insn (succ
) != i3
)
1809 all_adjacent
= false;
1810 if (next_active_insn (insn
) != succ
)
1811 all_adjacent
= false;
1813 else if (next_active_insn (insn
) != i3
)
1814 all_adjacent
= false;
1816 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1817 or a PARALLEL consisting of such a SET and CLOBBERs.
1819 If INSN has CLOBBER parallel parts, ignore them for our processing.
1820 By definition, these happen during the execution of the insn. When it
1821 is merged with another insn, all bets are off. If they are, in fact,
1822 needed and aren't also supplied in I3, they may be added by
1823 recog_for_combine. Otherwise, it won't match.
1825 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1828 Get the source and destination of INSN. If more than one, can't
1831 if (GET_CODE (PATTERN (insn
)) == SET
)
1832 set
= PATTERN (insn
);
1833 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1834 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1836 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1838 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1840 switch (GET_CODE (elt
))
1842 /* This is important to combine floating point insns
1843 for the SH4 port. */
1845 /* Combining an isolated USE doesn't make sense.
1846 We depend here on combinable_i3pat to reject them. */
1847 /* The code below this loop only verifies that the inputs of
1848 the SET in INSN do not change. We call reg_set_between_p
1849 to verify that the REG in the USE does not change between
1851 If the USE in INSN was for a pseudo register, the matching
1852 insn pattern will likely match any register; combining this
1853 with any other USE would only be safe if we knew that the
1854 used registers have identical values, or if there was
1855 something to tell them apart, e.g. different modes. For
1856 now, we forgo such complicated tests and simply disallow
1857 combining of USES of pseudo registers with any other USE. */
1858 if (REG_P (XEXP (elt
, 0))
1859 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1861 rtx i3pat
= PATTERN (i3
);
1862 int i
= XVECLEN (i3pat
, 0) - 1;
1863 unsigned int regno
= REGNO (XEXP (elt
, 0));
1867 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1869 if (GET_CODE (i3elt
) == USE
1870 && REG_P (XEXP (i3elt
, 0))
1871 && (REGNO (XEXP (i3elt
, 0)) == regno
1872 ? reg_set_between_p (XEXP (elt
, 0),
1873 PREV_INSN (insn
), i3
)
1874 : regno
>= FIRST_PSEUDO_REGISTER
))
1881 /* We can ignore CLOBBERs. */
1886 /* Ignore SETs whose result isn't used but not those that
1887 have side-effects. */
1888 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1889 && insn_nothrow_p (insn
)
1890 && !side_effects_p (elt
))
1893 /* If we have already found a SET, this is a second one and
1894 so we cannot combine with this insn. */
1902 /* Anything else means we can't combine. */
1908 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1909 so don't do anything with it. */
1910 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1919 /* The simplification in expand_field_assignment may call back to
1920 get_last_value, so set safe guard here. */
1921 subst_low_luid
= DF_INSN_LUID (insn
);
1923 set
= expand_field_assignment (set
);
1924 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1926 /* Do not eliminate user-specified register if it is in an
1927 asm input because we may break the register asm usage defined
1928 in GCC manual if allow to do so.
1929 Be aware that this may cover more cases than we expect but this
1930 should be harmless. */
1931 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1932 && extract_asm_operands (PATTERN (i3
)))
1935 /* Don't eliminate a store in the stack pointer. */
1936 if (dest
== stack_pointer_rtx
1937 /* Don't combine with an insn that sets a register to itself if it has
1938 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1939 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1940 /* Can't merge an ASM_OPERANDS. */
1941 || GET_CODE (src
) == ASM_OPERANDS
1942 /* Can't merge a function call. */
1943 || GET_CODE (src
) == CALL
1944 /* Don't eliminate a function call argument. */
1946 && (find_reg_fusage (i3
, USE
, dest
)
1948 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1949 && global_regs
[REGNO (dest
)])))
1950 /* Don't substitute into an incremented register. */
1951 || FIND_REG_INC_NOTE (i3
, dest
)
1952 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1953 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1954 /* Don't substitute into a non-local goto, this confuses CFG. */
1955 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1956 /* Make sure that DEST is not used after SUCC but before I3. */
1959 && (reg_used_between_p (dest
, succ2
, i3
)
1960 || reg_used_between_p (dest
, succ
, succ2
)))
1961 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1962 /* Make sure that the value that is to be substituted for the register
1963 does not use any registers whose values alter in between. However,
1964 If the insns are adjacent, a use can't cross a set even though we
1965 think it might (this can happen for a sequence of insns each setting
1966 the same destination; last_set of that register might point to
1967 a NOTE). If INSN has a REG_EQUIV note, the register is always
1968 equivalent to the memory so the substitution is valid even if there
1969 are intervening stores. Also, don't move a volatile asm or
1970 UNSPEC_VOLATILE across any other insns. */
1973 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1974 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1975 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1976 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1977 /* Don't combine across a CALL_INSN, because that would possibly
1978 change whether the life span of some REGs crosses calls or not,
1979 and it is a pain to update that information.
1980 Exception: if source is a constant, moving it later can't hurt.
1981 Accept that as a special case. */
1982 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1985 /* DEST must either be a REG or CC0. */
1988 /* If register alignment is being enforced for multi-word items in all
1989 cases except for parameters, it is possible to have a register copy
1990 insn referencing a hard register that is not allowed to contain the
1991 mode being copied and which would not be valid as an operand of most
1992 insns. Eliminate this problem by not combining with such an insn.
1994 Also, on some machines we don't want to extend the life of a hard
1998 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1999 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
2000 /* Don't extend the life of a hard register unless it is
2001 user variable (if we have few registers) or it can't
2002 fit into the desired register (meaning something special
2004 Also avoid substituting a return register into I3, because
2005 reload can't handle a conflict with constraints of other
2007 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2008 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2011 else if (GET_CODE (dest
) != CC0
)
2015 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2016 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2017 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2019 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2021 /* If the clobber represents an earlyclobber operand, we must not
2022 substitute an expression containing the clobbered register.
2023 As we do not analyze the constraint strings here, we have to
2024 make the conservative assumption. However, if the register is
2025 a fixed hard reg, the clobber cannot represent any operand;
2026 we leave it up to the machine description to either accept or
2027 reject use-and-clobber patterns. */
2029 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2030 || !fixed_regs
[REGNO (reg
)])
2031 if (reg_overlap_mentioned_p (reg
, src
))
2035 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2036 or not), reject, unless nothing volatile comes between it and I3 */
2038 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2040 /* Make sure neither succ nor succ2 contains a volatile reference. */
2041 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2043 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2045 /* We'll check insns between INSN and I3 below. */
2048 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2049 to be an explicit register variable, and was chosen for a reason. */
2051 if (GET_CODE (src
) == ASM_OPERANDS
2052 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2055 /* If INSN contains volatile references (specifically volatile MEMs),
2056 we cannot combine across any other volatile references.
2057 Even if INSN doesn't contain volatile references, any intervening
2058 volatile insn might affect machine state. */
2060 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2064 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2065 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2068 /* If INSN contains an autoincrement or autodecrement, make sure that
2069 register is not used between there and I3, and not already used in
2070 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2071 Also insist that I3 not be a jump; if it were one
2072 and the incremented register were spilled, we would lose. */
2075 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2076 if (REG_NOTE_KIND (link
) == REG_INC
2078 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2079 || (pred
!= NULL_RTX
2080 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2081 || (pred2
!= NULL_RTX
2082 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2083 || (succ
!= NULL_RTX
2084 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2085 || (succ2
!= NULL_RTX
2086 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2087 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2090 /* Don't combine an insn that follows a CC0-setting insn.
2091 An insn that uses CC0 must not be separated from the one that sets it.
2092 We do, however, allow I2 to follow a CC0-setting insn if that insn
2093 is passed as I1; in that case it will be deleted also.
2094 We also allow combining in this case if all the insns are adjacent
2095 because that would leave the two CC0 insns adjacent as well.
2096 It would be more logical to test whether CC0 occurs inside I1 or I2,
2097 but that would be much slower, and this ought to be equivalent. */
2101 p
= prev_nonnote_insn (insn
);
2102 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2107 /* If we get here, we have passed all the tests and the combination is
2116 /* LOC is the location within I3 that contains its pattern or the component
2117 of a PARALLEL of the pattern. We validate that it is valid for combining.
2119 One problem is if I3 modifies its output, as opposed to replacing it
2120 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2121 doing so would produce an insn that is not equivalent to the original insns.
2125 (set (reg:DI 101) (reg:DI 100))
2126 (set (subreg:SI (reg:DI 101) 0) <foo>)
2128 This is NOT equivalent to:
2130 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2131 (set (reg:DI 101) (reg:DI 100))])
2133 Not only does this modify 100 (in which case it might still be valid
2134 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2136 We can also run into a problem if I2 sets a register that I1
2137 uses and I1 gets directly substituted into I3 (not via I2). In that
2138 case, we would be getting the wrong value of I2DEST into I3, so we
2139 must reject the combination. This case occurs when I2 and I1 both
2140 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2141 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2142 of a SET must prevent combination from occurring. The same situation
2143 can occur for I0, in which case I0_NOT_IN_SRC is set.
2145 Before doing the above check, we first try to expand a field assignment
2146 into a set of logical operations.
2148 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2149 we place a register that is both set and used within I3. If more than one
2150 such register is detected, we fail.
2152 Return 1 if the combination is valid, zero otherwise. */
2155 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2156 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2160 if (GET_CODE (x
) == SET
)
2163 rtx dest
= SET_DEST (set
);
2164 rtx src
= SET_SRC (set
);
2165 rtx inner_dest
= dest
;
2168 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2169 || GET_CODE (inner_dest
) == SUBREG
2170 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2171 inner_dest
= XEXP (inner_dest
, 0);
2173 /* Check for the case where I3 modifies its output, as discussed
2174 above. We don't want to prevent pseudos from being combined
2175 into the address of a MEM, so only prevent the combination if
2176 i1 or i2 set the same MEM. */
2177 if ((inner_dest
!= dest
&&
2178 (!MEM_P (inner_dest
)
2179 || rtx_equal_p (i2dest
, inner_dest
)
2180 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2181 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2182 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2183 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2184 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2186 /* This is the same test done in can_combine_p except we can't test
2187 all_adjacent; we don't have to, since this instruction will stay
2188 in place, thus we are not considering increasing the lifetime of
2191 Also, if this insn sets a function argument, combining it with
2192 something that might need a spill could clobber a previous
2193 function argument; the all_adjacent test in can_combine_p also
2194 checks this; here, we do a more specific test for this case. */
2196 || (REG_P (inner_dest
)
2197 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2198 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2199 GET_MODE (inner_dest
))))
2200 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2201 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2204 /* If DEST is used in I3, it is being killed in this insn, so
2205 record that for later. We have to consider paradoxical
2206 subregs here, since they kill the whole register, but we
2207 ignore partial subregs, STRICT_LOW_PART, etc.
2208 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2209 STACK_POINTER_REGNUM, since these are always considered to be
2210 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2212 if (GET_CODE (subdest
) == SUBREG
2213 && (GET_MODE_SIZE (GET_MODE (subdest
))
2214 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2215 subdest
= SUBREG_REG (subdest
);
2218 && reg_referenced_p (subdest
, PATTERN (i3
))
2219 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2220 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2221 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2222 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2223 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2224 || ! fixed_regs
[REGNO (subdest
)]))
2225 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2227 if (*pi3dest_killed
)
2230 *pi3dest_killed
= subdest
;
2234 else if (GET_CODE (x
) == PARALLEL
)
2238 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2239 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2240 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2247 /* Return 1 if X is an arithmetic expression that contains a multiplication
2248 and division. We don't count multiplications by powers of two here. */
2251 contains_muldiv (rtx x
)
2253 switch (GET_CODE (x
))
2255 case MOD
: case DIV
: case UMOD
: case UDIV
:
2259 return ! (CONST_INT_P (XEXP (x
, 1))
2260 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2263 return contains_muldiv (XEXP (x
, 0))
2264 || contains_muldiv (XEXP (x
, 1));
2267 return contains_muldiv (XEXP (x
, 0));
2273 /* Determine whether INSN can be used in a combination. Return nonzero if
2274 not. This is used in try_combine to detect early some cases where we
2275 can't perform combinations. */
2278 cant_combine_insn_p (rtx_insn
*insn
)
2283 /* If this isn't really an insn, we can't do anything.
2284 This can occur when flow deletes an insn that it has merged into an
2285 auto-increment address. */
2286 if (!NONDEBUG_INSN_P (insn
))
2289 /* Never combine loads and stores involving hard regs that are likely
2290 to be spilled. The register allocator can usually handle such
2291 reg-reg moves by tying. If we allow the combiner to make
2292 substitutions of likely-spilled regs, reload might die.
2293 As an exception, we allow combinations involving fixed regs; these are
2294 not available to the register allocator so there's no risk involved. */
2296 set
= single_set (insn
);
2299 src
= SET_SRC (set
);
2300 dest
= SET_DEST (set
);
2301 if (GET_CODE (src
) == SUBREG
)
2302 src
= SUBREG_REG (src
);
2303 if (GET_CODE (dest
) == SUBREG
)
2304 dest
= SUBREG_REG (dest
);
2305 if (REG_P (src
) && REG_P (dest
)
2306 && ((HARD_REGISTER_P (src
)
2307 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2308 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2309 || (HARD_REGISTER_P (dest
)
2310 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2311 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2317 struct likely_spilled_retval_info
2319 unsigned regno
, nregs
;
2323 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2324 hard registers that are known to be written to / clobbered in full. */
2326 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2328 struct likely_spilled_retval_info
*const info
=
2329 (struct likely_spilled_retval_info
*) data
;
2330 unsigned regno
, nregs
;
2333 if (!REG_P (XEXP (set
, 0)))
2336 if (regno
>= info
->regno
+ info
->nregs
)
2338 nregs
= REG_NREGS (x
);
2339 if (regno
+ nregs
<= info
->regno
)
2341 new_mask
= (2U << (nregs
- 1)) - 1;
2342 if (regno
< info
->regno
)
2343 new_mask
>>= info
->regno
- regno
;
2345 new_mask
<<= regno
- info
->regno
;
2346 info
->mask
&= ~new_mask
;
2349 /* Return nonzero iff part of the return value is live during INSN, and
2350 it is likely spilled. This can happen when more than one insn is needed
2351 to copy the return value, e.g. when we consider to combine into the
2352 second copy insn for a complex value. */
2355 likely_spilled_retval_p (rtx_insn
*insn
)
2357 rtx_insn
*use
= BB_END (this_basic_block
);
2360 unsigned regno
, nregs
;
2361 /* We assume here that no machine mode needs more than
2362 32 hard registers when the value overlaps with a register
2363 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2365 struct likely_spilled_retval_info info
;
2367 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2369 reg
= XEXP (PATTERN (use
), 0);
2370 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2372 regno
= REGNO (reg
);
2373 nregs
= REG_NREGS (reg
);
2376 mask
= (2U << (nregs
- 1)) - 1;
2378 /* Disregard parts of the return value that are set later. */
2382 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2384 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2387 /* Check if any of the (probably) live return value registers is
2392 if ((mask
& 1 << nregs
)
2393 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2399 /* Adjust INSN after we made a change to its destination.
2401 Changing the destination can invalidate notes that say something about
2402 the results of the insn and a LOG_LINK pointing to the insn. */
2405 adjust_for_new_dest (rtx_insn
*insn
)
2407 /* For notes, be conservative and simply remove them. */
2408 remove_reg_equal_equiv_notes (insn
);
2410 /* The new insn will have a destination that was previously the destination
2411 of an insn just above it. Call distribute_links to make a LOG_LINK from
2412 the next use of that destination. */
2414 rtx set
= single_set (insn
);
2417 rtx reg
= SET_DEST (set
);
2419 while (GET_CODE (reg
) == ZERO_EXTRACT
2420 || GET_CODE (reg
) == STRICT_LOW_PART
2421 || GET_CODE (reg
) == SUBREG
)
2422 reg
= XEXP (reg
, 0);
2423 gcc_assert (REG_P (reg
));
2425 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2427 df_insn_rescan (insn
);
2430 /* Return TRUE if combine can reuse reg X in mode MODE.
2431 ADDED_SETS is nonzero if the original set is still required. */
2433 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2441 /* Allow hard registers if the new mode is legal, and occupies no more
2442 registers than the old mode. */
2443 if (regno
< FIRST_PSEUDO_REGISTER
)
2444 return (HARD_REGNO_MODE_OK (regno
, mode
)
2445 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2447 /* Or a pseudo that is only used once. */
2448 return (regno
< reg_n_sets_max
2449 && REG_N_SETS (regno
) == 1
2451 && !REG_USERVAR_P (x
));
2455 /* Check whether X, the destination of a set, refers to part of
2456 the register specified by REG. */
2459 reg_subword_p (rtx x
, rtx reg
)
2461 /* Check that reg is an integer mode register. */
2462 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2465 if (GET_CODE (x
) == STRICT_LOW_PART
2466 || GET_CODE (x
) == ZERO_EXTRACT
)
2469 return GET_CODE (x
) == SUBREG
2470 && SUBREG_REG (x
) == reg
2471 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2474 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2475 Note that the INSN should be deleted *after* removing dead edges, so
2476 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2477 but not for a (set (pc) (label_ref FOO)). */
2480 update_cfg_for_uncondjump (rtx_insn
*insn
)
2482 basic_block bb
= BLOCK_FOR_INSN (insn
);
2483 gcc_assert (BB_END (bb
) == insn
);
2485 purge_dead_edges (bb
);
2488 if (EDGE_COUNT (bb
->succs
) == 1)
2492 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2494 /* Remove barriers from the footer if there are any. */
2495 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2496 if (BARRIER_P (insn
))
2498 if (PREV_INSN (insn
))
2499 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2501 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2502 if (NEXT_INSN (insn
))
2503 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2505 else if (LABEL_P (insn
))
2510 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2511 by an arbitrary number of CLOBBERs. */
2513 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2515 if (GET_CODE (pat
) != PARALLEL
)
2518 int len
= XVECLEN (pat
, 0);
2523 for (i
= 0; i
< n
; i
++)
2524 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2525 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2527 for ( ; i
< len
; i
++)
2528 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
2529 || XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2535 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2536 CLOBBERs), can be split into individual SETs in that order, without
2537 changing semantics. */
2539 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2541 if (!insn_nothrow_p (insn
))
2544 rtx pat
= PATTERN (insn
);
2547 for (i
= 0; i
< n
; i
++)
2549 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2552 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2554 for (j
= i
+ 1; j
< n
; j
++)
2555 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2562 /* Set up a set of registers used in an insn. Called through note_uses,
2563 arguments as described for that function. */
2566 record_used_regs (rtx
*xptr
, void *data
)
2568 bitmap set
= (bitmap
)data
;
2574 /* repeat is used to turn tail-recursion into iteration since GCC
2575 can't do it when there's no return value. */
2580 code
= GET_CODE (x
);
2583 unsigned regno
= REGNO (x
);
2584 unsigned end_regno
= END_REGNO (x
);
2585 while (regno
< end_regno
)
2586 bitmap_set_bit (set
, regno
++);
2590 /* Recursively scan the operands of this expression. */
2592 for (i
= GET_RTX_LENGTH (code
) - 1, fmt
= GET_RTX_FORMAT (code
); i
>= 0; i
--)
2596 /* If we are about to do the last recursive call
2597 needed at this level, change it into iteration.
2598 This function is called enough to be worth it. */
2605 record_used_regs (&XEXP (x
, i
), data
);
2607 else if (fmt
[i
] == 'E')
2608 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2609 record_used_regs (&XVECEXP (x
, i
, j
), data
);
2613 /* Try to combine the insns I0, I1 and I2 into I3.
2614 Here I0, I1 and I2 appear earlier than I3.
2615 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2618 If we are combining more than two insns and the resulting insn is not
2619 recognized, try splitting it into two insns. If that happens, I2 and I3
2620 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2621 Otherwise, I0, I1 and I2 are pseudo-deleted.
2623 Return 0 if the combination does not work. Then nothing is changed.
2624 If we did the combination, return the insn at which combine should
2627 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2628 new direct jump instruction.
2630 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2631 been I3 passed to an earlier try_combine within the same basic
2635 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2636 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2638 /* New patterns for I3 and I2, respectively. */
2639 rtx newpat
, newi2pat
= 0;
2640 rtvec newpat_vec_with_clobbers
= 0;
2641 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2642 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2644 int added_sets_0
, added_sets_1
, added_sets_2
;
2645 /* Total number of SETs to put into I3. */
2647 /* Nonzero if I2's or I1's body now appears in I3. */
2648 int i2_is_used
= 0, i1_is_used
= 0;
2649 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2650 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2651 /* Contains I3 if the destination of I3 is used in its source, which means
2652 that the old life of I3 is being killed. If that usage is placed into
2653 I2 and not in I3, a REG_DEAD note must be made. */
2654 rtx i3dest_killed
= 0;
2655 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2656 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2657 /* Copy of SET_SRC of I1 and I0, if needed. */
2658 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2659 /* Set if I2DEST was reused as a scratch register. */
2660 bool i2scratch
= false;
2661 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2662 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2663 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2664 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2665 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2666 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2667 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2668 /* Notes that must be added to REG_NOTES in I3 and I2. */
2669 rtx new_i3_notes
, new_i2_notes
;
2670 /* Notes that we substituted I3 into I2 instead of the normal case. */
2671 int i3_subst_into_i2
= 0;
2672 /* Notes that I1, I2 or I3 is a MULT operation. */
2675 int changed_i3_dest
= 0;
2678 rtx_insn
*temp_insn
;
2680 struct insn_link
*link
;
2682 rtx new_other_notes
;
2685 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2687 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2690 /* Only try four-insn combinations when there's high likelihood of
2691 success. Look for simple insns, such as loads of constants or
2692 binary operations involving a constant. */
2700 if (!flag_expensive_optimizations
)
2703 for (i
= 0; i
< 4; i
++)
2705 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2706 rtx set
= single_set (insn
);
2710 src
= SET_SRC (set
);
2711 if (CONSTANT_P (src
))
2716 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2718 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2719 || GET_CODE (src
) == LSHIFTRT
)
2723 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2724 are likely manipulating its value. Ideally we'll be able to combine
2725 all four insns into a bitfield insertion of some kind.
2727 Note the source in I0 might be inside a sign/zero extension and the
2728 memory modes in I0 and I3 might be different. So extract the address
2729 from the destination of I3 and search for it in the source of I0.
2731 In the event that there's a match but the source/dest do not actually
2732 refer to the same memory, the worst that happens is we try some
2733 combinations that we wouldn't have otherwise. */
2734 if ((set0
= single_set (i0
))
2735 /* Ensure the source of SET0 is a MEM, possibly buried inside
2737 && (GET_CODE (SET_SRC (set0
)) == MEM
2738 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2739 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2740 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2741 && (set3
= single_set (i3
))
2742 /* Ensure the destination of SET3 is a MEM. */
2743 && GET_CODE (SET_DEST (set3
)) == MEM
2744 /* Would it be better to extract the base address for the MEM
2745 in SET3 and look for that? I don't have cases where it matters
2746 but I could envision such cases. */
2747 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2750 if (ngood
< 2 && nshift
< 2)
2754 /* Exit early if one of the insns involved can't be used for
2757 || (i1
&& CALL_P (i1
))
2758 || (i0
&& CALL_P (i0
))
2759 || cant_combine_insn_p (i3
)
2760 || cant_combine_insn_p (i2
)
2761 || (i1
&& cant_combine_insn_p (i1
))
2762 || (i0
&& cant_combine_insn_p (i0
))
2763 || likely_spilled_retval_p (i3
))
2767 undobuf
.other_insn
= 0;
2769 /* Reset the hard register usage information. */
2770 CLEAR_HARD_REG_SET (newpat_used_regs
);
2772 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2775 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2776 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2778 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2779 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2781 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2782 INSN_UID (i2
), INSN_UID (i3
));
2785 /* If multiple insns feed into one of I2 or I3, they can be in any
2786 order. To simplify the code below, reorder them in sequence. */
2787 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2789 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2791 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2794 added_links_insn
= 0;
2796 /* For combinations that may result in two insns, we have to gather
2797 some extra information about registers used, so that we can
2798 update all relevant LOG_LINKS later. */
2799 auto_bitmap i2_regset
, i3_regset
, links_regset
;
2802 note_uses (&PATTERN (i2
), record_used_regs
, (bitmap
)i2_regset
);
2803 note_uses (&PATTERN (i3
), record_used_regs
, (bitmap
)i3_regset
);
2805 FOR_EACH_LOG_LINK (ll
, i3
)
2806 bitmap_set_bit (links_regset
, ll
->regno
);
2807 FOR_EACH_LOG_LINK (ll
, i2
)
2808 bitmap_set_bit (links_regset
, ll
->regno
);
2810 FOR_EACH_LOG_LINK (ll
, i1
)
2811 bitmap_set_bit (links_regset
, ll
->regno
);
2813 FOR_EACH_LOG_LINK (ll
, i0
)
2814 bitmap_set_bit (links_regset
, ll
->regno
);
2817 /* First check for one important special case that the code below will
2818 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2819 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2820 we may be able to replace that destination with the destination of I3.
2821 This occurs in the common code where we compute both a quotient and
2822 remainder into a structure, in which case we want to do the computation
2823 directly into the structure to avoid register-register copies.
2825 Note that this case handles both multiple sets in I2 and also cases
2826 where I2 has a number of CLOBBERs inside the PARALLEL.
2828 We make very conservative checks below and only try to handle the
2829 most common cases of this. For example, we only handle the case
2830 where I2 and I3 are adjacent to avoid making difficult register
2833 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2834 && REG_P (SET_SRC (PATTERN (i3
)))
2835 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2836 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2837 && GET_CODE (PATTERN (i2
)) == PARALLEL
2838 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2839 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2840 below would need to check what is inside (and reg_overlap_mentioned_p
2841 doesn't support those codes anyway). Don't allow those destinations;
2842 the resulting insn isn't likely to be recognized anyway. */
2843 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2844 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2845 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2846 SET_DEST (PATTERN (i3
)))
2847 && next_active_insn (i2
) == i3
)
2849 rtx p2
= PATTERN (i2
);
2851 /* Make sure that the destination of I3,
2852 which we are going to substitute into one output of I2,
2853 is not used within another output of I2. We must avoid making this:
2854 (parallel [(set (mem (reg 69)) ...)
2855 (set (reg 69) ...)])
2856 which is not well-defined as to order of actions.
2857 (Besides, reload can't handle output reloads for this.)
2859 The problem can also happen if the dest of I3 is a memory ref,
2860 if another dest in I2 is an indirect memory ref.
2862 Neither can this PARALLEL be an asm. We do not allow combining
2863 that usually (see can_combine_p), so do not here either. */
2865 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2867 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2868 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2869 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2870 SET_DEST (XVECEXP (p2
, 0, i
))))
2872 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2873 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2878 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2879 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2880 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2885 subst_low_luid
= DF_INSN_LUID (i2
);
2887 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2888 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2889 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2890 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2892 /* Replace the dest in I2 with our dest and make the resulting
2893 insn the new pattern for I3. Then skip to where we validate
2894 the pattern. Everything was set up above. */
2895 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2897 i3_subst_into_i2
= 1;
2898 goto validate_replacement
;
2902 /* If I2 is setting a pseudo to a constant and I3 is setting some
2903 sub-part of it to another constant, merge them by making a new
2906 && (temp_expr
= single_set (i2
)) != 0
2907 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2908 && GET_CODE (PATTERN (i3
)) == SET
2909 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2910 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2912 rtx dest
= SET_DEST (PATTERN (i3
));
2916 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2918 if (CONST_INT_P (XEXP (dest
, 1))
2919 && CONST_INT_P (XEXP (dest
, 2)))
2921 width
= INTVAL (XEXP (dest
, 1));
2922 offset
= INTVAL (XEXP (dest
, 2));
2923 dest
= XEXP (dest
, 0);
2924 if (BITS_BIG_ENDIAN
)
2925 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2930 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2931 dest
= XEXP (dest
, 0);
2932 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2938 /* If this is the low part, we're done. */
2939 if (subreg_lowpart_p (dest
))
2941 /* Handle the case where inner is twice the size of outer. */
2942 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2943 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2944 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2945 /* Otherwise give up for now. */
2952 rtx inner
= SET_SRC (PATTERN (i3
));
2953 rtx outer
= SET_SRC (temp_expr
);
2956 = wi::insert (rtx_mode_t (outer
, GET_MODE (SET_DEST (temp_expr
))),
2957 rtx_mode_t (inner
, GET_MODE (dest
)),
2962 subst_low_luid
= DF_INSN_LUID (i2
);
2963 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2964 i2dest
= SET_DEST (temp_expr
);
2965 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2967 /* Replace the source in I2 with the new constant and make the
2968 resulting insn the new pattern for I3. Then skip to where we
2969 validate the pattern. Everything was set up above. */
2970 SUBST (SET_SRC (temp_expr
),
2971 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2973 newpat
= PATTERN (i2
);
2975 /* The dest of I3 has been replaced with the dest of I2. */
2976 changed_i3_dest
= 1;
2977 goto validate_replacement
;
2981 /* If we have no I1 and I2 looks like:
2982 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2984 make up a dummy I1 that is
2987 (set (reg:CC X) (compare:CC Y (const_int 0)))
2989 (We can ignore any trailing CLOBBERs.)
2991 This undoes a previous combination and allows us to match a branch-and-
2994 if (!HAVE_cc0
&& i1
== 0
2995 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2996 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2998 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2999 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
3000 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
3001 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
3002 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3003 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
3005 /* We make I1 with the same INSN_UID as I2. This gives it
3006 the same DF_INSN_LUID for value tracking. Our fake I1 will
3007 never appear in the insn stream so giving it the same INSN_UID
3008 as I2 will not cause a problem. */
3010 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3011 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
3013 INSN_UID (i1
) = INSN_UID (i2
);
3015 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
3016 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
3017 SET_DEST (PATTERN (i1
)));
3018 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
3019 SUBST_LINK (LOG_LINKS (i2
),
3020 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
3023 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3024 make those two SETs separate I1 and I2 insns, and make an I0 that is
3026 if (!HAVE_cc0
&& i0
== 0
3027 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
3028 && can_split_parallel_of_n_reg_sets (i2
, 2)
3029 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3030 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
3032 /* If there is no I1, there is no I0 either. */
3035 /* We make I1 with the same INSN_UID as I2. This gives it
3036 the same DF_INSN_LUID for value tracking. Our fake I1 will
3037 never appear in the insn stream so giving it the same INSN_UID
3038 as I2 will not cause a problem. */
3040 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3041 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
3043 INSN_UID (i1
) = INSN_UID (i2
);
3045 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
3048 /* Verify that I2 and I1 are valid for combining. */
3049 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
3050 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
3052 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
3059 /* Record whether I2DEST is used in I2SRC and similarly for the other
3060 cases. Knowing this will help in register status updating below. */
3061 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3062 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3063 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3064 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3065 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3066 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3067 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3068 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3069 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3071 /* For the earlier insns, determine which of the subsequent ones they
3073 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3074 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3075 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3076 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3077 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3079 /* Ensure that I3's pattern can be the destination of combines. */
3080 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3081 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3082 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3083 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3090 /* See if any of the insns is a MULT operation. Unless one is, we will
3091 reject a combination that is, since it must be slower. Be conservative
3093 if (GET_CODE (i2src
) == MULT
3094 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3095 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3096 || (GET_CODE (PATTERN (i3
)) == SET
3097 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3100 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3101 We used to do this EXCEPT in one case: I3 has a post-inc in an
3102 output operand. However, that exception can give rise to insns like
3104 which is a famous insn on the PDP-11 where the value of r3 used as the
3105 source was model-dependent. Avoid this sort of thing. */
3108 if (!(GET_CODE (PATTERN (i3
)) == SET
3109 && REG_P (SET_SRC (PATTERN (i3
)))
3110 && MEM_P (SET_DEST (PATTERN (i3
)))
3111 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3112 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3113 /* It's not the exception. */
3118 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3119 if (REG_NOTE_KIND (link
) == REG_INC
3120 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3122 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3129 /* See if the SETs in I1 or I2 need to be kept around in the merged
3130 instruction: whenever the value set there is still needed past I3.
3131 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3133 For the SET in I1, we have two cases: if I1 and I2 independently feed
3134 into I3, the set in I1 needs to be kept around unless I1DEST dies
3135 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3136 in I1 needs to be kept around unless I1DEST dies or is set in either
3137 I2 or I3. The same considerations apply to I0. */
3139 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3142 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3143 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3148 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3149 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3150 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3151 && dead_or_set_p (i2
, i0dest
)));
3155 /* We are about to copy insns for the case where they need to be kept
3156 around. Check that they can be copied in the merged instruction. */
3158 if (targetm
.cannot_copy_insn_p
3159 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3160 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3161 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3167 /* If the set in I2 needs to be kept around, we must make a copy of
3168 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3169 PATTERN (I2), we are only substituting for the original I1DEST, not into
3170 an already-substituted copy. This also prevents making self-referential
3171 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3176 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3177 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3179 i2pat
= copy_rtx (PATTERN (i2
));
3184 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3185 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3187 i1pat
= copy_rtx (PATTERN (i1
));
3192 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3193 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3195 i0pat
= copy_rtx (PATTERN (i0
));
3200 /* Substitute in the latest insn for the regs set by the earlier ones. */
3202 maxreg
= max_reg_num ();
3206 /* Many machines that don't use CC0 have insns that can both perform an
3207 arithmetic operation and set the condition code. These operations will
3208 be represented as a PARALLEL with the first element of the vector
3209 being a COMPARE of an arithmetic operation with the constant zero.
3210 The second element of the vector will set some pseudo to the result
3211 of the same arithmetic operation. If we simplify the COMPARE, we won't
3212 match such a pattern and so will generate an extra insn. Here we test
3213 for this case, where both the comparison and the operation result are
3214 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3215 I2SRC. Later we will make the PARALLEL that contains I2. */
3217 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3218 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3219 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3220 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3223 rtx
*cc_use_loc
= NULL
;
3224 rtx_insn
*cc_use_insn
= NULL
;
3225 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3226 machine_mode compare_mode
, orig_compare_mode
;
3227 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3229 newpat
= PATTERN (i3
);
3230 newpat_dest
= SET_DEST (newpat
);
3231 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3233 if (undobuf
.other_insn
== 0
3234 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3237 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3238 compare_code
= simplify_compare_const (compare_code
,
3239 GET_MODE (i2dest
), op0
, &op1
);
3240 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3243 /* Do the rest only if op1 is const0_rtx, which may be the
3244 result of simplification. */
3245 if (op1
== const0_rtx
)
3247 /* If a single use of the CC is found, prepare to modify it
3248 when SELECT_CC_MODE returns a new CC-class mode, or when
3249 the above simplify_compare_const() returned a new comparison
3250 operator. undobuf.other_insn is assigned the CC use insn
3251 when modifying it. */
3254 #ifdef SELECT_CC_MODE
3255 machine_mode new_mode
3256 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3257 if (new_mode
!= orig_compare_mode
3258 && can_change_dest_mode (SET_DEST (newpat
),
3259 added_sets_2
, new_mode
))
3261 unsigned int regno
= REGNO (newpat_dest
);
3262 compare_mode
= new_mode
;
3263 if (regno
< FIRST_PSEUDO_REGISTER
)
3264 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3267 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3268 newpat_dest
= regno_reg_rtx
[regno
];
3272 /* Cases for modifying the CC-using comparison. */
3273 if (compare_code
!= orig_compare_code
3274 /* ??? Do we need to verify the zero rtx? */
3275 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3277 /* Replace cc_use_loc with entire new RTX. */
3279 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3280 newpat_dest
, const0_rtx
));
3281 undobuf
.other_insn
= cc_use_insn
;
3283 else if (compare_mode
!= orig_compare_mode
)
3285 /* Just replace the CC reg with a new mode. */
3286 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3287 undobuf
.other_insn
= cc_use_insn
;
3291 /* Now we modify the current newpat:
3292 First, SET_DEST(newpat) is updated if the CC mode has been
3293 altered. For targets without SELECT_CC_MODE, this should be
3295 if (compare_mode
!= orig_compare_mode
)
3296 SUBST (SET_DEST (newpat
), newpat_dest
);
3297 /* This is always done to propagate i2src into newpat. */
3298 SUBST (SET_SRC (newpat
),
3299 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3300 /* Create new version of i2pat if needed; the below PARALLEL
3301 creation needs this to work correctly. */
3302 if (! rtx_equal_p (i2src
, op0
))
3303 i2pat
= gen_rtx_SET (i2dest
, op0
);
3308 if (i2_is_used
== 0)
3310 /* It is possible that the source of I2 or I1 may be performing
3311 an unneeded operation, such as a ZERO_EXTEND of something
3312 that is known to have the high part zero. Handle that case
3313 by letting subst look at the inner insns.
3315 Another way to do this would be to have a function that tries
3316 to simplify a single insn instead of merging two or more
3317 insns. We don't do this because of the potential of infinite
3318 loops and because of the potential extra memory required.
3319 However, doing it the way we are is a bit of a kludge and
3320 doesn't catch all cases.
3322 But only do this if -fexpensive-optimizations since it slows
3323 things down and doesn't usually win.
3325 This is not done in the COMPARE case above because the
3326 unmodified I2PAT is used in the PARALLEL and so a pattern
3327 with a modified I2SRC would not match. */
3329 if (flag_expensive_optimizations
)
3331 /* Pass pc_rtx so no substitutions are done, just
3335 subst_low_luid
= DF_INSN_LUID (i1
);
3336 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3339 subst_low_luid
= DF_INSN_LUID (i2
);
3340 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3343 n_occurrences
= 0; /* `subst' counts here */
3344 subst_low_luid
= DF_INSN_LUID (i2
);
3346 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3347 copy of I2SRC each time we substitute it, in order to avoid creating
3348 self-referential RTL when we will be substituting I1SRC for I1DEST
3349 later. Likewise if I0 feeds into I2, either directly or indirectly
3350 through I1, and I0DEST is in I0SRC. */
3351 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3352 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3353 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3354 && i0dest_in_i0src
));
3357 /* Record whether I2's body now appears within I3's body. */
3358 i2_is_used
= n_occurrences
;
3361 /* If we already got a failure, don't try to do more. Otherwise, try to
3362 substitute I1 if we have it. */
3364 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3366 /* Check that an autoincrement side-effect on I1 has not been lost.
3367 This happens if I1DEST is mentioned in I2 and dies there, and
3368 has disappeared from the new pattern. */
3369 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3371 && dead_or_set_p (i2
, i1dest
)
3372 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3373 /* Before we can do this substitution, we must redo the test done
3374 above (see detailed comments there) that ensures I1DEST isn't
3375 mentioned in any SETs in NEWPAT that are field assignments. */
3376 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3384 subst_low_luid
= DF_INSN_LUID (i1
);
3386 /* If the following substitution will modify I1SRC, make a copy of it
3387 for the case where it is substituted for I1DEST in I2PAT later. */
3388 if (added_sets_2
&& i1_feeds_i2_n
)
3389 i1src_copy
= copy_rtx (i1src
);
3391 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3392 copy of I1SRC each time we substitute it, in order to avoid creating
3393 self-referential RTL when we will be substituting I0SRC for I0DEST
3395 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3396 i0_feeds_i1_n
&& i0dest_in_i0src
);
3399 /* Record whether I1's body now appears within I3's body. */
3400 i1_is_used
= n_occurrences
;
3403 /* Likewise for I0 if we have it. */
3405 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3407 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3408 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3409 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3410 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3411 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3418 /* If the following substitution will modify I0SRC, make a copy of it
3419 for the case where it is substituted for I0DEST in I1PAT later. */
3420 if (added_sets_1
&& i0_feeds_i1_n
)
3421 i0src_copy
= copy_rtx (i0src
);
3422 /* And a copy for I0DEST in I2PAT substitution. */
3423 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3424 || (i0_feeds_i2_n
)))
3425 i0src_copy2
= copy_rtx (i0src
);
3428 subst_low_luid
= DF_INSN_LUID (i0
);
3429 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3433 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3434 to count all the ways that I2SRC and I1SRC can be used. */
3435 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3436 && i2_is_used
+ added_sets_2
> 1)
3437 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3438 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3440 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3441 && (n_occurrences
+ added_sets_0
3442 + (added_sets_1
&& i0_feeds_i1_n
)
3443 + (added_sets_2
&& i0_feeds_i2_n
)
3445 /* Fail if we tried to make a new register. */
3446 || max_reg_num () != maxreg
3447 /* Fail if we couldn't do something and have a CLOBBER. */
3448 || GET_CODE (newpat
) == CLOBBER
3449 /* Fail if this new pattern is a MULT and we didn't have one before
3450 at the outer level. */
3451 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3458 /* If the actions of the earlier insns must be kept
3459 in addition to substituting them into the latest one,
3460 we must make a new PARALLEL for the latest insn
3461 to hold additional the SETs. */
3463 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3465 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3468 if (GET_CODE (newpat
) == PARALLEL
)
3470 rtvec old
= XVEC (newpat
, 0);
3471 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3472 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3473 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3474 sizeof (old
->elem
[0]) * old
->num_elem
);
3479 total_sets
= 1 + extra_sets
;
3480 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3481 XVECEXP (newpat
, 0, 0) = old
;
3485 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3491 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3493 XVECEXP (newpat
, 0, --total_sets
) = t
;
3499 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3500 i0_feeds_i1_n
&& i0dest_in_i0src
);
3501 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3502 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3504 XVECEXP (newpat
, 0, --total_sets
) = t
;
3508 validate_replacement
:
3510 /* Note which hard regs this insn has as inputs. */
3511 mark_used_regs_combine (newpat
);
3513 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3514 consider splitting this pattern, we might need these clobbers. */
3515 if (i1
&& GET_CODE (newpat
) == PARALLEL
3516 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3518 int len
= XVECLEN (newpat
, 0);
3520 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3521 for (i
= 0; i
< len
; i
++)
3522 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3525 /* We have recognized nothing yet. */
3526 insn_code_number
= -1;
3528 /* See if this is a PARALLEL of two SETs where one SET's destination is
3529 a register that is unused and this isn't marked as an instruction that
3530 might trap in an EH region. In that case, we just need the other SET.
3531 We prefer this over the PARALLEL.
3533 This can occur when simplifying a divmod insn. We *must* test for this
3534 case here because the code below that splits two independent SETs doesn't
3535 handle this case correctly when it updates the register status.
3537 It's pointless doing this if we originally had two sets, one from
3538 i3, and one from i2. Combining then splitting the parallel results
3539 in the original i2 again plus an invalid insn (which we delete).
3540 The net effect is only to move instructions around, which makes
3541 debug info less accurate. */
3543 if (!(added_sets_2
&& i1
== 0)
3544 && is_parallel_of_n_reg_sets (newpat
, 2)
3545 && asm_noperands (newpat
) < 0)
3547 rtx set0
= XVECEXP (newpat
, 0, 0);
3548 rtx set1
= XVECEXP (newpat
, 0, 1);
3549 rtx oldpat
= newpat
;
3551 if (((REG_P (SET_DEST (set1
))
3552 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3553 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3554 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3555 && insn_nothrow_p (i3
)
3556 && !side_effects_p (SET_SRC (set1
)))
3559 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3562 else if (((REG_P (SET_DEST (set0
))
3563 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3564 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3565 && find_reg_note (i3
, REG_UNUSED
,
3566 SUBREG_REG (SET_DEST (set0
)))))
3567 && insn_nothrow_p (i3
)
3568 && !side_effects_p (SET_SRC (set0
)))
3571 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3573 if (insn_code_number
>= 0)
3574 changed_i3_dest
= 1;
3577 if (insn_code_number
< 0)
3581 /* Is the result of combination a valid instruction? */
3582 if (insn_code_number
< 0)
3583 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3585 /* If we were combining three insns and the result is a simple SET
3586 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3587 insns. There are two ways to do this. It can be split using a
3588 machine-specific method (like when you have an addition of a large
3589 constant) or by combine in the function find_split_point. */
3591 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3592 && asm_noperands (newpat
) < 0)
3594 rtx parallel
, *split
;
3595 rtx_insn
*m_split_insn
;
3597 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3598 use I2DEST as a scratch register will help. In the latter case,
3599 convert I2DEST to the mode of the source of NEWPAT if we can. */
3601 m_split_insn
= combine_split_insns (newpat
, i3
);
3603 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3604 inputs of NEWPAT. */
3606 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3607 possible to try that as a scratch reg. This would require adding
3608 more code to make it work though. */
3610 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3612 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3614 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3615 (temporarily, until we are committed to this instruction
3616 combination) does not work: for example, any call to nonzero_bits
3617 on the register (from a splitter in the MD file, for example)
3618 will get the old information, which is invalid.
3620 Since nowadays we can create registers during combine just fine,
3621 we should just create a new one here, not reuse i2dest. */
3623 /* First try to split using the original register as a
3624 scratch register. */
3625 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3626 gen_rtvec (2, newpat
,
3627 gen_rtx_CLOBBER (VOIDmode
,
3629 m_split_insn
= combine_split_insns (parallel
, i3
);
3631 /* If that didn't work, try changing the mode of I2DEST if
3633 if (m_split_insn
== 0
3634 && new_mode
!= GET_MODE (i2dest
)
3635 && new_mode
!= VOIDmode
3636 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3638 machine_mode old_mode
= GET_MODE (i2dest
);
3641 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3642 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3645 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3646 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3649 parallel
= (gen_rtx_PARALLEL
3651 gen_rtvec (2, newpat
,
3652 gen_rtx_CLOBBER (VOIDmode
,
3654 m_split_insn
= combine_split_insns (parallel
, i3
);
3656 if (m_split_insn
== 0
3657 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3661 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3662 buf
= undobuf
.undos
;
3663 undobuf
.undos
= buf
->next
;
3664 buf
->next
= undobuf
.frees
;
3665 undobuf
.frees
= buf
;
3669 i2scratch
= m_split_insn
!= 0;
3672 /* If recog_for_combine has discarded clobbers, try to use them
3673 again for the split. */
3674 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3676 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3677 m_split_insn
= combine_split_insns (parallel
, i3
);
3680 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3682 rtx m_split_pat
= PATTERN (m_split_insn
);
3683 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3684 if (insn_code_number
>= 0)
3685 newpat
= m_split_pat
;
3687 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3688 && (next_nonnote_nondebug_insn (i2
) == i3
3689 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3692 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3693 newi2pat
= PATTERN (m_split_insn
);
3695 i3set
= single_set (NEXT_INSN (m_split_insn
));
3696 i2set
= single_set (m_split_insn
);
3698 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3700 /* If I2 or I3 has multiple SETs, we won't know how to track
3701 register status, so don't use these insns. If I2's destination
3702 is used between I2 and I3, we also can't use these insns. */
3704 if (i2_code_number
>= 0 && i2set
&& i3set
3705 && (next_nonnote_nondebug_insn (i2
) == i3
3706 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3707 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3709 if (insn_code_number
>= 0)
3712 /* It is possible that both insns now set the destination of I3.
3713 If so, we must show an extra use of it. */
3715 if (insn_code_number
>= 0)
3717 rtx new_i3_dest
= SET_DEST (i3set
);
3718 rtx new_i2_dest
= SET_DEST (i2set
);
3720 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3721 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3722 || GET_CODE (new_i3_dest
) == SUBREG
)
3723 new_i3_dest
= XEXP (new_i3_dest
, 0);
3725 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3726 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3727 || GET_CODE (new_i2_dest
) == SUBREG
)
3728 new_i2_dest
= XEXP (new_i2_dest
, 0);
3730 if (REG_P (new_i3_dest
)
3731 && REG_P (new_i2_dest
)
3732 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3733 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3734 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3738 /* If we can split it and use I2DEST, go ahead and see if that
3739 helps things be recognized. Verify that none of the registers
3740 are set between I2 and I3. */
3741 if (insn_code_number
< 0
3742 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3743 && (!HAVE_cc0
|| REG_P (i2dest
))
3744 /* We need I2DEST in the proper mode. If it is a hard register
3745 or the only use of a pseudo, we can change its mode.
3746 Make sure we don't change a hard register to have a mode that
3747 isn't valid for it, or change the number of registers. */
3748 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3749 || GET_MODE (*split
) == VOIDmode
3750 || can_change_dest_mode (i2dest
, added_sets_2
,
3752 && (next_nonnote_nondebug_insn (i2
) == i3
3753 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3754 /* We can't overwrite I2DEST if its value is still used by
3756 && ! reg_referenced_p (i2dest
, newpat
))
3758 rtx newdest
= i2dest
;
3759 enum rtx_code split_code
= GET_CODE (*split
);
3760 machine_mode split_mode
= GET_MODE (*split
);
3761 bool subst_done
= false;
3762 newi2pat
= NULL_RTX
;
3766 /* *SPLIT may be part of I2SRC, so make sure we have the
3767 original expression around for later debug processing.
3768 We should not need I2SRC any more in other cases. */
3769 if (MAY_HAVE_DEBUG_INSNS
)
3770 i2src
= copy_rtx (i2src
);
3774 /* Get NEWDEST as a register in the proper mode. We have already
3775 validated that we can do this. */
3776 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3778 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3779 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3782 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3783 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3787 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3788 an ASHIFT. This can occur if it was inside a PLUS and hence
3789 appeared to be a memory address. This is a kludge. */
3790 if (split_code
== MULT
3791 && CONST_INT_P (XEXP (*split
, 1))
3792 && INTVAL (XEXP (*split
, 1)) > 0
3793 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3795 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3796 XEXP (*split
, 0), GEN_INT (i
)));
3797 /* Update split_code because we may not have a multiply
3799 split_code
= GET_CODE (*split
);
3802 /* Similarly for (plus (mult FOO (const_int pow2))). */
3803 if (split_code
== PLUS
3804 && GET_CODE (XEXP (*split
, 0)) == MULT
3805 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3806 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3807 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3809 rtx nsplit
= XEXP (*split
, 0);
3810 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3811 XEXP (nsplit
, 0), GEN_INT (i
)));
3812 /* Update split_code because we may not have a multiply
3814 split_code
= GET_CODE (*split
);
3817 #ifdef INSN_SCHEDULING
3818 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3819 be written as a ZERO_EXTEND. */
3820 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3822 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3823 what it really is. */
3824 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3826 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3827 SUBREG_REG (*split
)));
3829 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3830 SUBREG_REG (*split
)));
3834 /* Attempt to split binary operators using arithmetic identities. */
3835 if (BINARY_P (SET_SRC (newpat
))
3836 && split_mode
== GET_MODE (SET_SRC (newpat
))
3837 && ! side_effects_p (SET_SRC (newpat
)))
3839 rtx setsrc
= SET_SRC (newpat
);
3840 machine_mode mode
= GET_MODE (setsrc
);
3841 enum rtx_code code
= GET_CODE (setsrc
);
3842 rtx src_op0
= XEXP (setsrc
, 0);
3843 rtx src_op1
= XEXP (setsrc
, 1);
3845 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3846 if (rtx_equal_p (src_op0
, src_op1
))
3848 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3849 SUBST (XEXP (setsrc
, 0), newdest
);
3850 SUBST (XEXP (setsrc
, 1), newdest
);
3853 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3854 else if ((code
== PLUS
|| code
== MULT
)
3855 && GET_CODE (src_op0
) == code
3856 && GET_CODE (XEXP (src_op0
, 0)) == code
3857 && (INTEGRAL_MODE_P (mode
)
3858 || (FLOAT_MODE_P (mode
)
3859 && flag_unsafe_math_optimizations
)))
3861 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3862 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3863 rtx r
= XEXP (src_op0
, 1);
3866 /* Split both "((X op Y) op X) op Y" and
3867 "((X op Y) op Y) op X" as "T op T" where T is
3869 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3870 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3872 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3873 SUBST (XEXP (setsrc
, 0), newdest
);
3874 SUBST (XEXP (setsrc
, 1), newdest
);
3877 /* Split "((X op X) op Y) op Y)" as "T op T" where
3879 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3881 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3882 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3883 SUBST (XEXP (setsrc
, 0), newdest
);
3884 SUBST (XEXP (setsrc
, 1), newdest
);
3892 newi2pat
= gen_rtx_SET (newdest
, *split
);
3893 SUBST (*split
, newdest
);
3896 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3898 /* recog_for_combine might have added CLOBBERs to newi2pat.
3899 Make sure NEWPAT does not depend on the clobbered regs. */
3900 if (GET_CODE (newi2pat
) == PARALLEL
)
3901 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3902 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3904 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3905 if (reg_overlap_mentioned_p (reg
, newpat
))
3912 /* If the split point was a MULT and we didn't have one before,
3913 don't use one now. */
3914 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3915 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3919 /* Check for a case where we loaded from memory in a narrow mode and
3920 then sign extended it, but we need both registers. In that case,
3921 we have a PARALLEL with both loads from the same memory location.
3922 We can split this into a load from memory followed by a register-register
3923 copy. This saves at least one insn, more if register allocation can
3926 We cannot do this if the destination of the first assignment is a
3927 condition code register or cc0. We eliminate this case by making sure
3928 the SET_DEST and SET_SRC have the same mode.
3930 We cannot do this if the destination of the second assignment is
3931 a register that we have already assumed is zero-extended. Similarly
3932 for a SUBREG of such a register. */
3934 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3935 && GET_CODE (newpat
) == PARALLEL
3936 && XVECLEN (newpat
, 0) == 2
3937 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3938 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3939 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3940 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3941 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3942 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3943 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3944 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3946 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3947 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3948 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3950 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3951 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3952 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3953 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3954 != GET_MODE_MASK (word_mode
))))
3955 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3956 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3958 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3959 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3960 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3961 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3962 != GET_MODE_MASK (word_mode
)))))
3963 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3964 SET_SRC (XVECEXP (newpat
, 0, 1)))
3965 && ! find_reg_note (i3
, REG_UNUSED
,
3966 SET_DEST (XVECEXP (newpat
, 0, 0))))
3970 newi2pat
= XVECEXP (newpat
, 0, 0);
3971 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3972 newpat
= XVECEXP (newpat
, 0, 1);
3973 SUBST (SET_SRC (newpat
),
3974 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3975 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3977 if (i2_code_number
>= 0)
3978 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3980 if (insn_code_number
>= 0)
3984 /* Similarly, check for a case where we have a PARALLEL of two independent
3985 SETs but we started with three insns. In this case, we can do the sets
3986 as two separate insns. This case occurs when some SET allows two
3987 other insns to combine, but the destination of that SET is still live.
3989 Also do this if we started with two insns and (at least) one of the
3990 resulting sets is a noop; this noop will be deleted later. */
3992 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3993 && GET_CODE (newpat
) == PARALLEL
3994 && XVECLEN (newpat
, 0) == 2
3995 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3996 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3997 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3998 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3999 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
4000 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
4001 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
4002 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
4003 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
4004 XVECEXP (newpat
, 0, 0))
4005 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
4006 XVECEXP (newpat
, 0, 1))
4007 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
4008 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
4010 rtx set0
= XVECEXP (newpat
, 0, 0);
4011 rtx set1
= XVECEXP (newpat
, 0, 1);
4013 /* Normally, it doesn't matter which of the two is done first,
4014 but the one that references cc0 can't be the second, and
4015 one which uses any regs/memory set in between i2 and i3 can't
4016 be first. The PARALLEL might also have been pre-existing in i3,
4017 so we need to make sure that we won't wrongly hoist a SET to i2
4018 that would conflict with a death note present in there. */
4019 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
4020 && !(REG_P (SET_DEST (set1
))
4021 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
4022 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
4023 && find_reg_note (i2
, REG_DEAD
,
4024 SUBREG_REG (SET_DEST (set1
))))
4025 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
4026 /* If I3 is a jump, ensure that set0 is a jump so that
4027 we do not create invalid RTL. */
4028 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
4034 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
4035 && !(REG_P (SET_DEST (set0
))
4036 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
4037 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
4038 && find_reg_note (i2
, REG_DEAD
,
4039 SUBREG_REG (SET_DEST (set0
))))
4040 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
4041 /* If I3 is a jump, ensure that set1 is a jump so that
4042 we do not create invalid RTL. */
4043 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4055 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4057 if (i2_code_number
>= 0)
4059 /* recog_for_combine might have added CLOBBERs to newi2pat.
4060 Make sure NEWPAT does not depend on the clobbered regs. */
4061 if (GET_CODE (newi2pat
) == PARALLEL
)
4063 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4064 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4066 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4067 if (reg_overlap_mentioned_p (reg
, newpat
))
4075 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4079 /* If it still isn't recognized, fail and change things back the way they
4081 if ((insn_code_number
< 0
4082 /* Is the result a reasonable ASM_OPERANDS? */
4083 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4089 /* If we had to change another insn, make sure it is valid also. */
4090 if (undobuf
.other_insn
)
4092 CLEAR_HARD_REG_SET (newpat_used_regs
);
4094 other_pat
= PATTERN (undobuf
.other_insn
);
4095 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4098 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4105 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4106 they are adjacent to each other or not. */
4109 rtx_insn
*p
= prev_nonnote_insn (i3
);
4110 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4111 && sets_cc0_p (newi2pat
))
4118 /* Only allow this combination if insn_rtx_costs reports that the
4119 replacement instructions are cheaper than the originals. */
4120 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4126 auto_bitmap new_regs_in_i2
;
4129 /* We need to discover situations where we introduce a use of a
4130 register into I2, where none of the existing LOG_LINKS contain
4131 a reference to it. This can happen if previously I3 referenced
4132 the reg, and there is an additional use between I2 and I3. We
4133 must remove the LOG_LINKS entry from that additional use and
4134 distribute it along with our own ones. */
4135 note_uses (&newi2pat
, record_used_regs
, (bitmap
)new_regs_in_i2
);
4136 bitmap_and_compl_into (new_regs_in_i2
, i2_regset
);
4137 bitmap_and_compl_into (new_regs_in_i2
, links_regset
);
4139 /* Here, we first look for situations where a hard register use
4140 moved, and just give up. This should happen approximately
4141 never, and it's not worth it to deal with possibilities like
4142 multi-word registers. Later, when fixing up LOG_LINKS, we
4143 deal with the case where a pseudo use moved. */
4144 if (!bitmap_empty_p (new_regs_in_i2
)
4145 && prev_nonnote_insn (i3
) != i2
4146 && bitmap_first_set_bit (new_regs_in_i2
) < FIRST_PSEUDO_REGISTER
)
4153 if (MAY_HAVE_DEBUG_INSNS
)
4157 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4158 if (undo
->kind
== UNDO_MODE
)
4160 rtx reg
= *undo
->where
.r
;
4161 machine_mode new_mode
= GET_MODE (reg
);
4162 machine_mode old_mode
= undo
->old_contents
.m
;
4164 /* Temporarily revert mode back. */
4165 adjust_reg_mode (reg
, old_mode
);
4167 if (reg
== i2dest
&& i2scratch
)
4169 /* If we used i2dest as a scratch register with a
4170 different mode, substitute it for the original
4171 i2src while its original mode is temporarily
4172 restored, and then clear i2scratch so that we don't
4173 do it again later. */
4174 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4177 /* Put back the new mode. */
4178 adjust_reg_mode (reg
, new_mode
);
4182 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4183 rtx_insn
*first
, *last
;
4188 last
= last_combined_insn
;
4193 last
= undobuf
.other_insn
;
4195 if (DF_INSN_LUID (last
)
4196 < DF_INSN_LUID (last_combined_insn
))
4197 last
= last_combined_insn
;
4200 /* We're dealing with a reg that changed mode but not
4201 meaning, so we want to turn it into a subreg for
4202 the new mode. However, because of REG sharing and
4203 because its mode had already changed, we have to do
4204 it in two steps. First, replace any debug uses of
4205 reg, with its original mode temporarily restored,
4206 with this copy we have created; then, replace the
4207 copy with the SUBREG of the original shared reg,
4208 once again changed to the new mode. */
4209 propagate_for_debug (first
, last
, reg
, tempreg
,
4211 adjust_reg_mode (reg
, new_mode
);
4212 propagate_for_debug (first
, last
, tempreg
,
4213 lowpart_subreg (old_mode
, reg
, new_mode
),
4219 /* If we will be able to accept this, we have made a
4220 change to the destination of I3. This requires us to
4221 do a few adjustments. */
4223 if (changed_i3_dest
)
4225 PATTERN (i3
) = newpat
;
4226 adjust_for_new_dest (i3
);
4229 /* We now know that we can do this combination. Merge the insns and
4230 update the status of registers and LOG_LINKS. */
4232 if (undobuf
.other_insn
)
4236 PATTERN (undobuf
.other_insn
) = other_pat
;
4238 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4239 ensure that they are still valid. Then add any non-duplicate
4240 notes added by recog_for_combine. */
4241 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4243 next
= XEXP (note
, 1);
4245 if ((REG_NOTE_KIND (note
) == REG_DEAD
4246 && !reg_referenced_p (XEXP (note
, 0),
4247 PATTERN (undobuf
.other_insn
)))
4248 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4249 && !reg_set_p (XEXP (note
, 0),
4250 PATTERN (undobuf
.other_insn
)))
4251 /* Simply drop equal note since it may be no longer valid
4252 for other_insn. It may be possible to record that CC
4253 register is changed and only discard those notes, but
4254 in practice it's unnecessary complication and doesn't
4255 give any meaningful improvement.
4258 || REG_NOTE_KIND (note
) == REG_EQUAL
4259 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4260 remove_note (undobuf
.other_insn
, note
);
4263 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4264 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4271 struct insn_link
*link
;
4274 /* I3 now uses what used to be its destination and which is now
4275 I2's destination. This requires us to do a few adjustments. */
4276 PATTERN (i3
) = newpat
;
4277 adjust_for_new_dest (i3
);
4279 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4282 However, some later insn might be using I2's dest and have
4283 a LOG_LINK pointing at I3. We must remove this link.
4284 The simplest way to remove the link is to point it at I1,
4285 which we know will be a NOTE. */
4287 /* newi2pat is usually a SET here; however, recog_for_combine might
4288 have added some clobbers. */
4289 if (GET_CODE (newi2pat
) == PARALLEL
)
4290 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4292 ni2dest
= SET_DEST (newi2pat
);
4294 for (insn
= NEXT_INSN (i3
);
4295 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4296 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4297 insn
= NEXT_INSN (insn
))
4299 if (NONDEBUG_INSN_P (insn
)
4300 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4302 FOR_EACH_LOG_LINK (link
, insn
)
4303 if (link
->insn
== i3
)
4312 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4313 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4316 /* Compute which registers we expect to eliminate. newi2pat may be setting
4317 either i3dest or i2dest, so we must check it. */
4318 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4319 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4322 /* For i1, we need to compute both local elimination and global
4323 elimination information with respect to newi2pat because i1dest
4324 may be the same as i3dest, in which case newi2pat may be setting
4325 i1dest. Global information is used when distributing REG_DEAD
4326 note for i2 and i3, in which case it does matter if newi2pat sets
4329 Local information is used when distributing REG_DEAD note for i1,
4330 in which case it doesn't matter if newi2pat sets i1dest or not.
4331 See PR62151, if we have four insns combination:
4333 i1: r1 <- i1src (using r0)
4335 i2: r0 <- i2src (using r1)
4336 i3: r3 <- i3src (using r0)
4338 From i1's point of view, r0 is eliminated, no matter if it is set
4339 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4340 should be discarded.
4342 Note local information only affects cases in forms like "I1->I2->I3",
4343 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4344 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4346 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4349 rtx elim_i1
= (local_elim_i1
== 0
4350 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4352 /* Same case as i1. */
4353 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4355 rtx elim_i0
= (local_elim_i0
== 0
4356 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4359 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4361 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4362 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4364 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4366 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4368 /* Ensure that we do not have something that should not be shared but
4369 occurs multiple times in the new insns. Check this by first
4370 resetting all the `used' flags and then copying anything is shared. */
4372 reset_used_flags (i3notes
);
4373 reset_used_flags (i2notes
);
4374 reset_used_flags (i1notes
);
4375 reset_used_flags (i0notes
);
4376 reset_used_flags (newpat
);
4377 reset_used_flags (newi2pat
);
4378 if (undobuf
.other_insn
)
4379 reset_used_flags (PATTERN (undobuf
.other_insn
));
4381 i3notes
= copy_rtx_if_shared (i3notes
);
4382 i2notes
= copy_rtx_if_shared (i2notes
);
4383 i1notes
= copy_rtx_if_shared (i1notes
);
4384 i0notes
= copy_rtx_if_shared (i0notes
);
4385 newpat
= copy_rtx_if_shared (newpat
);
4386 newi2pat
= copy_rtx_if_shared (newi2pat
);
4387 if (undobuf
.other_insn
)
4388 reset_used_flags (PATTERN (undobuf
.other_insn
));
4390 INSN_CODE (i3
) = insn_code_number
;
4391 PATTERN (i3
) = newpat
;
4393 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4395 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4396 link
= XEXP (link
, 1))
4400 /* I2SRC must still be meaningful at this point. Some
4401 splitting operations can invalidate I2SRC, but those
4402 operations do not apply to calls. */
4404 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4408 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4411 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4416 if (undobuf
.other_insn
)
4417 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4419 /* We had one special case above where I2 had more than one set and
4420 we replaced a destination of one of those sets with the destination
4421 of I3. In that case, we have to update LOG_LINKS of insns later
4422 in this basic block. Note that this (expensive) case is rare.
4424 Also, in this case, we must pretend that all REG_NOTEs for I2
4425 actually came from I3, so that REG_UNUSED notes from I2 will be
4426 properly handled. */
4428 if (i3_subst_into_i2
)
4430 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4431 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4432 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4433 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4434 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4435 && ! find_reg_note (i2
, REG_UNUSED
,
4436 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4437 for (temp_insn
= NEXT_INSN (i2
);
4439 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4440 || BB_HEAD (this_basic_block
) != temp_insn
);
4441 temp_insn
= NEXT_INSN (temp_insn
))
4442 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4443 FOR_EACH_LOG_LINK (link
, temp_insn
)
4444 if (link
->insn
== i2
)
4450 while (XEXP (link
, 1))
4451 link
= XEXP (link
, 1);
4452 XEXP (link
, 1) = i2notes
;
4459 LOG_LINKS (i3
) = NULL
;
4461 LOG_LINKS (i2
) = NULL
;
4466 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4467 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4469 INSN_CODE (i2
) = i2_code_number
;
4470 PATTERN (i2
) = newi2pat
;
4474 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4475 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4477 SET_INSN_DELETED (i2
);
4482 LOG_LINKS (i1
) = NULL
;
4484 if (MAY_HAVE_DEBUG_INSNS
)
4485 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4487 SET_INSN_DELETED (i1
);
4492 LOG_LINKS (i0
) = NULL
;
4494 if (MAY_HAVE_DEBUG_INSNS
)
4495 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4497 SET_INSN_DELETED (i0
);
4500 /* Get death notes for everything that is now used in either I3 or
4501 I2 and used to die in a previous insn. If we built two new
4502 patterns, move from I1 to I2 then I2 to I3 so that we get the
4503 proper movement on registers that I2 modifies. */
4506 from_luid
= DF_INSN_LUID (i0
);
4508 from_luid
= DF_INSN_LUID (i1
);
4510 from_luid
= DF_INSN_LUID (i2
);
4512 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4513 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4515 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4517 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4518 elim_i2
, elim_i1
, elim_i0
);
4520 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4521 elim_i2
, elim_i1
, elim_i0
);
4523 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4524 elim_i2
, local_elim_i1
, local_elim_i0
);
4526 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4527 elim_i2
, elim_i1
, local_elim_i0
);
4529 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4530 elim_i2
, elim_i1
, elim_i0
);
4532 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4533 know these are REG_UNUSED and want them to go to the desired insn,
4534 so we always pass it as i3. */
4536 if (newi2pat
&& new_i2_notes
)
4537 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4541 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4544 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4545 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4546 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4547 in that case, it might delete I2. Similarly for I2 and I1.
4548 Show an additional death due to the REG_DEAD note we make here. If
4549 we discard it in distribute_notes, we will decrement it again. */
4553 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4554 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4555 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4558 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4559 elim_i2
, elim_i1
, elim_i0
);
4562 if (i2dest_in_i2src
)
4564 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4565 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4566 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4567 NULL_RTX
, NULL_RTX
);
4569 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4570 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4573 if (i1dest_in_i1src
)
4575 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4576 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4577 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4578 NULL_RTX
, NULL_RTX
);
4580 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4581 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4584 if (i0dest_in_i0src
)
4586 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4587 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4588 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4589 NULL_RTX
, NULL_RTX
);
4591 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4592 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4597 bitmap_iterator iter
;
4600 /* See comments above where we calculate the bitmap. */
4601 EXECUTE_IF_SET_IN_BITMAP ((bitmap
)new_regs_in_i2
,
4602 LAST_VIRTUAL_REGISTER
, i
, iter
)
4604 rtx reg
= regno_reg_rtx
[i
];
4606 for (other
= NEXT_INSN (i2
); other
!= i3
; other
= NEXT_INSN (other
))
4607 if (NONDEBUG_INSN_P (other
)
4608 && (reg_overlap_mentioned_p (reg
, PATTERN (other
))
4609 || (CALL_P (other
) && find_reg_fusage (other
, USE
, reg
))))
4613 "found extra use of reg %d at insn %d\n", i
,
4616 for (plink
= &LOG_LINKS (other
);
4618 plink
= &(*plink
)->next
)
4620 insn_link
*link
= *plink
;
4621 if (link
->regno
== i
)
4623 *plink
= link
->next
;
4624 link
->next
= i3links
;
4634 distribute_links (i3links
);
4635 distribute_links (i2links
);
4636 distribute_links (i1links
);
4637 distribute_links (i0links
);
4641 struct insn_link
*link
;
4642 rtx_insn
*i2_insn
= 0;
4643 rtx i2_val
= 0, set
;
4645 /* The insn that used to set this register doesn't exist, and
4646 this life of the register may not exist either. See if one of
4647 I3's links points to an insn that sets I2DEST. If it does,
4648 that is now the last known value for I2DEST. If we don't update
4649 this and I2 set the register to a value that depended on its old
4650 contents, we will get confused. If this insn is used, thing
4651 will be set correctly in combine_instructions. */
4652 FOR_EACH_LOG_LINK (link
, i3
)
4653 if ((set
= single_set (link
->insn
)) != 0
4654 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4655 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4657 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4659 /* If the reg formerly set in I2 died only once and that was in I3,
4660 zero its use count so it won't make `reload' do any work. */
4662 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4663 && ! i2dest_in_i2src
4664 && REGNO (i2dest
) < reg_n_sets_max
)
4665 INC_REG_N_SETS (REGNO (i2dest
), -1);
4668 if (i1
&& REG_P (i1dest
))
4670 struct insn_link
*link
;
4671 rtx_insn
*i1_insn
= 0;
4672 rtx i1_val
= 0, set
;
4674 FOR_EACH_LOG_LINK (link
, i3
)
4675 if ((set
= single_set (link
->insn
)) != 0
4676 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4677 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4679 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4682 && ! i1dest_in_i1src
4683 && REGNO (i1dest
) < reg_n_sets_max
)
4684 INC_REG_N_SETS (REGNO (i1dest
), -1);
4687 if (i0
&& REG_P (i0dest
))
4689 struct insn_link
*link
;
4690 rtx_insn
*i0_insn
= 0;
4691 rtx i0_val
= 0, set
;
4693 FOR_EACH_LOG_LINK (link
, i3
)
4694 if ((set
= single_set (link
->insn
)) != 0
4695 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4696 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4698 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4701 && ! i0dest_in_i0src
4702 && REGNO (i0dest
) < reg_n_sets_max
)
4703 INC_REG_N_SETS (REGNO (i0dest
), -1);
4706 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4707 been made to this insn. The order is important, because newi2pat
4708 can affect nonzero_bits of newpat. */
4710 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4711 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4714 if (undobuf
.other_insn
!= NULL_RTX
)
4718 fprintf (dump_file
, "modifying other_insn ");
4719 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4721 df_insn_rescan (undobuf
.other_insn
);
4724 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4728 fprintf (dump_file
, "modifying insn i0 ");
4729 dump_insn_slim (dump_file
, i0
);
4731 df_insn_rescan (i0
);
4734 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4738 fprintf (dump_file
, "modifying insn i1 ");
4739 dump_insn_slim (dump_file
, i1
);
4741 df_insn_rescan (i1
);
4744 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4748 fprintf (dump_file
, "modifying insn i2 ");
4749 dump_insn_slim (dump_file
, i2
);
4751 df_insn_rescan (i2
);
4754 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4758 fprintf (dump_file
, "modifying insn i3 ");
4759 dump_insn_slim (dump_file
, i3
);
4761 df_insn_rescan (i3
);
4764 /* Set new_direct_jump_p if a new return or simple jump instruction
4765 has been created. Adjust the CFG accordingly. */
4766 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4768 *new_direct_jump_p
= 1;
4769 mark_jump_label (PATTERN (i3
), i3
, 0);
4770 update_cfg_for_uncondjump (i3
);
4773 if (undobuf
.other_insn
!= NULL_RTX
4774 && (returnjump_p (undobuf
.other_insn
)
4775 || any_uncondjump_p (undobuf
.other_insn
)))
4777 *new_direct_jump_p
= 1;
4778 update_cfg_for_uncondjump (undobuf
.other_insn
);
4781 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4782 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4784 basic_block bb
= BLOCK_FOR_INSN (i3
);
4786 remove_edge (split_block (bb
, i3
));
4787 emit_barrier_after_bb (bb
);
4788 *new_direct_jump_p
= 1;
4791 if (undobuf
.other_insn
4792 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4793 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4795 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4797 remove_edge (split_block (bb
, undobuf
.other_insn
));
4798 emit_barrier_after_bb (bb
);
4799 *new_direct_jump_p
= 1;
4802 /* A noop might also need cleaning up of CFG, if it comes from the
4803 simplification of a jump. */
4805 && GET_CODE (newpat
) == SET
4806 && SET_SRC (newpat
) == pc_rtx
4807 && SET_DEST (newpat
) == pc_rtx
)
4809 *new_direct_jump_p
= 1;
4810 update_cfg_for_uncondjump (i3
);
4813 if (undobuf
.other_insn
!= NULL_RTX
4814 && JUMP_P (undobuf
.other_insn
)
4815 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4816 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4817 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4819 *new_direct_jump_p
= 1;
4820 update_cfg_for_uncondjump (undobuf
.other_insn
);
4823 combine_successes
++;
4826 if (added_links_insn
4827 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4828 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4829 return added_links_insn
;
4831 return newi2pat
? i2
: i3
;
4834 /* Get a marker for undoing to the current state. */
4837 get_undo_marker (void)
4839 return undobuf
.undos
;
4842 /* Undo the modifications up to the marker. */
4845 undo_to_marker (void *marker
)
4847 struct undo
*undo
, *next
;
4849 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4857 *undo
->where
.r
= undo
->old_contents
.r
;
4860 *undo
->where
.i
= undo
->old_contents
.i
;
4863 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4866 *undo
->where
.l
= undo
->old_contents
.l
;
4872 undo
->next
= undobuf
.frees
;
4873 undobuf
.frees
= undo
;
4876 undobuf
.undos
= (struct undo
*) marker
;
4879 /* Undo all the modifications recorded in undobuf. */
4887 /* We've committed to accepting the changes we made. Move all
4888 of the undos to the free list. */
4893 struct undo
*undo
, *next
;
4895 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4898 undo
->next
= undobuf
.frees
;
4899 undobuf
.frees
= undo
;
4904 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4905 where we have an arithmetic expression and return that point. LOC will
4908 try_combine will call this function to see if an insn can be split into
4912 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4915 enum rtx_code code
= GET_CODE (x
);
4917 unsigned HOST_WIDE_INT len
= 0;
4918 HOST_WIDE_INT pos
= 0;
4920 rtx inner
= NULL_RTX
;
4922 /* First special-case some codes. */
4926 #ifdef INSN_SCHEDULING
4927 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4929 if (MEM_P (SUBREG_REG (x
)))
4932 return find_split_point (&SUBREG_REG (x
), insn
, false);
4935 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4936 using LO_SUM and HIGH. */
4937 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4938 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4940 machine_mode address_mode
= get_address_mode (x
);
4943 gen_rtx_LO_SUM (address_mode
,
4944 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4946 return &XEXP (XEXP (x
, 0), 0);
4949 /* If we have a PLUS whose second operand is a constant and the
4950 address is not valid, perhaps will can split it up using
4951 the machine-specific way to split large constants. We use
4952 the first pseudo-reg (one of the virtual regs) as a placeholder;
4953 it will not remain in the result. */
4954 if (GET_CODE (XEXP (x
, 0)) == PLUS
4955 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4956 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4957 MEM_ADDR_SPACE (x
)))
4959 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4960 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4963 /* This should have produced two insns, each of which sets our
4964 placeholder. If the source of the second is a valid address,
4965 we can make put both sources together and make a split point
4969 && NEXT_INSN (seq
) != NULL_RTX
4970 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4971 && NONJUMP_INSN_P (seq
)
4972 && GET_CODE (PATTERN (seq
)) == SET
4973 && SET_DEST (PATTERN (seq
)) == reg
4974 && ! reg_mentioned_p (reg
,
4975 SET_SRC (PATTERN (seq
)))
4976 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4977 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4978 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4979 && memory_address_addr_space_p
4980 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4981 MEM_ADDR_SPACE (x
)))
4983 rtx src1
= SET_SRC (PATTERN (seq
));
4984 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4986 /* Replace the placeholder in SRC2 with SRC1. If we can
4987 find where in SRC2 it was placed, that can become our
4988 split point and we can replace this address with SRC2.
4989 Just try two obvious places. */
4991 src2
= replace_rtx (src2
, reg
, src1
);
4993 if (XEXP (src2
, 0) == src1
)
4994 split
= &XEXP (src2
, 0);
4995 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4996 && XEXP (XEXP (src2
, 0), 0) == src1
)
4997 split
= &XEXP (XEXP (src2
, 0), 0);
5001 SUBST (XEXP (x
, 0), src2
);
5006 /* If that didn't work, perhaps the first operand is complex and
5007 needs to be computed separately, so make a split point there.
5008 This will occur on machines that just support REG + CONST
5009 and have a constant moved through some previous computation. */
5011 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
5012 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
5013 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
5014 return &XEXP (XEXP (x
, 0), 0);
5017 /* If we have a PLUS whose first operand is complex, try computing it
5018 separately by making a split there. */
5019 if (GET_CODE (XEXP (x
, 0)) == PLUS
5020 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
5022 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
5023 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
5024 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
5025 return &XEXP (XEXP (x
, 0), 0);
5029 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
5030 ZERO_EXTRACT, the most likely reason why this doesn't match is that
5031 we need to put the operand into a register. So split at that
5034 if (SET_DEST (x
) == cc0_rtx
5035 && GET_CODE (SET_SRC (x
)) != COMPARE
5036 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
5037 && !OBJECT_P (SET_SRC (x
))
5038 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
5039 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
5040 return &SET_SRC (x
);
5042 /* See if we can split SET_SRC as it stands. */
5043 split
= find_split_point (&SET_SRC (x
), insn
, true);
5044 if (split
&& split
!= &SET_SRC (x
))
5047 /* See if we can split SET_DEST as it stands. */
5048 split
= find_split_point (&SET_DEST (x
), insn
, false);
5049 if (split
&& split
!= &SET_DEST (x
))
5052 /* See if this is a bitfield assignment with everything constant. If
5053 so, this is an IOR of an AND, so split it into that. */
5054 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5055 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
5056 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
5057 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
5058 && CONST_INT_P (SET_SRC (x
))
5059 && ((INTVAL (XEXP (SET_DEST (x
), 1))
5060 + INTVAL (XEXP (SET_DEST (x
), 2)))
5061 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
5062 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
5064 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
5065 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
5066 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
5067 rtx dest
= XEXP (SET_DEST (x
), 0);
5068 machine_mode mode
= GET_MODE (dest
);
5069 unsigned HOST_WIDE_INT mask
5070 = (HOST_WIDE_INT_1U
<< len
) - 1;
5073 if (BITS_BIG_ENDIAN
)
5074 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
5076 or_mask
= gen_int_mode (src
<< pos
, mode
);
5079 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
5082 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
5084 simplify_gen_binary (IOR
, mode
,
5085 simplify_gen_binary (AND
, mode
,
5090 SUBST (SET_DEST (x
), dest
);
5092 split
= find_split_point (&SET_SRC (x
), insn
, true);
5093 if (split
&& split
!= &SET_SRC (x
))
5097 /* Otherwise, see if this is an operation that we can split into two.
5098 If so, try to split that. */
5099 code
= GET_CODE (SET_SRC (x
));
5104 /* If we are AND'ing with a large constant that is only a single
5105 bit and the result is only being used in a context where we
5106 need to know if it is zero or nonzero, replace it with a bit
5107 extraction. This will avoid the large constant, which might
5108 have taken more than one insn to make. If the constant were
5109 not a valid argument to the AND but took only one insn to make,
5110 this is no worse, but if it took more than one insn, it will
5113 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5114 && REG_P (XEXP (SET_SRC (x
), 0))
5115 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
5116 && REG_P (SET_DEST (x
))
5117 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
5118 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
5119 && XEXP (*split
, 0) == SET_DEST (x
)
5120 && XEXP (*split
, 1) == const0_rtx
)
5122 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
5123 XEXP (SET_SRC (x
), 0),
5124 pos
, NULL_RTX
, 1, 1, 0, 0);
5125 if (extraction
!= 0)
5127 SUBST (SET_SRC (x
), extraction
);
5128 return find_split_point (loc
, insn
, false);
5134 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5135 is known to be on, this can be converted into a NEG of a shift. */
5136 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5137 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5138 && 1 <= (pos
= exact_log2
5139 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5140 GET_MODE (XEXP (SET_SRC (x
), 0))))))
5142 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5146 gen_rtx_LSHIFTRT (mode
,
5147 XEXP (SET_SRC (x
), 0),
5150 split
= find_split_point (&SET_SRC (x
), insn
, true);
5151 if (split
&& split
!= &SET_SRC (x
))
5157 inner
= XEXP (SET_SRC (x
), 0);
5159 /* We can't optimize if either mode is a partial integer
5160 mode as we don't know how many bits are significant
5162 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
5163 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5167 len
= GET_MODE_PRECISION (GET_MODE (inner
));
5173 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5174 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5176 inner
= XEXP (SET_SRC (x
), 0);
5177 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5178 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5180 if (BITS_BIG_ENDIAN
)
5181 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
5182 unsignedp
= (code
== ZERO_EXTRACT
);
5191 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5193 machine_mode mode
= GET_MODE (SET_SRC (x
));
5195 /* For unsigned, we have a choice of a shift followed by an
5196 AND or two shifts. Use two shifts for field sizes where the
5197 constant might be too large. We assume here that we can
5198 always at least get 8-bit constants in an AND insn, which is
5199 true for every current RISC. */
5201 if (unsignedp
&& len
<= 8)
5203 unsigned HOST_WIDE_INT mask
5204 = (HOST_WIDE_INT_1U
<< len
) - 1;
5208 (mode
, gen_lowpart (mode
, inner
),
5210 gen_int_mode (mask
, mode
)));
5212 split
= find_split_point (&SET_SRC (x
), insn
, true);
5213 if (split
&& split
!= &SET_SRC (x
))
5220 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5221 gen_rtx_ASHIFT (mode
,
5222 gen_lowpart (mode
, inner
),
5223 GEN_INT (GET_MODE_PRECISION (mode
)
5225 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5227 split
= find_split_point (&SET_SRC (x
), insn
, true);
5228 if (split
&& split
!= &SET_SRC (x
))
5233 /* See if this is a simple operation with a constant as the second
5234 operand. It might be that this constant is out of range and hence
5235 could be used as a split point. */
5236 if (BINARY_P (SET_SRC (x
))
5237 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5238 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5239 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5240 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5241 return &XEXP (SET_SRC (x
), 1);
5243 /* Finally, see if this is a simple operation with its first operand
5244 not in a register. The operation might require this operand in a
5245 register, so return it as a split point. We can always do this
5246 because if the first operand were another operation, we would have
5247 already found it as a split point. */
5248 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5249 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5250 return &XEXP (SET_SRC (x
), 0);
5256 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5257 it is better to write this as (not (ior A B)) so we can split it.
5258 Similarly for IOR. */
5259 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5262 gen_rtx_NOT (GET_MODE (x
),
5263 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5265 XEXP (XEXP (x
, 0), 0),
5266 XEXP (XEXP (x
, 1), 0))));
5267 return find_split_point (loc
, insn
, set_src
);
5270 /* Many RISC machines have a large set of logical insns. If the
5271 second operand is a NOT, put it first so we will try to split the
5272 other operand first. */
5273 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5275 rtx tem
= XEXP (x
, 0);
5276 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5277 SUBST (XEXP (x
, 1), tem
);
5283 /* Canonicalization can produce (minus A (mult B C)), where C is a
5284 constant. It may be better to try splitting (plus (mult B -C) A)
5285 instead if this isn't a multiply by a power of two. */
5286 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5287 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5288 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5290 machine_mode mode
= GET_MODE (x
);
5291 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5292 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5293 SUBST (*loc
, gen_rtx_PLUS (mode
,
5295 XEXP (XEXP (x
, 1), 0),
5296 gen_int_mode (other_int
,
5299 return find_split_point (loc
, insn
, set_src
);
5302 /* Split at a multiply-accumulate instruction. However if this is
5303 the SET_SRC, we likely do not have such an instruction and it's
5304 worthless to try this split. */
5306 && (GET_CODE (XEXP (x
, 0)) == MULT
5307 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5308 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5315 /* Otherwise, select our actions depending on our rtx class. */
5316 switch (GET_RTX_CLASS (code
))
5318 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5320 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5325 case RTX_COMM_ARITH
:
5327 case RTX_COMM_COMPARE
:
5328 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5333 /* Some machines have (and (shift ...) ...) insns. If X is not
5334 an AND, but XEXP (X, 0) is, use it as our split point. */
5335 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5336 return &XEXP (x
, 0);
5338 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5344 /* Otherwise, we don't have a split point. */
5349 /* Throughout X, replace FROM with TO, and return the result.
5350 The result is TO if X is FROM;
5351 otherwise the result is X, but its contents may have been modified.
5352 If they were modified, a record was made in undobuf so that
5353 undo_all will (among other things) return X to its original state.
5355 If the number of changes necessary is too much to record to undo,
5356 the excess changes are not made, so the result is invalid.
5357 The changes already made can still be undone.
5358 undobuf.num_undo is incremented for such changes, so by testing that
5359 the caller can tell whether the result is valid.
5361 `n_occurrences' is incremented each time FROM is replaced.
5363 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5365 IN_COND is nonzero if we are at the top level of a condition.
5367 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5368 by copying if `n_occurrences' is nonzero. */
5371 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5373 enum rtx_code code
= GET_CODE (x
);
5374 machine_mode op0_mode
= VOIDmode
;
5379 /* Two expressions are equal if they are identical copies of a shared
5380 RTX or if they are both registers with the same register number
5383 #define COMBINE_RTX_EQUAL_P(X,Y) \
5385 || (REG_P (X) && REG_P (Y) \
5386 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5388 /* Do not substitute into clobbers of regs -- this will never result in
5390 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5393 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5396 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5399 /* If X and FROM are the same register but different modes, they
5400 will not have been seen as equal above. However, the log links code
5401 will make a LOG_LINKS entry for that case. If we do nothing, we
5402 will try to rerecognize our original insn and, when it succeeds,
5403 we will delete the feeding insn, which is incorrect.
5405 So force this insn not to match in this (rare) case. */
5406 if (! in_dest
&& code
== REG
&& REG_P (from
)
5407 && reg_overlap_mentioned_p (x
, from
))
5408 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5410 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5411 of which may contain things that can be combined. */
5412 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5415 /* It is possible to have a subexpression appear twice in the insn.
5416 Suppose that FROM is a register that appears within TO.
5417 Then, after that subexpression has been scanned once by `subst',
5418 the second time it is scanned, TO may be found. If we were
5419 to scan TO here, we would find FROM within it and create a
5420 self-referent rtl structure which is completely wrong. */
5421 if (COMBINE_RTX_EQUAL_P (x
, to
))
5424 /* Parallel asm_operands need special attention because all of the
5425 inputs are shared across the arms. Furthermore, unsharing the
5426 rtl results in recognition failures. Failure to handle this case
5427 specially can result in circular rtl.
5429 Solve this by doing a normal pass across the first entry of the
5430 parallel, and only processing the SET_DESTs of the subsequent
5433 if (code
== PARALLEL
5434 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5435 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5437 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5439 /* If this substitution failed, this whole thing fails. */
5440 if (GET_CODE (new_rtx
) == CLOBBER
5441 && XEXP (new_rtx
, 0) == const0_rtx
)
5444 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5446 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5448 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5451 && GET_CODE (dest
) != CC0
5452 && GET_CODE (dest
) != PC
)
5454 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5456 /* If this substitution failed, this whole thing fails. */
5457 if (GET_CODE (new_rtx
) == CLOBBER
5458 && XEXP (new_rtx
, 0) == const0_rtx
)
5461 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5467 len
= GET_RTX_LENGTH (code
);
5468 fmt
= GET_RTX_FORMAT (code
);
5470 /* We don't need to process a SET_DEST that is a register, CC0,
5471 or PC, so set up to skip this common case. All other cases
5472 where we want to suppress replacing something inside a
5473 SET_SRC are handled via the IN_DEST operand. */
5475 && (REG_P (SET_DEST (x
))
5476 || GET_CODE (SET_DEST (x
)) == CC0
5477 || GET_CODE (SET_DEST (x
)) == PC
))
5480 /* Trying to simplify the operands of a widening MULT is not likely
5481 to create RTL matching a machine insn. */
5483 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5484 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5485 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5486 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5487 && REG_P (XEXP (XEXP (x
, 0), 0))
5488 && REG_P (XEXP (XEXP (x
, 1), 0))
5493 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5496 op0_mode
= GET_MODE (XEXP (x
, 0));
5498 for (i
= 0; i
< len
; i
++)
5503 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5505 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5507 new_rtx
= (unique_copy
&& n_occurrences
5508 ? copy_rtx (to
) : to
);
5513 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5516 /* If this substitution failed, this whole thing
5518 if (GET_CODE (new_rtx
) == CLOBBER
5519 && XEXP (new_rtx
, 0) == const0_rtx
)
5523 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5526 else if (fmt
[i
] == 'e')
5528 /* If this is a register being set, ignore it. */
5529 new_rtx
= XEXP (x
, i
);
5532 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5534 || code
== STRICT_LOW_PART
))
5537 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5539 /* In general, don't install a subreg involving two
5540 modes not tieable. It can worsen register
5541 allocation, and can even make invalid reload
5542 insns, since the reg inside may need to be copied
5543 from in the outside mode, and that may be invalid
5544 if it is an fp reg copied in integer mode.
5546 We allow two exceptions to this: It is valid if
5547 it is inside another SUBREG and the mode of that
5548 SUBREG and the mode of the inside of TO is
5549 tieable and it is valid if X is a SET that copies
5552 if (GET_CODE (to
) == SUBREG
5553 && ! MODES_TIEABLE_P (GET_MODE (to
),
5554 GET_MODE (SUBREG_REG (to
)))
5555 && ! (code
== SUBREG
5556 && MODES_TIEABLE_P (GET_MODE (x
),
5557 GET_MODE (SUBREG_REG (to
))))
5561 && XEXP (x
, 0) == cc0_rtx
))))
5562 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5566 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5567 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5570 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5572 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5576 /* If we are in a SET_DEST, suppress most cases unless we
5577 have gone inside a MEM, in which case we want to
5578 simplify the address. We assume here that things that
5579 are actually part of the destination have their inner
5580 parts in the first expression. This is true for SUBREG,
5581 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5582 things aside from REG and MEM that should appear in a
5584 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5586 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5587 || code
== ZERO_EXTRACT
))
5590 code
== IF_THEN_ELSE
&& i
== 0,
5593 /* If we found that we will have to reject this combination,
5594 indicate that by returning the CLOBBER ourselves, rather than
5595 an expression containing it. This will speed things up as
5596 well as prevent accidents where two CLOBBERs are considered
5597 to be equal, thus producing an incorrect simplification. */
5599 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5602 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5604 machine_mode mode
= GET_MODE (x
);
5606 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5607 GET_MODE (SUBREG_REG (x
)),
5610 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5612 else if (CONST_SCALAR_INT_P (new_rtx
)
5613 && GET_CODE (x
) == ZERO_EXTEND
)
5615 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5616 new_rtx
, GET_MODE (XEXP (x
, 0)));
5620 SUBST (XEXP (x
, i
), new_rtx
);
5625 /* Check if we are loading something from the constant pool via float
5626 extension; in this case we would undo compress_float_constant
5627 optimization and degenerate constant load to an immediate value. */
5628 if (GET_CODE (x
) == FLOAT_EXTEND
5629 && MEM_P (XEXP (x
, 0))
5630 && MEM_READONLY_P (XEXP (x
, 0)))
5632 rtx tmp
= avoid_constant_pool_reference (x
);
5637 /* Try to simplify X. If the simplification changed the code, it is likely
5638 that further simplification will help, so loop, but limit the number
5639 of repetitions that will be performed. */
5641 for (i
= 0; i
< 4; i
++)
5643 /* If X is sufficiently simple, don't bother trying to do anything
5645 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5646 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5648 if (GET_CODE (x
) == code
)
5651 code
= GET_CODE (x
);
5653 /* We no longer know the original mode of operand 0 since we
5654 have changed the form of X) */
5655 op0_mode
= VOIDmode
;
5661 /* If X is a commutative operation whose operands are not in the canonical
5662 order, use substitutions to swap them. */
5665 maybe_swap_commutative_operands (rtx x
)
5667 if (COMMUTATIVE_ARITH_P (x
)
5668 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5670 rtx temp
= XEXP (x
, 0);
5671 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5672 SUBST (XEXP (x
, 1), temp
);
5676 /* Simplify X, a piece of RTL. We just operate on the expression at the
5677 outer level; call `subst' to simplify recursively. Return the new
5680 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5681 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5685 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5688 enum rtx_code code
= GET_CODE (x
);
5689 machine_mode mode
= GET_MODE (x
);
5693 /* If this is a commutative operation, put a constant last and a complex
5694 expression first. We don't need to do this for comparisons here. */
5695 maybe_swap_commutative_operands (x
);
5697 /* Try to fold this expression in case we have constants that weren't
5700 switch (GET_RTX_CLASS (code
))
5703 if (op0_mode
== VOIDmode
)
5704 op0_mode
= GET_MODE (XEXP (x
, 0));
5705 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5708 case RTX_COMM_COMPARE
:
5710 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5711 if (cmp_mode
== VOIDmode
)
5713 cmp_mode
= GET_MODE (XEXP (x
, 1));
5714 if (cmp_mode
== VOIDmode
)
5715 cmp_mode
= op0_mode
;
5717 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5718 XEXP (x
, 0), XEXP (x
, 1));
5721 case RTX_COMM_ARITH
:
5723 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5725 case RTX_BITFIELD_OPS
:
5727 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5728 XEXP (x
, 1), XEXP (x
, 2));
5737 code
= GET_CODE (temp
);
5738 op0_mode
= VOIDmode
;
5739 mode
= GET_MODE (temp
);
5742 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5743 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5744 things. Check for cases where both arms are testing the same
5747 Don't do anything if all operands are very simple. */
5750 && ((!OBJECT_P (XEXP (x
, 0))
5751 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5752 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5753 || (!OBJECT_P (XEXP (x
, 1))
5754 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5755 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5757 && (!OBJECT_P (XEXP (x
, 0))
5758 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5759 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5761 rtx cond
, true_rtx
, false_rtx
;
5763 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5765 /* If everything is a comparison, what we have is highly unlikely
5766 to be simpler, so don't use it. */
5767 && ! (COMPARISON_P (x
)
5768 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5770 rtx cop1
= const0_rtx
;
5771 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5773 if (cond_code
== NE
&& COMPARISON_P (cond
))
5776 /* Simplify the alternative arms; this may collapse the true and
5777 false arms to store-flag values. Be careful to use copy_rtx
5778 here since true_rtx or false_rtx might share RTL with x as a
5779 result of the if_then_else_cond call above. */
5780 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5781 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5783 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5784 is unlikely to be simpler. */
5785 if (general_operand (true_rtx
, VOIDmode
)
5786 && general_operand (false_rtx
, VOIDmode
))
5788 enum rtx_code reversed
;
5790 /* Restarting if we generate a store-flag expression will cause
5791 us to loop. Just drop through in this case. */
5793 /* If the result values are STORE_FLAG_VALUE and zero, we can
5794 just make the comparison operation. */
5795 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5796 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5798 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5799 && ((reversed
= reversed_comparison_code_parts
5800 (cond_code
, cond
, cop1
, NULL
))
5802 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5805 /* Likewise, we can make the negate of a comparison operation
5806 if the result values are - STORE_FLAG_VALUE and zero. */
5807 else if (CONST_INT_P (true_rtx
)
5808 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5809 && false_rtx
== const0_rtx
)
5810 x
= simplify_gen_unary (NEG
, mode
,
5811 simplify_gen_relational (cond_code
,
5815 else if (CONST_INT_P (false_rtx
)
5816 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5817 && true_rtx
== const0_rtx
5818 && ((reversed
= reversed_comparison_code_parts
5819 (cond_code
, cond
, cop1
, NULL
))
5821 x
= simplify_gen_unary (NEG
, mode
,
5822 simplify_gen_relational (reversed
,
5827 return gen_rtx_IF_THEN_ELSE (mode
,
5828 simplify_gen_relational (cond_code
,
5833 true_rtx
, false_rtx
);
5835 code
= GET_CODE (x
);
5836 op0_mode
= VOIDmode
;
5841 /* First see if we can apply the inverse distributive law. */
5842 if (code
== PLUS
|| code
== MINUS
5843 || code
== AND
|| code
== IOR
|| code
== XOR
)
5845 x
= apply_distributive_law (x
);
5846 code
= GET_CODE (x
);
5847 op0_mode
= VOIDmode
;
5850 /* If CODE is an associative operation not otherwise handled, see if we
5851 can associate some operands. This can win if they are constants or
5852 if they are logically related (i.e. (a & b) & a). */
5853 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5854 || code
== AND
|| code
== IOR
|| code
== XOR
5855 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5856 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5857 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5859 if (GET_CODE (XEXP (x
, 0)) == code
)
5861 rtx other
= XEXP (XEXP (x
, 0), 0);
5862 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5863 rtx inner_op1
= XEXP (x
, 1);
5866 /* Make sure we pass the constant operand if any as the second
5867 one if this is a commutative operation. */
5868 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5869 std::swap (inner_op0
, inner_op1
);
5870 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5871 : code
== DIV
? MULT
5873 mode
, inner_op0
, inner_op1
);
5875 /* For commutative operations, try the other pair if that one
5877 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5879 other
= XEXP (XEXP (x
, 0), 1);
5880 inner
= simplify_binary_operation (code
, mode
,
5881 XEXP (XEXP (x
, 0), 0),
5886 return simplify_gen_binary (code
, mode
, other
, inner
);
5890 /* A little bit of algebraic simplification here. */
5894 /* Ensure that our address has any ASHIFTs converted to MULT in case
5895 address-recognizing predicates are called later. */
5896 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5897 SUBST (XEXP (x
, 0), temp
);
5901 if (op0_mode
== VOIDmode
)
5902 op0_mode
= GET_MODE (SUBREG_REG (x
));
5904 /* See if this can be moved to simplify_subreg. */
5905 if (CONSTANT_P (SUBREG_REG (x
))
5906 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5907 /* Don't call gen_lowpart if the inner mode
5908 is VOIDmode and we cannot simplify it, as SUBREG without
5909 inner mode is invalid. */
5910 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5911 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5912 return gen_lowpart (mode
, SUBREG_REG (x
));
5914 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5918 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5923 /* If op is known to have all lower bits zero, the result is zero. */
5925 && SCALAR_INT_MODE_P (mode
)
5926 && SCALAR_INT_MODE_P (op0_mode
)
5927 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5928 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5929 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5930 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5931 & GET_MODE_MASK (mode
)) == 0)
5932 return CONST0_RTX (mode
);
5935 /* Don't change the mode of the MEM if that would change the meaning
5937 if (MEM_P (SUBREG_REG (x
))
5938 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5939 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5940 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5941 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5943 /* Note that we cannot do any narrowing for non-constants since
5944 we might have been counting on using the fact that some bits were
5945 zero. We now do this in the SET. */
5950 temp
= expand_compound_operation (XEXP (x
, 0));
5952 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5953 replaced by (lshiftrt X C). This will convert
5954 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5956 if (GET_CODE (temp
) == ASHIFTRT
5957 && CONST_INT_P (XEXP (temp
, 1))
5958 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5959 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5960 INTVAL (XEXP (temp
, 1)));
5962 /* If X has only a single bit that might be nonzero, say, bit I, convert
5963 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5964 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5965 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5966 or a SUBREG of one since we'd be making the expression more
5967 complex if it was just a register. */
5970 && ! (GET_CODE (temp
) == SUBREG
5971 && REG_P (SUBREG_REG (temp
)))
5972 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5974 rtx temp1
= simplify_shift_const
5975 (NULL_RTX
, ASHIFTRT
, mode
,
5976 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5977 GET_MODE_PRECISION (mode
) - 1 - i
),
5978 GET_MODE_PRECISION (mode
) - 1 - i
);
5980 /* If all we did was surround TEMP with the two shifts, we
5981 haven't improved anything, so don't use it. Otherwise,
5982 we are better off with TEMP1. */
5983 if (GET_CODE (temp1
) != ASHIFTRT
5984 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5985 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5991 /* We can't handle truncation to a partial integer mode here
5992 because we don't know the real bitsize of the partial
5994 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5997 if (HWI_COMPUTABLE_MODE_P (mode
))
5999 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
6000 GET_MODE_MASK (mode
), 0));
6002 /* We can truncate a constant value and return it. */
6003 if (CONST_INT_P (XEXP (x
, 0)))
6004 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
6006 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
6007 whose value is a comparison can be replaced with a subreg if
6008 STORE_FLAG_VALUE permits. */
6009 if (HWI_COMPUTABLE_MODE_P (mode
)
6010 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
6011 && (temp
= get_last_value (XEXP (x
, 0)))
6012 && COMPARISON_P (temp
))
6013 return gen_lowpart (mode
, XEXP (x
, 0));
6017 /* (const (const X)) can become (const X). Do it this way rather than
6018 returning the inner CONST since CONST can be shared with a
6020 if (GET_CODE (XEXP (x
, 0)) == CONST
)
6021 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
6025 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6026 can add in an offset. find_split_point will split this address up
6027 again if it doesn't match. */
6028 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
6029 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
6034 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6035 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6036 bit-field and can be replaced by either a sign_extend or a
6037 sign_extract. The `and' may be a zero_extend and the two
6038 <c>, -<c> constants may be reversed. */
6039 if (GET_CODE (XEXP (x
, 0)) == XOR
6040 && CONST_INT_P (XEXP (x
, 1))
6041 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
6042 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
6043 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
6044 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
6045 && HWI_COMPUTABLE_MODE_P (mode
)
6046 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
6047 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6048 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6049 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
6050 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
6051 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
6052 == (unsigned int) i
+ 1))))
6053 return simplify_shift_const
6054 (NULL_RTX
, ASHIFTRT
, mode
,
6055 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6056 XEXP (XEXP (XEXP (x
, 0), 0), 0),
6057 GET_MODE_PRECISION (mode
) - (i
+ 1)),
6058 GET_MODE_PRECISION (mode
) - (i
+ 1));
6060 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6061 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6062 the bitsize of the mode - 1. This allows simplification of
6063 "a = (b & 8) == 0;" */
6064 if (XEXP (x
, 1) == constm1_rtx
6065 && !REG_P (XEXP (x
, 0))
6066 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
6067 && REG_P (SUBREG_REG (XEXP (x
, 0))))
6068 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
6069 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
6070 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6071 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
6072 GET_MODE_PRECISION (mode
) - 1),
6073 GET_MODE_PRECISION (mode
) - 1);
6075 /* If we are adding two things that have no bits in common, convert
6076 the addition into an IOR. This will often be further simplified,
6077 for example in cases like ((a & 1) + (a & 2)), which can
6080 if (HWI_COMPUTABLE_MODE_P (mode
)
6081 && (nonzero_bits (XEXP (x
, 0), mode
)
6082 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
6084 /* Try to simplify the expression further. */
6085 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
6086 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
6088 /* If we could, great. If not, do not go ahead with the IOR
6089 replacement, since PLUS appears in many special purpose
6090 address arithmetic instructions. */
6091 if (GET_CODE (temp
) != CLOBBER
6092 && (GET_CODE (temp
) != IOR
6093 || ((XEXP (temp
, 0) != XEXP (x
, 0)
6094 || XEXP (temp
, 1) != XEXP (x
, 1))
6095 && (XEXP (temp
, 0) != XEXP (x
, 1)
6096 || XEXP (temp
, 1) != XEXP (x
, 0)))))
6100 /* Canonicalize x + x into x << 1. */
6101 if (GET_MODE_CLASS (mode
) == MODE_INT
6102 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
6103 && !side_effects_p (XEXP (x
, 0)))
6104 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
6109 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6110 (and <foo> (const_int pow2-1)) */
6111 if (GET_CODE (XEXP (x
, 1)) == AND
6112 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
6113 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
6114 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6115 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
6116 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
6120 /* If we have (mult (plus A B) C), apply the distributive law and then
6121 the inverse distributive law to see if things simplify. This
6122 occurs mostly in addresses, often when unrolling loops. */
6124 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
6126 rtx result
= distribute_and_simplify_rtx (x
, 0);
6131 /* Try simplify a*(b/c) as (a*b)/c. */
6132 if (FLOAT_MODE_P (mode
) && flag_associative_math
6133 && GET_CODE (XEXP (x
, 0)) == DIV
)
6135 rtx tem
= simplify_binary_operation (MULT
, mode
,
6136 XEXP (XEXP (x
, 0), 0),
6139 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6144 /* If this is a divide by a power of two, treat it as a shift if
6145 its first operand is a shift. */
6146 if (CONST_INT_P (XEXP (x
, 1))
6147 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6148 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6149 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6150 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6151 || GET_CODE (XEXP (x
, 0)) == ROTATE
6152 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6153 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
6157 case GT
: case GTU
: case GE
: case GEU
:
6158 case LT
: case LTU
: case LE
: case LEU
:
6159 case UNEQ
: case LTGT
:
6160 case UNGT
: case UNGE
:
6161 case UNLT
: case UNLE
:
6162 case UNORDERED
: case ORDERED
:
6163 /* If the first operand is a condition code, we can't do anything
6165 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6166 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6167 && ! CC0_P (XEXP (x
, 0))))
6169 rtx op0
= XEXP (x
, 0);
6170 rtx op1
= XEXP (x
, 1);
6171 enum rtx_code new_code
;
6173 if (GET_CODE (op0
) == COMPARE
)
6174 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6176 /* Simplify our comparison, if possible. */
6177 new_code
= simplify_comparison (code
, &op0
, &op1
);
6179 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6180 if only the low-order bit is possibly nonzero in X (such as when
6181 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6182 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6183 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6186 Remove any ZERO_EXTRACT we made when thinking this was a
6187 comparison. It may now be simpler to use, e.g., an AND. If a
6188 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6189 the call to make_compound_operation in the SET case.
6191 Don't apply these optimizations if the caller would
6192 prefer a comparison rather than a value.
6193 E.g., for the condition in an IF_THEN_ELSE most targets need
6194 an explicit comparison. */
6199 else if (STORE_FLAG_VALUE
== 1
6200 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6201 && op1
== const0_rtx
6202 && mode
== GET_MODE (op0
)
6203 && nonzero_bits (op0
, mode
) == 1)
6204 return gen_lowpart (mode
,
6205 expand_compound_operation (op0
));
6207 else if (STORE_FLAG_VALUE
== 1
6208 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6209 && op1
== const0_rtx
6210 && mode
== GET_MODE (op0
)
6211 && (num_sign_bit_copies (op0
, mode
)
6212 == GET_MODE_PRECISION (mode
)))
6214 op0
= expand_compound_operation (op0
);
6215 return simplify_gen_unary (NEG
, mode
,
6216 gen_lowpart (mode
, op0
),
6220 else if (STORE_FLAG_VALUE
== 1
6221 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6222 && op1
== const0_rtx
6223 && mode
== GET_MODE (op0
)
6224 && nonzero_bits (op0
, mode
) == 1)
6226 op0
= expand_compound_operation (op0
);
6227 return simplify_gen_binary (XOR
, mode
,
6228 gen_lowpart (mode
, op0
),
6232 else if (STORE_FLAG_VALUE
== 1
6233 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6234 && op1
== const0_rtx
6235 && mode
== GET_MODE (op0
)
6236 && (num_sign_bit_copies (op0
, mode
)
6237 == GET_MODE_PRECISION (mode
)))
6239 op0
= expand_compound_operation (op0
);
6240 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6243 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6248 else if (STORE_FLAG_VALUE
== -1
6249 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6250 && op1
== const0_rtx
6251 && mode
== GET_MODE (op0
)
6252 && (num_sign_bit_copies (op0
, mode
)
6253 == GET_MODE_PRECISION (mode
)))
6254 return gen_lowpart (mode
,
6255 expand_compound_operation (op0
));
6257 else if (STORE_FLAG_VALUE
== -1
6258 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6259 && op1
== const0_rtx
6260 && mode
== GET_MODE (op0
)
6261 && nonzero_bits (op0
, mode
) == 1)
6263 op0
= expand_compound_operation (op0
);
6264 return simplify_gen_unary (NEG
, mode
,
6265 gen_lowpart (mode
, op0
),
6269 else if (STORE_FLAG_VALUE
== -1
6270 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6271 && op1
== const0_rtx
6272 && mode
== GET_MODE (op0
)
6273 && (num_sign_bit_copies (op0
, mode
)
6274 == GET_MODE_PRECISION (mode
)))
6276 op0
= expand_compound_operation (op0
);
6277 return simplify_gen_unary (NOT
, mode
,
6278 gen_lowpart (mode
, op0
),
6282 /* If X is 0/1, (eq X 0) is X-1. */
6283 else if (STORE_FLAG_VALUE
== -1
6284 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6285 && op1
== const0_rtx
6286 && mode
== GET_MODE (op0
)
6287 && nonzero_bits (op0
, mode
) == 1)
6289 op0
= expand_compound_operation (op0
);
6290 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6293 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6294 one bit that might be nonzero, we can convert (ne x 0) to
6295 (ashift x c) where C puts the bit in the sign bit. Remove any
6296 AND with STORE_FLAG_VALUE when we are done, since we are only
6297 going to test the sign bit. */
6298 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6299 && HWI_COMPUTABLE_MODE_P (mode
)
6300 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6301 && op1
== const0_rtx
6302 && mode
== GET_MODE (op0
)
6303 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6305 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6306 expand_compound_operation (op0
),
6307 GET_MODE_PRECISION (mode
) - 1 - i
);
6308 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6314 /* If the code changed, return a whole new comparison.
6315 We also need to avoid using SUBST in cases where
6316 simplify_comparison has widened a comparison with a CONST_INT,
6317 since in that case the wider CONST_INT may fail the sanity
6318 checks in do_SUBST. */
6319 if (new_code
!= code
6320 || (CONST_INT_P (op1
)
6321 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6322 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6323 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6325 /* Otherwise, keep this operation, but maybe change its operands.
6326 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6327 SUBST (XEXP (x
, 0), op0
);
6328 SUBST (XEXP (x
, 1), op1
);
6333 return simplify_if_then_else (x
);
6339 /* If we are processing SET_DEST, we are done. */
6343 return expand_compound_operation (x
);
6346 return simplify_set (x
);
6350 return simplify_logical (x
);
6357 /* If this is a shift by a constant amount, simplify it. */
6358 if (CONST_INT_P (XEXP (x
, 1)))
6359 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6360 INTVAL (XEXP (x
, 1)));
6362 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6364 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6366 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6378 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6381 simplify_if_then_else (rtx x
)
6383 machine_mode mode
= GET_MODE (x
);
6384 rtx cond
= XEXP (x
, 0);
6385 rtx true_rtx
= XEXP (x
, 1);
6386 rtx false_rtx
= XEXP (x
, 2);
6387 enum rtx_code true_code
= GET_CODE (cond
);
6388 int comparison_p
= COMPARISON_P (cond
);
6391 enum rtx_code false_code
;
6394 /* Simplify storing of the truth value. */
6395 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6396 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6397 XEXP (cond
, 0), XEXP (cond
, 1));
6399 /* Also when the truth value has to be reversed. */
6401 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6402 && (reversed
= reversed_comparison (cond
, mode
)))
6405 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6406 in it is being compared against certain values. Get the true and false
6407 comparisons and see if that says anything about the value of each arm. */
6410 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6412 && REG_P (XEXP (cond
, 0)))
6415 rtx from
= XEXP (cond
, 0);
6416 rtx true_val
= XEXP (cond
, 1);
6417 rtx false_val
= true_val
;
6420 /* If FALSE_CODE is EQ, swap the codes and arms. */
6422 if (false_code
== EQ
)
6424 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6425 std::swap (true_rtx
, false_rtx
);
6428 /* If we are comparing against zero and the expression being tested has
6429 only a single bit that might be nonzero, that is its value when it is
6430 not equal to zero. Similarly if it is known to be -1 or 0. */
6432 if (true_code
== EQ
&& true_val
== const0_rtx
6433 && pow2p_hwi (nzb
= nonzero_bits (from
, GET_MODE (from
))))
6436 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6438 else if (true_code
== EQ
&& true_val
== const0_rtx
6439 && (num_sign_bit_copies (from
, GET_MODE (from
))
6440 == GET_MODE_PRECISION (GET_MODE (from
))))
6443 false_val
= constm1_rtx
;
6446 /* Now simplify an arm if we know the value of the register in the
6447 branch and it is used in the arm. Be careful due to the potential
6448 of locally-shared RTL. */
6450 if (reg_mentioned_p (from
, true_rtx
))
6451 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6453 pc_rtx
, pc_rtx
, 0, 0, 0);
6454 if (reg_mentioned_p (from
, false_rtx
))
6455 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6457 pc_rtx
, pc_rtx
, 0, 0, 0);
6459 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6460 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6462 true_rtx
= XEXP (x
, 1);
6463 false_rtx
= XEXP (x
, 2);
6464 true_code
= GET_CODE (cond
);
6467 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6468 reversed, do so to avoid needing two sets of patterns for
6469 subtract-and-branch insns. Similarly if we have a constant in the true
6470 arm, the false arm is the same as the first operand of the comparison, or
6471 the false arm is more complicated than the true arm. */
6474 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6475 && (true_rtx
== pc_rtx
6476 || (CONSTANT_P (true_rtx
)
6477 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6478 || true_rtx
== const0_rtx
6479 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6480 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6481 && !OBJECT_P (false_rtx
))
6482 || reg_mentioned_p (true_rtx
, false_rtx
)
6483 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6485 true_code
= reversed_comparison_code (cond
, NULL
);
6486 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6487 SUBST (XEXP (x
, 1), false_rtx
);
6488 SUBST (XEXP (x
, 2), true_rtx
);
6490 std::swap (true_rtx
, false_rtx
);
6493 /* It is possible that the conditional has been simplified out. */
6494 true_code
= GET_CODE (cond
);
6495 comparison_p
= COMPARISON_P (cond
);
6498 /* If the two arms are identical, we don't need the comparison. */
6500 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6503 /* Convert a == b ? b : a to "a". */
6504 if (true_code
== EQ
&& ! side_effects_p (cond
)
6505 && !HONOR_NANS (mode
)
6506 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6507 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6509 else if (true_code
== NE
&& ! side_effects_p (cond
)
6510 && !HONOR_NANS (mode
)
6511 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6512 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6515 /* Look for cases where we have (abs x) or (neg (abs X)). */
6517 if (GET_MODE_CLASS (mode
) == MODE_INT
6519 && XEXP (cond
, 1) == const0_rtx
6520 && GET_CODE (false_rtx
) == NEG
6521 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6522 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6523 && ! side_effects_p (true_rtx
))
6528 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6532 simplify_gen_unary (NEG
, mode
,
6533 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6539 /* Look for MIN or MAX. */
6541 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6543 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6544 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6545 && ! side_effects_p (cond
))
6550 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6553 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6556 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6559 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6564 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6565 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6566 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6567 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6568 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6569 neither 1 or -1, but it isn't worth checking for. */
6571 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6573 && GET_MODE_CLASS (mode
) == MODE_INT
6574 && ! side_effects_p (x
))
6576 rtx t
= make_compound_operation (true_rtx
, SET
);
6577 rtx f
= make_compound_operation (false_rtx
, SET
);
6578 rtx cond_op0
= XEXP (cond
, 0);
6579 rtx cond_op1
= XEXP (cond
, 1);
6580 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6581 machine_mode m
= mode
;
6582 rtx z
= 0, c1
= NULL_RTX
;
6584 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6585 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6586 || GET_CODE (t
) == ASHIFT
6587 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6588 && rtx_equal_p (XEXP (t
, 0), f
))
6589 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6591 /* If an identity-zero op is commutative, check whether there
6592 would be a match if we swapped the operands. */
6593 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6594 || GET_CODE (t
) == XOR
)
6595 && rtx_equal_p (XEXP (t
, 1), f
))
6596 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6597 else if (GET_CODE (t
) == SIGN_EXTEND
6598 && (GET_CODE (XEXP (t
, 0)) == PLUS
6599 || GET_CODE (XEXP (t
, 0)) == MINUS
6600 || GET_CODE (XEXP (t
, 0)) == IOR
6601 || GET_CODE (XEXP (t
, 0)) == XOR
6602 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6603 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6604 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6605 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6606 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6607 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6608 && (num_sign_bit_copies (f
, GET_MODE (f
))
6610 (GET_MODE_PRECISION (mode
)
6611 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6613 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6614 extend_op
= SIGN_EXTEND
;
6615 m
= GET_MODE (XEXP (t
, 0));
6617 else if (GET_CODE (t
) == SIGN_EXTEND
6618 && (GET_CODE (XEXP (t
, 0)) == PLUS
6619 || GET_CODE (XEXP (t
, 0)) == IOR
6620 || GET_CODE (XEXP (t
, 0)) == XOR
)
6621 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6622 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6623 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6624 && (num_sign_bit_copies (f
, GET_MODE (f
))
6626 (GET_MODE_PRECISION (mode
)
6627 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6629 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6630 extend_op
= SIGN_EXTEND
;
6631 m
= GET_MODE (XEXP (t
, 0));
6633 else if (GET_CODE (t
) == ZERO_EXTEND
6634 && (GET_CODE (XEXP (t
, 0)) == PLUS
6635 || GET_CODE (XEXP (t
, 0)) == MINUS
6636 || GET_CODE (XEXP (t
, 0)) == IOR
6637 || GET_CODE (XEXP (t
, 0)) == XOR
6638 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6639 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6640 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6641 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6642 && HWI_COMPUTABLE_MODE_P (mode
)
6643 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6644 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6645 && ((nonzero_bits (f
, GET_MODE (f
))
6646 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6649 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6650 extend_op
= ZERO_EXTEND
;
6651 m
= GET_MODE (XEXP (t
, 0));
6653 else if (GET_CODE (t
) == ZERO_EXTEND
6654 && (GET_CODE (XEXP (t
, 0)) == PLUS
6655 || GET_CODE (XEXP (t
, 0)) == IOR
6656 || GET_CODE (XEXP (t
, 0)) == XOR
)
6657 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6658 && HWI_COMPUTABLE_MODE_P (mode
)
6659 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6660 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6661 && ((nonzero_bits (f
, GET_MODE (f
))
6662 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6665 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6666 extend_op
= ZERO_EXTEND
;
6667 m
= GET_MODE (XEXP (t
, 0));
6672 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6673 cond_op0
, cond_op1
),
6674 pc_rtx
, pc_rtx
, 0, 0, 0);
6675 temp
= simplify_gen_binary (MULT
, m
, temp
,
6676 simplify_gen_binary (MULT
, m
, c1
,
6678 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6679 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6681 if (extend_op
!= UNKNOWN
)
6682 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6688 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6689 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6690 negation of a single bit, we can convert this operation to a shift. We
6691 can actually do this more generally, but it doesn't seem worth it. */
6693 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6694 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6695 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6696 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6697 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6698 == GET_MODE_PRECISION (mode
))
6699 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6701 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6702 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6704 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6705 non-zero bit in A is C1. */
6706 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6707 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6708 && INTEGRAL_MODE_P (GET_MODE (XEXP (cond
, 0)))
6709 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6710 == nonzero_bits (XEXP (cond
, 0), GET_MODE (XEXP (cond
, 0)))
6711 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6713 rtx val
= XEXP (cond
, 0);
6714 enum machine_mode val_mode
= GET_MODE (val
);
6715 if (val_mode
== mode
)
6717 else if (GET_MODE_PRECISION (val_mode
) < GET_MODE_PRECISION (mode
))
6718 return simplify_gen_unary (ZERO_EXTEND
, mode
, val
, val_mode
);
6724 /* Simplify X, a SET expression. Return the new expression. */
6727 simplify_set (rtx x
)
6729 rtx src
= SET_SRC (x
);
6730 rtx dest
= SET_DEST (x
);
6732 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6733 rtx_insn
*other_insn
;
6736 /* (set (pc) (return)) gets written as (return). */
6737 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6740 /* Now that we know for sure which bits of SRC we are using, see if we can
6741 simplify the expression for the object knowing that we only need the
6744 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6746 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6747 SUBST (SET_SRC (x
), src
);
6750 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6751 the comparison result and try to simplify it unless we already have used
6752 undobuf.other_insn. */
6753 if ((GET_MODE_CLASS (mode
) == MODE_CC
6754 || GET_CODE (src
) == COMPARE
6756 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6757 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6758 && COMPARISON_P (*cc_use
)
6759 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6761 enum rtx_code old_code
= GET_CODE (*cc_use
);
6762 enum rtx_code new_code
;
6764 int other_changed
= 0;
6765 rtx inner_compare
= NULL_RTX
;
6766 machine_mode compare_mode
= GET_MODE (dest
);
6768 if (GET_CODE (src
) == COMPARE
)
6770 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6771 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6773 inner_compare
= op0
;
6774 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6778 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6780 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6783 new_code
= old_code
;
6784 else if (!CONSTANT_P (tmp
))
6786 new_code
= GET_CODE (tmp
);
6787 op0
= XEXP (tmp
, 0);
6788 op1
= XEXP (tmp
, 1);
6792 rtx pat
= PATTERN (other_insn
);
6793 undobuf
.other_insn
= other_insn
;
6794 SUBST (*cc_use
, tmp
);
6796 /* Attempt to simplify CC user. */
6797 if (GET_CODE (pat
) == SET
)
6799 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6800 if (new_rtx
!= NULL_RTX
)
6801 SUBST (SET_SRC (pat
), new_rtx
);
6804 /* Convert X into a no-op move. */
6805 SUBST (SET_DEST (x
), pc_rtx
);
6806 SUBST (SET_SRC (x
), pc_rtx
);
6810 /* Simplify our comparison, if possible. */
6811 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6813 #ifdef SELECT_CC_MODE
6814 /* If this machine has CC modes other than CCmode, check to see if we
6815 need to use a different CC mode here. */
6816 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6817 compare_mode
= GET_MODE (op0
);
6818 else if (inner_compare
6819 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6820 && new_code
== old_code
6821 && op0
== XEXP (inner_compare
, 0)
6822 && op1
== XEXP (inner_compare
, 1))
6823 compare_mode
= GET_MODE (inner_compare
);
6825 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6827 /* If the mode changed, we have to change SET_DEST, the mode in the
6828 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6829 a hard register, just build new versions with the proper mode. If it
6830 is a pseudo, we lose unless it is only time we set the pseudo, in
6831 which case we can safely change its mode. */
6832 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6834 if (can_change_dest_mode (dest
, 0, compare_mode
))
6836 unsigned int regno
= REGNO (dest
);
6839 if (regno
< FIRST_PSEUDO_REGISTER
)
6840 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6843 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6844 new_dest
= regno_reg_rtx
[regno
];
6847 SUBST (SET_DEST (x
), new_dest
);
6848 SUBST (XEXP (*cc_use
, 0), new_dest
);
6854 #endif /* SELECT_CC_MODE */
6856 /* If the code changed, we have to build a new comparison in
6857 undobuf.other_insn. */
6858 if (new_code
!= old_code
)
6860 int other_changed_previously
= other_changed
;
6861 unsigned HOST_WIDE_INT mask
;
6862 rtx old_cc_use
= *cc_use
;
6864 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6868 /* If the only change we made was to change an EQ into an NE or
6869 vice versa, OP0 has only one bit that might be nonzero, and OP1
6870 is zero, check if changing the user of the condition code will
6871 produce a valid insn. If it won't, we can keep the original code
6872 in that insn by surrounding our operation with an XOR. */
6874 if (((old_code
== NE
&& new_code
== EQ
)
6875 || (old_code
== EQ
&& new_code
== NE
))
6876 && ! other_changed_previously
&& op1
== const0_rtx
6877 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6878 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6880 rtx pat
= PATTERN (other_insn
), note
= 0;
6882 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6883 && ! check_asm_operands (pat
)))
6885 *cc_use
= old_cc_use
;
6888 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6896 undobuf
.other_insn
= other_insn
;
6898 /* Don't generate a compare of a CC with 0, just use that CC. */
6899 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6901 SUBST (SET_SRC (x
), op0
);
6904 /* Otherwise, if we didn't previously have the same COMPARE we
6905 want, create it from scratch. */
6906 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6907 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6909 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6915 /* Get SET_SRC in a form where we have placed back any
6916 compound expressions. Then do the checks below. */
6917 src
= make_compound_operation (src
, SET
);
6918 SUBST (SET_SRC (x
), src
);
6921 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6922 and X being a REG or (subreg (reg)), we may be able to convert this to
6923 (set (subreg:m2 x) (op)).
6925 We can always do this if M1 is narrower than M2 because that means that
6926 we only care about the low bits of the result.
6928 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6929 perform a narrower operation than requested since the high-order bits will
6930 be undefined. On machine where it is defined, this transformation is safe
6931 as long as M1 and M2 have the same number of words. */
6933 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6934 && !OBJECT_P (SUBREG_REG (src
))
6935 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6937 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6938 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6939 && (WORD_REGISTER_OPERATIONS
6940 || (GET_MODE_SIZE (GET_MODE (src
))
6941 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
6942 #ifdef CANNOT_CHANGE_MODE_CLASS
6943 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6944 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6945 GET_MODE (SUBREG_REG (src
)),
6949 || (GET_CODE (dest
) == SUBREG
6950 && REG_P (SUBREG_REG (dest
)))))
6952 SUBST (SET_DEST (x
),
6953 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6955 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6957 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6960 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6963 && GET_CODE (src
) == SUBREG
6964 && subreg_lowpart_p (src
)
6965 && (GET_MODE_PRECISION (GET_MODE (src
))
6966 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6968 rtx inner
= SUBREG_REG (src
);
6969 machine_mode inner_mode
= GET_MODE (inner
);
6971 /* Here we make sure that we don't have a sign bit on. */
6972 if (val_signbit_known_clear_p (GET_MODE (src
),
6973 nonzero_bits (inner
, inner_mode
)))
6975 SUBST (SET_SRC (x
), inner
);
6980 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6981 would require a paradoxical subreg. Replace the subreg with a
6982 zero_extend to avoid the reload that would otherwise be required. */
6984 enum rtx_code extend_op
;
6985 if (paradoxical_subreg_p (src
)
6986 && MEM_P (SUBREG_REG (src
))
6987 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
6990 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
6995 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6996 are comparing an item known to be 0 or -1 against 0, use a logical
6997 operation instead. Check for one of the arms being an IOR of the other
6998 arm with some value. We compute three terms to be IOR'ed together. In
6999 practice, at most two will be nonzero. Then we do the IOR's. */
7001 if (GET_CODE (dest
) != PC
7002 && GET_CODE (src
) == IF_THEN_ELSE
7003 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
7004 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
7005 && XEXP (XEXP (src
, 0), 1) == const0_rtx
7006 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
7007 && (!HAVE_conditional_move
7008 || ! can_conditionally_move_p (GET_MODE (src
)))
7009 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
7010 GET_MODE (XEXP (XEXP (src
, 0), 0)))
7011 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
7012 && ! side_effects_p (src
))
7014 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7015 ? XEXP (src
, 1) : XEXP (src
, 2));
7016 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7017 ? XEXP (src
, 2) : XEXP (src
, 1));
7018 rtx term1
= const0_rtx
, term2
, term3
;
7020 if (GET_CODE (true_rtx
) == IOR
7021 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
7022 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
7023 else if (GET_CODE (true_rtx
) == IOR
7024 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
7025 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
7026 else if (GET_CODE (false_rtx
) == IOR
7027 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
7028 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
7029 else if (GET_CODE (false_rtx
) == IOR
7030 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
7031 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
7033 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
7034 XEXP (XEXP (src
, 0), 0), true_rtx
);
7035 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
7036 simplify_gen_unary (NOT
, GET_MODE (src
),
7037 XEXP (XEXP (src
, 0), 0),
7042 simplify_gen_binary (IOR
, GET_MODE (src
),
7043 simplify_gen_binary (IOR
, GET_MODE (src
),
7050 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7051 whole thing fail. */
7052 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
7054 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
7057 /* Convert this into a field assignment operation, if possible. */
7058 return make_field_assignment (x
);
7061 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7065 simplify_logical (rtx x
)
7067 machine_mode mode
= GET_MODE (x
);
7068 rtx op0
= XEXP (x
, 0);
7069 rtx op1
= XEXP (x
, 1);
7071 switch (GET_CODE (x
))
7074 /* We can call simplify_and_const_int only if we don't lose
7075 any (sign) bits when converting INTVAL (op1) to
7076 "unsigned HOST_WIDE_INT". */
7077 if (CONST_INT_P (op1
)
7078 && (HWI_COMPUTABLE_MODE_P (mode
)
7079 || INTVAL (op1
) > 0))
7081 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
7082 if (GET_CODE (x
) != AND
)
7089 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7090 apply the distributive law and then the inverse distributive
7091 law to see if things simplify. */
7092 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
7094 rtx result
= distribute_and_simplify_rtx (x
, 0);
7098 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
7100 rtx result
= distribute_and_simplify_rtx (x
, 1);
7107 /* If we have (ior (and A B) C), apply the distributive law and then
7108 the inverse distributive law to see if things simplify. */
7110 if (GET_CODE (op0
) == AND
)
7112 rtx result
= distribute_and_simplify_rtx (x
, 0);
7117 if (GET_CODE (op1
) == AND
)
7119 rtx result
= distribute_and_simplify_rtx (x
, 1);
7132 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7133 operations" because they can be replaced with two more basic operations.
7134 ZERO_EXTEND is also considered "compound" because it can be replaced with
7135 an AND operation, which is simpler, though only one operation.
7137 The function expand_compound_operation is called with an rtx expression
7138 and will convert it to the appropriate shifts and AND operations,
7139 simplifying at each stage.
7141 The function make_compound_operation is called to convert an expression
7142 consisting of shifts and ANDs into the equivalent compound expression.
7143 It is the inverse of this function, loosely speaking. */
7146 expand_compound_operation (rtx x
)
7148 unsigned HOST_WIDE_INT pos
= 0, len
;
7150 unsigned int modewidth
;
7153 switch (GET_CODE (x
))
7159 /* We can't necessarily use a const_int for a multiword mode;
7160 it depends on implicitly extending the value.
7161 Since we don't know the right way to extend it,
7162 we can't tell whether the implicit way is right.
7164 Even for a mode that is no wider than a const_int,
7165 we can't win, because we need to sign extend one of its bits through
7166 the rest of it, and we don't know which bit. */
7167 if (CONST_INT_P (XEXP (x
, 0)))
7170 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7171 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7172 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7173 reloaded. If not for that, MEM's would very rarely be safe.
7175 Reject MODEs bigger than a word, because we might not be able
7176 to reference a two-register group starting with an arbitrary register
7177 (and currently gen_lowpart might crash for a SUBREG). */
7179 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
7182 /* Reject MODEs that aren't scalar integers because turning vector
7183 or complex modes into shifts causes problems. */
7185 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7188 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
7189 /* If the inner object has VOIDmode (the only way this can happen
7190 is if it is an ASM_OPERANDS), we can't do anything since we don't
7191 know how much masking to do. */
7203 /* If the operand is a CLOBBER, just return it. */
7204 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7207 if (!CONST_INT_P (XEXP (x
, 1))
7208 || !CONST_INT_P (XEXP (x
, 2))
7209 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7212 /* Reject MODEs that aren't scalar integers because turning vector
7213 or complex modes into shifts causes problems. */
7215 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7218 len
= INTVAL (XEXP (x
, 1));
7219 pos
= INTVAL (XEXP (x
, 2));
7221 /* This should stay within the object being extracted, fail otherwise. */
7222 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7225 if (BITS_BIG_ENDIAN
)
7226 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7233 /* Convert sign extension to zero extension, if we know that the high
7234 bit is not set, as this is easier to optimize. It will be converted
7235 back to cheaper alternative in make_extraction. */
7236 if (GET_CODE (x
) == SIGN_EXTEND
7237 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7238 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7239 & ~(((unsigned HOST_WIDE_INT
)
7240 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7244 machine_mode mode
= GET_MODE (x
);
7245 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7246 rtx temp2
= expand_compound_operation (temp
);
7248 /* Make sure this is a profitable operation. */
7249 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7250 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7252 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7253 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7259 /* We can optimize some special cases of ZERO_EXTEND. */
7260 if (GET_CODE (x
) == ZERO_EXTEND
)
7262 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7263 know that the last value didn't have any inappropriate bits
7265 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7266 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7267 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7268 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7269 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7270 return XEXP (XEXP (x
, 0), 0);
7272 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7273 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7274 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7275 && subreg_lowpart_p (XEXP (x
, 0))
7276 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7277 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7278 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7279 return SUBREG_REG (XEXP (x
, 0));
7281 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7282 is a comparison and STORE_FLAG_VALUE permits. This is like
7283 the first case, but it works even when GET_MODE (x) is larger
7284 than HOST_WIDE_INT. */
7285 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7286 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7287 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7288 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7289 <= HOST_BITS_PER_WIDE_INT
)
7290 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7291 return XEXP (XEXP (x
, 0), 0);
7293 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7294 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7295 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7296 && subreg_lowpart_p (XEXP (x
, 0))
7297 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7298 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7299 <= HOST_BITS_PER_WIDE_INT
)
7300 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7301 return SUBREG_REG (XEXP (x
, 0));
7305 /* If we reach here, we want to return a pair of shifts. The inner
7306 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7307 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7308 logical depending on the value of UNSIGNEDP.
7310 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7311 converted into an AND of a shift.
7313 We must check for the case where the left shift would have a negative
7314 count. This can happen in a case like (x >> 31) & 255 on machines
7315 that can't shift by a constant. On those machines, we would first
7316 combine the shift with the AND to produce a variable-position
7317 extraction. Then the constant of 31 would be substituted in
7318 to produce such a position. */
7320 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7321 if (modewidth
>= pos
+ len
)
7323 machine_mode mode
= GET_MODE (x
);
7324 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7325 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7327 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7328 tem
, modewidth
- pos
- len
);
7329 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7330 mode
, tem
, modewidth
- len
);
7332 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7333 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7334 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7337 (HOST_WIDE_INT_1U
<< len
) - 1);
7339 /* Any other cases we can't handle. */
7342 /* If we couldn't do this for some reason, return the original
7344 if (GET_CODE (tem
) == CLOBBER
)
7350 /* X is a SET which contains an assignment of one object into
7351 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7352 or certain SUBREGS). If possible, convert it into a series of
7355 We half-heartedly support variable positions, but do not at all
7356 support variable lengths. */
7359 expand_field_assignment (const_rtx x
)
7362 rtx pos
; /* Always counts from low bit. */
7364 rtx mask
, cleared
, masked
;
7365 machine_mode compute_mode
;
7367 /* Loop until we find something we can't simplify. */
7370 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7371 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7373 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7374 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7375 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7377 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7378 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7380 inner
= XEXP (SET_DEST (x
), 0);
7381 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7382 pos
= XEXP (SET_DEST (x
), 2);
7384 /* A constant position should stay within the width of INNER. */
7385 if (CONST_INT_P (pos
)
7386 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7389 if (BITS_BIG_ENDIAN
)
7391 if (CONST_INT_P (pos
))
7392 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7394 else if (GET_CODE (pos
) == MINUS
7395 && CONST_INT_P (XEXP (pos
, 1))
7396 && (INTVAL (XEXP (pos
, 1))
7397 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7398 /* If position is ADJUST - X, new position is X. */
7399 pos
= XEXP (pos
, 0);
7402 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7403 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7404 gen_int_mode (prec
- len
,
7411 /* A SUBREG between two modes that occupy the same numbers of words
7412 can be done by moving the SUBREG to the source. */
7413 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7414 /* We need SUBREGs to compute nonzero_bits properly. */
7415 && nonzero_sign_valid
7416 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7417 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7418 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7419 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7421 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7423 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7430 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7431 inner
= SUBREG_REG (inner
);
7433 compute_mode
= GET_MODE (inner
);
7435 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7436 if (! SCALAR_INT_MODE_P (compute_mode
))
7440 /* Don't do anything for vector or complex integral types. */
7441 if (! FLOAT_MODE_P (compute_mode
))
7444 /* Try to find an integral mode to pun with. */
7445 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7446 if (imode
== BLKmode
)
7449 compute_mode
= imode
;
7450 inner
= gen_lowpart (imode
, inner
);
7453 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7454 if (len
>= HOST_BITS_PER_WIDE_INT
)
7457 /* Don't try to compute in too wide unsupported modes. */
7458 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7461 /* Now compute the equivalent expression. Make a copy of INNER
7462 for the SET_DEST in case it is a MEM into which we will substitute;
7463 we don't want shared RTL in that case. */
7464 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7466 cleared
= simplify_gen_binary (AND
, compute_mode
,
7467 simplify_gen_unary (NOT
, compute_mode
,
7468 simplify_gen_binary (ASHIFT
,
7473 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7474 simplify_gen_binary (
7476 gen_lowpart (compute_mode
, SET_SRC (x
)),
7480 x
= gen_rtx_SET (copy_rtx (inner
),
7481 simplify_gen_binary (IOR
, compute_mode
,
7488 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7489 it is an RTX that represents the (variable) starting position; otherwise,
7490 POS is the (constant) starting bit position. Both are counted from the LSB.
7492 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7494 IN_DEST is nonzero if this is a reference in the destination of a SET.
7495 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7496 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7499 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7500 ZERO_EXTRACT should be built even for bits starting at bit 0.
7502 MODE is the desired mode of the result (if IN_DEST == 0).
7504 The result is an RTX for the extraction or NULL_RTX if the target
7508 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7509 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7510 int in_dest
, int in_compare
)
7512 /* This mode describes the size of the storage area
7513 to fetch the overall value from. Within that, we
7514 ignore the POS lowest bits, etc. */
7515 machine_mode is_mode
= GET_MODE (inner
);
7516 machine_mode inner_mode
;
7517 machine_mode wanted_inner_mode
;
7518 machine_mode wanted_inner_reg_mode
= word_mode
;
7519 machine_mode pos_mode
= word_mode
;
7520 machine_mode extraction_mode
= word_mode
;
7521 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7523 rtx orig_pos_rtx
= pos_rtx
;
7524 HOST_WIDE_INT orig_pos
;
7526 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7527 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7529 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7531 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7532 consider just the QI as the memory to extract from.
7533 The subreg adds or removes high bits; its mode is
7534 irrelevant to the meaning of this extraction,
7535 since POS and LEN count from the lsb. */
7536 if (MEM_P (SUBREG_REG (inner
)))
7537 is_mode
= GET_MODE (SUBREG_REG (inner
));
7538 inner
= SUBREG_REG (inner
);
7540 else if (GET_CODE (inner
) == ASHIFT
7541 && CONST_INT_P (XEXP (inner
, 1))
7542 && pos_rtx
== 0 && pos
== 0
7543 && len
> UINTVAL (XEXP (inner
, 1)))
7545 /* We're extracting the least significant bits of an rtx
7546 (ashift X (const_int C)), where LEN > C. Extract the
7547 least significant (LEN - C) bits of X, giving an rtx
7548 whose mode is MODE, then shift it left C times. */
7549 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7550 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7551 unsignedp
, in_dest
, in_compare
);
7553 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7555 else if (GET_CODE (inner
) == TRUNCATE
)
7556 inner
= XEXP (inner
, 0);
7558 inner_mode
= GET_MODE (inner
);
7560 /* See if this can be done without an extraction. We never can if the
7561 width of the field is not the same as that of some integer mode. For
7562 registers, we can only avoid the extraction if the position is at the
7563 low-order bit and this is either not in the destination or we have the
7564 appropriate STRICT_LOW_PART operation available.
7566 For MEM, we can avoid an extract if the field starts on an appropriate
7567 boundary and we can change the mode of the memory reference. */
7569 if (tmode
!= BLKmode
7570 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7572 && (pos
== 0 || REG_P (inner
))
7573 && (inner_mode
== tmode
7575 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7576 || reg_truncated_to_mode (tmode
, inner
))
7579 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7580 || (MEM_P (inner
) && pos_rtx
== 0
7582 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7583 : BITS_PER_UNIT
)) == 0
7584 /* We can't do this if we are widening INNER_MODE (it
7585 may not be aligned, for one thing). */
7586 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7587 && (inner_mode
== tmode
7588 || (! mode_dependent_address_p (XEXP (inner
, 0),
7589 MEM_ADDR_SPACE (inner
))
7590 && ! MEM_VOLATILE_P (inner
))))))
7592 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7593 field. If the original and current mode are the same, we need not
7594 adjust the offset. Otherwise, we do if bytes big endian.
7596 If INNER is not a MEM, get a piece consisting of just the field
7597 of interest (in this case POS % BITS_PER_WORD must be 0). */
7601 HOST_WIDE_INT offset
;
7603 /* POS counts from lsb, but make OFFSET count in memory order. */
7604 if (BYTES_BIG_ENDIAN
)
7605 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7607 offset
= pos
/ BITS_PER_UNIT
;
7609 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7611 else if (REG_P (inner
))
7613 if (tmode
!= inner_mode
)
7615 /* We can't call gen_lowpart in a DEST since we
7616 always want a SUBREG (see below) and it would sometimes
7617 return a new hard register. */
7620 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7622 if (WORDS_BIG_ENDIAN
7623 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7624 final_word
= ((GET_MODE_SIZE (inner_mode
)
7625 - GET_MODE_SIZE (tmode
))
7626 / UNITS_PER_WORD
) - final_word
;
7628 final_word
*= UNITS_PER_WORD
;
7629 if (BYTES_BIG_ENDIAN
&&
7630 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7631 final_word
+= (GET_MODE_SIZE (inner_mode
)
7632 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7634 /* Avoid creating invalid subregs, for example when
7635 simplifying (x>>32)&255. */
7636 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7639 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7642 new_rtx
= gen_lowpart (tmode
, inner
);
7648 new_rtx
= force_to_mode (inner
, tmode
,
7649 len
>= HOST_BITS_PER_WIDE_INT
7651 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7653 /* If this extraction is going into the destination of a SET,
7654 make a STRICT_LOW_PART unless we made a MEM. */
7657 return (MEM_P (new_rtx
) ? new_rtx
7658 : (GET_CODE (new_rtx
) != SUBREG
7659 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7660 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7665 if (CONST_SCALAR_INT_P (new_rtx
))
7666 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7667 mode
, new_rtx
, tmode
);
7669 /* If we know that no extraneous bits are set, and that the high
7670 bit is not set, convert the extraction to the cheaper of
7671 sign and zero extension, that are equivalent in these cases. */
7672 if (flag_expensive_optimizations
7673 && (HWI_COMPUTABLE_MODE_P (tmode
)
7674 && ((nonzero_bits (new_rtx
, tmode
)
7675 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7678 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7679 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7681 /* Prefer ZERO_EXTENSION, since it gives more information to
7683 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7684 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7689 /* Otherwise, sign- or zero-extend unless we already are in the
7692 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7696 /* Unless this is a COMPARE or we have a funny memory reference,
7697 don't do anything with zero-extending field extracts starting at
7698 the low-order bit since they are simple AND operations. */
7699 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7700 && ! in_compare
&& unsignedp
)
7703 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7704 if the position is not a constant and the length is not 1. In all
7705 other cases, we would only be going outside our object in cases when
7706 an original shift would have been undefined. */
7708 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7709 || (pos_rtx
!= 0 && len
!= 1)))
7712 enum extraction_pattern pattern
= (in_dest
? EP_insv
7713 : unsignedp
? EP_extzv
: EP_extv
);
7715 /* If INNER is not from memory, we want it to have the mode of a register
7716 extraction pattern's structure operand, or word_mode if there is no
7717 such pattern. The same applies to extraction_mode and pos_mode
7718 and their respective operands.
7720 For memory, assume that the desired extraction_mode and pos_mode
7721 are the same as for a register operation, since at present we don't
7722 have named patterns for aligned memory structures. */
7723 struct extraction_insn insn
;
7724 if (get_best_reg_extraction_insn (&insn
, pattern
,
7725 GET_MODE_BITSIZE (inner_mode
), mode
))
7727 wanted_inner_reg_mode
= insn
.struct_mode
;
7728 pos_mode
= insn
.pos_mode
;
7729 extraction_mode
= insn
.field_mode
;
7732 /* Never narrow an object, since that might not be safe. */
7734 if (mode
!= VOIDmode
7735 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7736 extraction_mode
= mode
;
7739 wanted_inner_mode
= wanted_inner_reg_mode
;
7742 /* Be careful not to go beyond the extracted object and maintain the
7743 natural alignment of the memory. */
7744 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7745 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7746 > GET_MODE_BITSIZE (wanted_inner_mode
))
7748 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7749 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7755 if (BITS_BIG_ENDIAN
)
7757 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7758 BITS_BIG_ENDIAN style. If position is constant, compute new
7759 position. Otherwise, build subtraction.
7760 Note that POS is relative to the mode of the original argument.
7761 If it's a MEM we need to recompute POS relative to that.
7762 However, if we're extracting from (or inserting into) a register,
7763 we want to recompute POS relative to wanted_inner_mode. */
7764 int width
= (MEM_P (inner
)
7765 ? GET_MODE_BITSIZE (is_mode
)
7766 : GET_MODE_BITSIZE (wanted_inner_mode
));
7769 pos
= width
- len
- pos
;
7772 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7773 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7775 /* POS may be less than 0 now, but we check for that below.
7776 Note that it can only be less than 0 if !MEM_P (inner). */
7779 /* If INNER has a wider mode, and this is a constant extraction, try to
7780 make it smaller and adjust the byte to point to the byte containing
7782 if (wanted_inner_mode
!= VOIDmode
7783 && inner_mode
!= wanted_inner_mode
7785 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7787 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7788 && ! MEM_VOLATILE_P (inner
))
7792 /* The computations below will be correct if the machine is big
7793 endian in both bits and bytes or little endian in bits and bytes.
7794 If it is mixed, we must adjust. */
7796 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7797 adjust OFFSET to compensate. */
7798 if (BYTES_BIG_ENDIAN
7799 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7800 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7802 /* We can now move to the desired byte. */
7803 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7804 * GET_MODE_SIZE (wanted_inner_mode
);
7805 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7807 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7808 && is_mode
!= wanted_inner_mode
)
7809 offset
= (GET_MODE_SIZE (is_mode
)
7810 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7812 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7815 /* If INNER is not memory, get it into the proper mode. If we are changing
7816 its mode, POS must be a constant and smaller than the size of the new
7818 else if (!MEM_P (inner
))
7820 /* On the LHS, don't create paradoxical subregs implicitely truncating
7821 the register unless TRULY_NOOP_TRUNCATION. */
7823 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7827 if (GET_MODE (inner
) != wanted_inner_mode
7829 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7835 inner
= force_to_mode (inner
, wanted_inner_mode
,
7837 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7839 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7844 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7845 have to zero extend. Otherwise, we can just use a SUBREG. */
7847 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7849 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7850 GET_MODE (pos_rtx
));
7852 /* If we know that no extraneous bits are set, and that the high
7853 bit is not set, convert extraction to cheaper one - either
7854 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7856 if (flag_expensive_optimizations
7857 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7858 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7859 & ~(((unsigned HOST_WIDE_INT
)
7860 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7864 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7865 GET_MODE (pos_rtx
));
7867 /* Prefer ZERO_EXTENSION, since it gives more information to
7869 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7870 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7876 /* Make POS_RTX unless we already have it and it is correct. If we don't
7877 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7879 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7880 pos_rtx
= orig_pos_rtx
;
7882 else if (pos_rtx
== 0)
7883 pos_rtx
= GEN_INT (pos
);
7885 /* Make the required operation. See if we can use existing rtx. */
7886 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7887 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7889 new_rtx
= gen_lowpart (mode
, new_rtx
);
7894 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7895 with any other operations in X. Return X without that shift if so. */
7898 extract_left_shift (rtx x
, int count
)
7900 enum rtx_code code
= GET_CODE (x
);
7901 machine_mode mode
= GET_MODE (x
);
7907 /* This is the shift itself. If it is wide enough, we will return
7908 either the value being shifted if the shift count is equal to
7909 COUNT or a shift for the difference. */
7910 if (CONST_INT_P (XEXP (x
, 1))
7911 && INTVAL (XEXP (x
, 1)) >= count
)
7912 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7913 INTVAL (XEXP (x
, 1)) - count
);
7917 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7918 return simplify_gen_unary (code
, mode
, tem
, mode
);
7922 case PLUS
: case IOR
: case XOR
: case AND
:
7923 /* If we can safely shift this constant and we find the inner shift,
7924 make a new operation. */
7925 if (CONST_INT_P (XEXP (x
, 1))
7926 && (UINTVAL (XEXP (x
, 1))
7927 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7928 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7930 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7931 return simplify_gen_binary (code
, mode
, tem
,
7932 gen_int_mode (val
, mode
));
7943 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7944 level of the expression and MODE is its mode. IN_CODE is as for
7945 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7946 that should be used when recursing on operands of *X_PTR.
7948 There are two possible actions:
7950 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7951 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7953 - Return a new rtx, which the caller returns directly. */
7956 make_compound_operation_int (machine_mode mode
, rtx
*x_ptr
,
7957 enum rtx_code in_code
,
7958 enum rtx_code
*next_code_ptr
)
7961 enum rtx_code next_code
= *next_code_ptr
;
7962 enum rtx_code code
= GET_CODE (x
);
7963 int mode_width
= GET_MODE_PRECISION (mode
);
7968 bool equality_comparison
= false;
7972 equality_comparison
= true;
7976 /* Process depending on the code of this operation. If NEW is set
7977 nonzero, it will be returned. */
7982 /* Convert shifts by constants into multiplications if inside
7984 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7985 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7986 && INTVAL (XEXP (x
, 1)) >= 0)
7988 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7989 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
7991 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7992 if (GET_CODE (new_rtx
) == NEG
)
7994 new_rtx
= XEXP (new_rtx
, 0);
7997 multval
= trunc_int_for_mode (multval
, mode
);
7998 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
8005 lhs
= make_compound_operation (lhs
, next_code
);
8006 rhs
= make_compound_operation (rhs
, next_code
);
8007 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
8009 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
8011 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8013 else if (GET_CODE (lhs
) == MULT
8014 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
8016 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
8017 simplify_gen_unary (NEG
, mode
,
8020 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8024 SUBST (XEXP (x
, 0), lhs
);
8025 SUBST (XEXP (x
, 1), rhs
);
8027 maybe_swap_commutative_operands (x
);
8033 lhs
= make_compound_operation (lhs
, next_code
);
8034 rhs
= make_compound_operation (rhs
, next_code
);
8035 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
8037 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
8039 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8041 else if (GET_CODE (rhs
) == MULT
8042 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
8044 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
8045 simplify_gen_unary (NEG
, mode
,
8048 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8052 SUBST (XEXP (x
, 0), lhs
);
8053 SUBST (XEXP (x
, 1), rhs
);
8058 /* If the second operand is not a constant, we can't do anything
8060 if (!CONST_INT_P (XEXP (x
, 1)))
8063 /* If the constant is a power of two minus one and the first operand
8064 is a logical right shift, make an extraction. */
8065 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8066 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8068 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8069 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
8070 0, in_code
== COMPARE
);
8073 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8074 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
8075 && subreg_lowpart_p (XEXP (x
, 0))
8076 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
8077 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8079 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
8080 machine_mode inner_mode
= GET_MODE (inner_x0
);
8081 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
8082 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
8084 i
, 1, 0, in_code
== COMPARE
);
8088 /* If we narrowed the mode when dropping the subreg, then
8089 we must zero-extend to keep the semantics of the AND. */
8090 if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
8092 else if (SCALAR_INT_MODE_P (inner_mode
))
8093 new_rtx
= simplify_gen_unary (ZERO_EXTEND
, mode
,
8094 new_rtx
, inner_mode
);
8099 /* If that didn't give anything, see if the AND simplifies on
8101 if (!new_rtx
&& i
>= 0)
8103 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8104 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
8105 0, in_code
== COMPARE
);
8108 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8109 else if ((GET_CODE (XEXP (x
, 0)) == XOR
8110 || GET_CODE (XEXP (x
, 0)) == IOR
)
8111 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
8112 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
8113 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8115 /* Apply the distributive law, and then try to make extractions. */
8116 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
8117 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
8119 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
8121 new_rtx
= make_compound_operation (new_rtx
, in_code
);
8124 /* If we are have (and (rotate X C) M) and C is larger than the number
8125 of bits in M, this is an extraction. */
8127 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
8128 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8129 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
8130 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
8132 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8133 new_rtx
= make_extraction (mode
, new_rtx
,
8134 (GET_MODE_PRECISION (mode
)
8135 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8136 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8139 /* On machines without logical shifts, if the operand of the AND is
8140 a logical shift and our mask turns off all the propagated sign
8141 bits, we can replace the logical shift with an arithmetic shift. */
8142 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8143 && !have_insn_for (LSHIFTRT
, mode
)
8144 && have_insn_for (ASHIFTRT
, mode
)
8145 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8146 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8147 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8148 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8150 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8152 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8153 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8155 gen_rtx_ASHIFTRT (mode
,
8156 make_compound_operation
8157 (XEXP (XEXP (x
, 0), 0), next_code
),
8158 XEXP (XEXP (x
, 0), 1)));
8161 /* If the constant is one less than a power of two, this might be
8162 representable by an extraction even if no shift is present.
8163 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8164 we are in a COMPARE. */
8165 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8166 new_rtx
= make_extraction (mode
,
8167 make_compound_operation (XEXP (x
, 0),
8169 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8171 /* If we are in a comparison and this is an AND with a power of two,
8172 convert this into the appropriate bit extract. */
8173 else if (in_code
== COMPARE
8174 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8175 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8176 new_rtx
= make_extraction (mode
,
8177 make_compound_operation (XEXP (x
, 0),
8179 i
, NULL_RTX
, 1, 1, 0, 1);
8181 /* If the one operand is a paradoxical subreg of a register or memory and
8182 the constant (limited to the smaller mode) has only zero bits where
8183 the sub expression has known zero bits, this can be expressed as
8185 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8189 sub
= XEXP (XEXP (x
, 0), 0);
8190 machine_mode sub_mode
= GET_MODE (sub
);
8191 if ((REG_P (sub
) || MEM_P (sub
))
8192 && GET_MODE_PRECISION (sub_mode
) < mode_width
)
8194 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8195 unsigned HOST_WIDE_INT mask
;
8197 /* original AND constant with all the known zero bits set */
8198 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8199 if ((mask
& mode_mask
) == mode_mask
)
8201 new_rtx
= make_compound_operation (sub
, next_code
);
8202 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0,
8203 GET_MODE_PRECISION (sub_mode
),
8204 1, 0, in_code
== COMPARE
);
8212 /* If the sign bit is known to be zero, replace this with an
8213 arithmetic shift. */
8214 if (have_insn_for (ASHIFTRT
, mode
)
8215 && ! have_insn_for (LSHIFTRT
, mode
)
8216 && mode_width
<= HOST_BITS_PER_WIDE_INT
8217 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8219 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8220 make_compound_operation (XEXP (x
, 0),
8232 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8233 this is a SIGN_EXTRACT. */
8234 if (CONST_INT_P (rhs
)
8235 && GET_CODE (lhs
) == ASHIFT
8236 && CONST_INT_P (XEXP (lhs
, 1))
8237 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8238 && INTVAL (XEXP (lhs
, 1)) >= 0
8239 && INTVAL (rhs
) < mode_width
)
8241 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8242 new_rtx
= make_extraction (mode
, new_rtx
,
8243 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8244 NULL_RTX
, mode_width
- INTVAL (rhs
),
8245 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8249 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8250 If so, try to merge the shifts into a SIGN_EXTEND. We could
8251 also do this for some cases of SIGN_EXTRACT, but it doesn't
8252 seem worth the effort; the case checked for occurs on Alpha. */
8255 && ! (GET_CODE (lhs
) == SUBREG
8256 && (OBJECT_P (SUBREG_REG (lhs
))))
8257 && CONST_INT_P (rhs
)
8258 && INTVAL (rhs
) >= 0
8259 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8260 && INTVAL (rhs
) < mode_width
8261 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8262 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8263 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8264 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8269 /* Call ourselves recursively on the inner expression. If we are
8270 narrowing the object and it has a different RTL code from
8271 what it originally did, do this SUBREG as a force_to_mode. */
8273 rtx inner
= SUBREG_REG (x
), simplified
;
8274 enum rtx_code subreg_code
= in_code
;
8276 /* If the SUBREG is masking of a logical right shift,
8277 make an extraction. */
8278 if (GET_CODE (inner
) == LSHIFTRT
8279 && CONST_INT_P (XEXP (inner
, 1))
8280 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8281 && (UINTVAL (XEXP (inner
, 1))
8282 < GET_MODE_PRECISION (GET_MODE (inner
)))
8283 && subreg_lowpart_p (x
))
8285 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8286 int width
= GET_MODE_PRECISION (GET_MODE (inner
))
8287 - INTVAL (XEXP (inner
, 1));
8288 if (width
> mode_width
)
8290 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8291 width
, 1, 0, in_code
== COMPARE
);
8295 /* If in_code is COMPARE, it isn't always safe to pass it through
8296 to the recursive make_compound_operation call. */
8297 if (subreg_code
== COMPARE
8298 && (!subreg_lowpart_p (x
)
8299 || GET_CODE (inner
) == SUBREG
8300 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8301 is (const_int 0), rather than
8302 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8303 || (GET_CODE (inner
) == AND
8304 && CONST_INT_P (XEXP (inner
, 1))
8305 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8306 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8307 >= GET_MODE_BITSIZE (mode
))))
8310 tem
= make_compound_operation (inner
, subreg_code
);
8313 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8317 if (GET_CODE (tem
) != GET_CODE (inner
)
8318 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8319 && subreg_lowpart_p (x
))
8322 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8324 /* If we have something other than a SUBREG, we might have
8325 done an expansion, so rerun ourselves. */
8326 if (GET_CODE (newer
) != SUBREG
)
8327 newer
= make_compound_operation (newer
, in_code
);
8329 /* force_to_mode can expand compounds. If it just re-expanded the
8330 compound, use gen_lowpart to convert to the desired mode. */
8331 if (rtx_equal_p (newer
, x
)
8332 /* Likewise if it re-expanded the compound only partially.
8333 This happens for SUBREG of ZERO_EXTRACT if they extract
8334 the same number of bits. */
8335 || (GET_CODE (newer
) == SUBREG
8336 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8337 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8338 && GET_CODE (inner
) == AND
8339 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8340 return gen_lowpart (GET_MODE (x
), tem
);
8355 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8356 *next_code_ptr
= next_code
;
8360 /* Look at the expression rooted at X. Look for expressions
8361 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8362 Form these expressions.
8364 Return the new rtx, usually just X.
8366 Also, for machines like the VAX that don't have logical shift insns,
8367 try to convert logical to arithmetic shift operations in cases where
8368 they are equivalent. This undoes the canonicalizations to logical
8369 shifts done elsewhere.
8371 We try, as much as possible, to re-use rtl expressions to save memory.
8373 IN_CODE says what kind of expression we are processing. Normally, it is
8374 SET. In a memory address it is MEM. When processing the arguments of
8375 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8376 precisely it is an equality comparison against zero. */
8379 make_compound_operation (rtx x
, enum rtx_code in_code
)
8381 enum rtx_code code
= GET_CODE (x
);
8384 enum rtx_code next_code
;
8387 /* Select the code to be used in recursive calls. Once we are inside an
8388 address, we stay there. If we have a comparison, set to COMPARE,
8389 but once inside, go back to our default of SET. */
8391 next_code
= (code
== MEM
? MEM
8392 : ((code
== COMPARE
|| COMPARISON_P (x
))
8393 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8394 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8396 if (SCALAR_INT_MODE_P (GET_MODE (x
)))
8398 rtx new_rtx
= make_compound_operation_int (GET_MODE (x
), &x
,
8399 in_code
, &next_code
);
8402 code
= GET_CODE (x
);
8405 /* Now recursively process each operand of this operation. We need to
8406 handle ZERO_EXTEND specially so that we don't lose track of the
8408 if (code
== ZERO_EXTEND
)
8410 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8411 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8412 new_rtx
, GET_MODE (XEXP (x
, 0)));
8415 SUBST (XEXP (x
, 0), new_rtx
);
8419 fmt
= GET_RTX_FORMAT (code
);
8420 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8423 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8424 SUBST (XEXP (x
, i
), new_rtx
);
8426 else if (fmt
[i
] == 'E')
8427 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8429 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8430 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8433 maybe_swap_commutative_operands (x
);
8437 /* Given M see if it is a value that would select a field of bits
8438 within an item, but not the entire word. Return -1 if not.
8439 Otherwise, return the starting position of the field, where 0 is the
8442 *PLEN is set to the length of the field. */
8445 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8447 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8448 int pos
= m
? ctz_hwi (m
) : -1;
8452 /* Now shift off the low-order zero bits and see if we have a
8453 power of two minus 1. */
8454 len
= exact_log2 ((m
>> pos
) + 1);
8463 /* If X refers to a register that equals REG in value, replace these
8464 references with REG. */
8466 canon_reg_for_combine (rtx x
, rtx reg
)
8473 enum rtx_code code
= GET_CODE (x
);
8474 switch (GET_RTX_CLASS (code
))
8477 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8478 if (op0
!= XEXP (x
, 0))
8479 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8484 case RTX_COMM_ARITH
:
8485 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8486 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8487 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8488 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8492 case RTX_COMM_COMPARE
:
8493 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8494 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8495 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8496 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8497 GET_MODE (op0
), op0
, op1
);
8501 case RTX_BITFIELD_OPS
:
8502 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8503 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8504 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8505 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8506 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8507 GET_MODE (op0
), op0
, op1
, op2
);
8513 if (rtx_equal_p (get_last_value (reg
), x
)
8514 || rtx_equal_p (reg
, get_last_value (x
)))
8523 fmt
= GET_RTX_FORMAT (code
);
8525 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8528 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8529 if (op
!= XEXP (x
, i
))
8539 else if (fmt
[i
] == 'E')
8542 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8544 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8545 if (op
!= XVECEXP (x
, i
, j
))
8552 XVECEXP (x
, i
, j
) = op
;
8563 /* Return X converted to MODE. If the value is already truncated to
8564 MODE we can just return a subreg even though in the general case we
8565 would need an explicit truncation. */
8568 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8570 if (!CONST_INT_P (x
)
8571 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8572 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8573 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8575 /* Bit-cast X into an integer mode. */
8576 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8577 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8578 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8582 return gen_lowpart (mode
, x
);
8585 /* See if X can be simplified knowing that we will only refer to it in
8586 MODE and will only refer to those bits that are nonzero in MASK.
8587 If other bits are being computed or if masking operations are done
8588 that select a superset of the bits in MASK, they can sometimes be
8591 Return a possibly simplified expression, but always convert X to
8592 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8594 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8595 are all off in X. This is used when X will be complemented, by either
8596 NOT, NEG, or XOR. */
8599 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8602 enum rtx_code code
= GET_CODE (x
);
8603 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8604 machine_mode op_mode
;
8605 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8608 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8609 code below will do the wrong thing since the mode of such an
8610 expression is VOIDmode.
8612 Also do nothing if X is a CLOBBER; this can happen if X was
8613 the return value from a call to gen_lowpart. */
8614 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8617 /* We want to perform the operation in its present mode unless we know
8618 that the operation is valid in MODE, in which case we do the operation
8620 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8621 && have_insn_for (code
, mode
))
8622 ? mode
: GET_MODE (x
));
8624 /* It is not valid to do a right-shift in a narrower mode
8625 than the one it came in with. */
8626 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8627 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8628 op_mode
= GET_MODE (x
);
8630 /* Truncate MASK to fit OP_MODE. */
8632 mask
&= GET_MODE_MASK (op_mode
);
8634 /* When we have an arithmetic operation, or a shift whose count we
8635 do not know, we need to assume that all bits up to the highest-order
8636 bit in MASK will be needed. This is how we form such a mask. */
8637 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8638 fuller_mask
= HOST_WIDE_INT_M1U
;
8640 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8643 /* Determine what bits of X are guaranteed to be (non)zero. */
8644 nonzero
= nonzero_bits (x
, mode
);
8646 /* If none of the bits in X are needed, return a zero. */
8647 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8650 /* If X is a CONST_INT, return a new one. Do this here since the
8651 test below will fail. */
8652 if (CONST_INT_P (x
))
8654 if (SCALAR_INT_MODE_P (mode
))
8655 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8658 x
= GEN_INT (INTVAL (x
) & mask
);
8659 return gen_lowpart_common (mode
, x
);
8663 /* If X is narrower than MODE and we want all the bits in X's mode, just
8664 get X in the proper mode. */
8665 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8666 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8667 return gen_lowpart (mode
, x
);
8669 /* We can ignore the effect of a SUBREG if it narrows the mode or
8670 if the constant masks to zero all the bits the mode doesn't have. */
8671 if (GET_CODE (x
) == SUBREG
8672 && subreg_lowpart_p (x
)
8673 && ((GET_MODE_SIZE (GET_MODE (x
))
8674 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8676 & GET_MODE_MASK (GET_MODE (x
))
8677 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8678 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8680 /* The arithmetic simplifications here only work for scalar integer modes. */
8681 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8682 return gen_lowpart_or_truncate (mode
, x
);
8687 /* If X is a (clobber (const_int)), return it since we know we are
8688 generating something that won't match. */
8695 x
= expand_compound_operation (x
);
8696 if (GET_CODE (x
) != code
)
8697 return force_to_mode (x
, mode
, mask
, next_select
);
8701 /* Similarly for a truncate. */
8702 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8705 /* If this is an AND with a constant, convert it into an AND
8706 whose constant is the AND of that constant with MASK. If it
8707 remains an AND of MASK, delete it since it is redundant. */
8709 if (CONST_INT_P (XEXP (x
, 1)))
8711 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8712 mask
& INTVAL (XEXP (x
, 1)));
8714 /* If X is still an AND, see if it is an AND with a mask that
8715 is just some low-order bits. If so, and it is MASK, we don't
8718 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8719 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8723 /* If it remains an AND, try making another AND with the bits
8724 in the mode mask that aren't in MASK turned on. If the
8725 constant in the AND is wide enough, this might make a
8726 cheaper constant. */
8728 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8729 && GET_MODE_MASK (GET_MODE (x
)) != mask
8730 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8732 unsigned HOST_WIDE_INT cval
8733 = UINTVAL (XEXP (x
, 1))
8734 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8737 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8738 gen_int_mode (cval
, GET_MODE (x
)));
8739 if (set_src_cost (y
, GET_MODE (x
), optimize_this_for_speed_p
)
8740 < set_src_cost (x
, GET_MODE (x
), optimize_this_for_speed_p
))
8750 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8751 low-order bits (as in an alignment operation) and FOO is already
8752 aligned to that boundary, mask C1 to that boundary as well.
8753 This may eliminate that PLUS and, later, the AND. */
8756 unsigned int width
= GET_MODE_PRECISION (mode
);
8757 unsigned HOST_WIDE_INT smask
= mask
;
8759 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8760 number, sign extend it. */
8762 if (width
< HOST_BITS_PER_WIDE_INT
8763 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8764 smask
|= HOST_WIDE_INT_M1U
<< width
;
8766 if (CONST_INT_P (XEXP (x
, 1))
8767 && pow2p_hwi (- smask
)
8768 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8769 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8770 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8771 (INTVAL (XEXP (x
, 1)) & smask
)),
8772 mode
, smask
, next_select
);
8778 /* Substituting into the operands of a widening MULT is not likely to
8779 create RTL matching a machine insn. */
8781 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8782 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8783 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8784 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8785 && REG_P (XEXP (XEXP (x
, 0), 0))
8786 && REG_P (XEXP (XEXP (x
, 1), 0)))
8787 return gen_lowpart_or_truncate (mode
, x
);
8789 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8790 most significant bit in MASK since carries from those bits will
8791 affect the bits we are interested in. */
8796 /* If X is (minus C Y) where C's least set bit is larger than any bit
8797 in the mask, then we may replace with (neg Y). */
8798 if (CONST_INT_P (XEXP (x
, 0))
8799 && least_bit_hwi (UINTVAL (XEXP (x
, 0))) > mask
)
8801 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8803 return force_to_mode (x
, mode
, mask
, next_select
);
8806 /* Similarly, if C contains every bit in the fuller_mask, then we may
8807 replace with (not Y). */
8808 if (CONST_INT_P (XEXP (x
, 0))
8809 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8811 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8812 XEXP (x
, 1), GET_MODE (x
));
8813 return force_to_mode (x
, mode
, mask
, next_select
);
8821 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8822 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8823 operation which may be a bitfield extraction. Ensure that the
8824 constant we form is not wider than the mode of X. */
8826 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8827 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8828 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8829 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8830 && CONST_INT_P (XEXP (x
, 1))
8831 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8832 + floor_log2 (INTVAL (XEXP (x
, 1))))
8833 < GET_MODE_PRECISION (GET_MODE (x
)))
8834 && (UINTVAL (XEXP (x
, 1))
8835 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8837 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8838 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8840 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8841 XEXP (XEXP (x
, 0), 0), temp
);
8842 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8843 XEXP (XEXP (x
, 0), 1));
8844 return force_to_mode (x
, mode
, mask
, next_select
);
8848 /* For most binary operations, just propagate into the operation and
8849 change the mode if we have an operation of that mode. */
8851 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8852 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8854 /* If we ended up truncating both operands, truncate the result of the
8855 operation instead. */
8856 if (GET_CODE (op0
) == TRUNCATE
8857 && GET_CODE (op1
) == TRUNCATE
)
8859 op0
= XEXP (op0
, 0);
8860 op1
= XEXP (op1
, 0);
8863 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8864 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8866 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8867 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8871 /* For left shifts, do the same, but just for the first operand.
8872 However, we cannot do anything with shifts where we cannot
8873 guarantee that the counts are smaller than the size of the mode
8874 because such a count will have a different meaning in a
8877 if (! (CONST_INT_P (XEXP (x
, 1))
8878 && INTVAL (XEXP (x
, 1)) >= 0
8879 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8880 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8881 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8882 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8885 /* If the shift count is a constant and we can do arithmetic in
8886 the mode of the shift, refine which bits we need. Otherwise, use the
8887 conservative form of the mask. */
8888 if (CONST_INT_P (XEXP (x
, 1))
8889 && INTVAL (XEXP (x
, 1)) >= 0
8890 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8891 && HWI_COMPUTABLE_MODE_P (op_mode
))
8892 mask
>>= INTVAL (XEXP (x
, 1));
8896 op0
= gen_lowpart_or_truncate (op_mode
,
8897 force_to_mode (XEXP (x
, 0), op_mode
,
8898 mask
, next_select
));
8900 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8901 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8905 /* Here we can only do something if the shift count is a constant,
8906 this shift constant is valid for the host, and we can do arithmetic
8909 if (CONST_INT_P (XEXP (x
, 1))
8910 && INTVAL (XEXP (x
, 1)) >= 0
8911 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8912 && HWI_COMPUTABLE_MODE_P (op_mode
))
8914 rtx inner
= XEXP (x
, 0);
8915 unsigned HOST_WIDE_INT inner_mask
;
8917 /* Select the mask of the bits we need for the shift operand. */
8918 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8920 /* We can only change the mode of the shift if we can do arithmetic
8921 in the mode of the shift and INNER_MASK is no wider than the
8922 width of X's mode. */
8923 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8924 op_mode
= GET_MODE (x
);
8926 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8928 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8929 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8932 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8933 shift and AND produces only copies of the sign bit (C2 is one less
8934 than a power of two), we can do this with just a shift. */
8936 if (GET_CODE (x
) == LSHIFTRT
8937 && CONST_INT_P (XEXP (x
, 1))
8938 /* The shift puts one of the sign bit copies in the least significant
8940 && ((INTVAL (XEXP (x
, 1))
8941 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8942 >= GET_MODE_PRECISION (GET_MODE (x
)))
8943 && pow2p_hwi (mask
+ 1)
8944 /* Number of bits left after the shift must be more than the mask
8946 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8947 <= GET_MODE_PRECISION (GET_MODE (x
)))
8948 /* Must be more sign bit copies than the mask needs. */
8949 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8950 >= exact_log2 (mask
+ 1)))
8951 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8952 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8953 - exact_log2 (mask
+ 1)));
8958 /* If we are just looking for the sign bit, we don't need this shift at
8959 all, even if it has a variable count. */
8960 if (val_signbit_p (GET_MODE (x
), mask
))
8961 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8963 /* If this is a shift by a constant, get a mask that contains those bits
8964 that are not copies of the sign bit. We then have two cases: If
8965 MASK only includes those bits, this can be a logical shift, which may
8966 allow simplifications. If MASK is a single-bit field not within
8967 those bits, we are requesting a copy of the sign bit and hence can
8968 shift the sign bit to the appropriate location. */
8970 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8971 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8975 /* If the considered data is wider than HOST_WIDE_INT, we can't
8976 represent a mask for all its bits in a single scalar.
8977 But we only care about the lower bits, so calculate these. */
8979 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8981 nonzero
= HOST_WIDE_INT_M1U
;
8983 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8984 is the number of bits a full-width mask would have set.
8985 We need only shift if these are fewer than nonzero can
8986 hold. If not, we must keep all bits set in nonzero. */
8988 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8989 < HOST_BITS_PER_WIDE_INT
)
8990 nonzero
>>= INTVAL (XEXP (x
, 1))
8991 + HOST_BITS_PER_WIDE_INT
8992 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8996 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8997 nonzero
>>= INTVAL (XEXP (x
, 1));
9000 if ((mask
& ~nonzero
) == 0)
9002 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
9003 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
9004 if (GET_CODE (x
) != ASHIFTRT
)
9005 return force_to_mode (x
, mode
, mask
, next_select
);
9008 else if ((i
= exact_log2 (mask
)) >= 0)
9010 x
= simplify_shift_const
9011 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
9012 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
9014 if (GET_CODE (x
) != ASHIFTRT
)
9015 return force_to_mode (x
, mode
, mask
, next_select
);
9019 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9020 even if the shift count isn't a constant. */
9022 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
9023 XEXP (x
, 0), XEXP (x
, 1));
9027 /* If this is a zero- or sign-extension operation that just affects bits
9028 we don't care about, remove it. Be sure the call above returned
9029 something that is still a shift. */
9031 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
9032 && CONST_INT_P (XEXP (x
, 1))
9033 && INTVAL (XEXP (x
, 1)) >= 0
9034 && (INTVAL (XEXP (x
, 1))
9035 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
9036 && GET_CODE (XEXP (x
, 0)) == ASHIFT
9037 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
9038 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
9045 /* If the shift count is constant and we can do computations
9046 in the mode of X, compute where the bits we care about are.
9047 Otherwise, we can't do anything. Don't change the mode of
9048 the shift or propagate MODE into the shift, though. */
9049 if (CONST_INT_P (XEXP (x
, 1))
9050 && INTVAL (XEXP (x
, 1)) >= 0)
9052 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
9054 gen_int_mode (mask
, GET_MODE (x
)),
9056 if (temp
&& CONST_INT_P (temp
))
9057 x
= simplify_gen_binary (code
, GET_MODE (x
),
9058 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
9059 INTVAL (temp
), next_select
),
9065 /* If we just want the low-order bit, the NEG isn't needed since it
9066 won't change the low-order bit. */
9068 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
9070 /* We need any bits less significant than the most significant bit in
9071 MASK since carries from those bits will affect the bits we are
9077 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9078 same as the XOR case above. Ensure that the constant we form is not
9079 wider than the mode of X. */
9081 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
9082 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
9083 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
9084 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
9085 < GET_MODE_PRECISION (GET_MODE (x
)))
9086 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
9088 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
9090 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
9091 XEXP (XEXP (x
, 0), 0), temp
);
9092 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
9093 temp
, XEXP (XEXP (x
, 0), 1));
9095 return force_to_mode (x
, mode
, mask
, next_select
);
9098 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9099 use the full mask inside the NOT. */
9103 op0
= gen_lowpart_or_truncate (op_mode
,
9104 force_to_mode (XEXP (x
, 0), mode
, mask
,
9106 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
9107 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
9111 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9112 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9113 which is equal to STORE_FLAG_VALUE. */
9114 if ((mask
& ~STORE_FLAG_VALUE
) == 0
9115 && XEXP (x
, 1) == const0_rtx
9116 && GET_MODE (XEXP (x
, 0)) == mode
9117 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
9118 && (nonzero_bits (XEXP (x
, 0), mode
)
9119 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
9120 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9125 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9126 written in a narrower mode. We play it safe and do not do so. */
9128 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
9129 force_to_mode (XEXP (x
, 1), mode
,
9130 mask
, next_select
));
9131 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
9132 force_to_mode (XEXP (x
, 2), mode
,
9133 mask
, next_select
));
9134 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9135 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
9136 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9144 /* Ensure we return a value of the proper mode. */
9145 return gen_lowpart_or_truncate (mode
, x
);
9148 /* Return nonzero if X is an expression that has one of two values depending on
9149 whether some other value is zero or nonzero. In that case, we return the
9150 value that is being tested, *PTRUE is set to the value if the rtx being
9151 returned has a nonzero value, and *PFALSE is set to the other alternative.
9153 If we return zero, we set *PTRUE and *PFALSE to X. */
9156 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9158 machine_mode mode
= GET_MODE (x
);
9159 enum rtx_code code
= GET_CODE (x
);
9160 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9161 unsigned HOST_WIDE_INT nz
;
9163 /* If we are comparing a value against zero, we are done. */
9164 if ((code
== NE
|| code
== EQ
)
9165 && XEXP (x
, 1) == const0_rtx
)
9167 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9168 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9172 /* If this is a unary operation whose operand has one of two values, apply
9173 our opcode to compute those values. */
9174 else if (UNARY_P (x
)
9175 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9177 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9178 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9179 GET_MODE (XEXP (x
, 0)));
9183 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9184 make can't possibly match and would suppress other optimizations. */
9185 else if (code
== COMPARE
)
9188 /* If this is a binary operation, see if either side has only one of two
9189 values. If either one does or if both do and they are conditional on
9190 the same value, compute the new true and false values. */
9191 else if (BINARY_P (x
))
9193 rtx op0
= XEXP (x
, 0);
9194 rtx op1
= XEXP (x
, 1);
9195 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9196 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9198 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9199 && (REG_P (op0
) || REG_P (op1
)))
9201 /* Try to enable a simplification by undoing work done by
9202 if_then_else_cond if it converted a REG into something more
9207 true0
= false0
= op0
;
9212 true1
= false1
= op1
;
9216 if ((cond0
!= 0 || cond1
!= 0)
9217 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9219 /* If if_then_else_cond returned zero, then true/false are the
9220 same rtl. We must copy one of them to prevent invalid rtl
9223 true0
= copy_rtx (true0
);
9224 else if (cond1
== 0)
9225 true1
= copy_rtx (true1
);
9227 if (COMPARISON_P (x
))
9229 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9231 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9236 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9237 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9240 return cond0
? cond0
: cond1
;
9243 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9244 operands is zero when the other is nonzero, and vice-versa,
9245 and STORE_FLAG_VALUE is 1 or -1. */
9247 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9248 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9250 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9252 rtx op0
= XEXP (XEXP (x
, 0), 1);
9253 rtx op1
= XEXP (XEXP (x
, 1), 1);
9255 cond0
= XEXP (XEXP (x
, 0), 0);
9256 cond1
= XEXP (XEXP (x
, 1), 0);
9258 if (COMPARISON_P (cond0
)
9259 && COMPARISON_P (cond1
)
9260 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9261 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9262 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9263 || ((swap_condition (GET_CODE (cond0
))
9264 == reversed_comparison_code (cond1
, NULL
))
9265 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9266 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9267 && ! side_effects_p (x
))
9269 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9270 *pfalse
= simplify_gen_binary (MULT
, mode
,
9272 ? simplify_gen_unary (NEG
, mode
,
9280 /* Similarly for MULT, AND and UMIN, except that for these the result
9282 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9283 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9284 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9286 cond0
= XEXP (XEXP (x
, 0), 0);
9287 cond1
= XEXP (XEXP (x
, 1), 0);
9289 if (COMPARISON_P (cond0
)
9290 && COMPARISON_P (cond1
)
9291 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9292 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9293 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9294 || ((swap_condition (GET_CODE (cond0
))
9295 == reversed_comparison_code (cond1
, NULL
))
9296 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9297 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9298 && ! side_effects_p (x
))
9300 *ptrue
= *pfalse
= const0_rtx
;
9306 else if (code
== IF_THEN_ELSE
)
9308 /* If we have IF_THEN_ELSE already, extract the condition and
9309 canonicalize it if it is NE or EQ. */
9310 cond0
= XEXP (x
, 0);
9311 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9312 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9313 return XEXP (cond0
, 0);
9314 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9316 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9317 return XEXP (cond0
, 0);
9323 /* If X is a SUBREG, we can narrow both the true and false values
9324 if the inner expression, if there is a condition. */
9325 else if (code
== SUBREG
9326 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9329 true0
= simplify_gen_subreg (mode
, true0
,
9330 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9331 false0
= simplify_gen_subreg (mode
, false0
,
9332 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9333 if (true0
&& false0
)
9341 /* If X is a constant, this isn't special and will cause confusions
9342 if we treat it as such. Likewise if it is equivalent to a constant. */
9343 else if (CONSTANT_P (x
)
9344 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9347 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9348 will be least confusing to the rest of the compiler. */
9349 else if (mode
== BImode
)
9351 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9355 /* If X is known to be either 0 or -1, those are the true and
9356 false values when testing X. */
9357 else if (x
== constm1_rtx
|| x
== const0_rtx
9358 || (mode
!= VOIDmode
&& mode
!= BLKmode
9359 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9361 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9365 /* Likewise for 0 or a single bit. */
9366 else if (HWI_COMPUTABLE_MODE_P (mode
)
9367 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9369 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9373 /* Otherwise fail; show no condition with true and false values the same. */
9374 *ptrue
= *pfalse
= x
;
9378 /* Return the value of expression X given the fact that condition COND
9379 is known to be true when applied to REG as its first operand and VAL
9380 as its second. X is known to not be shared and so can be modified in
9383 We only handle the simplest cases, and specifically those cases that
9384 arise with IF_THEN_ELSE expressions. */
9387 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9389 enum rtx_code code
= GET_CODE (x
);
9393 if (side_effects_p (x
))
9396 /* If either operand of the condition is a floating point value,
9397 then we have to avoid collapsing an EQ comparison. */
9399 && rtx_equal_p (x
, reg
)
9400 && ! FLOAT_MODE_P (GET_MODE (x
))
9401 && ! FLOAT_MODE_P (GET_MODE (val
)))
9404 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9407 /* If X is (abs REG) and we know something about REG's relationship
9408 with zero, we may be able to simplify this. */
9410 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9413 case GE
: case GT
: case EQ
:
9416 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9418 GET_MODE (XEXP (x
, 0)));
9423 /* The only other cases we handle are MIN, MAX, and comparisons if the
9424 operands are the same as REG and VAL. */
9426 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9428 if (rtx_equal_p (XEXP (x
, 0), val
))
9430 std::swap (val
, reg
);
9431 cond
= swap_condition (cond
);
9434 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9436 if (COMPARISON_P (x
))
9438 if (comparison_dominates_p (cond
, code
))
9439 return const_true_rtx
;
9441 code
= reversed_comparison_code (x
, NULL
);
9443 && comparison_dominates_p (cond
, code
))
9448 else if (code
== SMAX
|| code
== SMIN
9449 || code
== UMIN
|| code
== UMAX
)
9451 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9453 /* Do not reverse the condition when it is NE or EQ.
9454 This is because we cannot conclude anything about
9455 the value of 'SMAX (x, y)' when x is not equal to y,
9456 but we can when x equals y. */
9457 if ((code
== SMAX
|| code
== UMAX
)
9458 && ! (cond
== EQ
|| cond
== NE
))
9459 cond
= reverse_condition (cond
);
9464 return unsignedp
? x
: XEXP (x
, 1);
9466 return unsignedp
? x
: XEXP (x
, 0);
9468 return unsignedp
? XEXP (x
, 1) : x
;
9470 return unsignedp
? XEXP (x
, 0) : x
;
9477 else if (code
== SUBREG
)
9479 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9480 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9482 if (SUBREG_REG (x
) != r
)
9484 /* We must simplify subreg here, before we lose track of the
9485 original inner_mode. */
9486 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9487 inner_mode
, SUBREG_BYTE (x
));
9491 SUBST (SUBREG_REG (x
), r
);
9496 /* We don't have to handle SIGN_EXTEND here, because even in the
9497 case of replacing something with a modeless CONST_INT, a
9498 CONST_INT is already (supposed to be) a valid sign extension for
9499 its narrower mode, which implies it's already properly
9500 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9501 story is different. */
9502 else if (code
== ZERO_EXTEND
)
9504 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9505 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9507 if (XEXP (x
, 0) != r
)
9509 /* We must simplify the zero_extend here, before we lose
9510 track of the original inner_mode. */
9511 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9516 SUBST (XEXP (x
, 0), r
);
9522 fmt
= GET_RTX_FORMAT (code
);
9523 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9526 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9527 else if (fmt
[i
] == 'E')
9528 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9529 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9536 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9537 assignment as a field assignment. */
9540 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9542 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9544 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9546 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9548 /* For big endian, adjust the memory offset. */
9549 if (BYTES_BIG_ENDIAN
)
9550 x
= adjust_address_nv (x
, GET_MODE (y
),
9551 -subreg_lowpart_offset (GET_MODE (x
),
9554 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9557 if (x
== y
|| rtx_equal_p (x
, y
))
9560 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9563 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9564 Note that all SUBREGs of MEM are paradoxical; otherwise they
9565 would have been rewritten. */
9566 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9567 && MEM_P (SUBREG_REG (y
))
9568 && rtx_equal_p (SUBREG_REG (y
),
9569 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9572 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9573 && MEM_P (SUBREG_REG (x
))
9574 && rtx_equal_p (SUBREG_REG (x
),
9575 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9578 /* We used to see if get_last_value of X and Y were the same but that's
9579 not correct. In one direction, we'll cause the assignment to have
9580 the wrong destination and in the case, we'll import a register into this
9581 insn that might have already have been dead. So fail if none of the
9582 above cases are true. */
9586 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9587 Return that assignment if so.
9589 We only handle the most common cases. */
9592 make_field_assignment (rtx x
)
9594 rtx dest
= SET_DEST (x
);
9595 rtx src
= SET_SRC (x
);
9600 unsigned HOST_WIDE_INT len
;
9604 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9605 a clear of a one-bit field. We will have changed it to
9606 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9609 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9610 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9611 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9612 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9614 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9617 return gen_rtx_SET (assign
, const0_rtx
);
9621 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9622 && subreg_lowpart_p (XEXP (src
, 0))
9623 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9624 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9625 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9626 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9627 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9628 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9630 assign
= make_extraction (VOIDmode
, dest
, 0,
9631 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9634 return gen_rtx_SET (assign
, const0_rtx
);
9638 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9640 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9641 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9642 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9644 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9647 return gen_rtx_SET (assign
, const1_rtx
);
9651 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9652 SRC is an AND with all bits of that field set, then we can discard
9654 if (GET_CODE (dest
) == ZERO_EXTRACT
9655 && CONST_INT_P (XEXP (dest
, 1))
9656 && GET_CODE (src
) == AND
9657 && CONST_INT_P (XEXP (src
, 1)))
9659 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9660 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9661 unsigned HOST_WIDE_INT ze_mask
;
9663 if (width
>= HOST_BITS_PER_WIDE_INT
)
9666 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9668 /* Complete overlap. We can remove the source AND. */
9669 if ((and_mask
& ze_mask
) == ze_mask
)
9670 return gen_rtx_SET (dest
, XEXP (src
, 0));
9672 /* Partial overlap. We can reduce the source AND. */
9673 if ((and_mask
& ze_mask
) != and_mask
)
9675 mode
= GET_MODE (src
);
9676 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9677 gen_int_mode (and_mask
& ze_mask
, mode
));
9678 return gen_rtx_SET (dest
, src
);
9682 /* The other case we handle is assignments into a constant-position
9683 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9684 a mask that has all one bits except for a group of zero bits and
9685 OTHER is known to have zeros where C1 has ones, this is such an
9686 assignment. Compute the position and length from C1. Shift OTHER
9687 to the appropriate position, force it to the required mode, and
9688 make the extraction. Check for the AND in both operands. */
9690 /* One or more SUBREGs might obscure the constant-position field
9691 assignment. The first one we are likely to encounter is an outer
9692 narrowing SUBREG, which we can just strip for the purposes of
9693 identifying the constant-field assignment. */
9694 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9695 src
= SUBREG_REG (src
);
9697 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9700 rhs
= expand_compound_operation (XEXP (src
, 0));
9701 lhs
= expand_compound_operation (XEXP (src
, 1));
9703 if (GET_CODE (rhs
) == AND
9704 && CONST_INT_P (XEXP (rhs
, 1))
9705 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9706 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9707 /* The second SUBREG that might get in the way is a paradoxical
9708 SUBREG around the first operand of the AND. We want to
9709 pretend the operand is as wide as the destination here. We
9710 do this by adjusting the MEM to wider mode for the sole
9711 purpose of the call to rtx_equal_for_field_assignment_p. Also
9712 note this trick only works for MEMs. */
9713 else if (GET_CODE (rhs
) == AND
9714 && paradoxical_subreg_p (XEXP (rhs
, 0))
9715 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9716 && CONST_INT_P (XEXP (rhs
, 1))
9717 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9719 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9720 else if (GET_CODE (lhs
) == AND
9721 && CONST_INT_P (XEXP (lhs
, 1))
9722 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9723 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9724 /* The second SUBREG that might get in the way is a paradoxical
9725 SUBREG around the first operand of the AND. We want to
9726 pretend the operand is as wide as the destination here. We
9727 do this by adjusting the MEM to wider mode for the sole
9728 purpose of the call to rtx_equal_for_field_assignment_p. Also
9729 note this trick only works for MEMs. */
9730 else if (GET_CODE (lhs
) == AND
9731 && paradoxical_subreg_p (XEXP (lhs
, 0))
9732 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9733 && CONST_INT_P (XEXP (lhs
, 1))
9734 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9736 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9740 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9741 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9742 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9743 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9746 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9750 /* The mode to use for the source is the mode of the assignment, or of
9751 what is inside a possible STRICT_LOW_PART. */
9752 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9753 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9755 /* Shift OTHER right POS places and make it the source, restricting it
9756 to the proper length and mode. */
9758 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9762 src
= force_to_mode (src
, mode
,
9763 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9765 : (HOST_WIDE_INT_1U
<< len
) - 1,
9768 /* If SRC is masked by an AND that does not make a difference in
9769 the value being stored, strip it. */
9770 if (GET_CODE (assign
) == ZERO_EXTRACT
9771 && CONST_INT_P (XEXP (assign
, 1))
9772 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9773 && GET_CODE (src
) == AND
9774 && CONST_INT_P (XEXP (src
, 1))
9775 && UINTVAL (XEXP (src
, 1))
9776 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9777 src
= XEXP (src
, 0);
9779 return gen_rtx_SET (assign
, src
);
9782 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9786 apply_distributive_law (rtx x
)
9788 enum rtx_code code
= GET_CODE (x
);
9789 enum rtx_code inner_code
;
9790 rtx lhs
, rhs
, other
;
9793 /* Distributivity is not true for floating point as it can change the
9794 value. So we don't do it unless -funsafe-math-optimizations. */
9795 if (FLOAT_MODE_P (GET_MODE (x
))
9796 && ! flag_unsafe_math_optimizations
)
9799 /* The outer operation can only be one of the following: */
9800 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9801 && code
!= PLUS
&& code
!= MINUS
)
9807 /* If either operand is a primitive we can't do anything, so get out
9809 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9812 lhs
= expand_compound_operation (lhs
);
9813 rhs
= expand_compound_operation (rhs
);
9814 inner_code
= GET_CODE (lhs
);
9815 if (inner_code
!= GET_CODE (rhs
))
9818 /* See if the inner and outer operations distribute. */
9825 /* These all distribute except over PLUS. */
9826 if (code
== PLUS
|| code
== MINUS
)
9831 if (code
!= PLUS
&& code
!= MINUS
)
9836 /* This is also a multiply, so it distributes over everything. */
9839 /* This used to handle SUBREG, but this turned out to be counter-
9840 productive, since (subreg (op ...)) usually is not handled by
9841 insn patterns, and this "optimization" therefore transformed
9842 recognizable patterns into unrecognizable ones. Therefore the
9843 SUBREG case was removed from here.
9845 It is possible that distributing SUBREG over arithmetic operations
9846 leads to an intermediate result than can then be optimized further,
9847 e.g. by moving the outer SUBREG to the other side of a SET as done
9848 in simplify_set. This seems to have been the original intent of
9849 handling SUBREGs here.
9851 However, with current GCC this does not appear to actually happen,
9852 at least on major platforms. If some case is found where removing
9853 the SUBREG case here prevents follow-on optimizations, distributing
9854 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9860 /* Set LHS and RHS to the inner operands (A and B in the example
9861 above) and set OTHER to the common operand (C in the example).
9862 There is only one way to do this unless the inner operation is
9864 if (COMMUTATIVE_ARITH_P (lhs
)
9865 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9866 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9867 else if (COMMUTATIVE_ARITH_P (lhs
)
9868 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9869 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9870 else if (COMMUTATIVE_ARITH_P (lhs
)
9871 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9872 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9873 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9874 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9878 /* Form the new inner operation, seeing if it simplifies first. */
9879 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9881 /* There is one exception to the general way of distributing:
9882 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9883 if (code
== XOR
&& inner_code
== IOR
)
9886 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9889 /* We may be able to continuing distributing the result, so call
9890 ourselves recursively on the inner operation before forming the
9891 outer operation, which we return. */
9892 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9893 apply_distributive_law (tem
), other
);
9896 /* See if X is of the form (* (+ A B) C), and if so convert to
9897 (+ (* A C) (* B C)) and try to simplify.
9899 Most of the time, this results in no change. However, if some of
9900 the operands are the same or inverses of each other, simplifications
9903 For example, (and (ior A B) (not B)) can occur as the result of
9904 expanding a bit field assignment. When we apply the distributive
9905 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9906 which then simplifies to (and (A (not B))).
9908 Note that no checks happen on the validity of applying the inverse
9909 distributive law. This is pointless since we can do it in the
9910 few places where this routine is called.
9912 N is the index of the term that is decomposed (the arithmetic operation,
9913 i.e. (+ A B) in the first example above). !N is the index of the term that
9914 is distributed, i.e. of C in the first example above. */
9916 distribute_and_simplify_rtx (rtx x
, int n
)
9919 enum rtx_code outer_code
, inner_code
;
9920 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9922 /* Distributivity is not true for floating point as it can change the
9923 value. So we don't do it unless -funsafe-math-optimizations. */
9924 if (FLOAT_MODE_P (GET_MODE (x
))
9925 && ! flag_unsafe_math_optimizations
)
9928 decomposed
= XEXP (x
, n
);
9929 if (!ARITHMETIC_P (decomposed
))
9932 mode
= GET_MODE (x
);
9933 outer_code
= GET_CODE (x
);
9934 distributed
= XEXP (x
, !n
);
9936 inner_code
= GET_CODE (decomposed
);
9937 inner_op0
= XEXP (decomposed
, 0);
9938 inner_op1
= XEXP (decomposed
, 1);
9940 /* Special case (and (xor B C) (not A)), which is equivalent to
9941 (xor (ior A B) (ior A C)) */
9942 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9944 distributed
= XEXP (distributed
, 0);
9950 /* Distribute the second term. */
9951 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9952 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9956 /* Distribute the first term. */
9957 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9958 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9961 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9963 if (GET_CODE (tmp
) != outer_code
9964 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
9965 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
9971 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9972 in MODE. Return an equivalent form, if different from (and VAROP
9973 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9976 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9977 unsigned HOST_WIDE_INT constop
)
9979 unsigned HOST_WIDE_INT nonzero
;
9980 unsigned HOST_WIDE_INT orig_constop
;
9985 orig_constop
= constop
;
9986 if (GET_CODE (varop
) == CLOBBER
)
9989 /* Simplify VAROP knowing that we will be only looking at some of the
9992 Note by passing in CONSTOP, we guarantee that the bits not set in
9993 CONSTOP are not significant and will never be examined. We must
9994 ensure that is the case by explicitly masking out those bits
9995 before returning. */
9996 varop
= force_to_mode (varop
, mode
, constop
, 0);
9998 /* If VAROP is a CLOBBER, we will fail so return it. */
9999 if (GET_CODE (varop
) == CLOBBER
)
10002 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10003 to VAROP and return the new constant. */
10004 if (CONST_INT_P (varop
))
10005 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
10007 /* See what bits may be nonzero in VAROP. Unlike the general case of
10008 a call to nonzero_bits, here we don't care about bits outside
10011 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
10013 /* Turn off all bits in the constant that are known to already be zero.
10014 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10015 which is tested below. */
10017 constop
&= nonzero
;
10019 /* If we don't have any bits left, return zero. */
10023 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10024 a power of two, we can replace this with an ASHIFT. */
10025 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
10026 && (i
= exact_log2 (constop
)) >= 0)
10027 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
10029 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10030 or XOR, then try to apply the distributive law. This may eliminate
10031 operations if either branch can be simplified because of the AND.
10032 It may also make some cases more complex, but those cases probably
10033 won't match a pattern either with or without this. */
10035 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
10039 apply_distributive_law
10040 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
10041 simplify_and_const_int (NULL_RTX
,
10045 simplify_and_const_int (NULL_RTX
,
10050 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10051 the AND and see if one of the operands simplifies to zero. If so, we
10052 may eliminate it. */
10054 if (GET_CODE (varop
) == PLUS
10055 && pow2p_hwi (constop
+ 1))
10059 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
10060 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
10061 if (o0
== const0_rtx
)
10063 if (o1
== const0_rtx
)
10067 /* Make a SUBREG if necessary. If we can't make it, fail. */
10068 varop
= gen_lowpart (mode
, varop
);
10069 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10072 /* If we are only masking insignificant bits, return VAROP. */
10073 if (constop
== nonzero
)
10076 if (varop
== orig_varop
&& constop
== orig_constop
)
10079 /* Otherwise, return an AND. */
10080 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
10084 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10087 Return an equivalent form, if different from X. Otherwise, return X. If
10088 X is zero, we are to always construct the equivalent form. */
10091 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
10092 unsigned HOST_WIDE_INT constop
)
10094 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
10099 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
10100 gen_int_mode (constop
, mode
));
10101 if (GET_MODE (x
) != mode
)
10102 x
= gen_lowpart (mode
, x
);
10106 /* Given a REG, X, compute which bits in X can be nonzero.
10107 We don't care about bits outside of those defined in MODE.
10109 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10110 a shift, AND, or zero_extract, we can do better. */
10113 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
10114 const_rtx known_x ATTRIBUTE_UNUSED
,
10115 machine_mode known_mode ATTRIBUTE_UNUSED
,
10116 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
10117 unsigned HOST_WIDE_INT
*nonzero
)
10120 reg_stat_type
*rsp
;
10122 /* If X is a register whose nonzero bits value is current, use it.
10123 Otherwise, if X is a register whose value we can find, use that
10124 value. Otherwise, use the previously-computed global nonzero bits
10125 for this register. */
10127 rsp
= ®_stat
[REGNO (x
)];
10128 if (rsp
->last_set_value
!= 0
10129 && (rsp
->last_set_mode
== mode
10130 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
10131 && GET_MODE_CLASS (mode
) == MODE_INT
))
10132 && ((rsp
->last_set_label
>= label_tick_ebb_start
10133 && rsp
->last_set_label
< label_tick
)
10134 || (rsp
->last_set_label
== label_tick
10135 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10136 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10137 && REGNO (x
) < reg_n_sets_max
10138 && REG_N_SETS (REGNO (x
)) == 1
10139 && !REGNO_REG_SET_P
10140 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10143 /* Note that, even if the precision of last_set_mode is lower than that
10144 of mode, record_value_for_reg invoked nonzero_bits on the register
10145 with nonzero_bits_mode (because last_set_mode is necessarily integral
10146 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10147 are all valid, hence in mode too since nonzero_bits_mode is defined
10148 to the largest HWI_COMPUTABLE_MODE_P mode. */
10149 *nonzero
&= rsp
->last_set_nonzero_bits
;
10153 tem
= get_last_value (x
);
10156 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10157 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
10158 GET_MODE_PRECISION (mode
));
10163 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10165 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10167 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
10168 /* We don't know anything about the upper bits. */
10169 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
10177 /* Return the number of bits at the high-order end of X that are known to
10178 be equal to the sign bit. X will be used in mode MODE; if MODE is
10179 VOIDmode, X will be used in its own mode. The returned value will always
10180 be between 1 and the number of bits in MODE. */
10183 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
10184 const_rtx known_x ATTRIBUTE_UNUSED
,
10185 machine_mode known_mode
10187 unsigned int known_ret ATTRIBUTE_UNUSED
,
10188 unsigned int *result
)
10191 reg_stat_type
*rsp
;
10193 rsp
= ®_stat
[REGNO (x
)];
10194 if (rsp
->last_set_value
!= 0
10195 && rsp
->last_set_mode
== mode
10196 && ((rsp
->last_set_label
>= label_tick_ebb_start
10197 && rsp
->last_set_label
< label_tick
)
10198 || (rsp
->last_set_label
== label_tick
10199 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10200 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10201 && REGNO (x
) < reg_n_sets_max
10202 && REG_N_SETS (REGNO (x
)) == 1
10203 && !REGNO_REG_SET_P
10204 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10207 *result
= rsp
->last_set_sign_bit_copies
;
10211 tem
= get_last_value (x
);
10215 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10216 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
10217 *result
= rsp
->sign_bit_copies
;
10222 /* Return the number of "extended" bits there are in X, when interpreted
10223 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10224 unsigned quantities, this is the number of high-order zero bits.
10225 For signed quantities, this is the number of copies of the sign bit
10226 minus 1. In both case, this function returns the number of "spare"
10227 bits. For example, if two quantities for which this function returns
10228 at least 1 are added, the addition is known not to overflow.
10230 This function will always return 0 unless called during combine, which
10231 implies that it must be called from a define_split. */
10234 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10236 if (nonzero_sign_valid
== 0)
10240 ? (HWI_COMPUTABLE_MODE_P (mode
)
10241 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
10242 - floor_log2 (nonzero_bits (x
, mode
)))
10244 : num_sign_bit_copies (x
, mode
) - 1);
10247 /* This function is called from `simplify_shift_const' to merge two
10248 outer operations. Specifically, we have already found that we need
10249 to perform operation *POP0 with constant *PCONST0 at the outermost
10250 position. We would now like to also perform OP1 with constant CONST1
10251 (with *POP0 being done last).
10253 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10254 the resulting operation. *PCOMP_P is set to 1 if we would need to
10255 complement the innermost operand, otherwise it is unchanged.
10257 MODE is the mode in which the operation will be done. No bits outside
10258 the width of this mode matter. It is assumed that the width of this mode
10259 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10261 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10262 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10263 result is simply *PCONST0.
10265 If the resulting operation cannot be expressed as one operation, we
10266 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10269 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10271 enum rtx_code op0
= *pop0
;
10272 HOST_WIDE_INT const0
= *pconst0
;
10274 const0
&= GET_MODE_MASK (mode
);
10275 const1
&= GET_MODE_MASK (mode
);
10277 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10281 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10284 if (op1
== UNKNOWN
|| op0
== SET
)
10287 else if (op0
== UNKNOWN
)
10288 op0
= op1
, const0
= const1
;
10290 else if (op0
== op1
)
10314 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10315 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10318 /* If the two constants aren't the same, we can't do anything. The
10319 remaining six cases can all be done. */
10320 else if (const0
!= const1
)
10328 /* (a & b) | b == b */
10330 else /* op1 == XOR */
10331 /* (a ^ b) | b == a | b */
10337 /* (a & b) ^ b == (~a) & b */
10338 op0
= AND
, *pcomp_p
= 1;
10339 else /* op1 == IOR */
10340 /* (a | b) ^ b == a & ~b */
10341 op0
= AND
, const0
= ~const0
;
10346 /* (a | b) & b == b */
10348 else /* op1 == XOR */
10349 /* (a ^ b) & b) == (~a) & b */
10356 /* Check for NO-OP cases. */
10357 const0
&= GET_MODE_MASK (mode
);
10359 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10361 else if (const0
== 0 && op0
== AND
)
10363 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10369 /* ??? Slightly redundant with the above mask, but not entirely.
10370 Moving this above means we'd have to sign-extend the mode mask
10371 for the final test. */
10372 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10373 *pconst0
= trunc_int_for_mode (const0
, mode
);
10378 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10379 the shift in. The original shift operation CODE is performed on OP in
10380 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10381 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10382 result of the shift is subject to operation OUTER_CODE with operand
10385 static machine_mode
10386 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10387 machine_mode orig_mode
, machine_mode mode
,
10388 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10390 if (orig_mode
== mode
)
10392 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10394 /* In general we can't perform in wider mode for right shift and rotate. */
10398 /* We can still widen if the bits brought in from the left are identical
10399 to the sign bit of ORIG_MODE. */
10400 if (num_sign_bit_copies (op
, mode
)
10401 > (unsigned) (GET_MODE_PRECISION (mode
)
10402 - GET_MODE_PRECISION (orig_mode
)))
10407 /* Similarly here but with zero bits. */
10408 if (HWI_COMPUTABLE_MODE_P (mode
)
10409 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10412 /* We can also widen if the bits brought in will be masked off. This
10413 operation is performed in ORIG_MODE. */
10414 if (outer_code
== AND
)
10416 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10419 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10428 gcc_unreachable ();
10435 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10436 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10437 if we cannot simplify it. Otherwise, return a simplified value.
10439 The shift is normally computed in the widest mode we find in VAROP, as
10440 long as it isn't a different number of words than RESULT_MODE. Exceptions
10441 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10444 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10445 rtx varop
, int orig_count
)
10447 enum rtx_code orig_code
= code
;
10448 rtx orig_varop
= varop
;
10450 machine_mode mode
= result_mode
;
10451 machine_mode shift_mode
, tmode
;
10452 unsigned int mode_words
10453 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10454 /* We form (outer_op (code varop count) (outer_const)). */
10455 enum rtx_code outer_op
= UNKNOWN
;
10456 HOST_WIDE_INT outer_const
= 0;
10457 int complement_p
= 0;
10460 /* Make sure and truncate the "natural" shift on the way in. We don't
10461 want to do this inside the loop as it makes it more difficult to
10463 if (SHIFT_COUNT_TRUNCATED
)
10464 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10466 /* If we were given an invalid count, don't do anything except exactly
10467 what was requested. */
10469 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10472 count
= orig_count
;
10474 /* Unless one of the branches of the `if' in this loop does a `continue',
10475 we will `break' the loop after the `if'. */
10479 /* If we have an operand of (clobber (const_int 0)), fail. */
10480 if (GET_CODE (varop
) == CLOBBER
)
10483 /* Convert ROTATERT to ROTATE. */
10484 if (code
== ROTATERT
)
10486 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10488 count
= bitsize
- count
;
10491 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10492 mode
, outer_op
, outer_const
);
10493 machine_mode shift_unit_mode
= GET_MODE_INNER (shift_mode
);
10495 /* Handle cases where the count is greater than the size of the mode
10496 minus 1. For ASHIFT, use the size minus one as the count (this can
10497 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10498 take the count modulo the size. For other shifts, the result is
10501 Since these shifts are being produced by the compiler by combining
10502 multiple operations, each of which are defined, we know what the
10503 result is supposed to be. */
10505 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10507 if (code
== ASHIFTRT
)
10508 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10509 else if (code
== ROTATE
|| code
== ROTATERT
)
10510 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10513 /* We can't simply return zero because there may be an
10515 varop
= const0_rtx
;
10521 /* If we discovered we had to complement VAROP, leave. Making a NOT
10522 here would cause an infinite loop. */
10526 if (shift_mode
== shift_unit_mode
)
10528 /* An arithmetic right shift of a quantity known to be -1 or 0
10530 if (code
== ASHIFTRT
10531 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10532 == GET_MODE_PRECISION (shift_unit_mode
)))
10538 /* If we are doing an arithmetic right shift and discarding all but
10539 the sign bit copies, this is equivalent to doing a shift by the
10540 bitsize minus one. Convert it into that shift because it will
10541 often allow other simplifications. */
10543 if (code
== ASHIFTRT
10544 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10545 >= GET_MODE_PRECISION (shift_unit_mode
)))
10546 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10548 /* We simplify the tests below and elsewhere by converting
10549 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10550 `make_compound_operation' will convert it to an ASHIFTRT for
10551 those machines (such as VAX) that don't have an LSHIFTRT. */
10552 if (code
== ASHIFTRT
10553 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10554 && val_signbit_known_clear_p (shift_unit_mode
,
10555 nonzero_bits (varop
,
10559 if (((code
== LSHIFTRT
10560 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10561 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10563 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10564 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10565 & GET_MODE_MASK (shift_unit_mode
))))
10566 && !side_effects_p (varop
))
10567 varop
= const0_rtx
;
10570 switch (GET_CODE (varop
))
10576 new_rtx
= expand_compound_operation (varop
);
10577 if (new_rtx
!= varop
)
10585 /* The following rules apply only to scalars. */
10586 if (shift_mode
!= shift_unit_mode
)
10589 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10590 minus the width of a smaller mode, we can do this with a
10591 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10592 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10593 && ! mode_dependent_address_p (XEXP (varop
, 0),
10594 MEM_ADDR_SPACE (varop
))
10595 && ! MEM_VOLATILE_P (varop
)
10596 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10597 MODE_INT
, 1)) != BLKmode
)
10599 new_rtx
= adjust_address_nv (varop
, tmode
,
10600 BYTES_BIG_ENDIAN
? 0
10601 : count
/ BITS_PER_UNIT
);
10603 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10604 : ZERO_EXTEND
, mode
, new_rtx
);
10611 /* The following rules apply only to scalars. */
10612 if (shift_mode
!= shift_unit_mode
)
10615 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10616 the same number of words as what we've seen so far. Then store
10617 the widest mode in MODE. */
10618 if (subreg_lowpart_p (varop
)
10619 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10620 > GET_MODE_SIZE (GET_MODE (varop
)))
10621 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10622 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10624 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10625 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10627 varop
= SUBREG_REG (varop
);
10628 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10629 mode
= GET_MODE (varop
);
10635 /* Some machines use MULT instead of ASHIFT because MULT
10636 is cheaper. But it is still better on those machines to
10637 merge two shifts into one. */
10638 if (CONST_INT_P (XEXP (varop
, 1))
10639 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10642 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10644 GEN_INT (exact_log2 (
10645 UINTVAL (XEXP (varop
, 1)))));
10651 /* Similar, for when divides are cheaper. */
10652 if (CONST_INT_P (XEXP (varop
, 1))
10653 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10656 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10658 GEN_INT (exact_log2 (
10659 UINTVAL (XEXP (varop
, 1)))));
10665 /* If we are extracting just the sign bit of an arithmetic
10666 right shift, that shift is not needed. However, the sign
10667 bit of a wider mode may be different from what would be
10668 interpreted as the sign bit in a narrower mode, so, if
10669 the result is narrower, don't discard the shift. */
10670 if (code
== LSHIFTRT
10671 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10672 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10673 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10675 varop
= XEXP (varop
, 0);
10684 /* The following rules apply only to scalars. */
10685 if (shift_mode
!= shift_unit_mode
)
10688 /* Here we have two nested shifts. The result is usually the
10689 AND of a new shift with a mask. We compute the result below. */
10690 if (CONST_INT_P (XEXP (varop
, 1))
10691 && INTVAL (XEXP (varop
, 1)) >= 0
10692 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10693 && HWI_COMPUTABLE_MODE_P (result_mode
)
10694 && HWI_COMPUTABLE_MODE_P (mode
))
10696 enum rtx_code first_code
= GET_CODE (varop
);
10697 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10698 unsigned HOST_WIDE_INT mask
;
10701 /* We have one common special case. We can't do any merging if
10702 the inner code is an ASHIFTRT of a smaller mode. However, if
10703 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10704 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10705 we can convert it to
10706 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10707 This simplifies certain SIGN_EXTEND operations. */
10708 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10709 && count
== (GET_MODE_PRECISION (result_mode
)
10710 - GET_MODE_PRECISION (GET_MODE (varop
))))
10712 /* C3 has the low-order C1 bits zero. */
10714 mask
= GET_MODE_MASK (mode
)
10715 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10717 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10718 XEXP (varop
, 0), mask
);
10719 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10721 count
= first_count
;
10726 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10727 than C1 high-order bits equal to the sign bit, we can convert
10728 this to either an ASHIFT or an ASHIFTRT depending on the
10731 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10733 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10734 && GET_MODE (varop
) == shift_mode
10735 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10738 varop
= XEXP (varop
, 0);
10739 count
-= first_count
;
10749 /* There are some cases we can't do. If CODE is ASHIFTRT,
10750 we can only do this if FIRST_CODE is also ASHIFTRT.
10752 We can't do the case when CODE is ROTATE and FIRST_CODE is
10755 If the mode of this shift is not the mode of the outer shift,
10756 we can't do this if either shift is a right shift or ROTATE.
10758 Finally, we can't do any of these if the mode is too wide
10759 unless the codes are the same.
10761 Handle the case where the shift codes are the same
10764 if (code
== first_code
)
10766 if (GET_MODE (varop
) != result_mode
10767 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10768 || code
== ROTATE
))
10771 count
+= first_count
;
10772 varop
= XEXP (varop
, 0);
10776 if (code
== ASHIFTRT
10777 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10778 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10779 || (GET_MODE (varop
) != result_mode
10780 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10781 || first_code
== ROTATE
10782 || code
== ROTATE
)))
10785 /* To compute the mask to apply after the shift, shift the
10786 nonzero bits of the inner shift the same way the
10787 outer shift will. */
10789 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10793 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10796 /* Give up if we can't compute an outer operation to use. */
10798 || !CONST_INT_P (mask_rtx
)
10799 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10801 result_mode
, &complement_p
))
10804 /* If the shifts are in the same direction, we add the
10805 counts. Otherwise, we subtract them. */
10806 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10807 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10808 count
+= first_count
;
10810 count
-= first_count
;
10812 /* If COUNT is positive, the new shift is usually CODE,
10813 except for the two exceptions below, in which case it is
10814 FIRST_CODE. If the count is negative, FIRST_CODE should
10817 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10818 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10820 else if (count
< 0)
10821 code
= first_code
, count
= -count
;
10823 varop
= XEXP (varop
, 0);
10827 /* If we have (A << B << C) for any shift, we can convert this to
10828 (A << C << B). This wins if A is a constant. Only try this if
10829 B is not a constant. */
10831 else if (GET_CODE (varop
) == code
10832 && CONST_INT_P (XEXP (varop
, 0))
10833 && !CONST_INT_P (XEXP (varop
, 1)))
10835 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10836 sure the result will be masked. See PR70222. */
10837 if (code
== LSHIFTRT
10838 && mode
!= result_mode
10839 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10840 GET_MODE_MASK (result_mode
)
10841 >> orig_count
, result_mode
,
10844 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10845 up outer sign extension (often left and right shift) is
10846 hardly more efficient than the original. See PR70429. */
10847 if (code
== ASHIFTRT
&& mode
!= result_mode
)
10850 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10853 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10860 /* The following rules apply only to scalars. */
10861 if (shift_mode
!= shift_unit_mode
)
10864 /* Make this fit the case below. */
10865 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10871 /* The following rules apply only to scalars. */
10872 if (shift_mode
!= shift_unit_mode
)
10875 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10876 with C the size of VAROP - 1 and the shift is logical if
10877 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10878 we have an (le X 0) operation. If we have an arithmetic shift
10879 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10880 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10882 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10883 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10884 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10885 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10886 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10887 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10890 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10893 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10894 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10899 /* If we have (shift (logical)), move the logical to the outside
10900 to allow it to possibly combine with another logical and the
10901 shift to combine with another shift. This also canonicalizes to
10902 what a ZERO_EXTRACT looks like. Also, some machines have
10903 (and (shift)) insns. */
10905 if (CONST_INT_P (XEXP (varop
, 1))
10906 /* We can't do this if we have (ashiftrt (xor)) and the
10907 constant has its sign bit set in shift_mode with shift_mode
10908 wider than result_mode. */
10909 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10910 && result_mode
!= shift_mode
10911 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10913 && (new_rtx
= simplify_const_binary_operation
10914 (code
, result_mode
,
10915 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10916 GEN_INT (count
))) != 0
10917 && CONST_INT_P (new_rtx
)
10918 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10919 INTVAL (new_rtx
), result_mode
, &complement_p
))
10921 varop
= XEXP (varop
, 0);
10925 /* If we can't do that, try to simplify the shift in each arm of the
10926 logical expression, make a new logical expression, and apply
10927 the inverse distributive law. This also can't be done for
10928 (ashiftrt (xor)) where we've widened the shift and the constant
10929 changes the sign bit. */
10930 if (CONST_INT_P (XEXP (varop
, 1))
10931 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10932 && result_mode
!= shift_mode
10933 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10936 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10937 XEXP (varop
, 0), count
);
10938 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10939 XEXP (varop
, 1), count
);
10941 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10943 varop
= apply_distributive_law (varop
);
10951 /* The following rules apply only to scalars. */
10952 if (shift_mode
!= shift_unit_mode
)
10955 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10956 says that the sign bit can be tested, FOO has mode MODE, C is
10957 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10958 that may be nonzero. */
10959 if (code
== LSHIFTRT
10960 && XEXP (varop
, 1) == const0_rtx
10961 && GET_MODE (XEXP (varop
, 0)) == result_mode
10962 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10963 && HWI_COMPUTABLE_MODE_P (result_mode
)
10964 && STORE_FLAG_VALUE
== -1
10965 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10966 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10969 varop
= XEXP (varop
, 0);
10976 /* The following rules apply only to scalars. */
10977 if (shift_mode
!= shift_unit_mode
)
10980 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10981 than the number of bits in the mode is equivalent to A. */
10982 if (code
== LSHIFTRT
10983 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10984 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10986 varop
= XEXP (varop
, 0);
10991 /* NEG commutes with ASHIFT since it is multiplication. Move the
10992 NEG outside to allow shifts to combine. */
10994 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10997 varop
= XEXP (varop
, 0);
11003 /* The following rules apply only to scalars. */
11004 if (shift_mode
!= shift_unit_mode
)
11007 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11008 is one less than the number of bits in the mode is
11009 equivalent to (xor A 1). */
11010 if (code
== LSHIFTRT
11011 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
11012 && XEXP (varop
, 1) == constm1_rtx
11013 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
11014 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
11018 varop
= XEXP (varop
, 0);
11022 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11023 that might be nonzero in BAR are those being shifted out and those
11024 bits are known zero in FOO, we can replace the PLUS with FOO.
11025 Similarly in the other operand order. This code occurs when
11026 we are computing the size of a variable-size array. */
11028 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11029 && count
< HOST_BITS_PER_WIDE_INT
11030 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
11031 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
11032 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
11034 varop
= XEXP (varop
, 0);
11037 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11038 && count
< HOST_BITS_PER_WIDE_INT
11039 && HWI_COMPUTABLE_MODE_P (result_mode
)
11040 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
11042 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
11043 & nonzero_bits (XEXP (varop
, 1),
11046 varop
= XEXP (varop
, 1);
11050 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11052 && CONST_INT_P (XEXP (varop
, 1))
11053 && (new_rtx
= simplify_const_binary_operation
11054 (ASHIFT
, result_mode
,
11055 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
11056 GEN_INT (count
))) != 0
11057 && CONST_INT_P (new_rtx
)
11058 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
11059 INTVAL (new_rtx
), result_mode
, &complement_p
))
11061 varop
= XEXP (varop
, 0);
11065 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11066 signbit', and attempt to change the PLUS to an XOR and move it to
11067 the outer operation as is done above in the AND/IOR/XOR case
11068 leg for shift(logical). See details in logical handling above
11069 for reasoning in doing so. */
11070 if (code
== LSHIFTRT
11071 && CONST_INT_P (XEXP (varop
, 1))
11072 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
11073 && (new_rtx
= simplify_const_binary_operation
11074 (code
, result_mode
,
11075 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
11076 GEN_INT (count
))) != 0
11077 && CONST_INT_P (new_rtx
)
11078 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
11079 INTVAL (new_rtx
), result_mode
, &complement_p
))
11081 varop
= XEXP (varop
, 0);
11088 /* The following rules apply only to scalars. */
11089 if (shift_mode
!= shift_unit_mode
)
11092 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11093 with C the size of VAROP - 1 and the shift is logical if
11094 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11095 we have a (gt X 0) operation. If the shift is arithmetic with
11096 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11097 we have a (neg (gt X 0)) operation. */
11099 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11100 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
11101 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
11102 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11103 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11104 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
11105 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11108 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
11111 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11112 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
11119 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11120 if the truncate does not affect the value. */
11121 if (code
== LSHIFTRT
11122 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
11123 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11124 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
11125 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
11126 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
11128 rtx varop_inner
= XEXP (varop
, 0);
11131 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
11132 XEXP (varop_inner
, 0),
11134 (count
+ INTVAL (XEXP (varop_inner
, 1))));
11135 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11148 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
11149 outer_op
, outer_const
);
11151 /* We have now finished analyzing the shift. The result should be
11152 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11153 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11154 to the result of the shift. OUTER_CONST is the relevant constant,
11155 but we must turn off all bits turned off in the shift. */
11157 if (outer_op
== UNKNOWN
11158 && orig_code
== code
&& orig_count
== count
11159 && varop
== orig_varop
11160 && shift_mode
== GET_MODE (varop
))
11163 /* Make a SUBREG if necessary. If we can't make it, fail. */
11164 varop
= gen_lowpart (shift_mode
, varop
);
11165 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11168 /* If we have an outer operation and we just made a shift, it is
11169 possible that we could have simplified the shift were it not
11170 for the outer operation. So try to do the simplification
11173 if (outer_op
!= UNKNOWN
)
11174 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11179 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
11181 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11182 turn off all the bits that the shift would have turned off. */
11183 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11184 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
11185 GET_MODE_MASK (result_mode
) >> orig_count
);
11187 /* Do the remainder of the processing in RESULT_MODE. */
11188 x
= gen_lowpart_or_truncate (result_mode
, x
);
11190 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11193 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11195 if (outer_op
!= UNKNOWN
)
11197 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11198 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
11199 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
11201 if (outer_op
== AND
)
11202 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
11203 else if (outer_op
== SET
)
11205 /* This means that we have determined that the result is
11206 equivalent to a constant. This should be rare. */
11207 if (!side_effects_p (x
))
11208 x
= GEN_INT (outer_const
);
11210 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11211 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
11213 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
11214 GEN_INT (outer_const
));
11220 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11221 The result of the shift is RESULT_MODE. If we cannot simplify it,
11222 return X or, if it is NULL, synthesize the expression with
11223 simplify_gen_binary. Otherwise, return a simplified value.
11225 The shift is normally computed in the widest mode we find in VAROP, as
11226 long as it isn't a different number of words than RESULT_MODE. Exceptions
11227 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11230 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11231 rtx varop
, int count
)
11233 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11238 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
11239 if (GET_MODE (x
) != result_mode
)
11240 x
= gen_lowpart (result_mode
, x
);
11245 /* A subroutine of recog_for_combine. See there for arguments and
11249 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11251 rtx pat
= *pnewpat
;
11252 rtx pat_without_clobbers
;
11253 int insn_code_number
;
11254 int num_clobbers_to_add
= 0;
11256 rtx notes
= NULL_RTX
;
11257 rtx old_notes
, old_pat
;
11260 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11261 we use to indicate that something didn't match. If we find such a
11262 thing, force rejection. */
11263 if (GET_CODE (pat
) == PARALLEL
)
11264 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11265 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11266 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11269 old_pat
= PATTERN (insn
);
11270 old_notes
= REG_NOTES (insn
);
11271 PATTERN (insn
) = pat
;
11272 REG_NOTES (insn
) = NULL_RTX
;
11274 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11275 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11277 if (insn_code_number
< 0)
11278 fputs ("Failed to match this instruction:\n", dump_file
);
11280 fputs ("Successfully matched this instruction:\n", dump_file
);
11281 print_rtl_single (dump_file
, pat
);
11284 /* If it isn't, there is the possibility that we previously had an insn
11285 that clobbered some register as a side effect, but the combined
11286 insn doesn't need to do that. So try once more without the clobbers
11287 unless this represents an ASM insn. */
11289 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11290 && GET_CODE (pat
) == PARALLEL
)
11294 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11295 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11298 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11302 SUBST_INT (XVECLEN (pat
, 0), pos
);
11305 pat
= XVECEXP (pat
, 0, 0);
11307 PATTERN (insn
) = pat
;
11308 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11309 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11311 if (insn_code_number
< 0)
11312 fputs ("Failed to match this instruction:\n", dump_file
);
11314 fputs ("Successfully matched this instruction:\n", dump_file
);
11315 print_rtl_single (dump_file
, pat
);
11319 pat_without_clobbers
= pat
;
11321 PATTERN (insn
) = old_pat
;
11322 REG_NOTES (insn
) = old_notes
;
11324 /* Recognize all noop sets, these will be killed by followup pass. */
11325 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11326 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11328 /* If we had any clobbers to add, make a new pattern than contains
11329 them. Then check to make sure that all of them are dead. */
11330 if (num_clobbers_to_add
)
11332 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11333 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11334 ? (XVECLEN (pat
, 0)
11335 + num_clobbers_to_add
)
11336 : num_clobbers_to_add
+ 1));
11338 if (GET_CODE (pat
) == PARALLEL
)
11339 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11340 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11342 XVECEXP (newpat
, 0, 0) = pat
;
11344 add_clobbers (newpat
, insn_code_number
);
11346 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11347 i
< XVECLEN (newpat
, 0); i
++)
11349 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11350 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11352 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11354 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11355 notes
= alloc_reg_note (REG_UNUSED
,
11356 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11362 if (insn_code_number
>= 0
11363 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11365 old_pat
= PATTERN (insn
);
11366 old_notes
= REG_NOTES (insn
);
11367 old_icode
= INSN_CODE (insn
);
11368 PATTERN (insn
) = pat
;
11369 REG_NOTES (insn
) = notes
;
11370 INSN_CODE (insn
) = insn_code_number
;
11372 /* Allow targets to reject combined insn. */
11373 if (!targetm
.legitimate_combined_insn (insn
))
11375 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11376 fputs ("Instruction not appropriate for target.",
11379 /* Callers expect recog_for_combine to strip
11380 clobbers from the pattern on failure. */
11381 pat
= pat_without_clobbers
;
11384 insn_code_number
= -1;
11387 PATTERN (insn
) = old_pat
;
11388 REG_NOTES (insn
) = old_notes
;
11389 INSN_CODE (insn
) = old_icode
;
11395 return insn_code_number
;
11398 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11399 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11400 Return whether anything was so changed. */
11403 change_zero_ext (rtx pat
)
11405 bool changed
= false;
11406 rtx
*src
= &SET_SRC (pat
);
11408 subrtx_ptr_iterator::array_type array
;
11409 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11412 machine_mode mode
= GET_MODE (x
);
11415 if (GET_CODE (x
) == ZERO_EXTRACT
11416 && CONST_INT_P (XEXP (x
, 1))
11417 && CONST_INT_P (XEXP (x
, 2))
11418 && GET_MODE (XEXP (x
, 0)) != VOIDmode
11419 && GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
11420 <= GET_MODE_PRECISION (mode
))
11422 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
11424 size
= INTVAL (XEXP (x
, 1));
11426 int start
= INTVAL (XEXP (x
, 2));
11427 if (BITS_BIG_ENDIAN
)
11428 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11431 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0), GEN_INT (start
));
11434 if (mode
!= inner_mode
)
11435 x
= gen_lowpart_SUBREG (mode
, x
);
11437 else if (GET_CODE (x
) == ZERO_EXTEND
11438 && SCALAR_INT_MODE_P (mode
)
11439 && GET_CODE (XEXP (x
, 0)) == SUBREG
11440 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11441 && !paradoxical_subreg_p (XEXP (x
, 0))
11442 && subreg_lowpart_p (XEXP (x
, 0)))
11444 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11445 x
= SUBREG_REG (XEXP (x
, 0));
11446 if (GET_MODE (x
) != mode
)
11447 x
= gen_lowpart_SUBREG (mode
, x
);
11449 else if (GET_CODE (x
) == ZERO_EXTEND
11450 && SCALAR_INT_MODE_P (mode
)
11451 && REG_P (XEXP (x
, 0))
11452 && HARD_REGISTER_P (XEXP (x
, 0))
11453 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11455 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11456 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11461 if (!(GET_CODE (x
) == LSHIFTRT
11462 && CONST_INT_P (XEXP (x
, 1))
11463 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11465 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11466 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11474 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11475 maybe_swap_commutative_operands (**iter
);
11477 rtx
*dst
= &SET_DEST (pat
);
11478 if (GET_CODE (*dst
) == ZERO_EXTRACT
11479 && REG_P (XEXP (*dst
, 0))
11480 && CONST_INT_P (XEXP (*dst
, 1))
11481 && CONST_INT_P (XEXP (*dst
, 2)))
11483 rtx reg
= XEXP (*dst
, 0);
11484 int width
= INTVAL (XEXP (*dst
, 1));
11485 int offset
= INTVAL (XEXP (*dst
, 2));
11486 machine_mode mode
= GET_MODE (reg
);
11487 int reg_width
= GET_MODE_PRECISION (mode
);
11488 if (BITS_BIG_ENDIAN
)
11489 offset
= reg_width
- width
- offset
;
11492 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11493 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11494 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11496 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11499 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11500 w
= gen_rtx_IOR (mode
, x
, z
);
11501 SUBST (SET_DEST (pat
), reg
);
11502 SUBST (SET_SRC (pat
), w
);
11510 /* Like recog, but we receive the address of a pointer to a new pattern.
11511 We try to match the rtx that the pointer points to.
11512 If that fails, we may try to modify or replace the pattern,
11513 storing the replacement into the same pointer object.
11515 Modifications include deletion or addition of CLOBBERs. If the
11516 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11517 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11518 (and undo if that fails).
11520 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11521 the CLOBBERs are placed.
11523 The value is the final insn code from the pattern ultimately matched,
11527 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11529 rtx pat
= *pnewpat
;
11530 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11531 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11532 return insn_code_number
;
11534 void *marker
= get_undo_marker ();
11535 bool changed
= false;
11537 if (GET_CODE (pat
) == SET
)
11538 changed
= change_zero_ext (pat
);
11539 else if (GET_CODE (pat
) == PARALLEL
)
11542 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11544 rtx set
= XVECEXP (pat
, 0, i
);
11545 if (GET_CODE (set
) == SET
)
11546 changed
|= change_zero_ext (set
);
11552 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11554 if (insn_code_number
< 0)
11555 undo_to_marker (marker
);
11558 return insn_code_number
;
11561 /* Like gen_lowpart_general but for use by combine. In combine it
11562 is not possible to create any new pseudoregs. However, it is
11563 safe to create invalid memory addresses, because combine will
11564 try to recognize them and all they will do is make the combine
11567 If for some reason this cannot do its job, an rtx
11568 (clobber (const_int 0)) is returned.
11569 An insn containing that will not be recognized. */
11572 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11574 machine_mode imode
= GET_MODE (x
);
11575 unsigned int osize
= GET_MODE_SIZE (omode
);
11576 unsigned int isize
= GET_MODE_SIZE (imode
);
11579 if (omode
== imode
)
11582 /* We can only support MODE being wider than a word if X is a
11583 constant integer or has a mode the same size. */
11584 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11585 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11588 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11589 won't know what to do. So we will strip off the SUBREG here and
11590 process normally. */
11591 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11593 x
= SUBREG_REG (x
);
11595 /* For use in case we fall down into the address adjustments
11596 further below, we need to adjust the known mode and size of
11597 x; imode and isize, since we just adjusted x. */
11598 imode
= GET_MODE (x
);
11600 if (imode
== omode
)
11603 isize
= GET_MODE_SIZE (imode
);
11606 result
= gen_lowpart_common (omode
, x
);
11615 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11617 if (MEM_VOLATILE_P (x
)
11618 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11621 /* If we want to refer to something bigger than the original memref,
11622 generate a paradoxical subreg instead. That will force a reload
11623 of the original memref X. */
11625 return gen_rtx_SUBREG (omode
, x
, 0);
11627 if (WORDS_BIG_ENDIAN
)
11628 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11630 /* Adjust the address so that the address-after-the-data is
11632 if (BYTES_BIG_ENDIAN
)
11633 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11635 return adjust_address_nv (x
, omode
, offset
);
11638 /* If X is a comparison operator, rewrite it in a new mode. This
11639 probably won't match, but may allow further simplifications. */
11640 else if (COMPARISON_P (x
))
11641 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11643 /* If we couldn't simplify X any other way, just enclose it in a
11644 SUBREG. Normally, this SUBREG won't match, but some patterns may
11645 include an explicit SUBREG or we may simplify it further in combine. */
11650 if (imode
== VOIDmode
)
11652 imode
= int_mode_for_mode (omode
);
11653 x
= gen_lowpart_common (imode
, x
);
11657 res
= lowpart_subreg (omode
, x
, imode
);
11663 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11666 /* Try to simplify a comparison between OP0 and a constant OP1,
11667 where CODE is the comparison code that will be tested, into a
11668 (CODE OP0 const0_rtx) form.
11670 The result is a possibly different comparison code to use.
11671 *POP1 may be updated. */
11673 static enum rtx_code
11674 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11675 rtx op0
, rtx
*pop1
)
11677 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11678 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11680 /* Get the constant we are comparing against and turn off all bits
11681 not on in our mode. */
11682 if (mode
!= VOIDmode
)
11683 const_op
= trunc_int_for_mode (const_op
, mode
);
11685 /* If we are comparing against a constant power of two and the value
11686 being compared can only have that single bit nonzero (e.g., it was
11687 `and'ed with that bit), we can replace this with a comparison
11690 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11691 || code
== LT
|| code
== LTU
)
11692 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11693 && pow2p_hwi (const_op
& GET_MODE_MASK (mode
))
11694 && (nonzero_bits (op0
, mode
)
11695 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11697 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11701 /* Similarly, if we are comparing a value known to be either -1 or
11702 0 with -1, change it to the opposite comparison against zero. */
11704 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11705 || code
== GEU
|| code
== LTU
)
11706 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11708 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11712 /* Do some canonicalizations based on the comparison code. We prefer
11713 comparisons against zero and then prefer equality comparisons.
11714 If we can reduce the size of a constant, we will do that too. */
11718 /* < C is equivalent to <= (C - 1) */
11723 /* ... fall through to LE case below. */
11724 gcc_fallthrough ();
11730 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11737 /* If we are doing a <= 0 comparison on a value known to have
11738 a zero sign bit, we can replace this with == 0. */
11739 else if (const_op
== 0
11740 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11741 && (nonzero_bits (op0
, mode
)
11742 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11748 /* >= C is equivalent to > (C - 1). */
11753 /* ... fall through to GT below. */
11754 gcc_fallthrough ();
11760 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11767 /* If we are doing a > 0 comparison on a value known to have
11768 a zero sign bit, we can replace this with != 0. */
11769 else if (const_op
== 0
11770 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11771 && (nonzero_bits (op0
, mode
)
11772 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11778 /* < C is equivalent to <= (C - 1). */
11783 /* ... fall through ... */
11785 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11786 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11787 && (unsigned HOST_WIDE_INT
) const_op
11788 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11798 /* unsigned <= 0 is equivalent to == 0 */
11801 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11802 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11803 && (unsigned HOST_WIDE_INT
) const_op
11804 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11812 /* >= C is equivalent to > (C - 1). */
11817 /* ... fall through ... */
11820 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11821 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11822 && (unsigned HOST_WIDE_INT
) const_op
11823 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11833 /* unsigned > 0 is equivalent to != 0 */
11836 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11837 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11838 && (unsigned HOST_WIDE_INT
) const_op
11839 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11850 *pop1
= GEN_INT (const_op
);
11854 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11855 comparison code that will be tested.
11857 The result is a possibly different comparison code to use. *POP0 and
11858 *POP1 may be updated.
11860 It is possible that we might detect that a comparison is either always
11861 true or always false. However, we do not perform general constant
11862 folding in combine, so this knowledge isn't useful. Such tautologies
11863 should have been detected earlier. Hence we ignore all such cases. */
11865 static enum rtx_code
11866 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11872 machine_mode mode
, tmode
;
11874 /* Try a few ways of applying the same transformation to both operands. */
11877 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11878 so check specially. */
11879 if (!WORD_REGISTER_OPERATIONS
11880 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11881 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11882 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11883 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11884 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11885 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11886 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11887 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11888 && CONST_INT_P (XEXP (op0
, 1))
11889 && XEXP (op0
, 1) == XEXP (op1
, 1)
11890 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11891 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11892 && (INTVAL (XEXP (op0
, 1))
11893 == (GET_MODE_PRECISION (GET_MODE (op0
))
11894 - (GET_MODE_PRECISION
11895 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11897 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11898 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11901 /* If both operands are the same constant shift, see if we can ignore the
11902 shift. We can if the shift is a rotate or if the bits shifted out of
11903 this shift are known to be zero for both inputs and if the type of
11904 comparison is compatible with the shift. */
11905 if (GET_CODE (op0
) == GET_CODE (op1
)
11906 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11907 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11908 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11909 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11910 || (GET_CODE (op0
) == ASHIFTRT
11911 && (code
!= GTU
&& code
!= LTU
11912 && code
!= GEU
&& code
!= LEU
)))
11913 && CONST_INT_P (XEXP (op0
, 1))
11914 && INTVAL (XEXP (op0
, 1)) >= 0
11915 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11916 && XEXP (op0
, 1) == XEXP (op1
, 1))
11918 machine_mode mode
= GET_MODE (op0
);
11919 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11920 int shift_count
= INTVAL (XEXP (op0
, 1));
11922 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11923 mask
&= (mask
>> shift_count
) << shift_count
;
11924 else if (GET_CODE (op0
) == ASHIFT
)
11925 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11927 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11928 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11929 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11934 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11935 SUBREGs are of the same mode, and, in both cases, the AND would
11936 be redundant if the comparison was done in the narrower mode,
11937 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11938 and the operand's possibly nonzero bits are 0xffffff01; in that case
11939 if we only care about QImode, we don't need the AND). This case
11940 occurs if the output mode of an scc insn is not SImode and
11941 STORE_FLAG_VALUE == 1 (e.g., the 386).
11943 Similarly, check for a case where the AND's are ZERO_EXTEND
11944 operations from some narrower mode even though a SUBREG is not
11947 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11948 && CONST_INT_P (XEXP (op0
, 1))
11949 && CONST_INT_P (XEXP (op1
, 1)))
11951 rtx inner_op0
= XEXP (op0
, 0);
11952 rtx inner_op1
= XEXP (op1
, 0);
11953 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11954 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11957 if (paradoxical_subreg_p (inner_op0
)
11958 && GET_CODE (inner_op1
) == SUBREG
11959 && (GET_MODE (SUBREG_REG (inner_op0
))
11960 == GET_MODE (SUBREG_REG (inner_op1
)))
11961 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11962 <= HOST_BITS_PER_WIDE_INT
)
11963 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11964 GET_MODE (SUBREG_REG (inner_op0
)))))
11965 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11966 GET_MODE (SUBREG_REG (inner_op1
))))))
11968 op0
= SUBREG_REG (inner_op0
);
11969 op1
= SUBREG_REG (inner_op1
);
11971 /* The resulting comparison is always unsigned since we masked
11972 off the original sign bit. */
11973 code
= unsigned_condition (code
);
11979 for (tmode
= GET_CLASS_NARROWEST_MODE
11980 (GET_MODE_CLASS (GET_MODE (op0
)));
11981 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11982 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11984 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
11985 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
11986 code
= unsigned_condition (code
);
11995 /* If both operands are NOT, we can strip off the outer operation
11996 and adjust the comparison code for swapped operands; similarly for
11997 NEG, except that this must be an equality comparison. */
11998 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11999 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
12000 && (code
== EQ
|| code
== NE
)))
12001 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
12007 /* If the first operand is a constant, swap the operands and adjust the
12008 comparison code appropriately, but don't do this if the second operand
12009 is already a constant integer. */
12010 if (swap_commutative_operands_p (op0
, op1
))
12012 std::swap (op0
, op1
);
12013 code
= swap_condition (code
);
12016 /* We now enter a loop during which we will try to simplify the comparison.
12017 For the most part, we only are concerned with comparisons with zero,
12018 but some things may really be comparisons with zero but not start
12019 out looking that way. */
12021 while (CONST_INT_P (op1
))
12023 machine_mode mode
= GET_MODE (op0
);
12024 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
12025 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12026 int equality_comparison_p
;
12027 int sign_bit_comparison_p
;
12028 int unsigned_comparison_p
;
12029 HOST_WIDE_INT const_op
;
12031 /* We only want to handle integral modes. This catches VOIDmode,
12032 CCmode, and the floating-point modes. An exception is that we
12033 can handle VOIDmode if OP0 is a COMPARE or a comparison
12036 if (GET_MODE_CLASS (mode
) != MODE_INT
12037 && ! (mode
== VOIDmode
12038 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
12041 /* Try to simplify the compare to constant, possibly changing the
12042 comparison op, and/or changing op1 to zero. */
12043 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
12044 const_op
= INTVAL (op1
);
12046 /* Compute some predicates to simplify code below. */
12048 equality_comparison_p
= (code
== EQ
|| code
== NE
);
12049 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
12050 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
12053 /* If this is a sign bit comparison and we can do arithmetic in
12054 MODE, say that we will only be needing the sign bit of OP0. */
12055 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
12056 op0
= force_to_mode (op0
, mode
,
12058 << (GET_MODE_PRECISION (mode
) - 1),
12061 /* Now try cases based on the opcode of OP0. If none of the cases
12062 does a "continue", we exit this loop immediately after the
12065 switch (GET_CODE (op0
))
12068 /* If we are extracting a single bit from a variable position in
12069 a constant that has only a single bit set and are comparing it
12070 with zero, we can convert this into an equality comparison
12071 between the position and the location of the single bit. */
12072 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12073 have already reduced the shift count modulo the word size. */
12074 if (!SHIFT_COUNT_TRUNCATED
12075 && CONST_INT_P (XEXP (op0
, 0))
12076 && XEXP (op0
, 1) == const1_rtx
12077 && equality_comparison_p
&& const_op
== 0
12078 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
12080 if (BITS_BIG_ENDIAN
)
12081 i
= BITS_PER_WORD
- 1 - i
;
12083 op0
= XEXP (op0
, 2);
12087 /* Result is nonzero iff shift count is equal to I. */
12088 code
= reverse_condition (code
);
12095 tem
= expand_compound_operation (op0
);
12104 /* If testing for equality, we can take the NOT of the constant. */
12105 if (equality_comparison_p
12106 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
12108 op0
= XEXP (op0
, 0);
12113 /* If just looking at the sign bit, reverse the sense of the
12115 if (sign_bit_comparison_p
)
12117 op0
= XEXP (op0
, 0);
12118 code
= (code
== GE
? LT
: GE
);
12124 /* If testing for equality, we can take the NEG of the constant. */
12125 if (equality_comparison_p
12126 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
12128 op0
= XEXP (op0
, 0);
12133 /* The remaining cases only apply to comparisons with zero. */
12137 /* When X is ABS or is known positive,
12138 (neg X) is < 0 if and only if X != 0. */
12140 if (sign_bit_comparison_p
12141 && (GET_CODE (XEXP (op0
, 0)) == ABS
12142 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12143 && (nonzero_bits (XEXP (op0
, 0), mode
)
12144 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12147 op0
= XEXP (op0
, 0);
12148 code
= (code
== LT
? NE
: EQ
);
12152 /* If we have NEG of something whose two high-order bits are the
12153 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12154 if (num_sign_bit_copies (op0
, mode
) >= 2)
12156 op0
= XEXP (op0
, 0);
12157 code
= swap_condition (code
);
12163 /* If we are testing equality and our count is a constant, we
12164 can perform the inverse operation on our RHS. */
12165 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12166 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12167 op1
, XEXP (op0
, 1))) != 0)
12169 op0
= XEXP (op0
, 0);
12174 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12175 a particular bit. Convert it to an AND of a constant of that
12176 bit. This will be converted into a ZERO_EXTRACT. */
12177 if (const_op
== 0 && sign_bit_comparison_p
12178 && CONST_INT_P (XEXP (op0
, 1))
12179 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12181 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12184 - INTVAL (XEXP (op0
, 1)))));
12185 code
= (code
== LT
? NE
: EQ
);
12189 /* Fall through. */
12192 /* ABS is ignorable inside an equality comparison with zero. */
12193 if (const_op
== 0 && equality_comparison_p
)
12195 op0
= XEXP (op0
, 0);
12201 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12202 (compare FOO CONST) if CONST fits in FOO's mode and we
12203 are either testing inequality or have an unsigned
12204 comparison with ZERO_EXTEND or a signed comparison with
12205 SIGN_EXTEND. But don't do it if we don't have a compare
12206 insn of the given mode, since we'd have to revert it
12207 later on, and then we wouldn't know whether to sign- or
12209 mode
= GET_MODE (XEXP (op0
, 0));
12210 if (GET_MODE_CLASS (mode
) == MODE_INT
12211 && ! unsigned_comparison_p
12212 && HWI_COMPUTABLE_MODE_P (mode
)
12213 && trunc_int_for_mode (const_op
, mode
) == const_op
12214 && have_insn_for (COMPARE
, mode
))
12216 op0
= XEXP (op0
, 0);
12222 /* Check for the case where we are comparing A - C1 with C2, that is
12224 (subreg:MODE (plus (A) (-C1))) op (C2)
12226 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12227 comparison in the wider mode. One of the following two conditions
12228 must be true in order for this to be valid:
12230 1. The mode extension results in the same bit pattern being added
12231 on both sides and the comparison is equality or unsigned. As
12232 C2 has been truncated to fit in MODE, the pattern can only be
12235 2. The mode extension results in the sign bit being copied on
12238 The difficulty here is that we have predicates for A but not for
12239 (A - C1) so we need to check that C1 is within proper bounds so
12240 as to perturbate A as little as possible. */
12242 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12243 && subreg_lowpart_p (op0
)
12244 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
12245 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12246 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12248 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
12249 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12250 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12253 && (unsigned HOST_WIDE_INT
) c1
12254 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12255 && (equality_comparison_p
|| unsigned_comparison_p
)
12256 /* (A - C1) zero-extends if it is positive and sign-extends
12257 if it is negative, C2 both zero- and sign-extends. */
12258 && ((0 == (nonzero_bits (a
, inner_mode
)
12259 & ~GET_MODE_MASK (mode
))
12261 /* (A - C1) sign-extends if it is positive and 1-extends
12262 if it is negative, C2 both sign- and 1-extends. */
12263 || (num_sign_bit_copies (a
, inner_mode
)
12264 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12267 || ((unsigned HOST_WIDE_INT
) c1
12268 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12269 /* (A - C1) always sign-extends, like C2. */
12270 && num_sign_bit_copies (a
, inner_mode
)
12271 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12272 - (mode_width
- 1))))
12274 op0
= SUBREG_REG (op0
);
12279 /* If the inner mode is narrower and we are extracting the low part,
12280 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12281 if (subreg_lowpart_p (op0
)
12282 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
12284 else if (subreg_lowpart_p (op0
)
12285 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12286 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12287 && (code
== NE
|| code
== EQ
)
12288 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12289 <= HOST_BITS_PER_WIDE_INT
)
12290 && !paradoxical_subreg_p (op0
)
12291 && (nonzero_bits (SUBREG_REG (op0
),
12292 GET_MODE (SUBREG_REG (op0
)))
12293 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12295 /* Remove outer subregs that don't do anything. */
12296 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12298 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12299 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12301 op0
= SUBREG_REG (op0
);
12313 mode
= GET_MODE (XEXP (op0
, 0));
12314 if (GET_MODE_CLASS (mode
) == MODE_INT
12315 && (unsigned_comparison_p
|| equality_comparison_p
)
12316 && HWI_COMPUTABLE_MODE_P (mode
)
12317 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12319 && have_insn_for (COMPARE
, mode
))
12321 op0
= XEXP (op0
, 0);
12327 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12328 this for equality comparisons due to pathological cases involving
12330 if (equality_comparison_p
12331 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12332 op1
, XEXP (op0
, 1))))
12334 op0
= XEXP (op0
, 0);
12339 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12340 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12341 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12343 op0
= XEXP (XEXP (op0
, 0), 0);
12344 code
= (code
== LT
? EQ
: NE
);
12350 /* We used to optimize signed comparisons against zero, but that
12351 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12352 arrive here as equality comparisons, or (GEU, LTU) are
12353 optimized away. No need to special-case them. */
12355 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12356 (eq B (minus A C)), whichever simplifies. We can only do
12357 this for equality comparisons due to pathological cases involving
12359 if (equality_comparison_p
12360 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
12361 XEXP (op0
, 1), op1
)))
12363 op0
= XEXP (op0
, 0);
12368 if (equality_comparison_p
12369 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12370 XEXP (op0
, 0), op1
)))
12372 op0
= XEXP (op0
, 1);
12377 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12378 of bits in X minus 1, is one iff X > 0. */
12379 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12380 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12381 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12382 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12384 op0
= XEXP (op0
, 1);
12385 code
= (code
== GE
? LE
: GT
);
12391 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12392 if C is zero or B is a constant. */
12393 if (equality_comparison_p
12394 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
12395 XEXP (op0
, 1), op1
)))
12397 op0
= XEXP (op0
, 0);
12404 case UNEQ
: case LTGT
:
12405 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
12406 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
12407 case UNORDERED
: case ORDERED
:
12408 /* We can't do anything if OP0 is a condition code value, rather
12409 than an actual data value. */
12411 || CC0_P (XEXP (op0
, 0))
12412 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12415 /* Get the two operands being compared. */
12416 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12417 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12419 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12421 /* Check for the cases where we simply want the result of the
12422 earlier test or the opposite of that result. */
12423 if (code
== NE
|| code
== EQ
12424 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
12425 && (code
== LT
|| code
== GE
)))
12427 enum rtx_code new_code
;
12428 if (code
== LT
|| code
== NE
)
12429 new_code
= GET_CODE (op0
);
12431 new_code
= reversed_comparison_code (op0
, NULL
);
12433 if (new_code
!= UNKNOWN
)
12444 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12446 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12447 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12448 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12450 op0
= XEXP (op0
, 1);
12451 code
= (code
== GE
? GT
: LE
);
12457 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12458 will be converted to a ZERO_EXTRACT later. */
12459 if (const_op
== 0 && equality_comparison_p
12460 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12461 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12463 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12464 XEXP (XEXP (op0
, 0), 1));
12465 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12469 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12470 zero and X is a comparison and C1 and C2 describe only bits set
12471 in STORE_FLAG_VALUE, we can compare with X. */
12472 if (const_op
== 0 && equality_comparison_p
12473 && mode_width
<= HOST_BITS_PER_WIDE_INT
12474 && CONST_INT_P (XEXP (op0
, 1))
12475 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12476 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12477 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12478 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12480 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12481 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12482 if ((~STORE_FLAG_VALUE
& mask
) == 0
12483 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12484 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12485 && COMPARISON_P (tem
))))
12487 op0
= XEXP (XEXP (op0
, 0), 0);
12492 /* If we are doing an equality comparison of an AND of a bit equal
12493 to the sign bit, replace this with a LT or GE comparison of
12494 the underlying value. */
12495 if (equality_comparison_p
12497 && CONST_INT_P (XEXP (op0
, 1))
12498 && mode_width
<= HOST_BITS_PER_WIDE_INT
12499 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12500 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12502 op0
= XEXP (op0
, 0);
12503 code
= (code
== EQ
? GE
: LT
);
12507 /* If this AND operation is really a ZERO_EXTEND from a narrower
12508 mode, the constant fits within that mode, and this is either an
12509 equality or unsigned comparison, try to do this comparison in
12514 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12515 -> (ne:DI (reg:SI 4) (const_int 0))
12517 unless TRULY_NOOP_TRUNCATION allows it or the register is
12518 known to hold a value of the required mode the
12519 transformation is invalid. */
12520 if ((equality_comparison_p
|| unsigned_comparison_p
)
12521 && CONST_INT_P (XEXP (op0
, 1))
12522 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12523 & GET_MODE_MASK (mode
))
12525 && const_op
>> i
== 0
12526 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
12528 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12532 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12533 fits in both M1 and M2 and the SUBREG is either paradoxical
12534 or represents the low part, permute the SUBREG and the AND
12536 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12537 && CONST_INT_P (XEXP (op0
, 1)))
12539 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12540 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12541 /* Require an integral mode, to avoid creating something like
12543 if (SCALAR_INT_MODE_P (tmode
)
12544 /* It is unsafe to commute the AND into the SUBREG if the
12545 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12546 not defined. As originally written the upper bits
12547 have a defined value due to the AND operation.
12548 However, if we commute the AND inside the SUBREG then
12549 they no longer have defined values and the meaning of
12550 the code has been changed.
12551 Also C1 should not change value in the smaller mode,
12552 see PR67028 (a positive C1 can become negative in the
12553 smaller mode, so that the AND does no longer mask the
12555 && ((WORD_REGISTER_OPERATIONS
12556 && mode_width
> GET_MODE_PRECISION (tmode
)
12557 && mode_width
<= BITS_PER_WORD
12558 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12559 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12560 && subreg_lowpart_p (XEXP (op0
, 0))))
12561 && mode_width
<= HOST_BITS_PER_WIDE_INT
12562 && HWI_COMPUTABLE_MODE_P (tmode
)
12563 && (c1
& ~mask
) == 0
12564 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12566 && c1
!= GET_MODE_MASK (tmode
))
12568 op0
= simplify_gen_binary (AND
, tmode
,
12569 SUBREG_REG (XEXP (op0
, 0)),
12570 gen_int_mode (c1
, tmode
));
12571 op0
= gen_lowpart (mode
, op0
);
12576 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12577 if (const_op
== 0 && equality_comparison_p
12578 && XEXP (op0
, 1) == const1_rtx
12579 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12581 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12582 XEXP (XEXP (op0
, 0), 0), 1);
12583 code
= (code
== NE
? EQ
: NE
);
12587 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12588 (eq (and (lshiftrt X) 1) 0).
12589 Also handle the case where (not X) is expressed using xor. */
12590 if (const_op
== 0 && equality_comparison_p
12591 && XEXP (op0
, 1) == const1_rtx
12592 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12594 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12595 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12597 if (GET_CODE (shift_op
) == NOT
12598 || (GET_CODE (shift_op
) == XOR
12599 && CONST_INT_P (XEXP (shift_op
, 1))
12600 && CONST_INT_P (shift_count
)
12601 && HWI_COMPUTABLE_MODE_P (mode
)
12602 && (UINTVAL (XEXP (shift_op
, 1))
12603 == HOST_WIDE_INT_1U
12604 << INTVAL (shift_count
))))
12607 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12608 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12609 code
= (code
== NE
? EQ
: NE
);
12616 /* If we have (compare (ashift FOO N) (const_int C)) and
12617 the high order N bits of FOO (N+1 if an inequality comparison)
12618 are known to be zero, we can do this by comparing FOO with C
12619 shifted right N bits so long as the low-order N bits of C are
12621 if (CONST_INT_P (XEXP (op0
, 1))
12622 && INTVAL (XEXP (op0
, 1)) >= 0
12623 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12624 < HOST_BITS_PER_WIDE_INT
)
12625 && (((unsigned HOST_WIDE_INT
) const_op
12626 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12628 && mode_width
<= HOST_BITS_PER_WIDE_INT
12629 && (nonzero_bits (XEXP (op0
, 0), mode
)
12630 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12631 + ! equality_comparison_p
))) == 0)
12633 /* We must perform a logical shift, not an arithmetic one,
12634 as we want the top N bits of C to be zero. */
12635 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12637 temp
>>= INTVAL (XEXP (op0
, 1));
12638 op1
= gen_int_mode (temp
, mode
);
12639 op0
= XEXP (op0
, 0);
12643 /* If we are doing a sign bit comparison, it means we are testing
12644 a particular bit. Convert it to the appropriate AND. */
12645 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12646 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12648 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12651 - INTVAL (XEXP (op0
, 1)))));
12652 code
= (code
== LT
? NE
: EQ
);
12656 /* If this an equality comparison with zero and we are shifting
12657 the low bit to the sign bit, we can convert this to an AND of the
12659 if (const_op
== 0 && equality_comparison_p
12660 && CONST_INT_P (XEXP (op0
, 1))
12661 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12663 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12669 /* If this is an equality comparison with zero, we can do this
12670 as a logical shift, which might be much simpler. */
12671 if (equality_comparison_p
&& const_op
== 0
12672 && CONST_INT_P (XEXP (op0
, 1)))
12674 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12676 INTVAL (XEXP (op0
, 1)));
12680 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12681 do the comparison in a narrower mode. */
12682 if (! unsigned_comparison_p
12683 && CONST_INT_P (XEXP (op0
, 1))
12684 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12685 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12686 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12687 MODE_INT
, 1)) != BLKmode
12688 && (((unsigned HOST_WIDE_INT
) const_op
12689 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12690 <= GET_MODE_MASK (tmode
)))
12692 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12696 /* Likewise if OP0 is a PLUS of a sign extension with a
12697 constant, which is usually represented with the PLUS
12698 between the shifts. */
12699 if (! unsigned_comparison_p
12700 && CONST_INT_P (XEXP (op0
, 1))
12701 && GET_CODE (XEXP (op0
, 0)) == PLUS
12702 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12703 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12704 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12705 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12706 MODE_INT
, 1)) != BLKmode
12707 && (((unsigned HOST_WIDE_INT
) const_op
12708 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12709 <= GET_MODE_MASK (tmode
)))
12711 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12712 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12713 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12714 add_const
, XEXP (op0
, 1));
12716 op0
= simplify_gen_binary (PLUS
, tmode
,
12717 gen_lowpart (tmode
, inner
),
12724 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12725 the low order N bits of FOO are known to be zero, we can do this
12726 by comparing FOO with C shifted left N bits so long as no
12727 overflow occurs. Even if the low order N bits of FOO aren't known
12728 to be zero, if the comparison is >= or < we can use the same
12729 optimization and for > or <= by setting all the low
12730 order N bits in the comparison constant. */
12731 if (CONST_INT_P (XEXP (op0
, 1))
12732 && INTVAL (XEXP (op0
, 1)) > 0
12733 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12734 && mode_width
<= HOST_BITS_PER_WIDE_INT
12735 && (((unsigned HOST_WIDE_INT
) const_op
12736 + (GET_CODE (op0
) != LSHIFTRT
12737 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12740 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12742 unsigned HOST_WIDE_INT low_bits
12743 = (nonzero_bits (XEXP (op0
, 0), mode
)
12744 & ((HOST_WIDE_INT_1U
12745 << INTVAL (XEXP (op0
, 1))) - 1));
12746 if (low_bits
== 0 || !equality_comparison_p
)
12748 /* If the shift was logical, then we must make the condition
12750 if (GET_CODE (op0
) == LSHIFTRT
)
12751 code
= unsigned_condition (code
);
12753 const_op
= (unsigned HOST_WIDE_INT
) const_op
12754 << INTVAL (XEXP (op0
, 1));
12756 && (code
== GT
|| code
== GTU
12757 || code
== LE
|| code
== LEU
))
12759 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12760 op1
= GEN_INT (const_op
);
12761 op0
= XEXP (op0
, 0);
12766 /* If we are using this shift to extract just the sign bit, we
12767 can replace this with an LT or GE comparison. */
12769 && (equality_comparison_p
|| sign_bit_comparison_p
)
12770 && CONST_INT_P (XEXP (op0
, 1))
12771 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12773 op0
= XEXP (op0
, 0);
12774 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12786 /* Now make any compound operations involved in this comparison. Then,
12787 check for an outmost SUBREG on OP0 that is not doing anything or is
12788 paradoxical. The latter transformation must only be performed when
12789 it is known that the "extra" bits will be the same in op0 and op1 or
12790 that they don't matter. There are three cases to consider:
12792 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12793 care bits and we can assume they have any convenient value. So
12794 making the transformation is safe.
12796 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12797 In this case the upper bits of op0 are undefined. We should not make
12798 the simplification in that case as we do not know the contents of
12801 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12802 In that case we know those bits are zeros or ones. We must also be
12803 sure that they are the same as the upper bits of op1.
12805 We can never remove a SUBREG for a non-equality comparison because
12806 the sign bit is in a different place in the underlying object. */
12808 rtx_code op0_mco_code
= SET
;
12809 if (op1
== const0_rtx
)
12810 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12812 op0
= make_compound_operation (op0
, op0_mco_code
);
12813 op1
= make_compound_operation (op1
, SET
);
12815 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12816 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12817 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12818 && (code
== NE
|| code
== EQ
))
12820 if (paradoxical_subreg_p (op0
))
12822 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12824 if (REG_P (SUBREG_REG (op0
)))
12826 op0
= SUBREG_REG (op0
);
12827 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12830 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12831 <= HOST_BITS_PER_WIDE_INT
)
12832 && (nonzero_bits (SUBREG_REG (op0
),
12833 GET_MODE (SUBREG_REG (op0
)))
12834 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12836 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12838 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12839 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12840 op0
= SUBREG_REG (op0
), op1
= tem
;
12844 /* We now do the opposite procedure: Some machines don't have compare
12845 insns in all modes. If OP0's mode is an integer mode smaller than a
12846 word and we can't do a compare in that mode, see if there is a larger
12847 mode for which we can do the compare. There are a number of cases in
12848 which we can use the wider mode. */
12850 mode
= GET_MODE (op0
);
12851 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12852 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12853 && ! have_insn_for (COMPARE
, mode
))
12854 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12855 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12856 tmode
= GET_MODE_WIDER_MODE (tmode
))
12857 if (have_insn_for (COMPARE
, tmode
))
12861 /* If this is a test for negative, we can make an explicit
12862 test of the sign bit. Test this first so we can use
12863 a paradoxical subreg to extend OP0. */
12865 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12866 && HWI_COMPUTABLE_MODE_P (mode
))
12868 unsigned HOST_WIDE_INT sign
12869 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12870 op0
= simplify_gen_binary (AND
, tmode
,
12871 gen_lowpart (tmode
, op0
),
12872 gen_int_mode (sign
, tmode
));
12873 code
= (code
== LT
) ? NE
: EQ
;
12877 /* If the only nonzero bits in OP0 and OP1 are those in the
12878 narrower mode and this is an equality or unsigned comparison,
12879 we can use the wider mode. Similarly for sign-extended
12880 values, in which case it is true for all comparisons. */
12881 zero_extended
= ((code
== EQ
|| code
== NE
12882 || code
== GEU
|| code
== GTU
12883 || code
== LEU
|| code
== LTU
)
12884 && (nonzero_bits (op0
, tmode
)
12885 & ~GET_MODE_MASK (mode
)) == 0
12886 && ((CONST_INT_P (op1
)
12887 || (nonzero_bits (op1
, tmode
)
12888 & ~GET_MODE_MASK (mode
)) == 0)));
12891 || ((num_sign_bit_copies (op0
, tmode
)
12892 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12893 - GET_MODE_PRECISION (mode
)))
12894 && (num_sign_bit_copies (op1
, tmode
)
12895 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12896 - GET_MODE_PRECISION (mode
)))))
12898 /* If OP0 is an AND and we don't have an AND in MODE either,
12899 make a new AND in the proper mode. */
12900 if (GET_CODE (op0
) == AND
12901 && !have_insn_for (AND
, mode
))
12902 op0
= simplify_gen_binary (AND
, tmode
,
12903 gen_lowpart (tmode
,
12905 gen_lowpart (tmode
,
12911 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12912 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12916 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12917 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12924 /* We may have changed the comparison operands. Re-canonicalize. */
12925 if (swap_commutative_operands_p (op0
, op1
))
12927 std::swap (op0
, op1
);
12928 code
= swap_condition (code
);
12931 /* If this machine only supports a subset of valid comparisons, see if we
12932 can convert an unsupported one into a supported one. */
12933 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12941 /* Utility function for record_value_for_reg. Count number of
12946 enum rtx_code code
= GET_CODE (x
);
12950 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12951 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12953 rtx x0
= XEXP (x
, 0);
12954 rtx x1
= XEXP (x
, 1);
12957 return 1 + 2 * count_rtxs (x0
);
12959 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12960 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12961 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12962 return 2 + 2 * count_rtxs (x0
)
12963 + count_rtxs (x
== XEXP (x1
, 0)
12964 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12966 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12967 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12968 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12969 return 2 + 2 * count_rtxs (x1
)
12970 + count_rtxs (x
== XEXP (x0
, 0)
12971 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12974 fmt
= GET_RTX_FORMAT (code
);
12975 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12977 ret
+= count_rtxs (XEXP (x
, i
));
12978 else if (fmt
[i
] == 'E')
12979 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12980 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12985 /* Utility function for following routine. Called when X is part of a value
12986 being stored into last_set_value. Sets last_set_table_tick
12987 for each register mentioned. Similar to mention_regs in cse.c */
12990 update_table_tick (rtx x
)
12992 enum rtx_code code
= GET_CODE (x
);
12993 const char *fmt
= GET_RTX_FORMAT (code
);
12998 unsigned int regno
= REGNO (x
);
12999 unsigned int endregno
= END_REGNO (x
);
13002 for (r
= regno
; r
< endregno
; r
++)
13004 reg_stat_type
*rsp
= ®_stat
[r
];
13005 rsp
->last_set_table_tick
= label_tick
;
13011 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13014 /* Check for identical subexpressions. If x contains
13015 identical subexpression we only have to traverse one of
13017 if (i
== 0 && ARITHMETIC_P (x
))
13019 /* Note that at this point x1 has already been
13021 rtx x0
= XEXP (x
, 0);
13022 rtx x1
= XEXP (x
, 1);
13024 /* If x0 and x1 are identical then there is no need to
13029 /* If x0 is identical to a subexpression of x1 then while
13030 processing x1, x0 has already been processed. Thus we
13031 are done with x. */
13032 if (ARITHMETIC_P (x1
)
13033 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13036 /* If x1 is identical to a subexpression of x0 then we
13037 still have to process the rest of x0. */
13038 if (ARITHMETIC_P (x0
)
13039 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13041 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
13046 update_table_tick (XEXP (x
, i
));
13048 else if (fmt
[i
] == 'E')
13049 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13050 update_table_tick (XVECEXP (x
, i
, j
));
13053 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13054 are saying that the register is clobbered and we no longer know its
13055 value. If INSN is zero, don't update reg_stat[].last_set; this is
13056 only permitted with VALUE also zero and is used to invalidate the
13060 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
13062 unsigned int regno
= REGNO (reg
);
13063 unsigned int endregno
= END_REGNO (reg
);
13065 reg_stat_type
*rsp
;
13067 /* If VALUE contains REG and we have a previous value for REG, substitute
13068 the previous value. */
13069 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
13073 /* Set things up so get_last_value is allowed to see anything set up to
13075 subst_low_luid
= DF_INSN_LUID (insn
);
13076 tem
= get_last_value (reg
);
13078 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13079 it isn't going to be useful and will take a lot of time to process,
13080 so just use the CLOBBER. */
13084 if (ARITHMETIC_P (tem
)
13085 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
13086 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
13087 tem
= XEXP (tem
, 0);
13088 else if (count_occurrences (value
, reg
, 1) >= 2)
13090 /* If there are two or more occurrences of REG in VALUE,
13091 prevent the value from growing too much. */
13092 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
13093 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
13096 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
13100 /* For each register modified, show we don't know its value, that
13101 we don't know about its bitwise content, that its value has been
13102 updated, and that we don't know the location of the death of the
13104 for (i
= regno
; i
< endregno
; i
++)
13106 rsp
= ®_stat
[i
];
13109 rsp
->last_set
= insn
;
13111 rsp
->last_set_value
= 0;
13112 rsp
->last_set_mode
= VOIDmode
;
13113 rsp
->last_set_nonzero_bits
= 0;
13114 rsp
->last_set_sign_bit_copies
= 0;
13115 rsp
->last_death
= 0;
13116 rsp
->truncated_to_mode
= VOIDmode
;
13119 /* Mark registers that are being referenced in this value. */
13121 update_table_tick (value
);
13123 /* Now update the status of each register being set.
13124 If someone is using this register in this block, set this register
13125 to invalid since we will get confused between the two lives in this
13126 basic block. This makes using this register always invalid. In cse, we
13127 scan the table to invalidate all entries using this register, but this
13128 is too much work for us. */
13130 for (i
= regno
; i
< endregno
; i
++)
13132 rsp
= ®_stat
[i
];
13133 rsp
->last_set_label
= label_tick
;
13135 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13136 rsp
->last_set_invalid
= 1;
13138 rsp
->last_set_invalid
= 0;
13141 /* The value being assigned might refer to X (like in "x++;"). In that
13142 case, we must replace it with (clobber (const_int 0)) to prevent
13144 rsp
= ®_stat
[regno
];
13145 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
13147 value
= copy_rtx (value
);
13148 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
13152 /* For the main register being modified, update the value, the mode, the
13153 nonzero bits, and the number of sign bit copies. */
13155 rsp
->last_set_value
= value
;
13159 machine_mode mode
= GET_MODE (reg
);
13160 subst_low_luid
= DF_INSN_LUID (insn
);
13161 rsp
->last_set_mode
= mode
;
13162 if (GET_MODE_CLASS (mode
) == MODE_INT
13163 && HWI_COMPUTABLE_MODE_P (mode
))
13164 mode
= nonzero_bits_mode
;
13165 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13166 rsp
->last_set_sign_bit_copies
13167 = num_sign_bit_copies (value
, GET_MODE (reg
));
13171 /* Called via note_stores from record_dead_and_set_regs to handle one
13172 SET or CLOBBER in an insn. DATA is the instruction in which the
13173 set is occurring. */
13176 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13178 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13180 if (GET_CODE (dest
) == SUBREG
)
13181 dest
= SUBREG_REG (dest
);
13183 if (!record_dead_insn
)
13186 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13192 /* If we are setting the whole register, we know its value. Otherwise
13193 show that we don't know the value. We can handle SUBREG in
13195 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13196 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13197 else if (GET_CODE (setter
) == SET
13198 && GET_CODE (SET_DEST (setter
)) == SUBREG
13199 && SUBREG_REG (SET_DEST (setter
)) == dest
13200 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
13201 && subreg_lowpart_p (SET_DEST (setter
)))
13202 record_value_for_reg (dest
, record_dead_insn
,
13203 gen_lowpart (GET_MODE (dest
),
13204 SET_SRC (setter
)));
13206 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13208 else if (MEM_P (dest
)
13209 /* Ignore pushes, they clobber nothing. */
13210 && ! push_operand (dest
, GET_MODE (dest
)))
13211 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13214 /* Update the records of when each REG was most recently set or killed
13215 for the things done by INSN. This is the last thing done in processing
13216 INSN in the combiner loop.
13218 We update reg_stat[], in particular fields last_set, last_set_value,
13219 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13220 last_death, and also the similar information mem_last_set (which insn
13221 most recently modified memory) and last_call_luid (which insn was the
13222 most recent subroutine call). */
13225 record_dead_and_set_regs (rtx_insn
*insn
)
13230 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13232 if (REG_NOTE_KIND (link
) == REG_DEAD
13233 && REG_P (XEXP (link
, 0)))
13235 unsigned int regno
= REGNO (XEXP (link
, 0));
13236 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13238 for (i
= regno
; i
< endregno
; i
++)
13240 reg_stat_type
*rsp
;
13242 rsp
= ®_stat
[i
];
13243 rsp
->last_death
= insn
;
13246 else if (REG_NOTE_KIND (link
) == REG_INC
)
13247 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13252 hard_reg_set_iterator hrsi
;
13253 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
13255 reg_stat_type
*rsp
;
13257 rsp
= ®_stat
[i
];
13258 rsp
->last_set_invalid
= 1;
13259 rsp
->last_set
= insn
;
13260 rsp
->last_set_value
= 0;
13261 rsp
->last_set_mode
= VOIDmode
;
13262 rsp
->last_set_nonzero_bits
= 0;
13263 rsp
->last_set_sign_bit_copies
= 0;
13264 rsp
->last_death
= 0;
13265 rsp
->truncated_to_mode
= VOIDmode
;
13268 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13270 /* We can't combine into a call pattern. Remember, though, that
13271 the return value register is set at this LUID. We could
13272 still replace a register with the return value from the
13273 wrong subroutine call! */
13274 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
13277 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
13280 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13281 register present in the SUBREG, so for each such SUBREG go back and
13282 adjust nonzero and sign bit information of the registers that are
13283 known to have some zero/sign bits set.
13285 This is needed because when combine blows the SUBREGs away, the
13286 information on zero/sign bits is lost and further combines can be
13287 missed because of that. */
13290 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13292 struct insn_link
*links
;
13294 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13295 machine_mode mode
= GET_MODE (subreg
);
13297 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
13300 for (links
= LOG_LINKS (insn
); links
;)
13302 reg_stat_type
*rsp
;
13304 insn
= links
->insn
;
13305 set
= single_set (insn
);
13307 if (! set
|| !REG_P (SET_DEST (set
))
13308 || REGNO (SET_DEST (set
)) != regno
13309 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13311 links
= links
->next
;
13315 rsp
= ®_stat
[regno
];
13316 if (rsp
->last_set
== insn
)
13318 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13319 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13322 if (REG_P (SET_SRC (set
)))
13324 regno
= REGNO (SET_SRC (set
));
13325 links
= LOG_LINKS (insn
);
13332 /* Check if X, a register, is known to contain a value already
13333 truncated to MODE. In this case we can use a subreg to refer to
13334 the truncated value even though in the generic case we would need
13335 an explicit truncation. */
13338 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13340 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13341 machine_mode truncated
= rsp
->truncated_to_mode
;
13344 || rsp
->truncation_label
< label_tick_ebb_start
)
13346 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
13348 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13353 /* If X is a hard reg or a subreg record the mode that the register is
13354 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13355 to turn a truncate into a subreg using this information. Return true
13356 if traversing X is complete. */
13359 record_truncated_value (rtx x
)
13361 machine_mode truncated_mode
;
13362 reg_stat_type
*rsp
;
13364 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13366 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13367 truncated_mode
= GET_MODE (x
);
13369 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
13372 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13375 x
= SUBREG_REG (x
);
13377 /* ??? For hard-regs we now record everything. We might be able to
13378 optimize this using last_set_mode. */
13379 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13380 truncated_mode
= GET_MODE (x
);
13384 rsp
= ®_stat
[REGNO (x
)];
13385 if (rsp
->truncated_to_mode
== 0
13386 || rsp
->truncation_label
< label_tick_ebb_start
13387 || (GET_MODE_SIZE (truncated_mode
)
13388 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
13390 rsp
->truncated_to_mode
= truncated_mode
;
13391 rsp
->truncation_label
= label_tick
;
13397 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13398 the modes they are used in. This can help truning TRUNCATEs into
13402 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13404 subrtx_var_iterator::array_type array
;
13405 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13406 if (record_truncated_value (*iter
))
13407 iter
.skip_subrtxes ();
13410 /* Scan X for promoted SUBREGs. For each one found,
13411 note what it implies to the registers used in it. */
13414 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13416 if (GET_CODE (x
) == SUBREG
13417 && SUBREG_PROMOTED_VAR_P (x
)
13418 && REG_P (SUBREG_REG (x
)))
13419 record_promoted_value (insn
, x
);
13422 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13425 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13429 check_promoted_subreg (insn
, XEXP (x
, i
));
13433 if (XVEC (x
, i
) != 0)
13434 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13435 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13441 /* Verify that all the registers and memory references mentioned in *LOC are
13442 still valid. *LOC was part of a value set in INSN when label_tick was
13443 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13444 the invalid references with (clobber (const_int 0)) and return 1. This
13445 replacement is useful because we often can get useful information about
13446 the form of a value (e.g., if it was produced by a shift that always
13447 produces -1 or 0) even though we don't know exactly what registers it
13448 was produced from. */
13451 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13454 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13455 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13460 unsigned int regno
= REGNO (x
);
13461 unsigned int endregno
= END_REGNO (x
);
13464 for (j
= regno
; j
< endregno
; j
++)
13466 reg_stat_type
*rsp
= ®_stat
[j
];
13467 if (rsp
->last_set_invalid
13468 /* If this is a pseudo-register that was only set once and not
13469 live at the beginning of the function, it is always valid. */
13470 || (! (regno
>= FIRST_PSEUDO_REGISTER
13471 && regno
< reg_n_sets_max
13472 && REG_N_SETS (regno
) == 1
13473 && (!REGNO_REG_SET_P
13474 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13476 && rsp
->last_set_label
> tick
))
13479 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13486 /* If this is a memory reference, make sure that there were no stores after
13487 it that might have clobbered the value. We don't have alias info, so we
13488 assume any store invalidates it. Moreover, we only have local UIDs, so
13489 we also assume that there were stores in the intervening basic blocks. */
13490 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13491 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13494 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13498 for (i
= 0; i
< len
; i
++)
13502 /* Check for identical subexpressions. If x contains
13503 identical subexpression we only have to traverse one of
13505 if (i
== 1 && ARITHMETIC_P (x
))
13507 /* Note that at this point x0 has already been checked
13508 and found valid. */
13509 rtx x0
= XEXP (x
, 0);
13510 rtx x1
= XEXP (x
, 1);
13512 /* If x0 and x1 are identical then x is also valid. */
13516 /* If x1 is identical to a subexpression of x0 then
13517 while checking x0, x1 has already been checked. Thus
13518 it is valid and so as x. */
13519 if (ARITHMETIC_P (x0
)
13520 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13523 /* If x0 is identical to a subexpression of x1 then x is
13524 valid iff the rest of x1 is valid. */
13525 if (ARITHMETIC_P (x1
)
13526 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13528 get_last_value_validate (&XEXP (x1
,
13529 x0
== XEXP (x1
, 0) ? 1 : 0),
13530 insn
, tick
, replace
);
13533 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13537 else if (fmt
[i
] == 'E')
13538 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13539 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13540 insn
, tick
, replace
) == 0)
13544 /* If we haven't found a reason for it to be invalid, it is valid. */
13548 /* Get the last value assigned to X, if known. Some registers
13549 in the value may be replaced with (clobber (const_int 0)) if their value
13550 is known longer known reliably. */
13553 get_last_value (const_rtx x
)
13555 unsigned int regno
;
13557 reg_stat_type
*rsp
;
13559 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13560 then convert it to the desired mode. If this is a paradoxical SUBREG,
13561 we cannot predict what values the "extra" bits might have. */
13562 if (GET_CODE (x
) == SUBREG
13563 && subreg_lowpart_p (x
)
13564 && !paradoxical_subreg_p (x
)
13565 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13566 return gen_lowpart (GET_MODE (x
), value
);
13572 rsp
= ®_stat
[regno
];
13573 value
= rsp
->last_set_value
;
13575 /* If we don't have a value, or if it isn't for this basic block and
13576 it's either a hard register, set more than once, or it's a live
13577 at the beginning of the function, return 0.
13579 Because if it's not live at the beginning of the function then the reg
13580 is always set before being used (is never used without being set).
13581 And, if it's set only once, and it's always set before use, then all
13582 uses must have the same last value, even if it's not from this basic
13586 || (rsp
->last_set_label
< label_tick_ebb_start
13587 && (regno
< FIRST_PSEUDO_REGISTER
13588 || regno
>= reg_n_sets_max
13589 || REG_N_SETS (regno
) != 1
13591 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13594 /* If the value was set in a later insn than the ones we are processing,
13595 we can't use it even if the register was only set once. */
13596 if (rsp
->last_set_label
== label_tick
13597 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13600 /* If fewer bits were set than what we are asked for now, we cannot use
13602 if (GET_MODE_PRECISION (rsp
->last_set_mode
)
13603 < GET_MODE_PRECISION (GET_MODE (x
)))
13606 /* If the value has all its registers valid, return it. */
13607 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13610 /* Otherwise, make a copy and replace any invalid register with
13611 (clobber (const_int 0)). If that fails for some reason, return 0. */
13613 value
= copy_rtx (value
);
13614 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13620 /* Return nonzero if expression X refers to a REG or to memory
13621 that is set in an instruction more recent than FROM_LUID. */
13624 use_crosses_set_p (const_rtx x
, int from_luid
)
13628 enum rtx_code code
= GET_CODE (x
);
13632 unsigned int regno
= REGNO (x
);
13633 unsigned endreg
= END_REGNO (x
);
13635 #ifdef PUSH_ROUNDING
13636 /* Don't allow uses of the stack pointer to be moved,
13637 because we don't know whether the move crosses a push insn. */
13638 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13641 for (; regno
< endreg
; regno
++)
13643 reg_stat_type
*rsp
= ®_stat
[regno
];
13645 && rsp
->last_set_label
== label_tick
13646 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13652 if (code
== MEM
&& mem_last_set
> from_luid
)
13655 fmt
= GET_RTX_FORMAT (code
);
13657 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13662 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13663 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13666 else if (fmt
[i
] == 'e'
13667 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13673 /* Define three variables used for communication between the following
13676 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13677 static int reg_dead_flag
;
13679 /* Function called via note_stores from reg_dead_at_p.
13681 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13682 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13685 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13687 unsigned int regno
, endregno
;
13692 regno
= REGNO (dest
);
13693 endregno
= END_REGNO (dest
);
13694 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13695 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13698 /* Return nonzero if REG is known to be dead at INSN.
13700 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13701 referencing REG, it is dead. If we hit a SET referencing REG, it is
13702 live. Otherwise, see if it is live or dead at the start of the basic
13703 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13704 must be assumed to be always live. */
13707 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13712 /* Set variables for reg_dead_at_p_1. */
13713 reg_dead_regno
= REGNO (reg
);
13714 reg_dead_endregno
= END_REGNO (reg
);
13718 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13719 we allow the machine description to decide whether use-and-clobber
13720 patterns are OK. */
13721 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13723 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13724 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13728 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13729 beginning of basic block. */
13730 block
= BLOCK_FOR_INSN (insn
);
13735 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13738 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13740 return reg_dead_flag
== 1 ? 1 : 0;
13742 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13746 if (insn
== BB_HEAD (block
))
13749 insn
= PREV_INSN (insn
);
13752 /* Look at live-in sets for the basic block that we were in. */
13753 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13754 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13760 /* Note hard registers in X that are used. */
13763 mark_used_regs_combine (rtx x
)
13765 RTX_CODE code
= GET_CODE (x
);
13766 unsigned int regno
;
13777 case ADDR_DIFF_VEC
:
13779 /* CC0 must die in the insn after it is set, so we don't need to take
13780 special note of it here. */
13785 /* If we are clobbering a MEM, mark any hard registers inside the
13786 address as used. */
13787 if (MEM_P (XEXP (x
, 0)))
13788 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13793 /* A hard reg in a wide mode may really be multiple registers.
13794 If so, mark all of them just like the first. */
13795 if (regno
< FIRST_PSEUDO_REGISTER
)
13797 /* None of this applies to the stack, frame or arg pointers. */
13798 if (regno
== STACK_POINTER_REGNUM
13799 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13800 && regno
== HARD_FRAME_POINTER_REGNUM
)
13801 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13802 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13803 || regno
== FRAME_POINTER_REGNUM
)
13806 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13812 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13814 rtx testreg
= SET_DEST (x
);
13816 while (GET_CODE (testreg
) == SUBREG
13817 || GET_CODE (testreg
) == ZERO_EXTRACT
13818 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13819 testreg
= XEXP (testreg
, 0);
13821 if (MEM_P (testreg
))
13822 mark_used_regs_combine (XEXP (testreg
, 0));
13824 mark_used_regs_combine (SET_SRC (x
));
13832 /* Recursively scan the operands of this expression. */
13835 const char *fmt
= GET_RTX_FORMAT (code
);
13837 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13840 mark_used_regs_combine (XEXP (x
, i
));
13841 else if (fmt
[i
] == 'E')
13845 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13846 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13852 /* Remove register number REGNO from the dead registers list of INSN.
13854 Return the note used to record the death, if there was one. */
13857 remove_death (unsigned int regno
, rtx_insn
*insn
)
13859 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13862 remove_note (insn
, note
);
13867 /* For each register (hardware or pseudo) used within expression X, if its
13868 death is in an instruction with luid between FROM_LUID (inclusive) and
13869 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13870 list headed by PNOTES.
13872 That said, don't move registers killed by maybe_kill_insn.
13874 This is done when X is being merged by combination into TO_INSN. These
13875 notes will then be distributed as needed. */
13878 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13883 enum rtx_code code
= GET_CODE (x
);
13887 unsigned int regno
= REGNO (x
);
13888 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13890 /* Don't move the register if it gets killed in between from and to. */
13891 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13892 && ! reg_referenced_p (x
, maybe_kill_insn
))
13896 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13897 && DF_INSN_LUID (where_dead
) >= from_luid
13898 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13900 rtx note
= remove_death (regno
, where_dead
);
13902 /* It is possible for the call above to return 0. This can occur
13903 when last_death points to I2 or I1 that we combined with.
13904 In that case make a new note.
13906 We must also check for the case where X is a hard register
13907 and NOTE is a death note for a range of hard registers
13908 including X. In that case, we must put REG_DEAD notes for
13909 the remaining registers in place of NOTE. */
13911 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13912 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13913 > GET_MODE_SIZE (GET_MODE (x
))))
13915 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13916 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13917 unsigned int ourend
= END_REGNO (x
);
13920 for (i
= deadregno
; i
< deadend
; i
++)
13921 if (i
< regno
|| i
>= ourend
)
13922 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13925 /* If we didn't find any note, or if we found a REG_DEAD note that
13926 covers only part of the given reg, and we have a multi-reg hard
13927 register, then to be safe we must check for REG_DEAD notes
13928 for each register other than the first. They could have
13929 their own REG_DEAD notes lying around. */
13930 else if ((note
== 0
13932 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13933 < GET_MODE_SIZE (GET_MODE (x
)))))
13934 && regno
< FIRST_PSEUDO_REGISTER
13935 && REG_NREGS (x
) > 1)
13937 unsigned int ourend
= END_REGNO (x
);
13938 unsigned int i
, offset
;
13942 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13946 for (i
= regno
+ offset
; i
< ourend
; i
++)
13947 move_deaths (regno_reg_rtx
[i
],
13948 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13951 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13953 XEXP (note
, 1) = *pnotes
;
13957 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13963 else if (GET_CODE (x
) == SET
)
13965 rtx dest
= SET_DEST (x
);
13967 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13969 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13970 that accesses one word of a multi-word item, some
13971 piece of everything register in the expression is used by
13972 this insn, so remove any old death. */
13973 /* ??? So why do we test for equality of the sizes? */
13975 if (GET_CODE (dest
) == ZERO_EXTRACT
13976 || GET_CODE (dest
) == STRICT_LOW_PART
13977 || (GET_CODE (dest
) == SUBREG
13978 && (((GET_MODE_SIZE (GET_MODE (dest
))
13979 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13980 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13981 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13983 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13987 /* If this is some other SUBREG, we know it replaces the entire
13988 value, so use that as the destination. */
13989 if (GET_CODE (dest
) == SUBREG
)
13990 dest
= SUBREG_REG (dest
);
13992 /* If this is a MEM, adjust deaths of anything used in the address.
13993 For a REG (the only other possibility), the entire value is
13994 being replaced so the old value is not used in this insn. */
13997 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
14002 else if (GET_CODE (x
) == CLOBBER
)
14005 len
= GET_RTX_LENGTH (code
);
14006 fmt
= GET_RTX_FORMAT (code
);
14008 for (i
= 0; i
< len
; i
++)
14013 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
14014 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
14017 else if (fmt
[i
] == 'e')
14018 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14022 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14023 pattern of an insn. X must be a REG. */
14026 reg_bitfield_target_p (rtx x
, rtx body
)
14030 if (GET_CODE (body
) == SET
)
14032 rtx dest
= SET_DEST (body
);
14034 unsigned int regno
, tregno
, endregno
, endtregno
;
14036 if (GET_CODE (dest
) == ZERO_EXTRACT
)
14037 target
= XEXP (dest
, 0);
14038 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
14039 target
= SUBREG_REG (XEXP (dest
, 0));
14043 if (GET_CODE (target
) == SUBREG
)
14044 target
= SUBREG_REG (target
);
14046 if (!REG_P (target
))
14049 tregno
= REGNO (target
), regno
= REGNO (x
);
14050 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
14051 return target
== x
;
14053 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
14054 endregno
= end_hard_regno (GET_MODE (x
), regno
);
14056 return endregno
> tregno
&& regno
< endtregno
;
14059 else if (GET_CODE (body
) == PARALLEL
)
14060 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
14061 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
14067 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14068 as appropriate. I3 and I2 are the insns resulting from the combination
14069 insns including FROM (I2 may be zero).
14071 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14072 not need REG_DEAD notes because they are being substituted for. This
14073 saves searching in the most common cases.
14075 Each note in the list is either ignored or placed on some insns, depending
14076 on the type of note. */
14079 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
14080 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
14082 rtx note
, next_note
;
14084 rtx_insn
*tem_insn
;
14086 for (note
= notes
; note
; note
= next_note
)
14088 rtx_insn
*place
= 0, *place2
= 0;
14090 next_note
= XEXP (note
, 1);
14091 switch (REG_NOTE_KIND (note
))
14095 /* Doesn't matter much where we put this, as long as it's somewhere.
14096 It is preferable to keep these notes on branches, which is most
14097 likely to be i3. */
14101 case REG_NON_LOCAL_GOTO
:
14106 gcc_assert (i2
&& JUMP_P (i2
));
14111 case REG_EH_REGION
:
14112 /* These notes must remain with the call or trapping instruction. */
14115 else if (i2
&& CALL_P (i2
))
14119 gcc_assert (cfun
->can_throw_non_call_exceptions
);
14120 if (may_trap_p (i3
))
14122 else if (i2
&& may_trap_p (i2
))
14124 /* ??? Otherwise assume we've combined things such that we
14125 can now prove that the instructions can't trap. Drop the
14126 note in this case. */
14130 case REG_ARGS_SIZE
:
14131 /* ??? How to distribute between i3-i1. Assume i3 contains the
14132 entire adjustment. Assert i3 contains at least some adjust. */
14133 if (!noop_move_p (i3
))
14135 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
14136 /* fixup_args_size_notes looks at REG_NORETURN note,
14137 so ensure the note is placed there first. */
14141 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14142 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14146 XEXP (n
, 1) = REG_NOTES (i3
);
14147 REG_NOTES (i3
) = n
;
14151 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14152 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14153 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14154 gcc_assert (old_size
!= args_size
14156 && !ACCUMULATE_OUTGOING_ARGS
14157 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14164 case REG_CALL_DECL
:
14165 /* These notes must remain with the call. It should not be
14166 possible for both I2 and I3 to be a call. */
14171 gcc_assert (i2
&& CALL_P (i2
));
14177 /* Any clobbers for i3 may still exist, and so we must process
14178 REG_UNUSED notes from that insn.
14180 Any clobbers from i2 or i1 can only exist if they were added by
14181 recog_for_combine. In that case, recog_for_combine created the
14182 necessary REG_UNUSED notes. Trying to keep any original
14183 REG_UNUSED notes from these insns can cause incorrect output
14184 if it is for the same register as the original i3 dest.
14185 In that case, we will notice that the register is set in i3,
14186 and then add a REG_UNUSED note for the destination of i3, which
14187 is wrong. However, it is possible to have REG_UNUSED notes from
14188 i2 or i1 for register which were both used and clobbered, so
14189 we keep notes from i2 or i1 if they will turn into REG_DEAD
14192 /* If this register is set or clobbered in I3, put the note there
14193 unless there is one already. */
14194 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14196 if (from_insn
!= i3
)
14199 if (! (REG_P (XEXP (note
, 0))
14200 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14201 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14204 /* Otherwise, if this register is used by I3, then this register
14205 now dies here, so we must put a REG_DEAD note here unless there
14207 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14208 && ! (REG_P (XEXP (note
, 0))
14209 ? find_regno_note (i3
, REG_DEAD
,
14210 REGNO (XEXP (note
, 0)))
14211 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14213 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14221 /* These notes say something about results of an insn. We can
14222 only support them if they used to be on I3 in which case they
14223 remain on I3. Otherwise they are ignored.
14225 If the note refers to an expression that is not a constant, we
14226 must also ignore the note since we cannot tell whether the
14227 equivalence is still true. It might be possible to do
14228 slightly better than this (we only have a problem if I2DEST
14229 or I1DEST is present in the expression), but it doesn't
14230 seem worth the trouble. */
14232 if (from_insn
== i3
14233 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14238 /* These notes say something about how a register is used. They must
14239 be present on any use of the register in I2 or I3. */
14240 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14243 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14252 case REG_LABEL_TARGET
:
14253 case REG_LABEL_OPERAND
:
14254 /* This can show up in several ways -- either directly in the
14255 pattern, or hidden off in the constant pool with (or without?)
14256 a REG_EQUAL note. */
14257 /* ??? Ignore the without-reg_equal-note problem for now. */
14258 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14259 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14260 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14261 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14265 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14266 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14267 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14268 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14276 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14277 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14279 if (place
&& JUMP_P (place
)
14280 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14281 && (JUMP_LABEL (place
) == NULL
14282 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14284 rtx label
= JUMP_LABEL (place
);
14287 JUMP_LABEL (place
) = XEXP (note
, 0);
14288 else if (LABEL_P (label
))
14289 LABEL_NUSES (label
)--;
14292 if (place2
&& JUMP_P (place2
)
14293 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14294 && (JUMP_LABEL (place2
) == NULL
14295 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14297 rtx label
= JUMP_LABEL (place2
);
14300 JUMP_LABEL (place2
) = XEXP (note
, 0);
14301 else if (LABEL_P (label
))
14302 LABEL_NUSES (label
)--;
14308 /* This note says something about the value of a register prior
14309 to the execution of an insn. It is too much trouble to see
14310 if the note is still correct in all situations. It is better
14311 to simply delete it. */
14315 /* If we replaced the right hand side of FROM_INSN with a
14316 REG_EQUAL note, the original use of the dying register
14317 will not have been combined into I3 and I2. In such cases,
14318 FROM_INSN is guaranteed to be the first of the combined
14319 instructions, so we simply need to search back before
14320 FROM_INSN for the previous use or set of this register,
14321 then alter the notes there appropriately.
14323 If the register is used as an input in I3, it dies there.
14324 Similarly for I2, if it is nonzero and adjacent to I3.
14326 If the register is not used as an input in either I3 or I2
14327 and it is not one of the registers we were supposed to eliminate,
14328 there are two possibilities. We might have a non-adjacent I2
14329 or we might have somehow eliminated an additional register
14330 from a computation. For example, we might have had A & B where
14331 we discover that B will always be zero. In this case we will
14332 eliminate the reference to A.
14334 In both cases, we must search to see if we can find a previous
14335 use of A and put the death note there. */
14338 && from_insn
== i2mod
14339 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14340 tem_insn
= from_insn
;
14344 && CALL_P (from_insn
)
14345 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14347 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14349 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14350 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14352 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14354 && reg_overlap_mentioned_p (XEXP (note
, 0),
14356 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14357 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14360 /* If the new I2 sets the same register that is marked dead
14361 in the note, we do not know where to put the note.
14363 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14369 basic_block bb
= this_basic_block
;
14371 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14373 if (!NONDEBUG_INSN_P (tem_insn
))
14375 if (tem_insn
== BB_HEAD (bb
))
14380 /* If the register is being set at TEM_INSN, see if that is all
14381 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14382 into a REG_UNUSED note instead. Don't delete sets to
14383 global register vars. */
14384 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14385 || !global_regs
[REGNO (XEXP (note
, 0))])
14386 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14388 rtx set
= single_set (tem_insn
);
14389 rtx inner_dest
= 0;
14390 rtx_insn
*cc0_setter
= NULL
;
14393 for (inner_dest
= SET_DEST (set
);
14394 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14395 || GET_CODE (inner_dest
) == SUBREG
14396 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14397 inner_dest
= XEXP (inner_dest
, 0))
14400 /* Verify that it was the set, and not a clobber that
14401 modified the register.
14403 CC0 targets must be careful to maintain setter/user
14404 pairs. If we cannot delete the setter due to side
14405 effects, mark the user with an UNUSED note instead
14408 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14409 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14411 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14412 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14413 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14415 /* Move the notes and links of TEM_INSN elsewhere.
14416 This might delete other dead insns recursively.
14417 First set the pattern to something that won't use
14419 rtx old_notes
= REG_NOTES (tem_insn
);
14421 PATTERN (tem_insn
) = pc_rtx
;
14422 REG_NOTES (tem_insn
) = NULL
;
14424 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14425 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14426 distribute_links (LOG_LINKS (tem_insn
));
14428 unsigned int regno
= REGNO (XEXP (note
, 0));
14429 reg_stat_type
*rsp
= ®_stat
[regno
];
14430 if (rsp
->last_set
== tem_insn
)
14431 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14433 SET_INSN_DELETED (tem_insn
);
14434 if (tem_insn
== i2
)
14437 /* Delete the setter too. */
14440 PATTERN (cc0_setter
) = pc_rtx
;
14441 old_notes
= REG_NOTES (cc0_setter
);
14442 REG_NOTES (cc0_setter
) = NULL
;
14444 distribute_notes (old_notes
, cc0_setter
,
14446 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14447 distribute_links (LOG_LINKS (cc0_setter
));
14449 SET_INSN_DELETED (cc0_setter
);
14450 if (cc0_setter
== i2
)
14456 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14458 /* If there isn't already a REG_UNUSED note, put one
14459 here. Do not place a REG_DEAD note, even if
14460 the register is also used here; that would not
14461 match the algorithm used in lifetime analysis
14462 and can cause the consistency check in the
14463 scheduler to fail. */
14464 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14465 REGNO (XEXP (note
, 0))))
14470 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14471 || (CALL_P (tem_insn
)
14472 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14476 /* If we are doing a 3->2 combination, and we have a
14477 register which formerly died in i3 and was not used
14478 by i2, which now no longer dies in i3 and is used in
14479 i2 but does not die in i2, and place is between i2
14480 and i3, then we may need to move a link from place to
14482 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14484 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14485 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14487 struct insn_link
*links
= LOG_LINKS (place
);
14488 LOG_LINKS (place
) = NULL
;
14489 distribute_links (links
);
14494 if (tem_insn
== BB_HEAD (bb
))
14500 /* If the register is set or already dead at PLACE, we needn't do
14501 anything with this note if it is still a REG_DEAD note.
14502 We check here if it is set at all, not if is it totally replaced,
14503 which is what `dead_or_set_p' checks, so also check for it being
14506 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14508 unsigned int regno
= REGNO (XEXP (note
, 0));
14509 reg_stat_type
*rsp
= ®_stat
[regno
];
14511 if (dead_or_set_p (place
, XEXP (note
, 0))
14512 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14514 /* Unless the register previously died in PLACE, clear
14515 last_death. [I no longer understand why this is
14517 if (rsp
->last_death
!= place
)
14518 rsp
->last_death
= 0;
14522 rsp
->last_death
= place
;
14524 /* If this is a death note for a hard reg that is occupying
14525 multiple registers, ensure that we are still using all
14526 parts of the object. If we find a piece of the object
14527 that is unused, we must arrange for an appropriate REG_DEAD
14528 note to be added for it. However, we can't just emit a USE
14529 and tag the note to it, since the register might actually
14530 be dead; so we recourse, and the recursive call then finds
14531 the previous insn that used this register. */
14533 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14535 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14536 bool all_used
= true;
14539 for (i
= regno
; i
< endregno
; i
++)
14540 if ((! refers_to_regno_p (i
, PATTERN (place
))
14541 && ! find_regno_fusage (place
, USE
, i
))
14542 || dead_or_set_regno_p (place
, i
))
14550 /* Put only REG_DEAD notes for pieces that are
14551 not already dead or set. */
14553 for (i
= regno
; i
< endregno
;
14554 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14556 rtx piece
= regno_reg_rtx
[i
];
14557 basic_block bb
= this_basic_block
;
14559 if (! dead_or_set_p (place
, piece
)
14560 && ! reg_bitfield_target_p (piece
,
14563 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14566 distribute_notes (new_note
, place
, place
,
14567 NULL
, NULL_RTX
, NULL_RTX
,
14570 else if (! refers_to_regno_p (i
, PATTERN (place
))
14571 && ! find_regno_fusage (place
, USE
, i
))
14572 for (tem_insn
= PREV_INSN (place
); ;
14573 tem_insn
= PREV_INSN (tem_insn
))
14575 if (!NONDEBUG_INSN_P (tem_insn
))
14577 if (tem_insn
== BB_HEAD (bb
))
14581 if (dead_or_set_p (tem_insn
, piece
)
14582 || reg_bitfield_target_p (piece
,
14583 PATTERN (tem_insn
)))
14585 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14598 /* Any other notes should not be present at this point in the
14600 gcc_unreachable ();
14605 XEXP (note
, 1) = REG_NOTES (place
);
14606 REG_NOTES (place
) = note
;
14610 add_shallow_copy_of_reg_note (place2
, note
);
14614 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14615 I3, I2, and I1 to new locations. This is also called to add a link
14616 pointing at I3 when I3's destination is changed. */
14619 distribute_links (struct insn_link
*links
)
14621 struct insn_link
*link
, *next_link
;
14623 for (link
= links
; link
; link
= next_link
)
14625 rtx_insn
*place
= 0;
14629 next_link
= link
->next
;
14631 /* If the insn that this link points to is a NOTE, ignore it. */
14632 if (NOTE_P (link
->insn
))
14636 rtx pat
= PATTERN (link
->insn
);
14637 if (GET_CODE (pat
) == SET
)
14639 else if (GET_CODE (pat
) == PARALLEL
)
14642 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14644 set
= XVECEXP (pat
, 0, i
);
14645 if (GET_CODE (set
) != SET
)
14648 reg
= SET_DEST (set
);
14649 while (GET_CODE (reg
) == ZERO_EXTRACT
14650 || GET_CODE (reg
) == STRICT_LOW_PART
14651 || GET_CODE (reg
) == SUBREG
)
14652 reg
= XEXP (reg
, 0);
14657 if (REGNO (reg
) == link
->regno
)
14660 if (i
== XVECLEN (pat
, 0))
14666 reg
= SET_DEST (set
);
14668 while (GET_CODE (reg
) == ZERO_EXTRACT
14669 || GET_CODE (reg
) == STRICT_LOW_PART
14670 || GET_CODE (reg
) == SUBREG
)
14671 reg
= XEXP (reg
, 0);
14673 /* A LOG_LINK is defined as being placed on the first insn that uses
14674 a register and points to the insn that sets the register. Start
14675 searching at the next insn after the target of the link and stop
14676 when we reach a set of the register or the end of the basic block.
14678 Note that this correctly handles the link that used to point from
14679 I3 to I2. Also note that not much searching is typically done here
14680 since most links don't point very far away. */
14682 for (insn
= NEXT_INSN (link
->insn
);
14683 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14684 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14685 insn
= NEXT_INSN (insn
))
14686 if (DEBUG_INSN_P (insn
))
14688 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14690 if (reg_referenced_p (reg
, PATTERN (insn
)))
14694 else if (CALL_P (insn
)
14695 && find_reg_fusage (insn
, USE
, reg
))
14700 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14703 /* If we found a place to put the link, place it there unless there
14704 is already a link to the same insn as LINK at that point. */
14708 struct insn_link
*link2
;
14710 FOR_EACH_LOG_LINK (link2
, place
)
14711 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14716 link
->next
= LOG_LINKS (place
);
14717 LOG_LINKS (place
) = link
;
14719 /* Set added_links_insn to the earliest insn we added a
14721 if (added_links_insn
== 0
14722 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14723 added_links_insn
= place
;
14729 /* Check for any register or memory mentioned in EQUIV that is not
14730 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14731 of EXPR where some registers may have been replaced by constants. */
14734 unmentioned_reg_p (rtx equiv
, rtx expr
)
14736 subrtx_iterator::array_type array
;
14737 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14739 const_rtx x
= *iter
;
14740 if ((REG_P (x
) || MEM_P (x
))
14741 && !reg_mentioned_p (x
, expr
))
14747 DEBUG_FUNCTION
void
14748 dump_combine_stats (FILE *file
)
14752 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14753 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14757 dump_combine_total_stats (FILE *file
)
14761 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14762 total_attempts
, total_merges
, total_extras
, total_successes
);
14765 /* Try combining insns through substitution. */
14766 static unsigned int
14767 rest_of_handle_combine (void)
14769 int rebuild_jump_labels_after_combine
;
14771 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14772 df_note_add_problem ();
14775 regstat_init_n_sets_and_refs ();
14776 reg_n_sets_max
= max_reg_num ();
14778 rebuild_jump_labels_after_combine
14779 = combine_instructions (get_insns (), max_reg_num ());
14781 /* Combining insns may have turned an indirect jump into a
14782 direct jump. Rebuild the JUMP_LABEL fields of jumping
14784 if (rebuild_jump_labels_after_combine
)
14786 if (dom_info_available_p (CDI_DOMINATORS
))
14787 free_dominance_info (CDI_DOMINATORS
);
14788 timevar_push (TV_JUMP
);
14789 rebuild_jump_labels (get_insns ());
14791 timevar_pop (TV_JUMP
);
14794 regstat_free_n_sets_and_refs ();
14800 const pass_data pass_data_combine
=
14802 RTL_PASS
, /* type */
14803 "combine", /* name */
14804 OPTGROUP_NONE
, /* optinfo_flags */
14805 TV_COMBINE
, /* tv_id */
14806 PROP_cfglayout
, /* properties_required */
14807 0, /* properties_provided */
14808 0, /* properties_destroyed */
14809 0, /* todo_flags_start */
14810 TODO_df_finish
, /* todo_flags_finish */
14813 class pass_combine
: public rtl_opt_pass
14816 pass_combine (gcc::context
*ctxt
)
14817 : rtl_opt_pass (pass_data_combine
, ctxt
)
14820 /* opt_pass methods: */
14821 virtual bool gate (function
*) { return (optimize
> 0); }
14822 virtual unsigned int execute (function
*)
14824 return rest_of_handle_combine ();
14827 }; // class pass_combine
14829 } // anon namespace
14832 make_pass_combine (gcc::context
*ctxt
)
14834 return new pass_combine (ctxt
);