1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts
;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges
;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras
;
121 /* Number of instructions combined in this function. */
123 static int combine_successes
;
125 /* Totals over entire compilation. */
127 static int total_attempts
, total_merges
, total_extras
, total_successes
;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs
;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs
;
146 typedef struct reg_stat_struct
{
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label
;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 DEF_VEC_O(reg_stat_type
);
256 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
258 static VEC(reg_stat_type
,heap
) *reg_stat
;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set
;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid
;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn
;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid
;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs
;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn
;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block
;
300 static bool optimize_this_for_speed_p
;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known
;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost
;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
317 struct insn_link
*next
;
320 static struct insn_link
**uid_log_links
;
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
328 /* Links for LOG_LINKS are allocated from this obstack. */
330 static struct obstack insn_link_obstack
;
332 /* Allocate a link. */
334 static inline struct insn_link
*
335 alloc_insn_link (rtx insn
, struct insn_link
*next
)
338 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
339 sizeof (struct insn_link
));
345 /* Incremented for each basic block. */
347 static int label_tick
;
349 /* Reset to label_tick for each extended basic block in scanning order. */
351 static int label_tick_ebb_start
;
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
356 static enum machine_mode nonzero_bits_mode
;
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
364 static int nonzero_sign_valid
;
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
370 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
};
376 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
377 union { rtx
*r
; int *i
; } where
;
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
393 static struct undobuf undobuf
;
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
398 static int n_occurrences
;
400 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
402 unsigned HOST_WIDE_INT
,
403 unsigned HOST_WIDE_INT
*);
404 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
406 unsigned int, unsigned int *);
407 static void do_SUBST (rtx
*, rtx
);
408 static void do_SUBST_INT (int *, int);
409 static void init_reg_last (void);
410 static void setup_incoming_promotions (rtx
);
411 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
412 static int cant_combine_insn_p (rtx
);
413 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
414 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
415 static int contains_muldiv (rtx
);
416 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *, rtx
);
417 static void undo_all (void);
418 static void undo_commit (void);
419 static rtx
*find_split_point (rtx
*, rtx
, bool);
420 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
421 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
422 static rtx
simplify_if_then_else (rtx
);
423 static rtx
simplify_set (rtx
);
424 static rtx
simplify_logical (rtx
);
425 static rtx
expand_compound_operation (rtx
);
426 static const_rtx
expand_field_assignment (const_rtx
);
427 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
428 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
429 static rtx
extract_left_shift (rtx
, int);
430 static rtx
make_compound_operation (rtx
, enum rtx_code
);
431 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
432 unsigned HOST_WIDE_INT
*);
433 static rtx
canon_reg_for_combine (rtx
, rtx
);
434 static rtx
force_to_mode (rtx
, enum machine_mode
,
435 unsigned HOST_WIDE_INT
, int);
436 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
437 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
438 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
439 static rtx
make_field_assignment (rtx
);
440 static rtx
apply_distributive_law (rtx
);
441 static rtx
distribute_and_simplify_rtx (rtx
, int);
442 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
443 unsigned HOST_WIDE_INT
);
444 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
445 unsigned HOST_WIDE_INT
);
446 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
447 HOST_WIDE_INT
, enum machine_mode
, int *);
448 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
449 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
451 static int recog_for_combine (rtx
*, rtx
, rtx
*);
452 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
453 static enum rtx_code
simplify_compare_const (enum rtx_code
, rtx
, rtx
*);
454 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
455 static void update_table_tick (rtx
);
456 static void record_value_for_reg (rtx
, rtx
, rtx
);
457 static void check_promoted_subreg (rtx
, rtx
);
458 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
459 static void record_dead_and_set_regs (rtx
);
460 static int get_last_value_validate (rtx
*, rtx
, int, int);
461 static rtx
get_last_value (const_rtx
);
462 static int use_crosses_set_p (const_rtx
, int);
463 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
464 static int reg_dead_at_p (rtx
, rtx
);
465 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
466 static int reg_bitfield_target_p (rtx
, rtx
);
467 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
468 static void distribute_links (struct insn_link
*);
469 static void mark_used_regs_combine (rtx
);
470 static void record_promoted_value (rtx
, rtx
);
471 static int unmentioned_reg_p_1 (rtx
*, void *);
472 static bool unmentioned_reg_p (rtx
, rtx
);
473 static int record_truncated_value (rtx
*, void *);
474 static void record_truncated_values (rtx
*, void *);
475 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
476 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
479 /* It is not safe to use ordinary gen_lowpart in combine.
480 See comments in gen_lowpart_for_combine. */
481 #undef RTL_HOOKS_GEN_LOWPART
482 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
484 /* Our implementation of gen_lowpart never emits a new pseudo. */
485 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
486 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
488 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
489 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
491 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
492 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
494 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
495 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
497 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
500 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
501 PATTERN can not be split. Otherwise, it returns an insn sequence.
502 This is a wrapper around split_insns which ensures that the
503 reg_stat vector is made larger if the splitter creates a new
507 combine_split_insns (rtx pattern
, rtx insn
)
512 ret
= split_insns (pattern
, insn
);
513 nregs
= max_reg_num ();
514 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
515 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
519 /* This is used by find_single_use to locate an rtx in LOC that
520 contains exactly one use of DEST, which is typically either a REG
521 or CC0. It returns a pointer to the innermost rtx expression
522 containing DEST. Appearances of DEST that are being used to
523 totally replace it are not counted. */
526 find_single_use_1 (rtx dest
, rtx
*loc
)
529 enum rtx_code code
= GET_CODE (x
);
547 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
548 of a REG that occupies all of the REG, the insn uses DEST if
549 it is mentioned in the destination or the source. Otherwise, we
550 need just check the source. */
551 if (GET_CODE (SET_DEST (x
)) != CC0
552 && GET_CODE (SET_DEST (x
)) != PC
553 && !REG_P (SET_DEST (x
))
554 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
555 && REG_P (SUBREG_REG (SET_DEST (x
)))
556 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
557 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
558 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
559 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
562 return find_single_use_1 (dest
, &SET_SRC (x
));
566 return find_single_use_1 (dest
, &XEXP (x
, 0));
572 /* If it wasn't one of the common cases above, check each expression and
573 vector of this code. Look for a unique usage of DEST. */
575 fmt
= GET_RTX_FORMAT (code
);
576 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
580 if (dest
== XEXP (x
, i
)
581 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
582 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
585 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
588 result
= this_result
;
589 else if (this_result
)
590 /* Duplicate usage. */
593 else if (fmt
[i
] == 'E')
597 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
599 if (XVECEXP (x
, i
, j
) == dest
601 && REG_P (XVECEXP (x
, i
, j
))
602 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
605 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
608 result
= this_result
;
609 else if (this_result
)
619 /* See if DEST, produced in INSN, is used only a single time in the
620 sequel. If so, return a pointer to the innermost rtx expression in which
623 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
625 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
626 care about REG_DEAD notes or LOG_LINKS.
628 Otherwise, we find the single use by finding an insn that has a
629 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
630 only referenced once in that insn, we know that it must be the first
631 and last insn referencing DEST. */
634 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
639 struct insn_link
*link
;
644 next
= NEXT_INSN (insn
);
646 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
649 result
= find_single_use_1 (dest
, &PATTERN (next
));
659 bb
= BLOCK_FOR_INSN (insn
);
660 for (next
= NEXT_INSN (insn
);
661 next
&& BLOCK_FOR_INSN (next
) == bb
;
662 next
= NEXT_INSN (next
))
663 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
665 FOR_EACH_LOG_LINK (link
, next
)
666 if (link
->insn
== insn
)
671 result
= find_single_use_1 (dest
, &PATTERN (next
));
681 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
682 insn. The substitution can be undone by undo_all. If INTO is already
683 set to NEWVAL, do not record this change. Because computing NEWVAL might
684 also call SUBST, we have to compute it before we put anything into
688 do_SUBST (rtx
*into
, rtx newval
)
693 if (oldval
== newval
)
696 /* We'd like to catch as many invalid transformations here as
697 possible. Unfortunately, there are way too many mode changes
698 that are perfectly valid, so we'd waste too much effort for
699 little gain doing the checks here. Focus on catching invalid
700 transformations involving integer constants. */
701 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
702 && CONST_INT_P (newval
))
704 /* Sanity check that we're replacing oldval with a CONST_INT
705 that is a valid sign-extension for the original mode. */
706 gcc_assert (INTVAL (newval
)
707 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
709 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
710 CONST_INT is not valid, because after the replacement, the
711 original mode would be gone. Unfortunately, we can't tell
712 when do_SUBST is called to replace the operand thereof, so we
713 perform this test on oldval instead, checking whether an
714 invalid replacement took place before we got here. */
715 gcc_assert (!(GET_CODE (oldval
) == SUBREG
716 && CONST_INT_P (SUBREG_REG (oldval
))));
717 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
718 && CONST_INT_P (XEXP (oldval
, 0))));
722 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
724 buf
= XNEW (struct undo
);
726 buf
->kind
= UNDO_RTX
;
728 buf
->old_contents
.r
= oldval
;
731 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
734 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
736 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
737 for the value of a HOST_WIDE_INT value (including CONST_INT) is
741 do_SUBST_INT (int *into
, int newval
)
746 if (oldval
== newval
)
750 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
752 buf
= XNEW (struct undo
);
754 buf
->kind
= UNDO_INT
;
756 buf
->old_contents
.i
= oldval
;
759 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
762 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
764 /* Similar to SUBST, but just substitute the mode. This is used when
765 changing the mode of a pseudo-register, so that any other
766 references to the entry in the regno_reg_rtx array will change as
770 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
773 enum machine_mode oldval
= GET_MODE (*into
);
775 if (oldval
== newval
)
779 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
781 buf
= XNEW (struct undo
);
783 buf
->kind
= UNDO_MODE
;
785 buf
->old_contents
.m
= oldval
;
786 adjust_reg_mode (*into
, newval
);
788 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
791 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
793 /* Subroutine of try_combine. Determine whether the replacement patterns
794 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
795 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
796 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
797 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
798 of all the instructions can be estimated and the replacements are more
799 expensive than the original sequence. */
802 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
803 rtx newi2pat
, rtx newotherpat
)
805 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
806 int new_i2_cost
, new_i3_cost
;
807 int old_cost
, new_cost
;
809 /* Lookup the original insn_rtx_costs. */
810 i2_cost
= INSN_COST (i2
);
811 i3_cost
= INSN_COST (i3
);
815 i1_cost
= INSN_COST (i1
);
818 i0_cost
= INSN_COST (i0
);
819 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
820 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
824 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
825 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
831 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
832 i1_cost
= i0_cost
= 0;
835 /* Calculate the replacement insn_rtx_costs. */
836 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
839 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
840 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
841 ? new_i2_cost
+ new_i3_cost
: 0;
845 new_cost
= new_i3_cost
;
849 if (undobuf
.other_insn
)
851 int old_other_cost
, new_other_cost
;
853 old_other_cost
= INSN_COST (undobuf
.other_insn
);
854 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
855 if (old_other_cost
> 0 && new_other_cost
> 0)
857 old_cost
+= old_other_cost
;
858 new_cost
+= new_other_cost
;
864 /* Disallow this combination if both new_cost and old_cost are greater than
865 zero, and new_cost is greater than old cost. */
866 if (old_cost
> 0 && new_cost
> old_cost
)
873 "rejecting combination of insns %d, %d, %d and %d\n",
874 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
876 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
877 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
882 "rejecting combination of insns %d, %d and %d\n",
883 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
884 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
885 i1_cost
, i2_cost
, i3_cost
, old_cost
);
890 "rejecting combination of insns %d and %d\n",
891 INSN_UID (i2
), INSN_UID (i3
));
892 fprintf (dump_file
, "original costs %d + %d = %d\n",
893 i2_cost
, i3_cost
, old_cost
);
898 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
899 new_i2_cost
, new_i3_cost
, new_cost
);
902 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
908 /* Update the uid_insn_cost array with the replacement costs. */
909 INSN_COST (i2
) = new_i2_cost
;
910 INSN_COST (i3
) = new_i3_cost
;
922 /* Delete any insns that copy a register to itself. */
925 delete_noop_moves (void)
932 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
934 next
= NEXT_INSN (insn
);
935 if (INSN_P (insn
) && noop_move_p (insn
))
938 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
940 delete_insn_and_edges (insn
);
947 /* Fill in log links field for all insns. */
950 create_log_links (void)
954 df_ref
*def_vec
, *use_vec
;
956 next_use
= XCNEWVEC (rtx
, max_reg_num ());
958 /* Pass through each block from the end, recording the uses of each
959 register and establishing log links when def is encountered.
960 Note that we do not clear next_use array in order to save time,
961 so we have to test whether the use is in the same basic block as def.
963 There are a few cases below when we do not consider the definition or
964 usage -- these are taken from original flow.c did. Don't ask me why it is
965 done this way; I don't know and if it works, I don't want to know. */
969 FOR_BB_INSNS_REVERSE (bb
, insn
)
971 if (!NONDEBUG_INSN_P (insn
))
974 /* Log links are created only once. */
975 gcc_assert (!LOG_LINKS (insn
));
977 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
979 df_ref def
= *def_vec
;
980 int regno
= DF_REF_REGNO (def
);
983 if (!next_use
[regno
])
986 /* Do not consider if it is pre/post modification in MEM. */
987 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
990 /* Do not make the log link for frame pointer. */
991 if ((regno
== FRAME_POINTER_REGNUM
992 && (! reload_completed
|| frame_pointer_needed
))
993 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
994 || (regno
== HARD_FRAME_POINTER_REGNUM
995 && (! reload_completed
|| frame_pointer_needed
))
997 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
998 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1003 use_insn
= next_use
[regno
];
1004 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1008 We don't build a LOG_LINK for hard registers contained
1009 in ASM_OPERANDs. If these registers get replaced,
1010 we might wind up changing the semantics of the insn,
1011 even if reload can make what appear to be valid
1012 assignments later. */
1013 if (regno
>= FIRST_PSEUDO_REGISTER
1014 || asm_noperands (PATTERN (use_insn
)) < 0)
1016 /* Don't add duplicate links between instructions. */
1017 struct insn_link
*links
;
1018 FOR_EACH_LOG_LINK (links
, use_insn
)
1019 if (insn
== links
->insn
)
1023 LOG_LINKS (use_insn
)
1024 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1027 next_use
[regno
] = NULL_RTX
;
1030 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1032 df_ref use
= *use_vec
;
1033 int regno
= DF_REF_REGNO (use
);
1035 /* Do not consider the usage of the stack pointer
1036 by function call. */
1037 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1040 next_use
[regno
] = insn
;
1048 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1049 true if we found a LOG_LINK that proves that A feeds B. This only works
1050 if there are no instructions between A and B which could have a link
1051 depending on A, since in that case we would not record a link for B.
1052 We also check the implicit dependency created by a cc0 setter/user
1056 insn_a_feeds_b (rtx a
, rtx b
)
1058 struct insn_link
*links
;
1059 FOR_EACH_LOG_LINK (links
, b
)
1060 if (links
->insn
== a
)
1069 /* Main entry point for combiner. F is the first insn of the function.
1070 NREGS is the first unused pseudo-reg number.
1072 Return nonzero if the combiner has turned an indirect jump
1073 instruction into a direct jump. */
1075 combine_instructions (rtx f
, unsigned int nregs
)
1081 struct insn_link
*links
, *nextlinks
;
1083 basic_block last_bb
;
1085 int new_direct_jump_p
= 0;
1087 for (first
= f
; first
&& !INSN_P (first
); )
1088 first
= NEXT_INSN (first
);
1092 combine_attempts
= 0;
1095 combine_successes
= 0;
1097 rtl_hooks
= combine_rtl_hooks
;
1099 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1101 init_recog_no_volatile ();
1103 /* Allocate array for insn info. */
1104 max_uid_known
= get_max_uid ();
1105 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1106 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1107 gcc_obstack_init (&insn_link_obstack
);
1109 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1111 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1112 problems when, for example, we have j <<= 1 in a loop. */
1114 nonzero_sign_valid
= 0;
1115 label_tick
= label_tick_ebb_start
= 1;
1117 /* Scan all SETs and see if we can deduce anything about what
1118 bits are known to be zero for some registers and how many copies
1119 of the sign bit are known to exist for those registers.
1121 Also set any known values so that we can use it while searching
1122 for what bits are known to be set. */
1124 setup_incoming_promotions (first
);
1125 /* Allow the entry block and the first block to fall into the same EBB.
1126 Conceptually the incoming promotions are assigned to the entry block. */
1127 last_bb
= ENTRY_BLOCK_PTR
;
1129 create_log_links ();
1130 FOR_EACH_BB (this_basic_block
)
1132 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1137 if (!single_pred_p (this_basic_block
)
1138 || single_pred (this_basic_block
) != last_bb
)
1139 label_tick_ebb_start
= label_tick
;
1140 last_bb
= this_basic_block
;
1142 FOR_BB_INSNS (this_basic_block
, insn
)
1143 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1149 subst_low_luid
= DF_INSN_LUID (insn
);
1152 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1154 record_dead_and_set_regs (insn
);
1157 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1158 if (REG_NOTE_KIND (links
) == REG_INC
)
1159 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1163 /* Record the current insn_rtx_cost of this instruction. */
1164 if (NONJUMP_INSN_P (insn
))
1165 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1166 optimize_this_for_speed_p
);
1168 fprintf(dump_file
, "insn_cost %d: %d\n",
1169 INSN_UID (insn
), INSN_COST (insn
));
1173 nonzero_sign_valid
= 1;
1175 /* Now scan all the insns in forward order. */
1176 label_tick
= label_tick_ebb_start
= 1;
1178 setup_incoming_promotions (first
);
1179 last_bb
= ENTRY_BLOCK_PTR
;
1181 FOR_EACH_BB (this_basic_block
)
1183 rtx last_combined_insn
= NULL_RTX
;
1184 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1189 if (!single_pred_p (this_basic_block
)
1190 || single_pred (this_basic_block
) != last_bb
)
1191 label_tick_ebb_start
= label_tick
;
1192 last_bb
= this_basic_block
;
1194 rtl_profile_for_bb (this_basic_block
);
1195 for (insn
= BB_HEAD (this_basic_block
);
1196 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1197 insn
= next
? next
: NEXT_INSN (insn
))
1200 if (NONDEBUG_INSN_P (insn
))
1202 while (last_combined_insn
1203 && INSN_DELETED_P (last_combined_insn
))
1204 last_combined_insn
= PREV_INSN (last_combined_insn
);
1205 if (last_combined_insn
== NULL_RTX
1206 || BARRIER_P (last_combined_insn
)
1207 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1208 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1209 last_combined_insn
= insn
;
1211 /* See if we know about function return values before this
1212 insn based upon SUBREG flags. */
1213 check_promoted_subreg (insn
, PATTERN (insn
));
1215 /* See if we can find hardregs and subreg of pseudos in
1216 narrower modes. This could help turning TRUNCATEs
1218 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1220 /* Try this insn with each insn it links back to. */
1222 FOR_EACH_LOG_LINK (links
, insn
)
1223 if ((next
= try_combine (insn
, links
->insn
, NULL_RTX
,
1224 NULL_RTX
, &new_direct_jump_p
,
1225 last_combined_insn
)) != 0)
1228 /* Try each sequence of three linked insns ending with this one. */
1230 FOR_EACH_LOG_LINK (links
, insn
)
1232 rtx link
= links
->insn
;
1234 /* If the linked insn has been replaced by a note, then there
1235 is no point in pursuing this chain any further. */
1239 FOR_EACH_LOG_LINK (nextlinks
, link
)
1240 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1241 NULL_RTX
, &new_direct_jump_p
,
1242 last_combined_insn
)) != 0)
1247 /* Try to combine a jump insn that uses CC0
1248 with a preceding insn that sets CC0, and maybe with its
1249 logical predecessor as well.
1250 This is how we make decrement-and-branch insns.
1251 We need this special code because data flow connections
1252 via CC0 do not get entered in LOG_LINKS. */
1255 && (prev
= prev_nonnote_insn (insn
)) != 0
1256 && NONJUMP_INSN_P (prev
)
1257 && sets_cc0_p (PATTERN (prev
)))
1259 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1261 last_combined_insn
)) != 0)
1264 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1265 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1266 NULL_RTX
, &new_direct_jump_p
,
1267 last_combined_insn
)) != 0)
1271 /* Do the same for an insn that explicitly references CC0. */
1272 if (NONJUMP_INSN_P (insn
)
1273 && (prev
= prev_nonnote_insn (insn
)) != 0
1274 && NONJUMP_INSN_P (prev
)
1275 && sets_cc0_p (PATTERN (prev
))
1276 && GET_CODE (PATTERN (insn
)) == SET
1277 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1279 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1281 last_combined_insn
)) != 0)
1284 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1285 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1286 NULL_RTX
, &new_direct_jump_p
,
1287 last_combined_insn
)) != 0)
1291 /* Finally, see if any of the insns that this insn links to
1292 explicitly references CC0. If so, try this insn, that insn,
1293 and its predecessor if it sets CC0. */
1294 FOR_EACH_LOG_LINK (links
, insn
)
1295 if (NONJUMP_INSN_P (links
->insn
)
1296 && GET_CODE (PATTERN (links
->insn
)) == SET
1297 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1298 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1299 && NONJUMP_INSN_P (prev
)
1300 && sets_cc0_p (PATTERN (prev
))
1301 && (next
= try_combine (insn
, links
->insn
,
1302 prev
, NULL_RTX
, &new_direct_jump_p
,
1303 last_combined_insn
)) != 0)
1307 /* Try combining an insn with two different insns whose results it
1309 FOR_EACH_LOG_LINK (links
, insn
)
1310 for (nextlinks
= links
->next
; nextlinks
;
1311 nextlinks
= nextlinks
->next
)
1312 if ((next
= try_combine (insn
, links
->insn
,
1313 nextlinks
->insn
, NULL_RTX
,
1315 last_combined_insn
)) != 0)
1318 /* Try four-instruction combinations. */
1319 FOR_EACH_LOG_LINK (links
, insn
)
1321 struct insn_link
*next1
;
1322 rtx link
= links
->insn
;
1324 /* If the linked insn has been replaced by a note, then there
1325 is no point in pursuing this chain any further. */
1329 FOR_EACH_LOG_LINK (next1
, link
)
1331 rtx link1
= next1
->insn
;
1334 /* I0 -> I1 -> I2 -> I3. */
1335 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1336 if ((next
= try_combine (insn
, link
, link1
,
1339 last_combined_insn
)) != 0)
1341 /* I0, I1 -> I2, I2 -> I3. */
1342 for (nextlinks
= next1
->next
; nextlinks
;
1343 nextlinks
= nextlinks
->next
)
1344 if ((next
= try_combine (insn
, link
, link1
,
1347 last_combined_insn
)) != 0)
1351 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1353 rtx link1
= next1
->insn
;
1356 /* I0 -> I2; I1, I2 -> I3. */
1357 FOR_EACH_LOG_LINK (nextlinks
, link
)
1358 if ((next
= try_combine (insn
, link
, link1
,
1361 last_combined_insn
)) != 0)
1363 /* I0 -> I1; I1, I2 -> I3. */
1364 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1365 if ((next
= try_combine (insn
, link
, link1
,
1368 last_combined_insn
)) != 0)
1373 /* Try this insn with each REG_EQUAL note it links back to. */
1374 FOR_EACH_LOG_LINK (links
, insn
)
1377 rtx temp
= links
->insn
;
1378 if ((set
= single_set (temp
)) != 0
1379 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1380 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1381 /* Avoid using a register that may already been marked
1382 dead by an earlier instruction. */
1383 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1384 && (GET_MODE (note
) == VOIDmode
1385 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1386 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1388 /* Temporarily replace the set's source with the
1389 contents of the REG_EQUAL note. The insn will
1390 be deleted or recognized by try_combine. */
1391 rtx orig
= SET_SRC (set
);
1392 SET_SRC (set
) = note
;
1394 i2mod_old_rhs
= copy_rtx (orig
);
1395 i2mod_new_rhs
= copy_rtx (note
);
1396 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1398 last_combined_insn
);
1402 SET_SRC (set
) = orig
;
1407 record_dead_and_set_regs (insn
);
1415 default_rtl_profile ();
1417 new_direct_jump_p
|= purge_all_dead_edges ();
1418 delete_noop_moves ();
1421 obstack_free (&insn_link_obstack
, NULL
);
1422 free (uid_log_links
);
1423 free (uid_insn_cost
);
1424 VEC_free (reg_stat_type
, heap
, reg_stat
);
1427 struct undo
*undo
, *next
;
1428 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1436 total_attempts
+= combine_attempts
;
1437 total_merges
+= combine_merges
;
1438 total_extras
+= combine_extras
;
1439 total_successes
+= combine_successes
;
1441 nonzero_sign_valid
= 0;
1442 rtl_hooks
= general_rtl_hooks
;
1444 /* Make recognizer allow volatile MEMs again. */
1447 return new_direct_jump_p
;
1450 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1453 init_reg_last (void)
1458 FOR_EACH_VEC_ELT (reg_stat_type
, reg_stat
, i
, p
)
1459 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1462 /* Set up any promoted values for incoming argument registers. */
1465 setup_incoming_promotions (rtx first
)
1468 bool strictly_local
= false;
1470 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1471 arg
= DECL_CHAIN (arg
))
1473 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1475 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1477 /* Only continue if the incoming argument is in a register. */
1481 /* Determine, if possible, whether all call sites of the current
1482 function lie within the current compilation unit. (This does
1483 take into account the exporting of a function via taking its
1484 address, and so forth.) */
1485 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1487 /* The mode and signedness of the argument before any promotions happen
1488 (equal to the mode of the pseudo holding it at that stage). */
1489 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1490 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1492 /* The mode and signedness of the argument after any source language and
1493 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1494 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1495 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1497 /* The mode and signedness of the argument as it is actually passed,
1498 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1499 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1500 TREE_TYPE (cfun
->decl
), 0);
1502 /* The mode of the register in which the argument is being passed. */
1503 mode4
= GET_MODE (reg
);
1505 /* Eliminate sign extensions in the callee when:
1506 (a) A mode promotion has occurred; */
1509 /* (b) The mode of the register is the same as the mode of
1510 the argument as it is passed; */
1513 /* (c) There's no language level extension; */
1516 /* (c.1) All callers are from the current compilation unit. If that's
1517 the case we don't have to rely on an ABI, we only have to know
1518 what we're generating right now, and we know that we will do the
1519 mode1 to mode2 promotion with the given sign. */
1520 else if (!strictly_local
)
1522 /* (c.2) The combination of the two promotions is useful. This is
1523 true when the signs match, or if the first promotion is unsigned.
1524 In the later case, (sign_extend (zero_extend x)) is the same as
1525 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1531 /* Record that the value was promoted from mode1 to mode3,
1532 so that any sign extension at the head of the current
1533 function may be eliminated. */
1534 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1535 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1536 record_value_for_reg (reg
, first
, x
);
1540 /* Called via note_stores. If X is a pseudo that is narrower than
1541 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1543 If we are setting only a portion of X and we can't figure out what
1544 portion, assume all bits will be used since we don't know what will
1547 Similarly, set how many bits of X are known to be copies of the sign bit
1548 at all locations in the function. This is the smallest number implied
1552 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1554 rtx insn
= (rtx
) data
;
1558 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1559 /* If this register is undefined at the start of the file, we can't
1560 say what its contents were. */
1561 && ! REGNO_REG_SET_P
1562 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1563 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1565 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1567 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1569 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1570 rsp
->sign_bit_copies
= 1;
1574 /* If this register is being initialized using itself, and the
1575 register is uninitialized in this basic block, and there are
1576 no LOG_LINKS which set the register, then part of the
1577 register is uninitialized. In that case we can't assume
1578 anything about the number of nonzero bits.
1580 ??? We could do better if we checked this in
1581 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1582 could avoid making assumptions about the insn which initially
1583 sets the register, while still using the information in other
1584 insns. We would have to be careful to check every insn
1585 involved in the combination. */
1588 && reg_referenced_p (x
, PATTERN (insn
))
1589 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1592 struct insn_link
*link
;
1594 FOR_EACH_LOG_LINK (link
, insn
)
1595 if (dead_or_set_p (link
->insn
, x
))
1599 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1600 rsp
->sign_bit_copies
= 1;
1605 /* If this is a complex assignment, see if we can convert it into a
1606 simple assignment. */
1607 set
= expand_field_assignment (set
);
1609 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1610 set what we know about X. */
1612 if (SET_DEST (set
) == x
1613 || (paradoxical_subreg_p (SET_DEST (set
))
1614 && SUBREG_REG (SET_DEST (set
)) == x
))
1616 rtx src
= SET_SRC (set
);
1618 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1619 /* If X is narrower than a word and SRC is a non-negative
1620 constant that would appear negative in the mode of X,
1621 sign-extend it for use in reg_stat[].nonzero_bits because some
1622 machines (maybe most) will actually do the sign-extension
1623 and this is the conservative approach.
1625 ??? For 2.5, try to tighten up the MD files in this regard
1626 instead of this kludge. */
1628 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1629 && CONST_INT_P (src
)
1631 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1632 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1635 /* Don't call nonzero_bits if it cannot change anything. */
1636 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1637 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1638 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1639 if (rsp
->sign_bit_copies
== 0
1640 || rsp
->sign_bit_copies
> num
)
1641 rsp
->sign_bit_copies
= num
;
1645 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1646 rsp
->sign_bit_copies
= 1;
1651 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1652 optionally insns that were previously combined into I3 or that will be
1653 combined into the merger of INSN and I3. The order is PRED, PRED2,
1654 INSN, SUCC, SUCC2, I3.
1656 Return 0 if the combination is not allowed for any reason.
1658 If the combination is allowed, *PDEST will be set to the single
1659 destination of INSN and *PSRC to the single source, and this function
1663 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1664 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1665 rtx
*pdest
, rtx
*psrc
)
1674 bool all_adjacent
= true;
1680 if (next_active_insn (succ2
) != i3
)
1681 all_adjacent
= false;
1682 if (next_active_insn (succ
) != succ2
)
1683 all_adjacent
= false;
1685 else if (next_active_insn (succ
) != i3
)
1686 all_adjacent
= false;
1687 if (next_active_insn (insn
) != succ
)
1688 all_adjacent
= false;
1690 else if (next_active_insn (insn
) != i3
)
1691 all_adjacent
= false;
1693 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1694 or a PARALLEL consisting of such a SET and CLOBBERs.
1696 If INSN has CLOBBER parallel parts, ignore them for our processing.
1697 By definition, these happen during the execution of the insn. When it
1698 is merged with another insn, all bets are off. If they are, in fact,
1699 needed and aren't also supplied in I3, they may be added by
1700 recog_for_combine. Otherwise, it won't match.
1702 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1705 Get the source and destination of INSN. If more than one, can't
1708 if (GET_CODE (PATTERN (insn
)) == SET
)
1709 set
= PATTERN (insn
);
1710 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1711 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1713 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1715 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1717 switch (GET_CODE (elt
))
1719 /* This is important to combine floating point insns
1720 for the SH4 port. */
1722 /* Combining an isolated USE doesn't make sense.
1723 We depend here on combinable_i3pat to reject them. */
1724 /* The code below this loop only verifies that the inputs of
1725 the SET in INSN do not change. We call reg_set_between_p
1726 to verify that the REG in the USE does not change between
1728 If the USE in INSN was for a pseudo register, the matching
1729 insn pattern will likely match any register; combining this
1730 with any other USE would only be safe if we knew that the
1731 used registers have identical values, or if there was
1732 something to tell them apart, e.g. different modes. For
1733 now, we forgo such complicated tests and simply disallow
1734 combining of USES of pseudo registers with any other USE. */
1735 if (REG_P (XEXP (elt
, 0))
1736 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1738 rtx i3pat
= PATTERN (i3
);
1739 int i
= XVECLEN (i3pat
, 0) - 1;
1740 unsigned int regno
= REGNO (XEXP (elt
, 0));
1744 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1746 if (GET_CODE (i3elt
) == USE
1747 && REG_P (XEXP (i3elt
, 0))
1748 && (REGNO (XEXP (i3elt
, 0)) == regno
1749 ? reg_set_between_p (XEXP (elt
, 0),
1750 PREV_INSN (insn
), i3
)
1751 : regno
>= FIRST_PSEUDO_REGISTER
))
1758 /* We can ignore CLOBBERs. */
1763 /* Ignore SETs whose result isn't used but not those that
1764 have side-effects. */
1765 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1766 && insn_nothrow_p (insn
)
1767 && !side_effects_p (elt
))
1770 /* If we have already found a SET, this is a second one and
1771 so we cannot combine with this insn. */
1779 /* Anything else means we can't combine. */
1785 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1786 so don't do anything with it. */
1787 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1796 set
= expand_field_assignment (set
);
1797 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1799 /* Don't eliminate a store in the stack pointer. */
1800 if (dest
== stack_pointer_rtx
1801 /* Don't combine with an insn that sets a register to itself if it has
1802 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1803 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1804 /* Can't merge an ASM_OPERANDS. */
1805 || GET_CODE (src
) == ASM_OPERANDS
1806 /* Can't merge a function call. */
1807 || GET_CODE (src
) == CALL
1808 /* Don't eliminate a function call argument. */
1810 && (find_reg_fusage (i3
, USE
, dest
)
1812 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1813 && global_regs
[REGNO (dest
)])))
1814 /* Don't substitute into an incremented register. */
1815 || FIND_REG_INC_NOTE (i3
, dest
)
1816 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1817 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1818 /* Don't substitute into a non-local goto, this confuses CFG. */
1819 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1820 /* Make sure that DEST is not used after SUCC but before I3. */
1823 && (reg_used_between_p (dest
, succ2
, i3
)
1824 || reg_used_between_p (dest
, succ
, succ2
)))
1825 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1826 /* Make sure that the value that is to be substituted for the register
1827 does not use any registers whose values alter in between. However,
1828 If the insns are adjacent, a use can't cross a set even though we
1829 think it might (this can happen for a sequence of insns each setting
1830 the same destination; last_set of that register might point to
1831 a NOTE). If INSN has a REG_EQUIV note, the register is always
1832 equivalent to the memory so the substitution is valid even if there
1833 are intervening stores. Also, don't move a volatile asm or
1834 UNSPEC_VOLATILE across any other insns. */
1837 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1838 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1839 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1840 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1841 /* Don't combine across a CALL_INSN, because that would possibly
1842 change whether the life span of some REGs crosses calls or not,
1843 and it is a pain to update that information.
1844 Exception: if source is a constant, moving it later can't hurt.
1845 Accept that as a special case. */
1846 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1849 /* DEST must either be a REG or CC0. */
1852 /* If register alignment is being enforced for multi-word items in all
1853 cases except for parameters, it is possible to have a register copy
1854 insn referencing a hard register that is not allowed to contain the
1855 mode being copied and which would not be valid as an operand of most
1856 insns. Eliminate this problem by not combining with such an insn.
1858 Also, on some machines we don't want to extend the life of a hard
1862 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1863 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1864 /* Don't extend the life of a hard register unless it is
1865 user variable (if we have few registers) or it can't
1866 fit into the desired register (meaning something special
1868 Also avoid substituting a return register into I3, because
1869 reload can't handle a conflict with constraints of other
1871 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1872 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1875 else if (GET_CODE (dest
) != CC0
)
1879 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1880 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1881 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1883 /* Don't substitute for a register intended as a clobberable
1885 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1886 if (rtx_equal_p (reg
, dest
))
1889 /* If the clobber represents an earlyclobber operand, we must not
1890 substitute an expression containing the clobbered register.
1891 As we do not analyze the constraint strings here, we have to
1892 make the conservative assumption. However, if the register is
1893 a fixed hard reg, the clobber cannot represent any operand;
1894 we leave it up to the machine description to either accept or
1895 reject use-and-clobber patterns. */
1897 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1898 || !fixed_regs
[REGNO (reg
)])
1899 if (reg_overlap_mentioned_p (reg
, src
))
1903 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1904 or not), reject, unless nothing volatile comes between it and I3 */
1906 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1908 /* Make sure neither succ nor succ2 contains a volatile reference. */
1909 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1911 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1913 /* We'll check insns between INSN and I3 below. */
1916 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1917 to be an explicit register variable, and was chosen for a reason. */
1919 if (GET_CODE (src
) == ASM_OPERANDS
1920 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1923 /* If there are any volatile insns between INSN and I3, reject, because
1924 they might affect machine state. */
1926 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1927 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& volatile_insn_p (PATTERN (p
)))
1930 /* If INSN contains an autoincrement or autodecrement, make sure that
1931 register is not used between there and I3, and not already used in
1932 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1933 Also insist that I3 not be a jump; if it were one
1934 and the incremented register were spilled, we would lose. */
1937 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1938 if (REG_NOTE_KIND (link
) == REG_INC
1940 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1941 || (pred
!= NULL_RTX
1942 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1943 || (pred2
!= NULL_RTX
1944 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1945 || (succ
!= NULL_RTX
1946 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1947 || (succ2
!= NULL_RTX
1948 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1949 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1954 /* Don't combine an insn that follows a CC0-setting insn.
1955 An insn that uses CC0 must not be separated from the one that sets it.
1956 We do, however, allow I2 to follow a CC0-setting insn if that insn
1957 is passed as I1; in that case it will be deleted also.
1958 We also allow combining in this case if all the insns are adjacent
1959 because that would leave the two CC0 insns adjacent as well.
1960 It would be more logical to test whether CC0 occurs inside I1 or I2,
1961 but that would be much slower, and this ought to be equivalent. */
1963 p
= prev_nonnote_insn (insn
);
1964 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1969 /* If we get here, we have passed all the tests and the combination is
1978 /* LOC is the location within I3 that contains its pattern or the component
1979 of a PARALLEL of the pattern. We validate that it is valid for combining.
1981 One problem is if I3 modifies its output, as opposed to replacing it
1982 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1983 doing so would produce an insn that is not equivalent to the original insns.
1987 (set (reg:DI 101) (reg:DI 100))
1988 (set (subreg:SI (reg:DI 101) 0) <foo>)
1990 This is NOT equivalent to:
1992 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1993 (set (reg:DI 101) (reg:DI 100))])
1995 Not only does this modify 100 (in which case it might still be valid
1996 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1998 We can also run into a problem if I2 sets a register that I1
1999 uses and I1 gets directly substituted into I3 (not via I2). In that
2000 case, we would be getting the wrong value of I2DEST into I3, so we
2001 must reject the combination. This case occurs when I2 and I1 both
2002 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2003 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2004 of a SET must prevent combination from occurring. The same situation
2005 can occur for I0, in which case I0_NOT_IN_SRC is set.
2007 Before doing the above check, we first try to expand a field assignment
2008 into a set of logical operations.
2010 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2011 we place a register that is both set and used within I3. If more than one
2012 such register is detected, we fail.
2014 Return 1 if the combination is valid, zero otherwise. */
2017 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2018 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2022 if (GET_CODE (x
) == SET
)
2025 rtx dest
= SET_DEST (set
);
2026 rtx src
= SET_SRC (set
);
2027 rtx inner_dest
= dest
;
2030 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2031 || GET_CODE (inner_dest
) == SUBREG
2032 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2033 inner_dest
= XEXP (inner_dest
, 0);
2035 /* Check for the case where I3 modifies its output, as discussed
2036 above. We don't want to prevent pseudos from being combined
2037 into the address of a MEM, so only prevent the combination if
2038 i1 or i2 set the same MEM. */
2039 if ((inner_dest
!= dest
&&
2040 (!MEM_P (inner_dest
)
2041 || rtx_equal_p (i2dest
, inner_dest
)
2042 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2043 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2044 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2045 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2046 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2048 /* This is the same test done in can_combine_p except we can't test
2049 all_adjacent; we don't have to, since this instruction will stay
2050 in place, thus we are not considering increasing the lifetime of
2053 Also, if this insn sets a function argument, combining it with
2054 something that might need a spill could clobber a previous
2055 function argument; the all_adjacent test in can_combine_p also
2056 checks this; here, we do a more specific test for this case. */
2058 || (REG_P (inner_dest
)
2059 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2060 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2061 GET_MODE (inner_dest
))))
2062 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2063 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2066 /* If DEST is used in I3, it is being killed in this insn, so
2067 record that for later. We have to consider paradoxical
2068 subregs here, since they kill the whole register, but we
2069 ignore partial subregs, STRICT_LOW_PART, etc.
2070 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2071 STACK_POINTER_REGNUM, since these are always considered to be
2072 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2074 if (GET_CODE (subdest
) == SUBREG
2075 && (GET_MODE_SIZE (GET_MODE (subdest
))
2076 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2077 subdest
= SUBREG_REG (subdest
);
2080 && reg_referenced_p (subdest
, PATTERN (i3
))
2081 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2082 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2083 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2085 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2086 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2087 || ! fixed_regs
[REGNO (subdest
)])
2089 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2091 if (*pi3dest_killed
)
2094 *pi3dest_killed
= subdest
;
2098 else if (GET_CODE (x
) == PARALLEL
)
2102 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2103 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2104 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2111 /* Return 1 if X is an arithmetic expression that contains a multiplication
2112 and division. We don't count multiplications by powers of two here. */
2115 contains_muldiv (rtx x
)
2117 switch (GET_CODE (x
))
2119 case MOD
: case DIV
: case UMOD
: case UDIV
:
2123 return ! (CONST_INT_P (XEXP (x
, 1))
2124 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2127 return contains_muldiv (XEXP (x
, 0))
2128 || contains_muldiv (XEXP (x
, 1));
2131 return contains_muldiv (XEXP (x
, 0));
2137 /* Determine whether INSN can be used in a combination. Return nonzero if
2138 not. This is used in try_combine to detect early some cases where we
2139 can't perform combinations. */
2142 cant_combine_insn_p (rtx insn
)
2147 /* If this isn't really an insn, we can't do anything.
2148 This can occur when flow deletes an insn that it has merged into an
2149 auto-increment address. */
2150 if (! INSN_P (insn
))
2153 /* Never combine loads and stores involving hard regs that are likely
2154 to be spilled. The register allocator can usually handle such
2155 reg-reg moves by tying. If we allow the combiner to make
2156 substitutions of likely-spilled regs, reload might die.
2157 As an exception, we allow combinations involving fixed regs; these are
2158 not available to the register allocator so there's no risk involved. */
2160 set
= single_set (insn
);
2163 src
= SET_SRC (set
);
2164 dest
= SET_DEST (set
);
2165 if (GET_CODE (src
) == SUBREG
)
2166 src
= SUBREG_REG (src
);
2167 if (GET_CODE (dest
) == SUBREG
)
2168 dest
= SUBREG_REG (dest
);
2169 if (REG_P (src
) && REG_P (dest
)
2170 && ((HARD_REGISTER_P (src
)
2171 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2172 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2173 || (HARD_REGISTER_P (dest
)
2174 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2175 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2181 struct likely_spilled_retval_info
2183 unsigned regno
, nregs
;
2187 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2188 hard registers that are known to be written to / clobbered in full. */
2190 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2192 struct likely_spilled_retval_info
*const info
=
2193 (struct likely_spilled_retval_info
*) data
;
2194 unsigned regno
, nregs
;
2197 if (!REG_P (XEXP (set
, 0)))
2200 if (regno
>= info
->regno
+ info
->nregs
)
2202 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2203 if (regno
+ nregs
<= info
->regno
)
2205 new_mask
= (2U << (nregs
- 1)) - 1;
2206 if (regno
< info
->regno
)
2207 new_mask
>>= info
->regno
- regno
;
2209 new_mask
<<= regno
- info
->regno
;
2210 info
->mask
&= ~new_mask
;
2213 /* Return nonzero iff part of the return value is live during INSN, and
2214 it is likely spilled. This can happen when more than one insn is needed
2215 to copy the return value, e.g. when we consider to combine into the
2216 second copy insn for a complex value. */
2219 likely_spilled_retval_p (rtx insn
)
2221 rtx use
= BB_END (this_basic_block
);
2223 unsigned regno
, nregs
;
2224 /* We assume here that no machine mode needs more than
2225 32 hard registers when the value overlaps with a register
2226 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2228 struct likely_spilled_retval_info info
;
2230 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2232 reg
= XEXP (PATTERN (use
), 0);
2233 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2235 regno
= REGNO (reg
);
2236 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2239 mask
= (2U << (nregs
- 1)) - 1;
2241 /* Disregard parts of the return value that are set later. */
2245 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2247 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2250 /* Check if any of the (probably) live return value registers is
2255 if ((mask
& 1 << nregs
)
2256 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2262 /* Adjust INSN after we made a change to its destination.
2264 Changing the destination can invalidate notes that say something about
2265 the results of the insn and a LOG_LINK pointing to the insn. */
2268 adjust_for_new_dest (rtx insn
)
2270 /* For notes, be conservative and simply remove them. */
2271 remove_reg_equal_equiv_notes (insn
);
2273 /* The new insn will have a destination that was previously the destination
2274 of an insn just above it. Call distribute_links to make a LOG_LINK from
2275 the next use of that destination. */
2276 distribute_links (alloc_insn_link (insn
, NULL
));
2278 df_insn_rescan (insn
);
2281 /* Return TRUE if combine can reuse reg X in mode MODE.
2282 ADDED_SETS is nonzero if the original set is still required. */
2284 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2292 /* Allow hard registers if the new mode is legal, and occupies no more
2293 registers than the old mode. */
2294 if (regno
< FIRST_PSEUDO_REGISTER
)
2295 return (HARD_REGNO_MODE_OK (regno
, mode
)
2296 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2297 >= hard_regno_nregs
[regno
][mode
]));
2299 /* Or a pseudo that is only used once. */
2300 return (REG_N_SETS (regno
) == 1 && !added_sets
2301 && !REG_USERVAR_P (x
));
2305 /* Check whether X, the destination of a set, refers to part of
2306 the register specified by REG. */
2309 reg_subword_p (rtx x
, rtx reg
)
2311 /* Check that reg is an integer mode register. */
2312 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2315 if (GET_CODE (x
) == STRICT_LOW_PART
2316 || GET_CODE (x
) == ZERO_EXTRACT
)
2319 return GET_CODE (x
) == SUBREG
2320 && SUBREG_REG (x
) == reg
2321 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2325 /* Replace auto-increment addressing modes with explicit operations to access
2326 the same addresses without modifying the corresponding registers. */
2329 cleanup_auto_inc_dec (rtx src
, enum machine_mode mem_mode
)
2332 const RTX_CODE code
= GET_CODE (x
);
2348 /* SCRATCH must be shared because they represent distinct values. */
2351 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
2356 if (shared_const_p (x
))
2361 mem_mode
= GET_MODE (x
);
2366 gcc_assert (mem_mode
!= VOIDmode
&& mem_mode
!= BLKmode
);
2367 return gen_rtx_PLUS (GET_MODE (x
),
2368 cleanup_auto_inc_dec (XEXP (x
, 0), mem_mode
),
2369 GEN_INT (code
== PRE_INC
2370 ? GET_MODE_SIZE (mem_mode
)
2371 : -GET_MODE_SIZE (mem_mode
)));
2377 return cleanup_auto_inc_dec (code
== PRE_MODIFY
2378 ? XEXP (x
, 1) : XEXP (x
, 0),
2385 /* Copy the various flags, fields, and other information. We assume
2386 that all fields need copying, and then clear the fields that should
2387 not be copied. That is the sensible default behavior, and forces
2388 us to explicitly document why we are *not* copying a flag. */
2389 x
= shallow_copy_rtx (x
);
2391 /* We do not copy the USED flag, which is used as a mark bit during
2392 walks over the RTL. */
2393 RTX_FLAG (x
, used
) = 0;
2395 /* We do not copy FRAME_RELATED for INSNs. */
2397 RTX_FLAG (x
, frame_related
) = 0;
2399 fmt
= GET_RTX_FORMAT (code
);
2400 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2402 XEXP (x
, i
) = cleanup_auto_inc_dec (XEXP (x
, i
), mem_mode
);
2403 else if (fmt
[i
] == 'E' || fmt
[i
] == 'V')
2406 XVEC (x
, i
) = rtvec_alloc (XVECLEN (x
, i
));
2407 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2409 = cleanup_auto_inc_dec (XVECEXP (src
, i
, j
), mem_mode
);
2416 /* Auxiliary data structure for propagate_for_debug_stmt. */
2418 struct rtx_subst_pair
2424 /* DATA points to an rtx_subst_pair. Return the value that should be
2428 propagate_for_debug_subst (rtx from
, const_rtx old_rtx
, void *data
)
2430 struct rtx_subst_pair
*pair
= (struct rtx_subst_pair
*)data
;
2432 if (!rtx_equal_p (from
, old_rtx
))
2434 if (!pair
->adjusted
)
2436 pair
->adjusted
= true;
2438 pair
->to
= cleanup_auto_inc_dec (pair
->to
, VOIDmode
);
2440 pair
->to
= copy_rtx (pair
->to
);
2442 pair
->to
= make_compound_operation (pair
->to
, SET
);
2445 return copy_rtx (pair
->to
);
2448 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2449 and LAST, not including INSN, but including LAST. Also stop at the end
2450 of THIS_BASIC_BLOCK. */
2453 propagate_for_debug (rtx insn
, rtx last
, rtx dest
, rtx src
)
2455 rtx next
, loc
, end
= NEXT_INSN (BB_END (this_basic_block
));
2457 struct rtx_subst_pair p
;
2461 next
= NEXT_INSN (insn
);
2462 last
= NEXT_INSN (last
);
2463 while (next
!= last
&& next
!= end
)
2466 next
= NEXT_INSN (insn
);
2467 if (DEBUG_INSN_P (insn
))
2469 loc
= simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn
),
2470 dest
, propagate_for_debug_subst
, &p
);
2471 if (loc
== INSN_VAR_LOCATION_LOC (insn
))
2473 INSN_VAR_LOCATION_LOC (insn
) = loc
;
2474 df_insn_rescan (insn
);
2479 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2480 Note that the INSN should be deleted *after* removing dead edges, so
2481 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2482 but not for a (set (pc) (label_ref FOO)). */
2485 update_cfg_for_uncondjump (rtx insn
)
2487 basic_block bb
= BLOCK_FOR_INSN (insn
);
2488 gcc_assert (BB_END (bb
) == insn
);
2490 purge_dead_edges (bb
);
2493 if (EDGE_COUNT (bb
->succs
) == 1)
2497 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2499 /* Remove barriers from the footer if there are any. */
2500 for (insn
= bb
->il
.rtl
->footer
; insn
; insn
= NEXT_INSN (insn
))
2501 if (BARRIER_P (insn
))
2503 if (PREV_INSN (insn
))
2504 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2506 bb
->il
.rtl
->footer
= NEXT_INSN (insn
);
2507 if (NEXT_INSN (insn
))
2508 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2510 else if (LABEL_P (insn
))
2515 /* Try to combine the insns I0, I1 and I2 into I3.
2516 Here I0, I1 and I2 appear earlier than I3.
2517 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2520 If we are combining more than two insns and the resulting insn is not
2521 recognized, try splitting it into two insns. If that happens, I2 and I3
2522 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2523 Otherwise, I0, I1 and I2 are pseudo-deleted.
2525 Return 0 if the combination does not work. Then nothing is changed.
2526 If we did the combination, return the insn at which combine should
2529 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2530 new direct jump instruction.
2532 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2533 been I3 passed to an earlier try_combine within the same basic
2537 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
,
2538 rtx last_combined_insn
)
2540 /* New patterns for I3 and I2, respectively. */
2541 rtx newpat
, newi2pat
= 0;
2542 rtvec newpat_vec_with_clobbers
= 0;
2543 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2544 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2546 int added_sets_0
, added_sets_1
, added_sets_2
;
2547 /* Total number of SETs to put into I3. */
2549 /* Nonzero if I2's or I1's body now appears in I3. */
2550 int i2_is_used
= 0, i1_is_used
= 0;
2551 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2552 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2553 /* Contains I3 if the destination of I3 is used in its source, which means
2554 that the old life of I3 is being killed. If that usage is placed into
2555 I2 and not in I3, a REG_DEAD note must be made. */
2556 rtx i3dest_killed
= 0;
2557 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2558 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2559 /* Copy of SET_SRC of I1, if needed. */
2561 /* Set if I2DEST was reused as a scratch register. */
2562 bool i2scratch
= false;
2563 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2564 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2565 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2566 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2567 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2568 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2569 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2570 /* Notes that must be added to REG_NOTES in I3 and I2. */
2571 rtx new_i3_notes
, new_i2_notes
;
2572 /* Notes that we substituted I3 into I2 instead of the normal case. */
2573 int i3_subst_into_i2
= 0;
2574 /* Notes that I1, I2 or I3 is a MULT operation. */
2577 int changed_i3_dest
= 0;
2581 struct insn_link
*link
;
2583 rtx new_other_notes
;
2586 /* Only try four-insn combinations when there's high likelihood of
2587 success. Look for simple insns, such as loads of constants or
2588 binary operations involving a constant. */
2595 if (!flag_expensive_optimizations
)
2598 for (i
= 0; i
< 4; i
++)
2600 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2601 rtx set
= single_set (insn
);
2605 src
= SET_SRC (set
);
2606 if (CONSTANT_P (src
))
2611 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2613 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2614 || GET_CODE (src
) == LSHIFTRT
)
2617 if (ngood
< 2 && nshift
< 2)
2621 /* Exit early if one of the insns involved can't be used for
2623 if (cant_combine_insn_p (i3
)
2624 || cant_combine_insn_p (i2
)
2625 || (i1
&& cant_combine_insn_p (i1
))
2626 || (i0
&& cant_combine_insn_p (i0
))
2627 || likely_spilled_retval_p (i3
))
2631 undobuf
.other_insn
= 0;
2633 /* Reset the hard register usage information. */
2634 CLEAR_HARD_REG_SET (newpat_used_regs
);
2636 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2639 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2640 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2642 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2643 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2645 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2646 INSN_UID (i2
), INSN_UID (i3
));
2649 /* If multiple insns feed into one of I2 or I3, they can be in any
2650 order. To simplify the code below, reorder them in sequence. */
2651 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2652 temp
= i2
, i2
= i0
, i0
= temp
;
2653 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2654 temp
= i1
, i1
= i0
, i0
= temp
;
2655 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2656 temp
= i1
, i1
= i2
, i2
= temp
;
2658 added_links_insn
= 0;
2660 /* First check for one important special case that the code below will
2661 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2662 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2663 we may be able to replace that destination with the destination of I3.
2664 This occurs in the common code where we compute both a quotient and
2665 remainder into a structure, in which case we want to do the computation
2666 directly into the structure to avoid register-register copies.
2668 Note that this case handles both multiple sets in I2 and also cases
2669 where I2 has a number of CLOBBERs inside the PARALLEL.
2671 We make very conservative checks below and only try to handle the
2672 most common cases of this. For example, we only handle the case
2673 where I2 and I3 are adjacent to avoid making difficult register
2676 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2677 && REG_P (SET_SRC (PATTERN (i3
)))
2678 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2679 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2680 && GET_CODE (PATTERN (i2
)) == PARALLEL
2681 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2682 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2683 below would need to check what is inside (and reg_overlap_mentioned_p
2684 doesn't support those codes anyway). Don't allow those destinations;
2685 the resulting insn isn't likely to be recognized anyway. */
2686 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2687 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2688 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2689 SET_DEST (PATTERN (i3
)))
2690 && next_active_insn (i2
) == i3
)
2692 rtx p2
= PATTERN (i2
);
2694 /* Make sure that the destination of I3,
2695 which we are going to substitute into one output of I2,
2696 is not used within another output of I2. We must avoid making this:
2697 (parallel [(set (mem (reg 69)) ...)
2698 (set (reg 69) ...)])
2699 which is not well-defined as to order of actions.
2700 (Besides, reload can't handle output reloads for this.)
2702 The problem can also happen if the dest of I3 is a memory ref,
2703 if another dest in I2 is an indirect memory ref. */
2704 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2705 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2706 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2707 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2708 SET_DEST (XVECEXP (p2
, 0, i
))))
2711 if (i
== XVECLEN (p2
, 0))
2712 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2713 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2714 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2719 subst_low_luid
= DF_INSN_LUID (i2
);
2721 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2722 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2723 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2724 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2726 /* Replace the dest in I2 with our dest and make the resulting
2727 insn the new pattern for I3. Then skip to where we validate
2728 the pattern. Everything was set up above. */
2729 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2731 i3_subst_into_i2
= 1;
2732 goto validate_replacement
;
2736 /* If I2 is setting a pseudo to a constant and I3 is setting some
2737 sub-part of it to another constant, merge them by making a new
2740 && (temp
= single_set (i2
)) != 0
2741 && (CONST_INT_P (SET_SRC (temp
))
2742 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2743 && GET_CODE (PATTERN (i3
)) == SET
2744 && (CONST_INT_P (SET_SRC (PATTERN (i3
)))
2745 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2746 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2748 rtx dest
= SET_DEST (PATTERN (i3
));
2752 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2754 if (CONST_INT_P (XEXP (dest
, 1))
2755 && CONST_INT_P (XEXP (dest
, 2)))
2757 width
= INTVAL (XEXP (dest
, 1));
2758 offset
= INTVAL (XEXP (dest
, 2));
2759 dest
= XEXP (dest
, 0);
2760 if (BITS_BIG_ENDIAN
)
2761 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2766 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2767 dest
= XEXP (dest
, 0);
2768 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2774 /* If this is the low part, we're done. */
2775 if (subreg_lowpart_p (dest
))
2777 /* Handle the case where inner is twice the size of outer. */
2778 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2779 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2780 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2781 /* Otherwise give up for now. */
2787 && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2788 <= HOST_BITS_PER_DOUBLE_INT
))
2791 rtx inner
= SET_SRC (PATTERN (i3
));
2792 rtx outer
= SET_SRC (temp
);
2794 o
= rtx_to_double_int (outer
);
2795 i
= rtx_to_double_int (inner
);
2797 m
= double_int_mask (width
);
2798 i
= double_int_and (i
, m
);
2799 m
= double_int_lshift (m
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2800 i
= double_int_lshift (i
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2801 o
= double_int_ior (double_int_and_not (o
, m
), i
);
2805 subst_low_luid
= DF_INSN_LUID (i2
);
2806 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2807 i2dest
= SET_DEST (temp
);
2808 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2810 /* Replace the source in I2 with the new constant and make the
2811 resulting insn the new pattern for I3. Then skip to where we
2812 validate the pattern. Everything was set up above. */
2813 SUBST (SET_SRC (temp
),
2814 immed_double_int_const (o
, GET_MODE (SET_DEST (temp
))));
2816 newpat
= PATTERN (i2
);
2818 /* The dest of I3 has been replaced with the dest of I2. */
2819 changed_i3_dest
= 1;
2820 goto validate_replacement
;
2825 /* If we have no I1 and I2 looks like:
2826 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2828 make up a dummy I1 that is
2831 (set (reg:CC X) (compare:CC Y (const_int 0)))
2833 (We can ignore any trailing CLOBBERs.)
2835 This undoes a previous combination and allows us to match a branch-and-
2838 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2839 && XVECLEN (PATTERN (i2
), 0) >= 2
2840 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2841 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2843 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2844 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2845 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2846 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2847 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2848 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2850 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2851 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2856 /* We make I1 with the same INSN_UID as I2. This gives it
2857 the same DF_INSN_LUID for value tracking. Our fake I1 will
2858 never appear in the insn stream so giving it the same INSN_UID
2859 as I2 will not cause a problem. */
2861 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2862 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2863 INSN_LOCATOR (i2
), -1, NULL_RTX
);
2865 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2866 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2867 SET_DEST (PATTERN (i1
)));
2872 /* Verify that I2 and I1 are valid for combining. */
2873 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2874 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2876 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2883 /* Record whether I2DEST is used in I2SRC and similarly for the other
2884 cases. Knowing this will help in register status updating below. */
2885 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2886 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2887 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2888 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2889 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2890 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2891 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2892 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2893 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2895 /* For the earlier insns, determine which of the subsequent ones they
2897 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2898 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2899 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2900 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2901 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2903 /* Ensure that I3's pattern can be the destination of combines. */
2904 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2905 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2906 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2907 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2914 /* See if any of the insns is a MULT operation. Unless one is, we will
2915 reject a combination that is, since it must be slower. Be conservative
2917 if (GET_CODE (i2src
) == MULT
2918 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2919 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2920 || (GET_CODE (PATTERN (i3
)) == SET
2921 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2924 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2925 We used to do this EXCEPT in one case: I3 has a post-inc in an
2926 output operand. However, that exception can give rise to insns like
2928 which is a famous insn on the PDP-11 where the value of r3 used as the
2929 source was model-dependent. Avoid this sort of thing. */
2932 if (!(GET_CODE (PATTERN (i3
)) == SET
2933 && REG_P (SET_SRC (PATTERN (i3
)))
2934 && MEM_P (SET_DEST (PATTERN (i3
)))
2935 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2936 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2937 /* It's not the exception. */
2942 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2943 if (REG_NOTE_KIND (link
) == REG_INC
2944 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2946 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2954 /* See if the SETs in I1 or I2 need to be kept around in the merged
2955 instruction: whenever the value set there is still needed past I3.
2956 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2958 For the SET in I1, we have two cases: If I1 and I2 independently
2959 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2960 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2961 in I1 needs to be kept around unless I1DEST dies or is set in either
2962 I2 or I3. The same consideration applies to I0. */
2964 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2967 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2968 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2973 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2974 || (i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
2975 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)));
2979 /* We are about to copy insns for the case where they need to be kept
2980 around. Check that they can be copied in the merged instruction. */
2982 if (targetm
.cannot_copy_insn_p
2983 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2984 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2985 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2991 /* If the set in I2 needs to be kept around, we must make a copy of
2992 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2993 PATTERN (I2), we are only substituting for the original I1DEST, not into
2994 an already-substituted copy. This also prevents making self-referential
2995 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3000 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3001 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
3003 i2pat
= copy_rtx (PATTERN (i2
));
3008 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3009 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
3011 i1pat
= copy_rtx (PATTERN (i1
));
3016 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3017 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
3019 i0pat
= copy_rtx (PATTERN (i0
));
3024 /* Substitute in the latest insn for the regs set by the earlier ones. */
3026 maxreg
= max_reg_num ();
3031 /* Many machines that don't use CC0 have insns that can both perform an
3032 arithmetic operation and set the condition code. These operations will
3033 be represented as a PARALLEL with the first element of the vector
3034 being a COMPARE of an arithmetic operation with the constant zero.
3035 The second element of the vector will set some pseudo to the result
3036 of the same arithmetic operation. If we simplify the COMPARE, we won't
3037 match such a pattern and so will generate an extra insn. Here we test
3038 for this case, where both the comparison and the operation result are
3039 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3040 I2SRC. Later we will make the PARALLEL that contains I2. */
3042 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3043 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3044 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3045 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3048 rtx
*cc_use_loc
= NULL
, cc_use_insn
= NULL_RTX
;
3049 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3050 enum machine_mode compare_mode
, orig_compare_mode
;
3051 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3053 newpat
= PATTERN (i3
);
3054 newpat_dest
= SET_DEST (newpat
);
3055 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3057 if (undobuf
.other_insn
== 0
3058 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3061 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3062 compare_code
= simplify_compare_const (compare_code
,
3064 #ifdef CANONICALIZE_COMPARISON
3065 CANONICALIZE_COMPARISON (compare_code
, op0
, op1
);
3069 /* Do the rest only if op1 is const0_rtx, which may be the
3070 result of simplification. */
3071 if (op1
== const0_rtx
)
3073 /* If a single use of the CC is found, prepare to modify it
3074 when SELECT_CC_MODE returns a new CC-class mode, or when
3075 the above simplify_compare_const() returned a new comparison
3076 operator. undobuf.other_insn is assigned the CC use insn
3077 when modifying it. */
3080 #ifdef SELECT_CC_MODE
3081 enum machine_mode new_mode
3082 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3083 if (new_mode
!= orig_compare_mode
3084 && can_change_dest_mode (SET_DEST (newpat
),
3085 added_sets_2
, new_mode
))
3087 unsigned int regno
= REGNO (newpat_dest
);
3088 compare_mode
= new_mode
;
3089 if (regno
< FIRST_PSEUDO_REGISTER
)
3090 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3093 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3094 newpat_dest
= regno_reg_rtx
[regno
];
3098 /* Cases for modifying the CC-using comparison. */
3099 if (compare_code
!= orig_compare_code
3100 /* ??? Do we need to verify the zero rtx? */
3101 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3103 /* Replace cc_use_loc with entire new RTX. */
3105 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3106 newpat_dest
, const0_rtx
));
3107 undobuf
.other_insn
= cc_use_insn
;
3109 else if (compare_mode
!= orig_compare_mode
)
3111 /* Just replace the CC reg with a new mode. */
3112 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3113 undobuf
.other_insn
= cc_use_insn
;
3117 /* Now we modify the current newpat:
3118 First, SET_DEST(newpat) is updated if the CC mode has been
3119 altered. For targets without SELECT_CC_MODE, this should be
3121 if (compare_mode
!= orig_compare_mode
)
3122 SUBST (SET_DEST (newpat
), newpat_dest
);
3123 /* This is always done to propagate i2src into newpat. */
3124 SUBST (SET_SRC (newpat
),
3125 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3126 /* Create new version of i2pat if needed; the below PARALLEL
3127 creation needs this to work correctly. */
3128 if (! rtx_equal_p (i2src
, op0
))
3129 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3135 if (i2_is_used
== 0)
3137 /* It is possible that the source of I2 or I1 may be performing
3138 an unneeded operation, such as a ZERO_EXTEND of something
3139 that is known to have the high part zero. Handle that case
3140 by letting subst look at the inner insns.
3142 Another way to do this would be to have a function that tries
3143 to simplify a single insn instead of merging two or more
3144 insns. We don't do this because of the potential of infinite
3145 loops and because of the potential extra memory required.
3146 However, doing it the way we are is a bit of a kludge and
3147 doesn't catch all cases.
3149 But only do this if -fexpensive-optimizations since it slows
3150 things down and doesn't usually win.
3152 This is not done in the COMPARE case above because the
3153 unmodified I2PAT is used in the PARALLEL and so a pattern
3154 with a modified I2SRC would not match. */
3156 if (flag_expensive_optimizations
)
3158 /* Pass pc_rtx so no substitutions are done, just
3162 subst_low_luid
= DF_INSN_LUID (i1
);
3163 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3166 subst_low_luid
= DF_INSN_LUID (i2
);
3167 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3170 n_occurrences
= 0; /* `subst' counts here */
3171 subst_low_luid
= DF_INSN_LUID (i2
);
3173 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3174 copy of I2SRC each time we substitute it, in order to avoid creating
3175 self-referential RTL when we will be substituting I1SRC for I1DEST
3176 later. Likewise if I0 feeds into I2, either directly or indirectly
3177 through I1, and I0DEST is in I0SRC. */
3178 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3179 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3180 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3181 && i0dest_in_i0src
));
3184 /* Record whether I2's body now appears within I3's body. */
3185 i2_is_used
= n_occurrences
;
3188 /* If we already got a failure, don't try to do more. Otherwise, try to
3189 substitute I1 if we have it. */
3191 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3193 /* Check that an autoincrement side-effect on I1 has not been lost.
3194 This happens if I1DEST is mentioned in I2 and dies there, and
3195 has disappeared from the new pattern. */
3196 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3198 && dead_or_set_p (i2
, i1dest
)
3199 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3200 /* Before we can do this substitution, we must redo the test done
3201 above (see detailed comments there) that ensures I1DEST isn't
3202 mentioned in any SETs in NEWPAT that are field assignments. */
3203 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3211 subst_low_luid
= DF_INSN_LUID (i1
);
3213 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3214 copy of I1SRC each time we substitute it, in order to avoid creating
3215 self-referential RTL when we will be substituting I0SRC for I0DEST
3217 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3218 i0_feeds_i1_n
&& i0dest_in_i0src
);
3221 /* Record whether I1's body now appears within I3's body. */
3222 i1_is_used
= n_occurrences
;
3225 /* Likewise for I0 if we have it. */
3227 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3229 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3230 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3231 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3232 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3233 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3240 /* If the following substitution will modify I1SRC, make a copy of it
3241 for the case where it is substituted for I1DEST in I2PAT later. */
3242 if (i0_feeds_i1_n
&& added_sets_2
&& i1_feeds_i2_n
)
3243 i1src_copy
= copy_rtx (i1src
);
3246 subst_low_luid
= DF_INSN_LUID (i0
);
3247 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3251 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3252 to count all the ways that I2SRC and I1SRC can be used. */
3253 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3254 && i2_is_used
+ added_sets_2
> 1)
3255 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3256 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3258 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3259 && (n_occurrences
+ added_sets_0
3260 + (added_sets_1
&& i0_feeds_i1_n
)
3261 + (added_sets_2
&& i0_feeds_i2_n
)
3263 /* Fail if we tried to make a new register. */
3264 || max_reg_num () != maxreg
3265 /* Fail if we couldn't do something and have a CLOBBER. */
3266 || GET_CODE (newpat
) == CLOBBER
3267 /* Fail if this new pattern is a MULT and we didn't have one before
3268 at the outer level. */
3269 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3276 /* If the actions of the earlier insns must be kept
3277 in addition to substituting them into the latest one,
3278 we must make a new PARALLEL for the latest insn
3279 to hold additional the SETs. */
3281 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3283 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3286 if (GET_CODE (newpat
) == PARALLEL
)
3288 rtvec old
= XVEC (newpat
, 0);
3289 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3290 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3291 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3292 sizeof (old
->elem
[0]) * old
->num_elem
);
3297 total_sets
= 1 + extra_sets
;
3298 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3299 XVECEXP (newpat
, 0, 0) = old
;
3303 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3309 t
= subst (t
, i0dest
, i0src
, 0, 0, 0);
3311 XVECEXP (newpat
, 0, --total_sets
) = t
;
3317 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3318 i0_feeds_i1_n
&& i0dest_in_i0src
);
3319 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3320 t
= subst (t
, i0dest
, i0src
, 0, 0, 0);
3322 XVECEXP (newpat
, 0, --total_sets
) = t
;
3326 validate_replacement
:
3328 /* Note which hard regs this insn has as inputs. */
3329 mark_used_regs_combine (newpat
);
3331 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3332 consider splitting this pattern, we might need these clobbers. */
3333 if (i1
&& GET_CODE (newpat
) == PARALLEL
3334 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3336 int len
= XVECLEN (newpat
, 0);
3338 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3339 for (i
= 0; i
< len
; i
++)
3340 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3343 /* Is the result of combination a valid instruction? */
3344 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3346 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3347 the second SET's destination is a register that is unused and isn't
3348 marked as an instruction that might trap in an EH region. In that case,
3349 we just need the first SET. This can occur when simplifying a divmod
3350 insn. We *must* test for this case here because the code below that
3351 splits two independent SETs doesn't handle this case correctly when it
3352 updates the register status.
3354 It's pointless doing this if we originally had two sets, one from
3355 i3, and one from i2. Combining then splitting the parallel results
3356 in the original i2 again plus an invalid insn (which we delete).
3357 The net effect is only to move instructions around, which makes
3358 debug info less accurate.
3360 Also check the case where the first SET's destination is unused.
3361 That would not cause incorrect code, but does cause an unneeded
3364 if (insn_code_number
< 0
3365 && !(added_sets_2
&& i1
== 0)
3366 && GET_CODE (newpat
) == PARALLEL
3367 && XVECLEN (newpat
, 0) == 2
3368 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3369 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3370 && asm_noperands (newpat
) < 0)
3372 rtx set0
= XVECEXP (newpat
, 0, 0);
3373 rtx set1
= XVECEXP (newpat
, 0, 1);
3375 if (((REG_P (SET_DEST (set1
))
3376 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3377 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3378 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3379 && insn_nothrow_p (i3
)
3380 && !side_effects_p (SET_SRC (set1
)))
3383 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3386 else if (((REG_P (SET_DEST (set0
))
3387 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3388 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3389 && find_reg_note (i3
, REG_UNUSED
,
3390 SUBREG_REG (SET_DEST (set0
)))))
3391 && insn_nothrow_p (i3
)
3392 && !side_effects_p (SET_SRC (set0
)))
3395 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3397 if (insn_code_number
>= 0)
3398 changed_i3_dest
= 1;
3402 /* If we were combining three insns and the result is a simple SET
3403 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3404 insns. There are two ways to do this. It can be split using a
3405 machine-specific method (like when you have an addition of a large
3406 constant) or by combine in the function find_split_point. */
3408 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3409 && asm_noperands (newpat
) < 0)
3411 rtx parallel
, m_split
, *split
;
3413 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3414 use I2DEST as a scratch register will help. In the latter case,
3415 convert I2DEST to the mode of the source of NEWPAT if we can. */
3417 m_split
= combine_split_insns (newpat
, i3
);
3419 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3420 inputs of NEWPAT. */
3422 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3423 possible to try that as a scratch reg. This would require adding
3424 more code to make it work though. */
3426 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3428 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3430 /* First try to split using the original register as a
3431 scratch register. */
3432 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3433 gen_rtvec (2, newpat
,
3434 gen_rtx_CLOBBER (VOIDmode
,
3436 m_split
= combine_split_insns (parallel
, i3
);
3438 /* If that didn't work, try changing the mode of I2DEST if
3441 && new_mode
!= GET_MODE (i2dest
)
3442 && new_mode
!= VOIDmode
3443 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3445 enum machine_mode old_mode
= GET_MODE (i2dest
);
3448 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3449 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3452 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3453 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3456 parallel
= (gen_rtx_PARALLEL
3458 gen_rtvec (2, newpat
,
3459 gen_rtx_CLOBBER (VOIDmode
,
3461 m_split
= combine_split_insns (parallel
, i3
);
3464 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3468 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3469 buf
= undobuf
.undos
;
3470 undobuf
.undos
= buf
->next
;
3471 buf
->next
= undobuf
.frees
;
3472 undobuf
.frees
= buf
;
3476 i2scratch
= m_split
!= 0;
3479 /* If recog_for_combine has discarded clobbers, try to use them
3480 again for the split. */
3481 if (m_split
== 0 && newpat_vec_with_clobbers
)
3483 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3484 m_split
= combine_split_insns (parallel
, i3
);
3487 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3489 m_split
= PATTERN (m_split
);
3490 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3491 if (insn_code_number
>= 0)
3494 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3495 && (next_nonnote_nondebug_insn (i2
) == i3
3496 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3499 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3500 newi2pat
= PATTERN (m_split
);
3502 i3set
= single_set (NEXT_INSN (m_split
));
3503 i2set
= single_set (m_split
);
3505 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3507 /* If I2 or I3 has multiple SETs, we won't know how to track
3508 register status, so don't use these insns. If I2's destination
3509 is used between I2 and I3, we also can't use these insns. */
3511 if (i2_code_number
>= 0 && i2set
&& i3set
3512 && (next_nonnote_nondebug_insn (i2
) == i3
3513 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3514 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3516 if (insn_code_number
>= 0)
3519 /* It is possible that both insns now set the destination of I3.
3520 If so, we must show an extra use of it. */
3522 if (insn_code_number
>= 0)
3524 rtx new_i3_dest
= SET_DEST (i3set
);
3525 rtx new_i2_dest
= SET_DEST (i2set
);
3527 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3528 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3529 || GET_CODE (new_i3_dest
) == SUBREG
)
3530 new_i3_dest
= XEXP (new_i3_dest
, 0);
3532 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3533 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3534 || GET_CODE (new_i2_dest
) == SUBREG
)
3535 new_i2_dest
= XEXP (new_i2_dest
, 0);
3537 if (REG_P (new_i3_dest
)
3538 && REG_P (new_i2_dest
)
3539 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3540 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3544 /* If we can split it and use I2DEST, go ahead and see if that
3545 helps things be recognized. Verify that none of the registers
3546 are set between I2 and I3. */
3547 if (insn_code_number
< 0
3548 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3552 /* We need I2DEST in the proper mode. If it is a hard register
3553 or the only use of a pseudo, we can change its mode.
3554 Make sure we don't change a hard register to have a mode that
3555 isn't valid for it, or change the number of registers. */
3556 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3557 || GET_MODE (*split
) == VOIDmode
3558 || can_change_dest_mode (i2dest
, added_sets_2
,
3560 && (next_nonnote_nondebug_insn (i2
) == i3
3561 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3562 /* We can't overwrite I2DEST if its value is still used by
3564 && ! reg_referenced_p (i2dest
, newpat
))
3566 rtx newdest
= i2dest
;
3567 enum rtx_code split_code
= GET_CODE (*split
);
3568 enum machine_mode split_mode
= GET_MODE (*split
);
3569 bool subst_done
= false;
3570 newi2pat
= NULL_RTX
;
3574 /* *SPLIT may be part of I2SRC, so make sure we have the
3575 original expression around for later debug processing.
3576 We should not need I2SRC any more in other cases. */
3577 if (MAY_HAVE_DEBUG_INSNS
)
3578 i2src
= copy_rtx (i2src
);
3582 /* Get NEWDEST as a register in the proper mode. We have already
3583 validated that we can do this. */
3584 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3586 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3587 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3590 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3591 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3595 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3596 an ASHIFT. This can occur if it was inside a PLUS and hence
3597 appeared to be a memory address. This is a kludge. */
3598 if (split_code
== MULT
3599 && CONST_INT_P (XEXP (*split
, 1))
3600 && INTVAL (XEXP (*split
, 1)) > 0
3601 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3603 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3604 XEXP (*split
, 0), GEN_INT (i
)));
3605 /* Update split_code because we may not have a multiply
3607 split_code
= GET_CODE (*split
);
3610 #ifdef INSN_SCHEDULING
3611 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3612 be written as a ZERO_EXTEND. */
3613 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3615 #ifdef LOAD_EXTEND_OP
3616 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3617 what it really is. */
3618 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3620 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3621 SUBREG_REG (*split
)));
3624 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3625 SUBREG_REG (*split
)));
3629 /* Attempt to split binary operators using arithmetic identities. */
3630 if (BINARY_P (SET_SRC (newpat
))
3631 && split_mode
== GET_MODE (SET_SRC (newpat
))
3632 && ! side_effects_p (SET_SRC (newpat
)))
3634 rtx setsrc
= SET_SRC (newpat
);
3635 enum machine_mode mode
= GET_MODE (setsrc
);
3636 enum rtx_code code
= GET_CODE (setsrc
);
3637 rtx src_op0
= XEXP (setsrc
, 0);
3638 rtx src_op1
= XEXP (setsrc
, 1);
3640 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3641 if (rtx_equal_p (src_op0
, src_op1
))
3643 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3644 SUBST (XEXP (setsrc
, 0), newdest
);
3645 SUBST (XEXP (setsrc
, 1), newdest
);
3648 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3649 else if ((code
== PLUS
|| code
== MULT
)
3650 && GET_CODE (src_op0
) == code
3651 && GET_CODE (XEXP (src_op0
, 0)) == code
3652 && (INTEGRAL_MODE_P (mode
)
3653 || (FLOAT_MODE_P (mode
)
3654 && flag_unsafe_math_optimizations
)))
3656 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3657 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3658 rtx r
= XEXP (src_op0
, 1);
3661 /* Split both "((X op Y) op X) op Y" and
3662 "((X op Y) op Y) op X" as "T op T" where T is
3664 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3665 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3667 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3669 SUBST (XEXP (setsrc
, 0), newdest
);
3670 SUBST (XEXP (setsrc
, 1), newdest
);
3673 /* Split "((X op X) op Y) op Y)" as "T op T" where
3675 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3677 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3678 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3679 SUBST (XEXP (setsrc
, 0), newdest
);
3680 SUBST (XEXP (setsrc
, 1), newdest
);
3688 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3689 SUBST (*split
, newdest
);
3692 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3694 /* recog_for_combine might have added CLOBBERs to newi2pat.
3695 Make sure NEWPAT does not depend on the clobbered regs. */
3696 if (GET_CODE (newi2pat
) == PARALLEL
)
3697 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3698 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3700 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3701 if (reg_overlap_mentioned_p (reg
, newpat
))
3708 /* If the split point was a MULT and we didn't have one before,
3709 don't use one now. */
3710 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3711 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3715 /* Check for a case where we loaded from memory in a narrow mode and
3716 then sign extended it, but we need both registers. In that case,
3717 we have a PARALLEL with both loads from the same memory location.
3718 We can split this into a load from memory followed by a register-register
3719 copy. This saves at least one insn, more if register allocation can
3722 We cannot do this if the destination of the first assignment is a
3723 condition code register or cc0. We eliminate this case by making sure
3724 the SET_DEST and SET_SRC have the same mode.
3726 We cannot do this if the destination of the second assignment is
3727 a register that we have already assumed is zero-extended. Similarly
3728 for a SUBREG of such a register. */
3730 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3731 && GET_CODE (newpat
) == PARALLEL
3732 && XVECLEN (newpat
, 0) == 2
3733 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3734 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3735 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3736 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3737 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3738 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3739 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3740 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3742 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3743 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3744 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3746 && VEC_index (reg_stat_type
, reg_stat
,
3747 REGNO (temp
))->nonzero_bits
!= 0
3748 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3749 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3750 && (VEC_index (reg_stat_type
, reg_stat
,
3751 REGNO (temp
))->nonzero_bits
3752 != GET_MODE_MASK (word_mode
))))
3753 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3754 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3756 && VEC_index (reg_stat_type
, reg_stat
,
3757 REGNO (temp
))->nonzero_bits
!= 0
3758 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3759 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3760 && (VEC_index (reg_stat_type
, reg_stat
,
3761 REGNO (temp
))->nonzero_bits
3762 != GET_MODE_MASK (word_mode
)))))
3763 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3764 SET_SRC (XVECEXP (newpat
, 0, 1)))
3765 && ! find_reg_note (i3
, REG_UNUSED
,
3766 SET_DEST (XVECEXP (newpat
, 0, 0))))
3770 newi2pat
= XVECEXP (newpat
, 0, 0);
3771 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3772 newpat
= XVECEXP (newpat
, 0, 1);
3773 SUBST (SET_SRC (newpat
),
3774 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3775 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3777 if (i2_code_number
>= 0)
3778 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3780 if (insn_code_number
>= 0)
3784 /* Similarly, check for a case where we have a PARALLEL of two independent
3785 SETs but we started with three insns. In this case, we can do the sets
3786 as two separate insns. This case occurs when some SET allows two
3787 other insns to combine, but the destination of that SET is still live. */
3789 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3790 && GET_CODE (newpat
) == PARALLEL
3791 && XVECLEN (newpat
, 0) == 2
3792 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3793 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3794 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3795 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3796 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3797 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3798 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3799 XVECEXP (newpat
, 0, 0))
3800 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3801 XVECEXP (newpat
, 0, 1))
3802 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3803 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3805 /* Normally, it doesn't matter which of the two is done first,
3806 but the one that references cc0 can't be the second, and
3807 one which uses any regs/memory set in between i2 and i3 can't
3809 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3812 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3816 newi2pat
= XVECEXP (newpat
, 0, 1);
3817 newpat
= XVECEXP (newpat
, 0, 0);
3819 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 0)),
3822 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1))
3826 newi2pat
= XVECEXP (newpat
, 0, 0);
3827 newpat
= XVECEXP (newpat
, 0, 1);
3835 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3837 if (i2_code_number
>= 0)
3839 /* recog_for_combine might have added CLOBBERs to newi2pat.
3840 Make sure NEWPAT does not depend on the clobbered regs. */
3841 if (GET_CODE (newi2pat
) == PARALLEL
)
3843 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3844 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3846 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3847 if (reg_overlap_mentioned_p (reg
, newpat
))
3855 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3859 /* If it still isn't recognized, fail and change things back the way they
3861 if ((insn_code_number
< 0
3862 /* Is the result a reasonable ASM_OPERANDS? */
3863 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3869 /* If we had to change another insn, make sure it is valid also. */
3870 if (undobuf
.other_insn
)
3872 CLEAR_HARD_REG_SET (newpat_used_regs
);
3874 other_pat
= PATTERN (undobuf
.other_insn
);
3875 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3878 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3886 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3887 they are adjacent to each other or not. */
3889 rtx p
= prev_nonnote_insn (i3
);
3890 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3891 && sets_cc0_p (newi2pat
))
3899 /* Only allow this combination if insn_rtx_costs reports that the
3900 replacement instructions are cheaper than the originals. */
3901 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3907 if (MAY_HAVE_DEBUG_INSNS
)
3911 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3912 if (undo
->kind
== UNDO_MODE
)
3914 rtx reg
= *undo
->where
.r
;
3915 enum machine_mode new_mode
= GET_MODE (reg
);
3916 enum machine_mode old_mode
= undo
->old_contents
.m
;
3918 /* Temporarily revert mode back. */
3919 adjust_reg_mode (reg
, old_mode
);
3921 if (reg
== i2dest
&& i2scratch
)
3923 /* If we used i2dest as a scratch register with a
3924 different mode, substitute it for the original
3925 i2src while its original mode is temporarily
3926 restored, and then clear i2scratch so that we don't
3927 do it again later. */
3928 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
);
3930 /* Put back the new mode. */
3931 adjust_reg_mode (reg
, new_mode
);
3935 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3941 last
= last_combined_insn
;
3946 last
= undobuf
.other_insn
;
3948 if (DF_INSN_LUID (last
)
3949 < DF_INSN_LUID (last_combined_insn
))
3950 last
= last_combined_insn
;
3953 /* We're dealing with a reg that changed mode but not
3954 meaning, so we want to turn it into a subreg for
3955 the new mode. However, because of REG sharing and
3956 because its mode had already changed, we have to do
3957 it in two steps. First, replace any debug uses of
3958 reg, with its original mode temporarily restored,
3959 with this copy we have created; then, replace the
3960 copy with the SUBREG of the original shared reg,
3961 once again changed to the new mode. */
3962 propagate_for_debug (first
, last
, reg
, tempreg
);
3963 adjust_reg_mode (reg
, new_mode
);
3964 propagate_for_debug (first
, last
, tempreg
,
3965 lowpart_subreg (old_mode
, reg
, new_mode
));
3970 /* If we will be able to accept this, we have made a
3971 change to the destination of I3. This requires us to
3972 do a few adjustments. */
3974 if (changed_i3_dest
)
3976 PATTERN (i3
) = newpat
;
3977 adjust_for_new_dest (i3
);
3980 /* We now know that we can do this combination. Merge the insns and
3981 update the status of registers and LOG_LINKS. */
3983 if (undobuf
.other_insn
)
3987 PATTERN (undobuf
.other_insn
) = other_pat
;
3989 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3990 are still valid. Then add any non-duplicate notes added by
3991 recog_for_combine. */
3992 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3994 next
= XEXP (note
, 1);
3996 if (REG_NOTE_KIND (note
) == REG_UNUSED
3997 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3998 remove_note (undobuf
.other_insn
, note
);
4001 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4002 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4009 struct insn_link
*link
;
4012 /* I3 now uses what used to be its destination and which is now
4013 I2's destination. This requires us to do a few adjustments. */
4014 PATTERN (i3
) = newpat
;
4015 adjust_for_new_dest (i3
);
4017 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4020 However, some later insn might be using I2's dest and have
4021 a LOG_LINK pointing at I3. We must remove this link.
4022 The simplest way to remove the link is to point it at I1,
4023 which we know will be a NOTE. */
4025 /* newi2pat is usually a SET here; however, recog_for_combine might
4026 have added some clobbers. */
4027 if (GET_CODE (newi2pat
) == PARALLEL
)
4028 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4030 ni2dest
= SET_DEST (newi2pat
);
4032 for (insn
= NEXT_INSN (i3
);
4033 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4034 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4035 insn
= NEXT_INSN (insn
))
4037 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4039 FOR_EACH_LOG_LINK (link
, insn
)
4040 if (link
->insn
== i3
)
4049 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4050 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4053 /* Compute which registers we expect to eliminate. newi2pat may be setting
4054 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4055 same as i3dest, in which case newi2pat may be setting i1dest. */
4056 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4057 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4060 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4061 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4064 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
4065 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4069 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4071 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4072 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4074 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4076 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4078 /* Ensure that we do not have something that should not be shared but
4079 occurs multiple times in the new insns. Check this by first
4080 resetting all the `used' flags and then copying anything is shared. */
4082 reset_used_flags (i3notes
);
4083 reset_used_flags (i2notes
);
4084 reset_used_flags (i1notes
);
4085 reset_used_flags (i0notes
);
4086 reset_used_flags (newpat
);
4087 reset_used_flags (newi2pat
);
4088 if (undobuf
.other_insn
)
4089 reset_used_flags (PATTERN (undobuf
.other_insn
));
4091 i3notes
= copy_rtx_if_shared (i3notes
);
4092 i2notes
= copy_rtx_if_shared (i2notes
);
4093 i1notes
= copy_rtx_if_shared (i1notes
);
4094 i0notes
= copy_rtx_if_shared (i0notes
);
4095 newpat
= copy_rtx_if_shared (newpat
);
4096 newi2pat
= copy_rtx_if_shared (newi2pat
);
4097 if (undobuf
.other_insn
)
4098 reset_used_flags (PATTERN (undobuf
.other_insn
));
4100 INSN_CODE (i3
) = insn_code_number
;
4101 PATTERN (i3
) = newpat
;
4103 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4105 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4107 reset_used_flags (call_usage
);
4108 call_usage
= copy_rtx (call_usage
);
4112 /* I2SRC must still be meaningful at this point. Some splitting
4113 operations can invalidate I2SRC, but those operations do not
4116 replace_rtx (call_usage
, i2dest
, i2src
);
4120 replace_rtx (call_usage
, i1dest
, i1src
);
4122 replace_rtx (call_usage
, i0dest
, i0src
);
4124 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4127 if (undobuf
.other_insn
)
4128 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4130 /* We had one special case above where I2 had more than one set and
4131 we replaced a destination of one of those sets with the destination
4132 of I3. In that case, we have to update LOG_LINKS of insns later
4133 in this basic block. Note that this (expensive) case is rare.
4135 Also, in this case, we must pretend that all REG_NOTEs for I2
4136 actually came from I3, so that REG_UNUSED notes from I2 will be
4137 properly handled. */
4139 if (i3_subst_into_i2
)
4141 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4142 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4143 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4144 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4145 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4146 && ! find_reg_note (i2
, REG_UNUSED
,
4147 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4148 for (temp
= NEXT_INSN (i2
);
4149 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4150 || BB_HEAD (this_basic_block
) != temp
);
4151 temp
= NEXT_INSN (temp
))
4152 if (temp
!= i3
&& INSN_P (temp
))
4153 FOR_EACH_LOG_LINK (link
, temp
)
4154 if (link
->insn
== i2
)
4160 while (XEXP (link
, 1))
4161 link
= XEXP (link
, 1);
4162 XEXP (link
, 1) = i2notes
;
4169 LOG_LINKS (i3
) = NULL
;
4171 LOG_LINKS (i2
) = NULL
;
4176 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4177 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
);
4178 INSN_CODE (i2
) = i2_code_number
;
4179 PATTERN (i2
) = newi2pat
;
4183 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4184 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
);
4185 SET_INSN_DELETED (i2
);
4190 LOG_LINKS (i1
) = NULL
;
4192 if (MAY_HAVE_DEBUG_INSNS
)
4193 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
);
4194 SET_INSN_DELETED (i1
);
4199 LOG_LINKS (i0
) = NULL
;
4201 if (MAY_HAVE_DEBUG_INSNS
)
4202 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
);
4203 SET_INSN_DELETED (i0
);
4206 /* Get death notes for everything that is now used in either I3 or
4207 I2 and used to die in a previous insn. If we built two new
4208 patterns, move from I1 to I2 then I2 to I3 so that we get the
4209 proper movement on registers that I2 modifies. */
4212 from_luid
= DF_INSN_LUID (i0
);
4214 from_luid
= DF_INSN_LUID (i1
);
4216 from_luid
= DF_INSN_LUID (i2
);
4218 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4219 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4221 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4223 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4224 elim_i2
, elim_i1
, elim_i0
);
4226 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4227 elim_i2
, elim_i1
, elim_i0
);
4229 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4230 elim_i2
, elim_i1
, elim_i0
);
4232 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4233 elim_i2
, elim_i1
, elim_i0
);
4235 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4236 elim_i2
, elim_i1
, elim_i0
);
4238 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4239 know these are REG_UNUSED and want them to go to the desired insn,
4240 so we always pass it as i3. */
4242 if (newi2pat
&& new_i2_notes
)
4243 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4247 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4250 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4251 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4252 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4253 in that case, it might delete I2. Similarly for I2 and I1.
4254 Show an additional death due to the REG_DEAD note we make here. If
4255 we discard it in distribute_notes, we will decrement it again. */
4259 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4260 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4262 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
, elim_i0
);
4264 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4266 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4267 elim_i2
, elim_i1
, elim_i0
);
4270 if (i2dest_in_i2src
)
4272 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4273 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4274 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4275 NULL_RTX
, NULL_RTX
);
4277 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4278 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4281 if (i1dest_in_i1src
)
4283 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4284 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4285 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4286 NULL_RTX
, NULL_RTX
);
4288 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4289 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4292 if (i0dest_in_i0src
)
4294 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4295 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4296 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4297 NULL_RTX
, NULL_RTX
);
4299 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4300 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4303 distribute_links (i3links
);
4304 distribute_links (i2links
);
4305 distribute_links (i1links
);
4306 distribute_links (i0links
);
4310 struct insn_link
*link
;
4311 rtx i2_insn
= 0, i2_val
= 0, set
;
4313 /* The insn that used to set this register doesn't exist, and
4314 this life of the register may not exist either. See if one of
4315 I3's links points to an insn that sets I2DEST. If it does,
4316 that is now the last known value for I2DEST. If we don't update
4317 this and I2 set the register to a value that depended on its old
4318 contents, we will get confused. If this insn is used, thing
4319 will be set correctly in combine_instructions. */
4320 FOR_EACH_LOG_LINK (link
, i3
)
4321 if ((set
= single_set (link
->insn
)) != 0
4322 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4323 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4325 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4327 /* If the reg formerly set in I2 died only once and that was in I3,
4328 zero its use count so it won't make `reload' do any work. */
4330 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4331 && ! i2dest_in_i2src
)
4332 INC_REG_N_SETS (REGNO (i2dest
), -1);
4335 if (i1
&& REG_P (i1dest
))
4337 struct insn_link
*link
;
4338 rtx i1_insn
= 0, i1_val
= 0, set
;
4340 FOR_EACH_LOG_LINK (link
, i3
)
4341 if ((set
= single_set (link
->insn
)) != 0
4342 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4343 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4345 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4347 if (! added_sets_1
&& ! i1dest_in_i1src
)
4348 INC_REG_N_SETS (REGNO (i1dest
), -1);
4351 if (i0
&& REG_P (i0dest
))
4353 struct insn_link
*link
;
4354 rtx i0_insn
= 0, i0_val
= 0, set
;
4356 FOR_EACH_LOG_LINK (link
, i3
)
4357 if ((set
= single_set (link
->insn
)) != 0
4358 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4359 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4361 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4363 if (! added_sets_0
&& ! i0dest_in_i0src
)
4364 INC_REG_N_SETS (REGNO (i0dest
), -1);
4367 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4368 been made to this insn. The order of
4369 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4370 can affect nonzero_bits of newpat */
4372 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4373 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4376 if (undobuf
.other_insn
!= NULL_RTX
)
4380 fprintf (dump_file
, "modifying other_insn ");
4381 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4383 df_insn_rescan (undobuf
.other_insn
);
4386 if (i0
&& !(NOTE_P(i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4390 fprintf (dump_file
, "modifying insn i1 ");
4391 dump_insn_slim (dump_file
, i0
);
4393 df_insn_rescan (i0
);
4396 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4400 fprintf (dump_file
, "modifying insn i1 ");
4401 dump_insn_slim (dump_file
, i1
);
4403 df_insn_rescan (i1
);
4406 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4410 fprintf (dump_file
, "modifying insn i2 ");
4411 dump_insn_slim (dump_file
, i2
);
4413 df_insn_rescan (i2
);
4416 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4420 fprintf (dump_file
, "modifying insn i3 ");
4421 dump_insn_slim (dump_file
, i3
);
4423 df_insn_rescan (i3
);
4426 /* Set new_direct_jump_p if a new return or simple jump instruction
4427 has been created. Adjust the CFG accordingly. */
4429 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4431 *new_direct_jump_p
= 1;
4432 mark_jump_label (PATTERN (i3
), i3
, 0);
4433 update_cfg_for_uncondjump (i3
);
4436 if (undobuf
.other_insn
!= NULL_RTX
4437 && (returnjump_p (undobuf
.other_insn
)
4438 || any_uncondjump_p (undobuf
.other_insn
)))
4440 *new_direct_jump_p
= 1;
4441 update_cfg_for_uncondjump (undobuf
.other_insn
);
4444 /* A noop might also need cleaning up of CFG, if it comes from the
4445 simplification of a jump. */
4447 && GET_CODE (newpat
) == SET
4448 && SET_SRC (newpat
) == pc_rtx
4449 && SET_DEST (newpat
) == pc_rtx
)
4451 *new_direct_jump_p
= 1;
4452 update_cfg_for_uncondjump (i3
);
4455 if (undobuf
.other_insn
!= NULL_RTX
4456 && JUMP_P (undobuf
.other_insn
)
4457 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4458 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4459 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4461 *new_direct_jump_p
= 1;
4462 update_cfg_for_uncondjump (undobuf
.other_insn
);
4465 combine_successes
++;
4468 if (added_links_insn
4469 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4470 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4471 return added_links_insn
;
4473 return newi2pat
? i2
: i3
;
4476 /* Undo all the modifications recorded in undobuf. */
4481 struct undo
*undo
, *next
;
4483 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4489 *undo
->where
.r
= undo
->old_contents
.r
;
4492 *undo
->where
.i
= undo
->old_contents
.i
;
4495 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4501 undo
->next
= undobuf
.frees
;
4502 undobuf
.frees
= undo
;
4508 /* We've committed to accepting the changes we made. Move all
4509 of the undos to the free list. */
4514 struct undo
*undo
, *next
;
4516 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4519 undo
->next
= undobuf
.frees
;
4520 undobuf
.frees
= undo
;
4525 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4526 where we have an arithmetic expression and return that point. LOC will
4529 try_combine will call this function to see if an insn can be split into
4533 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4536 enum rtx_code code
= GET_CODE (x
);
4538 unsigned HOST_WIDE_INT len
= 0;
4539 HOST_WIDE_INT pos
= 0;
4541 rtx inner
= NULL_RTX
;
4543 /* First special-case some codes. */
4547 #ifdef INSN_SCHEDULING
4548 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4550 if (MEM_P (SUBREG_REG (x
)))
4553 return find_split_point (&SUBREG_REG (x
), insn
, false);
4557 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4558 using LO_SUM and HIGH. */
4559 if (GET_CODE (XEXP (x
, 0)) == CONST
4560 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4562 enum machine_mode address_mode
4563 = targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (x
));
4566 gen_rtx_LO_SUM (address_mode
,
4567 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4569 return &XEXP (XEXP (x
, 0), 0);
4573 /* If we have a PLUS whose second operand is a constant and the
4574 address is not valid, perhaps will can split it up using
4575 the machine-specific way to split large constants. We use
4576 the first pseudo-reg (one of the virtual regs) as a placeholder;
4577 it will not remain in the result. */
4578 if (GET_CODE (XEXP (x
, 0)) == PLUS
4579 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4580 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4581 MEM_ADDR_SPACE (x
)))
4583 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4584 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4588 /* This should have produced two insns, each of which sets our
4589 placeholder. If the source of the second is a valid address,
4590 we can make put both sources together and make a split point
4594 && NEXT_INSN (seq
) != NULL_RTX
4595 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4596 && NONJUMP_INSN_P (seq
)
4597 && GET_CODE (PATTERN (seq
)) == SET
4598 && SET_DEST (PATTERN (seq
)) == reg
4599 && ! reg_mentioned_p (reg
,
4600 SET_SRC (PATTERN (seq
)))
4601 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4602 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4603 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4604 && memory_address_addr_space_p
4605 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4606 MEM_ADDR_SPACE (x
)))
4608 rtx src1
= SET_SRC (PATTERN (seq
));
4609 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4611 /* Replace the placeholder in SRC2 with SRC1. If we can
4612 find where in SRC2 it was placed, that can become our
4613 split point and we can replace this address with SRC2.
4614 Just try two obvious places. */
4616 src2
= replace_rtx (src2
, reg
, src1
);
4618 if (XEXP (src2
, 0) == src1
)
4619 split
= &XEXP (src2
, 0);
4620 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4621 && XEXP (XEXP (src2
, 0), 0) == src1
)
4622 split
= &XEXP (XEXP (src2
, 0), 0);
4626 SUBST (XEXP (x
, 0), src2
);
4631 /* If that didn't work, perhaps the first operand is complex and
4632 needs to be computed separately, so make a split point there.
4633 This will occur on machines that just support REG + CONST
4634 and have a constant moved through some previous computation. */
4636 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4637 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4638 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4639 return &XEXP (XEXP (x
, 0), 0);
4642 /* If we have a PLUS whose first operand is complex, try computing it
4643 separately by making a split there. */
4644 if (GET_CODE (XEXP (x
, 0)) == PLUS
4645 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4647 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4648 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4649 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4650 return &XEXP (XEXP (x
, 0), 0);
4655 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4656 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4657 we need to put the operand into a register. So split at that
4660 if (SET_DEST (x
) == cc0_rtx
4661 && GET_CODE (SET_SRC (x
)) != COMPARE
4662 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4663 && !OBJECT_P (SET_SRC (x
))
4664 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4665 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4666 return &SET_SRC (x
);
4669 /* See if we can split SET_SRC as it stands. */
4670 split
= find_split_point (&SET_SRC (x
), insn
, true);
4671 if (split
&& split
!= &SET_SRC (x
))
4674 /* See if we can split SET_DEST as it stands. */
4675 split
= find_split_point (&SET_DEST (x
), insn
, false);
4676 if (split
&& split
!= &SET_DEST (x
))
4679 /* See if this is a bitfield assignment with everything constant. If
4680 so, this is an IOR of an AND, so split it into that. */
4681 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4682 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4683 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4684 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4685 && CONST_INT_P (SET_SRC (x
))
4686 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4687 + INTVAL (XEXP (SET_DEST (x
), 2)))
4688 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4689 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4691 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4692 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4693 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4694 rtx dest
= XEXP (SET_DEST (x
), 0);
4695 enum machine_mode mode
= GET_MODE (dest
);
4696 unsigned HOST_WIDE_INT mask
4697 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4700 if (BITS_BIG_ENDIAN
)
4701 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4703 or_mask
= gen_int_mode (src
<< pos
, mode
);
4706 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4709 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4711 simplify_gen_binary (IOR
, mode
,
4712 simplify_gen_binary (AND
, mode
,
4717 SUBST (SET_DEST (x
), dest
);
4719 split
= find_split_point (&SET_SRC (x
), insn
, true);
4720 if (split
&& split
!= &SET_SRC (x
))
4724 /* Otherwise, see if this is an operation that we can split into two.
4725 If so, try to split that. */
4726 code
= GET_CODE (SET_SRC (x
));
4731 /* If we are AND'ing with a large constant that is only a single
4732 bit and the result is only being used in a context where we
4733 need to know if it is zero or nonzero, replace it with a bit
4734 extraction. This will avoid the large constant, which might
4735 have taken more than one insn to make. If the constant were
4736 not a valid argument to the AND but took only one insn to make,
4737 this is no worse, but if it took more than one insn, it will
4740 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4741 && REG_P (XEXP (SET_SRC (x
), 0))
4742 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4743 && REG_P (SET_DEST (x
))
4744 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4745 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4746 && XEXP (*split
, 0) == SET_DEST (x
)
4747 && XEXP (*split
, 1) == const0_rtx
)
4749 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4750 XEXP (SET_SRC (x
), 0),
4751 pos
, NULL_RTX
, 1, 1, 0, 0);
4752 if (extraction
!= 0)
4754 SUBST (SET_SRC (x
), extraction
);
4755 return find_split_point (loc
, insn
, false);
4761 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4762 is known to be on, this can be converted into a NEG of a shift. */
4763 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4764 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4765 && 1 <= (pos
= exact_log2
4766 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4767 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4769 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4773 gen_rtx_LSHIFTRT (mode
,
4774 XEXP (SET_SRC (x
), 0),
4777 split
= find_split_point (&SET_SRC (x
), insn
, true);
4778 if (split
&& split
!= &SET_SRC (x
))
4784 inner
= XEXP (SET_SRC (x
), 0);
4786 /* We can't optimize if either mode is a partial integer
4787 mode as we don't know how many bits are significant
4789 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4790 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4794 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4800 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4801 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4803 inner
= XEXP (SET_SRC (x
), 0);
4804 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4805 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4807 if (BITS_BIG_ENDIAN
)
4808 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4809 unsignedp
= (code
== ZERO_EXTRACT
);
4818 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4820 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4822 /* For unsigned, we have a choice of a shift followed by an
4823 AND or two shifts. Use two shifts for field sizes where the
4824 constant might be too large. We assume here that we can
4825 always at least get 8-bit constants in an AND insn, which is
4826 true for every current RISC. */
4828 if (unsignedp
&& len
<= 8)
4833 (mode
, gen_lowpart (mode
, inner
),
4835 GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
)
4838 split
= find_split_point (&SET_SRC (x
), insn
, true);
4839 if (split
&& split
!= &SET_SRC (x
))
4846 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4847 gen_rtx_ASHIFT (mode
,
4848 gen_lowpart (mode
, inner
),
4849 GEN_INT (GET_MODE_PRECISION (mode
)
4851 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4853 split
= find_split_point (&SET_SRC (x
), insn
, true);
4854 if (split
&& split
!= &SET_SRC (x
))
4859 /* See if this is a simple operation with a constant as the second
4860 operand. It might be that this constant is out of range and hence
4861 could be used as a split point. */
4862 if (BINARY_P (SET_SRC (x
))
4863 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4864 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4865 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4866 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4867 return &XEXP (SET_SRC (x
), 1);
4869 /* Finally, see if this is a simple operation with its first operand
4870 not in a register. The operation might require this operand in a
4871 register, so return it as a split point. We can always do this
4872 because if the first operand were another operation, we would have
4873 already found it as a split point. */
4874 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4875 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4876 return &XEXP (SET_SRC (x
), 0);
4882 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4883 it is better to write this as (not (ior A B)) so we can split it.
4884 Similarly for IOR. */
4885 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4888 gen_rtx_NOT (GET_MODE (x
),
4889 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4891 XEXP (XEXP (x
, 0), 0),
4892 XEXP (XEXP (x
, 1), 0))));
4893 return find_split_point (loc
, insn
, set_src
);
4896 /* Many RISC machines have a large set of logical insns. If the
4897 second operand is a NOT, put it first so we will try to split the
4898 other operand first. */
4899 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4901 rtx tem
= XEXP (x
, 0);
4902 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4903 SUBST (XEXP (x
, 1), tem
);
4909 /* Canonicalization can produce (minus A (mult B C)), where C is a
4910 constant. It may be better to try splitting (plus (mult B -C) A)
4911 instead if this isn't a multiply by a power of two. */
4912 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4913 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4914 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4916 enum machine_mode mode
= GET_MODE (x
);
4917 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4918 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4919 SUBST (*loc
, gen_rtx_PLUS (mode
, gen_rtx_MULT (mode
,
4920 XEXP (XEXP (x
, 1), 0),
4921 GEN_INT (other_int
)),
4923 return find_split_point (loc
, insn
, set_src
);
4926 /* Split at a multiply-accumulate instruction. However if this is
4927 the SET_SRC, we likely do not have such an instruction and it's
4928 worthless to try this split. */
4929 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4936 /* Otherwise, select our actions depending on our rtx class. */
4937 switch (GET_RTX_CLASS (code
))
4939 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4941 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4944 /* ... fall through ... */
4946 case RTX_COMM_ARITH
:
4948 case RTX_COMM_COMPARE
:
4949 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4952 /* ... fall through ... */
4954 /* Some machines have (and (shift ...) ...) insns. If X is not
4955 an AND, but XEXP (X, 0) is, use it as our split point. */
4956 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4957 return &XEXP (x
, 0);
4959 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4965 /* Otherwise, we don't have a split point. */
4970 /* Throughout X, replace FROM with TO, and return the result.
4971 The result is TO if X is FROM;
4972 otherwise the result is X, but its contents may have been modified.
4973 If they were modified, a record was made in undobuf so that
4974 undo_all will (among other things) return X to its original state.
4976 If the number of changes necessary is too much to record to undo,
4977 the excess changes are not made, so the result is invalid.
4978 The changes already made can still be undone.
4979 undobuf.num_undo is incremented for such changes, so by testing that
4980 the caller can tell whether the result is valid.
4982 `n_occurrences' is incremented each time FROM is replaced.
4984 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4986 IN_COND is nonzero if we are at the top level of a condition.
4988 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4989 by copying if `n_occurrences' is nonzero. */
4992 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
4994 enum rtx_code code
= GET_CODE (x
);
4995 enum machine_mode op0_mode
= VOIDmode
;
5000 /* Two expressions are equal if they are identical copies of a shared
5001 RTX or if they are both registers with the same register number
5004 #define COMBINE_RTX_EQUAL_P(X,Y) \
5006 || (REG_P (X) && REG_P (Y) \
5007 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5009 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5012 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5015 /* If X and FROM are the same register but different modes, they
5016 will not have been seen as equal above. However, the log links code
5017 will make a LOG_LINKS entry for that case. If we do nothing, we
5018 will try to rerecognize our original insn and, when it succeeds,
5019 we will delete the feeding insn, which is incorrect.
5021 So force this insn not to match in this (rare) case. */
5022 if (! in_dest
&& code
== REG
&& REG_P (from
)
5023 && reg_overlap_mentioned_p (x
, from
))
5024 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5026 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5027 of which may contain things that can be combined. */
5028 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5031 /* It is possible to have a subexpression appear twice in the insn.
5032 Suppose that FROM is a register that appears within TO.
5033 Then, after that subexpression has been scanned once by `subst',
5034 the second time it is scanned, TO may be found. If we were
5035 to scan TO here, we would find FROM within it and create a
5036 self-referent rtl structure which is completely wrong. */
5037 if (COMBINE_RTX_EQUAL_P (x
, to
))
5040 /* Parallel asm_operands need special attention because all of the
5041 inputs are shared across the arms. Furthermore, unsharing the
5042 rtl results in recognition failures. Failure to handle this case
5043 specially can result in circular rtl.
5045 Solve this by doing a normal pass across the first entry of the
5046 parallel, and only processing the SET_DESTs of the subsequent
5049 if (code
== PARALLEL
5050 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5051 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5053 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5055 /* If this substitution failed, this whole thing fails. */
5056 if (GET_CODE (new_rtx
) == CLOBBER
5057 && XEXP (new_rtx
, 0) == const0_rtx
)
5060 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5062 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5064 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5067 && GET_CODE (dest
) != CC0
5068 && GET_CODE (dest
) != PC
)
5070 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5072 /* If this substitution failed, this whole thing fails. */
5073 if (GET_CODE (new_rtx
) == CLOBBER
5074 && XEXP (new_rtx
, 0) == const0_rtx
)
5077 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5083 len
= GET_RTX_LENGTH (code
);
5084 fmt
= GET_RTX_FORMAT (code
);
5086 /* We don't need to process a SET_DEST that is a register, CC0,
5087 or PC, so set up to skip this common case. All other cases
5088 where we want to suppress replacing something inside a
5089 SET_SRC are handled via the IN_DEST operand. */
5091 && (REG_P (SET_DEST (x
))
5092 || GET_CODE (SET_DEST (x
)) == CC0
5093 || GET_CODE (SET_DEST (x
)) == PC
))
5096 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5099 op0_mode
= GET_MODE (XEXP (x
, 0));
5101 for (i
= 0; i
< len
; i
++)
5106 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5108 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5110 new_rtx
= (unique_copy
&& n_occurrences
5111 ? copy_rtx (to
) : to
);
5116 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5119 /* If this substitution failed, this whole thing
5121 if (GET_CODE (new_rtx
) == CLOBBER
5122 && XEXP (new_rtx
, 0) == const0_rtx
)
5126 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5129 else if (fmt
[i
] == 'e')
5131 /* If this is a register being set, ignore it. */
5132 new_rtx
= XEXP (x
, i
);
5135 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5137 || code
== STRICT_LOW_PART
))
5140 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5142 /* In general, don't install a subreg involving two
5143 modes not tieable. It can worsen register
5144 allocation, and can even make invalid reload
5145 insns, since the reg inside may need to be copied
5146 from in the outside mode, and that may be invalid
5147 if it is an fp reg copied in integer mode.
5149 We allow two exceptions to this: It is valid if
5150 it is inside another SUBREG and the mode of that
5151 SUBREG and the mode of the inside of TO is
5152 tieable and it is valid if X is a SET that copies
5155 if (GET_CODE (to
) == SUBREG
5156 && ! MODES_TIEABLE_P (GET_MODE (to
),
5157 GET_MODE (SUBREG_REG (to
)))
5158 && ! (code
== SUBREG
5159 && MODES_TIEABLE_P (GET_MODE (x
),
5160 GET_MODE (SUBREG_REG (to
))))
5162 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5165 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5167 #ifdef CANNOT_CHANGE_MODE_CLASS
5170 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5171 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5174 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5177 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5181 /* If we are in a SET_DEST, suppress most cases unless we
5182 have gone inside a MEM, in which case we want to
5183 simplify the address. We assume here that things that
5184 are actually part of the destination have their inner
5185 parts in the first expression. This is true for SUBREG,
5186 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5187 things aside from REG and MEM that should appear in a
5189 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5191 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5192 || code
== ZERO_EXTRACT
))
5195 code
== IF_THEN_ELSE
&& i
== 0,
5198 /* If we found that we will have to reject this combination,
5199 indicate that by returning the CLOBBER ourselves, rather than
5200 an expression containing it. This will speed things up as
5201 well as prevent accidents where two CLOBBERs are considered
5202 to be equal, thus producing an incorrect simplification. */
5204 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5207 if (GET_CODE (x
) == SUBREG
5208 && (CONST_INT_P (new_rtx
)
5209 || GET_CODE (new_rtx
) == CONST_DOUBLE
))
5211 enum machine_mode mode
= GET_MODE (x
);
5213 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5214 GET_MODE (SUBREG_REG (x
)),
5217 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5219 else if (CONST_INT_P (new_rtx
)
5220 && GET_CODE (x
) == ZERO_EXTEND
)
5222 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5223 new_rtx
, GET_MODE (XEXP (x
, 0)));
5227 SUBST (XEXP (x
, i
), new_rtx
);
5232 /* Check if we are loading something from the constant pool via float
5233 extension; in this case we would undo compress_float_constant
5234 optimization and degenerate constant load to an immediate value. */
5235 if (GET_CODE (x
) == FLOAT_EXTEND
5236 && MEM_P (XEXP (x
, 0))
5237 && MEM_READONLY_P (XEXP (x
, 0)))
5239 rtx tmp
= avoid_constant_pool_reference (x
);
5244 /* Try to simplify X. If the simplification changed the code, it is likely
5245 that further simplification will help, so loop, but limit the number
5246 of repetitions that will be performed. */
5248 for (i
= 0; i
< 4; i
++)
5250 /* If X is sufficiently simple, don't bother trying to do anything
5252 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5253 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5255 if (GET_CODE (x
) == code
)
5258 code
= GET_CODE (x
);
5260 /* We no longer know the original mode of operand 0 since we
5261 have changed the form of X) */
5262 op0_mode
= VOIDmode
;
5268 /* Simplify X, a piece of RTL. We just operate on the expression at the
5269 outer level; call `subst' to simplify recursively. Return the new
5272 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5273 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5277 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
,
5280 enum rtx_code code
= GET_CODE (x
);
5281 enum machine_mode mode
= GET_MODE (x
);
5285 /* If this is a commutative operation, put a constant last and a complex
5286 expression first. We don't need to do this for comparisons here. */
5287 if (COMMUTATIVE_ARITH_P (x
)
5288 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5291 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5292 SUBST (XEXP (x
, 1), temp
);
5295 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5296 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5297 things. Check for cases where both arms are testing the same
5300 Don't do anything if all operands are very simple. */
5303 && ((!OBJECT_P (XEXP (x
, 0))
5304 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5305 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5306 || (!OBJECT_P (XEXP (x
, 1))
5307 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5308 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5310 && (!OBJECT_P (XEXP (x
, 0))
5311 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5312 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5314 rtx cond
, true_rtx
, false_rtx
;
5316 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5318 /* If everything is a comparison, what we have is highly unlikely
5319 to be simpler, so don't use it. */
5320 && ! (COMPARISON_P (x
)
5321 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5323 rtx cop1
= const0_rtx
;
5324 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5326 if (cond_code
== NE
&& COMPARISON_P (cond
))
5329 /* Simplify the alternative arms; this may collapse the true and
5330 false arms to store-flag values. Be careful to use copy_rtx
5331 here since true_rtx or false_rtx might share RTL with x as a
5332 result of the if_then_else_cond call above. */
5333 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5334 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5336 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5337 is unlikely to be simpler. */
5338 if (general_operand (true_rtx
, VOIDmode
)
5339 && general_operand (false_rtx
, VOIDmode
))
5341 enum rtx_code reversed
;
5343 /* Restarting if we generate a store-flag expression will cause
5344 us to loop. Just drop through in this case. */
5346 /* If the result values are STORE_FLAG_VALUE and zero, we can
5347 just make the comparison operation. */
5348 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5349 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5351 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5352 && ((reversed
= reversed_comparison_code_parts
5353 (cond_code
, cond
, cop1
, NULL
))
5355 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5358 /* Likewise, we can make the negate of a comparison operation
5359 if the result values are - STORE_FLAG_VALUE and zero. */
5360 else if (CONST_INT_P (true_rtx
)
5361 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5362 && false_rtx
== const0_rtx
)
5363 x
= simplify_gen_unary (NEG
, mode
,
5364 simplify_gen_relational (cond_code
,
5368 else if (CONST_INT_P (false_rtx
)
5369 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5370 && true_rtx
== const0_rtx
5371 && ((reversed
= reversed_comparison_code_parts
5372 (cond_code
, cond
, cop1
, NULL
))
5374 x
= simplify_gen_unary (NEG
, mode
,
5375 simplify_gen_relational (reversed
,
5380 return gen_rtx_IF_THEN_ELSE (mode
,
5381 simplify_gen_relational (cond_code
,
5386 true_rtx
, false_rtx
);
5388 code
= GET_CODE (x
);
5389 op0_mode
= VOIDmode
;
5394 /* Try to fold this expression in case we have constants that weren't
5397 switch (GET_RTX_CLASS (code
))
5400 if (op0_mode
== VOIDmode
)
5401 op0_mode
= GET_MODE (XEXP (x
, 0));
5402 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5405 case RTX_COMM_COMPARE
:
5407 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5408 if (cmp_mode
== VOIDmode
)
5410 cmp_mode
= GET_MODE (XEXP (x
, 1));
5411 if (cmp_mode
== VOIDmode
)
5412 cmp_mode
= op0_mode
;
5414 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5415 XEXP (x
, 0), XEXP (x
, 1));
5418 case RTX_COMM_ARITH
:
5420 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5422 case RTX_BITFIELD_OPS
:
5424 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5425 XEXP (x
, 1), XEXP (x
, 2));
5434 code
= GET_CODE (temp
);
5435 op0_mode
= VOIDmode
;
5436 mode
= GET_MODE (temp
);
5439 /* First see if we can apply the inverse distributive law. */
5440 if (code
== PLUS
|| code
== MINUS
5441 || code
== AND
|| code
== IOR
|| code
== XOR
)
5443 x
= apply_distributive_law (x
);
5444 code
= GET_CODE (x
);
5445 op0_mode
= VOIDmode
;
5448 /* If CODE is an associative operation not otherwise handled, see if we
5449 can associate some operands. This can win if they are constants or
5450 if they are logically related (i.e. (a & b) & a). */
5451 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5452 || code
== AND
|| code
== IOR
|| code
== XOR
5453 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5454 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5455 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5457 if (GET_CODE (XEXP (x
, 0)) == code
)
5459 rtx other
= XEXP (XEXP (x
, 0), 0);
5460 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5461 rtx inner_op1
= XEXP (x
, 1);
5464 /* Make sure we pass the constant operand if any as the second
5465 one if this is a commutative operation. */
5466 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5468 rtx tem
= inner_op0
;
5469 inner_op0
= inner_op1
;
5472 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5473 : code
== DIV
? MULT
5475 mode
, inner_op0
, inner_op1
);
5477 /* For commutative operations, try the other pair if that one
5479 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5481 other
= XEXP (XEXP (x
, 0), 1);
5482 inner
= simplify_binary_operation (code
, mode
,
5483 XEXP (XEXP (x
, 0), 0),
5488 return simplify_gen_binary (code
, mode
, other
, inner
);
5492 /* A little bit of algebraic simplification here. */
5496 /* Ensure that our address has any ASHIFTs converted to MULT in case
5497 address-recognizing predicates are called later. */
5498 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5499 SUBST (XEXP (x
, 0), temp
);
5503 if (op0_mode
== VOIDmode
)
5504 op0_mode
= GET_MODE (SUBREG_REG (x
));
5506 /* See if this can be moved to simplify_subreg. */
5507 if (CONSTANT_P (SUBREG_REG (x
))
5508 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5509 /* Don't call gen_lowpart if the inner mode
5510 is VOIDmode and we cannot simplify it, as SUBREG without
5511 inner mode is invalid. */
5512 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5513 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5514 return gen_lowpart (mode
, SUBREG_REG (x
));
5516 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5520 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5526 /* Don't change the mode of the MEM if that would change the meaning
5528 if (MEM_P (SUBREG_REG (x
))
5529 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5530 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
5531 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5533 /* Note that we cannot do any narrowing for non-constants since
5534 we might have been counting on using the fact that some bits were
5535 zero. We now do this in the SET. */
5540 temp
= expand_compound_operation (XEXP (x
, 0));
5542 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5543 replaced by (lshiftrt X C). This will convert
5544 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5546 if (GET_CODE (temp
) == ASHIFTRT
5547 && CONST_INT_P (XEXP (temp
, 1))
5548 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5549 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5550 INTVAL (XEXP (temp
, 1)));
5552 /* If X has only a single bit that might be nonzero, say, bit I, convert
5553 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5554 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5555 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5556 or a SUBREG of one since we'd be making the expression more
5557 complex if it was just a register. */
5560 && ! (GET_CODE (temp
) == SUBREG
5561 && REG_P (SUBREG_REG (temp
)))
5562 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5564 rtx temp1
= simplify_shift_const
5565 (NULL_RTX
, ASHIFTRT
, mode
,
5566 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5567 GET_MODE_PRECISION (mode
) - 1 - i
),
5568 GET_MODE_PRECISION (mode
) - 1 - i
);
5570 /* If all we did was surround TEMP with the two shifts, we
5571 haven't improved anything, so don't use it. Otherwise,
5572 we are better off with TEMP1. */
5573 if (GET_CODE (temp1
) != ASHIFTRT
5574 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5575 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5581 /* We can't handle truncation to a partial integer mode here
5582 because we don't know the real bitsize of the partial
5584 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5587 if (HWI_COMPUTABLE_MODE_P (mode
))
5589 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5590 GET_MODE_MASK (mode
), 0));
5592 /* We can truncate a constant value and return it. */
5593 if (CONST_INT_P (XEXP (x
, 0)))
5594 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5596 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5597 whose value is a comparison can be replaced with a subreg if
5598 STORE_FLAG_VALUE permits. */
5599 if (HWI_COMPUTABLE_MODE_P (mode
)
5600 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5601 && (temp
= get_last_value (XEXP (x
, 0)))
5602 && COMPARISON_P (temp
))
5603 return gen_lowpart (mode
, XEXP (x
, 0));
5607 /* (const (const X)) can become (const X). Do it this way rather than
5608 returning the inner CONST since CONST can be shared with a
5610 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5611 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5616 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5617 can add in an offset. find_split_point will split this address up
5618 again if it doesn't match. */
5619 if (GET_CODE (XEXP (x
, 0)) == HIGH
5620 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5626 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5627 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5628 bit-field and can be replaced by either a sign_extend or a
5629 sign_extract. The `and' may be a zero_extend and the two
5630 <c>, -<c> constants may be reversed. */
5631 if (GET_CODE (XEXP (x
, 0)) == XOR
5632 && CONST_INT_P (XEXP (x
, 1))
5633 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5634 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5635 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5636 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5637 && HWI_COMPUTABLE_MODE_P (mode
)
5638 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5639 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5640 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5641 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5642 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5643 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5644 == (unsigned int) i
+ 1))))
5645 return simplify_shift_const
5646 (NULL_RTX
, ASHIFTRT
, mode
,
5647 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5648 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5649 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5650 GET_MODE_PRECISION (mode
) - (i
+ 1));
5652 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5653 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5654 the bitsize of the mode - 1. This allows simplification of
5655 "a = (b & 8) == 0;" */
5656 if (XEXP (x
, 1) == constm1_rtx
5657 && !REG_P (XEXP (x
, 0))
5658 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5659 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5660 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5661 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5662 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5663 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5664 GET_MODE_PRECISION (mode
) - 1),
5665 GET_MODE_PRECISION (mode
) - 1);
5667 /* If we are adding two things that have no bits in common, convert
5668 the addition into an IOR. This will often be further simplified,
5669 for example in cases like ((a & 1) + (a & 2)), which can
5672 if (HWI_COMPUTABLE_MODE_P (mode
)
5673 && (nonzero_bits (XEXP (x
, 0), mode
)
5674 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5676 /* Try to simplify the expression further. */
5677 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5678 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5680 /* If we could, great. If not, do not go ahead with the IOR
5681 replacement, since PLUS appears in many special purpose
5682 address arithmetic instructions. */
5683 if (GET_CODE (temp
) != CLOBBER
5684 && (GET_CODE (temp
) != IOR
5685 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5686 || XEXP (temp
, 1) != XEXP (x
, 1))
5687 && (XEXP (temp
, 0) != XEXP (x
, 1)
5688 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5694 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5695 (and <foo> (const_int pow2-1)) */
5696 if (GET_CODE (XEXP (x
, 1)) == AND
5697 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5698 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5699 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5700 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5701 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5705 /* If we have (mult (plus A B) C), apply the distributive law and then
5706 the inverse distributive law to see if things simplify. This
5707 occurs mostly in addresses, often when unrolling loops. */
5709 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5711 rtx result
= distribute_and_simplify_rtx (x
, 0);
5716 /* Try simplify a*(b/c) as (a*b)/c. */
5717 if (FLOAT_MODE_P (mode
) && flag_associative_math
5718 && GET_CODE (XEXP (x
, 0)) == DIV
)
5720 rtx tem
= simplify_binary_operation (MULT
, mode
,
5721 XEXP (XEXP (x
, 0), 0),
5724 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5729 /* If this is a divide by a power of two, treat it as a shift if
5730 its first operand is a shift. */
5731 if (CONST_INT_P (XEXP (x
, 1))
5732 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5733 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5734 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5735 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5736 || GET_CODE (XEXP (x
, 0)) == ROTATE
5737 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5738 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5742 case GT
: case GTU
: case GE
: case GEU
:
5743 case LT
: case LTU
: case LE
: case LEU
:
5744 case UNEQ
: case LTGT
:
5745 case UNGT
: case UNGE
:
5746 case UNLT
: case UNLE
:
5747 case UNORDERED
: case ORDERED
:
5748 /* If the first operand is a condition code, we can't do anything
5750 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5751 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5752 && ! CC0_P (XEXP (x
, 0))))
5754 rtx op0
= XEXP (x
, 0);
5755 rtx op1
= XEXP (x
, 1);
5756 enum rtx_code new_code
;
5758 if (GET_CODE (op0
) == COMPARE
)
5759 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5761 /* Simplify our comparison, if possible. */
5762 new_code
= simplify_comparison (code
, &op0
, &op1
);
5764 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5765 if only the low-order bit is possibly nonzero in X (such as when
5766 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5767 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5768 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5771 Remove any ZERO_EXTRACT we made when thinking this was a
5772 comparison. It may now be simpler to use, e.g., an AND. If a
5773 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5774 the call to make_compound_operation in the SET case.
5776 Don't apply these optimizations if the caller would
5777 prefer a comparison rather than a value.
5778 E.g., for the condition in an IF_THEN_ELSE most targets need
5779 an explicit comparison. */
5784 else if (STORE_FLAG_VALUE
== 1
5785 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5786 && op1
== const0_rtx
5787 && mode
== GET_MODE (op0
)
5788 && nonzero_bits (op0
, mode
) == 1)
5789 return gen_lowpart (mode
,
5790 expand_compound_operation (op0
));
5792 else if (STORE_FLAG_VALUE
== 1
5793 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5794 && op1
== const0_rtx
5795 && mode
== GET_MODE (op0
)
5796 && (num_sign_bit_copies (op0
, mode
)
5797 == GET_MODE_PRECISION (mode
)))
5799 op0
= expand_compound_operation (op0
);
5800 return simplify_gen_unary (NEG
, mode
,
5801 gen_lowpart (mode
, op0
),
5805 else if (STORE_FLAG_VALUE
== 1
5806 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5807 && op1
== const0_rtx
5808 && mode
== GET_MODE (op0
)
5809 && nonzero_bits (op0
, mode
) == 1)
5811 op0
= expand_compound_operation (op0
);
5812 return simplify_gen_binary (XOR
, mode
,
5813 gen_lowpart (mode
, op0
),
5817 else if (STORE_FLAG_VALUE
== 1
5818 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5819 && op1
== const0_rtx
5820 && mode
== GET_MODE (op0
)
5821 && (num_sign_bit_copies (op0
, mode
)
5822 == GET_MODE_PRECISION (mode
)))
5824 op0
= expand_compound_operation (op0
);
5825 return plus_constant (gen_lowpart (mode
, op0
), 1);
5828 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5833 else if (STORE_FLAG_VALUE
== -1
5834 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5835 && op1
== const0_rtx
5836 && (num_sign_bit_copies (op0
, mode
)
5837 == GET_MODE_PRECISION (mode
)))
5838 return gen_lowpart (mode
,
5839 expand_compound_operation (op0
));
5841 else if (STORE_FLAG_VALUE
== -1
5842 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5843 && op1
== const0_rtx
5844 && mode
== GET_MODE (op0
)
5845 && nonzero_bits (op0
, mode
) == 1)
5847 op0
= expand_compound_operation (op0
);
5848 return simplify_gen_unary (NEG
, mode
,
5849 gen_lowpart (mode
, op0
),
5853 else if (STORE_FLAG_VALUE
== -1
5854 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5855 && op1
== const0_rtx
5856 && mode
== GET_MODE (op0
)
5857 && (num_sign_bit_copies (op0
, mode
)
5858 == GET_MODE_PRECISION (mode
)))
5860 op0
= expand_compound_operation (op0
);
5861 return simplify_gen_unary (NOT
, mode
,
5862 gen_lowpart (mode
, op0
),
5866 /* If X is 0/1, (eq X 0) is X-1. */
5867 else if (STORE_FLAG_VALUE
== -1
5868 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5869 && op1
== const0_rtx
5870 && mode
== GET_MODE (op0
)
5871 && nonzero_bits (op0
, mode
) == 1)
5873 op0
= expand_compound_operation (op0
);
5874 return plus_constant (gen_lowpart (mode
, op0
), -1);
5877 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5878 one bit that might be nonzero, we can convert (ne x 0) to
5879 (ashift x c) where C puts the bit in the sign bit. Remove any
5880 AND with STORE_FLAG_VALUE when we are done, since we are only
5881 going to test the sign bit. */
5882 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5883 && HWI_COMPUTABLE_MODE_P (mode
)
5884 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5885 && op1
== const0_rtx
5886 && mode
== GET_MODE (op0
)
5887 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5889 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5890 expand_compound_operation (op0
),
5891 GET_MODE_PRECISION (mode
) - 1 - i
);
5892 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5898 /* If the code changed, return a whole new comparison. */
5899 if (new_code
!= code
)
5900 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5902 /* Otherwise, keep this operation, but maybe change its operands.
5903 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5904 SUBST (XEXP (x
, 0), op0
);
5905 SUBST (XEXP (x
, 1), op1
);
5910 return simplify_if_then_else (x
);
5916 /* If we are processing SET_DEST, we are done. */
5920 return expand_compound_operation (x
);
5923 return simplify_set (x
);
5927 return simplify_logical (x
);
5934 /* If this is a shift by a constant amount, simplify it. */
5935 if (CONST_INT_P (XEXP (x
, 1)))
5936 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5937 INTVAL (XEXP (x
, 1)));
5939 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5941 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5942 targetm
.shift_truncation_mask (GET_MODE (x
)),
5953 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5956 simplify_if_then_else (rtx x
)
5958 enum machine_mode mode
= GET_MODE (x
);
5959 rtx cond
= XEXP (x
, 0);
5960 rtx true_rtx
= XEXP (x
, 1);
5961 rtx false_rtx
= XEXP (x
, 2);
5962 enum rtx_code true_code
= GET_CODE (cond
);
5963 int comparison_p
= COMPARISON_P (cond
);
5966 enum rtx_code false_code
;
5969 /* Simplify storing of the truth value. */
5970 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5971 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5972 XEXP (cond
, 0), XEXP (cond
, 1));
5974 /* Also when the truth value has to be reversed. */
5976 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5977 && (reversed
= reversed_comparison (cond
, mode
)))
5980 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5981 in it is being compared against certain values. Get the true and false
5982 comparisons and see if that says anything about the value of each arm. */
5985 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5987 && REG_P (XEXP (cond
, 0)))
5990 rtx from
= XEXP (cond
, 0);
5991 rtx true_val
= XEXP (cond
, 1);
5992 rtx false_val
= true_val
;
5995 /* If FALSE_CODE is EQ, swap the codes and arms. */
5997 if (false_code
== EQ
)
5999 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6000 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6003 /* If we are comparing against zero and the expression being tested has
6004 only a single bit that might be nonzero, that is its value when it is
6005 not equal to zero. Similarly if it is known to be -1 or 0. */
6007 if (true_code
== EQ
&& true_val
== const0_rtx
6008 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
6011 false_val
= GEN_INT (trunc_int_for_mode (nzb
, GET_MODE (from
)));
6013 else if (true_code
== EQ
&& true_val
== const0_rtx
6014 && (num_sign_bit_copies (from
, GET_MODE (from
))
6015 == GET_MODE_PRECISION (GET_MODE (from
))))
6018 false_val
= constm1_rtx
;
6021 /* Now simplify an arm if we know the value of the register in the
6022 branch and it is used in the arm. Be careful due to the potential
6023 of locally-shared RTL. */
6025 if (reg_mentioned_p (from
, true_rtx
))
6026 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6028 pc_rtx
, pc_rtx
, 0, 0, 0);
6029 if (reg_mentioned_p (from
, false_rtx
))
6030 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6032 pc_rtx
, pc_rtx
, 0, 0, 0);
6034 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6035 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6037 true_rtx
= XEXP (x
, 1);
6038 false_rtx
= XEXP (x
, 2);
6039 true_code
= GET_CODE (cond
);
6042 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6043 reversed, do so to avoid needing two sets of patterns for
6044 subtract-and-branch insns. Similarly if we have a constant in the true
6045 arm, the false arm is the same as the first operand of the comparison, or
6046 the false arm is more complicated than the true arm. */
6049 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6050 && (true_rtx
== pc_rtx
6051 || (CONSTANT_P (true_rtx
)
6052 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6053 || true_rtx
== const0_rtx
6054 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6055 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6056 && !OBJECT_P (false_rtx
))
6057 || reg_mentioned_p (true_rtx
, false_rtx
)
6058 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6060 true_code
= reversed_comparison_code (cond
, NULL
);
6061 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6062 SUBST (XEXP (x
, 1), false_rtx
);
6063 SUBST (XEXP (x
, 2), true_rtx
);
6065 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6068 /* It is possible that the conditional has been simplified out. */
6069 true_code
= GET_CODE (cond
);
6070 comparison_p
= COMPARISON_P (cond
);
6073 /* If the two arms are identical, we don't need the comparison. */
6075 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6078 /* Convert a == b ? b : a to "a". */
6079 if (true_code
== EQ
&& ! side_effects_p (cond
)
6080 && !HONOR_NANS (mode
)
6081 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6082 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6084 else if (true_code
== NE
&& ! side_effects_p (cond
)
6085 && !HONOR_NANS (mode
)
6086 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6087 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6090 /* Look for cases where we have (abs x) or (neg (abs X)). */
6092 if (GET_MODE_CLASS (mode
) == MODE_INT
6094 && XEXP (cond
, 1) == const0_rtx
6095 && GET_CODE (false_rtx
) == NEG
6096 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6097 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6098 && ! side_effects_p (true_rtx
))
6103 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6107 simplify_gen_unary (NEG
, mode
,
6108 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6114 /* Look for MIN or MAX. */
6116 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6118 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6119 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6120 && ! side_effects_p (cond
))
6125 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6128 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6131 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6134 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6139 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6140 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6141 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6142 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6143 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6144 neither 1 or -1, but it isn't worth checking for. */
6146 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6148 && GET_MODE_CLASS (mode
) == MODE_INT
6149 && ! side_effects_p (x
))
6151 rtx t
= make_compound_operation (true_rtx
, SET
);
6152 rtx f
= make_compound_operation (false_rtx
, SET
);
6153 rtx cond_op0
= XEXP (cond
, 0);
6154 rtx cond_op1
= XEXP (cond
, 1);
6155 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6156 enum machine_mode m
= mode
;
6157 rtx z
= 0, c1
= NULL_RTX
;
6159 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6160 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6161 || GET_CODE (t
) == ASHIFT
6162 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6163 && rtx_equal_p (XEXP (t
, 0), f
))
6164 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6166 /* If an identity-zero op is commutative, check whether there
6167 would be a match if we swapped the operands. */
6168 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6169 || GET_CODE (t
) == XOR
)
6170 && rtx_equal_p (XEXP (t
, 1), f
))
6171 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6172 else if (GET_CODE (t
) == SIGN_EXTEND
6173 && (GET_CODE (XEXP (t
, 0)) == PLUS
6174 || GET_CODE (XEXP (t
, 0)) == MINUS
6175 || GET_CODE (XEXP (t
, 0)) == IOR
6176 || GET_CODE (XEXP (t
, 0)) == XOR
6177 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6178 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6179 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6180 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6181 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6182 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6183 && (num_sign_bit_copies (f
, GET_MODE (f
))
6185 (GET_MODE_PRECISION (mode
)
6186 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6188 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6189 extend_op
= SIGN_EXTEND
;
6190 m
= GET_MODE (XEXP (t
, 0));
6192 else if (GET_CODE (t
) == SIGN_EXTEND
6193 && (GET_CODE (XEXP (t
, 0)) == PLUS
6194 || GET_CODE (XEXP (t
, 0)) == IOR
6195 || GET_CODE (XEXP (t
, 0)) == XOR
)
6196 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6197 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6198 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6199 && (num_sign_bit_copies (f
, GET_MODE (f
))
6201 (GET_MODE_PRECISION (mode
)
6202 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6204 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6205 extend_op
= SIGN_EXTEND
;
6206 m
= GET_MODE (XEXP (t
, 0));
6208 else if (GET_CODE (t
) == ZERO_EXTEND
6209 && (GET_CODE (XEXP (t
, 0)) == PLUS
6210 || GET_CODE (XEXP (t
, 0)) == MINUS
6211 || GET_CODE (XEXP (t
, 0)) == IOR
6212 || GET_CODE (XEXP (t
, 0)) == XOR
6213 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6214 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6215 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6216 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6217 && HWI_COMPUTABLE_MODE_P (mode
)
6218 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6219 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6220 && ((nonzero_bits (f
, GET_MODE (f
))
6221 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6224 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6225 extend_op
= ZERO_EXTEND
;
6226 m
= GET_MODE (XEXP (t
, 0));
6228 else if (GET_CODE (t
) == ZERO_EXTEND
6229 && (GET_CODE (XEXP (t
, 0)) == PLUS
6230 || GET_CODE (XEXP (t
, 0)) == IOR
6231 || GET_CODE (XEXP (t
, 0)) == XOR
)
6232 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6233 && HWI_COMPUTABLE_MODE_P (mode
)
6234 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6235 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6236 && ((nonzero_bits (f
, GET_MODE (f
))
6237 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6240 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6241 extend_op
= ZERO_EXTEND
;
6242 m
= GET_MODE (XEXP (t
, 0));
6247 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6248 cond_op0
, cond_op1
),
6249 pc_rtx
, pc_rtx
, 0, 0, 0);
6250 temp
= simplify_gen_binary (MULT
, m
, temp
,
6251 simplify_gen_binary (MULT
, m
, c1
,
6253 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6254 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6256 if (extend_op
!= UNKNOWN
)
6257 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6263 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6264 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6265 negation of a single bit, we can convert this operation to a shift. We
6266 can actually do this more generally, but it doesn't seem worth it. */
6268 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6269 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6270 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6271 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6272 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6273 == GET_MODE_PRECISION (mode
))
6274 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6276 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6277 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6279 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6280 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6281 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6282 && GET_MODE (XEXP (cond
, 0)) == mode
6283 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6284 == nonzero_bits (XEXP (cond
, 0), mode
)
6285 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6286 return XEXP (cond
, 0);
6291 /* Simplify X, a SET expression. Return the new expression. */
6294 simplify_set (rtx x
)
6296 rtx src
= SET_SRC (x
);
6297 rtx dest
= SET_DEST (x
);
6298 enum machine_mode mode
6299 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6303 /* (set (pc) (return)) gets written as (return). */
6304 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
6307 /* Now that we know for sure which bits of SRC we are using, see if we can
6308 simplify the expression for the object knowing that we only need the
6311 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6313 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6314 SUBST (SET_SRC (x
), src
);
6317 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6318 the comparison result and try to simplify it unless we already have used
6319 undobuf.other_insn. */
6320 if ((GET_MODE_CLASS (mode
) == MODE_CC
6321 || GET_CODE (src
) == COMPARE
6323 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6324 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6325 && COMPARISON_P (*cc_use
)
6326 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6328 enum rtx_code old_code
= GET_CODE (*cc_use
);
6329 enum rtx_code new_code
;
6331 int other_changed
= 0;
6332 rtx inner_compare
= NULL_RTX
;
6333 enum machine_mode compare_mode
= GET_MODE (dest
);
6335 if (GET_CODE (src
) == COMPARE
)
6337 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6338 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6340 inner_compare
= op0
;
6341 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6345 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6347 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6350 new_code
= old_code
;
6351 else if (!CONSTANT_P (tmp
))
6353 new_code
= GET_CODE (tmp
);
6354 op0
= XEXP (tmp
, 0);
6355 op1
= XEXP (tmp
, 1);
6359 rtx pat
= PATTERN (other_insn
);
6360 undobuf
.other_insn
= other_insn
;
6361 SUBST (*cc_use
, tmp
);
6363 /* Attempt to simplify CC user. */
6364 if (GET_CODE (pat
) == SET
)
6366 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6367 if (new_rtx
!= NULL_RTX
)
6368 SUBST (SET_SRC (pat
), new_rtx
);
6371 /* Convert X into a no-op move. */
6372 SUBST (SET_DEST (x
), pc_rtx
);
6373 SUBST (SET_SRC (x
), pc_rtx
);
6377 /* Simplify our comparison, if possible. */
6378 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6380 #ifdef SELECT_CC_MODE
6381 /* If this machine has CC modes other than CCmode, check to see if we
6382 need to use a different CC mode here. */
6383 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6384 compare_mode
= GET_MODE (op0
);
6385 else if (inner_compare
6386 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6387 && new_code
== old_code
6388 && op0
== XEXP (inner_compare
, 0)
6389 && op1
== XEXP (inner_compare
, 1))
6390 compare_mode
= GET_MODE (inner_compare
);
6392 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6395 /* If the mode changed, we have to change SET_DEST, the mode in the
6396 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6397 a hard register, just build new versions with the proper mode. If it
6398 is a pseudo, we lose unless it is only time we set the pseudo, in
6399 which case we can safely change its mode. */
6400 if (compare_mode
!= GET_MODE (dest
))
6402 if (can_change_dest_mode (dest
, 0, compare_mode
))
6404 unsigned int regno
= REGNO (dest
);
6407 if (regno
< FIRST_PSEUDO_REGISTER
)
6408 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6411 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6412 new_dest
= regno_reg_rtx
[regno
];
6415 SUBST (SET_DEST (x
), new_dest
);
6416 SUBST (XEXP (*cc_use
, 0), new_dest
);
6423 #endif /* SELECT_CC_MODE */
6425 /* If the code changed, we have to build a new comparison in
6426 undobuf.other_insn. */
6427 if (new_code
!= old_code
)
6429 int other_changed_previously
= other_changed
;
6430 unsigned HOST_WIDE_INT mask
;
6431 rtx old_cc_use
= *cc_use
;
6433 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6437 /* If the only change we made was to change an EQ into an NE or
6438 vice versa, OP0 has only one bit that might be nonzero, and OP1
6439 is zero, check if changing the user of the condition code will
6440 produce a valid insn. If it won't, we can keep the original code
6441 in that insn by surrounding our operation with an XOR. */
6443 if (((old_code
== NE
&& new_code
== EQ
)
6444 || (old_code
== EQ
&& new_code
== NE
))
6445 && ! other_changed_previously
&& op1
== const0_rtx
6446 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6447 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6449 rtx pat
= PATTERN (other_insn
), note
= 0;
6451 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6452 && ! check_asm_operands (pat
)))
6454 *cc_use
= old_cc_use
;
6457 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6458 op0
, GEN_INT (mask
));
6464 undobuf
.other_insn
= other_insn
;
6466 /* Otherwise, if we didn't previously have a COMPARE in the
6467 correct mode, we need one. */
6468 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6470 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6473 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6475 SUBST (SET_SRC (x
), op0
);
6478 /* Otherwise, update the COMPARE if needed. */
6479 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6481 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6487 /* Get SET_SRC in a form where we have placed back any
6488 compound expressions. Then do the checks below. */
6489 src
= make_compound_operation (src
, SET
);
6490 SUBST (SET_SRC (x
), src
);
6493 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6494 and X being a REG or (subreg (reg)), we may be able to convert this to
6495 (set (subreg:m2 x) (op)).
6497 We can always do this if M1 is narrower than M2 because that means that
6498 we only care about the low bits of the result.
6500 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6501 perform a narrower operation than requested since the high-order bits will
6502 be undefined. On machine where it is defined, this transformation is safe
6503 as long as M1 and M2 have the same number of words. */
6505 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6506 && !OBJECT_P (SUBREG_REG (src
))
6507 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6509 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6510 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6511 #ifndef WORD_REGISTER_OPERATIONS
6512 && (GET_MODE_SIZE (GET_MODE (src
))
6513 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6515 #ifdef CANNOT_CHANGE_MODE_CLASS
6516 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6517 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6518 GET_MODE (SUBREG_REG (src
)),
6522 || (GET_CODE (dest
) == SUBREG
6523 && REG_P (SUBREG_REG (dest
)))))
6525 SUBST (SET_DEST (x
),
6526 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6528 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6530 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6534 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6537 && GET_CODE (src
) == SUBREG
6538 && subreg_lowpart_p (src
)
6539 && (GET_MODE_PRECISION (GET_MODE (src
))
6540 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6542 rtx inner
= SUBREG_REG (src
);
6543 enum machine_mode inner_mode
= GET_MODE (inner
);
6545 /* Here we make sure that we don't have a sign bit on. */
6546 if (val_signbit_known_clear_p (GET_MODE (src
),
6547 nonzero_bits (inner
, inner_mode
)))
6549 SUBST (SET_SRC (x
), inner
);
6555 #ifdef LOAD_EXTEND_OP
6556 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6557 would require a paradoxical subreg. Replace the subreg with a
6558 zero_extend to avoid the reload that would otherwise be required. */
6560 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6561 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6562 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6563 && SUBREG_BYTE (src
) == 0
6564 && paradoxical_subreg_p (src
)
6565 && MEM_P (SUBREG_REG (src
)))
6568 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6569 GET_MODE (src
), SUBREG_REG (src
)));
6575 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6576 are comparing an item known to be 0 or -1 against 0, use a logical
6577 operation instead. Check for one of the arms being an IOR of the other
6578 arm with some value. We compute three terms to be IOR'ed together. In
6579 practice, at most two will be nonzero. Then we do the IOR's. */
6581 if (GET_CODE (dest
) != PC
6582 && GET_CODE (src
) == IF_THEN_ELSE
6583 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6584 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6585 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6586 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6587 #ifdef HAVE_conditional_move
6588 && ! can_conditionally_move_p (GET_MODE (src
))
6590 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6591 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6592 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6593 && ! side_effects_p (src
))
6595 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6596 ? XEXP (src
, 1) : XEXP (src
, 2));
6597 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6598 ? XEXP (src
, 2) : XEXP (src
, 1));
6599 rtx term1
= const0_rtx
, term2
, term3
;
6601 if (GET_CODE (true_rtx
) == IOR
6602 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6603 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6604 else if (GET_CODE (true_rtx
) == IOR
6605 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6606 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6607 else if (GET_CODE (false_rtx
) == IOR
6608 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6609 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6610 else if (GET_CODE (false_rtx
) == IOR
6611 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6612 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6614 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6615 XEXP (XEXP (src
, 0), 0), true_rtx
);
6616 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6617 simplify_gen_unary (NOT
, GET_MODE (src
),
6618 XEXP (XEXP (src
, 0), 0),
6623 simplify_gen_binary (IOR
, GET_MODE (src
),
6624 simplify_gen_binary (IOR
, GET_MODE (src
),
6631 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6632 whole thing fail. */
6633 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6635 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6638 /* Convert this into a field assignment operation, if possible. */
6639 return make_field_assignment (x
);
6642 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6646 simplify_logical (rtx x
)
6648 enum machine_mode mode
= GET_MODE (x
);
6649 rtx op0
= XEXP (x
, 0);
6650 rtx op1
= XEXP (x
, 1);
6652 switch (GET_CODE (x
))
6655 /* We can call simplify_and_const_int only if we don't lose
6656 any (sign) bits when converting INTVAL (op1) to
6657 "unsigned HOST_WIDE_INT". */
6658 if (CONST_INT_P (op1
)
6659 && (HWI_COMPUTABLE_MODE_P (mode
)
6660 || INTVAL (op1
) > 0))
6662 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6663 if (GET_CODE (x
) != AND
)
6670 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6671 apply the distributive law and then the inverse distributive
6672 law to see if things simplify. */
6673 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6675 rtx result
= distribute_and_simplify_rtx (x
, 0);
6679 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6681 rtx result
= distribute_and_simplify_rtx (x
, 1);
6688 /* If we have (ior (and A B) C), apply the distributive law and then
6689 the inverse distributive law to see if things simplify. */
6691 if (GET_CODE (op0
) == AND
)
6693 rtx result
= distribute_and_simplify_rtx (x
, 0);
6698 if (GET_CODE (op1
) == AND
)
6700 rtx result
= distribute_and_simplify_rtx (x
, 1);
6713 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6714 operations" because they can be replaced with two more basic operations.
6715 ZERO_EXTEND is also considered "compound" because it can be replaced with
6716 an AND operation, which is simpler, though only one operation.
6718 The function expand_compound_operation is called with an rtx expression
6719 and will convert it to the appropriate shifts and AND operations,
6720 simplifying at each stage.
6722 The function make_compound_operation is called to convert an expression
6723 consisting of shifts and ANDs into the equivalent compound expression.
6724 It is the inverse of this function, loosely speaking. */
6727 expand_compound_operation (rtx x
)
6729 unsigned HOST_WIDE_INT pos
= 0, len
;
6731 unsigned int modewidth
;
6734 switch (GET_CODE (x
))
6739 /* We can't necessarily use a const_int for a multiword mode;
6740 it depends on implicitly extending the value.
6741 Since we don't know the right way to extend it,
6742 we can't tell whether the implicit way is right.
6744 Even for a mode that is no wider than a const_int,
6745 we can't win, because we need to sign extend one of its bits through
6746 the rest of it, and we don't know which bit. */
6747 if (CONST_INT_P (XEXP (x
, 0)))
6750 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6751 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6752 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6753 reloaded. If not for that, MEM's would very rarely be safe.
6755 Reject MODEs bigger than a word, because we might not be able
6756 to reference a two-register group starting with an arbitrary register
6757 (and currently gen_lowpart might crash for a SUBREG). */
6759 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6762 /* Reject MODEs that aren't scalar integers because turning vector
6763 or complex modes into shifts causes problems. */
6765 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6768 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6769 /* If the inner object has VOIDmode (the only way this can happen
6770 is if it is an ASM_OPERANDS), we can't do anything since we don't
6771 know how much masking to do. */
6780 /* ... fall through ... */
6783 /* If the operand is a CLOBBER, just return it. */
6784 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6787 if (!CONST_INT_P (XEXP (x
, 1))
6788 || !CONST_INT_P (XEXP (x
, 2))
6789 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6792 /* Reject MODEs that aren't scalar integers because turning vector
6793 or complex modes into shifts causes problems. */
6795 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6798 len
= INTVAL (XEXP (x
, 1));
6799 pos
= INTVAL (XEXP (x
, 2));
6801 /* This should stay within the object being extracted, fail otherwise. */
6802 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6805 if (BITS_BIG_ENDIAN
)
6806 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6813 /* Convert sign extension to zero extension, if we know that the high
6814 bit is not set, as this is easier to optimize. It will be converted
6815 back to cheaper alternative in make_extraction. */
6816 if (GET_CODE (x
) == SIGN_EXTEND
6817 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6818 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6819 & ~(((unsigned HOST_WIDE_INT
)
6820 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6824 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6825 rtx temp2
= expand_compound_operation (temp
);
6827 /* Make sure this is a profitable operation. */
6828 if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6829 > rtx_cost (temp2
, SET
, optimize_this_for_speed_p
))
6831 else if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6832 > rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
6838 /* We can optimize some special cases of ZERO_EXTEND. */
6839 if (GET_CODE (x
) == ZERO_EXTEND
)
6841 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6842 know that the last value didn't have any inappropriate bits
6844 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6845 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6846 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6847 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6848 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6849 return XEXP (XEXP (x
, 0), 0);
6851 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6852 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6853 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6854 && subreg_lowpart_p (XEXP (x
, 0))
6855 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6856 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6857 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6858 return SUBREG_REG (XEXP (x
, 0));
6860 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6861 is a comparison and STORE_FLAG_VALUE permits. This is like
6862 the first case, but it works even when GET_MODE (x) is larger
6863 than HOST_WIDE_INT. */
6864 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6865 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6866 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6867 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6868 <= HOST_BITS_PER_WIDE_INT
)
6869 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6870 return XEXP (XEXP (x
, 0), 0);
6872 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6873 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6874 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6875 && subreg_lowpart_p (XEXP (x
, 0))
6876 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6877 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6878 <= HOST_BITS_PER_WIDE_INT
)
6879 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6880 return SUBREG_REG (XEXP (x
, 0));
6884 /* If we reach here, we want to return a pair of shifts. The inner
6885 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6886 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6887 logical depending on the value of UNSIGNEDP.
6889 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6890 converted into an AND of a shift.
6892 We must check for the case where the left shift would have a negative
6893 count. This can happen in a case like (x >> 31) & 255 on machines
6894 that can't shift by a constant. On those machines, we would first
6895 combine the shift with the AND to produce a variable-position
6896 extraction. Then the constant of 31 would be substituted in
6897 to produce such a position. */
6899 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6900 if (modewidth
>= pos
+ len
)
6902 enum machine_mode mode
= GET_MODE (x
);
6903 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6904 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6906 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6907 tem
, modewidth
- pos
- len
);
6908 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6909 mode
, tem
, modewidth
- len
);
6911 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6912 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6913 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6916 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6918 /* Any other cases we can't handle. */
6921 /* If we couldn't do this for some reason, return the original
6923 if (GET_CODE (tem
) == CLOBBER
)
6929 /* X is a SET which contains an assignment of one object into
6930 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6931 or certain SUBREGS). If possible, convert it into a series of
6934 We half-heartedly support variable positions, but do not at all
6935 support variable lengths. */
6938 expand_field_assignment (const_rtx x
)
6941 rtx pos
; /* Always counts from low bit. */
6943 rtx mask
, cleared
, masked
;
6944 enum machine_mode compute_mode
;
6946 /* Loop until we find something we can't simplify. */
6949 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6950 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6952 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6953 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
6954 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6956 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6957 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6959 inner
= XEXP (SET_DEST (x
), 0);
6960 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6961 pos
= XEXP (SET_DEST (x
), 2);
6963 /* A constant position should stay within the width of INNER. */
6964 if (CONST_INT_P (pos
)
6965 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
6968 if (BITS_BIG_ENDIAN
)
6970 if (CONST_INT_P (pos
))
6971 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
6973 else if (GET_CODE (pos
) == MINUS
6974 && CONST_INT_P (XEXP (pos
, 1))
6975 && (INTVAL (XEXP (pos
, 1))
6976 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
6977 /* If position is ADJUST - X, new position is X. */
6978 pos
= XEXP (pos
, 0);
6980 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6981 GEN_INT (GET_MODE_PRECISION (
6988 /* A SUBREG between two modes that occupy the same numbers of words
6989 can be done by moving the SUBREG to the source. */
6990 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6991 /* We need SUBREGs to compute nonzero_bits properly. */
6992 && nonzero_sign_valid
6993 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6994 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6995 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6996 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6998 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
7000 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7007 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7008 inner
= SUBREG_REG (inner
);
7010 compute_mode
= GET_MODE (inner
);
7012 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7013 if (! SCALAR_INT_MODE_P (compute_mode
))
7015 enum machine_mode imode
;
7017 /* Don't do anything for vector or complex integral types. */
7018 if (! FLOAT_MODE_P (compute_mode
))
7021 /* Try to find an integral mode to pun with. */
7022 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7023 if (imode
== BLKmode
)
7026 compute_mode
= imode
;
7027 inner
= gen_lowpart (imode
, inner
);
7030 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7031 if (len
>= HOST_BITS_PER_WIDE_INT
)
7034 /* Now compute the equivalent expression. Make a copy of INNER
7035 for the SET_DEST in case it is a MEM into which we will substitute;
7036 we don't want shared RTL in that case. */
7037 mask
= GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
7038 cleared
= simplify_gen_binary (AND
, compute_mode
,
7039 simplify_gen_unary (NOT
, compute_mode
,
7040 simplify_gen_binary (ASHIFT
,
7045 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7046 simplify_gen_binary (
7048 gen_lowpart (compute_mode
, SET_SRC (x
)),
7052 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
7053 simplify_gen_binary (IOR
, compute_mode
,
7060 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7061 it is an RTX that represents a variable starting position; otherwise,
7062 POS is the (constant) starting bit position (counted from the LSB).
7064 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7067 IN_DEST is nonzero if this is a reference in the destination of a
7068 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7069 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7072 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7073 ZERO_EXTRACT should be built even for bits starting at bit 0.
7075 MODE is the desired mode of the result (if IN_DEST == 0).
7077 The result is an RTX for the extraction or NULL_RTX if the target
7081 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7082 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7083 int in_dest
, int in_compare
)
7085 /* This mode describes the size of the storage area
7086 to fetch the overall value from. Within that, we
7087 ignore the POS lowest bits, etc. */
7088 enum machine_mode is_mode
= GET_MODE (inner
);
7089 enum machine_mode inner_mode
;
7090 enum machine_mode wanted_inner_mode
;
7091 enum machine_mode wanted_inner_reg_mode
= word_mode
;
7092 enum machine_mode pos_mode
= word_mode
;
7093 enum machine_mode extraction_mode
= word_mode
;
7094 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7096 rtx orig_pos_rtx
= pos_rtx
;
7097 HOST_WIDE_INT orig_pos
;
7099 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7101 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7102 consider just the QI as the memory to extract from.
7103 The subreg adds or removes high bits; its mode is
7104 irrelevant to the meaning of this extraction,
7105 since POS and LEN count from the lsb. */
7106 if (MEM_P (SUBREG_REG (inner
)))
7107 is_mode
= GET_MODE (SUBREG_REG (inner
));
7108 inner
= SUBREG_REG (inner
);
7110 else if (GET_CODE (inner
) == ASHIFT
7111 && CONST_INT_P (XEXP (inner
, 1))
7112 && pos_rtx
== 0 && pos
== 0
7113 && len
> UINTVAL (XEXP (inner
, 1)))
7115 /* We're extracting the least significant bits of an rtx
7116 (ashift X (const_int C)), where LEN > C. Extract the
7117 least significant (LEN - C) bits of X, giving an rtx
7118 whose mode is MODE, then shift it left C times. */
7119 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7120 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7121 unsignedp
, in_dest
, in_compare
);
7123 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7126 inner_mode
= GET_MODE (inner
);
7128 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7129 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7131 /* See if this can be done without an extraction. We never can if the
7132 width of the field is not the same as that of some integer mode. For
7133 registers, we can only avoid the extraction if the position is at the
7134 low-order bit and this is either not in the destination or we have the
7135 appropriate STRICT_LOW_PART operation available.
7137 For MEM, we can avoid an extract if the field starts on an appropriate
7138 boundary and we can change the mode of the memory reference. */
7140 if (tmode
!= BLKmode
7141 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7143 && (inner_mode
== tmode
7145 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7146 || reg_truncated_to_mode (tmode
, inner
))
7149 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7150 || (MEM_P (inner
) && pos_rtx
== 0
7152 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7153 : BITS_PER_UNIT
)) == 0
7154 /* We can't do this if we are widening INNER_MODE (it
7155 may not be aligned, for one thing). */
7156 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7157 && (inner_mode
== tmode
7158 || (! mode_dependent_address_p (XEXP (inner
, 0))
7159 && ! MEM_VOLATILE_P (inner
))))))
7161 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7162 field. If the original and current mode are the same, we need not
7163 adjust the offset. Otherwise, we do if bytes big endian.
7165 If INNER is not a MEM, get a piece consisting of just the field
7166 of interest (in this case POS % BITS_PER_WORD must be 0). */
7170 HOST_WIDE_INT offset
;
7172 /* POS counts from lsb, but make OFFSET count in memory order. */
7173 if (BYTES_BIG_ENDIAN
)
7174 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7176 offset
= pos
/ BITS_PER_UNIT
;
7178 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7180 else if (REG_P (inner
))
7182 if (tmode
!= inner_mode
)
7184 /* We can't call gen_lowpart in a DEST since we
7185 always want a SUBREG (see below) and it would sometimes
7186 return a new hard register. */
7189 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7191 if (WORDS_BIG_ENDIAN
7192 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7193 final_word
= ((GET_MODE_SIZE (inner_mode
)
7194 - GET_MODE_SIZE (tmode
))
7195 / UNITS_PER_WORD
) - final_word
;
7197 final_word
*= UNITS_PER_WORD
;
7198 if (BYTES_BIG_ENDIAN
&&
7199 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7200 final_word
+= (GET_MODE_SIZE (inner_mode
)
7201 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7203 /* Avoid creating invalid subregs, for example when
7204 simplifying (x>>32)&255. */
7205 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7208 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7211 new_rtx
= gen_lowpart (tmode
, inner
);
7217 new_rtx
= force_to_mode (inner
, tmode
,
7218 len
>= HOST_BITS_PER_WIDE_INT
7219 ? ~(unsigned HOST_WIDE_INT
) 0
7220 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7223 /* If this extraction is going into the destination of a SET,
7224 make a STRICT_LOW_PART unless we made a MEM. */
7227 return (MEM_P (new_rtx
) ? new_rtx
7228 : (GET_CODE (new_rtx
) != SUBREG
7229 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7230 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7235 if (CONST_INT_P (new_rtx
)
7236 || GET_CODE (new_rtx
) == CONST_DOUBLE
)
7237 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7238 mode
, new_rtx
, tmode
);
7240 /* If we know that no extraneous bits are set, and that the high
7241 bit is not set, convert the extraction to the cheaper of
7242 sign and zero extension, that are equivalent in these cases. */
7243 if (flag_expensive_optimizations
7244 && (HWI_COMPUTABLE_MODE_P (tmode
)
7245 && ((nonzero_bits (new_rtx
, tmode
)
7246 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7249 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7250 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7252 /* Prefer ZERO_EXTENSION, since it gives more information to
7254 if (rtx_cost (temp
, SET
, optimize_this_for_speed_p
)
7255 <= rtx_cost (temp1
, SET
, optimize_this_for_speed_p
))
7260 /* Otherwise, sign- or zero-extend unless we already are in the
7263 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7267 /* Unless this is a COMPARE or we have a funny memory reference,
7268 don't do anything with zero-extending field extracts starting at
7269 the low-order bit since they are simple AND operations. */
7270 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7271 && ! in_compare
&& unsignedp
)
7274 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7275 if the position is not a constant and the length is not 1. In all
7276 other cases, we would only be going outside our object in cases when
7277 an original shift would have been undefined. */
7279 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7280 || (pos_rtx
!= 0 && len
!= 1)))
7283 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7284 and the mode for the result. */
7285 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
7287 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
7288 pos_mode
= mode_for_extraction (EP_insv
, 2);
7289 extraction_mode
= mode_for_extraction (EP_insv
, 3);
7292 if (! in_dest
&& unsignedp
7293 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
7295 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
7296 pos_mode
= mode_for_extraction (EP_extzv
, 3);
7297 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
7300 if (! in_dest
&& ! unsignedp
7301 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
7303 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
7304 pos_mode
= mode_for_extraction (EP_extv
, 3);
7305 extraction_mode
= mode_for_extraction (EP_extv
, 0);
7308 /* Never narrow an object, since that might not be safe. */
7310 if (mode
!= VOIDmode
7311 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7312 extraction_mode
= mode
;
7314 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
7315 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7316 pos_mode
= GET_MODE (pos_rtx
);
7318 /* If this is not from memory, the desired mode is the preferred mode
7319 for an extraction pattern's first input operand, or word_mode if there
7322 wanted_inner_mode
= wanted_inner_reg_mode
;
7325 /* Be careful not to go beyond the extracted object and maintain the
7326 natural alignment of the memory. */
7327 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7328 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7329 > GET_MODE_BITSIZE (wanted_inner_mode
))
7331 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7332 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7335 /* If we have to change the mode of memory and cannot, the desired mode
7336 is EXTRACTION_MODE. */
7337 if (inner_mode
!= wanted_inner_mode
7338 && (mode_dependent_address_p (XEXP (inner
, 0))
7339 || MEM_VOLATILE_P (inner
)
7341 wanted_inner_mode
= extraction_mode
;
7346 if (BITS_BIG_ENDIAN
)
7348 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7349 BITS_BIG_ENDIAN style. If position is constant, compute new
7350 position. Otherwise, build subtraction.
7351 Note that POS is relative to the mode of the original argument.
7352 If it's a MEM we need to recompute POS relative to that.
7353 However, if we're extracting from (or inserting into) a register,
7354 we want to recompute POS relative to wanted_inner_mode. */
7355 int width
= (MEM_P (inner
)
7356 ? GET_MODE_BITSIZE (is_mode
)
7357 : GET_MODE_BITSIZE (wanted_inner_mode
));
7360 pos
= width
- len
- pos
;
7363 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
7364 /* POS may be less than 0 now, but we check for that below.
7365 Note that it can only be less than 0 if !MEM_P (inner). */
7368 /* If INNER has a wider mode, and this is a constant extraction, try to
7369 make it smaller and adjust the byte to point to the byte containing
7371 if (wanted_inner_mode
!= VOIDmode
7372 && inner_mode
!= wanted_inner_mode
7374 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7376 && ! mode_dependent_address_p (XEXP (inner
, 0))
7377 && ! MEM_VOLATILE_P (inner
))
7381 /* The computations below will be correct if the machine is big
7382 endian in both bits and bytes or little endian in bits and bytes.
7383 If it is mixed, we must adjust. */
7385 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7386 adjust OFFSET to compensate. */
7387 if (BYTES_BIG_ENDIAN
7388 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7389 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7391 /* We can now move to the desired byte. */
7392 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7393 * GET_MODE_SIZE (wanted_inner_mode
);
7394 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7396 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7397 && is_mode
!= wanted_inner_mode
)
7398 offset
= (GET_MODE_SIZE (is_mode
)
7399 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7401 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7404 /* If INNER is not memory, get it into the proper mode. If we are changing
7405 its mode, POS must be a constant and smaller than the size of the new
7407 else if (!MEM_P (inner
))
7409 /* On the LHS, don't create paradoxical subregs implicitely truncating
7410 the register unless TRULY_NOOP_TRUNCATION. */
7412 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7416 if (GET_MODE (inner
) != wanted_inner_mode
7418 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7424 inner
= force_to_mode (inner
, wanted_inner_mode
,
7426 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7427 ? ~(unsigned HOST_WIDE_INT
) 0
7428 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7433 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7434 have to zero extend. Otherwise, we can just use a SUBREG. */
7436 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7438 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
7440 /* If we know that no extraneous bits are set, and that the high
7441 bit is not set, convert extraction to cheaper one - either
7442 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7444 if (flag_expensive_optimizations
7445 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7446 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7447 & ~(((unsigned HOST_WIDE_INT
)
7448 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7452 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
7454 /* Prefer ZERO_EXTENSION, since it gives more information to
7456 if (rtx_cost (temp1
, SET
, optimize_this_for_speed_p
)
7457 < rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
7462 else if (pos_rtx
!= 0
7463 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7464 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
7466 /* Make POS_RTX unless we already have it and it is correct. If we don't
7467 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7469 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7470 pos_rtx
= orig_pos_rtx
;
7472 else if (pos_rtx
== 0)
7473 pos_rtx
= GEN_INT (pos
);
7475 /* Make the required operation. See if we can use existing rtx. */
7476 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7477 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7479 new_rtx
= gen_lowpart (mode
, new_rtx
);
7484 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7485 with any other operations in X. Return X without that shift if so. */
7488 extract_left_shift (rtx x
, int count
)
7490 enum rtx_code code
= GET_CODE (x
);
7491 enum machine_mode mode
= GET_MODE (x
);
7497 /* This is the shift itself. If it is wide enough, we will return
7498 either the value being shifted if the shift count is equal to
7499 COUNT or a shift for the difference. */
7500 if (CONST_INT_P (XEXP (x
, 1))
7501 && INTVAL (XEXP (x
, 1)) >= count
)
7502 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7503 INTVAL (XEXP (x
, 1)) - count
);
7507 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7508 return simplify_gen_unary (code
, mode
, tem
, mode
);
7512 case PLUS
: case IOR
: case XOR
: case AND
:
7513 /* If we can safely shift this constant and we find the inner shift,
7514 make a new operation. */
7515 if (CONST_INT_P (XEXP (x
, 1))
7516 && (UINTVAL (XEXP (x
, 1))
7517 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7518 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7519 return simplify_gen_binary (code
, mode
, tem
,
7520 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7531 /* Look at the expression rooted at X. Look for expressions
7532 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7533 Form these expressions.
7535 Return the new rtx, usually just X.
7537 Also, for machines like the VAX that don't have logical shift insns,
7538 try to convert logical to arithmetic shift operations in cases where
7539 they are equivalent. This undoes the canonicalizations to logical
7540 shifts done elsewhere.
7542 We try, as much as possible, to re-use rtl expressions to save memory.
7544 IN_CODE says what kind of expression we are processing. Normally, it is
7545 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7546 being kludges), it is MEM. When processing the arguments of a comparison
7547 or a COMPARE against zero, it is COMPARE. */
7550 make_compound_operation (rtx x
, enum rtx_code in_code
)
7552 enum rtx_code code
= GET_CODE (x
);
7553 enum machine_mode mode
= GET_MODE (x
);
7554 int mode_width
= GET_MODE_PRECISION (mode
);
7556 enum rtx_code next_code
;
7562 /* Select the code to be used in recursive calls. Once we are inside an
7563 address, we stay there. If we have a comparison, set to COMPARE,
7564 but once inside, go back to our default of SET. */
7566 next_code
= (code
== MEM
? MEM
7567 : ((code
== PLUS
|| code
== MINUS
)
7568 && SCALAR_INT_MODE_P (mode
)) ? MEM
7569 : ((code
== COMPARE
|| COMPARISON_P (x
))
7570 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7571 : in_code
== COMPARE
? SET
: in_code
);
7573 /* Process depending on the code of this operation. If NEW is set
7574 nonzero, it will be returned. */
7579 /* Convert shifts by constants into multiplications if inside
7581 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7582 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7583 && INTVAL (XEXP (x
, 1)) >= 0
7584 && SCALAR_INT_MODE_P (mode
))
7586 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7587 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7589 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7590 if (GET_CODE (new_rtx
) == NEG
)
7592 new_rtx
= XEXP (new_rtx
, 0);
7595 multval
= trunc_int_for_mode (multval
, mode
);
7596 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, GEN_INT (multval
));
7603 lhs
= make_compound_operation (lhs
, next_code
);
7604 rhs
= make_compound_operation (rhs
, next_code
);
7605 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7606 && SCALAR_INT_MODE_P (mode
))
7608 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7610 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7612 else if (GET_CODE (lhs
) == MULT
7613 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7615 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7616 simplify_gen_unary (NEG
, mode
,
7619 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7623 SUBST (XEXP (x
, 0), lhs
);
7624 SUBST (XEXP (x
, 1), rhs
);
7627 x
= gen_lowpart (mode
, new_rtx
);
7633 lhs
= make_compound_operation (lhs
, next_code
);
7634 rhs
= make_compound_operation (rhs
, next_code
);
7635 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7636 && SCALAR_INT_MODE_P (mode
))
7638 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7640 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7642 else if (GET_CODE (rhs
) == MULT
7643 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7645 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7646 simplify_gen_unary (NEG
, mode
,
7649 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7653 SUBST (XEXP (x
, 0), lhs
);
7654 SUBST (XEXP (x
, 1), rhs
);
7657 return gen_lowpart (mode
, new_rtx
);
7660 /* If the second operand is not a constant, we can't do anything
7662 if (!CONST_INT_P (XEXP (x
, 1)))
7665 /* If the constant is a power of two minus one and the first operand
7666 is a logical right shift, make an extraction. */
7667 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7668 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7670 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7671 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7672 0, in_code
== COMPARE
);
7675 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7676 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7677 && subreg_lowpart_p (XEXP (x
, 0))
7678 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7679 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7681 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7683 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7684 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7685 0, in_code
== COMPARE
);
7687 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7688 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7689 || GET_CODE (XEXP (x
, 0)) == IOR
)
7690 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7691 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7692 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7694 /* Apply the distributive law, and then try to make extractions. */
7695 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7696 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7698 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7700 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7703 /* If we are have (and (rotate X C) M) and C is larger than the number
7704 of bits in M, this is an extraction. */
7706 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7707 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7708 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7709 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7711 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7712 new_rtx
= make_extraction (mode
, new_rtx
,
7713 (GET_MODE_PRECISION (mode
)
7714 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7715 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7718 /* On machines without logical shifts, if the operand of the AND is
7719 a logical shift and our mask turns off all the propagated sign
7720 bits, we can replace the logical shift with an arithmetic shift. */
7721 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7722 && !have_insn_for (LSHIFTRT
, mode
)
7723 && have_insn_for (ASHIFTRT
, mode
)
7724 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7725 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7726 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7727 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7729 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7731 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7732 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7734 gen_rtx_ASHIFTRT (mode
,
7735 make_compound_operation
7736 (XEXP (XEXP (x
, 0), 0), next_code
),
7737 XEXP (XEXP (x
, 0), 1)));
7740 /* If the constant is one less than a power of two, this might be
7741 representable by an extraction even if no shift is present.
7742 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7743 we are in a COMPARE. */
7744 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7745 new_rtx
= make_extraction (mode
,
7746 make_compound_operation (XEXP (x
, 0),
7748 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7750 /* If we are in a comparison and this is an AND with a power of two,
7751 convert this into the appropriate bit extract. */
7752 else if (in_code
== COMPARE
7753 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7754 new_rtx
= make_extraction (mode
,
7755 make_compound_operation (XEXP (x
, 0),
7757 i
, NULL_RTX
, 1, 1, 0, 1);
7762 /* If the sign bit is known to be zero, replace this with an
7763 arithmetic shift. */
7764 if (have_insn_for (ASHIFTRT
, mode
)
7765 && ! have_insn_for (LSHIFTRT
, mode
)
7766 && mode_width
<= HOST_BITS_PER_WIDE_INT
7767 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7769 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7770 make_compound_operation (XEXP (x
, 0),
7776 /* ... fall through ... */
7782 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7783 this is a SIGN_EXTRACT. */
7784 if (CONST_INT_P (rhs
)
7785 && GET_CODE (lhs
) == ASHIFT
7786 && CONST_INT_P (XEXP (lhs
, 1))
7787 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7788 && INTVAL (rhs
) < mode_width
)
7790 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7791 new_rtx
= make_extraction (mode
, new_rtx
,
7792 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7793 NULL_RTX
, mode_width
- INTVAL (rhs
),
7794 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7798 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7799 If so, try to merge the shifts into a SIGN_EXTEND. We could
7800 also do this for some cases of SIGN_EXTRACT, but it doesn't
7801 seem worth the effort; the case checked for occurs on Alpha. */
7804 && ! (GET_CODE (lhs
) == SUBREG
7805 && (OBJECT_P (SUBREG_REG (lhs
))))
7806 && CONST_INT_P (rhs
)
7807 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7808 && INTVAL (rhs
) < mode_width
7809 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7810 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7811 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7812 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7817 /* Call ourselves recursively on the inner expression. If we are
7818 narrowing the object and it has a different RTL code from
7819 what it originally did, do this SUBREG as a force_to_mode. */
7821 rtx inner
= SUBREG_REG (x
), simplified
;
7823 tem
= make_compound_operation (inner
, in_code
);
7826 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7830 if (GET_CODE (tem
) != GET_CODE (inner
)
7831 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7832 && subreg_lowpart_p (x
))
7835 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7837 /* If we have something other than a SUBREG, we might have
7838 done an expansion, so rerun ourselves. */
7839 if (GET_CODE (newer
) != SUBREG
)
7840 newer
= make_compound_operation (newer
, in_code
);
7842 /* force_to_mode can expand compounds. If it just re-expanded the
7843 compound, use gen_lowpart to convert to the desired mode. */
7844 if (rtx_equal_p (newer
, x
)
7845 /* Likewise if it re-expanded the compound only partially.
7846 This happens for SUBREG of ZERO_EXTRACT if they extract
7847 the same number of bits. */
7848 || (GET_CODE (newer
) == SUBREG
7849 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7850 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7851 && GET_CODE (inner
) == AND
7852 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7853 return gen_lowpart (GET_MODE (x
), tem
);
7869 x
= gen_lowpart (mode
, new_rtx
);
7870 code
= GET_CODE (x
);
7873 /* Now recursively process each operand of this operation. We need to
7874 handle ZERO_EXTEND specially so that we don't lose track of the
7876 if (GET_CODE (x
) == ZERO_EXTEND
)
7878 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7879 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7880 new_rtx
, GET_MODE (XEXP (x
, 0)));
7883 SUBST (XEXP (x
, 0), new_rtx
);
7887 fmt
= GET_RTX_FORMAT (code
);
7888 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7891 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7892 SUBST (XEXP (x
, i
), new_rtx
);
7894 else if (fmt
[i
] == 'E')
7895 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7897 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7898 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7902 /* If this is a commutative operation, the changes to the operands
7903 may have made it noncanonical. */
7904 if (COMMUTATIVE_ARITH_P (x
)
7905 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7908 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7909 SUBST (XEXP (x
, 1), tem
);
7915 /* Given M see if it is a value that would select a field of bits
7916 within an item, but not the entire word. Return -1 if not.
7917 Otherwise, return the starting position of the field, where 0 is the
7920 *PLEN is set to the length of the field. */
7923 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7925 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7926 int pos
= m
? ctz_hwi (m
) : -1;
7930 /* Now shift off the low-order zero bits and see if we have a
7931 power of two minus 1. */
7932 len
= exact_log2 ((m
>> pos
) + 1);
7941 /* If X refers to a register that equals REG in value, replace these
7942 references with REG. */
7944 canon_reg_for_combine (rtx x
, rtx reg
)
7951 enum rtx_code code
= GET_CODE (x
);
7952 switch (GET_RTX_CLASS (code
))
7955 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7956 if (op0
!= XEXP (x
, 0))
7957 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7962 case RTX_COMM_ARITH
:
7963 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7964 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7965 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7966 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7970 case RTX_COMM_COMPARE
:
7971 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7972 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7973 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7974 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7975 GET_MODE (op0
), op0
, op1
);
7979 case RTX_BITFIELD_OPS
:
7980 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7981 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7982 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7983 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7984 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7985 GET_MODE (op0
), op0
, op1
, op2
);
7990 if (rtx_equal_p (get_last_value (reg
), x
)
7991 || rtx_equal_p (reg
, get_last_value (x
)))
8000 fmt
= GET_RTX_FORMAT (code
);
8002 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8005 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8006 if (op
!= XEXP (x
, i
))
8016 else if (fmt
[i
] == 'E')
8019 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8021 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8022 if (op
!= XVECEXP (x
, i
, j
))
8029 XVECEXP (x
, i
, j
) = op
;
8040 /* Return X converted to MODE. If the value is already truncated to
8041 MODE we can just return a subreg even though in the general case we
8042 would need an explicit truncation. */
8045 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
8047 if (!CONST_INT_P (x
)
8048 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8049 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8050 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8052 /* Bit-cast X into an integer mode. */
8053 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8054 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8055 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8059 return gen_lowpart (mode
, x
);
8062 /* See if X can be simplified knowing that we will only refer to it in
8063 MODE and will only refer to those bits that are nonzero in MASK.
8064 If other bits are being computed or if masking operations are done
8065 that select a superset of the bits in MASK, they can sometimes be
8068 Return a possibly simplified expression, but always convert X to
8069 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8071 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8072 are all off in X. This is used when X will be complemented, by either
8073 NOT, NEG, or XOR. */
8076 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8079 enum rtx_code code
= GET_CODE (x
);
8080 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8081 enum machine_mode op_mode
;
8082 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8085 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8086 code below will do the wrong thing since the mode of such an
8087 expression is VOIDmode.
8089 Also do nothing if X is a CLOBBER; this can happen if X was
8090 the return value from a call to gen_lowpart. */
8091 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8094 /* We want to perform the operation is its present mode unless we know
8095 that the operation is valid in MODE, in which case we do the operation
8097 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8098 && have_insn_for (code
, mode
))
8099 ? mode
: GET_MODE (x
));
8101 /* It is not valid to do a right-shift in a narrower mode
8102 than the one it came in with. */
8103 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8104 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8105 op_mode
= GET_MODE (x
);
8107 /* Truncate MASK to fit OP_MODE. */
8109 mask
&= GET_MODE_MASK (op_mode
);
8111 /* When we have an arithmetic operation, or a shift whose count we
8112 do not know, we need to assume that all bits up to the highest-order
8113 bit in MASK will be needed. This is how we form such a mask. */
8114 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8115 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8117 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8120 /* Determine what bits of X are guaranteed to be (non)zero. */
8121 nonzero
= nonzero_bits (x
, mode
);
8123 /* If none of the bits in X are needed, return a zero. */
8124 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8127 /* If X is a CONST_INT, return a new one. Do this here since the
8128 test below will fail. */
8129 if (CONST_INT_P (x
))
8131 if (SCALAR_INT_MODE_P (mode
))
8132 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8135 x
= GEN_INT (INTVAL (x
) & mask
);
8136 return gen_lowpart_common (mode
, x
);
8140 /* If X is narrower than MODE and we want all the bits in X's mode, just
8141 get X in the proper mode. */
8142 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8143 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8144 return gen_lowpart (mode
, x
);
8146 /* We can ignore the effect of a SUBREG if it narrows the mode or
8147 if the constant masks to zero all the bits the mode doesn't have. */
8148 if (GET_CODE (x
) == SUBREG
8149 && subreg_lowpart_p (x
)
8150 && ((GET_MODE_SIZE (GET_MODE (x
))
8151 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8153 & GET_MODE_MASK (GET_MODE (x
))
8154 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8155 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8157 /* The arithmetic simplifications here only work for scalar integer modes. */
8158 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8159 return gen_lowpart_or_truncate (mode
, x
);
8164 /* If X is a (clobber (const_int)), return it since we know we are
8165 generating something that won't match. */
8172 x
= expand_compound_operation (x
);
8173 if (GET_CODE (x
) != code
)
8174 return force_to_mode (x
, mode
, mask
, next_select
);
8178 /* Similarly for a truncate. */
8179 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8182 /* If this is an AND with a constant, convert it into an AND
8183 whose constant is the AND of that constant with MASK. If it
8184 remains an AND of MASK, delete it since it is redundant. */
8186 if (CONST_INT_P (XEXP (x
, 1)))
8188 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8189 mask
& INTVAL (XEXP (x
, 1)));
8191 /* If X is still an AND, see if it is an AND with a mask that
8192 is just some low-order bits. If so, and it is MASK, we don't
8195 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8196 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8200 /* If it remains an AND, try making another AND with the bits
8201 in the mode mask that aren't in MASK turned on. If the
8202 constant in the AND is wide enough, this might make a
8203 cheaper constant. */
8205 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8206 && GET_MODE_MASK (GET_MODE (x
)) != mask
8207 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8209 unsigned HOST_WIDE_INT cval
8210 = UINTVAL (XEXP (x
, 1))
8211 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8212 int width
= GET_MODE_PRECISION (GET_MODE (x
));
8215 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8216 number, sign extend it. */
8217 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8218 && (cval
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8219 cval
|= (unsigned HOST_WIDE_INT
) -1 << width
;
8221 y
= simplify_gen_binary (AND
, GET_MODE (x
),
8222 XEXP (x
, 0), GEN_INT (cval
));
8223 if (rtx_cost (y
, SET
, optimize_this_for_speed_p
)
8224 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
8234 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8235 low-order bits (as in an alignment operation) and FOO is already
8236 aligned to that boundary, mask C1 to that boundary as well.
8237 This may eliminate that PLUS and, later, the AND. */
8240 unsigned int width
= GET_MODE_PRECISION (mode
);
8241 unsigned HOST_WIDE_INT smask
= mask
;
8243 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8244 number, sign extend it. */
8246 if (width
< HOST_BITS_PER_WIDE_INT
8247 && (smask
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8248 smask
|= (unsigned HOST_WIDE_INT
) (-1) << width
;
8250 if (CONST_INT_P (XEXP (x
, 1))
8251 && exact_log2 (- smask
) >= 0
8252 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8253 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8254 return force_to_mode (plus_constant (XEXP (x
, 0),
8255 (INTVAL (XEXP (x
, 1)) & smask
)),
8256 mode
, smask
, next_select
);
8259 /* ... fall through ... */
8262 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8263 most significant bit in MASK since carries from those bits will
8264 affect the bits we are interested in. */
8269 /* If X is (minus C Y) where C's least set bit is larger than any bit
8270 in the mask, then we may replace with (neg Y). */
8271 if (CONST_INT_P (XEXP (x
, 0))
8272 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8273 & -INTVAL (XEXP (x
, 0))))
8276 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8278 return force_to_mode (x
, mode
, mask
, next_select
);
8281 /* Similarly, if C contains every bit in the fuller_mask, then we may
8282 replace with (not Y). */
8283 if (CONST_INT_P (XEXP (x
, 0))
8284 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8286 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8287 XEXP (x
, 1), GET_MODE (x
));
8288 return force_to_mode (x
, mode
, mask
, next_select
);
8296 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8297 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8298 operation which may be a bitfield extraction. Ensure that the
8299 constant we form is not wider than the mode of X. */
8301 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8302 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8303 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8304 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8305 && CONST_INT_P (XEXP (x
, 1))
8306 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8307 + floor_log2 (INTVAL (XEXP (x
, 1))))
8308 < GET_MODE_PRECISION (GET_MODE (x
)))
8309 && (UINTVAL (XEXP (x
, 1))
8310 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8312 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
8313 << INTVAL (XEXP (XEXP (x
, 0), 1)));
8314 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8315 XEXP (XEXP (x
, 0), 0), temp
);
8316 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8317 XEXP (XEXP (x
, 0), 1));
8318 return force_to_mode (x
, mode
, mask
, next_select
);
8322 /* For most binary operations, just propagate into the operation and
8323 change the mode if we have an operation of that mode. */
8325 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8326 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8328 /* If we ended up truncating both operands, truncate the result of the
8329 operation instead. */
8330 if (GET_CODE (op0
) == TRUNCATE
8331 && GET_CODE (op1
) == TRUNCATE
)
8333 op0
= XEXP (op0
, 0);
8334 op1
= XEXP (op1
, 0);
8337 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8338 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8340 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8341 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8345 /* For left shifts, do the same, but just for the first operand.
8346 However, we cannot do anything with shifts where we cannot
8347 guarantee that the counts are smaller than the size of the mode
8348 because such a count will have a different meaning in a
8351 if (! (CONST_INT_P (XEXP (x
, 1))
8352 && INTVAL (XEXP (x
, 1)) >= 0
8353 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8354 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8355 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8356 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8359 /* If the shift count is a constant and we can do arithmetic in
8360 the mode of the shift, refine which bits we need. Otherwise, use the
8361 conservative form of the mask. */
8362 if (CONST_INT_P (XEXP (x
, 1))
8363 && INTVAL (XEXP (x
, 1)) >= 0
8364 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8365 && HWI_COMPUTABLE_MODE_P (op_mode
))
8366 mask
>>= INTVAL (XEXP (x
, 1));
8370 op0
= gen_lowpart_or_truncate (op_mode
,
8371 force_to_mode (XEXP (x
, 0), op_mode
,
8372 mask
, next_select
));
8374 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8375 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8379 /* Here we can only do something if the shift count is a constant,
8380 this shift constant is valid for the host, and we can do arithmetic
8383 if (CONST_INT_P (XEXP (x
, 1))
8384 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8385 && HWI_COMPUTABLE_MODE_P (op_mode
))
8387 rtx inner
= XEXP (x
, 0);
8388 unsigned HOST_WIDE_INT inner_mask
;
8390 /* Select the mask of the bits we need for the shift operand. */
8391 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8393 /* We can only change the mode of the shift if we can do arithmetic
8394 in the mode of the shift and INNER_MASK is no wider than the
8395 width of X's mode. */
8396 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8397 op_mode
= GET_MODE (x
);
8399 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8401 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8402 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8405 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8406 shift and AND produces only copies of the sign bit (C2 is one less
8407 than a power of two), we can do this with just a shift. */
8409 if (GET_CODE (x
) == LSHIFTRT
8410 && CONST_INT_P (XEXP (x
, 1))
8411 /* The shift puts one of the sign bit copies in the least significant
8413 && ((INTVAL (XEXP (x
, 1))
8414 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8415 >= GET_MODE_PRECISION (GET_MODE (x
)))
8416 && exact_log2 (mask
+ 1) >= 0
8417 /* Number of bits left after the shift must be more than the mask
8419 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8420 <= GET_MODE_PRECISION (GET_MODE (x
)))
8421 /* Must be more sign bit copies than the mask needs. */
8422 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8423 >= exact_log2 (mask
+ 1)))
8424 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8425 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8426 - exact_log2 (mask
+ 1)));
8431 /* If we are just looking for the sign bit, we don't need this shift at
8432 all, even if it has a variable count. */
8433 if (val_signbit_p (GET_MODE (x
), mask
))
8434 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8436 /* If this is a shift by a constant, get a mask that contains those bits
8437 that are not copies of the sign bit. We then have two cases: If
8438 MASK only includes those bits, this can be a logical shift, which may
8439 allow simplifications. If MASK is a single-bit field not within
8440 those bits, we are requesting a copy of the sign bit and hence can
8441 shift the sign bit to the appropriate location. */
8443 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8444 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8448 /* If the considered data is wider than HOST_WIDE_INT, we can't
8449 represent a mask for all its bits in a single scalar.
8450 But we only care about the lower bits, so calculate these. */
8452 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8454 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8456 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8457 is the number of bits a full-width mask would have set.
8458 We need only shift if these are fewer than nonzero can
8459 hold. If not, we must keep all bits set in nonzero. */
8461 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8462 < HOST_BITS_PER_WIDE_INT
)
8463 nonzero
>>= INTVAL (XEXP (x
, 1))
8464 + HOST_BITS_PER_WIDE_INT
8465 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8469 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8470 nonzero
>>= INTVAL (XEXP (x
, 1));
8473 if ((mask
& ~nonzero
) == 0)
8475 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8476 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8477 if (GET_CODE (x
) != ASHIFTRT
)
8478 return force_to_mode (x
, mode
, mask
, next_select
);
8481 else if ((i
= exact_log2 (mask
)) >= 0)
8483 x
= simplify_shift_const
8484 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8485 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8487 if (GET_CODE (x
) != ASHIFTRT
)
8488 return force_to_mode (x
, mode
, mask
, next_select
);
8492 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8493 even if the shift count isn't a constant. */
8495 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8496 XEXP (x
, 0), XEXP (x
, 1));
8500 /* If this is a zero- or sign-extension operation that just affects bits
8501 we don't care about, remove it. Be sure the call above returned
8502 something that is still a shift. */
8504 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8505 && CONST_INT_P (XEXP (x
, 1))
8506 && INTVAL (XEXP (x
, 1)) >= 0
8507 && (INTVAL (XEXP (x
, 1))
8508 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8509 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8510 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8511 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8518 /* If the shift count is constant and we can do computations
8519 in the mode of X, compute where the bits we care about are.
8520 Otherwise, we can't do anything. Don't change the mode of
8521 the shift or propagate MODE into the shift, though. */
8522 if (CONST_INT_P (XEXP (x
, 1))
8523 && INTVAL (XEXP (x
, 1)) >= 0)
8525 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8526 GET_MODE (x
), GEN_INT (mask
),
8528 if (temp
&& CONST_INT_P (temp
))
8530 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8531 INTVAL (temp
), next_select
));
8536 /* If we just want the low-order bit, the NEG isn't needed since it
8537 won't change the low-order bit. */
8539 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8541 /* We need any bits less significant than the most significant bit in
8542 MASK since carries from those bits will affect the bits we are
8548 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8549 same as the XOR case above. Ensure that the constant we form is not
8550 wider than the mode of X. */
8552 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8553 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8554 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8555 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8556 < GET_MODE_PRECISION (GET_MODE (x
)))
8557 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8559 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8561 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8562 XEXP (XEXP (x
, 0), 0), temp
);
8563 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8564 temp
, XEXP (XEXP (x
, 0), 1));
8566 return force_to_mode (x
, mode
, mask
, next_select
);
8569 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8570 use the full mask inside the NOT. */
8574 op0
= gen_lowpart_or_truncate (op_mode
,
8575 force_to_mode (XEXP (x
, 0), mode
, mask
,
8577 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8578 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8582 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8583 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8584 which is equal to STORE_FLAG_VALUE. */
8585 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8586 && XEXP (x
, 1) == const0_rtx
8587 && GET_MODE (XEXP (x
, 0)) == mode
8588 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8589 && (nonzero_bits (XEXP (x
, 0), mode
)
8590 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8591 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8596 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8597 written in a narrower mode. We play it safe and do not do so. */
8600 gen_lowpart_or_truncate (GET_MODE (x
),
8601 force_to_mode (XEXP (x
, 1), mode
,
8602 mask
, next_select
)));
8604 gen_lowpart_or_truncate (GET_MODE (x
),
8605 force_to_mode (XEXP (x
, 2), mode
,
8606 mask
, next_select
)));
8613 /* Ensure we return a value of the proper mode. */
8614 return gen_lowpart_or_truncate (mode
, x
);
8617 /* Return nonzero if X is an expression that has one of two values depending on
8618 whether some other value is zero or nonzero. In that case, we return the
8619 value that is being tested, *PTRUE is set to the value if the rtx being
8620 returned has a nonzero value, and *PFALSE is set to the other alternative.
8622 If we return zero, we set *PTRUE and *PFALSE to X. */
8625 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8627 enum machine_mode mode
= GET_MODE (x
);
8628 enum rtx_code code
= GET_CODE (x
);
8629 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8630 unsigned HOST_WIDE_INT nz
;
8632 /* If we are comparing a value against zero, we are done. */
8633 if ((code
== NE
|| code
== EQ
)
8634 && XEXP (x
, 1) == const0_rtx
)
8636 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8637 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8641 /* If this is a unary operation whose operand has one of two values, apply
8642 our opcode to compute those values. */
8643 else if (UNARY_P (x
)
8644 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8646 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8647 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8648 GET_MODE (XEXP (x
, 0)));
8652 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8653 make can't possibly match and would suppress other optimizations. */
8654 else if (code
== COMPARE
)
8657 /* If this is a binary operation, see if either side has only one of two
8658 values. If either one does or if both do and they are conditional on
8659 the same value, compute the new true and false values. */
8660 else if (BINARY_P (x
))
8662 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8663 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8665 if ((cond0
!= 0 || cond1
!= 0)
8666 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8668 /* If if_then_else_cond returned zero, then true/false are the
8669 same rtl. We must copy one of them to prevent invalid rtl
8672 true0
= copy_rtx (true0
);
8673 else if (cond1
== 0)
8674 true1
= copy_rtx (true1
);
8676 if (COMPARISON_P (x
))
8678 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8680 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8685 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8686 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8689 return cond0
? cond0
: cond1
;
8692 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8693 operands is zero when the other is nonzero, and vice-versa,
8694 and STORE_FLAG_VALUE is 1 or -1. */
8696 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8697 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8699 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8701 rtx op0
= XEXP (XEXP (x
, 0), 1);
8702 rtx op1
= XEXP (XEXP (x
, 1), 1);
8704 cond0
= XEXP (XEXP (x
, 0), 0);
8705 cond1
= XEXP (XEXP (x
, 1), 0);
8707 if (COMPARISON_P (cond0
)
8708 && COMPARISON_P (cond1
)
8709 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8710 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8711 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8712 || ((swap_condition (GET_CODE (cond0
))
8713 == reversed_comparison_code (cond1
, NULL
))
8714 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8715 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8716 && ! side_effects_p (x
))
8718 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8719 *pfalse
= simplify_gen_binary (MULT
, mode
,
8721 ? simplify_gen_unary (NEG
, mode
,
8729 /* Similarly for MULT, AND and UMIN, except that for these the result
8731 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8732 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8733 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8735 cond0
= XEXP (XEXP (x
, 0), 0);
8736 cond1
= XEXP (XEXP (x
, 1), 0);
8738 if (COMPARISON_P (cond0
)
8739 && COMPARISON_P (cond1
)
8740 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8741 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8742 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8743 || ((swap_condition (GET_CODE (cond0
))
8744 == reversed_comparison_code (cond1
, NULL
))
8745 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8746 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8747 && ! side_effects_p (x
))
8749 *ptrue
= *pfalse
= const0_rtx
;
8755 else if (code
== IF_THEN_ELSE
)
8757 /* If we have IF_THEN_ELSE already, extract the condition and
8758 canonicalize it if it is NE or EQ. */
8759 cond0
= XEXP (x
, 0);
8760 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8761 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8762 return XEXP (cond0
, 0);
8763 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8765 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8766 return XEXP (cond0
, 0);
8772 /* If X is a SUBREG, we can narrow both the true and false values
8773 if the inner expression, if there is a condition. */
8774 else if (code
== SUBREG
8775 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8778 true0
= simplify_gen_subreg (mode
, true0
,
8779 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8780 false0
= simplify_gen_subreg (mode
, false0
,
8781 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8782 if (true0
&& false0
)
8790 /* If X is a constant, this isn't special and will cause confusions
8791 if we treat it as such. Likewise if it is equivalent to a constant. */
8792 else if (CONSTANT_P (x
)
8793 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8796 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8797 will be least confusing to the rest of the compiler. */
8798 else if (mode
== BImode
)
8800 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8804 /* If X is known to be either 0 or -1, those are the true and
8805 false values when testing X. */
8806 else if (x
== constm1_rtx
|| x
== const0_rtx
8807 || (mode
!= VOIDmode
8808 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8810 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8814 /* Likewise for 0 or a single bit. */
8815 else if (HWI_COMPUTABLE_MODE_P (mode
)
8816 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8818 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8822 /* Otherwise fail; show no condition with true and false values the same. */
8823 *ptrue
= *pfalse
= x
;
8827 /* Return the value of expression X given the fact that condition COND
8828 is known to be true when applied to REG as its first operand and VAL
8829 as its second. X is known to not be shared and so can be modified in
8832 We only handle the simplest cases, and specifically those cases that
8833 arise with IF_THEN_ELSE expressions. */
8836 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8838 enum rtx_code code
= GET_CODE (x
);
8843 if (side_effects_p (x
))
8846 /* If either operand of the condition is a floating point value,
8847 then we have to avoid collapsing an EQ comparison. */
8849 && rtx_equal_p (x
, reg
)
8850 && ! FLOAT_MODE_P (GET_MODE (x
))
8851 && ! FLOAT_MODE_P (GET_MODE (val
)))
8854 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8857 /* If X is (abs REG) and we know something about REG's relationship
8858 with zero, we may be able to simplify this. */
8860 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8863 case GE
: case GT
: case EQ
:
8866 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8868 GET_MODE (XEXP (x
, 0)));
8873 /* The only other cases we handle are MIN, MAX, and comparisons if the
8874 operands are the same as REG and VAL. */
8876 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8878 if (rtx_equal_p (XEXP (x
, 0), val
))
8879 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8881 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8883 if (COMPARISON_P (x
))
8885 if (comparison_dominates_p (cond
, code
))
8886 return const_true_rtx
;
8888 code
= reversed_comparison_code (x
, NULL
);
8890 && comparison_dominates_p (cond
, code
))
8895 else if (code
== SMAX
|| code
== SMIN
8896 || code
== UMIN
|| code
== UMAX
)
8898 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8900 /* Do not reverse the condition when it is NE or EQ.
8901 This is because we cannot conclude anything about
8902 the value of 'SMAX (x, y)' when x is not equal to y,
8903 but we can when x equals y. */
8904 if ((code
== SMAX
|| code
== UMAX
)
8905 && ! (cond
== EQ
|| cond
== NE
))
8906 cond
= reverse_condition (cond
);
8911 return unsignedp
? x
: XEXP (x
, 1);
8913 return unsignedp
? x
: XEXP (x
, 0);
8915 return unsignedp
? XEXP (x
, 1) : x
;
8917 return unsignedp
? XEXP (x
, 0) : x
;
8924 else if (code
== SUBREG
)
8926 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8927 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8929 if (SUBREG_REG (x
) != r
)
8931 /* We must simplify subreg here, before we lose track of the
8932 original inner_mode. */
8933 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8934 inner_mode
, SUBREG_BYTE (x
));
8938 SUBST (SUBREG_REG (x
), r
);
8943 /* We don't have to handle SIGN_EXTEND here, because even in the
8944 case of replacing something with a modeless CONST_INT, a
8945 CONST_INT is already (supposed to be) a valid sign extension for
8946 its narrower mode, which implies it's already properly
8947 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8948 story is different. */
8949 else if (code
== ZERO_EXTEND
)
8951 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8952 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8954 if (XEXP (x
, 0) != r
)
8956 /* We must simplify the zero_extend here, before we lose
8957 track of the original inner_mode. */
8958 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8963 SUBST (XEXP (x
, 0), r
);
8969 fmt
= GET_RTX_FORMAT (code
);
8970 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8973 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8974 else if (fmt
[i
] == 'E')
8975 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8976 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8983 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8984 assignment as a field assignment. */
8987 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8989 if (x
== y
|| rtx_equal_p (x
, y
))
8992 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8995 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8996 Note that all SUBREGs of MEM are paradoxical; otherwise they
8997 would have been rewritten. */
8998 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8999 && MEM_P (SUBREG_REG (y
))
9000 && rtx_equal_p (SUBREG_REG (y
),
9001 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9004 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9005 && MEM_P (SUBREG_REG (x
))
9006 && rtx_equal_p (SUBREG_REG (x
),
9007 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9010 /* We used to see if get_last_value of X and Y were the same but that's
9011 not correct. In one direction, we'll cause the assignment to have
9012 the wrong destination and in the case, we'll import a register into this
9013 insn that might have already have been dead. So fail if none of the
9014 above cases are true. */
9018 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9019 Return that assignment if so.
9021 We only handle the most common cases. */
9024 make_field_assignment (rtx x
)
9026 rtx dest
= SET_DEST (x
);
9027 rtx src
= SET_SRC (x
);
9032 unsigned HOST_WIDE_INT len
;
9034 enum machine_mode mode
;
9036 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9037 a clear of a one-bit field. We will have changed it to
9038 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9041 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9042 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9043 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9044 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9046 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9049 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9053 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9054 && subreg_lowpart_p (XEXP (src
, 0))
9055 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9056 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9057 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9058 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9059 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9060 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9062 assign
= make_extraction (VOIDmode
, dest
, 0,
9063 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9066 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9070 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9072 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9073 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9074 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9076 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9079 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9083 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9084 SRC is an AND with all bits of that field set, then we can discard
9086 if (GET_CODE (dest
) == ZERO_EXTRACT
9087 && CONST_INT_P (XEXP (dest
, 1))
9088 && GET_CODE (src
) == AND
9089 && CONST_INT_P (XEXP (src
, 1)))
9091 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9092 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9093 unsigned HOST_WIDE_INT ze_mask
;
9095 if (width
>= HOST_BITS_PER_WIDE_INT
)
9098 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9100 /* Complete overlap. We can remove the source AND. */
9101 if ((and_mask
& ze_mask
) == ze_mask
)
9102 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9104 /* Partial overlap. We can reduce the source AND. */
9105 if ((and_mask
& ze_mask
) != and_mask
)
9107 mode
= GET_MODE (src
);
9108 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9109 gen_int_mode (and_mask
& ze_mask
, mode
));
9110 return gen_rtx_SET (VOIDmode
, dest
, src
);
9114 /* The other case we handle is assignments into a constant-position
9115 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9116 a mask that has all one bits except for a group of zero bits and
9117 OTHER is known to have zeros where C1 has ones, this is such an
9118 assignment. Compute the position and length from C1. Shift OTHER
9119 to the appropriate position, force it to the required mode, and
9120 make the extraction. Check for the AND in both operands. */
9122 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9125 rhs
= expand_compound_operation (XEXP (src
, 0));
9126 lhs
= expand_compound_operation (XEXP (src
, 1));
9128 if (GET_CODE (rhs
) == AND
9129 && CONST_INT_P (XEXP (rhs
, 1))
9130 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9131 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9132 else if (GET_CODE (lhs
) == AND
9133 && CONST_INT_P (XEXP (lhs
, 1))
9134 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9135 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9139 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9140 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9141 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9142 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9145 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9149 /* The mode to use for the source is the mode of the assignment, or of
9150 what is inside a possible STRICT_LOW_PART. */
9151 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9152 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9154 /* Shift OTHER right POS places and make it the source, restricting it
9155 to the proper length and mode. */
9157 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9161 src
= force_to_mode (src
, mode
,
9162 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9163 ? ~(unsigned HOST_WIDE_INT
) 0
9164 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9167 /* If SRC is masked by an AND that does not make a difference in
9168 the value being stored, strip it. */
9169 if (GET_CODE (assign
) == ZERO_EXTRACT
9170 && CONST_INT_P (XEXP (assign
, 1))
9171 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9172 && GET_CODE (src
) == AND
9173 && CONST_INT_P (XEXP (src
, 1))
9174 && UINTVAL (XEXP (src
, 1))
9175 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9176 src
= XEXP (src
, 0);
9178 return gen_rtx_SET (VOIDmode
, assign
, src
);
9181 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9185 apply_distributive_law (rtx x
)
9187 enum rtx_code code
= GET_CODE (x
);
9188 enum rtx_code inner_code
;
9189 rtx lhs
, rhs
, other
;
9192 /* Distributivity is not true for floating point as it can change the
9193 value. So we don't do it unless -funsafe-math-optimizations. */
9194 if (FLOAT_MODE_P (GET_MODE (x
))
9195 && ! flag_unsafe_math_optimizations
)
9198 /* The outer operation can only be one of the following: */
9199 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9200 && code
!= PLUS
&& code
!= MINUS
)
9206 /* If either operand is a primitive we can't do anything, so get out
9208 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9211 lhs
= expand_compound_operation (lhs
);
9212 rhs
= expand_compound_operation (rhs
);
9213 inner_code
= GET_CODE (lhs
);
9214 if (inner_code
!= GET_CODE (rhs
))
9217 /* See if the inner and outer operations distribute. */
9224 /* These all distribute except over PLUS. */
9225 if (code
== PLUS
|| code
== MINUS
)
9230 if (code
!= PLUS
&& code
!= MINUS
)
9235 /* This is also a multiply, so it distributes over everything. */
9239 /* Non-paradoxical SUBREGs distributes over all operations,
9240 provided the inner modes and byte offsets are the same, this
9241 is an extraction of a low-order part, we don't convert an fp
9242 operation to int or vice versa, this is not a vector mode,
9243 and we would not be converting a single-word operation into a
9244 multi-word operation. The latter test is not required, but
9245 it prevents generating unneeded multi-word operations. Some
9246 of the previous tests are redundant given the latter test,
9247 but are retained because they are required for correctness.
9249 We produce the result slightly differently in this case. */
9251 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
9252 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
9253 || ! subreg_lowpart_p (lhs
)
9254 || (GET_MODE_CLASS (GET_MODE (lhs
))
9255 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
9256 || paradoxical_subreg_p (lhs
)
9257 || VECTOR_MODE_P (GET_MODE (lhs
))
9258 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
9259 /* Result might need to be truncated. Don't change mode if
9260 explicit truncation is needed. */
9261 || !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (x
),
9262 GET_MODE (SUBREG_REG (lhs
))))
9265 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
9266 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
9267 return gen_lowpart (GET_MODE (x
), tem
);
9273 /* Set LHS and RHS to the inner operands (A and B in the example
9274 above) and set OTHER to the common operand (C in the example).
9275 There is only one way to do this unless the inner operation is
9277 if (COMMUTATIVE_ARITH_P (lhs
)
9278 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9279 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9280 else if (COMMUTATIVE_ARITH_P (lhs
)
9281 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9282 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9283 else if (COMMUTATIVE_ARITH_P (lhs
)
9284 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9285 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9286 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9287 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9291 /* Form the new inner operation, seeing if it simplifies first. */
9292 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9294 /* There is one exception to the general way of distributing:
9295 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9296 if (code
== XOR
&& inner_code
== IOR
)
9299 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9302 /* We may be able to continuing distributing the result, so call
9303 ourselves recursively on the inner operation before forming the
9304 outer operation, which we return. */
9305 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9306 apply_distributive_law (tem
), other
);
9309 /* See if X is of the form (* (+ A B) C), and if so convert to
9310 (+ (* A C) (* B C)) and try to simplify.
9312 Most of the time, this results in no change. However, if some of
9313 the operands are the same or inverses of each other, simplifications
9316 For example, (and (ior A B) (not B)) can occur as the result of
9317 expanding a bit field assignment. When we apply the distributive
9318 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9319 which then simplifies to (and (A (not B))).
9321 Note that no checks happen on the validity of applying the inverse
9322 distributive law. This is pointless since we can do it in the
9323 few places where this routine is called.
9325 N is the index of the term that is decomposed (the arithmetic operation,
9326 i.e. (+ A B) in the first example above). !N is the index of the term that
9327 is distributed, i.e. of C in the first example above. */
9329 distribute_and_simplify_rtx (rtx x
, int n
)
9331 enum machine_mode mode
;
9332 enum rtx_code outer_code
, inner_code
;
9333 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9335 /* Distributivity is not true for floating point as it can change the
9336 value. So we don't do it unless -funsafe-math-optimizations. */
9337 if (FLOAT_MODE_P (GET_MODE (x
))
9338 && ! flag_unsafe_math_optimizations
)
9341 decomposed
= XEXP (x
, n
);
9342 if (!ARITHMETIC_P (decomposed
))
9345 mode
= GET_MODE (x
);
9346 outer_code
= GET_CODE (x
);
9347 distributed
= XEXP (x
, !n
);
9349 inner_code
= GET_CODE (decomposed
);
9350 inner_op0
= XEXP (decomposed
, 0);
9351 inner_op1
= XEXP (decomposed
, 1);
9353 /* Special case (and (xor B C) (not A)), which is equivalent to
9354 (xor (ior A B) (ior A C)) */
9355 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9357 distributed
= XEXP (distributed
, 0);
9363 /* Distribute the second term. */
9364 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9365 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9369 /* Distribute the first term. */
9370 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9371 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9374 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9376 if (GET_CODE (tmp
) != outer_code
9377 && rtx_cost (tmp
, SET
, optimize_this_for_speed_p
)
9378 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
9384 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9385 in MODE. Return an equivalent form, if different from (and VAROP
9386 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9389 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9390 unsigned HOST_WIDE_INT constop
)
9392 unsigned HOST_WIDE_INT nonzero
;
9393 unsigned HOST_WIDE_INT orig_constop
;
9398 orig_constop
= constop
;
9399 if (GET_CODE (varop
) == CLOBBER
)
9402 /* Simplify VAROP knowing that we will be only looking at some of the
9405 Note by passing in CONSTOP, we guarantee that the bits not set in
9406 CONSTOP are not significant and will never be examined. We must
9407 ensure that is the case by explicitly masking out those bits
9408 before returning. */
9409 varop
= force_to_mode (varop
, mode
, constop
, 0);
9411 /* If VAROP is a CLOBBER, we will fail so return it. */
9412 if (GET_CODE (varop
) == CLOBBER
)
9415 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9416 to VAROP and return the new constant. */
9417 if (CONST_INT_P (varop
))
9418 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9420 /* See what bits may be nonzero in VAROP. Unlike the general case of
9421 a call to nonzero_bits, here we don't care about bits outside
9424 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9426 /* Turn off all bits in the constant that are known to already be zero.
9427 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9428 which is tested below. */
9432 /* If we don't have any bits left, return zero. */
9436 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9437 a power of two, we can replace this with an ASHIFT. */
9438 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9439 && (i
= exact_log2 (constop
)) >= 0)
9440 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9442 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9443 or XOR, then try to apply the distributive law. This may eliminate
9444 operations if either branch can be simplified because of the AND.
9445 It may also make some cases more complex, but those cases probably
9446 won't match a pattern either with or without this. */
9448 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9452 apply_distributive_law
9453 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9454 simplify_and_const_int (NULL_RTX
,
9458 simplify_and_const_int (NULL_RTX
,
9463 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9464 the AND and see if one of the operands simplifies to zero. If so, we
9465 may eliminate it. */
9467 if (GET_CODE (varop
) == PLUS
9468 && exact_log2 (constop
+ 1) >= 0)
9472 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9473 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9474 if (o0
== const0_rtx
)
9476 if (o1
== const0_rtx
)
9480 /* Make a SUBREG if necessary. If we can't make it, fail. */
9481 varop
= gen_lowpart (mode
, varop
);
9482 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9485 /* If we are only masking insignificant bits, return VAROP. */
9486 if (constop
== nonzero
)
9489 if (varop
== orig_varop
&& constop
== orig_constop
)
9492 /* Otherwise, return an AND. */
9493 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9497 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9500 Return an equivalent form, if different from X. Otherwise, return X. If
9501 X is zero, we are to always construct the equivalent form. */
9504 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9505 unsigned HOST_WIDE_INT constop
)
9507 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9512 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9513 gen_int_mode (constop
, mode
));
9514 if (GET_MODE (x
) != mode
)
9515 x
= gen_lowpart (mode
, x
);
9519 /* Given a REG, X, compute which bits in X can be nonzero.
9520 We don't care about bits outside of those defined in MODE.
9522 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9523 a shift, AND, or zero_extract, we can do better. */
9526 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9527 const_rtx known_x ATTRIBUTE_UNUSED
,
9528 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9529 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9530 unsigned HOST_WIDE_INT
*nonzero
)
9535 /* If X is a register whose nonzero bits value is current, use it.
9536 Otherwise, if X is a register whose value we can find, use that
9537 value. Otherwise, use the previously-computed global nonzero bits
9538 for this register. */
9540 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9541 if (rsp
->last_set_value
!= 0
9542 && (rsp
->last_set_mode
== mode
9543 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9544 && GET_MODE_CLASS (mode
) == MODE_INT
))
9545 && ((rsp
->last_set_label
>= label_tick_ebb_start
9546 && rsp
->last_set_label
< label_tick
)
9547 || (rsp
->last_set_label
== label_tick
9548 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9549 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9550 && REG_N_SETS (REGNO (x
)) == 1
9552 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9554 *nonzero
&= rsp
->last_set_nonzero_bits
;
9558 tem
= get_last_value (x
);
9562 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9563 /* If X is narrower than MODE and TEM is a non-negative
9564 constant that would appear negative in the mode of X,
9565 sign-extend it for use in reg_nonzero_bits because some
9566 machines (maybe most) will actually do the sign-extension
9567 and this is the conservative approach.
9569 ??? For 2.5, try to tighten up the MD files in this regard
9570 instead of this kludge. */
9572 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9573 && CONST_INT_P (tem
)
9575 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9576 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9580 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9582 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9584 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9585 /* We don't know anything about the upper bits. */
9586 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9593 /* Return the number of bits at the high-order end of X that are known to
9594 be equal to the sign bit. X will be used in mode MODE; if MODE is
9595 VOIDmode, X will be used in its own mode. The returned value will always
9596 be between 1 and the number of bits in MODE. */
9599 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9600 const_rtx known_x ATTRIBUTE_UNUSED
,
9601 enum machine_mode known_mode
9603 unsigned int known_ret ATTRIBUTE_UNUSED
,
9604 unsigned int *result
)
9609 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9610 if (rsp
->last_set_value
!= 0
9611 && rsp
->last_set_mode
== mode
9612 && ((rsp
->last_set_label
>= label_tick_ebb_start
9613 && rsp
->last_set_label
< label_tick
)
9614 || (rsp
->last_set_label
== label_tick
9615 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9616 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9617 && REG_N_SETS (REGNO (x
)) == 1
9619 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9621 *result
= rsp
->last_set_sign_bit_copies
;
9625 tem
= get_last_value (x
);
9629 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9630 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9631 *result
= rsp
->sign_bit_copies
;
9636 /* Return the number of "extended" bits there are in X, when interpreted
9637 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9638 unsigned quantities, this is the number of high-order zero bits.
9639 For signed quantities, this is the number of copies of the sign bit
9640 minus 1. In both case, this function returns the number of "spare"
9641 bits. For example, if two quantities for which this function returns
9642 at least 1 are added, the addition is known not to overflow.
9644 This function will always return 0 unless called during combine, which
9645 implies that it must be called from a define_split. */
9648 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9650 if (nonzero_sign_valid
== 0)
9654 ? (HWI_COMPUTABLE_MODE_P (mode
)
9655 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9656 - floor_log2 (nonzero_bits (x
, mode
)))
9658 : num_sign_bit_copies (x
, mode
) - 1);
9661 /* This function is called from `simplify_shift_const' to merge two
9662 outer operations. Specifically, we have already found that we need
9663 to perform operation *POP0 with constant *PCONST0 at the outermost
9664 position. We would now like to also perform OP1 with constant CONST1
9665 (with *POP0 being done last).
9667 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9668 the resulting operation. *PCOMP_P is set to 1 if we would need to
9669 complement the innermost operand, otherwise it is unchanged.
9671 MODE is the mode in which the operation will be done. No bits outside
9672 the width of this mode matter. It is assumed that the width of this mode
9673 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9675 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9676 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9677 result is simply *PCONST0.
9679 If the resulting operation cannot be expressed as one operation, we
9680 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9683 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9685 enum rtx_code op0
= *pop0
;
9686 HOST_WIDE_INT const0
= *pconst0
;
9688 const0
&= GET_MODE_MASK (mode
);
9689 const1
&= GET_MODE_MASK (mode
);
9691 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9695 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9698 if (op1
== UNKNOWN
|| op0
== SET
)
9701 else if (op0
== UNKNOWN
)
9702 op0
= op1
, const0
= const1
;
9704 else if (op0
== op1
)
9728 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9729 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9732 /* If the two constants aren't the same, we can't do anything. The
9733 remaining six cases can all be done. */
9734 else if (const0
!= const1
)
9742 /* (a & b) | b == b */
9744 else /* op1 == XOR */
9745 /* (a ^ b) | b == a | b */
9751 /* (a & b) ^ b == (~a) & b */
9752 op0
= AND
, *pcomp_p
= 1;
9753 else /* op1 == IOR */
9754 /* (a | b) ^ b == a & ~b */
9755 op0
= AND
, const0
= ~const0
;
9760 /* (a | b) & b == b */
9762 else /* op1 == XOR */
9763 /* (a ^ b) & b) == (~a) & b */
9770 /* Check for NO-OP cases. */
9771 const0
&= GET_MODE_MASK (mode
);
9773 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9775 else if (const0
== 0 && op0
== AND
)
9777 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9783 /* ??? Slightly redundant with the above mask, but not entirely.
9784 Moving this above means we'd have to sign-extend the mode mask
9785 for the final test. */
9786 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9787 *pconst0
= trunc_int_for_mode (const0
, mode
);
9792 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9793 the shift in. The original shift operation CODE is performed on OP in
9794 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9795 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9796 result of the shift is subject to operation OUTER_CODE with operand
9799 static enum machine_mode
9800 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9801 enum machine_mode orig_mode
, enum machine_mode mode
,
9802 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9804 if (orig_mode
== mode
)
9806 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9808 /* In general we can't perform in wider mode for right shift and rotate. */
9812 /* We can still widen if the bits brought in from the left are identical
9813 to the sign bit of ORIG_MODE. */
9814 if (num_sign_bit_copies (op
, mode
)
9815 > (unsigned) (GET_MODE_PRECISION (mode
)
9816 - GET_MODE_PRECISION (orig_mode
)))
9821 /* Similarly here but with zero bits. */
9822 if (HWI_COMPUTABLE_MODE_P (mode
)
9823 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9826 /* We can also widen if the bits brought in will be masked off. This
9827 operation is performed in ORIG_MODE. */
9828 if (outer_code
== AND
)
9830 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9833 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9849 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9850 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9851 if we cannot simplify it. Otherwise, return a simplified value.
9853 The shift is normally computed in the widest mode we find in VAROP, as
9854 long as it isn't a different number of words than RESULT_MODE. Exceptions
9855 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9858 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9859 rtx varop
, int orig_count
)
9861 enum rtx_code orig_code
= code
;
9862 rtx orig_varop
= varop
;
9864 enum machine_mode mode
= result_mode
;
9865 enum machine_mode shift_mode
, tmode
;
9866 unsigned int mode_words
9867 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9868 /* We form (outer_op (code varop count) (outer_const)). */
9869 enum rtx_code outer_op
= UNKNOWN
;
9870 HOST_WIDE_INT outer_const
= 0;
9871 int complement_p
= 0;
9874 /* Make sure and truncate the "natural" shift on the way in. We don't
9875 want to do this inside the loop as it makes it more difficult to
9877 if (SHIFT_COUNT_TRUNCATED
)
9878 orig_count
&= targetm
.shift_truncation_mask (mode
);
9880 /* If we were given an invalid count, don't do anything except exactly
9881 what was requested. */
9883 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9888 /* Unless one of the branches of the `if' in this loop does a `continue',
9889 we will `break' the loop after the `if'. */
9893 /* If we have an operand of (clobber (const_int 0)), fail. */
9894 if (GET_CODE (varop
) == CLOBBER
)
9897 /* Convert ROTATERT to ROTATE. */
9898 if (code
== ROTATERT
)
9900 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9902 if (VECTOR_MODE_P (result_mode
))
9903 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9905 count
= bitsize
- count
;
9908 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9909 mode
, outer_op
, outer_const
);
9911 /* Handle cases where the count is greater than the size of the mode
9912 minus 1. For ASHIFT, use the size minus one as the count (this can
9913 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9914 take the count modulo the size. For other shifts, the result is
9917 Since these shifts are being produced by the compiler by combining
9918 multiple operations, each of which are defined, we know what the
9919 result is supposed to be. */
9921 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9923 if (code
== ASHIFTRT
)
9924 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9925 else if (code
== ROTATE
|| code
== ROTATERT
)
9926 count
%= GET_MODE_PRECISION (shift_mode
);
9929 /* We can't simply return zero because there may be an
9937 /* If we discovered we had to complement VAROP, leave. Making a NOT
9938 here would cause an infinite loop. */
9942 /* An arithmetic right shift of a quantity known to be -1 or 0
9944 if (code
== ASHIFTRT
9945 && (num_sign_bit_copies (varop
, shift_mode
)
9946 == GET_MODE_PRECISION (shift_mode
)))
9952 /* If we are doing an arithmetic right shift and discarding all but
9953 the sign bit copies, this is equivalent to doing a shift by the
9954 bitsize minus one. Convert it into that shift because it will often
9955 allow other simplifications. */
9957 if (code
== ASHIFTRT
9958 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9959 >= GET_MODE_PRECISION (shift_mode
)))
9960 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9962 /* We simplify the tests below and elsewhere by converting
9963 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9964 `make_compound_operation' will convert it to an ASHIFTRT for
9965 those machines (such as VAX) that don't have an LSHIFTRT. */
9966 if (code
== ASHIFTRT
9967 && val_signbit_known_clear_p (shift_mode
,
9968 nonzero_bits (varop
, shift_mode
)))
9971 if (((code
== LSHIFTRT
9972 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9973 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9975 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9976 && !((nonzero_bits (varop
, shift_mode
) << count
)
9977 & GET_MODE_MASK (shift_mode
))))
9978 && !side_effects_p (varop
))
9981 switch (GET_CODE (varop
))
9987 new_rtx
= expand_compound_operation (varop
);
9988 if (new_rtx
!= varop
)
9996 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9997 minus the width of a smaller mode, we can do this with a
9998 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9999 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10000 && ! mode_dependent_address_p (XEXP (varop
, 0))
10001 && ! MEM_VOLATILE_P (varop
)
10002 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10003 MODE_INT
, 1)) != BLKmode
)
10005 new_rtx
= adjust_address_nv (varop
, tmode
,
10006 BYTES_BIG_ENDIAN
? 0
10007 : count
/ BITS_PER_UNIT
);
10009 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10010 : ZERO_EXTEND
, mode
, new_rtx
);
10017 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10018 the same number of words as what we've seen so far. Then store
10019 the widest mode in MODE. */
10020 if (subreg_lowpart_p (varop
)
10021 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10022 > GET_MODE_SIZE (GET_MODE (varop
)))
10023 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10024 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10026 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10027 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10029 varop
= SUBREG_REG (varop
);
10030 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10031 mode
= GET_MODE (varop
);
10037 /* Some machines use MULT instead of ASHIFT because MULT
10038 is cheaper. But it is still better on those machines to
10039 merge two shifts into one. */
10040 if (CONST_INT_P (XEXP (varop
, 1))
10041 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10044 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10046 GEN_INT (exact_log2 (
10047 UINTVAL (XEXP (varop
, 1)))));
10053 /* Similar, for when divides are cheaper. */
10054 if (CONST_INT_P (XEXP (varop
, 1))
10055 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10058 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10060 GEN_INT (exact_log2 (
10061 UINTVAL (XEXP (varop
, 1)))));
10067 /* If we are extracting just the sign bit of an arithmetic
10068 right shift, that shift is not needed. However, the sign
10069 bit of a wider mode may be different from what would be
10070 interpreted as the sign bit in a narrower mode, so, if
10071 the result is narrower, don't discard the shift. */
10072 if (code
== LSHIFTRT
10073 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10074 && (GET_MODE_BITSIZE (result_mode
)
10075 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10077 varop
= XEXP (varop
, 0);
10081 /* ... fall through ... */
10086 /* Here we have two nested shifts. The result is usually the
10087 AND of a new shift with a mask. We compute the result below. */
10088 if (CONST_INT_P (XEXP (varop
, 1))
10089 && INTVAL (XEXP (varop
, 1)) >= 0
10090 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10091 && HWI_COMPUTABLE_MODE_P (result_mode
)
10092 && HWI_COMPUTABLE_MODE_P (mode
)
10093 && !VECTOR_MODE_P (result_mode
))
10095 enum rtx_code first_code
= GET_CODE (varop
);
10096 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10097 unsigned HOST_WIDE_INT mask
;
10100 /* We have one common special case. We can't do any merging if
10101 the inner code is an ASHIFTRT of a smaller mode. However, if
10102 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10103 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10104 we can convert it to
10105 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10106 This simplifies certain SIGN_EXTEND operations. */
10107 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10108 && count
== (GET_MODE_PRECISION (result_mode
)
10109 - GET_MODE_PRECISION (GET_MODE (varop
))))
10111 /* C3 has the low-order C1 bits zero. */
10113 mask
= GET_MODE_MASK (mode
)
10114 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10116 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10117 XEXP (varop
, 0), mask
);
10118 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10120 count
= first_count
;
10125 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10126 than C1 high-order bits equal to the sign bit, we can convert
10127 this to either an ASHIFT or an ASHIFTRT depending on the
10130 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10132 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10133 && GET_MODE (varop
) == shift_mode
10134 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10137 varop
= XEXP (varop
, 0);
10138 count
-= first_count
;
10148 /* There are some cases we can't do. If CODE is ASHIFTRT,
10149 we can only do this if FIRST_CODE is also ASHIFTRT.
10151 We can't do the case when CODE is ROTATE and FIRST_CODE is
10154 If the mode of this shift is not the mode of the outer shift,
10155 we can't do this if either shift is a right shift or ROTATE.
10157 Finally, we can't do any of these if the mode is too wide
10158 unless the codes are the same.
10160 Handle the case where the shift codes are the same
10163 if (code
== first_code
)
10165 if (GET_MODE (varop
) != result_mode
10166 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10167 || code
== ROTATE
))
10170 count
+= first_count
;
10171 varop
= XEXP (varop
, 0);
10175 if (code
== ASHIFTRT
10176 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10177 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10178 || (GET_MODE (varop
) != result_mode
10179 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10180 || first_code
== ROTATE
10181 || code
== ROTATE
)))
10184 /* To compute the mask to apply after the shift, shift the
10185 nonzero bits of the inner shift the same way the
10186 outer shift will. */
10188 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
10191 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10194 /* Give up if we can't compute an outer operation to use. */
10196 || !CONST_INT_P (mask_rtx
)
10197 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10199 result_mode
, &complement_p
))
10202 /* If the shifts are in the same direction, we add the
10203 counts. Otherwise, we subtract them. */
10204 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10205 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10206 count
+= first_count
;
10208 count
-= first_count
;
10210 /* If COUNT is positive, the new shift is usually CODE,
10211 except for the two exceptions below, in which case it is
10212 FIRST_CODE. If the count is negative, FIRST_CODE should
10215 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10216 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10218 else if (count
< 0)
10219 code
= first_code
, count
= -count
;
10221 varop
= XEXP (varop
, 0);
10225 /* If we have (A << B << C) for any shift, we can convert this to
10226 (A << C << B). This wins if A is a constant. Only try this if
10227 B is not a constant. */
10229 else if (GET_CODE (varop
) == code
10230 && CONST_INT_P (XEXP (varop
, 0))
10231 && !CONST_INT_P (XEXP (varop
, 1)))
10233 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10236 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10243 if (VECTOR_MODE_P (mode
))
10246 /* Make this fit the case below. */
10247 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
10248 GEN_INT (GET_MODE_MASK (mode
)));
10254 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10255 with C the size of VAROP - 1 and the shift is logical if
10256 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10257 we have an (le X 0) operation. If we have an arithmetic shift
10258 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10259 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10261 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10262 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10263 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10264 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10265 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10266 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10269 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10272 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10273 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10278 /* If we have (shift (logical)), move the logical to the outside
10279 to allow it to possibly combine with another logical and the
10280 shift to combine with another shift. This also canonicalizes to
10281 what a ZERO_EXTRACT looks like. Also, some machines have
10282 (and (shift)) insns. */
10284 if (CONST_INT_P (XEXP (varop
, 1))
10285 /* We can't do this if we have (ashiftrt (xor)) and the
10286 constant has its sign bit set in shift_mode. */
10287 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10288 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10290 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10292 GEN_INT (count
))) != 0
10293 && CONST_INT_P (new_rtx
)
10294 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10295 INTVAL (new_rtx
), result_mode
, &complement_p
))
10297 varop
= XEXP (varop
, 0);
10301 /* If we can't do that, try to simplify the shift in each arm of the
10302 logical expression, make a new logical expression, and apply
10303 the inverse distributive law. This also can't be done
10304 for some (ashiftrt (xor)). */
10305 if (CONST_INT_P (XEXP (varop
, 1))
10306 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10307 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10310 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10311 XEXP (varop
, 0), count
);
10312 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10313 XEXP (varop
, 1), count
);
10315 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10317 varop
= apply_distributive_law (varop
);
10325 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10326 says that the sign bit can be tested, FOO has mode MODE, C is
10327 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10328 that may be nonzero. */
10329 if (code
== LSHIFTRT
10330 && XEXP (varop
, 1) == const0_rtx
10331 && GET_MODE (XEXP (varop
, 0)) == result_mode
10332 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10333 && HWI_COMPUTABLE_MODE_P (result_mode
)
10334 && STORE_FLAG_VALUE
== -1
10335 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10336 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10339 varop
= XEXP (varop
, 0);
10346 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10347 than the number of bits in the mode is equivalent to A. */
10348 if (code
== LSHIFTRT
10349 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10350 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10352 varop
= XEXP (varop
, 0);
10357 /* NEG commutes with ASHIFT since it is multiplication. Move the
10358 NEG outside to allow shifts to combine. */
10360 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10363 varop
= XEXP (varop
, 0);
10369 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10370 is one less than the number of bits in the mode is
10371 equivalent to (xor A 1). */
10372 if (code
== LSHIFTRT
10373 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10374 && XEXP (varop
, 1) == constm1_rtx
10375 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10376 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10380 varop
= XEXP (varop
, 0);
10384 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10385 that might be nonzero in BAR are those being shifted out and those
10386 bits are known zero in FOO, we can replace the PLUS with FOO.
10387 Similarly in the other operand order. This code occurs when
10388 we are computing the size of a variable-size array. */
10390 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10391 && count
< HOST_BITS_PER_WIDE_INT
10392 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10393 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10394 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10396 varop
= XEXP (varop
, 0);
10399 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10400 && count
< HOST_BITS_PER_WIDE_INT
10401 && HWI_COMPUTABLE_MODE_P (result_mode
)
10402 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10404 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10405 & nonzero_bits (XEXP (varop
, 1),
10408 varop
= XEXP (varop
, 1);
10412 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10414 && CONST_INT_P (XEXP (varop
, 1))
10415 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10417 GEN_INT (count
))) != 0
10418 && CONST_INT_P (new_rtx
)
10419 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10420 INTVAL (new_rtx
), result_mode
, &complement_p
))
10422 varop
= XEXP (varop
, 0);
10426 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10427 signbit', and attempt to change the PLUS to an XOR and move it to
10428 the outer operation as is done above in the AND/IOR/XOR case
10429 leg for shift(logical). See details in logical handling above
10430 for reasoning in doing so. */
10431 if (code
== LSHIFTRT
10432 && CONST_INT_P (XEXP (varop
, 1))
10433 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10434 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10436 GEN_INT (count
))) != 0
10437 && CONST_INT_P (new_rtx
)
10438 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10439 INTVAL (new_rtx
), result_mode
, &complement_p
))
10441 varop
= XEXP (varop
, 0);
10448 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10449 with C the size of VAROP - 1 and the shift is logical if
10450 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10451 we have a (gt X 0) operation. If the shift is arithmetic with
10452 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10453 we have a (neg (gt X 0)) operation. */
10455 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10456 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10457 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10458 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10459 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10460 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10461 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10464 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10467 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10468 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10475 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10476 if the truncate does not affect the value. */
10477 if (code
== LSHIFTRT
10478 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10479 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10480 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10481 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10482 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10484 rtx varop_inner
= XEXP (varop
, 0);
10487 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10488 XEXP (varop_inner
, 0),
10490 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10491 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10504 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10505 outer_op
, outer_const
);
10507 /* We have now finished analyzing the shift. The result should be
10508 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10509 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10510 to the result of the shift. OUTER_CONST is the relevant constant,
10511 but we must turn off all bits turned off in the shift. */
10513 if (outer_op
== UNKNOWN
10514 && orig_code
== code
&& orig_count
== count
10515 && varop
== orig_varop
10516 && shift_mode
== GET_MODE (varop
))
10519 /* Make a SUBREG if necessary. If we can't make it, fail. */
10520 varop
= gen_lowpart (shift_mode
, varop
);
10521 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10524 /* If we have an outer operation and we just made a shift, it is
10525 possible that we could have simplified the shift were it not
10526 for the outer operation. So try to do the simplification
10529 if (outer_op
!= UNKNOWN
)
10530 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10535 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10537 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10538 turn off all the bits that the shift would have turned off. */
10539 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10540 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10541 GET_MODE_MASK (result_mode
) >> orig_count
);
10543 /* Do the remainder of the processing in RESULT_MODE. */
10544 x
= gen_lowpart_or_truncate (result_mode
, x
);
10546 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10549 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10551 if (outer_op
!= UNKNOWN
)
10553 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10554 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10555 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10557 if (outer_op
== AND
)
10558 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10559 else if (outer_op
== SET
)
10561 /* This means that we have determined that the result is
10562 equivalent to a constant. This should be rare. */
10563 if (!side_effects_p (x
))
10564 x
= GEN_INT (outer_const
);
10566 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10567 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10569 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10570 GEN_INT (outer_const
));
10576 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10577 The result of the shift is RESULT_MODE. If we cannot simplify it,
10578 return X or, if it is NULL, synthesize the expression with
10579 simplify_gen_binary. Otherwise, return a simplified value.
10581 The shift is normally computed in the widest mode we find in VAROP, as
10582 long as it isn't a different number of words than RESULT_MODE. Exceptions
10583 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10586 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10587 rtx varop
, int count
)
10589 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10594 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10595 if (GET_MODE (x
) != result_mode
)
10596 x
= gen_lowpart (result_mode
, x
);
10601 /* Like recog, but we receive the address of a pointer to a new pattern.
10602 We try to match the rtx that the pointer points to.
10603 If that fails, we may try to modify or replace the pattern,
10604 storing the replacement into the same pointer object.
10606 Modifications include deletion or addition of CLOBBERs.
10608 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10609 the CLOBBERs are placed.
10611 The value is the final insn code from the pattern ultimately matched,
10615 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10617 rtx pat
= *pnewpat
;
10618 int insn_code_number
;
10619 int num_clobbers_to_add
= 0;
10622 rtx old_notes
, old_pat
;
10624 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10625 we use to indicate that something didn't match. If we find such a
10626 thing, force rejection. */
10627 if (GET_CODE (pat
) == PARALLEL
)
10628 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10629 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10630 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10633 old_pat
= PATTERN (insn
);
10634 old_notes
= REG_NOTES (insn
);
10635 PATTERN (insn
) = pat
;
10636 REG_NOTES (insn
) = 0;
10638 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10639 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10641 if (insn_code_number
< 0)
10642 fputs ("Failed to match this instruction:\n", dump_file
);
10644 fputs ("Successfully matched this instruction:\n", dump_file
);
10645 print_rtl_single (dump_file
, pat
);
10648 /* If it isn't, there is the possibility that we previously had an insn
10649 that clobbered some register as a side effect, but the combined
10650 insn doesn't need to do that. So try once more without the clobbers
10651 unless this represents an ASM insn. */
10653 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10654 && GET_CODE (pat
) == PARALLEL
)
10658 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10659 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10662 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10666 SUBST_INT (XVECLEN (pat
, 0), pos
);
10669 pat
= XVECEXP (pat
, 0, 0);
10671 PATTERN (insn
) = pat
;
10672 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10673 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10675 if (insn_code_number
< 0)
10676 fputs ("Failed to match this instruction:\n", dump_file
);
10678 fputs ("Successfully matched this instruction:\n", dump_file
);
10679 print_rtl_single (dump_file
, pat
);
10682 PATTERN (insn
) = old_pat
;
10683 REG_NOTES (insn
) = old_notes
;
10685 /* Recognize all noop sets, these will be killed by followup pass. */
10686 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10687 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10689 /* If we had any clobbers to add, make a new pattern than contains
10690 them. Then check to make sure that all of them are dead. */
10691 if (num_clobbers_to_add
)
10693 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10694 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10695 ? (XVECLEN (pat
, 0)
10696 + num_clobbers_to_add
)
10697 : num_clobbers_to_add
+ 1));
10699 if (GET_CODE (pat
) == PARALLEL
)
10700 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10701 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10703 XVECEXP (newpat
, 0, 0) = pat
;
10705 add_clobbers (newpat
, insn_code_number
);
10707 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10708 i
< XVECLEN (newpat
, 0); i
++)
10710 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10711 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10713 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10715 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10716 notes
= alloc_reg_note (REG_UNUSED
,
10717 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10726 return insn_code_number
;
10729 /* Like gen_lowpart_general but for use by combine. In combine it
10730 is not possible to create any new pseudoregs. However, it is
10731 safe to create invalid memory addresses, because combine will
10732 try to recognize them and all they will do is make the combine
10735 If for some reason this cannot do its job, an rtx
10736 (clobber (const_int 0)) is returned.
10737 An insn containing that will not be recognized. */
10740 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10742 enum machine_mode imode
= GET_MODE (x
);
10743 unsigned int osize
= GET_MODE_SIZE (omode
);
10744 unsigned int isize
= GET_MODE_SIZE (imode
);
10747 if (omode
== imode
)
10750 /* Return identity if this is a CONST or symbolic reference. */
10752 && (GET_CODE (x
) == CONST
10753 || GET_CODE (x
) == SYMBOL_REF
10754 || GET_CODE (x
) == LABEL_REF
))
10757 /* We can only support MODE being wider than a word if X is a
10758 constant integer or has a mode the same size. */
10759 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10760 && ! ((imode
== VOIDmode
10761 && (CONST_INT_P (x
)
10762 || GET_CODE (x
) == CONST_DOUBLE
))
10763 || isize
== osize
))
10766 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10767 won't know what to do. So we will strip off the SUBREG here and
10768 process normally. */
10769 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10771 x
= SUBREG_REG (x
);
10773 /* For use in case we fall down into the address adjustments
10774 further below, we need to adjust the known mode and size of
10775 x; imode and isize, since we just adjusted x. */
10776 imode
= GET_MODE (x
);
10778 if (imode
== omode
)
10781 isize
= GET_MODE_SIZE (imode
);
10784 result
= gen_lowpart_common (omode
, x
);
10793 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10795 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10798 /* If we want to refer to something bigger than the original memref,
10799 generate a paradoxical subreg instead. That will force a reload
10800 of the original memref X. */
10802 return gen_rtx_SUBREG (omode
, x
, 0);
10804 if (WORDS_BIG_ENDIAN
)
10805 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10807 /* Adjust the address so that the address-after-the-data is
10809 if (BYTES_BIG_ENDIAN
)
10810 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10812 return adjust_address_nv (x
, omode
, offset
);
10815 /* If X is a comparison operator, rewrite it in a new mode. This
10816 probably won't match, but may allow further simplifications. */
10817 else if (COMPARISON_P (x
))
10818 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10820 /* If we couldn't simplify X any other way, just enclose it in a
10821 SUBREG. Normally, this SUBREG won't match, but some patterns may
10822 include an explicit SUBREG or we may simplify it further in combine. */
10828 offset
= subreg_lowpart_offset (omode
, imode
);
10829 if (imode
== VOIDmode
)
10831 imode
= int_mode_for_mode (omode
);
10832 x
= gen_lowpart_common (imode
, x
);
10836 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10842 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10845 /* Try to simplify a comparison between OP0 and a constant OP1,
10846 where CODE is the comparison code that will be tested, into a
10847 (CODE OP0 const0_rtx) form.
10849 The result is a possibly different comparison code to use.
10850 *POP1 may be updated. */
10852 static enum rtx_code
10853 simplify_compare_const (enum rtx_code code
, rtx op0
, rtx
*pop1
)
10855 enum machine_mode mode
= GET_MODE (op0
);
10856 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10857 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10859 /* Get the constant we are comparing against and turn off all bits
10860 not on in our mode. */
10861 if (mode
!= VOIDmode
)
10862 const_op
= trunc_int_for_mode (const_op
, mode
);
10864 /* If we are comparing against a constant power of two and the value
10865 being compared can only have that single bit nonzero (e.g., it was
10866 `and'ed with that bit), we can replace this with a comparison
10869 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10870 || code
== LT
|| code
== LTU
)
10871 && mode_width
<= HOST_BITS_PER_WIDE_INT
10872 && exact_log2 (const_op
) >= 0
10873 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10875 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10879 /* Similarly, if we are comparing a value known to be either -1 or
10880 0 with -1, change it to the opposite comparison against zero. */
10882 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10883 || code
== GEU
|| code
== LTU
)
10884 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10886 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10890 /* Do some canonicalizations based on the comparison code. We prefer
10891 comparisons against zero and then prefer equality comparisons.
10892 If we can reduce the size of a constant, we will do that too. */
10896 /* < C is equivalent to <= (C - 1) */
10901 /* ... fall through to LE case below. */
10907 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10914 /* If we are doing a <= 0 comparison on a value known to have
10915 a zero sign bit, we can replace this with == 0. */
10916 else if (const_op
== 0
10917 && mode_width
<= HOST_BITS_PER_WIDE_INT
10918 && (nonzero_bits (op0
, mode
)
10919 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10925 /* >= C is equivalent to > (C - 1). */
10930 /* ... fall through to GT below. */
10936 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10943 /* If we are doing a > 0 comparison on a value known to have
10944 a zero sign bit, we can replace this with != 0. */
10945 else if (const_op
== 0
10946 && mode_width
<= HOST_BITS_PER_WIDE_INT
10947 && (nonzero_bits (op0
, mode
)
10948 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10954 /* < C is equivalent to <= (C - 1). */
10959 /* ... fall through ... */
10961 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10962 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10963 && (unsigned HOST_WIDE_INT
) const_op
10964 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10974 /* unsigned <= 0 is equivalent to == 0 */
10977 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10978 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10979 && (unsigned HOST_WIDE_INT
) const_op
10980 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10988 /* >= C is equivalent to > (C - 1). */
10993 /* ... fall through ... */
10996 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10997 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10998 && (unsigned HOST_WIDE_INT
) const_op
10999 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11009 /* unsigned > 0 is equivalent to != 0 */
11012 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11013 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11014 && (unsigned HOST_WIDE_INT
) const_op
11015 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11026 *pop1
= GEN_INT (const_op
);
11030 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11031 comparison code that will be tested.
11033 The result is a possibly different comparison code to use. *POP0 and
11034 *POP1 may be updated.
11036 It is possible that we might detect that a comparison is either always
11037 true or always false. However, we do not perform general constant
11038 folding in combine, so this knowledge isn't useful. Such tautologies
11039 should have been detected earlier. Hence we ignore all such cases. */
11041 static enum rtx_code
11042 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11048 enum machine_mode mode
, tmode
;
11050 /* Try a few ways of applying the same transformation to both operands. */
11053 #ifndef WORD_REGISTER_OPERATIONS
11054 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11055 so check specially. */
11056 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11057 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11058 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11059 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11060 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11061 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11062 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11063 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11064 && CONST_INT_P (XEXP (op0
, 1))
11065 && XEXP (op0
, 1) == XEXP (op1
, 1)
11066 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11067 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11068 && (INTVAL (XEXP (op0
, 1))
11069 == (GET_MODE_PRECISION (GET_MODE (op0
))
11070 - (GET_MODE_PRECISION
11071 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11073 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11074 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11078 /* If both operands are the same constant shift, see if we can ignore the
11079 shift. We can if the shift is a rotate or if the bits shifted out of
11080 this shift are known to be zero for both inputs and if the type of
11081 comparison is compatible with the shift. */
11082 if (GET_CODE (op0
) == GET_CODE (op1
)
11083 && HWI_COMPUTABLE_MODE_P (GET_MODE(op0
))
11084 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11085 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11086 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11087 || (GET_CODE (op0
) == ASHIFTRT
11088 && (code
!= GTU
&& code
!= LTU
11089 && code
!= GEU
&& code
!= LEU
)))
11090 && CONST_INT_P (XEXP (op0
, 1))
11091 && INTVAL (XEXP (op0
, 1)) >= 0
11092 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11093 && XEXP (op0
, 1) == XEXP (op1
, 1))
11095 enum machine_mode mode
= GET_MODE (op0
);
11096 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11097 int shift_count
= INTVAL (XEXP (op0
, 1));
11099 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11100 mask
&= (mask
>> shift_count
) << shift_count
;
11101 else if (GET_CODE (op0
) == ASHIFT
)
11102 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11104 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11105 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11106 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11111 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11112 SUBREGs are of the same mode, and, in both cases, the AND would
11113 be redundant if the comparison was done in the narrower mode,
11114 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11115 and the operand's possibly nonzero bits are 0xffffff01; in that case
11116 if we only care about QImode, we don't need the AND). This case
11117 occurs if the output mode of an scc insn is not SImode and
11118 STORE_FLAG_VALUE == 1 (e.g., the 386).
11120 Similarly, check for a case where the AND's are ZERO_EXTEND
11121 operations from some narrower mode even though a SUBREG is not
11124 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11125 && CONST_INT_P (XEXP (op0
, 1))
11126 && CONST_INT_P (XEXP (op1
, 1)))
11128 rtx inner_op0
= XEXP (op0
, 0);
11129 rtx inner_op1
= XEXP (op1
, 0);
11130 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11131 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11134 if (paradoxical_subreg_p (inner_op0
)
11135 && GET_CODE (inner_op1
) == SUBREG
11136 && (GET_MODE (SUBREG_REG (inner_op0
))
11137 == GET_MODE (SUBREG_REG (inner_op1
)))
11138 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11139 <= HOST_BITS_PER_WIDE_INT
)
11140 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11141 GET_MODE (SUBREG_REG (inner_op0
)))))
11142 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11143 GET_MODE (SUBREG_REG (inner_op1
))))))
11145 op0
= SUBREG_REG (inner_op0
);
11146 op1
= SUBREG_REG (inner_op1
);
11148 /* The resulting comparison is always unsigned since we masked
11149 off the original sign bit. */
11150 code
= unsigned_condition (code
);
11156 for (tmode
= GET_CLASS_NARROWEST_MODE
11157 (GET_MODE_CLASS (GET_MODE (op0
)));
11158 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11159 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11161 op0
= gen_lowpart (tmode
, inner_op0
);
11162 op1
= gen_lowpart (tmode
, inner_op1
);
11163 code
= unsigned_condition (code
);
11172 /* If both operands are NOT, we can strip off the outer operation
11173 and adjust the comparison code for swapped operands; similarly for
11174 NEG, except that this must be an equality comparison. */
11175 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11176 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11177 && (code
== EQ
|| code
== NE
)))
11178 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11184 /* If the first operand is a constant, swap the operands and adjust the
11185 comparison code appropriately, but don't do this if the second operand
11186 is already a constant integer. */
11187 if (swap_commutative_operands_p (op0
, op1
))
11189 tem
= op0
, op0
= op1
, op1
= tem
;
11190 code
= swap_condition (code
);
11193 /* We now enter a loop during which we will try to simplify the comparison.
11194 For the most part, we only are concerned with comparisons with zero,
11195 but some things may really be comparisons with zero but not start
11196 out looking that way. */
11198 while (CONST_INT_P (op1
))
11200 enum machine_mode mode
= GET_MODE (op0
);
11201 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11202 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11203 int equality_comparison_p
;
11204 int sign_bit_comparison_p
;
11205 int unsigned_comparison_p
;
11206 HOST_WIDE_INT const_op
;
11208 /* We only want to handle integral modes. This catches VOIDmode,
11209 CCmode, and the floating-point modes. An exception is that we
11210 can handle VOIDmode if OP0 is a COMPARE or a comparison
11213 if (GET_MODE_CLASS (mode
) != MODE_INT
11214 && ! (mode
== VOIDmode
11215 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11218 /* Try to simplify the compare to constant, possibly changing the
11219 comparison op, and/or changing op1 to zero. */
11220 code
= simplify_compare_const (code
, op0
, &op1
);
11221 const_op
= INTVAL (op1
);
11223 /* Compute some predicates to simplify code below. */
11225 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11226 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11227 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11230 /* If this is a sign bit comparison and we can do arithmetic in
11231 MODE, say that we will only be needing the sign bit of OP0. */
11232 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11233 op0
= force_to_mode (op0
, mode
,
11234 (unsigned HOST_WIDE_INT
) 1
11235 << (GET_MODE_PRECISION (mode
) - 1),
11238 /* Now try cases based on the opcode of OP0. If none of the cases
11239 does a "continue", we exit this loop immediately after the
11242 switch (GET_CODE (op0
))
11245 /* If we are extracting a single bit from a variable position in
11246 a constant that has only a single bit set and are comparing it
11247 with zero, we can convert this into an equality comparison
11248 between the position and the location of the single bit. */
11249 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11250 have already reduced the shift count modulo the word size. */
11251 if (!SHIFT_COUNT_TRUNCATED
11252 && CONST_INT_P (XEXP (op0
, 0))
11253 && XEXP (op0
, 1) == const1_rtx
11254 && equality_comparison_p
&& const_op
== 0
11255 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11257 if (BITS_BIG_ENDIAN
)
11259 enum machine_mode new_mode
11260 = mode_for_extraction (EP_extzv
, 1);
11261 if (new_mode
== MAX_MACHINE_MODE
)
11262 i
= BITS_PER_WORD
- 1 - i
;
11266 i
= (GET_MODE_PRECISION (mode
) - 1 - i
);
11270 op0
= XEXP (op0
, 2);
11274 /* Result is nonzero iff shift count is equal to I. */
11275 code
= reverse_condition (code
);
11279 /* ... fall through ... */
11282 tem
= expand_compound_operation (op0
);
11291 /* If testing for equality, we can take the NOT of the constant. */
11292 if (equality_comparison_p
11293 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11295 op0
= XEXP (op0
, 0);
11300 /* If just looking at the sign bit, reverse the sense of the
11302 if (sign_bit_comparison_p
)
11304 op0
= XEXP (op0
, 0);
11305 code
= (code
== GE
? LT
: GE
);
11311 /* If testing for equality, we can take the NEG of the constant. */
11312 if (equality_comparison_p
11313 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11315 op0
= XEXP (op0
, 0);
11320 /* The remaining cases only apply to comparisons with zero. */
11324 /* When X is ABS or is known positive,
11325 (neg X) is < 0 if and only if X != 0. */
11327 if (sign_bit_comparison_p
11328 && (GET_CODE (XEXP (op0
, 0)) == ABS
11329 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11330 && (nonzero_bits (XEXP (op0
, 0), mode
)
11331 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11334 op0
= XEXP (op0
, 0);
11335 code
= (code
== LT
? NE
: EQ
);
11339 /* If we have NEG of something whose two high-order bits are the
11340 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11341 if (num_sign_bit_copies (op0
, mode
) >= 2)
11343 op0
= XEXP (op0
, 0);
11344 code
= swap_condition (code
);
11350 /* If we are testing equality and our count is a constant, we
11351 can perform the inverse operation on our RHS. */
11352 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11353 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11354 op1
, XEXP (op0
, 1))) != 0)
11356 op0
= XEXP (op0
, 0);
11361 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11362 a particular bit. Convert it to an AND of a constant of that
11363 bit. This will be converted into a ZERO_EXTRACT. */
11364 if (const_op
== 0 && sign_bit_comparison_p
11365 && CONST_INT_P (XEXP (op0
, 1))
11366 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11368 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11369 ((unsigned HOST_WIDE_INT
) 1
11371 - INTVAL (XEXP (op0
, 1)))));
11372 code
= (code
== LT
? NE
: EQ
);
11376 /* Fall through. */
11379 /* ABS is ignorable inside an equality comparison with zero. */
11380 if (const_op
== 0 && equality_comparison_p
)
11382 op0
= XEXP (op0
, 0);
11388 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11389 (compare FOO CONST) if CONST fits in FOO's mode and we
11390 are either testing inequality or have an unsigned
11391 comparison with ZERO_EXTEND or a signed comparison with
11392 SIGN_EXTEND. But don't do it if we don't have a compare
11393 insn of the given mode, since we'd have to revert it
11394 later on, and then we wouldn't know whether to sign- or
11396 mode
= GET_MODE (XEXP (op0
, 0));
11397 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11398 && ! unsigned_comparison_p
11399 && val_signbit_known_clear_p (mode
, const_op
)
11400 && have_insn_for (COMPARE
, mode
))
11402 op0
= XEXP (op0
, 0);
11408 /* Check for the case where we are comparing A - C1 with C2, that is
11410 (subreg:MODE (plus (A) (-C1))) op (C2)
11412 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11413 comparison in the wider mode. One of the following two conditions
11414 must be true in order for this to be valid:
11416 1. The mode extension results in the same bit pattern being added
11417 on both sides and the comparison is equality or unsigned. As
11418 C2 has been truncated to fit in MODE, the pattern can only be
11421 2. The mode extension results in the sign bit being copied on
11424 The difficulty here is that we have predicates for A but not for
11425 (A - C1) so we need to check that C1 is within proper bounds so
11426 as to perturbate A as little as possible. */
11428 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11429 && subreg_lowpart_p (op0
)
11430 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11431 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11432 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11434 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11435 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11436 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11439 && (unsigned HOST_WIDE_INT
) c1
11440 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11441 && (equality_comparison_p
|| unsigned_comparison_p
)
11442 /* (A - C1) zero-extends if it is positive and sign-extends
11443 if it is negative, C2 both zero- and sign-extends. */
11444 && ((0 == (nonzero_bits (a
, inner_mode
)
11445 & ~GET_MODE_MASK (mode
))
11447 /* (A - C1) sign-extends if it is positive and 1-extends
11448 if it is negative, C2 both sign- and 1-extends. */
11449 || (num_sign_bit_copies (a
, inner_mode
)
11450 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11453 || ((unsigned HOST_WIDE_INT
) c1
11454 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11455 /* (A - C1) always sign-extends, like C2. */
11456 && num_sign_bit_copies (a
, inner_mode
)
11457 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11458 - (mode_width
- 1))))
11460 op0
= SUBREG_REG (op0
);
11465 /* If the inner mode is narrower and we are extracting the low part,
11466 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11467 if (subreg_lowpart_p (op0
)
11468 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11469 /* Fall through */ ;
11473 /* ... fall through ... */
11476 mode
= GET_MODE (XEXP (op0
, 0));
11477 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11478 && (unsigned_comparison_p
|| equality_comparison_p
)
11479 && HWI_COMPUTABLE_MODE_P (mode
)
11480 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
11481 && have_insn_for (COMPARE
, mode
))
11483 op0
= XEXP (op0
, 0);
11489 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11490 this for equality comparisons due to pathological cases involving
11492 if (equality_comparison_p
11493 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11494 op1
, XEXP (op0
, 1))))
11496 op0
= XEXP (op0
, 0);
11501 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11502 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11503 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11505 op0
= XEXP (XEXP (op0
, 0), 0);
11506 code
= (code
== LT
? EQ
: NE
);
11512 /* We used to optimize signed comparisons against zero, but that
11513 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11514 arrive here as equality comparisons, or (GEU, LTU) are
11515 optimized away. No need to special-case them. */
11517 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11518 (eq B (minus A C)), whichever simplifies. We can only do
11519 this for equality comparisons due to pathological cases involving
11521 if (equality_comparison_p
11522 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11523 XEXP (op0
, 1), op1
)))
11525 op0
= XEXP (op0
, 0);
11530 if (equality_comparison_p
11531 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11532 XEXP (op0
, 0), op1
)))
11534 op0
= XEXP (op0
, 1);
11539 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11540 of bits in X minus 1, is one iff X > 0. */
11541 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11542 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11543 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11544 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11546 op0
= XEXP (op0
, 1);
11547 code
= (code
== GE
? LE
: GT
);
11553 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11554 if C is zero or B is a constant. */
11555 if (equality_comparison_p
11556 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11557 XEXP (op0
, 1), op1
)))
11559 op0
= XEXP (op0
, 0);
11566 case UNEQ
: case LTGT
:
11567 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11568 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11569 case UNORDERED
: case ORDERED
:
11570 /* We can't do anything if OP0 is a condition code value, rather
11571 than an actual data value. */
11573 || CC0_P (XEXP (op0
, 0))
11574 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11577 /* Get the two operands being compared. */
11578 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11579 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11581 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11583 /* Check for the cases where we simply want the result of the
11584 earlier test or the opposite of that result. */
11585 if (code
== NE
|| code
== EQ
11586 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11587 && (code
== LT
|| code
== GE
)))
11589 enum rtx_code new_code
;
11590 if (code
== LT
|| code
== NE
)
11591 new_code
= GET_CODE (op0
);
11593 new_code
= reversed_comparison_code (op0
, NULL
);
11595 if (new_code
!= UNKNOWN
)
11606 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11608 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11609 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11610 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11612 op0
= XEXP (op0
, 1);
11613 code
= (code
== GE
? GT
: LE
);
11619 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11620 will be converted to a ZERO_EXTRACT later. */
11621 if (const_op
== 0 && equality_comparison_p
11622 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11623 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11625 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11626 XEXP (XEXP (op0
, 0), 1));
11627 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11631 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11632 zero and X is a comparison and C1 and C2 describe only bits set
11633 in STORE_FLAG_VALUE, we can compare with X. */
11634 if (const_op
== 0 && equality_comparison_p
11635 && mode_width
<= HOST_BITS_PER_WIDE_INT
11636 && CONST_INT_P (XEXP (op0
, 1))
11637 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11638 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11639 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11640 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11642 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11643 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11644 if ((~STORE_FLAG_VALUE
& mask
) == 0
11645 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11646 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11647 && COMPARISON_P (tem
))))
11649 op0
= XEXP (XEXP (op0
, 0), 0);
11654 /* If we are doing an equality comparison of an AND of a bit equal
11655 to the sign bit, replace this with a LT or GE comparison of
11656 the underlying value. */
11657 if (equality_comparison_p
11659 && CONST_INT_P (XEXP (op0
, 1))
11660 && mode_width
<= HOST_BITS_PER_WIDE_INT
11661 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11662 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11664 op0
= XEXP (op0
, 0);
11665 code
= (code
== EQ
? GE
: LT
);
11669 /* If this AND operation is really a ZERO_EXTEND from a narrower
11670 mode, the constant fits within that mode, and this is either an
11671 equality or unsigned comparison, try to do this comparison in
11676 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11677 -> (ne:DI (reg:SI 4) (const_int 0))
11679 unless TRULY_NOOP_TRUNCATION allows it or the register is
11680 known to hold a value of the required mode the
11681 transformation is invalid. */
11682 if ((equality_comparison_p
|| unsigned_comparison_p
)
11683 && CONST_INT_P (XEXP (op0
, 1))
11684 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11685 & GET_MODE_MASK (mode
))
11687 && const_op
>> i
== 0
11688 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11689 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11690 || (REG_P (XEXP (op0
, 0))
11691 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11693 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11697 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11698 fits in both M1 and M2 and the SUBREG is either paradoxical
11699 or represents the low part, permute the SUBREG and the AND
11701 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11703 unsigned HOST_WIDE_INT c1
;
11704 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11705 /* Require an integral mode, to avoid creating something like
11707 if (SCALAR_INT_MODE_P (tmode
)
11708 /* It is unsafe to commute the AND into the SUBREG if the
11709 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11710 not defined. As originally written the upper bits
11711 have a defined value due to the AND operation.
11712 However, if we commute the AND inside the SUBREG then
11713 they no longer have defined values and the meaning of
11714 the code has been changed. */
11716 #ifdef WORD_REGISTER_OPERATIONS
11717 || (mode_width
> GET_MODE_PRECISION (tmode
)
11718 && mode_width
<= BITS_PER_WORD
)
11720 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11721 && subreg_lowpart_p (XEXP (op0
, 0))))
11722 && CONST_INT_P (XEXP (op0
, 1))
11723 && mode_width
<= HOST_BITS_PER_WIDE_INT
11724 && HWI_COMPUTABLE_MODE_P (tmode
)
11725 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11726 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11728 && c1
!= GET_MODE_MASK (tmode
))
11730 op0
= simplify_gen_binary (AND
, tmode
,
11731 SUBREG_REG (XEXP (op0
, 0)),
11732 gen_int_mode (c1
, tmode
));
11733 op0
= gen_lowpart (mode
, op0
);
11738 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11739 if (const_op
== 0 && equality_comparison_p
11740 && XEXP (op0
, 1) == const1_rtx
11741 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11743 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11744 XEXP (XEXP (op0
, 0), 0), 1);
11745 code
= (code
== NE
? EQ
: NE
);
11749 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11750 (eq (and (lshiftrt X) 1) 0).
11751 Also handle the case where (not X) is expressed using xor. */
11752 if (const_op
== 0 && equality_comparison_p
11753 && XEXP (op0
, 1) == const1_rtx
11754 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11756 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11757 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11759 if (GET_CODE (shift_op
) == NOT
11760 || (GET_CODE (shift_op
) == XOR
11761 && CONST_INT_P (XEXP (shift_op
, 1))
11762 && CONST_INT_P (shift_count
)
11763 && HWI_COMPUTABLE_MODE_P (mode
)
11764 && (UINTVAL (XEXP (shift_op
, 1))
11765 == (unsigned HOST_WIDE_INT
) 1
11766 << INTVAL (shift_count
))))
11769 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11770 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11771 code
= (code
== NE
? EQ
: NE
);
11778 /* If we have (compare (ashift FOO N) (const_int C)) and
11779 the high order N bits of FOO (N+1 if an inequality comparison)
11780 are known to be zero, we can do this by comparing FOO with C
11781 shifted right N bits so long as the low-order N bits of C are
11783 if (CONST_INT_P (XEXP (op0
, 1))
11784 && INTVAL (XEXP (op0
, 1)) >= 0
11785 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11786 < HOST_BITS_PER_WIDE_INT
)
11787 && (((unsigned HOST_WIDE_INT
) const_op
11788 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11790 && mode_width
<= HOST_BITS_PER_WIDE_INT
11791 && (nonzero_bits (XEXP (op0
, 0), mode
)
11792 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11793 + ! equality_comparison_p
))) == 0)
11795 /* We must perform a logical shift, not an arithmetic one,
11796 as we want the top N bits of C to be zero. */
11797 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11799 temp
>>= INTVAL (XEXP (op0
, 1));
11800 op1
= gen_int_mode (temp
, mode
);
11801 op0
= XEXP (op0
, 0);
11805 /* If we are doing a sign bit comparison, it means we are testing
11806 a particular bit. Convert it to the appropriate AND. */
11807 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11808 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11810 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11811 ((unsigned HOST_WIDE_INT
) 1
11813 - INTVAL (XEXP (op0
, 1)))));
11814 code
= (code
== LT
? NE
: EQ
);
11818 /* If this an equality comparison with zero and we are shifting
11819 the low bit to the sign bit, we can convert this to an AND of the
11821 if (const_op
== 0 && equality_comparison_p
11822 && CONST_INT_P (XEXP (op0
, 1))
11823 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11825 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11831 /* If this is an equality comparison with zero, we can do this
11832 as a logical shift, which might be much simpler. */
11833 if (equality_comparison_p
&& const_op
== 0
11834 && CONST_INT_P (XEXP (op0
, 1)))
11836 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11838 INTVAL (XEXP (op0
, 1)));
11842 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11843 do the comparison in a narrower mode. */
11844 if (! unsigned_comparison_p
11845 && CONST_INT_P (XEXP (op0
, 1))
11846 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11847 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11848 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11849 MODE_INT
, 1)) != BLKmode
11850 && (((unsigned HOST_WIDE_INT
) const_op
11851 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11852 <= GET_MODE_MASK (tmode
)))
11854 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11858 /* Likewise if OP0 is a PLUS of a sign extension with a
11859 constant, which is usually represented with the PLUS
11860 between the shifts. */
11861 if (! unsigned_comparison_p
11862 && CONST_INT_P (XEXP (op0
, 1))
11863 && GET_CODE (XEXP (op0
, 0)) == PLUS
11864 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11865 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11866 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11867 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11868 MODE_INT
, 1)) != BLKmode
11869 && (((unsigned HOST_WIDE_INT
) const_op
11870 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11871 <= GET_MODE_MASK (tmode
)))
11873 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11874 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11875 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11876 add_const
, XEXP (op0
, 1));
11878 op0
= simplify_gen_binary (PLUS
, tmode
,
11879 gen_lowpart (tmode
, inner
),
11884 /* ... fall through ... */
11886 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11887 the low order N bits of FOO are known to be zero, we can do this
11888 by comparing FOO with C shifted left N bits so long as no
11889 overflow occurs. Even if the low order N bits of FOO aren't known
11890 to be zero, if the comparison is >= or < we can use the same
11891 optimization and for > or <= by setting all the low
11892 order N bits in the comparison constant. */
11893 if (CONST_INT_P (XEXP (op0
, 1))
11894 && INTVAL (XEXP (op0
, 1)) > 0
11895 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11896 && mode_width
<= HOST_BITS_PER_WIDE_INT
11897 && (((unsigned HOST_WIDE_INT
) const_op
11898 + (GET_CODE (op0
) != LSHIFTRT
11899 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11902 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11904 unsigned HOST_WIDE_INT low_bits
11905 = (nonzero_bits (XEXP (op0
, 0), mode
)
11906 & (((unsigned HOST_WIDE_INT
) 1
11907 << INTVAL (XEXP (op0
, 1))) - 1));
11908 if (low_bits
== 0 || !equality_comparison_p
)
11910 /* If the shift was logical, then we must make the condition
11912 if (GET_CODE (op0
) == LSHIFTRT
)
11913 code
= unsigned_condition (code
);
11915 const_op
<<= INTVAL (XEXP (op0
, 1));
11917 && (code
== GT
|| code
== GTU
11918 || code
== LE
|| code
== LEU
))
11920 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11921 op1
= GEN_INT (const_op
);
11922 op0
= XEXP (op0
, 0);
11927 /* If we are using this shift to extract just the sign bit, we
11928 can replace this with an LT or GE comparison. */
11930 && (equality_comparison_p
|| sign_bit_comparison_p
)
11931 && CONST_INT_P (XEXP (op0
, 1))
11932 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11934 op0
= XEXP (op0
, 0);
11935 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11947 /* Now make any compound operations involved in this comparison. Then,
11948 check for an outmost SUBREG on OP0 that is not doing anything or is
11949 paradoxical. The latter transformation must only be performed when
11950 it is known that the "extra" bits will be the same in op0 and op1 or
11951 that they don't matter. There are three cases to consider:
11953 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11954 care bits and we can assume they have any convenient value. So
11955 making the transformation is safe.
11957 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11958 In this case the upper bits of op0 are undefined. We should not make
11959 the simplification in that case as we do not know the contents of
11962 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11963 UNKNOWN. In that case we know those bits are zeros or ones. We must
11964 also be sure that they are the same as the upper bits of op1.
11966 We can never remove a SUBREG for a non-equality comparison because
11967 the sign bit is in a different place in the underlying object. */
11969 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11970 op1
= make_compound_operation (op1
, SET
);
11972 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11973 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11974 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11975 && (code
== NE
|| code
== EQ
))
11977 if (paradoxical_subreg_p (op0
))
11979 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11981 if (REG_P (SUBREG_REG (op0
)))
11983 op0
= SUBREG_REG (op0
);
11984 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11987 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
11988 <= HOST_BITS_PER_WIDE_INT
)
11989 && (nonzero_bits (SUBREG_REG (op0
),
11990 GET_MODE (SUBREG_REG (op0
)))
11991 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11993 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11995 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11996 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11997 op0
= SUBREG_REG (op0
), op1
= tem
;
12001 /* We now do the opposite procedure: Some machines don't have compare
12002 insns in all modes. If OP0's mode is an integer mode smaller than a
12003 word and we can't do a compare in that mode, see if there is a larger
12004 mode for which we can do the compare. There are a number of cases in
12005 which we can use the wider mode. */
12007 mode
= GET_MODE (op0
);
12008 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12009 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12010 && ! have_insn_for (COMPARE
, mode
))
12011 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12012 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12013 tmode
= GET_MODE_WIDER_MODE (tmode
))
12014 if (have_insn_for (COMPARE
, tmode
))
12018 /* If this is a test for negative, we can make an explicit
12019 test of the sign bit. Test this first so we can use
12020 a paradoxical subreg to extend OP0. */
12022 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12023 && HWI_COMPUTABLE_MODE_P (mode
))
12025 op0
= simplify_gen_binary (AND
, tmode
,
12026 gen_lowpart (tmode
, op0
),
12027 GEN_INT ((unsigned HOST_WIDE_INT
) 1
12028 << (GET_MODE_BITSIZE (mode
)
12030 code
= (code
== LT
) ? NE
: EQ
;
12034 /* If the only nonzero bits in OP0 and OP1 are those in the
12035 narrower mode and this is an equality or unsigned comparison,
12036 we can use the wider mode. Similarly for sign-extended
12037 values, in which case it is true for all comparisons. */
12038 zero_extended
= ((code
== EQ
|| code
== NE
12039 || code
== GEU
|| code
== GTU
12040 || code
== LEU
|| code
== LTU
)
12041 && (nonzero_bits (op0
, tmode
)
12042 & ~GET_MODE_MASK (mode
)) == 0
12043 && ((CONST_INT_P (op1
)
12044 || (nonzero_bits (op1
, tmode
)
12045 & ~GET_MODE_MASK (mode
)) == 0)));
12048 || ((num_sign_bit_copies (op0
, tmode
)
12049 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12050 - GET_MODE_PRECISION (mode
)))
12051 && (num_sign_bit_copies (op1
, tmode
)
12052 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12053 - GET_MODE_PRECISION (mode
)))))
12055 /* If OP0 is an AND and we don't have an AND in MODE either,
12056 make a new AND in the proper mode. */
12057 if (GET_CODE (op0
) == AND
12058 && !have_insn_for (AND
, mode
))
12059 op0
= simplify_gen_binary (AND
, tmode
,
12060 gen_lowpart (tmode
,
12062 gen_lowpart (tmode
,
12068 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12069 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12073 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12074 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12081 #ifdef CANONICALIZE_COMPARISON
12082 /* If this machine only supports a subset of valid comparisons, see if we
12083 can convert an unsupported one into a supported one. */
12084 CANONICALIZE_COMPARISON (code
, op0
, op1
);
12093 /* Utility function for record_value_for_reg. Count number of
12098 enum rtx_code code
= GET_CODE (x
);
12102 if (GET_RTX_CLASS (code
) == '2'
12103 || GET_RTX_CLASS (code
) == 'c')
12105 rtx x0
= XEXP (x
, 0);
12106 rtx x1
= XEXP (x
, 1);
12109 return 1 + 2 * count_rtxs (x0
);
12111 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
12112 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
12113 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12114 return 2 + 2 * count_rtxs (x0
)
12115 + count_rtxs (x
== XEXP (x1
, 0)
12116 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12118 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
12119 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
12120 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12121 return 2 + 2 * count_rtxs (x1
)
12122 + count_rtxs (x
== XEXP (x0
, 0)
12123 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12126 fmt
= GET_RTX_FORMAT (code
);
12127 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12129 ret
+= count_rtxs (XEXP (x
, i
));
12130 else if (fmt
[i
] == 'E')
12131 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12132 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12137 /* Utility function for following routine. Called when X is part of a value
12138 being stored into last_set_value. Sets last_set_table_tick
12139 for each register mentioned. Similar to mention_regs in cse.c */
12142 update_table_tick (rtx x
)
12144 enum rtx_code code
= GET_CODE (x
);
12145 const char *fmt
= GET_RTX_FORMAT (code
);
12150 unsigned int regno
= REGNO (x
);
12151 unsigned int endregno
= END_REGNO (x
);
12154 for (r
= regno
; r
< endregno
; r
++)
12156 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, r
);
12157 rsp
->last_set_table_tick
= label_tick
;
12163 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12166 /* Check for identical subexpressions. If x contains
12167 identical subexpression we only have to traverse one of
12169 if (i
== 0 && ARITHMETIC_P (x
))
12171 /* Note that at this point x1 has already been
12173 rtx x0
= XEXP (x
, 0);
12174 rtx x1
= XEXP (x
, 1);
12176 /* If x0 and x1 are identical then there is no need to
12181 /* If x0 is identical to a subexpression of x1 then while
12182 processing x1, x0 has already been processed. Thus we
12183 are done with x. */
12184 if (ARITHMETIC_P (x1
)
12185 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12188 /* If x1 is identical to a subexpression of x0 then we
12189 still have to process the rest of x0. */
12190 if (ARITHMETIC_P (x0
)
12191 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12193 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12198 update_table_tick (XEXP (x
, i
));
12200 else if (fmt
[i
] == 'E')
12201 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12202 update_table_tick (XVECEXP (x
, i
, j
));
12205 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12206 are saying that the register is clobbered and we no longer know its
12207 value. If INSN is zero, don't update reg_stat[].last_set; this is
12208 only permitted with VALUE also zero and is used to invalidate the
12212 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12214 unsigned int regno
= REGNO (reg
);
12215 unsigned int endregno
= END_REGNO (reg
);
12217 reg_stat_type
*rsp
;
12219 /* If VALUE contains REG and we have a previous value for REG, substitute
12220 the previous value. */
12221 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12225 /* Set things up so get_last_value is allowed to see anything set up to
12227 subst_low_luid
= DF_INSN_LUID (insn
);
12228 tem
= get_last_value (reg
);
12230 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12231 it isn't going to be useful and will take a lot of time to process,
12232 so just use the CLOBBER. */
12236 if (ARITHMETIC_P (tem
)
12237 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12238 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12239 tem
= XEXP (tem
, 0);
12240 else if (count_occurrences (value
, reg
, 1) >= 2)
12242 /* If there are two or more occurrences of REG in VALUE,
12243 prevent the value from growing too much. */
12244 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12245 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12248 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12252 /* For each register modified, show we don't know its value, that
12253 we don't know about its bitwise content, that its value has been
12254 updated, and that we don't know the location of the death of the
12256 for (i
= regno
; i
< endregno
; i
++)
12258 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12261 rsp
->last_set
= insn
;
12263 rsp
->last_set_value
= 0;
12264 rsp
->last_set_mode
= VOIDmode
;
12265 rsp
->last_set_nonzero_bits
= 0;
12266 rsp
->last_set_sign_bit_copies
= 0;
12267 rsp
->last_death
= 0;
12268 rsp
->truncated_to_mode
= VOIDmode
;
12271 /* Mark registers that are being referenced in this value. */
12273 update_table_tick (value
);
12275 /* Now update the status of each register being set.
12276 If someone is using this register in this block, set this register
12277 to invalid since we will get confused between the two lives in this
12278 basic block. This makes using this register always invalid. In cse, we
12279 scan the table to invalidate all entries using this register, but this
12280 is too much work for us. */
12282 for (i
= regno
; i
< endregno
; i
++)
12284 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12285 rsp
->last_set_label
= label_tick
;
12287 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12288 rsp
->last_set_invalid
= 1;
12290 rsp
->last_set_invalid
= 0;
12293 /* The value being assigned might refer to X (like in "x++;"). In that
12294 case, we must replace it with (clobber (const_int 0)) to prevent
12296 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12297 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12299 value
= copy_rtx (value
);
12300 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12304 /* For the main register being modified, update the value, the mode, the
12305 nonzero bits, and the number of sign bit copies. */
12307 rsp
->last_set_value
= value
;
12311 enum machine_mode mode
= GET_MODE (reg
);
12312 subst_low_luid
= DF_INSN_LUID (insn
);
12313 rsp
->last_set_mode
= mode
;
12314 if (GET_MODE_CLASS (mode
) == MODE_INT
12315 && HWI_COMPUTABLE_MODE_P (mode
))
12316 mode
= nonzero_bits_mode
;
12317 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12318 rsp
->last_set_sign_bit_copies
12319 = num_sign_bit_copies (value
, GET_MODE (reg
));
12323 /* Called via note_stores from record_dead_and_set_regs to handle one
12324 SET or CLOBBER in an insn. DATA is the instruction in which the
12325 set is occurring. */
12328 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12330 rtx record_dead_insn
= (rtx
) data
;
12332 if (GET_CODE (dest
) == SUBREG
)
12333 dest
= SUBREG_REG (dest
);
12335 if (!record_dead_insn
)
12338 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12344 /* If we are setting the whole register, we know its value. Otherwise
12345 show that we don't know the value. We can handle SUBREG in
12347 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12348 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12349 else if (GET_CODE (setter
) == SET
12350 && GET_CODE (SET_DEST (setter
)) == SUBREG
12351 && SUBREG_REG (SET_DEST (setter
)) == dest
12352 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12353 && subreg_lowpart_p (SET_DEST (setter
)))
12354 record_value_for_reg (dest
, record_dead_insn
,
12355 gen_lowpart (GET_MODE (dest
),
12356 SET_SRC (setter
)));
12358 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12360 else if (MEM_P (dest
)
12361 /* Ignore pushes, they clobber nothing. */
12362 && ! push_operand (dest
, GET_MODE (dest
)))
12363 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12366 /* Update the records of when each REG was most recently set or killed
12367 for the things done by INSN. This is the last thing done in processing
12368 INSN in the combiner loop.
12370 We update reg_stat[], in particular fields last_set, last_set_value,
12371 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12372 last_death, and also the similar information mem_last_set (which insn
12373 most recently modified memory) and last_call_luid (which insn was the
12374 most recent subroutine call). */
12377 record_dead_and_set_regs (rtx insn
)
12382 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12384 if (REG_NOTE_KIND (link
) == REG_DEAD
12385 && REG_P (XEXP (link
, 0)))
12387 unsigned int regno
= REGNO (XEXP (link
, 0));
12388 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12390 for (i
= regno
; i
< endregno
; i
++)
12392 reg_stat_type
*rsp
;
12394 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12395 rsp
->last_death
= insn
;
12398 else if (REG_NOTE_KIND (link
) == REG_INC
)
12399 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12404 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12405 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
12407 reg_stat_type
*rsp
;
12409 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12410 rsp
->last_set_invalid
= 1;
12411 rsp
->last_set
= insn
;
12412 rsp
->last_set_value
= 0;
12413 rsp
->last_set_mode
= VOIDmode
;
12414 rsp
->last_set_nonzero_bits
= 0;
12415 rsp
->last_set_sign_bit_copies
= 0;
12416 rsp
->last_death
= 0;
12417 rsp
->truncated_to_mode
= VOIDmode
;
12420 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12422 /* We can't combine into a call pattern. Remember, though, that
12423 the return value register is set at this LUID. We could
12424 still replace a register with the return value from the
12425 wrong subroutine call! */
12426 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12429 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12432 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12433 register present in the SUBREG, so for each such SUBREG go back and
12434 adjust nonzero and sign bit information of the registers that are
12435 known to have some zero/sign bits set.
12437 This is needed because when combine blows the SUBREGs away, the
12438 information on zero/sign bits is lost and further combines can be
12439 missed because of that. */
12442 record_promoted_value (rtx insn
, rtx subreg
)
12444 struct insn_link
*links
;
12446 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12447 enum machine_mode mode
= GET_MODE (subreg
);
12449 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12452 for (links
= LOG_LINKS (insn
); links
;)
12454 reg_stat_type
*rsp
;
12456 insn
= links
->insn
;
12457 set
= single_set (insn
);
12459 if (! set
|| !REG_P (SET_DEST (set
))
12460 || REGNO (SET_DEST (set
)) != regno
12461 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12463 links
= links
->next
;
12467 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12468 if (rsp
->last_set
== insn
)
12470 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12471 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12474 if (REG_P (SET_SRC (set
)))
12476 regno
= REGNO (SET_SRC (set
));
12477 links
= LOG_LINKS (insn
);
12484 /* Check if X, a register, is known to contain a value already
12485 truncated to MODE. In this case we can use a subreg to refer to
12486 the truncated value even though in the generic case we would need
12487 an explicit truncation. */
12490 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12492 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12493 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12496 || rsp
->truncation_label
< label_tick_ebb_start
)
12498 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12500 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12505 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12506 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12507 might be able to turn a truncate into a subreg using this information.
12508 Return -1 if traversing *P is complete or 0 otherwise. */
12511 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12514 enum machine_mode truncated_mode
;
12515 reg_stat_type
*rsp
;
12517 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12519 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12520 truncated_mode
= GET_MODE (x
);
12522 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12525 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12528 x
= SUBREG_REG (x
);
12530 /* ??? For hard-regs we now record everything. We might be able to
12531 optimize this using last_set_mode. */
12532 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12533 truncated_mode
= GET_MODE (x
);
12537 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12538 if (rsp
->truncated_to_mode
== 0
12539 || rsp
->truncation_label
< label_tick_ebb_start
12540 || (GET_MODE_SIZE (truncated_mode
)
12541 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12543 rsp
->truncated_to_mode
= truncated_mode
;
12544 rsp
->truncation_label
= label_tick
;
12550 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12551 the modes they are used in. This can help truning TRUNCATEs into
12555 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12557 for_each_rtx (x
, record_truncated_value
, NULL
);
12560 /* Scan X for promoted SUBREGs. For each one found,
12561 note what it implies to the registers used in it. */
12564 check_promoted_subreg (rtx insn
, rtx x
)
12566 if (GET_CODE (x
) == SUBREG
12567 && SUBREG_PROMOTED_VAR_P (x
)
12568 && REG_P (SUBREG_REG (x
)))
12569 record_promoted_value (insn
, x
);
12572 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12575 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12579 check_promoted_subreg (insn
, XEXP (x
, i
));
12583 if (XVEC (x
, i
) != 0)
12584 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12585 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12591 /* Verify that all the registers and memory references mentioned in *LOC are
12592 still valid. *LOC was part of a value set in INSN when label_tick was
12593 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12594 the invalid references with (clobber (const_int 0)) and return 1. This
12595 replacement is useful because we often can get useful information about
12596 the form of a value (e.g., if it was produced by a shift that always
12597 produces -1 or 0) even though we don't know exactly what registers it
12598 was produced from. */
12601 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12604 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12605 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12610 unsigned int regno
= REGNO (x
);
12611 unsigned int endregno
= END_REGNO (x
);
12614 for (j
= regno
; j
< endregno
; j
++)
12616 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, j
);
12617 if (rsp
->last_set_invalid
12618 /* If this is a pseudo-register that was only set once and not
12619 live at the beginning of the function, it is always valid. */
12620 || (! (regno
>= FIRST_PSEUDO_REGISTER
12621 && REG_N_SETS (regno
) == 1
12622 && (!REGNO_REG_SET_P
12623 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12624 && rsp
->last_set_label
> tick
))
12627 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12634 /* If this is a memory reference, make sure that there were no stores after
12635 it that might have clobbered the value. We don't have alias info, so we
12636 assume any store invalidates it. Moreover, we only have local UIDs, so
12637 we also assume that there were stores in the intervening basic blocks. */
12638 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12639 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12642 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12646 for (i
= 0; i
< len
; i
++)
12650 /* Check for identical subexpressions. If x contains
12651 identical subexpression we only have to traverse one of
12653 if (i
== 1 && ARITHMETIC_P (x
))
12655 /* Note that at this point x0 has already been checked
12656 and found valid. */
12657 rtx x0
= XEXP (x
, 0);
12658 rtx x1
= XEXP (x
, 1);
12660 /* If x0 and x1 are identical then x is also valid. */
12664 /* If x1 is identical to a subexpression of x0 then
12665 while checking x0, x1 has already been checked. Thus
12666 it is valid and so as x. */
12667 if (ARITHMETIC_P (x0
)
12668 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12671 /* If x0 is identical to a subexpression of x1 then x is
12672 valid iff the rest of x1 is valid. */
12673 if (ARITHMETIC_P (x1
)
12674 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12676 get_last_value_validate (&XEXP (x1
,
12677 x0
== XEXP (x1
, 0) ? 1 : 0),
12678 insn
, tick
, replace
);
12681 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12685 else if (fmt
[i
] == 'E')
12686 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12687 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12688 insn
, tick
, replace
) == 0)
12692 /* If we haven't found a reason for it to be invalid, it is valid. */
12696 /* Get the last value assigned to X, if known. Some registers
12697 in the value may be replaced with (clobber (const_int 0)) if their value
12698 is known longer known reliably. */
12701 get_last_value (const_rtx x
)
12703 unsigned int regno
;
12705 reg_stat_type
*rsp
;
12707 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12708 then convert it to the desired mode. If this is a paradoxical SUBREG,
12709 we cannot predict what values the "extra" bits might have. */
12710 if (GET_CODE (x
) == SUBREG
12711 && subreg_lowpart_p (x
)
12712 && !paradoxical_subreg_p (x
)
12713 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12714 return gen_lowpart (GET_MODE (x
), value
);
12720 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12721 value
= rsp
->last_set_value
;
12723 /* If we don't have a value, or if it isn't for this basic block and
12724 it's either a hard register, set more than once, or it's a live
12725 at the beginning of the function, return 0.
12727 Because if it's not live at the beginning of the function then the reg
12728 is always set before being used (is never used without being set).
12729 And, if it's set only once, and it's always set before use, then all
12730 uses must have the same last value, even if it's not from this basic
12734 || (rsp
->last_set_label
< label_tick_ebb_start
12735 && (regno
< FIRST_PSEUDO_REGISTER
12736 || REG_N_SETS (regno
) != 1
12738 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12741 /* If the value was set in a later insn than the ones we are processing,
12742 we can't use it even if the register was only set once. */
12743 if (rsp
->last_set_label
== label_tick
12744 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12747 /* If the value has all its registers valid, return it. */
12748 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12751 /* Otherwise, make a copy and replace any invalid register with
12752 (clobber (const_int 0)). If that fails for some reason, return 0. */
12754 value
= copy_rtx (value
);
12755 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12761 /* Return nonzero if expression X refers to a REG or to memory
12762 that is set in an instruction more recent than FROM_LUID. */
12765 use_crosses_set_p (const_rtx x
, int from_luid
)
12769 enum rtx_code code
= GET_CODE (x
);
12773 unsigned int regno
= REGNO (x
);
12774 unsigned endreg
= END_REGNO (x
);
12776 #ifdef PUSH_ROUNDING
12777 /* Don't allow uses of the stack pointer to be moved,
12778 because we don't know whether the move crosses a push insn. */
12779 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12782 for (; regno
< endreg
; regno
++)
12784 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12786 && rsp
->last_set_label
== label_tick
12787 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12793 if (code
== MEM
&& mem_last_set
> from_luid
)
12796 fmt
= GET_RTX_FORMAT (code
);
12798 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12803 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12804 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12807 else if (fmt
[i
] == 'e'
12808 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12814 /* Define three variables used for communication between the following
12817 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12818 static int reg_dead_flag
;
12820 /* Function called via note_stores from reg_dead_at_p.
12822 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12823 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12826 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12828 unsigned int regno
, endregno
;
12833 regno
= REGNO (dest
);
12834 endregno
= END_REGNO (dest
);
12835 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12836 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12839 /* Return nonzero if REG is known to be dead at INSN.
12841 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12842 referencing REG, it is dead. If we hit a SET referencing REG, it is
12843 live. Otherwise, see if it is live or dead at the start of the basic
12844 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12845 must be assumed to be always live. */
12848 reg_dead_at_p (rtx reg
, rtx insn
)
12853 /* Set variables for reg_dead_at_p_1. */
12854 reg_dead_regno
= REGNO (reg
);
12855 reg_dead_endregno
= END_REGNO (reg
);
12859 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12860 we allow the machine description to decide whether use-and-clobber
12861 patterns are OK. */
12862 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12864 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12865 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12869 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12870 beginning of basic block. */
12871 block
= BLOCK_FOR_INSN (insn
);
12876 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12878 return reg_dead_flag
== 1 ? 1 : 0;
12880 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12884 if (insn
== BB_HEAD (block
))
12887 insn
= PREV_INSN (insn
);
12890 /* Look at live-in sets for the basic block that we were in. */
12891 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12892 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12898 /* Note hard registers in X that are used. */
12901 mark_used_regs_combine (rtx x
)
12903 RTX_CODE code
= GET_CODE (x
);
12904 unsigned int regno
;
12917 case ADDR_DIFF_VEC
:
12920 /* CC0 must die in the insn after it is set, so we don't need to take
12921 special note of it here. */
12927 /* If we are clobbering a MEM, mark any hard registers inside the
12928 address as used. */
12929 if (MEM_P (XEXP (x
, 0)))
12930 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12935 /* A hard reg in a wide mode may really be multiple registers.
12936 If so, mark all of them just like the first. */
12937 if (regno
< FIRST_PSEUDO_REGISTER
)
12939 /* None of this applies to the stack, frame or arg pointers. */
12940 if (regno
== STACK_POINTER_REGNUM
12941 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12942 || regno
== HARD_FRAME_POINTER_REGNUM
12944 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12945 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12947 || regno
== FRAME_POINTER_REGNUM
)
12950 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12956 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12958 rtx testreg
= SET_DEST (x
);
12960 while (GET_CODE (testreg
) == SUBREG
12961 || GET_CODE (testreg
) == ZERO_EXTRACT
12962 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12963 testreg
= XEXP (testreg
, 0);
12965 if (MEM_P (testreg
))
12966 mark_used_regs_combine (XEXP (testreg
, 0));
12968 mark_used_regs_combine (SET_SRC (x
));
12976 /* Recursively scan the operands of this expression. */
12979 const char *fmt
= GET_RTX_FORMAT (code
);
12981 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12984 mark_used_regs_combine (XEXP (x
, i
));
12985 else if (fmt
[i
] == 'E')
12989 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12990 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12996 /* Remove register number REGNO from the dead registers list of INSN.
12998 Return the note used to record the death, if there was one. */
13001 remove_death (unsigned int regno
, rtx insn
)
13003 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13006 remove_note (insn
, note
);
13011 /* For each register (hardware or pseudo) used within expression X, if its
13012 death is in an instruction with luid between FROM_LUID (inclusive) and
13013 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13014 list headed by PNOTES.
13016 That said, don't move registers killed by maybe_kill_insn.
13018 This is done when X is being merged by combination into TO_INSN. These
13019 notes will then be distributed as needed. */
13022 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
13027 enum rtx_code code
= GET_CODE (x
);
13031 unsigned int regno
= REGNO (x
);
13032 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
)->last_death
;
13034 /* Don't move the register if it gets killed in between from and to. */
13035 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13036 && ! reg_referenced_p (x
, maybe_kill_insn
))
13040 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13041 && DF_INSN_LUID (where_dead
) >= from_luid
13042 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13044 rtx note
= remove_death (regno
, where_dead
);
13046 /* It is possible for the call above to return 0. This can occur
13047 when last_death points to I2 or I1 that we combined with.
13048 In that case make a new note.
13050 We must also check for the case where X is a hard register
13051 and NOTE is a death note for a range of hard registers
13052 including X. In that case, we must put REG_DEAD notes for
13053 the remaining registers in place of NOTE. */
13055 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13056 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13057 > GET_MODE_SIZE (GET_MODE (x
))))
13059 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13060 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
13061 unsigned int ourend
= END_HARD_REGNO (x
);
13064 for (i
= deadregno
; i
< deadend
; i
++)
13065 if (i
< regno
|| i
>= ourend
)
13066 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13069 /* If we didn't find any note, or if we found a REG_DEAD note that
13070 covers only part of the given reg, and we have a multi-reg hard
13071 register, then to be safe we must check for REG_DEAD notes
13072 for each register other than the first. They could have
13073 their own REG_DEAD notes lying around. */
13074 else if ((note
== 0
13076 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13077 < GET_MODE_SIZE (GET_MODE (x
)))))
13078 && regno
< FIRST_PSEUDO_REGISTER
13079 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13081 unsigned int ourend
= END_HARD_REGNO (x
);
13082 unsigned int i
, offset
;
13086 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13090 for (i
= regno
+ offset
; i
< ourend
; i
++)
13091 move_deaths (regno_reg_rtx
[i
],
13092 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13095 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13097 XEXP (note
, 1) = *pnotes
;
13101 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13107 else if (GET_CODE (x
) == SET
)
13109 rtx dest
= SET_DEST (x
);
13111 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13113 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13114 that accesses one word of a multi-word item, some
13115 piece of everything register in the expression is used by
13116 this insn, so remove any old death. */
13117 /* ??? So why do we test for equality of the sizes? */
13119 if (GET_CODE (dest
) == ZERO_EXTRACT
13120 || GET_CODE (dest
) == STRICT_LOW_PART
13121 || (GET_CODE (dest
) == SUBREG
13122 && (((GET_MODE_SIZE (GET_MODE (dest
))
13123 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13124 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13125 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13127 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13131 /* If this is some other SUBREG, we know it replaces the entire
13132 value, so use that as the destination. */
13133 if (GET_CODE (dest
) == SUBREG
)
13134 dest
= SUBREG_REG (dest
);
13136 /* If this is a MEM, adjust deaths of anything used in the address.
13137 For a REG (the only other possibility), the entire value is
13138 being replaced so the old value is not used in this insn. */
13141 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13146 else if (GET_CODE (x
) == CLOBBER
)
13149 len
= GET_RTX_LENGTH (code
);
13150 fmt
= GET_RTX_FORMAT (code
);
13152 for (i
= 0; i
< len
; i
++)
13157 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13158 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13161 else if (fmt
[i
] == 'e')
13162 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13166 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13167 pattern of an insn. X must be a REG. */
13170 reg_bitfield_target_p (rtx x
, rtx body
)
13174 if (GET_CODE (body
) == SET
)
13176 rtx dest
= SET_DEST (body
);
13178 unsigned int regno
, tregno
, endregno
, endtregno
;
13180 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13181 target
= XEXP (dest
, 0);
13182 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13183 target
= SUBREG_REG (XEXP (dest
, 0));
13187 if (GET_CODE (target
) == SUBREG
)
13188 target
= SUBREG_REG (target
);
13190 if (!REG_P (target
))
13193 tregno
= REGNO (target
), regno
= REGNO (x
);
13194 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13195 return target
== x
;
13197 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13198 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13200 return endregno
> tregno
&& regno
< endtregno
;
13203 else if (GET_CODE (body
) == PARALLEL
)
13204 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13205 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13211 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13212 as appropriate. I3 and I2 are the insns resulting from the combination
13213 insns including FROM (I2 may be zero).
13215 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13216 not need REG_DEAD notes because they are being substituted for. This
13217 saves searching in the most common cases.
13219 Each note in the list is either ignored or placed on some insns, depending
13220 on the type of note. */
13223 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13224 rtx elim_i1
, rtx elim_i0
)
13226 rtx note
, next_note
;
13229 for (note
= notes
; note
; note
= next_note
)
13231 rtx place
= 0, place2
= 0;
13233 next_note
= XEXP (note
, 1);
13234 switch (REG_NOTE_KIND (note
))
13238 /* Doesn't matter much where we put this, as long as it's somewhere.
13239 It is preferable to keep these notes on branches, which is most
13240 likely to be i3. */
13244 case REG_NON_LOCAL_GOTO
:
13249 gcc_assert (i2
&& JUMP_P (i2
));
13254 case REG_EH_REGION
:
13255 /* These notes must remain with the call or trapping instruction. */
13258 else if (i2
&& CALL_P (i2
))
13262 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13263 if (may_trap_p (i3
))
13265 else if (i2
&& may_trap_p (i2
))
13267 /* ??? Otherwise assume we've combined things such that we
13268 can now prove that the instructions can't trap. Drop the
13269 note in this case. */
13275 /* These notes must remain with the call. It should not be
13276 possible for both I2 and I3 to be a call. */
13281 gcc_assert (i2
&& CALL_P (i2
));
13287 /* Any clobbers for i3 may still exist, and so we must process
13288 REG_UNUSED notes from that insn.
13290 Any clobbers from i2 or i1 can only exist if they were added by
13291 recog_for_combine. In that case, recog_for_combine created the
13292 necessary REG_UNUSED notes. Trying to keep any original
13293 REG_UNUSED notes from these insns can cause incorrect output
13294 if it is for the same register as the original i3 dest.
13295 In that case, we will notice that the register is set in i3,
13296 and then add a REG_UNUSED note for the destination of i3, which
13297 is wrong. However, it is possible to have REG_UNUSED notes from
13298 i2 or i1 for register which were both used and clobbered, so
13299 we keep notes from i2 or i1 if they will turn into REG_DEAD
13302 /* If this register is set or clobbered in I3, put the note there
13303 unless there is one already. */
13304 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13306 if (from_insn
!= i3
)
13309 if (! (REG_P (XEXP (note
, 0))
13310 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13311 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13314 /* Otherwise, if this register is used by I3, then this register
13315 now dies here, so we must put a REG_DEAD note here unless there
13317 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13318 && ! (REG_P (XEXP (note
, 0))
13319 ? find_regno_note (i3
, REG_DEAD
,
13320 REGNO (XEXP (note
, 0)))
13321 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13323 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13331 /* These notes say something about results of an insn. We can
13332 only support them if they used to be on I3 in which case they
13333 remain on I3. Otherwise they are ignored.
13335 If the note refers to an expression that is not a constant, we
13336 must also ignore the note since we cannot tell whether the
13337 equivalence is still true. It might be possible to do
13338 slightly better than this (we only have a problem if I2DEST
13339 or I1DEST is present in the expression), but it doesn't
13340 seem worth the trouble. */
13342 if (from_insn
== i3
13343 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13348 /* These notes say something about how a register is used. They must
13349 be present on any use of the register in I2 or I3. */
13350 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13353 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13362 case REG_LABEL_TARGET
:
13363 case REG_LABEL_OPERAND
:
13364 /* This can show up in several ways -- either directly in the
13365 pattern, or hidden off in the constant pool with (or without?)
13366 a REG_EQUAL note. */
13367 /* ??? Ignore the without-reg_equal-note problem for now. */
13368 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13369 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13370 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13371 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13375 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13376 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13377 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13378 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13386 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13387 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13389 if (place
&& JUMP_P (place
)
13390 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13391 && (JUMP_LABEL (place
) == NULL
13392 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13394 rtx label
= JUMP_LABEL (place
);
13397 JUMP_LABEL (place
) = XEXP (note
, 0);
13398 else if (LABEL_P (label
))
13399 LABEL_NUSES (label
)--;
13402 if (place2
&& JUMP_P (place2
)
13403 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13404 && (JUMP_LABEL (place2
) == NULL
13405 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13407 rtx label
= JUMP_LABEL (place2
);
13410 JUMP_LABEL (place2
) = XEXP (note
, 0);
13411 else if (LABEL_P (label
))
13412 LABEL_NUSES (label
)--;
13418 /* This note says something about the value of a register prior
13419 to the execution of an insn. It is too much trouble to see
13420 if the note is still correct in all situations. It is better
13421 to simply delete it. */
13425 /* If we replaced the right hand side of FROM_INSN with a
13426 REG_EQUAL note, the original use of the dying register
13427 will not have been combined into I3 and I2. In such cases,
13428 FROM_INSN is guaranteed to be the first of the combined
13429 instructions, so we simply need to search back before
13430 FROM_INSN for the previous use or set of this register,
13431 then alter the notes there appropriately.
13433 If the register is used as an input in I3, it dies there.
13434 Similarly for I2, if it is nonzero and adjacent to I3.
13436 If the register is not used as an input in either I3 or I2
13437 and it is not one of the registers we were supposed to eliminate,
13438 there are two possibilities. We might have a non-adjacent I2
13439 or we might have somehow eliminated an additional register
13440 from a computation. For example, we might have had A & B where
13441 we discover that B will always be zero. In this case we will
13442 eliminate the reference to A.
13444 In both cases, we must search to see if we can find a previous
13445 use of A and put the death note there. */
13448 && from_insn
== i2mod
13449 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13454 && CALL_P (from_insn
)
13455 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13457 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13459 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13460 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13462 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13464 && reg_overlap_mentioned_p (XEXP (note
, 0),
13466 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13467 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13474 basic_block bb
= this_basic_block
;
13476 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13478 if (!NONDEBUG_INSN_P (tem
))
13480 if (tem
== BB_HEAD (bb
))
13485 /* If the register is being set at TEM, see if that is all
13486 TEM is doing. If so, delete TEM. Otherwise, make this
13487 into a REG_UNUSED note instead. Don't delete sets to
13488 global register vars. */
13489 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13490 || !global_regs
[REGNO (XEXP (note
, 0))])
13491 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13493 rtx set
= single_set (tem
);
13494 rtx inner_dest
= 0;
13496 rtx cc0_setter
= NULL_RTX
;
13500 for (inner_dest
= SET_DEST (set
);
13501 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13502 || GET_CODE (inner_dest
) == SUBREG
13503 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13504 inner_dest
= XEXP (inner_dest
, 0))
13507 /* Verify that it was the set, and not a clobber that
13508 modified the register.
13510 CC0 targets must be careful to maintain setter/user
13511 pairs. If we cannot delete the setter due to side
13512 effects, mark the user with an UNUSED note instead
13515 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13516 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13518 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13519 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13520 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13524 /* Move the notes and links of TEM elsewhere.
13525 This might delete other dead insns recursively.
13526 First set the pattern to something that won't use
13528 rtx old_notes
= REG_NOTES (tem
);
13530 PATTERN (tem
) = pc_rtx
;
13531 REG_NOTES (tem
) = NULL
;
13533 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13534 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13535 distribute_links (LOG_LINKS (tem
));
13537 SET_INSN_DELETED (tem
);
13542 /* Delete the setter too. */
13545 PATTERN (cc0_setter
) = pc_rtx
;
13546 old_notes
= REG_NOTES (cc0_setter
);
13547 REG_NOTES (cc0_setter
) = NULL
;
13549 distribute_notes (old_notes
, cc0_setter
,
13550 cc0_setter
, NULL_RTX
,
13551 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13552 distribute_links (LOG_LINKS (cc0_setter
));
13554 SET_INSN_DELETED (cc0_setter
);
13555 if (cc0_setter
== i2
)
13562 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13564 /* If there isn't already a REG_UNUSED note, put one
13565 here. Do not place a REG_DEAD note, even if
13566 the register is also used here; that would not
13567 match the algorithm used in lifetime analysis
13568 and can cause the consistency check in the
13569 scheduler to fail. */
13570 if (! find_regno_note (tem
, REG_UNUSED
,
13571 REGNO (XEXP (note
, 0))))
13576 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13578 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13582 /* If we are doing a 3->2 combination, and we have a
13583 register which formerly died in i3 and was not used
13584 by i2, which now no longer dies in i3 and is used in
13585 i2 but does not die in i2, and place is between i2
13586 and i3, then we may need to move a link from place to
13588 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13590 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13591 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13593 struct insn_link
*links
= LOG_LINKS (place
);
13594 LOG_LINKS (place
) = NULL
;
13595 distribute_links (links
);
13600 if (tem
== BB_HEAD (bb
))
13606 /* If the register is set or already dead at PLACE, we needn't do
13607 anything with this note if it is still a REG_DEAD note.
13608 We check here if it is set at all, not if is it totally replaced,
13609 which is what `dead_or_set_p' checks, so also check for it being
13612 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13614 unsigned int regno
= REGNO (XEXP (note
, 0));
13615 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
13617 if (dead_or_set_p (place
, XEXP (note
, 0))
13618 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13620 /* Unless the register previously died in PLACE, clear
13621 last_death. [I no longer understand why this is
13623 if (rsp
->last_death
!= place
)
13624 rsp
->last_death
= 0;
13628 rsp
->last_death
= place
;
13630 /* If this is a death note for a hard reg that is occupying
13631 multiple registers, ensure that we are still using all
13632 parts of the object. If we find a piece of the object
13633 that is unused, we must arrange for an appropriate REG_DEAD
13634 note to be added for it. However, we can't just emit a USE
13635 and tag the note to it, since the register might actually
13636 be dead; so we recourse, and the recursive call then finds
13637 the previous insn that used this register. */
13639 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13640 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13642 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13646 for (i
= regno
; i
< endregno
; i
++)
13647 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13648 && ! find_regno_fusage (place
, USE
, i
))
13649 || dead_or_set_regno_p (place
, i
))
13654 /* Put only REG_DEAD notes for pieces that are
13655 not already dead or set. */
13657 for (i
= regno
; i
< endregno
;
13658 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13660 rtx piece
= regno_reg_rtx
[i
];
13661 basic_block bb
= this_basic_block
;
13663 if (! dead_or_set_p (place
, piece
)
13664 && ! reg_bitfield_target_p (piece
,
13667 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13670 distribute_notes (new_note
, place
, place
,
13671 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13674 else if (! refers_to_regno_p (i
, i
+ 1,
13675 PATTERN (place
), 0)
13676 && ! find_regno_fusage (place
, USE
, i
))
13677 for (tem
= PREV_INSN (place
); ;
13678 tem
= PREV_INSN (tem
))
13680 if (!NONDEBUG_INSN_P (tem
))
13682 if (tem
== BB_HEAD (bb
))
13686 if (dead_or_set_p (tem
, piece
)
13687 || reg_bitfield_target_p (piece
,
13690 add_reg_note (tem
, REG_UNUSED
, piece
);
13704 /* Any other notes should not be present at this point in the
13706 gcc_unreachable ();
13711 XEXP (note
, 1) = REG_NOTES (place
);
13712 REG_NOTES (place
) = note
;
13716 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13720 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13721 I3, I2, and I1 to new locations. This is also called to add a link
13722 pointing at I3 when I3's destination is changed. */
13725 distribute_links (struct insn_link
*links
)
13727 struct insn_link
*link
, *next_link
;
13729 for (link
= links
; link
; link
= next_link
)
13735 next_link
= link
->next
;
13737 /* If the insn that this link points to is a NOTE or isn't a single
13738 set, ignore it. In the latter case, it isn't clear what we
13739 can do other than ignore the link, since we can't tell which
13740 register it was for. Such links wouldn't be used by combine
13743 It is not possible for the destination of the target of the link to
13744 have been changed by combine. The only potential of this is if we
13745 replace I3, I2, and I1 by I3 and I2. But in that case the
13746 destination of I2 also remains unchanged. */
13748 if (NOTE_P (link
->insn
)
13749 || (set
= single_set (link
->insn
)) == 0)
13752 reg
= SET_DEST (set
);
13753 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13754 || GET_CODE (reg
) == STRICT_LOW_PART
)
13755 reg
= XEXP (reg
, 0);
13757 /* A LOG_LINK is defined as being placed on the first insn that uses
13758 a register and points to the insn that sets the register. Start
13759 searching at the next insn after the target of the link and stop
13760 when we reach a set of the register or the end of the basic block.
13762 Note that this correctly handles the link that used to point from
13763 I3 to I2. Also note that not much searching is typically done here
13764 since most links don't point very far away. */
13766 for (insn
= NEXT_INSN (link
->insn
);
13767 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13768 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13769 insn
= NEXT_INSN (insn
))
13770 if (DEBUG_INSN_P (insn
))
13772 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13774 if (reg_referenced_p (reg
, PATTERN (insn
)))
13778 else if (CALL_P (insn
)
13779 && find_reg_fusage (insn
, USE
, reg
))
13784 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13787 /* If we found a place to put the link, place it there unless there
13788 is already a link to the same insn as LINK at that point. */
13792 struct insn_link
*link2
;
13794 FOR_EACH_LOG_LINK (link2
, place
)
13795 if (link2
->insn
== link
->insn
)
13800 link
->next
= LOG_LINKS (place
);
13801 LOG_LINKS (place
) = link
;
13803 /* Set added_links_insn to the earliest insn we added a
13805 if (added_links_insn
== 0
13806 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13807 added_links_insn
= place
;
13813 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13814 Check whether the expression pointer to by LOC is a register or
13815 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13816 Otherwise return zero. */
13819 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13824 && (REG_P (x
) || MEM_P (x
))
13825 && ! reg_mentioned_p (x
, (rtx
) expr
))
13830 /* Check for any register or memory mentioned in EQUIV that is not
13831 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13832 of EXPR where some registers may have been replaced by constants. */
13835 unmentioned_reg_p (rtx equiv
, rtx expr
)
13837 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13841 dump_combine_stats (FILE *file
)
13845 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13846 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13850 dump_combine_total_stats (FILE *file
)
13854 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13855 total_attempts
, total_merges
, total_extras
, total_successes
);
13859 gate_handle_combine (void)
13861 return (optimize
> 0);
13864 /* Try combining insns through substitution. */
13865 static unsigned int
13866 rest_of_handle_combine (void)
13868 int rebuild_jump_labels_after_combine
;
13870 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13871 df_note_add_problem ();
13874 regstat_init_n_sets_and_refs ();
13876 rebuild_jump_labels_after_combine
13877 = combine_instructions (get_insns (), max_reg_num ());
13879 /* Combining insns may have turned an indirect jump into a
13880 direct jump. Rebuild the JUMP_LABEL fields of jumping
13882 if (rebuild_jump_labels_after_combine
)
13884 timevar_push (TV_JUMP
);
13885 rebuild_jump_labels (get_insns ());
13887 timevar_pop (TV_JUMP
);
13890 regstat_free_n_sets_and_refs ();
13894 struct rtl_opt_pass pass_combine
=
13898 "combine", /* name */
13899 gate_handle_combine
, /* gate */
13900 rest_of_handle_combine
, /* execute */
13903 0, /* static_pass_number */
13904 TV_COMBINE
, /* tv_id */
13905 PROP_cfglayout
, /* properties_required */
13906 0, /* properties_provided */
13907 0, /* properties_destroyed */
13908 0, /* todo_flags_start */
13909 TODO_df_finish
| TODO_verify_rtl_sharing
|
13910 TODO_ggc_collect
, /* todo_flags_finish */