1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 /* Number of attempts to combine instructions in this function. */
96 static int combine_attempts
;
98 /* Number of attempts that got as far as substitution in this function. */
100 static int combine_merges
;
102 /* Number of instructions combined with added SETs in this function. */
104 static int combine_extras
;
106 /* Number of instructions combined in this function. */
108 static int combine_successes
;
110 /* Totals over entire compilation. */
112 static int total_attempts
, total_merges
, total_extras
, total_successes
;
115 /* Vector mapping INSN_UIDs to cuids.
116 The cuids are like uids but increase monotonically always.
117 Combine always uses cuids so that it can compare them.
118 But actually renumbering the uids, which we used to do,
119 proves to be a bad idea because it makes it hard to compare
120 the dumps produced by earlier passes with those from later passes. */
122 static int *uid_cuid
;
123 static int max_uid_cuid
;
125 /* Get the cuid of an insn. */
127 #define INSN_CUID(INSN) \
128 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
130 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
131 BITS_PER_WORD would invoke undefined behavior. Work around it. */
133 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
134 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
136 #define nonzero_bits(X, M) \
137 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
139 #define num_sign_bit_copies(X, M) \
140 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno
;
146 /* Record last point of death of (hard or pseudo) register n. */
148 static rtx
*reg_last_death
;
150 /* Record last point of modification of (hard or pseudo) register n. */
152 static rtx
*reg_last_set
;
154 /* Record the cuid of the last insn that invalidated memory
155 (anything that writes memory, and subroutine calls, but not pushes). */
157 static int mem_last_set
;
159 /* Record the cuid of the last CALL_INSN
160 so we can tell whether a potential combination crosses any calls. */
162 static int last_call_cuid
;
164 /* When `subst' is called, this is the insn that is being modified
165 (by combining in a previous insn). The PATTERN of this insn
166 is still the old pattern partially modified and it should not be
167 looked at, but this may be used to examine the successors of the insn
168 to judge whether a simplification is valid. */
170 static rtx subst_insn
;
172 /* This is the lowest CUID that `subst' is currently dealing with.
173 get_last_value will not return a value if the register was set at or
174 after this CUID. If not for this mechanism, we could get confused if
175 I2 or I1 in try_combine were an insn that used the old value of a register
176 to obtain a new value. In that case, we might erroneously get the
177 new value of the register when we wanted the old one. */
179 static int subst_low_cuid
;
181 /* This contains any hard registers that are used in newpat; reg_dead_at_p
182 must consider all these registers to be always live. */
184 static HARD_REG_SET newpat_used_regs
;
186 /* This is an insn to which a LOG_LINKS entry has been added. If this
187 insn is the earlier than I2 or I3, combine should rescan starting at
190 static rtx added_links_insn
;
192 /* Basic block in which we are performing combines. */
193 static basic_block this_basic_block
;
195 /* A bitmap indicating which blocks had registers go dead at entry.
196 After combine, we'll need to re-do global life analysis with
197 those blocks as starting points. */
198 static sbitmap refresh_blocks
;
200 /* The next group of arrays allows the recording of the last value assigned
201 to (hard or pseudo) register n. We use this information to see if an
202 operation being processed is redundant given a prior operation performed
203 on the register. For example, an `and' with a constant is redundant if
204 all the zero bits are already known to be turned off.
206 We use an approach similar to that used by cse, but change it in the
209 (1) We do not want to reinitialize at each label.
210 (2) It is useful, but not critical, to know the actual value assigned
211 to a register. Often just its form is helpful.
213 Therefore, we maintain the following arrays:
215 reg_last_set_value the last value assigned
216 reg_last_set_label records the value of label_tick when the
217 register was assigned
218 reg_last_set_table_tick records the value of label_tick when a
219 value using the register is assigned
220 reg_last_set_invalid set to nonzero when it is not valid
221 to use the value of this register in some
224 To understand the usage of these tables, it is important to understand
225 the distinction between the value in reg_last_set_value being valid
226 and the register being validly contained in some other expression in the
229 Entry I in reg_last_set_value is valid if it is nonzero, and either
230 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
232 Register I may validly appear in any expression returned for the value
233 of another register if reg_n_sets[i] is 1. It may also appear in the
234 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
235 reg_last_set_invalid[j] is zero.
237 If an expression is found in the table containing a register which may
238 not validly appear in an expression, the register is replaced by
239 something that won't match, (clobber (const_int 0)).
241 reg_last_set_invalid[i] is set nonzero when register I is being assigned
242 to and reg_last_set_table_tick[i] == label_tick. */
244 /* Record last value assigned to (hard or pseudo) register n. */
246 static rtx
*reg_last_set_value
;
248 /* Record the value of label_tick when the value for register n is placed in
249 reg_last_set_value[n]. */
251 static int *reg_last_set_label
;
253 /* Record the value of label_tick when an expression involving register n
254 is placed in reg_last_set_value. */
256 static int *reg_last_set_table_tick
;
258 /* Set nonzero if references to register n in expressions should not be
261 static char *reg_last_set_invalid
;
263 /* Incremented for each label. */
265 static int label_tick
;
267 /* Some registers that are set more than once and used in more than one
268 basic block are nevertheless always set in similar ways. For example,
269 a QImode register may be loaded from memory in two places on a machine
270 where byte loads zero extend.
272 We record in the following array what we know about the nonzero
273 bits of a register, specifically which bits are known to be zero.
275 If an entry is zero, it means that we don't know anything special. */
277 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
279 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
280 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
282 static enum machine_mode nonzero_bits_mode
;
284 /* Nonzero if we know that a register has some leading bits that are always
285 equal to the sign bit. */
287 static unsigned char *reg_sign_bit_copies
;
289 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
290 It is zero while computing them and after combine has completed. This
291 former test prevents propagating values based on previously set values,
292 which can be incorrect if a variable is modified in a loop. */
294 static int nonzero_sign_valid
;
296 /* These arrays are maintained in parallel with reg_last_set_value
297 and are used to store the mode in which the register was last set,
298 the bits that were known to be zero when it was last set, and the
299 number of sign bits copies it was known to have when it was last set. */
301 static enum machine_mode
*reg_last_set_mode
;
302 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
303 static char *reg_last_set_sign_bit_copies
;
305 /* Record one modification to rtl structure
306 to be undone by storing old_contents into *where.
307 is_int is 1 if the contents are an int. */
313 union {rtx r
; int i
;} old_contents
;
314 union {rtx
*r
; int *i
;} where
;
317 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
318 num_undo says how many are currently recorded.
320 other_insn is nonzero if we have modified some other insn in the process
321 of working on subst_insn. It must be verified too. */
330 static struct undobuf undobuf
;
332 /* Number of times the pseudo being substituted for
333 was found and replaced. */
335 static int n_occurrences
;
337 static void do_SUBST (rtx
*, rtx
);
338 static void do_SUBST_INT (int *, int);
339 static void init_reg_last_arrays (void);
340 static void setup_incoming_promotions (void);
341 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
342 static int cant_combine_insn_p (rtx
);
343 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
344 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
345 static int contains_muldiv (rtx
);
346 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
347 static void undo_all (void);
348 static void undo_commit (void);
349 static rtx
*find_split_point (rtx
*, rtx
);
350 static rtx
subst (rtx
, rtx
, rtx
, int, int);
351 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
352 static rtx
simplify_if_then_else (rtx
);
353 static rtx
simplify_set (rtx
);
354 static rtx
simplify_logical (rtx
, int);
355 static rtx
expand_compound_operation (rtx
);
356 static rtx
expand_field_assignment (rtx
);
357 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
358 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
359 static rtx
extract_left_shift (rtx
, int);
360 static rtx
make_compound_operation (rtx
, enum rtx_code
);
361 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
362 unsigned HOST_WIDE_INT
*);
363 static rtx
force_to_mode (rtx
, enum machine_mode
,
364 unsigned HOST_WIDE_INT
, rtx
, int);
365 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
366 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
367 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
368 static rtx
make_field_assignment (rtx
);
369 static rtx
apply_distributive_law (rtx
);
370 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
371 unsigned HOST_WIDE_INT
);
372 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
373 rtx
, enum machine_mode
,
374 unsigned HOST_WIDE_INT
);
375 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
377 unsigned HOST_WIDE_INT
);
378 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
381 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
382 enum machine_mode
, unsigned int);
383 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
384 HOST_WIDE_INT
, enum machine_mode
, int *);
385 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
387 static int recog_for_combine (rtx
*, rtx
, rtx
*);
388 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
389 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
390 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
391 static void update_table_tick (rtx
);
392 static void record_value_for_reg (rtx
, rtx
, rtx
);
393 static void check_promoted_subreg (rtx
, rtx
);
394 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
395 static void record_dead_and_set_regs (rtx
);
396 static int get_last_value_validate (rtx
*, rtx
, int, int);
397 static rtx
get_last_value (rtx
);
398 static int use_crosses_set_p (rtx
, int);
399 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
400 static int reg_dead_at_p (rtx
, rtx
);
401 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
402 static int reg_bitfield_target_p (rtx
, rtx
);
403 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
404 static void distribute_links (rtx
);
405 static void mark_used_regs_combine (rtx
);
406 static int insn_cuid (rtx
);
407 static void record_promoted_value (rtx
, rtx
);
408 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
409 static enum rtx_code
combine_reversed_comparison_code (rtx
);
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (rtx
*into
, rtx newval
)
423 if (oldval
== newval
)
426 /* We'd like to catch as many invalid transformations here as
427 possible. Unfortunately, there are way too many mode changes
428 that are perfectly valid, so we'd waste too much effort for
429 little gain doing the checks here. Focus on catching invalid
430 transformations involving integer constants. */
431 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
432 && GET_CODE (newval
) == CONST_INT
)
434 /* Sanity check that we're replacing oldval with a CONST_INT
435 that is a valid sign-extension for the original mode. */
436 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
440 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
441 CONST_INT is not valid, because after the replacement, the
442 original mode would be gone. Unfortunately, we can't tell
443 when do_SUBST is called to replace the operand thereof, so we
444 perform this test on oldval instead, checking whether an
445 invalid replacement took place before we got here. */
446 if ((GET_CODE (oldval
) == SUBREG
447 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
448 || (GET_CODE (oldval
) == ZERO_EXTEND
449 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
454 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
456 buf
= xmalloc (sizeof (struct undo
));
460 buf
->old_contents
.r
= oldval
;
463 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
466 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
468 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
469 for the value of a HOST_WIDE_INT value (including CONST_INT) is
473 do_SUBST_INT (int *into
, int newval
)
478 if (oldval
== newval
)
482 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
484 buf
= xmalloc (sizeof (struct undo
));
488 buf
->old_contents
.i
= oldval
;
491 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
494 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
496 /* Main entry point for combiner. F is the first insn of the function.
497 NREGS is the first unused pseudo-reg number.
499 Return nonzero if the combiner has turned an indirect jump
500 instruction into a direct jump. */
502 combine_instructions (rtx f
, unsigned int nregs
)
509 rtx links
, nextlinks
;
511 int new_direct_jump_p
= 0;
513 combine_attempts
= 0;
516 combine_successes
= 0;
518 combine_max_regno
= nregs
;
520 /* It is not safe to use ordinary gen_lowpart in combine.
521 See comments in gen_lowpart_for_combine. */
522 gen_lowpart
= gen_lowpart_for_combine
;
524 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
525 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
527 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
528 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
530 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
531 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
532 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
533 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
534 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
535 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
537 init_reg_last_arrays ();
539 init_recog_no_volatile ();
541 /* Compute maximum uid value so uid_cuid can be allocated. */
543 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
544 if (INSN_UID (insn
) > i
)
547 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
550 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
552 /* Don't use reg_nonzero_bits when computing it. This can cause problems
553 when, for example, we have j <<= 1 in a loop. */
555 nonzero_sign_valid
= 0;
557 /* Compute the mapping from uids to cuids.
558 Cuids are numbers assigned to insns, like uids,
559 except that cuids increase monotonically through the code.
561 Scan all SETs and see if we can deduce anything about what
562 bits are known to be zero for some registers and how many copies
563 of the sign bit are known to exist for those registers.
565 Also set any known values so that we can use it while searching
566 for what bits are known to be set. */
570 setup_incoming_promotions ();
572 refresh_blocks
= sbitmap_alloc (last_basic_block
);
573 sbitmap_zero (refresh_blocks
);
575 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
577 uid_cuid
[INSN_UID (insn
)] = ++i
;
583 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
585 record_dead_and_set_regs (insn
);
588 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
589 if (REG_NOTE_KIND (links
) == REG_INC
)
590 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
595 if (GET_CODE (insn
) == CODE_LABEL
)
599 nonzero_sign_valid
= 1;
601 /* Now scan all the insns in forward order. */
606 init_reg_last_arrays ();
607 setup_incoming_promotions ();
609 FOR_EACH_BB (this_basic_block
)
611 for (insn
= BB_HEAD (this_basic_block
);
612 insn
!= NEXT_INSN (BB_END (this_basic_block
));
613 insn
= next
? next
: NEXT_INSN (insn
))
617 if (GET_CODE (insn
) == CODE_LABEL
)
620 else if (INSN_P (insn
))
622 /* See if we know about function return values before this
623 insn based upon SUBREG flags. */
624 check_promoted_subreg (insn
, PATTERN (insn
));
626 /* Try this insn with each insn it links back to. */
628 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
629 if ((next
= try_combine (insn
, XEXP (links
, 0),
630 NULL_RTX
, &new_direct_jump_p
)) != 0)
633 /* Try each sequence of three linked insns ending with this one. */
635 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
637 rtx link
= XEXP (links
, 0);
639 /* If the linked insn has been replaced by a note, then there
640 is no point in pursuing this chain any further. */
641 if (GET_CODE (link
) == NOTE
)
644 for (nextlinks
= LOG_LINKS (link
);
646 nextlinks
= XEXP (nextlinks
, 1))
647 if ((next
= try_combine (insn
, link
,
649 &new_direct_jump_p
)) != 0)
654 /* Try to combine a jump insn that uses CC0
655 with a preceding insn that sets CC0, and maybe with its
656 logical predecessor as well.
657 This is how we make decrement-and-branch insns.
658 We need this special code because data flow connections
659 via CC0 do not get entered in LOG_LINKS. */
661 if (GET_CODE (insn
) == JUMP_INSN
662 && (prev
= prev_nonnote_insn (insn
)) != 0
663 && GET_CODE (prev
) == INSN
664 && sets_cc0_p (PATTERN (prev
)))
666 if ((next
= try_combine (insn
, prev
,
667 NULL_RTX
, &new_direct_jump_p
)) != 0)
670 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
671 nextlinks
= XEXP (nextlinks
, 1))
672 if ((next
= try_combine (insn
, prev
,
674 &new_direct_jump_p
)) != 0)
678 /* Do the same for an insn that explicitly references CC0. */
679 if (GET_CODE (insn
) == INSN
680 && (prev
= prev_nonnote_insn (insn
)) != 0
681 && GET_CODE (prev
) == INSN
682 && sets_cc0_p (PATTERN (prev
))
683 && GET_CODE (PATTERN (insn
)) == SET
684 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
686 if ((next
= try_combine (insn
, prev
,
687 NULL_RTX
, &new_direct_jump_p
)) != 0)
690 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
691 nextlinks
= XEXP (nextlinks
, 1))
692 if ((next
= try_combine (insn
, prev
,
694 &new_direct_jump_p
)) != 0)
698 /* Finally, see if any of the insns that this insn links to
699 explicitly references CC0. If so, try this insn, that insn,
700 and its predecessor if it sets CC0. */
701 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
702 if (GET_CODE (XEXP (links
, 0)) == INSN
703 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
704 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
705 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
706 && GET_CODE (prev
) == INSN
707 && sets_cc0_p (PATTERN (prev
))
708 && (next
= try_combine (insn
, XEXP (links
, 0),
709 prev
, &new_direct_jump_p
)) != 0)
713 /* Try combining an insn with two different insns whose results it
715 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
716 for (nextlinks
= XEXP (links
, 1); nextlinks
;
717 nextlinks
= XEXP (nextlinks
, 1))
718 if ((next
= try_combine (insn
, XEXP (links
, 0),
720 &new_direct_jump_p
)) != 0)
723 if (GET_CODE (insn
) != NOTE
)
724 record_dead_and_set_regs (insn
);
733 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
734 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
735 new_direct_jump_p
|= purge_all_dead_edges (0);
736 delete_noop_moves (f
);
738 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
739 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
740 | PROP_KILL_DEAD_CODE
);
743 sbitmap_free (refresh_blocks
);
744 free (reg_nonzero_bits
);
745 free (reg_sign_bit_copies
);
746 free (reg_last_death
);
748 free (reg_last_set_value
);
749 free (reg_last_set_table_tick
);
750 free (reg_last_set_label
);
751 free (reg_last_set_invalid
);
752 free (reg_last_set_mode
);
753 free (reg_last_set_nonzero_bits
);
754 free (reg_last_set_sign_bit_copies
);
758 struct undo
*undo
, *next
;
759 for (undo
= undobuf
.frees
; undo
; undo
= next
)
767 total_attempts
+= combine_attempts
;
768 total_merges
+= combine_merges
;
769 total_extras
+= combine_extras
;
770 total_successes
+= combine_successes
;
772 nonzero_sign_valid
= 0;
773 gen_lowpart
= gen_lowpart_general
;
775 /* Make recognizer allow volatile MEMs again. */
778 return new_direct_jump_p
;
781 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
784 init_reg_last_arrays (void)
786 unsigned int nregs
= combine_max_regno
;
788 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
789 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
790 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
791 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
792 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
793 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
794 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
795 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
796 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
799 /* Set up any promoted values for incoming argument registers. */
802 setup_incoming_promotions (void)
806 enum machine_mode mode
;
808 rtx first
= get_insns ();
810 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
812 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
813 /* Check whether this register can hold an incoming pointer
814 argument. FUNCTION_ARG_REGNO_P tests outgoing register
815 numbers, so translate if necessary due to register windows. */
816 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
817 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
820 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
823 gen_rtx_CLOBBER (mode
, const0_rtx
)));
828 /* Called via note_stores. If X is a pseudo that is narrower than
829 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
831 If we are setting only a portion of X and we can't figure out what
832 portion, assume all bits will be used since we don't know what will
835 Similarly, set how many bits of X are known to be copies of the sign bit
836 at all locations in the function. This is the smallest number implied
840 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
841 void *data ATTRIBUTE_UNUSED
)
845 if (GET_CODE (x
) == REG
846 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
847 /* If this register is undefined at the start of the file, we can't
848 say what its contents were. */
849 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
850 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
852 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
854 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
855 reg_sign_bit_copies
[REGNO (x
)] = 1;
859 /* If this is a complex assignment, see if we can convert it into a
860 simple assignment. */
861 set
= expand_field_assignment (set
);
863 /* If this is a simple assignment, or we have a paradoxical SUBREG,
864 set what we know about X. */
866 if (SET_DEST (set
) == x
867 || (GET_CODE (SET_DEST (set
)) == SUBREG
868 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
869 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
870 && SUBREG_REG (SET_DEST (set
)) == x
))
872 rtx src
= SET_SRC (set
);
874 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
875 /* If X is narrower than a word and SRC is a non-negative
876 constant that would appear negative in the mode of X,
877 sign-extend it for use in reg_nonzero_bits because some
878 machines (maybe most) will actually do the sign-extension
879 and this is the conservative approach.
881 ??? For 2.5, try to tighten up the MD files in this regard
882 instead of this kludge. */
884 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
885 && GET_CODE (src
) == CONST_INT
887 && 0 != (INTVAL (src
)
889 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
890 src
= GEN_INT (INTVAL (src
)
891 | ((HOST_WIDE_INT
) (-1)
892 << GET_MODE_BITSIZE (GET_MODE (x
))));
895 /* Don't call nonzero_bits if it cannot change anything. */
896 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
897 reg_nonzero_bits
[REGNO (x
)]
898 |= nonzero_bits (src
, nonzero_bits_mode
);
899 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
900 if (reg_sign_bit_copies
[REGNO (x
)] == 0
901 || reg_sign_bit_copies
[REGNO (x
)] > num
)
902 reg_sign_bit_copies
[REGNO (x
)] = num
;
906 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
907 reg_sign_bit_copies
[REGNO (x
)] = 1;
912 /* See if INSN can be combined into I3. PRED and SUCC are optionally
913 insns that were previously combined into I3 or that will be combined
914 into the merger of INSN and I3.
916 Return 0 if the combination is not allowed for any reason.
918 If the combination is allowed, *PDEST will be set to the single
919 destination of INSN and *PSRC to the single source, and this function
923 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
924 rtx
*pdest
, rtx
*psrc
)
927 rtx set
= 0, src
, dest
;
932 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
933 && next_active_insn (succ
) == i3
)
934 : next_active_insn (insn
) == i3
);
936 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
937 or a PARALLEL consisting of such a SET and CLOBBERs.
939 If INSN has CLOBBER parallel parts, ignore them for our processing.
940 By definition, these happen during the execution of the insn. When it
941 is merged with another insn, all bets are off. If they are, in fact,
942 needed and aren't also supplied in I3, they may be added by
943 recog_for_combine. Otherwise, it won't match.
945 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
948 Get the source and destination of INSN. If more than one, can't
951 if (GET_CODE (PATTERN (insn
)) == SET
)
952 set
= PATTERN (insn
);
953 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
954 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
956 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
958 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
961 switch (GET_CODE (elt
))
963 /* This is important to combine floating point insns
966 /* Combining an isolated USE doesn't make sense.
967 We depend here on combinable_i3pat to reject them. */
968 /* The code below this loop only verifies that the inputs of
969 the SET in INSN do not change. We call reg_set_between_p
970 to verify that the REG in the USE does not change between
972 If the USE in INSN was for a pseudo register, the matching
973 insn pattern will likely match any register; combining this
974 with any other USE would only be safe if we knew that the
975 used registers have identical values, or if there was
976 something to tell them apart, e.g. different modes. For
977 now, we forgo such complicated tests and simply disallow
978 combining of USES of pseudo registers with any other USE. */
979 if (GET_CODE (XEXP (elt
, 0)) == REG
980 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
982 rtx i3pat
= PATTERN (i3
);
983 int i
= XVECLEN (i3pat
, 0) - 1;
984 unsigned int regno
= REGNO (XEXP (elt
, 0));
988 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
990 if (GET_CODE (i3elt
) == USE
991 && GET_CODE (XEXP (i3elt
, 0)) == REG
992 && (REGNO (XEXP (i3elt
, 0)) == regno
993 ? reg_set_between_p (XEXP (elt
, 0),
994 PREV_INSN (insn
), i3
)
995 : regno
>= FIRST_PSEUDO_REGISTER
))
1002 /* We can ignore CLOBBERs. */
1007 /* Ignore SETs whose result isn't used but not those that
1008 have side-effects. */
1009 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1010 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1011 || INTVAL (XEXP (note
, 0)) <= 0)
1012 && ! side_effects_p (elt
))
1015 /* If we have already found a SET, this is a second one and
1016 so we cannot combine with this insn. */
1024 /* Anything else means we can't combine. */
1030 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1031 so don't do anything with it. */
1032 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1041 set
= expand_field_assignment (set
);
1042 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1044 /* Don't eliminate a store in the stack pointer. */
1045 if (dest
== stack_pointer_rtx
1046 /* Don't combine with an insn that sets a register to itself if it has
1047 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1048 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1049 /* Can't merge an ASM_OPERANDS. */
1050 || GET_CODE (src
) == ASM_OPERANDS
1051 /* Can't merge a function call. */
1052 || GET_CODE (src
) == CALL
1053 /* Don't eliminate a function call argument. */
1054 || (GET_CODE (i3
) == CALL_INSN
1055 && (find_reg_fusage (i3
, USE
, dest
)
1056 || (GET_CODE (dest
) == REG
1057 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1058 && global_regs
[REGNO (dest
)])))
1059 /* Don't substitute into an incremented register. */
1060 || FIND_REG_INC_NOTE (i3
, dest
)
1061 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1063 /* Don't combine the end of a libcall into anything. */
1064 /* ??? This gives worse code, and appears to be unnecessary, since no
1065 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1066 use REG_RETVAL notes for noconflict blocks, but other code here
1067 makes sure that those insns don't disappear. */
1068 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1070 /* Make sure that DEST is not used after SUCC but before I3. */
1071 || (succ
&& ! all_adjacent
1072 && reg_used_between_p (dest
, succ
, i3
))
1073 /* Make sure that the value that is to be substituted for the register
1074 does not use any registers whose values alter in between. However,
1075 If the insns are adjacent, a use can't cross a set even though we
1076 think it might (this can happen for a sequence of insns each setting
1077 the same destination; reg_last_set of that register might point to
1078 a NOTE). If INSN has a REG_EQUIV note, the register is always
1079 equivalent to the memory so the substitution is valid even if there
1080 are intervening stores. Also, don't move a volatile asm or
1081 UNSPEC_VOLATILE across any other insns. */
1083 && (((GET_CODE (src
) != MEM
1084 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1085 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1086 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1087 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1088 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1089 better register allocation by not doing the combine. */
1090 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1091 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1092 /* Don't combine across a CALL_INSN, because that would possibly
1093 change whether the life span of some REGs crosses calls or not,
1094 and it is a pain to update that information.
1095 Exception: if source is a constant, moving it later can't hurt.
1096 Accept that special case, because it helps -fforce-addr a lot. */
1097 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1100 /* DEST must either be a REG or CC0. */
1101 if (GET_CODE (dest
) == REG
)
1103 /* If register alignment is being enforced for multi-word items in all
1104 cases except for parameters, it is possible to have a register copy
1105 insn referencing a hard register that is not allowed to contain the
1106 mode being copied and which would not be valid as an operand of most
1107 insns. Eliminate this problem by not combining with such an insn.
1109 Also, on some machines we don't want to extend the life of a hard
1112 if (GET_CODE (src
) == REG
1113 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1114 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1115 /* Don't extend the life of a hard register unless it is
1116 user variable (if we have few registers) or it can't
1117 fit into the desired register (meaning something special
1119 Also avoid substituting a return register into I3, because
1120 reload can't handle a conflict with constraints of other
1122 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1123 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1126 else if (GET_CODE (dest
) != CC0
)
1129 /* Don't substitute for a register intended as a clobberable operand.
1130 Similarly, don't substitute an expression containing a register that
1131 will be clobbered in I3. */
1132 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1133 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1134 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1135 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1137 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1140 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1141 or not), reject, unless nothing volatile comes between it and I3 */
1143 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1145 /* Make sure succ doesn't contain a volatile reference. */
1146 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1149 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1150 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1154 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1155 to be an explicit register variable, and was chosen for a reason. */
1157 if (GET_CODE (src
) == ASM_OPERANDS
1158 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1161 /* If there are any volatile insns between INSN and I3, reject, because
1162 they might affect machine state. */
1164 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1165 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1168 /* If INSN or I2 contains an autoincrement or autodecrement,
1169 make sure that register is not used between there and I3,
1170 and not already used in I3 either.
1171 Also insist that I3 not be a jump; if it were one
1172 and the incremented register were spilled, we would lose. */
1175 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1176 if (REG_NOTE_KIND (link
) == REG_INC
1177 && (GET_CODE (i3
) == JUMP_INSN
1178 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1179 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1184 /* Don't combine an insn that follows a CC0-setting insn.
1185 An insn that uses CC0 must not be separated from the one that sets it.
1186 We do, however, allow I2 to follow a CC0-setting insn if that insn
1187 is passed as I1; in that case it will be deleted also.
1188 We also allow combining in this case if all the insns are adjacent
1189 because that would leave the two CC0 insns adjacent as well.
1190 It would be more logical to test whether CC0 occurs inside I1 or I2,
1191 but that would be much slower, and this ought to be equivalent. */
1193 p
= prev_nonnote_insn (insn
);
1194 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1199 /* If we get here, we have passed all the tests and the combination is
1208 /* LOC is the location within I3 that contains its pattern or the component
1209 of a PARALLEL of the pattern. We validate that it is valid for combining.
1211 One problem is if I3 modifies its output, as opposed to replacing it
1212 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1213 so would produce an insn that is not equivalent to the original insns.
1217 (set (reg:DI 101) (reg:DI 100))
1218 (set (subreg:SI (reg:DI 101) 0) <foo>)
1220 This is NOT equivalent to:
1222 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1223 (set (reg:DI 101) (reg:DI 100))])
1225 Not only does this modify 100 (in which case it might still be valid
1226 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1228 We can also run into a problem if I2 sets a register that I1
1229 uses and I1 gets directly substituted into I3 (not via I2). In that
1230 case, we would be getting the wrong value of I2DEST into I3, so we
1231 must reject the combination. This case occurs when I2 and I1 both
1232 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1233 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1234 of a SET must prevent combination from occurring.
1236 Before doing the above check, we first try to expand a field assignment
1237 into a set of logical operations.
1239 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1240 we place a register that is both set and used within I3. If more than one
1241 such register is detected, we fail.
1243 Return 1 if the combination is valid, zero otherwise. */
1246 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1247 int i1_not_in_src
, rtx
*pi3dest_killed
)
1251 if (GET_CODE (x
) == SET
)
1254 rtx dest
= SET_DEST (set
);
1255 rtx src
= SET_SRC (set
);
1256 rtx inner_dest
= dest
;
1258 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1259 || GET_CODE (inner_dest
) == SUBREG
1260 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1261 inner_dest
= XEXP (inner_dest
, 0);
1263 /* Check for the case where I3 modifies its output, as discussed
1264 above. We don't want to prevent pseudos from being combined
1265 into the address of a MEM, so only prevent the combination if
1266 i1 or i2 set the same MEM. */
1267 if ((inner_dest
!= dest
&&
1268 (GET_CODE (inner_dest
) != MEM
1269 || rtx_equal_p (i2dest
, inner_dest
)
1270 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1271 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1272 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1274 /* This is the same test done in can_combine_p except we can't test
1275 all_adjacent; we don't have to, since this instruction will stay
1276 in place, thus we are not considering increasing the lifetime of
1279 Also, if this insn sets a function argument, combining it with
1280 something that might need a spill could clobber a previous
1281 function argument; the all_adjacent test in can_combine_p also
1282 checks this; here, we do a more specific test for this case. */
1284 || (GET_CODE (inner_dest
) == REG
1285 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1286 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1287 GET_MODE (inner_dest
))))
1288 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1291 /* If DEST is used in I3, it is being killed in this insn,
1292 so record that for later.
1293 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1294 STACK_POINTER_REGNUM, since these are always considered to be
1295 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1296 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1297 && reg_referenced_p (dest
, PATTERN (i3
))
1298 && REGNO (dest
) != FRAME_POINTER_REGNUM
1299 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1300 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1302 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1303 && (REGNO (dest
) != ARG_POINTER_REGNUM
1304 || ! fixed_regs
[REGNO (dest
)])
1306 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1308 if (*pi3dest_killed
)
1311 *pi3dest_killed
= dest
;
1315 else if (GET_CODE (x
) == PARALLEL
)
1319 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1320 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1321 i1_not_in_src
, pi3dest_killed
))
1328 /* Return 1 if X is an arithmetic expression that contains a multiplication
1329 and division. We don't count multiplications by powers of two here. */
1332 contains_muldiv (rtx x
)
1334 switch (GET_CODE (x
))
1336 case MOD
: case DIV
: case UMOD
: case UDIV
:
1340 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1341 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1343 switch (GET_RTX_CLASS (GET_CODE (x
)))
1345 case 'c': case '<': case '2':
1346 return contains_muldiv (XEXP (x
, 0))
1347 || contains_muldiv (XEXP (x
, 1));
1350 return contains_muldiv (XEXP (x
, 0));
1358 /* Determine whether INSN can be used in a combination. Return nonzero if
1359 not. This is used in try_combine to detect early some cases where we
1360 can't perform combinations. */
1363 cant_combine_insn_p (rtx insn
)
1368 /* If this isn't really an insn, we can't do anything.
1369 This can occur when flow deletes an insn that it has merged into an
1370 auto-increment address. */
1371 if (! INSN_P (insn
))
1374 /* Never combine loads and stores involving hard regs that are likely
1375 to be spilled. The register allocator can usually handle such
1376 reg-reg moves by tying. If we allow the combiner to make
1377 substitutions of likely-spilled regs, we may abort in reload.
1378 As an exception, we allow combinations involving fixed regs; these are
1379 not available to the register allocator so there's no risk involved. */
1381 set
= single_set (insn
);
1384 src
= SET_SRC (set
);
1385 dest
= SET_DEST (set
);
1386 if (GET_CODE (src
) == SUBREG
)
1387 src
= SUBREG_REG (src
);
1388 if (GET_CODE (dest
) == SUBREG
)
1389 dest
= SUBREG_REG (dest
);
1390 if (REG_P (src
) && REG_P (dest
)
1391 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1392 && ! fixed_regs
[REGNO (src
)]
1393 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1394 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1395 && ! fixed_regs
[REGNO (dest
)]
1396 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1402 /* Adjust INSN after we made a change to its destination.
1404 Changing the destination can invalidate notes that say something about
1405 the results of the insn and a LOG_LINK pointing to the insn. */
1408 adjust_for_new_dest (rtx insn
)
1412 /* For notes, be conservative and simply remove them. */
1413 loc
= ®_NOTES (insn
);
1416 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1417 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1418 *loc
= XEXP (*loc
, 1);
1420 loc
= &XEXP (*loc
, 1);
1423 /* The new insn will have a destination that was previously the destination
1424 of an insn just above it. Call distribute_links to make a LOG_LINK from
1425 the next use of that destination. */
1426 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1429 /* Try to combine the insns I1 and I2 into I3.
1430 Here I1 and I2 appear earlier than I3.
1431 I1 can be zero; then we combine just I2 into I3.
1433 If we are combining three insns and the resulting insn is not recognized,
1434 try splitting it into two insns. If that happens, I2 and I3 are retained
1435 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1438 Return 0 if the combination does not work. Then nothing is changed.
1439 If we did the combination, return the insn at which combine should
1442 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1443 new direct jump instruction. */
1446 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1448 /* New patterns for I3 and I2, respectively. */
1449 rtx newpat
, newi2pat
= 0;
1450 int substed_i2
= 0, substed_i1
= 0;
1451 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1452 int added_sets_1
, added_sets_2
;
1453 /* Total number of SETs to put into I3. */
1455 /* Nonzero if I2's body now appears in I3. */
1457 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1458 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1459 /* Contains I3 if the destination of I3 is used in its source, which means
1460 that the old life of I3 is being killed. If that usage is placed into
1461 I2 and not in I3, a REG_DEAD note must be made. */
1462 rtx i3dest_killed
= 0;
1463 /* SET_DEST and SET_SRC of I2 and I1. */
1464 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1465 /* PATTERN (I2), or a copy of it in certain cases. */
1467 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1468 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1469 int i1_feeds_i3
= 0;
1470 /* Notes that must be added to REG_NOTES in I3 and I2. */
1471 rtx new_i3_notes
, new_i2_notes
;
1472 /* Notes that we substituted I3 into I2 instead of the normal case. */
1473 int i3_subst_into_i2
= 0;
1474 /* Notes that I1, I2 or I3 is a MULT operation. */
1482 /* Exit early if one of the insns involved can't be used for
1484 if (cant_combine_insn_p (i3
)
1485 || cant_combine_insn_p (i2
)
1486 || (i1
&& cant_combine_insn_p (i1
))
1487 /* We also can't do anything if I3 has a
1488 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1491 /* ??? This gives worse code, and appears to be unnecessary, since no
1492 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1493 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1499 undobuf
.other_insn
= 0;
1501 /* Reset the hard register usage information. */
1502 CLEAR_HARD_REG_SET (newpat_used_regs
);
1504 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1505 code below, set I1 to be the earlier of the two insns. */
1506 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1507 temp
= i1
, i1
= i2
, i2
= temp
;
1509 added_links_insn
= 0;
1511 /* First check for one important special-case that the code below will
1512 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1513 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1514 we may be able to replace that destination with the destination of I3.
1515 This occurs in the common code where we compute both a quotient and
1516 remainder into a structure, in which case we want to do the computation
1517 directly into the structure to avoid register-register copies.
1519 Note that this case handles both multiple sets in I2 and also
1520 cases where I2 has a number of CLOBBER or PARALLELs.
1522 We make very conservative checks below and only try to handle the
1523 most common cases of this. For example, we only handle the case
1524 where I2 and I3 are adjacent to avoid making difficult register
1527 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1528 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1529 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1530 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1531 && GET_CODE (PATTERN (i2
)) == PARALLEL
1532 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1533 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1534 below would need to check what is inside (and reg_overlap_mentioned_p
1535 doesn't support those codes anyway). Don't allow those destinations;
1536 the resulting insn isn't likely to be recognized anyway. */
1537 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1538 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1539 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1540 SET_DEST (PATTERN (i3
)))
1541 && next_real_insn (i2
) == i3
)
1543 rtx p2
= PATTERN (i2
);
1545 /* Make sure that the destination of I3,
1546 which we are going to substitute into one output of I2,
1547 is not used within another output of I2. We must avoid making this:
1548 (parallel [(set (mem (reg 69)) ...)
1549 (set (reg 69) ...)])
1550 which is not well-defined as to order of actions.
1551 (Besides, reload can't handle output reloads for this.)
1553 The problem can also happen if the dest of I3 is a memory ref,
1554 if another dest in I2 is an indirect memory ref. */
1555 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1556 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1557 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1558 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1559 SET_DEST (XVECEXP (p2
, 0, i
))))
1562 if (i
== XVECLEN (p2
, 0))
1563 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1564 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1565 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1566 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1571 subst_low_cuid
= INSN_CUID (i2
);
1573 added_sets_2
= added_sets_1
= 0;
1574 i2dest
= SET_SRC (PATTERN (i3
));
1576 /* Replace the dest in I2 with our dest and make the resulting
1577 insn the new pattern for I3. Then skip to where we
1578 validate the pattern. Everything was set up above. */
1579 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1580 SET_DEST (PATTERN (i3
)));
1583 i3_subst_into_i2
= 1;
1584 goto validate_replacement
;
1588 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1589 one of those words to another constant, merge them by making a new
1592 && (temp
= single_set (i2
)) != 0
1593 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1594 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1595 && GET_CODE (SET_DEST (temp
)) == REG
1596 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1597 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1598 && GET_CODE (PATTERN (i3
)) == SET
1599 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1600 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1601 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1602 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1603 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1605 HOST_WIDE_INT lo
, hi
;
1607 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1608 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1611 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1612 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1615 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1617 /* We don't handle the case of the target word being wider
1618 than a host wide int. */
1619 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1622 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1623 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1624 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1626 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1627 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1628 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1630 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1631 >> (HOST_BITS_PER_WIDE_INT
- 1));
1633 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1634 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1635 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1636 (INTVAL (SET_SRC (PATTERN (i3
)))));
1638 hi
= lo
< 0 ? -1 : 0;
1641 /* We don't handle the case of the higher word not fitting
1642 entirely in either hi or lo. */
1647 subst_low_cuid
= INSN_CUID (i2
);
1648 added_sets_2
= added_sets_1
= 0;
1649 i2dest
= SET_DEST (temp
);
1651 SUBST (SET_SRC (temp
),
1652 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1654 newpat
= PATTERN (i2
);
1655 goto validate_replacement
;
1659 /* If we have no I1 and I2 looks like:
1660 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1662 make up a dummy I1 that is
1665 (set (reg:CC X) (compare:CC Y (const_int 0)))
1667 (We can ignore any trailing CLOBBERs.)
1669 This undoes a previous combination and allows us to match a branch-and-
1672 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1673 && XVECLEN (PATTERN (i2
), 0) >= 2
1674 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1675 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1677 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1678 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1679 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1680 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1681 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1682 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1684 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1685 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1690 /* We make I1 with the same INSN_UID as I2. This gives it
1691 the same INSN_CUID for value tracking. Our fake I1 will
1692 never appear in the insn stream so giving it the same INSN_UID
1693 as I2 will not cause a problem. */
1695 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1696 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1697 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1700 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1701 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1702 SET_DEST (PATTERN (i1
)));
1707 /* Verify that I2 and I1 are valid for combining. */
1708 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1709 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1715 /* Record whether I2DEST is used in I2SRC and similarly for the other
1716 cases. Knowing this will help in register status updating below. */
1717 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1718 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1719 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1721 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1723 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1725 /* Ensure that I3's pattern can be the destination of combines. */
1726 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1727 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1734 /* See if any of the insns is a MULT operation. Unless one is, we will
1735 reject a combination that is, since it must be slower. Be conservative
1737 if (GET_CODE (i2src
) == MULT
1738 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1739 || (GET_CODE (PATTERN (i3
)) == SET
1740 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1743 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1744 We used to do this EXCEPT in one case: I3 has a post-inc in an
1745 output operand. However, that exception can give rise to insns like
1747 which is a famous insn on the PDP-11 where the value of r3 used as the
1748 source was model-dependent. Avoid this sort of thing. */
1751 if (!(GET_CODE (PATTERN (i3
)) == SET
1752 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1753 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1754 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1755 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1756 /* It's not the exception. */
1759 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1760 if (REG_NOTE_KIND (link
) == REG_INC
1761 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1763 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1770 /* See if the SETs in I1 or I2 need to be kept around in the merged
1771 instruction: whenever the value set there is still needed past I3.
1772 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1774 For the SET in I1, we have two cases: If I1 and I2 independently
1775 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1776 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1777 in I1 needs to be kept around unless I1DEST dies or is set in either
1778 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1779 I1DEST. If so, we know I1 feeds into I2. */
1781 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1784 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1785 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1787 /* If the set in I2 needs to be kept around, we must make a copy of
1788 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1789 PATTERN (I2), we are only substituting for the original I1DEST, not into
1790 an already-substituted copy. This also prevents making self-referential
1791 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1794 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1795 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1799 i2pat
= copy_rtx (i2pat
);
1803 /* Substitute in the latest insn for the regs set by the earlier ones. */
1805 maxreg
= max_reg_num ();
1809 /* It is possible that the source of I2 or I1 may be performing an
1810 unneeded operation, such as a ZERO_EXTEND of something that is known
1811 to have the high part zero. Handle that case by letting subst look at
1812 the innermost one of them.
1814 Another way to do this would be to have a function that tries to
1815 simplify a single insn instead of merging two or more insns. We don't
1816 do this because of the potential of infinite loops and because
1817 of the potential extra memory required. However, doing it the way
1818 we are is a bit of a kludge and doesn't catch all cases.
1820 But only do this if -fexpensive-optimizations since it slows things down
1821 and doesn't usually win. */
1823 if (flag_expensive_optimizations
)
1825 /* Pass pc_rtx so no substitutions are done, just simplifications.
1826 The cases that we are interested in here do not involve the few
1827 cases were is_replaced is checked. */
1830 subst_low_cuid
= INSN_CUID (i1
);
1831 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1835 subst_low_cuid
= INSN_CUID (i2
);
1836 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1841 /* Many machines that don't use CC0 have insns that can both perform an
1842 arithmetic operation and set the condition code. These operations will
1843 be represented as a PARALLEL with the first element of the vector
1844 being a COMPARE of an arithmetic operation with the constant zero.
1845 The second element of the vector will set some pseudo to the result
1846 of the same arithmetic operation. If we simplify the COMPARE, we won't
1847 match such a pattern and so will generate an extra insn. Here we test
1848 for this case, where both the comparison and the operation result are
1849 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1850 I2SRC. Later we will make the PARALLEL that contains I2. */
1852 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1853 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1854 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1855 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1857 #ifdef SELECT_CC_MODE
1859 enum machine_mode compare_mode
;
1862 newpat
= PATTERN (i3
);
1863 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1867 #ifdef SELECT_CC_MODE
1868 /* See if a COMPARE with the operand we substituted in should be done
1869 with the mode that is currently being used. If not, do the same
1870 processing we do in `subst' for a SET; namely, if the destination
1871 is used only once, try to replace it with a register of the proper
1872 mode and also replace the COMPARE. */
1873 if (undobuf
.other_insn
== 0
1874 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1875 &undobuf
.other_insn
))
1876 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1878 != GET_MODE (SET_DEST (newpat
))))
1880 unsigned int regno
= REGNO (SET_DEST (newpat
));
1881 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1883 if (regno
< FIRST_PSEUDO_REGISTER
1884 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1885 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1887 if (regno
>= FIRST_PSEUDO_REGISTER
)
1888 SUBST (regno_reg_rtx
[regno
], new_dest
);
1890 SUBST (SET_DEST (newpat
), new_dest
);
1891 SUBST (XEXP (*cc_use
, 0), new_dest
);
1892 SUBST (SET_SRC (newpat
),
1893 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1896 undobuf
.other_insn
= 0;
1903 n_occurrences
= 0; /* `subst' counts here */
1905 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1906 need to make a unique copy of I2SRC each time we substitute it
1907 to avoid self-referential rtl. */
1909 subst_low_cuid
= INSN_CUID (i2
);
1910 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1911 ! i1_feeds_i3
&& i1dest_in_i1src
);
1914 /* Record whether i2's body now appears within i3's body. */
1915 i2_is_used
= n_occurrences
;
1918 /* If we already got a failure, don't try to do more. Otherwise,
1919 try to substitute in I1 if we have it. */
1921 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1923 /* Before we can do this substitution, we must redo the test done
1924 above (see detailed comments there) that ensures that I1DEST
1925 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1927 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1935 subst_low_cuid
= INSN_CUID (i1
);
1936 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1940 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1941 to count all the ways that I2SRC and I1SRC can be used. */
1942 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1943 && i2_is_used
+ added_sets_2
> 1)
1944 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1945 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1947 /* Fail if we tried to make a new register (we used to abort, but there's
1948 really no reason to). */
1949 || max_reg_num () != maxreg
1950 /* Fail if we couldn't do something and have a CLOBBER. */
1951 || GET_CODE (newpat
) == CLOBBER
1952 /* Fail if this new pattern is a MULT and we didn't have one before
1953 at the outer level. */
1954 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1961 /* If the actions of the earlier insns must be kept
1962 in addition to substituting them into the latest one,
1963 we must make a new PARALLEL for the latest insn
1964 to hold additional the SETs. */
1966 if (added_sets_1
|| added_sets_2
)
1970 if (GET_CODE (newpat
) == PARALLEL
)
1972 rtvec old
= XVEC (newpat
, 0);
1973 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1974 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1975 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1976 sizeof (old
->elem
[0]) * old
->num_elem
);
1981 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1982 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1983 XVECEXP (newpat
, 0, 0) = old
;
1987 XVECEXP (newpat
, 0, --total_sets
)
1988 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1989 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1993 /* If there is no I1, use I2's body as is. We used to also not do
1994 the subst call below if I2 was substituted into I3,
1995 but that could lose a simplification. */
1997 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1999 /* See comment where i2pat is assigned. */
2000 XVECEXP (newpat
, 0, --total_sets
)
2001 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2005 /* We come here when we are replacing a destination in I2 with the
2006 destination of I3. */
2007 validate_replacement
:
2009 /* Note which hard regs this insn has as inputs. */
2010 mark_used_regs_combine (newpat
);
2012 /* Is the result of combination a valid instruction? */
2013 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2015 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2016 the second SET's destination is a register that is unused and isn't
2017 marked as an instruction that might trap in an EH region. In that case,
2018 we just need the first SET. This can occur when simplifying a divmod
2019 insn. We *must* test for this case here because the code below that
2020 splits two independent SETs doesn't handle this case correctly when it
2021 updates the register status.
2023 It's pointless doing this if we originally had two sets, one from
2024 i3, and one from i2. Combining then splitting the parallel results
2025 in the original i2 again plus an invalid insn (which we delete).
2026 The net effect is only to move instructions around, which makes
2027 debug info less accurate.
2029 Also check the case where the first SET's destination is unused.
2030 That would not cause incorrect code, but does cause an unneeded
2033 if (insn_code_number
< 0
2034 && !(added_sets_2
&& i1
== 0)
2035 && GET_CODE (newpat
) == PARALLEL
2036 && XVECLEN (newpat
, 0) == 2
2037 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2038 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2039 && asm_noperands (newpat
) < 0)
2041 rtx set0
= XVECEXP (newpat
, 0, 0);
2042 rtx set1
= XVECEXP (newpat
, 0, 1);
2045 if (((GET_CODE (SET_DEST (set1
)) == REG
2046 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2047 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2048 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2049 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2050 || INTVAL (XEXP (note
, 0)) <= 0)
2051 && ! side_effects_p (SET_SRC (set1
)))
2054 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2057 else if (((GET_CODE (SET_DEST (set0
)) == REG
2058 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2059 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2060 && find_reg_note (i3
, REG_UNUSED
,
2061 SUBREG_REG (SET_DEST (set0
)))))
2062 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2063 || INTVAL (XEXP (note
, 0)) <= 0)
2064 && ! side_effects_p (SET_SRC (set0
)))
2067 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2069 if (insn_code_number
>= 0)
2071 /* If we will be able to accept this, we have made a
2072 change to the destination of I3. This requires us to
2073 do a few adjustments. */
2075 PATTERN (i3
) = newpat
;
2076 adjust_for_new_dest (i3
);
2081 /* If we were combining three insns and the result is a simple SET
2082 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2083 insns. There are two ways to do this. It can be split using a
2084 machine-specific method (like when you have an addition of a large
2085 constant) or by combine in the function find_split_point. */
2087 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2088 && asm_noperands (newpat
) < 0)
2090 rtx m_split
, *split
;
2091 rtx ni2dest
= i2dest
;
2093 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2094 use I2DEST as a scratch register will help. In the latter case,
2095 convert I2DEST to the mode of the source of NEWPAT if we can. */
2097 m_split
= split_insns (newpat
, i3
);
2099 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2100 inputs of NEWPAT. */
2102 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2103 possible to try that as a scratch reg. This would require adding
2104 more code to make it work though. */
2106 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2108 /* If I2DEST is a hard register or the only use of a pseudo,
2109 we can change its mode. */
2110 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2111 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2112 && GET_CODE (i2dest
) == REG
2113 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2114 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2115 && ! REG_USERVAR_P (i2dest
))))
2116 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2119 m_split
= split_insns (gen_rtx_PARALLEL
2121 gen_rtvec (2, newpat
,
2122 gen_rtx_CLOBBER (VOIDmode
,
2125 /* If the split with the mode-changed register didn't work, try
2126 the original register. */
2127 if (! m_split
&& ni2dest
!= i2dest
)
2130 m_split
= split_insns (gen_rtx_PARALLEL
2132 gen_rtvec (2, newpat
,
2133 gen_rtx_CLOBBER (VOIDmode
,
2139 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2141 m_split
= PATTERN (m_split
);
2142 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2143 if (insn_code_number
>= 0)
2146 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2147 && (next_real_insn (i2
) == i3
2148 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2151 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2152 newi2pat
= PATTERN (m_split
);
2154 i3set
= single_set (NEXT_INSN (m_split
));
2155 i2set
= single_set (m_split
);
2157 /* In case we changed the mode of I2DEST, replace it in the
2158 pseudo-register table here. We can't do it above in case this
2159 code doesn't get executed and we do a split the other way. */
2161 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2162 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2164 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2166 /* If I2 or I3 has multiple SETs, we won't know how to track
2167 register status, so don't use these insns. If I2's destination
2168 is used between I2 and I3, we also can't use these insns. */
2170 if (i2_code_number
>= 0 && i2set
&& i3set
2171 && (next_real_insn (i2
) == i3
2172 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2173 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2175 if (insn_code_number
>= 0)
2178 /* It is possible that both insns now set the destination of I3.
2179 If so, we must show an extra use of it. */
2181 if (insn_code_number
>= 0)
2183 rtx new_i3_dest
= SET_DEST (i3set
);
2184 rtx new_i2_dest
= SET_DEST (i2set
);
2186 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2187 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2188 || GET_CODE (new_i3_dest
) == SUBREG
)
2189 new_i3_dest
= XEXP (new_i3_dest
, 0);
2191 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2192 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2193 || GET_CODE (new_i2_dest
) == SUBREG
)
2194 new_i2_dest
= XEXP (new_i2_dest
, 0);
2196 if (GET_CODE (new_i3_dest
) == REG
2197 && GET_CODE (new_i2_dest
) == REG
2198 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2199 REG_N_SETS (REGNO (new_i2_dest
))++;
2203 /* If we can split it and use I2DEST, go ahead and see if that
2204 helps things be recognized. Verify that none of the registers
2205 are set between I2 and I3. */
2206 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2208 && GET_CODE (i2dest
) == REG
2210 /* We need I2DEST in the proper mode. If it is a hard register
2211 or the only use of a pseudo, we can change its mode. */
2212 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2213 || GET_MODE (*split
) == VOIDmode
2214 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2215 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2216 && ! REG_USERVAR_P (i2dest
)))
2217 && (next_real_insn (i2
) == i3
2218 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2219 /* We can't overwrite I2DEST if its value is still used by
2221 && ! reg_referenced_p (i2dest
, newpat
))
2223 rtx newdest
= i2dest
;
2224 enum rtx_code split_code
= GET_CODE (*split
);
2225 enum machine_mode split_mode
= GET_MODE (*split
);
2227 /* Get NEWDEST as a register in the proper mode. We have already
2228 validated that we can do this. */
2229 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2231 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2233 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2234 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2237 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2238 an ASHIFT. This can occur if it was inside a PLUS and hence
2239 appeared to be a memory address. This is a kludge. */
2240 if (split_code
== MULT
2241 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2242 && INTVAL (XEXP (*split
, 1)) > 0
2243 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2245 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2246 XEXP (*split
, 0), GEN_INT (i
)));
2247 /* Update split_code because we may not have a multiply
2249 split_code
= GET_CODE (*split
);
2252 #ifdef INSN_SCHEDULING
2253 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2254 be written as a ZERO_EXTEND. */
2255 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2257 #ifdef LOAD_EXTEND_OP
2258 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2259 what it really is. */
2260 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2262 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2263 SUBREG_REG (*split
)));
2266 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2267 SUBREG_REG (*split
)));
2271 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2272 SUBST (*split
, newdest
);
2273 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2275 /* If the split point was a MULT and we didn't have one before,
2276 don't use one now. */
2277 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2278 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2282 /* Check for a case where we loaded from memory in a narrow mode and
2283 then sign extended it, but we need both registers. In that case,
2284 we have a PARALLEL with both loads from the same memory location.
2285 We can split this into a load from memory followed by a register-register
2286 copy. This saves at least one insn, more if register allocation can
2289 We cannot do this if the destination of the first assignment is a
2290 condition code register or cc0. We eliminate this case by making sure
2291 the SET_DEST and SET_SRC have the same mode.
2293 We cannot do this if the destination of the second assignment is
2294 a register that we have already assumed is zero-extended. Similarly
2295 for a SUBREG of such a register. */
2297 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2298 && GET_CODE (newpat
) == PARALLEL
2299 && XVECLEN (newpat
, 0) == 2
2300 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2301 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2302 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2303 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2304 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2305 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2306 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2307 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2309 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2310 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2311 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2312 (GET_CODE (temp
) == REG
2313 && reg_nonzero_bits
[REGNO (temp
)] != 0
2314 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2315 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2316 && (reg_nonzero_bits
[REGNO (temp
)]
2317 != GET_MODE_MASK (word_mode
))))
2318 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2319 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2320 (GET_CODE (temp
) == REG
2321 && reg_nonzero_bits
[REGNO (temp
)] != 0
2322 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2323 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2324 && (reg_nonzero_bits
[REGNO (temp
)]
2325 != GET_MODE_MASK (word_mode
)))))
2326 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2327 SET_SRC (XVECEXP (newpat
, 0, 1)))
2328 && ! find_reg_note (i3
, REG_UNUSED
,
2329 SET_DEST (XVECEXP (newpat
, 0, 0))))
2333 newi2pat
= XVECEXP (newpat
, 0, 0);
2334 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2335 newpat
= XVECEXP (newpat
, 0, 1);
2336 SUBST (SET_SRC (newpat
),
2337 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2338 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2340 if (i2_code_number
>= 0)
2341 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2343 if (insn_code_number
>= 0)
2348 /* If we will be able to accept this, we have made a change to the
2349 destination of I3. This requires us to do a few adjustments. */
2350 PATTERN (i3
) = newpat
;
2351 adjust_for_new_dest (i3
);
2353 /* I3 now uses what used to be its destination and which is
2354 now I2's destination. That means we need a LOG_LINK from
2355 I3 to I2. But we used to have one, so we still will.
2357 However, some later insn might be using I2's dest and have
2358 a LOG_LINK pointing at I3. We must remove this link.
2359 The simplest way to remove the link is to point it at I1,
2360 which we know will be a NOTE. */
2362 for (insn
= NEXT_INSN (i3
);
2363 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2364 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2365 insn
= NEXT_INSN (insn
))
2367 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2369 for (link
= LOG_LINKS (insn
); link
;
2370 link
= XEXP (link
, 1))
2371 if (XEXP (link
, 0) == i3
)
2372 XEXP (link
, 0) = i1
;
2380 /* Similarly, check for a case where we have a PARALLEL of two independent
2381 SETs but we started with three insns. In this case, we can do the sets
2382 as two separate insns. This case occurs when some SET allows two
2383 other insns to combine, but the destination of that SET is still live. */
2385 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2386 && GET_CODE (newpat
) == PARALLEL
2387 && XVECLEN (newpat
, 0) == 2
2388 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2389 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2390 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2391 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2392 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2393 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2394 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2396 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2397 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2398 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2399 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2400 XVECEXP (newpat
, 0, 0))
2401 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2402 XVECEXP (newpat
, 0, 1))
2403 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2404 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2406 /* Normally, it doesn't matter which of the two is done first,
2407 but it does if one references cc0. In that case, it has to
2410 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2412 newi2pat
= XVECEXP (newpat
, 0, 0);
2413 newpat
= XVECEXP (newpat
, 0, 1);
2418 newi2pat
= XVECEXP (newpat
, 0, 1);
2419 newpat
= XVECEXP (newpat
, 0, 0);
2422 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2424 if (i2_code_number
>= 0)
2425 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2428 /* If it still isn't recognized, fail and change things back the way they
2430 if ((insn_code_number
< 0
2431 /* Is the result a reasonable ASM_OPERANDS? */
2432 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2438 /* If we had to change another insn, make sure it is valid also. */
2439 if (undobuf
.other_insn
)
2441 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2442 rtx new_other_notes
;
2445 CLEAR_HARD_REG_SET (newpat_used_regs
);
2447 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2450 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2456 PATTERN (undobuf
.other_insn
) = other_pat
;
2458 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2459 are still valid. Then add any non-duplicate notes added by
2460 recog_for_combine. */
2461 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2463 next
= XEXP (note
, 1);
2465 if (REG_NOTE_KIND (note
) == REG_UNUSED
2466 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2468 if (GET_CODE (XEXP (note
, 0)) == REG
)
2469 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2471 remove_note (undobuf
.other_insn
, note
);
2475 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2476 if (GET_CODE (XEXP (note
, 0)) == REG
)
2477 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2479 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2480 undobuf
.other_insn
, NULL_RTX
);
2483 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2484 they are adjacent to each other or not. */
2486 rtx p
= prev_nonnote_insn (i3
);
2487 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2488 && sets_cc0_p (newi2pat
))
2496 /* We now know that we can do this combination. Merge the insns and
2497 update the status of registers and LOG_LINKS. */
2500 rtx i3notes
, i2notes
, i1notes
= 0;
2501 rtx i3links
, i2links
, i1links
= 0;
2505 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2507 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2508 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2510 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2512 /* Ensure that we do not have something that should not be shared but
2513 occurs multiple times in the new insns. Check this by first
2514 resetting all the `used' flags and then copying anything is shared. */
2516 reset_used_flags (i3notes
);
2517 reset_used_flags (i2notes
);
2518 reset_used_flags (i1notes
);
2519 reset_used_flags (newpat
);
2520 reset_used_flags (newi2pat
);
2521 if (undobuf
.other_insn
)
2522 reset_used_flags (PATTERN (undobuf
.other_insn
));
2524 i3notes
= copy_rtx_if_shared (i3notes
);
2525 i2notes
= copy_rtx_if_shared (i2notes
);
2526 i1notes
= copy_rtx_if_shared (i1notes
);
2527 newpat
= copy_rtx_if_shared (newpat
);
2528 newi2pat
= copy_rtx_if_shared (newi2pat
);
2529 if (undobuf
.other_insn
)
2530 reset_used_flags (PATTERN (undobuf
.other_insn
));
2532 INSN_CODE (i3
) = insn_code_number
;
2533 PATTERN (i3
) = newpat
;
2535 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2537 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2539 reset_used_flags (call_usage
);
2540 call_usage
= copy_rtx (call_usage
);
2543 replace_rtx (call_usage
, i2dest
, i2src
);
2546 replace_rtx (call_usage
, i1dest
, i1src
);
2548 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2551 if (undobuf
.other_insn
)
2552 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2554 /* We had one special case above where I2 had more than one set and
2555 we replaced a destination of one of those sets with the destination
2556 of I3. In that case, we have to update LOG_LINKS of insns later
2557 in this basic block. Note that this (expensive) case is rare.
2559 Also, in this case, we must pretend that all REG_NOTEs for I2
2560 actually came from I3, so that REG_UNUSED notes from I2 will be
2561 properly handled. */
2563 if (i3_subst_into_i2
)
2565 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2566 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2567 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2568 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2569 && ! find_reg_note (i2
, REG_UNUSED
,
2570 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2571 for (temp
= NEXT_INSN (i2
);
2572 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2573 || BB_HEAD (this_basic_block
) != temp
);
2574 temp
= NEXT_INSN (temp
))
2575 if (temp
!= i3
&& INSN_P (temp
))
2576 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2577 if (XEXP (link
, 0) == i2
)
2578 XEXP (link
, 0) = i3
;
2583 while (XEXP (link
, 1))
2584 link
= XEXP (link
, 1);
2585 XEXP (link
, 1) = i2notes
;
2599 INSN_CODE (i2
) = i2_code_number
;
2600 PATTERN (i2
) = newi2pat
;
2604 PUT_CODE (i2
, NOTE
);
2605 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2606 NOTE_SOURCE_FILE (i2
) = 0;
2613 PUT_CODE (i1
, NOTE
);
2614 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2615 NOTE_SOURCE_FILE (i1
) = 0;
2618 /* Get death notes for everything that is now used in either I3 or
2619 I2 and used to die in a previous insn. If we built two new
2620 patterns, move from I1 to I2 then I2 to I3 so that we get the
2621 proper movement on registers that I2 modifies. */
2625 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2626 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2629 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2632 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2634 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2636 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2638 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2640 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2642 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2643 know these are REG_UNUSED and want them to go to the desired insn,
2644 so we always pass it as i3. We have not counted the notes in
2645 reg_n_deaths yet, so we need to do so now. */
2647 if (newi2pat
&& new_i2_notes
)
2649 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2650 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2651 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2653 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2658 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2659 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2660 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2662 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2665 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2666 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2667 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2668 in that case, it might delete I2. Similarly for I2 and I1.
2669 Show an additional death due to the REG_DEAD note we make here. If
2670 we discard it in distribute_notes, we will decrement it again. */
2674 if (GET_CODE (i3dest_killed
) == REG
)
2675 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2677 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2680 NULL_RTX
, i2
, NULL_RTX
);
2682 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2684 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2687 if (i2dest_in_i2src
)
2689 if (GET_CODE (i2dest
) == REG
)
2690 REG_N_DEATHS (REGNO (i2dest
))++;
2692 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2693 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2694 NULL_RTX
, i2
, NULL_RTX
);
2696 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2697 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2700 if (i1dest_in_i1src
)
2702 if (GET_CODE (i1dest
) == REG
)
2703 REG_N_DEATHS (REGNO (i1dest
))++;
2705 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2706 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2707 NULL_RTX
, i2
, NULL_RTX
);
2709 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2710 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2713 distribute_links (i3links
);
2714 distribute_links (i2links
);
2715 distribute_links (i1links
);
2717 if (GET_CODE (i2dest
) == REG
)
2720 rtx i2_insn
= 0, i2_val
= 0, set
;
2722 /* The insn that used to set this register doesn't exist, and
2723 this life of the register may not exist either. See if one of
2724 I3's links points to an insn that sets I2DEST. If it does,
2725 that is now the last known value for I2DEST. If we don't update
2726 this and I2 set the register to a value that depended on its old
2727 contents, we will get confused. If this insn is used, thing
2728 will be set correctly in combine_instructions. */
2730 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2731 if ((set
= single_set (XEXP (link
, 0))) != 0
2732 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2733 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2735 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2737 /* If the reg formerly set in I2 died only once and that was in I3,
2738 zero its use count so it won't make `reload' do any work. */
2740 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2741 && ! i2dest_in_i2src
)
2743 regno
= REGNO (i2dest
);
2744 REG_N_SETS (regno
)--;
2748 if (i1
&& GET_CODE (i1dest
) == REG
)
2751 rtx i1_insn
= 0, i1_val
= 0, set
;
2753 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2754 if ((set
= single_set (XEXP (link
, 0))) != 0
2755 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2756 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2758 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2760 regno
= REGNO (i1dest
);
2761 if (! added_sets_1
&& ! i1dest_in_i1src
)
2762 REG_N_SETS (regno
)--;
2765 /* Update reg_nonzero_bits et al for any changes that may have been made
2766 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2767 important. Because newi2pat can affect nonzero_bits of newpat */
2769 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2770 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2772 /* Set new_direct_jump_p if a new return or simple jump instruction
2775 If I3 is now an unconditional jump, ensure that it has a
2776 BARRIER following it since it may have initially been a
2777 conditional jump. It may also be the last nonnote insn. */
2779 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2781 *new_direct_jump_p
= 1;
2782 mark_jump_label (PATTERN (i3
), i3
, 0);
2784 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2785 || GET_CODE (temp
) != BARRIER
)
2786 emit_barrier_after (i3
);
2789 if (undobuf
.other_insn
!= NULL_RTX
2790 && (returnjump_p (undobuf
.other_insn
)
2791 || any_uncondjump_p (undobuf
.other_insn
)))
2793 *new_direct_jump_p
= 1;
2795 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2796 || GET_CODE (temp
) != BARRIER
)
2797 emit_barrier_after (undobuf
.other_insn
);
2800 /* An NOOP jump does not need barrier, but it does need cleaning up
2802 if (GET_CODE (newpat
) == SET
2803 && SET_SRC (newpat
) == pc_rtx
2804 && SET_DEST (newpat
) == pc_rtx
)
2805 *new_direct_jump_p
= 1;
2808 combine_successes
++;
2811 if (added_links_insn
2812 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2813 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2814 return added_links_insn
;
2816 return newi2pat
? i2
: i3
;
2819 /* Undo all the modifications recorded in undobuf. */
2824 struct undo
*undo
, *next
;
2826 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2830 *undo
->where
.i
= undo
->old_contents
.i
;
2832 *undo
->where
.r
= undo
->old_contents
.r
;
2834 undo
->next
= undobuf
.frees
;
2835 undobuf
.frees
= undo
;
2841 /* We've committed to accepting the changes we made. Move all
2842 of the undos to the free list. */
2847 struct undo
*undo
, *next
;
2849 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2852 undo
->next
= undobuf
.frees
;
2853 undobuf
.frees
= undo
;
2859 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2860 where we have an arithmetic expression and return that point. LOC will
2863 try_combine will call this function to see if an insn can be split into
2867 find_split_point (rtx
*loc
, rtx insn
)
2870 enum rtx_code code
= GET_CODE (x
);
2872 unsigned HOST_WIDE_INT len
= 0;
2873 HOST_WIDE_INT pos
= 0;
2875 rtx inner
= NULL_RTX
;
2877 /* First special-case some codes. */
2881 #ifdef INSN_SCHEDULING
2882 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2884 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2887 return find_split_point (&SUBREG_REG (x
), insn
);
2891 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2892 using LO_SUM and HIGH. */
2893 if (GET_CODE (XEXP (x
, 0)) == CONST
2894 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2897 gen_rtx_LO_SUM (Pmode
,
2898 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2900 return &XEXP (XEXP (x
, 0), 0);
2904 /* If we have a PLUS whose second operand is a constant and the
2905 address is not valid, perhaps will can split it up using
2906 the machine-specific way to split large constants. We use
2907 the first pseudo-reg (one of the virtual regs) as a placeholder;
2908 it will not remain in the result. */
2909 if (GET_CODE (XEXP (x
, 0)) == PLUS
2910 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2911 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2913 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2914 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2917 /* This should have produced two insns, each of which sets our
2918 placeholder. If the source of the second is a valid address,
2919 we can make put both sources together and make a split point
2923 && NEXT_INSN (seq
) != NULL_RTX
2924 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2925 && GET_CODE (seq
) == INSN
2926 && GET_CODE (PATTERN (seq
)) == SET
2927 && SET_DEST (PATTERN (seq
)) == reg
2928 && ! reg_mentioned_p (reg
,
2929 SET_SRC (PATTERN (seq
)))
2930 && GET_CODE (NEXT_INSN (seq
)) == INSN
2931 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2932 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2933 && memory_address_p (GET_MODE (x
),
2934 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2936 rtx src1
= SET_SRC (PATTERN (seq
));
2937 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2939 /* Replace the placeholder in SRC2 with SRC1. If we can
2940 find where in SRC2 it was placed, that can become our
2941 split point and we can replace this address with SRC2.
2942 Just try two obvious places. */
2944 src2
= replace_rtx (src2
, reg
, src1
);
2946 if (XEXP (src2
, 0) == src1
)
2947 split
= &XEXP (src2
, 0);
2948 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2949 && XEXP (XEXP (src2
, 0), 0) == src1
)
2950 split
= &XEXP (XEXP (src2
, 0), 0);
2954 SUBST (XEXP (x
, 0), src2
);
2959 /* If that didn't work, perhaps the first operand is complex and
2960 needs to be computed separately, so make a split point there.
2961 This will occur on machines that just support REG + CONST
2962 and have a constant moved through some previous computation. */
2964 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2965 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2966 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2968 return &XEXP (XEXP (x
, 0), 0);
2974 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2975 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2976 we need to put the operand into a register. So split at that
2979 if (SET_DEST (x
) == cc0_rtx
2980 && GET_CODE (SET_SRC (x
)) != COMPARE
2981 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2982 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2983 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2984 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2985 return &SET_SRC (x
);
2988 /* See if we can split SET_SRC as it stands. */
2989 split
= find_split_point (&SET_SRC (x
), insn
);
2990 if (split
&& split
!= &SET_SRC (x
))
2993 /* See if we can split SET_DEST as it stands. */
2994 split
= find_split_point (&SET_DEST (x
), insn
);
2995 if (split
&& split
!= &SET_DEST (x
))
2998 /* See if this is a bitfield assignment with everything constant. If
2999 so, this is an IOR of an AND, so split it into that. */
3000 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3001 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3002 <= HOST_BITS_PER_WIDE_INT
)
3003 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3004 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3005 && GET_CODE (SET_SRC (x
)) == CONST_INT
3006 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3007 + INTVAL (XEXP (SET_DEST (x
), 2)))
3008 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3009 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3011 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3012 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3013 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3014 rtx dest
= XEXP (SET_DEST (x
), 0);
3015 enum machine_mode mode
= GET_MODE (dest
);
3016 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3018 if (BITS_BIG_ENDIAN
)
3019 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3023 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3026 gen_binary (IOR
, mode
,
3027 gen_binary (AND
, mode
, dest
,
3028 gen_int_mode (~(mask
<< pos
),
3030 GEN_INT (src
<< pos
)));
3032 SUBST (SET_DEST (x
), dest
);
3034 split
= find_split_point (&SET_SRC (x
), insn
);
3035 if (split
&& split
!= &SET_SRC (x
))
3039 /* Otherwise, see if this is an operation that we can split into two.
3040 If so, try to split that. */
3041 code
= GET_CODE (SET_SRC (x
));
3046 /* If we are AND'ing with a large constant that is only a single
3047 bit and the result is only being used in a context where we
3048 need to know if it is zero or nonzero, replace it with a bit
3049 extraction. This will avoid the large constant, which might
3050 have taken more than one insn to make. If the constant were
3051 not a valid argument to the AND but took only one insn to make,
3052 this is no worse, but if it took more than one insn, it will
3055 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3056 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3057 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3058 && GET_CODE (SET_DEST (x
)) == REG
3059 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3060 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3061 && XEXP (*split
, 0) == SET_DEST (x
)
3062 && XEXP (*split
, 1) == const0_rtx
)
3064 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3065 XEXP (SET_SRC (x
), 0),
3066 pos
, NULL_RTX
, 1, 1, 0, 0);
3067 if (extraction
!= 0)
3069 SUBST (SET_SRC (x
), extraction
);
3070 return find_split_point (loc
, insn
);
3076 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3077 is known to be on, this can be converted into a NEG of a shift. */
3078 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3079 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3080 && 1 <= (pos
= exact_log2
3081 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3082 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3084 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3088 gen_rtx_LSHIFTRT (mode
,
3089 XEXP (SET_SRC (x
), 0),
3092 split
= find_split_point (&SET_SRC (x
), insn
);
3093 if (split
&& split
!= &SET_SRC (x
))
3099 inner
= XEXP (SET_SRC (x
), 0);
3101 /* We can't optimize if either mode is a partial integer
3102 mode as we don't know how many bits are significant
3104 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3105 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3109 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3115 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3116 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3118 inner
= XEXP (SET_SRC (x
), 0);
3119 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3120 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3122 if (BITS_BIG_ENDIAN
)
3123 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3124 unsignedp
= (code
== ZERO_EXTRACT
);
3132 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3134 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3136 /* For unsigned, we have a choice of a shift followed by an
3137 AND or two shifts. Use two shifts for field sizes where the
3138 constant might be too large. We assume here that we can
3139 always at least get 8-bit constants in an AND insn, which is
3140 true for every current RISC. */
3142 if (unsignedp
&& len
<= 8)
3147 (mode
, gen_lowpart (mode
, inner
),
3149 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3151 split
= find_split_point (&SET_SRC (x
), insn
);
3152 if (split
&& split
!= &SET_SRC (x
))
3159 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3160 gen_rtx_ASHIFT (mode
,
3161 gen_lowpart (mode
, inner
),
3162 GEN_INT (GET_MODE_BITSIZE (mode
)
3164 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3166 split
= find_split_point (&SET_SRC (x
), insn
);
3167 if (split
&& split
!= &SET_SRC (x
))
3172 /* See if this is a simple operation with a constant as the second
3173 operand. It might be that this constant is out of range and hence
3174 could be used as a split point. */
3175 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3176 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3177 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3178 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3179 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3180 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3181 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3183 return &XEXP (SET_SRC (x
), 1);
3185 /* Finally, see if this is a simple operation with its first operand
3186 not in a register. The operation might require this operand in a
3187 register, so return it as a split point. We can always do this
3188 because if the first operand were another operation, we would have
3189 already found it as a split point. */
3190 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3191 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3192 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3193 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3194 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3195 return &XEXP (SET_SRC (x
), 0);
3201 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3202 it is better to write this as (not (ior A B)) so we can split it.
3203 Similarly for IOR. */
3204 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3207 gen_rtx_NOT (GET_MODE (x
),
3208 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3210 XEXP (XEXP (x
, 0), 0),
3211 XEXP (XEXP (x
, 1), 0))));
3212 return find_split_point (loc
, insn
);
3215 /* Many RISC machines have a large set of logical insns. If the
3216 second operand is a NOT, put it first so we will try to split the
3217 other operand first. */
3218 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3220 rtx tem
= XEXP (x
, 0);
3221 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3222 SUBST (XEXP (x
, 1), tem
);
3230 /* Otherwise, select our actions depending on our rtx class. */
3231 switch (GET_RTX_CLASS (code
))
3233 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3235 split
= find_split_point (&XEXP (x
, 2), insn
);
3238 /* ... fall through ... */
3242 split
= find_split_point (&XEXP (x
, 1), insn
);
3245 /* ... fall through ... */
3247 /* Some machines have (and (shift ...) ...) insns. If X is not
3248 an AND, but XEXP (X, 0) is, use it as our split point. */
3249 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3250 return &XEXP (x
, 0);
3252 split
= find_split_point (&XEXP (x
, 0), insn
);
3258 /* Otherwise, we don't have a split point. */
3262 /* Throughout X, replace FROM with TO, and return the result.
3263 The result is TO if X is FROM;
3264 otherwise the result is X, but its contents may have been modified.
3265 If they were modified, a record was made in undobuf so that
3266 undo_all will (among other things) return X to its original state.
3268 If the number of changes necessary is too much to record to undo,
3269 the excess changes are not made, so the result is invalid.
3270 The changes already made can still be undone.
3271 undobuf.num_undo is incremented for such changes, so by testing that
3272 the caller can tell whether the result is valid.
3274 `n_occurrences' is incremented each time FROM is replaced.
3276 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3278 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3279 by copying if `n_occurrences' is nonzero. */
3282 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3284 enum rtx_code code
= GET_CODE (x
);
3285 enum machine_mode op0_mode
= VOIDmode
;
3290 /* Two expressions are equal if they are identical copies of a shared
3291 RTX or if they are both registers with the same register number
3294 #define COMBINE_RTX_EQUAL_P(X,Y) \
3296 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3297 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3299 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3302 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3305 /* If X and FROM are the same register but different modes, they will
3306 not have been seen as equal above. However, flow.c will make a
3307 LOG_LINKS entry for that case. If we do nothing, we will try to
3308 rerecognize our original insn and, when it succeeds, we will
3309 delete the feeding insn, which is incorrect.
3311 So force this insn not to match in this (rare) case. */
3312 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3313 && REGNO (x
) == REGNO (from
))
3314 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3316 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3317 of which may contain things that can be combined. */
3318 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3321 /* It is possible to have a subexpression appear twice in the insn.
3322 Suppose that FROM is a register that appears within TO.
3323 Then, after that subexpression has been scanned once by `subst',
3324 the second time it is scanned, TO may be found. If we were
3325 to scan TO here, we would find FROM within it and create a
3326 self-referent rtl structure which is completely wrong. */
3327 if (COMBINE_RTX_EQUAL_P (x
, to
))
3330 /* Parallel asm_operands need special attention because all of the
3331 inputs are shared across the arms. Furthermore, unsharing the
3332 rtl results in recognition failures. Failure to handle this case
3333 specially can result in circular rtl.
3335 Solve this by doing a normal pass across the first entry of the
3336 parallel, and only processing the SET_DESTs of the subsequent
3339 if (code
== PARALLEL
3340 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3341 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3343 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3345 /* If this substitution failed, this whole thing fails. */
3346 if (GET_CODE (new) == CLOBBER
3347 && XEXP (new, 0) == const0_rtx
)
3350 SUBST (XVECEXP (x
, 0, 0), new);
3352 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3354 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3356 if (GET_CODE (dest
) != REG
3357 && GET_CODE (dest
) != CC0
3358 && GET_CODE (dest
) != PC
)
3360 new = subst (dest
, from
, to
, 0, unique_copy
);
3362 /* If this substitution failed, this whole thing fails. */
3363 if (GET_CODE (new) == CLOBBER
3364 && XEXP (new, 0) == const0_rtx
)
3367 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3373 len
= GET_RTX_LENGTH (code
);
3374 fmt
= GET_RTX_FORMAT (code
);
3376 /* We don't need to process a SET_DEST that is a register, CC0,
3377 or PC, so set up to skip this common case. All other cases
3378 where we want to suppress replacing something inside a
3379 SET_SRC are handled via the IN_DEST operand. */
3381 && (GET_CODE (SET_DEST (x
)) == REG
3382 || GET_CODE (SET_DEST (x
)) == CC0
3383 || GET_CODE (SET_DEST (x
)) == PC
))
3386 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3389 op0_mode
= GET_MODE (XEXP (x
, 0));
3391 for (i
= 0; i
< len
; i
++)
3396 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3398 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3400 new = (unique_copy
&& n_occurrences
3401 ? copy_rtx (to
) : to
);
3406 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3409 /* If this substitution failed, this whole thing
3411 if (GET_CODE (new) == CLOBBER
3412 && XEXP (new, 0) == const0_rtx
)
3416 SUBST (XVECEXP (x
, i
, j
), new);
3419 else if (fmt
[i
] == 'e')
3421 /* If this is a register being set, ignore it. */
3424 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3425 || code
== ZERO_EXTRACT
)
3427 && GET_CODE (new) == REG
)
3430 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3432 /* In general, don't install a subreg involving two
3433 modes not tieable. It can worsen register
3434 allocation, and can even make invalid reload
3435 insns, since the reg inside may need to be copied
3436 from in the outside mode, and that may be invalid
3437 if it is an fp reg copied in integer mode.
3439 We allow two exceptions to this: It is valid if
3440 it is inside another SUBREG and the mode of that
3441 SUBREG and the mode of the inside of TO is
3442 tieable and it is valid if X is a SET that copies
3445 if (GET_CODE (to
) == SUBREG
3446 && ! MODES_TIEABLE_P (GET_MODE (to
),
3447 GET_MODE (SUBREG_REG (to
)))
3448 && ! (code
== SUBREG
3449 && MODES_TIEABLE_P (GET_MODE (x
),
3450 GET_MODE (SUBREG_REG (to
))))
3452 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3455 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3457 #ifdef CANNOT_CHANGE_MODE_CLASS
3459 && GET_CODE (to
) == REG
3460 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3461 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3464 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3467 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3471 /* If we are in a SET_DEST, suppress most cases unless we
3472 have gone inside a MEM, in which case we want to
3473 simplify the address. We assume here that things that
3474 are actually part of the destination have their inner
3475 parts in the first expression. This is true for SUBREG,
3476 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3477 things aside from REG and MEM that should appear in a
3479 new = subst (XEXP (x
, i
), from
, to
,
3481 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3482 || code
== ZERO_EXTRACT
))
3484 && i
== 0), unique_copy
);
3486 /* If we found that we will have to reject this combination,
3487 indicate that by returning the CLOBBER ourselves, rather than
3488 an expression containing it. This will speed things up as
3489 well as prevent accidents where two CLOBBERs are considered
3490 to be equal, thus producing an incorrect simplification. */
3492 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3495 if (GET_CODE (x
) == SUBREG
3496 && (GET_CODE (new) == CONST_INT
3497 || GET_CODE (new) == CONST_DOUBLE
))
3499 enum machine_mode mode
= GET_MODE (x
);
3501 x
= simplify_subreg (GET_MODE (x
), new,
3502 GET_MODE (SUBREG_REG (x
)),
3505 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3507 else if (GET_CODE (new) == CONST_INT
3508 && GET_CODE (x
) == ZERO_EXTEND
)
3510 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3511 new, GET_MODE (XEXP (x
, 0)));
3516 SUBST (XEXP (x
, i
), new);
3521 /* Try to simplify X. If the simplification changed the code, it is likely
3522 that further simplification will help, so loop, but limit the number
3523 of repetitions that will be performed. */
3525 for (i
= 0; i
< 4; i
++)
3527 /* If X is sufficiently simple, don't bother trying to do anything
3529 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3530 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3532 if (GET_CODE (x
) == code
)
3535 code
= GET_CODE (x
);
3537 /* We no longer know the original mode of operand 0 since we
3538 have changed the form of X) */
3539 op0_mode
= VOIDmode
;
3545 /* Simplify X, a piece of RTL. We just operate on the expression at the
3546 outer level; call `subst' to simplify recursively. Return the new
3549 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3550 will be the iteration even if an expression with a code different from
3551 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3554 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3557 enum rtx_code code
= GET_CODE (x
);
3558 enum machine_mode mode
= GET_MODE (x
);
3563 /* If this is a commutative operation, put a constant last and a complex
3564 expression first. We don't need to do this for comparisons here. */
3565 if (GET_RTX_CLASS (code
) == 'c'
3566 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3569 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3570 SUBST (XEXP (x
, 1), temp
);
3573 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3574 sign extension of a PLUS with a constant, reverse the order of the sign
3575 extension and the addition. Note that this not the same as the original
3576 code, but overflow is undefined for signed values. Also note that the
3577 PLUS will have been partially moved "inside" the sign-extension, so that
3578 the first operand of X will really look like:
3579 (ashiftrt (plus (ashift A C4) C5) C4).
3581 (plus (ashiftrt (ashift A C4) C2) C4)
3582 and replace the first operand of X with that expression. Later parts
3583 of this function may simplify the expression further.
3585 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3586 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3587 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3589 We do this to simplify address expressions. */
3591 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3592 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3593 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3594 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3595 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3596 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3597 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3598 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3599 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3600 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3601 XEXP (XEXP (x
, 0), 1))) != 0)
3604 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3605 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3606 INTVAL (XEXP (XEXP (x
, 0), 1)));
3608 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3609 INTVAL (XEXP (XEXP (x
, 0), 1)));
3611 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3614 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3615 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3616 things. Check for cases where both arms are testing the same
3619 Don't do anything if all operands are very simple. */
3621 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3622 || GET_RTX_CLASS (code
) == '<')
3623 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3624 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3625 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3627 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3628 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3629 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3631 || (GET_RTX_CLASS (code
) == '1'
3632 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3633 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3634 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3637 rtx cond
, true_rtx
, false_rtx
;
3639 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3641 /* If everything is a comparison, what we have is highly unlikely
3642 to be simpler, so don't use it. */
3643 && ! (GET_RTX_CLASS (code
) == '<'
3644 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3645 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3647 rtx cop1
= const0_rtx
;
3648 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3650 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3653 /* Simplify the alternative arms; this may collapse the true and
3654 false arms to store-flag values. Be careful to use copy_rtx
3655 here since true_rtx or false_rtx might share RTL with x as a
3656 result of the if_then_else_cond call above. */
3657 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3658 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3660 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3661 is unlikely to be simpler. */
3662 if (general_operand (true_rtx
, VOIDmode
)
3663 && general_operand (false_rtx
, VOIDmode
))
3665 enum rtx_code reversed
;
3667 /* Restarting if we generate a store-flag expression will cause
3668 us to loop. Just drop through in this case. */
3670 /* If the result values are STORE_FLAG_VALUE and zero, we can
3671 just make the comparison operation. */
3672 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3673 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3674 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3675 && ((reversed
= reversed_comparison_code_parts
3676 (cond_code
, cond
, cop1
, NULL
))
3678 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3680 /* Likewise, we can make the negate of a comparison operation
3681 if the result values are - STORE_FLAG_VALUE and zero. */
3682 else if (GET_CODE (true_rtx
) == CONST_INT
3683 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3684 && false_rtx
== const0_rtx
)
3685 x
= simplify_gen_unary (NEG
, mode
,
3686 gen_binary (cond_code
, mode
, cond
,
3689 else if (GET_CODE (false_rtx
) == CONST_INT
3690 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3691 && true_rtx
== const0_rtx
3692 && ((reversed
= reversed_comparison_code_parts
3693 (cond_code
, cond
, cop1
, NULL
))
3695 x
= simplify_gen_unary (NEG
, mode
,
3696 gen_binary (reversed
, mode
,
3700 return gen_rtx_IF_THEN_ELSE (mode
,
3701 gen_binary (cond_code
, VOIDmode
,
3703 true_rtx
, false_rtx
);
3705 code
= GET_CODE (x
);
3706 op0_mode
= VOIDmode
;
3711 /* Try to fold this expression in case we have constants that weren't
3714 switch (GET_RTX_CLASS (code
))
3717 if (op0_mode
== VOIDmode
)
3718 op0_mode
= GET_MODE (XEXP (x
, 0));
3719 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3723 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3724 if (cmp_mode
== VOIDmode
)
3726 cmp_mode
= GET_MODE (XEXP (x
, 1));
3727 if (cmp_mode
== VOIDmode
)
3728 cmp_mode
= op0_mode
;
3730 temp
= simplify_relational_operation (code
, cmp_mode
,
3731 XEXP (x
, 0), XEXP (x
, 1));
3733 #ifdef FLOAT_STORE_FLAG_VALUE
3734 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3736 if (temp
== const0_rtx
)
3737 temp
= CONST0_RTX (mode
);
3739 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3746 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3750 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3751 XEXP (x
, 1), XEXP (x
, 2));
3758 code
= GET_CODE (temp
);
3759 op0_mode
= VOIDmode
;
3760 mode
= GET_MODE (temp
);
3763 /* First see if we can apply the inverse distributive law. */
3764 if (code
== PLUS
|| code
== MINUS
3765 || code
== AND
|| code
== IOR
|| code
== XOR
)
3767 x
= apply_distributive_law (x
);
3768 code
= GET_CODE (x
);
3769 op0_mode
= VOIDmode
;
3772 /* If CODE is an associative operation not otherwise handled, see if we
3773 can associate some operands. This can win if they are constants or
3774 if they are logically related (i.e. (a & b) & a). */
3775 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3776 || code
== AND
|| code
== IOR
|| code
== XOR
3777 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3778 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3779 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3781 if (GET_CODE (XEXP (x
, 0)) == code
)
3783 rtx other
= XEXP (XEXP (x
, 0), 0);
3784 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3785 rtx inner_op1
= XEXP (x
, 1);
3788 /* Make sure we pass the constant operand if any as the second
3789 one if this is a commutative operation. */
3790 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3792 rtx tem
= inner_op0
;
3793 inner_op0
= inner_op1
;
3796 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3797 : code
== DIV
? MULT
3799 mode
, inner_op0
, inner_op1
);
3801 /* For commutative operations, try the other pair if that one
3803 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3805 other
= XEXP (XEXP (x
, 0), 1);
3806 inner
= simplify_binary_operation (code
, mode
,
3807 XEXP (XEXP (x
, 0), 0),
3812 return gen_binary (code
, mode
, other
, inner
);
3816 /* A little bit of algebraic simplification here. */
3820 /* Ensure that our address has any ASHIFTs converted to MULT in case
3821 address-recognizing predicates are called later. */
3822 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3823 SUBST (XEXP (x
, 0), temp
);
3827 if (op0_mode
== VOIDmode
)
3828 op0_mode
= GET_MODE (SUBREG_REG (x
));
3830 /* See if this can be moved to simplify_subreg. */
3831 if (CONSTANT_P (SUBREG_REG (x
))
3832 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3833 /* Don't call gen_lowpart if the inner mode
3834 is VOIDmode and we cannot simplify it, as SUBREG without
3835 inner mode is invalid. */
3836 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3837 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3838 return gen_lowpart (mode
, SUBREG_REG (x
));
3840 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3844 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3850 /* Don't change the mode of the MEM if that would change the meaning
3852 if (GET_CODE (SUBREG_REG (x
)) == MEM
3853 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3854 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3855 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3857 /* Note that we cannot do any narrowing for non-constants since
3858 we might have been counting on using the fact that some bits were
3859 zero. We now do this in the SET. */
3864 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3865 && subreg_lowpart_p (XEXP (x
, 0))
3866 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3867 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3868 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3869 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3871 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3873 x
= gen_rtx_ROTATE (inner_mode
,
3874 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3876 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3877 return gen_lowpart (mode
, x
);
3880 /* Apply De Morgan's laws to reduce number of patterns for machines
3881 with negating logical insns (and-not, nand, etc.). If result has
3882 only one NOT, put it first, since that is how the patterns are
3885 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3887 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3888 enum machine_mode op_mode
;
3890 op_mode
= GET_MODE (in1
);
3891 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3893 op_mode
= GET_MODE (in2
);
3894 if (op_mode
== VOIDmode
)
3896 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3898 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3901 in2
= in1
; in1
= tem
;
3904 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3910 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3911 if (GET_CODE (XEXP (x
, 0)) == XOR
3912 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3913 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3914 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3916 temp
= expand_compound_operation (XEXP (x
, 0));
3918 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3919 replaced by (lshiftrt X C). This will convert
3920 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3922 if (GET_CODE (temp
) == ASHIFTRT
3923 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3924 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3925 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3926 INTVAL (XEXP (temp
, 1)));
3928 /* If X has only a single bit that might be nonzero, say, bit I, convert
3929 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3930 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3931 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3932 or a SUBREG of one since we'd be making the expression more
3933 complex if it was just a register. */
3935 if (GET_CODE (temp
) != REG
3936 && ! (GET_CODE (temp
) == SUBREG
3937 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3938 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3940 rtx temp1
= simplify_shift_const
3941 (NULL_RTX
, ASHIFTRT
, mode
,
3942 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3943 GET_MODE_BITSIZE (mode
) - 1 - i
),
3944 GET_MODE_BITSIZE (mode
) - 1 - i
);
3946 /* If all we did was surround TEMP with the two shifts, we
3947 haven't improved anything, so don't use it. Otherwise,
3948 we are better off with TEMP1. */
3949 if (GET_CODE (temp1
) != ASHIFTRT
3950 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3951 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3957 /* We can't handle truncation to a partial integer mode here
3958 because we don't know the real bitsize of the partial
3960 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3963 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3964 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3965 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3967 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3968 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3970 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3971 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3972 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3973 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3974 return XEXP (XEXP (x
, 0), 0);
3976 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3977 (OP:SI foo:SI) if OP is NEG or ABS. */
3978 if ((GET_CODE (XEXP (x
, 0)) == ABS
3979 || GET_CODE (XEXP (x
, 0)) == NEG
)
3980 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3981 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3982 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3983 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3984 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3986 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3988 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3989 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3990 && subreg_lowpart_p (XEXP (x
, 0)))
3991 return SUBREG_REG (XEXP (x
, 0));
3993 /* If we know that the value is already truncated, we can
3994 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3995 is nonzero for the corresponding modes. But don't do this
3996 for an (LSHIFTRT (MULT ...)) since this will cause problems
3997 with the umulXi3_highpart patterns. */
3998 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3999 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4000 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4001 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4002 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4003 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4004 return gen_lowpart (mode
, XEXP (x
, 0));
4006 /* A truncate of a comparison can be replaced with a subreg if
4007 STORE_FLAG_VALUE permits. This is like the previous test,
4008 but it works even if the comparison is done in a mode larger
4009 than HOST_BITS_PER_WIDE_INT. */
4010 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4011 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4012 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4013 return gen_lowpart (mode
, XEXP (x
, 0));
4015 /* Similarly, a truncate of a register whose value is a
4016 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4018 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4019 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4020 && (temp
= get_last_value (XEXP (x
, 0)))
4021 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4022 return gen_lowpart (mode
, XEXP (x
, 0));
4026 case FLOAT_TRUNCATE
:
4027 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4028 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4029 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4030 return XEXP (XEXP (x
, 0), 0);
4032 /* (float_truncate:SF (float_truncate:DF foo:XF))
4033 = (float_truncate:SF foo:XF).
4034 This may eliminate double rounding, so it is unsafe.
4036 (float_truncate:SF (float_extend:XF foo:DF))
4037 = (float_truncate:SF foo:DF).
4039 (float_truncate:DF (float_extend:XF foo:SF))
4040 = (float_extend:SF foo:DF). */
4041 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4042 && flag_unsafe_math_optimizations
)
4043 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4044 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4046 > GET_MODE_SIZE (mode
)
4047 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4049 XEXP (XEXP (x
, 0), 0), mode
);
4051 /* (float_truncate (float x)) is (float x) */
4052 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4053 && (flag_unsafe_math_optimizations
4054 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4055 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4056 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4057 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4058 return simplify_gen_unary (FLOAT
, mode
,
4059 XEXP (XEXP (x
, 0), 0),
4060 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4062 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4063 (OP:SF foo:SF) if OP is NEG or ABS. */
4064 if ((GET_CODE (XEXP (x
, 0)) == ABS
4065 || GET_CODE (XEXP (x
, 0)) == NEG
)
4066 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4067 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4068 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4069 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4071 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4072 is (float_truncate:SF x). */
4073 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4074 && subreg_lowpart_p (XEXP (x
, 0))
4075 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4076 return SUBREG_REG (XEXP (x
, 0));
4079 /* (float_extend (float_extend x)) is (float_extend x)
4081 (float_extend (float x)) is (float x) assuming that double
4082 rounding can't happen.
4084 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4085 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4086 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4087 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4088 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4089 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4090 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4091 XEXP (XEXP (x
, 0), 0),
4092 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4097 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4098 using cc0, in which case we want to leave it as a COMPARE
4099 so we can distinguish it from a register-register-copy. */
4100 if (XEXP (x
, 1) == const0_rtx
)
4103 /* x - 0 is the same as x unless x's mode has signed zeros and
4104 allows rounding towards -infinity. Under those conditions,
4106 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4107 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4108 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4114 /* (const (const X)) can become (const X). Do it this way rather than
4115 returning the inner CONST since CONST can be shared with a
4117 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4118 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4123 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4124 can add in an offset. find_split_point will split this address up
4125 again if it doesn't match. */
4126 if (GET_CODE (XEXP (x
, 0)) == HIGH
4127 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4133 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4135 if (GET_CODE (XEXP (x
, 0)) == MULT
4136 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4140 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4141 in2
= XEXP (XEXP (x
, 0), 1);
4142 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4143 gen_binary (MULT
, mode
, in1
, in2
));
4146 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4147 outermost. That's because that's the way indexed addresses are
4148 supposed to appear. This code used to check many more cases, but
4149 they are now checked elsewhere. */
4150 if (GET_CODE (XEXP (x
, 0)) == PLUS
4151 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4152 return gen_binary (PLUS
, mode
,
4153 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4155 XEXP (XEXP (x
, 0), 1));
4157 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4158 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4159 bit-field and can be replaced by either a sign_extend or a
4160 sign_extract. The `and' may be a zero_extend and the two
4161 <c>, -<c> constants may be reversed. */
4162 if (GET_CODE (XEXP (x
, 0)) == XOR
4163 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4164 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4165 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4166 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4167 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4168 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4169 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4170 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4171 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4172 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4173 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4174 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4175 == (unsigned int) i
+ 1))))
4176 return simplify_shift_const
4177 (NULL_RTX
, ASHIFTRT
, mode
,
4178 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4179 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4180 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4181 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4183 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4184 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4185 is 1. This produces better code than the alternative immediately
4187 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4188 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4189 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4190 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4191 XEXP (XEXP (x
, 0), 0),
4192 XEXP (XEXP (x
, 0), 1))))
4194 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4196 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4197 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4198 the bitsize of the mode - 1. This allows simplification of
4199 "a = (b & 8) == 0;" */
4200 if (XEXP (x
, 1) == constm1_rtx
4201 && GET_CODE (XEXP (x
, 0)) != REG
4202 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4203 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4204 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4205 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4206 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4207 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4208 GET_MODE_BITSIZE (mode
) - 1),
4209 GET_MODE_BITSIZE (mode
) - 1);
4211 /* If we are adding two things that have no bits in common, convert
4212 the addition into an IOR. This will often be further simplified,
4213 for example in cases like ((a & 1) + (a & 2)), which can
4216 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4217 && (nonzero_bits (XEXP (x
, 0), mode
)
4218 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4220 /* Try to simplify the expression further. */
4221 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4222 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4224 /* If we could, great. If not, do not go ahead with the IOR
4225 replacement, since PLUS appears in many special purpose
4226 address arithmetic instructions. */
4227 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4233 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4234 by reversing the comparison code if valid. */
4235 if (STORE_FLAG_VALUE
== 1
4236 && XEXP (x
, 0) == const1_rtx
4237 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4238 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4239 XEXP (XEXP (x
, 1), 0),
4240 XEXP (XEXP (x
, 1), 1))))
4243 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4244 (and <foo> (const_int pow2-1)) */
4245 if (GET_CODE (XEXP (x
, 1)) == AND
4246 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4247 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4248 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4249 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4250 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4252 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4254 if (GET_CODE (XEXP (x
, 1)) == MULT
4255 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4259 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4260 in2
= XEXP (XEXP (x
, 1), 1);
4261 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4265 /* Canonicalize (minus (neg A) (mult B C)) to
4266 (minus (mult (neg B) C) A). */
4267 if (GET_CODE (XEXP (x
, 1)) == MULT
4268 && GET_CODE (XEXP (x
, 0)) == NEG
)
4272 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4273 in2
= XEXP (XEXP (x
, 1), 1);
4274 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4275 XEXP (XEXP (x
, 0), 0));
4278 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4280 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4281 return gen_binary (MINUS
, mode
,
4282 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4283 XEXP (XEXP (x
, 1), 0)),
4284 XEXP (XEXP (x
, 1), 1));
4288 /* If we have (mult (plus A B) C), apply the distributive law and then
4289 the inverse distributive law to see if things simplify. This
4290 occurs mostly in addresses, often when unrolling loops. */
4292 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4294 x
= apply_distributive_law
4295 (gen_binary (PLUS
, mode
,
4296 gen_binary (MULT
, mode
,
4297 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4298 gen_binary (MULT
, mode
,
4299 XEXP (XEXP (x
, 0), 1),
4300 copy_rtx (XEXP (x
, 1)))));
4302 if (GET_CODE (x
) != MULT
)
4305 /* Try simplify a*(b/c) as (a*b)/c. */
4306 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4307 && GET_CODE (XEXP (x
, 0)) == DIV
)
4309 rtx tem
= simplify_binary_operation (MULT
, mode
,
4310 XEXP (XEXP (x
, 0), 0),
4313 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4318 /* If this is a divide by a power of two, treat it as a shift if
4319 its first operand is a shift. */
4320 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4321 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4322 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4323 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4324 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4325 || GET_CODE (XEXP (x
, 0)) == ROTATE
4326 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4327 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4331 case GT
: case GTU
: case GE
: case GEU
:
4332 case LT
: case LTU
: case LE
: case LEU
:
4333 case UNEQ
: case LTGT
:
4334 case UNGT
: case UNGE
:
4335 case UNLT
: case UNLE
:
4336 case UNORDERED
: case ORDERED
:
4337 /* If the first operand is a condition code, we can't do anything
4339 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4340 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4341 && ! CC0_P (XEXP (x
, 0))))
4343 rtx op0
= XEXP (x
, 0);
4344 rtx op1
= XEXP (x
, 1);
4345 enum rtx_code new_code
;
4347 if (GET_CODE (op0
) == COMPARE
)
4348 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4350 /* Simplify our comparison, if possible. */
4351 new_code
= simplify_comparison (code
, &op0
, &op1
);
4353 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4354 if only the low-order bit is possibly nonzero in X (such as when
4355 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4356 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4357 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4360 Remove any ZERO_EXTRACT we made when thinking this was a
4361 comparison. It may now be simpler to use, e.g., an AND. If a
4362 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4363 the call to make_compound_operation in the SET case. */
4365 if (STORE_FLAG_VALUE
== 1
4366 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4367 && op1
== const0_rtx
4368 && mode
== GET_MODE (op0
)
4369 && nonzero_bits (op0
, mode
) == 1)
4370 return gen_lowpart (mode
,
4371 expand_compound_operation (op0
));
4373 else if (STORE_FLAG_VALUE
== 1
4374 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4375 && op1
== const0_rtx
4376 && mode
== GET_MODE (op0
)
4377 && (num_sign_bit_copies (op0
, mode
)
4378 == GET_MODE_BITSIZE (mode
)))
4380 op0
= expand_compound_operation (op0
);
4381 return simplify_gen_unary (NEG
, mode
,
4382 gen_lowpart (mode
, op0
),
4386 else if (STORE_FLAG_VALUE
== 1
4387 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4388 && op1
== const0_rtx
4389 && mode
== GET_MODE (op0
)
4390 && nonzero_bits (op0
, mode
) == 1)
4392 op0
= expand_compound_operation (op0
);
4393 return gen_binary (XOR
, mode
,
4394 gen_lowpart (mode
, op0
),
4398 else if (STORE_FLAG_VALUE
== 1
4399 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4400 && op1
== const0_rtx
4401 && mode
== GET_MODE (op0
)
4402 && (num_sign_bit_copies (op0
, mode
)
4403 == GET_MODE_BITSIZE (mode
)))
4405 op0
= expand_compound_operation (op0
);
4406 return plus_constant (gen_lowpart (mode
, op0
), 1);
4409 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4411 if (STORE_FLAG_VALUE
== -1
4412 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4413 && op1
== const0_rtx
4414 && (num_sign_bit_copies (op0
, mode
)
4415 == GET_MODE_BITSIZE (mode
)))
4416 return gen_lowpart (mode
,
4417 expand_compound_operation (op0
));
4419 else if (STORE_FLAG_VALUE
== -1
4420 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4421 && op1
== const0_rtx
4422 && mode
== GET_MODE (op0
)
4423 && nonzero_bits (op0
, mode
) == 1)
4425 op0
= expand_compound_operation (op0
);
4426 return simplify_gen_unary (NEG
, mode
,
4427 gen_lowpart (mode
, op0
),
4431 else if (STORE_FLAG_VALUE
== -1
4432 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4433 && op1
== const0_rtx
4434 && mode
== GET_MODE (op0
)
4435 && (num_sign_bit_copies (op0
, mode
)
4436 == GET_MODE_BITSIZE (mode
)))
4438 op0
= expand_compound_operation (op0
);
4439 return simplify_gen_unary (NOT
, mode
,
4440 gen_lowpart (mode
, op0
),
4444 /* If X is 0/1, (eq X 0) is X-1. */
4445 else if (STORE_FLAG_VALUE
== -1
4446 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4447 && op1
== const0_rtx
4448 && mode
== GET_MODE (op0
)
4449 && nonzero_bits (op0
, mode
) == 1)
4451 op0
= expand_compound_operation (op0
);
4452 return plus_constant (gen_lowpart (mode
, op0
), -1);
4455 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4456 one bit that might be nonzero, we can convert (ne x 0) to
4457 (ashift x c) where C puts the bit in the sign bit. Remove any
4458 AND with STORE_FLAG_VALUE when we are done, since we are only
4459 going to test the sign bit. */
4460 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4461 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4462 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4463 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4464 && op1
== const0_rtx
4465 && mode
== GET_MODE (op0
)
4466 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4468 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4469 expand_compound_operation (op0
),
4470 GET_MODE_BITSIZE (mode
) - 1 - i
);
4471 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4477 /* If the code changed, return a whole new comparison. */
4478 if (new_code
!= code
)
4479 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4481 /* Otherwise, keep this operation, but maybe change its operands.
4482 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4483 SUBST (XEXP (x
, 0), op0
);
4484 SUBST (XEXP (x
, 1), op1
);
4489 return simplify_if_then_else (x
);
4495 /* If we are processing SET_DEST, we are done. */
4499 return expand_compound_operation (x
);
4502 return simplify_set (x
);
4507 return simplify_logical (x
, last
);
4510 /* (abs (neg <foo>)) -> (abs <foo>) */
4511 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4512 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4514 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4516 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4519 /* If operand is something known to be positive, ignore the ABS. */
4520 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4521 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4522 <= HOST_BITS_PER_WIDE_INT
)
4523 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4524 & ((HOST_WIDE_INT
) 1
4525 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4529 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4530 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4531 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4536 /* (ffs (*_extend <X>)) = (ffs <X>) */
4537 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4538 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4539 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4544 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4545 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4546 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4550 /* (float (sign_extend <X>)) = (float <X>). */
4551 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4552 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4560 /* If this is a shift by a constant amount, simplify it. */
4561 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4562 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4563 INTVAL (XEXP (x
, 1)));
4565 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4567 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4569 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4576 rtx op0
= XEXP (x
, 0);
4577 rtx op1
= XEXP (x
, 1);
4580 if (GET_CODE (op1
) != PARALLEL
)
4582 len
= XVECLEN (op1
, 0);
4584 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4585 && GET_CODE (op0
) == VEC_CONCAT
)
4587 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4589 /* Try to find the element in the VEC_CONCAT. */
4592 if (GET_MODE (op0
) == GET_MODE (x
))
4594 if (GET_CODE (op0
) == VEC_CONCAT
)
4596 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4597 if (op0_size
< offset
)
4598 op0
= XEXP (op0
, 0);
4602 op0
= XEXP (op0
, 1);
4620 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4623 simplify_if_then_else (rtx x
)
4625 enum machine_mode mode
= GET_MODE (x
);
4626 rtx cond
= XEXP (x
, 0);
4627 rtx true_rtx
= XEXP (x
, 1);
4628 rtx false_rtx
= XEXP (x
, 2);
4629 enum rtx_code true_code
= GET_CODE (cond
);
4630 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4633 enum rtx_code false_code
;
4636 /* Simplify storing of the truth value. */
4637 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4638 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4640 /* Also when the truth value has to be reversed. */
4642 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4643 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4647 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4648 in it is being compared against certain values. Get the true and false
4649 comparisons and see if that says anything about the value of each arm. */
4652 && ((false_code
= combine_reversed_comparison_code (cond
))
4654 && GET_CODE (XEXP (cond
, 0)) == REG
)
4657 rtx from
= XEXP (cond
, 0);
4658 rtx true_val
= XEXP (cond
, 1);
4659 rtx false_val
= true_val
;
4662 /* If FALSE_CODE is EQ, swap the codes and arms. */
4664 if (false_code
== EQ
)
4666 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4667 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4670 /* If we are comparing against zero and the expression being tested has
4671 only a single bit that might be nonzero, that is its value when it is
4672 not equal to zero. Similarly if it is known to be -1 or 0. */
4674 if (true_code
== EQ
&& true_val
== const0_rtx
4675 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4676 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4677 else if (true_code
== EQ
&& true_val
== const0_rtx
4678 && (num_sign_bit_copies (from
, GET_MODE (from
))
4679 == GET_MODE_BITSIZE (GET_MODE (from
))))
4680 false_code
= EQ
, false_val
= constm1_rtx
;
4682 /* Now simplify an arm if we know the value of the register in the
4683 branch and it is used in the arm. Be careful due to the potential
4684 of locally-shared RTL. */
4686 if (reg_mentioned_p (from
, true_rtx
))
4687 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4689 pc_rtx
, pc_rtx
, 0, 0);
4690 if (reg_mentioned_p (from
, false_rtx
))
4691 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4693 pc_rtx
, pc_rtx
, 0, 0);
4695 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4696 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4698 true_rtx
= XEXP (x
, 1);
4699 false_rtx
= XEXP (x
, 2);
4700 true_code
= GET_CODE (cond
);
4703 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4704 reversed, do so to avoid needing two sets of patterns for
4705 subtract-and-branch insns. Similarly if we have a constant in the true
4706 arm, the false arm is the same as the first operand of the comparison, or
4707 the false arm is more complicated than the true arm. */
4710 && combine_reversed_comparison_code (cond
) != UNKNOWN
4711 && (true_rtx
== pc_rtx
4712 || (CONSTANT_P (true_rtx
)
4713 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4714 || true_rtx
== const0_rtx
4715 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4716 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4717 || (GET_CODE (true_rtx
) == SUBREG
4718 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4719 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4720 || reg_mentioned_p (true_rtx
, false_rtx
)
4721 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4723 true_code
= reversed_comparison_code (cond
, NULL
);
4725 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4728 SUBST (XEXP (x
, 1), false_rtx
);
4729 SUBST (XEXP (x
, 2), true_rtx
);
4731 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4734 /* It is possible that the conditional has been simplified out. */
4735 true_code
= GET_CODE (cond
);
4736 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4739 /* If the two arms are identical, we don't need the comparison. */
4741 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4744 /* Convert a == b ? b : a to "a". */
4745 if (true_code
== EQ
&& ! side_effects_p (cond
)
4746 && !HONOR_NANS (mode
)
4747 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4748 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4750 else if (true_code
== NE
&& ! side_effects_p (cond
)
4751 && !HONOR_NANS (mode
)
4752 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4753 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4756 /* Look for cases where we have (abs x) or (neg (abs X)). */
4758 if (GET_MODE_CLASS (mode
) == MODE_INT
4759 && GET_CODE (false_rtx
) == NEG
4760 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4762 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4763 && ! side_effects_p (true_rtx
))
4768 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4772 simplify_gen_unary (NEG
, mode
,
4773 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4779 /* Look for MIN or MAX. */
4781 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4783 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4784 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4785 && ! side_effects_p (cond
))
4790 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4793 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4796 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4799 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4804 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4805 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4806 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4807 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4808 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4809 neither 1 or -1, but it isn't worth checking for. */
4811 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4813 && GET_MODE_CLASS (mode
) == MODE_INT
4814 && ! side_effects_p (x
))
4816 rtx t
= make_compound_operation (true_rtx
, SET
);
4817 rtx f
= make_compound_operation (false_rtx
, SET
);
4818 rtx cond_op0
= XEXP (cond
, 0);
4819 rtx cond_op1
= XEXP (cond
, 1);
4820 enum rtx_code op
= NIL
, extend_op
= NIL
;
4821 enum machine_mode m
= mode
;
4822 rtx z
= 0, c1
= NULL_RTX
;
4824 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4825 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4826 || GET_CODE (t
) == ASHIFT
4827 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4828 && rtx_equal_p (XEXP (t
, 0), f
))
4829 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4831 /* If an identity-zero op is commutative, check whether there
4832 would be a match if we swapped the operands. */
4833 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4834 || GET_CODE (t
) == XOR
)
4835 && rtx_equal_p (XEXP (t
, 1), f
))
4836 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4837 else if (GET_CODE (t
) == SIGN_EXTEND
4838 && (GET_CODE (XEXP (t
, 0)) == PLUS
4839 || GET_CODE (XEXP (t
, 0)) == MINUS
4840 || GET_CODE (XEXP (t
, 0)) == IOR
4841 || GET_CODE (XEXP (t
, 0)) == XOR
4842 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4843 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4844 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4845 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4846 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4847 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4848 && (num_sign_bit_copies (f
, GET_MODE (f
))
4850 (GET_MODE_BITSIZE (mode
)
4851 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4853 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4854 extend_op
= SIGN_EXTEND
;
4855 m
= GET_MODE (XEXP (t
, 0));
4857 else if (GET_CODE (t
) == SIGN_EXTEND
4858 && (GET_CODE (XEXP (t
, 0)) == PLUS
4859 || GET_CODE (XEXP (t
, 0)) == IOR
4860 || GET_CODE (XEXP (t
, 0)) == XOR
)
4861 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4862 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4863 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4864 && (num_sign_bit_copies (f
, GET_MODE (f
))
4866 (GET_MODE_BITSIZE (mode
)
4867 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4869 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4870 extend_op
= SIGN_EXTEND
;
4871 m
= GET_MODE (XEXP (t
, 0));
4873 else if (GET_CODE (t
) == ZERO_EXTEND
4874 && (GET_CODE (XEXP (t
, 0)) == PLUS
4875 || GET_CODE (XEXP (t
, 0)) == MINUS
4876 || GET_CODE (XEXP (t
, 0)) == IOR
4877 || GET_CODE (XEXP (t
, 0)) == XOR
4878 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4879 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4880 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4881 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4882 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4883 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4884 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4885 && ((nonzero_bits (f
, GET_MODE (f
))
4886 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4889 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4890 extend_op
= ZERO_EXTEND
;
4891 m
= GET_MODE (XEXP (t
, 0));
4893 else if (GET_CODE (t
) == ZERO_EXTEND
4894 && (GET_CODE (XEXP (t
, 0)) == PLUS
4895 || GET_CODE (XEXP (t
, 0)) == IOR
4896 || GET_CODE (XEXP (t
, 0)) == XOR
)
4897 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4898 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4899 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4900 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4901 && ((nonzero_bits (f
, GET_MODE (f
))
4902 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4905 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4906 extend_op
= ZERO_EXTEND
;
4907 m
= GET_MODE (XEXP (t
, 0));
4912 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4913 pc_rtx
, pc_rtx
, 0, 0);
4914 temp
= gen_binary (MULT
, m
, temp
,
4915 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4916 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4917 temp
= gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
4919 if (extend_op
!= NIL
)
4920 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4926 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4927 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4928 negation of a single bit, we can convert this operation to a shift. We
4929 can actually do this more generally, but it doesn't seem worth it. */
4931 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4932 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4933 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4934 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4935 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4936 == GET_MODE_BITSIZE (mode
))
4937 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4939 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4940 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
4942 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4943 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4944 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4945 && GET_MODE (XEXP (cond
, 0)) == mode
4946 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4947 == nonzero_bits (XEXP (cond
, 0), mode
)
4948 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4949 return XEXP (cond
, 0);
4954 /* Simplify X, a SET expression. Return the new expression. */
4957 simplify_set (rtx x
)
4959 rtx src
= SET_SRC (x
);
4960 rtx dest
= SET_DEST (x
);
4961 enum machine_mode mode
4962 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4966 /* (set (pc) (return)) gets written as (return). */
4967 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4970 /* Now that we know for sure which bits of SRC we are using, see if we can
4971 simplify the expression for the object knowing that we only need the
4974 if (GET_MODE_CLASS (mode
) == MODE_INT
4975 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4977 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4978 SUBST (SET_SRC (x
), src
);
4981 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4982 the comparison result and try to simplify it unless we already have used
4983 undobuf.other_insn. */
4984 if ((GET_MODE_CLASS (mode
) == MODE_CC
4985 || GET_CODE (src
) == COMPARE
4987 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4988 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4989 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4990 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4992 enum rtx_code old_code
= GET_CODE (*cc_use
);
4993 enum rtx_code new_code
;
4995 int other_changed
= 0;
4996 enum machine_mode compare_mode
= GET_MODE (dest
);
4997 enum machine_mode tmp_mode
;
4999 if (GET_CODE (src
) == COMPARE
)
5000 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5002 op0
= src
, op1
= const0_rtx
;
5004 /* Check whether the comparison is known at compile time. */
5005 if (GET_MODE (op0
) != VOIDmode
)
5006 tmp_mode
= GET_MODE (op0
);
5007 else if (GET_MODE (op1
) != VOIDmode
)
5008 tmp_mode
= GET_MODE (op1
);
5010 tmp_mode
= compare_mode
;
5011 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5012 if (tmp
!= NULL_RTX
)
5014 rtx pat
= PATTERN (other_insn
);
5015 undobuf
.other_insn
= other_insn
;
5016 SUBST (*cc_use
, tmp
);
5018 /* Attempt to simplify CC user. */
5019 if (GET_CODE (pat
) == SET
)
5021 rtx
new = simplify_rtx (SET_SRC (pat
));
5022 if (new != NULL_RTX
)
5023 SUBST (SET_SRC (pat
), new);
5026 /* Convert X into a no-op move. */
5027 SUBST (SET_DEST (x
), pc_rtx
);
5028 SUBST (SET_SRC (x
), pc_rtx
);
5032 /* Simplify our comparison, if possible. */
5033 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5035 #ifdef SELECT_CC_MODE
5036 /* If this machine has CC modes other than CCmode, check to see if we
5037 need to use a different CC mode here. */
5038 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5041 /* If the mode changed, we have to change SET_DEST, the mode in the
5042 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5043 a hard register, just build new versions with the proper mode. If it
5044 is a pseudo, we lose unless it is only time we set the pseudo, in
5045 which case we can safely change its mode. */
5046 if (compare_mode
!= GET_MODE (dest
))
5048 unsigned int regno
= REGNO (dest
);
5049 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5051 if (regno
< FIRST_PSEUDO_REGISTER
5052 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5054 if (regno
>= FIRST_PSEUDO_REGISTER
)
5055 SUBST (regno_reg_rtx
[regno
], new_dest
);
5057 SUBST (SET_DEST (x
), new_dest
);
5058 SUBST (XEXP (*cc_use
, 0), new_dest
);
5065 #endif /* SELECT_CC_MODE */
5067 /* If the code changed, we have to build a new comparison in
5068 undobuf.other_insn. */
5069 if (new_code
!= old_code
)
5071 int other_changed_previously
= other_changed
;
5072 unsigned HOST_WIDE_INT mask
;
5074 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5078 /* If the only change we made was to change an EQ into an NE or
5079 vice versa, OP0 has only one bit that might be nonzero, and OP1
5080 is zero, check if changing the user of the condition code will
5081 produce a valid insn. If it won't, we can keep the original code
5082 in that insn by surrounding our operation with an XOR. */
5084 if (((old_code
== NE
&& new_code
== EQ
)
5085 || (old_code
== EQ
&& new_code
== NE
))
5086 && ! other_changed_previously
&& op1
== const0_rtx
5087 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5088 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5090 rtx pat
= PATTERN (other_insn
), note
= 0;
5092 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5093 && ! check_asm_operands (pat
)))
5095 PUT_CODE (*cc_use
, old_code
);
5098 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5104 undobuf
.other_insn
= other_insn
;
5107 /* If we are now comparing against zero, change our source if
5108 needed. If we do not use cc0, we always have a COMPARE. */
5109 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5111 SUBST (SET_SRC (x
), op0
);
5117 /* Otherwise, if we didn't previously have a COMPARE in the
5118 correct mode, we need one. */
5119 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5121 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5126 /* Otherwise, update the COMPARE if needed. */
5127 SUBST (XEXP (src
, 0), op0
);
5128 SUBST (XEXP (src
, 1), op1
);
5133 /* Get SET_SRC in a form where we have placed back any
5134 compound expressions. Then do the checks below. */
5135 src
= make_compound_operation (src
, SET
);
5136 SUBST (SET_SRC (x
), src
);
5139 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5140 and X being a REG or (subreg (reg)), we may be able to convert this to
5141 (set (subreg:m2 x) (op)).
5143 We can always do this if M1 is narrower than M2 because that means that
5144 we only care about the low bits of the result.
5146 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5147 perform a narrower operation than requested since the high-order bits will
5148 be undefined. On machine where it is defined, this transformation is safe
5149 as long as M1 and M2 have the same number of words. */
5151 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5152 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5153 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5155 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5156 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5157 #ifndef WORD_REGISTER_OPERATIONS
5158 && (GET_MODE_SIZE (GET_MODE (src
))
5159 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5161 #ifdef CANNOT_CHANGE_MODE_CLASS
5162 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5163 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5164 GET_MODE (SUBREG_REG (src
)),
5167 && (GET_CODE (dest
) == REG
5168 || (GET_CODE (dest
) == SUBREG
5169 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5171 SUBST (SET_DEST (x
),
5172 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5174 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5176 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5180 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5183 && GET_CODE (src
) == SUBREG
5184 && subreg_lowpart_p (src
)
5185 && (GET_MODE_BITSIZE (GET_MODE (src
))
5186 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5188 rtx inner
= SUBREG_REG (src
);
5189 enum machine_mode inner_mode
= GET_MODE (inner
);
5191 /* Here we make sure that we don't have a sign bit on. */
5192 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5193 && (nonzero_bits (inner
, inner_mode
)
5194 < ((unsigned HOST_WIDE_INT
) 1
5195 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5197 SUBST (SET_SRC (x
), inner
);
5203 #ifdef LOAD_EXTEND_OP
5204 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5205 would require a paradoxical subreg. Replace the subreg with a
5206 zero_extend to avoid the reload that would otherwise be required. */
5208 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5209 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5210 && SUBREG_BYTE (src
) == 0
5211 && (GET_MODE_SIZE (GET_MODE (src
))
5212 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5213 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5216 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5217 GET_MODE (src
), SUBREG_REG (src
)));
5223 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5224 are comparing an item known to be 0 or -1 against 0, use a logical
5225 operation instead. Check for one of the arms being an IOR of the other
5226 arm with some value. We compute three terms to be IOR'ed together. In
5227 practice, at most two will be nonzero. Then we do the IOR's. */
5229 if (GET_CODE (dest
) != PC
5230 && GET_CODE (src
) == IF_THEN_ELSE
5231 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5232 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5233 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5234 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5235 #ifdef HAVE_conditional_move
5236 && ! can_conditionally_move_p (GET_MODE (src
))
5238 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5239 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5240 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5241 && ! side_effects_p (src
))
5243 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5244 ? XEXP (src
, 1) : XEXP (src
, 2));
5245 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5246 ? XEXP (src
, 2) : XEXP (src
, 1));
5247 rtx term1
= const0_rtx
, term2
, term3
;
5249 if (GET_CODE (true_rtx
) == IOR
5250 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5251 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5252 else if (GET_CODE (true_rtx
) == IOR
5253 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5254 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5255 else if (GET_CODE (false_rtx
) == IOR
5256 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5257 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5258 else if (GET_CODE (false_rtx
) == IOR
5259 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5260 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5262 term2
= gen_binary (AND
, GET_MODE (src
),
5263 XEXP (XEXP (src
, 0), 0), true_rtx
);
5264 term3
= gen_binary (AND
, GET_MODE (src
),
5265 simplify_gen_unary (NOT
, GET_MODE (src
),
5266 XEXP (XEXP (src
, 0), 0),
5271 gen_binary (IOR
, GET_MODE (src
),
5272 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5278 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5279 whole thing fail. */
5280 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5282 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5285 /* Convert this into a field assignment operation, if possible. */
5286 return make_field_assignment (x
);
5289 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5290 result. LAST is nonzero if this is the last retry. */
5293 simplify_logical (rtx x
, int last
)
5295 enum machine_mode mode
= GET_MODE (x
);
5296 rtx op0
= XEXP (x
, 0);
5297 rtx op1
= XEXP (x
, 1);
5300 switch (GET_CODE (x
))
5303 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5304 insn (and may simplify more). */
5305 if (GET_CODE (op0
) == XOR
5306 && rtx_equal_p (XEXP (op0
, 0), op1
)
5307 && ! side_effects_p (op1
))
5308 x
= gen_binary (AND
, mode
,
5309 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5312 if (GET_CODE (op0
) == XOR
5313 && rtx_equal_p (XEXP (op0
, 1), op1
)
5314 && ! side_effects_p (op1
))
5315 x
= gen_binary (AND
, mode
,
5316 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5319 /* Similarly for (~(A ^ B)) & A. */
5320 if (GET_CODE (op0
) == NOT
5321 && GET_CODE (XEXP (op0
, 0)) == XOR
5322 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5323 && ! side_effects_p (op1
))
5324 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5326 if (GET_CODE (op0
) == NOT
5327 && GET_CODE (XEXP (op0
, 0)) == XOR
5328 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5329 && ! side_effects_p (op1
))
5330 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5332 /* We can call simplify_and_const_int only if we don't lose
5333 any (sign) bits when converting INTVAL (op1) to
5334 "unsigned HOST_WIDE_INT". */
5335 if (GET_CODE (op1
) == CONST_INT
5336 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5337 || INTVAL (op1
) > 0))
5339 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5341 /* If we have (ior (and (X C1) C2)) and the next restart would be
5342 the last, simplify this by making C1 as small as possible
5345 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5346 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5347 && GET_CODE (op1
) == CONST_INT
)
5348 return gen_binary (IOR
, mode
,
5349 gen_binary (AND
, mode
, XEXP (op0
, 0),
5350 GEN_INT (INTVAL (XEXP (op0
, 1))
5351 & ~INTVAL (op1
))), op1
);
5353 if (GET_CODE (x
) != AND
)
5356 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5357 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5358 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5361 /* Convert (A | B) & A to A. */
5362 if (GET_CODE (op0
) == IOR
5363 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5364 || rtx_equal_p (XEXP (op0
, 1), op1
))
5365 && ! side_effects_p (XEXP (op0
, 0))
5366 && ! side_effects_p (XEXP (op0
, 1)))
5369 /* In the following group of tests (and those in case IOR below),
5370 we start with some combination of logical operations and apply
5371 the distributive law followed by the inverse distributive law.
5372 Most of the time, this results in no change. However, if some of
5373 the operands are the same or inverses of each other, simplifications
5376 For example, (and (ior A B) (not B)) can occur as the result of
5377 expanding a bit field assignment. When we apply the distributive
5378 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5379 which then simplifies to (and (A (not B))).
5381 If we have (and (ior A B) C), apply the distributive law and then
5382 the inverse distributive law to see if things simplify. */
5384 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5386 x
= apply_distributive_law
5387 (gen_binary (GET_CODE (op0
), mode
,
5388 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5389 gen_binary (AND
, mode
, XEXP (op0
, 1),
5391 if (GET_CODE (x
) != AND
)
5395 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5396 return apply_distributive_law
5397 (gen_binary (GET_CODE (op1
), mode
,
5398 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5399 gen_binary (AND
, mode
, XEXP (op1
, 1),
5402 /* Similarly, taking advantage of the fact that
5403 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5405 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5406 return apply_distributive_law
5407 (gen_binary (XOR
, mode
,
5408 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5409 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5412 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5413 return apply_distributive_law
5414 (gen_binary (XOR
, mode
,
5415 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5416 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5420 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5421 if (GET_CODE (op1
) == CONST_INT
5422 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5423 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5426 /* Convert (A & B) | A to A. */
5427 if (GET_CODE (op0
) == AND
5428 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5429 || rtx_equal_p (XEXP (op0
, 1), op1
))
5430 && ! side_effects_p (XEXP (op0
, 0))
5431 && ! side_effects_p (XEXP (op0
, 1)))
5434 /* If we have (ior (and A B) C), apply the distributive law and then
5435 the inverse distributive law to see if things simplify. */
5437 if (GET_CODE (op0
) == AND
)
5439 x
= apply_distributive_law
5440 (gen_binary (AND
, mode
,
5441 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5442 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5445 if (GET_CODE (x
) != IOR
)
5449 if (GET_CODE (op1
) == AND
)
5451 x
= apply_distributive_law
5452 (gen_binary (AND
, mode
,
5453 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5454 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5457 if (GET_CODE (x
) != IOR
)
5461 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5462 mode size to (rotate A CX). */
5464 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5465 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5466 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5467 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5468 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5469 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5470 == GET_MODE_BITSIZE (mode
)))
5471 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5472 (GET_CODE (op0
) == ASHIFT
5473 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5475 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5476 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5477 does not affect any of the bits in OP1, it can really be done
5478 as a PLUS and we can associate. We do this by seeing if OP1
5479 can be safely shifted left C bits. */
5480 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5481 && GET_CODE (XEXP (op0
, 0)) == PLUS
5482 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5483 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5484 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5486 int count
= INTVAL (XEXP (op0
, 1));
5487 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5489 if (mask
>> count
== INTVAL (op1
)
5490 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5492 SUBST (XEXP (XEXP (op0
, 0), 1),
5493 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5500 /* If we are XORing two things that have no bits in common,
5501 convert them into an IOR. This helps to detect rotation encoded
5502 using those methods and possibly other simplifications. */
5504 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5505 && (nonzero_bits (op0
, mode
)
5506 & nonzero_bits (op1
, mode
)) == 0)
5507 return (gen_binary (IOR
, mode
, op0
, op1
));
5509 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5510 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5513 int num_negated
= 0;
5515 if (GET_CODE (op0
) == NOT
)
5516 num_negated
++, op0
= XEXP (op0
, 0);
5517 if (GET_CODE (op1
) == NOT
)
5518 num_negated
++, op1
= XEXP (op1
, 0);
5520 if (num_negated
== 2)
5522 SUBST (XEXP (x
, 0), op0
);
5523 SUBST (XEXP (x
, 1), op1
);
5525 else if (num_negated
== 1)
5527 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5531 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5532 correspond to a machine insn or result in further simplifications
5533 if B is a constant. */
5535 if (GET_CODE (op0
) == AND
5536 && rtx_equal_p (XEXP (op0
, 1), op1
)
5537 && ! side_effects_p (op1
))
5538 return gen_binary (AND
, mode
,
5539 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5542 else if (GET_CODE (op0
) == AND
5543 && rtx_equal_p (XEXP (op0
, 0), op1
)
5544 && ! side_effects_p (op1
))
5545 return gen_binary (AND
, mode
,
5546 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5549 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5550 comparison if STORE_FLAG_VALUE is 1. */
5551 if (STORE_FLAG_VALUE
== 1
5552 && op1
== const1_rtx
5553 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5554 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5558 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5559 is (lt foo (const_int 0)), so we can perform the above
5560 simplification if STORE_FLAG_VALUE is 1. */
5562 if (STORE_FLAG_VALUE
== 1
5563 && op1
== const1_rtx
5564 && GET_CODE (op0
) == LSHIFTRT
5565 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5566 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5567 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5569 /* (xor (comparison foo bar) (const_int sign-bit))
5570 when STORE_FLAG_VALUE is the sign bit. */
5571 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5572 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5573 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5574 && op1
== const_true_rtx
5575 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5576 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5589 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5590 operations" because they can be replaced with two more basic operations.
5591 ZERO_EXTEND is also considered "compound" because it can be replaced with
5592 an AND operation, which is simpler, though only one operation.
5594 The function expand_compound_operation is called with an rtx expression
5595 and will convert it to the appropriate shifts and AND operations,
5596 simplifying at each stage.
5598 The function make_compound_operation is called to convert an expression
5599 consisting of shifts and ANDs into the equivalent compound expression.
5600 It is the inverse of this function, loosely speaking. */
5603 expand_compound_operation (rtx x
)
5605 unsigned HOST_WIDE_INT pos
= 0, len
;
5607 unsigned int modewidth
;
5610 switch (GET_CODE (x
))
5615 /* We can't necessarily use a const_int for a multiword mode;
5616 it depends on implicitly extending the value.
5617 Since we don't know the right way to extend it,
5618 we can't tell whether the implicit way is right.
5620 Even for a mode that is no wider than a const_int,
5621 we can't win, because we need to sign extend one of its bits through
5622 the rest of it, and we don't know which bit. */
5623 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5626 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5627 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5628 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5629 reloaded. If not for that, MEM's would very rarely be safe.
5631 Reject MODEs bigger than a word, because we might not be able
5632 to reference a two-register group starting with an arbitrary register
5633 (and currently gen_lowpart might crash for a SUBREG). */
5635 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5638 /* Reject MODEs that aren't scalar integers because turning vector
5639 or complex modes into shifts causes problems. */
5641 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5644 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5645 /* If the inner object has VOIDmode (the only way this can happen
5646 is if it is an ASM_OPERANDS), we can't do anything since we don't
5647 know how much masking to do. */
5656 /* If the operand is a CLOBBER, just return it. */
5657 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5660 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5661 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5662 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5665 /* Reject MODEs that aren't scalar integers because turning vector
5666 or complex modes into shifts causes problems. */
5668 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5671 len
= INTVAL (XEXP (x
, 1));
5672 pos
= INTVAL (XEXP (x
, 2));
5674 /* If this goes outside the object being extracted, replace the object
5675 with a (use (mem ...)) construct that only combine understands
5676 and is used only for this purpose. */
5677 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5678 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5680 if (BITS_BIG_ENDIAN
)
5681 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5688 /* Convert sign extension to zero extension, if we know that the high
5689 bit is not set, as this is easier to optimize. It will be converted
5690 back to cheaper alternative in make_extraction. */
5691 if (GET_CODE (x
) == SIGN_EXTEND
5692 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5693 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5694 & ~(((unsigned HOST_WIDE_INT
)
5695 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5699 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5700 rtx temp2
= expand_compound_operation (temp
);
5702 /* Make sure this is a profitable operation. */
5703 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5705 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5711 /* We can optimize some special cases of ZERO_EXTEND. */
5712 if (GET_CODE (x
) == ZERO_EXTEND
)
5714 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5715 know that the last value didn't have any inappropriate bits
5717 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5718 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5719 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5720 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5721 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5722 return XEXP (XEXP (x
, 0), 0);
5724 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5725 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5726 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5727 && subreg_lowpart_p (XEXP (x
, 0))
5728 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5729 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5730 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5731 return SUBREG_REG (XEXP (x
, 0));
5733 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5734 is a comparison and STORE_FLAG_VALUE permits. This is like
5735 the first case, but it works even when GET_MODE (x) is larger
5736 than HOST_WIDE_INT. */
5737 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5738 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5739 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5740 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5741 <= HOST_BITS_PER_WIDE_INT
)
5742 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5743 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5744 return XEXP (XEXP (x
, 0), 0);
5746 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5747 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5748 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5749 && subreg_lowpart_p (XEXP (x
, 0))
5750 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5751 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5752 <= HOST_BITS_PER_WIDE_INT
)
5753 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5754 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5755 return SUBREG_REG (XEXP (x
, 0));
5759 /* If we reach here, we want to return a pair of shifts. The inner
5760 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5761 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5762 logical depending on the value of UNSIGNEDP.
5764 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5765 converted into an AND of a shift.
5767 We must check for the case where the left shift would have a negative
5768 count. This can happen in a case like (x >> 31) & 255 on machines
5769 that can't shift by a constant. On those machines, we would first
5770 combine the shift with the AND to produce a variable-position
5771 extraction. Then the constant of 31 would be substituted in to produce
5772 a such a position. */
5774 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5775 if (modewidth
+ len
>= pos
)
5776 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5778 simplify_shift_const (NULL_RTX
, ASHIFT
,
5781 modewidth
- pos
- len
),
5784 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5785 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5786 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5789 ((HOST_WIDE_INT
) 1 << len
) - 1);
5791 /* Any other cases we can't handle. */
5794 /* If we couldn't do this for some reason, return the original
5796 if (GET_CODE (tem
) == CLOBBER
)
5802 /* X is a SET which contains an assignment of one object into
5803 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5804 or certain SUBREGS). If possible, convert it into a series of
5807 We half-heartedly support variable positions, but do not at all
5808 support variable lengths. */
5811 expand_field_assignment (rtx x
)
5814 rtx pos
; /* Always counts from low bit. */
5817 enum machine_mode compute_mode
;
5819 /* Loop until we find something we can't simplify. */
5822 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5823 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5825 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5826 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5827 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5829 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5830 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5832 inner
= XEXP (SET_DEST (x
), 0);
5833 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5834 pos
= XEXP (SET_DEST (x
), 2);
5836 /* If the position is constant and spans the width of INNER,
5837 surround INNER with a USE to indicate this. */
5838 if (GET_CODE (pos
) == CONST_INT
5839 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5840 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5842 if (BITS_BIG_ENDIAN
)
5844 if (GET_CODE (pos
) == CONST_INT
)
5845 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5847 else if (GET_CODE (pos
) == MINUS
5848 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5849 && (INTVAL (XEXP (pos
, 1))
5850 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5851 /* If position is ADJUST - X, new position is X. */
5852 pos
= XEXP (pos
, 0);
5854 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5855 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5861 /* A SUBREG between two modes that occupy the same numbers of words
5862 can be done by moving the SUBREG to the source. */
5863 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5864 /* We need SUBREGs to compute nonzero_bits properly. */
5865 && nonzero_sign_valid
5866 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5867 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5868 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5869 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5871 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5873 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5880 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5881 inner
= SUBREG_REG (inner
);
5883 compute_mode
= GET_MODE (inner
);
5885 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5886 if (! SCALAR_INT_MODE_P (compute_mode
))
5888 enum machine_mode imode
;
5890 /* Don't do anything for vector or complex integral types. */
5891 if (! FLOAT_MODE_P (compute_mode
))
5894 /* Try to find an integral mode to pun with. */
5895 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5896 if (imode
== BLKmode
)
5899 compute_mode
= imode
;
5900 inner
= gen_lowpart (imode
, inner
);
5903 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5904 if (len
< HOST_BITS_PER_WIDE_INT
)
5905 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5909 /* Now compute the equivalent expression. Make a copy of INNER
5910 for the SET_DEST in case it is a MEM into which we will substitute;
5911 we don't want shared RTL in that case. */
5913 (VOIDmode
, copy_rtx (inner
),
5914 gen_binary (IOR
, compute_mode
,
5915 gen_binary (AND
, compute_mode
,
5916 simplify_gen_unary (NOT
, compute_mode
,
5922 gen_binary (ASHIFT
, compute_mode
,
5923 gen_binary (AND
, compute_mode
,
5925 (compute_mode
, SET_SRC (x
)),
5933 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5934 it is an RTX that represents a variable starting position; otherwise,
5935 POS is the (constant) starting bit position (counted from the LSB).
5937 INNER may be a USE. This will occur when we started with a bitfield
5938 that went outside the boundary of the object in memory, which is
5939 allowed on most machines. To isolate this case, we produce a USE
5940 whose mode is wide enough and surround the MEM with it. The only
5941 code that understands the USE is this routine. If it is not removed,
5942 it will cause the resulting insn not to match.
5944 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5947 IN_DEST is nonzero if this is a reference in the destination of a
5948 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5949 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5952 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5953 ZERO_EXTRACT should be built even for bits starting at bit 0.
5955 MODE is the desired mode of the result (if IN_DEST == 0).
5957 The result is an RTX for the extraction or NULL_RTX if the target
5961 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5962 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5963 int in_dest
, int in_compare
)
5965 /* This mode describes the size of the storage area
5966 to fetch the overall value from. Within that, we
5967 ignore the POS lowest bits, etc. */
5968 enum machine_mode is_mode
= GET_MODE (inner
);
5969 enum machine_mode inner_mode
;
5970 enum machine_mode wanted_inner_mode
= byte_mode
;
5971 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5972 enum machine_mode pos_mode
= word_mode
;
5973 enum machine_mode extraction_mode
= word_mode
;
5974 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5977 rtx orig_pos_rtx
= pos_rtx
;
5978 HOST_WIDE_INT orig_pos
;
5980 /* Get some information about INNER and get the innermost object. */
5981 if (GET_CODE (inner
) == USE
)
5982 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5983 /* We don't need to adjust the position because we set up the USE
5984 to pretend that it was a full-word object. */
5985 spans_byte
= 1, inner
= XEXP (inner
, 0);
5986 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5988 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5989 consider just the QI as the memory to extract from.
5990 The subreg adds or removes high bits; its mode is
5991 irrelevant to the meaning of this extraction,
5992 since POS and LEN count from the lsb. */
5993 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5994 is_mode
= GET_MODE (SUBREG_REG (inner
));
5995 inner
= SUBREG_REG (inner
);
5997 else if (GET_CODE (inner
) == ASHIFT
5998 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5999 && pos_rtx
== 0 && pos
== 0
6000 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6002 /* We're extracting the least significant bits of an rtx
6003 (ashift X (const_int C)), where LEN > C. Extract the
6004 least significant (LEN - C) bits of X, giving an rtx
6005 whose mode is MODE, then shift it left C times. */
6006 new = make_extraction (mode
, XEXP (inner
, 0),
6007 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6008 unsignedp
, in_dest
, in_compare
);
6010 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6013 inner_mode
= GET_MODE (inner
);
6015 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6016 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6018 /* See if this can be done without an extraction. We never can if the
6019 width of the field is not the same as that of some integer mode. For
6020 registers, we can only avoid the extraction if the position is at the
6021 low-order bit and this is either not in the destination or we have the
6022 appropriate STRICT_LOW_PART operation available.
6024 For MEM, we can avoid an extract if the field starts on an appropriate
6025 boundary and we can change the mode of the memory reference. However,
6026 we cannot directly access the MEM if we have a USE and the underlying
6027 MEM is not TMODE. This combination means that MEM was being used in a
6028 context where bits outside its mode were being referenced; that is only
6029 valid in bit-field insns. */
6031 if (tmode
!= BLKmode
6032 && ! (spans_byte
&& inner_mode
!= tmode
)
6033 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6034 && GET_CODE (inner
) != MEM
6036 || (GET_CODE (inner
) == REG
6037 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6038 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6040 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6041 : BITS_PER_UNIT
)) == 0
6042 /* We can't do this if we are widening INNER_MODE (it
6043 may not be aligned, for one thing). */
6044 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6045 && (inner_mode
== tmode
6046 || (! mode_dependent_address_p (XEXP (inner
, 0))
6047 && ! MEM_VOLATILE_P (inner
))))))
6049 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6050 field. If the original and current mode are the same, we need not
6051 adjust the offset. Otherwise, we do if bytes big endian.
6053 If INNER is not a MEM, get a piece consisting of just the field
6054 of interest (in this case POS % BITS_PER_WORD must be 0). */
6056 if (GET_CODE (inner
) == MEM
)
6058 HOST_WIDE_INT offset
;
6060 /* POS counts from lsb, but make OFFSET count in memory order. */
6061 if (BYTES_BIG_ENDIAN
)
6062 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6064 offset
= pos
/ BITS_PER_UNIT
;
6066 new = adjust_address_nv (inner
, tmode
, offset
);
6068 else if (GET_CODE (inner
) == REG
)
6070 if (tmode
!= inner_mode
)
6072 /* We can't call gen_lowpart in a DEST since we
6073 always want a SUBREG (see below) and it would sometimes
6074 return a new hard register. */
6077 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6079 if (WORDS_BIG_ENDIAN
6080 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6081 final_word
= ((GET_MODE_SIZE (inner_mode
)
6082 - GET_MODE_SIZE (tmode
))
6083 / UNITS_PER_WORD
) - final_word
;
6085 final_word
*= UNITS_PER_WORD
;
6086 if (BYTES_BIG_ENDIAN
&&
6087 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6088 final_word
+= (GET_MODE_SIZE (inner_mode
)
6089 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6091 /* Avoid creating invalid subregs, for example when
6092 simplifying (x>>32)&255. */
6093 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6096 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6099 new = gen_lowpart (tmode
, inner
);
6105 new = force_to_mode (inner
, tmode
,
6106 len
>= HOST_BITS_PER_WIDE_INT
6107 ? ~(unsigned HOST_WIDE_INT
) 0
6108 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6111 /* If this extraction is going into the destination of a SET,
6112 make a STRICT_LOW_PART unless we made a MEM. */
6115 return (GET_CODE (new) == MEM
? new
6116 : (GET_CODE (new) != SUBREG
6117 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6118 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6123 if (GET_CODE (new) == CONST_INT
)
6124 return gen_int_mode (INTVAL (new), mode
);
6126 /* If we know that no extraneous bits are set, and that the high
6127 bit is not set, convert the extraction to the cheaper of
6128 sign and zero extension, that are equivalent in these cases. */
6129 if (flag_expensive_optimizations
6130 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6131 && ((nonzero_bits (new, tmode
)
6132 & ~(((unsigned HOST_WIDE_INT
)
6133 GET_MODE_MASK (tmode
))
6137 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6138 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6140 /* Prefer ZERO_EXTENSION, since it gives more information to
6142 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6147 /* Otherwise, sign- or zero-extend unless we already are in the
6150 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6154 /* Unless this is a COMPARE or we have a funny memory reference,
6155 don't do anything with zero-extending field extracts starting at
6156 the low-order bit since they are simple AND operations. */
6157 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6158 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6161 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6162 we would be spanning bytes or if the position is not a constant and the
6163 length is not 1. In all other cases, we would only be going outside
6164 our object in cases when an original shift would have been
6166 if (! spans_byte
&& GET_CODE (inner
) == MEM
6167 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6168 || (pos_rtx
!= 0 && len
!= 1)))
6171 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6172 and the mode for the result. */
6173 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6175 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6176 pos_mode
= mode_for_extraction (EP_insv
, 2);
6177 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6180 if (! in_dest
&& unsignedp
6181 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6183 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6184 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6185 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6188 if (! in_dest
&& ! unsignedp
6189 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6191 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6192 pos_mode
= mode_for_extraction (EP_extv
, 3);
6193 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6196 /* Never narrow an object, since that might not be safe. */
6198 if (mode
!= VOIDmode
6199 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6200 extraction_mode
= mode
;
6202 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6203 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6204 pos_mode
= GET_MODE (pos_rtx
);
6206 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6207 if we have to change the mode of memory and cannot, the desired mode is
6209 if (GET_CODE (inner
) != MEM
)
6210 wanted_inner_mode
= wanted_inner_reg_mode
;
6211 else if (inner_mode
!= wanted_inner_mode
6212 && (mode_dependent_address_p (XEXP (inner
, 0))
6213 || MEM_VOLATILE_P (inner
)))
6214 wanted_inner_mode
= extraction_mode
;
6218 if (BITS_BIG_ENDIAN
)
6220 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6221 BITS_BIG_ENDIAN style. If position is constant, compute new
6222 position. Otherwise, build subtraction.
6223 Note that POS is relative to the mode of the original argument.
6224 If it's a MEM we need to recompute POS relative to that.
6225 However, if we're extracting from (or inserting into) a register,
6226 we want to recompute POS relative to wanted_inner_mode. */
6227 int width
= (GET_CODE (inner
) == MEM
6228 ? GET_MODE_BITSIZE (is_mode
)
6229 : GET_MODE_BITSIZE (wanted_inner_mode
));
6232 pos
= width
- len
- pos
;
6235 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6236 /* POS may be less than 0 now, but we check for that below.
6237 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6240 /* If INNER has a wider mode, make it smaller. If this is a constant
6241 extract, try to adjust the byte to point to the byte containing
6243 if (wanted_inner_mode
!= VOIDmode
6244 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6245 && ((GET_CODE (inner
) == MEM
6246 && (inner_mode
== wanted_inner_mode
6247 || (! mode_dependent_address_p (XEXP (inner
, 0))
6248 && ! MEM_VOLATILE_P (inner
))))))
6252 /* The computations below will be correct if the machine is big
6253 endian in both bits and bytes or little endian in bits and bytes.
6254 If it is mixed, we must adjust. */
6256 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6257 adjust OFFSET to compensate. */
6258 if (BYTES_BIG_ENDIAN
6260 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6261 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6263 /* If this is a constant position, we can move to the desired byte. */
6266 offset
+= pos
/ BITS_PER_UNIT
;
6267 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6270 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6272 && is_mode
!= wanted_inner_mode
)
6273 offset
= (GET_MODE_SIZE (is_mode
)
6274 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6276 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6277 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6280 /* If INNER is not memory, we can always get it into the proper mode. If we
6281 are changing its mode, POS must be a constant and smaller than the size
6283 else if (GET_CODE (inner
) != MEM
)
6285 if (GET_MODE (inner
) != wanted_inner_mode
6287 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6290 inner
= force_to_mode (inner
, wanted_inner_mode
,
6292 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6293 ? ~(unsigned HOST_WIDE_INT
) 0
6294 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6299 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6300 have to zero extend. Otherwise, we can just use a SUBREG. */
6302 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6304 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6306 /* If we know that no extraneous bits are set, and that the high
6307 bit is not set, convert extraction to cheaper one - either
6308 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6310 if (flag_expensive_optimizations
6311 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6312 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6313 & ~(((unsigned HOST_WIDE_INT
)
6314 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6318 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6320 /* Prefer ZERO_EXTENSION, since it gives more information to
6322 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6327 else if (pos_rtx
!= 0
6328 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6329 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6331 /* Make POS_RTX unless we already have it and it is correct. If we don't
6332 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6334 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6335 pos_rtx
= orig_pos_rtx
;
6337 else if (pos_rtx
== 0)
6338 pos_rtx
= GEN_INT (pos
);
6340 /* Make the required operation. See if we can use existing rtx. */
6341 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6342 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6344 new = gen_lowpart (mode
, new);
6349 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6350 with any other operations in X. Return X without that shift if so. */
6353 extract_left_shift (rtx x
, int count
)
6355 enum rtx_code code
= GET_CODE (x
);
6356 enum machine_mode mode
= GET_MODE (x
);
6362 /* This is the shift itself. If it is wide enough, we will return
6363 either the value being shifted if the shift count is equal to
6364 COUNT or a shift for the difference. */
6365 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6366 && INTVAL (XEXP (x
, 1)) >= count
)
6367 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6368 INTVAL (XEXP (x
, 1)) - count
);
6372 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6373 return simplify_gen_unary (code
, mode
, tem
, mode
);
6377 case PLUS
: case IOR
: case XOR
: case AND
:
6378 /* If we can safely shift this constant and we find the inner shift,
6379 make a new operation. */
6380 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6381 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6382 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6383 return gen_binary (code
, mode
, tem
,
6384 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6395 /* Look at the expression rooted at X. Look for expressions
6396 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6397 Form these expressions.
6399 Return the new rtx, usually just X.
6401 Also, for machines like the VAX that don't have logical shift insns,
6402 try to convert logical to arithmetic shift operations in cases where
6403 they are equivalent. This undoes the canonicalizations to logical
6404 shifts done elsewhere.
6406 We try, as much as possible, to re-use rtl expressions to save memory.
6408 IN_CODE says what kind of expression we are processing. Normally, it is
6409 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6410 being kludges), it is MEM. When processing the arguments of a comparison
6411 or a COMPARE against zero, it is COMPARE. */
6414 make_compound_operation (rtx x
, enum rtx_code in_code
)
6416 enum rtx_code code
= GET_CODE (x
);
6417 enum machine_mode mode
= GET_MODE (x
);
6418 int mode_width
= GET_MODE_BITSIZE (mode
);
6420 enum rtx_code next_code
;
6426 /* Select the code to be used in recursive calls. Once we are inside an
6427 address, we stay there. If we have a comparison, set to COMPARE,
6428 but once inside, go back to our default of SET. */
6430 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6431 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6432 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6433 : in_code
== COMPARE
? SET
: in_code
);
6435 /* Process depending on the code of this operation. If NEW is set
6436 nonzero, it will be returned. */
6441 /* Convert shifts by constants into multiplications if inside
6443 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6444 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6445 && INTVAL (XEXP (x
, 1)) >= 0)
6447 new = make_compound_operation (XEXP (x
, 0), next_code
);
6448 new = gen_rtx_MULT (mode
, new,
6449 GEN_INT ((HOST_WIDE_INT
) 1
6450 << INTVAL (XEXP (x
, 1))));
6455 /* If the second operand is not a constant, we can't do anything
6457 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6460 /* If the constant is a power of two minus one and the first operand
6461 is a logical right shift, make an extraction. */
6462 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6463 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6465 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6466 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6467 0, in_code
== COMPARE
);
6470 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6471 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6472 && subreg_lowpart_p (XEXP (x
, 0))
6473 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6474 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6476 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6478 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6479 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6480 0, in_code
== COMPARE
);
6482 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6483 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6484 || GET_CODE (XEXP (x
, 0)) == IOR
)
6485 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6486 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6487 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6489 /* Apply the distributive law, and then try to make extractions. */
6490 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6491 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6493 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6495 new = make_compound_operation (new, in_code
);
6498 /* If we are have (and (rotate X C) M) and C is larger than the number
6499 of bits in M, this is an extraction. */
6501 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6502 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6503 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6504 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6506 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6507 new = make_extraction (mode
, new,
6508 (GET_MODE_BITSIZE (mode
)
6509 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6510 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6513 /* On machines without logical shifts, if the operand of the AND is
6514 a logical shift and our mask turns off all the propagated sign
6515 bits, we can replace the logical shift with an arithmetic shift. */
6516 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6517 && !have_insn_for (LSHIFTRT
, mode
)
6518 && have_insn_for (ASHIFTRT
, mode
)
6519 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6520 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6521 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6522 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6524 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6526 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6527 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6529 gen_rtx_ASHIFTRT (mode
,
6530 make_compound_operation
6531 (XEXP (XEXP (x
, 0), 0), next_code
),
6532 XEXP (XEXP (x
, 0), 1)));
6535 /* If the constant is one less than a power of two, this might be
6536 representable by an extraction even if no shift is present.
6537 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6538 we are in a COMPARE. */
6539 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6540 new = make_extraction (mode
,
6541 make_compound_operation (XEXP (x
, 0),
6543 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6545 /* If we are in a comparison and this is an AND with a power of two,
6546 convert this into the appropriate bit extract. */
6547 else if (in_code
== COMPARE
6548 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6549 new = make_extraction (mode
,
6550 make_compound_operation (XEXP (x
, 0),
6552 i
, NULL_RTX
, 1, 1, 0, 1);
6557 /* If the sign bit is known to be zero, replace this with an
6558 arithmetic shift. */
6559 if (have_insn_for (ASHIFTRT
, mode
)
6560 && ! have_insn_for (LSHIFTRT
, mode
)
6561 && mode_width
<= HOST_BITS_PER_WIDE_INT
6562 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6564 new = gen_rtx_ASHIFTRT (mode
,
6565 make_compound_operation (XEXP (x
, 0),
6571 /* ... fall through ... */
6577 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6578 this is a SIGN_EXTRACT. */
6579 if (GET_CODE (rhs
) == CONST_INT
6580 && GET_CODE (lhs
) == ASHIFT
6581 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6582 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6584 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6585 new = make_extraction (mode
, new,
6586 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6587 NULL_RTX
, mode_width
- INTVAL (rhs
),
6588 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6592 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6593 If so, try to merge the shifts into a SIGN_EXTEND. We could
6594 also do this for some cases of SIGN_EXTRACT, but it doesn't
6595 seem worth the effort; the case checked for occurs on Alpha. */
6597 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6598 && ! (GET_CODE (lhs
) == SUBREG
6599 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6600 && GET_CODE (rhs
) == CONST_INT
6601 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6602 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6603 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6604 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6605 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6610 /* Call ourselves recursively on the inner expression. If we are
6611 narrowing the object and it has a different RTL code from
6612 what it originally did, do this SUBREG as a force_to_mode. */
6614 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6615 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6616 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6617 && subreg_lowpart_p (x
))
6619 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6622 /* If we have something other than a SUBREG, we might have
6623 done an expansion, so rerun ourselves. */
6624 if (GET_CODE (newer
) != SUBREG
)
6625 newer
= make_compound_operation (newer
, in_code
);
6630 /* If this is a paradoxical subreg, and the new code is a sign or
6631 zero extension, omit the subreg and widen the extension. If it
6632 is a regular subreg, we can still get rid of the subreg by not
6633 widening so much, or in fact removing the extension entirely. */
6634 if ((GET_CODE (tem
) == SIGN_EXTEND
6635 || GET_CODE (tem
) == ZERO_EXTEND
)
6636 && subreg_lowpart_p (x
))
6638 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6639 || (GET_MODE_SIZE (mode
) >
6640 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6642 if (! SCALAR_INT_MODE_P (mode
))
6644 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6647 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6658 x
= gen_lowpart (mode
, new);
6659 code
= GET_CODE (x
);
6662 /* Now recursively process each operand of this operation. */
6663 fmt
= GET_RTX_FORMAT (code
);
6664 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6667 new = make_compound_operation (XEXP (x
, i
), next_code
);
6668 SUBST (XEXP (x
, i
), new);
6674 /* Given M see if it is a value that would select a field of bits
6675 within an item, but not the entire word. Return -1 if not.
6676 Otherwise, return the starting position of the field, where 0 is the
6679 *PLEN is set to the length of the field. */
6682 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6684 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6685 int pos
= exact_log2 (m
& -m
);
6691 /* Now shift off the low-order zero bits and see if we have a power of
6693 len
= exact_log2 ((m
>> pos
) + 1);
6702 /* See if X can be simplified knowing that we will only refer to it in
6703 MODE and will only refer to those bits that are nonzero in MASK.
6704 If other bits are being computed or if masking operations are done
6705 that select a superset of the bits in MASK, they can sometimes be
6708 Return a possibly simplified expression, but always convert X to
6709 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6711 Also, if REG is nonzero and X is a register equal in value to REG,
6714 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6715 are all off in X. This is used when X will be complemented, by either
6716 NOT, NEG, or XOR. */
6719 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6720 rtx reg
, int just_select
)
6722 enum rtx_code code
= GET_CODE (x
);
6723 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6724 enum machine_mode op_mode
;
6725 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6728 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6729 code below will do the wrong thing since the mode of such an
6730 expression is VOIDmode.
6732 Also do nothing if X is a CLOBBER; this can happen if X was
6733 the return value from a call to gen_lowpart. */
6734 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6737 /* We want to perform the operation is its present mode unless we know
6738 that the operation is valid in MODE, in which case we do the operation
6740 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6741 && have_insn_for (code
, mode
))
6742 ? mode
: GET_MODE (x
));
6744 /* It is not valid to do a right-shift in a narrower mode
6745 than the one it came in with. */
6746 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6747 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6748 op_mode
= GET_MODE (x
);
6750 /* Truncate MASK to fit OP_MODE. */
6752 mask
&= GET_MODE_MASK (op_mode
);
6754 /* When we have an arithmetic operation, or a shift whose count we
6755 do not know, we need to assume that all bits up to the highest-order
6756 bit in MASK will be needed. This is how we form such a mask. */
6757 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6758 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6760 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6763 /* Determine what bits of X are guaranteed to be (non)zero. */
6764 nonzero
= nonzero_bits (x
, mode
);
6766 /* If none of the bits in X are needed, return a zero. */
6767 if (! just_select
&& (nonzero
& mask
) == 0)
6770 /* If X is a CONST_INT, return a new one. Do this here since the
6771 test below will fail. */
6772 if (GET_CODE (x
) == CONST_INT
)
6774 if (SCALAR_INT_MODE_P (mode
))
6775 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6778 x
= GEN_INT (INTVAL (x
) & mask
);
6779 return gen_lowpart_common (mode
, x
);
6783 /* If X is narrower than MODE and we want all the bits in X's mode, just
6784 get X in the proper mode. */
6785 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6786 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6787 return gen_lowpart (mode
, x
);
6789 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6790 MASK are already known to be zero in X, we need not do anything. */
6791 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6797 /* If X is a (clobber (const_int)), return it since we know we are
6798 generating something that won't match. */
6802 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6803 spanned the boundary of the MEM. If we are now masking so it is
6804 within that boundary, we don't need the USE any more. */
6805 if (! BITS_BIG_ENDIAN
6806 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6807 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6814 x
= expand_compound_operation (x
);
6815 if (GET_CODE (x
) != code
)
6816 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6820 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6821 || rtx_equal_p (reg
, get_last_value (x
))))
6826 if (subreg_lowpart_p (x
)
6827 /* We can ignore the effect of this SUBREG if it narrows the mode or
6828 if the constant masks to zero all the bits the mode doesn't
6830 && ((GET_MODE_SIZE (GET_MODE (x
))
6831 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6833 & GET_MODE_MASK (GET_MODE (x
))
6834 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6835 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6839 /* If this is an AND with a constant, convert it into an AND
6840 whose constant is the AND of that constant with MASK. If it
6841 remains an AND of MASK, delete it since it is redundant. */
6843 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6845 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6846 mask
& INTVAL (XEXP (x
, 1)));
6848 /* If X is still an AND, see if it is an AND with a mask that
6849 is just some low-order bits. If so, and it is MASK, we don't
6852 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6853 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6857 /* If it remains an AND, try making another AND with the bits
6858 in the mode mask that aren't in MASK turned on. If the
6859 constant in the AND is wide enough, this might make a
6860 cheaper constant. */
6862 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6863 && GET_MODE_MASK (GET_MODE (x
)) != mask
6864 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6866 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6867 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6868 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6871 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6872 number, sign extend it. */
6873 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6874 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6875 cval
|= (HOST_WIDE_INT
) -1 << width
;
6877 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6878 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6888 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6889 low-order bits (as in an alignment operation) and FOO is already
6890 aligned to that boundary, mask C1 to that boundary as well.
6891 This may eliminate that PLUS and, later, the AND. */
6894 unsigned int width
= GET_MODE_BITSIZE (mode
);
6895 unsigned HOST_WIDE_INT smask
= mask
;
6897 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6898 number, sign extend it. */
6900 if (width
< HOST_BITS_PER_WIDE_INT
6901 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6902 smask
|= (HOST_WIDE_INT
) -1 << width
;
6904 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6905 && exact_log2 (- smask
) >= 0
6906 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6907 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6908 return force_to_mode (plus_constant (XEXP (x
, 0),
6909 (INTVAL (XEXP (x
, 1)) & smask
)),
6910 mode
, smask
, reg
, next_select
);
6913 /* ... fall through ... */
6916 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6917 most significant bit in MASK since carries from those bits will
6918 affect the bits we are interested in. */
6923 /* If X is (minus C Y) where C's least set bit is larger than any bit
6924 in the mask, then we may replace with (neg Y). */
6925 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6926 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6927 & -INTVAL (XEXP (x
, 0))))
6930 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6932 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6935 /* Similarly, if C contains every bit in the fuller_mask, then we may
6936 replace with (not Y). */
6937 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6938 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6939 == INTVAL (XEXP (x
, 0))))
6941 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6942 XEXP (x
, 1), GET_MODE (x
));
6943 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6951 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6952 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6953 operation which may be a bitfield extraction. Ensure that the
6954 constant we form is not wider than the mode of X. */
6956 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6957 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6958 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6959 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6960 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6961 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6962 + floor_log2 (INTVAL (XEXP (x
, 1))))
6963 < GET_MODE_BITSIZE (GET_MODE (x
)))
6964 && (INTVAL (XEXP (x
, 1))
6965 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6967 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6968 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6969 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6970 XEXP (XEXP (x
, 0), 0), temp
);
6971 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6972 XEXP (XEXP (x
, 0), 1));
6973 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6977 /* For most binary operations, just propagate into the operation and
6978 change the mode if we have an operation of that mode. */
6980 op0
= gen_lowpart (op_mode
,
6981 force_to_mode (XEXP (x
, 0), mode
, mask
,
6983 op1
= gen_lowpart (op_mode
,
6984 force_to_mode (XEXP (x
, 1), mode
, mask
,
6987 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6988 x
= gen_binary (code
, op_mode
, op0
, op1
);
6992 /* For left shifts, do the same, but just for the first operand.
6993 However, we cannot do anything with shifts where we cannot
6994 guarantee that the counts are smaller than the size of the mode
6995 because such a count will have a different meaning in a
6998 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6999 && INTVAL (XEXP (x
, 1)) >= 0
7000 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7001 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7002 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7003 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7006 /* If the shift count is a constant and we can do arithmetic in
7007 the mode of the shift, refine which bits we need. Otherwise, use the
7008 conservative form of the mask. */
7009 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7010 && INTVAL (XEXP (x
, 1)) >= 0
7011 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7012 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7013 mask
>>= INTVAL (XEXP (x
, 1));
7017 op0
= gen_lowpart (op_mode
,
7018 force_to_mode (XEXP (x
, 0), op_mode
,
7019 mask
, reg
, next_select
));
7021 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7022 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7026 /* Here we can only do something if the shift count is a constant,
7027 this shift constant is valid for the host, and we can do arithmetic
7030 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7031 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7032 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7034 rtx inner
= XEXP (x
, 0);
7035 unsigned HOST_WIDE_INT inner_mask
;
7037 /* Select the mask of the bits we need for the shift operand. */
7038 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7040 /* We can only change the mode of the shift if we can do arithmetic
7041 in the mode of the shift and INNER_MASK is no wider than the
7042 width of OP_MODE. */
7043 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7044 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7045 op_mode
= GET_MODE (x
);
7047 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7049 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7050 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7053 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7054 shift and AND produces only copies of the sign bit (C2 is one less
7055 than a power of two), we can do this with just a shift. */
7057 if (GET_CODE (x
) == LSHIFTRT
7058 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7059 /* The shift puts one of the sign bit copies in the least significant
7061 && ((INTVAL (XEXP (x
, 1))
7062 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7063 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7064 && exact_log2 (mask
+ 1) >= 0
7065 /* Number of bits left after the shift must be more than the mask
7067 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7068 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7069 /* Must be more sign bit copies than the mask needs. */
7070 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7071 >= exact_log2 (mask
+ 1)))
7072 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7073 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7074 - exact_log2 (mask
+ 1)));
7079 /* If we are just looking for the sign bit, we don't need this shift at
7080 all, even if it has a variable count. */
7081 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7082 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7083 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7084 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7086 /* If this is a shift by a constant, get a mask that contains those bits
7087 that are not copies of the sign bit. We then have two cases: If
7088 MASK only includes those bits, this can be a logical shift, which may
7089 allow simplifications. If MASK is a single-bit field not within
7090 those bits, we are requesting a copy of the sign bit and hence can
7091 shift the sign bit to the appropriate location. */
7093 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7094 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7098 /* If the considered data is wider than HOST_WIDE_INT, we can't
7099 represent a mask for all its bits in a single scalar.
7100 But we only care about the lower bits, so calculate these. */
7102 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7104 nonzero
= ~(HOST_WIDE_INT
) 0;
7106 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7107 is the number of bits a full-width mask would have set.
7108 We need only shift if these are fewer than nonzero can
7109 hold. If not, we must keep all bits set in nonzero. */
7111 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7112 < HOST_BITS_PER_WIDE_INT
)
7113 nonzero
>>= INTVAL (XEXP (x
, 1))
7114 + HOST_BITS_PER_WIDE_INT
7115 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7119 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7120 nonzero
>>= INTVAL (XEXP (x
, 1));
7123 if ((mask
& ~nonzero
) == 0
7124 || (i
= exact_log2 (mask
)) >= 0)
7126 x
= simplify_shift_const
7127 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7128 i
< 0 ? INTVAL (XEXP (x
, 1))
7129 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7131 if (GET_CODE (x
) != ASHIFTRT
)
7132 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7136 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7137 even if the shift count isn't a constant. */
7139 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7143 /* If this is a zero- or sign-extension operation that just affects bits
7144 we don't care about, remove it. Be sure the call above returned
7145 something that is still a shift. */
7147 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7148 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7149 && INTVAL (XEXP (x
, 1)) >= 0
7150 && (INTVAL (XEXP (x
, 1))
7151 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7152 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7153 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7154 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7161 /* If the shift count is constant and we can do computations
7162 in the mode of X, compute where the bits we care about are.
7163 Otherwise, we can't do anything. Don't change the mode of
7164 the shift or propagate MODE into the shift, though. */
7165 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7166 && INTVAL (XEXP (x
, 1)) >= 0)
7168 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7169 GET_MODE (x
), GEN_INT (mask
),
7171 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7173 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7174 INTVAL (temp
), reg
, next_select
));
7179 /* If we just want the low-order bit, the NEG isn't needed since it
7180 won't change the low-order bit. */
7182 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7184 /* We need any bits less significant than the most significant bit in
7185 MASK since carries from those bits will affect the bits we are
7191 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7192 same as the XOR case above. Ensure that the constant we form is not
7193 wider than the mode of X. */
7195 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7196 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7197 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7198 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7199 < GET_MODE_BITSIZE (GET_MODE (x
)))
7200 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7202 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7204 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7205 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7207 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7210 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7211 use the full mask inside the NOT. */
7215 op0
= gen_lowpart (op_mode
,
7216 force_to_mode (XEXP (x
, 0), mode
, mask
,
7218 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7219 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7223 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7224 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7225 which is equal to STORE_FLAG_VALUE. */
7226 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7227 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7228 && (nonzero_bits (XEXP (x
, 0), mode
)
7229 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7230 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7235 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7236 written in a narrower mode. We play it safe and do not do so. */
7239 gen_lowpart (GET_MODE (x
),
7240 force_to_mode (XEXP (x
, 1), mode
,
7241 mask
, reg
, next_select
)));
7243 gen_lowpart (GET_MODE (x
),
7244 force_to_mode (XEXP (x
, 2), mode
,
7245 mask
, reg
, next_select
)));
7252 /* Ensure we return a value of the proper mode. */
7253 return gen_lowpart (mode
, x
);
7256 /* Return nonzero if X is an expression that has one of two values depending on
7257 whether some other value is zero or nonzero. In that case, we return the
7258 value that is being tested, *PTRUE is set to the value if the rtx being
7259 returned has a nonzero value, and *PFALSE is set to the other alternative.
7261 If we return zero, we set *PTRUE and *PFALSE to X. */
7264 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7266 enum machine_mode mode
= GET_MODE (x
);
7267 enum rtx_code code
= GET_CODE (x
);
7268 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7269 unsigned HOST_WIDE_INT nz
;
7271 /* If we are comparing a value against zero, we are done. */
7272 if ((code
== NE
|| code
== EQ
)
7273 && XEXP (x
, 1) == const0_rtx
)
7275 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7276 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7280 /* If this is a unary operation whose operand has one of two values, apply
7281 our opcode to compute those values. */
7282 else if (GET_RTX_CLASS (code
) == '1'
7283 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7285 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7286 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7287 GET_MODE (XEXP (x
, 0)));
7291 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7292 make can't possibly match and would suppress other optimizations. */
7293 else if (code
== COMPARE
)
7296 /* If this is a binary operation, see if either side has only one of two
7297 values. If either one does or if both do and they are conditional on
7298 the same value, compute the new true and false values. */
7299 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7300 || GET_RTX_CLASS (code
) == '<')
7302 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7303 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7305 if ((cond0
!= 0 || cond1
!= 0)
7306 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7308 /* If if_then_else_cond returned zero, then true/false are the
7309 same rtl. We must copy one of them to prevent invalid rtl
7312 true0
= copy_rtx (true0
);
7313 else if (cond1
== 0)
7314 true1
= copy_rtx (true1
);
7316 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7317 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7318 return cond0
? cond0
: cond1
;
7321 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7322 operands is zero when the other is nonzero, and vice-versa,
7323 and STORE_FLAG_VALUE is 1 or -1. */
7325 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7326 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7328 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7330 rtx op0
= XEXP (XEXP (x
, 0), 1);
7331 rtx op1
= XEXP (XEXP (x
, 1), 1);
7333 cond0
= XEXP (XEXP (x
, 0), 0);
7334 cond1
= XEXP (XEXP (x
, 1), 0);
7336 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7337 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7338 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7339 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7340 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7341 || ((swap_condition (GET_CODE (cond0
))
7342 == combine_reversed_comparison_code (cond1
))
7343 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7344 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7345 && ! side_effects_p (x
))
7347 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7348 *pfalse
= gen_binary (MULT
, mode
,
7350 ? simplify_gen_unary (NEG
, mode
, op1
,
7358 /* Similarly for MULT, AND and UMIN, except that for these the result
7360 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7361 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7362 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7364 cond0
= XEXP (XEXP (x
, 0), 0);
7365 cond1
= XEXP (XEXP (x
, 1), 0);
7367 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7368 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7369 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7370 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7371 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7372 || ((swap_condition (GET_CODE (cond0
))
7373 == combine_reversed_comparison_code (cond1
))
7374 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7375 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7376 && ! side_effects_p (x
))
7378 *ptrue
= *pfalse
= const0_rtx
;
7384 else if (code
== IF_THEN_ELSE
)
7386 /* If we have IF_THEN_ELSE already, extract the condition and
7387 canonicalize it if it is NE or EQ. */
7388 cond0
= XEXP (x
, 0);
7389 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7390 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7391 return XEXP (cond0
, 0);
7392 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7394 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7395 return XEXP (cond0
, 0);
7401 /* If X is a SUBREG, we can narrow both the true and false values
7402 if the inner expression, if there is a condition. */
7403 else if (code
== SUBREG
7404 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7407 *ptrue
= simplify_gen_subreg (mode
, true0
,
7408 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7409 *pfalse
= simplify_gen_subreg (mode
, false0
,
7410 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7415 /* If X is a constant, this isn't special and will cause confusions
7416 if we treat it as such. Likewise if it is equivalent to a constant. */
7417 else if (CONSTANT_P (x
)
7418 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7421 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7422 will be least confusing to the rest of the compiler. */
7423 else if (mode
== BImode
)
7425 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7429 /* If X is known to be either 0 or -1, those are the true and
7430 false values when testing X. */
7431 else if (x
== constm1_rtx
|| x
== const0_rtx
7432 || (mode
!= VOIDmode
7433 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7435 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7439 /* Likewise for 0 or a single bit. */
7440 else if (SCALAR_INT_MODE_P (mode
)
7441 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7442 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7444 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7448 /* Otherwise fail; show no condition with true and false values the same. */
7449 *ptrue
= *pfalse
= x
;
7453 /* Return the value of expression X given the fact that condition COND
7454 is known to be true when applied to REG as its first operand and VAL
7455 as its second. X is known to not be shared and so can be modified in
7458 We only handle the simplest cases, and specifically those cases that
7459 arise with IF_THEN_ELSE expressions. */
7462 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7464 enum rtx_code code
= GET_CODE (x
);
7469 if (side_effects_p (x
))
7472 /* If either operand of the condition is a floating point value,
7473 then we have to avoid collapsing an EQ comparison. */
7475 && rtx_equal_p (x
, reg
)
7476 && ! FLOAT_MODE_P (GET_MODE (x
))
7477 && ! FLOAT_MODE_P (GET_MODE (val
)))
7480 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7483 /* If X is (abs REG) and we know something about REG's relationship
7484 with zero, we may be able to simplify this. */
7486 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7489 case GE
: case GT
: case EQ
:
7492 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7494 GET_MODE (XEXP (x
, 0)));
7499 /* The only other cases we handle are MIN, MAX, and comparisons if the
7500 operands are the same as REG and VAL. */
7502 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7504 if (rtx_equal_p (XEXP (x
, 0), val
))
7505 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7507 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7509 if (GET_RTX_CLASS (code
) == '<')
7511 if (comparison_dominates_p (cond
, code
))
7512 return const_true_rtx
;
7514 code
= combine_reversed_comparison_code (x
);
7516 && comparison_dominates_p (cond
, code
))
7521 else if (code
== SMAX
|| code
== SMIN
7522 || code
== UMIN
|| code
== UMAX
)
7524 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7526 /* Do not reverse the condition when it is NE or EQ.
7527 This is because we cannot conclude anything about
7528 the value of 'SMAX (x, y)' when x is not equal to y,
7529 but we can when x equals y. */
7530 if ((code
== SMAX
|| code
== UMAX
)
7531 && ! (cond
== EQ
|| cond
== NE
))
7532 cond
= reverse_condition (cond
);
7537 return unsignedp
? x
: XEXP (x
, 1);
7539 return unsignedp
? x
: XEXP (x
, 0);
7541 return unsignedp
? XEXP (x
, 1) : x
;
7543 return unsignedp
? XEXP (x
, 0) : x
;
7550 else if (code
== SUBREG
)
7552 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7553 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7555 if (SUBREG_REG (x
) != r
)
7557 /* We must simplify subreg here, before we lose track of the
7558 original inner_mode. */
7559 new = simplify_subreg (GET_MODE (x
), r
,
7560 inner_mode
, SUBREG_BYTE (x
));
7564 SUBST (SUBREG_REG (x
), r
);
7569 /* We don't have to handle SIGN_EXTEND here, because even in the
7570 case of replacing something with a modeless CONST_INT, a
7571 CONST_INT is already (supposed to be) a valid sign extension for
7572 its narrower mode, which implies it's already properly
7573 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7574 story is different. */
7575 else if (code
== ZERO_EXTEND
)
7577 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7578 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7580 if (XEXP (x
, 0) != r
)
7582 /* We must simplify the zero_extend here, before we lose
7583 track of the original inner_mode. */
7584 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7589 SUBST (XEXP (x
, 0), r
);
7595 fmt
= GET_RTX_FORMAT (code
);
7596 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7599 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7600 else if (fmt
[i
] == 'E')
7601 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7602 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7609 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7610 assignment as a field assignment. */
7613 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7615 if (x
== y
|| rtx_equal_p (x
, y
))
7618 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7621 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7622 Note that all SUBREGs of MEM are paradoxical; otherwise they
7623 would have been rewritten. */
7624 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7625 && GET_CODE (SUBREG_REG (y
)) == MEM
7626 && rtx_equal_p (SUBREG_REG (y
),
7627 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7630 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7631 && GET_CODE (SUBREG_REG (x
)) == MEM
7632 && rtx_equal_p (SUBREG_REG (x
),
7633 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7636 /* We used to see if get_last_value of X and Y were the same but that's
7637 not correct. In one direction, we'll cause the assignment to have
7638 the wrong destination and in the case, we'll import a register into this
7639 insn that might have already have been dead. So fail if none of the
7640 above cases are true. */
7644 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7645 Return that assignment if so.
7647 We only handle the most common cases. */
7650 make_field_assignment (rtx x
)
7652 rtx dest
= SET_DEST (x
);
7653 rtx src
= SET_SRC (x
);
7658 unsigned HOST_WIDE_INT len
;
7660 enum machine_mode mode
;
7662 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7663 a clear of a one-bit field. We will have changed it to
7664 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7667 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7668 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7669 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7670 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7672 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7675 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7679 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7680 && subreg_lowpart_p (XEXP (src
, 0))
7681 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7682 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7683 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7684 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7685 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7686 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7688 assign
= make_extraction (VOIDmode
, dest
, 0,
7689 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7692 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7696 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7698 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7699 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7700 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7702 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7705 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7709 /* The other case we handle is assignments into a constant-position
7710 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7711 a mask that has all one bits except for a group of zero bits and
7712 OTHER is known to have zeros where C1 has ones, this is such an
7713 assignment. Compute the position and length from C1. Shift OTHER
7714 to the appropriate position, force it to the required mode, and
7715 make the extraction. Check for the AND in both operands. */
7717 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7720 rhs
= expand_compound_operation (XEXP (src
, 0));
7721 lhs
= expand_compound_operation (XEXP (src
, 1));
7723 if (GET_CODE (rhs
) == AND
7724 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7725 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7726 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7727 else if (GET_CODE (lhs
) == AND
7728 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7729 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7730 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7734 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7735 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7736 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7737 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7740 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7744 /* The mode to use for the source is the mode of the assignment, or of
7745 what is inside a possible STRICT_LOW_PART. */
7746 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7747 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7749 /* Shift OTHER right POS places and make it the source, restricting it
7750 to the proper length and mode. */
7752 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7753 GET_MODE (src
), other
, pos
),
7755 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7756 ? ~(unsigned HOST_WIDE_INT
) 0
7757 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7760 /* If SRC is masked by an AND that does not make a difference in
7761 the value being stored, strip it. */
7762 if (GET_CODE (assign
) == ZERO_EXTRACT
7763 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7764 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7765 && GET_CODE (src
) == AND
7766 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7767 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7768 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7769 src
= XEXP (src
, 0);
7771 return gen_rtx_SET (VOIDmode
, assign
, src
);
7774 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7778 apply_distributive_law (rtx x
)
7780 enum rtx_code code
= GET_CODE (x
);
7781 enum rtx_code inner_code
;
7782 rtx lhs
, rhs
, other
;
7785 /* Distributivity is not true for floating point as it can change the
7786 value. So we don't do it unless -funsafe-math-optimizations. */
7787 if (FLOAT_MODE_P (GET_MODE (x
))
7788 && ! flag_unsafe_math_optimizations
)
7791 /* The outer operation can only be one of the following: */
7792 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7793 && code
!= PLUS
&& code
!= MINUS
)
7799 /* If either operand is a primitive we can't do anything, so get out
7801 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7802 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7805 lhs
= expand_compound_operation (lhs
);
7806 rhs
= expand_compound_operation (rhs
);
7807 inner_code
= GET_CODE (lhs
);
7808 if (inner_code
!= GET_CODE (rhs
))
7811 /* See if the inner and outer operations distribute. */
7818 /* These all distribute except over PLUS. */
7819 if (code
== PLUS
|| code
== MINUS
)
7824 if (code
!= PLUS
&& code
!= MINUS
)
7829 /* This is also a multiply, so it distributes over everything. */
7833 /* Non-paradoxical SUBREGs distributes over all operations, provided
7834 the inner modes and byte offsets are the same, this is an extraction
7835 of a low-order part, we don't convert an fp operation to int or
7836 vice versa, and we would not be converting a single-word
7837 operation into a multi-word operation. The latter test is not
7838 required, but it prevents generating unneeded multi-word operations.
7839 Some of the previous tests are redundant given the latter test, but
7840 are retained because they are required for correctness.
7842 We produce the result slightly differently in this case. */
7844 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7845 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7846 || ! subreg_lowpart_p (lhs
)
7847 || (GET_MODE_CLASS (GET_MODE (lhs
))
7848 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7849 || (GET_MODE_SIZE (GET_MODE (lhs
))
7850 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7851 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7854 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7855 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7856 return gen_lowpart (GET_MODE (x
), tem
);
7862 /* Set LHS and RHS to the inner operands (A and B in the example
7863 above) and set OTHER to the common operand (C in the example).
7864 These is only one way to do this unless the inner operation is
7866 if (GET_RTX_CLASS (inner_code
) == 'c'
7867 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7868 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7869 else if (GET_RTX_CLASS (inner_code
) == 'c'
7870 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7871 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7872 else if (GET_RTX_CLASS (inner_code
) == 'c'
7873 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7874 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7875 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7876 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7880 /* Form the new inner operation, seeing if it simplifies first. */
7881 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7883 /* There is one exception to the general way of distributing:
7884 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7885 if (code
== XOR
&& inner_code
== IOR
)
7888 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7891 /* We may be able to continuing distributing the result, so call
7892 ourselves recursively on the inner operation before forming the
7893 outer operation, which we return. */
7894 return gen_binary (inner_code
, GET_MODE (x
),
7895 apply_distributive_law (tem
), other
);
7898 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7901 Return an equivalent form, if different from X. Otherwise, return X. If
7902 X is zero, we are to always construct the equivalent form. */
7905 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7906 unsigned HOST_WIDE_INT constop
)
7908 unsigned HOST_WIDE_INT nonzero
;
7911 /* Simplify VAROP knowing that we will be only looking at some of the
7914 Note by passing in CONSTOP, we guarantee that the bits not set in
7915 CONSTOP are not significant and will never be examined. We must
7916 ensure that is the case by explicitly masking out those bits
7917 before returning. */
7918 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7920 /* If VAROP is a CLOBBER, we will fail so return it. */
7921 if (GET_CODE (varop
) == CLOBBER
)
7924 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7925 to VAROP and return the new constant. */
7926 if (GET_CODE (varop
) == CONST_INT
)
7927 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7929 /* See what bits may be nonzero in VAROP. Unlike the general case of
7930 a call to nonzero_bits, here we don't care about bits outside
7933 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7935 /* Turn off all bits in the constant that are known to already be zero.
7936 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7937 which is tested below. */
7941 /* If we don't have any bits left, return zero. */
7945 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7946 a power of two, we can replace this with an ASHIFT. */
7947 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7948 && (i
= exact_log2 (constop
)) >= 0)
7949 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7951 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7952 or XOR, then try to apply the distributive law. This may eliminate
7953 operations if either branch can be simplified because of the AND.
7954 It may also make some cases more complex, but those cases probably
7955 won't match a pattern either with or without this. */
7957 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7961 apply_distributive_law
7962 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7963 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7964 XEXP (varop
, 0), constop
),
7965 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7966 XEXP (varop
, 1), constop
))));
7968 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7969 the AND and see if one of the operands simplifies to zero. If so, we
7970 may eliminate it. */
7972 if (GET_CODE (varop
) == PLUS
7973 && exact_log2 (constop
+ 1) >= 0)
7977 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7978 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7979 if (o0
== const0_rtx
)
7981 if (o1
== const0_rtx
)
7985 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7986 if we already had one (just check for the simplest cases). */
7987 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7988 && GET_MODE (XEXP (x
, 0)) == mode
7989 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7990 varop
= XEXP (x
, 0);
7992 varop
= gen_lowpart (mode
, varop
);
7994 /* If we can't make the SUBREG, try to return what we were given. */
7995 if (GET_CODE (varop
) == CLOBBER
)
7996 return x
? x
: varop
;
7998 /* If we are only masking insignificant bits, return VAROP. */
7999 if (constop
== nonzero
)
8003 /* Otherwise, return an AND. */
8004 constop
= trunc_int_for_mode (constop
, mode
);
8005 /* See how much, if any, of X we can use. */
8006 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8007 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8011 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8012 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8013 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8015 SUBST (XEXP (x
, 0), varop
);
8022 #define nonzero_bits_with_known(X, MODE) \
8023 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8025 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8026 It avoids exponential behavior in nonzero_bits1 when X has
8027 identical subexpressions on the first or the second level. */
8029 static unsigned HOST_WIDE_INT
8030 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8031 enum machine_mode known_mode
,
8032 unsigned HOST_WIDE_INT known_ret
)
8034 if (x
== known_x
&& mode
== known_mode
)
8037 /* Try to find identical subexpressions. If found call
8038 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8039 precomputed value for the subexpression as KNOWN_RET. */
8041 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8042 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8044 rtx x0
= XEXP (x
, 0);
8045 rtx x1
= XEXP (x
, 1);
8047 /* Check the first level. */
8049 return nonzero_bits1 (x
, mode
, x0
, mode
,
8050 nonzero_bits_with_known (x0
, mode
));
8052 /* Check the second level. */
8053 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8054 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8055 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8056 return nonzero_bits1 (x
, mode
, x1
, mode
,
8057 nonzero_bits_with_known (x1
, mode
));
8059 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8060 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8061 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8062 return nonzero_bits1 (x
, mode
, x0
, mode
,
8063 nonzero_bits_with_known (x0
, mode
));
8066 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8069 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8070 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8071 is less useful. We can't allow both, because that results in exponential
8072 run time recursion. There is a nullstone testcase that triggered
8073 this. This macro avoids accidental uses of num_sign_bit_copies. */
8074 #define cached_num_sign_bit_copies()
8076 /* Given an expression, X, compute which bits in X can be nonzero.
8077 We don't care about bits outside of those defined in MODE.
8079 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8080 a shift, AND, or zero_extract, we can do better. */
8082 static unsigned HOST_WIDE_INT
8083 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8084 enum machine_mode known_mode
,
8085 unsigned HOST_WIDE_INT known_ret
)
8087 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8088 unsigned HOST_WIDE_INT inner_nz
;
8090 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8093 /* For floating-point values, assume all bits are needed. */
8094 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8097 /* If X is wider than MODE, use its mode instead. */
8098 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8100 mode
= GET_MODE (x
);
8101 nonzero
= GET_MODE_MASK (mode
);
8102 mode_width
= GET_MODE_BITSIZE (mode
);
8105 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8106 /* Our only callers in this case look for single bit values. So
8107 just return the mode mask. Those tests will then be false. */
8110 #ifndef WORD_REGISTER_OPERATIONS
8111 /* If MODE is wider than X, but both are a single word for both the host
8112 and target machines, we can compute this from which bits of the
8113 object might be nonzero in its own mode, taking into account the fact
8114 that on many CISC machines, accessing an object in a wider mode
8115 causes the high-order bits to become undefined. So they are
8116 not known to be zero. */
8118 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8119 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8120 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8121 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8123 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8124 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8129 code
= GET_CODE (x
);
8133 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8134 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8135 all the bits above ptr_mode are known to be zero. */
8136 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8138 nonzero
&= GET_MODE_MASK (ptr_mode
);
8141 /* Include declared information about alignment of pointers. */
8142 /* ??? We don't properly preserve REG_POINTER changes across
8143 pointer-to-integer casts, so we can't trust it except for
8144 things that we know must be pointers. See execute/960116-1.c. */
8145 if ((x
== stack_pointer_rtx
8146 || x
== frame_pointer_rtx
8147 || x
== arg_pointer_rtx
)
8148 && REGNO_POINTER_ALIGN (REGNO (x
)))
8150 unsigned HOST_WIDE_INT alignment
8151 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8153 #ifdef PUSH_ROUNDING
8154 /* If PUSH_ROUNDING is defined, it is possible for the
8155 stack to be momentarily aligned only to that amount,
8156 so we pick the least alignment. */
8157 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8158 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8162 nonzero
&= ~(alignment
- 1);
8165 /* If X is a register whose nonzero bits value is current, use it.
8166 Otherwise, if X is a register whose value we can find, use that
8167 value. Otherwise, use the previously-computed global nonzero bits
8168 for this register. */
8170 if (reg_last_set_value
[REGNO (x
)] != 0
8171 && (reg_last_set_mode
[REGNO (x
)] == mode
8172 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8173 && GET_MODE_CLASS (mode
) == MODE_INT
))
8174 && (reg_last_set_label
[REGNO (x
)] == label_tick
8175 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8176 && REG_N_SETS (REGNO (x
)) == 1
8177 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8179 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8180 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8182 tem
= get_last_value (x
);
8186 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8187 /* If X is narrower than MODE and TEM is a non-negative
8188 constant that would appear negative in the mode of X,
8189 sign-extend it for use in reg_nonzero_bits because some
8190 machines (maybe most) will actually do the sign-extension
8191 and this is the conservative approach.
8193 ??? For 2.5, try to tighten up the MD files in this regard
8194 instead of this kludge. */
8196 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8197 && GET_CODE (tem
) == CONST_INT
8199 && 0 != (INTVAL (tem
)
8200 & ((HOST_WIDE_INT
) 1
8201 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8202 tem
= GEN_INT (INTVAL (tem
)
8203 | ((HOST_WIDE_INT
) (-1)
8204 << GET_MODE_BITSIZE (GET_MODE (x
))));
8206 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8208 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8210 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8212 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8213 /* We don't know anything about the upper bits. */
8214 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8215 return nonzero
& mask
;
8221 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8222 /* If X is negative in MODE, sign-extend the value. */
8223 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8224 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8225 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8231 #ifdef LOAD_EXTEND_OP
8232 /* In many, if not most, RISC machines, reading a byte from memory
8233 zeros the rest of the register. Noticing that fact saves a lot
8234 of extra zero-extends. */
8235 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8236 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8241 case UNEQ
: case LTGT
:
8242 case GT
: case GTU
: case UNGT
:
8243 case LT
: case LTU
: case UNLT
:
8244 case GE
: case GEU
: case UNGE
:
8245 case LE
: case LEU
: case UNLE
:
8246 case UNORDERED
: case ORDERED
:
8248 /* If this produces an integer result, we know which bits are set.
8249 Code here used to clear bits outside the mode of X, but that is
8252 if (GET_MODE_CLASS (mode
) == MODE_INT
8253 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8254 nonzero
= STORE_FLAG_VALUE
;
8259 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8260 and num_sign_bit_copies. */
8261 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8262 == GET_MODE_BITSIZE (GET_MODE (x
)))
8266 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8267 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8272 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8273 and num_sign_bit_copies. */
8274 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8275 == GET_MODE_BITSIZE (GET_MODE (x
)))
8281 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8282 & GET_MODE_MASK (mode
));
8286 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8287 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8288 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8292 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8293 Otherwise, show all the bits in the outer mode but not the inner
8295 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8296 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8298 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8300 & (((HOST_WIDE_INT
) 1
8301 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8302 inner_nz
|= (GET_MODE_MASK (mode
)
8303 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8306 nonzero
&= inner_nz
;
8310 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8311 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8315 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8317 unsigned HOST_WIDE_INT nonzero0
=
8318 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8320 /* Don't call nonzero_bits for the second time if it cannot change
8322 if ((nonzero
& nonzero0
) != nonzero
)
8323 nonzero
&= (nonzero0
8324 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8328 case PLUS
: case MINUS
:
8330 case DIV
: case UDIV
:
8331 case MOD
: case UMOD
:
8332 /* We can apply the rules of arithmetic to compute the number of
8333 high- and low-order zero bits of these operations. We start by
8334 computing the width (position of the highest-order nonzero bit)
8335 and the number of low-order zero bits for each value. */
8337 unsigned HOST_WIDE_INT nz0
=
8338 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8339 unsigned HOST_WIDE_INT nz1
=
8340 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8341 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8342 int width0
= floor_log2 (nz0
) + 1;
8343 int width1
= floor_log2 (nz1
) + 1;
8344 int low0
= floor_log2 (nz0
& -nz0
);
8345 int low1
= floor_log2 (nz1
& -nz1
);
8346 HOST_WIDE_INT op0_maybe_minusp
8347 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8348 HOST_WIDE_INT op1_maybe_minusp
8349 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8350 unsigned int result_width
= mode_width
;
8356 result_width
= MAX (width0
, width1
) + 1;
8357 result_low
= MIN (low0
, low1
);
8360 result_low
= MIN (low0
, low1
);
8363 result_width
= width0
+ width1
;
8364 result_low
= low0
+ low1
;
8369 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8370 result_width
= width0
;
8375 result_width
= width0
;
8380 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8381 result_width
= MIN (width0
, width1
);
8382 result_low
= MIN (low0
, low1
);
8387 result_width
= MIN (width0
, width1
);
8388 result_low
= MIN (low0
, low1
);
8394 if (result_width
< mode_width
)
8395 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8398 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8400 #ifdef POINTERS_EXTEND_UNSIGNED
8401 /* If pointers extend unsigned and this is an addition or subtraction
8402 to a pointer in Pmode, all the bits above ptr_mode are known to be
8404 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8405 && (code
== PLUS
|| code
== MINUS
)
8406 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8407 nonzero
&= GET_MODE_MASK (ptr_mode
);
8413 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8414 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8415 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8419 /* If this is a SUBREG formed for a promoted variable that has
8420 been zero-extended, we know that at least the high-order bits
8421 are zero, though others might be too. */
8423 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8424 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8425 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8427 /* If the inner mode is a single word for both the host and target
8428 machines, we can compute this from which bits of the inner
8429 object might be nonzero. */
8430 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8431 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8432 <= HOST_BITS_PER_WIDE_INT
))
8434 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8436 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8437 /* If this is a typical RISC machine, we only have to worry
8438 about the way loads are extended. */
8439 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8441 & (((unsigned HOST_WIDE_INT
) 1
8442 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8444 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8445 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8448 /* On many CISC machines, accessing an object in a wider mode
8449 causes the high-order bits to become undefined. So they are
8450 not known to be zero. */
8451 if (GET_MODE_SIZE (GET_MODE (x
))
8452 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8453 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8454 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8463 /* The nonzero bits are in two classes: any bits within MODE
8464 that aren't in GET_MODE (x) are always significant. The rest of the
8465 nonzero bits are those that are significant in the operand of
8466 the shift when shifted the appropriate number of bits. This
8467 shows that high-order bits are cleared by the right shift and
8468 low-order bits by left shifts. */
8469 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8470 && INTVAL (XEXP (x
, 1)) >= 0
8471 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8473 enum machine_mode inner_mode
= GET_MODE (x
);
8474 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8475 int count
= INTVAL (XEXP (x
, 1));
8476 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8477 unsigned HOST_WIDE_INT op_nonzero
=
8478 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8479 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8480 unsigned HOST_WIDE_INT outer
= 0;
8482 if (mode_width
> width
)
8483 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8485 if (code
== LSHIFTRT
)
8487 else if (code
== ASHIFTRT
)
8491 /* If the sign bit may have been nonzero before the shift, we
8492 need to mark all the places it could have been copied to
8493 by the shift as possibly nonzero. */
8494 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8495 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8497 else if (code
== ASHIFT
)
8500 inner
= ((inner
<< (count
% width
)
8501 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8503 nonzero
&= (outer
| inner
);
8509 /* This is at most the number of bits in the mode. */
8510 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8514 /* If CLZ has a known value at zero, then the nonzero bits are
8515 that value, plus the number of bits in the mode minus one. */
8516 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8517 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8523 /* If CTZ has a known value at zero, then the nonzero bits are
8524 that value, plus the number of bits in the mode minus one. */
8525 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8526 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8536 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8537 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8547 /* See the macro definition above. */
8548 #undef cached_num_sign_bit_copies
8550 #define num_sign_bit_copies_with_known(X, M) \
8551 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8553 /* The function cached_num_sign_bit_copies is a wrapper around
8554 num_sign_bit_copies1. It avoids exponential behavior in
8555 num_sign_bit_copies1 when X has identical subexpressions on the
8556 first or the second level. */
8559 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8560 enum machine_mode known_mode
,
8561 unsigned int known_ret
)
8563 if (x
== known_x
&& mode
== known_mode
)
8566 /* Try to find identical subexpressions. If found call
8567 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8568 the precomputed value for the subexpression as KNOWN_RET. */
8570 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8571 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8573 rtx x0
= XEXP (x
, 0);
8574 rtx x1
= XEXP (x
, 1);
8576 /* Check the first level. */
8579 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8580 num_sign_bit_copies_with_known (x0
, mode
));
8582 /* Check the second level. */
8583 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8584 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8585 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8587 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8588 num_sign_bit_copies_with_known (x1
, mode
));
8590 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8591 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8592 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8594 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8595 num_sign_bit_copies_with_known (x0
, mode
));
8598 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8601 /* Return the number of bits at the high-order end of X that are known to
8602 be equal to the sign bit. X will be used in mode MODE; if MODE is
8603 VOIDmode, X will be used in its own mode. The returned value will always
8604 be between 1 and the number of bits in MODE. */
8607 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8608 enum machine_mode known_mode
,
8609 unsigned int known_ret
)
8611 enum rtx_code code
= GET_CODE (x
);
8612 unsigned int bitwidth
;
8613 int num0
, num1
, result
;
8614 unsigned HOST_WIDE_INT nonzero
;
8617 /* If we weren't given a mode, use the mode of X. If the mode is still
8618 VOIDmode, we don't know anything. Likewise if one of the modes is
8621 if (mode
== VOIDmode
)
8622 mode
= GET_MODE (x
);
8624 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8627 bitwidth
= GET_MODE_BITSIZE (mode
);
8629 /* For a smaller object, just ignore the high bits. */
8630 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8632 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8634 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8637 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8639 #ifndef WORD_REGISTER_OPERATIONS
8640 /* If this machine does not do all register operations on the entire
8641 register and MODE is wider than the mode of X, we can say nothing
8642 at all about the high-order bits. */
8645 /* Likewise on machines that do, if the mode of the object is smaller
8646 than a word and loads of that size don't sign extend, we can say
8647 nothing about the high order bits. */
8648 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8649 #ifdef LOAD_EXTEND_OP
8650 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8661 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8662 /* If pointers extend signed and this is a pointer in Pmode, say that
8663 all the bits above ptr_mode are known to be sign bit copies. */
8664 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8666 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8669 if (reg_last_set_value
[REGNO (x
)] != 0
8670 && reg_last_set_mode
[REGNO (x
)] == mode
8671 && (reg_last_set_label
[REGNO (x
)] == label_tick
8672 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8673 && REG_N_SETS (REGNO (x
)) == 1
8674 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8676 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8677 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8679 tem
= get_last_value (x
);
8681 return num_sign_bit_copies_with_known (tem
, mode
);
8683 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8684 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8685 return reg_sign_bit_copies
[REGNO (x
)];
8689 #ifdef LOAD_EXTEND_OP
8690 /* Some RISC machines sign-extend all loads of smaller than a word. */
8691 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8692 return MAX (1, ((int) bitwidth
8693 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8698 /* If the constant is negative, take its 1's complement and remask.
8699 Then see how many zero bits we have. */
8700 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8701 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8702 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8703 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8705 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8708 /* If this is a SUBREG for a promoted object that is sign-extended
8709 and we are looking at it in a wider mode, we know that at least the
8710 high-order bits are known to be sign bit copies. */
8712 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8714 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8715 return MAX ((int) bitwidth
8716 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8720 /* For a smaller object, just ignore the high bits. */
8721 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8723 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8724 return MAX (1, (num0
8725 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8729 #ifdef WORD_REGISTER_OPERATIONS
8730 #ifdef LOAD_EXTEND_OP
8731 /* For paradoxical SUBREGs on machines where all register operations
8732 affect the entire register, just look inside. Note that we are
8733 passing MODE to the recursive call, so the number of sign bit copies
8734 will remain relative to that mode, not the inner mode. */
8736 /* This works only if loads sign extend. Otherwise, if we get a
8737 reload for the inner part, it may be loaded from the stack, and
8738 then we lose all sign bit copies that existed before the store
8741 if ((GET_MODE_SIZE (GET_MODE (x
))
8742 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8743 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8744 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8745 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8751 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8752 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8756 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8757 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8760 /* For a smaller object, just ignore the high bits. */
8761 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8762 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8766 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8768 case ROTATE
: case ROTATERT
:
8769 /* If we are rotating left by a number of bits less than the number
8770 of sign bit copies, we can just subtract that amount from the
8772 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8773 && INTVAL (XEXP (x
, 1)) >= 0
8774 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8776 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8777 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8778 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8783 /* In general, this subtracts one sign bit copy. But if the value
8784 is known to be positive, the number of sign bit copies is the
8785 same as that of the input. Finally, if the input has just one bit
8786 that might be nonzero, all the bits are copies of the sign bit. */
8787 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8788 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8789 return num0
> 1 ? num0
- 1 : 1;
8791 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8796 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8801 case IOR
: case AND
: case XOR
:
8802 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8803 /* Logical operations will preserve the number of sign-bit copies.
8804 MIN and MAX operations always return one of the operands. */
8805 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8806 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8807 return MIN (num0
, num1
);
8809 case PLUS
: case MINUS
:
8810 /* For addition and subtraction, we can have a 1-bit carry. However,
8811 if we are subtracting 1 from a positive number, there will not
8812 be such a carry. Furthermore, if the positive number is known to
8813 be 0 or 1, we know the result is either -1 or 0. */
8815 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8816 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8818 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8819 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8820 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8821 : bitwidth
- floor_log2 (nonzero
) - 1);
8824 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8825 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8826 result
= MAX (1, MIN (num0
, num1
) - 1);
8828 #ifdef POINTERS_EXTEND_UNSIGNED
8829 /* If pointers extend signed and this is an addition or subtraction
8830 to a pointer in Pmode, all the bits above ptr_mode are known to be
8832 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8833 && (code
== PLUS
|| code
== MINUS
)
8834 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8835 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8836 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8842 /* The number of bits of the product is the sum of the number of
8843 bits of both terms. However, unless one of the terms if known
8844 to be positive, we must allow for an additional bit since negating
8845 a negative number can remove one sign bit copy. */
8847 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8848 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8850 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8852 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8853 || (((nonzero_bits (XEXP (x
, 0), mode
)
8854 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8855 && ((nonzero_bits (XEXP (x
, 1), mode
)
8856 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8859 return MAX (1, result
);
8862 /* The result must be <= the first operand. If the first operand
8863 has the high bit set, we know nothing about the number of sign
8865 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8867 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8868 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8871 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8874 /* The result must be <= the second operand. */
8875 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8878 /* Similar to unsigned division, except that we have to worry about
8879 the case where the divisor is negative, in which case we have
8881 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8883 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8884 || (nonzero_bits (XEXP (x
, 1), mode
)
8885 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8891 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8893 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8894 || (nonzero_bits (XEXP (x
, 1), mode
)
8895 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8901 /* Shifts by a constant add to the number of bits equal to the
8903 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8904 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8905 && INTVAL (XEXP (x
, 1)) > 0)
8906 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8911 /* Left shifts destroy copies. */
8912 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8913 || INTVAL (XEXP (x
, 1)) < 0
8914 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8917 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8918 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8921 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8922 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8923 return MIN (num0
, num1
);
8925 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8926 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8927 case GEU
: case GTU
: case LEU
: case LTU
:
8928 case UNORDERED
: case ORDERED
:
8929 /* If the constant is negative, take its 1's complement and remask.
8930 Then see how many zero bits we have. */
8931 nonzero
= STORE_FLAG_VALUE
;
8932 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8933 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8934 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8936 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8943 /* If we haven't been able to figure it out by one of the above rules,
8944 see if some of the high-order bits are known to be zero. If so,
8945 count those bits and return one less than that amount. If we can't
8946 safely compute the mask for this mode, always return BITWIDTH. */
8948 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8951 nonzero
= nonzero_bits (x
, mode
);
8952 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8953 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8956 /* Return the number of "extended" bits there are in X, when interpreted
8957 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8958 unsigned quantities, this is the number of high-order zero bits.
8959 For signed quantities, this is the number of copies of the sign bit
8960 minus 1. In both case, this function returns the number of "spare"
8961 bits. For example, if two quantities for which this function returns
8962 at least 1 are added, the addition is known not to overflow.
8964 This function will always return 0 unless called during combine, which
8965 implies that it must be called from a define_split. */
8968 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8970 if (nonzero_sign_valid
== 0)
8974 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8975 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8976 - floor_log2 (nonzero_bits (x
, mode
)))
8978 : num_sign_bit_copies (x
, mode
) - 1);
8981 /* This function is called from `simplify_shift_const' to merge two
8982 outer operations. Specifically, we have already found that we need
8983 to perform operation *POP0 with constant *PCONST0 at the outermost
8984 position. We would now like to also perform OP1 with constant CONST1
8985 (with *POP0 being done last).
8987 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8988 the resulting operation. *PCOMP_P is set to 1 if we would need to
8989 complement the innermost operand, otherwise it is unchanged.
8991 MODE is the mode in which the operation will be done. No bits outside
8992 the width of this mode matter. It is assumed that the width of this mode
8993 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8995 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8996 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8997 result is simply *PCONST0.
8999 If the resulting operation cannot be expressed as one operation, we
9000 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9003 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9005 enum rtx_code op0
= *pop0
;
9006 HOST_WIDE_INT const0
= *pconst0
;
9008 const0
&= GET_MODE_MASK (mode
);
9009 const1
&= GET_MODE_MASK (mode
);
9011 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9015 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9018 if (op1
== NIL
|| op0
== SET
)
9021 else if (op0
== NIL
)
9022 op0
= op1
, const0
= const1
;
9024 else if (op0
== op1
)
9048 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9049 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9052 /* If the two constants aren't the same, we can't do anything. The
9053 remaining six cases can all be done. */
9054 else if (const0
!= const1
)
9062 /* (a & b) | b == b */
9064 else /* op1 == XOR */
9065 /* (a ^ b) | b == a | b */
9071 /* (a & b) ^ b == (~a) & b */
9072 op0
= AND
, *pcomp_p
= 1;
9073 else /* op1 == IOR */
9074 /* (a | b) ^ b == a & ~b */
9075 op0
= AND
, const0
= ~const0
;
9080 /* (a | b) & b == b */
9082 else /* op1 == XOR */
9083 /* (a ^ b) & b) == (~a) & b */
9090 /* Check for NO-OP cases. */
9091 const0
&= GET_MODE_MASK (mode
);
9093 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9095 else if (const0
== 0 && op0
== AND
)
9097 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9101 /* ??? Slightly redundant with the above mask, but not entirely.
9102 Moving this above means we'd have to sign-extend the mode mask
9103 for the final test. */
9104 const0
= trunc_int_for_mode (const0
, mode
);
9112 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9113 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9114 that we started with.
9116 The shift is normally computed in the widest mode we find in VAROP, as
9117 long as it isn't a different number of words than RESULT_MODE. Exceptions
9118 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9121 simplify_shift_const (rtx x
, enum rtx_code code
,
9122 enum machine_mode result_mode
, rtx varop
,
9125 enum rtx_code orig_code
= code
;
9128 enum machine_mode mode
= result_mode
;
9129 enum machine_mode shift_mode
, tmode
;
9130 unsigned int mode_words
9131 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9132 /* We form (outer_op (code varop count) (outer_const)). */
9133 enum rtx_code outer_op
= NIL
;
9134 HOST_WIDE_INT outer_const
= 0;
9136 int complement_p
= 0;
9139 /* Make sure and truncate the "natural" shift on the way in. We don't
9140 want to do this inside the loop as it makes it more difficult to
9142 if (SHIFT_COUNT_TRUNCATED
)
9143 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9145 /* If we were given an invalid count, don't do anything except exactly
9146 what was requested. */
9148 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9153 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9158 /* Unless one of the branches of the `if' in this loop does a `continue',
9159 we will `break' the loop after the `if'. */
9163 /* If we have an operand of (clobber (const_int 0)), just return that
9165 if (GET_CODE (varop
) == CLOBBER
)
9168 /* If we discovered we had to complement VAROP, leave. Making a NOT
9169 here would cause an infinite loop. */
9173 /* Convert ROTATERT to ROTATE. */
9174 if (code
== ROTATERT
)
9176 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9178 if (VECTOR_MODE_P (result_mode
))
9179 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9181 count
= bitsize
- count
;
9184 /* We need to determine what mode we will do the shift in. If the
9185 shift is a right shift or a ROTATE, we must always do it in the mode
9186 it was originally done in. Otherwise, we can do it in MODE, the
9187 widest mode encountered. */
9189 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9190 ? result_mode
: mode
);
9192 /* Handle cases where the count is greater than the size of the mode
9193 minus 1. For ASHIFT, use the size minus one as the count (this can
9194 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9195 take the count modulo the size. For other shifts, the result is
9198 Since these shifts are being produced by the compiler by combining
9199 multiple operations, each of which are defined, we know what the
9200 result is supposed to be. */
9202 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9204 if (code
== ASHIFTRT
)
9205 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9206 else if (code
== ROTATE
|| code
== ROTATERT
)
9207 count
%= GET_MODE_BITSIZE (shift_mode
);
9210 /* We can't simply return zero because there may be an
9218 /* An arithmetic right shift of a quantity known to be -1 or 0
9220 if (code
== ASHIFTRT
9221 && (num_sign_bit_copies (varop
, shift_mode
)
9222 == GET_MODE_BITSIZE (shift_mode
)))
9228 /* If we are doing an arithmetic right shift and discarding all but
9229 the sign bit copies, this is equivalent to doing a shift by the
9230 bitsize minus one. Convert it into that shift because it will often
9231 allow other simplifications. */
9233 if (code
== ASHIFTRT
9234 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9235 >= GET_MODE_BITSIZE (shift_mode
)))
9236 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9238 /* We simplify the tests below and elsewhere by converting
9239 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9240 `make_compound_operation' will convert it to an ASHIFTRT for
9241 those machines (such as VAX) that don't have an LSHIFTRT. */
9242 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9244 && ((nonzero_bits (varop
, shift_mode
)
9245 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9249 if (code
== LSHIFTRT
9250 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9251 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9254 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9255 && !((nonzero_bits (varop
, shift_mode
) << count
)
9256 & GET_MODE_MASK (shift_mode
)))
9259 switch (GET_CODE (varop
))
9265 new = expand_compound_operation (varop
);
9274 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9275 minus the width of a smaller mode, we can do this with a
9276 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9277 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9278 && ! mode_dependent_address_p (XEXP (varop
, 0))
9279 && ! MEM_VOLATILE_P (varop
)
9280 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9281 MODE_INT
, 1)) != BLKmode
)
9283 new = adjust_address_nv (varop
, tmode
,
9284 BYTES_BIG_ENDIAN
? 0
9285 : count
/ BITS_PER_UNIT
);
9287 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9288 : ZERO_EXTEND
, mode
, new);
9295 /* Similar to the case above, except that we can only do this if
9296 the resulting mode is the same as that of the underlying
9297 MEM and adjust the address depending on the *bits* endianness
9298 because of the way that bit-field extract insns are defined. */
9299 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9300 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9301 MODE_INT
, 1)) != BLKmode
9302 && tmode
== GET_MODE (XEXP (varop
, 0)))
9304 if (BITS_BIG_ENDIAN
)
9305 new = XEXP (varop
, 0);
9308 new = copy_rtx (XEXP (varop
, 0));
9309 SUBST (XEXP (new, 0),
9310 plus_constant (XEXP (new, 0),
9311 count
/ BITS_PER_UNIT
));
9314 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9315 : ZERO_EXTEND
, mode
, new);
9322 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9323 the same number of words as what we've seen so far. Then store
9324 the widest mode in MODE. */
9325 if (subreg_lowpart_p (varop
)
9326 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9327 > GET_MODE_SIZE (GET_MODE (varop
)))
9328 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9329 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9332 varop
= SUBREG_REG (varop
);
9333 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9334 mode
= GET_MODE (varop
);
9340 /* Some machines use MULT instead of ASHIFT because MULT
9341 is cheaper. But it is still better on those machines to
9342 merge two shifts into one. */
9343 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9344 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9347 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9348 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9354 /* Similar, for when divides are cheaper. */
9355 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9356 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9359 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9360 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9366 /* If we are extracting just the sign bit of an arithmetic
9367 right shift, that shift is not needed. However, the sign
9368 bit of a wider mode may be different from what would be
9369 interpreted as the sign bit in a narrower mode, so, if
9370 the result is narrower, don't discard the shift. */
9371 if (code
== LSHIFTRT
9372 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9373 && (GET_MODE_BITSIZE (result_mode
)
9374 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9376 varop
= XEXP (varop
, 0);
9380 /* ... fall through ... */
9385 /* Here we have two nested shifts. The result is usually the
9386 AND of a new shift with a mask. We compute the result below. */
9387 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9388 && INTVAL (XEXP (varop
, 1)) >= 0
9389 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9390 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9391 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9393 enum rtx_code first_code
= GET_CODE (varop
);
9394 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9395 unsigned HOST_WIDE_INT mask
;
9398 /* We have one common special case. We can't do any merging if
9399 the inner code is an ASHIFTRT of a smaller mode. However, if
9400 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9401 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9402 we can convert it to
9403 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9404 This simplifies certain SIGN_EXTEND operations. */
9405 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9406 && count
== (unsigned int)
9407 (GET_MODE_BITSIZE (result_mode
)
9408 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9410 /* C3 has the low-order C1 bits zero. */
9412 mask
= (GET_MODE_MASK (mode
)
9413 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9415 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9416 XEXP (varop
, 0), mask
);
9417 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9419 count
= first_count
;
9424 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9425 than C1 high-order bits equal to the sign bit, we can convert
9426 this to either an ASHIFT or an ASHIFTRT depending on the
9429 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9431 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9432 && GET_MODE (varop
) == shift_mode
9433 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9436 varop
= XEXP (varop
, 0);
9438 signed_count
= count
- first_count
;
9439 if (signed_count
< 0)
9440 count
= -signed_count
, code
= ASHIFT
;
9442 count
= signed_count
;
9447 /* There are some cases we can't do. If CODE is ASHIFTRT,
9448 we can only do this if FIRST_CODE is also ASHIFTRT.
9450 We can't do the case when CODE is ROTATE and FIRST_CODE is
9453 If the mode of this shift is not the mode of the outer shift,
9454 we can't do this if either shift is a right shift or ROTATE.
9456 Finally, we can't do any of these if the mode is too wide
9457 unless the codes are the same.
9459 Handle the case where the shift codes are the same
9462 if (code
== first_code
)
9464 if (GET_MODE (varop
) != result_mode
9465 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9469 count
+= first_count
;
9470 varop
= XEXP (varop
, 0);
9474 if (code
== ASHIFTRT
9475 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9476 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9477 || (GET_MODE (varop
) != result_mode
9478 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9479 || first_code
== ROTATE
9480 || code
== ROTATE
)))
9483 /* To compute the mask to apply after the shift, shift the
9484 nonzero bits of the inner shift the same way the
9485 outer shift will. */
9487 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9490 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9493 /* Give up if we can't compute an outer operation to use. */
9495 || GET_CODE (mask_rtx
) != CONST_INT
9496 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9498 result_mode
, &complement_p
))
9501 /* If the shifts are in the same direction, we add the
9502 counts. Otherwise, we subtract them. */
9503 signed_count
= count
;
9504 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9505 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9506 signed_count
+= first_count
;
9508 signed_count
-= first_count
;
9510 /* If COUNT is positive, the new shift is usually CODE,
9511 except for the two exceptions below, in which case it is
9512 FIRST_CODE. If the count is negative, FIRST_CODE should
9514 if (signed_count
> 0
9515 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9516 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9517 code
= first_code
, count
= signed_count
;
9518 else if (signed_count
< 0)
9519 code
= first_code
, count
= -signed_count
;
9521 count
= signed_count
;
9523 varop
= XEXP (varop
, 0);
9527 /* If we have (A << B << C) for any shift, we can convert this to
9528 (A << C << B). This wins if A is a constant. Only try this if
9529 B is not a constant. */
9531 else if (GET_CODE (varop
) == code
9532 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9534 = simplify_binary_operation (code
, mode
,
9538 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9545 /* Make this fit the case below. */
9546 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9547 GEN_INT (GET_MODE_MASK (mode
)));
9553 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9554 with C the size of VAROP - 1 and the shift is logical if
9555 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9556 we have an (le X 0) operation. If we have an arithmetic shift
9557 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9558 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9560 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9561 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9562 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9563 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9564 && count
== (unsigned int)
9565 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9566 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9569 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9572 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9573 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9578 /* If we have (shift (logical)), move the logical to the outside
9579 to allow it to possibly combine with another logical and the
9580 shift to combine with another shift. This also canonicalizes to
9581 what a ZERO_EXTRACT looks like. Also, some machines have
9582 (and (shift)) insns. */
9584 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9585 /* We can't do this if we have (ashiftrt (xor)) and the
9586 constant has its sign bit set in shift_mode. */
9587 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9588 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9590 && (new = simplify_binary_operation (code
, result_mode
,
9592 GEN_INT (count
))) != 0
9593 && GET_CODE (new) == CONST_INT
9594 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9595 INTVAL (new), result_mode
, &complement_p
))
9597 varop
= XEXP (varop
, 0);
9601 /* If we can't do that, try to simplify the shift in each arm of the
9602 logical expression, make a new logical expression, and apply
9603 the inverse distributive law. This also can't be done
9604 for some (ashiftrt (xor)). */
9605 if (code
!= ASHIFTRT
|| GET_CODE (varop
)!= XOR
9606 || 0 <= trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9609 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9610 XEXP (varop
, 0), count
);
9611 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9612 XEXP (varop
, 1), count
);
9614 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9615 varop
= apply_distributive_law (varop
);
9622 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9623 says that the sign bit can be tested, FOO has mode MODE, C is
9624 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9625 that may be nonzero. */
9626 if (code
== LSHIFTRT
9627 && XEXP (varop
, 1) == const0_rtx
9628 && GET_MODE (XEXP (varop
, 0)) == result_mode
9629 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9630 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9631 && ((STORE_FLAG_VALUE
9632 & ((HOST_WIDE_INT
) 1
9633 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9634 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9635 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9636 (HOST_WIDE_INT
) 1, result_mode
,
9639 varop
= XEXP (varop
, 0);
9646 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9647 than the number of bits in the mode is equivalent to A. */
9648 if (code
== LSHIFTRT
9649 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9650 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9652 varop
= XEXP (varop
, 0);
9657 /* NEG commutes with ASHIFT since it is multiplication. Move the
9658 NEG outside to allow shifts to combine. */
9660 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9661 (HOST_WIDE_INT
) 0, result_mode
,
9664 varop
= XEXP (varop
, 0);
9670 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9671 is one less than the number of bits in the mode is
9672 equivalent to (xor A 1). */
9673 if (code
== LSHIFTRT
9674 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9675 && XEXP (varop
, 1) == constm1_rtx
9676 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9677 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9678 (HOST_WIDE_INT
) 1, result_mode
,
9682 varop
= XEXP (varop
, 0);
9686 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9687 that might be nonzero in BAR are those being shifted out and those
9688 bits are known zero in FOO, we can replace the PLUS with FOO.
9689 Similarly in the other operand order. This code occurs when
9690 we are computing the size of a variable-size array. */
9692 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9693 && count
< HOST_BITS_PER_WIDE_INT
9694 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9695 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9696 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9698 varop
= XEXP (varop
, 0);
9701 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9702 && count
< HOST_BITS_PER_WIDE_INT
9703 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9704 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9706 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9707 & nonzero_bits (XEXP (varop
, 1),
9710 varop
= XEXP (varop
, 1);
9714 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9716 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9717 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9719 GEN_INT (count
))) != 0
9720 && GET_CODE (new) == CONST_INT
9721 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9722 INTVAL (new), result_mode
, &complement_p
))
9724 varop
= XEXP (varop
, 0);
9730 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9731 with C the size of VAROP - 1 and the shift is logical if
9732 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9733 we have a (gt X 0) operation. If the shift is arithmetic with
9734 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9735 we have a (neg (gt X 0)) operation. */
9737 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9738 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9739 && count
== (unsigned int)
9740 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9741 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9742 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9743 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9745 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9748 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9751 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9752 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9759 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9760 if the truncate does not affect the value. */
9761 if (code
== LSHIFTRT
9762 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9763 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9764 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9765 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9766 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9768 rtx varop_inner
= XEXP (varop
, 0);
9771 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9772 XEXP (varop_inner
, 0),
9774 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9775 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9788 /* We need to determine what mode to do the shift in. If the shift is
9789 a right shift or ROTATE, we must always do it in the mode it was
9790 originally done in. Otherwise, we can do it in MODE, the widest mode
9791 encountered. The code we care about is that of the shift that will
9792 actually be done, not the shift that was originally requested. */
9794 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9795 ? result_mode
: mode
);
9797 /* We have now finished analyzing the shift. The result should be
9798 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9799 OUTER_OP is non-NIL, it is an operation that needs to be applied
9800 to the result of the shift. OUTER_CONST is the relevant constant,
9801 but we must turn off all bits turned off in the shift.
9803 If we were passed a value for X, see if we can use any pieces of
9804 it. If not, make new rtx. */
9806 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9807 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9808 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9809 const_rtx
= XEXP (x
, 1);
9811 const_rtx
= GEN_INT (count
);
9813 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9814 && GET_MODE (XEXP (x
, 0)) == shift_mode
9815 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9816 varop
= XEXP (x
, 0);
9817 else if (GET_MODE (varop
) != shift_mode
)
9818 varop
= gen_lowpart (shift_mode
, varop
);
9820 /* If we can't make the SUBREG, try to return what we were given. */
9821 if (GET_CODE (varop
) == CLOBBER
)
9822 return x
? x
: varop
;
9824 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9828 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9830 /* If we have an outer operation and we just made a shift, it is
9831 possible that we could have simplified the shift were it not
9832 for the outer operation. So try to do the simplification
9835 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9836 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9837 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9838 INTVAL (XEXP (x
, 1)));
9840 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9841 turn off all the bits that the shift would have turned off. */
9842 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9843 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9844 GET_MODE_MASK (result_mode
) >> orig_count
);
9846 /* Do the remainder of the processing in RESULT_MODE. */
9847 x
= gen_lowpart (result_mode
, x
);
9849 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9852 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9854 if (outer_op
!= NIL
)
9856 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9857 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9859 if (outer_op
== AND
)
9860 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9861 else if (outer_op
== SET
)
9862 /* This means that we have determined that the result is
9863 equivalent to a constant. This should be rare. */
9864 x
= GEN_INT (outer_const
);
9865 else if (GET_RTX_CLASS (outer_op
) == '1')
9866 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9868 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9874 /* Like recog, but we receive the address of a pointer to a new pattern.
9875 We try to match the rtx that the pointer points to.
9876 If that fails, we may try to modify or replace the pattern,
9877 storing the replacement into the same pointer object.
9879 Modifications include deletion or addition of CLOBBERs.
9881 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9882 the CLOBBERs are placed.
9884 The value is the final insn code from the pattern ultimately matched,
9888 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9891 int insn_code_number
;
9892 int num_clobbers_to_add
= 0;
9895 rtx old_notes
, old_pat
;
9897 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9898 we use to indicate that something didn't match. If we find such a
9899 thing, force rejection. */
9900 if (GET_CODE (pat
) == PARALLEL
)
9901 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9902 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9903 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9906 old_pat
= PATTERN (insn
);
9907 old_notes
= REG_NOTES (insn
);
9908 PATTERN (insn
) = pat
;
9909 REG_NOTES (insn
) = 0;
9911 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9913 /* If it isn't, there is the possibility that we previously had an insn
9914 that clobbered some register as a side effect, but the combined
9915 insn doesn't need to do that. So try once more without the clobbers
9916 unless this represents an ASM insn. */
9918 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9919 && GET_CODE (pat
) == PARALLEL
)
9923 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9924 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9927 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9931 SUBST_INT (XVECLEN (pat
, 0), pos
);
9934 pat
= XVECEXP (pat
, 0, 0);
9936 PATTERN (insn
) = pat
;
9937 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9939 PATTERN (insn
) = old_pat
;
9940 REG_NOTES (insn
) = old_notes
;
9942 /* Recognize all noop sets, these will be killed by followup pass. */
9943 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9944 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9946 /* If we had any clobbers to add, make a new pattern than contains
9947 them. Then check to make sure that all of them are dead. */
9948 if (num_clobbers_to_add
)
9950 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9951 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9953 + num_clobbers_to_add
)
9954 : num_clobbers_to_add
+ 1));
9956 if (GET_CODE (pat
) == PARALLEL
)
9957 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9958 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9960 XVECEXP (newpat
, 0, 0) = pat
;
9962 add_clobbers (newpat
, insn_code_number
);
9964 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9965 i
< XVECLEN (newpat
, 0); i
++)
9967 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9968 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9970 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9971 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9979 return insn_code_number
;
9982 /* Like gen_lowpart_general but for use by combine. In combine it
9983 is not possible to create any new pseudoregs. However, it is
9984 safe to create invalid memory addresses, because combine will
9985 try to recognize them and all they will do is make the combine
9988 If for some reason this cannot do its job, an rtx
9989 (clobber (const_int 0)) is returned.
9990 An insn containing that will not be recognized. */
9993 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
9997 if (GET_MODE (x
) == mode
)
10000 /* Return identity if this is a CONST or symbolic
10003 && (GET_CODE (x
) == CONST
10004 || GET_CODE (x
) == SYMBOL_REF
10005 || GET_CODE (x
) == LABEL_REF
))
10008 /* We can only support MODE being wider than a word if X is a
10009 constant integer or has a mode the same size. */
10011 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
10012 && ! ((GET_MODE (x
) == VOIDmode
10013 && (GET_CODE (x
) == CONST_INT
10014 || GET_CODE (x
) == CONST_DOUBLE
))
10015 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
10016 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10018 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10019 won't know what to do. So we will strip off the SUBREG here and
10020 process normally. */
10021 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
10023 x
= SUBREG_REG (x
);
10024 if (GET_MODE (x
) == mode
)
10028 result
= gen_lowpart_common (mode
, x
);
10029 #ifdef CANNOT_CHANGE_MODE_CLASS
10031 && GET_CODE (result
) == SUBREG
10032 && GET_CODE (SUBREG_REG (result
)) == REG
10033 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10034 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10036 + GET_MODE (result
));
10042 if (GET_CODE (x
) == MEM
)
10046 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10048 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10049 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10051 /* If we want to refer to something bigger than the original memref,
10052 generate a perverse subreg instead. That will force a reload
10053 of the original memref X. */
10054 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10055 return gen_rtx_SUBREG (mode
, x
, 0);
10057 if (WORDS_BIG_ENDIAN
)
10058 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10059 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10061 if (BYTES_BIG_ENDIAN
)
10063 /* Adjust the address so that the address-after-the-data is
10065 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10066 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10069 return adjust_address_nv (x
, mode
, offset
);
10072 /* If X is a comparison operator, rewrite it in a new mode. This
10073 probably won't match, but may allow further simplifications. */
10074 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10075 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10077 /* If we couldn't simplify X any other way, just enclose it in a
10078 SUBREG. Normally, this SUBREG won't match, but some patterns may
10079 include an explicit SUBREG or we may simplify it further in combine. */
10084 enum machine_mode sub_mode
= GET_MODE (x
);
10086 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10087 if (sub_mode
== VOIDmode
)
10089 sub_mode
= int_mode_for_mode (mode
);
10090 x
= gen_lowpart_common (sub_mode
, x
);
10092 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10094 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10097 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10101 /* These routines make binary and unary operations by first seeing if they
10102 fold; if not, a new expression is allocated. */
10105 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10110 if (GET_CODE (op0
) == CLOBBER
)
10112 else if (GET_CODE (op1
) == CLOBBER
)
10115 if (GET_RTX_CLASS (code
) == 'c'
10116 && swap_commutative_operands_p (op0
, op1
))
10117 tem
= op0
, op0
= op1
, op1
= tem
;
10119 if (GET_RTX_CLASS (code
) == '<')
10121 enum machine_mode op_mode
= GET_MODE (op0
);
10123 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10124 just (REL_OP X Y). */
10125 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10127 op1
= XEXP (op0
, 1);
10128 op0
= XEXP (op0
, 0);
10129 op_mode
= GET_MODE (op0
);
10132 if (op_mode
== VOIDmode
)
10133 op_mode
= GET_MODE (op1
);
10134 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10137 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10142 /* Put complex operands first and constants second. */
10143 if (GET_RTX_CLASS (code
) == 'c'
10144 && swap_commutative_operands_p (op0
, op1
))
10145 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10147 /* If we are turning off bits already known off in OP0, we need not do
10149 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10150 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10151 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10154 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10157 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10158 comparison code that will be tested.
10160 The result is a possibly different comparison code to use. *POP0 and
10161 *POP1 may be updated.
10163 It is possible that we might detect that a comparison is either always
10164 true or always false. However, we do not perform general constant
10165 folding in combine, so this knowledge isn't useful. Such tautologies
10166 should have been detected earlier. Hence we ignore all such cases. */
10168 static enum rtx_code
10169 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10175 enum machine_mode mode
, tmode
;
10177 /* Try a few ways of applying the same transformation to both operands. */
10180 #ifndef WORD_REGISTER_OPERATIONS
10181 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10182 so check specially. */
10183 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10184 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10185 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10186 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10187 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10188 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10189 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10190 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10191 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10192 && XEXP (op0
, 1) == XEXP (op1
, 1)
10193 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10194 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10195 && (INTVAL (XEXP (op0
, 1))
10196 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10197 - (GET_MODE_BITSIZE
10198 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10200 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10201 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10205 /* If both operands are the same constant shift, see if we can ignore the
10206 shift. We can if the shift is a rotate or if the bits shifted out of
10207 this shift are known to be zero for both inputs and if the type of
10208 comparison is compatible with the shift. */
10209 if (GET_CODE (op0
) == GET_CODE (op1
)
10210 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10211 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10212 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10213 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10214 || (GET_CODE (op0
) == ASHIFTRT
10215 && (code
!= GTU
&& code
!= LTU
10216 && code
!= GEU
&& code
!= LEU
)))
10217 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10218 && INTVAL (XEXP (op0
, 1)) >= 0
10219 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10220 && XEXP (op0
, 1) == XEXP (op1
, 1))
10222 enum machine_mode mode
= GET_MODE (op0
);
10223 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10224 int shift_count
= INTVAL (XEXP (op0
, 1));
10226 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10227 mask
&= (mask
>> shift_count
) << shift_count
;
10228 else if (GET_CODE (op0
) == ASHIFT
)
10229 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10231 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10232 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10233 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10238 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10239 SUBREGs are of the same mode, and, in both cases, the AND would
10240 be redundant if the comparison was done in the narrower mode,
10241 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10242 and the operand's possibly nonzero bits are 0xffffff01; in that case
10243 if we only care about QImode, we don't need the AND). This case
10244 occurs if the output mode of an scc insn is not SImode and
10245 STORE_FLAG_VALUE == 1 (e.g., the 386).
10247 Similarly, check for a case where the AND's are ZERO_EXTEND
10248 operations from some narrower mode even though a SUBREG is not
10251 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10252 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10253 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10255 rtx inner_op0
= XEXP (op0
, 0);
10256 rtx inner_op1
= XEXP (op1
, 0);
10257 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10258 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10261 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10262 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10263 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10264 && (GET_MODE (SUBREG_REG (inner_op0
))
10265 == GET_MODE (SUBREG_REG (inner_op1
)))
10266 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10267 <= HOST_BITS_PER_WIDE_INT
)
10268 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10269 GET_MODE (SUBREG_REG (inner_op0
)))))
10270 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10271 GET_MODE (SUBREG_REG (inner_op1
))))))
10273 op0
= SUBREG_REG (inner_op0
);
10274 op1
= SUBREG_REG (inner_op1
);
10276 /* The resulting comparison is always unsigned since we masked
10277 off the original sign bit. */
10278 code
= unsigned_condition (code
);
10284 for (tmode
= GET_CLASS_NARROWEST_MODE
10285 (GET_MODE_CLASS (GET_MODE (op0
)));
10286 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10287 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10289 op0
= gen_lowpart (tmode
, inner_op0
);
10290 op1
= gen_lowpart (tmode
, inner_op1
);
10291 code
= unsigned_condition (code
);
10300 /* If both operands are NOT, we can strip off the outer operation
10301 and adjust the comparison code for swapped operands; similarly for
10302 NEG, except that this must be an equality comparison. */
10303 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10304 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10305 && (code
== EQ
|| code
== NE
)))
10306 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10312 /* If the first operand is a constant, swap the operands and adjust the
10313 comparison code appropriately, but don't do this if the second operand
10314 is already a constant integer. */
10315 if (swap_commutative_operands_p (op0
, op1
))
10317 tem
= op0
, op0
= op1
, op1
= tem
;
10318 code
= swap_condition (code
);
10321 /* We now enter a loop during which we will try to simplify the comparison.
10322 For the most part, we only are concerned with comparisons with zero,
10323 but some things may really be comparisons with zero but not start
10324 out looking that way. */
10326 while (GET_CODE (op1
) == CONST_INT
)
10328 enum machine_mode mode
= GET_MODE (op0
);
10329 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10330 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10331 int equality_comparison_p
;
10332 int sign_bit_comparison_p
;
10333 int unsigned_comparison_p
;
10334 HOST_WIDE_INT const_op
;
10336 /* We only want to handle integral modes. This catches VOIDmode,
10337 CCmode, and the floating-point modes. An exception is that we
10338 can handle VOIDmode if OP0 is a COMPARE or a comparison
10341 if (GET_MODE_CLASS (mode
) != MODE_INT
10342 && ! (mode
== VOIDmode
10343 && (GET_CODE (op0
) == COMPARE
10344 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10347 /* Get the constant we are comparing against and turn off all bits
10348 not on in our mode. */
10349 const_op
= INTVAL (op1
);
10350 if (mode
!= VOIDmode
)
10351 const_op
= trunc_int_for_mode (const_op
, mode
);
10352 op1
= GEN_INT (const_op
);
10354 /* If we are comparing against a constant power of two and the value
10355 being compared can only have that single bit nonzero (e.g., it was
10356 `and'ed with that bit), we can replace this with a comparison
10359 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10360 || code
== LT
|| code
== LTU
)
10361 && mode_width
<= HOST_BITS_PER_WIDE_INT
10362 && exact_log2 (const_op
) >= 0
10363 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10365 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10366 op1
= const0_rtx
, const_op
= 0;
10369 /* Similarly, if we are comparing a value known to be either -1 or
10370 0 with -1, change it to the opposite comparison against zero. */
10373 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10374 || code
== GEU
|| code
== LTU
)
10375 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10377 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10378 op1
= const0_rtx
, const_op
= 0;
10381 /* Do some canonicalizations based on the comparison code. We prefer
10382 comparisons against zero and then prefer equality comparisons.
10383 If we can reduce the size of a constant, we will do that too. */
10388 /* < C is equivalent to <= (C - 1) */
10392 op1
= GEN_INT (const_op
);
10394 /* ... fall through to LE case below. */
10400 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10404 op1
= GEN_INT (const_op
);
10408 /* If we are doing a <= 0 comparison on a value known to have
10409 a zero sign bit, we can replace this with == 0. */
10410 else if (const_op
== 0
10411 && mode_width
<= HOST_BITS_PER_WIDE_INT
10412 && (nonzero_bits (op0
, mode
)
10413 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10418 /* >= C is equivalent to > (C - 1). */
10422 op1
= GEN_INT (const_op
);
10424 /* ... fall through to GT below. */
10430 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10434 op1
= GEN_INT (const_op
);
10438 /* If we are doing a > 0 comparison on a value known to have
10439 a zero sign bit, we can replace this with != 0. */
10440 else if (const_op
== 0
10441 && mode_width
<= HOST_BITS_PER_WIDE_INT
10442 && (nonzero_bits (op0
, mode
)
10443 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10448 /* < C is equivalent to <= (C - 1). */
10452 op1
= GEN_INT (const_op
);
10454 /* ... fall through ... */
10457 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10458 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10459 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10461 const_op
= 0, op1
= const0_rtx
;
10469 /* unsigned <= 0 is equivalent to == 0 */
10473 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10474 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10475 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10477 const_op
= 0, op1
= const0_rtx
;
10483 /* >= C is equivalent to < (C - 1). */
10487 op1
= GEN_INT (const_op
);
10489 /* ... fall through ... */
10492 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10493 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10494 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10496 const_op
= 0, op1
= const0_rtx
;
10504 /* unsigned > 0 is equivalent to != 0 */
10508 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10509 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10510 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10512 const_op
= 0, op1
= const0_rtx
;
10521 /* Compute some predicates to simplify code below. */
10523 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10524 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10525 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10528 /* If this is a sign bit comparison and we can do arithmetic in
10529 MODE, say that we will only be needing the sign bit of OP0. */
10530 if (sign_bit_comparison_p
10531 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10532 op0
= force_to_mode (op0
, mode
,
10534 << (GET_MODE_BITSIZE (mode
) - 1)),
10537 /* Now try cases based on the opcode of OP0. If none of the cases
10538 does a "continue", we exit this loop immediately after the
10541 switch (GET_CODE (op0
))
10544 /* If we are extracting a single bit from a variable position in
10545 a constant that has only a single bit set and are comparing it
10546 with zero, we can convert this into an equality comparison
10547 between the position and the location of the single bit. */
10548 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10549 have already reduced the shift count modulo the word size. */
10550 if (!SHIFT_COUNT_TRUNCATED
10551 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10552 && XEXP (op0
, 1) == const1_rtx
10553 && equality_comparison_p
&& const_op
== 0
10554 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10556 if (BITS_BIG_ENDIAN
)
10558 enum machine_mode new_mode
10559 = mode_for_extraction (EP_extzv
, 1);
10560 if (new_mode
== MAX_MACHINE_MODE
)
10561 i
= BITS_PER_WORD
- 1 - i
;
10565 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10569 op0
= XEXP (op0
, 2);
10573 /* Result is nonzero iff shift count is equal to I. */
10574 code
= reverse_condition (code
);
10578 /* ... fall through ... */
10581 tem
= expand_compound_operation (op0
);
10590 /* If testing for equality, we can take the NOT of the constant. */
10591 if (equality_comparison_p
10592 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10594 op0
= XEXP (op0
, 0);
10599 /* If just looking at the sign bit, reverse the sense of the
10601 if (sign_bit_comparison_p
)
10603 op0
= XEXP (op0
, 0);
10604 code
= (code
== GE
? LT
: GE
);
10610 /* If testing for equality, we can take the NEG of the constant. */
10611 if (equality_comparison_p
10612 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10614 op0
= XEXP (op0
, 0);
10619 /* The remaining cases only apply to comparisons with zero. */
10623 /* When X is ABS or is known positive,
10624 (neg X) is < 0 if and only if X != 0. */
10626 if (sign_bit_comparison_p
10627 && (GET_CODE (XEXP (op0
, 0)) == ABS
10628 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10629 && (nonzero_bits (XEXP (op0
, 0), mode
)
10630 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10632 op0
= XEXP (op0
, 0);
10633 code
= (code
== LT
? NE
: EQ
);
10637 /* If we have NEG of something whose two high-order bits are the
10638 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10639 if (num_sign_bit_copies (op0
, mode
) >= 2)
10641 op0
= XEXP (op0
, 0);
10642 code
= swap_condition (code
);
10648 /* If we are testing equality and our count is a constant, we
10649 can perform the inverse operation on our RHS. */
10650 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10651 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10652 op1
, XEXP (op0
, 1))) != 0)
10654 op0
= XEXP (op0
, 0);
10659 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10660 a particular bit. Convert it to an AND of a constant of that
10661 bit. This will be converted into a ZERO_EXTRACT. */
10662 if (const_op
== 0 && sign_bit_comparison_p
10663 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10664 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10666 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10669 - INTVAL (XEXP (op0
, 1)))));
10670 code
= (code
== LT
? NE
: EQ
);
10674 /* Fall through. */
10677 /* ABS is ignorable inside an equality comparison with zero. */
10678 if (const_op
== 0 && equality_comparison_p
)
10680 op0
= XEXP (op0
, 0);
10686 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10687 to (compare FOO CONST) if CONST fits in FOO's mode and we
10688 are either testing inequality or have an unsigned comparison
10689 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10690 if (! unsigned_comparison_p
10691 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10692 <= HOST_BITS_PER_WIDE_INT
)
10693 && ((unsigned HOST_WIDE_INT
) const_op
10694 < (((unsigned HOST_WIDE_INT
) 1
10695 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10697 op0
= XEXP (op0
, 0);
10703 /* Check for the case where we are comparing A - C1 with C2,
10704 both constants are smaller than 1/2 the maximum positive
10705 value in MODE, and the comparison is equality or unsigned.
10706 In that case, if A is either zero-extended to MODE or has
10707 sufficient sign bits so that the high-order bit in MODE
10708 is a copy of the sign in the inner mode, we can prove that it is
10709 safe to do the operation in the wider mode. This simplifies
10710 many range checks. */
10712 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10713 && subreg_lowpart_p (op0
)
10714 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10715 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10716 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10717 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10718 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10719 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10720 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10721 GET_MODE (SUBREG_REG (op0
)))
10722 & ~GET_MODE_MASK (mode
))
10723 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10724 GET_MODE (SUBREG_REG (op0
)))
10726 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10727 - GET_MODE_BITSIZE (mode
)))))
10729 op0
= SUBREG_REG (op0
);
10733 /* If the inner mode is narrower and we are extracting the low part,
10734 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10735 if (subreg_lowpart_p (op0
)
10736 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10737 /* Fall through */ ;
10741 /* ... fall through ... */
10744 if ((unsigned_comparison_p
|| equality_comparison_p
)
10745 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10746 <= HOST_BITS_PER_WIDE_INT
)
10747 && ((unsigned HOST_WIDE_INT
) const_op
10748 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10750 op0
= XEXP (op0
, 0);
10756 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10757 this for equality comparisons due to pathological cases involving
10759 if (equality_comparison_p
10760 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10761 op1
, XEXP (op0
, 1))))
10763 op0
= XEXP (op0
, 0);
10768 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10769 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10770 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10772 op0
= XEXP (XEXP (op0
, 0), 0);
10773 code
= (code
== LT
? EQ
: NE
);
10779 /* We used to optimize signed comparisons against zero, but that
10780 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10781 arrive here as equality comparisons, or (GEU, LTU) are
10782 optimized away. No need to special-case them. */
10784 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10785 (eq B (minus A C)), whichever simplifies. We can only do
10786 this for equality comparisons due to pathological cases involving
10788 if (equality_comparison_p
10789 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10790 XEXP (op0
, 1), op1
)))
10792 op0
= XEXP (op0
, 0);
10797 if (equality_comparison_p
10798 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10799 XEXP (op0
, 0), op1
)))
10801 op0
= XEXP (op0
, 1);
10806 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10807 of bits in X minus 1, is one iff X > 0. */
10808 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10809 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10810 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10812 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10814 op0
= XEXP (op0
, 1);
10815 code
= (code
== GE
? LE
: GT
);
10821 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10822 if C is zero or B is a constant. */
10823 if (equality_comparison_p
10824 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10825 XEXP (op0
, 1), op1
)))
10827 op0
= XEXP (op0
, 0);
10834 case UNEQ
: case LTGT
:
10835 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10836 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10837 case UNORDERED
: case ORDERED
:
10838 /* We can't do anything if OP0 is a condition code value, rather
10839 than an actual data value. */
10841 || CC0_P (XEXP (op0
, 0))
10842 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10845 /* Get the two operands being compared. */
10846 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10847 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10849 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10851 /* Check for the cases where we simply want the result of the
10852 earlier test or the opposite of that result. */
10853 if (code
== NE
|| code
== EQ
10854 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10855 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10856 && (STORE_FLAG_VALUE
10857 & (((HOST_WIDE_INT
) 1
10858 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10859 && (code
== LT
|| code
== GE
)))
10861 enum rtx_code new_code
;
10862 if (code
== LT
|| code
== NE
)
10863 new_code
= GET_CODE (op0
);
10865 new_code
= combine_reversed_comparison_code (op0
);
10867 if (new_code
!= UNKNOWN
)
10878 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10880 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10881 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10882 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10884 op0
= XEXP (op0
, 1);
10885 code
= (code
== GE
? GT
: LE
);
10891 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10892 will be converted to a ZERO_EXTRACT later. */
10893 if (const_op
== 0 && equality_comparison_p
10894 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10895 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10897 op0
= simplify_and_const_int
10898 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10900 XEXP (XEXP (op0
, 0), 1)),
10901 (HOST_WIDE_INT
) 1);
10905 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10906 zero and X is a comparison and C1 and C2 describe only bits set
10907 in STORE_FLAG_VALUE, we can compare with X. */
10908 if (const_op
== 0 && equality_comparison_p
10909 && mode_width
<= HOST_BITS_PER_WIDE_INT
10910 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10911 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10912 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10913 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10914 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10916 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10917 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10918 if ((~STORE_FLAG_VALUE
& mask
) == 0
10919 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10920 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10921 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10923 op0
= XEXP (XEXP (op0
, 0), 0);
10928 /* If we are doing an equality comparison of an AND of a bit equal
10929 to the sign bit, replace this with a LT or GE comparison of
10930 the underlying value. */
10931 if (equality_comparison_p
10933 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10934 && mode_width
<= HOST_BITS_PER_WIDE_INT
10935 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10936 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10938 op0
= XEXP (op0
, 0);
10939 code
= (code
== EQ
? GE
: LT
);
10943 /* If this AND operation is really a ZERO_EXTEND from a narrower
10944 mode, the constant fits within that mode, and this is either an
10945 equality or unsigned comparison, try to do this comparison in
10946 the narrower mode. */
10947 if ((equality_comparison_p
|| unsigned_comparison_p
)
10948 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10949 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10950 & GET_MODE_MASK (mode
))
10952 && const_op
>> i
== 0
10953 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10955 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10959 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10960 fits in both M1 and M2 and the SUBREG is either paradoxical
10961 or represents the low part, permute the SUBREG and the AND
10963 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10965 unsigned HOST_WIDE_INT c1
;
10966 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10967 /* Require an integral mode, to avoid creating something like
10969 if (SCALAR_INT_MODE_P (tmode
)
10970 /* It is unsafe to commute the AND into the SUBREG if the
10971 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10972 not defined. As originally written the upper bits
10973 have a defined value due to the AND operation.
10974 However, if we commute the AND inside the SUBREG then
10975 they no longer have defined values and the meaning of
10976 the code has been changed. */
10978 #ifdef WORD_REGISTER_OPERATIONS
10979 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10980 && mode_width
<= BITS_PER_WORD
)
10982 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10983 && subreg_lowpart_p (XEXP (op0
, 0))))
10984 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10985 && mode_width
<= HOST_BITS_PER_WIDE_INT
10986 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10987 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10988 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10990 && c1
!= GET_MODE_MASK (tmode
))
10992 op0
= gen_binary (AND
, tmode
,
10993 SUBREG_REG (XEXP (op0
, 0)),
10994 gen_int_mode (c1
, tmode
));
10995 op0
= gen_lowpart (mode
, op0
);
11000 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11001 if (const_op
== 0 && equality_comparison_p
11002 && XEXP (op0
, 1) == const1_rtx
11003 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11005 op0
= simplify_and_const_int
11006 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
11007 code
= (code
== NE
? EQ
: NE
);
11011 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11012 (eq (and (lshiftrt X) 1) 0).
11013 Also handle the case where (not X) is expressed using xor. */
11014 if (const_op
== 0 && equality_comparison_p
11015 && XEXP (op0
, 1) == const1_rtx
11016 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11018 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11019 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11021 if (GET_CODE (shift_op
) == NOT
11022 || (GET_CODE (shift_op
) == XOR
11023 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
11024 && GET_CODE (shift_count
) == CONST_INT
11025 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11026 && (INTVAL (XEXP (shift_op
, 1))
11027 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11029 op0
= simplify_and_const_int
11031 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11032 (HOST_WIDE_INT
) 1);
11033 code
= (code
== NE
? EQ
: NE
);
11040 /* If we have (compare (ashift FOO N) (const_int C)) and
11041 the high order N bits of FOO (N+1 if an inequality comparison)
11042 are known to be zero, we can do this by comparing FOO with C
11043 shifted right N bits so long as the low-order N bits of C are
11045 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11046 && INTVAL (XEXP (op0
, 1)) >= 0
11047 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11048 < HOST_BITS_PER_WIDE_INT
)
11050 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11051 && mode_width
<= HOST_BITS_PER_WIDE_INT
11052 && (nonzero_bits (XEXP (op0
, 0), mode
)
11053 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11054 + ! equality_comparison_p
))) == 0)
11056 /* We must perform a logical shift, not an arithmetic one,
11057 as we want the top N bits of C to be zero. */
11058 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11060 temp
>>= INTVAL (XEXP (op0
, 1));
11061 op1
= gen_int_mode (temp
, mode
);
11062 op0
= XEXP (op0
, 0);
11066 /* If we are doing a sign bit comparison, it means we are testing
11067 a particular bit. Convert it to the appropriate AND. */
11068 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11069 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11071 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11074 - INTVAL (XEXP (op0
, 1)))));
11075 code
= (code
== LT
? NE
: EQ
);
11079 /* If this an equality comparison with zero and we are shifting
11080 the low bit to the sign bit, we can convert this to an AND of the
11082 if (const_op
== 0 && equality_comparison_p
11083 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11084 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11087 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11088 (HOST_WIDE_INT
) 1);
11094 /* If this is an equality comparison with zero, we can do this
11095 as a logical shift, which might be much simpler. */
11096 if (equality_comparison_p
&& const_op
== 0
11097 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11099 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11101 INTVAL (XEXP (op0
, 1)));
11105 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11106 do the comparison in a narrower mode. */
11107 if (! unsigned_comparison_p
11108 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11109 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11110 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11111 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11112 MODE_INT
, 1)) != BLKmode
11113 && (((unsigned HOST_WIDE_INT
) const_op
11114 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11115 <= GET_MODE_MASK (tmode
)))
11117 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11121 /* Likewise if OP0 is a PLUS of a sign extension with a
11122 constant, which is usually represented with the PLUS
11123 between the shifts. */
11124 if (! unsigned_comparison_p
11125 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11126 && GET_CODE (XEXP (op0
, 0)) == PLUS
11127 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11128 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11129 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11130 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11131 MODE_INT
, 1)) != BLKmode
11132 && (((unsigned HOST_WIDE_INT
) const_op
11133 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11134 <= GET_MODE_MASK (tmode
)))
11136 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11137 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11138 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11141 op0
= gen_binary (PLUS
, tmode
,
11142 gen_lowpart (tmode
, inner
),
11147 /* ... fall through ... */
11149 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11150 the low order N bits of FOO are known to be zero, we can do this
11151 by comparing FOO with C shifted left N bits so long as no
11152 overflow occurs. */
11153 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11154 && INTVAL (XEXP (op0
, 1)) >= 0
11155 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11156 && mode_width
<= HOST_BITS_PER_WIDE_INT
11157 && (nonzero_bits (XEXP (op0
, 0), mode
)
11158 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11159 && (((unsigned HOST_WIDE_INT
) const_op
11160 + (GET_CODE (op0
) != LSHIFTRT
11161 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11164 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11166 /* If the shift was logical, then we must make the condition
11168 if (GET_CODE (op0
) == LSHIFTRT
)
11169 code
= unsigned_condition (code
);
11171 const_op
<<= INTVAL (XEXP (op0
, 1));
11172 op1
= GEN_INT (const_op
);
11173 op0
= XEXP (op0
, 0);
11177 /* If we are using this shift to extract just the sign bit, we
11178 can replace this with an LT or GE comparison. */
11180 && (equality_comparison_p
|| sign_bit_comparison_p
)
11181 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11182 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11185 op0
= XEXP (op0
, 0);
11186 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11198 /* Now make any compound operations involved in this comparison. Then,
11199 check for an outmost SUBREG on OP0 that is not doing anything or is
11200 paradoxical. The latter transformation must only be performed when
11201 it is known that the "extra" bits will be the same in op0 and op1 or
11202 that they don't matter. There are three cases to consider:
11204 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11205 care bits and we can assume they have any convenient value. So
11206 making the transformation is safe.
11208 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11209 In this case the upper bits of op0 are undefined. We should not make
11210 the simplification in that case as we do not know the contents of
11213 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11214 NIL. In that case we know those bits are zeros or ones. We must
11215 also be sure that they are the same as the upper bits of op1.
11217 We can never remove a SUBREG for a non-equality comparison because
11218 the sign bit is in a different place in the underlying object. */
11220 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11221 op1
= make_compound_operation (op1
, SET
);
11223 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11224 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11225 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11226 && (code
== NE
|| code
== EQ
))
11228 if (GET_MODE_SIZE (GET_MODE (op0
))
11229 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11231 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11233 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
11235 op0
= SUBREG_REG (op0
);
11236 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11239 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11240 <= HOST_BITS_PER_WIDE_INT
)
11241 && (nonzero_bits (SUBREG_REG (op0
),
11242 GET_MODE (SUBREG_REG (op0
)))
11243 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11245 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11247 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11248 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11249 op0
= SUBREG_REG (op0
), op1
= tem
;
11253 /* We now do the opposite procedure: Some machines don't have compare
11254 insns in all modes. If OP0's mode is an integer mode smaller than a
11255 word and we can't do a compare in that mode, see if there is a larger
11256 mode for which we can do the compare. There are a number of cases in
11257 which we can use the wider mode. */
11259 mode
= GET_MODE (op0
);
11260 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11261 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11262 && ! have_insn_for (COMPARE
, mode
))
11263 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11265 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11266 tmode
= GET_MODE_WIDER_MODE (tmode
))
11267 if (have_insn_for (COMPARE
, tmode
))
11271 /* If the only nonzero bits in OP0 and OP1 are those in the
11272 narrower mode and this is an equality or unsigned comparison,
11273 we can use the wider mode. Similarly for sign-extended
11274 values, in which case it is true for all comparisons. */
11275 zero_extended
= ((code
== EQ
|| code
== NE
11276 || code
== GEU
|| code
== GTU
11277 || code
== LEU
|| code
== LTU
)
11278 && (nonzero_bits (op0
, tmode
)
11279 & ~GET_MODE_MASK (mode
)) == 0
11280 && ((GET_CODE (op1
) == CONST_INT
11281 || (nonzero_bits (op1
, tmode
)
11282 & ~GET_MODE_MASK (mode
)) == 0)));
11285 || ((num_sign_bit_copies (op0
, tmode
)
11286 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11287 - GET_MODE_BITSIZE (mode
)))
11288 && (num_sign_bit_copies (op1
, tmode
)
11289 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11290 - GET_MODE_BITSIZE (mode
)))))
11292 /* If OP0 is an AND and we don't have an AND in MODE either,
11293 make a new AND in the proper mode. */
11294 if (GET_CODE (op0
) == AND
11295 && !have_insn_for (AND
, mode
))
11296 op0
= gen_binary (AND
, tmode
,
11297 gen_lowpart (tmode
,
11299 gen_lowpart (tmode
,
11302 op0
= gen_lowpart (tmode
, op0
);
11303 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11304 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11305 op1
= gen_lowpart (tmode
, op1
);
11309 /* If this is a test for negative, we can make an explicit
11310 test of the sign bit. */
11312 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11313 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11315 op0
= gen_binary (AND
, tmode
,
11316 gen_lowpart (tmode
, op0
),
11317 GEN_INT ((HOST_WIDE_INT
) 1
11318 << (GET_MODE_BITSIZE (mode
) - 1)));
11319 code
= (code
== LT
) ? NE
: EQ
;
11324 #ifdef CANONICALIZE_COMPARISON
11325 /* If this machine only supports a subset of valid comparisons, see if we
11326 can convert an unsupported one into a supported one. */
11327 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11336 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11337 searching backward. */
11338 static enum rtx_code
11339 combine_reversed_comparison_code (rtx exp
)
11341 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11344 if (code1
!= UNKNOWN
11345 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11347 /* Otherwise try and find where the condition codes were last set and
11349 x
= get_last_value (XEXP (exp
, 0));
11350 if (!x
|| GET_CODE (x
) != COMPARE
)
11352 return reversed_comparison_code_parts (GET_CODE (exp
),
11353 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11356 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11357 Return NULL_RTX in case we fail to do the reversal. */
11359 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11361 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11362 if (reversed_code
== UNKNOWN
)
11365 return gen_binary (reversed_code
, mode
, op0
, op1
);
11368 /* Utility function for following routine. Called when X is part of a value
11369 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11370 for each register mentioned. Similar to mention_regs in cse.c */
11373 update_table_tick (rtx x
)
11375 enum rtx_code code
= GET_CODE (x
);
11376 const char *fmt
= GET_RTX_FORMAT (code
);
11381 unsigned int regno
= REGNO (x
);
11382 unsigned int endregno
11383 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11384 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11387 for (r
= regno
; r
< endregno
; r
++)
11388 reg_last_set_table_tick
[r
] = label_tick
;
11393 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11394 /* Note that we can't have an "E" in values stored; see
11395 get_last_value_validate. */
11398 /* Check for identical subexpressions. If x contains
11399 identical subexpression we only have to traverse one of
11402 && (GET_RTX_CLASS (code
) == '2'
11403 || GET_RTX_CLASS (code
) == 'c'))
11405 /* Note that at this point x1 has already been
11407 rtx x0
= XEXP (x
, 0);
11408 rtx x1
= XEXP (x
, 1);
11410 /* If x0 and x1 are identical then there is no need to
11415 /* If x0 is identical to a subexpression of x1 then while
11416 processing x1, x0 has already been processed. Thus we
11417 are done with x. */
11418 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11419 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11420 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11423 /* If x1 is identical to a subexpression of x0 then we
11424 still have to process the rest of x0. */
11425 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11426 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11427 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11429 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11434 update_table_tick (XEXP (x
, i
));
11438 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11439 are saying that the register is clobbered and we no longer know its
11440 value. If INSN is zero, don't update reg_last_set; this is only permitted
11441 with VALUE also zero and is used to invalidate the register. */
11444 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11446 unsigned int regno
= REGNO (reg
);
11447 unsigned int endregno
11448 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11449 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
11452 /* If VALUE contains REG and we have a previous value for REG, substitute
11453 the previous value. */
11454 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11458 /* Set things up so get_last_value is allowed to see anything set up to
11460 subst_low_cuid
= INSN_CUID (insn
);
11461 tem
= get_last_value (reg
);
11463 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11464 it isn't going to be useful and will take a lot of time to process,
11465 so just use the CLOBBER. */
11469 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11470 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11471 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11472 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11473 tem
= XEXP (tem
, 0);
11475 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11479 /* For each register modified, show we don't know its value, that
11480 we don't know about its bitwise content, that its value has been
11481 updated, and that we don't know the location of the death of the
11483 for (i
= regno
; i
< endregno
; i
++)
11486 reg_last_set
[i
] = insn
;
11488 reg_last_set_value
[i
] = 0;
11489 reg_last_set_mode
[i
] = 0;
11490 reg_last_set_nonzero_bits
[i
] = 0;
11491 reg_last_set_sign_bit_copies
[i
] = 0;
11492 reg_last_death
[i
] = 0;
11495 /* Mark registers that are being referenced in this value. */
11497 update_table_tick (value
);
11499 /* Now update the status of each register being set.
11500 If someone is using this register in this block, set this register
11501 to invalid since we will get confused between the two lives in this
11502 basic block. This makes using this register always invalid. In cse, we
11503 scan the table to invalidate all entries using this register, but this
11504 is too much work for us. */
11506 for (i
= regno
; i
< endregno
; i
++)
11508 reg_last_set_label
[i
] = label_tick
;
11509 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11510 reg_last_set_invalid
[i
] = 1;
11512 reg_last_set_invalid
[i
] = 0;
11515 /* The value being assigned might refer to X (like in "x++;"). In that
11516 case, we must replace it with (clobber (const_int 0)) to prevent
11518 if (value
&& ! get_last_value_validate (&value
, insn
,
11519 reg_last_set_label
[regno
], 0))
11521 value
= copy_rtx (value
);
11522 if (! get_last_value_validate (&value
, insn
,
11523 reg_last_set_label
[regno
], 1))
11527 /* For the main register being modified, update the value, the mode, the
11528 nonzero bits, and the number of sign bit copies. */
11530 reg_last_set_value
[regno
] = value
;
11534 enum machine_mode mode
= GET_MODE (reg
);
11535 subst_low_cuid
= INSN_CUID (insn
);
11536 reg_last_set_mode
[regno
] = mode
;
11537 if (GET_MODE_CLASS (mode
) == MODE_INT
11538 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11539 mode
= nonzero_bits_mode
;
11540 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11541 reg_last_set_sign_bit_copies
[regno
]
11542 = num_sign_bit_copies (value
, GET_MODE (reg
));
11546 /* Called via note_stores from record_dead_and_set_regs to handle one
11547 SET or CLOBBER in an insn. DATA is the instruction in which the
11548 set is occurring. */
11551 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11553 rtx record_dead_insn
= (rtx
) data
;
11555 if (GET_CODE (dest
) == SUBREG
)
11556 dest
= SUBREG_REG (dest
);
11558 if (GET_CODE (dest
) == REG
)
11560 /* If we are setting the whole register, we know its value. Otherwise
11561 show that we don't know the value. We can handle SUBREG in
11563 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11564 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11565 else if (GET_CODE (setter
) == SET
11566 && GET_CODE (SET_DEST (setter
)) == SUBREG
11567 && SUBREG_REG (SET_DEST (setter
)) == dest
11568 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11569 && subreg_lowpart_p (SET_DEST (setter
)))
11570 record_value_for_reg (dest
, record_dead_insn
,
11571 gen_lowpart (GET_MODE (dest
),
11572 SET_SRC (setter
)));
11574 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11576 else if (GET_CODE (dest
) == MEM
11577 /* Ignore pushes, they clobber nothing. */
11578 && ! push_operand (dest
, GET_MODE (dest
)))
11579 mem_last_set
= INSN_CUID (record_dead_insn
);
11582 /* Update the records of when each REG was most recently set or killed
11583 for the things done by INSN. This is the last thing done in processing
11584 INSN in the combiner loop.
11586 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11587 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11588 and also the similar information mem_last_set (which insn most recently
11589 modified memory) and last_call_cuid (which insn was the most recent
11590 subroutine call). */
11593 record_dead_and_set_regs (rtx insn
)
11598 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11600 if (REG_NOTE_KIND (link
) == REG_DEAD
11601 && GET_CODE (XEXP (link
, 0)) == REG
)
11603 unsigned int regno
= REGNO (XEXP (link
, 0));
11604 unsigned int endregno
11605 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11606 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11609 for (i
= regno
; i
< endregno
; i
++)
11610 reg_last_death
[i
] = insn
;
11612 else if (REG_NOTE_KIND (link
) == REG_INC
)
11613 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11616 if (GET_CODE (insn
) == CALL_INSN
)
11618 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11619 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11621 reg_last_set_value
[i
] = 0;
11622 reg_last_set_mode
[i
] = 0;
11623 reg_last_set_nonzero_bits
[i
] = 0;
11624 reg_last_set_sign_bit_copies
[i
] = 0;
11625 reg_last_death
[i
] = 0;
11628 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11630 /* Don't bother recording what this insn does. It might set the
11631 return value register, but we can't combine into a call
11632 pattern anyway, so there's no point trying (and it may cause
11633 a crash, if e.g. we wind up asking for last_set_value of a
11634 SUBREG of the return value register). */
11638 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11641 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11642 register present in the SUBREG, so for each such SUBREG go back and
11643 adjust nonzero and sign bit information of the registers that are
11644 known to have some zero/sign bits set.
11646 This is needed because when combine blows the SUBREGs away, the
11647 information on zero/sign bits is lost and further combines can be
11648 missed because of that. */
11651 record_promoted_value (rtx insn
, rtx subreg
)
11654 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11655 enum machine_mode mode
= GET_MODE (subreg
);
11657 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11660 for (links
= LOG_LINKS (insn
); links
;)
11662 insn
= XEXP (links
, 0);
11663 set
= single_set (insn
);
11665 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11666 || REGNO (SET_DEST (set
)) != regno
11667 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11669 links
= XEXP (links
, 1);
11673 if (reg_last_set
[regno
] == insn
)
11675 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11676 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11679 if (GET_CODE (SET_SRC (set
)) == REG
)
11681 regno
= REGNO (SET_SRC (set
));
11682 links
= LOG_LINKS (insn
);
11689 /* Scan X for promoted SUBREGs. For each one found,
11690 note what it implies to the registers used in it. */
11693 check_promoted_subreg (rtx insn
, rtx x
)
11695 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11696 && GET_CODE (SUBREG_REG (x
)) == REG
)
11697 record_promoted_value (insn
, x
);
11700 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11703 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11707 check_promoted_subreg (insn
, XEXP (x
, i
));
11711 if (XVEC (x
, i
) != 0)
11712 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11713 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11719 /* Utility routine for the following function. Verify that all the registers
11720 mentioned in *LOC are valid when *LOC was part of a value set when
11721 label_tick == TICK. Return 0 if some are not.
11723 If REPLACE is nonzero, replace the invalid reference with
11724 (clobber (const_int 0)) and return 1. This replacement is useful because
11725 we often can get useful information about the form of a value (e.g., if
11726 it was produced by a shift that always produces -1 or 0) even though
11727 we don't know exactly what registers it was produced from. */
11730 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11733 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11734 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11737 if (GET_CODE (x
) == REG
)
11739 unsigned int regno
= REGNO (x
);
11740 unsigned int endregno
11741 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11742 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11745 for (j
= regno
; j
< endregno
; j
++)
11746 if (reg_last_set_invalid
[j
]
11747 /* If this is a pseudo-register that was only set once and not
11748 live at the beginning of the function, it is always valid. */
11749 || (! (regno
>= FIRST_PSEUDO_REGISTER
11750 && REG_N_SETS (regno
) == 1
11751 && (! REGNO_REG_SET_P
11752 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11753 && reg_last_set_label
[j
] > tick
))
11756 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11762 /* If this is a memory reference, make sure that there were
11763 no stores after it that might have clobbered the value. We don't
11764 have alias info, so we assume any store invalidates it. */
11765 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11766 && INSN_CUID (insn
) <= mem_last_set
)
11769 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11773 for (i
= 0; i
< len
; i
++)
11777 /* Check for identical subexpressions. If x contains
11778 identical subexpression we only have to traverse one of
11781 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11782 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11784 /* Note that at this point x0 has already been checked
11785 and found valid. */
11786 rtx x0
= XEXP (x
, 0);
11787 rtx x1
= XEXP (x
, 1);
11789 /* If x0 and x1 are identical then x is also valid. */
11793 /* If x1 is identical to a subexpression of x0 then
11794 while checking x0, x1 has already been checked. Thus
11795 it is valid and so as x. */
11796 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11797 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11798 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11801 /* If x0 is identical to a subexpression of x1 then x is
11802 valid iff the rest of x1 is valid. */
11803 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11804 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11805 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11807 get_last_value_validate (&XEXP (x1
,
11808 x0
== XEXP (x1
, 0) ? 1 : 0),
11809 insn
, tick
, replace
);
11812 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11816 /* Don't bother with these. They shouldn't occur anyway. */
11817 else if (fmt
[i
] == 'E')
11821 /* If we haven't found a reason for it to be invalid, it is valid. */
11825 /* Get the last value assigned to X, if known. Some registers
11826 in the value may be replaced with (clobber (const_int 0)) if their value
11827 is known longer known reliably. */
11830 get_last_value (rtx x
)
11832 unsigned int regno
;
11835 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11836 then convert it to the desired mode. If this is a paradoxical SUBREG,
11837 we cannot predict what values the "extra" bits might have. */
11838 if (GET_CODE (x
) == SUBREG
11839 && subreg_lowpart_p (x
)
11840 && (GET_MODE_SIZE (GET_MODE (x
))
11841 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11842 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11843 return gen_lowpart (GET_MODE (x
), value
);
11845 if (GET_CODE (x
) != REG
)
11849 value
= reg_last_set_value
[regno
];
11851 /* If we don't have a value, or if it isn't for this basic block and
11852 it's either a hard register, set more than once, or it's a live
11853 at the beginning of the function, return 0.
11855 Because if it's not live at the beginning of the function then the reg
11856 is always set before being used (is never used without being set).
11857 And, if it's set only once, and it's always set before use, then all
11858 uses must have the same last value, even if it's not from this basic
11862 || (reg_last_set_label
[regno
] != label_tick
11863 && (regno
< FIRST_PSEUDO_REGISTER
11864 || REG_N_SETS (regno
) != 1
11865 || (REGNO_REG_SET_P
11866 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11869 /* If the value was set in a later insn than the ones we are processing,
11870 we can't use it even if the register was only set once. */
11871 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11874 /* If the value has all its registers valid, return it. */
11875 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11876 reg_last_set_label
[regno
], 0))
11879 /* Otherwise, make a copy and replace any invalid register with
11880 (clobber (const_int 0)). If that fails for some reason, return 0. */
11882 value
= copy_rtx (value
);
11883 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11884 reg_last_set_label
[regno
], 1))
11890 /* Return nonzero if expression X refers to a REG or to memory
11891 that is set in an instruction more recent than FROM_CUID. */
11894 use_crosses_set_p (rtx x
, int from_cuid
)
11898 enum rtx_code code
= GET_CODE (x
);
11902 unsigned int regno
= REGNO (x
);
11903 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11904 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11906 #ifdef PUSH_ROUNDING
11907 /* Don't allow uses of the stack pointer to be moved,
11908 because we don't know whether the move crosses a push insn. */
11909 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11912 for (; regno
< endreg
; regno
++)
11913 if (reg_last_set
[regno
]
11914 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11919 if (code
== MEM
&& mem_last_set
> from_cuid
)
11922 fmt
= GET_RTX_FORMAT (code
);
11924 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11929 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11930 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11933 else if (fmt
[i
] == 'e'
11934 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11940 /* Define three variables used for communication between the following
11943 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11944 static int reg_dead_flag
;
11946 /* Function called via note_stores from reg_dead_at_p.
11948 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11949 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11952 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11954 unsigned int regno
, endregno
;
11956 if (GET_CODE (dest
) != REG
)
11959 regno
= REGNO (dest
);
11960 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11961 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11963 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11964 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11967 /* Return nonzero if REG is known to be dead at INSN.
11969 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11970 referencing REG, it is dead. If we hit a SET referencing REG, it is
11971 live. Otherwise, see if it is live or dead at the start of the basic
11972 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11973 must be assumed to be always live. */
11976 reg_dead_at_p (rtx reg
, rtx insn
)
11981 /* Set variables for reg_dead_at_p_1. */
11982 reg_dead_regno
= REGNO (reg
);
11983 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11984 ? hard_regno_nregs
[reg_dead_regno
]
11990 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11991 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11993 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11994 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11998 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11999 beginning of function. */
12000 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
12001 insn
= prev_nonnote_insn (insn
))
12003 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12005 return reg_dead_flag
== 1 ? 1 : 0;
12007 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12011 /* Get the basic block that we were in. */
12013 block
= ENTRY_BLOCK_PTR
->next_bb
;
12016 FOR_EACH_BB (block
)
12017 if (insn
== BB_HEAD (block
))
12020 if (block
== EXIT_BLOCK_PTR
)
12024 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12025 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
12031 /* Note hard registers in X that are used. This code is similar to
12032 that in flow.c, but much simpler since we don't care about pseudos. */
12035 mark_used_regs_combine (rtx x
)
12037 RTX_CODE code
= GET_CODE (x
);
12038 unsigned int regno
;
12051 case ADDR_DIFF_VEC
:
12054 /* CC0 must die in the insn after it is set, so we don't need to take
12055 special note of it here. */
12061 /* If we are clobbering a MEM, mark any hard registers inside the
12062 address as used. */
12063 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12064 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12069 /* A hard reg in a wide mode may really be multiple registers.
12070 If so, mark all of them just like the first. */
12071 if (regno
< FIRST_PSEUDO_REGISTER
)
12073 unsigned int endregno
, r
;
12075 /* None of this applies to the stack, frame or arg pointers. */
12076 if (regno
== STACK_POINTER_REGNUM
12077 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12078 || regno
== HARD_FRAME_POINTER_REGNUM
12080 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12081 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12083 || regno
== FRAME_POINTER_REGNUM
)
12086 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12087 for (r
= regno
; r
< endregno
; r
++)
12088 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12094 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12096 rtx testreg
= SET_DEST (x
);
12098 while (GET_CODE (testreg
) == SUBREG
12099 || GET_CODE (testreg
) == ZERO_EXTRACT
12100 || GET_CODE (testreg
) == SIGN_EXTRACT
12101 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12102 testreg
= XEXP (testreg
, 0);
12104 if (GET_CODE (testreg
) == MEM
)
12105 mark_used_regs_combine (XEXP (testreg
, 0));
12107 mark_used_regs_combine (SET_SRC (x
));
12115 /* Recursively scan the operands of this expression. */
12118 const char *fmt
= GET_RTX_FORMAT (code
);
12120 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12123 mark_used_regs_combine (XEXP (x
, i
));
12124 else if (fmt
[i
] == 'E')
12128 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12129 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12135 /* Remove register number REGNO from the dead registers list of INSN.
12137 Return the note used to record the death, if there was one. */
12140 remove_death (unsigned int regno
, rtx insn
)
12142 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12146 REG_N_DEATHS (regno
)--;
12147 remove_note (insn
, note
);
12153 /* For each register (hardware or pseudo) used within expression X, if its
12154 death is in an instruction with cuid between FROM_CUID (inclusive) and
12155 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12156 list headed by PNOTES.
12158 That said, don't move registers killed by maybe_kill_insn.
12160 This is done when X is being merged by combination into TO_INSN. These
12161 notes will then be distributed as needed. */
12164 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12169 enum rtx_code code
= GET_CODE (x
);
12173 unsigned int regno
= REGNO (x
);
12174 rtx where_dead
= reg_last_death
[regno
];
12175 rtx before_dead
, after_dead
;
12177 /* Don't move the register if it gets killed in between from and to. */
12178 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12179 && ! reg_referenced_p (x
, maybe_kill_insn
))
12182 /* WHERE_DEAD could be a USE insn made by combine, so first we
12183 make sure that we have insns with valid INSN_CUID values. */
12184 before_dead
= where_dead
;
12185 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12186 before_dead
= PREV_INSN (before_dead
);
12188 after_dead
= where_dead
;
12189 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12190 after_dead
= NEXT_INSN (after_dead
);
12192 if (before_dead
&& after_dead
12193 && INSN_CUID (before_dead
) >= from_cuid
12194 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12195 || (where_dead
!= after_dead
12196 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12198 rtx note
= remove_death (regno
, where_dead
);
12200 /* It is possible for the call above to return 0. This can occur
12201 when reg_last_death points to I2 or I1 that we combined with.
12202 In that case make a new note.
12204 We must also check for the case where X is a hard register
12205 and NOTE is a death note for a range of hard registers
12206 including X. In that case, we must put REG_DEAD notes for
12207 the remaining registers in place of NOTE. */
12209 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12210 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12211 > GET_MODE_SIZE (GET_MODE (x
))))
12213 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12214 unsigned int deadend
12215 = (deadregno
+ hard_regno_nregs
[deadregno
]
12216 [GET_MODE (XEXP (note
, 0))]);
12217 unsigned int ourend
12218 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12221 for (i
= deadregno
; i
< deadend
; i
++)
12222 if (i
< regno
|| i
>= ourend
)
12223 REG_NOTES (where_dead
)
12224 = gen_rtx_EXPR_LIST (REG_DEAD
,
12226 REG_NOTES (where_dead
));
12229 /* If we didn't find any note, or if we found a REG_DEAD note that
12230 covers only part of the given reg, and we have a multi-reg hard
12231 register, then to be safe we must check for REG_DEAD notes
12232 for each register other than the first. They could have
12233 their own REG_DEAD notes lying around. */
12234 else if ((note
== 0
12236 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12237 < GET_MODE_SIZE (GET_MODE (x
)))))
12238 && regno
< FIRST_PSEUDO_REGISTER
12239 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12241 unsigned int ourend
12242 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12243 unsigned int i
, offset
;
12247 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12251 for (i
= regno
+ offset
; i
< ourend
; i
++)
12252 move_deaths (regno_reg_rtx
[i
],
12253 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12256 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12258 XEXP (note
, 1) = *pnotes
;
12262 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12264 REG_N_DEATHS (regno
)++;
12270 else if (GET_CODE (x
) == SET
)
12272 rtx dest
= SET_DEST (x
);
12274 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12276 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12277 that accesses one word of a multi-word item, some
12278 piece of everything register in the expression is used by
12279 this insn, so remove any old death. */
12280 /* ??? So why do we test for equality of the sizes? */
12282 if (GET_CODE (dest
) == ZERO_EXTRACT
12283 || GET_CODE (dest
) == STRICT_LOW_PART
12284 || (GET_CODE (dest
) == SUBREG
12285 && (((GET_MODE_SIZE (GET_MODE (dest
))
12286 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12287 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12288 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12290 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12294 /* If this is some other SUBREG, we know it replaces the entire
12295 value, so use that as the destination. */
12296 if (GET_CODE (dest
) == SUBREG
)
12297 dest
= SUBREG_REG (dest
);
12299 /* If this is a MEM, adjust deaths of anything used in the address.
12300 For a REG (the only other possibility), the entire value is
12301 being replaced so the old value is not used in this insn. */
12303 if (GET_CODE (dest
) == MEM
)
12304 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12309 else if (GET_CODE (x
) == CLOBBER
)
12312 len
= GET_RTX_LENGTH (code
);
12313 fmt
= GET_RTX_FORMAT (code
);
12315 for (i
= 0; i
< len
; i
++)
12320 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12321 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12324 else if (fmt
[i
] == 'e')
12325 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12329 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12330 pattern of an insn. X must be a REG. */
12333 reg_bitfield_target_p (rtx x
, rtx body
)
12337 if (GET_CODE (body
) == SET
)
12339 rtx dest
= SET_DEST (body
);
12341 unsigned int regno
, tregno
, endregno
, endtregno
;
12343 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12344 target
= XEXP (dest
, 0);
12345 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12346 target
= SUBREG_REG (XEXP (dest
, 0));
12350 if (GET_CODE (target
) == SUBREG
)
12351 target
= SUBREG_REG (target
);
12353 if (GET_CODE (target
) != REG
)
12356 tregno
= REGNO (target
), regno
= REGNO (x
);
12357 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12358 return target
== x
;
12360 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
12361 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12363 return endregno
> tregno
&& regno
< endtregno
;
12366 else if (GET_CODE (body
) == PARALLEL
)
12367 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12368 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12374 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12375 as appropriate. I3 and I2 are the insns resulting from the combination
12376 insns including FROM (I2 may be zero).
12378 Each note in the list is either ignored or placed on some insns, depending
12379 on the type of note. */
12382 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12384 rtx note
, next_note
;
12387 for (note
= notes
; note
; note
= next_note
)
12389 rtx place
= 0, place2
= 0;
12391 /* If this NOTE references a pseudo register, ensure it references
12392 the latest copy of that register. */
12393 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12394 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12395 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12397 next_note
= XEXP (note
, 1);
12398 switch (REG_NOTE_KIND (note
))
12402 /* Doesn't matter much where we put this, as long as it's somewhere.
12403 It is preferable to keep these notes on branches, which is most
12404 likely to be i3. */
12408 case REG_VALUE_PROFILE
:
12409 /* Just get rid of this note, as it is unused later anyway. */
12412 case REG_VTABLE_REF
:
12413 /* ??? Should remain with *a particular* memory load. Given the
12414 nature of vtable data, the last insn seems relatively safe. */
12418 case REG_NON_LOCAL_GOTO
:
12419 if (GET_CODE (i3
) == JUMP_INSN
)
12421 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12427 case REG_EH_REGION
:
12428 /* These notes must remain with the call or trapping instruction. */
12429 if (GET_CODE (i3
) == CALL_INSN
)
12431 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12433 else if (flag_non_call_exceptions
)
12435 if (may_trap_p (i3
))
12437 else if (i2
&& may_trap_p (i2
))
12439 /* ??? Otherwise assume we've combined things such that we
12440 can now prove that the instructions can't trap. Drop the
12441 note in this case. */
12447 case REG_ALWAYS_RETURN
:
12450 /* These notes must remain with the call. It should not be
12451 possible for both I2 and I3 to be a call. */
12452 if (GET_CODE (i3
) == CALL_INSN
)
12454 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12461 /* Any clobbers for i3 may still exist, and so we must process
12462 REG_UNUSED notes from that insn.
12464 Any clobbers from i2 or i1 can only exist if they were added by
12465 recog_for_combine. In that case, recog_for_combine created the
12466 necessary REG_UNUSED notes. Trying to keep any original
12467 REG_UNUSED notes from these insns can cause incorrect output
12468 if it is for the same register as the original i3 dest.
12469 In that case, we will notice that the register is set in i3,
12470 and then add a REG_UNUSED note for the destination of i3, which
12471 is wrong. However, it is possible to have REG_UNUSED notes from
12472 i2 or i1 for register which were both used and clobbered, so
12473 we keep notes from i2 or i1 if they will turn into REG_DEAD
12476 /* If this register is set or clobbered in I3, put the note there
12477 unless there is one already. */
12478 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12480 if (from_insn
!= i3
)
12483 if (! (GET_CODE (XEXP (note
, 0)) == REG
12484 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12485 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12488 /* Otherwise, if this register is used by I3, then this register
12489 now dies here, so we must put a REG_DEAD note here unless there
12491 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12492 && ! (GET_CODE (XEXP (note
, 0)) == REG
12493 ? find_regno_note (i3
, REG_DEAD
,
12494 REGNO (XEXP (note
, 0)))
12495 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12497 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12505 /* These notes say something about results of an insn. We can
12506 only support them if they used to be on I3 in which case they
12507 remain on I3. Otherwise they are ignored.
12509 If the note refers to an expression that is not a constant, we
12510 must also ignore the note since we cannot tell whether the
12511 equivalence is still true. It might be possible to do
12512 slightly better than this (we only have a problem if I2DEST
12513 or I1DEST is present in the expression), but it doesn't
12514 seem worth the trouble. */
12516 if (from_insn
== i3
12517 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12522 case REG_NO_CONFLICT
:
12523 /* These notes say something about how a register is used. They must
12524 be present on any use of the register in I2 or I3. */
12525 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12528 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12538 /* This can show up in several ways -- either directly in the
12539 pattern, or hidden off in the constant pool with (or without?)
12540 a REG_EQUAL note. */
12541 /* ??? Ignore the without-reg_equal-note problem for now. */
12542 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12543 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12544 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12545 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12549 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12550 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12551 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12552 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12560 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12561 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12562 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12564 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12566 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12567 LABEL_NUSES (JUMP_LABEL (place
))--;
12570 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12572 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12574 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12575 LABEL_NUSES (JUMP_LABEL (place2
))--;
12581 /* This note says something about the value of a register prior
12582 to the execution of an insn. It is too much trouble to see
12583 if the note is still correct in all situations. It is better
12584 to simply delete it. */
12588 /* If the insn previously containing this note still exists,
12589 put it back where it was. Otherwise move it to the previous
12590 insn. Adjust the corresponding REG_LIBCALL note. */
12591 if (GET_CODE (from_insn
) != NOTE
)
12595 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12596 place
= prev_real_insn (from_insn
);
12598 XEXP (tem
, 0) = place
;
12599 /* If we're deleting the last remaining instruction of a
12600 libcall sequence, don't add the notes. */
12601 else if (XEXP (note
, 0) == from_insn
)
12607 /* This is handled similarly to REG_RETVAL. */
12608 if (GET_CODE (from_insn
) != NOTE
)
12612 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12613 place
= next_real_insn (from_insn
);
12615 XEXP (tem
, 0) = place
;
12616 /* If we're deleting the last remaining instruction of a
12617 libcall sequence, don't add the notes. */
12618 else if (XEXP (note
, 0) == from_insn
)
12624 /* If the register is used as an input in I3, it dies there.
12625 Similarly for I2, if it is nonzero and adjacent to I3.
12627 If the register is not used as an input in either I3 or I2
12628 and it is not one of the registers we were supposed to eliminate,
12629 there are two possibilities. We might have a non-adjacent I2
12630 or we might have somehow eliminated an additional register
12631 from a computation. For example, we might have had A & B where
12632 we discover that B will always be zero. In this case we will
12633 eliminate the reference to A.
12635 In both cases, we must search to see if we can find a previous
12636 use of A and put the death note there. */
12639 && GET_CODE (from_insn
) == CALL_INSN
12640 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12642 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12644 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12645 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12650 basic_block bb
= this_basic_block
;
12652 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12654 if (! INSN_P (tem
))
12656 if (tem
== BB_HEAD (bb
))
12661 /* If the register is being set at TEM, see if that is all
12662 TEM is doing. If so, delete TEM. Otherwise, make this
12663 into a REG_UNUSED note instead. */
12664 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12666 rtx set
= single_set (tem
);
12667 rtx inner_dest
= 0;
12669 rtx cc0_setter
= NULL_RTX
;
12673 for (inner_dest
= SET_DEST (set
);
12674 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12675 || GET_CODE (inner_dest
) == SUBREG
12676 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12677 inner_dest
= XEXP (inner_dest
, 0))
12680 /* Verify that it was the set, and not a clobber that
12681 modified the register.
12683 CC0 targets must be careful to maintain setter/user
12684 pairs. If we cannot delete the setter due to side
12685 effects, mark the user with an UNUSED note instead
12688 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12689 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12691 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12692 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12693 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12697 /* Move the notes and links of TEM elsewhere.
12698 This might delete other dead insns recursively.
12699 First set the pattern to something that won't use
12701 rtx old_notes
= REG_NOTES (tem
);
12703 PATTERN (tem
) = pc_rtx
;
12704 REG_NOTES (tem
) = NULL
;
12706 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12707 distribute_links (LOG_LINKS (tem
));
12709 PUT_CODE (tem
, NOTE
);
12710 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12711 NOTE_SOURCE_FILE (tem
) = 0;
12714 /* Delete the setter too. */
12717 PATTERN (cc0_setter
) = pc_rtx
;
12718 old_notes
= REG_NOTES (cc0_setter
);
12719 REG_NOTES (cc0_setter
) = NULL
;
12721 distribute_notes (old_notes
, cc0_setter
,
12722 cc0_setter
, NULL_RTX
);
12723 distribute_links (LOG_LINKS (cc0_setter
));
12725 PUT_CODE (cc0_setter
, NOTE
);
12726 NOTE_LINE_NUMBER (cc0_setter
)
12727 = NOTE_INSN_DELETED
;
12728 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12732 /* If the register is both set and used here, put the
12733 REG_DEAD note here, but place a REG_UNUSED note
12734 here too unless there already is one. */
12735 else if (reg_referenced_p (XEXP (note
, 0),
12740 if (! find_regno_note (tem
, REG_UNUSED
,
12741 REGNO (XEXP (note
, 0))))
12743 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12748 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12750 /* If there isn't already a REG_UNUSED note, put one
12752 if (! find_regno_note (tem
, REG_UNUSED
,
12753 REGNO (XEXP (note
, 0))))
12758 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12759 || (GET_CODE (tem
) == CALL_INSN
12760 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12764 /* If we are doing a 3->2 combination, and we have a
12765 register which formerly died in i3 and was not used
12766 by i2, which now no longer dies in i3 and is used in
12767 i2 but does not die in i2, and place is between i2
12768 and i3, then we may need to move a link from place to
12770 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12771 && INSN_CUID (place
) > INSN_CUID (i2
)
12773 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12774 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12776 rtx links
= LOG_LINKS (place
);
12777 LOG_LINKS (place
) = 0;
12778 distribute_links (links
);
12783 if (tem
== BB_HEAD (bb
))
12787 /* We haven't found an insn for the death note and it
12788 is still a REG_DEAD note, but we have hit the beginning
12789 of the block. If the existing life info says the reg
12790 was dead, there's nothing left to do. Otherwise, we'll
12791 need to do a global life update after combine. */
12792 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12793 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12794 REGNO (XEXP (note
, 0))))
12795 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12798 /* If the register is set or already dead at PLACE, we needn't do
12799 anything with this note if it is still a REG_DEAD note.
12800 We can here if it is set at all, not if is it totally replace,
12801 which is what `dead_or_set_p' checks, so also check for it being
12804 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12806 unsigned int regno
= REGNO (XEXP (note
, 0));
12808 /* Similarly, if the instruction on which we want to place
12809 the note is a noop, we'll need do a global live update
12810 after we remove them in delete_noop_moves. */
12811 if (noop_move_p (place
))
12812 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12814 if (dead_or_set_p (place
, XEXP (note
, 0))
12815 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12817 /* Unless the register previously died in PLACE, clear
12818 reg_last_death. [I no longer understand why this is
12820 if (reg_last_death
[regno
] != place
)
12821 reg_last_death
[regno
] = 0;
12825 reg_last_death
[regno
] = place
;
12827 /* If this is a death note for a hard reg that is occupying
12828 multiple registers, ensure that we are still using all
12829 parts of the object. If we find a piece of the object
12830 that is unused, we must arrange for an appropriate REG_DEAD
12831 note to be added for it. However, we can't just emit a USE
12832 and tag the note to it, since the register might actually
12833 be dead; so we recourse, and the recursive call then finds
12834 the previous insn that used this register. */
12836 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12837 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12839 unsigned int endregno
12840 = regno
+ hard_regno_nregs
[regno
]
12841 [GET_MODE (XEXP (note
, 0))];
12845 for (i
= regno
; i
< endregno
; i
++)
12846 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12847 && ! find_regno_fusage (place
, USE
, i
))
12848 || dead_or_set_regno_p (place
, i
))
12853 /* Put only REG_DEAD notes for pieces that are
12854 not already dead or set. */
12856 for (i
= regno
; i
< endregno
;
12857 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12859 rtx piece
= regno_reg_rtx
[i
];
12860 basic_block bb
= this_basic_block
;
12862 if (! dead_or_set_p (place
, piece
)
12863 && ! reg_bitfield_target_p (piece
,
12867 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12869 distribute_notes (new_note
, place
, place
,
12872 else if (! refers_to_regno_p (i
, i
+ 1,
12873 PATTERN (place
), 0)
12874 && ! find_regno_fusage (place
, USE
, i
))
12875 for (tem
= PREV_INSN (place
); ;
12876 tem
= PREV_INSN (tem
))
12878 if (! INSN_P (tem
))
12880 if (tem
== BB_HEAD (bb
))
12882 SET_BIT (refresh_blocks
,
12883 this_basic_block
->index
);
12888 if (dead_or_set_p (tem
, piece
)
12889 || reg_bitfield_target_p (piece
,
12893 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12908 /* Any other notes should not be present at this point in the
12915 XEXP (note
, 1) = REG_NOTES (place
);
12916 REG_NOTES (place
) = note
;
12918 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12919 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12920 && GET_CODE (XEXP (note
, 0)) == REG
)
12921 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12925 if ((REG_NOTE_KIND (note
) == REG_DEAD
12926 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12927 && GET_CODE (XEXP (note
, 0)) == REG
)
12928 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12930 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12931 REG_NOTE_KIND (note
),
12933 REG_NOTES (place2
));
12938 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12939 I3, I2, and I1 to new locations. This is also called to add a link
12940 pointing at I3 when I3's destination is changed. */
12943 distribute_links (rtx links
)
12945 rtx link
, next_link
;
12947 for (link
= links
; link
; link
= next_link
)
12953 next_link
= XEXP (link
, 1);
12955 /* If the insn that this link points to is a NOTE or isn't a single
12956 set, ignore it. In the latter case, it isn't clear what we
12957 can do other than ignore the link, since we can't tell which
12958 register it was for. Such links wouldn't be used by combine
12961 It is not possible for the destination of the target of the link to
12962 have been changed by combine. The only potential of this is if we
12963 replace I3, I2, and I1 by I3 and I2. But in that case the
12964 destination of I2 also remains unchanged. */
12966 if (GET_CODE (XEXP (link
, 0)) == NOTE
12967 || (set
= single_set (XEXP (link
, 0))) == 0)
12970 reg
= SET_DEST (set
);
12971 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12972 || GET_CODE (reg
) == SIGN_EXTRACT
12973 || GET_CODE (reg
) == STRICT_LOW_PART
)
12974 reg
= XEXP (reg
, 0);
12976 /* A LOG_LINK is defined as being placed on the first insn that uses
12977 a register and points to the insn that sets the register. Start
12978 searching at the next insn after the target of the link and stop
12979 when we reach a set of the register or the end of the basic block.
12981 Note that this correctly handles the link that used to point from
12982 I3 to I2. Also note that not much searching is typically done here
12983 since most links don't point very far away. */
12985 for (insn
= NEXT_INSN (XEXP (link
, 0));
12986 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12987 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12988 insn
= NEXT_INSN (insn
))
12989 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12991 if (reg_referenced_p (reg
, PATTERN (insn
)))
12995 else if (GET_CODE (insn
) == CALL_INSN
12996 && find_reg_fusage (insn
, USE
, reg
))
13001 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13004 /* If we found a place to put the link, place it there unless there
13005 is already a link to the same insn as LINK at that point. */
13011 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13012 if (XEXP (link2
, 0) == XEXP (link
, 0))
13017 XEXP (link
, 1) = LOG_LINKS (place
);
13018 LOG_LINKS (place
) = link
;
13020 /* Set added_links_insn to the earliest insn we added a
13022 if (added_links_insn
== 0
13023 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
13024 added_links_insn
= place
;
13030 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13033 insn_cuid (rtx insn
)
13035 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13036 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13037 insn
= NEXT_INSN (insn
);
13039 if (INSN_UID (insn
) > max_uid_cuid
)
13042 return INSN_CUID (insn
);
13046 dump_combine_stats (FILE *file
)
13050 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13051 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13055 dump_combine_total_stats (FILE *file
)
13059 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13060 total_attempts
, total_merges
, total_extras
, total_successes
);